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3417ba8a JG |
1 | /* |
2 | * Copyright (c) 2016 Linaro Ltd. | |
3 | * Copyright (c) 2016 Hisilicon Limited. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | */ | |
11 | ||
12 | #include "hisi_sas.h" | |
13 | #define DRV_NAME "hisi_sas_v2_hw" | |
14 | ||
45c901b8 JG |
15 | /* global registers need init*/ |
16 | #define DLVRY_QUEUE_ENABLE 0x0 | |
17 | #define IOST_BASE_ADDR_LO 0x8 | |
18 | #define IOST_BASE_ADDR_HI 0xc | |
19 | #define ITCT_BASE_ADDR_LO 0x10 | |
20 | #define ITCT_BASE_ADDR_HI 0x14 | |
21 | #define IO_BROKEN_MSG_ADDR_LO 0x18 | |
22 | #define IO_BROKEN_MSG_ADDR_HI 0x1c | |
23 | #define PHY_CONTEXT 0x20 | |
24 | #define PHY_STATE 0x24 | |
25 | #define PHY_PORT_NUM_MA 0x28 | |
26 | #define PORT_STATE 0x2c | |
27 | #define PORT_STATE_PHY8_PORT_NUM_OFF 16 | |
28 | #define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF) | |
29 | #define PORT_STATE_PHY8_CONN_RATE_OFF 20 | |
30 | #define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF) | |
31 | #define PHY_CONN_RATE 0x30 | |
32 | #define HGC_TRANS_TASK_CNT_LIMIT 0x38 | |
33 | #define AXI_AHB_CLK_CFG 0x3c | |
34 | #define ITCT_CLR 0x44 | |
35 | #define ITCT_CLR_EN_OFF 16 | |
36 | #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) | |
37 | #define ITCT_DEV_OFF 0 | |
38 | #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) | |
39 | #define AXI_USER1 0x48 | |
40 | #define AXI_USER2 0x4c | |
41 | #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 | |
42 | #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c | |
43 | #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 | |
44 | #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 | |
45 | #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 | |
46 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 | |
47 | #define HGC_GET_ITV_TIME 0x90 | |
48 | #define DEVICE_MSG_WORK_MODE 0x94 | |
49 | #define OPENA_WT_CONTI_TIME 0x9c | |
50 | #define I_T_NEXUS_LOSS_TIME 0xa0 | |
51 | #define MAX_CON_TIME_LIMIT_TIME 0xa4 | |
52 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 | |
53 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac | |
54 | #define CFG_AGING_TIME 0xbc | |
55 | #define HGC_DFX_CFG2 0xc0 | |
56 | #define HGC_IOMB_PROC1_STATUS 0x104 | |
57 | #define CFG_1US_TIMER_TRSH 0xcc | |
58 | #define HGC_INVLD_DQE_INFO 0x148 | |
59 | #define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9 | |
60 | #define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF) | |
61 | #define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18 | |
62 | #define INT_COAL_EN 0x19c | |
63 | #define OQ_INT_COAL_TIME 0x1a0 | |
64 | #define OQ_INT_COAL_CNT 0x1a4 | |
65 | #define ENT_INT_COAL_TIME 0x1a8 | |
66 | #define ENT_INT_COAL_CNT 0x1ac | |
67 | #define OQ_INT_SRC 0x1b0 | |
68 | #define OQ_INT_SRC_MSK 0x1b4 | |
69 | #define ENT_INT_SRC1 0x1b8 | |
70 | #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 | |
71 | #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) | |
72 | #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 | |
73 | #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) | |
74 | #define ENT_INT_SRC2 0x1bc | |
75 | #define ENT_INT_SRC3 0x1c0 | |
76 | #define ENT_INT_SRC3_ITC_INT_OFF 15 | |
77 | #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) | |
78 | #define ENT_INT_SRC_MSK1 0x1c4 | |
79 | #define ENT_INT_SRC_MSK2 0x1c8 | |
80 | #define ENT_INT_SRC_MSK3 0x1cc | |
81 | #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 | |
82 | #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) | |
83 | #define SAS_ECC_INTR_MSK 0x1ec | |
84 | #define HGC_ERR_STAT_EN 0x238 | |
85 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 | |
86 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 | |
87 | #define DLVRY_Q_0_DEPTH 0x268 | |
88 | #define DLVRY_Q_0_WR_PTR 0x26c | |
89 | #define DLVRY_Q_0_RD_PTR 0x270 | |
90 | #define HYPER_STREAM_ID_EN_CFG 0xc80 | |
91 | #define OQ0_INT_SRC_MSK 0xc90 | |
92 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 | |
93 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 | |
94 | #define COMPL_Q_0_DEPTH 0x4e8 | |
95 | #define COMPL_Q_0_WR_PTR 0x4ec | |
96 | #define COMPL_Q_0_RD_PTR 0x4f0 | |
97 | ||
98 | /* phy registers need init */ | |
99 | #define PORT_BASE (0x2000) | |
100 | ||
101 | #define PHY_CFG (PORT_BASE + 0x0) | |
102 | #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) | |
103 | #define PHY_CFG_ENA_OFF 0 | |
104 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) | |
105 | #define PHY_CFG_DC_OPT_OFF 2 | |
106 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) | |
107 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) | |
108 | #define PROG_PHY_LINK_RATE_MAX_OFF 0 | |
109 | #define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF) | |
110 | #define PHY_CTRL (PORT_BASE + 0x14) | |
111 | #define PHY_CTRL_RESET_OFF 0 | |
112 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | |
113 | #define SAS_PHY_CTRL (PORT_BASE + 0x20) | |
114 | #define SL_CFG (PORT_BASE + 0x84) | |
115 | #define PHY_PCN (PORT_BASE + 0x44) | |
116 | #define SL_TOUT_CFG (PORT_BASE + 0x8c) | |
117 | #define SL_CONTROL (PORT_BASE + 0x94) | |
118 | #define SL_CONTROL_NOTIFY_EN_OFF 0 | |
119 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) | |
120 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) | |
121 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) | |
122 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) | |
123 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) | |
124 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) | |
125 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) | |
126 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) | |
127 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) | |
128 | #define RX_IDAF_DWORD1 (PORT_BASE + 0xc8) | |
129 | #define RX_IDAF_DWORD2 (PORT_BASE + 0xcc) | |
130 | #define RX_IDAF_DWORD3 (PORT_BASE + 0xd0) | |
131 | #define RX_IDAF_DWORD4 (PORT_BASE + 0xd4) | |
132 | #define RX_IDAF_DWORD5 (PORT_BASE + 0xd8) | |
133 | #define RX_IDAF_DWORD6 (PORT_BASE + 0xdc) | |
134 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) | |
135 | #define DONE_RECEIVED_TIME (PORT_BASE + 0x11c) | |
136 | #define CHL_INT0 (PORT_BASE + 0x1b4) | |
137 | #define CHL_INT0_HOTPLUG_TOUT_OFF 0 | |
138 | #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) | |
139 | #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 | |
140 | #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) | |
141 | #define CHL_INT0_SL_PHY_ENABLE_OFF 2 | |
142 | #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) | |
143 | #define CHL_INT0_NOT_RDY_OFF 4 | |
144 | #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) | |
145 | #define CHL_INT0_PHY_RDY_OFF 5 | |
146 | #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) | |
147 | #define CHL_INT1 (PORT_BASE + 0x1b8) | |
148 | #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 | |
149 | #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) | |
150 | #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 | |
151 | #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) | |
152 | #define CHL_INT2 (PORT_BASE + 0x1bc) | |
153 | #define CHL_INT0_MSK (PORT_BASE + 0x1c0) | |
154 | #define CHL_INT1_MSK (PORT_BASE + 0x1c4) | |
155 | #define CHL_INT2_MSK (PORT_BASE + 0x1c8) | |
156 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) | |
157 | #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) | |
158 | #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) | |
159 | #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) | |
160 | #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) | |
161 | #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) | |
162 | #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) | |
163 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) | |
164 | #define DMA_TX_STATUS_BUSY_OFF 0 | |
165 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) | |
166 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) | |
167 | #define DMA_RX_STATUS_BUSY_OFF 0 | |
168 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) | |
169 | ||
170 | #define AXI_CFG (0x5100) | |
171 | #define AM_CFG_MAX_TRANS (0x5010) | |
172 | #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) | |
173 | ||
174 | /* HW dma structures */ | |
175 | /* Delivery queue header */ | |
176 | /* dw0 */ | |
a3e665d9 JG |
177 | #define CMD_HDR_ABORT_FLAG_OFF 0 |
178 | #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) | |
179 | #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 | |
180 | #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
45c901b8 JG |
181 | #define CMD_HDR_RESP_REPORT_OFF 5 |
182 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) | |
183 | #define CMD_HDR_TLR_CTRL_OFF 6 | |
184 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) | |
185 | #define CMD_HDR_PORT_OFF 18 | |
186 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) | |
187 | #define CMD_HDR_PRIORITY_OFF 27 | |
188 | #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) | |
189 | #define CMD_HDR_CMD_OFF 29 | |
190 | #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) | |
191 | /* dw1 */ | |
192 | #define CMD_HDR_DIR_OFF 5 | |
193 | #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) | |
194 | #define CMD_HDR_RESET_OFF 7 | |
195 | #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) | |
196 | #define CMD_HDR_VDTL_OFF 10 | |
197 | #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) | |
198 | #define CMD_HDR_FRAME_TYPE_OFF 11 | |
199 | #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) | |
200 | #define CMD_HDR_DEV_ID_OFF 16 | |
201 | #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) | |
202 | /* dw2 */ | |
203 | #define CMD_HDR_CFL_OFF 0 | |
204 | #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) | |
205 | #define CMD_HDR_NCQ_TAG_OFF 10 | |
206 | #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) | |
207 | #define CMD_HDR_MRFL_OFF 15 | |
208 | #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) | |
209 | #define CMD_HDR_SG_MOD_OFF 24 | |
210 | #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) | |
211 | #define CMD_HDR_FIRST_BURST_OFF 26 | |
212 | #define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF) | |
213 | /* dw3 */ | |
214 | #define CMD_HDR_IPTT_OFF 0 | |
215 | #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) | |
216 | /* dw6 */ | |
217 | #define CMD_HDR_DIF_SGL_LEN_OFF 0 | |
218 | #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) | |
219 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 | |
220 | #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) | |
a3e665d9 JG |
221 | #define CMD_HDR_ABORT_IPTT_OFF 16 |
222 | #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) | |
45c901b8 JG |
223 | |
224 | /* Completion header */ | |
225 | /* dw0 */ | |
226 | #define CMPLT_HDR_RSPNS_XFRD_OFF 10 | |
227 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) | |
228 | #define CMPLT_HDR_ERX_OFF 12 | |
229 | #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) | |
df032d0e JG |
230 | #define CMPLT_HDR_ABORT_STAT_OFF 13 |
231 | #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) | |
232 | /* abort_stat */ | |
233 | #define STAT_IO_NOT_VALID 0x1 | |
234 | #define STAT_IO_NO_DEVICE 0x2 | |
235 | #define STAT_IO_COMPLETE 0x3 | |
236 | #define STAT_IO_ABORTED 0x4 | |
45c901b8 JG |
237 | /* dw1 */ |
238 | #define CMPLT_HDR_IPTT_OFF 0 | |
239 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) | |
240 | #define CMPLT_HDR_DEV_ID_OFF 16 | |
241 | #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) | |
242 | ||
243 | /* ITCT header */ | |
244 | /* qw0 */ | |
245 | #define ITCT_HDR_DEV_TYPE_OFF 0 | |
246 | #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) | |
247 | #define ITCT_HDR_VALID_OFF 2 | |
248 | #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) | |
249 | #define ITCT_HDR_MCR_OFF 5 | |
250 | #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) | |
251 | #define ITCT_HDR_VLN_OFF 9 | |
252 | #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) | |
253 | #define ITCT_HDR_PORT_ID_OFF 28 | |
254 | #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) | |
255 | /* qw2 */ | |
256 | #define ITCT_HDR_INLT_OFF 0 | |
257 | #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) | |
258 | #define ITCT_HDR_BITLT_OFF 16 | |
259 | #define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF) | |
260 | #define ITCT_HDR_MCTLT_OFF 32 | |
261 | #define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF) | |
262 | #define ITCT_HDR_RTOLT_OFF 48 | |
263 | #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) | |
264 | ||
94eac9e1 JG |
265 | struct hisi_sas_complete_v2_hdr { |
266 | __le32 dw0; | |
267 | __le32 dw1; | |
268 | __le32 act; | |
269 | __le32 dw3; | |
270 | }; | |
271 | ||
e8fed0e9 JG |
272 | struct hisi_sas_err_record_v2 { |
273 | /* dw0 */ | |
274 | __le32 trans_tx_fail_type; | |
275 | ||
276 | /* dw1 */ | |
277 | __le32 trans_rx_fail_type; | |
278 | ||
279 | /* dw2 */ | |
280 | __le16 dma_tx_err_type; | |
281 | __le16 sipc_rx_err_type; | |
282 | ||
283 | /* dw3 */ | |
284 | __le32 dma_rx_err_type; | |
285 | }; | |
286 | ||
7911e66f JG |
287 | enum { |
288 | HISI_SAS_PHY_PHY_UPDOWN, | |
d3bf3d84 | 289 | HISI_SAS_PHY_CHNL_INT, |
7911e66f JG |
290 | HISI_SAS_PHY_INT_NR |
291 | }; | |
292 | ||
e8fed0e9 JG |
293 | enum { |
294 | TRANS_TX_FAIL_BASE = 0x0, /* dw0 */ | |
295 | TRANS_RX_FAIL_BASE = 0x100, /* dw1 */ | |
296 | DMA_TX_ERR_BASE = 0x200, /* dw2 bit 15-0 */ | |
297 | SIPC_RX_ERR_BASE = 0x300, /* dw2 bit 31-16*/ | |
298 | DMA_RX_ERR_BASE = 0x400, /* dw3 */ | |
299 | ||
300 | /* trans tx*/ | |
301 | TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS = TRANS_TX_FAIL_BASE, /* 0x0 */ | |
302 | TRANS_TX_ERR_PHY_NOT_ENABLE, /* 0x1 */ | |
303 | TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION, /* 0x2 */ | |
304 | TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION, /* 0x3 */ | |
305 | TRANS_TX_OPEN_CNX_ERR_BY_OTHER, /* 0x4 */ | |
306 | RESERVED0, /* 0x5 */ | |
307 | TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT, /* 0x6 */ | |
308 | TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY, /* 0x7 */ | |
309 | TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED, /* 0x8 */ | |
310 | TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED, /* 0x9 */ | |
311 | TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION, /* 0xa */ | |
312 | TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD, /* 0xb */ | |
313 | TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER, /* 0xc */ | |
314 | TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED, /* 0xd */ | |
315 | TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT, /* 0xe */ | |
316 | TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION, /* 0xf */ | |
317 | TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED, /* 0x10 */ | |
318 | TRANS_TX_ERR_FRAME_TXED, /* 0x11 */ | |
319 | TRANS_TX_ERR_WITH_BREAK_TIMEOUT, /* 0x12 */ | |
320 | TRANS_TX_ERR_WITH_BREAK_REQUEST, /* 0x13 */ | |
321 | TRANS_TX_ERR_WITH_BREAK_RECEVIED, /* 0x14 */ | |
322 | TRANS_TX_ERR_WITH_CLOSE_TIMEOUT, /* 0x15 */ | |
323 | TRANS_TX_ERR_WITH_CLOSE_NORMAL, /* 0x16 for ssp*/ | |
324 | TRANS_TX_ERR_WITH_CLOSE_PHYDISALE, /* 0x17 */ | |
325 | TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x18 */ | |
326 | TRANS_TX_ERR_WITH_CLOSE_COMINIT, /* 0x19 */ | |
327 | TRANS_TX_ERR_WITH_NAK_RECEVIED, /* 0x1a for ssp*/ | |
328 | TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT, /* 0x1b for ssp*/ | |
329 | /*IO_TX_ERR_WITH_R_ERR_RECEVIED, [> 0x1b for sata/stp<] */ | |
330 | TRANS_TX_ERR_WITH_CREDIT_TIMEOUT, /* 0x1c for ssp */ | |
331 | /*IO_RX_ERR_WITH_SATA_DEVICE_LOST 0x1c for sata/stp */ | |
332 | TRANS_TX_ERR_WITH_IPTT_CONFLICT, /* 0x1d for ssp/smp */ | |
333 | TRANS_TX_ERR_WITH_OPEN_BY_DES_OR_OTHERS, /* 0x1e */ | |
334 | /*IO_TX_ERR_WITH_SYNC_RXD, [> 0x1e <] for sata/stp */ | |
335 | TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT, /* 0x1f for sata/stp */ | |
336 | ||
337 | /* trans rx */ | |
338 | TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR = TRANS_RX_FAIL_BASE, /* 0x100 */ | |
339 | TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR, /* 0x101 for sata/stp */ | |
340 | TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM, /* 0x102 for ssp/smp */ | |
341 | /*IO_ERR_WITH_RXFIS_8B10B_CODE_ERR, [> 0x102 <] for sata/stp */ | |
342 | TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR, /* 0x103 for sata/stp */ | |
343 | TRANS_RX_ERR_WITH_RXFIS_CRC_ERR, /* 0x104 for sata/stp */ | |
344 | TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN, /* 0x105 for smp */ | |
345 | /*IO_ERR_WITH_RXFIS_TX SYNCP, [> 0x105 <] for sata/stp */ | |
346 | TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP, /* 0x106 for sata/stp*/ | |
347 | TRANS_RX_ERR_WITH_LINK_BUF_OVERRUN, /* 0x107 */ | |
348 | TRANS_RX_ERR_WITH_BREAK_TIMEOUT, /* 0x108 */ | |
349 | TRANS_RX_ERR_WITH_BREAK_REQUEST, /* 0x109 */ | |
350 | TRANS_RX_ERR_WITH_BREAK_RECEVIED, /* 0x10a */ | |
351 | RESERVED1, /* 0x10b */ | |
352 | TRANS_RX_ERR_WITH_CLOSE_NORMAL, /* 0x10c */ | |
353 | TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE, /* 0x10d */ | |
354 | TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT, /* 0x10e */ | |
355 | TRANS_RX_ERR_WITH_CLOSE_COMINIT, /* 0x10f */ | |
356 | TRANS_RX_ERR_WITH_DATA_LEN0, /* 0x110 for ssp/smp */ | |
357 | TRANS_RX_ERR_WITH_BAD_HASH, /* 0x111 for ssp */ | |
358 | /*IO_RX_ERR_WITH_FIS_TOO_SHORT, [> 0x111 <] for sata/stp */ | |
359 | TRANS_RX_XRDY_WLEN_ZERO_ERR, /* 0x112 for ssp*/ | |
360 | /*IO_RX_ERR_WITH_FIS_TOO_LONG, [> 0x112 <] for sata/stp */ | |
361 | TRANS_RX_SSP_FRM_LEN_ERR, /* 0x113 for ssp */ | |
362 | /*IO_RX_ERR_WITH_SATA_DEVICE_LOST, [> 0x113 <] for sata */ | |
363 | RESERVED2, /* 0x114 */ | |
364 | RESERVED3, /* 0x115 */ | |
365 | RESERVED4, /* 0x116 */ | |
366 | RESERVED5, /* 0x117 */ | |
367 | TRANS_RX_ERR_WITH_BAD_FRM_TYPE, /* 0x118 */ | |
368 | TRANS_RX_SMP_FRM_LEN_ERR, /* 0x119 */ | |
369 | TRANS_RX_SMP_RESP_TIMEOUT_ERR, /* 0x11a */ | |
370 | RESERVED6, /* 0x11b */ | |
371 | RESERVED7, /* 0x11c */ | |
372 | RESERVED8, /* 0x11d */ | |
373 | RESERVED9, /* 0x11e */ | |
374 | TRANS_RX_R_ERR, /* 0x11f */ | |
375 | ||
376 | /* dma tx */ | |
377 | DMA_TX_DIF_CRC_ERR = DMA_TX_ERR_BASE, /* 0x200 */ | |
378 | DMA_TX_DIF_APP_ERR, /* 0x201 */ | |
379 | DMA_TX_DIF_RPP_ERR, /* 0x202 */ | |
380 | DMA_TX_DATA_SGL_OVERFLOW, /* 0x203 */ | |
381 | DMA_TX_DIF_SGL_OVERFLOW, /* 0x204 */ | |
382 | DMA_TX_UNEXP_XFER_ERR, /* 0x205 */ | |
383 | DMA_TX_UNEXP_RETRANS_ERR, /* 0x206 */ | |
384 | DMA_TX_XFER_LEN_OVERFLOW, /* 0x207 */ | |
385 | DMA_TX_XFER_OFFSET_ERR, /* 0x208 */ | |
386 | DMA_TX_RAM_ECC_ERR, /* 0x209 */ | |
387 | DMA_TX_DIF_LEN_ALIGN_ERR, /* 0x20a */ | |
388 | ||
389 | /* sipc rx */ | |
390 | SIPC_RX_FIS_STATUS_ERR_BIT_VLD = SIPC_RX_ERR_BASE, /* 0x300 */ | |
391 | SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR, /* 0x301 */ | |
392 | SIPC_RX_FIS_STATUS_BSY_BIT_ERR, /* 0x302 */ | |
393 | SIPC_RX_WRSETUP_LEN_ODD_ERR, /* 0x303 */ | |
394 | SIPC_RX_WRSETUP_LEN_ZERO_ERR, /* 0x304 */ | |
395 | SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR, /* 0x305 */ | |
396 | SIPC_RX_NCQ_WRSETUP_OFFSET_ERR, /* 0x306 */ | |
397 | SIPC_RX_NCQ_WRSETUP_AUTO_ACTIVE_ERR, /* 0x307 */ | |
398 | SIPC_RX_SATA_UNEXP_FIS_ERR, /* 0x308 */ | |
399 | SIPC_RX_WRSETUP_ESTATUS_ERR, /* 0x309 */ | |
400 | SIPC_RX_DATA_UNDERFLOW_ERR, /* 0x30a */ | |
401 | ||
402 | /* dma rx */ | |
403 | DMA_RX_DIF_CRC_ERR = DMA_RX_ERR_BASE, /* 0x400 */ | |
404 | DMA_RX_DIF_APP_ERR, /* 0x401 */ | |
405 | DMA_RX_DIF_RPP_ERR, /* 0x402 */ | |
406 | DMA_RX_DATA_SGL_OVERFLOW, /* 0x403 */ | |
407 | DMA_RX_DIF_SGL_OVERFLOW, /* 0x404 */ | |
408 | DMA_RX_DATA_LEN_OVERFLOW, /* 0x405 */ | |
409 | DMA_RX_DATA_LEN_UNDERFLOW, /* 0x406 */ | |
410 | DMA_RX_DATA_OFFSET_ERR, /* 0x407 */ | |
411 | RESERVED10, /* 0x408 */ | |
412 | DMA_RX_SATA_FRAME_TYPE_ERR, /* 0x409 */ | |
413 | DMA_RX_RESP_BUF_OVERFLOW, /* 0x40a */ | |
414 | DMA_RX_UNEXP_RETRANS_RESP_ERR, /* 0x40b */ | |
415 | DMA_RX_UNEXP_NORM_RESP_ERR, /* 0x40c */ | |
416 | DMA_RX_UNEXP_RDFRAME_ERR, /* 0x40d */ | |
417 | DMA_RX_PIO_DATA_LEN_ERR, /* 0x40e */ | |
418 | DMA_RX_RDSETUP_STATUS_ERR, /* 0x40f */ | |
419 | DMA_RX_RDSETUP_STATUS_DRQ_ERR, /* 0x410 */ | |
420 | DMA_RX_RDSETUP_STATUS_BSY_ERR, /* 0x411 */ | |
421 | DMA_RX_RDSETUP_LEN_ODD_ERR, /* 0x412 */ | |
422 | DMA_RX_RDSETUP_LEN_ZERO_ERR, /* 0x413 */ | |
423 | DMA_RX_RDSETUP_LEN_OVER_ERR, /* 0x414 */ | |
424 | DMA_RX_RDSETUP_OFFSET_ERR, /* 0x415 */ | |
425 | DMA_RX_RDSETUP_ACTIVE_ERR, /* 0x416 */ | |
426 | DMA_RX_RDSETUP_ESTATUS_ERR, /* 0x417 */ | |
427 | DMA_RX_RAM_ECC_ERR, /* 0x418 */ | |
428 | DMA_RX_UNKNOWN_FRM_ERR, /* 0x419 */ | |
429 | }; | |
430 | ||
94eac9e1 JG |
431 | #define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096 |
432 | ||
8c36e31d JG |
433 | #define DIR_NO_DATA 0 |
434 | #define DIR_TO_INI 1 | |
435 | #define DIR_TO_DEVICE 2 | |
436 | #define DIR_RESERVED 3 | |
437 | ||
6f2ff1a1 JG |
438 | #define SATA_PROTOCOL_NONDATA 0x1 |
439 | #define SATA_PROTOCOL_PIO 0x2 | |
440 | #define SATA_PROTOCOL_DMA 0x4 | |
441 | #define SATA_PROTOCOL_FPDMA 0x8 | |
442 | #define SATA_PROTOCOL_ATAPI 0x10 | |
443 | ||
94eac9e1 JG |
444 | static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) |
445 | { | |
446 | void __iomem *regs = hisi_hba->regs + off; | |
447 | ||
448 | return readl(regs); | |
449 | } | |
450 | ||
8c36e31d JG |
451 | static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) |
452 | { | |
453 | void __iomem *regs = hisi_hba->regs + off; | |
454 | ||
455 | return readl_relaxed(regs); | |
456 | } | |
457 | ||
94eac9e1 JG |
458 | static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) |
459 | { | |
460 | void __iomem *regs = hisi_hba->regs + off; | |
461 | ||
462 | writel(val, regs); | |
463 | } | |
464 | ||
465 | static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, | |
466 | u32 off, u32 val) | |
467 | { | |
468 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
469 | ||
470 | writel(val, regs); | |
471 | } | |
472 | ||
473 | static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, | |
474 | int phy_no, u32 off) | |
475 | { | |
476 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
477 | ||
478 | return readl(regs); | |
479 | } | |
480 | ||
330fa7f3 JG |
481 | /* This function needs to be protected from pre-emption. */ |
482 | static int | |
483 | slot_index_alloc_quirk_v2_hw(struct hisi_hba *hisi_hba, int *slot_idx, | |
484 | struct domain_device *device) | |
485 | { | |
486 | unsigned int index = 0; | |
487 | void *bitmap = hisi_hba->slot_index_tags; | |
488 | int sata_dev = dev_is_sata(device); | |
489 | ||
490 | while (1) { | |
491 | index = find_next_zero_bit(bitmap, hisi_hba->slot_index_count, | |
492 | index); | |
493 | if (index >= hisi_hba->slot_index_count) | |
494 | return -SAS_QUEUE_FULL; | |
495 | /* | |
496 | * SAS IPTT bit0 should be 1 | |
497 | */ | |
498 | if (sata_dev || (index & 1)) | |
499 | break; | |
500 | index++; | |
501 | } | |
502 | ||
503 | set_bit(index, bitmap); | |
504 | *slot_idx = index; | |
505 | return 0; | |
506 | } | |
507 | ||
b2bdaf2b JG |
508 | static struct |
509 | hisi_sas_device *alloc_dev_quirk_v2_hw(struct domain_device *device) | |
510 | { | |
511 | struct hisi_hba *hisi_hba = device->port->ha->lldd_ha; | |
512 | struct hisi_sas_device *sas_dev = NULL; | |
513 | int i, sata_dev = dev_is_sata(device); | |
514 | ||
515 | spin_lock(&hisi_hba->lock); | |
516 | for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) { | |
517 | /* | |
518 | * SATA device id bit0 should be 0 | |
519 | */ | |
520 | if (sata_dev && (i & 1)) | |
521 | continue; | |
522 | if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) { | |
523 | hisi_hba->devices[i].device_id = i; | |
524 | sas_dev = &hisi_hba->devices[i]; | |
525 | sas_dev->dev_status = HISI_SAS_DEV_NORMAL; | |
526 | sas_dev->dev_type = device->dev_type; | |
527 | sas_dev->hisi_hba = hisi_hba; | |
528 | sas_dev->sas_device = device; | |
529 | break; | |
530 | } | |
531 | } | |
532 | spin_unlock(&hisi_hba->lock); | |
533 | ||
534 | return sas_dev; | |
535 | } | |
536 | ||
29a20428 JG |
537 | static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
538 | { | |
539 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
540 | ||
541 | cfg &= ~PHY_CFG_DC_OPT_MSK; | |
542 | cfg |= 1 << PHY_CFG_DC_OPT_OFF; | |
543 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
544 | } | |
545 | ||
806bb768 JG |
546 | static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
547 | { | |
548 | struct sas_identify_frame identify_frame; | |
549 | u32 *identify_buffer; | |
550 | ||
551 | memset(&identify_frame, 0, sizeof(identify_frame)); | |
552 | identify_frame.dev_type = SAS_END_DEVICE; | |
553 | identify_frame.frame_type = 0; | |
554 | identify_frame._un1 = 1; | |
555 | identify_frame.initiator_bits = SAS_PROTOCOL_ALL; | |
556 | identify_frame.target_bits = SAS_PROTOCOL_NONE; | |
557 | memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
558 | memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
559 | identify_frame.phy_id = phy_no; | |
560 | identify_buffer = (u32 *)(&identify_frame); | |
561 | ||
562 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, | |
563 | __swab32(identify_buffer[0])); | |
564 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, | |
d82debec | 565 | __swab32(identify_buffer[1])); |
806bb768 | 566 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, |
d82debec | 567 | __swab32(identify_buffer[2])); |
806bb768 | 568 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, |
d82debec | 569 | __swab32(identify_buffer[3])); |
806bb768 | 570 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, |
d82debec | 571 | __swab32(identify_buffer[4])); |
806bb768 JG |
572 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, |
573 | __swab32(identify_buffer[5])); | |
574 | } | |
575 | ||
85b2c3c0 JG |
576 | static void setup_itct_v2_hw(struct hisi_hba *hisi_hba, |
577 | struct hisi_sas_device *sas_dev) | |
578 | { | |
579 | struct domain_device *device = sas_dev->sas_device; | |
580 | struct device *dev = &hisi_hba->pdev->dev; | |
581 | u64 qw0, device_id = sas_dev->device_id; | |
582 | struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; | |
583 | struct domain_device *parent_dev = device->parent; | |
584 | struct hisi_sas_port *port = device->port->lldd_port; | |
585 | ||
586 | memset(itct, 0, sizeof(*itct)); | |
587 | ||
588 | /* qw0 */ | |
589 | qw0 = 0; | |
590 | switch (sas_dev->dev_type) { | |
591 | case SAS_END_DEVICE: | |
592 | case SAS_EDGE_EXPANDER_DEVICE: | |
593 | case SAS_FANOUT_EXPANDER_DEVICE: | |
594 | qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; | |
595 | break; | |
596 | case SAS_SATA_DEV: | |
597 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
598 | qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; | |
599 | else | |
600 | qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; | |
601 | break; | |
602 | default: | |
603 | dev_warn(dev, "setup itct: unsupported dev type (%d)\n", | |
604 | sas_dev->dev_type); | |
605 | } | |
606 | ||
607 | qw0 |= ((1 << ITCT_HDR_VALID_OFF) | | |
75249268 | 608 | (device->linkrate << ITCT_HDR_MCR_OFF) | |
85b2c3c0 JG |
609 | (1 << ITCT_HDR_VLN_OFF) | |
610 | (port->id << ITCT_HDR_PORT_ID_OFF)); | |
611 | itct->qw0 = cpu_to_le64(qw0); | |
612 | ||
613 | /* qw1 */ | |
614 | memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); | |
615 | itct->sas_addr = __swab64(itct->sas_addr); | |
616 | ||
617 | /* qw2 */ | |
f76a0b49 JG |
618 | if (!dev_is_sata(device)) |
619 | itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) | | |
620 | (0x1ULL << ITCT_HDR_BITLT_OFF) | | |
621 | (0x32ULL << ITCT_HDR_MCTLT_OFF) | | |
622 | (0x1ULL << ITCT_HDR_RTOLT_OFF)); | |
85b2c3c0 JG |
623 | } |
624 | ||
625 | static void free_device_v2_hw(struct hisi_hba *hisi_hba, | |
626 | struct hisi_sas_device *sas_dev) | |
627 | { | |
628 | u64 qw0, dev_id = sas_dev->device_id; | |
629 | struct device *dev = &hisi_hba->pdev->dev; | |
630 | struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; | |
631 | u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
632 | int i; | |
633 | ||
634 | /* clear the itct interrupt state */ | |
635 | if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) | |
636 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, | |
637 | ENT_INT_SRC3_ITC_INT_MSK); | |
638 | ||
639 | /* clear the itct int*/ | |
640 | for (i = 0; i < 2; i++) { | |
641 | /* clear the itct table*/ | |
642 | reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); | |
643 | reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); | |
644 | hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); | |
645 | ||
646 | udelay(10); | |
647 | reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
648 | if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) { | |
649 | dev_dbg(dev, "got clear ITCT done interrupt\n"); | |
650 | ||
651 | /* invalid the itct state*/ | |
652 | qw0 = cpu_to_le64(itct->qw0); | |
653 | qw0 &= ~(1 << ITCT_HDR_VALID_OFF); | |
654 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, | |
655 | ENT_INT_SRC3_ITC_INT_MSK); | |
656 | hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED; | |
657 | hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL; | |
658 | ||
659 | /* clear the itct */ | |
660 | hisi_sas_write32(hisi_hba, ITCT_CLR, 0); | |
661 | dev_dbg(dev, "clear ITCT ok\n"); | |
662 | break; | |
663 | } | |
664 | } | |
665 | } | |
666 | ||
94eac9e1 JG |
667 | static int reset_hw_v2_hw(struct hisi_hba *hisi_hba) |
668 | { | |
669 | int i, reset_val; | |
670 | u32 val; | |
671 | unsigned long end_time; | |
672 | struct device *dev = &hisi_hba->pdev->dev; | |
673 | ||
674 | /* The mask needs to be set depending on the number of phys */ | |
675 | if (hisi_hba->n_phy == 9) | |
676 | reset_val = 0x1fffff; | |
677 | else | |
678 | reset_val = 0x7ffff; | |
679 | ||
d0df8f9a | 680 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); |
94eac9e1 JG |
681 | |
682 | /* Disable all of the PHYs */ | |
683 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
684 | u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG); | |
685 | ||
686 | phy_cfg &= ~PHY_CTRL_RESET_MSK; | |
687 | hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg); | |
688 | } | |
689 | udelay(50); | |
690 | ||
691 | /* Ensure DMA tx & rx idle */ | |
692 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
693 | u32 dma_tx_status, dma_rx_status; | |
694 | ||
695 | end_time = jiffies + msecs_to_jiffies(1000); | |
696 | ||
697 | while (1) { | |
698 | dma_tx_status = hisi_sas_phy_read32(hisi_hba, i, | |
699 | DMA_TX_STATUS); | |
700 | dma_rx_status = hisi_sas_phy_read32(hisi_hba, i, | |
701 | DMA_RX_STATUS); | |
702 | ||
703 | if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) && | |
704 | !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK)) | |
705 | break; | |
706 | ||
707 | msleep(20); | |
708 | if (time_after(jiffies, end_time)) | |
709 | return -EIO; | |
710 | } | |
711 | } | |
712 | ||
713 | /* Ensure axi bus idle */ | |
714 | end_time = jiffies + msecs_to_jiffies(1000); | |
715 | while (1) { | |
716 | u32 axi_status = | |
717 | hisi_sas_read32(hisi_hba, AXI_CFG); | |
718 | ||
719 | if (axi_status == 0) | |
720 | break; | |
721 | ||
722 | msleep(20); | |
723 | if (time_after(jiffies, end_time)) | |
724 | return -EIO; | |
725 | } | |
726 | ||
50408712 JG |
727 | if (ACPI_HANDLE(dev)) { |
728 | acpi_status s; | |
94eac9e1 | 729 | |
50408712 JG |
730 | s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); |
731 | if (ACPI_FAILURE(s)) { | |
732 | dev_err(dev, "Reset failed\n"); | |
733 | return -EIO; | |
734 | } | |
735 | } else if (hisi_hba->ctrl) { | |
736 | /* reset and disable clock*/ | |
737 | regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg, | |
738 | reset_val); | |
739 | regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4, | |
740 | reset_val); | |
741 | msleep(1); | |
742 | regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val); | |
743 | if (reset_val != (val & reset_val)) { | |
744 | dev_err(dev, "SAS reset fail.\n"); | |
745 | return -EIO; | |
746 | } | |
747 | ||
748 | /* De-reset and enable clock*/ | |
749 | regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4, | |
750 | reset_val); | |
751 | regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg, | |
752 | reset_val); | |
753 | msleep(1); | |
754 | regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, | |
755 | &val); | |
756 | if (val & reset_val) { | |
757 | dev_err(dev, "SAS de-reset fail.\n"); | |
758 | return -EIO; | |
759 | } | |
760 | } else | |
761 | dev_warn(dev, "no reset method\n"); | |
94eac9e1 JG |
762 | |
763 | return 0; | |
764 | } | |
765 | ||
766 | static void init_reg_v2_hw(struct hisi_hba *hisi_hba) | |
767 | { | |
768 | struct device *dev = &hisi_hba->pdev->dev; | |
94eac9e1 JG |
769 | int i; |
770 | ||
771 | /* Global registers init */ | |
772 | ||
773 | /* Deal with am-max-transmissions quirk */ | |
50408712 | 774 | if (device_property_present(dev, "hip06-sas-v2-quirk-amt")) { |
94eac9e1 JG |
775 | hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020); |
776 | hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS, | |
777 | 0x2020); | |
778 | } /* Else, use defaults -> do nothing */ | |
779 | ||
780 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, | |
781 | (u32)((1ULL << hisi_hba->queue_count) - 1)); | |
782 | hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000); | |
783 | hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000); | |
784 | hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); | |
785 | hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF); | |
786 | hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1); | |
787 | hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4); | |
f76a0b49 | 788 | hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32); |
94eac9e1 JG |
789 | hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1); |
790 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); | |
791 | hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1); | |
792 | hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1); | |
793 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); | |
794 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
795 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
796 | hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1); | |
797 | hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1); | |
798 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0); | |
799 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); | |
800 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); | |
801 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); | |
802 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe); | |
803 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe); | |
804 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe); | |
805 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0); | |
806 | for (i = 0; i < hisi_hba->queue_count; i++) | |
807 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); | |
808 | ||
809 | hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1); | |
810 | hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); | |
811 | ||
812 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
813 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855); | |
814 | hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908); | |
815 | hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d); | |
816 | hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10); | |
817 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); | |
818 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); | |
819 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); | |
820 | hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); | |
821 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); | |
822 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff); | |
823 | hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc); | |
824 | hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); | |
825 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); | |
826 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); | |
827 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); | |
828 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); | |
829 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0); | |
830 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0); | |
831 | hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694); | |
832 | } | |
833 | ||
834 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
835 | /* Delivery queue */ | |
836 | hisi_sas_write32(hisi_hba, | |
837 | DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), | |
838 | upper_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
839 | ||
840 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), | |
841 | lower_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
842 | ||
843 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), | |
844 | HISI_SAS_QUEUE_SLOTS); | |
845 | ||
846 | /* Completion queue */ | |
847 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), | |
848 | upper_32_bits(hisi_hba->complete_hdr_dma[i])); | |
849 | ||
850 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), | |
851 | lower_32_bits(hisi_hba->complete_hdr_dma[i])); | |
852 | ||
853 | hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), | |
854 | HISI_SAS_QUEUE_SLOTS); | |
855 | } | |
856 | ||
857 | /* itct */ | |
858 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, | |
859 | lower_32_bits(hisi_hba->itct_dma)); | |
860 | ||
861 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, | |
862 | upper_32_bits(hisi_hba->itct_dma)); | |
863 | ||
864 | /* iost */ | |
865 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, | |
866 | lower_32_bits(hisi_hba->iost_dma)); | |
867 | ||
868 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, | |
869 | upper_32_bits(hisi_hba->iost_dma)); | |
870 | ||
871 | /* breakpoint */ | |
872 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, | |
873 | lower_32_bits(hisi_hba->breakpoint_dma)); | |
874 | ||
875 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, | |
876 | upper_32_bits(hisi_hba->breakpoint_dma)); | |
877 | ||
878 | /* SATA broken msg */ | |
879 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, | |
880 | lower_32_bits(hisi_hba->sata_breakpoint_dma)); | |
881 | ||
882 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, | |
883 | upper_32_bits(hisi_hba->sata_breakpoint_dma)); | |
884 | ||
885 | /* SATA initial fis */ | |
886 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, | |
887 | lower_32_bits(hisi_hba->initial_fis_dma)); | |
888 | ||
889 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, | |
890 | upper_32_bits(hisi_hba->initial_fis_dma)); | |
891 | } | |
892 | ||
893 | static int hw_init_v2_hw(struct hisi_hba *hisi_hba) | |
894 | { | |
895 | struct device *dev = &hisi_hba->pdev->dev; | |
896 | int rc; | |
897 | ||
898 | rc = reset_hw_v2_hw(hisi_hba); | |
899 | if (rc) { | |
900 | dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); | |
901 | return rc; | |
902 | } | |
903 | ||
904 | msleep(100); | |
905 | init_reg_v2_hw(hisi_hba); | |
806bb768 | 906 | |
94eac9e1 JG |
907 | return 0; |
908 | } | |
909 | ||
29a20428 JG |
910 | static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
911 | { | |
912 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
913 | ||
914 | cfg |= PHY_CFG_ENA_MSK; | |
915 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
916 | } | |
917 | ||
63fb11b8 JG |
918 | static void disable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
919 | { | |
920 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
921 | ||
922 | cfg &= ~PHY_CFG_ENA_MSK; | |
923 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
924 | } | |
925 | ||
29a20428 JG |
926 | static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
927 | { | |
928 | config_id_frame_v2_hw(hisi_hba, phy_no); | |
929 | config_phy_opt_mode_v2_hw(hisi_hba, phy_no); | |
930 | enable_phy_v2_hw(hisi_hba, phy_no); | |
931 | } | |
932 | ||
63fb11b8 JG |
933 | static void stop_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
934 | { | |
935 | disable_phy_v2_hw(hisi_hba, phy_no); | |
936 | } | |
937 | ||
938 | static void phy_hard_reset_v2_hw(struct hisi_hba *hisi_hba, int phy_no) | |
939 | { | |
940 | stop_phy_v2_hw(hisi_hba, phy_no); | |
941 | msleep(100); | |
942 | start_phy_v2_hw(hisi_hba, phy_no); | |
943 | } | |
944 | ||
29a20428 JG |
945 | static void start_phys_v2_hw(unsigned long data) |
946 | { | |
947 | struct hisi_hba *hisi_hba = (struct hisi_hba *)data; | |
948 | int i; | |
949 | ||
950 | for (i = 0; i < hisi_hba->n_phy; i++) | |
951 | start_phy_v2_hw(hisi_hba, i); | |
952 | } | |
953 | ||
954 | static void phys_init_v2_hw(struct hisi_hba *hisi_hba) | |
955 | { | |
29a20428 JG |
956 | struct timer_list *timer = &hisi_hba->timer; |
957 | ||
29a20428 JG |
958 | setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba); |
959 | mod_timer(timer, jiffies + HZ); | |
960 | } | |
961 | ||
7911e66f JG |
962 | static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no) |
963 | { | |
964 | u32 sl_control; | |
965 | ||
966 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
967 | sl_control |= SL_CONTROL_NOTIFY_EN_MSK; | |
968 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
969 | msleep(1); | |
970 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
971 | sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; | |
972 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
973 | } | |
974 | ||
5473c060 JG |
975 | static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id) |
976 | { | |
977 | int i, bitmap = 0; | |
978 | u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
979 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
980 | ||
981 | for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++) | |
982 | if (phy_state & 1 << i) | |
983 | if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) | |
984 | bitmap |= 1 << i; | |
985 | ||
986 | if (hisi_hba->n_phy == 9) { | |
987 | u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); | |
988 | ||
989 | if (phy_state & 1 << 8) | |
990 | if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> | |
991 | PORT_STATE_PHY8_PORT_NUM_OFF) == port_id) | |
992 | bitmap |= 1 << 9; | |
993 | } | |
994 | ||
995 | return bitmap; | |
996 | } | |
997 | ||
8c36e31d JG |
998 | /** |
999 | * This function allocates across all queues to load balance. | |
1000 | * Slots are allocated from queues in a round-robin fashion. | |
1001 | * | |
1002 | * The callpath to this function and upto writing the write | |
1003 | * queue pointer should be safe from interruption. | |
1004 | */ | |
1005 | static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s) | |
1006 | { | |
1007 | struct device *dev = &hisi_hba->pdev->dev; | |
4fde02ad | 1008 | struct hisi_sas_dq *dq; |
8c36e31d JG |
1009 | u32 r, w; |
1010 | int queue = hisi_hba->queue; | |
1011 | ||
1012 | while (1) { | |
4fde02ad JG |
1013 | dq = &hisi_hba->dq[queue]; |
1014 | w = dq->wr_point; | |
8c36e31d JG |
1015 | r = hisi_sas_read32_relaxed(hisi_hba, |
1016 | DLVRY_Q_0_RD_PTR + (queue * 0x14)); | |
1017 | if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { | |
1018 | queue = (queue + 1) % hisi_hba->queue_count; | |
1019 | if (queue == hisi_hba->queue) { | |
1020 | dev_warn(dev, "could not find free slot\n"); | |
1021 | return -EAGAIN; | |
1022 | } | |
1023 | continue; | |
1024 | } | |
1025 | break; | |
1026 | } | |
1027 | hisi_hba->queue = (queue + 1) % hisi_hba->queue_count; | |
1028 | *q = queue; | |
1029 | *s = w; | |
1030 | return 0; | |
1031 | } | |
1032 | ||
1033 | static void start_delivery_v2_hw(struct hisi_hba *hisi_hba) | |
1034 | { | |
1035 | int dlvry_queue = hisi_hba->slot_prep->dlvry_queue; | |
1036 | int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot; | |
4fde02ad | 1037 | struct hisi_sas_dq *dq = &hisi_hba->dq[dlvry_queue]; |
8c36e31d | 1038 | |
4fde02ad | 1039 | dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS; |
8c36e31d | 1040 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), |
4fde02ad | 1041 | dq->wr_point); |
8c36e31d JG |
1042 | } |
1043 | ||
1044 | static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba, | |
1045 | struct hisi_sas_slot *slot, | |
1046 | struct hisi_sas_cmd_hdr *hdr, | |
1047 | struct scatterlist *scatter, | |
1048 | int n_elem) | |
1049 | { | |
1050 | struct device *dev = &hisi_hba->pdev->dev; | |
1051 | struct scatterlist *sg; | |
1052 | int i; | |
1053 | ||
1054 | if (n_elem > HISI_SAS_SGE_PAGE_CNT) { | |
1055 | dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT", | |
1056 | n_elem); | |
1057 | return -EINVAL; | |
1058 | } | |
1059 | ||
1060 | slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC, | |
1061 | &slot->sge_page_dma); | |
1062 | if (!slot->sge_page) | |
1063 | return -ENOMEM; | |
1064 | ||
1065 | for_each_sg(scatter, sg, n_elem, i) { | |
1066 | struct hisi_sas_sge *entry = &slot->sge_page->sge[i]; | |
1067 | ||
1068 | entry->addr = cpu_to_le64(sg_dma_address(sg)); | |
1069 | entry->page_ctrl_0 = entry->page_ctrl_1 = 0; | |
1070 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); | |
1071 | entry->data_off = 0; | |
1072 | } | |
1073 | ||
1074 | hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma); | |
1075 | ||
1076 | hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); | |
1077 | ||
1078 | return 0; | |
1079 | } | |
1080 | ||
c2d89392 JG |
1081 | static int prep_smp_v2_hw(struct hisi_hba *hisi_hba, |
1082 | struct hisi_sas_slot *slot) | |
1083 | { | |
1084 | struct sas_task *task = slot->task; | |
1085 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1086 | struct domain_device *device = task->dev; | |
1087 | struct device *dev = &hisi_hba->pdev->dev; | |
1088 | struct hisi_sas_port *port = slot->port; | |
1089 | struct scatterlist *sg_req, *sg_resp; | |
1090 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1091 | dma_addr_t req_dma_addr; | |
1092 | unsigned int req_len, resp_len; | |
1093 | int elem, rc; | |
1094 | ||
1095 | /* | |
1096 | * DMA-map SMP request, response buffers | |
1097 | */ | |
1098 | /* req */ | |
1099 | sg_req = &task->smp_task.smp_req; | |
1100 | elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE); | |
1101 | if (!elem) | |
1102 | return -ENOMEM; | |
1103 | req_len = sg_dma_len(sg_req); | |
1104 | req_dma_addr = sg_dma_address(sg_req); | |
1105 | ||
1106 | /* resp */ | |
1107 | sg_resp = &task->smp_task.smp_resp; | |
1108 | elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE); | |
1109 | if (!elem) { | |
1110 | rc = -ENOMEM; | |
1111 | goto err_out_req; | |
1112 | } | |
1113 | resp_len = sg_dma_len(sg_resp); | |
1114 | if ((req_len & 0x3) || (resp_len & 0x3)) { | |
1115 | rc = -EINVAL; | |
1116 | goto err_out_resp; | |
1117 | } | |
1118 | ||
1119 | /* create header */ | |
1120 | /* dw0 */ | |
1121 | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | | |
1122 | (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ | |
1123 | (2 << CMD_HDR_CMD_OFF)); /* smp */ | |
1124 | ||
1125 | /* map itct entry */ | |
1126 | hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | | |
1127 | (1 << CMD_HDR_FRAME_TYPE_OFF) | | |
1128 | (DIR_NO_DATA << CMD_HDR_DIR_OFF)); | |
1129 | ||
1130 | /* dw2 */ | |
1131 | hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | | |
1132 | (HISI_SAS_MAX_SMP_RESP_SZ / 4 << | |
1133 | CMD_HDR_MRFL_OFF)); | |
1134 | ||
1135 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); | |
1136 | ||
1137 | hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); | |
1138 | hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); | |
1139 | ||
1140 | return 0; | |
1141 | ||
1142 | err_out_resp: | |
1143 | dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1, | |
1144 | DMA_FROM_DEVICE); | |
1145 | err_out_req: | |
1146 | dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1, | |
1147 | DMA_TO_DEVICE); | |
1148 | return rc; | |
1149 | } | |
1150 | ||
8c36e31d JG |
1151 | static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba, |
1152 | struct hisi_sas_slot *slot, int is_tmf, | |
1153 | struct hisi_sas_tmf_task *tmf) | |
1154 | { | |
1155 | struct sas_task *task = slot->task; | |
1156 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1157 | struct domain_device *device = task->dev; | |
1158 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1159 | struct hisi_sas_port *port = slot->port; | |
1160 | struct sas_ssp_task *ssp_task = &task->ssp_task; | |
1161 | struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; | |
1162 | int has_data = 0, rc, priority = is_tmf; | |
1163 | u8 *buf_cmd; | |
1164 | u32 dw1 = 0, dw2 = 0; | |
1165 | ||
1166 | hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | | |
1167 | (2 << CMD_HDR_TLR_CTRL_OFF) | | |
1168 | (port->id << CMD_HDR_PORT_OFF) | | |
1169 | (priority << CMD_HDR_PRIORITY_OFF) | | |
1170 | (1 << CMD_HDR_CMD_OFF)); /* ssp */ | |
1171 | ||
1172 | dw1 = 1 << CMD_HDR_VDTL_OFF; | |
1173 | if (is_tmf) { | |
1174 | dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; | |
1175 | dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; | |
1176 | } else { | |
1177 | dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; | |
1178 | switch (scsi_cmnd->sc_data_direction) { | |
1179 | case DMA_TO_DEVICE: | |
1180 | has_data = 1; | |
1181 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1182 | break; | |
1183 | case DMA_FROM_DEVICE: | |
1184 | has_data = 1; | |
1185 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1186 | break; | |
1187 | default: | |
1188 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | /* map itct entry */ | |
1193 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
1194 | hdr->dw1 = cpu_to_le32(dw1); | |
1195 | ||
1196 | dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) | |
1197 | + 3) / 4) << CMD_HDR_CFL_OFF) | | |
1198 | ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | | |
1199 | (2 << CMD_HDR_SG_MOD_OFF); | |
1200 | hdr->dw2 = cpu_to_le32(dw2); | |
1201 | ||
1202 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1203 | ||
1204 | if (has_data) { | |
1205 | rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, | |
1206 | slot->n_elem); | |
1207 | if (rc) | |
1208 | return rc; | |
1209 | } | |
1210 | ||
1211 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
1212 | hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); | |
1213 | hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); | |
1214 | ||
1215 | buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr); | |
1216 | ||
1217 | memcpy(buf_cmd, &task->ssp_task.LUN, 8); | |
1218 | if (!is_tmf) { | |
1219 | buf_cmd[9] = task->ssp_task.task_attr | | |
1220 | (task->ssp_task.task_prio << 3); | |
1221 | memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd, | |
1222 | task->ssp_task.cmd->cmd_len); | |
1223 | } else { | |
1224 | buf_cmd[10] = tmf->tmf; | |
1225 | switch (tmf->tmf) { | |
1226 | case TMF_ABORT_TASK: | |
1227 | case TMF_QUERY_TASK: | |
1228 | buf_cmd[12] = | |
1229 | (tmf->tag_of_task_to_be_managed >> 8) & 0xff; | |
1230 | buf_cmd[13] = | |
1231 | tmf->tag_of_task_to_be_managed & 0xff; | |
1232 | break; | |
1233 | default: | |
1234 | break; | |
1235 | } | |
1236 | } | |
1237 | ||
1238 | return 0; | |
1239 | } | |
1240 | ||
6f2ff1a1 JG |
1241 | static void sata_done_v2_hw(struct hisi_hba *hisi_hba, struct sas_task *task, |
1242 | struct hisi_sas_slot *slot) | |
1243 | { | |
1244 | struct task_status_struct *ts = &task->task_status; | |
1245 | struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf; | |
1246 | struct dev_to_host_fis *d2h = slot->status_buffer + | |
1247 | sizeof(struct hisi_sas_err_record); | |
1248 | ||
1249 | resp->frame_len = sizeof(struct dev_to_host_fis); | |
1250 | memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis)); | |
1251 | ||
1252 | ts->buf_valid_size = sizeof(*resp); | |
1253 | } | |
e8fed0e9 JG |
1254 | |
1255 | /* by default, task resp is complete */ | |
1256 | static void slot_err_v2_hw(struct hisi_hba *hisi_hba, | |
1257 | struct sas_task *task, | |
1258 | struct hisi_sas_slot *slot) | |
1259 | { | |
1260 | struct task_status_struct *ts = &task->task_status; | |
1261 | struct hisi_sas_err_record_v2 *err_record = slot->status_buffer; | |
1262 | u32 trans_tx_fail_type = cpu_to_le32(err_record->trans_tx_fail_type); | |
1263 | u32 trans_rx_fail_type = cpu_to_le32(err_record->trans_rx_fail_type); | |
1264 | u16 dma_tx_err_type = cpu_to_le16(err_record->dma_tx_err_type); | |
1265 | u16 sipc_rx_err_type = cpu_to_le16(err_record->sipc_rx_err_type); | |
1266 | u32 dma_rx_err_type = cpu_to_le32(err_record->dma_rx_err_type); | |
1267 | int error = -1; | |
1268 | ||
1269 | if (dma_rx_err_type) { | |
1270 | error = ffs(dma_rx_err_type) | |
1271 | - 1 + DMA_RX_ERR_BASE; | |
1272 | } else if (sipc_rx_err_type) { | |
1273 | error = ffs(sipc_rx_err_type) | |
1274 | - 1 + SIPC_RX_ERR_BASE; | |
1275 | } else if (dma_tx_err_type) { | |
1276 | error = ffs(dma_tx_err_type) | |
1277 | - 1 + DMA_TX_ERR_BASE; | |
1278 | } else if (trans_rx_fail_type) { | |
1279 | error = ffs(trans_rx_fail_type) | |
1280 | - 1 + TRANS_RX_FAIL_BASE; | |
1281 | } else if (trans_tx_fail_type) { | |
1282 | error = ffs(trans_tx_fail_type) | |
1283 | - 1 + TRANS_TX_FAIL_BASE; | |
1284 | } | |
1285 | ||
1286 | switch (task->task_proto) { | |
1287 | case SAS_PROTOCOL_SSP: | |
1288 | { | |
1289 | switch (error) { | |
1290 | case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: | |
1291 | { | |
1292 | ts->stat = SAS_OPEN_REJECT; | |
1293 | ts->open_rej_reason = SAS_OREJ_NO_DEST; | |
1294 | break; | |
1295 | } | |
1296 | case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: | |
1297 | { | |
1298 | ts->stat = SAS_OPEN_REJECT; | |
1299 | ts->open_rej_reason = SAS_OREJ_PATH_BLOCKED; | |
1300 | break; | |
1301 | } | |
1302 | case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: | |
1303 | { | |
1304 | ts->stat = SAS_OPEN_REJECT; | |
1305 | ts->open_rej_reason = SAS_OREJ_EPROTO; | |
1306 | break; | |
1307 | } | |
1308 | case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: | |
1309 | { | |
1310 | ts->stat = SAS_OPEN_REJECT; | |
1311 | ts->open_rej_reason = SAS_OREJ_CONN_RATE; | |
1312 | break; | |
1313 | } | |
1314 | case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: | |
1315 | { | |
1316 | ts->stat = SAS_OPEN_REJECT; | |
1317 | ts->open_rej_reason = SAS_OREJ_BAD_DEST; | |
1318 | break; | |
1319 | } | |
1320 | case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: | |
1321 | { | |
1322 | ts->stat = SAS_OPEN_REJECT; | |
1323 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1324 | break; | |
1325 | } | |
1326 | case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: | |
1327 | { | |
1328 | ts->stat = SAS_OPEN_REJECT; | |
1329 | ts->open_rej_reason = SAS_OREJ_WRONG_DEST; | |
1330 | break; | |
1331 | } | |
1332 | case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: | |
1333 | { | |
1334 | ts->stat = SAS_OPEN_REJECT; | |
1335 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1336 | break; | |
1337 | } | |
1338 | case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: | |
1339 | { | |
1340 | /* not sure */ | |
1341 | ts->stat = SAS_DEV_NO_RESPONSE; | |
1342 | break; | |
1343 | } | |
1344 | case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: | |
1345 | { | |
1346 | ts->stat = SAS_PHY_DOWN; | |
1347 | break; | |
1348 | } | |
1349 | case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: | |
1350 | { | |
1351 | ts->stat = SAS_OPEN_TO; | |
1352 | break; | |
1353 | } | |
1354 | case DMA_RX_DATA_LEN_OVERFLOW: | |
1355 | { | |
1356 | ts->stat = SAS_DATA_OVERRUN; | |
1357 | ts->residual = 0; | |
1358 | break; | |
1359 | } | |
1360 | case DMA_RX_DATA_LEN_UNDERFLOW: | |
1361 | case SIPC_RX_DATA_UNDERFLOW_ERR: | |
1362 | { | |
1363 | ts->residual = trans_tx_fail_type; | |
1364 | ts->stat = SAS_DATA_UNDERRUN; | |
1365 | break; | |
1366 | } | |
9c8ee657 JG |
1367 | case TRANS_TX_ERR_FRAME_TXED: |
1368 | { | |
1369 | /* This will request a retry */ | |
1370 | ts->stat = SAS_QUEUE_FULL; | |
1371 | slot->abort = 1; | |
1372 | break; | |
1373 | } | |
e8fed0e9 JG |
1374 | case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: |
1375 | case TRANS_TX_ERR_PHY_NOT_ENABLE: | |
1376 | case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: | |
1377 | case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: | |
1378 | case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: | |
1379 | case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: | |
1380 | case TRANS_TX_ERR_WITH_BREAK_REQUEST: | |
1381 | case TRANS_TX_ERR_WITH_BREAK_RECEVIED: | |
1382 | case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: | |
1383 | case TRANS_TX_ERR_WITH_CLOSE_NORMAL: | |
1384 | case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: | |
1385 | case TRANS_TX_ERR_WITH_CLOSE_COMINIT: | |
1386 | case TRANS_TX_ERR_WITH_NAK_RECEVIED: | |
1387 | case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: | |
1388 | case TRANS_TX_ERR_WITH_IPTT_CONFLICT: | |
1389 | case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: | |
1390 | case TRANS_RX_ERR_WITH_RXFRAME_CRC_ERR: | |
1391 | case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: | |
1392 | case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: | |
1393 | case TRANS_RX_ERR_WITH_BREAK_TIMEOUT: | |
1394 | case TRANS_RX_ERR_WITH_BREAK_REQUEST: | |
1395 | case TRANS_RX_ERR_WITH_BREAK_RECEVIED: | |
1396 | case TRANS_RX_ERR_WITH_CLOSE_NORMAL: | |
1397 | case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: | |
1398 | case TRANS_RX_ERR_WITH_CLOSE_COMINIT: | |
1399 | case TRANS_RX_ERR_WITH_DATA_LEN0: | |
1400 | case TRANS_RX_ERR_WITH_BAD_HASH: | |
1401 | case TRANS_RX_XRDY_WLEN_ZERO_ERR: | |
1402 | case TRANS_RX_SSP_FRM_LEN_ERR: | |
1403 | case TRANS_RX_ERR_WITH_BAD_FRM_TYPE: | |
1404 | case DMA_TX_UNEXP_XFER_ERR: | |
1405 | case DMA_TX_UNEXP_RETRANS_ERR: | |
1406 | case DMA_TX_XFER_LEN_OVERFLOW: | |
1407 | case DMA_TX_XFER_OFFSET_ERR: | |
1408 | case DMA_RX_DATA_OFFSET_ERR: | |
1409 | case DMA_RX_UNEXP_NORM_RESP_ERR: | |
1410 | case DMA_RX_UNEXP_RDFRAME_ERR: | |
1411 | case DMA_RX_UNKNOWN_FRM_ERR: | |
1412 | { | |
1413 | ts->stat = SAS_OPEN_REJECT; | |
1414 | ts->open_rej_reason = SAS_OREJ_UNKNOWN; | |
1415 | break; | |
1416 | } | |
1417 | default: | |
1418 | break; | |
1419 | } | |
1420 | } | |
1421 | break; | |
1422 | case SAS_PROTOCOL_SMP: | |
1423 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1424 | break; | |
1425 | ||
1426 | case SAS_PROTOCOL_SATA: | |
1427 | case SAS_PROTOCOL_STP: | |
1428 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
1429 | { | |
1430 | switch (error) { | |
1431 | case TRANS_TX_OPEN_CNX_ERR_LOW_PHY_POWER: | |
1432 | case TRANS_TX_OPEN_CNX_ERR_PATHWAY_BLOCKED: | |
1433 | case TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION: | |
1434 | { | |
1435 | ts->resp = SAS_TASK_UNDELIVERED; | |
1436 | ts->stat = SAS_DEV_NO_RESPONSE; | |
1437 | break; | |
1438 | } | |
1439 | case TRANS_TX_OPEN_CNX_ERR_PROTOCOL_NOT_SUPPORTED: | |
1440 | case TRANS_TX_OPEN_CNX_ERR_CONNECTION_RATE_NOT_SUPPORTED: | |
1441 | case TRANS_TX_OPEN_CNX_ERR_BAD_DESTINATION: | |
1442 | case TRANS_TX_OPEN_CNX_ERR_BREAK_RCVD: | |
1443 | case TRANS_TX_OPEN_CNX_ERR_WRONG_DESTINATION: | |
1444 | case TRANS_TX_OPEN_CNX_ERR_ZONE_VIOLATION: | |
1445 | case TRANS_TX_OPEN_CNX_ERR_STP_RESOURCES_BUSY: | |
1446 | { | |
1447 | ts->stat = SAS_OPEN_REJECT; | |
1448 | break; | |
1449 | } | |
1450 | case TRANS_TX_OPEN_CNX_ERR_OPEN_TIMEOUT: | |
1451 | { | |
1452 | ts->stat = SAS_OPEN_TO; | |
1453 | break; | |
1454 | } | |
1455 | case DMA_RX_DATA_LEN_OVERFLOW: | |
1456 | { | |
1457 | ts->stat = SAS_DATA_OVERRUN; | |
1458 | break; | |
1459 | } | |
1460 | case TRANS_TX_OPEN_FAIL_WITH_IT_NEXUS_LOSS: | |
1461 | case TRANS_TX_ERR_PHY_NOT_ENABLE: | |
1462 | case TRANS_TX_OPEN_CNX_ERR_BY_OTHER: | |
1463 | case TRANS_TX_OPEN_CNX_ERR_AIP_TIMEOUT: | |
1464 | case TRANS_TX_OPEN_RETRY_ERR_THRESHOLD_REACHED: | |
1465 | case TRANS_TX_ERR_WITH_BREAK_TIMEOUT: | |
1466 | case TRANS_TX_ERR_WITH_BREAK_REQUEST: | |
1467 | case TRANS_TX_ERR_WITH_BREAK_RECEVIED: | |
1468 | case TRANS_TX_ERR_WITH_CLOSE_TIMEOUT: | |
1469 | case TRANS_TX_ERR_WITH_CLOSE_NORMAL: | |
1470 | case TRANS_TX_ERR_WITH_CLOSE_DWS_TIMEOUT: | |
1471 | case TRANS_TX_ERR_WITH_CLOSE_COMINIT: | |
1472 | case TRANS_TX_ERR_WITH_NAK_RECEVIED: | |
1473 | case TRANS_TX_ERR_WITH_ACK_NAK_TIMEOUT: | |
1474 | case TRANS_TX_ERR_WITH_CREDIT_TIMEOUT: | |
1475 | case TRANS_TX_ERR_WITH_WAIT_RECV_TIMEOUT: | |
1476 | case TRANS_RX_ERR_WITH_RXFIS_8B10B_DISP_ERR: | |
1477 | case TRANS_RX_ERR_WITH_RXFRAME_HAVE_ERRPRM: | |
1478 | case TRANS_RX_ERR_WITH_RXFIS_DECODE_ERROR: | |
1479 | case TRANS_RX_ERR_WITH_RXFIS_CRC_ERR: | |
1480 | case TRANS_RX_ERR_WITH_RXFRAME_LENGTH_OVERRUN: | |
1481 | case TRANS_RX_ERR_WITH_RXFIS_RX_SYNCP: | |
1482 | case TRANS_RX_ERR_WITH_CLOSE_NORMAL: | |
1483 | case TRANS_RX_ERR_WITH_CLOSE_PHY_DISABLE: | |
1484 | case TRANS_RX_ERR_WITH_CLOSE_DWS_TIMEOUT: | |
1485 | case TRANS_RX_ERR_WITH_CLOSE_COMINIT: | |
1486 | case TRANS_RX_ERR_WITH_DATA_LEN0: | |
1487 | case TRANS_RX_ERR_WITH_BAD_HASH: | |
1488 | case TRANS_RX_XRDY_WLEN_ZERO_ERR: | |
1489 | case TRANS_RX_SSP_FRM_LEN_ERR: | |
1490 | case SIPC_RX_FIS_STATUS_ERR_BIT_VLD: | |
1491 | case SIPC_RX_PIO_WRSETUP_STATUS_DRQ_ERR: | |
1492 | case SIPC_RX_FIS_STATUS_BSY_BIT_ERR: | |
1493 | case SIPC_RX_WRSETUP_LEN_ODD_ERR: | |
1494 | case SIPC_RX_WRSETUP_LEN_ZERO_ERR: | |
1495 | case SIPC_RX_WRDATA_LEN_NOT_MATCH_ERR: | |
1496 | case SIPC_RX_SATA_UNEXP_FIS_ERR: | |
1497 | case DMA_RX_SATA_FRAME_TYPE_ERR: | |
1498 | case DMA_RX_UNEXP_RDFRAME_ERR: | |
1499 | case DMA_RX_PIO_DATA_LEN_ERR: | |
1500 | case DMA_RX_RDSETUP_STATUS_ERR: | |
1501 | case DMA_RX_RDSETUP_STATUS_DRQ_ERR: | |
1502 | case DMA_RX_RDSETUP_STATUS_BSY_ERR: | |
1503 | case DMA_RX_RDSETUP_LEN_ODD_ERR: | |
1504 | case DMA_RX_RDSETUP_LEN_ZERO_ERR: | |
1505 | case DMA_RX_RDSETUP_LEN_OVER_ERR: | |
1506 | case DMA_RX_RDSETUP_OFFSET_ERR: | |
1507 | case DMA_RX_RDSETUP_ACTIVE_ERR: | |
1508 | case DMA_RX_RDSETUP_ESTATUS_ERR: | |
1509 | case DMA_RX_UNKNOWN_FRM_ERR: | |
1510 | { | |
1511 | ts->stat = SAS_OPEN_REJECT; | |
1512 | break; | |
1513 | } | |
1514 | default: | |
1515 | { | |
1516 | ts->stat = SAS_PROTO_RESPONSE; | |
1517 | break; | |
1518 | } | |
1519 | } | |
1520 | sata_done_v2_hw(hisi_hba, task, slot); | |
1521 | } | |
1522 | break; | |
1523 | default: | |
1524 | break; | |
1525 | } | |
1526 | } | |
1527 | ||
31a9cfa6 JG |
1528 | static int |
1529 | slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot, | |
1530 | int abort) | |
1531 | { | |
1532 | struct sas_task *task = slot->task; | |
1533 | struct hisi_sas_device *sas_dev; | |
1534 | struct device *dev = &hisi_hba->pdev->dev; | |
1535 | struct task_status_struct *ts; | |
1536 | struct domain_device *device; | |
1537 | enum exec_status sts; | |
1538 | struct hisi_sas_complete_v2_hdr *complete_queue = | |
1539 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
1540 | struct hisi_sas_complete_v2_hdr *complete_hdr = | |
1541 | &complete_queue[slot->cmplt_queue_slot]; | |
1542 | ||
1543 | if (unlikely(!task || !task->lldd_task || !task->dev)) | |
1544 | return -EINVAL; | |
1545 | ||
1546 | ts = &task->task_status; | |
1547 | device = task->dev; | |
1548 | sas_dev = device->lldd_dev; | |
1549 | ||
1550 | task->task_state_flags &= | |
1551 | ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); | |
1552 | task->task_state_flags |= SAS_TASK_STATE_DONE; | |
1553 | ||
1554 | memset(ts, 0, sizeof(*ts)); | |
1555 | ts->resp = SAS_TASK_COMPLETE; | |
1556 | ||
1557 | if (unlikely(!sas_dev || abort)) { | |
1558 | if (!sas_dev) | |
1559 | dev_dbg(dev, "slot complete: port has not device\n"); | |
1560 | ts->stat = SAS_PHY_DOWN; | |
1561 | goto out; | |
1562 | } | |
1563 | ||
df032d0e JG |
1564 | /* Use SAS+TMF status codes */ |
1565 | switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) | |
1566 | >> CMPLT_HDR_ABORT_STAT_OFF) { | |
1567 | case STAT_IO_ABORTED: | |
1568 | /* this io has been aborted by abort command */ | |
1569 | ts->stat = SAS_ABORTED_TASK; | |
1570 | goto out; | |
1571 | case STAT_IO_COMPLETE: | |
1572 | /* internal abort command complete */ | |
1573 | ts->stat = TMF_RESP_FUNC_COMPLETE; | |
1574 | goto out; | |
1575 | case STAT_IO_NO_DEVICE: | |
1576 | ts->stat = TMF_RESP_FUNC_COMPLETE; | |
1577 | goto out; | |
1578 | case STAT_IO_NOT_VALID: | |
1579 | /* abort single io, controller don't find | |
1580 | * the io need to abort | |
1581 | */ | |
1582 | ts->stat = TMF_RESP_FUNC_FAILED; | |
1583 | goto out; | |
1584 | default: | |
1585 | break; | |
1586 | } | |
1587 | ||
31a9cfa6 JG |
1588 | if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) && |
1589 | (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) { | |
31a9cfa6 | 1590 | |
e8fed0e9 | 1591 | slot_err_v2_hw(hisi_hba, task, slot); |
9c8ee657 JG |
1592 | if (unlikely(slot->abort)) { |
1593 | queue_work(hisi_hba->wq, &slot->abort_slot); | |
1594 | /* immediately return and do not complete */ | |
1595 | return ts->stat; | |
1596 | } | |
31a9cfa6 JG |
1597 | goto out; |
1598 | } | |
1599 | ||
1600 | switch (task->task_proto) { | |
1601 | case SAS_PROTOCOL_SSP: | |
1602 | { | |
1603 | struct ssp_response_iu *iu = slot->status_buffer + | |
1604 | sizeof(struct hisi_sas_err_record); | |
1605 | ||
1606 | sas_ssp_task_response(dev, task, iu); | |
1607 | break; | |
1608 | } | |
1609 | case SAS_PROTOCOL_SMP: | |
1610 | { | |
1611 | struct scatterlist *sg_resp = &task->smp_task.smp_resp; | |
1612 | void *to; | |
1613 | ||
1614 | ts->stat = SAM_STAT_GOOD; | |
1615 | to = kmap_atomic(sg_page(sg_resp)); | |
1616 | ||
1617 | dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, | |
1618 | DMA_FROM_DEVICE); | |
1619 | dma_unmap_sg(dev, &task->smp_task.smp_req, 1, | |
1620 | DMA_TO_DEVICE); | |
1621 | memcpy(to + sg_resp->offset, | |
1622 | slot->status_buffer + | |
1623 | sizeof(struct hisi_sas_err_record), | |
1624 | sg_dma_len(sg_resp)); | |
1625 | kunmap_atomic(to); | |
1626 | break; | |
1627 | } | |
1628 | case SAS_PROTOCOL_SATA: | |
1629 | case SAS_PROTOCOL_STP: | |
1630 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
6f2ff1a1 JG |
1631 | { |
1632 | ts->stat = SAM_STAT_GOOD; | |
1633 | sata_done_v2_hw(hisi_hba, task, slot); | |
1634 | break; | |
1635 | } | |
31a9cfa6 JG |
1636 | default: |
1637 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1638 | break; | |
1639 | } | |
1640 | ||
1641 | if (!slot->port->port_attached) { | |
1642 | dev_err(dev, "slot complete: port %d has removed\n", | |
1643 | slot->port->sas_port.id); | |
1644 | ts->stat = SAS_PHY_DOWN; | |
1645 | } | |
1646 | ||
1647 | out: | |
1648 | if (sas_dev && sas_dev->running_req) | |
1649 | sas_dev->running_req--; | |
1650 | ||
1651 | hisi_sas_slot_task_free(hisi_hba, task, slot); | |
1652 | sts = ts->stat; | |
1653 | ||
1654 | if (task->task_done) | |
1655 | task->task_done(task); | |
1656 | ||
1657 | return sts; | |
1658 | } | |
1659 | ||
6f2ff1a1 JG |
1660 | static u8 get_ata_protocol(u8 cmd, int direction) |
1661 | { | |
1662 | switch (cmd) { | |
1663 | case ATA_CMD_FPDMA_WRITE: | |
1664 | case ATA_CMD_FPDMA_READ: | |
ef026b18 HR |
1665 | case ATA_CMD_FPDMA_RECV: |
1666 | case ATA_CMD_FPDMA_SEND: | |
661ce1f0 | 1667 | case ATA_CMD_NCQ_NON_DATA: |
6f2ff1a1 JG |
1668 | return SATA_PROTOCOL_FPDMA; |
1669 | ||
1670 | case ATA_CMD_ID_ATA: | |
1671 | case ATA_CMD_PMP_READ: | |
1672 | case ATA_CMD_READ_LOG_EXT: | |
1673 | case ATA_CMD_PIO_READ: | |
1674 | case ATA_CMD_PIO_READ_EXT: | |
1675 | case ATA_CMD_PMP_WRITE: | |
1676 | case ATA_CMD_WRITE_LOG_EXT: | |
1677 | case ATA_CMD_PIO_WRITE: | |
1678 | case ATA_CMD_PIO_WRITE_EXT: | |
1679 | return SATA_PROTOCOL_PIO; | |
1680 | ||
1681 | case ATA_CMD_READ: | |
1682 | case ATA_CMD_READ_EXT: | |
1683 | case ATA_CMD_READ_LOG_DMA_EXT: | |
1684 | case ATA_CMD_WRITE: | |
1685 | case ATA_CMD_WRITE_EXT: | |
1686 | case ATA_CMD_WRITE_QUEUED: | |
1687 | case ATA_CMD_WRITE_LOG_DMA_EXT: | |
1688 | return SATA_PROTOCOL_DMA; | |
1689 | ||
1690 | case ATA_CMD_DOWNLOAD_MICRO: | |
1691 | case ATA_CMD_DEV_RESET: | |
1692 | case ATA_CMD_CHK_POWER: | |
1693 | case ATA_CMD_FLUSH: | |
1694 | case ATA_CMD_FLUSH_EXT: | |
1695 | case ATA_CMD_VERIFY: | |
1696 | case ATA_CMD_VERIFY_EXT: | |
1697 | case ATA_CMD_SET_FEATURES: | |
1698 | case ATA_CMD_STANDBY: | |
1699 | case ATA_CMD_STANDBYNOW1: | |
1700 | return SATA_PROTOCOL_NONDATA; | |
1701 | default: | |
1702 | if (direction == DMA_NONE) | |
1703 | return SATA_PROTOCOL_NONDATA; | |
1704 | return SATA_PROTOCOL_PIO; | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | static int get_ncq_tag_v2_hw(struct sas_task *task, u32 *tag) | |
1709 | { | |
1710 | struct ata_queued_cmd *qc = task->uldd_task; | |
1711 | ||
1712 | if (qc) { | |
1713 | if (qc->tf.command == ATA_CMD_FPDMA_WRITE || | |
1714 | qc->tf.command == ATA_CMD_FPDMA_READ) { | |
1715 | *tag = qc->tag; | |
1716 | return 1; | |
1717 | } | |
1718 | } | |
1719 | return 0; | |
1720 | } | |
1721 | ||
1722 | static int prep_ata_v2_hw(struct hisi_hba *hisi_hba, | |
1723 | struct hisi_sas_slot *slot) | |
1724 | { | |
1725 | struct sas_task *task = slot->task; | |
1726 | struct domain_device *device = task->dev; | |
1727 | struct domain_device *parent_dev = device->parent; | |
1728 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1729 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1730 | struct hisi_sas_port *port = device->port->lldd_port; | |
1731 | u8 *buf_cmd; | |
1732 | int has_data = 0, rc = 0, hdr_tag = 0; | |
1733 | u32 dw1 = 0, dw2 = 0; | |
1734 | ||
1735 | /* create header */ | |
1736 | /* dw0 */ | |
1737 | hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); | |
1738 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
1739 | hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); | |
1740 | else | |
1741 | hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); | |
1742 | ||
1743 | /* dw1 */ | |
1744 | switch (task->data_dir) { | |
1745 | case DMA_TO_DEVICE: | |
1746 | has_data = 1; | |
1747 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1748 | break; | |
1749 | case DMA_FROM_DEVICE: | |
1750 | has_data = 1; | |
1751 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1752 | break; | |
1753 | default: | |
1754 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1755 | } | |
1756 | ||
1757 | if (0 == task->ata_task.fis.command) | |
1758 | dw1 |= 1 << CMD_HDR_RESET_OFF; | |
1759 | ||
1760 | dw1 |= (get_ata_protocol(task->ata_task.fis.command, task->data_dir)) | |
1761 | << CMD_HDR_FRAME_TYPE_OFF; | |
1762 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
1763 | hdr->dw1 = cpu_to_le32(dw1); | |
1764 | ||
1765 | /* dw2 */ | |
1766 | if (task->ata_task.use_ncq && get_ncq_tag_v2_hw(task, &hdr_tag)) { | |
1767 | task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); | |
1768 | dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; | |
1769 | } | |
1770 | ||
1771 | dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | | |
1772 | 2 << CMD_HDR_SG_MOD_OFF; | |
1773 | hdr->dw2 = cpu_to_le32(dw2); | |
1774 | ||
1775 | /* dw3 */ | |
1776 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1777 | ||
1778 | if (has_data) { | |
1779 | rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter, | |
1780 | slot->n_elem); | |
1781 | if (rc) | |
1782 | return rc; | |
1783 | } | |
1784 | ||
1785 | ||
1786 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
1787 | hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma); | |
1788 | hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma); | |
1789 | ||
1790 | buf_cmd = slot->command_table; | |
1791 | ||
1792 | if (likely(!task->ata_task.device_control_reg_update)) | |
1793 | task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ | |
1794 | /* fill in command FIS */ | |
1795 | memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); | |
1796 | ||
1797 | return 0; | |
1798 | } | |
1799 | ||
a3e665d9 JG |
1800 | static int prep_abort_v2_hw(struct hisi_hba *hisi_hba, |
1801 | struct hisi_sas_slot *slot, | |
1802 | int device_id, int abort_flag, int tag_to_abort) | |
1803 | { | |
1804 | struct sas_task *task = slot->task; | |
1805 | struct domain_device *dev = task->dev; | |
1806 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1807 | struct hisi_sas_port *port = slot->port; | |
1808 | ||
1809 | /* dw0 */ | |
1810 | hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ | |
1811 | (port->id << CMD_HDR_PORT_OFF) | | |
1812 | ((dev_is_sata(dev) ? 1:0) << | |
1813 | CMD_HDR_ABORT_DEVICE_TYPE_OFF) | | |
1814 | (abort_flag << CMD_HDR_ABORT_FLAG_OFF)); | |
1815 | ||
1816 | /* dw1 */ | |
1817 | hdr->dw1 = cpu_to_le32(device_id << CMD_HDR_DEV_ID_OFF); | |
1818 | ||
1819 | /* dw7 */ | |
1820 | hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); | |
1821 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1822 | ||
1823 | return 0; | |
1824 | } | |
1825 | ||
7911e66f JG |
1826 | static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba) |
1827 | { | |
1828 | int i, res = 0; | |
1829 | u32 context, port_id, link_rate, hard_phy_linkrate; | |
1830 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1831 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1832 | struct device *dev = &hisi_hba->pdev->dev; | |
1833 | u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; | |
1834 | struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd; | |
1835 | ||
1836 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); | |
1837 | ||
1838 | /* Check for SATA dev */ | |
1839 | context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); | |
1840 | if (context & (1 << phy_no)) | |
1841 | goto end; | |
1842 | ||
1843 | if (phy_no == 8) { | |
1844 | u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); | |
1845 | ||
1846 | port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> | |
1847 | PORT_STATE_PHY8_PORT_NUM_OFF; | |
1848 | link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> | |
1849 | PORT_STATE_PHY8_CONN_RATE_OFF; | |
1850 | } else { | |
1851 | port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
1852 | port_id = (port_id >> (4 * phy_no)) & 0xf; | |
1853 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); | |
1854 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; | |
1855 | } | |
1856 | ||
1857 | if (port_id == 0xf) { | |
1858 | dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); | |
1859 | res = IRQ_NONE; | |
1860 | goto end; | |
1861 | } | |
1862 | ||
1863 | for (i = 0; i < 6; i++) { | |
1864 | u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1865 | RX_IDAF_DWORD0 + (i * 4)); | |
1866 | frame_rcvd[i] = __swab32(idaf); | |
1867 | } | |
1868 | ||
7911e66f JG |
1869 | sas_phy->linkrate = link_rate; |
1870 | hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1871 | HARD_PHY_LINKRATE); | |
1872 | phy->maximum_linkrate = hard_phy_linkrate & 0xf; | |
1873 | phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; | |
1874 | ||
1875 | sas_phy->oob_mode = SAS_OOB_MODE; | |
1876 | memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE); | |
1877 | dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); | |
1878 | phy->port_id = port_id; | |
1879 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); | |
1880 | phy->phy_type |= PORT_TYPE_SAS; | |
1881 | phy->phy_attached = 1; | |
1882 | phy->identify.device_type = id->dev_type; | |
1883 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame); | |
1884 | if (phy->identify.device_type == SAS_END_DEVICE) | |
1885 | phy->identify.target_port_protocols = | |
1886 | SAS_PROTOCOL_SSP; | |
1887 | else if (phy->identify.device_type != SAS_PHY_UNUSED) | |
1888 | phy->identify.target_port_protocols = | |
1889 | SAS_PROTOCOL_SMP; | |
1890 | queue_work(hisi_hba->wq, &phy->phyup_ws); | |
1891 | ||
1892 | end: | |
1893 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, | |
1894 | CHL_INT0_SL_PHY_ENABLE_MSK); | |
1895 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); | |
1896 | ||
1897 | return res; | |
1898 | } | |
1899 | ||
5473c060 JG |
1900 | static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba) |
1901 | { | |
1902 | int res = 0; | |
1903 | u32 phy_cfg, phy_state; | |
1904 | ||
1905 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); | |
1906 | ||
1907 | phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
1908 | ||
1909 | phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1910 | ||
1911 | hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); | |
1912 | ||
1913 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); | |
1914 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); | |
1915 | ||
1916 | return res; | |
1917 | } | |
1918 | ||
7911e66f JG |
1919 | static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p) |
1920 | { | |
1921 | struct hisi_hba *hisi_hba = p; | |
1922 | u32 irq_msk; | |
1923 | int phy_no = 0; | |
1924 | irqreturn_t res = IRQ_HANDLED; | |
1925 | ||
1926 | irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) | |
1927 | >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff; | |
1928 | while (irq_msk) { | |
1929 | if (irq_msk & 1) { | |
1930 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1931 | CHL_INT0); | |
1932 | ||
1933 | if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) | |
1934 | /* phy up */ | |
1935 | if (phy_up_v2_hw(phy_no, hisi_hba)) { | |
1936 | res = IRQ_NONE; | |
1937 | goto end; | |
1938 | } | |
1939 | ||
5473c060 JG |
1940 | if (irq_value & CHL_INT0_NOT_RDY_MSK) |
1941 | /* phy down */ | |
1942 | if (phy_down_v2_hw(phy_no, hisi_hba)) { | |
1943 | res = IRQ_NONE; | |
1944 | goto end; | |
1945 | } | |
7911e66f JG |
1946 | } |
1947 | irq_msk >>= 1; | |
1948 | phy_no++; | |
1949 | } | |
1950 | ||
1951 | end: | |
1952 | return res; | |
1953 | } | |
1954 | ||
d3bf3d84 JG |
1955 | static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba) |
1956 | { | |
1957 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1958 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1959 | struct sas_ha_struct *sas_ha = &hisi_hba->sha; | |
d3bf3d84 JG |
1960 | |
1961 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); | |
d3bf3d84 | 1962 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
d3bf3d84 JG |
1963 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, |
1964 | CHL_INT0_SL_RX_BCST_ACK_MSK); | |
1965 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); | |
1966 | } | |
1967 | ||
1968 | static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p) | |
1969 | { | |
1970 | struct hisi_hba *hisi_hba = p; | |
1971 | struct device *dev = &hisi_hba->pdev->dev; | |
1972 | u32 ent_msk, ent_tmp, irq_msk; | |
1973 | int phy_no = 0; | |
1974 | ||
1975 | ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); | |
1976 | ent_tmp = ent_msk; | |
1977 | ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK; | |
1978 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk); | |
1979 | ||
1980 | irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >> | |
1981 | HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff; | |
1982 | ||
1983 | while (irq_msk) { | |
1984 | if (irq_msk & (1 << phy_no)) { | |
1985 | u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1986 | CHL_INT0); | |
1987 | u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1988 | CHL_INT1); | |
1989 | u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1990 | CHL_INT2); | |
1991 | ||
1992 | if (irq_value1) { | |
1993 | if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK | | |
1994 | CHL_INT1_DMAC_TX_ECC_ERR_MSK)) | |
1995 | panic("%s: DMAC RX/TX ecc bad error! (0x%x)", | |
1996 | dev_name(dev), irq_value1); | |
1997 | ||
1998 | hisi_sas_phy_write32(hisi_hba, phy_no, | |
1999 | CHL_INT1, irq_value1); | |
2000 | } | |
2001 | ||
2002 | if (irq_value2) | |
2003 | hisi_sas_phy_write32(hisi_hba, phy_no, | |
2004 | CHL_INT2, irq_value2); | |
2005 | ||
2006 | ||
2007 | if (irq_value0) { | |
2008 | if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK) | |
2009 | phy_bcast_v2_hw(phy_no, hisi_hba); | |
2010 | ||
2011 | hisi_sas_phy_write32(hisi_hba, phy_no, | |
2012 | CHL_INT0, irq_value0 | |
2013 | & (~CHL_INT0_HOTPLUG_TOUT_MSK) | |
2014 | & (~CHL_INT0_SL_PHY_ENABLE_MSK) | |
2015 | & (~CHL_INT0_NOT_RDY_MSK)); | |
2016 | } | |
2017 | } | |
2018 | irq_msk &= ~(1 << phy_no); | |
2019 | phy_no++; | |
2020 | } | |
2021 | ||
2022 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp); | |
2023 | ||
2024 | return IRQ_HANDLED; | |
2025 | } | |
2026 | ||
31a9cfa6 JG |
2027 | static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p) |
2028 | { | |
2029 | struct hisi_sas_cq *cq = p; | |
2030 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
2031 | struct hisi_sas_slot *slot; | |
2032 | struct hisi_sas_itct *itct; | |
2033 | struct hisi_sas_complete_v2_hdr *complete_queue; | |
e6c346f3 | 2034 | u32 irq_value, rd_point = cq->rd_point, wr_point, dev_id; |
31a9cfa6 JG |
2035 | int queue = cq->id; |
2036 | ||
2037 | complete_queue = hisi_hba->complete_hdr[queue]; | |
2038 | irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC); | |
2039 | ||
2040 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); | |
2041 | ||
31a9cfa6 JG |
2042 | wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + |
2043 | (0x14 * queue)); | |
2044 | ||
2045 | while (rd_point != wr_point) { | |
2046 | struct hisi_sas_complete_v2_hdr *complete_hdr; | |
2047 | int iptt; | |
2048 | ||
2049 | complete_hdr = &complete_queue[rd_point]; | |
2050 | ||
2051 | /* Check for NCQ completion */ | |
2052 | if (complete_hdr->act) { | |
2053 | u32 act_tmp = complete_hdr->act; | |
2054 | int ncq_tag_count = ffs(act_tmp); | |
2055 | ||
2056 | dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >> | |
2057 | CMPLT_HDR_DEV_ID_OFF; | |
2058 | itct = &hisi_hba->itct[dev_id]; | |
2059 | ||
2060 | /* The NCQ tags are held in the itct header */ | |
2061 | while (ncq_tag_count) { | |
2062 | __le64 *ncq_tag = &itct->qw4_15[0]; | |
2063 | ||
2064 | ncq_tag_count -= 1; | |
2065 | iptt = (ncq_tag[ncq_tag_count / 5] | |
2066 | >> (ncq_tag_count % 5) * 12) & 0xfff; | |
2067 | ||
2068 | slot = &hisi_hba->slot_info[iptt]; | |
2069 | slot->cmplt_queue_slot = rd_point; | |
2070 | slot->cmplt_queue = queue; | |
2071 | slot_complete_v2_hw(hisi_hba, slot, 0); | |
2072 | ||
2073 | act_tmp &= ~(1 << ncq_tag_count); | |
2074 | ncq_tag_count = ffs(act_tmp); | |
2075 | } | |
2076 | } else { | |
2077 | iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; | |
2078 | slot = &hisi_hba->slot_info[iptt]; | |
2079 | slot->cmplt_queue_slot = rd_point; | |
2080 | slot->cmplt_queue = queue; | |
2081 | slot_complete_v2_hw(hisi_hba, slot, 0); | |
2082 | } | |
2083 | ||
2084 | if (++rd_point >= HISI_SAS_QUEUE_SLOTS) | |
2085 | rd_point = 0; | |
2086 | } | |
2087 | ||
2088 | /* update rd_point */ | |
e6c346f3 | 2089 | cq->rd_point = rd_point; |
31a9cfa6 JG |
2090 | hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); |
2091 | return IRQ_HANDLED; | |
2092 | } | |
2093 | ||
d43f9cdb JG |
2094 | static irqreturn_t sata_int_v2_hw(int irq_no, void *p) |
2095 | { | |
2096 | struct hisi_sas_phy *phy = p; | |
2097 | struct hisi_hba *hisi_hba = phy->hisi_hba; | |
2098 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
2099 | struct device *dev = &hisi_hba->pdev->dev; | |
2100 | struct hisi_sas_initial_fis *initial_fis; | |
2101 | struct dev_to_host_fis *fis; | |
2102 | u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate; | |
2103 | irqreturn_t res = IRQ_HANDLED; | |
2104 | u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; | |
11826e5d | 2105 | int phy_no, offset; |
d43f9cdb JG |
2106 | |
2107 | phy_no = sas_phy->id; | |
2108 | initial_fis = &hisi_hba->initial_fis[phy_no]; | |
2109 | fis = &initial_fis->fis; | |
2110 | ||
11826e5d JG |
2111 | offset = 4 * (phy_no / 4); |
2112 | ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1 + offset); | |
2113 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, | |
2114 | ent_msk | 1 << ((phy_no % 4) * 8)); | |
d43f9cdb | 2115 | |
11826e5d JG |
2116 | ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1 + offset); |
2117 | ent_tmp = ent_int & (1 << (ENT_INT_SRC1_D2H_FIS_CH1_OFF * | |
2118 | (phy_no % 4))); | |
d43f9cdb JG |
2119 | ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4); |
2120 | if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) { | |
2121 | dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no); | |
d43f9cdb JG |
2122 | res = IRQ_NONE; |
2123 | goto end; | |
2124 | } | |
2125 | ||
2126 | if (unlikely(phy_no == 8)) { | |
2127 | u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE); | |
2128 | ||
2129 | port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >> | |
2130 | PORT_STATE_PHY8_PORT_NUM_OFF; | |
2131 | link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >> | |
2132 | PORT_STATE_PHY8_CONN_RATE_OFF; | |
2133 | } else { | |
2134 | port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
2135 | port_id = (port_id >> (4 * phy_no)) & 0xf; | |
2136 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); | |
2137 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; | |
2138 | } | |
2139 | ||
2140 | if (port_id == 0xf) { | |
2141 | dev_err(dev, "sata int: phy%d invalid portid\n", phy_no); | |
2142 | res = IRQ_NONE; | |
2143 | goto end; | |
2144 | } | |
2145 | ||
2146 | sas_phy->linkrate = link_rate; | |
2147 | hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no, | |
2148 | HARD_PHY_LINKRATE); | |
2149 | phy->maximum_linkrate = hard_phy_linkrate & 0xf; | |
2150 | phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf; | |
2151 | ||
2152 | sas_phy->oob_mode = SATA_OOB_MODE; | |
2153 | /* Make up some unique SAS address */ | |
2154 | attached_sas_addr[0] = 0x50; | |
2155 | attached_sas_addr[7] = phy_no; | |
2156 | memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE); | |
2157 | memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis)); | |
2158 | dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate); | |
2159 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); | |
2160 | phy->port_id = port_id; | |
2161 | phy->phy_type |= PORT_TYPE_SATA; | |
2162 | phy->phy_attached = 1; | |
2163 | phy->identify.device_type = SAS_SATA_DEV; | |
2164 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); | |
2165 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; | |
2166 | queue_work(hisi_hba->wq, &phy->phyup_ws); | |
2167 | ||
2168 | end: | |
11826e5d JG |
2169 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1 + offset, ent_tmp); |
2170 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1 + offset, ent_msk); | |
d43f9cdb JG |
2171 | |
2172 | return res; | |
2173 | } | |
2174 | ||
7911e66f JG |
2175 | static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = { |
2176 | int_phy_updown_v2_hw, | |
d3bf3d84 | 2177 | int_chnl_int_v2_hw, |
7911e66f JG |
2178 | }; |
2179 | ||
2180 | /** | |
2181 | * There is a limitation in the hip06 chipset that we need | |
2182 | * to map in all mbigen interrupts, even if they are not used. | |
2183 | */ | |
2184 | static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba) | |
2185 | { | |
2186 | struct platform_device *pdev = hisi_hba->pdev; | |
2187 | struct device *dev = &pdev->dev; | |
2188 | int i, irq, rc, irq_map[128]; | |
2189 | ||
2190 | ||
2191 | for (i = 0; i < 128; i++) | |
2192 | irq_map[i] = platform_get_irq(pdev, i); | |
2193 | ||
2194 | for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) { | |
2195 | int idx = i; | |
2196 | ||
2197 | irq = irq_map[idx + 1]; /* Phy up/down is irq1 */ | |
2198 | if (!irq) { | |
2199 | dev_err(dev, "irq init: fail map phy interrupt %d\n", | |
2200 | idx); | |
2201 | return -ENOENT; | |
2202 | } | |
2203 | ||
2204 | rc = devm_request_irq(dev, irq, phy_interrupts[i], 0, | |
2205 | DRV_NAME " phy", hisi_hba); | |
2206 | if (rc) { | |
2207 | dev_err(dev, "irq init: could not request " | |
2208 | "phy interrupt %d, rc=%d\n", | |
2209 | irq, rc); | |
2210 | return -ENOENT; | |
2211 | } | |
2212 | } | |
2213 | ||
d43f9cdb JG |
2214 | for (i = 0; i < hisi_hba->n_phy; i++) { |
2215 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; | |
2216 | int idx = i + 72; /* First SATA interrupt is irq72 */ | |
2217 | ||
2218 | irq = irq_map[idx]; | |
2219 | if (!irq) { | |
2220 | dev_err(dev, "irq init: fail map phy interrupt %d\n", | |
2221 | idx); | |
2222 | return -ENOENT; | |
2223 | } | |
2224 | ||
2225 | rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0, | |
2226 | DRV_NAME " sata", phy); | |
2227 | if (rc) { | |
2228 | dev_err(dev, "irq init: could not request " | |
2229 | "sata interrupt %d, rc=%d\n", | |
2230 | irq, rc); | |
2231 | return -ENOENT; | |
2232 | } | |
2233 | } | |
31a9cfa6 JG |
2234 | |
2235 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
2236 | int idx = i + 96; /* First cq interrupt is irq96 */ | |
2237 | ||
2238 | irq = irq_map[idx]; | |
2239 | if (!irq) { | |
2240 | dev_err(dev, | |
2241 | "irq init: could not map cq interrupt %d\n", | |
2242 | idx); | |
2243 | return -ENOENT; | |
2244 | } | |
2245 | rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0, | |
2246 | DRV_NAME " cq", &hisi_hba->cq[i]); | |
2247 | if (rc) { | |
2248 | dev_err(dev, | |
2249 | "irq init: could not request cq interrupt %d, rc=%d\n", | |
2250 | irq, rc); | |
2251 | return -ENOENT; | |
2252 | } | |
2253 | } | |
2254 | ||
7911e66f JG |
2255 | return 0; |
2256 | } | |
2257 | ||
94eac9e1 JG |
2258 | static int hisi_sas_v2_init(struct hisi_hba *hisi_hba) |
2259 | { | |
2260 | int rc; | |
2261 | ||
2262 | rc = hw_init_v2_hw(hisi_hba); | |
2263 | if (rc) | |
2264 | return rc; | |
2265 | ||
7911e66f JG |
2266 | rc = interrupt_init_v2_hw(hisi_hba); |
2267 | if (rc) | |
2268 | return rc; | |
2269 | ||
29a20428 JG |
2270 | phys_init_v2_hw(hisi_hba); |
2271 | ||
94eac9e1 JG |
2272 | return 0; |
2273 | } | |
2274 | ||
3417ba8a | 2275 | static const struct hisi_sas_hw hisi_sas_v2_hw = { |
94eac9e1 | 2276 | .hw_init = hisi_sas_v2_init, |
85b2c3c0 | 2277 | .setup_itct = setup_itct_v2_hw, |
330fa7f3 | 2278 | .slot_index_alloc = slot_index_alloc_quirk_v2_hw, |
b2bdaf2b | 2279 | .alloc_dev = alloc_dev_quirk_v2_hw, |
7911e66f | 2280 | .sl_notify = sl_notify_v2_hw, |
5473c060 | 2281 | .get_wideport_bitmap = get_wideport_bitmap_v2_hw, |
85b2c3c0 | 2282 | .free_device = free_device_v2_hw, |
c2d89392 | 2283 | .prep_smp = prep_smp_v2_hw, |
8c36e31d | 2284 | .prep_ssp = prep_ssp_v2_hw, |
6f2ff1a1 | 2285 | .prep_stp = prep_ata_v2_hw, |
a3e665d9 | 2286 | .prep_abort = prep_abort_v2_hw, |
8c36e31d JG |
2287 | .get_free_slot = get_free_slot_v2_hw, |
2288 | .start_delivery = start_delivery_v2_hw, | |
31a9cfa6 | 2289 | .slot_complete = slot_complete_v2_hw, |
63fb11b8 JG |
2290 | .phy_enable = enable_phy_v2_hw, |
2291 | .phy_disable = disable_phy_v2_hw, | |
2292 | .phy_hard_reset = phy_hard_reset_v2_hw, | |
94eac9e1 JG |
2293 | .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW, |
2294 | .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr), | |
3417ba8a JG |
2295 | }; |
2296 | ||
2297 | static int hisi_sas_v2_probe(struct platform_device *pdev) | |
2298 | { | |
2299 | return hisi_sas_probe(pdev, &hisi_sas_v2_hw); | |
2300 | } | |
2301 | ||
2302 | static int hisi_sas_v2_remove(struct platform_device *pdev) | |
2303 | { | |
2304 | return hisi_sas_remove(pdev); | |
2305 | } | |
2306 | ||
2307 | static const struct of_device_id sas_v2_of_match[] = { | |
2308 | { .compatible = "hisilicon,hip06-sas-v2",}, | |
2309 | {}, | |
2310 | }; | |
2311 | MODULE_DEVICE_TABLE(of, sas_v2_of_match); | |
2312 | ||
50408712 JG |
2313 | static const struct acpi_device_id sas_v2_acpi_match[] = { |
2314 | { "HISI0162", 0 }, | |
2315 | { } | |
2316 | }; | |
2317 | ||
2318 | MODULE_DEVICE_TABLE(acpi, sas_v2_acpi_match); | |
2319 | ||
3417ba8a JG |
2320 | static struct platform_driver hisi_sas_v2_driver = { |
2321 | .probe = hisi_sas_v2_probe, | |
2322 | .remove = hisi_sas_v2_remove, | |
2323 | .driver = { | |
2324 | .name = DRV_NAME, | |
2325 | .of_match_table = sas_v2_of_match, | |
50408712 | 2326 | .acpi_match_table = ACPI_PTR(sas_v2_acpi_match), |
3417ba8a JG |
2327 | }, |
2328 | }; | |
2329 | ||
2330 | module_platform_driver(hisi_sas_v2_driver); | |
2331 | ||
2332 | MODULE_LICENSE("GPL"); | |
2333 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); | |
2334 | MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver"); | |
2335 | MODULE_ALIAS("platform:" DRV_NAME); |