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hisi_sas: add v2 code for itct setup and free
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
CommitLineData
3417ba8a
JG		 1/*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v2_hw"
14
45c901b8
JG		 15/* global registers need init*/
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define IO_BROKEN_MSG_ADDR_LO 0x18
22#define IO_BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PORT_STATE_PHY8_PORT_NUM_OFF 16
28#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29#define PORT_STATE_PHY8_CONN_RATE_OFF 20
30#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31#define PHY_CONN_RATE 0x30
32#define HGC_TRANS_TASK_CNT_LIMIT 0x38
33#define AXI_AHB_CLK_CFG 0x3c
34#define ITCT_CLR 0x44
35#define ITCT_CLR_EN_OFF 16
36#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37#define ITCT_DEV_OFF 0
38#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39#define AXI_USER1 0x48
40#define AXI_USER2 0x4c
41#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47#define HGC_GET_ITV_TIME 0x90
48#define DEVICE_MSG_WORK_MODE 0x94
49#define OPENA_WT_CONTI_TIME 0x9c
50#define I_T_NEXUS_LOSS_TIME 0xa0
51#define MAX_CON_TIME_LIMIT_TIME 0xa4
52#define BUS_INACTIVE_LIMIT_TIME 0xa8
53#define REJECT_TO_OPEN_LIMIT_TIME 0xac
54#define CFG_AGING_TIME 0xbc
55#define HGC_DFX_CFG2 0xc0
56#define HGC_IOMB_PROC1_STATUS 0x104
57#define CFG_1US_TIMER_TRSH 0xcc
58#define HGC_INVLD_DQE_INFO 0x148
59#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62#define INT_COAL_EN 0x19c
63#define OQ_INT_COAL_TIME 0x1a0
64#define OQ_INT_COAL_CNT 0x1a4
65#define ENT_INT_COAL_TIME 0x1a8
66#define ENT_INT_COAL_CNT 0x1ac
67#define OQ_INT_SRC 0x1b0
68#define OQ_INT_SRC_MSK 0x1b4
69#define ENT_INT_SRC1 0x1b8
70#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74#define ENT_INT_SRC2 0x1bc
75#define ENT_INT_SRC3 0x1c0
76#define ENT_INT_SRC3_ITC_INT_OFF 15
77#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83#define SAS_ECC_INTR_MSK 0x1ec
84#define HGC_ERR_STAT_EN 0x238
85#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87#define DLVRY_Q_0_DEPTH 0x268
88#define DLVRY_Q_0_WR_PTR 0x26c
89#define DLVRY_Q_0_RD_PTR 0x270
90#define HYPER_STREAM_ID_EN_CFG 0xc80
91#define OQ0_INT_SRC_MSK 0xc90
92#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94#define COMPL_Q_0_DEPTH 0x4e8
95#define COMPL_Q_0_WR_PTR 0x4ec
96#define COMPL_Q_0_RD_PTR 0x4f0
97
98/* phy registers need init */
99#define PORT_BASE (0x2000)
100
101#define PHY_CFG (PORT_BASE + 0x0)
102#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103#define PHY_CFG_ENA_OFF 0
104#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105#define PHY_CFG_DC_OPT_OFF 2
106#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108#define PROG_PHY_LINK_RATE_MAX_OFF 0
109#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110#define PHY_CTRL (PORT_BASE + 0x14)
111#define PHY_CTRL_RESET_OFF 0
112#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114#define SL_CFG (PORT_BASE + 0x84)
115#define PHY_PCN (PORT_BASE + 0x44)
116#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136#define CHL_INT0 (PORT_BASE + 0x1b4)
137#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143#define CHL_INT0_NOT_RDY_OFF 4
144#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145#define CHL_INT0_PHY_RDY_OFF 5
146#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147#define CHL_INT1 (PORT_BASE + 0x1b8)
148#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152#define CHL_INT2 (PORT_BASE + 0x1bc)
153#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164#define DMA_TX_STATUS_BUSY_OFF 0
165#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167#define DMA_RX_STATUS_BUSY_OFF 0
168#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170#define AXI_CFG (0x5100)
171#define AM_CFG_MAX_TRANS (0x5010)
172#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174/* HW dma structures */
175/* Delivery queue header */
176/* dw0 */
177#define CMD_HDR_RESP_REPORT_OFF 5
178#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179#define CMD_HDR_TLR_CTRL_OFF 6
180#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181#define CMD_HDR_PORT_OFF 18
182#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183#define CMD_HDR_PRIORITY_OFF 27
184#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185#define CMD_HDR_CMD_OFF 29
186#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187/* dw1 */
188#define CMD_HDR_DIR_OFF 5
189#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190#define CMD_HDR_RESET_OFF 7
191#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192#define CMD_HDR_VDTL_OFF 10
193#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194#define CMD_HDR_FRAME_TYPE_OFF 11
195#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196#define CMD_HDR_DEV_ID_OFF 16
197#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198/* dw2 */
199#define CMD_HDR_CFL_OFF 0
200#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201#define CMD_HDR_NCQ_TAG_OFF 10
202#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203#define CMD_HDR_MRFL_OFF 15
204#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205#define CMD_HDR_SG_MOD_OFF 24
206#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207#define CMD_HDR_FIRST_BURST_OFF 26
208#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209/* dw3 */
210#define CMD_HDR_IPTT_OFF 0
211#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212/* dw6 */
213#define CMD_HDR_DIF_SGL_LEN_OFF 0
214#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215#define CMD_HDR_DATA_SGL_LEN_OFF 16
216#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218/* Completion header */
219/* dw0 */
220#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222#define CMPLT_HDR_ERX_OFF 12
223#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224/* dw1 */
225#define CMPLT_HDR_IPTT_OFF 0
226#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227#define CMPLT_HDR_DEV_ID_OFF 16
228#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230/* ITCT header */
231/* qw0 */
232#define ITCT_HDR_DEV_TYPE_OFF 0
233#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234#define ITCT_HDR_VALID_OFF 2
235#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236#define ITCT_HDR_MCR_OFF 5
237#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238#define ITCT_HDR_VLN_OFF 9
239#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240#define ITCT_HDR_PORT_ID_OFF 28
241#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242/* qw2 */
243#define ITCT_HDR_INLT_OFF 0
244#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245#define ITCT_HDR_BITLT_OFF 16
246#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247#define ITCT_HDR_MCTLT_OFF 32
248#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249#define ITCT_HDR_RTOLT_OFF 48
250#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1
JG		 252struct hisi_sas_complete_v2_hdr {
253 __le32 dw0;
254 __le32 dw1;
255 __le32 act;
256 __le32 dw3;
257};
258
7911e66f
JG		 259enum {
260 HISI_SAS_PHY_PHY_UPDOWN,
d3bf3d84 261 HISI_SAS_PHY_CHNL_INT,
7911e66f
JG		 262 HISI_SAS_PHY_INT_NR
263};
264
94eac9e1
JG		 265#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
266
8c36e31d
JG		 267#define DIR_NO_DATA 0
268#define DIR_TO_INI 1
269#define DIR_TO_DEVICE 2
270#define DIR_RESERVED 3
271
94eac9e1
JG		 272static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
273{
274 void __iomem *regs = hisi_hba->regs + off;
275
276 return readl(regs);
277}
278
8c36e31d
JG		 279static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
280{
281 void __iomem *regs = hisi_hba->regs + off;
282
283 return readl_relaxed(regs);
284}
285
94eac9e1
JG		 286static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
287{
288 void __iomem *regs = hisi_hba->regs + off;
289
290 writel(val, regs);
291}
292
293static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
294 u32 off, u32 val)
295{
296 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
297
298 writel(val, regs);
299}
300
301static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
302 int phy_no, u32 off)
303{
304 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
305
306 return readl(regs);
307}
308
29a20428
JG		 309static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
310{
311 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
312
313 cfg &= ~PHY_CFG_DC_OPT_MSK;
314 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
315 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
316}
317
806bb768
JG		 318static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
319{
320 struct sas_identify_frame identify_frame;
321 u32 *identify_buffer;
322
323 memset(&identify_frame, 0, sizeof(identify_frame));
324 identify_frame.dev_type = SAS_END_DEVICE;
325 identify_frame.frame_type = 0;
326 identify_frame._un1 = 1;
327 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
328 identify_frame.target_bits = SAS_PROTOCOL_NONE;
329 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
330 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
331 identify_frame.phy_id = phy_no;
332 identify_buffer = (u32 *)(&identify_frame);
333
334 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
335 __swab32(identify_buffer[0]));
336 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
337 identify_buffer[2]);
338 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
339 identify_buffer[1]);
340 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
341 identify_buffer[4]);
342 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
343 identify_buffer[3]);
344 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
345 __swab32(identify_buffer[5]));
346}
347
348static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
349{
350 int i;
351
352 for (i = 0; i < hisi_hba->n_phy; i++)
353 config_id_frame_v2_hw(hisi_hba, i);
354}
355
85b2c3c0
JG		 356static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
357 struct hisi_sas_device *sas_dev)
358{
359 struct domain_device *device = sas_dev->sas_device;
360 struct device *dev = &hisi_hba->pdev->dev;
361 u64 qw0, device_id = sas_dev->device_id;
362 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
363 struct domain_device *parent_dev = device->parent;
364 struct hisi_sas_port *port = device->port->lldd_port;
365
366 memset(itct, 0, sizeof(*itct));
367
368 /* qw0 */
369 qw0 = 0;
370 switch (sas_dev->dev_type) {
371 case SAS_END_DEVICE:
372 case SAS_EDGE_EXPANDER_DEVICE:
373 case SAS_FANOUT_EXPANDER_DEVICE:
374 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
375 break;
376 case SAS_SATA_DEV:
377 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
378 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
379 else
380 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
381 break;
382 default:
383 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
384 sas_dev->dev_type);
385 }
386
387 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
388 (device->max_linkrate << ITCT_HDR_MCR_OFF) |
389 (1 << ITCT_HDR_VLN_OFF) |
390 (port->id << ITCT_HDR_PORT_ID_OFF));
391 itct->qw0 = cpu_to_le64(qw0);
392
393 /* qw1 */
394 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
395 itct->sas_addr = __swab64(itct->sas_addr);
396
397 /* qw2 */
398 itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
399 (0xff00ULL << ITCT_HDR_BITLT_OFF) |
400 (0xff00ULL << ITCT_HDR_MCTLT_OFF) |
401 (0xff00ULL << ITCT_HDR_RTOLT_OFF));
402}
403
404static void free_device_v2_hw(struct hisi_hba *hisi_hba,
405 struct hisi_sas_device *sas_dev)
406{
407 u64 qw0, dev_id = sas_dev->device_id;
408 struct device *dev = &hisi_hba->pdev->dev;
409 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
410 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
411 int i;
412
413 /* clear the itct interrupt state */
414 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
415 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
416 ENT_INT_SRC3_ITC_INT_MSK);
417
418 /* clear the itct int*/
419 for (i = 0; i < 2; i++) {
420 /* clear the itct table*/
421 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
422 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
423 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
424
425 udelay(10);
426 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
427 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
428 dev_dbg(dev, "got clear ITCT done interrupt\n");
429
430 /* invalid the itct state*/
431 qw0 = cpu_to_le64(itct->qw0);
432 qw0 &= ~(1 << ITCT_HDR_VALID_OFF);
433 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
434 ENT_INT_SRC3_ITC_INT_MSK);
435 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
436 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
437
438 /* clear the itct */
439 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
440 dev_dbg(dev, "clear ITCT ok\n");
441 break;
442 }
443 }
444}
445
94eac9e1
JG		 446static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
447{
448 int i, reset_val;
449 u32 val;
450 unsigned long end_time;
451 struct device *dev = &hisi_hba->pdev->dev;
452
453 /* The mask needs to be set depending on the number of phys */
454 if (hisi_hba->n_phy == 9)
455 reset_val = 0x1fffff;
456 else
457 reset_val = 0x7ffff;
458
459 /* Disable all of the DQ */
460 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
461 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
462
463 /* Disable all of the PHYs */
464 for (i = 0; i < hisi_hba->n_phy; i++) {
465 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
466
467 phy_cfg &= ~PHY_CTRL_RESET_MSK;
468 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
469 }
470 udelay(50);
471
472 /* Ensure DMA tx & rx idle */
473 for (i = 0; i < hisi_hba->n_phy; i++) {
474 u32 dma_tx_status, dma_rx_status;
475
476 end_time = jiffies + msecs_to_jiffies(1000);
477
478 while (1) {
479 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
480 DMA_TX_STATUS);
481 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
482 DMA_RX_STATUS);
483
484 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
485 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
486 break;
487
488 msleep(20);
489 if (time_after(jiffies, end_time))
490 return -EIO;
491 }
492 }
493
494 /* Ensure axi bus idle */
495 end_time = jiffies + msecs_to_jiffies(1000);
496 while (1) {
497 u32 axi_status =
498 hisi_sas_read32(hisi_hba, AXI_CFG);
499
500 if (axi_status == 0)
501 break;
502
503 msleep(20);
504 if (time_after(jiffies, end_time))
505 return -EIO;
506 }
507
508 /* reset and disable clock*/
509 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
510 reset_val);
511 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
512 reset_val);
513 msleep(1);
514 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
515 if (reset_val != (val & reset_val)) {
516 dev_err(dev, "SAS reset fail.\n");
517 return -EIO;
518 }
519
520 /* De-reset and enable clock*/
521 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
522 reset_val);
523 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
524 reset_val);
525 msleep(1);
526 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
527 &val);
528 if (val & reset_val) {
529 dev_err(dev, "SAS de-reset fail.\n");
530 return -EIO;
531 }
532
533 return 0;
534}
535
536static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
537{
538 struct device *dev = &hisi_hba->pdev->dev;
539 struct device_node *np = dev->of_node;
540 int i;
541
542 /* Global registers init */
543
544 /* Deal with am-max-transmissions quirk */
545 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
546 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
547 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
548 0x2020);
549 } /* Else, use defaults -> do nothing */
550
551 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
552 (u32)((1ULL << hisi_hba->queue_count) - 1));
553 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
554 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
555 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
556 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
557 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
558 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
559 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
560 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
561 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
562 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
563 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
564 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
565 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
566 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
567 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
568 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
569 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
570 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
571 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
572 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
573 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
574 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
575 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
576 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
577 for (i = 0; i < hisi_hba->queue_count; i++)
578 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
579
580 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
581 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
582
583 for (i = 0; i < hisi_hba->n_phy; i++) {
584 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
585 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
586 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
587 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
588 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
589 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
590 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
591 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
592 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
593 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
594 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
595 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
596 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
597 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
598 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
599 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
600 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
601 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
602 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
603 }
604
605 for (i = 0; i < hisi_hba->queue_count; i++) {
606 /* Delivery queue */
607 hisi_sas_write32(hisi_hba,
608 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
609 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
610
611 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
612 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
613
614 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
615 HISI_SAS_QUEUE_SLOTS);
616
617 /* Completion queue */
618 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
619 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
620
621 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
622 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
623
624 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
625 HISI_SAS_QUEUE_SLOTS);
626 }
627
628 /* itct */
629 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
630 lower_32_bits(hisi_hba->itct_dma));
631
632 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
633 upper_32_bits(hisi_hba->itct_dma));
634
635 /* iost */
636 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
637 lower_32_bits(hisi_hba->iost_dma));
638
639 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
640 upper_32_bits(hisi_hba->iost_dma));
641
642 /* breakpoint */
643 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
644 lower_32_bits(hisi_hba->breakpoint_dma));
645
646 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
647 upper_32_bits(hisi_hba->breakpoint_dma));
648
649 /* SATA broken msg */
650 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
651 lower_32_bits(hisi_hba->sata_breakpoint_dma));
652
653 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
654 upper_32_bits(hisi_hba->sata_breakpoint_dma));
655
656 /* SATA initial fis */
657 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
658 lower_32_bits(hisi_hba->initial_fis_dma));
659
660 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
661 upper_32_bits(hisi_hba->initial_fis_dma));
662}
663
664static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
665{
666 struct device *dev = &hisi_hba->pdev->dev;
667 int rc;
668
669 rc = reset_hw_v2_hw(hisi_hba);
670 if (rc) {
671 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
672 return rc;
673 }
674
675 msleep(100);
676 init_reg_v2_hw(hisi_hba);
677
806bb768
JG		 678 init_id_frame_v2_hw(hisi_hba);
679
94eac9e1
JG		 680 return 0;
681}
682
29a20428
JG		 683static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
684{
685 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
686
687 cfg |= PHY_CFG_ENA_MSK;
688 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
689}
690
691static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
692{
693 config_id_frame_v2_hw(hisi_hba, phy_no);
694 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
695 enable_phy_v2_hw(hisi_hba, phy_no);
696}
697
698static void start_phys_v2_hw(unsigned long data)
699{
700 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
701 int i;
702
703 for (i = 0; i < hisi_hba->n_phy; i++)
704 start_phy_v2_hw(hisi_hba, i);
705}
706
707static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
708{
709 int i;
710 struct timer_list *timer = &hisi_hba->timer;
711
712 for (i = 0; i < hisi_hba->n_phy; i++) {
713 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
714 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
715 }
716
717 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
718 mod_timer(timer, jiffies + HZ);
719}
720
7911e66f
JG		 721static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
722{
723 u32 sl_control;
724
725 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
726 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
727 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
728 msleep(1);
729 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
730 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
731 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
732}
733
5473c060
JG		 734static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
735{
736 int i, bitmap = 0;
737 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
738 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
739
740 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
741 if (phy_state & 1 << i)
742 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
743 bitmap |= 1 << i;
744
745 if (hisi_hba->n_phy == 9) {
746 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
747
748 if (phy_state & 1 << 8)
749 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
750 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
751 bitmap |= 1 << 9;
752 }
753
754 return bitmap;
755}
756
8c36e31d
JG		 757/**
758 * This function allocates across all queues to load balance.
759 * Slots are allocated from queues in a round-robin fashion.
760 *
761 * The callpath to this function and upto writing the write
762 * queue pointer should be safe from interruption.
763 */
764static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
765{
766 struct device *dev = &hisi_hba->pdev->dev;
767 u32 r, w;
768 int queue = hisi_hba->queue;
769
770 while (1) {
771 w = hisi_sas_read32_relaxed(hisi_hba,
772 DLVRY_Q_0_WR_PTR + (queue * 0x14));
773 r = hisi_sas_read32_relaxed(hisi_hba,
774 DLVRY_Q_0_RD_PTR + (queue * 0x14));
775 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
776 queue = (queue + 1) % hisi_hba->queue_count;
777 if (queue == hisi_hba->queue) {
778 dev_warn(dev, "could not find free slot\n");
779 return -EAGAIN;
780 }
781 continue;
782 }
783 break;
784 }
785 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
786 *q = queue;
787 *s = w;
788 return 0;
789}
790
791static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
792{
793 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
794 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
795
796 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
797 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
798}
799
800static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
801 struct hisi_sas_slot *slot,
802 struct hisi_sas_cmd_hdr *hdr,
803 struct scatterlist *scatter,
804 int n_elem)
805{
806 struct device *dev = &hisi_hba->pdev->dev;
807 struct scatterlist *sg;
808 int i;
809
810 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
811 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
812 n_elem);
813 return -EINVAL;
814 }
815
816 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
817 &slot->sge_page_dma);
818 if (!slot->sge_page)
819 return -ENOMEM;
820
821 for_each_sg(scatter, sg, n_elem, i) {
822 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
823
824 entry->addr = cpu_to_le64(sg_dma_address(sg));
825 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
826 entry->data_len = cpu_to_le32(sg_dma_len(sg));
827 entry->data_off = 0;
828 }
829
830 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
831
832 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
833
834 return 0;
835}
836
c2d89392
JG		 837static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
838 struct hisi_sas_slot *slot)
839{
840 struct sas_task *task = slot->task;
841 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
842 struct domain_device *device = task->dev;
843 struct device *dev = &hisi_hba->pdev->dev;
844 struct hisi_sas_port *port = slot->port;
845 struct scatterlist *sg_req, *sg_resp;
846 struct hisi_sas_device *sas_dev = device->lldd_dev;
847 dma_addr_t req_dma_addr;
848 unsigned int req_len, resp_len;
849 int elem, rc;
850
851 /*
852 * DMA-map SMP request, response buffers
853 */
854 /* req */
855 sg_req = &task->smp_task.smp_req;
856 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
857 if (!elem)
858 return -ENOMEM;
859 req_len = sg_dma_len(sg_req);
860 req_dma_addr = sg_dma_address(sg_req);
861
862 /* resp */
863 sg_resp = &task->smp_task.smp_resp;
864 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
865 if (!elem) {
866 rc = -ENOMEM;
867 goto err_out_req;
868 }
869 resp_len = sg_dma_len(sg_resp);
870 if ((req_len & 0x3) || (resp_len & 0x3)) {
871 rc = -EINVAL;
872 goto err_out_resp;
873 }
874
875 /* create header */
876 /* dw0 */
877 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
878 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
879 (2 << CMD_HDR_CMD_OFF)); /* smp */
880
881 /* map itct entry */
882 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
883 (1 << CMD_HDR_FRAME_TYPE_OFF) |
884 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
885
886 /* dw2 */
887 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
888 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
889 CMD_HDR_MRFL_OFF));
890
891 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
892
893 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
894 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
895
896 return 0;
897
898err_out_resp:
899 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
900 DMA_FROM_DEVICE);
901err_out_req:
902 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
903 DMA_TO_DEVICE);
904 return rc;
905}
906
8c36e31d
JG		 907static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
908 struct hisi_sas_slot *slot, int is_tmf,
909 struct hisi_sas_tmf_task *tmf)
910{
911 struct sas_task *task = slot->task;
912 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
913 struct domain_device *device = task->dev;
914 struct hisi_sas_device *sas_dev = device->lldd_dev;
915 struct hisi_sas_port *port = slot->port;
916 struct sas_ssp_task *ssp_task = &task->ssp_task;
917 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
918 int has_data = 0, rc, priority = is_tmf;
919 u8 *buf_cmd;
920 u32 dw1 = 0, dw2 = 0;
921
922 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
923 (2 << CMD_HDR_TLR_CTRL_OFF) |
924 (port->id << CMD_HDR_PORT_OFF) |
925 (priority << CMD_HDR_PRIORITY_OFF) |
926 (1 << CMD_HDR_CMD_OFF)); /* ssp */
927
928 dw1 = 1 << CMD_HDR_VDTL_OFF;
929 if (is_tmf) {
930 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
931 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
932 } else {
933 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
934 switch (scsi_cmnd->sc_data_direction) {
935 case DMA_TO_DEVICE:
936 has_data = 1;
937 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
938 break;
939 case DMA_FROM_DEVICE:
940 has_data = 1;
941 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
942 break;
943 default:
944 dw1 &= ~CMD_HDR_DIR_MSK;
945 }
946 }
947
948 /* map itct entry */
949 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
950 hdr->dw1 = cpu_to_le32(dw1);
951
952 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
953 + 3) / 4) << CMD_HDR_CFL_OFF) |
954 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
955 (2 << CMD_HDR_SG_MOD_OFF);
956 hdr->dw2 = cpu_to_le32(dw2);
957
958 hdr->transfer_tags = cpu_to_le32(slot->idx);
959
960 if (has_data) {
961 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
962 slot->n_elem);
963 if (rc)
964 return rc;
965 }
966
967 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
968 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
969 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
970
971 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
972
973 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
974 if (!is_tmf) {
975 buf_cmd[9] = task->ssp_task.task_attr |
976 (task->ssp_task.task_prio << 3);
977 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
978 task->ssp_task.cmd->cmd_len);
979 } else {
980 buf_cmd[10] = tmf->tmf;
981 switch (tmf->tmf) {
982 case TMF_ABORT_TASK:
983 case TMF_QUERY_TASK:
984 buf_cmd[12] =
985 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
986 buf_cmd[13] =
987 tmf->tag_of_task_to_be_managed & 0xff;
988 break;
989 default:
990 break;
991 }
992 }
993
994 return 0;
995}
996
31a9cfa6
JG		 997static int
998slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
999 int abort)
1000{
1001 struct sas_task *task = slot->task;
1002 struct hisi_sas_device *sas_dev;
1003 struct device *dev = &hisi_hba->pdev->dev;
1004 struct task_status_struct *ts;
1005 struct domain_device *device;
1006 enum exec_status sts;
1007 struct hisi_sas_complete_v2_hdr *complete_queue =
1008 hisi_hba->complete_hdr[slot->cmplt_queue];
1009 struct hisi_sas_complete_v2_hdr *complete_hdr =
1010 &complete_queue[slot->cmplt_queue_slot];
1011
1012 if (unlikely(!task || !task->lldd_task || !task->dev))
1013 return -EINVAL;
1014
1015 ts = &task->task_status;
1016 device = task->dev;
1017 sas_dev = device->lldd_dev;
1018
1019 task->task_state_flags &=
1020 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1021 task->task_state_flags |= SAS_TASK_STATE_DONE;
1022
1023 memset(ts, 0, sizeof(*ts));
1024 ts->resp = SAS_TASK_COMPLETE;
1025
1026 if (unlikely(!sas_dev || abort)) {
1027 if (!sas_dev)
1028 dev_dbg(dev, "slot complete: port has not device\n");
1029 ts->stat = SAS_PHY_DOWN;
1030 goto out;
1031 }
1032
1033 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
1034 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
1035 dev_dbg(dev, "%s slot %d has error info 0x%x\n",
1036 __func__, slot->cmplt_queue_slot,
1037 complete_hdr->dw0 & CMPLT_HDR_ERX_MSK);
1038
1039 goto out;
1040 }
1041
1042 switch (task->task_proto) {
1043 case SAS_PROTOCOL_SSP:
1044 {
1045 struct ssp_response_iu *iu = slot->status_buffer +
1046 sizeof(struct hisi_sas_err_record);
1047
1048 sas_ssp_task_response(dev, task, iu);
1049 break;
1050 }
1051 case SAS_PROTOCOL_SMP:
1052 {
1053 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1054 void *to;
1055
1056 ts->stat = SAM_STAT_GOOD;
1057 to = kmap_atomic(sg_page(sg_resp));
1058
1059 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1060 DMA_FROM_DEVICE);
1061 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1062 DMA_TO_DEVICE);
1063 memcpy(to + sg_resp->offset,
1064 slot->status_buffer +
1065 sizeof(struct hisi_sas_err_record),
1066 sg_dma_len(sg_resp));
1067 kunmap_atomic(to);
1068 break;
1069 }
1070 case SAS_PROTOCOL_SATA:
1071 case SAS_PROTOCOL_STP:
1072 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1073 default:
1074 ts->stat = SAM_STAT_CHECK_CONDITION;
1075 break;
1076 }
1077
1078 if (!slot->port->port_attached) {
1079 dev_err(dev, "slot complete: port %d has removed\n",
1080 slot->port->sas_port.id);
1081 ts->stat = SAS_PHY_DOWN;
1082 }
1083
1084out:
1085 if (sas_dev && sas_dev->running_req)
1086 sas_dev->running_req--;
1087
1088 hisi_sas_slot_task_free(hisi_hba, task, slot);
1089 sts = ts->stat;
1090
1091 if (task->task_done)
1092 task->task_done(task);
1093
1094 return sts;
1095}
1096
7911e66f
JG		 1097static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1098{
1099 int i, res = 0;
1100 u32 context, port_id, link_rate, hard_phy_linkrate;
1101 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1102 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1103 struct device *dev = &hisi_hba->pdev->dev;
1104 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1105 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1106
1107 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1108
1109 /* Check for SATA dev */
1110 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1111 if (context & (1 << phy_no))
1112 goto end;
1113
1114 if (phy_no == 8) {
1115 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1116
1117 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1118 PORT_STATE_PHY8_PORT_NUM_OFF;
1119 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1120 PORT_STATE_PHY8_CONN_RATE_OFF;
1121 } else {
1122 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1123 port_id = (port_id >> (4 * phy_no)) & 0xf;
1124 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1125 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1126 }
1127
1128 if (port_id == 0xf) {
1129 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1130 res = IRQ_NONE;
1131 goto end;
1132 }
1133
1134 for (i = 0; i < 6; i++) {
1135 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1136 RX_IDAF_DWORD0 + (i * 4));
1137 frame_rcvd[i] = __swab32(idaf);
1138 }
1139
1140 /* Get the linkrates */
1141 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1142 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1143 sas_phy->linkrate = link_rate;
1144 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1145 HARD_PHY_LINKRATE);
1146 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1147 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1148
1149 sas_phy->oob_mode = SAS_OOB_MODE;
1150 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1151 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1152 phy->port_id = port_id;
1153 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1154 phy->phy_type |= PORT_TYPE_SAS;
1155 phy->phy_attached = 1;
1156 phy->identify.device_type = id->dev_type;
1157 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1158 if (phy->identify.device_type == SAS_END_DEVICE)
1159 phy->identify.target_port_protocols =
1160 SAS_PROTOCOL_SSP;
1161 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1162 phy->identify.target_port_protocols =
1163 SAS_PROTOCOL_SMP;
1164 queue_work(hisi_hba->wq, &phy->phyup_ws);
1165
1166end:
1167 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1168 CHL_INT0_SL_PHY_ENABLE_MSK);
1169 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1170
1171 return res;
1172}
1173
5473c060
JG		 1174static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1175{
1176 int res = 0;
1177 u32 phy_cfg, phy_state;
1178
1179 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1180
1181 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1182
1183 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1184
1185 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1186
1187 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1188 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1189
1190 return res;
1191}
1192
7911e66f
JG		 1193static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1194{
1195 struct hisi_hba *hisi_hba = p;
1196 u32 irq_msk;
1197 int phy_no = 0;
1198 irqreturn_t res = IRQ_HANDLED;
1199
1200 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1201 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1202 while (irq_msk) {
1203 if (irq_msk & 1) {
1204 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1205 CHL_INT0);
1206
1207 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1208 /* phy up */
1209 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1210 res = IRQ_NONE;
1211 goto end;
1212 }
1213
5473c060
JG		 1214 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1215 /* phy down */
1216 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1217 res = IRQ_NONE;
1218 goto end;
1219 }
7911e66f
JG		 1220 }
1221 irq_msk >>= 1;
1222 phy_no++;
1223 }
1224
1225end:
1226 return res;
1227}
1228
d3bf3d84
JG		 1229static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1230{
1231 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1232 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1233 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1234 unsigned long flags;
1235
1236 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1237
1238 spin_lock_irqsave(&hisi_hba->lock, flags);
1239 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1240 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1241
1242 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1243 CHL_INT0_SL_RX_BCST_ACK_MSK);
1244 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1245}
1246
1247static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1248{
1249 struct hisi_hba *hisi_hba = p;
1250 struct device *dev = &hisi_hba->pdev->dev;
1251 u32 ent_msk, ent_tmp, irq_msk;
1252 int phy_no = 0;
1253
1254 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1255 ent_tmp = ent_msk;
1256 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1257 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1258
1259 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1260 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1261
1262 while (irq_msk) {
1263 if (irq_msk & (1 << phy_no)) {
1264 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1265 CHL_INT0);
1266 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1267 CHL_INT1);
1268 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1269 CHL_INT2);
1270
1271 if (irq_value1) {
1272 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1273 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1274 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1275 dev_name(dev), irq_value1);
1276
1277 hisi_sas_phy_write32(hisi_hba, phy_no,
1278 CHL_INT1, irq_value1);
1279 }
1280
1281 if (irq_value2)
1282 hisi_sas_phy_write32(hisi_hba, phy_no,
1283 CHL_INT2, irq_value2);
1284
1285
1286 if (irq_value0) {
1287 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1288 phy_bcast_v2_hw(phy_no, hisi_hba);
1289
1290 hisi_sas_phy_write32(hisi_hba, phy_no,
1291 CHL_INT0, irq_value0
1292 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1293 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1294 & (~CHL_INT0_NOT_RDY_MSK));
1295 }
1296 }
1297 irq_msk &= ~(1 << phy_no);
1298 phy_no++;
1299 }
1300
1301 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1302
1303 return IRQ_HANDLED;
1304}
1305
31a9cfa6
JG		 1306static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1307{
1308 struct hisi_sas_cq *cq = p;
1309 struct hisi_hba *hisi_hba = cq->hisi_hba;
1310 struct hisi_sas_slot *slot;
1311 struct hisi_sas_itct *itct;
1312 struct hisi_sas_complete_v2_hdr *complete_queue;
1313 u32 irq_value, rd_point, wr_point, dev_id;
1314 int queue = cq->id;
1315
1316 complete_queue = hisi_hba->complete_hdr[queue];
1317 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1318
1319 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1320
1321 rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1322 (0x14 * queue));
1323 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1324 (0x14 * queue));
1325
1326 while (rd_point != wr_point) {
1327 struct hisi_sas_complete_v2_hdr *complete_hdr;
1328 int iptt;
1329
1330 complete_hdr = &complete_queue[rd_point];
1331
1332 /* Check for NCQ completion */
1333 if (complete_hdr->act) {
1334 u32 act_tmp = complete_hdr->act;
1335 int ncq_tag_count = ffs(act_tmp);
1336
1337 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1338 CMPLT_HDR_DEV_ID_OFF;
1339 itct = &hisi_hba->itct[dev_id];
1340
1341 /* The NCQ tags are held in the itct header */
1342 while (ncq_tag_count) {
1343 __le64 *ncq_tag = &itct->qw4_15[0];
1344
1345 ncq_tag_count -= 1;
1346 iptt = (ncq_tag[ncq_tag_count / 5]
1347 >> (ncq_tag_count % 5) * 12) & 0xfff;
1348
1349 slot = &hisi_hba->slot_info[iptt];
1350 slot->cmplt_queue_slot = rd_point;
1351 slot->cmplt_queue = queue;
1352 slot_complete_v2_hw(hisi_hba, slot, 0);
1353
1354 act_tmp &= ~(1 << ncq_tag_count);
1355 ncq_tag_count = ffs(act_tmp);
1356 }
1357 } else {
1358 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1359 slot = &hisi_hba->slot_info[iptt];
1360 slot->cmplt_queue_slot = rd_point;
1361 slot->cmplt_queue = queue;
1362 slot_complete_v2_hw(hisi_hba, slot, 0);
1363 }
1364
1365 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1366 rd_point = 0;
1367 }
1368
1369 /* update rd_point */
1370 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1371 return IRQ_HANDLED;
1372}
1373
d43f9cdb
JG		 1374static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
1375{
1376 struct hisi_sas_phy *phy = p;
1377 struct hisi_hba *hisi_hba = phy->hisi_hba;
1378 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1379 struct device *dev = &hisi_hba->pdev->dev;
1380 struct hisi_sas_initial_fis *initial_fis;
1381 struct dev_to_host_fis *fis;
1382 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
1383 irqreturn_t res = IRQ_HANDLED;
1384 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1385 int phy_no;
1386
1387 phy_no = sas_phy->id;
1388 initial_fis = &hisi_hba->initial_fis[phy_no];
1389 fis = &initial_fis->fis;
1390
1391 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1);
1392 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no);
1393
1394 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1);
1395 ent_tmp = ent_int;
1396 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
1397 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
1398 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
1399 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1400 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1401 res = IRQ_NONE;
1402 goto end;
1403 }
1404
1405 if (unlikely(phy_no == 8)) {
1406 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1407
1408 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1409 PORT_STATE_PHY8_PORT_NUM_OFF;
1410 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1411 PORT_STATE_PHY8_CONN_RATE_OFF;
1412 } else {
1413 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1414 port_id = (port_id >> (4 * phy_no)) & 0xf;
1415 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1416 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1417 }
1418
1419 if (port_id == 0xf) {
1420 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
1421 res = IRQ_NONE;
1422 goto end;
1423 }
1424
1425 sas_phy->linkrate = link_rate;
1426 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1427 HARD_PHY_LINKRATE);
1428 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1429 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1430
1431 sas_phy->oob_mode = SATA_OOB_MODE;
1432 /* Make up some unique SAS address */
1433 attached_sas_addr[0] = 0x50;
1434 attached_sas_addr[7] = phy_no;
1435 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
1436 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
1437 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1438 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1439 phy->port_id = port_id;
1440 phy->phy_type |= PORT_TYPE_SATA;
1441 phy->phy_attached = 1;
1442 phy->identify.device_type = SAS_SATA_DEV;
1443 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1444 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1445 queue_work(hisi_hba->wq, &phy->phyup_ws);
1446
1447end:
1448 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1449 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1450
1451 return res;
1452}
1453
7911e66f
JG		 1454static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1455 int_phy_updown_v2_hw,
d3bf3d84 1456 int_chnl_int_v2_hw,
7911e66f
JG		 1457};
1458
1459/**
1460 * There is a limitation in the hip06 chipset that we need
1461 * to map in all mbigen interrupts, even if they are not used.
1462 */
1463static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
1464{
1465 struct platform_device *pdev = hisi_hba->pdev;
1466 struct device *dev = &pdev->dev;
1467 int i, irq, rc, irq_map[128];
1468
1469
1470 for (i = 0; i < 128; i++)
1471 irq_map[i] = platform_get_irq(pdev, i);
1472
1473 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
1474 int idx = i;
1475
1476 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
1477 if (!irq) {
1478 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1479 idx);
1480 return -ENOENT;
1481 }
1482
1483 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
1484 DRV_NAME " phy", hisi_hba);
1485 if (rc) {
1486 dev_err(dev, "irq init: could not request "
1487 "phy interrupt %d, rc=%d\n",
1488 irq, rc);
1489 return -ENOENT;
1490 }
1491 }
1492
d43f9cdb
JG		 1493 for (i = 0; i < hisi_hba->n_phy; i++) {
1494 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1495 int idx = i + 72; /* First SATA interrupt is irq72 */
1496
1497 irq = irq_map[idx];
1498 if (!irq) {
1499 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1500 idx);
1501 return -ENOENT;
1502 }
1503
1504 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
1505 DRV_NAME " sata", phy);
1506 if (rc) {
1507 dev_err(dev, "irq init: could not request "
1508 "sata interrupt %d, rc=%d\n",
1509 irq, rc);
1510 return -ENOENT;
1511 }
1512 }
31a9cfa6
JG		 1513
1514 for (i = 0; i < hisi_hba->queue_count; i++) {
1515 int idx = i + 96; /* First cq interrupt is irq96 */
1516
1517 irq = irq_map[idx];
1518 if (!irq) {
1519 dev_err(dev,
1520 "irq init: could not map cq interrupt %d\n",
1521 idx);
1522 return -ENOENT;
1523 }
1524 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
1525 DRV_NAME " cq", &hisi_hba->cq[i]);
1526 if (rc) {
1527 dev_err(dev,
1528 "irq init: could not request cq interrupt %d, rc=%d\n",
1529 irq, rc);
1530 return -ENOENT;
1531 }
1532 }
1533
7911e66f
JG		 1534 return 0;
1535}
1536
94eac9e1
JG		 1537static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
1538{
1539 int rc;
1540
1541 rc = hw_init_v2_hw(hisi_hba);
1542 if (rc)
1543 return rc;
1544
7911e66f
JG		 1545 rc = interrupt_init_v2_hw(hisi_hba);
1546 if (rc)
1547 return rc;
1548
29a20428
JG		 1549 phys_init_v2_hw(hisi_hba);
1550
94eac9e1
JG		 1551 return 0;
1552}
1553
3417ba8a 1554static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 1555 .hw_init = hisi_sas_v2_init,
85b2c3c0 1556 .setup_itct = setup_itct_v2_hw,
7911e66f 1557 .sl_notify = sl_notify_v2_hw,
5473c060 1558 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
85b2c3c0 1559 .free_device = free_device_v2_hw,
c2d89392 1560 .prep_smp = prep_smp_v2_hw,
8c36e31d
JG		 1561 .prep_ssp = prep_ssp_v2_hw,
1562 .get_free_slot = get_free_slot_v2_hw,
1563 .start_delivery = start_delivery_v2_hw,
31a9cfa6 1564 .slot_complete = slot_complete_v2_hw,
94eac9e1
JG		 1565 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
1566 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a
JG		 1567};
1568
1569static int hisi_sas_v2_probe(struct platform_device *pdev)
1570{
1571 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
1572}
1573
1574static int hisi_sas_v2_remove(struct platform_device *pdev)
1575{
1576 return hisi_sas_remove(pdev);
1577}
1578
1579static const struct of_device_id sas_v2_of_match[] = {
1580 { .compatible = "hisilicon,hip06-sas-v2",},
1581 {},
1582};
1583MODULE_DEVICE_TABLE(of, sas_v2_of_match);
1584
1585static struct platform_driver hisi_sas_v2_driver = {
1586 .probe = hisi_sas_v2_probe,
1587 .remove = hisi_sas_v2_remove,
1588 .driver = {
1589 .name = DRV_NAME,
1590 .of_match_table = sas_v2_of_match,
1591 },
1592};
1593
1594module_platform_driver(hisi_sas_v2_driver);
1595
1596MODULE_LICENSE("GPL");
1597MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1598MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
1599MODULE_ALIAS("platform:" DRV_NAME);
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