[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c

/*
 * Copyright (c) 2016 Linaro Ltd.
 * Copyright (c) 2016 Hisilicon Limited.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 */

#include "hisi_sas.h"
#define DRV_NAME "hisi_sas_v2_hw"

/* global registers need init*/
#define DLVRY_QUEUE_ENABLE		0x0
#define IOST_BASE_ADDR_LO		0x8
#define IOST_BASE_ADDR_HI		0xc
#define ITCT_BASE_ADDR_LO		0x10
#define ITCT_BASE_ADDR_HI		0x14
#define IO_BROKEN_MSG_ADDR_LO		0x18
#define IO_BROKEN_MSG_ADDR_HI		0x1c
#define PHY_CONTEXT			0x20
#define PHY_STATE			0x24
#define PHY_PORT_NUM_MA			0x28
#define PORT_STATE			0x2c
#define PORT_STATE_PHY8_PORT_NUM_OFF	16
#define PORT_STATE_PHY8_PORT_NUM_MSK	(0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
#define PORT_STATE_PHY8_CONN_RATE_OFF	20
#define PORT_STATE_PHY8_CONN_RATE_MSK	(0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
#define PHY_CONN_RATE			0x30
#define HGC_TRANS_TASK_CNT_LIMIT	0x38
#define AXI_AHB_CLK_CFG			0x3c
#define ITCT_CLR			0x44
#define ITCT_CLR_EN_OFF			16
#define ITCT_CLR_EN_MSK			(0x1 << ITCT_CLR_EN_OFF)
#define ITCT_DEV_OFF			0
#define ITCT_DEV_MSK			(0x7ff << ITCT_DEV_OFF)
#define AXI_USER1			0x48
#define AXI_USER2			0x4c
#define IO_SATA_BROKEN_MSG_ADDR_LO	0x58
#define IO_SATA_BROKEN_MSG_ADDR_HI	0x5c
#define SATA_INITI_D2H_STORE_ADDR_LO	0x60
#define SATA_INITI_D2H_STORE_ADDR_HI	0x64
#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL	0x84
#define HGC_SAS_TXFAIL_RETRY_CTRL	0x88
#define HGC_GET_ITV_TIME		0x90
#define DEVICE_MSG_WORK_MODE		0x94
#define OPENA_WT_CONTI_TIME		0x9c
#define I_T_NEXUS_LOSS_TIME		0xa0
#define MAX_CON_TIME_LIMIT_TIME		0xa4
#define BUS_INACTIVE_LIMIT_TIME		0xa8
#define REJECT_TO_OPEN_LIMIT_TIME	0xac
#define CFG_AGING_TIME			0xbc
#define HGC_DFX_CFG2			0xc0
#define HGC_IOMB_PROC1_STATUS	0x104
#define CFG_1US_TIMER_TRSH		0xcc
#define HGC_INVLD_DQE_INFO		0x148
#define HGC_INVLD_DQE_INFO_FB_CH0_OFF	9
#define HGC_INVLD_DQE_INFO_FB_CH0_MSK	(0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
#define HGC_INVLD_DQE_INFO_FB_CH3_OFF	18
#define INT_COAL_EN			0x19c
#define OQ_INT_COAL_TIME		0x1a0
#define OQ_INT_COAL_CNT			0x1a4
#define ENT_INT_COAL_TIME		0x1a8
#define ENT_INT_COAL_CNT		0x1ac
#define OQ_INT_SRC			0x1b0
#define OQ_INT_SRC_MSK			0x1b4
#define ENT_INT_SRC1			0x1b8
#define ENT_INT_SRC1_D2H_FIS_CH0_OFF	0
#define ENT_INT_SRC1_D2H_FIS_CH0_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
#define ENT_INT_SRC1_D2H_FIS_CH1_OFF	8
#define ENT_INT_SRC1_D2H_FIS_CH1_MSK	(0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
#define ENT_INT_SRC2			0x1bc
#define ENT_INT_SRC3			0x1c0
#define ENT_INT_SRC3_ITC_INT_OFF	15
#define ENT_INT_SRC3_ITC_INT_MSK	(0x1 << ENT_INT_SRC3_ITC_INT_OFF)
#define ENT_INT_SRC_MSK1		0x1c4
#define ENT_INT_SRC_MSK2		0x1c8
#define ENT_INT_SRC_MSK3		0x1cc
#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF	31
#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK	(0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
#define SAS_ECC_INTR_MSK		0x1ec
#define HGC_ERR_STAT_EN			0x238
#define DLVRY_Q_0_BASE_ADDR_LO		0x260
#define DLVRY_Q_0_BASE_ADDR_HI		0x264
#define DLVRY_Q_0_DEPTH			0x268
#define DLVRY_Q_0_WR_PTR		0x26c
#define DLVRY_Q_0_RD_PTR		0x270
#define HYPER_STREAM_ID_EN_CFG		0xc80
#define OQ0_INT_SRC_MSK			0xc90
#define COMPL_Q_0_BASE_ADDR_LO		0x4e0
#define COMPL_Q_0_BASE_ADDR_HI		0x4e4
#define COMPL_Q_0_DEPTH			0x4e8
#define COMPL_Q_0_WR_PTR		0x4ec
#define COMPL_Q_0_RD_PTR		0x4f0

/* phy registers need init */
#define PORT_BASE			(0x2000)

#define PHY_CFG				(PORT_BASE + 0x0)
#define HARD_PHY_LINKRATE		(PORT_BASE + 0x4)
#define PHY_CFG_ENA_OFF			0
#define PHY_CFG_ENA_MSK			(0x1 << PHY_CFG_ENA_OFF)
#define PHY_CFG_DC_OPT_OFF		2
#define PHY_CFG_DC_OPT_MSK		(0x1 << PHY_CFG_DC_OPT_OFF)
#define PROG_PHY_LINK_RATE		(PORT_BASE + 0x8)
#define PROG_PHY_LINK_RATE_MAX_OFF	0
#define PROG_PHY_LINK_RATE_MAX_MSK	(0xff << PROG_PHY_LINK_RATE_MAX_OFF)
#define PHY_CTRL			(PORT_BASE + 0x14)
#define PHY_CTRL_RESET_OFF		0
#define PHY_CTRL_RESET_MSK		(0x1 << PHY_CTRL_RESET_OFF)
#define SAS_PHY_CTRL			(PORT_BASE + 0x20)
#define SL_CFG				(PORT_BASE + 0x84)
#define PHY_PCN				(PORT_BASE + 0x44)
#define SL_TOUT_CFG			(PORT_BASE + 0x8c)
#define SL_CONTROL			(PORT_BASE + 0x94)
#define SL_CONTROL_NOTIFY_EN_OFF	0
#define SL_CONTROL_NOTIFY_EN_MSK	(0x1 << SL_CONTROL_NOTIFY_EN_OFF)
#define TX_ID_DWORD0			(PORT_BASE + 0x9c)
#define TX_ID_DWORD1			(PORT_BASE + 0xa0)
#define TX_ID_DWORD2			(PORT_BASE + 0xa4)
#define TX_ID_DWORD3			(PORT_BASE + 0xa8)
#define TX_ID_DWORD4			(PORT_BASE + 0xaC)
#define TX_ID_DWORD5			(PORT_BASE + 0xb0)
#define TX_ID_DWORD6			(PORT_BASE + 0xb4)
#define RX_IDAF_DWORD0			(PORT_BASE + 0xc4)
#define RX_IDAF_DWORD1			(PORT_BASE + 0xc8)
#define RX_IDAF_DWORD2			(PORT_BASE + 0xcc)
#define RX_IDAF_DWORD3			(PORT_BASE + 0xd0)
#define RX_IDAF_DWORD4			(PORT_BASE + 0xd4)
#define RX_IDAF_DWORD5			(PORT_BASE + 0xd8)
#define RX_IDAF_DWORD6			(PORT_BASE + 0xdc)
#define RXOP_CHECK_CFG_H		(PORT_BASE + 0xfc)
#define DONE_RECEIVED_TIME		(PORT_BASE + 0x11c)
#define CHL_INT0			(PORT_BASE + 0x1b4)
#define CHL_INT0_HOTPLUG_TOUT_OFF	0
#define CHL_INT0_HOTPLUG_TOUT_MSK	(0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
#define CHL_INT0_SL_RX_BCST_ACK_OFF	1
#define CHL_INT0_SL_RX_BCST_ACK_MSK	(0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
#define CHL_INT0_SL_PHY_ENABLE_OFF	2
#define CHL_INT0_SL_PHY_ENABLE_MSK	(0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
#define CHL_INT0_NOT_RDY_OFF		4
#define CHL_INT0_NOT_RDY_MSK		(0x1 << CHL_INT0_NOT_RDY_OFF)
#define CHL_INT0_PHY_RDY_OFF		5
#define CHL_INT0_PHY_RDY_MSK		(0x1 << CHL_INT0_PHY_RDY_OFF)
#define CHL_INT1			(PORT_BASE + 0x1b8)
#define CHL_INT1_DMAC_TX_ECC_ERR_OFF	15
#define CHL_INT1_DMAC_TX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
#define CHL_INT1_DMAC_RX_ECC_ERR_OFF	17
#define CHL_INT1_DMAC_RX_ECC_ERR_MSK	(0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
#define CHL_INT2			(PORT_BASE + 0x1bc)
#define CHL_INT0_MSK			(PORT_BASE + 0x1c0)
#define CHL_INT1_MSK			(PORT_BASE + 0x1c4)
#define CHL_INT2_MSK			(PORT_BASE + 0x1c8)
#define CHL_INT_COAL_EN			(PORT_BASE + 0x1d0)
#define PHY_CTRL_RDY_MSK		(PORT_BASE + 0x2b0)
#define PHYCTRL_NOT_RDY_MSK		(PORT_BASE + 0x2b4)
#define PHYCTRL_DWS_RESET_MSK		(PORT_BASE + 0x2b8)
#define PHYCTRL_PHY_ENA_MSK		(PORT_BASE + 0x2bc)
#define SL_RX_BCAST_CHK_MSK		(PORT_BASE + 0x2c0)
#define PHYCTRL_OOB_RESTART_MSK		(PORT_BASE + 0x2c4)
#define DMA_TX_STATUS			(PORT_BASE + 0x2d0)
#define DMA_TX_STATUS_BUSY_OFF		0
#define DMA_TX_STATUS_BUSY_MSK		(0x1 << DMA_TX_STATUS_BUSY_OFF)
#define DMA_RX_STATUS			(PORT_BASE + 0x2e8)
#define DMA_RX_STATUS_BUSY_OFF		0
#define DMA_RX_STATUS_BUSY_MSK		(0x1 << DMA_RX_STATUS_BUSY_OFF)

#define AXI_CFG				(0x5100)
#define AM_CFG_MAX_TRANS		(0x5010)
#define AM_CFG_SINGLE_PORT_MAX_TRANS	(0x5014)

/* HW dma structures */
/* Delivery queue header */
/* dw0 */
#define CMD_HDR_RESP_REPORT_OFF		5
#define CMD_HDR_RESP_REPORT_MSK		(0x1 << CMD_HDR_RESP_REPORT_OFF)
#define CMD_HDR_TLR_CTRL_OFF		6
#define CMD_HDR_TLR_CTRL_MSK		(0x3 << CMD_HDR_TLR_CTRL_OFF)
#define CMD_HDR_PORT_OFF		18
#define CMD_HDR_PORT_MSK		(0xf << CMD_HDR_PORT_OFF)
#define CMD_HDR_PRIORITY_OFF		27
#define CMD_HDR_PRIORITY_MSK		(0x1 << CMD_HDR_PRIORITY_OFF)
#define CMD_HDR_CMD_OFF			29
#define CMD_HDR_CMD_MSK			(0x7 << CMD_HDR_CMD_OFF)
/* dw1 */
#define CMD_HDR_DIR_OFF			5
#define CMD_HDR_DIR_MSK			(0x3 << CMD_HDR_DIR_OFF)
#define CMD_HDR_RESET_OFF		7
#define CMD_HDR_RESET_MSK		(0x1 << CMD_HDR_RESET_OFF)
#define CMD_HDR_VDTL_OFF		10
#define CMD_HDR_VDTL_MSK		(0x1 << CMD_HDR_VDTL_OFF)
#define CMD_HDR_FRAME_TYPE_OFF		11
#define CMD_HDR_FRAME_TYPE_MSK		(0x1f << CMD_HDR_FRAME_TYPE_OFF)
#define CMD_HDR_DEV_ID_OFF		16
#define CMD_HDR_DEV_ID_MSK		(0xffff << CMD_HDR_DEV_ID_OFF)
/* dw2 */
#define CMD_HDR_CFL_OFF			0
#define CMD_HDR_CFL_MSK			(0x1ff << CMD_HDR_CFL_OFF)
#define CMD_HDR_NCQ_TAG_OFF		10
#define CMD_HDR_NCQ_TAG_MSK		(0x1f << CMD_HDR_NCQ_TAG_OFF)
#define CMD_HDR_MRFL_OFF		15
#define CMD_HDR_MRFL_MSK		(0x1ff << CMD_HDR_MRFL_OFF)
#define CMD_HDR_SG_MOD_OFF		24
#define CMD_HDR_SG_MOD_MSK		(0x3 << CMD_HDR_SG_MOD_OFF)
#define CMD_HDR_FIRST_BURST_OFF		26
#define CMD_HDR_FIRST_BURST_MSK		(0x1 << CMD_HDR_SG_MOD_OFF)
/* dw3 */
#define CMD_HDR_IPTT_OFF		0
#define CMD_HDR_IPTT_MSK		(0xffff << CMD_HDR_IPTT_OFF)
/* dw6 */
#define CMD_HDR_DIF_SGL_LEN_OFF		0
#define CMD_HDR_DIF_SGL_LEN_MSK		(0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
#define CMD_HDR_DATA_SGL_LEN_OFF	16
#define CMD_HDR_DATA_SGL_LEN_MSK	(0xffff << CMD_HDR_DATA_SGL_LEN_OFF)

/* Completion header */
/* dw0 */
#define CMPLT_HDR_RSPNS_XFRD_OFF	10
#define CMPLT_HDR_RSPNS_XFRD_MSK	(0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
#define CMPLT_HDR_ERX_OFF		12
#define CMPLT_HDR_ERX_MSK		(0x1 << CMPLT_HDR_ERX_OFF)
/* dw1 */
#define CMPLT_HDR_IPTT_OFF		0
#define CMPLT_HDR_IPTT_MSK		(0xffff << CMPLT_HDR_IPTT_OFF)
#define CMPLT_HDR_DEV_ID_OFF		16
#define CMPLT_HDR_DEV_ID_MSK		(0xffff << CMPLT_HDR_DEV_ID_OFF)

/* ITCT header */
/* qw0 */
#define ITCT_HDR_DEV_TYPE_OFF		0
#define ITCT_HDR_DEV_TYPE_MSK		(0x3 << ITCT_HDR_DEV_TYPE_OFF)
#define ITCT_HDR_VALID_OFF		2
#define ITCT_HDR_VALID_MSK		(0x1 << ITCT_HDR_VALID_OFF)
#define ITCT_HDR_MCR_OFF		5
#define ITCT_HDR_MCR_MSK		(0xf << ITCT_HDR_MCR_OFF)
#define ITCT_HDR_VLN_OFF		9
#define ITCT_HDR_VLN_MSK		(0xf << ITCT_HDR_VLN_OFF)
#define ITCT_HDR_PORT_ID_OFF		28
#define ITCT_HDR_PORT_ID_MSK		(0xf << ITCT_HDR_PORT_ID_OFF)
/* qw2 */
#define ITCT_HDR_INLT_OFF		0
#define ITCT_HDR_INLT_MSK		(0xffffULL << ITCT_HDR_INLT_OFF)
#define ITCT_HDR_BITLT_OFF		16
#define ITCT_HDR_BITLT_MSK		(0xffffULL << ITCT_HDR_BITLT_OFF)
#define ITCT_HDR_MCTLT_OFF		32
#define ITCT_HDR_MCTLT_MSK		(0xffffULL << ITCT_HDR_MCTLT_OFF)
#define ITCT_HDR_RTOLT_OFF		48
#define ITCT_HDR_RTOLT_MSK		(0xffffULL << ITCT_HDR_RTOLT_OFF)

struct hisi_sas_complete_v2_hdr {
	__le32 dw0;
	__le32 dw1;
	__le32 act;
	__le32 dw3;
};

#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096

static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
{
	void __iomem *regs = hisi_hba->regs + off;

	return readl(regs);
}

static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
{
	void __iomem *regs = hisi_hba->regs + off;

	writel(val, regs);
}

static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
				 u32 off, u32 val)
{
	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;

	writel(val, regs);
}

static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
				      int phy_no, u32 off)
{
	void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;

	return readl(regs);
}

static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
{
	int i, reset_val;
	u32 val;
	unsigned long end_time;
	struct device *dev = &hisi_hba->pdev->dev;

	/* The mask needs to be set depending on the number of phys */
	if (hisi_hba->n_phy == 9)
		reset_val = 0x1fffff;
	else
		reset_val = 0x7ffff;

	/* Disable all of the DQ */
	for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
		hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);

	/* Disable all of the PHYs */
	for (i = 0; i < hisi_hba->n_phy; i++) {
		u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);

		phy_cfg &= ~PHY_CTRL_RESET_MSK;
		hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
	}
	udelay(50);

	/* Ensure DMA tx & rx idle */
	for (i = 0; i < hisi_hba->n_phy; i++) {
		u32 dma_tx_status, dma_rx_status;

		end_time = jiffies + msecs_to_jiffies(1000);

		while (1) {
			dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
							    DMA_TX_STATUS);
			dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
							    DMA_RX_STATUS);

			if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
				!(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
				break;

			msleep(20);
			if (time_after(jiffies, end_time))
				return -EIO;
		}
	}

	/* Ensure axi bus idle */
	end_time = jiffies + msecs_to_jiffies(1000);
	while (1) {
		u32 axi_status =
			hisi_sas_read32(hisi_hba, AXI_CFG);

		if (axi_status == 0)
			break;

		msleep(20);
		if (time_after(jiffies, end_time))
			return -EIO;
	}

	/* reset and disable clock*/
	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
			reset_val);
	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
			reset_val);
	msleep(1);
	regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
	if (reset_val != (val & reset_val)) {
		dev_err(dev, "SAS reset fail.\n");
		return -EIO;
	}

	/* De-reset and enable clock*/
	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
			reset_val);
	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
			reset_val);
	msleep(1);
	regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
			&val);
	if (val & reset_val) {
		dev_err(dev, "SAS de-reset fail.\n");
		return -EIO;
	}

	return 0;
}

static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = &hisi_hba->pdev->dev;
	struct device_node *np = dev->of_node;
	int i;

	/* Global registers init */

	/* Deal with am-max-transmissions quirk */
	if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
		hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
		hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
				 0x2020);
	} /* Else, use defaults -> do nothing */

	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
			 (u32)((1ULL << hisi_hba->queue_count) - 1));
	hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
	hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
	hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
	hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
	hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
	hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
	hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
	hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
	hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
	hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
	hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
	for (i = 0; i < hisi_hba->queue_count; i++)
		hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);

	hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);

	for (i = 0; i < hisi_hba->n_phy; i++) {
		hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
		hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
		hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
		hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
		hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
		hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
	}

	for (i = 0; i < hisi_hba->queue_count; i++) {
		/* Delivery queue */
		hisi_sas_write32(hisi_hba,
				 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
				 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
				 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
				 HISI_SAS_QUEUE_SLOTS);

		/* Completion queue */
		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
				 upper_32_bits(hisi_hba->complete_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
				 lower_32_bits(hisi_hba->complete_hdr_dma[i]));

		hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
				 HISI_SAS_QUEUE_SLOTS);
	}

	/* itct */
	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
			 lower_32_bits(hisi_hba->itct_dma));

	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
			 upper_32_bits(hisi_hba->itct_dma));

	/* iost */
	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
			 lower_32_bits(hisi_hba->iost_dma));

	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
			 upper_32_bits(hisi_hba->iost_dma));

	/* breakpoint */
	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
			 lower_32_bits(hisi_hba->breakpoint_dma));

	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
			 upper_32_bits(hisi_hba->breakpoint_dma));

	/* SATA broken msg */
	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
			 lower_32_bits(hisi_hba->sata_breakpoint_dma));

	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
			 upper_32_bits(hisi_hba->sata_breakpoint_dma));

	/* SATA initial fis */
	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
			 lower_32_bits(hisi_hba->initial_fis_dma));

	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
			 upper_32_bits(hisi_hba->initial_fis_dma));
}

static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
{
	struct device *dev = &hisi_hba->pdev->dev;
	int rc;

	rc = reset_hw_v2_hw(hisi_hba);
	if (rc) {
		dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
		return rc;
	}

	msleep(100);
	init_reg_v2_hw(hisi_hba);

	return 0;
}

static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
{
	int rc;

	rc = hw_init_v2_hw(hisi_hba);
	if (rc)
		return rc;

	return 0;
}

static const struct hisi_sas_hw hisi_sas_v2_hw = {
	.hw_init = hisi_sas_v2_init,
	.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
	.complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
};

static int hisi_sas_v2_probe(struct platform_device *pdev)
{
	return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
}

static int hisi_sas_v2_remove(struct platform_device *pdev)
{
	return hisi_sas_remove(pdev);
}

static const struct of_device_id sas_v2_of_match[] = {
	{ .compatible = "hisilicon,hip06-sas-v2",},
	{},
};
MODULE_DEVICE_TABLE(of, sas_v2_of_match);

static struct platform_driver hisi_sas_v2_driver = {
	.probe = hisi_sas_v2_probe,
	.remove = hisi_sas_v2_remove,
	.driver = {
		.name = DRV_NAME,
		.of_match_table = sas_v2_of_match,
	},
};

module_platform_driver(hisi_sas_v2_driver);

MODULE_LICENSE("GPL");
MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
3417ba8a JG	1	/*
	2	* Copyright (c) 2016 Linaro Ltd.
	3	* Copyright (c) 2016 Hisilicon Limited.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; either version 2 of the License, or
	8	* (at your option) any later version.
	9	*
	10	*/
	11
	12	#include "hisi_sas.h"
	13	#define DRV_NAME "hisi_sas_v2_hw"
	14
45c901b8 JG	15	/* global registers need init*/
	16	#define DLVRY_QUEUE_ENABLE 0x0
	17	#define IOST_BASE_ADDR_LO 0x8
	18	#define IOST_BASE_ADDR_HI 0xc
	19	#define ITCT_BASE_ADDR_LO 0x10
	20	#define ITCT_BASE_ADDR_HI 0x14
	21	#define IO_BROKEN_MSG_ADDR_LO 0x18
	22	#define IO_BROKEN_MSG_ADDR_HI 0x1c
	23	#define PHY_CONTEXT 0x20
	24	#define PHY_STATE 0x24
	25	#define PHY_PORT_NUM_MA 0x28
	26	#define PORT_STATE 0x2c
	27	#define PORT_STATE_PHY8_PORT_NUM_OFF 16
	28	#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
	29	#define PORT_STATE_PHY8_CONN_RATE_OFF 20
	30	#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
	31	#define PHY_CONN_RATE 0x30
	32	#define HGC_TRANS_TASK_CNT_LIMIT 0x38
	33	#define AXI_AHB_CLK_CFG 0x3c
	34	#define ITCT_CLR 0x44
	35	#define ITCT_CLR_EN_OFF 16
	36	#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
	37	#define ITCT_DEV_OFF 0
	38	#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
	39	#define AXI_USER1 0x48
	40	#define AXI_USER2 0x4c
	41	#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
	42	#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
	43	#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
	44	#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
	45	#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
	46	#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
	47	#define HGC_GET_ITV_TIME 0x90
	48	#define DEVICE_MSG_WORK_MODE 0x94
	49	#define OPENA_WT_CONTI_TIME 0x9c
	50	#define I_T_NEXUS_LOSS_TIME 0xa0
	51	#define MAX_CON_TIME_LIMIT_TIME 0xa4
	52	#define BUS_INACTIVE_LIMIT_TIME 0xa8
	53	#define REJECT_TO_OPEN_LIMIT_TIME 0xac
	54	#define CFG_AGING_TIME 0xbc
	55	#define HGC_DFX_CFG2 0xc0
	56	#define HGC_IOMB_PROC1_STATUS 0x104
	57	#define CFG_1US_TIMER_TRSH 0xcc
	58	#define HGC_INVLD_DQE_INFO 0x148
	59	#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
	60	#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
	61	#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
	62	#define INT_COAL_EN 0x19c
	63	#define OQ_INT_COAL_TIME 0x1a0
	64	#define OQ_INT_COAL_CNT 0x1a4
	65	#define ENT_INT_COAL_TIME 0x1a8
	66	#define ENT_INT_COAL_CNT 0x1ac
	67	#define OQ_INT_SRC 0x1b0
	68	#define OQ_INT_SRC_MSK 0x1b4
	69	#define ENT_INT_SRC1 0x1b8
	70	#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
	71	#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
	72	#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
	73	#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
	74	#define ENT_INT_SRC2 0x1bc
	75	#define ENT_INT_SRC3 0x1c0
	76	#define ENT_INT_SRC3_ITC_INT_OFF 15
	77	#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
	78	#define ENT_INT_SRC_MSK1 0x1c4
79	#define ENT_INT_SRC_MSK2 0x1c8
80	#define ENT_INT_SRC_MSK3 0x1cc
81	#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82	#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83	#define SAS_ECC_INTR_MSK 0x1ec
84	#define HGC_ERR_STAT_EN 0x238
85	#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86	#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87	#define DLVRY_Q_0_DEPTH 0x268
88	#define DLVRY_Q_0_WR_PTR 0x26c
89	#define DLVRY_Q_0_RD_PTR 0x270
90	#define HYPER_STREAM_ID_EN_CFG 0xc80
91	#define OQ0_INT_SRC_MSK 0xc90
92	#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93	#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94	#define COMPL_Q_0_DEPTH 0x4e8
95	#define COMPL_Q_0_WR_PTR 0x4ec
96	#define COMPL_Q_0_RD_PTR 0x4f0
97
98	/* phy registers need init */
99	#define PORT_BASE (0x2000)
100
101	#define PHY_CFG (PORT_BASE + 0x0)
102	#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103	#define PHY_CFG_ENA_OFF 0
104	#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105	#define PHY_CFG_DC_OPT_OFF 2
106	#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107	#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108	#define PROG_PHY_LINK_RATE_MAX_OFF 0
109	#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110	#define PHY_CTRL (PORT_BASE + 0x14)
111	#define PHY_CTRL_RESET_OFF 0
112	#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113	#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114	#define SL_CFG (PORT_BASE + 0x84)
115	#define PHY_PCN (PORT_BASE + 0x44)
116	#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117	#define SL_CONTROL (PORT_BASE + 0x94)
118	#define SL_CONTROL_NOTIFY_EN_OFF 0
119	#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120	#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121	#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122	#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123	#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124	#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125	#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126	#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127	#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128	#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129	#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130	#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131	#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132	#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133	#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134	#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135	#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136	#define CHL_INT0 (PORT_BASE + 0x1b4)
137	#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138	#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139	#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140	#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141	#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142	#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143	#define CHL_INT0_NOT_RDY_OFF 4
144	#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145	#define CHL_INT0_PHY_RDY_OFF 5
146	#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147	#define CHL_INT1 (PORT_BASE + 0x1b8)
148	#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149	#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150	#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151	#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152	#define CHL_INT2 (PORT_BASE + 0x1bc)
153	#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154	#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155	#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156	#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157	#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158	#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159	#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160	#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161	#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162	#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163	#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164	#define DMA_TX_STATUS_BUSY_OFF 0
165	#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166	#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167	#define DMA_RX_STATUS_BUSY_OFF 0
168	#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170	#define AXI_CFG (0x5100)
171	#define AM_CFG_MAX_TRANS (0x5010)
172	#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174	/* HW dma structures */
175	/* Delivery queue header */
176	/* dw0 */
177	#define CMD_HDR_RESP_REPORT_OFF 5
178	#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179	#define CMD_HDR_TLR_CTRL_OFF 6
180	#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181	#define CMD_HDR_PORT_OFF 18
182	#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183	#define CMD_HDR_PRIORITY_OFF 27
184	#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185	#define CMD_HDR_CMD_OFF 29
186	#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187	/* dw1 */
188	#define CMD_HDR_DIR_OFF 5
189	#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190	#define CMD_HDR_RESET_OFF 7
191	#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192	#define CMD_HDR_VDTL_OFF 10
193	#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194	#define CMD_HDR_FRAME_TYPE_OFF 11
195	#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196	#define CMD_HDR_DEV_ID_OFF 16
197	#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198	/* dw2 */
199	#define CMD_HDR_CFL_OFF 0
200	#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201	#define CMD_HDR_NCQ_TAG_OFF 10
202	#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203	#define CMD_HDR_MRFL_OFF 15
204	#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205	#define CMD_HDR_SG_MOD_OFF 24
206	#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207	#define CMD_HDR_FIRST_BURST_OFF 26
208	#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209	/* dw3 */
210	#define CMD_HDR_IPTT_OFF 0
211	#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212	/* dw6 */
213	#define CMD_HDR_DIF_SGL_LEN_OFF 0
214	#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215	#define CMD_HDR_DATA_SGL_LEN_OFF 16
216	#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218	/* Completion header */
219	/* dw0 */
220	#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221	#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222	#define CMPLT_HDR_ERX_OFF 12
223	#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224	/* dw1 */
225	#define CMPLT_HDR_IPTT_OFF 0
226	#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227	#define CMPLT_HDR_DEV_ID_OFF 16
228	#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230	/* ITCT header */
231	/* qw0 */
232	#define ITCT_HDR_DEV_TYPE_OFF 0
233	#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234	#define ITCT_HDR_VALID_OFF 2
235	#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236	#define ITCT_HDR_MCR_OFF 5
237	#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238	#define ITCT_HDR_VLN_OFF 9
239	#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240	#define ITCT_HDR_PORT_ID_OFF 28
241	#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242	/* qw2 */
243	#define ITCT_HDR_INLT_OFF 0
244	#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245	#define ITCT_HDR_BITLT_OFF 16
246	#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247	#define ITCT_HDR_MCTLT_OFF 32
248	#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249	#define ITCT_HDR_RTOLT_OFF 48
250	#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1 JG	252	struct hisi_sas_complete_v2_hdr {
	253	__le32 dw0;
	254	__le32 dw1;
	255	__le32 act;
	256	__le32 dw3;
	257	};
	258
	259	#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
	260
	261	static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
	262	{
	263	void __iomem *regs = hisi_hba->regs + off;
	264
	265	return readl(regs);
	266	}
	267
	268	static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
	269	{
	270	void __iomem *regs = hisi_hba->regs + off;
	271
	272	writel(val, regs);
	273	}
	274
	275	static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
	276	u32 off, u32 val)
	277	{
	278	void __iomem regs = hisi_hba->regs + (0x400 phy_no) + off;
	279
	280	writel(val, regs);
	281	}
	282
	283	static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
	284	int phy_no, u32 off)
	285	{
	286	void __iomem regs = hisi_hba->regs + (0x400 phy_no) + off;
	287
	288	return readl(regs);
	289	}
	290
	291	static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
	292	{
	293	int i, reset_val;
	294	u32 val;
	295	unsigned long end_time;
	296	struct device *dev = &hisi_hba->pdev->dev;
	297
	298	/* The mask needs to be set depending on the number of phys */
	299	if (hisi_hba->n_phy == 9)
	300	reset_val = 0x1fffff;
	301	else
	302	reset_val = 0x7ffff;
	303
	304	/* Disable all of the DQ */
	305	for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
	306	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
	307
	308	/* Disable all of the PHYs */
	309	for (i = 0; i < hisi_hba->n_phy; i++) {
	310	u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
	311
	312	phy_cfg &= ~PHY_CTRL_RESET_MSK;
	313	hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
	314	}
	315	udelay(50);
316
317	/* Ensure DMA tx & rx idle */
318	for (i = 0; i < hisi_hba->n_phy; i++) {
319	u32 dma_tx_status, dma_rx_status;
320
321	end_time = jiffies + msecs_to_jiffies(1000);
322
323	while (1) {
324	dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
325	DMA_TX_STATUS);
326	dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
327	DMA_RX_STATUS);
328
329	if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
330	!(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
331	break;
332
333	msleep(20);
334	if (time_after(jiffies, end_time))
335	return -EIO;
336	}
337	}
338
339	/* Ensure axi bus idle */
340	end_time = jiffies + msecs_to_jiffies(1000);
341	while (1) {
342	u32 axi_status =
343	hisi_sas_read32(hisi_hba, AXI_CFG);
344
345	if (axi_status == 0)
346	break;
347
348	msleep(20);
349	if (time_after(jiffies, end_time))
350	return -EIO;
351	}
352
353	/* reset and disable clock*/
354	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
355	reset_val);
356	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
357	reset_val);
358	msleep(1);
359	regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
360	if (reset_val != (val & reset_val)) {
361	dev_err(dev, "SAS reset fail.\n");
362	return -EIO;
363	}
364
365	/* De-reset and enable clock*/
366	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
367	reset_val);
368	regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
369	reset_val);
370	msleep(1);
371	regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
372	&val);
373	if (val & reset_val) {
374	dev_err(dev, "SAS de-reset fail.\n");
375	return -EIO;
376	}
377
378	return 0;
379	}
380
381	static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
382	{
383	struct device *dev = &hisi_hba->pdev->dev;
384	struct device_node *np = dev->of_node;
385	int i;
386
387	/* Global registers init */
388
389	/* Deal with am-max-transmissions quirk */
390	if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
391	hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
392	hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
393	0x2020);
394	} /* Else, use defaults -> do nothing */
395
396	hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
397	(u32)((1ULL << hisi_hba->queue_count) - 1));
398	hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
399	hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
400	hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
401	hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
402	hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
403	hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
404	hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
405	hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
406	hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
407	hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
408	hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
409	hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
410	hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
411	hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
412	hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
413	hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
414	hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
415	hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
416	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
417	hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
418	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
419	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
420	hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
421	hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
422	for (i = 0; i < hisi_hba->queue_count; i++)
423	hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
424
425	hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
426	hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
427
428	for (i = 0; i < hisi_hba->n_phy; i++) {
429	hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
430	hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
431	hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
432	hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
433	hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
434	hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
435	hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
436	hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
437	hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
438	hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
439	hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
440	hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
441	hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
442	hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
443	hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
444	hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
445	hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
446	hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
447	hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
448	}
449
450	for (i = 0; i < hisi_hba->queue_count; i++) {
451	/* Delivery queue */
452	hisi_sas_write32(hisi_hba,
453	DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
454	upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
455
456	hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
457	lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
458
459	hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
460	HISI_SAS_QUEUE_SLOTS);
461
462	/* Completion queue */
463	hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
464	upper_32_bits(hisi_hba->complete_hdr_dma[i]));
465
466	hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
467	lower_32_bits(hisi_hba->complete_hdr_dma[i]));
468
469	hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
470	HISI_SAS_QUEUE_SLOTS);
471	}
472
473	/* itct */
474	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
475	lower_32_bits(hisi_hba->itct_dma));
476
477	hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
478	upper_32_bits(hisi_hba->itct_dma));
479
480	/* iost */
481	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
482	lower_32_bits(hisi_hba->iost_dma));
483
484	hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
485	upper_32_bits(hisi_hba->iost_dma));
486
487	/* breakpoint */
488	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
489	lower_32_bits(hisi_hba->breakpoint_dma));
490
491	hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
492	upper_32_bits(hisi_hba->breakpoint_dma));
493
494	/* SATA broken msg */
495	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
496	lower_32_bits(hisi_hba->sata_breakpoint_dma));
497
498	hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
499	upper_32_bits(hisi_hba->sata_breakpoint_dma));
500
501	/* SATA initial fis */
502	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
503	lower_32_bits(hisi_hba->initial_fis_dma));
504
505	hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
506	upper_32_bits(hisi_hba->initial_fis_dma));
507	}
508
509	static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
510	{
511	struct device *dev = &hisi_hba->pdev->dev;
512	int rc;
513
514	rc = reset_hw_v2_hw(hisi_hba);
515	if (rc) {
516	dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
517	return rc;
518	}
519
520	msleep(100);
521	init_reg_v2_hw(hisi_hba);
522
523	return 0;
524	}
525
526	static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
527	{
528	int rc;
529
530	rc = hw_init_v2_hw(hisi_hba);
531	if (rc)
532	return rc;
533
534	return 0;
535	}
536
3417ba8a	537	static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 JG	538	.hw_init = hisi_sas_v2_init,
	539	.max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
	540	.complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a JG	541	};
	542
	543	static int hisi_sas_v2_probe(struct platform_device *pdev)
	544	{
	545	return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
	546	}
	547
	548	static int hisi_sas_v2_remove(struct platform_device *pdev)
	549	{
	550	return hisi_sas_remove(pdev);
	551	}
	552
	553	static const struct of_device_id sas_v2_of_match[] = {
	554	{ .compatible = "hisilicon,hip06-sas-v2",},
	555	{},
	556	};
	557	MODULE_DEVICE_TABLE(of, sas_v2_of_match);
	558
	559	static struct platform_driver hisi_sas_v2_driver = {
	560	.probe = hisi_sas_v2_probe,
	561	.remove = hisi_sas_v2_remove,
	562	.driver = {
	563	.name = DRV_NAME,
	564	.of_match_table = sas_v2_of_match,
	565	},
	566	};
	567
	568	module_platform_driver(hisi_sas_v2_driver);
	569
	570	MODULE_LICENSE("GPL");
	571	MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
	572	MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
	573	MODULE_ALIAS("platform:" DRV_NAME);