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hisi_sas: add v2 code to send smp command
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
CommitLineData
3417ba8a
JG		 1/*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v2_hw"
14
45c901b8
JG		 15/* global registers need init*/
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define IO_BROKEN_MSG_ADDR_LO 0x18
22#define IO_BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PORT_STATE_PHY8_PORT_NUM_OFF 16
28#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29#define PORT_STATE_PHY8_CONN_RATE_OFF 20
30#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31#define PHY_CONN_RATE 0x30
32#define HGC_TRANS_TASK_CNT_LIMIT 0x38
33#define AXI_AHB_CLK_CFG 0x3c
34#define ITCT_CLR 0x44
35#define ITCT_CLR_EN_OFF 16
36#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37#define ITCT_DEV_OFF 0
38#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39#define AXI_USER1 0x48
40#define AXI_USER2 0x4c
41#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47#define HGC_GET_ITV_TIME 0x90
48#define DEVICE_MSG_WORK_MODE 0x94
49#define OPENA_WT_CONTI_TIME 0x9c
50#define I_T_NEXUS_LOSS_TIME 0xa0
51#define MAX_CON_TIME_LIMIT_TIME 0xa4
52#define BUS_INACTIVE_LIMIT_TIME 0xa8
53#define REJECT_TO_OPEN_LIMIT_TIME 0xac
54#define CFG_AGING_TIME 0xbc
55#define HGC_DFX_CFG2 0xc0
56#define HGC_IOMB_PROC1_STATUS 0x104
57#define CFG_1US_TIMER_TRSH 0xcc
58#define HGC_INVLD_DQE_INFO 0x148
59#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62#define INT_COAL_EN 0x19c
63#define OQ_INT_COAL_TIME 0x1a0
64#define OQ_INT_COAL_CNT 0x1a4
65#define ENT_INT_COAL_TIME 0x1a8
66#define ENT_INT_COAL_CNT 0x1ac
67#define OQ_INT_SRC 0x1b0
68#define OQ_INT_SRC_MSK 0x1b4
69#define ENT_INT_SRC1 0x1b8
70#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74#define ENT_INT_SRC2 0x1bc
75#define ENT_INT_SRC3 0x1c0
76#define ENT_INT_SRC3_ITC_INT_OFF 15
77#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83#define SAS_ECC_INTR_MSK 0x1ec
84#define HGC_ERR_STAT_EN 0x238
85#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87#define DLVRY_Q_0_DEPTH 0x268
88#define DLVRY_Q_0_WR_PTR 0x26c
89#define DLVRY_Q_0_RD_PTR 0x270
90#define HYPER_STREAM_ID_EN_CFG 0xc80
91#define OQ0_INT_SRC_MSK 0xc90
92#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94#define COMPL_Q_0_DEPTH 0x4e8
95#define COMPL_Q_0_WR_PTR 0x4ec
96#define COMPL_Q_0_RD_PTR 0x4f0
97
98/* phy registers need init */
99#define PORT_BASE (0x2000)
100
101#define PHY_CFG (PORT_BASE + 0x0)
102#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103#define PHY_CFG_ENA_OFF 0
104#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105#define PHY_CFG_DC_OPT_OFF 2
106#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108#define PROG_PHY_LINK_RATE_MAX_OFF 0
109#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110#define PHY_CTRL (PORT_BASE + 0x14)
111#define PHY_CTRL_RESET_OFF 0
112#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114#define SL_CFG (PORT_BASE + 0x84)
115#define PHY_PCN (PORT_BASE + 0x44)
116#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136#define CHL_INT0 (PORT_BASE + 0x1b4)
137#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143#define CHL_INT0_NOT_RDY_OFF 4
144#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145#define CHL_INT0_PHY_RDY_OFF 5
146#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147#define CHL_INT1 (PORT_BASE + 0x1b8)
148#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152#define CHL_INT2 (PORT_BASE + 0x1bc)
153#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164#define DMA_TX_STATUS_BUSY_OFF 0
165#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167#define DMA_RX_STATUS_BUSY_OFF 0
168#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170#define AXI_CFG (0x5100)
171#define AM_CFG_MAX_TRANS (0x5010)
172#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174/* HW dma structures */
175/* Delivery queue header */
176/* dw0 */
177#define CMD_HDR_RESP_REPORT_OFF 5
178#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179#define CMD_HDR_TLR_CTRL_OFF 6
180#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181#define CMD_HDR_PORT_OFF 18
182#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183#define CMD_HDR_PRIORITY_OFF 27
184#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185#define CMD_HDR_CMD_OFF 29
186#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187/* dw1 */
188#define CMD_HDR_DIR_OFF 5
189#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190#define CMD_HDR_RESET_OFF 7
191#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192#define CMD_HDR_VDTL_OFF 10
193#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194#define CMD_HDR_FRAME_TYPE_OFF 11
195#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196#define CMD_HDR_DEV_ID_OFF 16
197#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198/* dw2 */
199#define CMD_HDR_CFL_OFF 0
200#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201#define CMD_HDR_NCQ_TAG_OFF 10
202#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203#define CMD_HDR_MRFL_OFF 15
204#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205#define CMD_HDR_SG_MOD_OFF 24
206#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207#define CMD_HDR_FIRST_BURST_OFF 26
208#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209/* dw3 */
210#define CMD_HDR_IPTT_OFF 0
211#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212/* dw6 */
213#define CMD_HDR_DIF_SGL_LEN_OFF 0
214#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215#define CMD_HDR_DATA_SGL_LEN_OFF 16
216#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218/* Completion header */
219/* dw0 */
220#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222#define CMPLT_HDR_ERX_OFF 12
223#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224/* dw1 */
225#define CMPLT_HDR_IPTT_OFF 0
226#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227#define CMPLT_HDR_DEV_ID_OFF 16
228#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230/* ITCT header */
231/* qw0 */
232#define ITCT_HDR_DEV_TYPE_OFF 0
233#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234#define ITCT_HDR_VALID_OFF 2
235#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236#define ITCT_HDR_MCR_OFF 5
237#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238#define ITCT_HDR_VLN_OFF 9
239#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240#define ITCT_HDR_PORT_ID_OFF 28
241#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242/* qw2 */
243#define ITCT_HDR_INLT_OFF 0
244#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245#define ITCT_HDR_BITLT_OFF 16
246#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247#define ITCT_HDR_MCTLT_OFF 32
248#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249#define ITCT_HDR_RTOLT_OFF 48
250#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1
JG		 252struct hisi_sas_complete_v2_hdr {
253 __le32 dw0;
254 __le32 dw1;
255 __le32 act;
256 __le32 dw3;
257};
258
7911e66f
JG		 259enum {
260 HISI_SAS_PHY_PHY_UPDOWN,
d3bf3d84 261 HISI_SAS_PHY_CHNL_INT,
7911e66f
JG		 262 HISI_SAS_PHY_INT_NR
263};
264
94eac9e1
JG		 265#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
266
8c36e31d
JG		 267#define DIR_NO_DATA 0
268#define DIR_TO_INI 1
269#define DIR_TO_DEVICE 2
270#define DIR_RESERVED 3
271
94eac9e1
JG		 272static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
273{
274 void __iomem *regs = hisi_hba->regs + off;
275
276 return readl(regs);
277}
278
8c36e31d
JG		 279static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
280{
281 void __iomem *regs = hisi_hba->regs + off;
282
283 return readl_relaxed(regs);
284}
285
94eac9e1
JG		 286static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
287{
288 void __iomem *regs = hisi_hba->regs + off;
289
290 writel(val, regs);
291}
292
293static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
294 u32 off, u32 val)
295{
296 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
297
298 writel(val, regs);
299}
300
301static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
302 int phy_no, u32 off)
303{
304 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
305
306 return readl(regs);
307}
308
29a20428
JG		 309static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
310{
311 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
312
313 cfg &= ~PHY_CFG_DC_OPT_MSK;
314 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
315 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
316}
317
806bb768
JG		 318static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
319{
320 struct sas_identify_frame identify_frame;
321 u32 *identify_buffer;
322
323 memset(&identify_frame, 0, sizeof(identify_frame));
324 identify_frame.dev_type = SAS_END_DEVICE;
325 identify_frame.frame_type = 0;
326 identify_frame._un1 = 1;
327 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
328 identify_frame.target_bits = SAS_PROTOCOL_NONE;
329 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
330 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
331 identify_frame.phy_id = phy_no;
332 identify_buffer = (u32 *)(&identify_frame);
333
334 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
335 __swab32(identify_buffer[0]));
336 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
337 identify_buffer[2]);
338 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
339 identify_buffer[1]);
340 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
341 identify_buffer[4]);
342 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
343 identify_buffer[3]);
344 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
345 __swab32(identify_buffer[5]));
346}
347
348static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
349{
350 int i;
351
352 for (i = 0; i < hisi_hba->n_phy; i++)
353 config_id_frame_v2_hw(hisi_hba, i);
354}
355
94eac9e1
JG		 356static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
357{
358 int i, reset_val;
359 u32 val;
360 unsigned long end_time;
361 struct device *dev = &hisi_hba->pdev->dev;
362
363 /* The mask needs to be set depending on the number of phys */
364 if (hisi_hba->n_phy == 9)
365 reset_val = 0x1fffff;
366 else
367 reset_val = 0x7ffff;
368
369 /* Disable all of the DQ */
370 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
371 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
372
373 /* Disable all of the PHYs */
374 for (i = 0; i < hisi_hba->n_phy; i++) {
375 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
376
377 phy_cfg &= ~PHY_CTRL_RESET_MSK;
378 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
379 }
380 udelay(50);
381
382 /* Ensure DMA tx & rx idle */
383 for (i = 0; i < hisi_hba->n_phy; i++) {
384 u32 dma_tx_status, dma_rx_status;
385
386 end_time = jiffies + msecs_to_jiffies(1000);
387
388 while (1) {
389 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
390 DMA_TX_STATUS);
391 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
392 DMA_RX_STATUS);
393
394 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
395 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
396 break;
397
398 msleep(20);
399 if (time_after(jiffies, end_time))
400 return -EIO;
401 }
402 }
403
404 /* Ensure axi bus idle */
405 end_time = jiffies + msecs_to_jiffies(1000);
406 while (1) {
407 u32 axi_status =
408 hisi_sas_read32(hisi_hba, AXI_CFG);
409
410 if (axi_status == 0)
411 break;
412
413 msleep(20);
414 if (time_after(jiffies, end_time))
415 return -EIO;
416 }
417
418 /* reset and disable clock*/
419 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
420 reset_val);
421 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
422 reset_val);
423 msleep(1);
424 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
425 if (reset_val != (val & reset_val)) {
426 dev_err(dev, "SAS reset fail.\n");
427 return -EIO;
428 }
429
430 /* De-reset and enable clock*/
431 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
432 reset_val);
433 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
434 reset_val);
435 msleep(1);
436 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
437 &val);
438 if (val & reset_val) {
439 dev_err(dev, "SAS de-reset fail.\n");
440 return -EIO;
441 }
442
443 return 0;
444}
445
446static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
447{
448 struct device *dev = &hisi_hba->pdev->dev;
449 struct device_node *np = dev->of_node;
450 int i;
451
452 /* Global registers init */
453
454 /* Deal with am-max-transmissions quirk */
455 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
456 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
457 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
458 0x2020);
459 } /* Else, use defaults -> do nothing */
460
461 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
462 (u32)((1ULL << hisi_hba->queue_count) - 1));
463 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
464 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
465 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
466 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
467 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
468 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
469 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
470 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
471 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
472 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
473 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
474 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
475 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
476 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
477 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
478 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
479 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
480 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
481 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
482 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
483 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
484 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
485 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
486 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
487 for (i = 0; i < hisi_hba->queue_count; i++)
488 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
489
490 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
491 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
492
493 for (i = 0; i < hisi_hba->n_phy; i++) {
494 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
495 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
496 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
497 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
498 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
499 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
500 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
501 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
502 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
503 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
504 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
505 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
506 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
507 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
508 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
509 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
510 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
511 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
512 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
513 }
514
515 for (i = 0; i < hisi_hba->queue_count; i++) {
516 /* Delivery queue */
517 hisi_sas_write32(hisi_hba,
518 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
519 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
520
521 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
522 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
523
524 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
525 HISI_SAS_QUEUE_SLOTS);
526
527 /* Completion queue */
528 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
529 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
530
531 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
532 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
533
534 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
535 HISI_SAS_QUEUE_SLOTS);
536 }
537
538 /* itct */
539 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
540 lower_32_bits(hisi_hba->itct_dma));
541
542 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
543 upper_32_bits(hisi_hba->itct_dma));
544
545 /* iost */
546 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
547 lower_32_bits(hisi_hba->iost_dma));
548
549 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
550 upper_32_bits(hisi_hba->iost_dma));
551
552 /* breakpoint */
553 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
554 lower_32_bits(hisi_hba->breakpoint_dma));
555
556 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
557 upper_32_bits(hisi_hba->breakpoint_dma));
558
559 /* SATA broken msg */
560 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
561 lower_32_bits(hisi_hba->sata_breakpoint_dma));
562
563 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
564 upper_32_bits(hisi_hba->sata_breakpoint_dma));
565
566 /* SATA initial fis */
567 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
568 lower_32_bits(hisi_hba->initial_fis_dma));
569
570 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
571 upper_32_bits(hisi_hba->initial_fis_dma));
572}
573
574static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
575{
576 struct device *dev = &hisi_hba->pdev->dev;
577 int rc;
578
579 rc = reset_hw_v2_hw(hisi_hba);
580 if (rc) {
581 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
582 return rc;
583 }
584
585 msleep(100);
586 init_reg_v2_hw(hisi_hba);
587
806bb768
JG		 588 init_id_frame_v2_hw(hisi_hba);
589
94eac9e1
JG		 590 return 0;
591}
592
29a20428
JG		 593static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
594{
595 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
596
597 cfg |= PHY_CFG_ENA_MSK;
598 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
599}
600
601static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
602{
603 config_id_frame_v2_hw(hisi_hba, phy_no);
604 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
605 enable_phy_v2_hw(hisi_hba, phy_no);
606}
607
608static void start_phys_v2_hw(unsigned long data)
609{
610 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
611 int i;
612
613 for (i = 0; i < hisi_hba->n_phy; i++)
614 start_phy_v2_hw(hisi_hba, i);
615}
616
617static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
618{
619 int i;
620 struct timer_list *timer = &hisi_hba->timer;
621
622 for (i = 0; i < hisi_hba->n_phy; i++) {
623 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
624 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
625 }
626
627 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
628 mod_timer(timer, jiffies + HZ);
629}
630
7911e66f
JG		 631static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
632{
633 u32 sl_control;
634
635 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
636 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
637 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
638 msleep(1);
639 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
640 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
641 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
642}
643
5473c060
JG		 644static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
645{
646 int i, bitmap = 0;
647 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
648 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
649
650 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
651 if (phy_state & 1 << i)
652 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
653 bitmap |= 1 << i;
654
655 if (hisi_hba->n_phy == 9) {
656 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
657
658 if (phy_state & 1 << 8)
659 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
660 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
661 bitmap |= 1 << 9;
662 }
663
664 return bitmap;
665}
666
8c36e31d
JG		 667/**
668 * This function allocates across all queues to load balance.
669 * Slots are allocated from queues in a round-robin fashion.
670 *
671 * The callpath to this function and upto writing the write
672 * queue pointer should be safe from interruption.
673 */
674static int get_free_slot_v2_hw(struct hisi_hba *hisi_hba, int *q, int *s)
675{
676 struct device *dev = &hisi_hba->pdev->dev;
677 u32 r, w;
678 int queue = hisi_hba->queue;
679
680 while (1) {
681 w = hisi_sas_read32_relaxed(hisi_hba,
682 DLVRY_Q_0_WR_PTR + (queue * 0x14));
683 r = hisi_sas_read32_relaxed(hisi_hba,
684 DLVRY_Q_0_RD_PTR + (queue * 0x14));
685 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
686 queue = (queue + 1) % hisi_hba->queue_count;
687 if (queue == hisi_hba->queue) {
688 dev_warn(dev, "could not find free slot\n");
689 return -EAGAIN;
690 }
691 continue;
692 }
693 break;
694 }
695 hisi_hba->queue = (queue + 1) % hisi_hba->queue_count;
696 *q = queue;
697 *s = w;
698 return 0;
699}
700
701static void start_delivery_v2_hw(struct hisi_hba *hisi_hba)
702{
703 int dlvry_queue = hisi_hba->slot_prep->dlvry_queue;
704 int dlvry_queue_slot = hisi_hba->slot_prep->dlvry_queue_slot;
705
706 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
707 ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS);
708}
709
710static int prep_prd_sge_v2_hw(struct hisi_hba *hisi_hba,
711 struct hisi_sas_slot *slot,
712 struct hisi_sas_cmd_hdr *hdr,
713 struct scatterlist *scatter,
714 int n_elem)
715{
716 struct device *dev = &hisi_hba->pdev->dev;
717 struct scatterlist *sg;
718 int i;
719
720 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
721 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
722 n_elem);
723 return -EINVAL;
724 }
725
726 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
727 &slot->sge_page_dma);
728 if (!slot->sge_page)
729 return -ENOMEM;
730
731 for_each_sg(scatter, sg, n_elem, i) {
732 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
733
734 entry->addr = cpu_to_le64(sg_dma_address(sg));
735 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
736 entry->data_len = cpu_to_le32(sg_dma_len(sg));
737 entry->data_off = 0;
738 }
739
740 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
741
742 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
743
744 return 0;
745}
746
c2d89392
JG		 747static int prep_smp_v2_hw(struct hisi_hba *hisi_hba,
748 struct hisi_sas_slot *slot)
749{
750 struct sas_task *task = slot->task;
751 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
752 struct domain_device *device = task->dev;
753 struct device *dev = &hisi_hba->pdev->dev;
754 struct hisi_sas_port *port = slot->port;
755 struct scatterlist *sg_req, *sg_resp;
756 struct hisi_sas_device *sas_dev = device->lldd_dev;
757 dma_addr_t req_dma_addr;
758 unsigned int req_len, resp_len;
759 int elem, rc;
760
761 /*
762 * DMA-map SMP request, response buffers
763 */
764 /* req */
765 sg_req = &task->smp_task.smp_req;
766 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
767 if (!elem)
768 return -ENOMEM;
769 req_len = sg_dma_len(sg_req);
770 req_dma_addr = sg_dma_address(sg_req);
771
772 /* resp */
773 sg_resp = &task->smp_task.smp_resp;
774 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
775 if (!elem) {
776 rc = -ENOMEM;
777 goto err_out_req;
778 }
779 resp_len = sg_dma_len(sg_resp);
780 if ((req_len & 0x3) || (resp_len & 0x3)) {
781 rc = -EINVAL;
782 goto err_out_resp;
783 }
784
785 /* create header */
786 /* dw0 */
787 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
788 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
789 (2 << CMD_HDR_CMD_OFF)); /* smp */
790
791 /* map itct entry */
792 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
793 (1 << CMD_HDR_FRAME_TYPE_OFF) |
794 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
795
796 /* dw2 */
797 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
798 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
799 CMD_HDR_MRFL_OFF));
800
801 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
802
803 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
804 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
805
806 return 0;
807
808err_out_resp:
809 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
810 DMA_FROM_DEVICE);
811err_out_req:
812 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
813 DMA_TO_DEVICE);
814 return rc;
815}
816
8c36e31d
JG		 817static int prep_ssp_v2_hw(struct hisi_hba *hisi_hba,
818 struct hisi_sas_slot *slot, int is_tmf,
819 struct hisi_sas_tmf_task *tmf)
820{
821 struct sas_task *task = slot->task;
822 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
823 struct domain_device *device = task->dev;
824 struct hisi_sas_device *sas_dev = device->lldd_dev;
825 struct hisi_sas_port *port = slot->port;
826 struct sas_ssp_task *ssp_task = &task->ssp_task;
827 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
828 int has_data = 0, rc, priority = is_tmf;
829 u8 *buf_cmd;
830 u32 dw1 = 0, dw2 = 0;
831
832 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
833 (2 << CMD_HDR_TLR_CTRL_OFF) |
834 (port->id << CMD_HDR_PORT_OFF) |
835 (priority << CMD_HDR_PRIORITY_OFF) |
836 (1 << CMD_HDR_CMD_OFF)); /* ssp */
837
838 dw1 = 1 << CMD_HDR_VDTL_OFF;
839 if (is_tmf) {
840 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
841 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
842 } else {
843 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
844 switch (scsi_cmnd->sc_data_direction) {
845 case DMA_TO_DEVICE:
846 has_data = 1;
847 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
848 break;
849 case DMA_FROM_DEVICE:
850 has_data = 1;
851 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
852 break;
853 default:
854 dw1 &= ~CMD_HDR_DIR_MSK;
855 }
856 }
857
858 /* map itct entry */
859 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
860 hdr->dw1 = cpu_to_le32(dw1);
861
862 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
863 + 3) / 4) << CMD_HDR_CFL_OFF) |
864 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
865 (2 << CMD_HDR_SG_MOD_OFF);
866 hdr->dw2 = cpu_to_le32(dw2);
867
868 hdr->transfer_tags = cpu_to_le32(slot->idx);
869
870 if (has_data) {
871 rc = prep_prd_sge_v2_hw(hisi_hba, slot, hdr, task->scatter,
872 slot->n_elem);
873 if (rc)
874 return rc;
875 }
876
877 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
878 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
879 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
880
881 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
882
883 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
884 if (!is_tmf) {
885 buf_cmd[9] = task->ssp_task.task_attr |
886 (task->ssp_task.task_prio << 3);
887 memcpy(buf_cmd + 12, task->ssp_task.cmd->cmnd,
888 task->ssp_task.cmd->cmd_len);
889 } else {
890 buf_cmd[10] = tmf->tmf;
891 switch (tmf->tmf) {
892 case TMF_ABORT_TASK:
893 case TMF_QUERY_TASK:
894 buf_cmd[12] =
895 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
896 buf_cmd[13] =
897 tmf->tag_of_task_to_be_managed & 0xff;
898 break;
899 default:
900 break;
901 }
902 }
903
904 return 0;
905}
906
31a9cfa6
JG		 907static int
908slot_complete_v2_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot,
909 int abort)
910{
911 struct sas_task *task = slot->task;
912 struct hisi_sas_device *sas_dev;
913 struct device *dev = &hisi_hba->pdev->dev;
914 struct task_status_struct *ts;
915 struct domain_device *device;
916 enum exec_status sts;
917 struct hisi_sas_complete_v2_hdr *complete_queue =
918 hisi_hba->complete_hdr[slot->cmplt_queue];
919 struct hisi_sas_complete_v2_hdr *complete_hdr =
920 &complete_queue[slot->cmplt_queue_slot];
921
922 if (unlikely(!task || !task->lldd_task || !task->dev))
923 return -EINVAL;
924
925 ts = &task->task_status;
926 device = task->dev;
927 sas_dev = device->lldd_dev;
928
929 task->task_state_flags &=
930 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
931 task->task_state_flags |= SAS_TASK_STATE_DONE;
932
933 memset(ts, 0, sizeof(*ts));
934 ts->resp = SAS_TASK_COMPLETE;
935
936 if (unlikely(!sas_dev || abort)) {
937 if (!sas_dev)
938 dev_dbg(dev, "slot complete: port has not device\n");
939 ts->stat = SAS_PHY_DOWN;
940 goto out;
941 }
942
943 if ((complete_hdr->dw0 & CMPLT_HDR_ERX_MSK) &&
944 (!(complete_hdr->dw0 & CMPLT_HDR_RSPNS_XFRD_MSK))) {
945 dev_dbg(dev, "%s slot %d has error info 0x%x\n",
946 __func__, slot->cmplt_queue_slot,
947 complete_hdr->dw0 & CMPLT_HDR_ERX_MSK);
948
949 goto out;
950 }
951
952 switch (task->task_proto) {
953 case SAS_PROTOCOL_SSP:
954 {
955 struct ssp_response_iu *iu = slot->status_buffer +
956 sizeof(struct hisi_sas_err_record);
957
958 sas_ssp_task_response(dev, task, iu);
959 break;
960 }
961 case SAS_PROTOCOL_SMP:
962 {
963 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
964 void *to;
965
966 ts->stat = SAM_STAT_GOOD;
967 to = kmap_atomic(sg_page(sg_resp));
968
969 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
970 DMA_FROM_DEVICE);
971 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
972 DMA_TO_DEVICE);
973 memcpy(to + sg_resp->offset,
974 slot->status_buffer +
975 sizeof(struct hisi_sas_err_record),
976 sg_dma_len(sg_resp));
977 kunmap_atomic(to);
978 break;
979 }
980 case SAS_PROTOCOL_SATA:
981 case SAS_PROTOCOL_STP:
982 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
983 default:
984 ts->stat = SAM_STAT_CHECK_CONDITION;
985 break;
986 }
987
988 if (!slot->port->port_attached) {
989 dev_err(dev, "slot complete: port %d has removed\n",
990 slot->port->sas_port.id);
991 ts->stat = SAS_PHY_DOWN;
992 }
993
994out:
995 if (sas_dev && sas_dev->running_req)
996 sas_dev->running_req--;
997
998 hisi_sas_slot_task_free(hisi_hba, task, slot);
999 sts = ts->stat;
1000
1001 if (task->task_done)
1002 task->task_done(task);
1003
1004 return sts;
1005}
1006
7911e66f
JG		 1007static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1008{
1009 int i, res = 0;
1010 u32 context, port_id, link_rate, hard_phy_linkrate;
1011 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1012 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1013 struct device *dev = &hisi_hba->pdev->dev;
1014 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1015 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
1016
1017 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
1018
1019 /* Check for SATA dev */
1020 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1021 if (context & (1 << phy_no))
1022 goto end;
1023
1024 if (phy_no == 8) {
1025 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1026
1027 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1028 PORT_STATE_PHY8_PORT_NUM_OFF;
1029 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1030 PORT_STATE_PHY8_CONN_RATE_OFF;
1031 } else {
1032 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1033 port_id = (port_id >> (4 * phy_no)) & 0xf;
1034 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1035 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1036 }
1037
1038 if (port_id == 0xf) {
1039 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
1040 res = IRQ_NONE;
1041 goto end;
1042 }
1043
1044 for (i = 0; i < 6; i++) {
1045 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1046 RX_IDAF_DWORD0 + (i * 4));
1047 frame_rcvd[i] = __swab32(idaf);
1048 }
1049
1050 /* Get the linkrates */
1051 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1052 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1053 sas_phy->linkrate = link_rate;
1054 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1055 HARD_PHY_LINKRATE);
1056 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1057 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1058
1059 sas_phy->oob_mode = SAS_OOB_MODE;
1060 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
1061 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1062 phy->port_id = port_id;
1063 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1064 phy->phy_type |= PORT_TYPE_SAS;
1065 phy->phy_attached = 1;
1066 phy->identify.device_type = id->dev_type;
1067 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1068 if (phy->identify.device_type == SAS_END_DEVICE)
1069 phy->identify.target_port_protocols =
1070 SAS_PROTOCOL_SSP;
1071 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1072 phy->identify.target_port_protocols =
1073 SAS_PROTOCOL_SMP;
1074 queue_work(hisi_hba->wq, &phy->phyup_ws);
1075
1076end:
1077 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1078 CHL_INT0_SL_PHY_ENABLE_MSK);
1079 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1080
1081 return res;
1082}
1083
5473c060
JG		 1084static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1085{
1086 int res = 0;
1087 u32 phy_cfg, phy_state;
1088
1089 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1090
1091 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
1092
1093 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1094
1095 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1096
1097 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1098 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1099
1100 return res;
1101}
1102
7911e66f
JG		 1103static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
1104{
1105 struct hisi_hba *hisi_hba = p;
1106 u32 irq_msk;
1107 int phy_no = 0;
1108 irqreturn_t res = IRQ_HANDLED;
1109
1110 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
1111 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
1112 while (irq_msk) {
1113 if (irq_msk & 1) {
1114 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1115 CHL_INT0);
1116
1117 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1118 /* phy up */
1119 if (phy_up_v2_hw(phy_no, hisi_hba)) {
1120 res = IRQ_NONE;
1121 goto end;
1122 }
1123
5473c060
JG		 1124 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1125 /* phy down */
1126 if (phy_down_v2_hw(phy_no, hisi_hba)) {
1127 res = IRQ_NONE;
1128 goto end;
1129 }
7911e66f
JG		 1130 }
1131 irq_msk >>= 1;
1132 phy_no++;
1133 }
1134
1135end:
1136 return res;
1137}
1138
d3bf3d84
JG		 1139static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
1140{
1141 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1142 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1143 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1144 unsigned long flags;
1145
1146 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1147
1148 spin_lock_irqsave(&hisi_hba->lock, flags);
1149 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1150 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1151
1152 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1153 CHL_INT0_SL_RX_BCST_ACK_MSK);
1154 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1155}
1156
1157static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
1158{
1159 struct hisi_hba *hisi_hba = p;
1160 struct device *dev = &hisi_hba->pdev->dev;
1161 u32 ent_msk, ent_tmp, irq_msk;
1162 int phy_no = 0;
1163
1164 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1165 ent_tmp = ent_msk;
1166 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1167 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1168
1169 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
1170 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
1171
1172 while (irq_msk) {
1173 if (irq_msk & (1 << phy_no)) {
1174 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1175 CHL_INT0);
1176 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1177 CHL_INT1);
1178 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1179 CHL_INT2);
1180
1181 if (irq_value1) {
1182 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1183 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1184 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1185 dev_name(dev), irq_value1);
1186
1187 hisi_sas_phy_write32(hisi_hba, phy_no,
1188 CHL_INT1, irq_value1);
1189 }
1190
1191 if (irq_value2)
1192 hisi_sas_phy_write32(hisi_hba, phy_no,
1193 CHL_INT2, irq_value2);
1194
1195
1196 if (irq_value0) {
1197 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
1198 phy_bcast_v2_hw(phy_no, hisi_hba);
1199
1200 hisi_sas_phy_write32(hisi_hba, phy_no,
1201 CHL_INT0, irq_value0
1202 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1203 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1204 & (~CHL_INT0_NOT_RDY_MSK));
1205 }
1206 }
1207 irq_msk &= ~(1 << phy_no);
1208 phy_no++;
1209 }
1210
1211 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1212
1213 return IRQ_HANDLED;
1214}
1215
31a9cfa6
JG		 1216static irqreturn_t cq_interrupt_v2_hw(int irq_no, void *p)
1217{
1218 struct hisi_sas_cq *cq = p;
1219 struct hisi_hba *hisi_hba = cq->hisi_hba;
1220 struct hisi_sas_slot *slot;
1221 struct hisi_sas_itct *itct;
1222 struct hisi_sas_complete_v2_hdr *complete_queue;
1223 u32 irq_value, rd_point, wr_point, dev_id;
1224 int queue = cq->id;
1225
1226 complete_queue = hisi_hba->complete_hdr[queue];
1227 irq_value = hisi_sas_read32(hisi_hba, OQ_INT_SRC);
1228
1229 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1230
1231 rd_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_RD_PTR +
1232 (0x14 * queue));
1233 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1234 (0x14 * queue));
1235
1236 while (rd_point != wr_point) {
1237 struct hisi_sas_complete_v2_hdr *complete_hdr;
1238 int iptt;
1239
1240 complete_hdr = &complete_queue[rd_point];
1241
1242 /* Check for NCQ completion */
1243 if (complete_hdr->act) {
1244 u32 act_tmp = complete_hdr->act;
1245 int ncq_tag_count = ffs(act_tmp);
1246
1247 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1248 CMPLT_HDR_DEV_ID_OFF;
1249 itct = &hisi_hba->itct[dev_id];
1250
1251 /* The NCQ tags are held in the itct header */
1252 while (ncq_tag_count) {
1253 __le64 *ncq_tag = &itct->qw4_15[0];
1254
1255 ncq_tag_count -= 1;
1256 iptt = (ncq_tag[ncq_tag_count / 5]
1257 >> (ncq_tag_count % 5) * 12) & 0xfff;
1258
1259 slot = &hisi_hba->slot_info[iptt];
1260 slot->cmplt_queue_slot = rd_point;
1261 slot->cmplt_queue = queue;
1262 slot_complete_v2_hw(hisi_hba, slot, 0);
1263
1264 act_tmp &= ~(1 << ncq_tag_count);
1265 ncq_tag_count = ffs(act_tmp);
1266 }
1267 } else {
1268 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1269 slot = &hisi_hba->slot_info[iptt];
1270 slot->cmplt_queue_slot = rd_point;
1271 slot->cmplt_queue = queue;
1272 slot_complete_v2_hw(hisi_hba, slot, 0);
1273 }
1274
1275 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1276 rd_point = 0;
1277 }
1278
1279 /* update rd_point */
1280 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1281 return IRQ_HANDLED;
1282}
1283
d43f9cdb
JG		 1284static irqreturn_t sata_int_v2_hw(int irq_no, void *p)
1285{
1286 struct hisi_sas_phy *phy = p;
1287 struct hisi_hba *hisi_hba = phy->hisi_hba;
1288 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1289 struct device *dev = &hisi_hba->pdev->dev;
1290 struct hisi_sas_initial_fis *initial_fis;
1291 struct dev_to_host_fis *fis;
1292 u32 ent_tmp, ent_msk, ent_int, port_id, link_rate, hard_phy_linkrate;
1293 irqreturn_t res = IRQ_HANDLED;
1294 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1295 int phy_no;
1296
1297 phy_no = sas_phy->id;
1298 initial_fis = &hisi_hba->initial_fis[phy_no];
1299 fis = &initial_fis->fis;
1300
1301 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK1);
1302 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk | 1 << phy_no);
1303
1304 ent_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC1);
1305 ent_tmp = ent_int;
1306 ent_int >>= ENT_INT_SRC1_D2H_FIS_CH1_OFF * (phy_no % 4);
1307 if ((ent_int & ENT_INT_SRC1_D2H_FIS_CH0_MSK) == 0) {
1308 dev_warn(dev, "sata int: phy%d did not receive FIS\n", phy_no);
1309 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1310 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1311 res = IRQ_NONE;
1312 goto end;
1313 }
1314
1315 if (unlikely(phy_no == 8)) {
1316 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
1317
1318 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
1319 PORT_STATE_PHY8_PORT_NUM_OFF;
1320 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
1321 PORT_STATE_PHY8_CONN_RATE_OFF;
1322 } else {
1323 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
1324 port_id = (port_id >> (4 * phy_no)) & 0xf;
1325 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
1326 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
1327 }
1328
1329 if (port_id == 0xf) {
1330 dev_err(dev, "sata int: phy%d invalid portid\n", phy_no);
1331 res = IRQ_NONE;
1332 goto end;
1333 }
1334
1335 sas_phy->linkrate = link_rate;
1336 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1337 HARD_PHY_LINKRATE);
1338 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1339 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1340
1341 sas_phy->oob_mode = SATA_OOB_MODE;
1342 /* Make up some unique SAS address */
1343 attached_sas_addr[0] = 0x50;
1344 attached_sas_addr[7] = phy_no;
1345 memcpy(sas_phy->attached_sas_addr, attached_sas_addr, SAS_ADDR_SIZE);
1346 memcpy(sas_phy->frame_rcvd, fis, sizeof(struct dev_to_host_fis));
1347 dev_info(dev, "sata int phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1348 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1349 phy->port_id = port_id;
1350 phy->phy_type |= PORT_TYPE_SATA;
1351 phy->phy_attached = 1;
1352 phy->identify.device_type = SAS_SATA_DEV;
1353 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1354 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1355 queue_work(hisi_hba->wq, &phy->phyup_ws);
1356
1357end:
1358 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, ent_tmp);
1359 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, ent_msk);
1360
1361 return res;
1362}
1363
7911e66f
JG		 1364static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
1365 int_phy_updown_v2_hw,
d3bf3d84 1366 int_chnl_int_v2_hw,
7911e66f
JG		 1367};
1368
1369/**
1370 * There is a limitation in the hip06 chipset that we need
1371 * to map in all mbigen interrupts, even if they are not used.
1372 */
1373static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
1374{
1375 struct platform_device *pdev = hisi_hba->pdev;
1376 struct device *dev = &pdev->dev;
1377 int i, irq, rc, irq_map[128];
1378
1379
1380 for (i = 0; i < 128; i++)
1381 irq_map[i] = platform_get_irq(pdev, i);
1382
1383 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
1384 int idx = i;
1385
1386 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
1387 if (!irq) {
1388 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1389 idx);
1390 return -ENOENT;
1391 }
1392
1393 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
1394 DRV_NAME " phy", hisi_hba);
1395 if (rc) {
1396 dev_err(dev, "irq init: could not request "
1397 "phy interrupt %d, rc=%d\n",
1398 irq, rc);
1399 return -ENOENT;
1400 }
1401 }
1402
d43f9cdb
JG		 1403 for (i = 0; i < hisi_hba->n_phy; i++) {
1404 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
1405 int idx = i + 72; /* First SATA interrupt is irq72 */
1406
1407 irq = irq_map[idx];
1408 if (!irq) {
1409 dev_err(dev, "irq init: fail map phy interrupt %d\n",
1410 idx);
1411 return -ENOENT;
1412 }
1413
1414 rc = devm_request_irq(dev, irq, sata_int_v2_hw, 0,
1415 DRV_NAME " sata", phy);
1416 if (rc) {
1417 dev_err(dev, "irq init: could not request "
1418 "sata interrupt %d, rc=%d\n",
1419 irq, rc);
1420 return -ENOENT;
1421 }
1422 }
31a9cfa6
JG		 1423
1424 for (i = 0; i < hisi_hba->queue_count; i++) {
1425 int idx = i + 96; /* First cq interrupt is irq96 */
1426
1427 irq = irq_map[idx];
1428 if (!irq) {
1429 dev_err(dev,
1430 "irq init: could not map cq interrupt %d\n",
1431 idx);
1432 return -ENOENT;
1433 }
1434 rc = devm_request_irq(dev, irq, cq_interrupt_v2_hw, 0,
1435 DRV_NAME " cq", &hisi_hba->cq[i]);
1436 if (rc) {
1437 dev_err(dev,
1438 "irq init: could not request cq interrupt %d, rc=%d\n",
1439 irq, rc);
1440 return -ENOENT;
1441 }
1442 }
1443
7911e66f
JG		 1444 return 0;
1445}
1446
94eac9e1
JG		 1447static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
1448{
1449 int rc;
1450
1451 rc = hw_init_v2_hw(hisi_hba);
1452 if (rc)
1453 return rc;
1454
7911e66f
JG		 1455 rc = interrupt_init_v2_hw(hisi_hba);
1456 if (rc)
1457 return rc;
1458
29a20428
JG		 1459 phys_init_v2_hw(hisi_hba);
1460
94eac9e1
JG		 1461 return 0;
1462}
1463
3417ba8a 1464static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 1465 .hw_init = hisi_sas_v2_init,
7911e66f 1466 .sl_notify = sl_notify_v2_hw,
5473c060 1467 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
c2d89392 1468 .prep_smp = prep_smp_v2_hw,
8c36e31d
JG		 1469 .prep_ssp = prep_ssp_v2_hw,
1470 .get_free_slot = get_free_slot_v2_hw,
1471 .start_delivery = start_delivery_v2_hw,
31a9cfa6 1472 .slot_complete = slot_complete_v2_hw,
94eac9e1
JG		 1473 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
1474 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a
JG		 1475};
1476
1477static int hisi_sas_v2_probe(struct platform_device *pdev)
1478{
1479 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
1480}
1481
1482static int hisi_sas_v2_remove(struct platform_device *pdev)
1483{
1484 return hisi_sas_remove(pdev);
1485}
1486
1487static const struct of_device_id sas_v2_of_match[] = {
1488 { .compatible = "hisilicon,hip06-sas-v2",},
1489 {},
1490};
1491MODULE_DEVICE_TABLE(of, sas_v2_of_match);
1492
1493static struct platform_driver hisi_sas_v2_driver = {
1494 .probe = hisi_sas_v2_probe,
1495 .remove = hisi_sas_v2_remove,
1496 .driver = {
1497 .name = DRV_NAME,
1498 .of_match_table = sas_v2_of_match,
1499 },
1500};
1501
1502module_platform_driver(hisi_sas_v2_driver);
1503
1504MODULE_LICENSE("GPL");
1505MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1506MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
1507MODULE_ALIAS("platform:" DRV_NAME);
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