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hisi_sas: add v2 channel interrupt handler
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
CommitLineData
3417ba8a
JG		 1/*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v2_hw"
14
45c901b8
JG		 15/* global registers need init*/
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define IO_BROKEN_MSG_ADDR_LO 0x18
22#define IO_BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PORT_STATE_PHY8_PORT_NUM_OFF 16
28#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29#define PORT_STATE_PHY8_CONN_RATE_OFF 20
30#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31#define PHY_CONN_RATE 0x30
32#define HGC_TRANS_TASK_CNT_LIMIT 0x38
33#define AXI_AHB_CLK_CFG 0x3c
34#define ITCT_CLR 0x44
35#define ITCT_CLR_EN_OFF 16
36#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37#define ITCT_DEV_OFF 0
38#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39#define AXI_USER1 0x48
40#define AXI_USER2 0x4c
41#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47#define HGC_GET_ITV_TIME 0x90
48#define DEVICE_MSG_WORK_MODE 0x94
49#define OPENA_WT_CONTI_TIME 0x9c
50#define I_T_NEXUS_LOSS_TIME 0xa0
51#define MAX_CON_TIME_LIMIT_TIME 0xa4
52#define BUS_INACTIVE_LIMIT_TIME 0xa8
53#define REJECT_TO_OPEN_LIMIT_TIME 0xac
54#define CFG_AGING_TIME 0xbc
55#define HGC_DFX_CFG2 0xc0
56#define HGC_IOMB_PROC1_STATUS 0x104
57#define CFG_1US_TIMER_TRSH 0xcc
58#define HGC_INVLD_DQE_INFO 0x148
59#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62#define INT_COAL_EN 0x19c
63#define OQ_INT_COAL_TIME 0x1a0
64#define OQ_INT_COAL_CNT 0x1a4
65#define ENT_INT_COAL_TIME 0x1a8
66#define ENT_INT_COAL_CNT 0x1ac
67#define OQ_INT_SRC 0x1b0
68#define OQ_INT_SRC_MSK 0x1b4
69#define ENT_INT_SRC1 0x1b8
70#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74#define ENT_INT_SRC2 0x1bc
75#define ENT_INT_SRC3 0x1c0
76#define ENT_INT_SRC3_ITC_INT_OFF 15
77#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83#define SAS_ECC_INTR_MSK 0x1ec
84#define HGC_ERR_STAT_EN 0x238
85#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87#define DLVRY_Q_0_DEPTH 0x268
88#define DLVRY_Q_0_WR_PTR 0x26c
89#define DLVRY_Q_0_RD_PTR 0x270
90#define HYPER_STREAM_ID_EN_CFG 0xc80
91#define OQ0_INT_SRC_MSK 0xc90
92#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94#define COMPL_Q_0_DEPTH 0x4e8
95#define COMPL_Q_0_WR_PTR 0x4ec
96#define COMPL_Q_0_RD_PTR 0x4f0
97
98/* phy registers need init */
99#define PORT_BASE (0x2000)
100
101#define PHY_CFG (PORT_BASE + 0x0)
102#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103#define PHY_CFG_ENA_OFF 0
104#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105#define PHY_CFG_DC_OPT_OFF 2
106#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108#define PROG_PHY_LINK_RATE_MAX_OFF 0
109#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110#define PHY_CTRL (PORT_BASE + 0x14)
111#define PHY_CTRL_RESET_OFF 0
112#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114#define SL_CFG (PORT_BASE + 0x84)
115#define PHY_PCN (PORT_BASE + 0x44)
116#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136#define CHL_INT0 (PORT_BASE + 0x1b4)
137#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143#define CHL_INT0_NOT_RDY_OFF 4
144#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145#define CHL_INT0_PHY_RDY_OFF 5
146#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147#define CHL_INT1 (PORT_BASE + 0x1b8)
148#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152#define CHL_INT2 (PORT_BASE + 0x1bc)
153#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164#define DMA_TX_STATUS_BUSY_OFF 0
165#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167#define DMA_RX_STATUS_BUSY_OFF 0
168#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170#define AXI_CFG (0x5100)
171#define AM_CFG_MAX_TRANS (0x5010)
172#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174/* HW dma structures */
175/* Delivery queue header */
176/* dw0 */
177#define CMD_HDR_RESP_REPORT_OFF 5
178#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179#define CMD_HDR_TLR_CTRL_OFF 6
180#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181#define CMD_HDR_PORT_OFF 18
182#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183#define CMD_HDR_PRIORITY_OFF 27
184#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185#define CMD_HDR_CMD_OFF 29
186#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187/* dw1 */
188#define CMD_HDR_DIR_OFF 5
189#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190#define CMD_HDR_RESET_OFF 7
191#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192#define CMD_HDR_VDTL_OFF 10
193#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194#define CMD_HDR_FRAME_TYPE_OFF 11
195#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196#define CMD_HDR_DEV_ID_OFF 16
197#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198/* dw2 */
199#define CMD_HDR_CFL_OFF 0
200#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201#define CMD_HDR_NCQ_TAG_OFF 10
202#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203#define CMD_HDR_MRFL_OFF 15
204#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205#define CMD_HDR_SG_MOD_OFF 24
206#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207#define CMD_HDR_FIRST_BURST_OFF 26
208#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209/* dw3 */
210#define CMD_HDR_IPTT_OFF 0
211#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212/* dw6 */
213#define CMD_HDR_DIF_SGL_LEN_OFF 0
214#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215#define CMD_HDR_DATA_SGL_LEN_OFF 16
216#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218/* Completion header */
219/* dw0 */
220#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222#define CMPLT_HDR_ERX_OFF 12
223#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224/* dw1 */
225#define CMPLT_HDR_IPTT_OFF 0
226#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227#define CMPLT_HDR_DEV_ID_OFF 16
228#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230/* ITCT header */
231/* qw0 */
232#define ITCT_HDR_DEV_TYPE_OFF 0
233#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234#define ITCT_HDR_VALID_OFF 2
235#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236#define ITCT_HDR_MCR_OFF 5
237#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238#define ITCT_HDR_VLN_OFF 9
239#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240#define ITCT_HDR_PORT_ID_OFF 28
241#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242/* qw2 */
243#define ITCT_HDR_INLT_OFF 0
244#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245#define ITCT_HDR_BITLT_OFF 16
246#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247#define ITCT_HDR_MCTLT_OFF 32
248#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249#define ITCT_HDR_RTOLT_OFF 48
250#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1
JG		 252struct hisi_sas_complete_v2_hdr {
253 __le32 dw0;
254 __le32 dw1;
255 __le32 act;
256 __le32 dw3;
257};
258
7911e66f
JG		 259enum {
260 HISI_SAS_PHY_PHY_UPDOWN,
d3bf3d84 261 HISI_SAS_PHY_CHNL_INT,
7911e66f
JG		 262 HISI_SAS_PHY_INT_NR
263};
264
94eac9e1
JG		 265#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
266
267static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
268{
269 void __iomem *regs = hisi_hba->regs + off;
270
271 return readl(regs);
272}
273
274static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
275{
276 void __iomem *regs = hisi_hba->regs + off;
277
278 writel(val, regs);
279}
280
281static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
282 u32 off, u32 val)
283{
284 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
285
286 writel(val, regs);
287}
288
289static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
290 int phy_no, u32 off)
291{
292 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
293
294 return readl(regs);
295}
296
29a20428
JG		 297static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
298{
299 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
300
301 cfg &= ~PHY_CFG_DC_OPT_MSK;
302 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
303 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
304}
305
806bb768
JG		 306static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
307{
308 struct sas_identify_frame identify_frame;
309 u32 *identify_buffer;
310
311 memset(&identify_frame, 0, sizeof(identify_frame));
312 identify_frame.dev_type = SAS_END_DEVICE;
313 identify_frame.frame_type = 0;
314 identify_frame._un1 = 1;
315 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
316 identify_frame.target_bits = SAS_PROTOCOL_NONE;
317 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
318 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
319 identify_frame.phy_id = phy_no;
320 identify_buffer = (u32 *)(&identify_frame);
321
322 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
323 __swab32(identify_buffer[0]));
324 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
325 identify_buffer[2]);
326 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
327 identify_buffer[1]);
328 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
329 identify_buffer[4]);
330 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
331 identify_buffer[3]);
332 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
333 __swab32(identify_buffer[5]));
334}
335
336static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
337{
338 int i;
339
340 for (i = 0; i < hisi_hba->n_phy; i++)
341 config_id_frame_v2_hw(hisi_hba, i);
342}
343
94eac9e1
JG		 344static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
345{
346 int i, reset_val;
347 u32 val;
348 unsigned long end_time;
349 struct device *dev = &hisi_hba->pdev->dev;
350
351 /* The mask needs to be set depending on the number of phys */
352 if (hisi_hba->n_phy == 9)
353 reset_val = 0x1fffff;
354 else
355 reset_val = 0x7ffff;
356
357 /* Disable all of the DQ */
358 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
359 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
360
361 /* Disable all of the PHYs */
362 for (i = 0; i < hisi_hba->n_phy; i++) {
363 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
364
365 phy_cfg &= ~PHY_CTRL_RESET_MSK;
366 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
367 }
368 udelay(50);
369
370 /* Ensure DMA tx & rx idle */
371 for (i = 0; i < hisi_hba->n_phy; i++) {
372 u32 dma_tx_status, dma_rx_status;
373
374 end_time = jiffies + msecs_to_jiffies(1000);
375
376 while (1) {
377 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
378 DMA_TX_STATUS);
379 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
380 DMA_RX_STATUS);
381
382 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
383 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
384 break;
385
386 msleep(20);
387 if (time_after(jiffies, end_time))
388 return -EIO;
389 }
390 }
391
392 /* Ensure axi bus idle */
393 end_time = jiffies + msecs_to_jiffies(1000);
394 while (1) {
395 u32 axi_status =
396 hisi_sas_read32(hisi_hba, AXI_CFG);
397
398 if (axi_status == 0)
399 break;
400
401 msleep(20);
402 if (time_after(jiffies, end_time))
403 return -EIO;
404 }
405
406 /* reset and disable clock*/
407 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
408 reset_val);
409 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
410 reset_val);
411 msleep(1);
412 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
413 if (reset_val != (val & reset_val)) {
414 dev_err(dev, "SAS reset fail.\n");
415 return -EIO;
416 }
417
418 /* De-reset and enable clock*/
419 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
420 reset_val);
421 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
422 reset_val);
423 msleep(1);
424 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
425 &val);
426 if (val & reset_val) {
427 dev_err(dev, "SAS de-reset fail.\n");
428 return -EIO;
429 }
430
431 return 0;
432}
433
434static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
435{
436 struct device *dev = &hisi_hba->pdev->dev;
437 struct device_node *np = dev->of_node;
438 int i;
439
440 /* Global registers init */
441
442 /* Deal with am-max-transmissions quirk */
443 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
444 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
445 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
446 0x2020);
447 } /* Else, use defaults -> do nothing */
448
449 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
450 (u32)((1ULL << hisi_hba->queue_count) - 1));
451 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
452 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
453 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
454 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
455 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
456 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
457 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
458 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
459 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
460 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
461 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
462 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
463 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
464 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
465 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
466 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
467 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
468 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
469 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
470 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
471 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
472 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
473 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
474 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
475 for (i = 0; i < hisi_hba->queue_count; i++)
476 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
477
478 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
479 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
480
481 for (i = 0; i < hisi_hba->n_phy; i++) {
482 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
483 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
484 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
485 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
486 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
487 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
488 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
489 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
490 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
491 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
492 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
493 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
494 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
495 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
496 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
497 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
498 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
499 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
500 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
501 }
502
503 for (i = 0; i < hisi_hba->queue_count; i++) {
504 /* Delivery queue */
505 hisi_sas_write32(hisi_hba,
506 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
507 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
508
509 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
510 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
511
512 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
513 HISI_SAS_QUEUE_SLOTS);
514
515 /* Completion queue */
516 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
517 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
518
519 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
520 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
521
522 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
523 HISI_SAS_QUEUE_SLOTS);
524 }
525
526 /* itct */
527 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
528 lower_32_bits(hisi_hba->itct_dma));
529
530 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
531 upper_32_bits(hisi_hba->itct_dma));
532
533 /* iost */
534 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
535 lower_32_bits(hisi_hba->iost_dma));
536
537 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
538 upper_32_bits(hisi_hba->iost_dma));
539
540 /* breakpoint */
541 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
542 lower_32_bits(hisi_hba->breakpoint_dma));
543
544 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
545 upper_32_bits(hisi_hba->breakpoint_dma));
546
547 /* SATA broken msg */
548 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
549 lower_32_bits(hisi_hba->sata_breakpoint_dma));
550
551 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
552 upper_32_bits(hisi_hba->sata_breakpoint_dma));
553
554 /* SATA initial fis */
555 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
556 lower_32_bits(hisi_hba->initial_fis_dma));
557
558 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
559 upper_32_bits(hisi_hba->initial_fis_dma));
560}
561
562static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
563{
564 struct device *dev = &hisi_hba->pdev->dev;
565 int rc;
566
567 rc = reset_hw_v2_hw(hisi_hba);
568 if (rc) {
569 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
570 return rc;
571 }
572
573 msleep(100);
574 init_reg_v2_hw(hisi_hba);
575
806bb768
JG		 576 init_id_frame_v2_hw(hisi_hba);
577
94eac9e1
JG		 578 return 0;
579}
580
29a20428
JG		 581static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
582{
583 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
584
585 cfg |= PHY_CFG_ENA_MSK;
586 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
587}
588
589static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
590{
591 config_id_frame_v2_hw(hisi_hba, phy_no);
592 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
593 enable_phy_v2_hw(hisi_hba, phy_no);
594}
595
596static void start_phys_v2_hw(unsigned long data)
597{
598 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
599 int i;
600
601 for (i = 0; i < hisi_hba->n_phy; i++)
602 start_phy_v2_hw(hisi_hba, i);
603}
604
605static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
606{
607 int i;
608 struct timer_list *timer = &hisi_hba->timer;
609
610 for (i = 0; i < hisi_hba->n_phy; i++) {
611 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
612 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
613 }
614
615 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
616 mod_timer(timer, jiffies + HZ);
617}
618
7911e66f
JG		 619static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
620{
621 u32 sl_control;
622
623 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
624 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
625 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
626 msleep(1);
627 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
628 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
629 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
630}
631
5473c060
JG		 632static int get_wideport_bitmap_v2_hw(struct hisi_hba *hisi_hba, int port_id)
633{
634 int i, bitmap = 0;
635 u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
636 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
637
638 for (i = 0; i < (hisi_hba->n_phy < 9 ? hisi_hba->n_phy : 8); i++)
639 if (phy_state & 1 << i)
640 if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id)
641 bitmap |= 1 << i;
642
643 if (hisi_hba->n_phy == 9) {
644 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
645
646 if (phy_state & 1 << 8)
647 if (((port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
648 PORT_STATE_PHY8_PORT_NUM_OFF) == port_id)
649 bitmap |= 1 << 9;
650 }
651
652 return bitmap;
653}
654
7911e66f
JG		 655static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
656{
657 int i, res = 0;
658 u32 context, port_id, link_rate, hard_phy_linkrate;
659 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
660 struct asd_sas_phy *sas_phy = &phy->sas_phy;
661 struct device *dev = &hisi_hba->pdev->dev;
662 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
663 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
664
665 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
666
667 /* Check for SATA dev */
668 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
669 if (context & (1 << phy_no))
670 goto end;
671
672 if (phy_no == 8) {
673 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
674
675 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
676 PORT_STATE_PHY8_PORT_NUM_OFF;
677 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
678 PORT_STATE_PHY8_CONN_RATE_OFF;
679 } else {
680 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
681 port_id = (port_id >> (4 * phy_no)) & 0xf;
682 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
683 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
684 }
685
686 if (port_id == 0xf) {
687 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
688 res = IRQ_NONE;
689 goto end;
690 }
691
692 for (i = 0; i < 6; i++) {
693 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
694 RX_IDAF_DWORD0 + (i * 4));
695 frame_rcvd[i] = __swab32(idaf);
696 }
697
698 /* Get the linkrates */
699 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
700 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
701 sas_phy->linkrate = link_rate;
702 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
703 HARD_PHY_LINKRATE);
704 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
705 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
706
707 sas_phy->oob_mode = SAS_OOB_MODE;
708 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
709 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
710 phy->port_id = port_id;
711 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
712 phy->phy_type |= PORT_TYPE_SAS;
713 phy->phy_attached = 1;
714 phy->identify.device_type = id->dev_type;
715 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
716 if (phy->identify.device_type == SAS_END_DEVICE)
717 phy->identify.target_port_protocols =
718 SAS_PROTOCOL_SSP;
719 else if (phy->identify.device_type != SAS_PHY_UNUSED)
720 phy->identify.target_port_protocols =
721 SAS_PROTOCOL_SMP;
722 queue_work(hisi_hba->wq, &phy->phyup_ws);
723
724end:
725 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
726 CHL_INT0_SL_PHY_ENABLE_MSK);
727 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
728
729 return res;
730}
731
5473c060
JG		 732static int phy_down_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
733{
734 int res = 0;
735 u32 phy_cfg, phy_state;
736
737 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
738
739 phy_cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
740
741 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
742
743 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
744
745 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
746 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
747
748 return res;
749}
750
7911e66f
JG		 751static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
752{
753 struct hisi_hba *hisi_hba = p;
754 u32 irq_msk;
755 int phy_no = 0;
756 irqreturn_t res = IRQ_HANDLED;
757
758 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
759 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
760 while (irq_msk) {
761 if (irq_msk & 1) {
762 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
763 CHL_INT0);
764
765 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
766 /* phy up */
767 if (phy_up_v2_hw(phy_no, hisi_hba)) {
768 res = IRQ_NONE;
769 goto end;
770 }
771
5473c060
JG		 772 if (irq_value & CHL_INT0_NOT_RDY_MSK)
773 /* phy down */
774 if (phy_down_v2_hw(phy_no, hisi_hba)) {
775 res = IRQ_NONE;
776 goto end;
777 }
7911e66f
JG		 778 }
779 irq_msk >>= 1;
780 phy_no++;
781 }
782
783end:
784 return res;
785}
786
d3bf3d84
JG		 787static void phy_bcast_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
788{
789 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
790 struct asd_sas_phy *sas_phy = &phy->sas_phy;
791 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
792 unsigned long flags;
793
794 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
795
796 spin_lock_irqsave(&hisi_hba->lock, flags);
797 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
798 spin_unlock_irqrestore(&hisi_hba->lock, flags);
799
800 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
801 CHL_INT0_SL_RX_BCST_ACK_MSK);
802 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
803}
804
805static irqreturn_t int_chnl_int_v2_hw(int irq_no, void *p)
806{
807 struct hisi_hba *hisi_hba = p;
808 struct device *dev = &hisi_hba->pdev->dev;
809 u32 ent_msk, ent_tmp, irq_msk;
810 int phy_no = 0;
811
812 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
813 ent_tmp = ent_msk;
814 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
815 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
816
817 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO) >>
818 HGC_INVLD_DQE_INFO_FB_CH3_OFF) & 0x1ff;
819
820 while (irq_msk) {
821 if (irq_msk & (1 << phy_no)) {
822 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
823 CHL_INT0);
824 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
825 CHL_INT1);
826 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
827 CHL_INT2);
828
829 if (irq_value1) {
830 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
831 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
832 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
833 dev_name(dev), irq_value1);
834
835 hisi_sas_phy_write32(hisi_hba, phy_no,
836 CHL_INT1, irq_value1);
837 }
838
839 if (irq_value2)
840 hisi_sas_phy_write32(hisi_hba, phy_no,
841 CHL_INT2, irq_value2);
842
843
844 if (irq_value0) {
845 if (irq_value0 & CHL_INT0_SL_RX_BCST_ACK_MSK)
846 phy_bcast_v2_hw(phy_no, hisi_hba);
847
848 hisi_sas_phy_write32(hisi_hba, phy_no,
849 CHL_INT0, irq_value0
850 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
851 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
852 & (~CHL_INT0_NOT_RDY_MSK));
853 }
854 }
855 irq_msk &= ~(1 << phy_no);
856 phy_no++;
857 }
858
859 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
860
861 return IRQ_HANDLED;
862}
863
7911e66f
JG		 864static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
865 int_phy_updown_v2_hw,
d3bf3d84 866 int_chnl_int_v2_hw,
7911e66f
JG		 867};
868
869/**
870 * There is a limitation in the hip06 chipset that we need
871 * to map in all mbigen interrupts, even if they are not used.
872 */
873static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
874{
875 struct platform_device *pdev = hisi_hba->pdev;
876 struct device *dev = &pdev->dev;
877 int i, irq, rc, irq_map[128];
878
879
880 for (i = 0; i < 128; i++)
881 irq_map[i] = platform_get_irq(pdev, i);
882
883 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
884 int idx = i;
885
886 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
887 if (!irq) {
888 dev_err(dev, "irq init: fail map phy interrupt %d\n",
889 idx);
890 return -ENOENT;
891 }
892
893 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
894 DRV_NAME " phy", hisi_hba);
895 if (rc) {
896 dev_err(dev, "irq init: could not request "
897 "phy interrupt %d, rc=%d\n",
898 irq, rc);
899 return -ENOENT;
900 }
901 }
902
903 return 0;
904}
905
94eac9e1
JG		 906static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
907{
908 int rc;
909
910 rc = hw_init_v2_hw(hisi_hba);
911 if (rc)
912 return rc;
913
7911e66f
JG		 914 rc = interrupt_init_v2_hw(hisi_hba);
915 if (rc)
916 return rc;
917
29a20428
JG		 918 phys_init_v2_hw(hisi_hba);
919
94eac9e1
JG		 920 return 0;
921}
922
3417ba8a 923static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 924 .hw_init = hisi_sas_v2_init,
7911e66f 925 .sl_notify = sl_notify_v2_hw,
5473c060 926 .get_wideport_bitmap = get_wideport_bitmap_v2_hw,
94eac9e1
JG		 927 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
928 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a
JG		 929};
930
931static int hisi_sas_v2_probe(struct platform_device *pdev)
932{
933 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
934}
935
936static int hisi_sas_v2_remove(struct platform_device *pdev)
937{
938 return hisi_sas_remove(pdev);
939}
940
941static const struct of_device_id sas_v2_of_match[] = {
942 { .compatible = "hisilicon,hip06-sas-v2",},
943 {},
944};
945MODULE_DEVICE_TABLE(of, sas_v2_of_match);
946
947static struct platform_driver hisi_sas_v2_driver = {
948 .probe = hisi_sas_v2_probe,
949 .remove = hisi_sas_v2_remove,
950 .driver = {
951 .name = DRV_NAME,
952 .of_match_table = sas_v2_of_match,
953 },
954};
955
956module_platform_driver(hisi_sas_v2_driver);
957
958MODULE_LICENSE("GPL");
959MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
960MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
961MODULE_ALIAS("platform:" DRV_NAME);
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