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92f61e3b JG |
1 | /* |
2 | * Copyright (c) 2017 Hisilicon Limited. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include "hisi_sas.h" | |
12 | #define DRV_NAME "hisi_sas_v3_hw" | |
13 | ||
c94d8ca2 XC |
14 | /* global registers need init*/ |
15 | #define DLVRY_QUEUE_ENABLE 0x0 | |
16 | #define IOST_BASE_ADDR_LO 0x8 | |
17 | #define IOST_BASE_ADDR_HI 0xc | |
18 | #define ITCT_BASE_ADDR_LO 0x10 | |
19 | #define ITCT_BASE_ADDR_HI 0x14 | |
20 | #define IO_BROKEN_MSG_ADDR_LO 0x18 | |
21 | #define IO_BROKEN_MSG_ADDR_HI 0x1c | |
3975f605 XC |
22 | #define PHY_CONTEXT 0x20 |
23 | #define PHY_STATE 0x24 | |
24 | #define PHY_PORT_NUM_MA 0x28 | |
25 | #define PHY_CONN_RATE 0x30 | |
182e7222 XC |
26 | #define ITCT_CLR 0x44 |
27 | #define ITCT_CLR_EN_OFF 16 | |
28 | #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) | |
29 | #define ITCT_DEV_OFF 0 | |
30 | #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) | |
c94d8ca2 XC |
31 | #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 |
32 | #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c | |
33 | #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 | |
34 | #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 | |
35 | #define CFG_MAX_TAG 0x68 | |
36 | #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 | |
37 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 | |
38 | #define HGC_GET_ITV_TIME 0x90 | |
39 | #define DEVICE_MSG_WORK_MODE 0x94 | |
40 | #define OPENA_WT_CONTI_TIME 0x9c | |
41 | #define I_T_NEXUS_LOSS_TIME 0xa0 | |
42 | #define MAX_CON_TIME_LIMIT_TIME 0xa4 | |
43 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 | |
44 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac | |
45 | #define CFG_AGING_TIME 0xbc | |
46 | #define HGC_DFX_CFG2 0xc0 | |
47 | #define CFG_ABT_SET_QUERY_IPTT 0xd4 | |
48 | #define CFG_SET_ABORTED_IPTT_OFF 0 | |
49 | #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) | |
d30ff263 XC |
50 | #define CFG_SET_ABORTED_EN_OFF 12 |
51 | #define CFG_ABT_SET_IPTT_DONE 0xd8 | |
52 | #define CFG_ABT_SET_IPTT_DONE_OFF 0 | |
53 | #define HGC_IOMB_PROC1_STATUS 0x104 | |
3975f605 | 54 | #define CHNL_INT_STATUS 0x148 |
fa231408 XT |
55 | #define HGC_AXI_FIFO_ERR_INFO 0x154 |
56 | #define AXI_ERR_INFO_OFF 0 | |
57 | #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) | |
58 | #define FIFO_ERR_INFO_OFF 8 | |
59 | #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) | |
c94d8ca2 XC |
60 | #define INT_COAL_EN 0x19c |
61 | #define OQ_INT_COAL_TIME 0x1a0 | |
62 | #define OQ_INT_COAL_CNT 0x1a4 | |
63 | #define ENT_INT_COAL_TIME 0x1a8 | |
64 | #define ENT_INT_COAL_CNT 0x1ac | |
65 | #define OQ_INT_SRC 0x1b0 | |
66 | #define OQ_INT_SRC_MSK 0x1b4 | |
67 | #define ENT_INT_SRC1 0x1b8 | |
68 | #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 | |
69 | #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) | |
70 | #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 | |
71 | #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) | |
72 | #define ENT_INT_SRC2 0x1bc | |
73 | #define ENT_INT_SRC3 0x1c0 | |
74 | #define ENT_INT_SRC3_WP_DEPTH_OFF 8 | |
75 | #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 | |
76 | #define ENT_INT_SRC3_RP_DEPTH_OFF 10 | |
77 | #define ENT_INT_SRC3_AXI_OFF 11 | |
78 | #define ENT_INT_SRC3_FIFO_OFF 12 | |
79 | #define ENT_INT_SRC3_LM_OFF 14 | |
80 | #define ENT_INT_SRC3_ITC_INT_OFF 15 | |
81 | #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) | |
82 | #define ENT_INT_SRC3_ABT_OFF 16 | |
83 | #define ENT_INT_SRC_MSK1 0x1c4 | |
84 | #define ENT_INT_SRC_MSK2 0x1c8 | |
85 | #define ENT_INT_SRC_MSK3 0x1cc | |
3975f605 | 86 | #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 |
c94d8ca2 XC |
87 | #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 |
88 | #define CHNL_ENT_INT_MSK 0x1d4 | |
89 | #define HGC_COM_INT_MSK 0x1d8 | |
3975f605 | 90 | #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) |
c94d8ca2 XC |
91 | #define SAS_ECC_INTR 0x1e8 |
92 | #define SAS_ECC_INTR_MSK 0x1ec | |
93 | #define HGC_ERR_STAT_EN 0x238 | |
1a7068b3 | 94 | #define CQE_SEND_CNT 0x248 |
c94d8ca2 XC |
95 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 |
96 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 | |
97 | #define DLVRY_Q_0_DEPTH 0x268 | |
98 | #define DLVRY_Q_0_WR_PTR 0x26c | |
99 | #define DLVRY_Q_0_RD_PTR 0x270 | |
100 | #define HYPER_STREAM_ID_EN_CFG 0xc80 | |
101 | #define OQ0_INT_SRC_MSK 0xc90 | |
102 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 | |
103 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 | |
104 | #define COMPL_Q_0_DEPTH 0x4e8 | |
105 | #define COMPL_Q_0_WR_PTR 0x4ec | |
106 | #define COMPL_Q_0_RD_PTR 0x4f0 | |
107 | #define AWQOS_AWCACHE_CFG 0xc84 | |
108 | #define ARQOS_ARCACHE_CFG 0xc88 | |
70230be3 | 109 | #define HILINK_ERR_DFX 0xe04 |
e24fe507 XT |
110 | #define SAS_GPIO_CFG_0 0x1000 |
111 | #define SAS_GPIO_CFG_1 0x1004 | |
112 | #define SAS_GPIO_TX_0_1 0x1040 | |
113 | #define SAS_CFG_DRIVE_VLD 0x1070 | |
c94d8ca2 XC |
114 | |
115 | /* phy registers requiring init */ | |
116 | #define PORT_BASE (0x2000) | |
3975f605 XC |
117 | #define PHY_CFG (PORT_BASE + 0x0) |
118 | #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) | |
119 | #define PHY_CFG_ENA_OFF 0 | |
120 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) | |
121 | #define PHY_CFG_DC_OPT_OFF 2 | |
122 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) | |
17d59a57 XT |
123 | #define PHY_CFG_PHY_RST_OFF 3 |
124 | #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) | |
c94d8ca2 XC |
125 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) |
126 | #define PHY_CTRL (PORT_BASE + 0x14) | |
127 | #define PHY_CTRL_RESET_OFF 0 | |
128 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | |
129 | #define SL_CFG (PORT_BASE + 0x84) | |
3975f605 XC |
130 | #define SL_CONTROL (PORT_BASE + 0x94) |
131 | #define SL_CONTROL_NOTIFY_EN_OFF 0 | |
132 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) | |
133 | #define SL_CTA_OFF 17 | |
134 | #define SL_CTA_MSK (0x1 << SL_CTA_OFF) | |
45651175 XT |
135 | #define RX_PRIMS_STATUS (PORT_BASE + 0x98) |
136 | #define RX_BCAST_CHG_OFF 1 | |
137 | #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) | |
3975f605 XC |
138 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) |
139 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) | |
140 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) | |
141 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) | |
142 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) | |
143 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) | |
144 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) | |
145 | #define TXID_AUTO (PORT_BASE + 0xb8) | |
146 | #define CT3_OFF 1 | |
147 | #define CT3_MSK (0x1 << CT3_OFF) | |
402cd9f0 XC |
148 | #define TX_HARDRST_OFF 2 |
149 | #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) | |
3975f605 | 150 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) |
c94d8ca2 | 151 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) |
81036731 | 152 | #define STP_LINK_TIMER (PORT_BASE + 0x120) |
066312f6 | 153 | #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) |
d40bfb0d | 154 | #define CON_CFG_DRIVER (PORT_BASE + 0x130) |
c94d8ca2 XC |
155 | #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) |
156 | #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) | |
157 | #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) | |
158 | #define CHL_INT0 (PORT_BASE + 0x1b4) | |
159 | #define CHL_INT0_HOTPLUG_TOUT_OFF 0 | |
160 | #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) | |
161 | #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 | |
162 | #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) | |
163 | #define CHL_INT0_SL_PHY_ENABLE_OFF 2 | |
164 | #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) | |
165 | #define CHL_INT0_NOT_RDY_OFF 4 | |
166 | #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) | |
167 | #define CHL_INT0_PHY_RDY_OFF 5 | |
168 | #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) | |
169 | #define CHL_INT1 (PORT_BASE + 0x1b8) | |
170 | #define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15 | |
171 | #define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF) | |
172 | #define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17 | |
173 | #define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF) | |
4a6125c5 XT |
174 | #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 |
175 | #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 | |
176 | #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 | |
177 | #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 | |
c94d8ca2 | 178 | #define CHL_INT2 (PORT_BASE + 0x1bc) |
066312f6 | 179 | #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 |
70230be3 | 180 | #define CHL_INT2_RX_INVLD_DW_OFF 30 |
066312f6 | 181 | #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 |
c94d8ca2 XC |
182 | #define CHL_INT0_MSK (PORT_BASE + 0x1c0) |
183 | #define CHL_INT1_MSK (PORT_BASE + 0x1c4) | |
184 | #define CHL_INT2_MSK (PORT_BASE + 0x1c8) | |
185 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) | |
2b9174ae | 186 | #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) |
c94d8ca2 XC |
187 | #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) |
188 | #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) | |
189 | #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) | |
190 | #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) | |
191 | #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) | |
192 | #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) | |
a25d0d3d XC |
193 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) |
194 | #define DMA_TX_STATUS_BUSY_OFF 0 | |
195 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) | |
196 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) | |
197 | #define DMA_RX_STATUS_BUSY_OFF 0 | |
198 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) | |
2b9174ae XT |
199 | |
200 | #define COARSETUNE_TIME (PORT_BASE + 0x304) | |
ffc8f149 XT |
201 | #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) |
202 | #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) | |
203 | #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) | |
204 | #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) | |
a25d0d3d | 205 | |
a25d0d3d XC |
206 | #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ |
207 | #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) | |
208 | #error Max ITCT exceeded | |
209 | #endif | |
210 | ||
211 | #define AXI_MASTER_CFG_BASE (0x5000) | |
212 | #define AM_CTRL_GLOBAL (0x0) | |
1d51757d XT |
213 | #define AM_CTRL_SHUTDOWN_REQ_OFF 0 |
214 | #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) | |
a25d0d3d XC |
215 | #define AM_CURR_TRANS_RETURN (0x150) |
216 | ||
217 | #define AM_CFG_MAX_TRANS (0x5010) | |
218 | #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) | |
219 | #define AXI_CFG (0x5100) | |
220 | #define AM_ROB_ECC_ERR_ADDR (0x510c) | |
221 | #define AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF 0 | |
222 | #define AM_ROB_ECC_ONEBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_ONEBIT_ERR_ADDR_OFF) | |
223 | #define AM_ROB_ECC_MULBIT_ERR_ADDR_OFF 8 | |
224 | #define AM_ROB_ECC_MULBIT_ERR_ADDR_MSK (0xff << AM_ROB_ECC_MULBIT_ERR_ADDR_OFF) | |
c94d8ca2 | 225 | |
56b72168 XT |
226 | /* RAS registers need init */ |
227 | #define RAS_BASE (0x6000) | |
228 | #define SAS_RAS_INTR0 (RAS_BASE) | |
229 | #define SAS_RAS_INTR1 (RAS_BASE + 0x04) | |
230 | #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) | |
231 | #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) | |
c13c7ac5 XT |
232 | #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) |
233 | #define SAS_RAS_INTR2 (RAS_BASE + 0x20) | |
234 | #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) | |
56b72168 | 235 | |
a2204723 XC |
236 | /* HW dma structures */ |
237 | /* Delivery queue header */ | |
238 | /* dw0 */ | |
4de0ca69 XC |
239 | #define CMD_HDR_ABORT_FLAG_OFF 0 |
240 | #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) | |
241 | #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 | |
242 | #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
a2204723 XC |
243 | #define CMD_HDR_RESP_REPORT_OFF 5 |
244 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) | |
245 | #define CMD_HDR_TLR_CTRL_OFF 6 | |
246 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) | |
247 | #define CMD_HDR_PORT_OFF 18 | |
248 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) | |
249 | #define CMD_HDR_PRIORITY_OFF 27 | |
250 | #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) | |
251 | #define CMD_HDR_CMD_OFF 29 | |
252 | #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) | |
253 | /* dw1 */ | |
ce60689e | 254 | #define CMD_HDR_UNCON_CMD_OFF 3 |
a2204723 XC |
255 | #define CMD_HDR_DIR_OFF 5 |
256 | #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) | |
ce60689e XC |
257 | #define CMD_HDR_RESET_OFF 7 |
258 | #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) | |
a2204723 XC |
259 | #define CMD_HDR_VDTL_OFF 10 |
260 | #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) | |
261 | #define CMD_HDR_FRAME_TYPE_OFF 11 | |
262 | #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) | |
263 | #define CMD_HDR_DEV_ID_OFF 16 | |
264 | #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) | |
265 | /* dw2 */ | |
266 | #define CMD_HDR_CFL_OFF 0 | |
267 | #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) | |
ce60689e XC |
268 | #define CMD_HDR_NCQ_TAG_OFF 10 |
269 | #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) | |
a2204723 XC |
270 | #define CMD_HDR_MRFL_OFF 15 |
271 | #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) | |
272 | #define CMD_HDR_SG_MOD_OFF 24 | |
273 | #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) | |
fa913de2 XC |
274 | /* dw3 */ |
275 | #define CMD_HDR_IPTT_OFF 0 | |
276 | #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) | |
a2204723 XC |
277 | /* dw6 */ |
278 | #define CMD_HDR_DIF_SGL_LEN_OFF 0 | |
279 | #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) | |
280 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 | |
281 | #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) | |
4de0ca69 XC |
282 | /* dw7 */ |
283 | #define CMD_HDR_ADDR_MODE_SEL_OFF 15 | |
284 | #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) | |
285 | #define CMD_HDR_ABORT_IPTT_OFF 16 | |
286 | #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) | |
a2204723 | 287 | |
60b4a5ee XC |
288 | /* Completion header */ |
289 | /* dw0 */ | |
290 | #define CMPLT_HDR_CMPLT_OFF 0 | |
291 | #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) | |
292 | #define CMPLT_HDR_ERROR_PHASE_OFF 2 | |
293 | #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) | |
294 | #define CMPLT_HDR_RSPNS_XFRD_OFF 10 | |
295 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) | |
296 | #define CMPLT_HDR_ERX_OFF 12 | |
297 | #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) | |
298 | #define CMPLT_HDR_ABORT_STAT_OFF 13 | |
299 | #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) | |
300 | /* abort_stat */ | |
301 | #define STAT_IO_NOT_VALID 0x1 | |
302 | #define STAT_IO_NO_DEVICE 0x2 | |
303 | #define STAT_IO_COMPLETE 0x3 | |
304 | #define STAT_IO_ABORTED 0x4 | |
305 | /* dw1 */ | |
306 | #define CMPLT_HDR_IPTT_OFF 0 | |
307 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) | |
308 | #define CMPLT_HDR_DEV_ID_OFF 16 | |
309 | #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) | |
310 | /* dw3 */ | |
311 | #define CMPLT_HDR_IO_IN_TARGET_OFF 17 | |
312 | #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) | |
313 | ||
182e7222 XC |
314 | /* ITCT header */ |
315 | /* qw0 */ | |
316 | #define ITCT_HDR_DEV_TYPE_OFF 0 | |
317 | #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) | |
318 | #define ITCT_HDR_VALID_OFF 2 | |
319 | #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) | |
320 | #define ITCT_HDR_MCR_OFF 5 | |
321 | #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) | |
322 | #define ITCT_HDR_VLN_OFF 9 | |
323 | #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) | |
324 | #define ITCT_HDR_SMP_TIMEOUT_OFF 16 | |
325 | #define ITCT_HDR_AWT_CONTINUE_OFF 25 | |
326 | #define ITCT_HDR_PORT_ID_OFF 28 | |
327 | #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) | |
328 | /* qw2 */ | |
329 | #define ITCT_HDR_INLT_OFF 0 | |
330 | #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) | |
331 | #define ITCT_HDR_RTOLT_OFF 48 | |
332 | #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) | |
333 | ||
c94d8ca2 XC |
334 | struct hisi_sas_complete_v3_hdr { |
335 | __le32 dw0; | |
336 | __le32 dw1; | |
337 | __le32 act; | |
338 | __le32 dw3; | |
339 | }; | |
340 | ||
60b4a5ee XC |
341 | struct hisi_sas_err_record_v3 { |
342 | /* dw0 */ | |
343 | __le32 trans_tx_fail_type; | |
344 | ||
345 | /* dw1 */ | |
346 | __le32 trans_rx_fail_type; | |
347 | ||
348 | /* dw2 */ | |
349 | __le16 dma_tx_err_type; | |
350 | __le16 sipc_rx_err_type; | |
351 | ||
352 | /* dw3 */ | |
353 | __le32 dma_rx_err_type; | |
354 | }; | |
355 | ||
356 | #define RX_DATA_LEN_UNDERFLOW_OFF 6 | |
357 | #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) | |
358 | ||
c94d8ca2 | 359 | #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 |
3975f605 XC |
360 | #define HISI_SAS_MSI_COUNT_V3_HW 32 |
361 | ||
a2204723 XC |
362 | #define DIR_NO_DATA 0 |
363 | #define DIR_TO_INI 1 | |
364 | #define DIR_TO_DEVICE 2 | |
365 | #define DIR_RESERVED 3 | |
366 | ||
ed80f9c4 XC |
367 | #define FIS_CMD_IS_UNCONSTRAINED(fis) \ |
368 | ((fis.command == ATA_CMD_READ_LOG_EXT) || \ | |
369 | (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ | |
370 | ((fis.command == ATA_CMD_DEV_RESET) && \ | |
371 | ((fis.control & ATA_SRST) != 0))) | |
ce60689e | 372 | |
54edeee1 XC |
373 | static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) |
374 | { | |
375 | void __iomem *regs = hisi_hba->regs + off; | |
376 | ||
377 | return readl(regs); | |
378 | } | |
379 | ||
a2204723 XC |
380 | static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off) |
381 | { | |
382 | void __iomem *regs = hisi_hba->regs + off; | |
383 | ||
384 | return readl_relaxed(regs); | |
385 | } | |
386 | ||
c94d8ca2 XC |
387 | static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) |
388 | { | |
389 | void __iomem *regs = hisi_hba->regs + off; | |
390 | ||
391 | writel(val, regs); | |
392 | } | |
393 | ||
394 | static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, | |
395 | u32 off, u32 val) | |
396 | { | |
397 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
398 | ||
399 | writel(val, regs); | |
400 | } | |
401 | ||
3975f605 XC |
402 | static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, |
403 | int phy_no, u32 off) | |
404 | { | |
405 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
406 | ||
407 | return readl(regs); | |
408 | } | |
409 | ||
70bfdcae JG |
410 | #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ |
411 | timeout_us) \ | |
412 | ({ \ | |
413 | void __iomem *regs = hisi_hba->regs + off; \ | |
414 | readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ | |
415 | }) | |
416 | ||
417 | #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ | |
418 | timeout_us) \ | |
419 | ({ \ | |
420 | void __iomem *regs = hisi_hba->regs + off; \ | |
421 | readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ | |
422 | }) | |
423 | ||
c94d8ca2 XC |
424 | static void init_reg_v3_hw(struct hisi_hba *hisi_hba) |
425 | { | |
c13c7ac5 | 426 | struct pci_dev *pdev = hisi_hba->pci_dev; |
c94d8ca2 XC |
427 | int i; |
428 | ||
429 | /* Global registers init */ | |
430 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, | |
431 | (u32)((1ULL << hisi_hba->queue_count) - 1)); | |
3297ded1 | 432 | hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); |
c94d8ca2 | 433 | hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); |
c94d8ca2 XC |
434 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); |
435 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
436 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
437 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); | |
438 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); | |
439 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); | |
440 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); | |
441 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); | |
442 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); | |
c13c7ac5 XT |
443 | if (pdev->revision >= 0x21) |
444 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffff7fff); | |
445 | else | |
446 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xfffe20ff); | |
c94d8ca2 XC |
447 | hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); |
448 | hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); | |
449 | hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); | |
056e4cc6 | 450 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x0); |
c94d8ca2 XC |
451 | hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); |
452 | hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); | |
453 | for (i = 0; i < hisi_hba->queue_count; i++) | |
454 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); | |
455 | ||
c94d8ca2 | 456 | hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); |
c94d8ca2 XC |
457 | |
458 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
f385b4ff XC |
459 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; |
460 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
461 | u32 prog_phy_link_rate = 0x800; | |
462 | ||
463 | if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < | |
464 | SAS_LINK_RATE_1_5_GBPS)) { | |
465 | prog_phy_link_rate = 0x855; | |
466 | } else { | |
467 | enum sas_linkrate max = sas_phy->phy->maximum_linkrate; | |
468 | ||
469 | prog_phy_link_rate = | |
470 | hisi_sas_get_prog_phy_linkrate_mask(max) | | |
471 | 0x800; | |
472 | } | |
473 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, | |
474 | prog_phy_link_rate); | |
2b9174ae | 475 | hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); |
c94d8ca2 XC |
476 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); |
477 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); | |
478 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); | |
479 | hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); | |
c13c7ac5 XT |
480 | if (pdev->revision >= 0x21) |
481 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, | |
482 | 0xffffffff); | |
483 | else | |
484 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, | |
485 | 0xff87ffff); | |
066312f6 | 486 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); |
c94d8ca2 XC |
487 | hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); |
488 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); | |
489 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); | |
490 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); | |
491 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); | |
2b9174ae XT |
492 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); |
493 | hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); | |
fe058330 | 494 | hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); |
2b9174ae XT |
495 | |
496 | /* used for 12G negotiate */ | |
497 | hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); | |
c94d8ca2 | 498 | } |
2b9174ae | 499 | |
c94d8ca2 XC |
500 | for (i = 0; i < hisi_hba->queue_count; i++) { |
501 | /* Delivery queue */ | |
502 | hisi_sas_write32(hisi_hba, | |
503 | DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), | |
504 | upper_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
505 | ||
506 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), | |
507 | lower_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
508 | ||
509 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), | |
510 | HISI_SAS_QUEUE_SLOTS); | |
511 | ||
512 | /* Completion queue */ | |
513 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), | |
514 | upper_32_bits(hisi_hba->complete_hdr_dma[i])); | |
515 | ||
516 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), | |
517 | lower_32_bits(hisi_hba->complete_hdr_dma[i])); | |
518 | ||
519 | hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), | |
520 | HISI_SAS_QUEUE_SLOTS); | |
521 | } | |
522 | ||
523 | /* itct */ | |
524 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, | |
525 | lower_32_bits(hisi_hba->itct_dma)); | |
526 | ||
527 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, | |
528 | upper_32_bits(hisi_hba->itct_dma)); | |
529 | ||
530 | /* iost */ | |
531 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, | |
532 | lower_32_bits(hisi_hba->iost_dma)); | |
533 | ||
534 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, | |
535 | upper_32_bits(hisi_hba->iost_dma)); | |
536 | ||
537 | /* breakpoint */ | |
538 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, | |
539 | lower_32_bits(hisi_hba->breakpoint_dma)); | |
540 | ||
541 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, | |
542 | upper_32_bits(hisi_hba->breakpoint_dma)); | |
543 | ||
544 | /* SATA broken msg */ | |
545 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, | |
546 | lower_32_bits(hisi_hba->sata_breakpoint_dma)); | |
547 | ||
548 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, | |
549 | upper_32_bits(hisi_hba->sata_breakpoint_dma)); | |
550 | ||
551 | /* SATA initial fis */ | |
552 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, | |
553 | lower_32_bits(hisi_hba->initial_fis_dma)); | |
554 | ||
555 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, | |
556 | upper_32_bits(hisi_hba->initial_fis_dma)); | |
56b72168 XT |
557 | |
558 | /* RAS registers init */ | |
559 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); | |
560 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); | |
c13c7ac5 XT |
561 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); |
562 | hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); | |
e24fe507 XT |
563 | |
564 | /* LED registers init */ | |
565 | hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); | |
566 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); | |
567 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); | |
568 | /* Configure blink generator rate A to 1Hz and B to 4Hz */ | |
569 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); | |
570 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); | |
c94d8ca2 XC |
571 | } |
572 | ||
3975f605 XC |
573 | static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
574 | { | |
575 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
576 | ||
577 | cfg &= ~PHY_CFG_DC_OPT_MSK; | |
578 | cfg |= 1 << PHY_CFG_DC_OPT_OFF; | |
579 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
580 | } | |
581 | ||
582 | static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
583 | { | |
584 | struct sas_identify_frame identify_frame; | |
585 | u32 *identify_buffer; | |
586 | ||
587 | memset(&identify_frame, 0, sizeof(identify_frame)); | |
588 | identify_frame.dev_type = SAS_END_DEVICE; | |
589 | identify_frame.frame_type = 0; | |
590 | identify_frame._un1 = 1; | |
591 | identify_frame.initiator_bits = SAS_PROTOCOL_ALL; | |
592 | identify_frame.target_bits = SAS_PROTOCOL_NONE; | |
593 | memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
594 | memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
595 | identify_frame.phy_id = phy_no; | |
596 | identify_buffer = (u32 *)(&identify_frame); | |
597 | ||
598 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, | |
599 | __swab32(identify_buffer[0])); | |
600 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, | |
601 | __swab32(identify_buffer[1])); | |
602 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, | |
603 | __swab32(identify_buffer[2])); | |
604 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, | |
605 | __swab32(identify_buffer[3])); | |
606 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, | |
607 | __swab32(identify_buffer[4])); | |
608 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, | |
609 | __swab32(identify_buffer[5])); | |
610 | } | |
611 | ||
182e7222 XC |
612 | static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, |
613 | struct hisi_sas_device *sas_dev) | |
614 | { | |
615 | struct domain_device *device = sas_dev->sas_device; | |
616 | struct device *dev = hisi_hba->dev; | |
617 | u64 qw0, device_id = sas_dev->device_id; | |
618 | struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; | |
619 | struct domain_device *parent_dev = device->parent; | |
620 | struct asd_sas_port *sas_port = device->port; | |
621 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
622 | ||
623 | memset(itct, 0, sizeof(*itct)); | |
624 | ||
625 | /* qw0 */ | |
626 | qw0 = 0; | |
627 | switch (sas_dev->dev_type) { | |
628 | case SAS_END_DEVICE: | |
629 | case SAS_EDGE_EXPANDER_DEVICE: | |
630 | case SAS_FANOUT_EXPANDER_DEVICE: | |
631 | qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; | |
632 | break; | |
633 | case SAS_SATA_DEV: | |
634 | case SAS_SATA_PENDING: | |
635 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
636 | qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; | |
637 | else | |
638 | qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; | |
639 | break; | |
640 | default: | |
641 | dev_warn(dev, "setup itct: unsupported dev type (%d)\n", | |
642 | sas_dev->dev_type); | |
643 | } | |
644 | ||
645 | qw0 |= ((1 << ITCT_HDR_VALID_OFF) | | |
646 | (device->linkrate << ITCT_HDR_MCR_OFF) | | |
647 | (1 << ITCT_HDR_VLN_OFF) | | |
648 | (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | | |
649 | (1 << ITCT_HDR_AWT_CONTINUE_OFF) | | |
650 | (port->id << ITCT_HDR_PORT_ID_OFF)); | |
651 | itct->qw0 = cpu_to_le64(qw0); | |
652 | ||
653 | /* qw1 */ | |
654 | memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE); | |
655 | itct->sas_addr = __swab64(itct->sas_addr); | |
656 | ||
657 | /* qw2 */ | |
658 | if (!dev_is_sata(device)) | |
659 | itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | | |
660 | (0x1ULL << ITCT_HDR_RTOLT_OFF)); | |
661 | } | |
662 | ||
f39943ee | 663 | static void clear_itct_v3_hw(struct hisi_hba *hisi_hba, |
182e7222 XC |
664 | struct hisi_sas_device *sas_dev) |
665 | { | |
13cd5ed6 | 666 | DECLARE_COMPLETION_ONSTACK(completion); |
182e7222 | 667 | u64 dev_id = sas_dev->device_id; |
182e7222 XC |
668 | struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; |
669 | u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
670 | ||
13cd5ed6 XC |
671 | sas_dev->completion = &completion; |
672 | ||
182e7222 XC |
673 | /* clear the itct interrupt state */ |
674 | if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) | |
675 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, | |
676 | ENT_INT_SRC3_ITC_INT_MSK); | |
677 | ||
678 | /* clear the itct table*/ | |
13cd5ed6 | 679 | reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); |
182e7222 XC |
680 | hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); |
681 | ||
13cd5ed6 XC |
682 | wait_for_completion(sas_dev->completion); |
683 | memset(itct, 0, sizeof(struct hisi_sas_itct)); | |
182e7222 XC |
684 | } |
685 | ||
d30ff263 XC |
686 | static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, |
687 | struct domain_device *device) | |
688 | { | |
689 | struct hisi_sas_slot *slot, *slot2; | |
690 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
691 | u32 cfg_abt_set_query_iptt; | |
692 | ||
693 | cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, | |
694 | CFG_ABT_SET_QUERY_IPTT); | |
695 | list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { | |
696 | cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; | |
697 | cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | | |
698 | (slot->idx << CFG_SET_ABORTED_IPTT_OFF); | |
699 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
700 | cfg_abt_set_query_iptt); | |
701 | } | |
702 | cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); | |
703 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
704 | cfg_abt_set_query_iptt); | |
705 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, | |
706 | 1 << CFG_ABT_SET_IPTT_DONE_OFF); | |
707 | } | |
708 | ||
a25d0d3d XC |
709 | static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) |
710 | { | |
711 | struct device *dev = hisi_hba->dev; | |
712 | int ret; | |
713 | u32 val; | |
714 | ||
715 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); | |
716 | ||
717 | /* Disable all of the PHYs */ | |
718 | hisi_sas_stop_phys(hisi_hba); | |
719 | udelay(50); | |
720 | ||
721 | /* Ensure axi bus idle */ | |
70bfdcae JG |
722 | ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, |
723 | 20000, 1000000); | |
a25d0d3d XC |
724 | if (ret) { |
725 | dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); | |
726 | return -EIO; | |
727 | } | |
728 | ||
729 | if (ACPI_HANDLE(dev)) { | |
730 | acpi_status s; | |
731 | ||
732 | s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); | |
733 | if (ACPI_FAILURE(s)) { | |
734 | dev_err(dev, "Reset failed\n"); | |
735 | return -EIO; | |
736 | } | |
bcbc7f1c | 737 | } else { |
a25d0d3d | 738 | dev_err(dev, "no reset method!\n"); |
bcbc7f1c XC |
739 | return -EINVAL; |
740 | } | |
a25d0d3d XC |
741 | |
742 | return 0; | |
743 | } | |
744 | ||
c94d8ca2 XC |
745 | static int hw_init_v3_hw(struct hisi_hba *hisi_hba) |
746 | { | |
a25d0d3d XC |
747 | struct device *dev = hisi_hba->dev; |
748 | int rc; | |
749 | ||
750 | rc = reset_hw_v3_hw(hisi_hba); | |
751 | if (rc) { | |
752 | dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); | |
753 | return rc; | |
754 | } | |
755 | ||
756 | msleep(100); | |
c94d8ca2 XC |
757 | init_reg_v3_hw(hisi_hba); |
758 | ||
759 | return 0; | |
760 | } | |
761 | ||
3975f605 XC |
762 | static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
763 | { | |
764 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
765 | ||
766 | cfg |= PHY_CFG_ENA_MSK; | |
17d59a57 | 767 | cfg &= ~PHY_CFG_PHY_RST_MSK; |
3975f605 XC |
768 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); |
769 | } | |
770 | ||
402cd9f0 XC |
771 | static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
772 | { | |
773 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
17d59a57 | 774 | u32 state; |
402cd9f0 XC |
775 | |
776 | cfg &= ~PHY_CFG_ENA_MSK; | |
777 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
17d59a57 XT |
778 | |
779 | mdelay(50); | |
780 | ||
781 | state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
782 | if (state & BIT(phy_no)) { | |
783 | cfg |= PHY_CFG_PHY_RST_MSK; | |
784 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
785 | } | |
402cd9f0 XC |
786 | } |
787 | ||
3975f605 XC |
788 | static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
789 | { | |
790 | config_id_frame_v3_hw(hisi_hba, phy_no); | |
791 | config_phy_opt_mode_v3_hw(hisi_hba, phy_no); | |
792 | enable_phy_v3_hw(hisi_hba, phy_no); | |
793 | } | |
794 | ||
402cd9f0 XC |
795 | static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
796 | { | |
797 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
798 | u32 txid_auto; | |
799 | ||
a25d0d3d | 800 | disable_phy_v3_hw(hisi_hba, phy_no); |
402cd9f0 XC |
801 | if (phy->identify.device_type == SAS_END_DEVICE) { |
802 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
803 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
804 | txid_auto | TX_HARDRST_MSK); | |
805 | } | |
806 | msleep(100); | |
807 | start_phy_v3_hw(hisi_hba, phy_no); | |
808 | } | |
809 | ||
bcbc7f1c | 810 | static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) |
402cd9f0 XC |
811 | { |
812 | return SAS_LINK_RATE_12_0_GBPS; | |
813 | } | |
814 | ||
3975f605 XC |
815 | static void phys_init_v3_hw(struct hisi_hba *hisi_hba) |
816 | { | |
a25d0d3d XC |
817 | int i; |
818 | ||
819 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
820 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; | |
821 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
822 | ||
823 | if (!sas_phy->phy->enabled) | |
824 | continue; | |
825 | ||
826 | start_phy_v3_hw(hisi_hba, i); | |
827 | } | |
3975f605 XC |
828 | } |
829 | ||
830 | static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
831 | { | |
832 | u32 sl_control; | |
833 | ||
834 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
835 | sl_control |= SL_CONTROL_NOTIFY_EN_MSK; | |
836 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
837 | msleep(1); | |
838 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
839 | sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; | |
840 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
841 | } | |
842 | ||
f771d3b0 XC |
843 | static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) |
844 | { | |
845 | int i, bitmap = 0; | |
846 | u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
0e3231fc | 847 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); |
f771d3b0 XC |
848 | |
849 | for (i = 0; i < hisi_hba->n_phy; i++) | |
0e3231fc XT |
850 | if (phy_state & BIT(i)) |
851 | if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) | |
852 | bitmap |= BIT(i); | |
f771d3b0 XC |
853 | |
854 | return bitmap; | |
855 | } | |
856 | ||
a2204723 XC |
857 | /** |
858 | * The callpath to this function and upto writing the write | |
859 | * queue pointer should be safe from interruption. | |
860 | */ | |
861 | static int | |
862 | get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq) | |
863 | { | |
864 | struct device *dev = hisi_hba->dev; | |
865 | int queue = dq->id; | |
866 | u32 r, w; | |
867 | ||
868 | w = dq->wr_point; | |
869 | r = hisi_sas_read32_relaxed(hisi_hba, | |
870 | DLVRY_Q_0_RD_PTR + (queue * 0x14)); | |
871 | if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) { | |
c58ec824 | 872 | dev_warn(dev, "full queue=%d r=%d w=%d\n", |
a2204723 XC |
873 | queue, r, w); |
874 | return -EAGAIN; | |
875 | } | |
876 | ||
c58ec824 XC |
877 | dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS; |
878 | ||
879 | return w; | |
a2204723 XC |
880 | } |
881 | ||
882 | static void start_delivery_v3_hw(struct hisi_sas_dq *dq) | |
883 | { | |
884 | struct hisi_hba *hisi_hba = dq->hisi_hba; | |
5a61a535 | 885 | struct hisi_sas_slot *s, *s1, *s2 = NULL; |
c58ec824 XC |
886 | struct list_head *dq_list; |
887 | int dlvry_queue = dq->id; | |
5a61a535 | 888 | int wp; |
c58ec824 XC |
889 | |
890 | dq_list = &dq->list; | |
891 | list_for_each_entry_safe(s, s1, &dq->list, delivery) { | |
892 | if (!s->ready) | |
893 | break; | |
5a61a535 | 894 | s2 = s; |
c58ec824 XC |
895 | list_del(&s->delivery); |
896 | } | |
897 | ||
5a61a535 | 898 | if (!s2) |
c58ec824 | 899 | return; |
a2204723 | 900 | |
5a61a535 XT |
901 | /* |
902 | * Ensure that memories for slots built on other CPUs is observed. | |
903 | */ | |
904 | smp_rmb(); | |
905 | wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; | |
906 | ||
c58ec824 | 907 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); |
a2204723 XC |
908 | } |
909 | ||
81d115ec | 910 | static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, |
a2204723 XC |
911 | struct hisi_sas_slot *slot, |
912 | struct hisi_sas_cmd_hdr *hdr, | |
913 | struct scatterlist *scatter, | |
914 | int n_elem) | |
915 | { | |
f557e32c | 916 | struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); |
a2204723 XC |
917 | struct scatterlist *sg; |
918 | int i; | |
919 | ||
a2204723 | 920 | for_each_sg(scatter, sg, n_elem, i) { |
f557e32c | 921 | struct hisi_sas_sge *entry = &sge_page->sge[i]; |
a2204723 XC |
922 | |
923 | entry->addr = cpu_to_le64(sg_dma_address(sg)); | |
924 | entry->page_ctrl_0 = entry->page_ctrl_1 = 0; | |
925 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); | |
926 | entry->data_off = 0; | |
927 | } | |
928 | ||
f557e32c XT |
929 | hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); |
930 | ||
a2204723 | 931 | hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); |
a2204723 XC |
932 | } |
933 | ||
81d115ec | 934 | static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, |
9a98d728 | 935 | struct hisi_sas_slot *slot) |
a2204723 XC |
936 | { |
937 | struct sas_task *task = slot->task; | |
938 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
939 | struct domain_device *device = task->dev; | |
940 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
941 | struct hisi_sas_port *port = slot->port; | |
942 | struct sas_ssp_task *ssp_task = &task->ssp_task; | |
943 | struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; | |
9a98d728 XT |
944 | struct hisi_sas_tmf_task *tmf = slot->tmf; |
945 | int has_data = 0, priority = !!tmf; | |
a2204723 XC |
946 | u8 *buf_cmd; |
947 | u32 dw1 = 0, dw2 = 0; | |
948 | ||
949 | hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | | |
950 | (2 << CMD_HDR_TLR_CTRL_OFF) | | |
951 | (port->id << CMD_HDR_PORT_OFF) | | |
952 | (priority << CMD_HDR_PRIORITY_OFF) | | |
953 | (1 << CMD_HDR_CMD_OFF)); /* ssp */ | |
954 | ||
955 | dw1 = 1 << CMD_HDR_VDTL_OFF; | |
9a98d728 | 956 | if (tmf) { |
a2204723 XC |
957 | dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; |
958 | dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; | |
959 | } else { | |
960 | dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; | |
961 | switch (scsi_cmnd->sc_data_direction) { | |
962 | case DMA_TO_DEVICE: | |
963 | has_data = 1; | |
964 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
965 | break; | |
966 | case DMA_FROM_DEVICE: | |
967 | has_data = 1; | |
968 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
969 | break; | |
970 | default: | |
971 | dw1 &= ~CMD_HDR_DIR_MSK; | |
972 | } | |
973 | } | |
974 | ||
975 | /* map itct entry */ | |
976 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
977 | hdr->dw1 = cpu_to_le32(dw1); | |
978 | ||
979 | dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) | |
980 | + 3) / 4) << CMD_HDR_CFL_OFF) | | |
981 | ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | | |
982 | (2 << CMD_HDR_SG_MOD_OFF); | |
983 | hdr->dw2 = cpu_to_le32(dw2); | |
984 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
985 | ||
81d115ec XC |
986 | if (has_data) |
987 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, | |
a2204723 | 988 | slot->n_elem); |
a2204723 XC |
989 | |
990 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
f557e32c XT |
991 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
992 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
a2204723 | 993 | |
f557e32c XT |
994 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + |
995 | sizeof(struct ssp_frame_hdr); | |
a2204723 | 996 | |
f557e32c | 997 | memcpy(buf_cmd, &task->ssp_task.LUN, 8); |
9a98d728 | 998 | if (!tmf) { |
a2204723 XC |
999 | buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); |
1000 | memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); | |
1001 | } else { | |
1002 | buf_cmd[10] = tmf->tmf; | |
1003 | switch (tmf->tmf) { | |
1004 | case TMF_ABORT_TASK: | |
1005 | case TMF_QUERY_TASK: | |
1006 | buf_cmd[12] = | |
1007 | (tmf->tag_of_task_to_be_managed >> 8) & 0xff; | |
1008 | buf_cmd[13] = | |
1009 | tmf->tag_of_task_to_be_managed & 0xff; | |
1010 | break; | |
1011 | default: | |
1012 | break; | |
1013 | } | |
1014 | } | |
a2204723 XC |
1015 | } |
1016 | ||
81d115ec | 1017 | static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, |
fa913de2 XC |
1018 | struct hisi_sas_slot *slot) |
1019 | { | |
1020 | struct sas_task *task = slot->task; | |
1021 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1022 | struct domain_device *device = task->dev; | |
fa913de2 | 1023 | struct hisi_sas_port *port = slot->port; |
8118ae07 | 1024 | struct scatterlist *sg_req; |
fa913de2 XC |
1025 | struct hisi_sas_device *sas_dev = device->lldd_dev; |
1026 | dma_addr_t req_dma_addr; | |
8118ae07 | 1027 | unsigned int req_len; |
fa913de2 | 1028 | |
fa913de2 XC |
1029 | /* req */ |
1030 | sg_req = &task->smp_task.smp_req; | |
fa913de2 XC |
1031 | req_len = sg_dma_len(sg_req); |
1032 | req_dma_addr = sg_dma_address(sg_req); | |
1033 | ||
fa913de2 XC |
1034 | /* create header */ |
1035 | /* dw0 */ | |
1036 | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | | |
1037 | (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ | |
1038 | (2 << CMD_HDR_CMD_OFF)); /* smp */ | |
1039 | ||
1040 | /* map itct entry */ | |
1041 | hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | | |
1042 | (1 << CMD_HDR_FRAME_TYPE_OFF) | | |
1043 | (DIR_NO_DATA << CMD_HDR_DIR_OFF)); | |
1044 | ||
1045 | /* dw2 */ | |
1046 | hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | | |
1047 | (HISI_SAS_MAX_SMP_RESP_SZ / 4 << | |
1048 | CMD_HDR_MRFL_OFF)); | |
1049 | ||
1050 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); | |
1051 | ||
1052 | hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); | |
f557e32c | 1053 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); |
fa913de2 | 1054 | |
fa913de2 XC |
1055 | } |
1056 | ||
81d115ec | 1057 | static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, |
ce60689e XC |
1058 | struct hisi_sas_slot *slot) |
1059 | { | |
1060 | struct sas_task *task = slot->task; | |
1061 | struct domain_device *device = task->dev; | |
1062 | struct domain_device *parent_dev = device->parent; | |
1063 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1064 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1065 | struct asd_sas_port *sas_port = device->port; | |
1066 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
1067 | u8 *buf_cmd; | |
81d115ec | 1068 | int has_data = 0, hdr_tag = 0; |
ce60689e XC |
1069 | u32 dw1 = 0, dw2 = 0; |
1070 | ||
1071 | hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); | |
1072 | if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type)) | |
1073 | hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); | |
1074 | else | |
1075 | hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF); | |
1076 | ||
1077 | switch (task->data_dir) { | |
1078 | case DMA_TO_DEVICE: | |
1079 | has_data = 1; | |
1080 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1081 | break; | |
1082 | case DMA_FROM_DEVICE: | |
1083 | has_data = 1; | |
1084 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1085 | break; | |
1086 | default: | |
1087 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1088 | } | |
1089 | ||
1090 | if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && | |
1091 | (task->ata_task.fis.control & ATA_SRST)) | |
1092 | dw1 |= 1 << CMD_HDR_RESET_OFF; | |
1093 | ||
1094 | dw1 |= (hisi_sas_get_ata_protocol( | |
ba0bb2be | 1095 | &task->ata_task.fis, task->data_dir)) |
ce60689e XC |
1096 | << CMD_HDR_FRAME_TYPE_OFF; |
1097 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
1098 | ||
ed80f9c4 | 1099 | if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) |
ce60689e XC |
1100 | dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; |
1101 | ||
1102 | hdr->dw1 = cpu_to_le32(dw1); | |
1103 | ||
1104 | /* dw2 */ | |
8ae6725d | 1105 | if (task->ata_task.use_ncq && hisi_sas_get_ncq_tag(task, &hdr_tag)) { |
ce60689e XC |
1106 | task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); |
1107 | dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; | |
1108 | } | |
1109 | ||
1110 | dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | | |
1111 | 2 << CMD_HDR_SG_MOD_OFF; | |
1112 | hdr->dw2 = cpu_to_le32(dw2); | |
1113 | ||
1114 | /* dw3 */ | |
1115 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1116 | ||
81d115ec XC |
1117 | if (has_data) |
1118 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, | |
ce60689e | 1119 | slot->n_elem); |
ce60689e XC |
1120 | |
1121 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
f557e32c XT |
1122 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1123 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
ce60689e | 1124 | |
f557e32c | 1125 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); |
ce60689e XC |
1126 | |
1127 | if (likely(!task->ata_task.device_control_reg_update)) | |
1128 | task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ | |
1129 | /* fill in command FIS */ | |
1130 | memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); | |
ce60689e XC |
1131 | } |
1132 | ||
81d115ec | 1133 | static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, |
4de0ca69 XC |
1134 | struct hisi_sas_slot *slot, |
1135 | int device_id, int abort_flag, int tag_to_abort) | |
1136 | { | |
1137 | struct sas_task *task = slot->task; | |
1138 | struct domain_device *dev = task->dev; | |
1139 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1140 | struct hisi_sas_port *port = slot->port; | |
1141 | ||
1142 | /* dw0 */ | |
1143 | hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/ | |
1144 | (port->id << CMD_HDR_PORT_OFF) | | |
bcbc7f1c | 1145 | (dev_is_sata(dev) |
4de0ca69 XC |
1146 | << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
1147 | (abort_flag | |
1148 | << CMD_HDR_ABORT_FLAG_OFF)); | |
1149 | ||
1150 | /* dw1 */ | |
1151 | hdr->dw1 = cpu_to_le32(device_id | |
1152 | << CMD_HDR_DEV_ID_OFF); | |
1153 | ||
1154 | /* dw7 */ | |
1155 | hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); | |
1156 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1157 | ||
4de0ca69 XC |
1158 | } |
1159 | ||
bcbc7f1c | 1160 | static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1161 | { |
bcbc7f1c | 1162 | int i, res; |
c57eb4e4 | 1163 | u32 context, port_id, link_rate; |
54edeee1 XC |
1164 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; |
1165 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1166 | struct device *dev = hisi_hba->dev; | |
cca25cbc | 1167 | unsigned long flags; |
54edeee1 XC |
1168 | |
1169 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); | |
1170 | ||
1171 | port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
1172 | port_id = (port_id >> (4 * phy_no)) & 0xf; | |
1173 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); | |
1174 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; | |
1175 | ||
1176 | if (port_id == 0xf) { | |
1177 | dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); | |
1178 | res = IRQ_NONE; | |
1179 | goto end; | |
1180 | } | |
1181 | sas_phy->linkrate = link_rate; | |
54edeee1 XC |
1182 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); |
1183 | ||
1184 | /* Check for SATA dev */ | |
1185 | context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); | |
1186 | if (context & (1 << phy_no)) { | |
1187 | struct hisi_sas_initial_fis *initial_fis; | |
1188 | struct dev_to_host_fis *fis; | |
1189 | u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; | |
1190 | ||
081a1608 | 1191 | dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); |
54edeee1 XC |
1192 | initial_fis = &hisi_hba->initial_fis[phy_no]; |
1193 | fis = &initial_fis->fis; | |
a2d76b6b XC |
1194 | |
1195 | /* check ERR bit of Status Register */ | |
1196 | if (fis->status & ATA_ERR) { | |
1197 | dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", | |
1198 | phy_no, fis->status); | |
1199 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1200 | res = IRQ_NONE; | |
1201 | goto end; | |
1202 | } | |
1203 | ||
54edeee1 XC |
1204 | sas_phy->oob_mode = SATA_OOB_MODE; |
1205 | attached_sas_addr[0] = 0x50; | |
1206 | attached_sas_addr[7] = phy_no; | |
1207 | memcpy(sas_phy->attached_sas_addr, | |
1208 | attached_sas_addr, | |
1209 | SAS_ADDR_SIZE); | |
1210 | memcpy(sas_phy->frame_rcvd, fis, | |
1211 | sizeof(struct dev_to_host_fis)); | |
1212 | phy->phy_type |= PORT_TYPE_SATA; | |
1213 | phy->identify.device_type = SAS_SATA_DEV; | |
1214 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); | |
1215 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; | |
1216 | } else { | |
1217 | u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; | |
1218 | struct sas_identify_frame *id = | |
1219 | (struct sas_identify_frame *)frame_rcvd; | |
1220 | ||
1221 | dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); | |
1222 | for (i = 0; i < 6; i++) { | |
1223 | u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1224 | RX_IDAF_DWORD0 + (i * 4)); | |
1225 | frame_rcvd[i] = __swab32(idaf); | |
1226 | } | |
1227 | sas_phy->oob_mode = SAS_OOB_MODE; | |
1228 | memcpy(sas_phy->attached_sas_addr, | |
1229 | &id->sas_addr, | |
1230 | SAS_ADDR_SIZE); | |
1231 | phy->phy_type |= PORT_TYPE_SAS; | |
1232 | phy->identify.device_type = id->dev_type; | |
1233 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame); | |
1234 | if (phy->identify.device_type == SAS_END_DEVICE) | |
1235 | phy->identify.target_port_protocols = | |
1236 | SAS_PROTOCOL_SSP; | |
1237 | else if (phy->identify.device_type != SAS_PHY_UNUSED) | |
1238 | phy->identify.target_port_protocols = | |
1239 | SAS_PROTOCOL_SMP; | |
1240 | } | |
1241 | ||
1242 | phy->port_id = port_id; | |
1243 | phy->phy_attached = 1; | |
320cd6f1 | 1244 | hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); |
bcbc7f1c | 1245 | res = IRQ_HANDLED; |
cca25cbc XC |
1246 | spin_lock_irqsave(&phy->lock, flags); |
1247 | if (phy->reset_completion) { | |
1248 | phy->in_reset = 0; | |
1249 | complete(phy->reset_completion); | |
1250 | } | |
1251 | spin_unlock_irqrestore(&phy->lock, flags); | |
54edeee1 XC |
1252 | end: |
1253 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, | |
1254 | CHL_INT0_SL_PHY_ENABLE_MSK); | |
1255 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); | |
1256 | ||
1257 | return res; | |
1258 | } | |
1259 | ||
bcbc7f1c | 1260 | static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1261 | { |
54edeee1 XC |
1262 | u32 phy_state, sl_ctrl, txid_auto; |
1263 | struct device *dev = hisi_hba->dev; | |
1264 | ||
1265 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); | |
1266 | ||
1267 | phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1268 | dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); | |
1269 | hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); | |
1270 | ||
1271 | sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
1272 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, | |
1273 | sl_ctrl&(~SL_CTA_MSK)); | |
1274 | ||
1275 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
1276 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
1277 | txid_auto | CT3_MSK); | |
1278 | ||
1279 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); | |
1280 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); | |
1281 | ||
bcbc7f1c | 1282 | return IRQ_HANDLED; |
54edeee1 XC |
1283 | } |
1284 | ||
bcbc7f1c | 1285 | static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 XC |
1286 | { |
1287 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1288 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1289 | struct sas_ha_struct *sas_ha = &hisi_hba->sha; | |
45651175 | 1290 | u32 bcast_status; |
54edeee1 XC |
1291 | |
1292 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); | |
45651175 | 1293 | bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); |
df48a904 XT |
1294 | if ((bcast_status & RX_BCAST_CHG_MSK) && |
1295 | !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) | |
45651175 | 1296 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
54edeee1 XC |
1297 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, |
1298 | CHL_INT0_SL_RX_BCST_ACK_MSK); | |
1299 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); | |
bcbc7f1c XC |
1300 | |
1301 | return IRQ_HANDLED; | |
54edeee1 XC |
1302 | } |
1303 | ||
1304 | static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) | |
1305 | { | |
1306 | struct hisi_hba *hisi_hba = p; | |
1307 | u32 irq_msk; | |
1308 | int phy_no = 0; | |
1309 | irqreturn_t res = IRQ_NONE; | |
1310 | ||
1311 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) | |
1312 | & 0x11111111; | |
1313 | while (irq_msk) { | |
1314 | if (irq_msk & 1) { | |
1315 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1316 | CHL_INT0); | |
1317 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1318 | int rdy = phy_state & (1 << phy_no); | |
1319 | ||
1320 | if (rdy) { | |
1321 | if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) | |
1322 | /* phy up */ | |
1323 | if (phy_up_v3_hw(phy_no, hisi_hba) | |
1324 | == IRQ_HANDLED) | |
1325 | res = IRQ_HANDLED; | |
1326 | if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) | |
1327 | /* phy bcast */ | |
bcbc7f1c XC |
1328 | if (phy_bcast_v3_hw(phy_no, hisi_hba) |
1329 | == IRQ_HANDLED) | |
1330 | res = IRQ_HANDLED; | |
54edeee1 XC |
1331 | } else { |
1332 | if (irq_value & CHL_INT0_NOT_RDY_MSK) | |
1333 | /* phy down */ | |
1334 | if (phy_down_v3_hw(phy_no, hisi_hba) | |
1335 | == IRQ_HANDLED) | |
1336 | res = IRQ_HANDLED; | |
1337 | } | |
1338 | } | |
1339 | irq_msk >>= 4; | |
1340 | phy_no++; | |
1341 | } | |
1342 | ||
1343 | return res; | |
1344 | } | |
1345 | ||
4a6125c5 XT |
1346 | static const struct hisi_sas_hw_error port_axi_error[] = { |
1347 | { | |
1348 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), | |
1349 | .msg = "dma_tx_axi_wr_err", | |
1350 | }, | |
1351 | { | |
1352 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), | |
1353 | .msg = "dma_tx_axi_rd_err", | |
1354 | }, | |
1355 | { | |
1356 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), | |
1357 | .msg = "dma_rx_axi_wr_err", | |
1358 | }, | |
1359 | { | |
1360 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), | |
1361 | .msg = "dma_rx_axi_rd_err", | |
1362 | }, | |
1363 | }; | |
1364 | ||
cdb76c15 | 1365 | static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
54edeee1 | 1366 | { |
cdb76c15 XT |
1367 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); |
1368 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); | |
54edeee1 | 1369 | struct device *dev = hisi_hba->dev; |
cdb76c15 XT |
1370 | int i; |
1371 | ||
1372 | irq_value &= ~irq_msk; | |
1373 | if (!irq_value) | |
1374 | return; | |
1375 | ||
1376 | for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { | |
1377 | const struct hisi_sas_hw_error *error = &port_axi_error[i]; | |
1378 | ||
1379 | if (!(irq_value & error->irq_msk)) | |
1380 | continue; | |
1381 | ||
1382 | dev_err(dev, "%s error (phy%d 0x%x) found!\n", | |
1383 | error->msg, phy_no, irq_value); | |
1384 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1385 | } | |
1386 | ||
1387 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); | |
1388 | } | |
1389 | ||
1390 | static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
1391 | { | |
1392 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); | |
1393 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); | |
1394 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
70230be3 | 1395 | struct pci_dev *pci_dev = hisi_hba->pci_dev; |
cdb76c15 XT |
1396 | struct device *dev = hisi_hba->dev; |
1397 | ||
1398 | irq_value &= ~irq_msk; | |
1399 | if (!irq_value) | |
1400 | return; | |
1401 | ||
1402 | if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { | |
1403 | dev_warn(dev, "phy%d identify timeout\n", phy_no); | |
1404 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1405 | } | |
1406 | ||
1407 | if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { | |
1408 | u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1409 | STP_LINK_TIMEOUT_STATE); | |
1410 | ||
1411 | dev_warn(dev, "phy%d stp link timeout (0x%x)\n", | |
1412 | phy_no, reg_value); | |
1413 | if (reg_value & BIT(4)) | |
1414 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1415 | } | |
1416 | ||
cdb76c15 XT |
1417 | if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && |
1418 | (pci_dev->revision == 0x20)) { | |
1419 | u32 reg_value; | |
1420 | int rc; | |
1421 | ||
1422 | rc = hisi_sas_read32_poll_timeout_atomic( | |
1423 | HILINK_ERR_DFX, reg_value, | |
1424 | !((reg_value >> 8) & BIT(phy_no)), | |
1425 | 1000, 10000); | |
17d59a57 XT |
1426 | if (rc) |
1427 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
cdb76c15 | 1428 | } |
17d59a57 XT |
1429 | |
1430 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); | |
cdb76c15 XT |
1431 | } |
1432 | ||
1433 | static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) | |
1434 | { | |
1435 | struct hisi_hba *hisi_hba = p; | |
ab39f052 | 1436 | u32 irq_msk; |
54edeee1 XC |
1437 | int phy_no = 0; |
1438 | ||
54edeee1 XC |
1439 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) |
1440 | & 0xeeeeeeee; | |
1441 | ||
1442 | while (irq_msk) { | |
1443 | u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1444 | CHL_INT0); | |
066312f6 | 1445 | |
cdb76c15 XT |
1446 | if (irq_msk & (4 << (phy_no * 4))) |
1447 | handle_chl_int1_v3_hw(hisi_hba, phy_no); | |
066312f6 | 1448 | |
cdb76c15 XT |
1449 | if (irq_msk & (8 << (phy_no * 4))) |
1450 | handle_chl_int2_v3_hw(hisi_hba, phy_no); | |
54edeee1 XC |
1451 | |
1452 | if (irq_msk & (2 << (phy_no * 4)) && irq_value0) { | |
1453 | hisi_sas_phy_write32(hisi_hba, phy_no, | |
1454 | CHL_INT0, irq_value0 | |
4f73575a | 1455 | & (~CHL_INT0_SL_RX_BCST_ACK_MSK) |
54edeee1 XC |
1456 | & (~CHL_INT0_SL_PHY_ENABLE_MSK) |
1457 | & (~CHL_INT0_NOT_RDY_MSK)); | |
1458 | } | |
1459 | irq_msk &= ~(0xe << (phy_no * 4)); | |
1460 | phy_no++; | |
1461 | } | |
1462 | ||
54edeee1 XC |
1463 | return IRQ_HANDLED; |
1464 | } | |
1465 | ||
fa231408 XT |
1466 | static const struct hisi_sas_hw_error axi_error[] = { |
1467 | { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, | |
1468 | { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, | |
1469 | { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, | |
1470 | { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, | |
1471 | { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, | |
1472 | { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, | |
1473 | { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, | |
1474 | { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, | |
1475 | {}, | |
1476 | }; | |
1477 | ||
1478 | static const struct hisi_sas_hw_error fifo_error[] = { | |
1479 | { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, | |
1480 | { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, | |
1481 | { .msk = BIT(10), .msg = "GETDQE_FIFO" }, | |
1482 | { .msk = BIT(11), .msg = "CMDP_FIFO" }, | |
1483 | { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, | |
1484 | {}, | |
1485 | }; | |
1486 | ||
1487 | static const struct hisi_sas_hw_error fatal_axi_error[] = { | |
1488 | { | |
1489 | .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), | |
1490 | .msg = "write pointer and depth", | |
1491 | }, | |
1492 | { | |
1493 | .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), | |
1494 | .msg = "iptt no match slot", | |
1495 | }, | |
1496 | { | |
1497 | .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), | |
1498 | .msg = "read pointer and depth", | |
1499 | }, | |
1500 | { | |
1501 | .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), | |
1502 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1503 | .sub = axi_error, | |
1504 | }, | |
1505 | { | |
1506 | .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), | |
1507 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1508 | .sub = fifo_error, | |
1509 | }, | |
1510 | { | |
1511 | .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), | |
1512 | .msg = "LM add/fetch list", | |
1513 | }, | |
1514 | { | |
1515 | .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), | |
1516 | .msg = "SAS_HGC_ABT fetch LM list", | |
1517 | }, | |
1518 | }; | |
1519 | ||
1520 | static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) | |
1521 | { | |
1522 | u32 irq_value, irq_msk; | |
1523 | struct hisi_hba *hisi_hba = p; | |
1524 | struct device *dev = hisi_hba->dev; | |
1525 | int i; | |
1526 | ||
1527 | irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); | |
1528 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); | |
1529 | ||
1530 | irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
c13c7ac5 | 1531 | irq_value &= ~irq_msk; |
fa231408 XT |
1532 | |
1533 | for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { | |
1534 | const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; | |
1535 | ||
1536 | if (!(irq_value & error->irq_msk)) | |
1537 | continue; | |
1538 | ||
1539 | if (error->sub) { | |
1540 | const struct hisi_sas_hw_error *sub = error->sub; | |
1541 | u32 err_value = hisi_sas_read32(hisi_hba, error->reg); | |
1542 | ||
1543 | for (; sub->msk || sub->msg; sub++) { | |
1544 | if (!(err_value & sub->msk)) | |
1545 | continue; | |
1546 | ||
081a1608 | 1547 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
1548 | sub->msg, irq_value); |
1549 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1550 | } | |
1551 | } else { | |
081a1608 | 1552 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
1553 | error->msg, irq_value); |
1554 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1555 | } | |
1556 | } | |
1557 | ||
1558 | if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { | |
1559 | u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); | |
1560 | u32 dev_id = reg_val & ITCT_DEV_MSK; | |
1561 | struct hisi_sas_device *sas_dev = | |
1562 | &hisi_hba->devices[dev_id]; | |
1563 | ||
1564 | hisi_sas_write32(hisi_hba, ITCT_CLR, 0); | |
1565 | dev_dbg(dev, "clear ITCT ok\n"); | |
1566 | complete(sas_dev->completion); | |
1567 | } | |
1568 | ||
1569 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); | |
1570 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); | |
1571 | ||
1572 | return IRQ_HANDLED; | |
1573 | } | |
1574 | ||
60b4a5ee XC |
1575 | static void |
1576 | slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, | |
1577 | struct hisi_sas_slot *slot) | |
1578 | { | |
1579 | struct task_status_struct *ts = &task->task_status; | |
1580 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
1581 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
1582 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
1583 | &complete_queue[slot->cmplt_queue_slot]; | |
f557e32c XT |
1584 | struct hisi_sas_err_record_v3 *record = |
1585 | hisi_sas_status_buf_addr_mem(slot); | |
60b4a5ee XC |
1586 | u32 dma_rx_err_type = record->dma_rx_err_type; |
1587 | u32 trans_tx_fail_type = record->trans_tx_fail_type; | |
1588 | ||
1589 | switch (task->task_proto) { | |
1590 | case SAS_PROTOCOL_SSP: | |
1591 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
1592 | ts->residual = trans_tx_fail_type; | |
1593 | ts->stat = SAS_DATA_UNDERRUN; | |
1594 | } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { | |
1595 | ts->stat = SAS_QUEUE_FULL; | |
1596 | slot->abort = 1; | |
1597 | } else { | |
1598 | ts->stat = SAS_OPEN_REJECT; | |
1599 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1600 | } | |
1601 | break; | |
1602 | case SAS_PROTOCOL_SATA: | |
1603 | case SAS_PROTOCOL_STP: | |
1604 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
1605 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
1606 | ts->residual = trans_tx_fail_type; | |
1607 | ts->stat = SAS_DATA_UNDERRUN; | |
1608 | } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { | |
1609 | ts->stat = SAS_PHY_DOWN; | |
1610 | slot->abort = 1; | |
1611 | } else { | |
1612 | ts->stat = SAS_OPEN_REJECT; | |
1613 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
1614 | } | |
1615 | hisi_sas_sata_done(task, slot); | |
1616 | break; | |
1617 | case SAS_PROTOCOL_SMP: | |
1618 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1619 | break; | |
1620 | default: | |
1621 | break; | |
1622 | } | |
1623 | } | |
1624 | ||
1625 | static int | |
1626 | slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) | |
1627 | { | |
1628 | struct sas_task *task = slot->task; | |
1629 | struct hisi_sas_device *sas_dev; | |
1630 | struct device *dev = hisi_hba->dev; | |
1631 | struct task_status_struct *ts; | |
1632 | struct domain_device *device; | |
68e6bace | 1633 | struct sas_ha_struct *ha; |
60b4a5ee XC |
1634 | enum exec_status sts; |
1635 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
1636 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
1637 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
1638 | &complete_queue[slot->cmplt_queue_slot]; | |
60b4a5ee | 1639 | unsigned long flags; |
68e6bace | 1640 | bool is_internal = slot->is_internal; |
60b4a5ee XC |
1641 | |
1642 | if (unlikely(!task || !task->lldd_task || !task->dev)) | |
1643 | return -EINVAL; | |
1644 | ||
1645 | ts = &task->task_status; | |
1646 | device = task->dev; | |
68e6bace | 1647 | ha = device->port->ha; |
60b4a5ee XC |
1648 | sas_dev = device->lldd_dev; |
1649 | ||
1650 | spin_lock_irqsave(&task->task_state_lock, flags); | |
60b4a5ee XC |
1651 | task->task_state_flags &= |
1652 | ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); | |
1653 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
1654 | ||
1655 | memset(ts, 0, sizeof(*ts)); | |
1656 | ts->resp = SAS_TASK_COMPLETE; | |
60b4a5ee XC |
1657 | |
1658 | if (unlikely(!sas_dev)) { | |
1659 | dev_dbg(dev, "slot complete: port has not device\n"); | |
1660 | ts->stat = SAS_PHY_DOWN; | |
1661 | goto out; | |
1662 | } | |
1663 | ||
1664 | /* | |
1665 | * Use SAS+TMF status codes | |
1666 | */ | |
1667 | switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK) | |
1668 | >> CMPLT_HDR_ABORT_STAT_OFF) { | |
1669 | case STAT_IO_ABORTED: | |
1670 | /* this IO has been aborted by abort command */ | |
1671 | ts->stat = SAS_ABORTED_TASK; | |
1672 | goto out; | |
1673 | case STAT_IO_COMPLETE: | |
1674 | /* internal abort command complete */ | |
1675 | ts->stat = TMF_RESP_FUNC_SUCC; | |
1676 | goto out; | |
1677 | case STAT_IO_NO_DEVICE: | |
1678 | ts->stat = TMF_RESP_FUNC_COMPLETE; | |
1679 | goto out; | |
1680 | case STAT_IO_NOT_VALID: | |
1681 | /* | |
1682 | * abort single IO, the controller can't find the IO | |
1683 | */ | |
1684 | ts->stat = TMF_RESP_FUNC_FAILED; | |
1685 | goto out; | |
1686 | default: | |
1687 | break; | |
1688 | } | |
1689 | ||
1690 | /* check for erroneous completion */ | |
1691 | if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { | |
081a1608 XC |
1692 | u32 *error_info = hisi_sas_status_buf_addr_mem(slot); |
1693 | ||
60b4a5ee | 1694 | slot_err_v3_hw(hisi_hba, task, slot); |
081a1608 | 1695 | if (ts->stat != SAS_DATA_UNDERRUN) |
ab2d8bd6 | 1696 | dev_info(dev, "erroneous completion iptt=%d task=%p dev id=%d " |
081a1608 XC |
1697 | "CQ hdr: 0x%x 0x%x 0x%x 0x%x " |
1698 | "Error info: 0x%x 0x%x 0x%x 0x%x\n", | |
ab2d8bd6 | 1699 | slot->idx, task, sas_dev->device_id, |
081a1608 XC |
1700 | complete_hdr->dw0, complete_hdr->dw1, |
1701 | complete_hdr->act, complete_hdr->dw3, | |
1702 | error_info[0], error_info[1], | |
1703 | error_info[2], error_info[3]); | |
60b4a5ee XC |
1704 | if (unlikely(slot->abort)) |
1705 | return ts->stat; | |
1706 | goto out; | |
1707 | } | |
1708 | ||
1709 | switch (task->task_proto) { | |
1710 | case SAS_PROTOCOL_SSP: { | |
f557e32c XT |
1711 | struct ssp_response_iu *iu = |
1712 | hisi_sas_status_buf_addr_mem(slot) + | |
60b4a5ee XC |
1713 | sizeof(struct hisi_sas_err_record); |
1714 | ||
1715 | sas_ssp_task_response(dev, task, iu); | |
1716 | break; | |
1717 | } | |
1718 | case SAS_PROTOCOL_SMP: { | |
1719 | struct scatterlist *sg_resp = &task->smp_task.smp_resp; | |
1720 | void *to; | |
1721 | ||
1722 | ts->stat = SAM_STAT_GOOD; | |
1723 | to = kmap_atomic(sg_page(sg_resp)); | |
1724 | ||
1725 | dma_unmap_sg(dev, &task->smp_task.smp_resp, 1, | |
1726 | DMA_FROM_DEVICE); | |
1727 | dma_unmap_sg(dev, &task->smp_task.smp_req, 1, | |
1728 | DMA_TO_DEVICE); | |
1729 | memcpy(to + sg_resp->offset, | |
f557e32c | 1730 | hisi_sas_status_buf_addr_mem(slot) + |
60b4a5ee XC |
1731 | sizeof(struct hisi_sas_err_record), |
1732 | sg_dma_len(sg_resp)); | |
1733 | kunmap_atomic(to); | |
1734 | break; | |
1735 | } | |
1736 | case SAS_PROTOCOL_SATA: | |
1737 | case SAS_PROTOCOL_STP: | |
1738 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
1739 | ts->stat = SAM_STAT_GOOD; | |
1740 | hisi_sas_sata_done(task, slot); | |
1741 | break; | |
1742 | default: | |
1743 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
1744 | break; | |
1745 | } | |
1746 | ||
1747 | if (!slot->port->port_attached) { | |
081a1608 | 1748 | dev_warn(dev, "slot complete: port %d has removed\n", |
60b4a5ee XC |
1749 | slot->port->sas_port.id); |
1750 | ts->stat = SAS_PHY_DOWN; | |
1751 | } | |
1752 | ||
1753 | out: | |
52ed2bba XC |
1754 | hisi_sas_slot_task_free(hisi_hba, task, slot); |
1755 | sts = ts->stat; | |
60b4a5ee | 1756 | spin_lock_irqsave(&task->task_state_lock, flags); |
52ed2bba XC |
1757 | if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { |
1758 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
1759 | dev_info(dev, "slot complete: task(%p) aborted\n", task); | |
1760 | return SAS_ABORTED_TASK; | |
1761 | } | |
60b4a5ee XC |
1762 | task->task_state_flags |= SAS_TASK_STATE_DONE; |
1763 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
60b4a5ee | 1764 | |
68e6bace XC |
1765 | if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { |
1766 | spin_lock_irqsave(&device->done_lock, flags); | |
1767 | if (test_bit(SAS_HA_FROZEN, &ha->state)) { | |
1768 | spin_unlock_irqrestore(&device->done_lock, flags); | |
1769 | dev_info(dev, "slot complete: task(%p) ignored\n ", | |
1770 | task); | |
1771 | return sts; | |
1772 | } | |
1773 | spin_unlock_irqrestore(&device->done_lock, flags); | |
1774 | } | |
1775 | ||
60b4a5ee XC |
1776 | if (task->task_done) |
1777 | task->task_done(task); | |
1778 | ||
1779 | return sts; | |
1780 | } | |
1781 | ||
1782 | static void cq_tasklet_v3_hw(unsigned long val) | |
1783 | { | |
1784 | struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; | |
1785 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
1786 | struct hisi_sas_slot *slot; | |
60b4a5ee | 1787 | struct hisi_sas_complete_v3_hdr *complete_queue; |
ee076d5b | 1788 | u32 rd_point = cq->rd_point, wr_point; |
60b4a5ee | 1789 | int queue = cq->id; |
60b4a5ee XC |
1790 | |
1791 | complete_queue = hisi_hba->complete_hdr[queue]; | |
1792 | ||
60b4a5ee XC |
1793 | wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + |
1794 | (0x14 * queue)); | |
1795 | ||
1796 | while (rd_point != wr_point) { | |
1797 | struct hisi_sas_complete_v3_hdr *complete_hdr; | |
e812cf8c | 1798 | struct device *dev = hisi_hba->dev; |
60b4a5ee XC |
1799 | int iptt; |
1800 | ||
1801 | complete_hdr = &complete_queue[rd_point]; | |
1802 | ||
ee076d5b | 1803 | iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK; |
e812cf8c XT |
1804 | if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { |
1805 | slot = &hisi_hba->slot_info[iptt]; | |
1806 | slot->cmplt_queue_slot = rd_point; | |
1807 | slot->cmplt_queue = queue; | |
1808 | slot_complete_v3_hw(hisi_hba, slot); | |
1809 | } else | |
1810 | dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); | |
60b4a5ee XC |
1811 | |
1812 | if (++rd_point >= HISI_SAS_QUEUE_SLOTS) | |
1813 | rd_point = 0; | |
1814 | } | |
1815 | ||
1816 | /* update rd_point */ | |
1817 | cq->rd_point = rd_point; | |
1818 | hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); | |
60b4a5ee XC |
1819 | } |
1820 | ||
1821 | static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) | |
1822 | { | |
1823 | struct hisi_sas_cq *cq = p; | |
1824 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
1825 | int queue = cq->id; | |
1826 | ||
1827 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); | |
1828 | ||
1829 | tasklet_schedule(&cq->tasklet); | |
1830 | ||
1831 | return IRQ_HANDLED; | |
1832 | } | |
1833 | ||
54edeee1 XC |
1834 | static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) |
1835 | { | |
1836 | struct device *dev = hisi_hba->dev; | |
1837 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
1838 | int vectors, rc; | |
60b4a5ee | 1839 | int i, k; |
54edeee1 XC |
1840 | int max_msi = HISI_SAS_MSI_COUNT_V3_HW; |
1841 | ||
1842 | vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1, | |
1843 | max_msi, PCI_IRQ_MSI); | |
1844 | if (vectors < max_msi) { | |
1845 | dev_err(dev, "could not allocate all msi (%d)\n", vectors); | |
1846 | return -ENOENT; | |
1847 | } | |
1848 | ||
1849 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), | |
1850 | int_phy_up_down_bcast_v3_hw, 0, | |
1851 | DRV_NAME " phy", hisi_hba); | |
1852 | if (rc) { | |
1853 | dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); | |
1854 | rc = -ENOENT; | |
1855 | goto free_irq_vectors; | |
1856 | } | |
1857 | ||
1858 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), | |
1859 | int_chnl_int_v3_hw, 0, | |
1860 | DRV_NAME " channel", hisi_hba); | |
1861 | if (rc) { | |
1862 | dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); | |
1863 | rc = -ENOENT; | |
1864 | goto free_phy_irq; | |
1865 | } | |
1866 | ||
fa231408 XT |
1867 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), |
1868 | fatal_axi_int_v3_hw, 0, | |
1869 | DRV_NAME " fatal", hisi_hba); | |
1870 | if (rc) { | |
1871 | dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); | |
1872 | rc = -ENOENT; | |
1873 | goto free_chnl_interrupt; | |
1874 | } | |
1875 | ||
60b4a5ee XC |
1876 | /* Init tasklets for cq only */ |
1877 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
1878 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; | |
1879 | struct tasklet_struct *t = &cq->tasklet; | |
1880 | ||
1881 | rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16), | |
1882 | cq_interrupt_v3_hw, 0, | |
1883 | DRV_NAME " cq", cq); | |
1884 | if (rc) { | |
1885 | dev_err(dev, | |
1886 | "could not request cq%d interrupt, rc=%d\n", | |
1887 | i, rc); | |
1888 | rc = -ENOENT; | |
1889 | goto free_cq_irqs; | |
1890 | } | |
1891 | ||
1892 | tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); | |
1893 | } | |
54edeee1 XC |
1894 | |
1895 | return 0; | |
1896 | ||
60b4a5ee XC |
1897 | free_cq_irqs: |
1898 | for (k = 0; k < i; k++) { | |
1899 | struct hisi_sas_cq *cq = &hisi_hba->cq[k]; | |
1900 | ||
1901 | free_irq(pci_irq_vector(pdev, k+16), cq); | |
1902 | } | |
fa231408 XT |
1903 | free_irq(pci_irq_vector(pdev, 11), hisi_hba); |
1904 | free_chnl_interrupt: | |
60b4a5ee | 1905 | free_irq(pci_irq_vector(pdev, 2), hisi_hba); |
54edeee1 XC |
1906 | free_phy_irq: |
1907 | free_irq(pci_irq_vector(pdev, 1), hisi_hba); | |
1908 | free_irq_vectors: | |
1909 | pci_free_irq_vectors(pdev); | |
1910 | return rc; | |
1911 | } | |
1912 | ||
c94d8ca2 XC |
1913 | static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) |
1914 | { | |
1915 | int rc; | |
1916 | ||
1917 | rc = hw_init_v3_hw(hisi_hba); | |
1918 | if (rc) | |
1919 | return rc; | |
1920 | ||
54edeee1 XC |
1921 | rc = interrupt_init_v3_hw(hisi_hba); |
1922 | if (rc) | |
1923 | return rc; | |
1924 | ||
c94d8ca2 XC |
1925 | return 0; |
1926 | } | |
1927 | ||
2400620c XC |
1928 | static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, |
1929 | struct sas_phy_linkrates *r) | |
1930 | { | |
2400620c XC |
1931 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; |
1932 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
2400620c | 1933 | enum sas_linkrate min, max; |
f385b4ff | 1934 | u32 prog_phy_link_rate = 0x800; |
2400620c XC |
1935 | |
1936 | if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) { | |
1937 | max = sas_phy->phy->maximum_linkrate; | |
1938 | min = r->minimum_linkrate; | |
1939 | } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) { | |
1940 | max = r->maximum_linkrate; | |
1941 | min = sas_phy->phy->minimum_linkrate; | |
1942 | } else | |
1943 | return; | |
1944 | ||
1945 | sas_phy->phy->maximum_linkrate = max; | |
1946 | sas_phy->phy->minimum_linkrate = min; | |
f385b4ff | 1947 | prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); |
2400620c | 1948 | |
5dcac3a4 XT |
1949 | disable_phy_v3_hw(hisi_hba, phy_no); |
1950 | msleep(100); | |
2400620c XC |
1951 | hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, |
1952 | prog_phy_link_rate); | |
5dcac3a4 | 1953 | start_phy_v3_hw(hisi_hba, phy_no); |
2400620c XC |
1954 | } |
1955 | ||
a25d0d3d XC |
1956 | static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) |
1957 | { | |
1958 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
1959 | int i; | |
1960 | ||
1961 | synchronize_irq(pci_irq_vector(pdev, 1)); | |
1962 | synchronize_irq(pci_irq_vector(pdev, 2)); | |
1963 | synchronize_irq(pci_irq_vector(pdev, 11)); | |
1964 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
1965 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); | |
1966 | synchronize_irq(pci_irq_vector(pdev, i + 16)); | |
1967 | } | |
1968 | ||
1969 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); | |
1970 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); | |
1971 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); | |
1972 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); | |
1973 | ||
1974 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
1975 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); | |
1976 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); | |
1977 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); | |
1978 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); | |
1979 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); | |
1980 | } | |
1981 | } | |
1982 | ||
1983 | static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) | |
1984 | { | |
1985 | return hisi_sas_read32(hisi_hba, PHY_STATE); | |
1986 | } | |
1987 | ||
ffc8f149 XT |
1988 | static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
1989 | { | |
1990 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1991 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1992 | struct sas_phy *sphy = sas_phy->phy; | |
1993 | u32 reg_value; | |
1994 | ||
1995 | /* loss dword sync */ | |
1996 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); | |
1997 | sphy->loss_of_dword_sync_count += reg_value; | |
1998 | ||
1999 | /* phy reset problem */ | |
2000 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); | |
2001 | sphy->phy_reset_problem_count += reg_value; | |
2002 | ||
2003 | /* invalid dword */ | |
2004 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); | |
2005 | sphy->invalid_dword_count += reg_value; | |
2006 | ||
2007 | /* disparity err */ | |
2008 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); | |
2009 | sphy->running_disparity_error_count += reg_value; | |
2010 | ||
2011 | } | |
2012 | ||
1d51757d | 2013 | static int disable_host_v3_hw(struct hisi_hba *hisi_hba) |
a25d0d3d XC |
2014 | { |
2015 | struct device *dev = hisi_hba->dev; | |
1d51757d | 2016 | u32 status, reg_val; |
a25d0d3d | 2017 | int rc; |
a25d0d3d XC |
2018 | |
2019 | interrupt_disable_v3_hw(hisi_hba); | |
2020 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); | |
571295f8 | 2021 | hisi_sas_kill_tasklets(hisi_hba); |
a25d0d3d XC |
2022 | |
2023 | hisi_sas_stop_phys(hisi_hba); | |
2024 | ||
2025 | mdelay(10); | |
2026 | ||
1d51757d XT |
2027 | reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + |
2028 | AM_CTRL_GLOBAL); | |
2029 | reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; | |
2030 | hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + | |
2031 | AM_CTRL_GLOBAL, reg_val); | |
a25d0d3d XC |
2032 | |
2033 | /* wait until bus idle */ | |
70bfdcae JG |
2034 | rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + |
2035 | AM_CURR_TRANS_RETURN, status, | |
2036 | status == 0x3, 10, 100); | |
a25d0d3d | 2037 | if (rc) { |
1d51757d XT |
2038 | dev_err(dev, "axi bus is not idle, rc=%d\n", rc); |
2039 | return rc; | |
2040 | } | |
2041 | ||
2042 | return 0; | |
2043 | } | |
2044 | ||
2045 | static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) | |
2046 | { | |
2047 | struct device *dev = hisi_hba->dev; | |
2048 | int rc; | |
2049 | ||
2050 | rc = disable_host_v3_hw(hisi_hba); | |
2051 | if (rc) { | |
2052 | dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); | |
a25d0d3d XC |
2053 | return rc; |
2054 | } | |
2055 | ||
2056 | hisi_sas_init_mem(hisi_hba); | |
2057 | ||
2058 | return hw_init_v3_hw(hisi_hba); | |
2059 | } | |
2060 | ||
e24fe507 XT |
2061 | static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, |
2062 | u8 reg_index, u8 reg_count, u8 *write_data) | |
2063 | { | |
2064 | struct device *dev = hisi_hba->dev; | |
2065 | u32 *data = (u32 *)write_data; | |
2066 | int i; | |
2067 | ||
2068 | switch (reg_type) { | |
2069 | case SAS_GPIO_REG_TX: | |
2070 | if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { | |
2071 | dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", | |
2072 | reg_index, reg_index + reg_count - 1); | |
2073 | return -EINVAL; | |
2074 | } | |
2075 | ||
2076 | for (i = 0; i < reg_count; i++) | |
2077 | hisi_sas_write32(hisi_hba, | |
2078 | SAS_GPIO_TX_0_1 + (reg_index + i) * 4, | |
2079 | data[i]); | |
2080 | break; | |
2081 | default: | |
2082 | dev_err(dev, "write gpio: unsupported or bad reg type %d\n", | |
2083 | reg_type); | |
2084 | return -EINVAL; | |
2085 | } | |
2086 | ||
2087 | return 0; | |
2088 | } | |
2089 | ||
1a7068b3 XT |
2090 | static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, |
2091 | int delay_ms, int timeout_ms) | |
2092 | { | |
2093 | struct device *dev = hisi_hba->dev; | |
2094 | int entries, entries_old = 0, time; | |
2095 | ||
2096 | for (time = 0; time < timeout_ms; time += delay_ms) { | |
2097 | entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); | |
2098 | if (entries == entries_old) | |
2099 | break; | |
2100 | ||
2101 | entries_old = entries; | |
2102 | msleep(delay_ms); | |
2103 | } | |
2104 | ||
2105 | dev_dbg(dev, "wait commands complete %dms\n", time); | |
2106 | } | |
2107 | ||
b1793064 XC |
2108 | static struct scsi_host_template sht_v3_hw = { |
2109 | .name = DRV_NAME, | |
2110 | .module = THIS_MODULE, | |
2111 | .queuecommand = sas_queuecommand, | |
2112 | .target_alloc = sas_target_alloc, | |
2113 | .slave_configure = hisi_sas_slave_configure, | |
2114 | .scan_finished = hisi_sas_scan_finished, | |
2115 | .scan_start = hisi_sas_scan_start, | |
2116 | .change_queue_depth = sas_change_queue_depth, | |
2117 | .bios_param = sas_bios_param, | |
2118 | .can_queue = 1, | |
2119 | .this_id = -1, | |
2120 | .sg_tablesize = SG_ALL, | |
2121 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, | |
2122 | .use_clustering = ENABLE_CLUSTERING, | |
2123 | .eh_device_reset_handler = sas_eh_device_reset_handler, | |
2124 | .eh_target_reset_handler = sas_eh_target_reset_handler, | |
2125 | .target_destroy = sas_target_destroy, | |
2126 | .ioctl = sas_ioctl, | |
2127 | .shost_attrs = host_attrs, | |
2128 | }; | |
2129 | ||
e21fe3a5 | 2130 | static const struct hisi_sas_hw hisi_sas_v3_hw = { |
c94d8ca2 | 2131 | .hw_init = hisi_sas_v3_init, |
182e7222 | 2132 | .setup_itct = setup_itct_v3_hw, |
c94d8ca2 | 2133 | .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW, |
f771d3b0 | 2134 | .get_wideport_bitmap = get_wideport_bitmap_v3_hw, |
c94d8ca2 | 2135 | .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), |
f39943ee | 2136 | .clear_itct = clear_itct_v3_hw, |
3975f605 | 2137 | .sl_notify = sl_notify_v3_hw, |
a2204723 | 2138 | .prep_ssp = prep_ssp_v3_hw, |
fa913de2 | 2139 | .prep_smp = prep_smp_v3_hw, |
ce60689e | 2140 | .prep_stp = prep_ata_v3_hw, |
4de0ca69 | 2141 | .prep_abort = prep_abort_v3_hw, |
a2204723 XC |
2142 | .get_free_slot = get_free_slot_v3_hw, |
2143 | .start_delivery = start_delivery_v3_hw, | |
2144 | .slot_complete = slot_complete_v3_hw, | |
3975f605 | 2145 | .phys_init = phys_init_v3_hw, |
1eb8eeac | 2146 | .phy_start = start_phy_v3_hw, |
402cd9f0 XC |
2147 | .phy_disable = disable_phy_v3_hw, |
2148 | .phy_hard_reset = phy_hard_reset_v3_hw, | |
2149 | .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, | |
2400620c | 2150 | .phy_set_linkrate = phy_set_linkrate_v3_hw, |
d30ff263 | 2151 | .dereg_device = dereg_device_v3_hw, |
a25d0d3d XC |
2152 | .soft_reset = soft_reset_v3_hw, |
2153 | .get_phys_state = get_phys_state_v3_hw, | |
ffc8f149 | 2154 | .get_events = phy_get_events_v3_hw, |
e24fe507 | 2155 | .write_gpio = write_gpio_v3_hw, |
1a7068b3 | 2156 | .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, |
e21fe3a5 JG |
2157 | }; |
2158 | ||
2159 | static struct Scsi_Host * | |
2160 | hisi_sas_shost_alloc_pci(struct pci_dev *pdev) | |
2161 | { | |
2162 | struct Scsi_Host *shost; | |
2163 | struct hisi_hba *hisi_hba; | |
2164 | struct device *dev = &pdev->dev; | |
2165 | ||
b1793064 | 2166 | shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); |
76aae5f6 JG |
2167 | if (!shost) { |
2168 | dev_err(dev, "shost alloc failed\n"); | |
2169 | return NULL; | |
2170 | } | |
e21fe3a5 JG |
2171 | hisi_hba = shost_priv(shost); |
2172 | ||
b4241f0f | 2173 | INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); |
e21fe3a5 JG |
2174 | hisi_hba->hw = &hisi_sas_v3_hw; |
2175 | hisi_hba->pci_dev = pdev; | |
2176 | hisi_hba->dev = dev; | |
2177 | hisi_hba->shost = shost; | |
2178 | SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; | |
2179 | ||
77570eed | 2180 | timer_setup(&hisi_hba->timer, NULL, 0); |
e21fe3a5 JG |
2181 | |
2182 | if (hisi_sas_get_fw_info(hisi_hba) < 0) | |
2183 | goto err_out; | |
2184 | ||
2185 | if (hisi_sas_alloc(hisi_hba, shost)) { | |
2186 | hisi_sas_free(hisi_hba); | |
2187 | goto err_out; | |
2188 | } | |
2189 | ||
2190 | return shost; | |
2191 | err_out: | |
76aae5f6 | 2192 | scsi_host_put(shost); |
e21fe3a5 JG |
2193 | dev_err(dev, "shost alloc failed\n"); |
2194 | return NULL; | |
2195 | } | |
2196 | ||
92f61e3b JG |
2197 | static int |
2198 | hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
2199 | { | |
e21fe3a5 JG |
2200 | struct Scsi_Host *shost; |
2201 | struct hisi_hba *hisi_hba; | |
2202 | struct device *dev = &pdev->dev; | |
2203 | struct asd_sas_phy **arr_phy; | |
2204 | struct asd_sas_port **arr_port; | |
2205 | struct sas_ha_struct *sha; | |
2206 | int rc, phy_nr, port_nr, i; | |
2207 | ||
2208 | rc = pci_enable_device(pdev); | |
2209 | if (rc) | |
2210 | goto err_out; | |
2211 | ||
2212 | pci_set_master(pdev); | |
2213 | ||
2214 | rc = pci_request_regions(pdev, DRV_NAME); | |
2215 | if (rc) | |
2216 | goto err_out_disable_device; | |
2217 | ||
2218 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || | |
2219 | (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { | |
2220 | if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || | |
2221 | (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) { | |
2222 | dev_err(dev, "No usable DMA addressing method\n"); | |
2223 | rc = -EIO; | |
2224 | goto err_out_regions; | |
2225 | } | |
2226 | } | |
2227 | ||
2228 | shost = hisi_sas_shost_alloc_pci(pdev); | |
2229 | if (!shost) { | |
2230 | rc = -ENOMEM; | |
2231 | goto err_out_regions; | |
2232 | } | |
2233 | ||
2234 | sha = SHOST_TO_SAS_HA(shost); | |
2235 | hisi_hba = shost_priv(shost); | |
2236 | dev_set_drvdata(dev, sha); | |
2237 | ||
2238 | hisi_hba->regs = pcim_iomap(pdev, 5, 0); | |
2239 | if (!hisi_hba->regs) { | |
2240 | dev_err(dev, "cannot map register.\n"); | |
2241 | rc = -ENOMEM; | |
2242 | goto err_out_ha; | |
2243 | } | |
2244 | ||
2245 | phy_nr = port_nr = hisi_hba->n_phy; | |
2246 | ||
2247 | arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); | |
2248 | arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); | |
2249 | if (!arr_phy || !arr_port) { | |
2250 | rc = -ENOMEM; | |
2251 | goto err_out_ha; | |
2252 | } | |
2253 | ||
2254 | sha->sas_phy = arr_phy; | |
2255 | sha->sas_port = arr_port; | |
2256 | sha->core.shost = shost; | |
2257 | sha->lldd_ha = hisi_hba; | |
2258 | ||
2259 | shost->transportt = hisi_sas_stt; | |
2260 | shost->max_id = HISI_SAS_MAX_DEVICES; | |
2261 | shost->max_lun = ~0; | |
2262 | shost->max_channel = 1; | |
2263 | shost->max_cmd_len = 16; | |
2264 | shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT); | |
2265 | shost->can_queue = hisi_hba->hw->max_command_entries; | |
2266 | shost->cmd_per_lun = hisi_hba->hw->max_command_entries; | |
2267 | ||
2268 | sha->sas_ha_name = DRV_NAME; | |
2269 | sha->dev = dev; | |
2270 | sha->lldd_module = THIS_MODULE; | |
2271 | sha->sas_addr = &hisi_hba->sas_addr[0]; | |
2272 | sha->num_phys = hisi_hba->n_phy; | |
2273 | sha->core.shost = hisi_hba->shost; | |
2274 | ||
2275 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
2276 | sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; | |
2277 | sha->sas_port[i] = &hisi_hba->port[i].sas_port; | |
2278 | } | |
2279 | ||
e21fe3a5 JG |
2280 | rc = scsi_add_host(shost, dev); |
2281 | if (rc) | |
2282 | goto err_out_ha; | |
2283 | ||
2284 | rc = sas_register_ha(sha); | |
2285 | if (rc) | |
2286 | goto err_out_register_ha; | |
2287 | ||
2288 | rc = hisi_hba->hw->hw_init(hisi_hba); | |
2289 | if (rc) | |
2290 | goto err_out_register_ha; | |
2291 | ||
2292 | scsi_scan_host(shost); | |
2293 | ||
92f61e3b | 2294 | return 0; |
e21fe3a5 JG |
2295 | |
2296 | err_out_register_ha: | |
2297 | scsi_remove_host(shost); | |
2298 | err_out_ha: | |
76aae5f6 | 2299 | scsi_host_put(shost); |
e21fe3a5 JG |
2300 | err_out_regions: |
2301 | pci_release_regions(pdev); | |
2302 | err_out_disable_device: | |
2303 | pci_disable_device(pdev); | |
2304 | err_out: | |
2305 | return rc; | |
92f61e3b JG |
2306 | } |
2307 | ||
54edeee1 XC |
2308 | static void |
2309 | hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) | |
2310 | { | |
60b4a5ee XC |
2311 | int i; |
2312 | ||
54edeee1 XC |
2313 | free_irq(pci_irq_vector(pdev, 1), hisi_hba); |
2314 | free_irq(pci_irq_vector(pdev, 2), hisi_hba); | |
fa231408 | 2315 | free_irq(pci_irq_vector(pdev, 11), hisi_hba); |
60b4a5ee XC |
2316 | for (i = 0; i < hisi_hba->queue_count; i++) { |
2317 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; | |
2318 | ||
2319 | free_irq(pci_irq_vector(pdev, i+16), cq); | |
2320 | } | |
54edeee1 XC |
2321 | pci_free_irq_vectors(pdev); |
2322 | } | |
2323 | ||
92f61e3b JG |
2324 | static void hisi_sas_v3_remove(struct pci_dev *pdev) |
2325 | { | |
e21fe3a5 JG |
2326 | struct device *dev = &pdev->dev; |
2327 | struct sas_ha_struct *sha = dev_get_drvdata(dev); | |
2328 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
76aae5f6 | 2329 | struct Scsi_Host *shost = sha->core.shost; |
e21fe3a5 | 2330 | |
a417a9c1 XC |
2331 | if (timer_pending(&hisi_hba->timer)) |
2332 | del_timer(&hisi_hba->timer); | |
2333 | ||
e21fe3a5 JG |
2334 | sas_unregister_ha(sha); |
2335 | sas_remove_host(sha->core.shost); | |
2336 | ||
54edeee1 | 2337 | hisi_sas_v3_destroy_irqs(pdev, hisi_hba); |
571295f8 | 2338 | hisi_sas_kill_tasklets(hisi_hba); |
e21fe3a5 JG |
2339 | pci_release_regions(pdev); |
2340 | pci_disable_device(pdev); | |
76aae5f6 JG |
2341 | hisi_sas_free(hisi_hba); |
2342 | scsi_host_put(shost); | |
92f61e3b JG |
2343 | } |
2344 | ||
56b72168 XT |
2345 | static const struct hisi_sas_hw_error sas_ras_intr0_nfe[] = { |
2346 | { .irq_msk = BIT(19), .msg = "HILINK_INT" }, | |
2347 | { .irq_msk = BIT(20), .msg = "HILINK_PLL0_OUT_OF_LOCK" }, | |
2348 | { .irq_msk = BIT(21), .msg = "HILINK_PLL1_OUT_OF_LOCK" }, | |
2349 | { .irq_msk = BIT(22), .msg = "HILINK_LOSS_OF_REFCLK0" }, | |
2350 | { .irq_msk = BIT(23), .msg = "HILINK_LOSS_OF_REFCLK1" }, | |
2351 | { .irq_msk = BIT(24), .msg = "DMAC0_TX_POISON" }, | |
2352 | { .irq_msk = BIT(25), .msg = "DMAC1_TX_POISON" }, | |
2353 | { .irq_msk = BIT(26), .msg = "DMAC2_TX_POISON" }, | |
2354 | { .irq_msk = BIT(27), .msg = "DMAC3_TX_POISON" }, | |
2355 | { .irq_msk = BIT(28), .msg = "DMAC4_TX_POISON" }, | |
2356 | { .irq_msk = BIT(29), .msg = "DMAC5_TX_POISON" }, | |
2357 | { .irq_msk = BIT(30), .msg = "DMAC6_TX_POISON" }, | |
2358 | { .irq_msk = BIT(31), .msg = "DMAC7_TX_POISON" }, | |
2359 | }; | |
2360 | ||
2361 | static const struct hisi_sas_hw_error sas_ras_intr1_nfe[] = { | |
2362 | { .irq_msk = BIT(0), .msg = "RXM_CFG_MEM3_ECC2B_INTR" }, | |
2363 | { .irq_msk = BIT(1), .msg = "RXM_CFG_MEM2_ECC2B_INTR" }, | |
2364 | { .irq_msk = BIT(2), .msg = "RXM_CFG_MEM1_ECC2B_INTR" }, | |
2365 | { .irq_msk = BIT(3), .msg = "RXM_CFG_MEM0_ECC2B_INTR" }, | |
2366 | { .irq_msk = BIT(4), .msg = "HGC_CQE_ECC2B_INTR" }, | |
2367 | { .irq_msk = BIT(5), .msg = "LM_CFG_IOSTL_ECC2B_INTR" }, | |
2368 | { .irq_msk = BIT(6), .msg = "LM_CFG_ITCTL_ECC2B_INTR" }, | |
2369 | { .irq_msk = BIT(7), .msg = "HGC_ITCT_ECC2B_INTR" }, | |
2370 | { .irq_msk = BIT(8), .msg = "HGC_IOST_ECC2B_INTR" }, | |
2371 | { .irq_msk = BIT(9), .msg = "HGC_DQE_ECC2B_INTR" }, | |
2372 | { .irq_msk = BIT(10), .msg = "DMAC0_RAM_ECC2B_INTR" }, | |
2373 | { .irq_msk = BIT(11), .msg = "DMAC1_RAM_ECC2B_INTR" }, | |
2374 | { .irq_msk = BIT(12), .msg = "DMAC2_RAM_ECC2B_INTR" }, | |
2375 | { .irq_msk = BIT(13), .msg = "DMAC3_RAM_ECC2B_INTR" }, | |
2376 | { .irq_msk = BIT(14), .msg = "DMAC4_RAM_ECC2B_INTR" }, | |
2377 | { .irq_msk = BIT(15), .msg = "DMAC5_RAM_ECC2B_INTR" }, | |
2378 | { .irq_msk = BIT(16), .msg = "DMAC6_RAM_ECC2B_INTR" }, | |
2379 | { .irq_msk = BIT(17), .msg = "DMAC7_RAM_ECC2B_INTR" }, | |
2380 | { .irq_msk = BIT(18), .msg = "OOO_RAM_ECC2B_INTR" }, | |
2381 | { .irq_msk = BIT(20), .msg = "HGC_DQE_POISON_INTR" }, | |
2382 | { .irq_msk = BIT(21), .msg = "HGC_IOST_POISON_INTR" }, | |
2383 | { .irq_msk = BIT(22), .msg = "HGC_ITCT_POISON_INTR" }, | |
2384 | { .irq_msk = BIT(23), .msg = "HGC_ITCT_NCQ_POISON_INTR" }, | |
2385 | { .irq_msk = BIT(24), .msg = "DMAC0_RX_POISON" }, | |
2386 | { .irq_msk = BIT(25), .msg = "DMAC1_RX_POISON" }, | |
2387 | { .irq_msk = BIT(26), .msg = "DMAC2_RX_POISON" }, | |
2388 | { .irq_msk = BIT(27), .msg = "DMAC3_RX_POISON" }, | |
2389 | { .irq_msk = BIT(28), .msg = "DMAC4_RX_POISON" }, | |
2390 | { .irq_msk = BIT(29), .msg = "DMAC5_RX_POISON" }, | |
2391 | { .irq_msk = BIT(30), .msg = "DMAC6_RX_POISON" }, | |
2392 | { .irq_msk = BIT(31), .msg = "DMAC7_RX_POISON" }, | |
2393 | }; | |
2394 | ||
c13c7ac5 XT |
2395 | static const struct hisi_sas_hw_error sas_ras_intr2_nfe[] = { |
2396 | { .irq_msk = BIT(0), .msg = "DMAC0_AXI_BUS_ERR" }, | |
2397 | { .irq_msk = BIT(1), .msg = "DMAC1_AXI_BUS_ERR" }, | |
2398 | { .irq_msk = BIT(2), .msg = "DMAC2_AXI_BUS_ERR" }, | |
2399 | { .irq_msk = BIT(3), .msg = "DMAC3_AXI_BUS_ERR" }, | |
2400 | { .irq_msk = BIT(4), .msg = "DMAC4_AXI_BUS_ERR" }, | |
2401 | { .irq_msk = BIT(5), .msg = "DMAC5_AXI_BUS_ERR" }, | |
2402 | { .irq_msk = BIT(6), .msg = "DMAC6_AXI_BUS_ERR" }, | |
2403 | { .irq_msk = BIT(7), .msg = "DMAC7_AXI_BUS_ERR" }, | |
2404 | { .irq_msk = BIT(8), .msg = "DMAC0_FIFO_OMIT_ERR" }, | |
2405 | { .irq_msk = BIT(9), .msg = "DMAC1_FIFO_OMIT_ERR" }, | |
2406 | { .irq_msk = BIT(10), .msg = "DMAC2_FIFO_OMIT_ERR" }, | |
2407 | { .irq_msk = BIT(11), .msg = "DMAC3_FIFO_OMIT_ERR" }, | |
2408 | { .irq_msk = BIT(12), .msg = "DMAC4_FIFO_OMIT_ERR" }, | |
2409 | { .irq_msk = BIT(13), .msg = "DMAC5_FIFO_OMIT_ERR" }, | |
2410 | { .irq_msk = BIT(14), .msg = "DMAC6_FIFO_OMIT_ERR" }, | |
2411 | { .irq_msk = BIT(15), .msg = "DMAC7_FIFO_OMIT_ERR" }, | |
2412 | { .irq_msk = BIT(16), .msg = "HGC_RLSE_SLOT_UNMATCH" }, | |
2413 | { .irq_msk = BIT(17), .msg = "HGC_LM_ADD_FCH_LIST_ERR" }, | |
2414 | { .irq_msk = BIT(18), .msg = "HGC_AXI_BUS_ERR" }, | |
2415 | { .irq_msk = BIT(19), .msg = "HGC_FIFO_OMIT_ERR" }, | |
2416 | }; | |
2417 | ||
56b72168 XT |
2418 | static bool process_non_fatal_error_v3_hw(struct hisi_hba *hisi_hba) |
2419 | { | |
2420 | struct device *dev = hisi_hba->dev; | |
2421 | const struct hisi_sas_hw_error *ras_error; | |
2422 | bool need_reset = false; | |
2423 | u32 irq_value; | |
2424 | int i; | |
2425 | ||
2426 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR0); | |
2427 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr0_nfe); i++) { | |
2428 | ras_error = &sas_ras_intr0_nfe[i]; | |
2429 | if (ras_error->irq_msk & irq_value) { | |
2430 | dev_warn(dev, "SAS_RAS_INTR0: %s(irq_value=0x%x) found.\n", | |
2431 | ras_error->msg, irq_value); | |
2432 | need_reset = true; | |
2433 | } | |
2434 | } | |
2435 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR0, irq_value); | |
2436 | ||
2437 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR1); | |
2438 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr1_nfe); i++) { | |
2439 | ras_error = &sas_ras_intr1_nfe[i]; | |
2440 | if (ras_error->irq_msk & irq_value) { | |
2441 | dev_warn(dev, "SAS_RAS_INTR1: %s(irq_value=0x%x) found.\n", | |
2442 | ras_error->msg, irq_value); | |
2443 | need_reset = true; | |
2444 | } | |
2445 | } | |
2446 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR1, irq_value); | |
2447 | ||
c13c7ac5 XT |
2448 | irq_value = hisi_sas_read32(hisi_hba, SAS_RAS_INTR2); |
2449 | for (i = 0; i < ARRAY_SIZE(sas_ras_intr2_nfe); i++) { | |
2450 | ras_error = &sas_ras_intr2_nfe[i]; | |
2451 | if (ras_error->irq_msk & irq_value) { | |
2452 | dev_warn(dev, "SAS_RAS_INTR2: %s(irq_value=0x%x) found.\n", | |
2453 | ras_error->msg, irq_value); | |
2454 | need_reset = true; | |
2455 | } | |
2456 | } | |
2457 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR2, irq_value); | |
2458 | ||
56b72168 XT |
2459 | return need_reset; |
2460 | } | |
2461 | ||
2462 | static pci_ers_result_t hisi_sas_error_detected_v3_hw(struct pci_dev *pdev, | |
2463 | pci_channel_state_t state) | |
2464 | { | |
2465 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2466 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2467 | struct device *dev = hisi_hba->dev; | |
2468 | ||
2469 | dev_info(dev, "PCI error: detected callback, state(%d)!!\n", state); | |
2470 | if (state == pci_channel_io_perm_failure) | |
2471 | return PCI_ERS_RESULT_DISCONNECT; | |
2472 | ||
2473 | if (process_non_fatal_error_v3_hw(hisi_hba)) | |
2474 | return PCI_ERS_RESULT_NEED_RESET; | |
2475 | ||
2476 | return PCI_ERS_RESULT_CAN_RECOVER; | |
2477 | } | |
2478 | ||
2479 | static pci_ers_result_t hisi_sas_mmio_enabled_v3_hw(struct pci_dev *pdev) | |
2480 | { | |
2481 | return PCI_ERS_RESULT_RECOVERED; | |
2482 | } | |
2483 | ||
2484 | static pci_ers_result_t hisi_sas_slot_reset_v3_hw(struct pci_dev *pdev) | |
2485 | { | |
2486 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2487 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2488 | struct device *dev = hisi_hba->dev; | |
2489 | HISI_SAS_DECLARE_RST_WORK_ON_STACK(r); | |
2490 | ||
2491 | dev_info(dev, "PCI error: slot reset callback!!\n"); | |
2492 | queue_work(hisi_hba->wq, &r.work); | |
2493 | wait_for_completion(r.completion); | |
2494 | if (r.done) | |
2495 | return PCI_ERS_RESULT_RECOVERED; | |
2496 | ||
2497 | return PCI_ERS_RESULT_DISCONNECT; | |
2498 | } | |
2499 | ||
e851852b XT |
2500 | static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) |
2501 | { | |
2502 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2503 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2504 | struct device *dev = hisi_hba->dev; | |
2505 | int rc; | |
2506 | ||
2507 | dev_info(dev, "FLR prepare\n"); | |
2508 | set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2509 | hisi_sas_controller_reset_prepare(hisi_hba); | |
2510 | ||
2511 | rc = disable_host_v3_hw(hisi_hba); | |
2512 | if (rc) | |
2513 | dev_err(dev, "FLR: disable host failed rc=%d\n", rc); | |
2514 | } | |
2515 | ||
2516 | static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) | |
2517 | { | |
2518 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2519 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2520 | struct device *dev = hisi_hba->dev; | |
2521 | int rc; | |
2522 | ||
2523 | hisi_sas_init_mem(hisi_hba); | |
2524 | ||
2525 | rc = hw_init_v3_hw(hisi_hba); | |
2526 | if (rc) { | |
2527 | dev_err(dev, "FLR: hw init failed rc=%d\n", rc); | |
2528 | return; | |
2529 | } | |
2530 | ||
2531 | hisi_sas_controller_reset_done(hisi_hba); | |
2532 | dev_info(dev, "FLR done\n"); | |
2533 | } | |
2534 | ||
92f61e3b JG |
2535 | enum { |
2536 | /* instances of the controller */ | |
2537 | hip08, | |
2538 | }; | |
2539 | ||
33623483 XC |
2540 | static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) |
2541 | { | |
2542 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2543 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2544 | struct device *dev = hisi_hba->dev; | |
2545 | struct Scsi_Host *shost = hisi_hba->shost; | |
1d51757d | 2546 | u32 device_state; |
33623483 | 2547 | int rc; |
33623483 XC |
2548 | |
2549 | if (!pdev->pm_cap) { | |
2550 | dev_err(dev, "PCI PM not supported\n"); | |
2551 | return -ENODEV; | |
2552 | } | |
2553 | ||
84b58ff9 XT |
2554 | if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) |
2555 | return -1; | |
2556 | ||
33623483 XC |
2557 | scsi_block_requests(shost); |
2558 | set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
2559 | flush_workqueue(hisi_hba->wq); | |
33623483 | 2560 | |
1d51757d | 2561 | rc = disable_host_v3_hw(hisi_hba); |
33623483 | 2562 | if (rc) { |
1d51757d | 2563 | dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); |
33623483 XC |
2564 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); |
2565 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2566 | scsi_unblock_requests(shost); | |
2567 | return rc; | |
2568 | } | |
2569 | ||
2570 | hisi_sas_init_mem(hisi_hba); | |
2571 | ||
2572 | device_state = pci_choose_state(pdev, state); | |
2573 | dev_warn(dev, "entering operating state [D%d]\n", | |
2574 | device_state); | |
2575 | pci_save_state(pdev); | |
2576 | pci_disable_device(pdev); | |
2577 | pci_set_power_state(pdev, device_state); | |
2578 | ||
33623483 | 2579 | hisi_sas_release_tasks(hisi_hba); |
33623483 XC |
2580 | |
2581 | sas_suspend_ha(sha); | |
2582 | return 0; | |
2583 | } | |
2584 | ||
2585 | static int hisi_sas_v3_resume(struct pci_dev *pdev) | |
2586 | { | |
2587 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
2588 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
2589 | struct Scsi_Host *shost = hisi_hba->shost; | |
2590 | struct device *dev = hisi_hba->dev; | |
2591 | unsigned int rc; | |
2592 | u32 device_state = pdev->current_state; | |
2593 | ||
2594 | dev_warn(dev, "resuming from operating state [D%d]\n", | |
2595 | device_state); | |
2596 | pci_set_power_state(pdev, PCI_D0); | |
2597 | pci_enable_wake(pdev, PCI_D0, 0); | |
2598 | pci_restore_state(pdev); | |
2599 | rc = pci_enable_device(pdev); | |
2600 | if (rc) | |
2601 | dev_err(dev, "enable device failed during resume (%d)\n", rc); | |
2602 | ||
2603 | pci_set_master(pdev); | |
2604 | scsi_unblock_requests(shost); | |
2605 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
2606 | ||
2607 | sas_prep_resume_ha(sha); | |
2608 | init_reg_v3_hw(hisi_hba); | |
2609 | hisi_hba->hw->phys_init(hisi_hba); | |
2610 | sas_resume_ha(sha); | |
2611 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
2612 | ||
2613 | return 0; | |
2614 | } | |
2615 | ||
92f61e3b JG |
2616 | static const struct pci_device_id sas_v3_pci_table[] = { |
2617 | { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, | |
2618 | {} | |
2619 | }; | |
a48c4524 | 2620 | MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); |
92f61e3b | 2621 | |
56b72168 XT |
2622 | static const struct pci_error_handlers hisi_sas_err_handler = { |
2623 | .error_detected = hisi_sas_error_detected_v3_hw, | |
2624 | .mmio_enabled = hisi_sas_mmio_enabled_v3_hw, | |
2625 | .slot_reset = hisi_sas_slot_reset_v3_hw, | |
e851852b XT |
2626 | .reset_prepare = hisi_sas_reset_prepare_v3_hw, |
2627 | .reset_done = hisi_sas_reset_done_v3_hw, | |
56b72168 XT |
2628 | }; |
2629 | ||
92f61e3b JG |
2630 | static struct pci_driver sas_v3_pci_driver = { |
2631 | .name = DRV_NAME, | |
2632 | .id_table = sas_v3_pci_table, | |
2633 | .probe = hisi_sas_v3_probe, | |
2634 | .remove = hisi_sas_v3_remove, | |
33623483 XC |
2635 | .suspend = hisi_sas_v3_suspend, |
2636 | .resume = hisi_sas_v3_resume, | |
56b72168 | 2637 | .err_handler = &hisi_sas_err_handler, |
92f61e3b JG |
2638 | }; |
2639 | ||
2640 | module_pci_driver(sas_v3_pci_driver); | |
2641 | ||
92f61e3b JG |
2642 | MODULE_LICENSE("GPL"); |
2643 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); | |
2644 | MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); | |
a48c4524 | 2645 | MODULE_ALIAS("pci:" DRV_NAME); |