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scsi: hisi_sas: add v3 code to send internal abort command
[mirror_ubuntu-focal-kernel.git] / drivers / scsi / hisi_sas / hisi_sas_v3_hw.c
CommitLineData
92f61e3b
JG		 1/*
2 * Copyright (c) 2017 Hisilicon Limited.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include "hisi_sas.h"
12#define DRV_NAME "hisi_sas_v3_hw"
13
c94d8ca2
XC		 14/* global registers need init*/
15#define DLVRY_QUEUE_ENABLE 0x0
16#define IOST_BASE_ADDR_LO 0x8
17#define IOST_BASE_ADDR_HI 0xc
18#define ITCT_BASE_ADDR_LO 0x10
19#define ITCT_BASE_ADDR_HI 0x14
20#define IO_BROKEN_MSG_ADDR_LO 0x18
21#define IO_BROKEN_MSG_ADDR_HI 0x1c
3975f605
XC		 22#define PHY_CONTEXT 0x20
23#define PHY_STATE 0x24
24#define PHY_PORT_NUM_MA 0x28
25#define PHY_CONN_RATE 0x30
c94d8ca2 26#define AXI_AHB_CLK_CFG 0x3c
182e7222
XC		 27#define ITCT_CLR 0x44
28#define ITCT_CLR_EN_OFF 16
29#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
30#define ITCT_DEV_OFF 0
31#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
c94d8ca2
XC		 32#define AXI_USER1 0x48
33#define AXI_USER2 0x4c
34#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
35#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
36#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
37#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
38#define CFG_MAX_TAG 0x68
39#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
40#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
41#define HGC_GET_ITV_TIME 0x90
42#define DEVICE_MSG_WORK_MODE 0x94
43#define OPENA_WT_CONTI_TIME 0x9c
44#define I_T_NEXUS_LOSS_TIME 0xa0
45#define MAX_CON_TIME_LIMIT_TIME 0xa4
46#define BUS_INACTIVE_LIMIT_TIME 0xa8
47#define REJECT_TO_OPEN_LIMIT_TIME 0xac
48#define CFG_AGING_TIME 0xbc
49#define HGC_DFX_CFG2 0xc0
50#define CFG_ABT_SET_QUERY_IPTT 0xd4
51#define CFG_SET_ABORTED_IPTT_OFF 0
52#define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF)
53#define CFG_1US_TIMER_TRSH 0xcc
3975f605 54#define CHNL_INT_STATUS 0x148
c94d8ca2
XC		 55#define INT_COAL_EN 0x19c
56#define OQ_INT_COAL_TIME 0x1a0
57#define OQ_INT_COAL_CNT 0x1a4
58#define ENT_INT_COAL_TIME 0x1a8
59#define ENT_INT_COAL_CNT 0x1ac
60#define OQ_INT_SRC 0x1b0
61#define OQ_INT_SRC_MSK 0x1b4
62#define ENT_INT_SRC1 0x1b8
63#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
64#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
65#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
66#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
67#define ENT_INT_SRC2 0x1bc
68#define ENT_INT_SRC3 0x1c0
69#define ENT_INT_SRC3_WP_DEPTH_OFF 8
70#define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9
71#define ENT_INT_SRC3_RP_DEPTH_OFF 10
72#define ENT_INT_SRC3_AXI_OFF 11
73#define ENT_INT_SRC3_FIFO_OFF 12
74#define ENT_INT_SRC3_LM_OFF 14
75#define ENT_INT_SRC3_ITC_INT_OFF 15
76#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
77#define ENT_INT_SRC3_ABT_OFF 16
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
3975f605 81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
c94d8ca2
XC		 82#define CHNL_PHYUPDOWN_INT_MSK 0x1d0
83#define CHNL_ENT_INT_MSK 0x1d4
84#define HGC_COM_INT_MSK 0x1d8
3975f605 85#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
c94d8ca2
XC		 86#define SAS_ECC_INTR 0x1e8
87#define SAS_ECC_INTR_MSK 0x1ec
88#define HGC_ERR_STAT_EN 0x238
89#define DLVRY_Q_0_BASE_ADDR_LO 0x260
90#define DLVRY_Q_0_BASE_ADDR_HI 0x264
91#define DLVRY_Q_0_DEPTH 0x268
92#define DLVRY_Q_0_WR_PTR 0x26c
93#define DLVRY_Q_0_RD_PTR 0x270
94#define HYPER_STREAM_ID_EN_CFG 0xc80
95#define OQ0_INT_SRC_MSK 0xc90
96#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
97#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
98#define COMPL_Q_0_DEPTH 0x4e8
99#define COMPL_Q_0_WR_PTR 0x4ec
100#define COMPL_Q_0_RD_PTR 0x4f0
101#define AWQOS_AWCACHE_CFG 0xc84
102#define ARQOS_ARCACHE_CFG 0xc88
103
104/* phy registers requiring init */
105#define PORT_BASE (0x2000)
3975f605
XC		 106#define PHY_CFG (PORT_BASE + 0x0)
107#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
108#define PHY_CFG_ENA_OFF 0
109#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
110#define PHY_CFG_DC_OPT_OFF 2
111#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
c94d8ca2
XC		 112#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
113#define PHY_CTRL (PORT_BASE + 0x14)
114#define PHY_CTRL_RESET_OFF 0
115#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
116#define SL_CFG (PORT_BASE + 0x84)
3975f605
XC		 117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define SL_CTA_OFF 17
121#define SL_CTA_MSK (0x1 << SL_CTA_OFF)
122#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
123#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
124#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
125#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
126#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
127#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
128#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
129#define TXID_AUTO (PORT_BASE + 0xb8)
130#define CT3_OFF 1
131#define CT3_MSK (0x1 << CT3_OFF)
132#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
c94d8ca2
XC		 133#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
134#define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134)
135#define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138)
136#define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c)
137#define CHL_INT0 (PORT_BASE + 0x1b4)
138#define CHL_INT0_HOTPLUG_TOUT_OFF 0
139#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
140#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
141#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
142#define CHL_INT0_SL_PHY_ENABLE_OFF 2
143#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
144#define CHL_INT0_NOT_RDY_OFF 4
145#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
146#define CHL_INT0_PHY_RDY_OFF 5
147#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
148#define CHL_INT1 (PORT_BASE + 0x1b8)
149#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
150#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
151#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
152#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
153#define CHL_INT2 (PORT_BASE + 0x1bc)
154#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
155#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
156#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
157#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
158#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
159#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
160#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
161#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
162#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
163#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
164
a2204723
XC		 165/* HW dma structures */
166/* Delivery queue header */
167/* dw0 */
4de0ca69
XC		 168#define CMD_HDR_ABORT_FLAG_OFF 0
169#define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF)
170#define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2
171#define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF)
a2204723
XC		 172#define CMD_HDR_RESP_REPORT_OFF 5
173#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
174#define CMD_HDR_TLR_CTRL_OFF 6
175#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
176#define CMD_HDR_PORT_OFF 18
177#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
178#define CMD_HDR_PRIORITY_OFF 27
179#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
180#define CMD_HDR_CMD_OFF 29
181#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
182/* dw1 */
ce60689e 183#define CMD_HDR_UNCON_CMD_OFF 3
a2204723
XC		 184#define CMD_HDR_DIR_OFF 5
185#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
ce60689e
XC		 186#define CMD_HDR_RESET_OFF 7
187#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
a2204723
XC		 188#define CMD_HDR_VDTL_OFF 10
189#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
190#define CMD_HDR_FRAME_TYPE_OFF 11
191#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
192#define CMD_HDR_DEV_ID_OFF 16
193#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
194/* dw2 */
195#define CMD_HDR_CFL_OFF 0
196#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
ce60689e
XC		 197#define CMD_HDR_NCQ_TAG_OFF 10
198#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
a2204723
XC		 199#define CMD_HDR_MRFL_OFF 15
200#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
201#define CMD_HDR_SG_MOD_OFF 24
202#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
fa913de2
XC		 203/* dw3 */
204#define CMD_HDR_IPTT_OFF 0
205#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
a2204723
XC		 206/* dw6 */
207#define CMD_HDR_DIF_SGL_LEN_OFF 0
208#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
209#define CMD_HDR_DATA_SGL_LEN_OFF 16
210#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
4de0ca69
XC		 211/* dw7 */
212#define CMD_HDR_ADDR_MODE_SEL_OFF 15
213#define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF)
214#define CMD_HDR_ABORT_IPTT_OFF 16
215#define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF)
a2204723 216
60b4a5ee
XC		 217/* Completion header */
218/* dw0 */
219#define CMPLT_HDR_CMPLT_OFF 0
220#define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF)
221#define CMPLT_HDR_ERROR_PHASE_OFF 2
222#define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF)
223#define CMPLT_HDR_RSPNS_XFRD_OFF 10
224#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
225#define CMPLT_HDR_ERX_OFF 12
226#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
227#define CMPLT_HDR_ABORT_STAT_OFF 13
228#define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF)
229/* abort_stat */
230#define STAT_IO_NOT_VALID 0x1
231#define STAT_IO_NO_DEVICE 0x2
232#define STAT_IO_COMPLETE 0x3
233#define STAT_IO_ABORTED 0x4
234/* dw1 */
235#define CMPLT_HDR_IPTT_OFF 0
236#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
237#define CMPLT_HDR_DEV_ID_OFF 16
238#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
239/* dw3 */
240#define CMPLT_HDR_IO_IN_TARGET_OFF 17
241#define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF)
242
182e7222
XC		 243/* ITCT header */
244/* qw0 */
245#define ITCT_HDR_DEV_TYPE_OFF 0
246#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
247#define ITCT_HDR_VALID_OFF 2
248#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
249#define ITCT_HDR_MCR_OFF 5
250#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
251#define ITCT_HDR_VLN_OFF 9
252#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
253#define ITCT_HDR_SMP_TIMEOUT_OFF 16
254#define ITCT_HDR_AWT_CONTINUE_OFF 25
255#define ITCT_HDR_PORT_ID_OFF 28
256#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
257/* qw2 */
258#define ITCT_HDR_INLT_OFF 0
259#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
260#define ITCT_HDR_RTOLT_OFF 48
261#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
262
c94d8ca2
XC		 263struct hisi_sas_complete_v3_hdr {
264 __le32 dw0;
265 __le32 dw1;
266 __le32 act;
267 __le32 dw3;
268};
269
60b4a5ee
XC		 270struct hisi_sas_err_record_v3 {
271 /* dw0 */
272 __le32 trans_tx_fail_type;
273
274 /* dw1 */
275 __le32 trans_rx_fail_type;
276
277 /* dw2 */
278 __le16 dma_tx_err_type;
279 __le16 sipc_rx_err_type;
280
281 /* dw3 */
282 __le32 dma_rx_err_type;
283};
284
285#define RX_DATA_LEN_UNDERFLOW_OFF 6
286#define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF)
287
c94d8ca2 288#define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096
3975f605
XC		 289#define HISI_SAS_MSI_COUNT_V3_HW 32
290
291enum {
292 HISI_SAS_PHY_PHY_UPDOWN,
293 HISI_SAS_PHY_CHNL_INT,
294 HISI_SAS_PHY_INT_NR
295};
c94d8ca2 296
a2204723
XC		 297#define DIR_NO_DATA 0
298#define DIR_TO_INI 1
299#define DIR_TO_DEVICE 2
300#define DIR_RESERVED 3
301
ce60689e
XC		 302#define CMD_IS_UNCONSTRAINT(cmd) \
303 ((cmd == ATA_CMD_READ_LOG_EXT) || \
304 (cmd == ATA_CMD_READ_LOG_DMA_EXT) || \
305 (cmd == ATA_CMD_DEV_RESET))
306
54edeee1
XC		 307static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
308{
309 void __iomem *regs = hisi_hba->regs + off;
310
311 return readl(regs);
312}
313
a2204723
XC		 314static u32 hisi_sas_read32_relaxed(struct hisi_hba *hisi_hba, u32 off)
315{
316 void __iomem *regs = hisi_hba->regs + off;
317
318 return readl_relaxed(regs);
319}
320
c94d8ca2
XC		 321static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
322{
323 void __iomem *regs = hisi_hba->regs + off;
324
325 writel(val, regs);
326}
327
328static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
329 u32 off, u32 val)
330{
331 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
332
333 writel(val, regs);
334}
335
3975f605
XC		 336static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
337 int phy_no, u32 off)
338{
339 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
340
341 return readl(regs);
342}
343
c94d8ca2
XC		 344static void init_reg_v3_hw(struct hisi_hba *hisi_hba)
345{
346 int i;
347
348 /* Global registers init */
349 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
350 (u32)((1ULL << hisi_hba->queue_count) - 1));
351 hisi_sas_write32(hisi_hba, AXI_USER1, 0x0);
352 hisi_sas_write32(hisi_hba, AXI_USER2, 0x40000060);
353 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
354 hisi_sas_write32(hisi_hba, CFG_1US_TIMER_TRSH, 0xd);
355 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
356 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
357 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
358 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff);
359 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
360 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
361 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
362 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe);
363 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe);
364 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff);
365 hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0);
366 hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0);
367 hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0);
368 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfff00c30);
369 hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0);
370 hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0);
371 for (i = 0; i < hisi_hba->queue_count; i++)
372 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
373
374 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
375 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
376 hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff07fff);
377
378 for (i = 0; i < hisi_hba->n_phy; i++) {
379 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x801);
380 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
381 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
382 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
383 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
384 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
385 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
386 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x83f801fc);
387 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
388 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
389 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
390 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
391 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
392 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
393 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199b4fa);
394 hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG,
395 0xa0064);
396 hisi_sas_phy_write32(hisi_hba, i, SAS_STP_CON_TIMER_CFG,
397 0xa0064);
398 }
399 for (i = 0; i < hisi_hba->queue_count; i++) {
400 /* Delivery queue */
401 hisi_sas_write32(hisi_hba,
402 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
403 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
404
405 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
406 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
407
408 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
409 HISI_SAS_QUEUE_SLOTS);
410
411 /* Completion queue */
412 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
413 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
414
415 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
416 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
417
418 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
419 HISI_SAS_QUEUE_SLOTS);
420 }
421
422 /* itct */
423 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
424 lower_32_bits(hisi_hba->itct_dma));
425
426 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
427 upper_32_bits(hisi_hba->itct_dma));
428
429 /* iost */
430 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
431 lower_32_bits(hisi_hba->iost_dma));
432
433 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
434 upper_32_bits(hisi_hba->iost_dma));
435
436 /* breakpoint */
437 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
438 lower_32_bits(hisi_hba->breakpoint_dma));
439
440 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
441 upper_32_bits(hisi_hba->breakpoint_dma));
442
443 /* SATA broken msg */
444 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
445 lower_32_bits(hisi_hba->sata_breakpoint_dma));
446
447 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
448 upper_32_bits(hisi_hba->sata_breakpoint_dma));
449
450 /* SATA initial fis */
451 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
452 lower_32_bits(hisi_hba->initial_fis_dma));
453
454 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
455 upper_32_bits(hisi_hba->initial_fis_dma));
456}
457
3975f605
XC		 458static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
459{
460 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
461
462 cfg &= ~PHY_CFG_DC_OPT_MSK;
463 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
464 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
465}
466
467static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
468{
469 struct sas_identify_frame identify_frame;
470 u32 *identify_buffer;
471
472 memset(&identify_frame, 0, sizeof(identify_frame));
473 identify_frame.dev_type = SAS_END_DEVICE;
474 identify_frame.frame_type = 0;
475 identify_frame._un1 = 1;
476 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
477 identify_frame.target_bits = SAS_PROTOCOL_NONE;
478 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
479 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
480 identify_frame.phy_id = phy_no;
481 identify_buffer = (u32 *)(&identify_frame);
482
483 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
484 __swab32(identify_buffer[0]));
485 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
486 __swab32(identify_buffer[1]));
487 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
488 __swab32(identify_buffer[2]));
489 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
490 __swab32(identify_buffer[3]));
491 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
492 __swab32(identify_buffer[4]));
493 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
494 __swab32(identify_buffer[5]));
495}
496
182e7222
XC		 497static void setup_itct_v3_hw(struct hisi_hba *hisi_hba,
498 struct hisi_sas_device *sas_dev)
499{
500 struct domain_device *device = sas_dev->sas_device;
501 struct device *dev = hisi_hba->dev;
502 u64 qw0, device_id = sas_dev->device_id;
503 struct hisi_sas_itct *itct = &hisi_hba->itct[device_id];
504 struct domain_device *parent_dev = device->parent;
505 struct asd_sas_port *sas_port = device->port;
506 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
507
508 memset(itct, 0, sizeof(*itct));
509
510 /* qw0 */
511 qw0 = 0;
512 switch (sas_dev->dev_type) {
513 case SAS_END_DEVICE:
514 case SAS_EDGE_EXPANDER_DEVICE:
515 case SAS_FANOUT_EXPANDER_DEVICE:
516 qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF;
517 break;
518 case SAS_SATA_DEV:
519 case SAS_SATA_PENDING:
520 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
521 qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF;
522 else
523 qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF;
524 break;
525 default:
526 dev_warn(dev, "setup itct: unsupported dev type (%d)\n",
527 sas_dev->dev_type);
528 }
529
530 qw0 |= ((1 << ITCT_HDR_VALID_OFF) |
531 (device->linkrate << ITCT_HDR_MCR_OFF) |
532 (1 << ITCT_HDR_VLN_OFF) |
533 (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) |
534 (1 << ITCT_HDR_AWT_CONTINUE_OFF) |
535 (port->id << ITCT_HDR_PORT_ID_OFF));
536 itct->qw0 = cpu_to_le64(qw0);
537
538 /* qw1 */
539 memcpy(&itct->sas_addr, device->sas_addr, SAS_ADDR_SIZE);
540 itct->sas_addr = __swab64(itct->sas_addr);
541
542 /* qw2 */
543 if (!dev_is_sata(device))
544 itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) |
545 (0x1ULL << ITCT_HDR_RTOLT_OFF));
546}
547
548static void free_device_v3_hw(struct hisi_hba *hisi_hba,
549 struct hisi_sas_device *sas_dev)
550{
551 u64 dev_id = sas_dev->device_id;
552 struct device *dev = hisi_hba->dev;
553 struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id];
554 u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
555
556 /* clear the itct interrupt state */
557 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val)
558 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
559 ENT_INT_SRC3_ITC_INT_MSK);
560
561 /* clear the itct table*/
562 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR);
563 reg_val |= ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK);
564 hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val);
565
566 udelay(10);
567 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3);
568 if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) {
569 dev_dbg(dev, "got clear ITCT done interrupt\n");
570
571 /* invalid the itct state*/
572 memset(itct, 0, sizeof(struct hisi_sas_itct));
573 hisi_sas_write32(hisi_hba, ENT_INT_SRC3,
574 ENT_INT_SRC3_ITC_INT_MSK);
575 hisi_hba->devices[dev_id].dev_type = SAS_PHY_UNUSED;
576 hisi_hba->devices[dev_id].dev_status = HISI_SAS_DEV_NORMAL;
577
578 /* clear the itct */
579 hisi_sas_write32(hisi_hba, ITCT_CLR, 0);
580 dev_dbg(dev, "clear ITCT ok\n");
581 }
582}
583
c94d8ca2
XC		 584static int hw_init_v3_hw(struct hisi_hba *hisi_hba)
585{
586 init_reg_v3_hw(hisi_hba);
587
588 return 0;
589}
590
3975f605
XC		 591static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
592{
593 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
594
595 cfg |= PHY_CFG_ENA_MSK;
596 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
597}
598
599static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
600{
601 config_id_frame_v3_hw(hisi_hba, phy_no);
602 config_phy_opt_mode_v3_hw(hisi_hba, phy_no);
603 enable_phy_v3_hw(hisi_hba, phy_no);
604}
605
606static void start_phys_v3_hw(struct hisi_hba *hisi_hba)
607{
608 int i;
609
610 for (i = 0; i < hisi_hba->n_phy; i++)
611 start_phy_v3_hw(hisi_hba, i);
612}
613
614static void phys_init_v3_hw(struct hisi_hba *hisi_hba)
615{
616 start_phys_v3_hw(hisi_hba);
617}
618
619static void sl_notify_v3_hw(struct hisi_hba *hisi_hba, int phy_no)
620{
621 u32 sl_control;
622
623 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
624 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
625 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
626 msleep(1);
627 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
628 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
629 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
630}
631
a2204723
XC		 632/**
633 * The callpath to this function and upto writing the write
634 * queue pointer should be safe from interruption.
635 */
636static int
637get_free_slot_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_dq *dq)
638{
639 struct device *dev = hisi_hba->dev;
640 int queue = dq->id;
641 u32 r, w;
642
643 w = dq->wr_point;
644 r = hisi_sas_read32_relaxed(hisi_hba,
645 DLVRY_Q_0_RD_PTR + (queue * 0x14));
646 if (r == (w+1) % HISI_SAS_QUEUE_SLOTS) {
647 dev_warn(dev, "full queue=%d r=%d w=%d\n\n",
648 queue, r, w);
649 return -EAGAIN;
650 }
651
652 return 0;
653}
654
655static void start_delivery_v3_hw(struct hisi_sas_dq *dq)
656{
657 struct hisi_hba *hisi_hba = dq->hisi_hba;
658 int dlvry_queue = dq->slot_prep->dlvry_queue;
659 int dlvry_queue_slot = dq->slot_prep->dlvry_queue_slot;
660
661 dq->wr_point = ++dlvry_queue_slot % HISI_SAS_QUEUE_SLOTS;
662 hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14),
663 dq->wr_point);
664}
665
666static int prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba,
667 struct hisi_sas_slot *slot,
668 struct hisi_sas_cmd_hdr *hdr,
669 struct scatterlist *scatter,
670 int n_elem)
671{
672 struct device *dev = hisi_hba->dev;
673 struct scatterlist *sg;
674 int i;
675
676 if (n_elem > HISI_SAS_SGE_PAGE_CNT) {
677 dev_err(dev, "prd err: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT",
678 n_elem);
679 return -EINVAL;
680 }
681
682 slot->sge_page = dma_pool_alloc(hisi_hba->sge_page_pool, GFP_ATOMIC,
683 &slot->sge_page_dma);
684 if (!slot->sge_page)
685 return -ENOMEM;
686
687 for_each_sg(scatter, sg, n_elem, i) {
688 struct hisi_sas_sge *entry = &slot->sge_page->sge[i];
689
690 entry->addr = cpu_to_le64(sg_dma_address(sg));
691 entry->page_ctrl_0 = entry->page_ctrl_1 = 0;
692 entry->data_len = cpu_to_le32(sg_dma_len(sg));
693 entry->data_off = 0;
694 }
695
696 hdr->prd_table_addr = cpu_to_le64(slot->sge_page_dma);
697 hdr->sg_len = cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF);
698
699 return 0;
700}
701
702static int prep_ssp_v3_hw(struct hisi_hba *hisi_hba,
703 struct hisi_sas_slot *slot, int is_tmf,
704 struct hisi_sas_tmf_task *tmf)
705{
706 struct sas_task *task = slot->task;
707 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
708 struct domain_device *device = task->dev;
709 struct hisi_sas_device *sas_dev = device->lldd_dev;
710 struct hisi_sas_port *port = slot->port;
711 struct sas_ssp_task *ssp_task = &task->ssp_task;
712 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
713 int has_data = 0, rc, priority = is_tmf;
714 u8 *buf_cmd;
715 u32 dw1 = 0, dw2 = 0;
716
717 hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) |
718 (2 << CMD_HDR_TLR_CTRL_OFF) |
719 (port->id << CMD_HDR_PORT_OFF) |
720 (priority << CMD_HDR_PRIORITY_OFF) |
721 (1 << CMD_HDR_CMD_OFF)); /* ssp */
722
723 dw1 = 1 << CMD_HDR_VDTL_OFF;
724 if (is_tmf) {
725 dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF;
726 dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF;
727 } else {
728 dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF;
729 switch (scsi_cmnd->sc_data_direction) {
730 case DMA_TO_DEVICE:
731 has_data = 1;
732 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
733 break;
734 case DMA_FROM_DEVICE:
735 has_data = 1;
736 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
737 break;
738 default:
739 dw1 &= ~CMD_HDR_DIR_MSK;
740 }
741 }
742
743 /* map itct entry */
744 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
745 hdr->dw1 = cpu_to_le32(dw1);
746
747 dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr)
748 + 3) / 4) << CMD_HDR_CFL_OFF) |
749 ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) |
750 (2 << CMD_HDR_SG_MOD_OFF);
751 hdr->dw2 = cpu_to_le32(dw2);
752 hdr->transfer_tags = cpu_to_le32(slot->idx);
753
754 if (has_data) {
755 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
756 slot->n_elem);
757 if (rc)
758 return rc;
759 }
760
761 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
762 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
763 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
764
765 buf_cmd = slot->command_table + sizeof(struct ssp_frame_hdr);
766 memcpy(buf_cmd, ssp_task->LUN, 8);
767
768 if (!is_tmf) {
769 buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3);
770 memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len);
771 } else {
772 buf_cmd[10] = tmf->tmf;
773 switch (tmf->tmf) {
774 case TMF_ABORT_TASK:
775 case TMF_QUERY_TASK:
776 buf_cmd[12] =
777 (tmf->tag_of_task_to_be_managed >> 8) & 0xff;
778 buf_cmd[13] =
779 tmf->tag_of_task_to_be_managed & 0xff;
780 break;
781 default:
782 break;
783 }
784 }
785
786 return 0;
787}
788
fa913de2
XC		 789static int prep_smp_v3_hw(struct hisi_hba *hisi_hba,
790 struct hisi_sas_slot *slot)
791{
792 struct sas_task *task = slot->task;
793 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
794 struct domain_device *device = task->dev;
795 struct device *dev = hisi_hba->dev;
796 struct hisi_sas_port *port = slot->port;
797 struct scatterlist *sg_req, *sg_resp;
798 struct hisi_sas_device *sas_dev = device->lldd_dev;
799 dma_addr_t req_dma_addr;
800 unsigned int req_len, resp_len;
801 int elem, rc;
802
803 /*
804 * DMA-map SMP request, response buffers
805 */
806 /* req */
807 sg_req = &task->smp_task.smp_req;
808 elem = dma_map_sg(dev, sg_req, 1, DMA_TO_DEVICE);
809 if (!elem)
810 return -ENOMEM;
811 req_len = sg_dma_len(sg_req);
812 req_dma_addr = sg_dma_address(sg_req);
813
814 /* resp */
815 sg_resp = &task->smp_task.smp_resp;
816 elem = dma_map_sg(dev, sg_resp, 1, DMA_FROM_DEVICE);
817 if (!elem) {
818 rc = -ENOMEM;
819 goto err_out_req;
820 }
821 resp_len = sg_dma_len(sg_resp);
822 if ((req_len & 0x3) || (resp_len & 0x3)) {
823 rc = -EINVAL;
824 goto err_out_resp;
825 }
826
827 /* create header */
828 /* dw0 */
829 hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) |
830 (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */
831 (2 << CMD_HDR_CMD_OFF)); /* smp */
832
833 /* map itct entry */
834 hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) |
835 (1 << CMD_HDR_FRAME_TYPE_OFF) |
836 (DIR_NO_DATA << CMD_HDR_DIR_OFF));
837
838 /* dw2 */
839 hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) |
840 (HISI_SAS_MAX_SMP_RESP_SZ / 4 <<
841 CMD_HDR_MRFL_OFF));
842
843 hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF);
844
845 hdr->cmd_table_addr = cpu_to_le64(req_dma_addr);
846 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
847
848 return 0;
849
850err_out_resp:
851 dma_unmap_sg(dev, &slot->task->smp_task.smp_resp, 1,
852 DMA_FROM_DEVICE);
853err_out_req:
854 dma_unmap_sg(dev, &slot->task->smp_task.smp_req, 1,
855 DMA_TO_DEVICE);
856 return rc;
857}
858
ce60689e
XC		 859static int get_ncq_tag_v3_hw(struct sas_task *task, u32 *tag)
860{
861 struct ata_queued_cmd *qc = task->uldd_task;
862
863 if (qc) {
864 if (qc->tf.command == ATA_CMD_FPDMA_WRITE ||
865 qc->tf.command == ATA_CMD_FPDMA_READ) {
866 *tag = qc->tag;
867 return 1;
868 }
869 }
870 return 0;
871}
872
873static int prep_ata_v3_hw(struct hisi_hba *hisi_hba,
874 struct hisi_sas_slot *slot)
875{
876 struct sas_task *task = slot->task;
877 struct domain_device *device = task->dev;
878 struct domain_device *parent_dev = device->parent;
879 struct hisi_sas_device *sas_dev = device->lldd_dev;
880 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
881 struct asd_sas_port *sas_port = device->port;
882 struct hisi_sas_port *port = to_hisi_sas_port(sas_port);
883 u8 *buf_cmd;
884 int has_data = 0, rc = 0, hdr_tag = 0;
885 u32 dw1 = 0, dw2 = 0;
886
887 hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF);
888 if (parent_dev && DEV_IS_EXPANDER(parent_dev->dev_type))
889 hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF);
890 else
891 hdr->dw0 |= cpu_to_le32(4 << CMD_HDR_CMD_OFF);
892
893 switch (task->data_dir) {
894 case DMA_TO_DEVICE:
895 has_data = 1;
896 dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF;
897 break;
898 case DMA_FROM_DEVICE:
899 has_data = 1;
900 dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF;
901 break;
902 default:
903 dw1 &= ~CMD_HDR_DIR_MSK;
904 }
905
906 if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) &&
907 (task->ata_task.fis.control & ATA_SRST))
908 dw1 |= 1 << CMD_HDR_RESET_OFF;
909
910 dw1 |= (hisi_sas_get_ata_protocol(
911 task->ata_task.fis.command, task->data_dir))
912 << CMD_HDR_FRAME_TYPE_OFF;
913 dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF;
914
915 if (CMD_IS_UNCONSTRAINT(task->ata_task.fis.command))
916 dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF;
917
918 hdr->dw1 = cpu_to_le32(dw1);
919
920 /* dw2 */
921 if (task->ata_task.use_ncq && get_ncq_tag_v3_hw(task, &hdr_tag)) {
922 task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3);
923 dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF;
924 }
925
926 dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF |
927 2 << CMD_HDR_SG_MOD_OFF;
928 hdr->dw2 = cpu_to_le32(dw2);
929
930 /* dw3 */
931 hdr->transfer_tags = cpu_to_le32(slot->idx);
932
933 if (has_data) {
934 rc = prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter,
935 slot->n_elem);
936 if (rc)
937 return rc;
938 }
939
940 hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len);
941 hdr->cmd_table_addr = cpu_to_le64(slot->command_table_dma);
942 hdr->sts_buffer_addr = cpu_to_le64(slot->status_buffer_dma);
943
944 buf_cmd = slot->command_table;
945
946 if (likely(!task->ata_task.device_control_reg_update))
947 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
948 /* fill in command FIS */
949 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
950
951 return 0;
952}
953
4de0ca69
XC		 954static int prep_abort_v3_hw(struct hisi_hba *hisi_hba,
955 struct hisi_sas_slot *slot,
956 int device_id, int abort_flag, int tag_to_abort)
957{
958 struct sas_task *task = slot->task;
959 struct domain_device *dev = task->dev;
960 struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr;
961 struct hisi_sas_port *port = slot->port;
962
963 /* dw0 */
964 hdr->dw0 = cpu_to_le32((5 << CMD_HDR_CMD_OFF) | /*abort*/
965 (port->id << CMD_HDR_PORT_OFF) |
966 ((dev_is_sata(dev) ? 1:0)
967 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) |
968 (abort_flag
969 << CMD_HDR_ABORT_FLAG_OFF));
970
971 /* dw1 */
972 hdr->dw1 = cpu_to_le32(device_id
973 << CMD_HDR_DEV_ID_OFF);
974
975 /* dw7 */
976 hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF);
977 hdr->transfer_tags = cpu_to_le32(slot->idx);
978
979 return 0;
980}
981
54edeee1
XC		 982static int phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
983{
984 int i, res = 0;
985 u32 context, port_id, link_rate, hard_phy_linkrate;
986 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
987 struct asd_sas_phy *sas_phy = &phy->sas_phy;
988 struct device *dev = hisi_hba->dev;
989
990 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
991
992 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
993 port_id = (port_id >> (4 * phy_no)) & 0xf;
994 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
995 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
996
997 if (port_id == 0xf) {
998 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
999 res = IRQ_NONE;
1000 goto end;
1001 }
1002 sas_phy->linkrate = link_rate;
1003 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
1004 HARD_PHY_LINKRATE);
1005 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
1006 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
1007 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
1008
1009 /* Check for SATA dev */
1010 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
1011 if (context & (1 << phy_no)) {
1012 struct hisi_sas_initial_fis *initial_fis;
1013 struct dev_to_host_fis *fis;
1014 u8 attached_sas_addr[SAS_ADDR_SIZE] = {0};
1015
1016 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1017 initial_fis = &hisi_hba->initial_fis[phy_no];
1018 fis = &initial_fis->fis;
1019 sas_phy->oob_mode = SATA_OOB_MODE;
1020 attached_sas_addr[0] = 0x50;
1021 attached_sas_addr[7] = phy_no;
1022 memcpy(sas_phy->attached_sas_addr,
1023 attached_sas_addr,
1024 SAS_ADDR_SIZE);
1025 memcpy(sas_phy->frame_rcvd, fis,
1026 sizeof(struct dev_to_host_fis));
1027 phy->phy_type |= PORT_TYPE_SATA;
1028 phy->identify.device_type = SAS_SATA_DEV;
1029 phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
1030 phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
1031 } else {
1032 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
1033 struct sas_identify_frame *id =
1034 (struct sas_identify_frame *)frame_rcvd;
1035
1036 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
1037 for (i = 0; i < 6; i++) {
1038 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
1039 RX_IDAF_DWORD0 + (i * 4));
1040 frame_rcvd[i] = __swab32(idaf);
1041 }
1042 sas_phy->oob_mode = SAS_OOB_MODE;
1043 memcpy(sas_phy->attached_sas_addr,
1044 &id->sas_addr,
1045 SAS_ADDR_SIZE);
1046 phy->phy_type |= PORT_TYPE_SAS;
1047 phy->identify.device_type = id->dev_type;
1048 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
1049 if (phy->identify.device_type == SAS_END_DEVICE)
1050 phy->identify.target_port_protocols =
1051 SAS_PROTOCOL_SSP;
1052 else if (phy->identify.device_type != SAS_PHY_UNUSED)
1053 phy->identify.target_port_protocols =
1054 SAS_PROTOCOL_SMP;
1055 }
1056
1057 phy->port_id = port_id;
1058 phy->phy_attached = 1;
1059 queue_work(hisi_hba->wq, &phy->phyup_ws);
1060
1061end:
1062 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1063 CHL_INT0_SL_PHY_ENABLE_MSK);
1064 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
1065
1066 return res;
1067}
1068
1069static int phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1070{
1071 int res = 0;
1072 u32 phy_state, sl_ctrl, txid_auto;
1073 struct device *dev = hisi_hba->dev;
1074
1075 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1);
1076
1077 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1078 dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state);
1079 hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0);
1080
1081 sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
1082 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL,
1083 sl_ctrl&(~SL_CTA_MSK));
1084
1085 txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO);
1086 hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO,
1087 txid_auto | CT3_MSK);
1088
1089 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK);
1090 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0);
1091
1092 return res;
1093}
1094
1095static void phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba)
1096{
1097 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1098 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1099 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
1100
1101 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1);
1102 sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD);
1103 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
1104 CHL_INT0_SL_RX_BCST_ACK_MSK);
1105 hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0);
1106}
1107
1108static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p)
1109{
1110 struct hisi_hba *hisi_hba = p;
1111 u32 irq_msk;
1112 int phy_no = 0;
1113 irqreturn_t res = IRQ_NONE;
1114
1115 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1116 & 0x11111111;
1117 while (irq_msk) {
1118 if (irq_msk & 1) {
1119 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
1120 CHL_INT0);
1121 u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE);
1122 int rdy = phy_state & (1 << phy_no);
1123
1124 if (rdy) {
1125 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
1126 /* phy up */
1127 if (phy_up_v3_hw(phy_no, hisi_hba)
1128 == IRQ_HANDLED)
1129 res = IRQ_HANDLED;
1130 if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK)
1131 /* phy bcast */
1132 phy_bcast_v3_hw(phy_no, hisi_hba);
1133 } else {
1134 if (irq_value & CHL_INT0_NOT_RDY_MSK)
1135 /* phy down */
1136 if (phy_down_v3_hw(phy_no, hisi_hba)
1137 == IRQ_HANDLED)
1138 res = IRQ_HANDLED;
1139 }
1140 }
1141 irq_msk >>= 4;
1142 phy_no++;
1143 }
1144
1145 return res;
1146}
1147
1148static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p)
1149{
1150 struct hisi_hba *hisi_hba = p;
1151 struct device *dev = hisi_hba->dev;
1152 u32 ent_msk, ent_tmp, irq_msk;
1153 int phy_no = 0;
1154
1155 ent_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3);
1156 ent_tmp = ent_msk;
1157 ent_msk |= ENT_INT_SRC_MSK3_ENT95_MSK_MSK;
1158 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_msk);
1159
1160 irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS)
1161 & 0xeeeeeeee;
1162
1163 while (irq_msk) {
1164 u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no,
1165 CHL_INT0);
1166 u32 irq_value1 = hisi_sas_phy_read32(hisi_hba, phy_no,
1167 CHL_INT1);
1168 u32 irq_value2 = hisi_sas_phy_read32(hisi_hba, phy_no,
1169 CHL_INT2);
1170
1171 if ((irq_msk & (4 << (phy_no * 4))) &&
1172 irq_value1) {
1173 if (irq_value1 & (CHL_INT1_DMAC_RX_ECC_ERR_MSK |
1174 CHL_INT1_DMAC_TX_ECC_ERR_MSK))
1175 panic("%s: DMAC RX/TX ecc bad error! (0x%x)",
1176 dev_name(dev), irq_value1);
1177
1178 hisi_sas_phy_write32(hisi_hba, phy_no,
1179 CHL_INT1, irq_value1);
1180 }
1181
1182 if (irq_msk & (8 << (phy_no * 4)) && irq_value2)
1183 hisi_sas_phy_write32(hisi_hba, phy_no,
1184 CHL_INT2, irq_value2);
1185
1186
1187 if (irq_msk & (2 << (phy_no * 4)) && irq_value0) {
1188 hisi_sas_phy_write32(hisi_hba, phy_no,
1189 CHL_INT0, irq_value0
1190 & (~CHL_INT0_HOTPLUG_TOUT_MSK)
1191 & (~CHL_INT0_SL_PHY_ENABLE_MSK)
1192 & (~CHL_INT0_NOT_RDY_MSK));
1193 }
1194 irq_msk &= ~(0xe << (phy_no * 4));
1195 phy_no++;
1196 }
1197
1198 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, ent_tmp);
1199
1200 return IRQ_HANDLED;
1201}
1202
60b4a5ee
XC		 1203static void
1204slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task,
1205 struct hisi_sas_slot *slot)
1206{
1207 struct task_status_struct *ts = &task->task_status;
1208 struct hisi_sas_complete_v3_hdr *complete_queue =
1209 hisi_hba->complete_hdr[slot->cmplt_queue];
1210 struct hisi_sas_complete_v3_hdr *complete_hdr =
1211 &complete_queue[slot->cmplt_queue_slot];
1212 struct hisi_sas_err_record_v3 *record = slot->status_buffer;
1213 u32 dma_rx_err_type = record->dma_rx_err_type;
1214 u32 trans_tx_fail_type = record->trans_tx_fail_type;
1215
1216 switch (task->task_proto) {
1217 case SAS_PROTOCOL_SSP:
1218 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1219 ts->residual = trans_tx_fail_type;
1220 ts->stat = SAS_DATA_UNDERRUN;
1221 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1222 ts->stat = SAS_QUEUE_FULL;
1223 slot->abort = 1;
1224 } else {
1225 ts->stat = SAS_OPEN_REJECT;
1226 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1227 }
1228 break;
1229 case SAS_PROTOCOL_SATA:
1230 case SAS_PROTOCOL_STP:
1231 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1232 if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) {
1233 ts->residual = trans_tx_fail_type;
1234 ts->stat = SAS_DATA_UNDERRUN;
1235 } else if (complete_hdr->dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) {
1236 ts->stat = SAS_PHY_DOWN;
1237 slot->abort = 1;
1238 } else {
1239 ts->stat = SAS_OPEN_REJECT;
1240 ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1241 }
1242 hisi_sas_sata_done(task, slot);
1243 break;
1244 case SAS_PROTOCOL_SMP:
1245 ts->stat = SAM_STAT_CHECK_CONDITION;
1246 break;
1247 default:
1248 break;
1249 }
1250}
1251
1252static int
1253slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot)
1254{
1255 struct sas_task *task = slot->task;
1256 struct hisi_sas_device *sas_dev;
1257 struct device *dev = hisi_hba->dev;
1258 struct task_status_struct *ts;
1259 struct domain_device *device;
1260 enum exec_status sts;
1261 struct hisi_sas_complete_v3_hdr *complete_queue =
1262 hisi_hba->complete_hdr[slot->cmplt_queue];
1263 struct hisi_sas_complete_v3_hdr *complete_hdr =
1264 &complete_queue[slot->cmplt_queue_slot];
1265 int aborted;
1266 unsigned long flags;
1267
1268 if (unlikely(!task || !task->lldd_task || !task->dev))
1269 return -EINVAL;
1270
1271 ts = &task->task_status;
1272 device = task->dev;
1273 sas_dev = device->lldd_dev;
1274
1275 spin_lock_irqsave(&task->task_state_lock, flags);
1276 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1277 task->task_state_flags &=
1278 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1279 spin_unlock_irqrestore(&task->task_state_lock, flags);
1280
1281 memset(ts, 0, sizeof(*ts));
1282 ts->resp = SAS_TASK_COMPLETE;
1283 if (unlikely(aborted)) {
1284 ts->stat = SAS_ABORTED_TASK;
1285 hisi_sas_slot_task_free(hisi_hba, task, slot);
1286 return -1;
1287 }
1288
1289 if (unlikely(!sas_dev)) {
1290 dev_dbg(dev, "slot complete: port has not device\n");
1291 ts->stat = SAS_PHY_DOWN;
1292 goto out;
1293 }
1294
1295 /*
1296 * Use SAS+TMF status codes
1297 */
1298 switch ((complete_hdr->dw0 & CMPLT_HDR_ABORT_STAT_MSK)
1299 >> CMPLT_HDR_ABORT_STAT_OFF) {
1300 case STAT_IO_ABORTED:
1301 /* this IO has been aborted by abort command */
1302 ts->stat = SAS_ABORTED_TASK;
1303 goto out;
1304 case STAT_IO_COMPLETE:
1305 /* internal abort command complete */
1306 ts->stat = TMF_RESP_FUNC_SUCC;
1307 goto out;
1308 case STAT_IO_NO_DEVICE:
1309 ts->stat = TMF_RESP_FUNC_COMPLETE;
1310 goto out;
1311 case STAT_IO_NOT_VALID:
1312 /*
1313 * abort single IO, the controller can't find the IO
1314 */
1315 ts->stat = TMF_RESP_FUNC_FAILED;
1316 goto out;
1317 default:
1318 break;
1319 }
1320
1321 /* check for erroneous completion */
1322 if ((complete_hdr->dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) {
1323 slot_err_v3_hw(hisi_hba, task, slot);
1324 if (unlikely(slot->abort))
1325 return ts->stat;
1326 goto out;
1327 }
1328
1329 switch (task->task_proto) {
1330 case SAS_PROTOCOL_SSP: {
1331 struct ssp_response_iu *iu = slot->status_buffer +
1332 sizeof(struct hisi_sas_err_record);
1333
1334 sas_ssp_task_response(dev, task, iu);
1335 break;
1336 }
1337 case SAS_PROTOCOL_SMP: {
1338 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1339 void *to;
1340
1341 ts->stat = SAM_STAT_GOOD;
1342 to = kmap_atomic(sg_page(sg_resp));
1343
1344 dma_unmap_sg(dev, &task->smp_task.smp_resp, 1,
1345 DMA_FROM_DEVICE);
1346 dma_unmap_sg(dev, &task->smp_task.smp_req, 1,
1347 DMA_TO_DEVICE);
1348 memcpy(to + sg_resp->offset,
1349 slot->status_buffer +
1350 sizeof(struct hisi_sas_err_record),
1351 sg_dma_len(sg_resp));
1352 kunmap_atomic(to);
1353 break;
1354 }
1355 case SAS_PROTOCOL_SATA:
1356 case SAS_PROTOCOL_STP:
1357 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1358 ts->stat = SAM_STAT_GOOD;
1359 hisi_sas_sata_done(task, slot);
1360 break;
1361 default:
1362 ts->stat = SAM_STAT_CHECK_CONDITION;
1363 break;
1364 }
1365
1366 if (!slot->port->port_attached) {
1367 dev_err(dev, "slot complete: port %d has removed\n",
1368 slot->port->sas_port.id);
1369 ts->stat = SAS_PHY_DOWN;
1370 }
1371
1372out:
1373 spin_lock_irqsave(&task->task_state_lock, flags);
1374 task->task_state_flags |= SAS_TASK_STATE_DONE;
1375 spin_unlock_irqrestore(&task->task_state_lock, flags);
1376 spin_lock_irqsave(&hisi_hba->lock, flags);
1377 hisi_sas_slot_task_free(hisi_hba, task, slot);
1378 spin_unlock_irqrestore(&hisi_hba->lock, flags);
1379 sts = ts->stat;
1380
1381 if (task->task_done)
1382 task->task_done(task);
1383
1384 return sts;
1385}
1386
1387static void cq_tasklet_v3_hw(unsigned long val)
1388{
1389 struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val;
1390 struct hisi_hba *hisi_hba = cq->hisi_hba;
1391 struct hisi_sas_slot *slot;
1392 struct hisi_sas_itct *itct;
1393 struct hisi_sas_complete_v3_hdr *complete_queue;
1394 u32 rd_point = cq->rd_point, wr_point, dev_id;
1395 int queue = cq->id;
1396 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
1397
1398 complete_queue = hisi_hba->complete_hdr[queue];
1399
1400 spin_lock(&dq->lock);
1401 wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR +
1402 (0x14 * queue));
1403
1404 while (rd_point != wr_point) {
1405 struct hisi_sas_complete_v3_hdr *complete_hdr;
1406 int iptt;
1407
1408 complete_hdr = &complete_queue[rd_point];
1409
1410 /* Check for NCQ completion */
1411 if (complete_hdr->act) {
1412 u32 act_tmp = complete_hdr->act;
1413 int ncq_tag_count = ffs(act_tmp);
1414
1415 dev_id = (complete_hdr->dw1 & CMPLT_HDR_DEV_ID_MSK) >>
1416 CMPLT_HDR_DEV_ID_OFF;
1417 itct = &hisi_hba->itct[dev_id];
1418
1419 /* The NCQ tags are held in the itct header */
1420 while (ncq_tag_count) {
1421 __le64 *ncq_tag = &itct->qw4_15[0];
1422
1423 ncq_tag_count -= 1;
1424 iptt = (ncq_tag[ncq_tag_count / 5]
1425 >> (ncq_tag_count % 5) * 12) & 0xfff;
1426
1427 slot = &hisi_hba->slot_info[iptt];
1428 slot->cmplt_queue_slot = rd_point;
1429 slot->cmplt_queue = queue;
1430 slot_complete_v3_hw(hisi_hba, slot);
1431
1432 act_tmp &= ~(1 << ncq_tag_count);
1433 ncq_tag_count = ffs(act_tmp);
1434 }
1435 } else {
1436 iptt = (complete_hdr->dw1) & CMPLT_HDR_IPTT_MSK;
1437 slot = &hisi_hba->slot_info[iptt];
1438 slot->cmplt_queue_slot = rd_point;
1439 slot->cmplt_queue = queue;
1440 slot_complete_v3_hw(hisi_hba, slot);
1441 }
1442
1443 if (++rd_point >= HISI_SAS_QUEUE_SLOTS)
1444 rd_point = 0;
1445 }
1446
1447 /* update rd_point */
1448 cq->rd_point = rd_point;
1449 hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point);
1450 spin_unlock(&dq->lock);
1451}
1452
1453static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p)
1454{
1455 struct hisi_sas_cq *cq = p;
1456 struct hisi_hba *hisi_hba = cq->hisi_hba;
1457 int queue = cq->id;
1458
1459 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue);
1460
1461 tasklet_schedule(&cq->tasklet);
1462
1463 return IRQ_HANDLED;
1464}
1465
54edeee1
XC		 1466static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba)
1467{
1468 struct device *dev = hisi_hba->dev;
1469 struct pci_dev *pdev = hisi_hba->pci_dev;
1470 int vectors, rc;
60b4a5ee 1471 int i, k;
54edeee1
XC		 1472 int max_msi = HISI_SAS_MSI_COUNT_V3_HW;
1473
1474 vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, 1,
1475 max_msi, PCI_IRQ_MSI);
1476 if (vectors < max_msi) {
1477 dev_err(dev, "could not allocate all msi (%d)\n", vectors);
1478 return -ENOENT;
1479 }
1480
1481 rc = devm_request_irq(dev, pci_irq_vector(pdev, 1),
1482 int_phy_up_down_bcast_v3_hw, 0,
1483 DRV_NAME " phy", hisi_hba);
1484 if (rc) {
1485 dev_err(dev, "could not request phy interrupt, rc=%d\n", rc);
1486 rc = -ENOENT;
1487 goto free_irq_vectors;
1488 }
1489
1490 rc = devm_request_irq(dev, pci_irq_vector(pdev, 2),
1491 int_chnl_int_v3_hw, 0,
1492 DRV_NAME " channel", hisi_hba);
1493 if (rc) {
1494 dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc);
1495 rc = -ENOENT;
1496 goto free_phy_irq;
1497 }
1498
60b4a5ee
XC		 1499 /* Init tasklets for cq only */
1500 for (i = 0; i < hisi_hba->queue_count; i++) {
1501 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1502 struct tasklet_struct *t = &cq->tasklet;
1503
1504 rc = devm_request_irq(dev, pci_irq_vector(pdev, i+16),
1505 cq_interrupt_v3_hw, 0,
1506 DRV_NAME " cq", cq);
1507 if (rc) {
1508 dev_err(dev,
1509 "could not request cq%d interrupt, rc=%d\n",
1510 i, rc);
1511 rc = -ENOENT;
1512 goto free_cq_irqs;
1513 }
1514
1515 tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq);
1516 }
54edeee1
XC		 1517
1518 return 0;
1519
60b4a5ee
XC		 1520free_cq_irqs:
1521 for (k = 0; k < i; k++) {
1522 struct hisi_sas_cq *cq = &hisi_hba->cq[k];
1523
1524 free_irq(pci_irq_vector(pdev, k+16), cq);
1525 }
1526 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
54edeee1
XC		 1527free_phy_irq:
1528 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1529free_irq_vectors:
1530 pci_free_irq_vectors(pdev);
1531 return rc;
1532}
1533
c94d8ca2
XC		 1534static int hisi_sas_v3_init(struct hisi_hba *hisi_hba)
1535{
1536 int rc;
1537
1538 rc = hw_init_v3_hw(hisi_hba);
1539 if (rc)
1540 return rc;
1541
54edeee1
XC		 1542 rc = interrupt_init_v3_hw(hisi_hba);
1543 if (rc)
1544 return rc;
1545
c94d8ca2
XC		 1546 return 0;
1547}
1548
e21fe3a5 1549static const struct hisi_sas_hw hisi_sas_v3_hw = {
c94d8ca2 1550 .hw_init = hisi_sas_v3_init,
182e7222 1551 .setup_itct = setup_itct_v3_hw,
c94d8ca2
XC		 1552 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V3_HW,
1553 .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr),
182e7222 1554 .free_device = free_device_v3_hw,
3975f605 1555 .sl_notify = sl_notify_v3_hw,
a2204723 1556 .prep_ssp = prep_ssp_v3_hw,
fa913de2 1557 .prep_smp = prep_smp_v3_hw,
ce60689e 1558 .prep_stp = prep_ata_v3_hw,
4de0ca69 1559 .prep_abort = prep_abort_v3_hw,
a2204723
XC		 1560 .get_free_slot = get_free_slot_v3_hw,
1561 .start_delivery = start_delivery_v3_hw,
1562 .slot_complete = slot_complete_v3_hw,
3975f605 1563 .phys_init = phys_init_v3_hw,
e21fe3a5
JG		 1564};
1565
1566static struct Scsi_Host *
1567hisi_sas_shost_alloc_pci(struct pci_dev *pdev)
1568{
1569 struct Scsi_Host *shost;
1570 struct hisi_hba *hisi_hba;
1571 struct device *dev = &pdev->dev;
1572
1573 shost = scsi_host_alloc(hisi_sas_sht, sizeof(*hisi_hba));
1574 if (!shost)
1575 goto err_out;
1576 hisi_hba = shost_priv(shost);
1577
1578 hisi_hba->hw = &hisi_sas_v3_hw;
1579 hisi_hba->pci_dev = pdev;
1580 hisi_hba->dev = dev;
1581 hisi_hba->shost = shost;
1582 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
1583
1584 init_timer(&hisi_hba->timer);
1585
1586 if (hisi_sas_get_fw_info(hisi_hba) < 0)
1587 goto err_out;
1588
1589 if (hisi_sas_alloc(hisi_hba, shost)) {
1590 hisi_sas_free(hisi_hba);
1591 goto err_out;
1592 }
1593
1594 return shost;
1595err_out:
1596 dev_err(dev, "shost alloc failed\n");
1597 return NULL;
1598}
1599
92f61e3b
JG		 1600static int
1601hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1602{
e21fe3a5
JG		 1603 struct Scsi_Host *shost;
1604 struct hisi_hba *hisi_hba;
1605 struct device *dev = &pdev->dev;
1606 struct asd_sas_phy **arr_phy;
1607 struct asd_sas_port **arr_port;
1608 struct sas_ha_struct *sha;
1609 int rc, phy_nr, port_nr, i;
1610
1611 rc = pci_enable_device(pdev);
1612 if (rc)
1613 goto err_out;
1614
1615 pci_set_master(pdev);
1616
1617 rc = pci_request_regions(pdev, DRV_NAME);
1618 if (rc)
1619 goto err_out_disable_device;
1620
1621 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
1622 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
1623 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
1624 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)) != 0)) {
1625 dev_err(dev, "No usable DMA addressing method\n");
1626 rc = -EIO;
1627 goto err_out_regions;
1628 }
1629 }
1630
1631 shost = hisi_sas_shost_alloc_pci(pdev);
1632 if (!shost) {
1633 rc = -ENOMEM;
1634 goto err_out_regions;
1635 }
1636
1637 sha = SHOST_TO_SAS_HA(shost);
1638 hisi_hba = shost_priv(shost);
1639 dev_set_drvdata(dev, sha);
1640
1641 hisi_hba->regs = pcim_iomap(pdev, 5, 0);
1642 if (!hisi_hba->regs) {
1643 dev_err(dev, "cannot map register.\n");
1644 rc = -ENOMEM;
1645 goto err_out_ha;
1646 }
1647
1648 phy_nr = port_nr = hisi_hba->n_phy;
1649
1650 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
1651 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
1652 if (!arr_phy || !arr_port) {
1653 rc = -ENOMEM;
1654 goto err_out_ha;
1655 }
1656
1657 sha->sas_phy = arr_phy;
1658 sha->sas_port = arr_port;
1659 sha->core.shost = shost;
1660 sha->lldd_ha = hisi_hba;
1661
1662 shost->transportt = hisi_sas_stt;
1663 shost->max_id = HISI_SAS_MAX_DEVICES;
1664 shost->max_lun = ~0;
1665 shost->max_channel = 1;
1666 shost->max_cmd_len = 16;
1667 shost->sg_tablesize = min_t(u16, SG_ALL, HISI_SAS_SGE_PAGE_CNT);
1668 shost->can_queue = hisi_hba->hw->max_command_entries;
1669 shost->cmd_per_lun = hisi_hba->hw->max_command_entries;
1670
1671 sha->sas_ha_name = DRV_NAME;
1672 sha->dev = dev;
1673 sha->lldd_module = THIS_MODULE;
1674 sha->sas_addr = &hisi_hba->sas_addr[0];
1675 sha->num_phys = hisi_hba->n_phy;
1676 sha->core.shost = hisi_hba->shost;
1677
1678 for (i = 0; i < hisi_hba->n_phy; i++) {
1679 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
1680 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
1681 }
1682
1683 hisi_sas_init_add(hisi_hba);
1684
1685 rc = scsi_add_host(shost, dev);
1686 if (rc)
1687 goto err_out_ha;
1688
1689 rc = sas_register_ha(sha);
1690 if (rc)
1691 goto err_out_register_ha;
1692
1693 rc = hisi_hba->hw->hw_init(hisi_hba);
1694 if (rc)
1695 goto err_out_register_ha;
1696
1697 scsi_scan_host(shost);
1698
92f61e3b 1699 return 0;
e21fe3a5
JG		 1700
1701err_out_register_ha:
1702 scsi_remove_host(shost);
1703err_out_ha:
1704 kfree(shost);
1705err_out_regions:
1706 pci_release_regions(pdev);
1707err_out_disable_device:
1708 pci_disable_device(pdev);
1709err_out:
1710 return rc;
92f61e3b
JG		 1711}
1712
54edeee1
XC		 1713static void
1714hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba)
1715{
60b4a5ee
XC		 1716 int i;
1717
54edeee1
XC		 1718 free_irq(pci_irq_vector(pdev, 1), hisi_hba);
1719 free_irq(pci_irq_vector(pdev, 2), hisi_hba);
60b4a5ee
XC		 1720 for (i = 0; i < hisi_hba->queue_count; i++) {
1721 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1722
1723 free_irq(pci_irq_vector(pdev, i+16), cq);
1724 }
54edeee1
XC		 1725 pci_free_irq_vectors(pdev);
1726}
1727
92f61e3b
JG		 1728static void hisi_sas_v3_remove(struct pci_dev *pdev)
1729{
e21fe3a5
JG		 1730 struct device *dev = &pdev->dev;
1731 struct sas_ha_struct *sha = dev_get_drvdata(dev);
1732 struct hisi_hba *hisi_hba = sha->lldd_ha;
1733
1734 sas_unregister_ha(sha);
1735 sas_remove_host(sha->core.shost);
1736
1737 hisi_sas_free(hisi_hba);
54edeee1 1738 hisi_sas_v3_destroy_irqs(pdev, hisi_hba);
e21fe3a5
JG		 1739 pci_release_regions(pdev);
1740 pci_disable_device(pdev);
92f61e3b
JG		 1741}
1742
1743enum {
1744 /* instances of the controller */
1745 hip08,
1746};
1747
1748static const struct pci_device_id sas_v3_pci_table[] = {
1749 { PCI_VDEVICE(HUAWEI, 0xa230), hip08 },
1750 {}
1751};
1752
1753static struct pci_driver sas_v3_pci_driver = {
1754 .name = DRV_NAME,
1755 .id_table = sas_v3_pci_table,
1756 .probe = hisi_sas_v3_probe,
1757 .remove = hisi_sas_v3_remove,
1758};
1759
1760module_pci_driver(sas_v3_pci_driver);
1761
1762MODULE_VERSION(DRV_VERSION);
1763MODULE_LICENSE("GPL");
1764MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
1765MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device");
1766MODULE_ALIAS("platform:" DRV_NAME);
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