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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
92f61e3b JG |
2 | /* |
3 | * Copyright (c) 2017 Hisilicon Limited. | |
92f61e3b JG |
4 | */ |
5 | ||
6 | #include "hisi_sas.h" | |
7 | #define DRV_NAME "hisi_sas_v3_hw" | |
8 | ||
4a8bec88 | 9 | /* global registers need init */ |
c94d8ca2 XC |
10 | #define DLVRY_QUEUE_ENABLE 0x0 |
11 | #define IOST_BASE_ADDR_LO 0x8 | |
12 | #define IOST_BASE_ADDR_HI 0xc | |
13 | #define ITCT_BASE_ADDR_LO 0x10 | |
14 | #define ITCT_BASE_ADDR_HI 0x14 | |
15 | #define IO_BROKEN_MSG_ADDR_LO 0x18 | |
16 | #define IO_BROKEN_MSG_ADDR_HI 0x1c | |
3975f605 XC |
17 | #define PHY_CONTEXT 0x20 |
18 | #define PHY_STATE 0x24 | |
19 | #define PHY_PORT_NUM_MA 0x28 | |
20 | #define PHY_CONN_RATE 0x30 | |
182e7222 XC |
21 | #define ITCT_CLR 0x44 |
22 | #define ITCT_CLR_EN_OFF 16 | |
23 | #define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF) | |
24 | #define ITCT_DEV_OFF 0 | |
25 | #define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF) | |
97fcf176 | 26 | #define SAS_AXI_USER3 0x50 |
c94d8ca2 XC |
27 | #define IO_SATA_BROKEN_MSG_ADDR_LO 0x58 |
28 | #define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c | |
29 | #define SATA_INITI_D2H_STORE_ADDR_LO 0x60 | |
30 | #define SATA_INITI_D2H_STORE_ADDR_HI 0x64 | |
31 | #define CFG_MAX_TAG 0x68 | |
32 | #define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84 | |
33 | #define HGC_SAS_TXFAIL_RETRY_CTRL 0x88 | |
34 | #define HGC_GET_ITV_TIME 0x90 | |
35 | #define DEVICE_MSG_WORK_MODE 0x94 | |
36 | #define OPENA_WT_CONTI_TIME 0x9c | |
37 | #define I_T_NEXUS_LOSS_TIME 0xa0 | |
38 | #define MAX_CON_TIME_LIMIT_TIME 0xa4 | |
39 | #define BUS_INACTIVE_LIMIT_TIME 0xa8 | |
40 | #define REJECT_TO_OPEN_LIMIT_TIME 0xac | |
488cf558 | 41 | #define CQ_INT_CONVERGE_EN 0xb0 |
c94d8ca2 XC |
42 | #define CFG_AGING_TIME 0xbc |
43 | #define HGC_DFX_CFG2 0xc0 | |
44 | #define CFG_ABT_SET_QUERY_IPTT 0xd4 | |
45 | #define CFG_SET_ABORTED_IPTT_OFF 0 | |
46 | #define CFG_SET_ABORTED_IPTT_MSK (0xfff << CFG_SET_ABORTED_IPTT_OFF) | |
d30ff263 XC |
47 | #define CFG_SET_ABORTED_EN_OFF 12 |
48 | #define CFG_ABT_SET_IPTT_DONE 0xd8 | |
49 | #define CFG_ABT_SET_IPTT_DONE_OFF 0 | |
50 | #define HGC_IOMB_PROC1_STATUS 0x104 | |
3168d4f8 XT |
51 | #define HGC_LM_DFX_STATUS2 0x128 |
52 | #define HGC_LM_DFX_STATUS2_IOSTLIST_OFF 0 | |
53 | #define HGC_LM_DFX_STATUS2_IOSTLIST_MSK (0xfff << \ | |
54 | HGC_LM_DFX_STATUS2_IOSTLIST_OFF) | |
55 | #define HGC_LM_DFX_STATUS2_ITCTLIST_OFF 12 | |
56 | #define HGC_LM_DFX_STATUS2_ITCTLIST_MSK (0x7ff << \ | |
57 | HGC_LM_DFX_STATUS2_ITCTLIST_OFF) | |
58 | #define HGC_CQE_ECC_ADDR 0x13c | |
59 | #define HGC_CQE_ECC_1B_ADDR_OFF 0 | |
60 | #define HGC_CQE_ECC_1B_ADDR_MSK (0x3f << HGC_CQE_ECC_1B_ADDR_OFF) | |
61 | #define HGC_CQE_ECC_MB_ADDR_OFF 8 | |
62 | #define HGC_CQE_ECC_MB_ADDR_MSK (0x3f << HGC_CQE_ECC_MB_ADDR_OFF) | |
63 | #define HGC_IOST_ECC_ADDR 0x140 | |
64 | #define HGC_IOST_ECC_1B_ADDR_OFF 0 | |
65 | #define HGC_IOST_ECC_1B_ADDR_MSK (0x3ff << HGC_IOST_ECC_1B_ADDR_OFF) | |
66 | #define HGC_IOST_ECC_MB_ADDR_OFF 16 | |
67 | #define HGC_IOST_ECC_MB_ADDR_MSK (0x3ff << HGC_IOST_ECC_MB_ADDR_OFF) | |
68 | #define HGC_DQE_ECC_ADDR 0x144 | |
69 | #define HGC_DQE_ECC_1B_ADDR_OFF 0 | |
70 | #define HGC_DQE_ECC_1B_ADDR_MSK (0xfff << HGC_DQE_ECC_1B_ADDR_OFF) | |
71 | #define HGC_DQE_ECC_MB_ADDR_OFF 16 | |
72 | #define HGC_DQE_ECC_MB_ADDR_MSK (0xfff << HGC_DQE_ECC_MB_ADDR_OFF) | |
3975f605 | 73 | #define CHNL_INT_STATUS 0x148 |
bbe0a7b3 | 74 | #define TAB_DFX 0x14c |
3168d4f8 XT |
75 | #define HGC_ITCT_ECC_ADDR 0x150 |
76 | #define HGC_ITCT_ECC_1B_ADDR_OFF 0 | |
77 | #define HGC_ITCT_ECC_1B_ADDR_MSK (0x3ff << \ | |
78 | HGC_ITCT_ECC_1B_ADDR_OFF) | |
79 | #define HGC_ITCT_ECC_MB_ADDR_OFF 16 | |
80 | #define HGC_ITCT_ECC_MB_ADDR_MSK (0x3ff << \ | |
81 | HGC_ITCT_ECC_MB_ADDR_OFF) | |
fa231408 XT |
82 | #define HGC_AXI_FIFO_ERR_INFO 0x154 |
83 | #define AXI_ERR_INFO_OFF 0 | |
84 | #define AXI_ERR_INFO_MSK (0xff << AXI_ERR_INFO_OFF) | |
85 | #define FIFO_ERR_INFO_OFF 8 | |
86 | #define FIFO_ERR_INFO_MSK (0xff << FIFO_ERR_INFO_OFF) | |
bbe0a7b3 | 87 | #define TAB_RD_TYPE 0x15c |
c94d8ca2 XC |
88 | #define INT_COAL_EN 0x19c |
89 | #define OQ_INT_COAL_TIME 0x1a0 | |
90 | #define OQ_INT_COAL_CNT 0x1a4 | |
91 | #define ENT_INT_COAL_TIME 0x1a8 | |
92 | #define ENT_INT_COAL_CNT 0x1ac | |
93 | #define OQ_INT_SRC 0x1b0 | |
94 | #define OQ_INT_SRC_MSK 0x1b4 | |
95 | #define ENT_INT_SRC1 0x1b8 | |
96 | #define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0 | |
97 | #define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF) | |
98 | #define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8 | |
99 | #define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF) | |
100 | #define ENT_INT_SRC2 0x1bc | |
101 | #define ENT_INT_SRC3 0x1c0 | |
102 | #define ENT_INT_SRC3_WP_DEPTH_OFF 8 | |
103 | #define ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF 9 | |
104 | #define ENT_INT_SRC3_RP_DEPTH_OFF 10 | |
105 | #define ENT_INT_SRC3_AXI_OFF 11 | |
106 | #define ENT_INT_SRC3_FIFO_OFF 12 | |
107 | #define ENT_INT_SRC3_LM_OFF 14 | |
108 | #define ENT_INT_SRC3_ITC_INT_OFF 15 | |
109 | #define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF) | |
110 | #define ENT_INT_SRC3_ABT_OFF 16 | |
3168d4f8 XT |
111 | #define ENT_INT_SRC3_DQE_POISON_OFF 18 |
112 | #define ENT_INT_SRC3_IOST_POISON_OFF 19 | |
113 | #define ENT_INT_SRC3_ITCT_POISON_OFF 20 | |
114 | #define ENT_INT_SRC3_ITCT_NCQ_POISON_OFF 21 | |
c94d8ca2 XC |
115 | #define ENT_INT_SRC_MSK1 0x1c4 |
116 | #define ENT_INT_SRC_MSK2 0x1c8 | |
117 | #define ENT_INT_SRC_MSK3 0x1cc | |
3975f605 | 118 | #define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31 |
c94d8ca2 XC |
119 | #define CHNL_PHYUPDOWN_INT_MSK 0x1d0 |
120 | #define CHNL_ENT_INT_MSK 0x1d4 | |
121 | #define HGC_COM_INT_MSK 0x1d8 | |
3975f605 | 122 | #define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF) |
c94d8ca2 | 123 | #define SAS_ECC_INTR 0x1e8 |
3168d4f8 XT |
124 | #define SAS_ECC_INTR_DQE_ECC_1B_OFF 0 |
125 | #define SAS_ECC_INTR_DQE_ECC_MB_OFF 1 | |
126 | #define SAS_ECC_INTR_IOST_ECC_1B_OFF 2 | |
127 | #define SAS_ECC_INTR_IOST_ECC_MB_OFF 3 | |
128 | #define SAS_ECC_INTR_ITCT_ECC_1B_OFF 4 | |
129 | #define SAS_ECC_INTR_ITCT_ECC_MB_OFF 5 | |
130 | #define SAS_ECC_INTR_ITCTLIST_ECC_1B_OFF 6 | |
131 | #define SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF 7 | |
132 | #define SAS_ECC_INTR_IOSTLIST_ECC_1B_OFF 8 | |
133 | #define SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF 9 | |
134 | #define SAS_ECC_INTR_CQE_ECC_1B_OFF 10 | |
135 | #define SAS_ECC_INTR_CQE_ECC_MB_OFF 11 | |
136 | #define SAS_ECC_INTR_NCQ_MEM0_ECC_1B_OFF 12 | |
137 | #define SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF 13 | |
138 | #define SAS_ECC_INTR_NCQ_MEM1_ECC_1B_OFF 14 | |
139 | #define SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF 15 | |
140 | #define SAS_ECC_INTR_NCQ_MEM2_ECC_1B_OFF 16 | |
141 | #define SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF 17 | |
142 | #define SAS_ECC_INTR_NCQ_MEM3_ECC_1B_OFF 18 | |
143 | #define SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF 19 | |
144 | #define SAS_ECC_INTR_OOO_RAM_ECC_1B_OFF 20 | |
145 | #define SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF 21 | |
c94d8ca2 XC |
146 | #define SAS_ECC_INTR_MSK 0x1ec |
147 | #define HGC_ERR_STAT_EN 0x238 | |
a865ae14 | 148 | #define CQE_SEND_CNT 0x248 |
c94d8ca2 XC |
149 | #define DLVRY_Q_0_BASE_ADDR_LO 0x260 |
150 | #define DLVRY_Q_0_BASE_ADDR_HI 0x264 | |
151 | #define DLVRY_Q_0_DEPTH 0x268 | |
152 | #define DLVRY_Q_0_WR_PTR 0x26c | |
153 | #define DLVRY_Q_0_RD_PTR 0x270 | |
154 | #define HYPER_STREAM_ID_EN_CFG 0xc80 | |
155 | #define OQ0_INT_SRC_MSK 0xc90 | |
156 | #define COMPL_Q_0_BASE_ADDR_LO 0x4e0 | |
157 | #define COMPL_Q_0_BASE_ADDR_HI 0x4e4 | |
158 | #define COMPL_Q_0_DEPTH 0x4e8 | |
159 | #define COMPL_Q_0_WR_PTR 0x4ec | |
160 | #define COMPL_Q_0_RD_PTR 0x4f0 | |
3168d4f8 XT |
161 | #define HGC_RXM_DFX_STATUS14 0xae8 |
162 | #define HGC_RXM_DFX_STATUS14_MEM0_OFF 0 | |
163 | #define HGC_RXM_DFX_STATUS14_MEM0_MSK (0x1ff << \ | |
164 | HGC_RXM_DFX_STATUS14_MEM0_OFF) | |
165 | #define HGC_RXM_DFX_STATUS14_MEM1_OFF 9 | |
166 | #define HGC_RXM_DFX_STATUS14_MEM1_MSK (0x1ff << \ | |
167 | HGC_RXM_DFX_STATUS14_MEM1_OFF) | |
168 | #define HGC_RXM_DFX_STATUS14_MEM2_OFF 18 | |
169 | #define HGC_RXM_DFX_STATUS14_MEM2_MSK (0x1ff << \ | |
170 | HGC_RXM_DFX_STATUS14_MEM2_OFF) | |
171 | #define HGC_RXM_DFX_STATUS15 0xaec | |
172 | #define HGC_RXM_DFX_STATUS15_MEM3_OFF 0 | |
173 | #define HGC_RXM_DFX_STATUS15_MEM3_MSK (0x1ff << \ | |
174 | HGC_RXM_DFX_STATUS15_MEM3_OFF) | |
c94d8ca2 XC |
175 | #define AWQOS_AWCACHE_CFG 0xc84 |
176 | #define ARQOS_ARCACHE_CFG 0xc88 | |
f70c1251 | 177 | #define HILINK_ERR_DFX 0xe04 |
428f1b34 XT |
178 | #define SAS_GPIO_CFG_0 0x1000 |
179 | #define SAS_GPIO_CFG_1 0x1004 | |
180 | #define SAS_GPIO_TX_0_1 0x1040 | |
181 | #define SAS_CFG_DRIVE_VLD 0x1070 | |
c94d8ca2 XC |
182 | |
183 | /* phy registers requiring init */ | |
184 | #define PORT_BASE (0x2000) | |
3975f605 XC |
185 | #define PHY_CFG (PORT_BASE + 0x0) |
186 | #define HARD_PHY_LINKRATE (PORT_BASE + 0x4) | |
187 | #define PHY_CFG_ENA_OFF 0 | |
188 | #define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF) | |
189 | #define PHY_CFG_DC_OPT_OFF 2 | |
190 | #define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF) | |
25908cac XT |
191 | #define PHY_CFG_PHY_RST_OFF 3 |
192 | #define PHY_CFG_PHY_RST_MSK (0x1 << PHY_CFG_PHY_RST_OFF) | |
c94d8ca2 | 193 | #define PROG_PHY_LINK_RATE (PORT_BASE + 0x8) |
97b151e7 XC |
194 | #define CFG_PROG_PHY_LINK_RATE_OFF 8 |
195 | #define CFG_PROG_PHY_LINK_RATE_MSK (0xf << CFG_PROG_PHY_LINK_RATE_OFF) | |
c94d8ca2 XC |
196 | #define PHY_CTRL (PORT_BASE + 0x14) |
197 | #define PHY_CTRL_RESET_OFF 0 | |
198 | #define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF) | |
d6a9000b XC |
199 | #define CMD_HDR_PIR_OFF 8 |
200 | #define CMD_HDR_PIR_MSK (0x1 << CMD_HDR_PIR_OFF) | |
cf9efd5d | 201 | #define SERDES_CFG (PORT_BASE + 0x1c) |
97b151e7 XC |
202 | #define CFG_ALOS_CHK_DISABLE_OFF 9 |
203 | #define CFG_ALOS_CHK_DISABLE_MSK (0x1 << CFG_ALOS_CHK_DISABLE_OFF) | |
204 | #define SAS_PHY_BIST_CTRL (PORT_BASE + 0x2c) | |
205 | #define CFG_BIST_MODE_SEL_OFF 0 | |
206 | #define CFG_BIST_MODE_SEL_MSK (0xf << CFG_BIST_MODE_SEL_OFF) | |
207 | #define CFG_LOOP_TEST_MODE_OFF 14 | |
208 | #define CFG_LOOP_TEST_MODE_MSK (0x3 << CFG_LOOP_TEST_MODE_OFF) | |
209 | #define CFG_RX_BIST_EN_OFF 16 | |
210 | #define CFG_RX_BIST_EN_MSK (0x1 << CFG_RX_BIST_EN_OFF) | |
211 | #define CFG_TX_BIST_EN_OFF 17 | |
212 | #define CFG_TX_BIST_EN_MSK (0x1 << CFG_TX_BIST_EN_OFF) | |
213 | #define CFG_BIST_TEST_OFF 18 | |
214 | #define CFG_BIST_TEST_MSK (0x1 << CFG_BIST_TEST_OFF) | |
215 | #define SAS_PHY_BIST_CODE (PORT_BASE + 0x30) | |
216 | #define SAS_PHY_BIST_CODE1 (PORT_BASE + 0x34) | |
217 | #define SAS_BIST_ERR_CNT (PORT_BASE + 0x38) | |
c94d8ca2 | 218 | #define SL_CFG (PORT_BASE + 0x84) |
3bccfba8 | 219 | #define AIP_LIMIT (PORT_BASE + 0x90) |
3975f605 XC |
220 | #define SL_CONTROL (PORT_BASE + 0x94) |
221 | #define SL_CONTROL_NOTIFY_EN_OFF 0 | |
222 | #define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF) | |
223 | #define SL_CTA_OFF 17 | |
224 | #define SL_CTA_MSK (0x1 << SL_CTA_OFF) | |
1324ae1c XT |
225 | #define RX_PRIMS_STATUS (PORT_BASE + 0x98) |
226 | #define RX_BCAST_CHG_OFF 1 | |
227 | #define RX_BCAST_CHG_MSK (0x1 << RX_BCAST_CHG_OFF) | |
3975f605 XC |
228 | #define TX_ID_DWORD0 (PORT_BASE + 0x9c) |
229 | #define TX_ID_DWORD1 (PORT_BASE + 0xa0) | |
230 | #define TX_ID_DWORD2 (PORT_BASE + 0xa4) | |
231 | #define TX_ID_DWORD3 (PORT_BASE + 0xa8) | |
232 | #define TX_ID_DWORD4 (PORT_BASE + 0xaC) | |
233 | #define TX_ID_DWORD5 (PORT_BASE + 0xb0) | |
234 | #define TX_ID_DWORD6 (PORT_BASE + 0xb4) | |
235 | #define TXID_AUTO (PORT_BASE + 0xb8) | |
236 | #define CT3_OFF 1 | |
237 | #define CT3_MSK (0x1 << CT3_OFF) | |
402cd9f0 XC |
238 | #define TX_HARDRST_OFF 2 |
239 | #define TX_HARDRST_MSK (0x1 << TX_HARDRST_OFF) | |
3975f605 | 240 | #define RX_IDAF_DWORD0 (PORT_BASE + 0xc4) |
c94d8ca2 | 241 | #define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc) |
81036731 | 242 | #define STP_LINK_TIMER (PORT_BASE + 0x120) |
057c3d1f | 243 | #define STP_LINK_TIMEOUT_STATE (PORT_BASE + 0x124) |
d40bfb0d | 244 | #define CON_CFG_DRIVER (PORT_BASE + 0x130) |
c94d8ca2 XC |
245 | #define SAS_SSP_CON_TIMER_CFG (PORT_BASE + 0x134) |
246 | #define SAS_SMP_CON_TIMER_CFG (PORT_BASE + 0x138) | |
247 | #define SAS_STP_CON_TIMER_CFG (PORT_BASE + 0x13c) | |
248 | #define CHL_INT0 (PORT_BASE + 0x1b4) | |
249 | #define CHL_INT0_HOTPLUG_TOUT_OFF 0 | |
250 | #define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF) | |
251 | #define CHL_INT0_SL_RX_BCST_ACK_OFF 1 | |
252 | #define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF) | |
253 | #define CHL_INT0_SL_PHY_ENABLE_OFF 2 | |
254 | #define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF) | |
255 | #define CHL_INT0_NOT_RDY_OFF 4 | |
256 | #define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF) | |
257 | #define CHL_INT0_PHY_RDY_OFF 5 | |
258 | #define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF) | |
259 | #define CHL_INT1 (PORT_BASE + 0x1b8) | |
3168d4f8 XT |
260 | #define CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF 15 |
261 | #define CHL_INT1_DMAC_TX_ECC_1B_ERR_OFF 16 | |
262 | #define CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF 17 | |
263 | #define CHL_INT1_DMAC_RX_ECC_1B_ERR_OFF 18 | |
4a6125c5 XT |
264 | #define CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF 19 |
265 | #define CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF 20 | |
266 | #define CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF 21 | |
267 | #define CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF 22 | |
3168d4f8 XT |
268 | #define CHL_INT1_DMAC_TX_FIFO_ERR_OFF 23 |
269 | #define CHL_INT1_DMAC_RX_FIFO_ERR_OFF 24 | |
270 | #define CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF 26 | |
271 | #define CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF 27 | |
c94d8ca2 | 272 | #define CHL_INT2 (PORT_BASE + 0x1bc) |
057c3d1f | 273 | #define CHL_INT2_SL_IDAF_TOUT_CONF_OFF 0 |
aaeb8232 XT |
274 | #define CHL_INT2_RX_DISP_ERR_OFF 28 |
275 | #define CHL_INT2_RX_CODE_ERR_OFF 29 | |
f70c1251 | 276 | #define CHL_INT2_RX_INVLD_DW_OFF 30 |
057c3d1f | 277 | #define CHL_INT2_STP_LINK_TIMEOUT_OFF 31 |
c94d8ca2 XC |
278 | #define CHL_INT0_MSK (PORT_BASE + 0x1c0) |
279 | #define CHL_INT1_MSK (PORT_BASE + 0x1c4) | |
280 | #define CHL_INT2_MSK (PORT_BASE + 0x1c8) | |
61a6ebf3 | 281 | #define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc) |
c94d8ca2 | 282 | #define CHL_INT_COAL_EN (PORT_BASE + 0x1d0) |
15c38e31 | 283 | #define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4) |
c94d8ca2 XC |
284 | #define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0) |
285 | #define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4) | |
286 | #define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8) | |
287 | #define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc) | |
288 | #define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0) | |
289 | #define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4) | |
a25d0d3d XC |
290 | #define DMA_TX_STATUS (PORT_BASE + 0x2d0) |
291 | #define DMA_TX_STATUS_BUSY_OFF 0 | |
292 | #define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF) | |
293 | #define DMA_RX_STATUS (PORT_BASE + 0x2e8) | |
294 | #define DMA_RX_STATUS_BUSY_OFF 0 | |
295 | #define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF) | |
15c38e31 XT |
296 | |
297 | #define COARSETUNE_TIME (PORT_BASE + 0x304) | |
ffc8f149 XT |
298 | #define ERR_CNT_DWS_LOST (PORT_BASE + 0x380) |
299 | #define ERR_CNT_RESET_PROB (PORT_BASE + 0x384) | |
300 | #define ERR_CNT_INVLD_DW (PORT_BASE + 0x390) | |
61a6ebf3 | 301 | #define ERR_CNT_CODE_ERR (PORT_BASE + 0x394) |
ffc8f149 | 302 | #define ERR_CNT_DISP_ERR (PORT_BASE + 0x398) |
a25d0d3d | 303 | |
a25d0d3d XC |
304 | #define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */ |
305 | #if (HISI_SAS_MAX_DEVICES > DEFAULT_ITCT_HW) | |
306 | #error Max ITCT exceeded | |
307 | #endif | |
308 | ||
309 | #define AXI_MASTER_CFG_BASE (0x5000) | |
310 | #define AM_CTRL_GLOBAL (0x0) | |
e8ce775e XT |
311 | #define AM_CTRL_SHUTDOWN_REQ_OFF 0 |
312 | #define AM_CTRL_SHUTDOWN_REQ_MSK (0x1 << AM_CTRL_SHUTDOWN_REQ_OFF) | |
a25d0d3d XC |
313 | #define AM_CURR_TRANS_RETURN (0x150) |
314 | ||
315 | #define AM_CFG_MAX_TRANS (0x5010) | |
316 | #define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014) | |
317 | #define AXI_CFG (0x5100) | |
318 | #define AM_ROB_ECC_ERR_ADDR (0x510c) | |
3168d4f8 XT |
319 | #define AM_ROB_ECC_ERR_ADDR_OFF 0 |
320 | #define AM_ROB_ECC_ERR_ADDR_MSK 0xffffffff | |
c94d8ca2 | 321 | |
1aaf81e0 XT |
322 | /* RAS registers need init */ |
323 | #define RAS_BASE (0x6000) | |
324 | #define SAS_RAS_INTR0 (RAS_BASE) | |
325 | #define SAS_RAS_INTR1 (RAS_BASE + 0x04) | |
326 | #define SAS_RAS_INTR0_MASK (RAS_BASE + 0x08) | |
327 | #define SAS_RAS_INTR1_MASK (RAS_BASE + 0x0c) | |
61573630 XT |
328 | #define CFG_SAS_RAS_INTR_MASK (RAS_BASE + 0x1c) |
329 | #define SAS_RAS_INTR2 (RAS_BASE + 0x20) | |
330 | #define SAS_RAS_INTR2_MASK (RAS_BASE + 0x24) | |
1aaf81e0 | 331 | |
a2204723 XC |
332 | /* HW dma structures */ |
333 | /* Delivery queue header */ | |
334 | /* dw0 */ | |
4de0ca69 XC |
335 | #define CMD_HDR_ABORT_FLAG_OFF 0 |
336 | #define CMD_HDR_ABORT_FLAG_MSK (0x3 << CMD_HDR_ABORT_FLAG_OFF) | |
337 | #define CMD_HDR_ABORT_DEVICE_TYPE_OFF 2 | |
338 | #define CMD_HDR_ABORT_DEVICE_TYPE_MSK (0x1 << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
a2204723 XC |
339 | #define CMD_HDR_RESP_REPORT_OFF 5 |
340 | #define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF) | |
341 | #define CMD_HDR_TLR_CTRL_OFF 6 | |
342 | #define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF) | |
343 | #define CMD_HDR_PORT_OFF 18 | |
344 | #define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF) | |
345 | #define CMD_HDR_PRIORITY_OFF 27 | |
346 | #define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF) | |
347 | #define CMD_HDR_CMD_OFF 29 | |
348 | #define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF) | |
349 | /* dw1 */ | |
ce60689e | 350 | #define CMD_HDR_UNCON_CMD_OFF 3 |
a2204723 XC |
351 | #define CMD_HDR_DIR_OFF 5 |
352 | #define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF) | |
ce60689e XC |
353 | #define CMD_HDR_RESET_OFF 7 |
354 | #define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF) | |
a2204723 XC |
355 | #define CMD_HDR_VDTL_OFF 10 |
356 | #define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF) | |
357 | #define CMD_HDR_FRAME_TYPE_OFF 11 | |
358 | #define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF) | |
359 | #define CMD_HDR_DEV_ID_OFF 16 | |
360 | #define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF) | |
361 | /* dw2 */ | |
362 | #define CMD_HDR_CFL_OFF 0 | |
363 | #define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF) | |
ce60689e XC |
364 | #define CMD_HDR_NCQ_TAG_OFF 10 |
365 | #define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF) | |
a2204723 XC |
366 | #define CMD_HDR_MRFL_OFF 15 |
367 | #define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF) | |
368 | #define CMD_HDR_SG_MOD_OFF 24 | |
369 | #define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF) | |
fa913de2 XC |
370 | /* dw3 */ |
371 | #define CMD_HDR_IPTT_OFF 0 | |
372 | #define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF) | |
a2204723 XC |
373 | /* dw6 */ |
374 | #define CMD_HDR_DIF_SGL_LEN_OFF 0 | |
375 | #define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF) | |
376 | #define CMD_HDR_DATA_SGL_LEN_OFF 16 | |
377 | #define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF) | |
4de0ca69 XC |
378 | /* dw7 */ |
379 | #define CMD_HDR_ADDR_MODE_SEL_OFF 15 | |
380 | #define CMD_HDR_ADDR_MODE_SEL_MSK (1 << CMD_HDR_ADDR_MODE_SEL_OFF) | |
381 | #define CMD_HDR_ABORT_IPTT_OFF 16 | |
382 | #define CMD_HDR_ABORT_IPTT_MSK (0xffff << CMD_HDR_ABORT_IPTT_OFF) | |
a2204723 | 383 | |
60b4a5ee XC |
384 | /* Completion header */ |
385 | /* dw0 */ | |
386 | #define CMPLT_HDR_CMPLT_OFF 0 | |
387 | #define CMPLT_HDR_CMPLT_MSK (0x3 << CMPLT_HDR_CMPLT_OFF) | |
388 | #define CMPLT_HDR_ERROR_PHASE_OFF 2 | |
389 | #define CMPLT_HDR_ERROR_PHASE_MSK (0xff << CMPLT_HDR_ERROR_PHASE_OFF) | |
390 | #define CMPLT_HDR_RSPNS_XFRD_OFF 10 | |
391 | #define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF) | |
392 | #define CMPLT_HDR_ERX_OFF 12 | |
393 | #define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF) | |
394 | #define CMPLT_HDR_ABORT_STAT_OFF 13 | |
395 | #define CMPLT_HDR_ABORT_STAT_MSK (0x7 << CMPLT_HDR_ABORT_STAT_OFF) | |
396 | /* abort_stat */ | |
397 | #define STAT_IO_NOT_VALID 0x1 | |
398 | #define STAT_IO_NO_DEVICE 0x2 | |
399 | #define STAT_IO_COMPLETE 0x3 | |
400 | #define STAT_IO_ABORTED 0x4 | |
401 | /* dw1 */ | |
402 | #define CMPLT_HDR_IPTT_OFF 0 | |
403 | #define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF) | |
404 | #define CMPLT_HDR_DEV_ID_OFF 16 | |
405 | #define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF) | |
406 | /* dw3 */ | |
407 | #define CMPLT_HDR_IO_IN_TARGET_OFF 17 | |
408 | #define CMPLT_HDR_IO_IN_TARGET_MSK (0x1 << CMPLT_HDR_IO_IN_TARGET_OFF) | |
409 | ||
182e7222 XC |
410 | /* ITCT header */ |
411 | /* qw0 */ | |
412 | #define ITCT_HDR_DEV_TYPE_OFF 0 | |
413 | #define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF) | |
414 | #define ITCT_HDR_VALID_OFF 2 | |
415 | #define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF) | |
416 | #define ITCT_HDR_MCR_OFF 5 | |
417 | #define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF) | |
418 | #define ITCT_HDR_VLN_OFF 9 | |
419 | #define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF) | |
420 | #define ITCT_HDR_SMP_TIMEOUT_OFF 16 | |
421 | #define ITCT_HDR_AWT_CONTINUE_OFF 25 | |
422 | #define ITCT_HDR_PORT_ID_OFF 28 | |
423 | #define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF) | |
424 | /* qw2 */ | |
425 | #define ITCT_HDR_INLT_OFF 0 | |
426 | #define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF) | |
427 | #define ITCT_HDR_RTOLT_OFF 48 | |
428 | #define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF) | |
429 | ||
d6a9000b XC |
430 | struct hisi_sas_protect_iu_v3_hw { |
431 | u32 dw0; | |
432 | u32 lbrtcv; | |
433 | u32 lbrtgv; | |
434 | u32 dw3; | |
435 | u32 dw4; | |
436 | u32 dw5; | |
437 | u32 rsv; | |
438 | }; | |
439 | ||
c94d8ca2 XC |
440 | struct hisi_sas_complete_v3_hdr { |
441 | __le32 dw0; | |
442 | __le32 dw1; | |
443 | __le32 act; | |
444 | __le32 dw3; | |
445 | }; | |
446 | ||
60b4a5ee XC |
447 | struct hisi_sas_err_record_v3 { |
448 | /* dw0 */ | |
449 | __le32 trans_tx_fail_type; | |
450 | ||
451 | /* dw1 */ | |
452 | __le32 trans_rx_fail_type; | |
453 | ||
454 | /* dw2 */ | |
455 | __le16 dma_tx_err_type; | |
456 | __le16 sipc_rx_err_type; | |
457 | ||
458 | /* dw3 */ | |
459 | __le32 dma_rx_err_type; | |
460 | }; | |
461 | ||
462 | #define RX_DATA_LEN_UNDERFLOW_OFF 6 | |
463 | #define RX_DATA_LEN_UNDERFLOW_MSK (1 << RX_DATA_LEN_UNDERFLOW_OFF) | |
464 | ||
c94d8ca2 | 465 | #define HISI_SAS_COMMAND_ENTRIES_V3_HW 4096 |
3975f605 XC |
466 | #define HISI_SAS_MSI_COUNT_V3_HW 32 |
467 | ||
a2204723 XC |
468 | #define DIR_NO_DATA 0 |
469 | #define DIR_TO_INI 1 | |
470 | #define DIR_TO_DEVICE 2 | |
471 | #define DIR_RESERVED 3 | |
472 | ||
94135327 XC |
473 | #define FIS_CMD_IS_UNCONSTRAINED(fis) \ |
474 | ((fis.command == ATA_CMD_READ_LOG_EXT) || \ | |
475 | (fis.command == ATA_CMD_READ_LOG_DMA_EXT) || \ | |
476 | ((fis.command == ATA_CMD_DEV_RESET) && \ | |
477 | ((fis.control & ATA_SRST) != 0))) | |
ce60689e | 478 | |
d6a9000b XC |
479 | #define T10_INSRT_EN_OFF 0 |
480 | #define T10_INSRT_EN_MSK (1 << T10_INSRT_EN_OFF) | |
481 | #define T10_RMV_EN_OFF 1 | |
482 | #define T10_RMV_EN_MSK (1 << T10_RMV_EN_OFF) | |
483 | #define T10_RPLC_EN_OFF 2 | |
484 | #define T10_RPLC_EN_MSK (1 << T10_RPLC_EN_OFF) | |
485 | #define T10_CHK_EN_OFF 3 | |
486 | #define T10_CHK_EN_MSK (1 << T10_CHK_EN_OFF) | |
487 | #define INCR_LBRT_OFF 5 | |
488 | #define INCR_LBRT_MSK (1 << INCR_LBRT_OFF) | |
489 | #define USR_DATA_BLOCK_SZ_OFF 20 | |
490 | #define USR_DATA_BLOCK_SZ_MSK (0x3 << USR_DATA_BLOCK_SZ_OFF) | |
491 | #define T10_CHK_MSK_OFF 16 | |
b3cce125 XC |
492 | #define T10_CHK_REF_TAG_MSK (0xf0 << T10_CHK_MSK_OFF) |
493 | #define T10_CHK_APP_TAG_MSK (0xc << T10_CHK_MSK_OFF) | |
d6a9000b | 494 | |
795f25a3 | 495 | #define BASE_VECTORS_V3_HW 16 |
4fefe5bb | 496 | #define MIN_AFFINE_VECTORS_V3_HW (BASE_VECTORS_V3_HW + 1) |
d6a9000b | 497 | |
3168d4f8 XT |
498 | enum { |
499 | DSM_FUNC_ERR_HANDLE_MSI = 0, | |
500 | }; | |
501 | ||
488cf558 XC |
502 | static bool hisi_sas_intr_conv; |
503 | MODULE_PARM_DESC(intr_conv, "interrupt converge enable (0-1)"); | |
504 | ||
d6a9000b XC |
505 | /* permit overriding the host protection capabilities mask (EEDP/T10 PI) */ |
506 | static int prot_mask; | |
507 | module_param(prot_mask, int, 0); | |
508 | MODULE_PARM_DESC(prot_mask, " host protection capabilities mask, def=0x0 "); | |
509 | ||
4fefe5bb XC |
510 | static bool auto_affine_msi_experimental; |
511 | module_param(auto_affine_msi_experimental, bool, 0444); | |
512 | MODULE_PARM_DESC(auto_affine_msi_experimental, "Enable auto-affinity of MSI IRQs as experimental:\n" | |
513 | "default is off"); | |
514 | ||
54edeee1 XC |
515 | static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off) |
516 | { | |
517 | void __iomem *regs = hisi_hba->regs + off; | |
518 | ||
519 | return readl(regs); | |
520 | } | |
521 | ||
c94d8ca2 XC |
522 | static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val) |
523 | { | |
524 | void __iomem *regs = hisi_hba->regs + off; | |
525 | ||
526 | writel(val, regs); | |
527 | } | |
528 | ||
529 | static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no, | |
530 | u32 off, u32 val) | |
531 | { | |
532 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
533 | ||
534 | writel(val, regs); | |
535 | } | |
536 | ||
3975f605 XC |
537 | static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba, |
538 | int phy_no, u32 off) | |
539 | { | |
540 | void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off; | |
541 | ||
542 | return readl(regs); | |
543 | } | |
544 | ||
9b8addf3 JG |
545 | #define hisi_sas_read32_poll_timeout(off, val, cond, delay_us, \ |
546 | timeout_us) \ | |
547 | ({ \ | |
548 | void __iomem *regs = hisi_hba->regs + off; \ | |
549 | readl_poll_timeout(regs, val, cond, delay_us, timeout_us); \ | |
550 | }) | |
551 | ||
552 | #define hisi_sas_read32_poll_timeout_atomic(off, val, cond, delay_us, \ | |
553 | timeout_us) \ | |
554 | ({ \ | |
555 | void __iomem *regs = hisi_hba->regs + off; \ | |
556 | readl_poll_timeout_atomic(regs, val, cond, delay_us, timeout_us);\ | |
557 | }) | |
558 | ||
c94d8ca2 XC |
559 | static void init_reg_v3_hw(struct hisi_hba *hisi_hba) |
560 | { | |
561 | int i; | |
562 | ||
563 | /* Global registers init */ | |
564 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, | |
565 | (u32)((1ULL << hisi_hba->queue_count) - 1)); | |
97fcf176 | 566 | hisi_sas_write32(hisi_hba, SAS_AXI_USER3, 0); |
3297ded1 | 567 | hisi_sas_write32(hisi_hba, CFG_MAX_TAG, 0xfff0400); |
c94d8ca2 | 568 | hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108); |
3bccfba8 | 569 | hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1); |
c94d8ca2 XC |
570 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); |
571 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
572 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
488cf558 XC |
573 | hisi_sas_write32(hisi_hba, CQ_INT_CONVERGE_EN, |
574 | hisi_sas_intr_conv); | |
c94d8ca2 XC |
575 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0xffff); |
576 | hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff); | |
577 | hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff); | |
578 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff); | |
579 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xfefefefe); | |
580 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xfefefefe); | |
3168d4f8 | 581 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffc220ff); |
c94d8ca2 XC |
582 | hisi_sas_write32(hisi_hba, CHNL_PHYUPDOWN_INT_MSK, 0x0); |
583 | hisi_sas_write32(hisi_hba, CHNL_ENT_INT_MSK, 0x0); | |
584 | hisi_sas_write32(hisi_hba, HGC_COM_INT_MSK, 0x0); | |
3168d4f8 | 585 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0x155555); |
c94d8ca2 XC |
586 | hisi_sas_write32(hisi_hba, AWQOS_AWCACHE_CFG, 0xf0f0); |
587 | hisi_sas_write32(hisi_hba, ARQOS_ARCACHE_CFG, 0xf0f0); | |
588 | for (i = 0; i < hisi_hba->queue_count; i++) | |
589 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0); | |
590 | ||
c94d8ca2 | 591 | hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1); |
c94d8ca2 XC |
592 | |
593 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
c2c1d9de XC |
594 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; |
595 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
596 | u32 prog_phy_link_rate = 0x800; | |
597 | ||
598 | if (!sas_phy->phy || (sas_phy->phy->maximum_linkrate < | |
599 | SAS_LINK_RATE_1_5_GBPS)) { | |
600 | prog_phy_link_rate = 0x855; | |
601 | } else { | |
602 | enum sas_linkrate max = sas_phy->phy->maximum_linkrate; | |
603 | ||
604 | prog_phy_link_rate = | |
605 | hisi_sas_get_prog_phy_linkrate_mask(max) | | |
606 | 0x800; | |
607 | } | |
608 | hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, | |
609 | prog_phy_link_rate); | |
cf9efd5d | 610 | hisi_sas_phy_write32(hisi_hba, i, SERDES_CFG, 0xffc00); |
15c38e31 | 611 | hisi_sas_phy_write32(hisi_hba, i, SAS_RX_TRAIN_TIMER, 0x13e80); |
c94d8ca2 XC |
612 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff); |
613 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff); | |
614 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff); | |
615 | hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000); | |
3168d4f8 | 616 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xf2057fff); |
057c3d1f | 617 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffbfe); |
c94d8ca2 XC |
618 | hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0); |
619 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0); | |
620 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0); | |
621 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0); | |
622 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0); | |
15c38e31 XT |
623 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x1); |
624 | hisi_sas_phy_write32(hisi_hba, i, STP_LINK_TIMER, 0x7f7a120); | |
7931cd91 | 625 | hisi_sas_phy_write32(hisi_hba, i, CON_CFG_DRIVER, 0x2a0a01); |
15bc43f3 | 626 | hisi_sas_phy_write32(hisi_hba, i, SAS_SSP_CON_TIMER_CFG, 0x32); |
aaeb8232 XT |
627 | hisi_sas_phy_write32(hisi_hba, i, SAS_EC_INT_COAL_TIME, |
628 | 0x30f4240); | |
15c38e31 XT |
629 | /* used for 12G negotiate */ |
630 | hisi_sas_phy_write32(hisi_hba, i, COARSETUNE_TIME, 0x1e); | |
3bccfba8 | 631 | hisi_sas_phy_write32(hisi_hba, i, AIP_LIMIT, 0x2ffff); |
c94d8ca2 | 632 | } |
15c38e31 | 633 | |
c94d8ca2 XC |
634 | for (i = 0; i < hisi_hba->queue_count; i++) { |
635 | /* Delivery queue */ | |
636 | hisi_sas_write32(hisi_hba, | |
637 | DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14), | |
638 | upper_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
639 | ||
640 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14), | |
641 | lower_32_bits(hisi_hba->cmd_hdr_dma[i])); | |
642 | ||
643 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14), | |
644 | HISI_SAS_QUEUE_SLOTS); | |
645 | ||
646 | /* Completion queue */ | |
647 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14), | |
648 | upper_32_bits(hisi_hba->complete_hdr_dma[i])); | |
649 | ||
650 | hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14), | |
651 | lower_32_bits(hisi_hba->complete_hdr_dma[i])); | |
652 | ||
653 | hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14), | |
654 | HISI_SAS_QUEUE_SLOTS); | |
655 | } | |
656 | ||
657 | /* itct */ | |
658 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO, | |
659 | lower_32_bits(hisi_hba->itct_dma)); | |
660 | ||
661 | hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI, | |
662 | upper_32_bits(hisi_hba->itct_dma)); | |
663 | ||
664 | /* iost */ | |
665 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO, | |
666 | lower_32_bits(hisi_hba->iost_dma)); | |
667 | ||
668 | hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI, | |
669 | upper_32_bits(hisi_hba->iost_dma)); | |
670 | ||
671 | /* breakpoint */ | |
672 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO, | |
673 | lower_32_bits(hisi_hba->breakpoint_dma)); | |
674 | ||
675 | hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI, | |
676 | upper_32_bits(hisi_hba->breakpoint_dma)); | |
677 | ||
678 | /* SATA broken msg */ | |
679 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO, | |
680 | lower_32_bits(hisi_hba->sata_breakpoint_dma)); | |
681 | ||
682 | hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI, | |
683 | upper_32_bits(hisi_hba->sata_breakpoint_dma)); | |
684 | ||
685 | /* SATA initial fis */ | |
686 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO, | |
687 | lower_32_bits(hisi_hba->initial_fis_dma)); | |
688 | ||
689 | hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI, | |
690 | upper_32_bits(hisi_hba->initial_fis_dma)); | |
1aaf81e0 XT |
691 | |
692 | /* RAS registers init */ | |
693 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR0_MASK, 0x0); | |
694 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR1_MASK, 0x0); | |
61573630 XT |
695 | hisi_sas_write32(hisi_hba, SAS_RAS_INTR2_MASK, 0x0); |
696 | hisi_sas_write32(hisi_hba, CFG_SAS_RAS_INTR_MASK, 0x0); | |
428f1b34 XT |
697 | |
698 | /* LED registers init */ | |
699 | hisi_sas_write32(hisi_hba, SAS_CFG_DRIVE_VLD, 0x80000ff); | |
700 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1, 0x80808080); | |
701 | hisi_sas_write32(hisi_hba, SAS_GPIO_TX_0_1 + 0x4, 0x80808080); | |
702 | /* Configure blink generator rate A to 1Hz and B to 4Hz */ | |
703 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_1, 0x121700); | |
704 | hisi_sas_write32(hisi_hba, SAS_GPIO_CFG_0, 0x800000); | |
c94d8ca2 XC |
705 | } |
706 | ||
3975f605 XC |
707 | static void config_phy_opt_mode_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
708 | { | |
709 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
710 | ||
711 | cfg &= ~PHY_CFG_DC_OPT_MSK; | |
712 | cfg |= 1 << PHY_CFG_DC_OPT_OFF; | |
713 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
714 | } | |
715 | ||
716 | static void config_id_frame_v3_hw(struct hisi_hba *hisi_hba, int phy_no) | |
717 | { | |
718 | struct sas_identify_frame identify_frame; | |
719 | u32 *identify_buffer; | |
720 | ||
721 | memset(&identify_frame, 0, sizeof(identify_frame)); | |
722 | identify_frame.dev_type = SAS_END_DEVICE; | |
723 | identify_frame.frame_type = 0; | |
724 | identify_frame._un1 = 1; | |
725 | identify_frame.initiator_bits = SAS_PROTOCOL_ALL; | |
726 | identify_frame.target_bits = SAS_PROTOCOL_NONE; | |
727 | memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
728 | memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE); | |
729 | identify_frame.phy_id = phy_no; | |
730 | identify_buffer = (u32 *)(&identify_frame); | |
731 | ||
732 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0, | |
733 | __swab32(identify_buffer[0])); | |
734 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1, | |
735 | __swab32(identify_buffer[1])); | |
736 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2, | |
737 | __swab32(identify_buffer[2])); | |
738 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3, | |
739 | __swab32(identify_buffer[3])); | |
740 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4, | |
741 | __swab32(identify_buffer[4])); | |
742 | hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5, | |
743 | __swab32(identify_buffer[5])); | |
744 | } | |
745 | ||
182e7222 XC |
746 | static void setup_itct_v3_hw(struct hisi_hba *hisi_hba, |
747 | struct hisi_sas_device *sas_dev) | |
748 | { | |
749 | struct domain_device *device = sas_dev->sas_device; | |
750 | struct device *dev = hisi_hba->dev; | |
751 | u64 qw0, device_id = sas_dev->device_id; | |
752 | struct hisi_sas_itct *itct = &hisi_hba->itct[device_id]; | |
753 | struct domain_device *parent_dev = device->parent; | |
754 | struct asd_sas_port *sas_port = device->port; | |
755 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
735bcc77 | 756 | u64 sas_addr; |
182e7222 XC |
757 | |
758 | memset(itct, 0, sizeof(*itct)); | |
759 | ||
760 | /* qw0 */ | |
761 | qw0 = 0; | |
762 | switch (sas_dev->dev_type) { | |
763 | case SAS_END_DEVICE: | |
764 | case SAS_EDGE_EXPANDER_DEVICE: | |
765 | case SAS_FANOUT_EXPANDER_DEVICE: | |
766 | qw0 = HISI_SAS_DEV_TYPE_SSP << ITCT_HDR_DEV_TYPE_OFF; | |
767 | break; | |
768 | case SAS_SATA_DEV: | |
769 | case SAS_SATA_PENDING: | |
924a3541 | 770 | if (parent_dev && dev_is_expander(parent_dev->dev_type)) |
182e7222 XC |
771 | qw0 = HISI_SAS_DEV_TYPE_STP << ITCT_HDR_DEV_TYPE_OFF; |
772 | else | |
773 | qw0 = HISI_SAS_DEV_TYPE_SATA << ITCT_HDR_DEV_TYPE_OFF; | |
774 | break; | |
775 | default: | |
776 | dev_warn(dev, "setup itct: unsupported dev type (%d)\n", | |
777 | sas_dev->dev_type); | |
778 | } | |
779 | ||
780 | qw0 |= ((1 << ITCT_HDR_VALID_OFF) | | |
781 | (device->linkrate << ITCT_HDR_MCR_OFF) | | |
782 | (1 << ITCT_HDR_VLN_OFF) | | |
783 | (0xfa << ITCT_HDR_SMP_TIMEOUT_OFF) | | |
784 | (1 << ITCT_HDR_AWT_CONTINUE_OFF) | | |
785 | (port->id << ITCT_HDR_PORT_ID_OFF)); | |
786 | itct->qw0 = cpu_to_le64(qw0); | |
787 | ||
788 | /* qw1 */ | |
735bcc77 JG |
789 | memcpy(&sas_addr, device->sas_addr, SAS_ADDR_SIZE); |
790 | itct->sas_addr = cpu_to_le64(__swab64(sas_addr)); | |
182e7222 XC |
791 | |
792 | /* qw2 */ | |
793 | if (!dev_is_sata(device)) | |
794 | itct->qw2 = cpu_to_le64((5000ULL << ITCT_HDR_INLT_OFF) | | |
795 | (0x1ULL << ITCT_HDR_RTOLT_OFF)); | |
796 | } | |
797 | ||
6a79e8ce XC |
798 | static int clear_itct_v3_hw(struct hisi_hba *hisi_hba, |
799 | struct hisi_sas_device *sas_dev) | |
182e7222 | 800 | { |
13cd5ed6 | 801 | DECLARE_COMPLETION_ONSTACK(completion); |
182e7222 | 802 | u64 dev_id = sas_dev->device_id; |
182e7222 XC |
803 | struct hisi_sas_itct *itct = &hisi_hba->itct[dev_id]; |
804 | u32 reg_val = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
6a79e8ce | 805 | struct device *dev = hisi_hba->dev; |
182e7222 | 806 | |
13cd5ed6 XC |
807 | sas_dev->completion = &completion; |
808 | ||
182e7222 XC |
809 | /* clear the itct interrupt state */ |
810 | if (ENT_INT_SRC3_ITC_INT_MSK & reg_val) | |
811 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, | |
812 | ENT_INT_SRC3_ITC_INT_MSK); | |
813 | ||
4a8bec88 | 814 | /* clear the itct table */ |
13cd5ed6 | 815 | reg_val = ITCT_CLR_EN_MSK | (dev_id & ITCT_DEV_MSK); |
182e7222 XC |
816 | hisi_sas_write32(hisi_hba, ITCT_CLR, reg_val); |
817 | ||
6a79e8ce XC |
818 | if (!wait_for_completion_timeout(sas_dev->completion, |
819 | CLEAR_ITCT_TIMEOUT * HZ)) { | |
820 | dev_warn(dev, "failed to clear ITCT\n"); | |
821 | return -ETIMEDOUT; | |
822 | } | |
823 | ||
13cd5ed6 | 824 | memset(itct, 0, sizeof(struct hisi_sas_itct)); |
6a79e8ce | 825 | return 0; |
182e7222 XC |
826 | } |
827 | ||
d30ff263 XC |
828 | static void dereg_device_v3_hw(struct hisi_hba *hisi_hba, |
829 | struct domain_device *device) | |
830 | { | |
831 | struct hisi_sas_slot *slot, *slot2; | |
832 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
833 | u32 cfg_abt_set_query_iptt; | |
834 | ||
835 | cfg_abt_set_query_iptt = hisi_sas_read32(hisi_hba, | |
836 | CFG_ABT_SET_QUERY_IPTT); | |
837 | list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry) { | |
838 | cfg_abt_set_query_iptt &= ~CFG_SET_ABORTED_IPTT_MSK; | |
839 | cfg_abt_set_query_iptt |= (1 << CFG_SET_ABORTED_EN_OFF) | | |
840 | (slot->idx << CFG_SET_ABORTED_IPTT_OFF); | |
841 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
842 | cfg_abt_set_query_iptt); | |
843 | } | |
844 | cfg_abt_set_query_iptt &= ~(1 << CFG_SET_ABORTED_EN_OFF); | |
845 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_QUERY_IPTT, | |
846 | cfg_abt_set_query_iptt); | |
847 | hisi_sas_write32(hisi_hba, CFG_ABT_SET_IPTT_DONE, | |
848 | 1 << CFG_ABT_SET_IPTT_DONE_OFF); | |
849 | } | |
850 | ||
a25d0d3d XC |
851 | static int reset_hw_v3_hw(struct hisi_hba *hisi_hba) |
852 | { | |
853 | struct device *dev = hisi_hba->dev; | |
854 | int ret; | |
855 | u32 val; | |
856 | ||
857 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); | |
858 | ||
859 | /* Disable all of the PHYs */ | |
860 | hisi_sas_stop_phys(hisi_hba); | |
861 | udelay(50); | |
862 | ||
863 | /* Ensure axi bus idle */ | |
9b8addf3 JG |
864 | ret = hisi_sas_read32_poll_timeout(AXI_CFG, val, !val, |
865 | 20000, 1000000); | |
a25d0d3d XC |
866 | if (ret) { |
867 | dev_err(dev, "axi bus is not idle, ret = %d!\n", ret); | |
868 | return -EIO; | |
869 | } | |
870 | ||
871 | if (ACPI_HANDLE(dev)) { | |
872 | acpi_status s; | |
873 | ||
874 | s = acpi_evaluate_object(ACPI_HANDLE(dev), "_RST", NULL, NULL); | |
875 | if (ACPI_FAILURE(s)) { | |
876 | dev_err(dev, "Reset failed\n"); | |
877 | return -EIO; | |
878 | } | |
edafeef4 | 879 | } else { |
a25d0d3d | 880 | dev_err(dev, "no reset method!\n"); |
edafeef4 XC |
881 | return -EINVAL; |
882 | } | |
a25d0d3d XC |
883 | |
884 | return 0; | |
885 | } | |
886 | ||
c94d8ca2 XC |
887 | static int hw_init_v3_hw(struct hisi_hba *hisi_hba) |
888 | { | |
a25d0d3d | 889 | struct device *dev = hisi_hba->dev; |
3168d4f8 XT |
890 | union acpi_object *obj; |
891 | guid_t guid; | |
a25d0d3d XC |
892 | int rc; |
893 | ||
894 | rc = reset_hw_v3_hw(hisi_hba); | |
895 | if (rc) { | |
896 | dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc); | |
897 | return rc; | |
898 | } | |
899 | ||
900 | msleep(100); | |
c94d8ca2 XC |
901 | init_reg_v3_hw(hisi_hba); |
902 | ||
3168d4f8 XT |
903 | if (guid_parse("D5918B4B-37AE-4E10-A99F-E5E8A6EF4C1F", &guid)) { |
904 | dev_err(dev, "Parse GUID failed\n"); | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
908 | /* Switch over to MSI handling , from PCI AER default */ | |
909 | obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &guid, 0, | |
910 | DSM_FUNC_ERR_HANDLE_MSI, NULL); | |
911 | if (!obj) | |
912 | dev_warn(dev, "Switch over to MSI handling failed\n"); | |
913 | else | |
914 | ACPI_FREE(obj); | |
915 | ||
c94d8ca2 XC |
916 | return 0; |
917 | } | |
918 | ||
3975f605 XC |
919 | static void enable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
920 | { | |
921 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
922 | ||
923 | cfg |= PHY_CFG_ENA_MSK; | |
25908cac | 924 | cfg &= ~PHY_CFG_PHY_RST_MSK; |
3975f605 XC |
925 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); |
926 | } | |
927 | ||
402cd9f0 XC |
928 | static void disable_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
929 | { | |
930 | u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG); | |
e4c19deb LJ |
931 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); |
932 | static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | | |
933 | BIT(CHL_INT2_RX_CODE_ERR_OFF) | | |
934 | BIT(CHL_INT2_RX_INVLD_DW_OFF); | |
25908cac | 935 | u32 state; |
402cd9f0 | 936 | |
e4c19deb LJ |
937 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, msk | irq_msk); |
938 | ||
402cd9f0 XC |
939 | cfg &= ~PHY_CFG_ENA_MSK; |
940 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
25908cac XT |
941 | |
942 | mdelay(50); | |
943 | ||
944 | state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
945 | if (state & BIT(phy_no)) { | |
946 | cfg |= PHY_CFG_PHY_RST_MSK; | |
947 | hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg); | |
948 | } | |
e4c19deb LJ |
949 | |
950 | udelay(1); | |
951 | ||
952 | hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); | |
953 | hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); | |
954 | hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); | |
955 | ||
956 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, msk); | |
957 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2_MSK, irq_msk); | |
402cd9f0 XC |
958 | } |
959 | ||
3975f605 XC |
960 | static void start_phy_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
961 | { | |
962 | config_id_frame_v3_hw(hisi_hba, phy_no); | |
963 | config_phy_opt_mode_v3_hw(hisi_hba, phy_no); | |
964 | enable_phy_v3_hw(hisi_hba, phy_no); | |
965 | } | |
966 | ||
402cd9f0 XC |
967 | static void phy_hard_reset_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
968 | { | |
969 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
970 | u32 txid_auto; | |
971 | ||
c63b88cc | 972 | hisi_sas_phy_enable(hisi_hba, phy_no, 0); |
402cd9f0 XC |
973 | if (phy->identify.device_type == SAS_END_DEVICE) { |
974 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
975 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
976 | txid_auto | TX_HARDRST_MSK); | |
977 | } | |
978 | msleep(100); | |
c63b88cc | 979 | hisi_sas_phy_enable(hisi_hba, phy_no, 1); |
402cd9f0 XC |
980 | } |
981 | ||
edafeef4 | 982 | static enum sas_linkrate phy_get_max_linkrate_v3_hw(void) |
402cd9f0 XC |
983 | { |
984 | return SAS_LINK_RATE_12_0_GBPS; | |
985 | } | |
986 | ||
3975f605 XC |
987 | static void phys_init_v3_hw(struct hisi_hba *hisi_hba) |
988 | { | |
a25d0d3d XC |
989 | int i; |
990 | ||
991 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
992 | struct hisi_sas_phy *phy = &hisi_hba->phy[i]; | |
993 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
994 | ||
995 | if (!sas_phy->phy->enabled) | |
996 | continue; | |
997 | ||
c63b88cc | 998 | hisi_sas_phy_enable(hisi_hba, i, 1); |
a25d0d3d | 999 | } |
3975f605 XC |
1000 | } |
1001 | ||
569eddcf | 1002 | static void sl_notify_ssp_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
3975f605 XC |
1003 | { |
1004 | u32 sl_control; | |
1005 | ||
1006 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
1007 | sl_control |= SL_CONTROL_NOTIFY_EN_MSK; | |
1008 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
1009 | msleep(1); | |
1010 | sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
1011 | sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK; | |
1012 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control); | |
1013 | } | |
1014 | ||
f771d3b0 XC |
1015 | static int get_wideport_bitmap_v3_hw(struct hisi_hba *hisi_hba, int port_id) |
1016 | { | |
1017 | int i, bitmap = 0; | |
1018 | u32 phy_port_num_ma = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
0e3231fc | 1019 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); |
f771d3b0 XC |
1020 | |
1021 | for (i = 0; i < hisi_hba->n_phy; i++) | |
0e3231fc XT |
1022 | if (phy_state & BIT(i)) |
1023 | if (((phy_port_num_ma >> (i * 4)) & 0xf) == port_id) | |
1024 | bitmap |= BIT(i); | |
f771d3b0 XC |
1025 | |
1026 | return bitmap; | |
1027 | } | |
1028 | ||
a2204723 XC |
1029 | static void start_delivery_v3_hw(struct hisi_sas_dq *dq) |
1030 | { | |
1031 | struct hisi_hba *hisi_hba = dq->hisi_hba; | |
1c09b663 | 1032 | struct hisi_sas_slot *s, *s1, *s2 = NULL; |
fa222db0 | 1033 | int dlvry_queue = dq->id; |
1c09b663 | 1034 | int wp; |
fa222db0 | 1035 | |
fa222db0 XC |
1036 | list_for_each_entry_safe(s, s1, &dq->list, delivery) { |
1037 | if (!s->ready) | |
1038 | break; | |
1c09b663 | 1039 | s2 = s; |
fa222db0 XC |
1040 | list_del(&s->delivery); |
1041 | } | |
1042 | ||
1c09b663 | 1043 | if (!s2) |
fa222db0 | 1044 | return; |
a2204723 | 1045 | |
1c09b663 XT |
1046 | /* |
1047 | * Ensure that memories for slots built on other CPUs is observed. | |
1048 | */ | |
1049 | smp_rmb(); | |
1050 | wp = (s2->dlvry_queue_slot + 1) % HISI_SAS_QUEUE_SLOTS; | |
1051 | ||
fa222db0 | 1052 | hisi_sas_write32(hisi_hba, DLVRY_Q_0_WR_PTR + (dlvry_queue * 0x14), wp); |
a2204723 XC |
1053 | } |
1054 | ||
a2b3820b | 1055 | static void prep_prd_sge_v3_hw(struct hisi_hba *hisi_hba, |
a2204723 XC |
1056 | struct hisi_sas_slot *slot, |
1057 | struct hisi_sas_cmd_hdr *hdr, | |
1058 | struct scatterlist *scatter, | |
1059 | int n_elem) | |
1060 | { | |
f557e32c | 1061 | struct hisi_sas_sge_page *sge_page = hisi_sas_sge_addr_mem(slot); |
a2204723 XC |
1062 | struct scatterlist *sg; |
1063 | int i; | |
1064 | ||
a2204723 | 1065 | for_each_sg(scatter, sg, n_elem, i) { |
f557e32c | 1066 | struct hisi_sas_sge *entry = &sge_page->sge[i]; |
a2204723 XC |
1067 | |
1068 | entry->addr = cpu_to_le64(sg_dma_address(sg)); | |
1069 | entry->page_ctrl_0 = entry->page_ctrl_1 = 0; | |
1070 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); | |
1071 | entry->data_off = 0; | |
1072 | } | |
1073 | ||
f557e32c XT |
1074 | hdr->prd_table_addr = cpu_to_le64(hisi_sas_sge_addr_dma(slot)); |
1075 | ||
b3cce125 XC |
1076 | hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DATA_SGL_LEN_OFF); |
1077 | } | |
1078 | ||
1079 | static void prep_prd_sge_dif_v3_hw(struct hisi_hba *hisi_hba, | |
1080 | struct hisi_sas_slot *slot, | |
1081 | struct hisi_sas_cmd_hdr *hdr, | |
1082 | struct scatterlist *scatter, | |
1083 | int n_elem) | |
1084 | { | |
1085 | struct hisi_sas_sge_dif_page *sge_dif_page; | |
1086 | struct scatterlist *sg; | |
1087 | int i; | |
1088 | ||
1089 | sge_dif_page = hisi_sas_sge_dif_addr_mem(slot); | |
1090 | ||
1091 | for_each_sg(scatter, sg, n_elem, i) { | |
1092 | struct hisi_sas_sge *entry = &sge_dif_page->sge[i]; | |
1093 | ||
1094 | entry->addr = cpu_to_le64(sg_dma_address(sg)); | |
1095 | entry->page_ctrl_0 = 0; | |
1096 | entry->page_ctrl_1 = 0; | |
1097 | entry->data_len = cpu_to_le32(sg_dma_len(sg)); | |
1098 | entry->data_off = 0; | |
1099 | } | |
1100 | ||
1101 | hdr->dif_prd_table_addr = | |
1102 | cpu_to_le64(hisi_sas_sge_dif_addr_dma(slot)); | |
1103 | ||
1104 | hdr->sg_len |= cpu_to_le32(n_elem << CMD_HDR_DIF_SGL_LEN_OFF); | |
a2204723 XC |
1105 | } |
1106 | ||
d6a9000b XC |
1107 | static u32 get_prot_chk_msk_v3_hw(struct scsi_cmnd *scsi_cmnd) |
1108 | { | |
1109 | unsigned char prot_flags = scsi_cmnd->prot_flags; | |
1110 | ||
b3cce125 XC |
1111 | if (prot_flags & SCSI_PROT_REF_CHECK) |
1112 | return T10_CHK_APP_TAG_MSK; | |
1113 | return T10_CHK_REF_TAG_MSK | T10_CHK_APP_TAG_MSK; | |
d6a9000b XC |
1114 | } |
1115 | ||
1116 | static void fill_prot_v3_hw(struct scsi_cmnd *scsi_cmnd, | |
1117 | struct hisi_sas_protect_iu_v3_hw *prot) | |
1118 | { | |
1119 | unsigned char prot_op = scsi_get_prot_op(scsi_cmnd); | |
1120 | unsigned int interval = scsi_prot_interval(scsi_cmnd); | |
1121 | u32 lbrt_chk_val = t10_pi_ref_tag(scsi_cmnd->request); | |
1122 | ||
1123 | switch (prot_op) { | |
b3cce125 XC |
1124 | case SCSI_PROT_READ_INSERT: |
1125 | prot->dw0 |= T10_INSRT_EN_MSK; | |
1126 | prot->lbrtgv = lbrt_chk_val; | |
1127 | break; | |
d6a9000b XC |
1128 | case SCSI_PROT_READ_STRIP: |
1129 | prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); | |
1130 | prot->lbrtcv = lbrt_chk_val; | |
1131 | prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); | |
1132 | break; | |
b3cce125 XC |
1133 | case SCSI_PROT_READ_PASS: |
1134 | prot->dw0 |= T10_CHK_EN_MSK; | |
1135 | prot->lbrtcv = lbrt_chk_val; | |
1136 | prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); | |
1137 | break; | |
d6a9000b XC |
1138 | case SCSI_PROT_WRITE_INSERT: |
1139 | prot->dw0 |= T10_INSRT_EN_MSK; | |
1140 | prot->lbrtgv = lbrt_chk_val; | |
1141 | break; | |
b3cce125 XC |
1142 | case SCSI_PROT_WRITE_STRIP: |
1143 | prot->dw0 |= (T10_RMV_EN_MSK | T10_CHK_EN_MSK); | |
1144 | prot->lbrtcv = lbrt_chk_val; | |
1145 | break; | |
1146 | case SCSI_PROT_WRITE_PASS: | |
1147 | prot->dw0 |= T10_CHK_EN_MSK; | |
1148 | prot->lbrtcv = lbrt_chk_val; | |
1149 | prot->dw4 |= get_prot_chk_msk_v3_hw(scsi_cmnd); | |
1150 | break; | |
d6a9000b XC |
1151 | default: |
1152 | WARN(1, "prot_op(0x%x) is not valid\n", prot_op); | |
1153 | break; | |
1154 | } | |
1155 | ||
1156 | switch (interval) { | |
1157 | case 512: | |
1158 | break; | |
1159 | case 4096: | |
1160 | prot->dw0 |= (0x1 << USR_DATA_BLOCK_SZ_OFF); | |
1161 | break; | |
1162 | case 520: | |
1163 | prot->dw0 |= (0x2 << USR_DATA_BLOCK_SZ_OFF); | |
1164 | break; | |
1165 | default: | |
1166 | WARN(1, "protection interval (0x%x) invalid\n", | |
1167 | interval); | |
1168 | break; | |
1169 | } | |
1170 | ||
1171 | prot->dw0 |= INCR_LBRT_MSK; | |
1172 | } | |
1173 | ||
a2b3820b | 1174 | static void prep_ssp_v3_hw(struct hisi_hba *hisi_hba, |
78bd2b4f | 1175 | struct hisi_sas_slot *slot) |
a2204723 XC |
1176 | { |
1177 | struct sas_task *task = slot->task; | |
1178 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1179 | struct domain_device *device = task->dev; | |
1180 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1181 | struct hisi_sas_port *port = slot->port; | |
1182 | struct sas_ssp_task *ssp_task = &task->ssp_task; | |
1183 | struct scsi_cmnd *scsi_cmnd = ssp_task->cmd; | |
78bd2b4f XT |
1184 | struct hisi_sas_tmf_task *tmf = slot->tmf; |
1185 | int has_data = 0, priority = !!tmf; | |
e1ba0b0b | 1186 | unsigned char prot_op; |
a2204723 | 1187 | u8 *buf_cmd; |
d6a9000b | 1188 | u32 dw1 = 0, dw2 = 0, len = 0; |
a2204723 XC |
1189 | |
1190 | hdr->dw0 = cpu_to_le32((1 << CMD_HDR_RESP_REPORT_OFF) | | |
1191 | (2 << CMD_HDR_TLR_CTRL_OFF) | | |
1192 | (port->id << CMD_HDR_PORT_OFF) | | |
1193 | (priority << CMD_HDR_PRIORITY_OFF) | | |
1194 | (1 << CMD_HDR_CMD_OFF)); /* ssp */ | |
1195 | ||
1196 | dw1 = 1 << CMD_HDR_VDTL_OFF; | |
78bd2b4f | 1197 | if (tmf) { |
a2204723 XC |
1198 | dw1 |= 2 << CMD_HDR_FRAME_TYPE_OFF; |
1199 | dw1 |= DIR_NO_DATA << CMD_HDR_DIR_OFF; | |
1200 | } else { | |
e1ba0b0b | 1201 | prot_op = scsi_get_prot_op(scsi_cmnd); |
a2204723 XC |
1202 | dw1 |= 1 << CMD_HDR_FRAME_TYPE_OFF; |
1203 | switch (scsi_cmnd->sc_data_direction) { | |
1204 | case DMA_TO_DEVICE: | |
1205 | has_data = 1; | |
1206 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1207 | break; | |
1208 | case DMA_FROM_DEVICE: | |
1209 | has_data = 1; | |
1210 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1211 | break; | |
1212 | default: | |
1213 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1214 | } | |
1215 | } | |
1216 | ||
1217 | /* map itct entry */ | |
1218 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
a2204723 XC |
1219 | |
1220 | dw2 = (((sizeof(struct ssp_command_iu) + sizeof(struct ssp_frame_hdr) | |
1221 | + 3) / 4) << CMD_HDR_CFL_OFF) | | |
1222 | ((HISI_SAS_MAX_SSP_RESP_SZ / 4) << CMD_HDR_MRFL_OFF) | | |
1223 | (2 << CMD_HDR_SG_MOD_OFF); | |
1224 | hdr->dw2 = cpu_to_le32(dw2); | |
1225 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1226 | ||
b3cce125 | 1227 | if (has_data) { |
a2b3820b | 1228 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, |
b3cce125 XC |
1229 | slot->n_elem); |
1230 | ||
1231 | if (scsi_prot_sg_count(scsi_cmnd)) | |
1232 | prep_prd_sge_dif_v3_hw(hisi_hba, slot, hdr, | |
1233 | scsi_prot_sglist(scsi_cmnd), | |
1234 | slot->n_elem_dif); | |
1235 | } | |
a2204723 | 1236 | |
f557e32c XT |
1237 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1238 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
a2204723 | 1239 | |
f557e32c XT |
1240 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot) + |
1241 | sizeof(struct ssp_frame_hdr); | |
a2204723 | 1242 | |
f557e32c | 1243 | memcpy(buf_cmd, &task->ssp_task.LUN, 8); |
78bd2b4f | 1244 | if (!tmf) { |
a2204723 XC |
1245 | buf_cmd[9] = ssp_task->task_attr | (ssp_task->task_prio << 3); |
1246 | memcpy(buf_cmd + 12, scsi_cmnd->cmnd, scsi_cmnd->cmd_len); | |
1247 | } else { | |
1248 | buf_cmd[10] = tmf->tmf; | |
1249 | switch (tmf->tmf) { | |
1250 | case TMF_ABORT_TASK: | |
1251 | case TMF_QUERY_TASK: | |
1252 | buf_cmd[12] = | |
1253 | (tmf->tag_of_task_to_be_managed >> 8) & 0xff; | |
1254 | buf_cmd[13] = | |
1255 | tmf->tag_of_task_to_be_managed & 0xff; | |
1256 | break; | |
1257 | default: | |
1258 | break; | |
1259 | } | |
1260 | } | |
d6a9000b XC |
1261 | |
1262 | if (has_data && (prot_op != SCSI_PROT_NORMAL)) { | |
1263 | struct hisi_sas_protect_iu_v3_hw prot; | |
1264 | u8 *buf_cmd_prot; | |
1265 | ||
1266 | hdr->dw7 |= cpu_to_le32(1 << CMD_HDR_ADDR_MODE_SEL_OFF); | |
1267 | dw1 |= CMD_HDR_PIR_MSK; | |
1268 | buf_cmd_prot = hisi_sas_cmd_hdr_addr_mem(slot) + | |
1269 | sizeof(struct ssp_frame_hdr) + | |
1270 | sizeof(struct ssp_command_iu); | |
1271 | ||
1272 | memset(&prot, 0, sizeof(struct hisi_sas_protect_iu_v3_hw)); | |
1273 | fill_prot_v3_hw(scsi_cmnd, &prot); | |
1274 | memcpy(buf_cmd_prot, &prot, | |
1275 | sizeof(struct hisi_sas_protect_iu_v3_hw)); | |
d6a9000b XC |
1276 | /* |
1277 | * For READ, we need length of info read to memory, while for | |
1278 | * WRITE we need length of data written to the disk. | |
1279 | */ | |
b3cce125 XC |
1280 | if (prot_op == SCSI_PROT_WRITE_INSERT || |
1281 | prot_op == SCSI_PROT_READ_INSERT || | |
1282 | prot_op == SCSI_PROT_WRITE_PASS || | |
1283 | prot_op == SCSI_PROT_READ_PASS) { | |
d6a9000b XC |
1284 | unsigned int interval = scsi_prot_interval(scsi_cmnd); |
1285 | unsigned int ilog2_interval = ilog2(interval); | |
1286 | ||
1287 | len = (task->total_xfer_len >> ilog2_interval) * 8; | |
1288 | } | |
d6a9000b XC |
1289 | } |
1290 | ||
1291 | hdr->dw1 = cpu_to_le32(dw1); | |
1292 | ||
1293 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len + len); | |
a2204723 XC |
1294 | } |
1295 | ||
a2b3820b | 1296 | static void prep_smp_v3_hw(struct hisi_hba *hisi_hba, |
fa913de2 XC |
1297 | struct hisi_sas_slot *slot) |
1298 | { | |
1299 | struct sas_task *task = slot->task; | |
1300 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1301 | struct domain_device *device = task->dev; | |
fa913de2 | 1302 | struct hisi_sas_port *port = slot->port; |
7eee4b92 | 1303 | struct scatterlist *sg_req; |
fa913de2 XC |
1304 | struct hisi_sas_device *sas_dev = device->lldd_dev; |
1305 | dma_addr_t req_dma_addr; | |
7eee4b92 | 1306 | unsigned int req_len; |
fa913de2 | 1307 | |
fa913de2 XC |
1308 | /* req */ |
1309 | sg_req = &task->smp_task.smp_req; | |
fa913de2 XC |
1310 | req_len = sg_dma_len(sg_req); |
1311 | req_dma_addr = sg_dma_address(sg_req); | |
1312 | ||
fa913de2 XC |
1313 | /* create header */ |
1314 | /* dw0 */ | |
1315 | hdr->dw0 = cpu_to_le32((port->id << CMD_HDR_PORT_OFF) | | |
1316 | (1 << CMD_HDR_PRIORITY_OFF) | /* high pri */ | |
1317 | (2 << CMD_HDR_CMD_OFF)); /* smp */ | |
1318 | ||
1319 | /* map itct entry */ | |
1320 | hdr->dw1 = cpu_to_le32((sas_dev->device_id << CMD_HDR_DEV_ID_OFF) | | |
1321 | (1 << CMD_HDR_FRAME_TYPE_OFF) | | |
1322 | (DIR_NO_DATA << CMD_HDR_DIR_OFF)); | |
1323 | ||
1324 | /* dw2 */ | |
1325 | hdr->dw2 = cpu_to_le32((((req_len - 4) / 4) << CMD_HDR_CFL_OFF) | | |
1326 | (HISI_SAS_MAX_SMP_RESP_SZ / 4 << | |
1327 | CMD_HDR_MRFL_OFF)); | |
1328 | ||
1329 | hdr->transfer_tags = cpu_to_le32(slot->idx << CMD_HDR_IPTT_OFF); | |
1330 | ||
1331 | hdr->cmd_table_addr = cpu_to_le64(req_dma_addr); | |
f557e32c | 1332 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); |
fa913de2 | 1333 | |
fa913de2 XC |
1334 | } |
1335 | ||
a2b3820b | 1336 | static void prep_ata_v3_hw(struct hisi_hba *hisi_hba, |
ce60689e XC |
1337 | struct hisi_sas_slot *slot) |
1338 | { | |
1339 | struct sas_task *task = slot->task; | |
1340 | struct domain_device *device = task->dev; | |
1341 | struct domain_device *parent_dev = device->parent; | |
1342 | struct hisi_sas_device *sas_dev = device->lldd_dev; | |
1343 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1344 | struct asd_sas_port *sas_port = device->port; | |
1345 | struct hisi_sas_port *port = to_hisi_sas_port(sas_port); | |
1346 | u8 *buf_cmd; | |
a2b3820b | 1347 | int has_data = 0, hdr_tag = 0; |
ce60689e XC |
1348 | u32 dw1 = 0, dw2 = 0; |
1349 | ||
1350 | hdr->dw0 = cpu_to_le32(port->id << CMD_HDR_PORT_OFF); | |
924a3541 | 1351 | if (parent_dev && dev_is_expander(parent_dev->dev_type)) |
ce60689e XC |
1352 | hdr->dw0 |= cpu_to_le32(3 << CMD_HDR_CMD_OFF); |
1353 | else | |
0ab7bc82 | 1354 | hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF); |
ce60689e XC |
1355 | |
1356 | switch (task->data_dir) { | |
1357 | case DMA_TO_DEVICE: | |
1358 | has_data = 1; | |
1359 | dw1 |= DIR_TO_DEVICE << CMD_HDR_DIR_OFF; | |
1360 | break; | |
1361 | case DMA_FROM_DEVICE: | |
1362 | has_data = 1; | |
1363 | dw1 |= DIR_TO_INI << CMD_HDR_DIR_OFF; | |
1364 | break; | |
1365 | default: | |
1366 | dw1 &= ~CMD_HDR_DIR_MSK; | |
1367 | } | |
1368 | ||
1369 | if ((task->ata_task.fis.command == ATA_CMD_DEV_RESET) && | |
1370 | (task->ata_task.fis.control & ATA_SRST)) | |
1371 | dw1 |= 1 << CMD_HDR_RESET_OFF; | |
1372 | ||
1373 | dw1 |= (hisi_sas_get_ata_protocol( | |
468f4b8d | 1374 | &task->ata_task.fis, task->data_dir)) |
ce60689e XC |
1375 | << CMD_HDR_FRAME_TYPE_OFF; |
1376 | dw1 |= sas_dev->device_id << CMD_HDR_DEV_ID_OFF; | |
1377 | ||
94135327 | 1378 | if (FIS_CMD_IS_UNCONSTRAINED(task->ata_task.fis)) |
ce60689e XC |
1379 | dw1 |= 1 << CMD_HDR_UNCON_CMD_OFF; |
1380 | ||
1381 | hdr->dw1 = cpu_to_le32(dw1); | |
1382 | ||
1383 | /* dw2 */ | |
435a05cf XC |
1384 | if (task->ata_task.use_ncq) { |
1385 | struct ata_queued_cmd *qc = task->uldd_task; | |
1386 | ||
1387 | hdr_tag = qc->tag; | |
ce60689e XC |
1388 | task->ata_task.fis.sector_count |= (u8) (hdr_tag << 3); |
1389 | dw2 |= hdr_tag << CMD_HDR_NCQ_TAG_OFF; | |
1390 | } | |
1391 | ||
1392 | dw2 |= (HISI_SAS_MAX_STP_RESP_SZ / 4) << CMD_HDR_CFL_OFF | | |
1393 | 2 << CMD_HDR_SG_MOD_OFF; | |
1394 | hdr->dw2 = cpu_to_le32(dw2); | |
1395 | ||
1396 | /* dw3 */ | |
1397 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1398 | ||
a2b3820b XC |
1399 | if (has_data) |
1400 | prep_prd_sge_v3_hw(hisi_hba, slot, hdr, task->scatter, | |
ce60689e | 1401 | slot->n_elem); |
ce60689e XC |
1402 | |
1403 | hdr->data_transfer_len = cpu_to_le32(task->total_xfer_len); | |
f557e32c XT |
1404 | hdr->cmd_table_addr = cpu_to_le64(hisi_sas_cmd_hdr_addr_dma(slot)); |
1405 | hdr->sts_buffer_addr = cpu_to_le64(hisi_sas_status_buf_addr_dma(slot)); | |
ce60689e | 1406 | |
f557e32c | 1407 | buf_cmd = hisi_sas_cmd_hdr_addr_mem(slot); |
ce60689e XC |
1408 | |
1409 | if (likely(!task->ata_task.device_control_reg_update)) | |
1410 | task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */ | |
1411 | /* fill in command FIS */ | |
1412 | memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis)); | |
ce60689e XC |
1413 | } |
1414 | ||
a2b3820b | 1415 | static void prep_abort_v3_hw(struct hisi_hba *hisi_hba, |
4de0ca69 XC |
1416 | struct hisi_sas_slot *slot, |
1417 | int device_id, int abort_flag, int tag_to_abort) | |
1418 | { | |
1419 | struct sas_task *task = slot->task; | |
1420 | struct domain_device *dev = task->dev; | |
1421 | struct hisi_sas_cmd_hdr *hdr = slot->cmd_hdr; | |
1422 | struct hisi_sas_port *port = slot->port; | |
1423 | ||
1424 | /* dw0 */ | |
0ab7bc82 | 1425 | hdr->dw0 = cpu_to_le32((5U << CMD_HDR_CMD_OFF) | /*abort*/ |
4de0ca69 | 1426 | (port->id << CMD_HDR_PORT_OFF) | |
edafeef4 | 1427 | (dev_is_sata(dev) |
4de0ca69 XC |
1428 | << CMD_HDR_ABORT_DEVICE_TYPE_OFF) | |
1429 | (abort_flag | |
1430 | << CMD_HDR_ABORT_FLAG_OFF)); | |
1431 | ||
1432 | /* dw1 */ | |
1433 | hdr->dw1 = cpu_to_le32(device_id | |
1434 | << CMD_HDR_DEV_ID_OFF); | |
1435 | ||
1436 | /* dw7 */ | |
1437 | hdr->dw7 = cpu_to_le32(tag_to_abort << CMD_HDR_ABORT_IPTT_OFF); | |
1438 | hdr->transfer_tags = cpu_to_le32(slot->idx); | |
1439 | ||
4de0ca69 XC |
1440 | } |
1441 | ||
edafeef4 | 1442 | static irqreturn_t phy_up_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1443 | { |
fba770c6 XC |
1444 | int i; |
1445 | irqreturn_t res; | |
eba8c20c | 1446 | u32 context, port_id, link_rate; |
54edeee1 XC |
1447 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; |
1448 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1449 | struct device *dev = hisi_hba->dev; | |
3e1fb1b8 | 1450 | unsigned long flags; |
54edeee1 | 1451 | |
b6c9b15e | 1452 | del_timer(&phy->timer); |
54edeee1 XC |
1453 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1); |
1454 | ||
1455 | port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA); | |
1456 | port_id = (port_id >> (4 * phy_no)) & 0xf; | |
1457 | link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE); | |
1458 | link_rate = (link_rate >> (phy_no * 4)) & 0xf; | |
1459 | ||
1460 | if (port_id == 0xf) { | |
1461 | dev_err(dev, "phyup: phy%d invalid portid\n", phy_no); | |
1462 | res = IRQ_NONE; | |
1463 | goto end; | |
1464 | } | |
1465 | sas_phy->linkrate = link_rate; | |
54edeee1 XC |
1466 | phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA); |
1467 | ||
1468 | /* Check for SATA dev */ | |
1469 | context = hisi_sas_read32(hisi_hba, PHY_CONTEXT); | |
1470 | if (context & (1 << phy_no)) { | |
1471 | struct hisi_sas_initial_fis *initial_fis; | |
1472 | struct dev_to_host_fis *fis; | |
1473 | u8 attached_sas_addr[SAS_ADDR_SIZE] = {0}; | |
adb5b38c | 1474 | struct Scsi_Host *shost = hisi_hba->shost; |
54edeee1 | 1475 | |
f1c88211 | 1476 | dev_info(dev, "phyup: phy%d link_rate=%d(sata)\n", phy_no, link_rate); |
54edeee1 XC |
1477 | initial_fis = &hisi_hba->initial_fis[phy_no]; |
1478 | fis = &initial_fis->fis; | |
f4e34f2a XC |
1479 | |
1480 | /* check ERR bit of Status Register */ | |
1481 | if (fis->status & ATA_ERR) { | |
1482 | dev_warn(dev, "sata int: phy%d FIS status: 0x%x\n", | |
1483 | phy_no, fis->status); | |
1484 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1485 | res = IRQ_NONE; | |
1486 | goto end; | |
1487 | } | |
1488 | ||
54edeee1 XC |
1489 | sas_phy->oob_mode = SATA_OOB_MODE; |
1490 | attached_sas_addr[0] = 0x50; | |
adb5b38c | 1491 | attached_sas_addr[6] = shost->host_no; |
54edeee1 XC |
1492 | attached_sas_addr[7] = phy_no; |
1493 | memcpy(sas_phy->attached_sas_addr, | |
1494 | attached_sas_addr, | |
1495 | SAS_ADDR_SIZE); | |
1496 | memcpy(sas_phy->frame_rcvd, fis, | |
1497 | sizeof(struct dev_to_host_fis)); | |
1498 | phy->phy_type |= PORT_TYPE_SATA; | |
1499 | phy->identify.device_type = SAS_SATA_DEV; | |
1500 | phy->frame_rcvd_size = sizeof(struct dev_to_host_fis); | |
1501 | phy->identify.target_port_protocols = SAS_PROTOCOL_SATA; | |
1502 | } else { | |
1503 | u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd; | |
1504 | struct sas_identify_frame *id = | |
1505 | (struct sas_identify_frame *)frame_rcvd; | |
1506 | ||
1507 | dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate); | |
1508 | for (i = 0; i < 6; i++) { | |
1509 | u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1510 | RX_IDAF_DWORD0 + (i * 4)); | |
1511 | frame_rcvd[i] = __swab32(idaf); | |
1512 | } | |
1513 | sas_phy->oob_mode = SAS_OOB_MODE; | |
1514 | memcpy(sas_phy->attached_sas_addr, | |
1515 | &id->sas_addr, | |
1516 | SAS_ADDR_SIZE); | |
1517 | phy->phy_type |= PORT_TYPE_SAS; | |
1518 | phy->identify.device_type = id->dev_type; | |
1519 | phy->frame_rcvd_size = sizeof(struct sas_identify_frame); | |
1520 | if (phy->identify.device_type == SAS_END_DEVICE) | |
1521 | phy->identify.target_port_protocols = | |
1522 | SAS_PROTOCOL_SSP; | |
1523 | else if (phy->identify.device_type != SAS_PHY_UNUSED) | |
1524 | phy->identify.target_port_protocols = | |
1525 | SAS_PROTOCOL_SMP; | |
1526 | } | |
1527 | ||
1528 | phy->port_id = port_id; | |
1529 | phy->phy_attached = 1; | |
e537b62b | 1530 | hisi_sas_notify_phy_event(phy, HISI_PHYE_PHY_UP); |
edafeef4 | 1531 | res = IRQ_HANDLED; |
3e1fb1b8 XC |
1532 | spin_lock_irqsave(&phy->lock, flags); |
1533 | if (phy->reset_completion) { | |
1534 | phy->in_reset = 0; | |
1535 | complete(phy->reset_completion); | |
1536 | } | |
1537 | spin_unlock_irqrestore(&phy->lock, flags); | |
54edeee1 XC |
1538 | end: |
1539 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, | |
1540 | CHL_INT0_SL_PHY_ENABLE_MSK); | |
1541 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0); | |
1542 | ||
1543 | return res; | |
1544 | } | |
1545 | ||
edafeef4 | 1546 | static irqreturn_t phy_down_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 | 1547 | { |
b6c9b15e | 1548 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; |
54edeee1 XC |
1549 | u32 phy_state, sl_ctrl, txid_auto; |
1550 | struct device *dev = hisi_hba->dev; | |
1551 | ||
b6c9b15e | 1552 | del_timer(&phy->timer); |
54edeee1 XC |
1553 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 1); |
1554 | ||
1555 | phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1556 | dev_info(dev, "phydown: phy%d phy_state=0x%x\n", phy_no, phy_state); | |
1557 | hisi_sas_phy_down(hisi_hba, phy_no, (phy_state & 1 << phy_no) ? 1 : 0); | |
1558 | ||
1559 | sl_ctrl = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL); | |
1560 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, | |
1561 | sl_ctrl&(~SL_CTA_MSK)); | |
1562 | ||
1563 | txid_auto = hisi_sas_phy_read32(hisi_hba, phy_no, TXID_AUTO); | |
1564 | hisi_sas_phy_write32(hisi_hba, phy_no, TXID_AUTO, | |
1565 | txid_auto | CT3_MSK); | |
1566 | ||
1567 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, CHL_INT0_NOT_RDY_MSK); | |
1568 | hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_NOT_RDY_MSK, 0); | |
1569 | ||
edafeef4 | 1570 | return IRQ_HANDLED; |
54edeee1 XC |
1571 | } |
1572 | ||
edafeef4 | 1573 | static irqreturn_t phy_bcast_v3_hw(int phy_no, struct hisi_hba *hisi_hba) |
54edeee1 XC |
1574 | { |
1575 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1576 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1577 | struct sas_ha_struct *sas_ha = &hisi_hba->sha; | |
1324ae1c | 1578 | u32 bcast_status; |
54edeee1 XC |
1579 | |
1580 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 1); | |
1324ae1c | 1581 | bcast_status = hisi_sas_phy_read32(hisi_hba, phy_no, RX_PRIMS_STATUS); |
ed99e1d9 XT |
1582 | if ((bcast_status & RX_BCAST_CHG_MSK) && |
1583 | !test_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) | |
1324ae1c | 1584 | sas_ha->notify_port_event(sas_phy, PORTE_BROADCAST_RCVD); |
54edeee1 XC |
1585 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, |
1586 | CHL_INT0_SL_RX_BCST_ACK_MSK); | |
1587 | hisi_sas_phy_write32(hisi_hba, phy_no, SL_RX_BCAST_CHK_MSK, 0); | |
edafeef4 XC |
1588 | |
1589 | return IRQ_HANDLED; | |
54edeee1 XC |
1590 | } |
1591 | ||
1592 | static irqreturn_t int_phy_up_down_bcast_v3_hw(int irq_no, void *p) | |
1593 | { | |
1594 | struct hisi_hba *hisi_hba = p; | |
1595 | u32 irq_msk; | |
1596 | int phy_no = 0; | |
1597 | irqreturn_t res = IRQ_NONE; | |
1598 | ||
1599 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) | |
1600 | & 0x11111111; | |
1601 | while (irq_msk) { | |
1602 | if (irq_msk & 1) { | |
1603 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1604 | CHL_INT0); | |
1605 | u32 phy_state = hisi_sas_read32(hisi_hba, PHY_STATE); | |
1606 | int rdy = phy_state & (1 << phy_no); | |
1607 | ||
1608 | if (rdy) { | |
1609 | if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK) | |
1610 | /* phy up */ | |
1611 | if (phy_up_v3_hw(phy_no, hisi_hba) | |
1612 | == IRQ_HANDLED) | |
1613 | res = IRQ_HANDLED; | |
1614 | if (irq_value & CHL_INT0_SL_RX_BCST_ACK_MSK) | |
1615 | /* phy bcast */ | |
edafeef4 XC |
1616 | if (phy_bcast_v3_hw(phy_no, hisi_hba) |
1617 | == IRQ_HANDLED) | |
1618 | res = IRQ_HANDLED; | |
54edeee1 XC |
1619 | } else { |
1620 | if (irq_value & CHL_INT0_NOT_RDY_MSK) | |
1621 | /* phy down */ | |
1622 | if (phy_down_v3_hw(phy_no, hisi_hba) | |
1623 | == IRQ_HANDLED) | |
1624 | res = IRQ_HANDLED; | |
1625 | } | |
1626 | } | |
1627 | irq_msk >>= 4; | |
1628 | phy_no++; | |
1629 | } | |
1630 | ||
1631 | return res; | |
1632 | } | |
1633 | ||
4a6125c5 | 1634 | static const struct hisi_sas_hw_error port_axi_error[] = { |
3168d4f8 XT |
1635 | { |
1636 | .irq_msk = BIT(CHL_INT1_DMAC_TX_ECC_MB_ERR_OFF), | |
1637 | .msg = "dmac_tx_ecc_bad_err", | |
1638 | }, | |
1639 | { | |
1640 | .irq_msk = BIT(CHL_INT1_DMAC_RX_ECC_MB_ERR_OFF), | |
1641 | .msg = "dmac_rx_ecc_bad_err", | |
1642 | }, | |
4a6125c5 XT |
1643 | { |
1644 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_WR_ERR_OFF), | |
1645 | .msg = "dma_tx_axi_wr_err", | |
1646 | }, | |
1647 | { | |
1648 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RD_ERR_OFF), | |
1649 | .msg = "dma_tx_axi_rd_err", | |
1650 | }, | |
1651 | { | |
1652 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_WR_ERR_OFF), | |
1653 | .msg = "dma_rx_axi_wr_err", | |
1654 | }, | |
1655 | { | |
1656 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RD_ERR_OFF), | |
1657 | .msg = "dma_rx_axi_rd_err", | |
1658 | }, | |
3168d4f8 XT |
1659 | { |
1660 | .irq_msk = BIT(CHL_INT1_DMAC_TX_FIFO_ERR_OFF), | |
1661 | .msg = "dma_tx_fifo_err", | |
1662 | }, | |
1663 | { | |
1664 | .irq_msk = BIT(CHL_INT1_DMAC_RX_FIFO_ERR_OFF), | |
1665 | .msg = "dma_rx_fifo_err", | |
1666 | }, | |
1667 | { | |
1668 | .irq_msk = BIT(CHL_INT1_DMAC_TX_AXI_RUSER_ERR_OFF), | |
1669 | .msg = "dma_tx_axi_ruser_err", | |
1670 | }, | |
1671 | { | |
1672 | .irq_msk = BIT(CHL_INT1_DMAC_RX_AXI_RUSER_ERR_OFF), | |
1673 | .msg = "dma_rx_axi_ruser_err", | |
1674 | }, | |
4a6125c5 XT |
1675 | }; |
1676 | ||
d9d51e0c | 1677 | static void handle_chl_int1_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
54edeee1 | 1678 | { |
d9d51e0c XT |
1679 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1); |
1680 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT1_MSK); | |
54edeee1 | 1681 | struct device *dev = hisi_hba->dev; |
d9d51e0c XT |
1682 | int i; |
1683 | ||
1684 | irq_value &= ~irq_msk; | |
1685 | if (!irq_value) | |
1686 | return; | |
1687 | ||
1688 | for (i = 0; i < ARRAY_SIZE(port_axi_error); i++) { | |
1689 | const struct hisi_sas_hw_error *error = &port_axi_error[i]; | |
1690 | ||
1691 | if (!(irq_value & error->irq_msk)) | |
1692 | continue; | |
1693 | ||
1694 | dev_err(dev, "%s error (phy%d 0x%x) found!\n", | |
1695 | error->msg, phy_no, irq_value); | |
1696 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
1697 | } | |
1698 | ||
1699 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT1, irq_value); | |
1700 | } | |
1701 | ||
aaeb8232 XT |
1702 | static void phy_get_events_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
1703 | { | |
1704 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
1705 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1706 | struct sas_phy *sphy = sas_phy->phy; | |
1707 | unsigned long flags; | |
1708 | u32 reg_value; | |
1709 | ||
1710 | spin_lock_irqsave(&phy->lock, flags); | |
1711 | ||
1712 | /* loss dword sync */ | |
1713 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DWS_LOST); | |
1714 | sphy->loss_of_dword_sync_count += reg_value; | |
1715 | ||
1716 | /* phy reset problem */ | |
1717 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_RESET_PROB); | |
1718 | sphy->phy_reset_problem_count += reg_value; | |
1719 | ||
1720 | /* invalid dword */ | |
1721 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_INVLD_DW); | |
1722 | sphy->invalid_dword_count += reg_value; | |
1723 | ||
1724 | /* disparity err */ | |
1725 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_DISP_ERR); | |
1726 | sphy->running_disparity_error_count += reg_value; | |
1727 | ||
1728 | /* code violation error */ | |
1729 | reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, ERR_CNT_CODE_ERR); | |
1730 | phy->code_violation_err_count += reg_value; | |
1731 | ||
1732 | spin_unlock_irqrestore(&phy->lock, flags); | |
1733 | } | |
1734 | ||
d9d51e0c XT |
1735 | static void handle_chl_int2_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
1736 | { | |
1737 | u32 irq_msk = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2_MSK); | |
1738 | u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT2); | |
1739 | struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no]; | |
f70c1251 | 1740 | struct pci_dev *pci_dev = hisi_hba->pci_dev; |
d9d51e0c | 1741 | struct device *dev = hisi_hba->dev; |
aaeb8232 XT |
1742 | static const u32 msk = BIT(CHL_INT2_RX_DISP_ERR_OFF) | |
1743 | BIT(CHL_INT2_RX_CODE_ERR_OFF) | | |
1744 | BIT(CHL_INT2_RX_INVLD_DW_OFF); | |
d9d51e0c XT |
1745 | |
1746 | irq_value &= ~irq_msk; | |
1747 | if (!irq_value) | |
1748 | return; | |
1749 | ||
1750 | if (irq_value & BIT(CHL_INT2_SL_IDAF_TOUT_CONF_OFF)) { | |
1751 | dev_warn(dev, "phy%d identify timeout\n", phy_no); | |
1752 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1753 | } | |
1754 | ||
1755 | if (irq_value & BIT(CHL_INT2_STP_LINK_TIMEOUT_OFF)) { | |
1756 | u32 reg_value = hisi_sas_phy_read32(hisi_hba, phy_no, | |
1757 | STP_LINK_TIMEOUT_STATE); | |
1758 | ||
1759 | dev_warn(dev, "phy%d stp link timeout (0x%x)\n", | |
1760 | phy_no, reg_value); | |
1761 | if (reg_value & BIT(4)) | |
1762 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
1763 | } | |
1764 | ||
aaeb8232 XT |
1765 | if (pci_dev->revision > 0x20 && (irq_value & msk)) { |
1766 | struct asd_sas_phy *sas_phy = &phy->sas_phy; | |
1767 | struct sas_phy *sphy = sas_phy->phy; | |
1768 | ||
1769 | phy_get_events_v3_hw(hisi_hba, phy_no); | |
1770 | ||
1771 | if (irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) | |
1772 | dev_info(dev, "phy%d invalid dword cnt: %u\n", phy_no, | |
1773 | sphy->invalid_dword_count); | |
1774 | ||
1775 | if (irq_value & BIT(CHL_INT2_RX_CODE_ERR_OFF)) | |
1776 | dev_info(dev, "phy%d code violation cnt: %u\n", phy_no, | |
1777 | phy->code_violation_err_count); | |
1778 | ||
1779 | if (irq_value & BIT(CHL_INT2_RX_DISP_ERR_OFF)) | |
1780 | dev_info(dev, "phy%d disparity error cnt: %u\n", phy_no, | |
1781 | sphy->running_disparity_error_count); | |
1782 | } | |
1783 | ||
d9d51e0c XT |
1784 | if ((irq_value & BIT(CHL_INT2_RX_INVLD_DW_OFF)) && |
1785 | (pci_dev->revision == 0x20)) { | |
1786 | u32 reg_value; | |
1787 | int rc; | |
1788 | ||
1789 | rc = hisi_sas_read32_poll_timeout_atomic( | |
1790 | HILINK_ERR_DFX, reg_value, | |
1791 | !((reg_value >> 8) & BIT(phy_no)), | |
1792 | 1000, 10000); | |
25908cac XT |
1793 | if (rc) |
1794 | hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET); | |
d9d51e0c | 1795 | } |
25908cac XT |
1796 | |
1797 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT2, irq_value); | |
d9d51e0c XT |
1798 | } |
1799 | ||
b6c9b15e XT |
1800 | static void handle_chl_int0_v3_hw(struct hisi_hba *hisi_hba, int phy_no) |
1801 | { | |
1802 | u32 irq_value0 = hisi_sas_phy_read32(hisi_hba, phy_no, CHL_INT0); | |
1803 | ||
1804 | if (irq_value0 & CHL_INT0_PHY_RDY_MSK) | |
1805 | hisi_sas_phy_oob_ready(hisi_hba, phy_no); | |
1806 | ||
1807 | hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0, | |
1808 | irq_value0 & (~CHL_INT0_SL_RX_BCST_ACK_MSK) | |
1809 | & (~CHL_INT0_SL_PHY_ENABLE_MSK) | |
1810 | & (~CHL_INT0_NOT_RDY_MSK)); | |
1811 | } | |
1812 | ||
d9d51e0c XT |
1813 | static irqreturn_t int_chnl_int_v3_hw(int irq_no, void *p) |
1814 | { | |
1815 | struct hisi_hba *hisi_hba = p; | |
bf081d5d | 1816 | u32 irq_msk; |
54edeee1 XC |
1817 | int phy_no = 0; |
1818 | ||
54edeee1 XC |
1819 | irq_msk = hisi_sas_read32(hisi_hba, CHNL_INT_STATUS) |
1820 | & 0xeeeeeeee; | |
1821 | ||
1822 | while (irq_msk) { | |
b6c9b15e XT |
1823 | if (irq_msk & (2 << (phy_no * 4))) |
1824 | handle_chl_int0_v3_hw(hisi_hba, phy_no); | |
057c3d1f | 1825 | |
d9d51e0c XT |
1826 | if (irq_msk & (4 << (phy_no * 4))) |
1827 | handle_chl_int1_v3_hw(hisi_hba, phy_no); | |
057c3d1f | 1828 | |
d9d51e0c XT |
1829 | if (irq_msk & (8 << (phy_no * 4))) |
1830 | handle_chl_int2_v3_hw(hisi_hba, phy_no); | |
54edeee1 | 1831 | |
54edeee1 XC |
1832 | irq_msk &= ~(0xe << (phy_no * 4)); |
1833 | phy_no++; | |
1834 | } | |
1835 | ||
54edeee1 XC |
1836 | return IRQ_HANDLED; |
1837 | } | |
1838 | ||
3168d4f8 XT |
1839 | static const struct hisi_sas_hw_error multi_bit_ecc_errors[] = { |
1840 | { | |
1841 | .irq_msk = BIT(SAS_ECC_INTR_DQE_ECC_MB_OFF), | |
1842 | .msk = HGC_DQE_ECC_MB_ADDR_MSK, | |
1843 | .shift = HGC_DQE_ECC_MB_ADDR_OFF, | |
794327ab | 1844 | .msg = "hgc_dqe_eccbad_intr", |
3168d4f8 XT |
1845 | .reg = HGC_DQE_ECC_ADDR, |
1846 | }, | |
1847 | { | |
1848 | .irq_msk = BIT(SAS_ECC_INTR_IOST_ECC_MB_OFF), | |
1849 | .msk = HGC_IOST_ECC_MB_ADDR_MSK, | |
1850 | .shift = HGC_IOST_ECC_MB_ADDR_OFF, | |
794327ab | 1851 | .msg = "hgc_iost_eccbad_intr", |
3168d4f8 XT |
1852 | .reg = HGC_IOST_ECC_ADDR, |
1853 | }, | |
1854 | { | |
1855 | .irq_msk = BIT(SAS_ECC_INTR_ITCT_ECC_MB_OFF), | |
1856 | .msk = HGC_ITCT_ECC_MB_ADDR_MSK, | |
1857 | .shift = HGC_ITCT_ECC_MB_ADDR_OFF, | |
794327ab | 1858 | .msg = "hgc_itct_eccbad_intr", |
3168d4f8 XT |
1859 | .reg = HGC_ITCT_ECC_ADDR, |
1860 | }, | |
1861 | { | |
1862 | .irq_msk = BIT(SAS_ECC_INTR_IOSTLIST_ECC_MB_OFF), | |
1863 | .msk = HGC_LM_DFX_STATUS2_IOSTLIST_MSK, | |
1864 | .shift = HGC_LM_DFX_STATUS2_IOSTLIST_OFF, | |
794327ab | 1865 | .msg = "hgc_iostl_eccbad_intr", |
3168d4f8 XT |
1866 | .reg = HGC_LM_DFX_STATUS2, |
1867 | }, | |
1868 | { | |
1869 | .irq_msk = BIT(SAS_ECC_INTR_ITCTLIST_ECC_MB_OFF), | |
1870 | .msk = HGC_LM_DFX_STATUS2_ITCTLIST_MSK, | |
1871 | .shift = HGC_LM_DFX_STATUS2_ITCTLIST_OFF, | |
794327ab | 1872 | .msg = "hgc_itctl_eccbad_intr", |
3168d4f8 XT |
1873 | .reg = HGC_LM_DFX_STATUS2, |
1874 | }, | |
1875 | { | |
1876 | .irq_msk = BIT(SAS_ECC_INTR_CQE_ECC_MB_OFF), | |
1877 | .msk = HGC_CQE_ECC_MB_ADDR_MSK, | |
1878 | .shift = HGC_CQE_ECC_MB_ADDR_OFF, | |
794327ab | 1879 | .msg = "hgc_cqe_eccbad_intr", |
3168d4f8 XT |
1880 | .reg = HGC_CQE_ECC_ADDR, |
1881 | }, | |
1882 | { | |
1883 | .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM0_ECC_MB_OFF), | |
1884 | .msk = HGC_RXM_DFX_STATUS14_MEM0_MSK, | |
1885 | .shift = HGC_RXM_DFX_STATUS14_MEM0_OFF, | |
794327ab | 1886 | .msg = "rxm_mem0_eccbad_intr", |
3168d4f8 XT |
1887 | .reg = HGC_RXM_DFX_STATUS14, |
1888 | }, | |
1889 | { | |
1890 | .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM1_ECC_MB_OFF), | |
1891 | .msk = HGC_RXM_DFX_STATUS14_MEM1_MSK, | |
1892 | .shift = HGC_RXM_DFX_STATUS14_MEM1_OFF, | |
794327ab | 1893 | .msg = "rxm_mem1_eccbad_intr", |
3168d4f8 XT |
1894 | .reg = HGC_RXM_DFX_STATUS14, |
1895 | }, | |
1896 | { | |
1897 | .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM2_ECC_MB_OFF), | |
1898 | .msk = HGC_RXM_DFX_STATUS14_MEM2_MSK, | |
1899 | .shift = HGC_RXM_DFX_STATUS14_MEM2_OFF, | |
794327ab | 1900 | .msg = "rxm_mem2_eccbad_intr", |
3168d4f8 XT |
1901 | .reg = HGC_RXM_DFX_STATUS14, |
1902 | }, | |
1903 | { | |
1904 | .irq_msk = BIT(SAS_ECC_INTR_NCQ_MEM3_ECC_MB_OFF), | |
1905 | .msk = HGC_RXM_DFX_STATUS15_MEM3_MSK, | |
1906 | .shift = HGC_RXM_DFX_STATUS15_MEM3_OFF, | |
794327ab | 1907 | .msg = "rxm_mem3_eccbad_intr", |
3168d4f8 XT |
1908 | .reg = HGC_RXM_DFX_STATUS15, |
1909 | }, | |
1910 | { | |
1911 | .irq_msk = BIT(SAS_ECC_INTR_OOO_RAM_ECC_MB_OFF), | |
1912 | .msk = AM_ROB_ECC_ERR_ADDR_MSK, | |
1913 | .shift = AM_ROB_ECC_ERR_ADDR_OFF, | |
794327ab | 1914 | .msg = "ooo_ram_eccbad_intr", |
3168d4f8 XT |
1915 | .reg = AM_ROB_ECC_ERR_ADDR, |
1916 | }, | |
1917 | }; | |
1918 | ||
1919 | static void multi_bit_ecc_error_process_v3_hw(struct hisi_hba *hisi_hba, | |
1920 | u32 irq_value) | |
1921 | { | |
1922 | struct device *dev = hisi_hba->dev; | |
1923 | const struct hisi_sas_hw_error *ecc_error; | |
1924 | u32 val; | |
1925 | int i; | |
1926 | ||
1927 | for (i = 0; i < ARRAY_SIZE(multi_bit_ecc_errors); i++) { | |
1928 | ecc_error = &multi_bit_ecc_errors[i]; | |
1929 | if (irq_value & ecc_error->irq_msk) { | |
1930 | val = hisi_sas_read32(hisi_hba, ecc_error->reg); | |
1931 | val &= ecc_error->msk; | |
1932 | val >>= ecc_error->shift; | |
794327ab XT |
1933 | dev_err(dev, "%s (0x%x) found: mem addr is 0x%08X\n", |
1934 | ecc_error->msg, irq_value, val); | |
3168d4f8 XT |
1935 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); |
1936 | } | |
1937 | } | |
1938 | } | |
1939 | ||
1940 | static void fatal_ecc_int_v3_hw(struct hisi_hba *hisi_hba) | |
1941 | { | |
1942 | u32 irq_value, irq_msk; | |
1943 | ||
1944 | irq_msk = hisi_sas_read32(hisi_hba, SAS_ECC_INTR_MSK); | |
a07b4876 | 1945 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); |
3168d4f8 XT |
1946 | |
1947 | irq_value = hisi_sas_read32(hisi_hba, SAS_ECC_INTR); | |
1948 | if (irq_value) | |
1949 | multi_bit_ecc_error_process_v3_hw(hisi_hba, irq_value); | |
1950 | ||
1951 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR, irq_value); | |
1952 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, irq_msk); | |
1953 | } | |
1954 | ||
fa231408 XT |
1955 | static const struct hisi_sas_hw_error axi_error[] = { |
1956 | { .msk = BIT(0), .msg = "IOST_AXI_W_ERR" }, | |
1957 | { .msk = BIT(1), .msg = "IOST_AXI_R_ERR" }, | |
1958 | { .msk = BIT(2), .msg = "ITCT_AXI_W_ERR" }, | |
1959 | { .msk = BIT(3), .msg = "ITCT_AXI_R_ERR" }, | |
1960 | { .msk = BIT(4), .msg = "SATA_AXI_W_ERR" }, | |
1961 | { .msk = BIT(5), .msg = "SATA_AXI_R_ERR" }, | |
1962 | { .msk = BIT(6), .msg = "DQE_AXI_R_ERR" }, | |
1963 | { .msk = BIT(7), .msg = "CQE_AXI_W_ERR" }, | |
01d4e3a2 | 1964 | {} |
fa231408 XT |
1965 | }; |
1966 | ||
1967 | static const struct hisi_sas_hw_error fifo_error[] = { | |
1968 | { .msk = BIT(8), .msg = "CQE_WINFO_FIFO" }, | |
1969 | { .msk = BIT(9), .msg = "CQE_MSG_FIFIO" }, | |
1970 | { .msk = BIT(10), .msg = "GETDQE_FIFO" }, | |
1971 | { .msk = BIT(11), .msg = "CMDP_FIFO" }, | |
1972 | { .msk = BIT(12), .msg = "AWTCTRL_FIFO" }, | |
01d4e3a2 | 1973 | {} |
fa231408 XT |
1974 | }; |
1975 | ||
1976 | static const struct hisi_sas_hw_error fatal_axi_error[] = { | |
1977 | { | |
1978 | .irq_msk = BIT(ENT_INT_SRC3_WP_DEPTH_OFF), | |
1979 | .msg = "write pointer and depth", | |
1980 | }, | |
1981 | { | |
1982 | .irq_msk = BIT(ENT_INT_SRC3_IPTT_SLOT_NOMATCH_OFF), | |
1983 | .msg = "iptt no match slot", | |
1984 | }, | |
1985 | { | |
1986 | .irq_msk = BIT(ENT_INT_SRC3_RP_DEPTH_OFF), | |
1987 | .msg = "read pointer and depth", | |
1988 | }, | |
1989 | { | |
1990 | .irq_msk = BIT(ENT_INT_SRC3_AXI_OFF), | |
1991 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1992 | .sub = axi_error, | |
1993 | }, | |
1994 | { | |
1995 | .irq_msk = BIT(ENT_INT_SRC3_FIFO_OFF), | |
1996 | .reg = HGC_AXI_FIFO_ERR_INFO, | |
1997 | .sub = fifo_error, | |
1998 | }, | |
1999 | { | |
2000 | .irq_msk = BIT(ENT_INT_SRC3_LM_OFF), | |
2001 | .msg = "LM add/fetch list", | |
2002 | }, | |
2003 | { | |
2004 | .irq_msk = BIT(ENT_INT_SRC3_ABT_OFF), | |
2005 | .msg = "SAS_HGC_ABT fetch LM list", | |
2006 | }, | |
3168d4f8 XT |
2007 | { |
2008 | .irq_msk = BIT(ENT_INT_SRC3_DQE_POISON_OFF), | |
2009 | .msg = "read dqe poison", | |
2010 | }, | |
2011 | { | |
2012 | .irq_msk = BIT(ENT_INT_SRC3_IOST_POISON_OFF), | |
2013 | .msg = "read iost poison", | |
2014 | }, | |
2015 | { | |
2016 | .irq_msk = BIT(ENT_INT_SRC3_ITCT_POISON_OFF), | |
2017 | .msg = "read itct poison", | |
2018 | }, | |
2019 | { | |
2020 | .irq_msk = BIT(ENT_INT_SRC3_ITCT_NCQ_POISON_OFF), | |
2021 | .msg = "read itct ncq poison", | |
2022 | }, | |
2023 | ||
fa231408 XT |
2024 | }; |
2025 | ||
2026 | static irqreturn_t fatal_axi_int_v3_hw(int irq_no, void *p) | |
2027 | { | |
2028 | u32 irq_value, irq_msk; | |
2029 | struct hisi_hba *hisi_hba = p; | |
2030 | struct device *dev = hisi_hba->dev; | |
5c31b0c6 | 2031 | struct pci_dev *pdev = hisi_hba->pci_dev; |
fa231408 XT |
2032 | int i; |
2033 | ||
2034 | irq_msk = hisi_sas_read32(hisi_hba, ENT_INT_SRC_MSK3); | |
2035 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk | 0x1df00); | |
2036 | ||
2037 | irq_value = hisi_sas_read32(hisi_hba, ENT_INT_SRC3); | |
61573630 | 2038 | irq_value &= ~irq_msk; |
fa231408 XT |
2039 | |
2040 | for (i = 0; i < ARRAY_SIZE(fatal_axi_error); i++) { | |
2041 | const struct hisi_sas_hw_error *error = &fatal_axi_error[i]; | |
2042 | ||
2043 | if (!(irq_value & error->irq_msk)) | |
2044 | continue; | |
2045 | ||
2046 | if (error->sub) { | |
2047 | const struct hisi_sas_hw_error *sub = error->sub; | |
2048 | u32 err_value = hisi_sas_read32(hisi_hba, error->reg); | |
2049 | ||
2050 | for (; sub->msk || sub->msg; sub++) { | |
2051 | if (!(err_value & sub->msk)) | |
2052 | continue; | |
2053 | ||
f1c88211 | 2054 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
2055 | sub->msg, irq_value); |
2056 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
2057 | } | |
2058 | } else { | |
f1c88211 | 2059 | dev_err(dev, "%s error (0x%x) found!\n", |
fa231408 XT |
2060 | error->msg, irq_value); |
2061 | queue_work(hisi_hba->wq, &hisi_hba->rst_work); | |
2062 | } | |
5c31b0c6 XC |
2063 | |
2064 | if (pdev->revision < 0x21) { | |
2065 | u32 reg_val; | |
2066 | ||
2067 | reg_val = hisi_sas_read32(hisi_hba, | |
2068 | AXI_MASTER_CFG_BASE + | |
2069 | AM_CTRL_GLOBAL); | |
2070 | reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; | |
2071 | hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + | |
2072 | AM_CTRL_GLOBAL, reg_val); | |
2073 | } | |
fa231408 XT |
2074 | } |
2075 | ||
3168d4f8 XT |
2076 | fatal_ecc_int_v3_hw(hisi_hba); |
2077 | ||
fa231408 XT |
2078 | if (irq_value & BIT(ENT_INT_SRC3_ITC_INT_OFF)) { |
2079 | u32 reg_val = hisi_sas_read32(hisi_hba, ITCT_CLR); | |
2080 | u32 dev_id = reg_val & ITCT_DEV_MSK; | |
2081 | struct hisi_sas_device *sas_dev = | |
2082 | &hisi_hba->devices[dev_id]; | |
2083 | ||
2084 | hisi_sas_write32(hisi_hba, ITCT_CLR, 0); | |
2085 | dev_dbg(dev, "clear ITCT ok\n"); | |
2086 | complete(sas_dev->completion); | |
2087 | } | |
2088 | ||
2089 | hisi_sas_write32(hisi_hba, ENT_INT_SRC3, irq_value & 0x1df00); | |
2090 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, irq_msk); | |
2091 | ||
2092 | return IRQ_HANDLED; | |
2093 | } | |
2094 | ||
60b4a5ee XC |
2095 | static void |
2096 | slot_err_v3_hw(struct hisi_hba *hisi_hba, struct sas_task *task, | |
2097 | struct hisi_sas_slot *slot) | |
2098 | { | |
2099 | struct task_status_struct *ts = &task->task_status; | |
2100 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
2101 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
2102 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
2103 | &complete_queue[slot->cmplt_queue_slot]; | |
f557e32c XT |
2104 | struct hisi_sas_err_record_v3 *record = |
2105 | hisi_sas_status_buf_addr_mem(slot); | |
735bcc77 JG |
2106 | u32 dma_rx_err_type = le32_to_cpu(record->dma_rx_err_type); |
2107 | u32 trans_tx_fail_type = le32_to_cpu(record->trans_tx_fail_type); | |
2108 | u32 dw3 = le32_to_cpu(complete_hdr->dw3); | |
60b4a5ee XC |
2109 | |
2110 | switch (task->task_proto) { | |
2111 | case SAS_PROTOCOL_SSP: | |
2112 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
2113 | ts->residual = trans_tx_fail_type; | |
2114 | ts->stat = SAS_DATA_UNDERRUN; | |
735bcc77 | 2115 | } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { |
60b4a5ee XC |
2116 | ts->stat = SAS_QUEUE_FULL; |
2117 | slot->abort = 1; | |
2118 | } else { | |
2119 | ts->stat = SAS_OPEN_REJECT; | |
2120 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2121 | } | |
2122 | break; | |
2123 | case SAS_PROTOCOL_SATA: | |
2124 | case SAS_PROTOCOL_STP: | |
2125 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
2126 | if (dma_rx_err_type & RX_DATA_LEN_UNDERFLOW_MSK) { | |
2127 | ts->residual = trans_tx_fail_type; | |
2128 | ts->stat = SAS_DATA_UNDERRUN; | |
735bcc77 | 2129 | } else if (dw3 & CMPLT_HDR_IO_IN_TARGET_MSK) { |
60b4a5ee XC |
2130 | ts->stat = SAS_PHY_DOWN; |
2131 | slot->abort = 1; | |
2132 | } else { | |
2133 | ts->stat = SAS_OPEN_REJECT; | |
2134 | ts->open_rej_reason = SAS_OREJ_RSVD_RETRY; | |
2135 | } | |
2136 | hisi_sas_sata_done(task, slot); | |
2137 | break; | |
2138 | case SAS_PROTOCOL_SMP: | |
2139 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
2140 | break; | |
2141 | default: | |
2142 | break; | |
2143 | } | |
2144 | } | |
2145 | ||
2146 | static int | |
2147 | slot_complete_v3_hw(struct hisi_hba *hisi_hba, struct hisi_sas_slot *slot) | |
2148 | { | |
2149 | struct sas_task *task = slot->task; | |
2150 | struct hisi_sas_device *sas_dev; | |
2151 | struct device *dev = hisi_hba->dev; | |
2152 | struct task_status_struct *ts; | |
2153 | struct domain_device *device; | |
cd938e53 | 2154 | struct sas_ha_struct *ha; |
60b4a5ee XC |
2155 | enum exec_status sts; |
2156 | struct hisi_sas_complete_v3_hdr *complete_queue = | |
2157 | hisi_hba->complete_hdr[slot->cmplt_queue]; | |
2158 | struct hisi_sas_complete_v3_hdr *complete_hdr = | |
2159 | &complete_queue[slot->cmplt_queue_slot]; | |
60b4a5ee | 2160 | unsigned long flags; |
cd938e53 | 2161 | bool is_internal = slot->is_internal; |
735bcc77 | 2162 | u32 dw0, dw1, dw3; |
60b4a5ee XC |
2163 | |
2164 | if (unlikely(!task || !task->lldd_task || !task->dev)) | |
2165 | return -EINVAL; | |
2166 | ||
2167 | ts = &task->task_status; | |
2168 | device = task->dev; | |
cd938e53 | 2169 | ha = device->port->ha; |
60b4a5ee XC |
2170 | sas_dev = device->lldd_dev; |
2171 | ||
2172 | spin_lock_irqsave(&task->task_state_lock, flags); | |
60b4a5ee XC |
2173 | task->task_state_flags &= |
2174 | ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR); | |
2175 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
2176 | ||
2177 | memset(ts, 0, sizeof(*ts)); | |
2178 | ts->resp = SAS_TASK_COMPLETE; | |
60b4a5ee XC |
2179 | |
2180 | if (unlikely(!sas_dev)) { | |
2181 | dev_dbg(dev, "slot complete: port has not device\n"); | |
2182 | ts->stat = SAS_PHY_DOWN; | |
2183 | goto out; | |
2184 | } | |
2185 | ||
735bcc77 JG |
2186 | dw0 = le32_to_cpu(complete_hdr->dw0); |
2187 | dw1 = le32_to_cpu(complete_hdr->dw1); | |
2188 | dw3 = le32_to_cpu(complete_hdr->dw3); | |
2189 | ||
60b4a5ee XC |
2190 | /* |
2191 | * Use SAS+TMF status codes | |
2192 | */ | |
735bcc77 | 2193 | switch ((dw0 & CMPLT_HDR_ABORT_STAT_MSK) >> CMPLT_HDR_ABORT_STAT_OFF) { |
60b4a5ee XC |
2194 | case STAT_IO_ABORTED: |
2195 | /* this IO has been aborted by abort command */ | |
2196 | ts->stat = SAS_ABORTED_TASK; | |
2197 | goto out; | |
2198 | case STAT_IO_COMPLETE: | |
2199 | /* internal abort command complete */ | |
2200 | ts->stat = TMF_RESP_FUNC_SUCC; | |
2201 | goto out; | |
2202 | case STAT_IO_NO_DEVICE: | |
2203 | ts->stat = TMF_RESP_FUNC_COMPLETE; | |
2204 | goto out; | |
2205 | case STAT_IO_NOT_VALID: | |
2206 | /* | |
2207 | * abort single IO, the controller can't find the IO | |
2208 | */ | |
2209 | ts->stat = TMF_RESP_FUNC_FAILED; | |
2210 | goto out; | |
2211 | default: | |
2212 | break; | |
2213 | } | |
2214 | ||
2215 | /* check for erroneous completion */ | |
735bcc77 | 2216 | if ((dw0 & CMPLT_HDR_CMPLT_MSK) == 0x3) { |
f1c88211 XC |
2217 | u32 *error_info = hisi_sas_status_buf_addr_mem(slot); |
2218 | ||
60b4a5ee | 2219 | slot_err_v3_hw(hisi_hba, task, slot); |
f1c88211 | 2220 | if (ts->stat != SAS_DATA_UNDERRUN) |
e7513f66 | 2221 | dev_info(dev, "erroneous completion iptt=%d task=%pK dev id=%d CQ hdr: 0x%x 0x%x 0x%x 0x%x Error info: 0x%x 0x%x 0x%x 0x%x\n", |
01d4e3a2 XC |
2222 | slot->idx, task, sas_dev->device_id, |
2223 | dw0, dw1, complete_hdr->act, dw3, | |
2224 | error_info[0], error_info[1], | |
2225 | error_info[2], error_info[3]); | |
60b4a5ee XC |
2226 | if (unlikely(slot->abort)) |
2227 | return ts->stat; | |
2228 | goto out; | |
2229 | } | |
2230 | ||
2231 | switch (task->task_proto) { | |
2232 | case SAS_PROTOCOL_SSP: { | |
f557e32c XT |
2233 | struct ssp_response_iu *iu = |
2234 | hisi_sas_status_buf_addr_mem(slot) + | |
60b4a5ee XC |
2235 | sizeof(struct hisi_sas_err_record); |
2236 | ||
2237 | sas_ssp_task_response(dev, task, iu); | |
2238 | break; | |
2239 | } | |
2240 | case SAS_PROTOCOL_SMP: { | |
2241 | struct scatterlist *sg_resp = &task->smp_task.smp_resp; | |
1c003146 | 2242 | void *to = page_address(sg_page(sg_resp)); |
60b4a5ee XC |
2243 | |
2244 | ts->stat = SAM_STAT_GOOD; | |
60b4a5ee | 2245 | |
60b4a5ee XC |
2246 | dma_unmap_sg(dev, &task->smp_task.smp_req, 1, |
2247 | DMA_TO_DEVICE); | |
2248 | memcpy(to + sg_resp->offset, | |
f557e32c | 2249 | hisi_sas_status_buf_addr_mem(slot) + |
60b4a5ee | 2250 | sizeof(struct hisi_sas_err_record), |
5f6c32d7 | 2251 | sg_resp->length); |
60b4a5ee XC |
2252 | break; |
2253 | } | |
2254 | case SAS_PROTOCOL_SATA: | |
2255 | case SAS_PROTOCOL_STP: | |
2256 | case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: | |
2257 | ts->stat = SAM_STAT_GOOD; | |
2258 | hisi_sas_sata_done(task, slot); | |
2259 | break; | |
2260 | default: | |
2261 | ts->stat = SAM_STAT_CHECK_CONDITION; | |
2262 | break; | |
2263 | } | |
2264 | ||
2265 | if (!slot->port->port_attached) { | |
f1c88211 | 2266 | dev_warn(dev, "slot complete: port %d has removed\n", |
60b4a5ee XC |
2267 | slot->port->sas_port.id); |
2268 | ts->stat = SAS_PHY_DOWN; | |
2269 | } | |
2270 | ||
2271 | out: | |
b81b6cce | 2272 | sts = ts->stat; |
60b4a5ee | 2273 | spin_lock_irqsave(&task->task_state_lock, flags); |
b81b6cce XC |
2274 | if (task->task_state_flags & SAS_TASK_STATE_ABORTED) { |
2275 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
e7513f66 | 2276 | dev_info(dev, "slot complete: task(%pK) aborted\n", task); |
b81b6cce XC |
2277 | return SAS_ABORTED_TASK; |
2278 | } | |
60b4a5ee XC |
2279 | task->task_state_flags |= SAS_TASK_STATE_DONE; |
2280 | spin_unlock_irqrestore(&task->task_state_lock, flags); | |
3e178f3e | 2281 | hisi_sas_slot_task_free(hisi_hba, task, slot); |
60b4a5ee | 2282 | |
cd938e53 XC |
2283 | if (!is_internal && (task->task_proto != SAS_PROTOCOL_SMP)) { |
2284 | spin_lock_irqsave(&device->done_lock, flags); | |
2285 | if (test_bit(SAS_HA_FROZEN, &ha->state)) { | |
2286 | spin_unlock_irqrestore(&device->done_lock, flags); | |
e7513f66 | 2287 | dev_info(dev, "slot complete: task(%pK) ignored\n ", |
cd938e53 XC |
2288 | task); |
2289 | return sts; | |
2290 | } | |
2291 | spin_unlock_irqrestore(&device->done_lock, flags); | |
2292 | } | |
2293 | ||
60b4a5ee XC |
2294 | if (task->task_done) |
2295 | task->task_done(task); | |
2296 | ||
2297 | return sts; | |
2298 | } | |
2299 | ||
2300 | static void cq_tasklet_v3_hw(unsigned long val) | |
2301 | { | |
2302 | struct hisi_sas_cq *cq = (struct hisi_sas_cq *)val; | |
2303 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
2304 | struct hisi_sas_slot *slot; | |
60b4a5ee | 2305 | struct hisi_sas_complete_v3_hdr *complete_queue; |
9f347b2f | 2306 | u32 rd_point = cq->rd_point, wr_point; |
60b4a5ee | 2307 | int queue = cq->id; |
60b4a5ee XC |
2308 | |
2309 | complete_queue = hisi_hba->complete_hdr[queue]; | |
2310 | ||
60b4a5ee XC |
2311 | wr_point = hisi_sas_read32(hisi_hba, COMPL_Q_0_WR_PTR + |
2312 | (0x14 * queue)); | |
2313 | ||
2314 | while (rd_point != wr_point) { | |
2315 | struct hisi_sas_complete_v3_hdr *complete_hdr; | |
327f242f | 2316 | struct device *dev = hisi_hba->dev; |
735bcc77 | 2317 | u32 dw1; |
60b4a5ee XC |
2318 | int iptt; |
2319 | ||
2320 | complete_hdr = &complete_queue[rd_point]; | |
735bcc77 | 2321 | dw1 = le32_to_cpu(complete_hdr->dw1); |
60b4a5ee | 2322 | |
735bcc77 | 2323 | iptt = dw1 & CMPLT_HDR_IPTT_MSK; |
327f242f XT |
2324 | if (likely(iptt < HISI_SAS_COMMAND_ENTRIES_V3_HW)) { |
2325 | slot = &hisi_hba->slot_info[iptt]; | |
2326 | slot->cmplt_queue_slot = rd_point; | |
2327 | slot->cmplt_queue = queue; | |
2328 | slot_complete_v3_hw(hisi_hba, slot); | |
2329 | } else | |
2330 | dev_err(dev, "IPTT %d is invalid, discard it.\n", iptt); | |
60b4a5ee XC |
2331 | |
2332 | if (++rd_point >= HISI_SAS_QUEUE_SLOTS) | |
2333 | rd_point = 0; | |
2334 | } | |
2335 | ||
2336 | /* update rd_point */ | |
2337 | cq->rd_point = rd_point; | |
2338 | hisi_sas_write32(hisi_hba, COMPL_Q_0_RD_PTR + (0x14 * queue), rd_point); | |
60b4a5ee XC |
2339 | } |
2340 | ||
2341 | static irqreturn_t cq_interrupt_v3_hw(int irq_no, void *p) | |
2342 | { | |
2343 | struct hisi_sas_cq *cq = p; | |
2344 | struct hisi_hba *hisi_hba = cq->hisi_hba; | |
2345 | int queue = cq->id; | |
2346 | ||
2347 | hisi_sas_write32(hisi_hba, OQ_INT_SRC, 1 << queue); | |
2348 | ||
2349 | tasklet_schedule(&cq->tasklet); | |
2350 | ||
2351 | return IRQ_HANDLED; | |
2352 | } | |
2353 | ||
4fefe5bb XC |
2354 | static void setup_reply_map_v3_hw(struct hisi_hba *hisi_hba, int nvecs) |
2355 | { | |
2356 | const struct cpumask *mask; | |
2357 | int queue, cpu; | |
2358 | ||
2359 | for (queue = 0; queue < nvecs; queue++) { | |
2360 | struct hisi_sas_cq *cq = &hisi_hba->cq[queue]; | |
2361 | ||
2362 | mask = pci_irq_get_affinity(hisi_hba->pci_dev, queue + | |
2363 | BASE_VECTORS_V3_HW); | |
2364 | if (!mask) | |
2365 | goto fallback; | |
2366 | cq->pci_irq_mask = mask; | |
2367 | for_each_cpu(cpu, mask) | |
2368 | hisi_hba->reply_map[cpu] = queue; | |
2369 | } | |
2370 | return; | |
2371 | ||
2372 | fallback: | |
2373 | for_each_possible_cpu(cpu) | |
2374 | hisi_hba->reply_map[cpu] = cpu % hisi_hba->queue_count; | |
2375 | /* Don't clean all CQ masks */ | |
2376 | } | |
2377 | ||
54edeee1 XC |
2378 | static int interrupt_init_v3_hw(struct hisi_hba *hisi_hba) |
2379 | { | |
2380 | struct device *dev = hisi_hba->dev; | |
2381 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
e16963f3 | 2382 | int vectors, rc, i; |
4fefe5bb XC |
2383 | int max_msi = HISI_SAS_MSI_COUNT_V3_HW, min_msi; |
2384 | ||
2385 | if (auto_affine_msi_experimental) { | |
2386 | struct irq_affinity desc = { | |
2387 | .pre_vectors = BASE_VECTORS_V3_HW, | |
2388 | }; | |
2389 | ||
2390 | min_msi = MIN_AFFINE_VECTORS_V3_HW; | |
2391 | ||
2392 | hisi_hba->reply_map = devm_kcalloc(dev, nr_cpu_ids, | |
2393 | sizeof(unsigned int), | |
2394 | GFP_KERNEL); | |
2395 | if (!hisi_hba->reply_map) | |
2396 | return -ENOMEM; | |
2397 | vectors = pci_alloc_irq_vectors_affinity(hisi_hba->pci_dev, | |
2398 | min_msi, max_msi, | |
2399 | PCI_IRQ_MSI | | |
2400 | PCI_IRQ_AFFINITY, | |
2401 | &desc); | |
2402 | if (vectors < 0) | |
2403 | return -ENOENT; | |
2404 | setup_reply_map_v3_hw(hisi_hba, vectors - BASE_VECTORS_V3_HW); | |
2405 | } else { | |
2406 | min_msi = max_msi; | |
2407 | vectors = pci_alloc_irq_vectors(hisi_hba->pci_dev, min_msi, | |
2408 | max_msi, PCI_IRQ_MSI); | |
2409 | if (vectors < 0) | |
2410 | return vectors; | |
54edeee1 XC |
2411 | } |
2412 | ||
795f25a3 JG |
2413 | hisi_hba->cq_nvecs = vectors - BASE_VECTORS_V3_HW; |
2414 | ||
54edeee1 XC |
2415 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 1), |
2416 | int_phy_up_down_bcast_v3_hw, 0, | |
2417 | DRV_NAME " phy", hisi_hba); | |
2418 | if (rc) { | |
2419 | dev_err(dev, "could not request phy interrupt, rc=%d\n", rc); | |
2420 | rc = -ENOENT; | |
2421 | goto free_irq_vectors; | |
2422 | } | |
2423 | ||
2424 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 2), | |
2425 | int_chnl_int_v3_hw, 0, | |
2426 | DRV_NAME " channel", hisi_hba); | |
2427 | if (rc) { | |
2428 | dev_err(dev, "could not request chnl interrupt, rc=%d\n", rc); | |
2429 | rc = -ENOENT; | |
e16963f3 | 2430 | goto free_irq_vectors; |
54edeee1 XC |
2431 | } |
2432 | ||
fa231408 XT |
2433 | rc = devm_request_irq(dev, pci_irq_vector(pdev, 11), |
2434 | fatal_axi_int_v3_hw, 0, | |
2435 | DRV_NAME " fatal", hisi_hba); | |
2436 | if (rc) { | |
2437 | dev_err(dev, "could not request fatal interrupt, rc=%d\n", rc); | |
2438 | rc = -ENOENT; | |
e16963f3 | 2439 | goto free_irq_vectors; |
fa231408 XT |
2440 | } |
2441 | ||
60b4a5ee | 2442 | /* Init tasklets for cq only */ |
795f25a3 | 2443 | for (i = 0; i < hisi_hba->cq_nvecs; i++) { |
60b4a5ee XC |
2444 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; |
2445 | struct tasklet_struct *t = &cq->tasklet; | |
488cf558 XC |
2446 | int nr = hisi_sas_intr_conv ? 16 : 16 + i; |
2447 | unsigned long irqflags = hisi_sas_intr_conv ? IRQF_SHARED : 0; | |
60b4a5ee | 2448 | |
488cf558 XC |
2449 | rc = devm_request_irq(dev, pci_irq_vector(pdev, nr), |
2450 | cq_interrupt_v3_hw, irqflags, | |
2451 | DRV_NAME " cq", cq); | |
60b4a5ee | 2452 | if (rc) { |
01d4e3a2 | 2453 | dev_err(dev, "could not request cq%d interrupt, rc=%d\n", |
60b4a5ee XC |
2454 | i, rc); |
2455 | rc = -ENOENT; | |
e16963f3 | 2456 | goto free_irq_vectors; |
60b4a5ee XC |
2457 | } |
2458 | ||
2459 | tasklet_init(t, cq_tasklet_v3_hw, (unsigned long)cq); | |
2460 | } | |
54edeee1 XC |
2461 | |
2462 | return 0; | |
2463 | ||
54edeee1 XC |
2464 | free_irq_vectors: |
2465 | pci_free_irq_vectors(pdev); | |
2466 | return rc; | |
2467 | } | |
2468 | ||
c94d8ca2 XC |
2469 | static int hisi_sas_v3_init(struct hisi_hba *hisi_hba) |
2470 | { | |
2471 | int rc; | |
2472 | ||
2473 | rc = hw_init_v3_hw(hisi_hba); | |
2474 | if (rc) | |
2475 | return rc; | |
2476 | ||
54edeee1 XC |
2477 | rc = interrupt_init_v3_hw(hisi_hba); |
2478 | if (rc) | |
2479 | return rc; | |
2480 | ||
c94d8ca2 XC |
2481 | return 0; |
2482 | } | |
2483 | ||
2400620c XC |
2484 | static void phy_set_linkrate_v3_hw(struct hisi_hba *hisi_hba, int phy_no, |
2485 | struct sas_phy_linkrates *r) | |
2486 | { | |
757db2da | 2487 | enum sas_linkrate max = r->maximum_linkrate; |
c2c1d9de | 2488 | u32 prog_phy_link_rate = 0x800; |
2400620c | 2489 | |
c2c1d9de | 2490 | prog_phy_link_rate |= hisi_sas_get_prog_phy_linkrate_mask(max); |
2400620c | 2491 | hisi_sas_phy_write32(hisi_hba, phy_no, PROG_PHY_LINK_RATE, |
757db2da | 2492 | prog_phy_link_rate); |
2400620c XC |
2493 | } |
2494 | ||
a25d0d3d XC |
2495 | static void interrupt_disable_v3_hw(struct hisi_hba *hisi_hba) |
2496 | { | |
2497 | struct pci_dev *pdev = hisi_hba->pci_dev; | |
2498 | int i; | |
2499 | ||
2500 | synchronize_irq(pci_irq_vector(pdev, 1)); | |
2501 | synchronize_irq(pci_irq_vector(pdev, 2)); | |
2502 | synchronize_irq(pci_irq_vector(pdev, 11)); | |
2503 | for (i = 0; i < hisi_hba->queue_count; i++) { | |
2504 | hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK + 0x4 * i, 0x1); | |
2505 | synchronize_irq(pci_irq_vector(pdev, i + 16)); | |
2506 | } | |
2507 | ||
2508 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0xffffffff); | |
2509 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0xffffffff); | |
2510 | hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0xffffffff); | |
2511 | hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xffffffff); | |
2512 | ||
2513 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
2514 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff); | |
2515 | hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0xffffffff); | |
2516 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x1); | |
2517 | hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x1); | |
2518 | hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x1); | |
2519 | } | |
2520 | } | |
2521 | ||
2522 | static u32 get_phys_state_v3_hw(struct hisi_hba *hisi_hba) | |
2523 | { | |
2524 | return hisi_sas_read32(hisi_hba, PHY_STATE); | |
2525 | } | |
2526 | ||
e8ce775e | 2527 | static int disable_host_v3_hw(struct hisi_hba *hisi_hba) |
a25d0d3d XC |
2528 | { |
2529 | struct device *dev = hisi_hba->dev; | |
e8ce775e | 2530 | u32 status, reg_val; |
a25d0d3d | 2531 | int rc; |
a25d0d3d XC |
2532 | |
2533 | interrupt_disable_v3_hw(hisi_hba); | |
2534 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0x0); | |
571295f8 | 2535 | hisi_sas_kill_tasklets(hisi_hba); |
a25d0d3d XC |
2536 | |
2537 | hisi_sas_stop_phys(hisi_hba); | |
2538 | ||
2539 | mdelay(10); | |
2540 | ||
e8ce775e XT |
2541 | reg_val = hisi_sas_read32(hisi_hba, AXI_MASTER_CFG_BASE + |
2542 | AM_CTRL_GLOBAL); | |
2543 | reg_val |= AM_CTRL_SHUTDOWN_REQ_MSK; | |
2544 | hisi_sas_write32(hisi_hba, AXI_MASTER_CFG_BASE + | |
2545 | AM_CTRL_GLOBAL, reg_val); | |
a25d0d3d XC |
2546 | |
2547 | /* wait until bus idle */ | |
9b8addf3 JG |
2548 | rc = hisi_sas_read32_poll_timeout(AXI_MASTER_CFG_BASE + |
2549 | AM_CURR_TRANS_RETURN, status, | |
2550 | status == 0x3, 10, 100); | |
a25d0d3d | 2551 | if (rc) { |
e8ce775e XT |
2552 | dev_err(dev, "axi bus is not idle, rc=%d\n", rc); |
2553 | return rc; | |
2554 | } | |
2555 | ||
2556 | return 0; | |
2557 | } | |
2558 | ||
2559 | static int soft_reset_v3_hw(struct hisi_hba *hisi_hba) | |
2560 | { | |
2561 | struct device *dev = hisi_hba->dev; | |
2562 | int rc; | |
2563 | ||
2564 | rc = disable_host_v3_hw(hisi_hba); | |
2565 | if (rc) { | |
2566 | dev_err(dev, "soft reset: disable host failed rc=%d\n", rc); | |
a25d0d3d XC |
2567 | return rc; |
2568 | } | |
2569 | ||
2570 | hisi_sas_init_mem(hisi_hba); | |
2571 | ||
2572 | return hw_init_v3_hw(hisi_hba); | |
2573 | } | |
2574 | ||
428f1b34 XT |
2575 | static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type, |
2576 | u8 reg_index, u8 reg_count, u8 *write_data) | |
2577 | { | |
2578 | struct device *dev = hisi_hba->dev; | |
2579 | u32 *data = (u32 *)write_data; | |
2580 | int i; | |
2581 | ||
2582 | switch (reg_type) { | |
2583 | case SAS_GPIO_REG_TX: | |
2584 | if ((reg_index + reg_count) > ((hisi_hba->n_phy + 3) / 4)) { | |
2585 | dev_err(dev, "write gpio: invalid reg range[%d, %d]\n", | |
2586 | reg_index, reg_index + reg_count - 1); | |
2587 | return -EINVAL; | |
2588 | } | |
2589 | ||
2590 | for (i = 0; i < reg_count; i++) | |
2591 | hisi_sas_write32(hisi_hba, | |
2592 | SAS_GPIO_TX_0_1 + (reg_index + i) * 4, | |
2593 | data[i]); | |
2594 | break; | |
2595 | default: | |
2596 | dev_err(dev, "write gpio: unsupported or bad reg type %d\n", | |
01d4e3a2 | 2597 | reg_type); |
428f1b34 XT |
2598 | return -EINVAL; |
2599 | } | |
2600 | ||
2601 | return 0; | |
2602 | } | |
2603 | ||
4bc05809 LJ |
2604 | static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba, |
2605 | int delay_ms, int timeout_ms) | |
a865ae14 XT |
2606 | { |
2607 | struct device *dev = hisi_hba->dev; | |
2608 | int entries, entries_old = 0, time; | |
2609 | ||
2610 | for (time = 0; time < timeout_ms; time += delay_ms) { | |
2611 | entries = hisi_sas_read32(hisi_hba, CQE_SEND_CNT); | |
2612 | if (entries == entries_old) | |
2613 | break; | |
2614 | ||
2615 | entries_old = entries; | |
2616 | msleep(delay_ms); | |
2617 | } | |
2618 | ||
4bc05809 LJ |
2619 | if (time >= timeout_ms) { |
2620 | dev_dbg(dev, "Wait commands complete timeout!\n"); | |
2621 | return; | |
2622 | } | |
49159a5e | 2623 | |
a865ae14 XT |
2624 | dev_dbg(dev, "wait commands complete %dms\n", time); |
2625 | } | |
2626 | ||
488cf558 XC |
2627 | static ssize_t intr_conv_v3_hw_show(struct device *dev, |
2628 | struct device_attribute *attr, char *buf) | |
2629 | { | |
2630 | return scnprintf(buf, PAGE_SIZE, "%u\n", hisi_sas_intr_conv); | |
2631 | } | |
2632 | static DEVICE_ATTR_RO(intr_conv_v3_hw); | |
2633 | ||
37359798 XC |
2634 | static void config_intr_coal_v3_hw(struct hisi_hba *hisi_hba) |
2635 | { | |
2636 | /* config those registers between enable and disable PHYs */ | |
2637 | hisi_sas_stop_phys(hisi_hba); | |
2638 | ||
2639 | if (hisi_hba->intr_coal_ticks == 0 || | |
2640 | hisi_hba->intr_coal_count == 0) { | |
2641 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1); | |
2642 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1); | |
2643 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1); | |
2644 | } else { | |
2645 | hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x3); | |
2646 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, | |
2647 | hisi_hba->intr_coal_ticks); | |
2648 | hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, | |
2649 | hisi_hba->intr_coal_count); | |
2650 | } | |
2651 | phys_init_v3_hw(hisi_hba); | |
2652 | } | |
2653 | ||
2654 | static ssize_t intr_coal_ticks_v3_hw_show(struct device *dev, | |
2655 | struct device_attribute *attr, | |
2656 | char *buf) | |
2657 | { | |
2658 | struct Scsi_Host *shost = class_to_shost(dev); | |
2659 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2660 | ||
2661 | return scnprintf(buf, PAGE_SIZE, "%u\n", | |
2662 | hisi_hba->intr_coal_ticks); | |
2663 | } | |
2664 | ||
2665 | static ssize_t intr_coal_ticks_v3_hw_store(struct device *dev, | |
2666 | struct device_attribute *attr, | |
2667 | const char *buf, size_t count) | |
2668 | { | |
2669 | struct Scsi_Host *shost = class_to_shost(dev); | |
2670 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2671 | u32 intr_coal_ticks; | |
2672 | int ret; | |
2673 | ||
2674 | ret = kstrtou32(buf, 10, &intr_coal_ticks); | |
2675 | if (ret) { | |
2676 | dev_err(dev, "Input data of interrupt coalesce unmatch\n"); | |
2677 | return -EINVAL; | |
2678 | } | |
2679 | ||
2680 | if (intr_coal_ticks >= BIT(24)) { | |
2681 | dev_err(dev, "intr_coal_ticks must be less than 2^24!\n"); | |
2682 | return -EINVAL; | |
2683 | } | |
2684 | ||
2685 | hisi_hba->intr_coal_ticks = intr_coal_ticks; | |
2686 | ||
2687 | config_intr_coal_v3_hw(hisi_hba); | |
2688 | ||
2689 | return count; | |
2690 | } | |
2691 | static DEVICE_ATTR_RW(intr_coal_ticks_v3_hw); | |
2692 | ||
2693 | static ssize_t intr_coal_count_v3_hw_show(struct device *dev, | |
2694 | struct device_attribute | |
2695 | *attr, char *buf) | |
2696 | { | |
2697 | struct Scsi_Host *shost = class_to_shost(dev); | |
2698 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2699 | ||
2700 | return scnprintf(buf, PAGE_SIZE, "%u\n", | |
2701 | hisi_hba->intr_coal_count); | |
2702 | } | |
2703 | ||
2704 | static ssize_t intr_coal_count_v3_hw_store(struct device *dev, | |
2705 | struct device_attribute | |
2706 | *attr, const char *buf, size_t count) | |
2707 | { | |
2708 | struct Scsi_Host *shost = class_to_shost(dev); | |
2709 | struct hisi_hba *hisi_hba = shost_priv(shost); | |
2710 | u32 intr_coal_count; | |
2711 | int ret; | |
2712 | ||
2713 | ret = kstrtou32(buf, 10, &intr_coal_count); | |
2714 | if (ret) { | |
2715 | dev_err(dev, "Input data of interrupt coalesce unmatch\n"); | |
2716 | return -EINVAL; | |
2717 | } | |
2718 | ||
2719 | if (intr_coal_count >= BIT(8)) { | |
2720 | dev_err(dev, "intr_coal_count must be less than 2^8!\n"); | |
2721 | return -EINVAL; | |
2722 | } | |
2723 | ||
2724 | hisi_hba->intr_coal_count = intr_coal_count; | |
2725 | ||
2726 | config_intr_coal_v3_hw(hisi_hba); | |
2727 | ||
2728 | return count; | |
2729 | } | |
2730 | static DEVICE_ATTR_RW(intr_coal_count_v3_hw); | |
2731 | ||
735bcc77 | 2732 | static struct device_attribute *host_attrs_v3_hw[] = { |
c3566f9a | 2733 | &dev_attr_phy_event_threshold, |
488cf558 | 2734 | &dev_attr_intr_conv_v3_hw, |
37359798 XC |
2735 | &dev_attr_intr_coal_ticks_v3_hw, |
2736 | &dev_attr_intr_coal_count_v3_hw, | |
c3566f9a XC |
2737 | NULL |
2738 | }; | |
2739 | ||
61a6ebf3 LJ |
2740 | static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = { |
2741 | HISI_SAS_DEBUGFS_REG(PHY_CFG), | |
2742 | HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE), | |
2743 | HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE), | |
2744 | HISI_SAS_DEBUGFS_REG(PHY_CTRL), | |
2745 | HISI_SAS_DEBUGFS_REG(SL_CFG), | |
2746 | HISI_SAS_DEBUGFS_REG(AIP_LIMIT), | |
2747 | HISI_SAS_DEBUGFS_REG(SL_CONTROL), | |
2748 | HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS), | |
2749 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0), | |
2750 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1), | |
2751 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2), | |
2752 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3), | |
2753 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4), | |
2754 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5), | |
2755 | HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6), | |
2756 | HISI_SAS_DEBUGFS_REG(TXID_AUTO), | |
2757 | HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0), | |
2758 | HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H), | |
2759 | HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER), | |
2760 | HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE), | |
2761 | HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER), | |
2762 | HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG), | |
2763 | HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG), | |
2764 | HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG), | |
2765 | HISI_SAS_DEBUGFS_REG(CHL_INT0), | |
2766 | HISI_SAS_DEBUGFS_REG(CHL_INT1), | |
2767 | HISI_SAS_DEBUGFS_REG(CHL_INT2), | |
2768 | HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK), | |
2769 | HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK), | |
2770 | HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK), | |
2771 | HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME), | |
2772 | HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN), | |
2773 | HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER), | |
2774 | HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK), | |
2775 | HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK), | |
2776 | HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK), | |
2777 | HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK), | |
2778 | HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK), | |
2779 | HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK), | |
2780 | HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS), | |
2781 | HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS), | |
2782 | HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME), | |
2783 | HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST), | |
2784 | HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB), | |
2785 | HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW), | |
2786 | HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR), | |
2787 | HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR), | |
2788 | {} | |
2789 | }; | |
2790 | ||
eb1c2b72 | 2791 | static const struct hisi_sas_debugfs_reg debugfs_port_reg = { |
61a6ebf3 LJ |
2792 | .lu = debugfs_port_reg_lu, |
2793 | .count = 0x100, | |
49159a5e LJ |
2794 | .base_off = PORT_BASE, |
2795 | .read_port_reg = hisi_sas_phy_read32, | |
eb1c2b72 LJ |
2796 | }; |
2797 | ||
caefac19 LJ |
2798 | static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = { |
2799 | HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE), | |
2800 | HISI_SAS_DEBUGFS_REG(PHY_CONTEXT), | |
2801 | HISI_SAS_DEBUGFS_REG(PHY_STATE), | |
2802 | HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA), | |
2803 | HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE), | |
2804 | HISI_SAS_DEBUGFS_REG(ITCT_CLR), | |
2805 | HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO), | |
2806 | HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI), | |
2807 | HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO), | |
2808 | HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI), | |
2809 | HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG), | |
2810 | HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL), | |
2811 | HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL), | |
2812 | HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME), | |
2813 | HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE), | |
2814 | HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME), | |
2815 | HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME), | |
2816 | HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME), | |
2817 | HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME), | |
2818 | HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME), | |
2819 | HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN), | |
2820 | HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME), | |
2821 | HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2), | |
2822 | HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT), | |
2823 | HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE), | |
2824 | HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS), | |
2825 | HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS), | |
2826 | HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO), | |
2827 | HISI_SAS_DEBUGFS_REG(INT_COAL_EN), | |
2828 | HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME), | |
2829 | HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT), | |
2830 | HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME), | |
2831 | HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT), | |
2832 | HISI_SAS_DEBUGFS_REG(OQ_INT_SRC), | |
2833 | HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK), | |
2834 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1), | |
2835 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2), | |
2836 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3), | |
2837 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1), | |
2838 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2), | |
2839 | HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3), | |
2840 | HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK), | |
2841 | HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK), | |
2842 | HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK), | |
2843 | HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR), | |
2844 | HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK), | |
2845 | HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN), | |
2846 | HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT), | |
2847 | HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH), | |
2848 | HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR), | |
2849 | HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR), | |
2850 | HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG), | |
2851 | HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK), | |
2852 | HISI_SAS_DEBUGFS_REG(COMPL_Q_0_DEPTH), | |
2853 | HISI_SAS_DEBUGFS_REG(COMPL_Q_0_WR_PTR), | |
2854 | HISI_SAS_DEBUGFS_REG(COMPL_Q_0_RD_PTR), | |
2855 | HISI_SAS_DEBUGFS_REG(AWQOS_AWCACHE_CFG), | |
2856 | HISI_SAS_DEBUGFS_REG(ARQOS_ARCACHE_CFG), | |
2857 | HISI_SAS_DEBUGFS_REG(HILINK_ERR_DFX), | |
2858 | HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_0), | |
2859 | HISI_SAS_DEBUGFS_REG(SAS_GPIO_CFG_1), | |
2860 | HISI_SAS_DEBUGFS_REG(SAS_GPIO_TX_0_1), | |
2861 | HISI_SAS_DEBUGFS_REG(SAS_CFG_DRIVE_VLD), | |
2862 | {} | |
2863 | }; | |
2864 | ||
eb1c2b72 | 2865 | static const struct hisi_sas_debugfs_reg debugfs_global_reg = { |
caefac19 LJ |
2866 | .lu = debugfs_global_reg_lu, |
2867 | .count = 0x800, | |
49159a5e | 2868 | .read_global_reg = hisi_sas_read32, |
eb1c2b72 LJ |
2869 | }; |
2870 | ||
b0b3e429 LJ |
2871 | static const struct hisi_sas_debugfs_reg_lu debugfs_axi_reg_lu[] = { |
2872 | HISI_SAS_DEBUGFS_REG(AM_CFG_MAX_TRANS), | |
2873 | HISI_SAS_DEBUGFS_REG(AM_CFG_SINGLE_PORT_MAX_TRANS), | |
2874 | HISI_SAS_DEBUGFS_REG(AXI_CFG), | |
2875 | HISI_SAS_DEBUGFS_REG(AM_ROB_ECC_ERR_ADDR), | |
2876 | {} | |
2877 | }; | |
2878 | ||
2879 | static const struct hisi_sas_debugfs_reg debugfs_axi_reg = { | |
2880 | .lu = debugfs_axi_reg_lu, | |
2881 | .count = 0x61, | |
2882 | .base_off = AXI_MASTER_CFG_BASE, | |
2883 | .read_global_reg = hisi_sas_read32, | |
2884 | }; | |
2885 | ||
2886 | static const struct hisi_sas_debugfs_reg_lu debugfs_ras_reg_lu[] = { | |
2887 | HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1), | |
2888 | HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR0_MASK), | |
2889 | HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR1_MASK), | |
2890 | HISI_SAS_DEBUGFS_REG(CFG_SAS_RAS_INTR_MASK), | |
2891 | HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2), | |
2892 | HISI_SAS_DEBUGFS_REG(SAS_RAS_INTR2_MASK), | |
2893 | {} | |
2894 | }; | |
2895 | ||
2896 | static const struct hisi_sas_debugfs_reg debugfs_ras_reg = { | |
2897 | .lu = debugfs_ras_reg_lu, | |
2898 | .count = 0x10, | |
2899 | .base_off = RAS_BASE, | |
2900 | .read_global_reg = hisi_sas_read32, | |
2901 | }; | |
2902 | ||
49159a5e LJ |
2903 | static void debugfs_snapshot_prepare_v3_hw(struct hisi_hba *hisi_hba) |
2904 | { | |
49159a5e LJ |
2905 | set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); |
2906 | ||
2907 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0); | |
2908 | ||
4bc05809 | 2909 | wait_cmds_complete_timeout_v3_hw(hisi_hba, 100, 5000); |
49159a5e LJ |
2910 | |
2911 | hisi_sas_kill_tasklets(hisi_hba); | |
2912 | } | |
2913 | ||
2914 | static void debugfs_snapshot_restore_v3_hw(struct hisi_hba *hisi_hba) | |
2915 | { | |
2916 | hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, | |
2917 | (u32)((1ULL << hisi_hba->queue_count) - 1)); | |
2918 | ||
2919 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
2920 | } | |
2921 | ||
bbe0a7b3 LJ |
2922 | static void read_iost_itct_cache_v3_hw(struct hisi_hba *hisi_hba, |
2923 | enum hisi_sas_debugfs_cache_type type, | |
2924 | u32 *cache) | |
2925 | { | |
2926 | u32 cache_dw_size = HISI_SAS_IOST_ITCT_CACHE_DW_SZ * | |
2927 | HISI_SAS_IOST_ITCT_CACHE_NUM; | |
2928 | u32 *buf = cache; | |
2929 | u32 i, val; | |
2930 | ||
2931 | hisi_sas_write32(hisi_hba, TAB_RD_TYPE, type); | |
2932 | ||
2933 | for (i = 0; i < HISI_SAS_IOST_ITCT_CACHE_DW_SZ; i++) { | |
2934 | val = hisi_sas_read32(hisi_hba, TAB_DFX); | |
2935 | if (val == 0xffffffff) | |
2936 | break; | |
2937 | } | |
2938 | ||
2939 | if (val != 0xffffffff) { | |
2940 | pr_err("Issue occur when reading IOST/ITCT cache!\n"); | |
2941 | return; | |
2942 | } | |
2943 | ||
2944 | memset(buf, 0, cache_dw_size * 4); | |
2945 | buf[0] = val; | |
2946 | ||
2947 | for (i = 1; i < cache_dw_size; i++) | |
2948 | buf[i] = hisi_sas_read32(hisi_hba, TAB_DFX); | |
2949 | } | |
2950 | ||
97b151e7 XC |
2951 | static void hisi_sas_bist_test_prep_v3_hw(struct hisi_hba *hisi_hba) |
2952 | { | |
2953 | u32 reg_val; | |
2954 | int phy_id = hisi_hba->debugfs_bist_phy_no; | |
2955 | ||
2956 | /* disable PHY */ | |
2957 | hisi_sas_phy_enable(hisi_hba, phy_id, 0); | |
2958 | ||
2959 | /* disable ALOS */ | |
2960 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG); | |
2961 | reg_val |= CFG_ALOS_CHK_DISABLE_MSK; | |
2962 | hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val); | |
2963 | } | |
2964 | ||
2965 | static void hisi_sas_bist_test_restore_v3_hw(struct hisi_hba *hisi_hba) | |
2966 | { | |
2967 | u32 reg_val; | |
2968 | int phy_id = hisi_hba->debugfs_bist_phy_no; | |
2969 | ||
2970 | /* disable loopback */ | |
2971 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL); | |
2972 | reg_val &= ~(CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK | | |
2973 | CFG_BIST_TEST_MSK); | |
2974 | hisi_sas_phy_write32(hisi_hba, phy_id, SAS_PHY_BIST_CTRL, reg_val); | |
2975 | ||
2976 | /* enable ALOS */ | |
2977 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, SERDES_CFG); | |
2978 | reg_val &= ~CFG_ALOS_CHK_DISABLE_MSK; | |
2979 | hisi_sas_phy_write32(hisi_hba, phy_id, SERDES_CFG, reg_val); | |
2980 | ||
2981 | /* restore the linkrate */ | |
2982 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, PROG_PHY_LINK_RATE); | |
2983 | /* init OOB link rate as 1.5 Gbits */ | |
2984 | reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK; | |
2985 | reg_val |= (0x8 << CFG_PROG_PHY_LINK_RATE_OFF); | |
2986 | hisi_sas_phy_write32(hisi_hba, phy_id, PROG_PHY_LINK_RATE, reg_val); | |
2987 | ||
2988 | /* enable PHY */ | |
2989 | hisi_sas_phy_enable(hisi_hba, phy_id, 1); | |
2990 | } | |
2991 | ||
2992 | #define SAS_PHY_BIST_CODE_INIT 0x1 | |
2993 | #define SAS_PHY_BIST_CODE1_INIT 0X80 | |
2994 | static int debugfs_set_bist_v3_hw(struct hisi_hba *hisi_hba, bool enable) | |
2995 | { | |
2996 | u32 reg_val, mode_tmp; | |
2997 | u32 linkrate = hisi_hba->debugfs_bist_linkrate; | |
2998 | u32 phy_id = hisi_hba->debugfs_bist_phy_no; | |
2999 | u32 code_mode = hisi_hba->debugfs_bist_code_mode; | |
3000 | u32 path_mode = hisi_hba->debugfs_bist_mode; | |
3001 | struct device *dev = hisi_hba->dev; | |
3002 | ||
3003 | dev_info(dev, "BIST info:linkrate=%d phy_id=%d code_mode=%d path_mode=%d\n", | |
3004 | linkrate, phy_id, code_mode, path_mode); | |
3005 | mode_tmp = path_mode ? 2 : 1; | |
3006 | if (enable) { | |
3007 | /* some preparations before bist test */ | |
3008 | hisi_sas_bist_test_prep_v3_hw(hisi_hba); | |
3009 | ||
3010 | /* set linkrate of bit test*/ | |
3011 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, | |
3012 | PROG_PHY_LINK_RATE); | |
3013 | reg_val &= ~CFG_PROG_PHY_LINK_RATE_MSK; | |
3014 | reg_val |= (linkrate << CFG_PROG_PHY_LINK_RATE_OFF); | |
3015 | hisi_sas_phy_write32(hisi_hba, phy_id, | |
3016 | PROG_PHY_LINK_RATE, reg_val); | |
3017 | ||
3018 | /* set code mode of bit test */ | |
3019 | reg_val = hisi_sas_phy_read32(hisi_hba, phy_id, | |
3020 | SAS_PHY_BIST_CTRL); | |
3021 | reg_val &= ~(CFG_BIST_MODE_SEL_MSK | | |
3022 | CFG_LOOP_TEST_MODE_MSK | | |
3023 | CFG_RX_BIST_EN_MSK | | |
3024 | CFG_TX_BIST_EN_MSK | | |
3025 | CFG_BIST_TEST_MSK); | |
3026 | reg_val |= ((code_mode << CFG_BIST_MODE_SEL_OFF) | | |
3027 | (mode_tmp << CFG_LOOP_TEST_MODE_OFF) | | |
3028 | CFG_BIST_TEST_MSK); | |
3029 | hisi_sas_phy_write32(hisi_hba, phy_id, | |
3030 | SAS_PHY_BIST_CTRL, reg_val); | |
3031 | ||
97b151e7 XC |
3032 | /* set the bist init value */ |
3033 | hisi_sas_phy_write32(hisi_hba, phy_id, | |
3034 | SAS_PHY_BIST_CODE, | |
3035 | SAS_PHY_BIST_CODE_INIT); | |
3036 | hisi_sas_phy_write32(hisi_hba, phy_id, | |
3037 | SAS_PHY_BIST_CODE1, | |
3038 | SAS_PHY_BIST_CODE1_INIT); | |
3039 | ||
1dead632 XC |
3040 | mdelay(100); |
3041 | reg_val |= (CFG_RX_BIST_EN_MSK | CFG_TX_BIST_EN_MSK); | |
3042 | hisi_sas_phy_write32(hisi_hba, phy_id, | |
3043 | SAS_PHY_BIST_CTRL, reg_val); | |
3044 | ||
97b151e7 XC |
3045 | /* clear error bit */ |
3046 | mdelay(100); | |
3047 | hisi_sas_phy_read32(hisi_hba, phy_id, SAS_BIST_ERR_CNT); | |
3048 | } else { | |
3049 | /* disable bist test and recover it */ | |
3050 | hisi_hba->debugfs_bist_cnt += hisi_sas_phy_read32(hisi_hba, | |
3051 | phy_id, SAS_BIST_ERR_CNT); | |
3052 | hisi_sas_bist_test_restore_v3_hw(hisi_hba); | |
3053 | } | |
3054 | ||
3055 | return 0; | |
3056 | } | |
3057 | ||
235bfc7f XC |
3058 | static struct scsi_host_template sht_v3_hw = { |
3059 | .name = DRV_NAME, | |
3060 | .module = THIS_MODULE, | |
3061 | .queuecommand = sas_queuecommand, | |
3062 | .target_alloc = sas_target_alloc, | |
3063 | .slave_configure = hisi_sas_slave_configure, | |
3064 | .scan_finished = hisi_sas_scan_finished, | |
3065 | .scan_start = hisi_sas_scan_start, | |
3066 | .change_queue_depth = sas_change_queue_depth, | |
3067 | .bios_param = sas_bios_param, | |
235bfc7f | 3068 | .this_id = -1, |
6db831f4 | 3069 | .sg_tablesize = HISI_SAS_SGE_PAGE_CNT, |
b3cce125 | 3070 | .sg_prot_tablesize = HISI_SAS_SGE_PAGE_CNT, |
235bfc7f | 3071 | .max_sectors = SCSI_DEFAULT_MAX_SECTORS, |
235bfc7f XC |
3072 | .eh_device_reset_handler = sas_eh_device_reset_handler, |
3073 | .eh_target_reset_handler = sas_eh_target_reset_handler, | |
3074 | .target_destroy = sas_target_destroy, | |
3075 | .ioctl = sas_ioctl, | |
c3566f9a | 3076 | .shost_attrs = host_attrs_v3_hw, |
784b46b7 | 3077 | .tag_alloc_policy = BLK_TAG_ALLOC_RR, |
a97fa586 | 3078 | .host_reset = hisi_sas_host_reset, |
235bfc7f XC |
3079 | }; |
3080 | ||
e21fe3a5 | 3081 | static const struct hisi_sas_hw hisi_sas_v3_hw = { |
c94d8ca2 | 3082 | .hw_init = hisi_sas_v3_init, |
182e7222 | 3083 | .setup_itct = setup_itct_v3_hw, |
f771d3b0 | 3084 | .get_wideport_bitmap = get_wideport_bitmap_v3_hw, |
c94d8ca2 | 3085 | .complete_hdr_size = sizeof(struct hisi_sas_complete_v3_hdr), |
0258141a | 3086 | .clear_itct = clear_itct_v3_hw, |
569eddcf | 3087 | .sl_notify_ssp = sl_notify_ssp_v3_hw, |
a2204723 | 3088 | .prep_ssp = prep_ssp_v3_hw, |
fa913de2 | 3089 | .prep_smp = prep_smp_v3_hw, |
ce60689e | 3090 | .prep_stp = prep_ata_v3_hw, |
4de0ca69 | 3091 | .prep_abort = prep_abort_v3_hw, |
a2204723 | 3092 | .start_delivery = start_delivery_v3_hw, |
3975f605 | 3093 | .phys_init = phys_init_v3_hw, |
1eb8eeac | 3094 | .phy_start = start_phy_v3_hw, |
402cd9f0 XC |
3095 | .phy_disable = disable_phy_v3_hw, |
3096 | .phy_hard_reset = phy_hard_reset_v3_hw, | |
3097 | .phy_get_max_linkrate = phy_get_max_linkrate_v3_hw, | |
2400620c | 3098 | .phy_set_linkrate = phy_set_linkrate_v3_hw, |
d30ff263 | 3099 | .dereg_device = dereg_device_v3_hw, |
a25d0d3d XC |
3100 | .soft_reset = soft_reset_v3_hw, |
3101 | .get_phys_state = get_phys_state_v3_hw, | |
ffc8f149 | 3102 | .get_events = phy_get_events_v3_hw, |
428f1b34 | 3103 | .write_gpio = write_gpio_v3_hw, |
a865ae14 | 3104 | .wait_cmds_complete_timeout = wait_cmds_complete_timeout_v3_hw, |
b0b3e429 LJ |
3105 | .debugfs_reg_array[DEBUGFS_GLOBAL] = &debugfs_global_reg, |
3106 | .debugfs_reg_array[DEBUGFS_AXI] = &debugfs_axi_reg, | |
3107 | .debugfs_reg_array[DEBUGFS_RAS] = &debugfs_ras_reg, | |
eb1c2b72 | 3108 | .debugfs_reg_port = &debugfs_port_reg, |
49159a5e LJ |
3109 | .snapshot_prepare = debugfs_snapshot_prepare_v3_hw, |
3110 | .snapshot_restore = debugfs_snapshot_restore_v3_hw, | |
bbe0a7b3 | 3111 | .read_iost_itct_cache = read_iost_itct_cache_v3_hw, |
97b151e7 | 3112 | .set_bist = debugfs_set_bist_v3_hw, |
e21fe3a5 JG |
3113 | }; |
3114 | ||
3115 | static struct Scsi_Host * | |
3116 | hisi_sas_shost_alloc_pci(struct pci_dev *pdev) | |
3117 | { | |
3118 | struct Scsi_Host *shost; | |
3119 | struct hisi_hba *hisi_hba; | |
3120 | struct device *dev = &pdev->dev; | |
3121 | ||
235bfc7f | 3122 | shost = scsi_host_alloc(&sht_v3_hw, sizeof(*hisi_hba)); |
76aae5f6 JG |
3123 | if (!shost) { |
3124 | dev_err(dev, "shost alloc failed\n"); | |
3125 | return NULL; | |
3126 | } | |
e21fe3a5 JG |
3127 | hisi_hba = shost_priv(shost); |
3128 | ||
b4241f0f | 3129 | INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler); |
49159a5e | 3130 | INIT_WORK(&hisi_hba->debugfs_work, hisi_sas_debugfs_work_handler); |
e21fe3a5 JG |
3131 | hisi_hba->hw = &hisi_sas_v3_hw; |
3132 | hisi_hba->pci_dev = pdev; | |
3133 | hisi_hba->dev = dev; | |
3134 | hisi_hba->shost = shost; | |
3135 | SHOST_TO_SAS_HA(shost) = &hisi_hba->sha; | |
3136 | ||
d6a9000b XC |
3137 | if (prot_mask & ~HISI_SAS_PROT_MASK) |
3138 | dev_err(dev, "unsupported protection mask 0x%x, using default (0x0)\n", | |
3139 | prot_mask); | |
3140 | else | |
3141 | hisi_hba->prot_mask = prot_mask; | |
3142 | ||
e21fe3a5 JG |
3143 | if (hisi_sas_get_fw_info(hisi_hba) < 0) |
3144 | goto err_out; | |
3145 | ||
ae68b566 | 3146 | if (hisi_sas_alloc(hisi_hba)) { |
e21fe3a5 JG |
3147 | hisi_sas_free(hisi_hba); |
3148 | goto err_out; | |
3149 | } | |
3150 | ||
3151 | return shost; | |
3152 | err_out: | |
76aae5f6 | 3153 | scsi_host_put(shost); |
e21fe3a5 JG |
3154 | dev_err(dev, "shost alloc failed\n"); |
3155 | return NULL; | |
3156 | } | |
3157 | ||
92f61e3b JG |
3158 | static int |
3159 | hisi_sas_v3_probe(struct pci_dev *pdev, const struct pci_device_id *id) | |
3160 | { | |
e21fe3a5 JG |
3161 | struct Scsi_Host *shost; |
3162 | struct hisi_hba *hisi_hba; | |
3163 | struct device *dev = &pdev->dev; | |
3164 | struct asd_sas_phy **arr_phy; | |
3165 | struct asd_sas_port **arr_port; | |
3166 | struct sas_ha_struct *sha; | |
3167 | int rc, phy_nr, port_nr, i; | |
3168 | ||
3169 | rc = pci_enable_device(pdev); | |
3170 | if (rc) | |
3171 | goto err_out; | |
3172 | ||
3173 | pci_set_master(pdev); | |
3174 | ||
3175 | rc = pci_request_regions(pdev, DRV_NAME); | |
3176 | if (rc) | |
3177 | goto err_out_disable_device; | |
3178 | ||
d9a00459 HR |
3179 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
3180 | if (rc) | |
3181 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); | |
3182 | if (rc) { | |
e4db40e7 | 3183 | dev_err(dev, "No usable DMA addressing method\n"); |
d9a00459 | 3184 | rc = -ENODEV; |
e4db40e7 | 3185 | goto err_out_regions; |
e21fe3a5 JG |
3186 | } |
3187 | ||
3188 | shost = hisi_sas_shost_alloc_pci(pdev); | |
3189 | if (!shost) { | |
3190 | rc = -ENOMEM; | |
3191 | goto err_out_regions; | |
3192 | } | |
3193 | ||
3194 | sha = SHOST_TO_SAS_HA(shost); | |
3195 | hisi_hba = shost_priv(shost); | |
3196 | dev_set_drvdata(dev, sha); | |
3197 | ||
3198 | hisi_hba->regs = pcim_iomap(pdev, 5, 0); | |
3199 | if (!hisi_hba->regs) { | |
01d4e3a2 | 3200 | dev_err(dev, "cannot map register\n"); |
e21fe3a5 JG |
3201 | rc = -ENOMEM; |
3202 | goto err_out_ha; | |
3203 | } | |
3204 | ||
3205 | phy_nr = port_nr = hisi_hba->n_phy; | |
3206 | ||
3207 | arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL); | |
3208 | arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL); | |
3209 | if (!arr_phy || !arr_port) { | |
3210 | rc = -ENOMEM; | |
3211 | goto err_out_ha; | |
3212 | } | |
3213 | ||
3214 | sha->sas_phy = arr_phy; | |
3215 | sha->sas_port = arr_port; | |
3216 | sha->core.shost = shost; | |
3217 | sha->lldd_ha = hisi_hba; | |
3218 | ||
3219 | shost->transportt = hisi_sas_stt; | |
3220 | shost->max_id = HISI_SAS_MAX_DEVICES; | |
3221 | shost->max_lun = ~0; | |
3222 | shost->max_channel = 1; | |
3223 | shost->max_cmd_len = 16; | |
93352abc JG |
3224 | shost->can_queue = HISI_SAS_UNRESERVED_IPTT; |
3225 | shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT; | |
e21fe3a5 JG |
3226 | |
3227 | sha->sas_ha_name = DRV_NAME; | |
3228 | sha->dev = dev; | |
3229 | sha->lldd_module = THIS_MODULE; | |
3230 | sha->sas_addr = &hisi_hba->sas_addr[0]; | |
3231 | sha->num_phys = hisi_hba->n_phy; | |
e21fe3a5 JG |
3232 | |
3233 | for (i = 0; i < hisi_hba->n_phy; i++) { | |
3234 | sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy; | |
3235 | sha->sas_port[i] = &hisi_hba->port[i].sas_port; | |
3236 | } | |
3237 | ||
7bb25a89 JG |
3238 | if (hisi_hba->prot_mask) { |
3239 | dev_info(dev, "Registering for DIF/DIX prot_mask=0x%x\n", | |
3240 | prot_mask); | |
3241 | scsi_host_set_prot(hisi_hba->shost, prot_mask); | |
92fff53b LT |
3242 | if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK) |
3243 | scsi_host_set_guard(hisi_hba->shost, | |
3244 | SHOST_DIX_GUARD_CRC); | |
7bb25a89 JG |
3245 | } |
3246 | ||
ef63464b LJ |
3247 | if (hisi_sas_debugfs_enable) |
3248 | hisi_sas_debugfs_init(hisi_hba); | |
3249 | ||
e21fe3a5 JG |
3250 | rc = scsi_add_host(shost, dev); |
3251 | if (rc) | |
3252 | goto err_out_ha; | |
3253 | ||
3254 | rc = sas_register_ha(sha); | |
3255 | if (rc) | |
3256 | goto err_out_register_ha; | |
3257 | ||
3258 | rc = hisi_hba->hw->hw_init(hisi_hba); | |
3259 | if (rc) | |
3260 | goto err_out_register_ha; | |
3261 | ||
3262 | scsi_scan_host(shost); | |
3263 | ||
92f61e3b | 3264 | return 0; |
e21fe3a5 JG |
3265 | |
3266 | err_out_register_ha: | |
3267 | scsi_remove_host(shost); | |
3268 | err_out_ha: | |
916b8583 | 3269 | hisi_sas_debugfs_exit(hisi_hba); |
76aae5f6 | 3270 | scsi_host_put(shost); |
e21fe3a5 JG |
3271 | err_out_regions: |
3272 | pci_release_regions(pdev); | |
3273 | err_out_disable_device: | |
3274 | pci_disable_device(pdev); | |
3275 | err_out: | |
3276 | return rc; | |
92f61e3b JG |
3277 | } |
3278 | ||
54edeee1 XC |
3279 | static void |
3280 | hisi_sas_v3_destroy_irqs(struct pci_dev *pdev, struct hisi_hba *hisi_hba) | |
3281 | { | |
60b4a5ee XC |
3282 | int i; |
3283 | ||
54edeee1 XC |
3284 | free_irq(pci_irq_vector(pdev, 1), hisi_hba); |
3285 | free_irq(pci_irq_vector(pdev, 2), hisi_hba); | |
fa231408 | 3286 | free_irq(pci_irq_vector(pdev, 11), hisi_hba); |
795f25a3 | 3287 | for (i = 0; i < hisi_hba->cq_nvecs; i++) { |
60b4a5ee | 3288 | struct hisi_sas_cq *cq = &hisi_hba->cq[i]; |
488cf558 | 3289 | int nr = hisi_sas_intr_conv ? 16 : 16 + i; |
60b4a5ee | 3290 | |
488cf558 | 3291 | free_irq(pci_irq_vector(pdev, nr), cq); |
60b4a5ee | 3292 | } |
54edeee1 XC |
3293 | pci_free_irq_vectors(pdev); |
3294 | } | |
3295 | ||
92f61e3b JG |
3296 | static void hisi_sas_v3_remove(struct pci_dev *pdev) |
3297 | { | |
e21fe3a5 JG |
3298 | struct device *dev = &pdev->dev; |
3299 | struct sas_ha_struct *sha = dev_get_drvdata(dev); | |
3300 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
76aae5f6 | 3301 | struct Scsi_Host *shost = sha->core.shost; |
e21fe3a5 | 3302 | |
ef63464b LJ |
3303 | hisi_sas_debugfs_exit(hisi_hba); |
3304 | ||
5df41af4 XC |
3305 | if (timer_pending(&hisi_hba->timer)) |
3306 | del_timer(&hisi_hba->timer); | |
3307 | ||
e21fe3a5 JG |
3308 | sas_unregister_ha(sha); |
3309 | sas_remove_host(sha->core.shost); | |
3310 | ||
54edeee1 | 3311 | hisi_sas_v3_destroy_irqs(pdev, hisi_hba); |
571295f8 | 3312 | hisi_sas_kill_tasklets(hisi_hba); |
e21fe3a5 JG |
3313 | pci_release_regions(pdev); |
3314 | pci_disable_device(pdev); | |
76aae5f6 JG |
3315 | hisi_sas_free(hisi_hba); |
3316 | scsi_host_put(shost); | |
92f61e3b JG |
3317 | } |
3318 | ||
e5ea4801 XT |
3319 | static void hisi_sas_reset_prepare_v3_hw(struct pci_dev *pdev) |
3320 | { | |
3321 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
3322 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
3323 | struct device *dev = hisi_hba->dev; | |
3324 | int rc; | |
3325 | ||
3326 | dev_info(dev, "FLR prepare\n"); | |
3327 | set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
3328 | hisi_sas_controller_reset_prepare(hisi_hba); | |
3329 | ||
3330 | rc = disable_host_v3_hw(hisi_hba); | |
3331 | if (rc) | |
3332 | dev_err(dev, "FLR: disable host failed rc=%d\n", rc); | |
3333 | } | |
3334 | ||
3335 | static void hisi_sas_reset_done_v3_hw(struct pci_dev *pdev) | |
3336 | { | |
3337 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
3338 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
3339 | struct device *dev = hisi_hba->dev; | |
3340 | int rc; | |
3341 | ||
3342 | hisi_sas_init_mem(hisi_hba); | |
3343 | ||
3344 | rc = hw_init_v3_hw(hisi_hba); | |
3345 | if (rc) { | |
3346 | dev_err(dev, "FLR: hw init failed rc=%d\n", rc); | |
3347 | return; | |
3348 | } | |
3349 | ||
3350 | hisi_sas_controller_reset_done(hisi_hba); | |
3351 | dev_info(dev, "FLR done\n"); | |
3352 | } | |
3353 | ||
92f61e3b JG |
3354 | enum { |
3355 | /* instances of the controller */ | |
3356 | hip08, | |
3357 | }; | |
3358 | ||
4d0951ee XC |
3359 | static int hisi_sas_v3_suspend(struct pci_dev *pdev, pm_message_t state) |
3360 | { | |
3361 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
3362 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
3363 | struct device *dev = hisi_hba->dev; | |
3364 | struct Scsi_Host *shost = hisi_hba->shost; | |
735bcc77 | 3365 | pci_power_t device_state; |
4d0951ee | 3366 | int rc; |
4d0951ee XC |
3367 | |
3368 | if (!pdev->pm_cap) { | |
3369 | dev_err(dev, "PCI PM not supported\n"); | |
3370 | return -ENODEV; | |
3371 | } | |
3372 | ||
214e702d XT |
3373 | if (test_and_set_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags)) |
3374 | return -1; | |
3375 | ||
4d0951ee XC |
3376 | scsi_block_requests(shost); |
3377 | set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
3378 | flush_workqueue(hisi_hba->wq); | |
4d0951ee | 3379 | |
e8ce775e | 3380 | rc = disable_host_v3_hw(hisi_hba); |
4d0951ee | 3381 | if (rc) { |
e8ce775e | 3382 | dev_err(dev, "PM suspend: disable host failed rc=%d\n", rc); |
4d0951ee XC |
3383 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); |
3384 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
3385 | scsi_unblock_requests(shost); | |
3386 | return rc; | |
3387 | } | |
3388 | ||
3389 | hisi_sas_init_mem(hisi_hba); | |
3390 | ||
3391 | device_state = pci_choose_state(pdev, state); | |
3392 | dev_warn(dev, "entering operating state [D%d]\n", | |
3393 | device_state); | |
3394 | pci_save_state(pdev); | |
3395 | pci_disable_device(pdev); | |
3396 | pci_set_power_state(pdev, device_state); | |
3397 | ||
4d0951ee | 3398 | hisi_sas_release_tasks(hisi_hba); |
4d0951ee XC |
3399 | |
3400 | sas_suspend_ha(sha); | |
3401 | return 0; | |
3402 | } | |
3403 | ||
3404 | static int hisi_sas_v3_resume(struct pci_dev *pdev) | |
3405 | { | |
3406 | struct sas_ha_struct *sha = pci_get_drvdata(pdev); | |
3407 | struct hisi_hba *hisi_hba = sha->lldd_ha; | |
3408 | struct Scsi_Host *shost = hisi_hba->shost; | |
3409 | struct device *dev = hisi_hba->dev; | |
3410 | unsigned int rc; | |
735bcc77 | 3411 | pci_power_t device_state = pdev->current_state; |
4d0951ee XC |
3412 | |
3413 | dev_warn(dev, "resuming from operating state [D%d]\n", | |
01d4e3a2 | 3414 | device_state); |
4d0951ee XC |
3415 | pci_set_power_state(pdev, PCI_D0); |
3416 | pci_enable_wake(pdev, PCI_D0, 0); | |
3417 | pci_restore_state(pdev); | |
3418 | rc = pci_enable_device(pdev); | |
73a4925d | 3419 | if (rc) { |
4d0951ee | 3420 | dev_err(dev, "enable device failed during resume (%d)\n", rc); |
73a4925d XC |
3421 | return rc; |
3422 | } | |
4d0951ee XC |
3423 | |
3424 | pci_set_master(pdev); | |
3425 | scsi_unblock_requests(shost); | |
3426 | clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags); | |
3427 | ||
3428 | sas_prep_resume_ha(sha); | |
73a4925d XC |
3429 | rc = hw_init_v3_hw(hisi_hba); |
3430 | if (rc) { | |
3431 | scsi_remove_host(shost); | |
3432 | pci_disable_device(pdev); | |
3433 | } | |
4d0951ee XC |
3434 | hisi_hba->hw->phys_init(hisi_hba); |
3435 | sas_resume_ha(sha); | |
3436 | clear_bit(HISI_SAS_RESET_BIT, &hisi_hba->flags); | |
3437 | ||
3438 | return 0; | |
3439 | } | |
3440 | ||
92f61e3b JG |
3441 | static const struct pci_device_id sas_v3_pci_table[] = { |
3442 | { PCI_VDEVICE(HUAWEI, 0xa230), hip08 }, | |
3443 | {} | |
3444 | }; | |
40ec66b1 | 3445 | MODULE_DEVICE_TABLE(pci, sas_v3_pci_table); |
92f61e3b | 3446 | |
1aaf81e0 | 3447 | static const struct pci_error_handlers hisi_sas_err_handler = { |
e5ea4801 XT |
3448 | .reset_prepare = hisi_sas_reset_prepare_v3_hw, |
3449 | .reset_done = hisi_sas_reset_done_v3_hw, | |
1aaf81e0 XT |
3450 | }; |
3451 | ||
92f61e3b JG |
3452 | static struct pci_driver sas_v3_pci_driver = { |
3453 | .name = DRV_NAME, | |
3454 | .id_table = sas_v3_pci_table, | |
3455 | .probe = hisi_sas_v3_probe, | |
3456 | .remove = hisi_sas_v3_remove, | |
4d0951ee XC |
3457 | .suspend = hisi_sas_v3_suspend, |
3458 | .resume = hisi_sas_v3_resume, | |
1aaf81e0 | 3459 | .err_handler = &hisi_sas_err_handler, |
92f61e3b JG |
3460 | }; |
3461 | ||
3462 | module_pci_driver(sas_v3_pci_driver); | |
488cf558 | 3463 | module_param_named(intr_conv, hisi_sas_intr_conv, bool, 0444); |
92f61e3b | 3464 | |
92f61e3b JG |
3465 | MODULE_LICENSE("GPL"); |
3466 | MODULE_AUTHOR("John Garry <john.garry@huawei.com>"); | |
3467 | MODULE_DESCRIPTION("HISILICON SAS controller v3 hw driver based on pci device"); | |
40ec66b1 | 3468 | MODULE_ALIAS("pci:" DRV_NAME); |