]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/hpsa.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hpsa: correct ioaccel2 error procecssing.
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
94c7bc31 3 * Copyright 2016 Microsemi Corporation
1358f6dc
DB		 4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
94c7bc31 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
edd16368
SC		 17 *
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <linux/pci.h>
e5a44df8 24#include <linux/pci-aspm.h>
edd16368
SC		 25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/fs.h>
29#include <linux/timer.h>
edd16368
SC		 30#include <linux/init.h>
31#include <linux/spinlock.h>
edd16368
SC		 32#include <linux/compat.h>
33#include <linux/blktrace_api.h>
34#include <linux/uaccess.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/completion.h>
38#include <linux/moduleparam.h>
39#include <scsi/scsi.h>
40#include <scsi/scsi_cmnd.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_host.h>
667e23d4 43#include <scsi/scsi_tcq.h>
9437ac43 44#include <scsi/scsi_eh.h>
d04e62b9 45#include <scsi/scsi_transport_sas.h>
73153fe5 46#include <scsi/scsi_dbg.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
ec2c3aa9
DB		 59/*
60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
61 * with an optional trailing '-' followed by a byte value (0-255).
62 */
63#define HPSA_DRIVER_VERSION "3.4.14-0"
edd16368 64#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 65#define HPSA "hpsa"
edd16368 66
007e7aa9
RE		 67/* How long to wait for CISS doorbell communication */
68#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
69#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
70#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
71#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 72#define MAX_IOCTL_CONFIG_WAIT 1000
73
74/*define how many times we will try a command because of bus resets */
75#define MAX_CMD_RETRIES 3
76
77/* Embedded module documentation macros - see modules.h */
78MODULE_AUTHOR("Hewlett-Packard Company");
79MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
80 HPSA_DRIVER_VERSION);
81MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
82MODULE_VERSION(HPSA_DRIVER_VERSION);
83MODULE_LICENSE("GPL");
84
85static int hpsa_allow_any;
86module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(hpsa_allow_any,
88 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 89static int hpsa_simple_mode;
90module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
91MODULE_PARM_DESC(hpsa_simple_mode,
92 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 93
94/* define the PCI info for the cards we can control */
95static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
135 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
141 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
145 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
146 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 147 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 148 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 149 {0,}
150};
151
152MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
153
154/* board_id = Subsystem Device ID & Vendor ID
155 * product = Marketing Name for the board
156 * access = Address of the struct of function pointers
157 */
158static struct board_type products[] = {
edd16368
SC		 159 {0x3241103C, "Smart Array P212", &SA5_access},
160 {0x3243103C, "Smart Array P410", &SA5_access},
161 {0x3245103C, "Smart Array P410i", &SA5_access},
162 {0x3247103C, "Smart Array P411", &SA5_access},
163 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 164 {0x324A103C, "Smart Array P712m", &SA5_access},
165 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 166 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 167 {0x3350103C, "Smart Array P222", &SA5_access},
168 {0x3351103C, "Smart Array P420", &SA5_access},
169 {0x3352103C, "Smart Array P421", &SA5_access},
170 {0x3353103C, "Smart Array P822", &SA5_access},
171 {0x3354103C, "Smart Array P420i", &SA5_access},
172 {0x3355103C, "Smart Array P220i", &SA5_access},
173 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 174 {0x1921103C, "Smart Array P830i", &SA5_access},
175 {0x1922103C, "Smart Array P430", &SA5_access},
176 {0x1923103C, "Smart Array P431", &SA5_access},
177 {0x1924103C, "Smart Array P830", &SA5_access},
178 {0x1926103C, "Smart Array P731m", &SA5_access},
179 {0x1928103C, "Smart Array P230i", &SA5_access},
180 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 181 {0x21BD103C, "Smart Array P244br", &SA5_access},
182 {0x21BE103C, "Smart Array P741m", &SA5_access},
183 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
184 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 185 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 186 {0x21C2103C, "Smart Array P440", &SA5_access},
187 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 188 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21C5103C, "Smart Array P841", &SA5_access},
190 {0x21C6103C, "Smart HBA H244br", &SA5_access},
191 {0x21C7103C, "Smart HBA H240", &SA5_access},
192 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 193 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 194 {0x21CA103C, "Smart Array P246br", &SA5_access},
195 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 196 {0x21CC103C, "Smart Array", &SA5_access},
197 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 198 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 199 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 200 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
201 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
202 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
203 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
204 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 205 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
206 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
207 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
208 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
209 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 210 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
211};
212
d04e62b9
KB		 213static struct scsi_transport_template *hpsa_sas_transport_template;
214static int hpsa_add_sas_host(struct ctlr_info *h);
215static void hpsa_delete_sas_host(struct ctlr_info *h);
216static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
217 struct hpsa_scsi_dev_t *device);
218static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
219static struct hpsa_scsi_dev_t
220 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
221 struct sas_rphy *rphy);
222
a58e7e53
WS		 223#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
224static const struct scsi_cmnd hpsa_cmd_busy;
225#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
226static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 227static int number_of_controllers;
228
10f66018
SC		 229static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
230static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 231static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 232
233#ifdef CONFIG_COMPAT
42a91641
DB		 234static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
235 void __user *arg);
edd16368
SC		 236#endif
237
238static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 239static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 240static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
241static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
242 struct scsi_cmnd *scmd);
a2dac136 243static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 244 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 245 int cmd_type);
2c143342 246static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 247#define VPD_PAGE (1 << 8)
b48d9804 248#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 249
f281233d 250static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 251static void hpsa_scan_start(struct Scsi_Host *);
252static int hpsa_scan_finished(struct Scsi_Host *sh,
253 unsigned long elapsed_time);
7c0a0229 254static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 255
256static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 257static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 258static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 259static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 260static void hpsa_slave_destroy(struct scsi_device *sdev);
261
8aa60681 262static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 263static int check_for_unit_attention(struct ctlr_info *h,
264 struct CommandList *c);
265static void check_ioctl_unit_attention(struct ctlr_info *h,
266 struct CommandList *c);
303932fd
DB		 267/* performant mode helper functions */
268static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 269 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 270static void hpsa_free_performant_mode(struct ctlr_info *h);
271static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 272static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 273static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
274 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
275 u64 *cfg_offset);
276static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
277 unsigned long *memory_bar);
278static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
279static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
280 int wait_for_ready);
75167d2c 281static inline void finish_cmd(struct CommandList *c);
c706a795 282static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 283#define BOARD_NOT_READY 0
284#define BOARD_READY 1
23100dd9 285static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 286static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 287static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 289 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 290static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 291static u32 lockup_detected(struct ctlr_info *h);
292static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 293static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 294static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
295 struct ReportExtendedLUNdata *buf, int bufsize);
34592254 296static int hpsa_luns_changed(struct ctlr_info *h);
edd16368 297
edd16368
SC		 298static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
299{
300 unsigned long *priv = shost_priv(sdev->host);
301 return (struct ctlr_info *) *priv;
302}
303
a23513e8
SC		 304static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
305{
306 unsigned long *priv = shost_priv(sh);
307 return (struct ctlr_info *) *priv;
308}
309
a58e7e53
WS		 310static inline bool hpsa_is_cmd_idle(struct CommandList *c)
311{
312 return c->scsi_cmd == SCSI_CMD_IDLE;
313}
314
d604f533
WS		 315static inline bool hpsa_is_pending_event(struct CommandList *c)
316{
317 return c->abort_pending || c->reset_pending;
318}
319
9437ac43
SC		 320/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
321static void decode_sense_data(const u8 *sense_data, int sense_data_len,
322 u8 *sense_key, u8 *asc, u8 *ascq)
323{
324 struct scsi_sense_hdr sshdr;
325 bool rc;
326
327 *sense_key = -1;
328 *asc = -1;
329 *ascq = -1;
330
331 if (sense_data_len < 1)
332 return;
333
334 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
335 if (rc) {
336 *sense_key = sshdr.sense_key;
337 *asc = sshdr.asc;
338 *ascq = sshdr.ascq;
339 }
340}
341
edd16368
SC		 342static int check_for_unit_attention(struct ctlr_info *h,
343 struct CommandList *c)
344{
9437ac43
SC		 345 u8 sense_key, asc, ascq;
346 int sense_len;
347
348 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
349 sense_len = sizeof(c->err_info->SenseInfo);
350 else
351 sense_len = c->err_info->SenseLen;
352
353 decode_sense_data(c->err_info->SenseInfo, sense_len,
354 &sense_key, &asc, &ascq);
81c27557 355 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 356 return 0;
357
9437ac43 358 switch (asc) {
edd16368 359 case STATE_CHANGED:
9437ac43 360 dev_warn(&h->pdev->dev,
2946e82b
RE		 361 "%s: a state change detected, command retried\n",
362 h->devname);
edd16368
SC		 363 break;
364 case LUN_FAILED:
7f73695a 365 dev_warn(&h->pdev->dev,
2946e82b 366 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 367 break;
368 case REPORT_LUNS_CHANGED:
7f73695a 369 dev_warn(&h->pdev->dev,
2946e82b 370 "%s: report LUN data changed\n", h->devname);
edd16368 371 /*
4f4eb9f1
ST		 372 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
373 * target (array) devices.
edd16368
SC		 374 */
375 break;
376 case POWER_OR_RESET:
2946e82b
RE		 377 dev_warn(&h->pdev->dev,
378 "%s: a power on or device reset detected\n",
379 h->devname);
edd16368
SC		 380 break;
381 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 382 dev_warn(&h->pdev->dev,
383 "%s: unit attention cleared by another initiator\n",
384 h->devname);
edd16368
SC		 385 break;
386 default:
2946e82b
RE		 387 dev_warn(&h->pdev->dev,
388 "%s: unknown unit attention detected\n",
389 h->devname);
edd16368
SC		 390 break;
391 }
392 return 1;
393}
394
852af20a
MB		 395static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
396{
397 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
398 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
399 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
400 return 0;
401 dev_warn(&h->pdev->dev, HPSA "device busy");
402 return 1;
403}
404
e985c58f
SC		 405static u32 lockup_detected(struct ctlr_info *h);
406static ssize_t host_show_lockup_detected(struct device *dev,
407 struct device_attribute *attr, char *buf)
408{
409 int ld;
410 struct ctlr_info *h;
411 struct Scsi_Host *shost = class_to_shost(dev);
412
413 h = shost_to_hba(shost);
414 ld = lockup_detected(h);
415
416 return sprintf(buf, "ld=%d\n", ld);
417}
418
da0697bd
ST		 419static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
420 struct device_attribute *attr,
421 const char *buf, size_t count)
422{
423 int status, len;
424 struct ctlr_info *h;
425 struct Scsi_Host *shost = class_to_shost(dev);
426 char tmpbuf[10];
427
428 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
429 return -EACCES;
430 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
431 strncpy(tmpbuf, buf, len);
432 tmpbuf[len] = '\0';
433 if (sscanf(tmpbuf, "%d", &status) != 1)
434 return -EINVAL;
435 h = shost_to_hba(shost);
436 h->acciopath_status = !!status;
437 dev_warn(&h->pdev->dev,
438 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
439 h->acciopath_status ? "enabled" : "disabled");
440 return count;
441}
442
2ba8bfc8
SC		 443static ssize_t host_store_raid_offload_debug(struct device *dev,
444 struct device_attribute *attr,
445 const char *buf, size_t count)
446{
447 int debug_level, len;
448 struct ctlr_info *h;
449 struct Scsi_Host *shost = class_to_shost(dev);
450 char tmpbuf[10];
451
452 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
453 return -EACCES;
454 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
455 strncpy(tmpbuf, buf, len);
456 tmpbuf[len] = '\0';
457 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
458 return -EINVAL;
459 if (debug_level < 0)
460 debug_level = 0;
461 h = shost_to_hba(shost);
462 h->raid_offload_debug = debug_level;
463 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
464 h->raid_offload_debug);
465 return count;
466}
467
edd16368
SC		 468static ssize_t host_store_rescan(struct device *dev,
469 struct device_attribute *attr,
470 const char *buf, size_t count)
471{
472 struct ctlr_info *h;
473 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 474 h = shost_to_hba(shost);
31468401 475 hpsa_scan_start(h->scsi_host);
edd16368
SC		 476 return count;
477}
478
d28ce020
SC		 479static ssize_t host_show_firmware_revision(struct device *dev,
480 struct device_attribute *attr, char *buf)
481{
482 struct ctlr_info *h;
483 struct Scsi_Host *shost = class_to_shost(dev);
484 unsigned char *fwrev;
485
486 h = shost_to_hba(shost);
487 if (!h->hba_inquiry_data)
488 return 0;
489 fwrev = &h->hba_inquiry_data[32];
490 return snprintf(buf, 20, "%c%c%c%c\n",
491 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
492}
493
94a13649
SC		 494static ssize_t host_show_commands_outstanding(struct device *dev,
495 struct device_attribute *attr, char *buf)
496{
497 struct Scsi_Host *shost = class_to_shost(dev);
498 struct ctlr_info *h = shost_to_hba(shost);
499
0cbf768e
SC		 500 return snprintf(buf, 20, "%d\n",
501 atomic_read(&h->commands_outstanding));
94a13649
SC		 502}
503
745a7a25
SC		 504static ssize_t host_show_transport_mode(struct device *dev,
505 struct device_attribute *attr, char *buf)
506{
507 struct ctlr_info *h;
508 struct Scsi_Host *shost = class_to_shost(dev);
509
510 h = shost_to_hba(shost);
511 return snprintf(buf, 20, "%s\n",
960a30e7 512 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 513 "performant" : "simple");
514}
515
da0697bd
ST		 516static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
517 struct device_attribute *attr, char *buf)
518{
519 struct ctlr_info *h;
520 struct Scsi_Host *shost = class_to_shost(dev);
521
522 h = shost_to_hba(shost);
523 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
524 (h->acciopath_status == 1) ? "enabled" : "disabled");
525}
526
46380786 527/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 528static u32 unresettable_controller[] = {
529 0x324a103C, /* Smart Array P712m */
9b5c48c2 530 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 531 0x3223103C, /* Smart Array P800 */
532 0x3234103C, /* Smart Array P400 */
533 0x3235103C, /* Smart Array P400i */
534 0x3211103C, /* Smart Array E200i */
535 0x3212103C, /* Smart Array E200 */
536 0x3213103C, /* Smart Array E200i */
537 0x3214103C, /* Smart Array E200i */
538 0x3215103C, /* Smart Array E200i */
539 0x3237103C, /* Smart Array E500 */
540 0x323D103C, /* Smart Array P700m */
7af0abbc 541 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 542 0x409C0E11, /* Smart Array 6400 */
543 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 544 0x40700E11, /* Smart Array 5300 */
545 0x40820E11, /* Smart Array 532 */
546 0x40830E11, /* Smart Array 5312 */
547 0x409A0E11, /* Smart Array 641 */
548 0x409B0E11, /* Smart Array 642 */
549 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 550};
551
46380786
SC		 552/* List of controllers which cannot even be soft reset */
553static u32 soft_unresettable_controller[] = {
7af0abbc 554 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 555 0x40700E11, /* Smart Array 5300 */
556 0x40820E11, /* Smart Array 532 */
557 0x40830E11, /* Smart Array 5312 */
558 0x409A0E11, /* Smart Array 641 */
559 0x409B0E11, /* Smart Array 642 */
560 0x40910E11, /* Smart Array 6i */
46380786
SC		 561 /* Exclude 640x boards. These are two pci devices in one slot
562 * which share a battery backed cache module. One controls the
563 * cache, the other accesses the cache through the one that controls
564 * it. If we reset the one controlling the cache, the other will
565 * likely not be happy. Just forbid resetting this conjoined mess.
566 * The 640x isn't really supported by hpsa anyway.
567 */
568 0x409C0E11, /* Smart Array 6400 */
569 0x409D0E11, /* Smart Array 6400 EM */
570};
571
9b5c48c2
SC		 572static u32 needs_abort_tags_swizzled[] = {
573 0x323D103C, /* Smart Array P700m */
574 0x324a103C, /* Smart Array P712m */
575 0x324b103C, /* SmartArray P711m */
576};
577
578static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 579{
580 int i;
581
9b5c48c2
SC		 582 for (i = 0; i < nelems; i++)
583 if (a[i] == board_id)
584 return 1;
585 return 0;
46380786
SC		 586}
587
9b5c48c2 588static int ctlr_is_hard_resettable(u32 board_id)
46380786 589{
9b5c48c2
SC		 590 return !board_id_in_array(unresettable_controller,
591 ARRAY_SIZE(unresettable_controller), board_id);
592}
46380786 593
9b5c48c2
SC		 594static int ctlr_is_soft_resettable(u32 board_id)
595{
596 return !board_id_in_array(soft_unresettable_controller,
597 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 598}
599
46380786
SC		 600static int ctlr_is_resettable(u32 board_id)
601{
602 return ctlr_is_hard_resettable(board_id) ||
603 ctlr_is_soft_resettable(board_id);
604}
605
9b5c48c2
SC		 606static int ctlr_needs_abort_tags_swizzled(u32 board_id)
607{
608 return board_id_in_array(needs_abort_tags_swizzled,
609 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
610}
611
941b1cda
SC		 612static ssize_t host_show_resettable(struct device *dev,
613 struct device_attribute *attr, char *buf)
614{
615 struct ctlr_info *h;
616 struct Scsi_Host *shost = class_to_shost(dev);
617
618 h = shost_to_hba(shost);
46380786 619 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 620}
621
edd16368
SC		 622static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
623{
624 return (scsi3addr[3] & 0xC0) == 0x40;
625}
626
f2ef0ce7 627static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 628 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 629};
6b80b18f
ST		 630#define HPSA_RAID_0 0
631#define HPSA_RAID_4 1
632#define HPSA_RAID_1 2 /* also used for RAID 10 */
633#define HPSA_RAID_5 3 /* also used for RAID 50 */
634#define HPSA_RAID_51 4
635#define HPSA_RAID_6 5 /* also used for RAID 60 */
636#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 637#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
638#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 639
f3f01730
KB		 640static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
641{
642 return !device->physical_device;
643}
edd16368
SC		 644
645static ssize_t raid_level_show(struct device *dev,
646 struct device_attribute *attr, char *buf)
647{
648 ssize_t l = 0;
82a72c0a 649 unsigned char rlevel;
edd16368
SC		 650 struct ctlr_info *h;
651 struct scsi_device *sdev;
652 struct hpsa_scsi_dev_t *hdev;
653 unsigned long flags;
654
655 sdev = to_scsi_device(dev);
656 h = sdev_to_hba(sdev);
657 spin_lock_irqsave(&h->lock, flags);
658 hdev = sdev->hostdata;
659 if (!hdev) {
660 spin_unlock_irqrestore(&h->lock, flags);
661 return -ENODEV;
662 }
663
664 /* Is this even a logical drive? */
f3f01730 665 if (!is_logical_device(hdev)) {
edd16368
SC		 666 spin_unlock_irqrestore(&h->lock, flags);
667 l = snprintf(buf, PAGE_SIZE, "N/A\n");
668 return l;
669 }
670
671 rlevel = hdev->raid_level;
672 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 673 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 674 rlevel = RAID_UNKNOWN;
675 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
676 return l;
677}
678
679static ssize_t lunid_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681{
682 struct ctlr_info *h;
683 struct scsi_device *sdev;
684 struct hpsa_scsi_dev_t *hdev;
685 unsigned long flags;
686 unsigned char lunid[8];
687
688 sdev = to_scsi_device(dev);
689 h = sdev_to_hba(sdev);
690 spin_lock_irqsave(&h->lock, flags);
691 hdev = sdev->hostdata;
692 if (!hdev) {
693 spin_unlock_irqrestore(&h->lock, flags);
694 return -ENODEV;
695 }
696 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
697 spin_unlock_irqrestore(&h->lock, flags);
698 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
699 lunid[0], lunid[1], lunid[2], lunid[3],
700 lunid[4], lunid[5], lunid[6], lunid[7]);
701}
702
703static ssize_t unique_id_show(struct device *dev,
704 struct device_attribute *attr, char *buf)
705{
706 struct ctlr_info *h;
707 struct scsi_device *sdev;
708 struct hpsa_scsi_dev_t *hdev;
709 unsigned long flags;
710 unsigned char sn[16];
711
712 sdev = to_scsi_device(dev);
713 h = sdev_to_hba(sdev);
714 spin_lock_irqsave(&h->lock, flags);
715 hdev = sdev->hostdata;
716 if (!hdev) {
717 spin_unlock_irqrestore(&h->lock, flags);
718 return -ENODEV;
719 }
720 memcpy(sn, hdev->device_id, sizeof(sn));
721 spin_unlock_irqrestore(&h->lock, flags);
722 return snprintf(buf, 16 * 2 + 2,
723 "%02X%02X%02X%02X%02X%02X%02X%02X"
724 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
725 sn[0], sn[1], sn[2], sn[3],
726 sn[4], sn[5], sn[6], sn[7],
727 sn[8], sn[9], sn[10], sn[11],
728 sn[12], sn[13], sn[14], sn[15]);
729}
730
ded1be4a
JH		 731static ssize_t sas_address_show(struct device *dev,
732 struct device_attribute *attr, char *buf)
733{
734 struct ctlr_info *h;
735 struct scsi_device *sdev;
736 struct hpsa_scsi_dev_t *hdev;
737 unsigned long flags;
738 u64 sas_address;
739
740 sdev = to_scsi_device(dev);
741 h = sdev_to_hba(sdev);
742 spin_lock_irqsave(&h->lock, flags);
743 hdev = sdev->hostdata;
744 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
745 spin_unlock_irqrestore(&h->lock, flags);
746 return -ENODEV;
747 }
748 sas_address = hdev->sas_address;
749 spin_unlock_irqrestore(&h->lock, flags);
750
751 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
752}
753
c1988684
ST		 754static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
755 struct device_attribute *attr, char *buf)
756{
757 struct ctlr_info *h;
758 struct scsi_device *sdev;
759 struct hpsa_scsi_dev_t *hdev;
760 unsigned long flags;
761 int offload_enabled;
762
763 sdev = to_scsi_device(dev);
764 h = sdev_to_hba(sdev);
765 spin_lock_irqsave(&h->lock, flags);
766 hdev = sdev->hostdata;
767 if (!hdev) {
768 spin_unlock_irqrestore(&h->lock, flags);
769 return -ENODEV;
770 }
771 offload_enabled = hdev->offload_enabled;
772 spin_unlock_irqrestore(&h->lock, flags);
773 return snprintf(buf, 20, "%d\n", offload_enabled);
774}
775
8270b862 776#define MAX_PATHS 8
8270b862
JH		 777static ssize_t path_info_show(struct device *dev,
778 struct device_attribute *attr, char *buf)
779{
780 struct ctlr_info *h;
781 struct scsi_device *sdev;
782 struct hpsa_scsi_dev_t *hdev;
783 unsigned long flags;
784 int i;
785 int output_len = 0;
786 u8 box;
787 u8 bay;
788 u8 path_map_index = 0;
789 char *active;
790 unsigned char phys_connector[2];
8270b862 791
8270b862
JH		 792 sdev = to_scsi_device(dev);
793 h = sdev_to_hba(sdev);
794 spin_lock_irqsave(&h->devlock, flags);
795 hdev = sdev->hostdata;
796 if (!hdev) {
797 spin_unlock_irqrestore(&h->devlock, flags);
798 return -ENODEV;
799 }
800
801 bay = hdev->bay;
802 for (i = 0; i < MAX_PATHS; i++) {
803 path_map_index = 1<<i;
804 if (i == hdev->active_path_index)
805 active = "Active";
806 else if (hdev->path_map & path_map_index)
807 active = "Inactive";
808 else
809 continue;
810
1faf072c
RV		 811 output_len += scnprintf(buf + output_len,
812 PAGE_SIZE - output_len,
813 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 814 h->scsi_host->host_no,
815 hdev->bus, hdev->target, hdev->lun,
816 scsi_device_type(hdev->devtype));
817
cca8f13b 818 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 819 output_len += scnprintf(buf + output_len,
1faf072c
RV		 820 PAGE_SIZE - output_len,
821 "%s\n", active);
8270b862
JH		 822 continue;
823 }
824
825 box = hdev->box[i];
826 memcpy(&phys_connector, &hdev->phys_connector[i],
827 sizeof(phys_connector));
828 if (phys_connector[0] < '0')
829 phys_connector[0] = '0';
830 if (phys_connector[1] < '0')
831 phys_connector[1] = '0';
cca8f13b 832 output_len += scnprintf(buf + output_len,
1faf072c 833 PAGE_SIZE - output_len,
8270b862
JH		 834 "PORT: %.2s ",
835 phys_connector);
af15ed36
DB		 836 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
837 hdev->expose_device) {
8270b862 838 if (box == 0 || box == 0xFF) {
2708f295 839 output_len += scnprintf(buf + output_len,
1faf072c 840 PAGE_SIZE - output_len,
8270b862
JH		 841 "BAY: %hhu %s\n",
842 bay, active);
843 } else {
2708f295 844 output_len += scnprintf(buf + output_len,
1faf072c 845 PAGE_SIZE - output_len,
8270b862
JH		 846 "BOX: %hhu BAY: %hhu %s\n",
847 box, bay, active);
848 }
849 } else if (box != 0 && box != 0xFF) {
2708f295 850 output_len += scnprintf(buf + output_len,
1faf072c 851 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 852 box, active);
853 } else
2708f295 854 output_len += scnprintf(buf + output_len,
1faf072c 855 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 856 }
857
858 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 859 return output_len;
8270b862
JH		 860}
861
3f5eac3a
SC		 862static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
863static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
864static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
865static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
ded1be4a 866static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL);
c1988684
ST		 867static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
868 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 869static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 870static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
871 host_show_hp_ssd_smart_path_status,
872 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 873static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
874 host_store_raid_offload_debug);
3f5eac3a
SC		 875static DEVICE_ATTR(firmware_revision, S_IRUGO,
876 host_show_firmware_revision, NULL);
877static DEVICE_ATTR(commands_outstanding, S_IRUGO,
878 host_show_commands_outstanding, NULL);
879static DEVICE_ATTR(transport_mode, S_IRUGO,
880 host_show_transport_mode, NULL);
941b1cda
SC		 881static DEVICE_ATTR(resettable, S_IRUGO,
882 host_show_resettable, NULL);
e985c58f
SC		 883static DEVICE_ATTR(lockup_detected, S_IRUGO,
884 host_show_lockup_detected, NULL);
3f5eac3a
SC		 885
886static struct device_attribute *hpsa_sdev_attrs[] = {
887 &dev_attr_raid_level,
888 &dev_attr_lunid,
889 &dev_attr_unique_id,
c1988684 890 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 891 &dev_attr_path_info,
ded1be4a 892 &dev_attr_sas_address,
3f5eac3a
SC		 893 NULL,
894};
895
896static struct device_attribute *hpsa_shost_attrs[] = {
897 &dev_attr_rescan,
898 &dev_attr_firmware_revision,
899 &dev_attr_commands_outstanding,
900 &dev_attr_transport_mode,
941b1cda 901 &dev_attr_resettable,
da0697bd 902 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 903 &dev_attr_raid_offload_debug,
fb53c439 904 &dev_attr_lockup_detected,
3f5eac3a
SC		 905 NULL,
906};
907
41ce4c35
SC		 908#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
909 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
910
3f5eac3a
SC		 911static struct scsi_host_template hpsa_driver_template = {
912 .module = THIS_MODULE,
f79cfec6
SC		 913 .name = HPSA,
914 .proc_name = HPSA,
3f5eac3a
SC		 915 .queuecommand = hpsa_scsi_queue_command,
916 .scan_start = hpsa_scan_start,
917 .scan_finished = hpsa_scan_finished,
7c0a0229 918 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 919 .this_id = -1,
920 .use_clustering = ENABLE_CLUSTERING,
75167d2c 921 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 922 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
923 .ioctl = hpsa_ioctl,
924 .slave_alloc = hpsa_slave_alloc,
41ce4c35 925 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 926 .slave_destroy = hpsa_slave_destroy,
927#ifdef CONFIG_COMPAT
928 .compat_ioctl = hpsa_compat_ioctl,
929#endif
930 .sdev_attrs = hpsa_sdev_attrs,
931 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 932 .max_sectors = 8192,
54b2b50c 933 .no_write_same = 1,
3f5eac3a
SC		 934};
935
254f796b 936static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 937{
938 u32 a;
072b0518 939 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 940
e1f7de0c
MG		 941 if (h->transMethod & CFGTBL_Trans_io_accel1)
942 return h->access.command_completed(h, q);
943
3f5eac3a 944 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 945 return h->access.command_completed(h, q);
3f5eac3a 946
254f796b
MG		 947 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
948 a = rq->head[rq->current_entry];
949 rq->current_entry++;
0cbf768e 950 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 951 } else {
952 a = FIFO_EMPTY;
953 }
954 /* Check for wraparound */
254f796b
MG		 955 if (rq->current_entry == h->max_commands) {
956 rq->current_entry = 0;
957 rq->wraparound ^= 1;
3f5eac3a
SC		 958 }
959 return a;
960}
961
c349775e
ST		 962/*
963 * There are some special bits in the bus address of the
964 * command that we have to set for the controller to know
965 * how to process the command:
966 *
967 * Normal performant mode:
968 * bit 0: 1 means performant mode, 0 means simple mode.
969 * bits 1-3 = block fetch table entry
970 * bits 4-6 = command type (== 0)
971 *
972 * ioaccel1 mode:
973 * bit 0 = "performant mode" bit.
974 * bits 1-3 = block fetch table entry
975 * bits 4-6 = command type (== 110)
976 * (command type is needed because ioaccel1 mode
977 * commands are submitted through the same register as normal
978 * mode commands, so this is how the controller knows whether
979 * the command is normal mode or ioaccel1 mode.)
980 *
981 * ioaccel2 mode:
982 * bit 0 = "performant mode" bit.
983 * bits 1-4 = block fetch table entry (note extra bit)
984 * bits 4-6 = not needed, because ioaccel2 mode has
985 * a separate special register for submitting commands.
986 */
987
25163bd5
WS		 988/*
989 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 990 * set bit 0 for pull model, bits 3-1 for block fetch
991 * register number
992 */
25163bd5
WS		 993#define DEFAULT_REPLY_QUEUE (-1)
994static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
995 int reply_queue)
3f5eac3a 996{
254f796b 997 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 998 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 999 if (unlikely(!h->msix_vector))
1000 return;
1001 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 1002 c->Header.ReplyQueue =
804a5cb5 1003 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 1004 else
1005 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 1006 }
3f5eac3a
SC		 1007}
1008
c349775e 1009static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1010 struct CommandList *c,
1011 int reply_queue)
c349775e
ST		 1012{
1013 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
1014
25163bd5
WS		 1015 /*
1016 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1017 * processor. This seems to give the best I/O throughput.
1018 */
25163bd5
WS		 1019 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1020 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
1021 else
1022 cp->ReplyQueue = reply_queue % h->nreply_queues;
1023 /*
1024 * Set the bits in the address sent down to include:
c349775e
ST		 1025 * - performant mode bit (bit 0)
1026 * - pull count (bits 1-3)
1027 * - command type (bits 4-6)
1028 */
1029 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1030 IOACCEL1_BUSADDR_CMDTYPE;
1031}
1032
8be986cc
SC		 1033static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1034 struct CommandList *c,
1035 int reply_queue)
1036{
1037 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1038 &h->ioaccel2_cmd_pool[c->cmdindex];
1039
1040 /* Tell the controller to post the reply to the queue for this
1041 * processor. This seems to give the best I/O throughput.
1042 */
1043 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1044 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1045 else
1046 cp->reply_queue = reply_queue % h->nreply_queues;
1047 /* Set the bits in the address sent down to include:
1048 * - performant mode bit not used in ioaccel mode 2
1049 * - pull count (bits 0-3)
1050 * - command type isn't needed for ioaccel2
1051 */
1052 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1053}
1054
c349775e 1055static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1056 struct CommandList *c,
1057 int reply_queue)
c349775e
ST		 1058{
1059 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1060
25163bd5
WS		 1061 /*
1062 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1063 * processor. This seems to give the best I/O throughput.
1064 */
25163bd5
WS		 1065 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1066 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1067 else
1068 cp->reply_queue = reply_queue % h->nreply_queues;
1069 /*
1070 * Set the bits in the address sent down to include:
c349775e
ST		 1071 * - performant mode bit not used in ioaccel mode 2
1072 * - pull count (bits 0-3)
1073 * - command type isn't needed for ioaccel2
1074 */
1075 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1076}
1077
e85c5974
SC		 1078static int is_firmware_flash_cmd(u8 *cdb)
1079{
1080 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1081}
1082
1083/*
1084 * During firmware flash, the heartbeat register may not update as frequently
1085 * as it should. So we dial down lockup detection during firmware flash. and
1086 * dial it back up when firmware flash completes.
1087 */
1088#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1089#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1090static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1091 struct CommandList *c)
1092{
1093 if (!is_firmware_flash_cmd(c->Request.CDB))
1094 return;
1095 atomic_inc(&h->firmware_flash_in_progress);
1096 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1097}
1098
1099static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1100 struct CommandList *c)
1101{
1102 if (is_firmware_flash_cmd(c->Request.CDB) &&
1103 atomic_dec_and_test(&h->firmware_flash_in_progress))
1104 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1105}
1106
25163bd5
WS		 1107static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1108 struct CommandList *c, int reply_queue)
3f5eac3a 1109{
c05e8866
SC		 1110 dial_down_lockup_detection_during_fw_flash(h, c);
1111 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1112 switch (c->cmd_type) {
1113 case CMD_IOACCEL1:
25163bd5 1114 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1115 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1116 break;
1117 case CMD_IOACCEL2:
25163bd5 1118 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1119 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1120 break;
8be986cc
SC		 1121 case IOACCEL2_TMF:
1122 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1123 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1124 break;
c349775e 1125 default:
25163bd5 1126 set_performant_mode(h, c, reply_queue);
c05e8866 1127 h->access.submit_command(h, c);
c349775e 1128 }
3f5eac3a
SC		 1129}
1130
a58e7e53 1131static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1132{
d604f533 1133 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1134 return finish_cmd(c);
1135
25163bd5
WS		 1136 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1137}
1138
3f5eac3a
SC		 1139static inline int is_hba_lunid(unsigned char scsi3addr[])
1140{
1141 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1142}
1143
1144static inline int is_scsi_rev_5(struct ctlr_info *h)
1145{
1146 if (!h->hba_inquiry_data)
1147 return 0;
1148 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1149 return 1;
1150 return 0;
1151}
1152
edd16368
SC		 1153static int hpsa_find_target_lun(struct ctlr_info *h,
1154 unsigned char scsi3addr[], int bus, int *target, int *lun)
1155{
1156 /* finds an unused bus, target, lun for a new physical device
1157 * assumes h->devlock is held
1158 */
1159 int i, found = 0;
cfe5badc 1160 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1161
263d9401 1162 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1163
1164 for (i = 0; i < h->ndevices; i++) {
1165 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1166 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1167 }
1168
263d9401
AM		 1169 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1170 if (i < HPSA_MAX_DEVICES) {
1171 /* *bus = 1; */
1172 *target = i;
1173 *lun = 0;
1174 found = 1;
edd16368
SC		 1175 }
1176 return !found;
1177}
1178
1d33d85d 1179static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1180 struct hpsa_scsi_dev_t *dev, char *description)
1181{
7c59a0d4
DB		 1182#define LABEL_SIZE 25
1183 char label[LABEL_SIZE];
1184
9975ec9d
DB		 1185 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1186 return;
1187
7c59a0d4
DB		 1188 switch (dev->devtype) {
1189 case TYPE_RAID:
1190 snprintf(label, LABEL_SIZE, "controller");
1191 break;
1192 case TYPE_ENCLOSURE:
1193 snprintf(label, LABEL_SIZE, "enclosure");
1194 break;
1195 case TYPE_DISK:
af15ed36 1196 case TYPE_ZBC:
7c59a0d4
DB		 1197 if (dev->external)
1198 snprintf(label, LABEL_SIZE, "external");
1199 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1200 snprintf(label, LABEL_SIZE, "%s",
1201 raid_label[PHYSICAL_DRIVE]);
1202 else
1203 snprintf(label, LABEL_SIZE, "RAID-%s",
1204 dev->raid_level > RAID_UNKNOWN ? "?" :
1205 raid_label[dev->raid_level]);
1206 break;
1207 case TYPE_ROM:
1208 snprintf(label, LABEL_SIZE, "rom");
1209 break;
1210 case TYPE_TAPE:
1211 snprintf(label, LABEL_SIZE, "tape");
1212 break;
1213 case TYPE_MEDIUM_CHANGER:
1214 snprintf(label, LABEL_SIZE, "changer");
1215 break;
1216 default:
1217 snprintf(label, LABEL_SIZE, "UNKNOWN");
1218 break;
1219 }
1220
0d96ef5f 1221 dev_printk(level, &h->pdev->dev,
7c59a0d4 1222 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1223 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1224 description,
1225 scsi_device_type(dev->devtype),
1226 dev->vendor,
1227 dev->model,
7c59a0d4 1228 label,
0d96ef5f
WS		 1229 dev->offload_config ? '+' : '-',
1230 dev->offload_enabled ? '+' : '-',
2a168208 1231 dev->expose_device);
0d96ef5f
WS		 1232}
1233
edd16368 1234/* Add an entry into h->dev[] array. */
8aa60681 1235static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1236 struct hpsa_scsi_dev_t *device,
1237 struct hpsa_scsi_dev_t *added[], int *nadded)
1238{
1239 /* assumes h->devlock is held */
1240 int n = h->ndevices;
1241 int i;
1242 unsigned char addr1[8], addr2[8];
1243 struct hpsa_scsi_dev_t *sd;
1244
cfe5badc 1245 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1246 dev_err(&h->pdev->dev, "too many devices, some will be "
1247 "inaccessible.\n");
1248 return -1;
1249 }
1250
1251 /* physical devices do not have lun or target assigned until now. */
1252 if (device->lun != -1)
1253 /* Logical device, lun is already assigned. */
1254 goto lun_assigned;
1255
1256 /* If this device a non-zero lun of a multi-lun device
1257 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1258 * unit no, zero otherwise.
edd16368
SC		 1259 */
1260 if (device->scsi3addr[4] == 0) {
1261 /* This is not a non-zero lun of a multi-lun device */
1262 if (hpsa_find_target_lun(h, device->scsi3addr,
1263 device->bus, &device->target, &device->lun) != 0)
1264 return -1;
1265 goto lun_assigned;
1266 }
1267
1268 /* This is a non-zero lun of a multi-lun device.
1269 * Search through our list and find the device which
9a4178b7 1270 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1271 * Assign the same bus and target for this new LUN.
1272 * Use the logical unit number from the firmware.
1273 */
1274 memcpy(addr1, device->scsi3addr, 8);
1275 addr1[4] = 0;
9a4178b7 1276 addr1[5] = 0;
edd16368
SC		 1277 for (i = 0; i < n; i++) {
1278 sd = h->dev[i];
1279 memcpy(addr2, sd->scsi3addr, 8);
1280 addr2[4] = 0;
9a4178b7 1281 addr2[5] = 0;
1282 /* differ only in byte 4 and 5? */
edd16368
SC		 1283 if (memcmp(addr1, addr2, 8) == 0) {
1284 device->bus = sd->bus;
1285 device->target = sd->target;
1286 device->lun = device->scsi3addr[4];
1287 break;
1288 }
1289 }
1290 if (device->lun == -1) {
1291 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1292 " suspect firmware bug or unsupported hardware "
1293 "configuration.\n");
1294 return -1;
1295 }
1296
1297lun_assigned:
1298
1299 h->dev[n] = device;
1300 h->ndevices++;
1301 added[*nadded] = device;
1302 (*nadded)++;
0d96ef5f 1303 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1304 device->expose_device ? "added" : "masked");
a473d86c
RE		 1305 device->offload_to_be_enabled = device->offload_enabled;
1306 device->offload_enabled = 0;
edd16368
SC		 1307 return 0;
1308}
1309
bd9244f7 1310/* Update an entry in h->dev[] array. */
8aa60681 1311static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1312 int entry, struct hpsa_scsi_dev_t *new_entry)
1313{
a473d86c 1314 int offload_enabled;
bd9244f7
ST		 1315 /* assumes h->devlock is held */
1316 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1317
1318 /* Raid level changed. */
1319 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1320
03383736
DB		 1321 /* Raid offload parameters changed. Careful about the ordering. */
1322 if (new_entry->offload_config && new_entry->offload_enabled) {
1323 /*
1324 * if drive is newly offload_enabled, we want to copy the
1325 * raid map data first. If previously offload_enabled and
1326 * offload_config were set, raid map data had better be
1327 * the same as it was before. if raid map data is changed
1328 * then it had better be the case that
1329 * h->dev[entry]->offload_enabled is currently 0.
1330 */
1331 h->dev[entry]->raid_map = new_entry->raid_map;
1332 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1333 }
a3144e0b
JH		 1334 if (new_entry->hba_ioaccel_enabled) {
1335 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1336 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1337 }
1338 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1339 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1340 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1341 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1342
41ce4c35
SC		 1343 /*
1344 * We can turn off ioaccel offload now, but need to delay turning
1345 * it on until we can update h->dev[entry]->phys_disk[], but we
1346 * can't do that until all the devices are updated.
1347 */
1348 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1349 if (!new_entry->offload_enabled)
1350 h->dev[entry]->offload_enabled = 0;
1351
a473d86c
RE		 1352 offload_enabled = h->dev[entry]->offload_enabled;
1353 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1354 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1355 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1356}
1357
2a8ccf31 1358/* Replace an entry from h->dev[] array. */
8aa60681 1359static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1360 int entry, struct hpsa_scsi_dev_t *new_entry,
1361 struct hpsa_scsi_dev_t *added[], int *nadded,
1362 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1363{
1364 /* assumes h->devlock is held */
cfe5badc 1365 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1366 removed[*nremoved] = h->dev[entry];
1367 (*nremoved)++;
01350d05
SC		 1368
1369 /*
1370 * New physical devices won't have target/lun assigned yet
1371 * so we need to preserve the values in the slot we are replacing.
1372 */
1373 if (new_entry->target == -1) {
1374 new_entry->target = h->dev[entry]->target;
1375 new_entry->lun = h->dev[entry]->lun;
1376 }
1377
2a8ccf31
SC		 1378 h->dev[entry] = new_entry;
1379 added[*nadded] = new_entry;
1380 (*nadded)++;
0d96ef5f 1381 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1382 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1383 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1384}
1385
edd16368 1386/* Remove an entry from h->dev[] array. */
8aa60681 1387static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1388 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1389{
1390 /* assumes h->devlock is held */
1391 int i;
1392 struct hpsa_scsi_dev_t *sd;
1393
cfe5badc 1394 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1395
1396 sd = h->dev[entry];
1397 removed[*nremoved] = h->dev[entry];
1398 (*nremoved)++;
1399
1400 for (i = entry; i < h->ndevices-1; i++)
1401 h->dev[i] = h->dev[i+1];
1402 h->ndevices--;
0d96ef5f 1403 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1404}
1405
1406#define SCSI3ADDR_EQ(a, b) ( \
1407 (a)[7] == (b)[7] && \
1408 (a)[6] == (b)[6] && \
1409 (a)[5] == (b)[5] && \
1410 (a)[4] == (b)[4] && \
1411 (a)[3] == (b)[3] && \
1412 (a)[2] == (b)[2] && \
1413 (a)[1] == (b)[1] && \
1414 (a)[0] == (b)[0])
1415
1416static void fixup_botched_add(struct ctlr_info *h,
1417 struct hpsa_scsi_dev_t *added)
1418{
1419 /* called when scsi_add_device fails in order to re-adjust
1420 * h->dev[] to match the mid layer's view.
1421 */
1422 unsigned long flags;
1423 int i, j;
1424
1425 spin_lock_irqsave(&h->lock, flags);
1426 for (i = 0; i < h->ndevices; i++) {
1427 if (h->dev[i] == added) {
1428 for (j = i; j < h->ndevices-1; j++)
1429 h->dev[j] = h->dev[j+1];
1430 h->ndevices--;
1431 break;
1432 }
1433 }
1434 spin_unlock_irqrestore(&h->lock, flags);
1435 kfree(added);
1436}
1437
1438static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1439 struct hpsa_scsi_dev_t *dev2)
1440{
edd16368
SC		 1441 /* we compare everything except lun and target as these
1442 * are not yet assigned. Compare parts likely
1443 * to differ first
1444 */
1445 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1446 sizeof(dev1->scsi3addr)) != 0)
1447 return 0;
1448 if (memcmp(dev1->device_id, dev2->device_id,
1449 sizeof(dev1->device_id)) != 0)
1450 return 0;
1451 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1452 return 0;
1453 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1454 return 0;
edd16368
SC		 1455 if (dev1->devtype != dev2->devtype)
1456 return 0;
edd16368
SC		 1457 if (dev1->bus != dev2->bus)
1458 return 0;
1459 return 1;
1460}
1461
bd9244f7
ST		 1462static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1463 struct hpsa_scsi_dev_t *dev2)
1464{
1465 /* Device attributes that can change, but don't mean
1466 * that the device is a different device, nor that the OS
1467 * needs to be told anything about the change.
1468 */
1469 if (dev1->raid_level != dev2->raid_level)
1470 return 1;
250fb125
SC		 1471 if (dev1->offload_config != dev2->offload_config)
1472 return 1;
1473 if (dev1->offload_enabled != dev2->offload_enabled)
1474 return 1;
93849508
DB		 1475 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1476 if (dev1->queue_depth != dev2->queue_depth)
1477 return 1;
bd9244f7
ST		 1478 return 0;
1479}
1480
edd16368
SC		 1481/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1482 * and return needle location in *index. If scsi3addr matches, but not
1483 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1484 * location in *index.
1485 * In the case of a minor device attribute change, such as RAID level, just
1486 * return DEVICE_UPDATED, along with the updated device's location in index.
1487 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1488 */
1489static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1490 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1491 int *index)
1492{
1493 int i;
1494#define DEVICE_NOT_FOUND 0
1495#define DEVICE_CHANGED 1
1496#define DEVICE_SAME 2
bd9244f7 1497#define DEVICE_UPDATED 3
1d33d85d
DB		 1498 if (needle == NULL)
1499 return DEVICE_NOT_FOUND;
1500
edd16368 1501 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1502 if (haystack[i] == NULL) /* previously removed. */
1503 continue;
edd16368
SC		 1504 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1505 *index = i;
bd9244f7
ST		 1506 if (device_is_the_same(needle, haystack[i])) {
1507 if (device_updated(needle, haystack[i]))
1508 return DEVICE_UPDATED;
edd16368 1509 return DEVICE_SAME;
bd9244f7 1510 } else {
9846590e
SC		 1511 /* Keep offline devices offline */
1512 if (needle->volume_offline)
1513 return DEVICE_NOT_FOUND;
edd16368 1514 return DEVICE_CHANGED;
bd9244f7 1515 }
edd16368
SC		 1516 }
1517 }
1518 *index = -1;
1519 return DEVICE_NOT_FOUND;
1520}
1521
9846590e
SC		 1522static void hpsa_monitor_offline_device(struct ctlr_info *h,
1523 unsigned char scsi3addr[])
1524{
1525 struct offline_device_entry *device;
1526 unsigned long flags;
1527
1528 /* Check to see if device is already on the list */
1529 spin_lock_irqsave(&h->offline_device_lock, flags);
1530 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1531 if (memcmp(device->scsi3addr, scsi3addr,
1532 sizeof(device->scsi3addr)) == 0) {
1533 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1534 return;
1535 }
1536 }
1537 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1538
1539 /* Device is not on the list, add it. */
1540 device = kmalloc(sizeof(*device), GFP_KERNEL);
1541 if (!device) {
1542 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1543 return;
1544 }
1545 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1546 spin_lock_irqsave(&h->offline_device_lock, flags);
1547 list_add_tail(&device->offline_list, &h->offline_device_list);
1548 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1549}
1550
1551/* Print a message explaining various offline volume states */
1552static void hpsa_show_volume_status(struct ctlr_info *h,
1553 struct hpsa_scsi_dev_t *sd)
1554{
1555 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1556 dev_info(&h->pdev->dev,
1557 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1558 h->scsi_host->host_no,
1559 sd->bus, sd->target, sd->lun);
1560 switch (sd->volume_offline) {
1561 case HPSA_LV_OK:
1562 break;
1563 case HPSA_LV_UNDERGOING_ERASE:
1564 dev_info(&h->pdev->dev,
1565 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1566 h->scsi_host->host_no,
1567 sd->bus, sd->target, sd->lun);
1568 break;
5ca01204
SB		 1569 case HPSA_LV_NOT_AVAILABLE:
1570 dev_info(&h->pdev->dev,
1571 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1572 h->scsi_host->host_no,
1573 sd->bus, sd->target, sd->lun);
1574 break;
9846590e
SC		 1575 case HPSA_LV_UNDERGOING_RPI:
1576 dev_info(&h->pdev->dev,
5ca01204 1577 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1578 h->scsi_host->host_no,
1579 sd->bus, sd->target, sd->lun);
1580 break;
1581 case HPSA_LV_PENDING_RPI:
1582 dev_info(&h->pdev->dev,
5ca01204
SB		 1583 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1584 h->scsi_host->host_no,
1585 sd->bus, sd->target, sd->lun);
9846590e
SC		 1586 break;
1587 case HPSA_LV_ENCRYPTED_NO_KEY:
1588 dev_info(&h->pdev->dev,
1589 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1590 h->scsi_host->host_no,
1591 sd->bus, sd->target, sd->lun);
1592 break;
1593 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1594 dev_info(&h->pdev->dev,
1595 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1596 h->scsi_host->host_no,
1597 sd->bus, sd->target, sd->lun);
1598 break;
1599 case HPSA_LV_UNDERGOING_ENCRYPTION:
1600 dev_info(&h->pdev->dev,
1601 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1602 h->scsi_host->host_no,
1603 sd->bus, sd->target, sd->lun);
1604 break;
1605 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1606 dev_info(&h->pdev->dev,
1607 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1608 h->scsi_host->host_no,
1609 sd->bus, sd->target, sd->lun);
1610 break;
1611 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1612 dev_info(&h->pdev->dev,
1613 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1614 h->scsi_host->host_no,
1615 sd->bus, sd->target, sd->lun);
1616 break;
1617 case HPSA_LV_PENDING_ENCRYPTION:
1618 dev_info(&h->pdev->dev,
1619 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1620 h->scsi_host->host_no,
1621 sd->bus, sd->target, sd->lun);
1622 break;
1623 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1624 dev_info(&h->pdev->dev,
1625 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1626 h->scsi_host->host_no,
1627 sd->bus, sd->target, sd->lun);
1628 break;
1629 }
1630}
1631
03383736
DB		 1632/*
1633 * Figure the list of physical drive pointers for a logical drive with
1634 * raid offload configured.
1635 */
1636static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1637 struct hpsa_scsi_dev_t *dev[], int ndevices,
1638 struct hpsa_scsi_dev_t *logical_drive)
1639{
1640 struct raid_map_data *map = &logical_drive->raid_map;
1641 struct raid_map_disk_data *dd = &map->data[0];
1642 int i, j;
1643 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1644 le16_to_cpu(map->metadata_disks_per_row);
1645 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1646 le16_to_cpu(map->layout_map_count) *
1647 total_disks_per_row;
1648 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1649 total_disks_per_row;
1650 int qdepth;
1651
1652 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1653 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1654
d604f533
WS		 1655 logical_drive->nphysical_disks = nraid_map_entries;
1656
03383736
DB		 1657 qdepth = 0;
1658 for (i = 0; i < nraid_map_entries; i++) {
1659 logical_drive->phys_disk[i] = NULL;
1660 if (!logical_drive->offload_config)
1661 continue;
1662 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1663 if (dev[j] == NULL)
1664 continue;
03383736
DB		 1665 if (dev[j]->devtype != TYPE_DISK)
1666 continue;
af15ed36
DB		 1667 if (dev[j]->devtype != TYPE_ZBC)
1668 continue;
f3f01730 1669 if (is_logical_device(dev[j]))
03383736
DB		 1670 continue;
1671 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1672 continue;
1673
1674 logical_drive->phys_disk[i] = dev[j];
1675 if (i < nphys_disk)
1676 qdepth = min(h->nr_cmds, qdepth +
1677 logical_drive->phys_disk[i]->queue_depth);
1678 break;
1679 }
1680
1681 /*
1682 * This can happen if a physical drive is removed and
1683 * the logical drive is degraded. In that case, the RAID
1684 * map data will refer to a physical disk which isn't actually
1685 * present. And in that case offload_enabled should already
1686 * be 0, but we'll turn it off here just in case
1687 */
1688 if (!logical_drive->phys_disk[i]) {
1689 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1690 logical_drive->offload_to_be_enabled = 0;
1691 logical_drive->queue_depth = 8;
03383736
DB		 1692 }
1693 }
1694 if (nraid_map_entries)
1695 /*
1696 * This is correct for reads, too high for full stripe writes,
1697 * way too high for partial stripe writes
1698 */
1699 logical_drive->queue_depth = qdepth;
1700 else
1701 logical_drive->queue_depth = h->nr_cmds;
1702}
1703
1704static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1705 struct hpsa_scsi_dev_t *dev[], int ndevices)
1706{
1707 int i;
1708
1709 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1710 if (dev[i] == NULL)
1711 continue;
03383736
DB		 1712 if (dev[i]->devtype != TYPE_DISK)
1713 continue;
af15ed36
DB		 1714 if (dev[i]->devtype != TYPE_ZBC)
1715 continue;
f3f01730 1716 if (!is_logical_device(dev[i]))
03383736 1717 continue;
41ce4c35
SC		 1718
1719 /*
1720 * If offload is currently enabled, the RAID map and
1721 * phys_disk[] assignment *better* not be changing
1722 * and since it isn't changing, we do not need to
1723 * update it.
1724 */
1725 if (dev[i]->offload_enabled)
1726 continue;
1727
03383736
DB		 1728 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1729 }
1730}
1731
096ccff4
KB		 1732static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1733{
1734 int rc = 0;
1735
1736 if (!h->scsi_host)
1737 return 1;
1738
d04e62b9
KB		 1739 if (is_logical_device(device)) /* RAID */
1740 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1741 device->target, device->lun);
d04e62b9
KB		 1742 else /* HBA */
1743 rc = hpsa_add_sas_device(h->sas_host, device);
1744
096ccff4
KB		 1745 return rc;
1746}
1747
1748static void hpsa_remove_device(struct ctlr_info *h,
1749 struct hpsa_scsi_dev_t *device)
1750{
1751 struct scsi_device *sdev = NULL;
1752
1753 if (!h->scsi_host)
1754 return;
1755
d04e62b9
KB		 1756 if (is_logical_device(device)) { /* RAID */
1757 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1758 device->target, device->lun);
d04e62b9
KB		 1759 if (sdev) {
1760 scsi_remove_device(sdev);
1761 scsi_device_put(sdev);
1762 } else {
1763 /*
1764 * We don't expect to get here. Future commands
1765 * to this device will get a selection timeout as
1766 * if the device were gone.
1767 */
1768 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1769 "didn't find device for removal.");
d04e62b9
KB		 1770 }
1771 } else /* HBA */
1772 hpsa_remove_sas_device(device);
096ccff4
KB		 1773}
1774
8aa60681 1775static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1776 struct hpsa_scsi_dev_t *sd[], int nsds)
1777{
1778 /* sd contains scsi3 addresses and devtypes, and inquiry
1779 * data. This function takes what's in sd to be the current
1780 * reality and updates h->dev[] to reflect that reality.
1781 */
1782 int i, entry, device_change, changes = 0;
1783 struct hpsa_scsi_dev_t *csd;
1784 unsigned long flags;
1785 struct hpsa_scsi_dev_t **added, **removed;
1786 int nadded, nremoved;
edd16368 1787
da03ded0
DB		 1788 /*
1789 * A reset can cause a device status to change
1790 * re-schedule the scan to see what happened.
1791 */
1792 if (h->reset_in_progress) {
1793 h->drv_req_rescan = 1;
1794 return;
1795 }
edd16368 1796
cfe5badc
ST		 1797 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1798 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1799
1800 if (!added || !removed) {
1801 dev_warn(&h->pdev->dev, "out of memory in "
1802 "adjust_hpsa_scsi_table\n");
1803 goto free_and_out;
1804 }
1805
1806 spin_lock_irqsave(&h->devlock, flags);
1807
1808 /* find any devices in h->dev[] that are not in
1809 * sd[] and remove them from h->dev[], and for any
1810 * devices which have changed, remove the old device
1811 * info and add the new device info.
bd9244f7
ST		 1812 * If minor device attributes change, just update
1813 * the existing device structure.
edd16368
SC		 1814 */
1815 i = 0;
1816 nremoved = 0;
1817 nadded = 0;
1818 while (i < h->ndevices) {
1819 csd = h->dev[i];
1820 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1821 if (device_change == DEVICE_NOT_FOUND) {
1822 changes++;
8aa60681 1823 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1824 continue; /* remove ^^^, hence i not incremented */
1825 } else if (device_change == DEVICE_CHANGED) {
1826 changes++;
8aa60681 1827 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1828 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1829 /* Set it to NULL to prevent it from being freed
1830 * at the bottom of hpsa_update_scsi_devices()
1831 */
1832 sd[entry] = NULL;
bd9244f7 1833 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1834 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1835 }
1836 i++;
1837 }
1838
1839 /* Now, make sure every device listed in sd[] is also
1840 * listed in h->dev[], adding them if they aren't found
1841 */
1842
1843 for (i = 0; i < nsds; i++) {
1844 if (!sd[i]) /* if already added above. */
1845 continue;
9846590e
SC		 1846
1847 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1848 * as the SCSI mid-layer does not handle such devices well.
1849 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1850 * at 160Hz, and prevents the system from coming up.
1851 */
1852 if (sd[i]->volume_offline) {
1853 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1854 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1855 continue;
1856 }
1857
edd16368
SC		 1858 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1859 h->ndevices, &entry);
1860 if (device_change == DEVICE_NOT_FOUND) {
1861 changes++;
8aa60681 1862 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1863 break;
1864 sd[i] = NULL; /* prevent from being freed later. */
1865 } else if (device_change == DEVICE_CHANGED) {
1866 /* should never happen... */
1867 changes++;
1868 dev_warn(&h->pdev->dev,
1869 "device unexpectedly changed.\n");
1870 /* but if it does happen, we just ignore that device */
1871 }
1872 }
41ce4c35
SC		 1873 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1874
1875 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1876 * any logical drives that need it enabled.
1877 */
1d33d85d
DB		 1878 for (i = 0; i < h->ndevices; i++) {
1879 if (h->dev[i] == NULL)
1880 continue;
41ce4c35 1881 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1882 }
41ce4c35 1883
edd16368
SC		 1884 spin_unlock_irqrestore(&h->devlock, flags);
1885
9846590e
SC		 1886 /* Monitor devices which are in one of several NOT READY states to be
1887 * brought online later. This must be done without holding h->devlock,
1888 * so don't touch h->dev[]
1889 */
1890 for (i = 0; i < nsds; i++) {
1891 if (!sd[i]) /* if already added above. */
1892 continue;
1893 if (sd[i]->volume_offline)
1894 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1895 }
1896
edd16368
SC		 1897 /* Don't notify scsi mid layer of any changes the first time through
1898 * (or if there are no changes) scsi_scan_host will do it later the
1899 * first time through.
1900 */
8aa60681 1901 if (!changes)
edd16368
SC		 1902 goto free_and_out;
1903
edd16368
SC		 1904 /* Notify scsi mid layer of any removed devices */
1905 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1906 if (removed[i] == NULL)
1907 continue;
096ccff4
KB		 1908 if (removed[i]->expose_device)
1909 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1910 kfree(removed[i]);
1911 removed[i] = NULL;
1912 }
1913
1914 /* Notify scsi mid layer of any added devices */
1915 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1916 int rc = 0;
1917
1d33d85d
DB		 1918 if (added[i] == NULL)
1919 continue;
2a168208 1920 if (!(added[i]->expose_device))
41ce4c35 1921 continue;
096ccff4
KB		 1922 rc = hpsa_add_device(h, added[i]);
1923 if (!rc)
edd16368 1924 continue;
096ccff4
KB		 1925 dev_warn(&h->pdev->dev,
1926 "addition failed %d, device not added.", rc);
edd16368
SC		 1927 /* now we have to remove it from h->dev,
1928 * since it didn't get added to scsi mid layer
1929 */
1930 fixup_botched_add(h, added[i]);
853633e8 1931 h->drv_req_rescan = 1;
edd16368
SC		 1932 }
1933
1934free_and_out:
1935 kfree(added);
1936 kfree(removed);
edd16368
SC		 1937}
1938
1939/*
9e03aa2f 1940 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1941 * Assume's h->devlock is held.
1942 */
1943static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1944 int bus, int target, int lun)
1945{
1946 int i;
1947 struct hpsa_scsi_dev_t *sd;
1948
1949 for (i = 0; i < h->ndevices; i++) {
1950 sd = h->dev[i];
1951 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1952 return sd;
1953 }
1954 return NULL;
1955}
1956
edd16368
SC		 1957static int hpsa_slave_alloc(struct scsi_device *sdev)
1958{
1959 struct hpsa_scsi_dev_t *sd;
1960 unsigned long flags;
1961 struct ctlr_info *h;
1962
1963 h = sdev_to_hba(sdev);
1964 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 1965 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
1966 struct scsi_target *starget;
1967 struct sas_rphy *rphy;
1968
1969 starget = scsi_target(sdev);
1970 rphy = target_to_rphy(starget);
1971 sd = hpsa_find_device_by_sas_rphy(h, rphy);
1972 if (sd) {
1973 sd->target = sdev_id(sdev);
1974 sd->lun = sdev->lun;
1975 }
1976 } else
1977 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1978 sdev_id(sdev), sdev->lun);
1979
1980 if (sd && sd->expose_device) {
03383736 1981 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 1982 sdev->hostdata = sd;
41ce4c35
SC		 1983 } else
1984 sdev->hostdata = NULL;
edd16368
SC		 1985 spin_unlock_irqrestore(&h->devlock, flags);
1986 return 0;
1987}
1988
41ce4c35
SC		 1989/* configure scsi device based on internal per-device structure */
1990static int hpsa_slave_configure(struct scsi_device *sdev)
1991{
1992 struct hpsa_scsi_dev_t *sd;
1993 int queue_depth;
1994
1995 sd = sdev->hostdata;
2a168208 1996 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 1997
1998 if (sd)
1999 queue_depth = sd->queue_depth != 0 ?
2000 sd->queue_depth : sdev->host->can_queue;
2001 else
2002 queue_depth = sdev->host->can_queue;
2003
2004 scsi_change_queue_depth(sdev, queue_depth);
2005
2006 return 0;
2007}
2008
edd16368
SC		 2009static void hpsa_slave_destroy(struct scsi_device *sdev)
2010{
bcc44255 2011 /* nothing to do. */
edd16368
SC		 2012}
2013
d9a729f3
WS		 2014static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2015{
2016 int i;
2017
2018 if (!h->ioaccel2_cmd_sg_list)
2019 return;
2020 for (i = 0; i < h->nr_cmds; i++) {
2021 kfree(h->ioaccel2_cmd_sg_list[i]);
2022 h->ioaccel2_cmd_sg_list[i] = NULL;
2023 }
2024 kfree(h->ioaccel2_cmd_sg_list);
2025 h->ioaccel2_cmd_sg_list = NULL;
2026}
2027
2028static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2029{
2030 int i;
2031
2032 if (h->chainsize <= 0)
2033 return 0;
2034
2035 h->ioaccel2_cmd_sg_list =
2036 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
2037 GFP_KERNEL);
2038 if (!h->ioaccel2_cmd_sg_list)
2039 return -ENOMEM;
2040 for (i = 0; i < h->nr_cmds; i++) {
2041 h->ioaccel2_cmd_sg_list[i] =
2042 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
2043 h->maxsgentries, GFP_KERNEL);
2044 if (!h->ioaccel2_cmd_sg_list[i])
2045 goto clean;
2046 }
2047 return 0;
2048
2049clean:
2050 hpsa_free_ioaccel2_sg_chain_blocks(h);
2051 return -ENOMEM;
2052}
2053
33a2ffce
SC		 2054static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2055{
2056 int i;
2057
2058 if (!h->cmd_sg_list)
2059 return;
2060 for (i = 0; i < h->nr_cmds; i++) {
2061 kfree(h->cmd_sg_list[i]);
2062 h->cmd_sg_list[i] = NULL;
2063 }
2064 kfree(h->cmd_sg_list);
2065 h->cmd_sg_list = NULL;
2066}
2067
105a3dbc 2068static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2069{
2070 int i;
2071
2072 if (h->chainsize <= 0)
2073 return 0;
2074
2075 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
2076 GFP_KERNEL);
3d4e6af8
RE		 2077 if (!h->cmd_sg_list) {
2078 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 2079 return -ENOMEM;
3d4e6af8 2080 }
33a2ffce
SC		 2081 for (i = 0; i < h->nr_cmds; i++) {
2082 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
2083 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 2084 if (!h->cmd_sg_list[i]) {
2085 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 2086 goto clean;
3d4e6af8 2087 }
33a2ffce
SC		 2088 }
2089 return 0;
2090
2091clean:
2092 hpsa_free_sg_chain_blocks(h);
2093 return -ENOMEM;
2094}
2095
d9a729f3
WS		 2096static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2097 struct io_accel2_cmd *cp, struct CommandList *c)
2098{
2099 struct ioaccel2_sg_element *chain_block;
2100 u64 temp64;
2101 u32 chain_size;
2102
2103 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2104 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2105 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2106 PCI_DMA_TODEVICE);
2107 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2108 /* prevent subsequent unmapping */
2109 cp->sg->address = 0;
2110 return -1;
2111 }
2112 cp->sg->address = cpu_to_le64(temp64);
2113 return 0;
2114}
2115
2116static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2117 struct io_accel2_cmd *cp)
2118{
2119 struct ioaccel2_sg_element *chain_sg;
2120 u64 temp64;
2121 u32 chain_size;
2122
2123 chain_sg = cp->sg;
2124 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2125 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2126 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2127}
2128
e2bea6df 2129static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2130 struct CommandList *c)
2131{
2132 struct SGDescriptor *chain_sg, *chain_block;
2133 u64 temp64;
50a0decf 2134 u32 chain_len;
33a2ffce
SC		 2135
2136 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2137 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2138 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2139 chain_len = sizeof(*chain_sg) *
2b08b3e9 2140 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2141 chain_sg->Len = cpu_to_le32(chain_len);
2142 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2143 PCI_DMA_TODEVICE);
e2bea6df
SC		 2144 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2145 /* prevent subsequent unmapping */
50a0decf 2146 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2147 return -1;
2148 }
50a0decf 2149 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2150 return 0;
33a2ffce
SC		 2151}
2152
2153static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2154 struct CommandList *c)
2155{
2156 struct SGDescriptor *chain_sg;
33a2ffce 2157
50a0decf 2158 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2159 return;
2160
2161 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2162 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2163 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2164}
2165
a09c1441
ST		 2166
2167/* Decode the various types of errors on ioaccel2 path.
2168 * Return 1 for any error that should generate a RAID path retry.
2169 * Return 0 for errors that don't require a RAID path retry.
2170 */
2171static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2172 struct CommandList *c,
2173 struct scsi_cmnd *cmd,
2174 struct io_accel2_cmd *c2)
2175{
2176 int data_len;
a09c1441 2177 int retry = 0;
c40820d5 2178 u32 ioaccel2_resid = 0;
c349775e
ST		 2179
2180 switch (c2->error_data.serv_response) {
2181 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2182 switch (c2->error_data.status) {
2183 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2184 break;
2185 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2186 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2187 if (c2->error_data.data_present !=
ee6b1889
SC		 2188 IOACCEL2_SENSE_DATA_PRESENT) {
2189 memset(cmd->sense_buffer, 0,
2190 SCSI_SENSE_BUFFERSIZE);
c349775e 2191 break;
ee6b1889 2192 }
c349775e
ST		 2193 /* copy the sense data */
2194 data_len = c2->error_data.sense_data_len;
2195 if (data_len > SCSI_SENSE_BUFFERSIZE)
2196 data_len = SCSI_SENSE_BUFFERSIZE;
2197 if (data_len > sizeof(c2->error_data.sense_data_buff))
2198 data_len =
2199 sizeof(c2->error_data.sense_data_buff);
2200 memcpy(cmd->sense_buffer,
2201 c2->error_data.sense_data_buff, data_len);
a09c1441 2202 retry = 1;
c349775e
ST		 2203 break;
2204 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2205 retry = 1;
c349775e
ST		 2206 break;
2207 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2208 retry = 1;
c349775e
ST		 2209 break;
2210 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2211 retry = 1;
c349775e
ST		 2212 break;
2213 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2214 retry = 1;
c349775e
ST		 2215 break;
2216 default:
a09c1441 2217 retry = 1;
c349775e
ST		 2218 break;
2219 }
2220 break;
2221 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2222 switch (c2->error_data.status) {
2223 case IOACCEL2_STATUS_SR_IO_ERROR:
2224 case IOACCEL2_STATUS_SR_IO_ABORTED:
2225 case IOACCEL2_STATUS_SR_OVERRUN:
2226 retry = 1;
2227 break;
2228 case IOACCEL2_STATUS_SR_UNDERRUN:
2229 cmd->result = (DID_OK << 16); /* host byte */
2230 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2231 ioaccel2_resid = get_unaligned_le32(
2232 &c2->error_data.resid_cnt[0]);
2233 scsi_set_resid(cmd, ioaccel2_resid);
2234 break;
2235 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2236 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2237 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2238 /* We will get an event from ctlr to trigger rescan */
2239 retry = 1;
2240 break;
2241 default:
2242 retry = 1;
c40820d5 2243 }
c349775e
ST		 2244 break;
2245 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2246 break;
2247 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2248 break;
2249 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2250 retry = 1;
c349775e
ST		 2251 break;
2252 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2253 break;
2254 default:
a09c1441 2255 retry = 1;
c349775e
ST		 2256 break;
2257 }
a09c1441
ST		 2258
2259 return retry; /* retry on raid path? */
c349775e
ST		 2260}
2261
a58e7e53
WS		 2262static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2263 struct CommandList *c)
2264{
d604f533
WS		 2265 bool do_wake = false;
2266
a58e7e53
WS		 2267 /*
2268 * Prevent the following race in the abort handler:
2269 *
2270 * 1. LLD is requested to abort a SCSI command
2271 * 2. The SCSI command completes
2272 * 3. The struct CommandList associated with step 2 is made available
2273 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2274 * 5. Abort handler follows scsi_cmnd->host_scribble and
2275 * finds struct CommandList and tries to aborts it
2276 * Now we have aborted the wrong command.
2277 *
d604f533
WS		 2278 * Reset c->scsi_cmd here so that the abort or reset handler will know
2279 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2280 * waiting for this command, and, if so, wake it.
2281 */
2282 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2283 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2284 if (c->abort_pending) {
d604f533 2285 do_wake = true;
a58e7e53 2286 c->abort_pending = false;
a58e7e53 2287 }
d604f533
WS		 2288 if (c->reset_pending) {
2289 unsigned long flags;
2290 struct hpsa_scsi_dev_t *dev;
2291
2292 /*
2293 * There appears to be a reset pending; lock the lock and
2294 * reconfirm. If so, then decrement the count of outstanding
2295 * commands and wake the reset command if this is the last one.
2296 */
2297 spin_lock_irqsave(&h->lock, flags);
2298 dev = c->reset_pending; /* Re-fetch under the lock. */
2299 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2300 do_wake = true;
2301 c->reset_pending = NULL;
2302 spin_unlock_irqrestore(&h->lock, flags);
2303 }
2304
2305 if (do_wake)
2306 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2307}
2308
73153fe5
WS		 2309static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2310 struct CommandList *c)
2311{
2312 hpsa_cmd_resolve_events(h, c);
2313 cmd_tagged_free(h, c);
2314}
2315
8a0ff92c
WS		 2316static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2317 struct CommandList *c, struct scsi_cmnd *cmd)
2318{
73153fe5 2319 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2320 cmd->scsi_done(cmd);
2321}
2322
2323static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2324{
2325 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2326 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2327}
2328
a58e7e53
WS		 2329static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2330{
2331 cmd->result = DID_ABORT << 16;
2332}
2333
2334static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2335 struct scsi_cmnd *cmd)
2336{
2337 hpsa_set_scsi_cmd_aborted(cmd);
2338 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2339 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2340 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2341}
2342
c349775e
ST		 2343static void process_ioaccel2_completion(struct ctlr_info *h,
2344 struct CommandList *c, struct scsi_cmnd *cmd,
2345 struct hpsa_scsi_dev_t *dev)
2346{
2347 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2348
2349 /* check for good status */
2350 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2351 c2->error_data.status == 0))
2352 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2353
8a0ff92c
WS		 2354 /*
2355 * Any RAID offload error results in retry which will use
c349775e
ST		 2356 * the normal I/O path so the controller can handle whatever's
2357 * wrong.
2358 */
f3f01730 2359 if (is_logical_device(dev) &&
c349775e
ST		 2360 c2->error_data.serv_response ==
2361 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc 2362 if (c2->error_data.status ==
064d1b1d 2363 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
080ef1cc 2364 dev->offload_enabled = 0;
064d1b1d
DB		 2365 dev->offload_to_be_enabled = 0;
2366 }
8a0ff92c
WS		 2367
2368 return hpsa_retry_cmd(h, c);
a09c1441 2369 }
080ef1cc
DB		 2370
2371 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2372 return hpsa_retry_cmd(h, c);
080ef1cc 2373
8a0ff92c 2374 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2375}
2376
9437ac43
SC		 2377/* Returns 0 on success, < 0 otherwise. */
2378static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2379 struct CommandList *cp)
2380{
2381 u8 tmf_status = cp->err_info->ScsiStatus;
2382
2383 switch (tmf_status) {
2384 case CISS_TMF_COMPLETE:
2385 /*
2386 * CISS_TMF_COMPLETE never happens, instead,
2387 * ei->CommandStatus == 0 for this case.
2388 */
2389 case CISS_TMF_SUCCESS:
2390 return 0;
2391 case CISS_TMF_INVALID_FRAME:
2392 case CISS_TMF_NOT_SUPPORTED:
2393 case CISS_TMF_FAILED:
2394 case CISS_TMF_WRONG_LUN:
2395 case CISS_TMF_OVERLAPPED_TAG:
2396 break;
2397 default:
2398 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2399 tmf_status);
2400 break;
2401 }
2402 return -tmf_status;
2403}
2404
1fb011fb 2405static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2406{
2407 struct scsi_cmnd *cmd;
2408 struct ctlr_info *h;
2409 struct ErrorInfo *ei;
283b4a9b 2410 struct hpsa_scsi_dev_t *dev;
d9a729f3 2411 struct io_accel2_cmd *c2;
edd16368 2412
9437ac43
SC		 2413 u8 sense_key;
2414 u8 asc; /* additional sense code */
2415 u8 ascq; /* additional sense code qualifier */
db111e18 2416 unsigned long sense_data_size;
edd16368
SC		 2417
2418 ei = cp->err_info;
7fa3030c 2419 cmd = cp->scsi_cmd;
edd16368 2420 h = cp->h;
283b4a9b 2421 dev = cmd->device->hostdata;
d9a729f3 2422 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2423
2424 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2425 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2426 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2427 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2428
d9a729f3
WS		 2429 if ((cp->cmd_type == CMD_IOACCEL2) &&
2430 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2431 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2432
edd16368
SC		 2433 cmd->result = (DID_OK << 16); /* host byte */
2434 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2435
03383736
DB		 2436 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2437 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2438
25163bd5
WS		 2439 /*
2440 * We check for lockup status here as it may be set for
2441 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2442 * fail_all_oustanding_cmds()
2443 */
2444 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2445 /* DID_NO_CONNECT will prevent a retry */
2446 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2447 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2448 }
2449
d604f533
WS		 2450 if ((unlikely(hpsa_is_pending_event(cp)))) {
2451 if (cp->reset_pending)
2452 return hpsa_cmd_resolve_and_free(h, cp);
2453 if (cp->abort_pending)
2454 return hpsa_cmd_abort_and_free(h, cp, cmd);
2455 }
2456
c349775e
ST		 2457 if (cp->cmd_type == CMD_IOACCEL2)
2458 return process_ioaccel2_completion(h, cp, cmd, dev);
2459
6aa4c361 2460 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2461 if (ei->CommandStatus == 0)
2462 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2463
e1f7de0c
MG		 2464 /* For I/O accelerator commands, copy over some fields to the normal
2465 * CISS header used below for error handling.
2466 */
2467 if (cp->cmd_type == CMD_IOACCEL1) {
2468 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2469 cp->Header.SGList = scsi_sg_count(cmd);
2470 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2471 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2472 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2473 cp->Header.tag = c->tag;
e1f7de0c
MG		 2474 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2475 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2476
2477 /* Any RAID offload error results in retry which will use
2478 * the normal I/O path so the controller can handle whatever's
2479 * wrong.
2480 */
f3f01730 2481 if (is_logical_device(dev)) {
283b4a9b
SC		 2482 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2483 dev->offload_enabled = 0;
d604f533 2484 return hpsa_retry_cmd(h, cp);
283b4a9b 2485 }
e1f7de0c
MG		 2486 }
2487
edd16368
SC		 2488 /* an error has occurred */
2489 switch (ei->CommandStatus) {
2490
2491 case CMD_TARGET_STATUS:
9437ac43
SC		 2492 cmd->result |= ei->ScsiStatus;
2493 /* copy the sense data */
2494 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2495 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2496 else
2497 sense_data_size = sizeof(ei->SenseInfo);
2498 if (ei->SenseLen < sense_data_size)
2499 sense_data_size = ei->SenseLen;
2500 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2501 if (ei->ScsiStatus)
2502 decode_sense_data(ei->SenseInfo, sense_data_size,
2503 &sense_key, &asc, &ascq);
edd16368 2504 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2505 if (sense_key == ABORTED_COMMAND) {
2e311fba 2506 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2507 break;
2508 }
edd16368
SC		 2509 break;
2510 }
edd16368
SC		 2511 /* Problem was not a check condition
2512 * Pass it up to the upper layers...
2513 */
2514 if (ei->ScsiStatus) {
2515 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2516 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2517 "Returning result: 0x%x\n",
2518 cp, ei->ScsiStatus,
2519 sense_key, asc, ascq,
2520 cmd->result);
2521 } else { /* scsi status is zero??? How??? */
2522 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2523 "Returning no connection.\n", cp),
2524
2525 /* Ordinarily, this case should never happen,
2526 * but there is a bug in some released firmware
2527 * revisions that allows it to happen if, for
2528 * example, a 4100 backplane loses power and
2529 * the tape drive is in it. We assume that
2530 * it's a fatal error of some kind because we
2531 * can't show that it wasn't. We will make it
2532 * look like selection timeout since that is
2533 * the most common reason for this to occur,
2534 * and it's severe enough.
2535 */
2536
2537 cmd->result = DID_NO_CONNECT << 16;
2538 }
2539 break;
2540
2541 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2542 break;
2543 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2544 dev_warn(&h->pdev->dev,
2545 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2546 break;
2547 case CMD_INVALID: {
2548 /* print_bytes(cp, sizeof(*cp), 1, 0);
2549 print_cmd(cp); */
2550 /* We get CMD_INVALID if you address a non-existent device
2551 * instead of a selection timeout (no response). You will
2552 * see this if you yank out a drive, then try to access it.
2553 * This is kind of a shame because it means that any other
2554 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2555 * missing target. */
2556 cmd->result = DID_NO_CONNECT << 16;
2557 }
2558 break;
2559 case CMD_PROTOCOL_ERR:
256d0eaa 2560 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2561 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2562 cp->Request.CDB);
edd16368
SC		 2563 break;
2564 case CMD_HARDWARE_ERR:
2565 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2566 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2567 cp->Request.CDB);
edd16368
SC		 2568 break;
2569 case CMD_CONNECTION_LOST:
2570 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2571 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2572 cp->Request.CDB);
edd16368
SC		 2573 break;
2574 case CMD_ABORTED:
a58e7e53
WS		 2575 /* Return now to avoid calling scsi_done(). */
2576 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2577 case CMD_ABORT_FAILED:
2578 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2579 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2580 cp->Request.CDB);
edd16368
SC		 2581 break;
2582 case CMD_UNSOLICITED_ABORT:
f6e76055 2583 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2584 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2585 cp->Request.CDB);
edd16368
SC		 2586 break;
2587 case CMD_TIMEOUT:
2588 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2589 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2590 cp->Request.CDB);
edd16368 2591 break;
1d5e2ed0
SC		 2592 case CMD_UNABORTABLE:
2593 cmd->result = DID_ERROR << 16;
2594 dev_warn(&h->pdev->dev, "Command unabortable\n");
2595 break;
9437ac43
SC		 2596 case CMD_TMF_STATUS:
2597 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2598 cmd->result = DID_ERROR << 16;
2599 break;
283b4a9b
SC		 2600 case CMD_IOACCEL_DISABLED:
2601 /* This only handles the direct pass-through case since RAID
2602 * offload is handled above. Just attempt a retry.
2603 */
2604 cmd->result = DID_SOFT_ERROR << 16;
2605 dev_warn(&h->pdev->dev,
2606 "cp %p had HP SSD Smart Path error\n", cp);
2607 break;
edd16368
SC		 2608 default:
2609 cmd->result = DID_ERROR << 16;
2610 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2611 cp, ei->CommandStatus);
2612 }
8a0ff92c
WS		 2613
2614 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2615}
2616
edd16368
SC		 2617static void hpsa_pci_unmap(struct pci_dev *pdev,
2618 struct CommandList *c, int sg_used, int data_direction)
2619{
2620 int i;
edd16368 2621
50a0decf
SC		 2622 for (i = 0; i < sg_used; i++)
2623 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2624 le32_to_cpu(c->SG[i].Len),
2625 data_direction);
edd16368
SC		 2626}
2627
a2dac136 2628static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2629 struct CommandList *cp,
2630 unsigned char *buf,
2631 size_t buflen,
2632 int data_direction)
2633{
01a02ffc 2634 u64 addr64;
edd16368
SC		 2635
2636 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2637 cp->Header.SGList = 0;
50a0decf 2638 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2639 return 0;
edd16368
SC		 2640 }
2641
50a0decf 2642 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2643 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2644 /* Prevent subsequent unmap of something never mapped */
eceaae18 2645 cp->Header.SGList = 0;
50a0decf 2646 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2647 return -1;
eceaae18 2648 }
50a0decf
SC		 2649 cp->SG[0].Addr = cpu_to_le64(addr64);
2650 cp->SG[0].Len = cpu_to_le32(buflen);
2651 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2652 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2653 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2654 return 0;
edd16368
SC		 2655}
2656
25163bd5
WS		 2657#define NO_TIMEOUT ((unsigned long) -1)
2658#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2659static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2660 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2661{
2662 DECLARE_COMPLETION_ONSTACK(wait);
2663
2664 c->waiting = &wait;
25163bd5
WS		 2665 __enqueue_cmd_and_start_io(h, c, reply_queue);
2666 if (timeout_msecs == NO_TIMEOUT) {
2667 /* TODO: get rid of this no-timeout thing */
2668 wait_for_completion_io(&wait);
2669 return IO_OK;
2670 }
2671 if (!wait_for_completion_io_timeout(&wait,
2672 msecs_to_jiffies(timeout_msecs))) {
2673 dev_warn(&h->pdev->dev, "Command timed out.\n");
2674 return -ETIMEDOUT;
2675 }
2676 return IO_OK;
2677}
2678
2679static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2680 int reply_queue, unsigned long timeout_msecs)
2681{
2682 if (unlikely(lockup_detected(h))) {
2683 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2684 return IO_OK;
2685 }
2686 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2687}
2688
094963da
SC		 2689static u32 lockup_detected(struct ctlr_info *h)
2690{
2691 int cpu;
2692 u32 rc, *lockup_detected;
2693
2694 cpu = get_cpu();
2695 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2696 rc = *lockup_detected;
2697 put_cpu();
2698 return rc;
2699}
2700
9c2fc160 2701#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2702static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2703 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2704{
9c2fc160 2705 int backoff_time = 10, retry_count = 0;
25163bd5 2706 int rc;
edd16368
SC		 2707
2708 do {
7630abd0 2709 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2710 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2711 timeout_msecs);
2712 if (rc)
2713 break;
edd16368 2714 retry_count++;
9c2fc160
SC		 2715 if (retry_count > 3) {
2716 msleep(backoff_time);
2717 if (backoff_time < 1000)
2718 backoff_time *= 2;
2719 }
852af20a 2720 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2721 check_for_busy(h, c)) &&
2722 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2723 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2724 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2725 rc = -EIO;
2726 return rc;
edd16368
SC		 2727}
2728
d1e8beac
SC		 2729static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2730 struct CommandList *c)
edd16368 2731{
d1e8beac
SC		 2732 const u8 *cdb = c->Request.CDB;
2733 const u8 *lun = c->Header.LUN.LunAddrBytes;
2734
2735 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2736 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2737 txt, lun[0], lun[1], lun[2], lun[3],
2738 lun[4], lun[5], lun[6], lun[7],
2739 cdb[0], cdb[1], cdb[2], cdb[3],
2740 cdb[4], cdb[5], cdb[6], cdb[7],
2741 cdb[8], cdb[9], cdb[10], cdb[11],
2742 cdb[12], cdb[13], cdb[14], cdb[15]);
2743}
2744
2745static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2746 struct CommandList *cp)
2747{
2748 const struct ErrorInfo *ei = cp->err_info;
edd16368 2749 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2750 u8 sense_key, asc, ascq;
2751 int sense_len;
edd16368 2752
edd16368
SC		 2753 switch (ei->CommandStatus) {
2754 case CMD_TARGET_STATUS:
9437ac43
SC		 2755 if (ei->SenseLen > sizeof(ei->SenseInfo))
2756 sense_len = sizeof(ei->SenseInfo);
2757 else
2758 sense_len = ei->SenseLen;
2759 decode_sense_data(ei->SenseInfo, sense_len,
2760 &sense_key, &asc, &ascq);
d1e8beac
SC		 2761 hpsa_print_cmd(h, "SCSI status", cp);
2762 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2763 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2764 sense_key, asc, ascq);
d1e8beac 2765 else
9437ac43 2766 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2767 if (ei->ScsiStatus == 0)
2768 dev_warn(d, "SCSI status is abnormally zero. "
2769 "(probably indicates selection timeout "
2770 "reported incorrectly due to a known "
2771 "firmware bug, circa July, 2001.)\n");
2772 break;
2773 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2774 break;
2775 case CMD_DATA_OVERRUN:
d1e8beac 2776 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2777 break;
2778 case CMD_INVALID: {
2779 /* controller unfortunately reports SCSI passthru's
2780 * to non-existent targets as invalid commands.
2781 */
d1e8beac
SC		 2782 hpsa_print_cmd(h, "invalid command", cp);
2783 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2784 }
2785 break;
2786 case CMD_PROTOCOL_ERR:
d1e8beac 2787 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2788 break;
2789 case CMD_HARDWARE_ERR:
d1e8beac 2790 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2791 break;
2792 case CMD_CONNECTION_LOST:
d1e8beac 2793 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2794 break;
2795 case CMD_ABORTED:
d1e8beac 2796 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2797 break;
2798 case CMD_ABORT_FAILED:
d1e8beac 2799 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2800 break;
2801 case CMD_UNSOLICITED_ABORT:
d1e8beac 2802 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2803 break;
2804 case CMD_TIMEOUT:
d1e8beac 2805 hpsa_print_cmd(h, "timed out", cp);
edd16368 2806 break;
1d5e2ed0 2807 case CMD_UNABORTABLE:
d1e8beac 2808 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2809 break;
25163bd5
WS		 2810 case CMD_CTLR_LOCKUP:
2811 hpsa_print_cmd(h, "controller lockup detected", cp);
2812 break;
edd16368 2813 default:
d1e8beac
SC		 2814 hpsa_print_cmd(h, "unknown status", cp);
2815 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2816 ei->CommandStatus);
2817 }
2818}
2819
2820static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2821 u16 page, unsigned char *buf,
edd16368
SC		 2822 unsigned char bufsize)
2823{
2824 int rc = IO_OK;
2825 struct CommandList *c;
2826 struct ErrorInfo *ei;
2827
45fcb86e 2828 c = cmd_alloc(h);
edd16368 2829
a2dac136
SC		 2830 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2831 page, scsi3addr, TYPE_CMD)) {
2832 rc = -1;
2833 goto out;
2834 }
25163bd5 2835 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 2836 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 2837 if (rc)
2838 goto out;
edd16368
SC		 2839 ei = c->err_info;
2840 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2841 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2842 rc = -1;
2843 }
a2dac136 2844out:
45fcb86e 2845 cmd_free(h, c);
edd16368
SC		 2846 return rc;
2847}
2848
bf711ac6 2849static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2850 u8 reset_type, int reply_queue)
edd16368
SC		 2851{
2852 int rc = IO_OK;
2853 struct CommandList *c;
2854 struct ErrorInfo *ei;
2855
45fcb86e 2856 c = cmd_alloc(h);
edd16368 2857
edd16368 2858
a2dac136 2859 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2860 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2861 scsi3addr, TYPE_MSG);
c448ecfa 2862 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
25163bd5
WS		 2863 if (rc) {
2864 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2865 goto out;
2866 }
edd16368
SC		 2867 /* no unmap needed here because no data xfer. */
2868
2869 ei = c->err_info;
2870 if (ei->CommandStatus != 0) {
d1e8beac 2871 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2872 rc = -1;
2873 }
25163bd5 2874out:
45fcb86e 2875 cmd_free(h, c);
edd16368
SC		 2876 return rc;
2877}
2878
d604f533
WS		 2879static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2880 struct hpsa_scsi_dev_t *dev,
2881 unsigned char *scsi3addr)
2882{
2883 int i;
2884 bool match = false;
2885 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2886 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2887
2888 if (hpsa_is_cmd_idle(c))
2889 return false;
2890
2891 switch (c->cmd_type) {
2892 case CMD_SCSI:
2893 case CMD_IOCTL_PEND:
2894 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2895 sizeof(c->Header.LUN.LunAddrBytes));
2896 break;
2897
2898 case CMD_IOACCEL1:
2899 case CMD_IOACCEL2:
2900 if (c->phys_disk == dev) {
2901 /* HBA mode match */
2902 match = true;
2903 } else {
2904 /* Possible RAID mode -- check each phys dev. */
2905 /* FIXME: Do we need to take out a lock here? If
2906 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2907 * instead. */
2908 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2909 /* FIXME: an alternate test might be
2910 *
2911 * match = dev->phys_disk[i]->ioaccel_handle
2912 * == c2->scsi_nexus; */
2913 match = dev->phys_disk[i] == c->phys_disk;
2914 }
2915 }
2916 break;
2917
2918 case IOACCEL2_TMF:
2919 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2920 match = dev->phys_disk[i]->ioaccel_handle ==
2921 le32_to_cpu(ac->it_nexus);
2922 }
2923 break;
2924
2925 case 0: /* The command is in the middle of being initialized. */
2926 match = false;
2927 break;
2928
2929 default:
2930 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2931 c->cmd_type);
2932 BUG();
2933 }
2934
2935 return match;
2936}
2937
2938static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2939 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2940{
2941 int i;
2942 int rc = 0;
2943
2944 /* We can really only handle one reset at a time */
2945 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2946 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2947 return -EINTR;
2948 }
2949
2950 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2951
2952 for (i = 0; i < h->nr_cmds; i++) {
2953 struct CommandList *c = h->cmd_pool + i;
2954 int refcount = atomic_inc_return(&c->refcount);
2955
2956 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2957 unsigned long flags;
2958
2959 /*
2960 * Mark the target command as having a reset pending,
2961 * then lock a lock so that the command cannot complete
2962 * while we're considering it. If the command is not
2963 * idle then count it; otherwise revoke the event.
2964 */
2965 c->reset_pending = dev;
2966 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2967 if (!hpsa_is_cmd_idle(c))
2968 atomic_inc(&dev->reset_cmds_out);
2969 else
2970 c->reset_pending = NULL;
2971 spin_unlock_irqrestore(&h->lock, flags);
2972 }
2973
2974 cmd_free(h, c);
2975 }
2976
2977 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2978 if (!rc)
2979 wait_event(h->event_sync_wait_queue,
2980 atomic_read(&dev->reset_cmds_out) == 0 ||
2981 lockup_detected(h));
2982
2983 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2984 dev_warn(&h->pdev->dev,
2985 "Controller lockup detected during reset wait\n");
2986 rc = -ENODEV;
2987 }
d604f533
WS		 2988
2989 if (unlikely(rc))
2990 atomic_set(&dev->reset_cmds_out, 0);
2991
2992 mutex_unlock(&h->reset_mutex);
2993 return rc;
2994}
2995
edd16368
SC		 2996static void hpsa_get_raid_level(struct ctlr_info *h,
2997 unsigned char *scsi3addr, unsigned char *raid_level)
2998{
2999 int rc;
3000 unsigned char *buf;
3001
3002 *raid_level = RAID_UNKNOWN;
3003 buf = kzalloc(64, GFP_KERNEL);
3004 if (!buf)
3005 return;
b7bb24eb 3006 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 3007 if (rc == 0)
3008 *raid_level = buf[8];
3009 if (*raid_level > RAID_UNKNOWN)
3010 *raid_level = RAID_UNKNOWN;
3011 kfree(buf);
3012 return;
3013}
3014
283b4a9b
SC		 3015#define HPSA_MAP_DEBUG
3016#ifdef HPSA_MAP_DEBUG
3017static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
3018 struct raid_map_data *map_buff)
3019{
3020 struct raid_map_disk_data *dd = &map_buff->data[0];
3021 int map, row, col;
3022 u16 map_cnt, row_cnt, disks_per_row;
3023
3024 if (rc != 0)
3025 return;
3026
2ba8bfc8
SC		 3027 /* Show details only if debugging has been activated. */
3028 if (h->raid_offload_debug < 2)
3029 return;
3030
283b4a9b
SC		 3031 dev_info(&h->pdev->dev, "structure_size = %u\n",
3032 le32_to_cpu(map_buff->structure_size));
3033 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3034 le32_to_cpu(map_buff->volume_blk_size));
3035 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3036 le64_to_cpu(map_buff->volume_blk_cnt));
3037 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3038 map_buff->phys_blk_shift);
3039 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3040 map_buff->parity_rotation_shift);
3041 dev_info(&h->pdev->dev, "strip_size = %u\n",
3042 le16_to_cpu(map_buff->strip_size));
3043 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3044 le64_to_cpu(map_buff->disk_starting_blk));
3045 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3046 le64_to_cpu(map_buff->disk_blk_cnt));
3047 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3048 le16_to_cpu(map_buff->data_disks_per_row));
3049 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3050 le16_to_cpu(map_buff->metadata_disks_per_row));
3051 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3052 le16_to_cpu(map_buff->row_cnt));
3053 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3054 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3055 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3056 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 3057 dev_info(&h->pdev->dev, "encrypytion = %s\n",
3058 le16_to_cpu(map_buff->flags) &
3059 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3060 dev_info(&h->pdev->dev, "dekindex = %u\n",
3061 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3062 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3063 for (map = 0; map < map_cnt; map++) {
3064 dev_info(&h->pdev->dev, "Map%u:\n", map);
3065 row_cnt = le16_to_cpu(map_buff->row_cnt);
3066 for (row = 0; row < row_cnt; row++) {
3067 dev_info(&h->pdev->dev, " Row%u:\n", row);
3068 disks_per_row =
3069 le16_to_cpu(map_buff->data_disks_per_row);
3070 for (col = 0; col < disks_per_row; col++, dd++)
3071 dev_info(&h->pdev->dev,
3072 " D%02u: h=0x%04x xor=%u,%u\n",
3073 col, dd->ioaccel_handle,
3074 dd->xor_mult[0], dd->xor_mult[1]);
3075 disks_per_row =
3076 le16_to_cpu(map_buff->metadata_disks_per_row);
3077 for (col = 0; col < disks_per_row; col++, dd++)
3078 dev_info(&h->pdev->dev,
3079 " M%02u: h=0x%04x xor=%u,%u\n",
3080 col, dd->ioaccel_handle,
3081 dd->xor_mult[0], dd->xor_mult[1]);
3082 }
3083 }
3084}
3085#else
3086static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3087 __attribute__((unused)) int rc,
3088 __attribute__((unused)) struct raid_map_data *map_buff)
3089{
3090}
3091#endif
3092
3093static int hpsa_get_raid_map(struct ctlr_info *h,
3094 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3095{
3096 int rc = 0;
3097 struct CommandList *c;
3098 struct ErrorInfo *ei;
3099
45fcb86e 3100 c = cmd_alloc(h);
bf43caf3 3101
283b4a9b
SC		 3102 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3103 sizeof(this_device->raid_map), 0,
3104 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3105 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3106 cmd_free(h, c);
3107 return -1;
283b4a9b 3108 }
25163bd5 3109 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3110 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3111 if (rc)
3112 goto out;
283b4a9b
SC		 3113 ei = c->err_info;
3114 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3115 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3116 rc = -1;
3117 goto out;
283b4a9b 3118 }
45fcb86e 3119 cmd_free(h, c);
283b4a9b
SC		 3120
3121 /* @todo in the future, dynamically allocate RAID map memory */
3122 if (le32_to_cpu(this_device->raid_map.structure_size) >
3123 sizeof(this_device->raid_map)) {
3124 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3125 rc = -1;
3126 }
3127 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3128 return rc;
25163bd5
WS		 3129out:
3130 cmd_free(h, c);
3131 return rc;
283b4a9b
SC		 3132}
3133
d04e62b9
KB		 3134static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3135 unsigned char scsi3addr[], u16 bmic_device_index,
3136 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3137{
3138 int rc = IO_OK;
3139 struct CommandList *c;
3140 struct ErrorInfo *ei;
3141
3142 c = cmd_alloc(h);
3143
3144 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3145 0, RAID_CTLR_LUNID, TYPE_CMD);
3146 if (rc)
3147 goto out;
3148
3149 c->Request.CDB[2] = bmic_device_index & 0xff;
3150 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3151
3152 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3153 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
d04e62b9
KB		 3154 if (rc)
3155 goto out;
3156 ei = c->err_info;
3157 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3158 hpsa_scsi_interpret_error(h, c);
3159 rc = -1;
3160 }
3161out:
3162 cmd_free(h, c);
3163 return rc;
3164}
3165
66749d0d
ST		 3166static int hpsa_bmic_id_controller(struct ctlr_info *h,
3167 struct bmic_identify_controller *buf, size_t bufsize)
3168{
3169 int rc = IO_OK;
3170 struct CommandList *c;
3171 struct ErrorInfo *ei;
3172
3173 c = cmd_alloc(h);
3174
3175 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3176 0, RAID_CTLR_LUNID, TYPE_CMD);
3177 if (rc)
3178 goto out;
3179
3180 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3181 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
66749d0d
ST		 3182 if (rc)
3183 goto out;
3184 ei = c->err_info;
3185 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3186 hpsa_scsi_interpret_error(h, c);
3187 rc = -1;
3188 }
3189out:
3190 cmd_free(h, c);
3191 return rc;
3192}
3193
03383736
DB		 3194static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3195 unsigned char scsi3addr[], u16 bmic_device_index,
3196 struct bmic_identify_physical_device *buf, size_t bufsize)
3197{
3198 int rc = IO_OK;
3199 struct CommandList *c;
3200 struct ErrorInfo *ei;
3201
3202 c = cmd_alloc(h);
3203 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3204 0, RAID_CTLR_LUNID, TYPE_CMD);
3205 if (rc)
3206 goto out;
3207
3208 c->Request.CDB[2] = bmic_device_index & 0xff;
3209 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3210
25163bd5 3211 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3212 DEFAULT_TIMEOUT);
03383736
DB		 3213 ei = c->err_info;
3214 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3215 hpsa_scsi_interpret_error(h, c);
3216 rc = -1;
3217 }
3218out:
3219 cmd_free(h, c);
d04e62b9 3220
03383736
DB		 3221 return rc;
3222}
3223
cca8f13b
DB		 3224/*
3225 * get enclosure information
3226 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3227 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3228 * Uses id_physical_device to determine the box_index.
3229 */
3230static void hpsa_get_enclosure_info(struct ctlr_info *h,
3231 unsigned char *scsi3addr,
3232 struct ReportExtendedLUNdata *rlep, int rle_index,
3233 struct hpsa_scsi_dev_t *encl_dev)
3234{
3235 int rc = -1;
3236 struct CommandList *c = NULL;
3237 struct ErrorInfo *ei = NULL;
3238 struct bmic_sense_storage_box_params *bssbp = NULL;
3239 struct bmic_identify_physical_device *id_phys = NULL;
3240 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3241 u16 bmic_device_index = 0;
3242
3243 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3244
17a9e54a
DB		 3245 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3246 rc = IO_OK;
cca8f13b 3247 goto out;
17a9e54a 3248 }
cca8f13b
DB		 3249
3250 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3251 if (!bssbp)
3252 goto out;
3253
3254 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3255 if (!id_phys)
3256 goto out;
3257
3258 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3259 id_phys, sizeof(*id_phys));
3260 if (rc) {
3261 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3262 __func__, encl_dev->external, bmic_device_index);
3263 goto out;
3264 }
3265
3266 c = cmd_alloc(h);
3267
3268 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3269 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3270
3271 if (rc)
3272 goto out;
3273
3274 if (id_phys->phys_connector[1] == 'E')
3275 c->Request.CDB[5] = id_phys->box_index;
3276 else
3277 c->Request.CDB[5] = 0;
3278
3279 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3280 DEFAULT_TIMEOUT);
cca8f13b
DB		 3281 if (rc)
3282 goto out;
3283
3284 ei = c->err_info;
3285 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3286 rc = -1;
3287 goto out;
3288 }
3289
3290 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3291 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3292 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3293
3294 rc = IO_OK;
3295out:
3296 kfree(bssbp);
3297 kfree(id_phys);
3298
3299 if (c)
3300 cmd_free(h, c);
3301
3302 if (rc != IO_OK)
3303 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
3304 "Error, could not get enclosure information\n");
3305}
3306
d04e62b9
KB		 3307static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3308 unsigned char *scsi3addr)
3309{
3310 struct ReportExtendedLUNdata *physdev;
3311 u32 nphysicals;
3312 u64 sa = 0;
3313 int i;
3314
3315 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3316 if (!physdev)
3317 return 0;
3318
3319 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3320 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3321 kfree(physdev);
3322 return 0;
3323 }
3324 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3325
3326 for (i = 0; i < nphysicals; i++)
3327 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3328 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3329 break;
3330 }
3331
3332 kfree(physdev);
3333
3334 return sa;
3335}
3336
3337static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3338 struct hpsa_scsi_dev_t *dev)
3339{
3340 int rc;
3341 u64 sa = 0;
3342
3343 if (is_hba_lunid(scsi3addr)) {
3344 struct bmic_sense_subsystem_info *ssi;
3345
3346 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
3347 if (ssi == NULL) {
3348 dev_warn(&h->pdev->dev,
3349 "%s: out of memory\n", __func__);
3350 return;
3351 }
3352
3353 rc = hpsa_bmic_sense_subsystem_information(h,
3354 scsi3addr, 0, ssi, sizeof(*ssi));
3355 if (rc == 0) {
3356 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3357 h->sas_address = sa;
3358 }
3359
3360 kfree(ssi);
3361 } else
3362 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3363
3364 dev->sas_address = sa;
3365}
3366
3367/* Get a device id from inquiry page 0x83 */
1b70150a
SC		 3368static int hpsa_vpd_page_supported(struct ctlr_info *h,
3369 unsigned char scsi3addr[], u8 page)
3370{
3371 int rc;
3372 int i;
3373 int pages;
3374 unsigned char *buf, bufsize;
3375
3376 buf = kzalloc(256, GFP_KERNEL);
3377 if (!buf)
3378 return 0;
3379
3380 /* Get the size of the page list first */
3381 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3382 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3383 buf, HPSA_VPD_HEADER_SZ);
3384 if (rc != 0)
3385 goto exit_unsupported;
3386 pages = buf[3];
3387 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3388 bufsize = pages + HPSA_VPD_HEADER_SZ;
3389 else
3390 bufsize = 255;
3391
3392 /* Get the whole VPD page list */
3393 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3394 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3395 buf, bufsize);
3396 if (rc != 0)
3397 goto exit_unsupported;
3398
3399 pages = buf[3];
3400 for (i = 1; i <= pages; i++)
3401 if (buf[3 + i] == page)
3402 goto exit_supported;
3403exit_unsupported:
3404 kfree(buf);
3405 return 0;
3406exit_supported:
3407 kfree(buf);
3408 return 1;
3409}
3410
283b4a9b
SC		 3411static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3412 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3413{
3414 int rc;
3415 unsigned char *buf;
3416 u8 ioaccel_status;
3417
3418 this_device->offload_config = 0;
3419 this_device->offload_enabled = 0;
41ce4c35 3420 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3421
3422 buf = kzalloc(64, GFP_KERNEL);
3423 if (!buf)
3424 return;
1b70150a
SC		 3425 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3426 goto out;
283b4a9b 3427 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3428 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3429 if (rc != 0)
3430 goto out;
3431
3432#define IOACCEL_STATUS_BYTE 4
3433#define OFFLOAD_CONFIGURED_BIT 0x01
3434#define OFFLOAD_ENABLED_BIT 0x02
3435 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3436 this_device->offload_config =
3437 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3438 if (this_device->offload_config) {
3439 this_device->offload_enabled =
3440 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3441 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3442 this_device->offload_enabled = 0;
3443 }
41ce4c35 3444 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3445out:
3446 kfree(buf);
3447 return;
3448}
3449
edd16368
SC		 3450/* Get the device id from inquiry page 0x83 */
3451static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3452 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3453{
3454 int rc;
3455 unsigned char *buf;
3456
3457 if (buflen > 16)
3458 buflen = 16;
3459 buf = kzalloc(64, GFP_KERNEL);
3460 if (!buf)
a84d794d 3461 return -ENOMEM;
b7bb24eb 3462 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368 3463 if (rc == 0)
75d23d89
DB		 3464 memcpy(device_id, &buf[index], buflen);
3465
edd16368 3466 kfree(buf);
75d23d89 3467
edd16368
SC		 3468 return rc != 0;
3469}
3470
3471static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3472 void *buf, int bufsize,
edd16368
SC		 3473 int extended_response)
3474{
3475 int rc = IO_OK;
3476 struct CommandList *c;
3477 unsigned char scsi3addr[8];
3478 struct ErrorInfo *ei;
3479
45fcb86e 3480 c = cmd_alloc(h);
bf43caf3 3481
e89c0ae7
SC		 3482 /* address the controller */
3483 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3484 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3485 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3486 rc = -1;
3487 goto out;
3488 }
edd16368
SC		 3489 if (extended_response)
3490 c->Request.CDB[1] = extended_response;
25163bd5 3491 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3492 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3493 if (rc)
3494 goto out;
edd16368
SC		 3495 ei = c->err_info;
3496 if (ei->CommandStatus != 0 &&
3497 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3498 hpsa_scsi_interpret_error(h, c);
edd16368 3499 rc = -1;
283b4a9b 3500 } else {
03383736
DB		 3501 struct ReportLUNdata *rld = buf;
3502
3503 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3504 dev_err(&h->pdev->dev,
3505 "report luns requested format %u, got %u\n",
3506 extended_response,
03383736 3507 rld->extended_response_flag);
283b4a9b
SC		 3508 rc = -1;
3509 }
edd16368 3510 }
a2dac136 3511out:
45fcb86e 3512 cmd_free(h, c);
edd16368
SC		 3513 return rc;
3514}
3515
3516static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3517 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3518{
03383736
DB		 3519 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3520 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3521}
3522
3523static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3524 struct ReportLUNdata *buf, int bufsize)
3525{
3526 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3527}
3528
3529static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3530 int bus, int target, int lun)
3531{
3532 device->bus = bus;
3533 device->target = target;
3534 device->lun = lun;
3535}
3536
9846590e
SC		 3537/* Use VPD inquiry to get details of volume status */
3538static int hpsa_get_volume_status(struct ctlr_info *h,
3539 unsigned char scsi3addr[])
3540{
3541 int rc;
3542 int status;
3543 int size;
3544 unsigned char *buf;
3545
3546 buf = kzalloc(64, GFP_KERNEL);
3547 if (!buf)
3548 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3549
3550 /* Does controller have VPD for logical volume status? */
24a4b078 3551 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3552 goto exit_failed;
9846590e
SC		 3553
3554 /* Get the size of the VPD return buffer */
3555 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3556 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3557 if (rc != 0)
9846590e 3558 goto exit_failed;
9846590e
SC		 3559 size = buf[3];
3560
3561 /* Now get the whole VPD buffer */
3562 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3563 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3564 if (rc != 0)
9846590e 3565 goto exit_failed;
9846590e
SC		 3566 status = buf[4]; /* status byte */
3567
3568 kfree(buf);
3569 return status;
3570exit_failed:
3571 kfree(buf);
3572 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3573}
3574
3575/* Determine offline status of a volume.
3576 * Return either:
3577 * 0 (not offline)
67955ba3 3578 * 0xff (offline for unknown reasons)
9846590e
SC		 3579 * # (integer code indicating one of several NOT READY states
3580 * describing why a volume is to be kept offline)
3581 */
67955ba3 3582static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3583 unsigned char scsi3addr[])
3584{
3585 struct CommandList *c;
9437ac43
SC		 3586 unsigned char *sense;
3587 u8 sense_key, asc, ascq;
3588 int sense_len;
25163bd5 3589 int rc, ldstat = 0;
9846590e
SC		 3590 u16 cmd_status;
3591 u8 scsi_status;
3592#define ASC_LUN_NOT_READY 0x04
3593#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3594#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3595
3596 c = cmd_alloc(h);
bf43caf3 3597
9846590e 3598 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
c448ecfa
DB		 3599 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3600 DEFAULT_TIMEOUT);
25163bd5
WS		 3601 if (rc) {
3602 cmd_free(h, c);
3603 return 0;
3604 }
9846590e 3605 sense = c->err_info->SenseInfo;
9437ac43
SC		 3606 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3607 sense_len = sizeof(c->err_info->SenseInfo);
3608 else
3609 sense_len = c->err_info->SenseLen;
3610 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3611 cmd_status = c->err_info->CommandStatus;
3612 scsi_status = c->err_info->ScsiStatus;
3613 cmd_free(h, c);
3614 /* Is the volume 'not ready'? */
3615 if (cmd_status != CMD_TARGET_STATUS ||
3616 scsi_status != SAM_STAT_CHECK_CONDITION ||
3617 sense_key != NOT_READY ||
3618 asc != ASC_LUN_NOT_READY) {
3619 return 0;
3620 }
3621
3622 /* Determine the reason for not ready state */
3623 ldstat = hpsa_get_volume_status(h, scsi3addr);
3624
3625 /* Keep volume offline in certain cases: */
3626 switch (ldstat) {
3627 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3628 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3629 case HPSA_LV_UNDERGOING_RPI:
3630 case HPSA_LV_PENDING_RPI:
3631 case HPSA_LV_ENCRYPTED_NO_KEY:
3632 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3633 case HPSA_LV_UNDERGOING_ENCRYPTION:
3634 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3635 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3636 return ldstat;
3637 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3638 /* If VPD status page isn't available,
3639 * use ASC/ASCQ to determine state
3640 */
3641 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3642 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3643 return ldstat;
3644 break;
3645 default:
3646 break;
3647 }
3648 return 0;
3649}
3650
9b5c48c2
SC		 3651/*
3652 * Find out if a logical device supports aborts by simply trying one.
3653 * Smart Array may claim not to support aborts on logical drives, but
3654 * if a MSA2000 * is connected, the drives on that will be presented
3655 * by the Smart Array as logical drives, and aborts may be sent to
3656 * those devices successfully. So the simplest way to find out is
3657 * to simply try an abort and see how the device responds.
3658 */
3659static int hpsa_device_supports_aborts(struct ctlr_info *h,
3660 unsigned char *scsi3addr)
3661{
3662 struct CommandList *c;
3663 struct ErrorInfo *ei;
3664 int rc = 0;
3665
3666 u64 tag = (u64) -1; /* bogus tag */
3667
3668 /* Assume that physical devices support aborts */
3669 if (!is_logical_dev_addr_mode(scsi3addr))
3670 return 1;
3671
3672 c = cmd_alloc(h);
bf43caf3 3673
9b5c48c2 3674 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
c448ecfa
DB		 3675 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3676 DEFAULT_TIMEOUT);
9b5c48c2
SC		 3677 /* no unmap needed here because no data xfer. */
3678 ei = c->err_info;
3679 switch (ei->CommandStatus) {
3680 case CMD_INVALID:
3681 rc = 0;
3682 break;
3683 case CMD_UNABORTABLE:
3684 case CMD_ABORT_FAILED:
3685 rc = 1;
3686 break;
9437ac43
SC		 3687 case CMD_TMF_STATUS:
3688 rc = hpsa_evaluate_tmf_status(h, c);
3689 break;
9b5c48c2
SC		 3690 default:
3691 rc = 0;
3692 break;
3693 }
3694 cmd_free(h, c);
3695 return rc;
3696}
3697
edd16368 3698static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3699 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3700 unsigned char *is_OBDR_device)
edd16368 3701{
0b0e1d6c
SC		 3702
3703#define OBDR_SIG_OFFSET 43
3704#define OBDR_TAPE_SIG "$DR-10"
3705#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3706#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3707
ea6d3bc3 3708 unsigned char *inq_buff;
0b0e1d6c 3709 unsigned char *obdr_sig;
683fc444 3710 int rc = 0;
edd16368 3711
ea6d3bc3 3712 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3713 if (!inq_buff) {
3714 rc = -ENOMEM;
edd16368 3715 goto bail_out;
683fc444 3716 }
edd16368 3717
edd16368
SC		 3718 /* Do an inquiry to the device to see what it is. */
3719 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3720 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3721 /* Inquiry failed (msg printed already) */
3722 dev_err(&h->pdev->dev,
3723 "hpsa_update_device_info: inquiry failed\n");
683fc444 3724 rc = -EIO;
edd16368
SC		 3725 goto bail_out;
3726 }
3727
4af61e4f
DB		 3728 scsi_sanitize_inquiry_string(&inq_buff[8], 8);
3729 scsi_sanitize_inquiry_string(&inq_buff[16], 16);
75d23d89 3730
edd16368
SC		 3731 this_device->devtype = (inq_buff[0] & 0x1f);
3732 memcpy(this_device->scsi3addr, scsi3addr, 8);
3733 memcpy(this_device->vendor, &inq_buff[8],
3734 sizeof(this_device->vendor));
3735 memcpy(this_device->model, &inq_buff[16],
3736 sizeof(this_device->model));
edd16368
SC		 3737 memset(this_device->device_id, 0,
3738 sizeof(this_device->device_id));
75d23d89 3739 hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
edd16368
SC		 3740 sizeof(this_device->device_id));
3741
af15ed36
DB		 3742 if ((this_device->devtype == TYPE_DISK ||
3743 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3744 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3745 int volume_offline;
3746
edd16368 3747 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3748 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3749 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3750 volume_offline = hpsa_volume_offline(h, scsi3addr);
3751 if (volume_offline < 0 || volume_offline > 0xff)
3752 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3753 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3754 } else {
edd16368 3755 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3756 this_device->offload_config = 0;
3757 this_device->offload_enabled = 0;
41ce4c35 3758 this_device->offload_to_be_enabled = 0;
a3144e0b 3759 this_device->hba_ioaccel_enabled = 0;
9846590e 3760 this_device->volume_offline = 0;
03383736 3761 this_device->queue_depth = h->nr_cmds;
283b4a9b 3762 }
edd16368 3763
0b0e1d6c
SC		 3764 if (is_OBDR_device) {
3765 /* See if this is a One-Button-Disaster-Recovery device
3766 * by looking for "$DR-10" at offset 43 in inquiry data.
3767 */
3768 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3769 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3770 strncmp(obdr_sig, OBDR_TAPE_SIG,
3771 OBDR_SIG_LEN) == 0);
3772 }
edd16368
SC		 3773 kfree(inq_buff);
3774 return 0;
3775
3776bail_out:
3777 kfree(inq_buff);
683fc444 3778 return rc;
edd16368
SC		 3779}
3780
9b5c48c2
SC		 3781static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3782 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3783{
3784 unsigned long flags;
3785 int rc, entry;
3786 /*
3787 * See if this device supports aborts. If we already know
3788 * the device, we already know if it supports aborts, otherwise
3789 * we have to find out if it supports aborts by trying one.
3790 */
3791 spin_lock_irqsave(&h->devlock, flags);
3792 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3793 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3794 entry >= 0 && entry < h->ndevices) {
3795 dev->supports_aborts = h->dev[entry]->supports_aborts;
3796 spin_unlock_irqrestore(&h->devlock, flags);
3797 } else {
3798 spin_unlock_irqrestore(&h->devlock, flags);
3799 dev->supports_aborts =
3800 hpsa_device_supports_aborts(h, scsi3addr);
3801 if (dev->supports_aborts < 0)
3802 dev->supports_aborts = 0;
3803 }
3804}
3805
c795505a
KB		 3806/*
3807 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3808 * Logical drive target and lun are assigned at this time, but
3809 * physical device lun and target assignment are deferred (assigned
3810 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3811*/
edd16368 3812static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3813 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3814{
c795505a 3815 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3816
3817 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3818 /* physical device, target and lun filled in later */
edd16368 3819 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3820 hpsa_set_bus_target_lun(device,
3821 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3822 else
1f310bde 3823 /* defer target, lun assignment for physical devices */
c795505a
KB		 3824 hpsa_set_bus_target_lun(device,
3825 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3826 return;
3827 }
3828 /* It's a logical device */
66749d0d 3829 if (device->external) {
1f310bde 3830 hpsa_set_bus_target_lun(device,
c795505a
KB		 3831 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3832 lunid & 0x00ff);
1f310bde 3833 return;
edd16368 3834 }
c795505a
KB		 3835 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3836 0, lunid & 0x3fff);
edd16368
SC		 3837}
3838
edd16368 3839
54b6e9e9
ST		 3840/*
3841 * Get address of physical disk used for an ioaccel2 mode command:
3842 * 1. Extract ioaccel2 handle from the command.
3843 * 2. Find a matching ioaccel2 handle from list of physical disks.
3844 * 3. Return:
3845 * 1 and set scsi3addr to address of matching physical
3846 * 0 if no matching physical disk was found.
3847 */
3848static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3849 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3850{
41ce4c35
SC		 3851 struct io_accel2_cmd *c2 =
3852 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3853 unsigned long flags;
54b6e9e9 3854 int i;
54b6e9e9 3855
41ce4c35
SC		 3856 spin_lock_irqsave(&h->devlock, flags);
3857 for (i = 0; i < h->ndevices; i++)
3858 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3859 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3860 sizeof(h->dev[i]->scsi3addr));
3861 spin_unlock_irqrestore(&h->devlock, flags);
3862 return 1;
3863 }
3864 spin_unlock_irqrestore(&h->devlock, flags);
3865 return 0;
54b6e9e9 3866}
41ce4c35 3867
66749d0d
ST		 3868static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3869 int i, int nphysicals, int nlocal_logicals)
3870{
3871 /* In report logicals, local logicals are listed first,
3872 * then any externals.
3873 */
3874 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3875
3876 if (i == raid_ctlr_position)
3877 return 0;
3878
3879 if (i < logicals_start)
3880 return 0;
3881
3882 /* i is in logicals range, but still within local logicals */
3883 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3884 return 0;
3885
3886 return 1; /* it's an external lun */
3887}
3888
edd16368
SC		 3889/*
3890 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3891 * logdev. The number of luns in physdev and logdev are returned in
3892 * *nphysicals and *nlogicals, respectively.
3893 * Returns 0 on success, -1 otherwise.
3894 */
3895static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3896 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3897 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3898{
03383736 3899 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3900 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3901 return -1;
3902 }
03383736 3903 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3904 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3905 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3906 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3907 *nphysicals = HPSA_MAX_PHYS_LUN;
3908 }
03383736 3909 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3910 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3911 return -1;
3912 }
6df1e954 3913 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3914 /* Reject Logicals in excess of our max capability. */
3915 if (*nlogicals > HPSA_MAX_LUN) {
3916 dev_warn(&h->pdev->dev,
3917 "maximum logical LUNs (%d) exceeded. "
3918 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3919 *nlogicals - HPSA_MAX_LUN);
3920 *nlogicals = HPSA_MAX_LUN;
3921 }
3922 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3923 dev_warn(&h->pdev->dev,
3924 "maximum logical + physical LUNs (%d) exceeded. "
3925 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3926 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3927 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3928 }
3929 return 0;
3930}
3931
42a91641
DB		 3932static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3933 int i, int nphysicals, int nlogicals,
a93aa1fe 3934 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3935 struct ReportLUNdata *logdev_list)
3936{
3937 /* Helper function, figure out where the LUN ID info is coming from
3938 * given index i, lists of physical and logical devices, where in
3939 * the list the raid controller is supposed to appear (first or last)
3940 */
3941
3942 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3943 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3944
3945 if (i == raid_ctlr_position)
3946 return RAID_CTLR_LUNID;
3947
3948 if (i < logicals_start)
d5b5d964
SC		 3949 return &physdev_list->LUN[i -
3950 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3951
3952 if (i < last_device)
3953 return &logdev_list->LUN[i - nphysicals -
3954 (raid_ctlr_position == 0)][0];
3955 BUG();
3956 return NULL;
3957}
3958
03383736
DB		 3959/* get physical drive ioaccel handle and queue depth */
3960static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3961 struct hpsa_scsi_dev_t *dev,
f2039b03 3962 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 3963 struct bmic_identify_physical_device *id_phys)
3964{
3965 int rc;
f2039b03 3966 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 3967
3968 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 3969 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 3970 dev->hba_ioaccel_enabled = 1;
03383736 3971 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 3972 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3973 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 3974 sizeof(*id_phys));
3975 if (!rc)
3976 /* Reserve space for FW operations */
3977#define DRIVE_CMDS_RESERVED_FOR_FW 2
3978#define DRIVE_QUEUE_DEPTH 7
3979 dev->queue_depth =
3980 le16_to_cpu(id_phys->current_queue_depth_limit) -
3981 DRIVE_CMDS_RESERVED_FOR_FW;
3982 else
3983 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3984}
3985
8270b862 3986static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 3987 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 3988 struct bmic_identify_physical_device *id_phys)
3989{
f2039b03
DB		 3990 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3991
3992 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 3993 this_device->hba_ioaccel_enabled = 1;
3994
3995 memcpy(&this_device->active_path_index,
3996 &id_phys->active_path_number,
3997 sizeof(this_device->active_path_index));
3998 memcpy(&this_device->path_map,
3999 &id_phys->redundant_path_present_map,
4000 sizeof(this_device->path_map));
4001 memcpy(&this_device->box,
4002 &id_phys->alternate_paths_phys_box_on_port,
4003 sizeof(this_device->box));
4004 memcpy(&this_device->phys_connector,
4005 &id_phys->alternate_paths_phys_connector,
4006 sizeof(this_device->phys_connector));
4007 memcpy(&this_device->bay,
4008 &id_phys->phys_bay_in_box,
4009 sizeof(this_device->bay));
4010}
4011
66749d0d
ST		 4012/* get number of local logical disks. */
4013static int hpsa_set_local_logical_count(struct ctlr_info *h,
4014 struct bmic_identify_controller *id_ctlr,
4015 u32 *nlocals)
4016{
4017 int rc;
4018
4019 if (!id_ctlr) {
4020 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4021 __func__);
4022 return -ENOMEM;
4023 }
4024 memset(id_ctlr, 0, sizeof(*id_ctlr));
4025 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4026 if (!rc)
4027 if (id_ctlr->configured_logical_drive_count < 256)
4028 *nlocals = id_ctlr->configured_logical_drive_count;
4029 else
4030 *nlocals = le16_to_cpu(
4031 id_ctlr->extended_logical_unit_count);
4032 else
4033 *nlocals = -1;
4034 return rc;
4035}
4036
4037
8aa60681 4038static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4039{
4040 /* the idea here is we could get notified
4041 * that some devices have changed, so we do a report
4042 * physical luns and report logical luns cmd, and adjust
4043 * our list of devices accordingly.
4044 *
4045 * The scsi3addr's of devices won't change so long as the
4046 * adapter is not reset. That means we can rescan and
4047 * tell which devices we already know about, vs. new
4048 * devices, vs. disappearing devices.
4049 */
a93aa1fe 4050 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4051 struct ReportLUNdata *logdev_list = NULL;
03383736 4052 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4053 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4054 u32 nphysicals = 0;
4055 u32 nlogicals = 0;
66749d0d 4056 u32 nlocal_logicals = 0;
01a02ffc 4057 u32 ndev_allocated = 0;
edd16368
SC		 4058 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4059 int ncurrent = 0;
4f4eb9f1 4060 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4061 int raid_ctlr_position;
04fa2f44 4062 bool physical_device;
aca4a520 4063 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4064
cfe5badc 4065 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 4066 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4067 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4068 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4069 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4070 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4071
03383736 4072 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4073 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4074 dev_err(&h->pdev->dev, "out of memory\n");
4075 goto out;
4076 }
4077 memset(lunzerobits, 0, sizeof(lunzerobits));
4078
853633e8
DB		 4079 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4080
03383736 4081 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4082 logdev_list, &nlogicals)) {
4083 h->drv_req_rescan = 1;
edd16368 4084 goto out;
853633e8 4085 }
edd16368 4086
66749d0d
ST		 4087 /* Set number of local logicals (non PTRAID) */
4088 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4089 dev_warn(&h->pdev->dev,
4090 "%s: Can't determine number of local logical devices.\n",
4091 __func__);
4092 }
edd16368 4093
aca4a520
ST		 4094 /* We might see up to the maximum number of logical and physical disks
4095 * plus external target devices, and a device for the local RAID
4096 * controller.
edd16368 4097 */
aca4a520 4098 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 4099
4100 /* Allocate the per device structures */
4101 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4102 if (i >= HPSA_MAX_DEVICES) {
4103 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4104 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4105 ndevs_to_allocate - HPSA_MAX_DEVICES);
4106 break;
4107 }
4108
edd16368
SC		 4109 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4110 if (!currentsd[i]) {
4111 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
4112 __FILE__, __LINE__);
853633e8 4113 h->drv_req_rescan = 1;
edd16368
SC		 4114 goto out;
4115 }
4116 ndev_allocated++;
4117 }
4118
8645291b 4119 if (is_scsi_rev_5(h))
339b2b14
SC		 4120 raid_ctlr_position = 0;
4121 else
4122 raid_ctlr_position = nphysicals + nlogicals;
4123
edd16368 4124 /* adjust our table of devices */
4f4eb9f1 4125 n_ext_target_devs = 0;
edd16368 4126 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4127 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4128 int rc = 0;
f2039b03 4129 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 4130
04fa2f44 4131 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4132
4133 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4134 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4135 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 4136
4137 /* skip masked non-disk devices */
04fa2f44 4138 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
cca8f13b
DB		 4139 (physdev_list->LUN[phys_dev_index].device_type != 0x06) &&
4140 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
04fa2f44 4141 continue;
edd16368
SC		 4142
4143 /* Get device type, vendor, model, device id */
683fc444
DB		 4144 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4145 &is_OBDR);
4146 if (rc == -ENOMEM) {
4147 dev_warn(&h->pdev->dev,
4148 "Out of memory, rescan deferred.\n");
853633e8 4149 h->drv_req_rescan = 1;
683fc444 4150 goto out;
853633e8 4151 }
683fc444
DB		 4152 if (rc) {
4153 dev_warn(&h->pdev->dev,
4154 "Inquiry failed, skipping device.\n");
4155 continue;
4156 }
4157
66749d0d
ST		 4158 /* Determine if this is a lun from an external target array */
4159 tmpdevice->external =
4160 figure_external_status(h, raid_ctlr_position, i,
4161 nphysicals, nlocal_logicals);
4162
1f310bde 4163 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 4164 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 4165 this_device = currentsd[ncurrent];
4166
34592254
ST		 4167 /* Turn on discovery_polling if there are ext target devices.
4168 * Event-based change notification is unreliable for those.
edd16368 4169 */
34592254
ST		 4170 if (!h->discovery_polling) {
4171 if (tmpdevice->external) {
4172 h->discovery_polling = 1;
4173 dev_info(&h->pdev->dev,
4174 "External target, activate discovery polling.\n");
4175 }
edd16368
SC		 4176 }
4177
34592254 4178
edd16368 4179 *this_device = *tmpdevice;
04fa2f44 4180 this_device->physical_device = physical_device;
edd16368 4181
04fa2f44
KB		 4182 /*
4183 * Expose all devices except for physical devices that
4184 * are masked.
4185 */
4186 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4187 this_device->expose_device = 0;
4188 else
4189 this_device->expose_device = 1;
41ce4c35 4190
d04e62b9
KB		 4191
4192 /*
4193 * Get the SAS address for physical devices that are exposed.
4194 */
4195 if (this_device->physical_device && this_device->expose_device)
4196 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4197
edd16368 4198 switch (this_device->devtype) {
0b0e1d6c 4199 case TYPE_ROM:
edd16368
SC		 4200 /* We don't *really* support actual CD-ROM devices,
4201 * just "One Button Disaster Recovery" tape drive
4202 * which temporarily pretends to be a CD-ROM drive.
4203 * So we check that the device is really an OBDR tape
4204 * device by checking for "$DR-10" in bytes 43-48 of
4205 * the inquiry data.
4206 */
0b0e1d6c
SC		 4207 if (is_OBDR)
4208 ncurrent++;
edd16368
SC		 4209 break;
4210 case TYPE_DISK:
af15ed36 4211 case TYPE_ZBC:
04fa2f44 4212 if (this_device->physical_device) {
b9092b79
KB		 4213 /* The disk is in HBA mode. */
4214 /* Never use RAID mapper in HBA mode. */
ecf418d1 4215 this_device->offload_enabled = 0;
b9092b79 4216 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4217 physdev_list, phys_dev_index, id_phys);
4218 hpsa_get_path_info(this_device,
4219 physdev_list, phys_dev_index, id_phys);
b9092b79 4220 }
ecf418d1 4221 ncurrent++;
edd16368
SC		 4222 break;
4223 case TYPE_TAPE:
4224 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4225 ncurrent++;
4226 break;
41ce4c35 4227 case TYPE_ENCLOSURE:
17a9e54a
DB		 4228 if (!this_device->external)
4229 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4230 physdev_list, phys_dev_index,
4231 this_device);
b9092b79 4232 ncurrent++;
41ce4c35 4233 break;
edd16368
SC		 4234 case TYPE_RAID:
4235 /* Only present the Smartarray HBA as a RAID controller.
4236 * If it's a RAID controller other than the HBA itself
4237 * (an external RAID controller, MSA500 or similar)
4238 * don't present it.
4239 */
4240 if (!is_hba_lunid(lunaddrbytes))
4241 break;
4242 ncurrent++;
4243 break;
4244 default:
4245 break;
4246 }
cfe5badc 4247 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4248 break;
4249 }
d04e62b9
KB		 4250
4251 if (h->sas_host == NULL) {
4252 int rc = 0;
4253
4254 rc = hpsa_add_sas_host(h);
4255 if (rc) {
4256 dev_warn(&h->pdev->dev,
4257 "Could not add sas host %d\n", rc);
4258 goto out;
4259 }
4260 }
4261
8aa60681 4262 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4263out:
4264 kfree(tmpdevice);
4265 for (i = 0; i < ndev_allocated; i++)
4266 kfree(currentsd[i]);
4267 kfree(currentsd);
edd16368
SC		 4268 kfree(physdev_list);
4269 kfree(logdev_list);
66749d0d 4270 kfree(id_ctlr);
03383736 4271 kfree(id_phys);
edd16368
SC		 4272}
4273
ec5cbf04
WS		 4274static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4275 struct scatterlist *sg)
4276{
4277 u64 addr64 = (u64) sg_dma_address(sg);
4278 unsigned int len = sg_dma_len(sg);
4279
4280 desc->Addr = cpu_to_le64(addr64);
4281 desc->Len = cpu_to_le32(len);
4282 desc->Ext = 0;
4283}
4284
c7ee65b3
WS		 4285/*
4286 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4287 * dma mapping and fills in the scatter gather entries of the
4288 * hpsa command, cp.
4289 */
33a2ffce 4290static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4291 struct CommandList *cp,
4292 struct scsi_cmnd *cmd)
4293{
edd16368 4294 struct scatterlist *sg;
b3a7ba7c 4295 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4296 struct SGDescriptor *curr_sg;
edd16368 4297
33a2ffce 4298 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4299
4300 use_sg = scsi_dma_map(cmd);
4301 if (use_sg < 0)
4302 return use_sg;
4303
4304 if (!use_sg)
4305 goto sglist_finished;
4306
b3a7ba7c
WS		 4307 /*
4308 * If the number of entries is greater than the max for a single list,
4309 * then we have a chained list; we will set up all but one entry in the
4310 * first list (the last entry is saved for link information);
4311 * otherwise, we don't have a chained list and we'll set up at each of
4312 * the entries in the one list.
4313 */
33a2ffce 4314 curr_sg = cp->SG;
b3a7ba7c
WS		 4315 chained = use_sg > h->max_cmd_sg_entries;
4316 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4317 last_sg = scsi_sg_count(cmd) - 1;
4318 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4319 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4320 curr_sg++;
4321 }
ec5cbf04 4322
b3a7ba7c
WS		 4323 if (chained) {
4324 /*
4325 * Continue with the chained list. Set curr_sg to the chained
4326 * list. Modify the limit to the total count less the entries
4327 * we've already set up. Resume the scan at the list entry
4328 * where the previous loop left off.
4329 */
4330 curr_sg = h->cmd_sg_list[cp->cmdindex];
4331 sg_limit = use_sg - sg_limit;
4332 for_each_sg(sg, sg, sg_limit, i) {
4333 hpsa_set_sg_descriptor(curr_sg, sg);
4334 curr_sg++;
4335 }
4336 }
4337
ec5cbf04 4338 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4339 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4340
4341 if (use_sg + chained > h->maxSG)
4342 h->maxSG = use_sg + chained;
4343
4344 if (chained) {
4345 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4346 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4347 if (hpsa_map_sg_chain_block(h, cp)) {
4348 scsi_dma_unmap(cmd);
4349 return -1;
4350 }
33a2ffce 4351 return 0;
edd16368
SC		 4352 }
4353
4354sglist_finished:
4355
01a02ffc 4356 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4357 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4358 return 0;
4359}
4360
283b4a9b
SC		 4361#define IO_ACCEL_INELIGIBLE (1)
4362static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4363{
4364 int is_write = 0;
4365 u32 block;
4366 u32 block_cnt;
4367
4368 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4369 switch (cdb[0]) {
4370 case WRITE_6:
4371 case WRITE_12:
4372 is_write = 1;
4373 case READ_6:
4374 case READ_12:
4375 if (*cdb_len == 6) {
c8a6c9a6 4376 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4377 block_cnt = cdb[4];
c8a6c9a6
DB		 4378 if (block_cnt == 0)
4379 block_cnt = 256;
283b4a9b
SC		 4380 } else {
4381 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4382 block = get_unaligned_be32(&cdb[2]);
4383 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4384 }
4385 if (block_cnt > 0xffff)
4386 return IO_ACCEL_INELIGIBLE;
4387
4388 cdb[0] = is_write ? WRITE_10 : READ_10;
4389 cdb[1] = 0;
4390 cdb[2] = (u8) (block >> 24);
4391 cdb[3] = (u8) (block >> 16);
4392 cdb[4] = (u8) (block >> 8);
4393 cdb[5] = (u8) (block);
4394 cdb[6] = 0;
4395 cdb[7] = (u8) (block_cnt >> 8);
4396 cdb[8] = (u8) (block_cnt);
4397 cdb[9] = 0;
4398 *cdb_len = 10;
4399 break;
4400 }
4401 return 0;
4402}
4403
c349775e 4404static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4405 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4406 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4407{
4408 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4409 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4410 unsigned int len;
4411 unsigned int total_len = 0;
4412 struct scatterlist *sg;
4413 u64 addr64;
4414 int use_sg, i;
4415 struct SGDescriptor *curr_sg;
4416 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4417
283b4a9b 4418 /* TODO: implement chaining support */
03383736
DB		 4419 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4420 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4421 return IO_ACCEL_INELIGIBLE;
03383736 4422 }
283b4a9b 4423
e1f7de0c
MG		 4424 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4425
03383736
DB		 4426 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4427 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4428 return IO_ACCEL_INELIGIBLE;
03383736 4429 }
283b4a9b 4430
e1f7de0c
MG		 4431 c->cmd_type = CMD_IOACCEL1;
4432
4433 /* Adjust the DMA address to point to the accelerated command buffer */
4434 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4435 (c->cmdindex * sizeof(*cp));
4436 BUG_ON(c->busaddr & 0x0000007F);
4437
4438 use_sg = scsi_dma_map(cmd);
03383736
DB		 4439 if (use_sg < 0) {
4440 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4441 return use_sg;
03383736 4442 }
e1f7de0c
MG		 4443
4444 if (use_sg) {
4445 curr_sg = cp->SG;
4446 scsi_for_each_sg(cmd, sg, use_sg, i) {
4447 addr64 = (u64) sg_dma_address(sg);
4448 len = sg_dma_len(sg);
4449 total_len += len;
50a0decf
SC		 4450 curr_sg->Addr = cpu_to_le64(addr64);
4451 curr_sg->Len = cpu_to_le32(len);
4452 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4453 curr_sg++;
4454 }
50a0decf 4455 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4456
4457 switch (cmd->sc_data_direction) {
4458 case DMA_TO_DEVICE:
4459 control |= IOACCEL1_CONTROL_DATA_OUT;
4460 break;
4461 case DMA_FROM_DEVICE:
4462 control |= IOACCEL1_CONTROL_DATA_IN;
4463 break;
4464 case DMA_NONE:
4465 control |= IOACCEL1_CONTROL_NODATAXFER;
4466 break;
4467 default:
4468 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4469 cmd->sc_data_direction);
4470 BUG();
4471 break;
4472 }
4473 } else {
4474 control |= IOACCEL1_CONTROL_NODATAXFER;
4475 }
4476
c349775e 4477 c->Header.SGList = use_sg;
e1f7de0c 4478 /* Fill out the command structure to submit */
2b08b3e9
DB		 4479 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4480 cp->transfer_len = cpu_to_le32(total_len);
4481 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4482 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4483 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4484 memcpy(cp->CDB, cdb, cdb_len);
4485 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4486 /* Tag was already set at init time. */
283b4a9b 4487 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4488 return 0;
4489}
edd16368 4490
283b4a9b
SC		 4491/*
4492 * Queue a command directly to a device behind the controller using the
4493 * I/O accelerator path.
4494 */
4495static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4496 struct CommandList *c)
4497{
4498 struct scsi_cmnd *cmd = c->scsi_cmd;
4499 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4500
03383736
DB		 4501 c->phys_disk = dev;
4502
283b4a9b 4503 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4504 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4505}
4506
dd0e19f3
ST		 4507/*
4508 * Set encryption parameters for the ioaccel2 request
4509 */
4510static void set_encrypt_ioaccel2(struct ctlr_info *h,
4511 struct CommandList *c, struct io_accel2_cmd *cp)
4512{
4513 struct scsi_cmnd *cmd = c->scsi_cmd;
4514 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4515 struct raid_map_data *map = &dev->raid_map;
4516 u64 first_block;
4517
dd0e19f3 4518 /* Are we doing encryption on this device */
2b08b3e9 4519 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4520 return;
4521 /* Set the data encryption key index. */
4522 cp->dekindex = map->dekindex;
4523
4524 /* Set the encryption enable flag, encoded into direction field. */
4525 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4526
4527 /* Set encryption tweak values based on logical block address
4528 * If block size is 512, tweak value is LBA.
4529 * For other block sizes, tweak is (LBA * block size)/ 512)
4530 */
4531 switch (cmd->cmnd[0]) {
4532 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4533 case WRITE_6:
4534 case READ_6:
2b08b3e9 4535 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4536 break;
4537 case WRITE_10:
4538 case READ_10:
dd0e19f3
ST		 4539 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4540 case WRITE_12:
4541 case READ_12:
2b08b3e9 4542 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4543 break;
4544 case WRITE_16:
4545 case READ_16:
2b08b3e9 4546 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4547 break;
4548 default:
4549 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4550 "ERROR: %s: size (0x%x) not supported for encryption\n",
4551 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4552 BUG();
4553 break;
4554 }
2b08b3e9
DB		 4555
4556 if (le32_to_cpu(map->volume_blk_size) != 512)
4557 first_block = first_block *
4558 le32_to_cpu(map->volume_blk_size)/512;
4559
4560 cp->tweak_lower = cpu_to_le32(first_block);
4561 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4562}
4563
c349775e
ST		 4564static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4565 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4566 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4567{
4568 struct scsi_cmnd *cmd = c->scsi_cmd;
4569 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4570 struct ioaccel2_sg_element *curr_sg;
4571 int use_sg, i;
4572 struct scatterlist *sg;
4573 u64 addr64;
4574 u32 len;
4575 u32 total_len = 0;
4576
d9a729f3 4577 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4578
03383736
DB		 4579 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4580 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4581 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4582 }
4583
c349775e
ST		 4584 c->cmd_type = CMD_IOACCEL2;
4585 /* Adjust the DMA address to point to the accelerated command buffer */
4586 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4587 (c->cmdindex * sizeof(*cp));
4588 BUG_ON(c->busaddr & 0x0000007F);
4589
4590 memset(cp, 0, sizeof(*cp));
4591 cp->IU_type = IOACCEL2_IU_TYPE;
4592
4593 use_sg = scsi_dma_map(cmd);
03383736
DB		 4594 if (use_sg < 0) {
4595 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4596 return use_sg;
03383736 4597 }
c349775e
ST		 4598
4599 if (use_sg) {
c349775e 4600 curr_sg = cp->sg;
d9a729f3
WS		 4601 if (use_sg > h->ioaccel_maxsg) {
4602 addr64 = le64_to_cpu(
4603 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4604 curr_sg->address = cpu_to_le64(addr64);
4605 curr_sg->length = 0;
4606 curr_sg->reserved[0] = 0;
4607 curr_sg->reserved[1] = 0;
4608 curr_sg->reserved[2] = 0;
4609 curr_sg->chain_indicator = 0x80;
4610
4611 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4612 }
c349775e
ST		 4613 scsi_for_each_sg(cmd, sg, use_sg, i) {
4614 addr64 = (u64) sg_dma_address(sg);
4615 len = sg_dma_len(sg);
4616 total_len += len;
4617 curr_sg->address = cpu_to_le64(addr64);
4618 curr_sg->length = cpu_to_le32(len);
4619 curr_sg->reserved[0] = 0;
4620 curr_sg->reserved[1] = 0;
4621 curr_sg->reserved[2] = 0;
4622 curr_sg->chain_indicator = 0;
4623 curr_sg++;
4624 }
4625
4626 switch (cmd->sc_data_direction) {
4627 case DMA_TO_DEVICE:
dd0e19f3
ST		 4628 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4629 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4630 break;
4631 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4632 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4633 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4634 break;
4635 case DMA_NONE:
dd0e19f3
ST		 4636 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4637 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4638 break;
4639 default:
4640 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4641 cmd->sc_data_direction);
4642 BUG();
4643 break;
4644 }
4645 } else {
dd0e19f3
ST		 4646 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4647 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4648 }
dd0e19f3
ST		 4649
4650 /* Set encryption parameters, if necessary */
4651 set_encrypt_ioaccel2(h, c, cp);
4652
2b08b3e9 4653 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4654 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4655 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4656
c349775e
ST		 4657 cp->data_len = cpu_to_le32(total_len);
4658 cp->err_ptr = cpu_to_le64(c->busaddr +
4659 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4660 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4661
d9a729f3
WS		 4662 /* fill in sg elements */
4663 if (use_sg > h->ioaccel_maxsg) {
4664 cp->sg_count = 1;
a736e9b6 4665 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4666 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4667 atomic_dec(&phys_disk->ioaccel_cmds_out);
4668 scsi_dma_unmap(cmd);
4669 return -1;
4670 }
4671 } else
4672 cp->sg_count = (u8) use_sg;
4673
c349775e
ST		 4674 enqueue_cmd_and_start_io(h, c);
4675 return 0;
4676}
4677
4678/*
4679 * Queue a command to the correct I/O accelerator path.
4680 */
4681static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4682 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4683 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4684{
03383736
DB		 4685 /* Try to honor the device's queue depth */
4686 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4687 phys_disk->queue_depth) {
4688 atomic_dec(&phys_disk->ioaccel_cmds_out);
4689 return IO_ACCEL_INELIGIBLE;
4690 }
c349775e
ST		 4691 if (h->transMethod & CFGTBL_Trans_io_accel1)
4692 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4693 cdb, cdb_len, scsi3addr,
4694 phys_disk);
c349775e
ST		 4695 else
4696 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4697 cdb, cdb_len, scsi3addr,
4698 phys_disk);
c349775e
ST		 4699}
4700
6b80b18f
ST		 4701static void raid_map_helper(struct raid_map_data *map,
4702 int offload_to_mirror, u32 *map_index, u32 *current_group)
4703{
4704 if (offload_to_mirror == 0) {
4705 /* use physical disk in the first mirrored group. */
2b08b3e9 4706 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4707 return;
4708 }
4709 do {
4710 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4711 *current_group = *map_index /
4712 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4713 if (offload_to_mirror == *current_group)
4714 continue;
2b08b3e9 4715 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4716 /* select map index from next group */
2b08b3e9 4717 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4718 (*current_group)++;
4719 } else {
4720 /* select map index from first group */
2b08b3e9 4721 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4722 *current_group = 0;
4723 }
4724 } while (offload_to_mirror != *current_group);
4725}
4726
283b4a9b
SC		 4727/*
4728 * Attempt to perform offload RAID mapping for a logical volume I/O.
4729 */
4730static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4731 struct CommandList *c)
4732{
4733 struct scsi_cmnd *cmd = c->scsi_cmd;
4734 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4735 struct raid_map_data *map = &dev->raid_map;
4736 struct raid_map_disk_data *dd = &map->data[0];
4737 int is_write = 0;
4738 u32 map_index;
4739 u64 first_block, last_block;
4740 u32 block_cnt;
4741 u32 blocks_per_row;
4742 u64 first_row, last_row;
4743 u32 first_row_offset, last_row_offset;
4744 u32 first_column, last_column;
6b80b18f
ST		 4745 u64 r0_first_row, r0_last_row;
4746 u32 r5or6_blocks_per_row;
4747 u64 r5or6_first_row, r5or6_last_row;
4748 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4749 u32 r5or6_first_column, r5or6_last_column;
4750 u32 total_disks_per_row;
4751 u32 stripesize;
4752 u32 first_group, last_group, current_group;
283b4a9b
SC		 4753 u32 map_row;
4754 u32 disk_handle;
4755 u64 disk_block;
4756 u32 disk_block_cnt;
4757 u8 cdb[16];
4758 u8 cdb_len;
2b08b3e9 4759 u16 strip_size;
283b4a9b
SC		 4760#if BITS_PER_LONG == 32
4761 u64 tmpdiv;
4762#endif
6b80b18f 4763 int offload_to_mirror;
283b4a9b 4764
283b4a9b
SC		 4765 /* check for valid opcode, get LBA and block count */
4766 switch (cmd->cmnd[0]) {
4767 case WRITE_6:
4768 is_write = 1;
4769 case READ_6:
c8a6c9a6 4770 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4771 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4772 if (block_cnt == 0)
4773 block_cnt = 256;
283b4a9b
SC		 4774 break;
4775 case WRITE_10:
4776 is_write = 1;
4777 case READ_10:
4778 first_block =
4779 (((u64) cmd->cmnd[2]) << 24) |
4780 (((u64) cmd->cmnd[3]) << 16) |
4781 (((u64) cmd->cmnd[4]) << 8) |
4782 cmd->cmnd[5];
4783 block_cnt =
4784 (((u32) cmd->cmnd[7]) << 8) |
4785 cmd->cmnd[8];
4786 break;
4787 case WRITE_12:
4788 is_write = 1;
4789 case READ_12:
4790 first_block =
4791 (((u64) cmd->cmnd[2]) << 24) |
4792 (((u64) cmd->cmnd[3]) << 16) |
4793 (((u64) cmd->cmnd[4]) << 8) |
4794 cmd->cmnd[5];
4795 block_cnt =
4796 (((u32) cmd->cmnd[6]) << 24) |
4797 (((u32) cmd->cmnd[7]) << 16) |
4798 (((u32) cmd->cmnd[8]) << 8) |
4799 cmd->cmnd[9];
4800 break;
4801 case WRITE_16:
4802 is_write = 1;
4803 case READ_16:
4804 first_block =
4805 (((u64) cmd->cmnd[2]) << 56) |
4806 (((u64) cmd->cmnd[3]) << 48) |
4807 (((u64) cmd->cmnd[4]) << 40) |
4808 (((u64) cmd->cmnd[5]) << 32) |
4809 (((u64) cmd->cmnd[6]) << 24) |
4810 (((u64) cmd->cmnd[7]) << 16) |
4811 (((u64) cmd->cmnd[8]) << 8) |
4812 cmd->cmnd[9];
4813 block_cnt =
4814 (((u32) cmd->cmnd[10]) << 24) |
4815 (((u32) cmd->cmnd[11]) << 16) |
4816 (((u32) cmd->cmnd[12]) << 8) |
4817 cmd->cmnd[13];
4818 break;
4819 default:
4820 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4821 }
283b4a9b
SC		 4822 last_block = first_block + block_cnt - 1;
4823
4824 /* check for write to non-RAID-0 */
4825 if (is_write && dev->raid_level != 0)
4826 return IO_ACCEL_INELIGIBLE;
4827
4828 /* check for invalid block or wraparound */
2b08b3e9
DB		 4829 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4830 last_block < first_block)
283b4a9b
SC		 4831 return IO_ACCEL_INELIGIBLE;
4832
4833 /* calculate stripe information for the request */
2b08b3e9
DB		 4834 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4835 le16_to_cpu(map->strip_size);
4836 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4837#if BITS_PER_LONG == 32
4838 tmpdiv = first_block;
4839 (void) do_div(tmpdiv, blocks_per_row);
4840 first_row = tmpdiv;
4841 tmpdiv = last_block;
4842 (void) do_div(tmpdiv, blocks_per_row);
4843 last_row = tmpdiv;
4844 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4845 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4846 tmpdiv = first_row_offset;
2b08b3e9 4847 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4848 first_column = tmpdiv;
4849 tmpdiv = last_row_offset;
2b08b3e9 4850 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4851 last_column = tmpdiv;
4852#else
4853 first_row = first_block / blocks_per_row;
4854 last_row = last_block / blocks_per_row;
4855 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4856 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4857 first_column = first_row_offset / strip_size;
4858 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4859#endif
4860
4861 /* if this isn't a single row/column then give to the controller */
4862 if ((first_row != last_row) || (first_column != last_column))
4863 return IO_ACCEL_INELIGIBLE;
4864
4865 /* proceeding with driver mapping */
2b08b3e9
DB		 4866 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4867 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4868 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4869 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4870 map_index = (map_row * total_disks_per_row) + first_column;
4871
4872 switch (dev->raid_level) {
4873 case HPSA_RAID_0:
4874 break; /* nothing special to do */
4875 case HPSA_RAID_1:
4876 /* Handles load balance across RAID 1 members.
4877 * (2-drive R1 and R10 with even # of drives.)
4878 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4879 */
2b08b3e9 4880 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4881 if (dev->offload_to_mirror)
2b08b3e9 4882 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4883 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4884 break;
4885 case HPSA_RAID_ADM:
4886 /* Handles N-way mirrors (R1-ADM)
4887 * and R10 with # of drives divisible by 3.)
4888 */
2b08b3e9 4889 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4890
4891 offload_to_mirror = dev->offload_to_mirror;
4892 raid_map_helper(map, offload_to_mirror,
4893 &map_index, &current_group);
4894 /* set mirror group to use next time */
4895 offload_to_mirror =
2b08b3e9
DB		 4896 (offload_to_mirror >=
4897 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4898 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4899 dev->offload_to_mirror = offload_to_mirror;
4900 /* Avoid direct use of dev->offload_to_mirror within this
4901 * function since multiple threads might simultaneously
4902 * increment it beyond the range of dev->layout_map_count -1.
4903 */
4904 break;
4905 case HPSA_RAID_5:
4906 case HPSA_RAID_6:
2b08b3e9 4907 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4908 break;
4909
4910 /* Verify first and last block are in same RAID group */
4911 r5or6_blocks_per_row =
2b08b3e9
DB		 4912 le16_to_cpu(map->strip_size) *
4913 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4914 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4915 stripesize = r5or6_blocks_per_row *
4916 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4917#if BITS_PER_LONG == 32
4918 tmpdiv = first_block;
4919 first_group = do_div(tmpdiv, stripesize);
4920 tmpdiv = first_group;
4921 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4922 first_group = tmpdiv;
4923 tmpdiv = last_block;
4924 last_group = do_div(tmpdiv, stripesize);
4925 tmpdiv = last_group;
4926 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4927 last_group = tmpdiv;
4928#else
4929 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4930 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4931#endif
000ff7c2 4932 if (first_group != last_group)
6b80b18f
ST		 4933 return IO_ACCEL_INELIGIBLE;
4934
4935 /* Verify request is in a single row of RAID 5/6 */
4936#if BITS_PER_LONG == 32
4937 tmpdiv = first_block;
4938 (void) do_div(tmpdiv, stripesize);
4939 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4940 tmpdiv = last_block;
4941 (void) do_div(tmpdiv, stripesize);
4942 r5or6_last_row = r0_last_row = tmpdiv;
4943#else
4944 first_row = r5or6_first_row = r0_first_row =
4945 first_block / stripesize;
4946 r5or6_last_row = r0_last_row = last_block / stripesize;
4947#endif
4948 if (r5or6_first_row != r5or6_last_row)
4949 return IO_ACCEL_INELIGIBLE;
4950
4951
4952 /* Verify request is in a single column */
4953#if BITS_PER_LONG == 32
4954 tmpdiv = first_block;
4955 first_row_offset = do_div(tmpdiv, stripesize);
4956 tmpdiv = first_row_offset;
4957 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4958 r5or6_first_row_offset = first_row_offset;
4959 tmpdiv = last_block;
4960 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4961 tmpdiv = r5or6_last_row_offset;
4962 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4963 tmpdiv = r5or6_first_row_offset;
4964 (void) do_div(tmpdiv, map->strip_size);
4965 first_column = r5or6_first_column = tmpdiv;
4966 tmpdiv = r5or6_last_row_offset;
4967 (void) do_div(tmpdiv, map->strip_size);
4968 r5or6_last_column = tmpdiv;
4969#else
4970 first_row_offset = r5or6_first_row_offset =
4971 (u32)((first_block % stripesize) %
4972 r5or6_blocks_per_row);
4973
4974 r5or6_last_row_offset =
4975 (u32)((last_block % stripesize) %
4976 r5or6_blocks_per_row);
4977
4978 first_column = r5or6_first_column =
2b08b3e9 4979 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4980 r5or6_last_column =
2b08b3e9 4981 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4982#endif
4983 if (r5or6_first_column != r5or6_last_column)
4984 return IO_ACCEL_INELIGIBLE;
4985
4986 /* Request is eligible */
4987 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4988 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4989
4990 map_index = (first_group *
2b08b3e9 4991 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4992 (map_row * total_disks_per_row) + first_column;
4993 break;
4994 default:
4995 return IO_ACCEL_INELIGIBLE;
283b4a9b 4996 }
6b80b18f 4997
07543e0c
SC		 4998 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4999 return IO_ACCEL_INELIGIBLE;
5000
03383736 5001 c->phys_disk = dev->phys_disk[map_index];
c3390df4
DB		 5002 if (!c->phys_disk)
5003 return IO_ACCEL_INELIGIBLE;
03383736 5004
283b4a9b 5005 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 5006 disk_block = le64_to_cpu(map->disk_starting_blk) +
5007 first_row * le16_to_cpu(map->strip_size) +
5008 (first_row_offset - first_column *
5009 le16_to_cpu(map->strip_size));
283b4a9b
SC		 5010 disk_block_cnt = block_cnt;
5011
5012 /* handle differing logical/physical block sizes */
5013 if (map->phys_blk_shift) {
5014 disk_block <<= map->phys_blk_shift;
5015 disk_block_cnt <<= map->phys_blk_shift;
5016 }
5017 BUG_ON(disk_block_cnt > 0xffff);
5018
5019 /* build the new CDB for the physical disk I/O */
5020 if (disk_block > 0xffffffff) {
5021 cdb[0] = is_write ? WRITE_16 : READ_16;
5022 cdb[1] = 0;
5023 cdb[2] = (u8) (disk_block >> 56);
5024 cdb[3] = (u8) (disk_block >> 48);
5025 cdb[4] = (u8) (disk_block >> 40);
5026 cdb[5] = (u8) (disk_block >> 32);
5027 cdb[6] = (u8) (disk_block >> 24);
5028 cdb[7] = (u8) (disk_block >> 16);
5029 cdb[8] = (u8) (disk_block >> 8);
5030 cdb[9] = (u8) (disk_block);
5031 cdb[10] = (u8) (disk_block_cnt >> 24);
5032 cdb[11] = (u8) (disk_block_cnt >> 16);
5033 cdb[12] = (u8) (disk_block_cnt >> 8);
5034 cdb[13] = (u8) (disk_block_cnt);
5035 cdb[14] = 0;
5036 cdb[15] = 0;
5037 cdb_len = 16;
5038 } else {
5039 cdb[0] = is_write ? WRITE_10 : READ_10;
5040 cdb[1] = 0;
5041 cdb[2] = (u8) (disk_block >> 24);
5042 cdb[3] = (u8) (disk_block >> 16);
5043 cdb[4] = (u8) (disk_block >> 8);
5044 cdb[5] = (u8) (disk_block);
5045 cdb[6] = 0;
5046 cdb[7] = (u8) (disk_block_cnt >> 8);
5047 cdb[8] = (u8) (disk_block_cnt);
5048 cdb[9] = 0;
5049 cdb_len = 10;
5050 }
5051 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5052 dev->scsi3addr,
5053 dev->phys_disk[map_index]);
283b4a9b
SC		 5054}
5055
25163bd5
WS		 5056/*
5057 * Submit commands down the "normal" RAID stack path
5058 * All callers to hpsa_ciss_submit must check lockup_detected
5059 * beforehand, before (opt.) and after calling cmd_alloc
5060 */
574f05d3
SC		 5061static int hpsa_ciss_submit(struct ctlr_info *h,
5062 struct CommandList *c, struct scsi_cmnd *cmd,
5063 unsigned char scsi3addr[])
edd16368 5064{
edd16368 5065 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5066 c->cmd_type = CMD_SCSI;
5067 c->scsi_cmd = cmd;
5068 c->Header.ReplyQueue = 0; /* unused in simple mode */
5069 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5070 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5071
5072 /* Fill in the request block... */
5073
5074 c->Request.Timeout = 0;
edd16368
SC		 5075 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5076 c->Request.CDBLen = cmd->cmd_len;
5077 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5078 switch (cmd->sc_data_direction) {
5079 case DMA_TO_DEVICE:
a505b86f
SC		 5080 c->Request.type_attr_dir =
5081 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5082 break;
5083 case DMA_FROM_DEVICE:
a505b86f
SC		 5084 c->Request.type_attr_dir =
5085 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5086 break;
5087 case DMA_NONE:
a505b86f
SC		 5088 c->Request.type_attr_dir =
5089 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5090 break;
5091 case DMA_BIDIRECTIONAL:
5092 /* This can happen if a buggy application does a scsi passthru
5093 * and sets both inlen and outlen to non-zero. ( see
5094 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5095 */
5096
a505b86f
SC		 5097 c->Request.type_attr_dir =
5098 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5099 /* This is technically wrong, and hpsa controllers should
5100 * reject it with CMD_INVALID, which is the most correct
5101 * response, but non-fibre backends appear to let it
5102 * slide by, and give the same results as if this field
5103 * were set correctly. Either way is acceptable for
5104 * our purposes here.
5105 */
5106
5107 break;
5108
5109 default:
5110 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5111 cmd->sc_data_direction);
5112 BUG();
5113 break;
5114 }
5115
33a2ffce 5116 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5117 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5118 return SCSI_MLQUEUE_HOST_BUSY;
5119 }
5120 enqueue_cmd_and_start_io(h, c);
5121 /* the cmd'll come back via intr handler in complete_scsi_command() */
5122 return 0;
5123}
5124
360c73bd
SC		 5125static void hpsa_cmd_init(struct ctlr_info *h, int index,
5126 struct CommandList *c)
5127{
5128 dma_addr_t cmd_dma_handle, err_dma_handle;
5129
5130 /* Zero out all of commandlist except the last field, refcount */
5131 memset(c, 0, offsetof(struct CommandList, refcount));
5132 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5133 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5134 c->err_info = h->errinfo_pool + index;
5135 memset(c->err_info, 0, sizeof(*c->err_info));
5136 err_dma_handle = h->errinfo_pool_dhandle
5137 + index * sizeof(*c->err_info);
5138 c->cmdindex = index;
5139 c->busaddr = (u32) cmd_dma_handle;
5140 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5141 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5142 c->h = h;
a58e7e53 5143 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5144}
5145
5146static void hpsa_preinitialize_commands(struct ctlr_info *h)
5147{
5148 int i;
5149
5150 for (i = 0; i < h->nr_cmds; i++) {
5151 struct CommandList *c = h->cmd_pool + i;
5152
5153 hpsa_cmd_init(h, i, c);
5154 atomic_set(&c->refcount, 0);
5155 }
5156}
5157
5158static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5159 struct CommandList *c)
5160{
5161 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5162
73153fe5
WS		 5163 BUG_ON(c->cmdindex != index);
5164
360c73bd
SC		 5165 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5166 memset(c->err_info, 0, sizeof(*c->err_info));
5167 c->busaddr = (u32) cmd_dma_handle;
5168}
5169
592a0ad5
WS		 5170static int hpsa_ioaccel_submit(struct ctlr_info *h,
5171 struct CommandList *c, struct scsi_cmnd *cmd,
5172 unsigned char *scsi3addr)
5173{
5174 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5175 int rc = IO_ACCEL_INELIGIBLE;
5176
5177 cmd->host_scribble = (unsigned char *) c;
5178
5179 if (dev->offload_enabled) {
5180 hpsa_cmd_init(h, c->cmdindex, c);
5181 c->cmd_type = CMD_SCSI;
5182 c->scsi_cmd = cmd;
5183 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5184 if (rc < 0) /* scsi_dma_map failed. */
5185 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5186 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5187 hpsa_cmd_init(h, c->cmdindex, c);
5188 c->cmd_type = CMD_SCSI;
5189 c->scsi_cmd = cmd;
5190 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5191 if (rc < 0) /* scsi_dma_map failed. */
5192 rc = SCSI_MLQUEUE_HOST_BUSY;
5193 }
5194 return rc;
5195}
5196
080ef1cc
DB		 5197static void hpsa_command_resubmit_worker(struct work_struct *work)
5198{
5199 struct scsi_cmnd *cmd;
5200 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5201 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5202
5203 cmd = c->scsi_cmd;
5204 dev = cmd->device->hostdata;
5205 if (!dev) {
5206 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5207 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5208 }
d604f533
WS		 5209 if (c->reset_pending)
5210 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 5211 if (c->abort_pending)
5212 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 5213 if (c->cmd_type == CMD_IOACCEL2) {
5214 struct ctlr_info *h = c->h;
5215 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5216 int rc;
5217
5218 if (c2->error_data.serv_response ==
5219 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5220 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5221 if (rc == 0)
5222 return;
5223 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5224 /*
5225 * If we get here, it means dma mapping failed.
5226 * Try again via scsi mid layer, which will
5227 * then get SCSI_MLQUEUE_HOST_BUSY.
5228 */
5229 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5230 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5231 }
5232 /* else, fall thru and resubmit down CISS path */
5233 }
5234 }
360c73bd 5235 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5236 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5237 /*
5238 * If we get here, it means dma mapping failed. Try
5239 * again via scsi mid layer, which will then get
5240 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5241 *
5242 * hpsa_ciss_submit will have already freed c
5243 * if it encountered a dma mapping failure.
080ef1cc
DB		 5244 */
5245 cmd->result = DID_IMM_RETRY << 16;
5246 cmd->scsi_done(cmd);
5247 }
5248}
5249
574f05d3
SC		 5250/* Running in struct Scsi_Host->host_lock less mode */
5251static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5252{
5253 struct ctlr_info *h;
5254 struct hpsa_scsi_dev_t *dev;
5255 unsigned char scsi3addr[8];
5256 struct CommandList *c;
5257 int rc = 0;
5258
5259 /* Get the ptr to our adapter structure out of cmd->host. */
5260 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5261
5262 BUG_ON(cmd->request->tag < 0);
5263
574f05d3
SC		 5264 dev = cmd->device->hostdata;
5265 if (!dev) {
5266 cmd->result = DID_NO_CONNECT << 16;
5267 cmd->scsi_done(cmd);
5268 return 0;
5269 }
574f05d3 5270
73153fe5 5271 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5272
407863cb 5273 if (unlikely(lockup_detected(h))) {
25163bd5 5274 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5275 cmd->scsi_done(cmd);
5276 return 0;
5277 }
73153fe5 5278 c = cmd_tagged_alloc(h, cmd);
574f05d3 5279
407863cb
SC		 5280 /*
5281 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5282 * Retries always go down the normal I/O path.
5283 */
5284 if (likely(cmd->retries == 0 &&
5285 cmd->request->cmd_type == REQ_TYPE_FS &&
5286 h->acciopath_status)) {
592a0ad5
WS		 5287 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5288 if (rc == 0)
5289 return 0;
5290 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5291 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5292 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5293 }
5294 }
5295 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5296}
5297
8ebc9248 5298static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5299{
5300 unsigned long flags;
5301
8ebc9248
WS		 5302 spin_lock_irqsave(&h->scan_lock, flags);
5303 h->scan_finished = 1;
5304 wake_up_all(&h->scan_wait_queue);
5305 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5306}
5307
a08a8471
SC		 5308static void hpsa_scan_start(struct Scsi_Host *sh)
5309{
5310 struct ctlr_info *h = shost_to_hba(sh);
5311 unsigned long flags;
5312
8ebc9248
WS		 5313 /*
5314 * Don't let rescans be initiated on a controller known to be locked
5315 * up. If the controller locks up *during* a rescan, that thread is
5316 * probably hosed, but at least we can prevent new rescan threads from
5317 * piling up on a locked up controller.
5318 */
5319 if (unlikely(lockup_detected(h)))
5320 return hpsa_scan_complete(h);
5f389360 5321
a08a8471
SC		 5322 /* wait until any scan already in progress is finished. */
5323 while (1) {
5324 spin_lock_irqsave(&h->scan_lock, flags);
5325 if (h->scan_finished)
5326 break;
5327 spin_unlock_irqrestore(&h->scan_lock, flags);
5328 wait_event(h->scan_wait_queue, h->scan_finished);
5329 /* Note: We don't need to worry about a race between this
5330 * thread and driver unload because the midlayer will
5331 * have incremented the reference count, so unload won't
5332 * happen if we're in here.
5333 */
5334 }
5335 h->scan_finished = 0; /* mark scan as in progress */
5336 spin_unlock_irqrestore(&h->scan_lock, flags);
5337
8ebc9248
WS		 5338 if (unlikely(lockup_detected(h)))
5339 return hpsa_scan_complete(h);
5f389360 5340
8aa60681 5341 hpsa_update_scsi_devices(h);
a08a8471 5342
8ebc9248 5343 hpsa_scan_complete(h);
a08a8471
SC		 5344}
5345
7c0a0229
DB		 5346static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5347{
03383736
DB		 5348 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5349
5350 if (!logical_drive)
5351 return -ENODEV;
7c0a0229
DB		 5352
5353 if (qdepth < 1)
5354 qdepth = 1;
03383736
DB		 5355 else if (qdepth > logical_drive->queue_depth)
5356 qdepth = logical_drive->queue_depth;
5357
5358 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5359}
5360
a08a8471
SC		 5361static int hpsa_scan_finished(struct Scsi_Host *sh,
5362 unsigned long elapsed_time)
5363{
5364 struct ctlr_info *h = shost_to_hba(sh);
5365 unsigned long flags;
5366 int finished;
5367
5368 spin_lock_irqsave(&h->scan_lock, flags);
5369 finished = h->scan_finished;
5370 spin_unlock_irqrestore(&h->scan_lock, flags);
5371 return finished;
5372}
5373
2946e82b 5374static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5375{
b705690d 5376 struct Scsi_Host *sh;
edd16368 5377
b705690d 5378 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5379 if (sh == NULL) {
5380 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5381 return -ENOMEM;
5382 }
b705690d
SC		 5383
5384 sh->io_port = 0;
5385 sh->n_io_port = 0;
5386 sh->this_id = -1;
5387 sh->max_channel = 3;
5388 sh->max_cmd_len = MAX_COMMAND_SIZE;
5389 sh->max_lun = HPSA_MAX_LUN;
5390 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5391 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5392 sh->cmd_per_lun = sh->can_queue;
b705690d 5393 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5394 sh->transportt = hpsa_sas_transport_template;
b705690d
SC		 5395 sh->hostdata[0] = (unsigned long) h;
5396 sh->irq = h->intr[h->intr_mode];
5397 sh->unique_id = sh->irq;
64d513ac 5398
2946e82b 5399 h->scsi_host = sh;
b705690d 5400 return 0;
2946e82b 5401}
b705690d 5402
2946e82b
RE		 5403static int hpsa_scsi_add_host(struct ctlr_info *h)
5404{
5405 int rv;
5406
5407 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5408 if (rv) {
5409 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5410 return rv;
5411 }
5412 scsi_scan_host(h->scsi_host);
5413 return 0;
edd16368
SC		 5414}
5415
73153fe5
WS		 5416/*
5417 * The block layer has already gone to the trouble of picking out a unique,
5418 * small-integer tag for this request. We use an offset from that value as
5419 * an index to select our command block. (The offset allows us to reserve the
5420 * low-numbered entries for our own uses.)
5421 */
5422static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5423{
5424 int idx = scmd->request->tag;
5425
5426 if (idx < 0)
5427 return idx;
5428
5429 /* Offset to leave space for internal cmds. */
5430 return idx += HPSA_NRESERVED_CMDS;
5431}
5432
b69324ff
WS		 5433/*
5434 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5435 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5436 */
5437static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5438 struct CommandList *c, unsigned char lunaddr[],
5439 int reply_queue)
5440{
5441 int rc;
5442
5443 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5444 (void) fill_cmd(c, TEST_UNIT_READY, h,
5445 NULL, 0, 0, lunaddr, TYPE_CMD);
c448ecfa 5446 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
b69324ff
WS		 5447 if (rc)
5448 return rc;
5449 /* no unmap needed here because no data xfer. */
5450
5451 /* Check if the unit is already ready. */
5452 if (c->err_info->CommandStatus == CMD_SUCCESS)
5453 return 0;
5454
5455 /*
5456 * The first command sent after reset will receive "unit attention" to
5457 * indicate that the LUN has been reset...this is actually what we're
5458 * looking for (but, success is good too).
5459 */
5460 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5461 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5462 (c->err_info->SenseInfo[2] == NO_SENSE ||
5463 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5464 return 0;
5465
5466 return 1;
5467}
5468
5469/*
5470 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5471 * returns zero when the unit is ready, and non-zero when giving up.
5472 */
5473static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5474 struct CommandList *c,
5475 unsigned char lunaddr[], int reply_queue)
edd16368 5476{
8919358e 5477 int rc;
edd16368
SC		 5478 int count = 0;
5479 int waittime = 1; /* seconds */
edd16368
SC		 5480
5481 /* Send test unit ready until device ready, or give up. */
b69324ff 5482 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5483
b69324ff
WS		 5484 /*
5485 * Wait for a bit. do this first, because if we send
edd16368
SC		 5486 * the TUR right away, the reset will just abort it.
5487 */
5488 msleep(1000 * waittime);
b69324ff
WS		 5489
5490 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5491 if (!rc)
5492 break;
edd16368
SC		 5493
5494 /* Increase wait time with each try, up to a point. */
5495 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5496 waittime *= 2;
edd16368 5497
b69324ff
WS		 5498 dev_warn(&h->pdev->dev,
5499 "waiting %d secs for device to become ready.\n",
5500 waittime);
5501 }
edd16368 5502
b69324ff
WS		 5503 return rc;
5504}
edd16368 5505
b69324ff
WS		 5506static int wait_for_device_to_become_ready(struct ctlr_info *h,
5507 unsigned char lunaddr[],
5508 int reply_queue)
5509{
5510 int first_queue;
5511 int last_queue;
5512 int rq;
5513 int rc = 0;
5514 struct CommandList *c;
5515
5516 c = cmd_alloc(h);
5517
5518 /*
5519 * If no specific reply queue was requested, then send the TUR
5520 * repeatedly, requesting a reply on each reply queue; otherwise execute
5521 * the loop exactly once using only the specified queue.
5522 */
5523 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5524 first_queue = 0;
5525 last_queue = h->nreply_queues - 1;
5526 } else {
5527 first_queue = reply_queue;
5528 last_queue = reply_queue;
5529 }
5530
5531 for (rq = first_queue; rq <= last_queue; rq++) {
5532 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5533 if (rc)
edd16368 5534 break;
edd16368
SC		 5535 }
5536
5537 if (rc)
5538 dev_warn(&h->pdev->dev, "giving up on device.\n");
5539 else
5540 dev_warn(&h->pdev->dev, "device is ready.\n");
5541
45fcb86e 5542 cmd_free(h, c);
edd16368
SC		 5543 return rc;
5544}
5545
5546/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5547 * complaining. Doing a host- or bus-reset can't do anything good here.
5548 */
5549static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5550{
5551 int rc;
5552 struct ctlr_info *h;
5553 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5554 u8 reset_type;
2dc127bb 5555 char msg[48];
edd16368
SC		 5556
5557 /* find the controller to which the command to be aborted was sent */
5558 h = sdev_to_hba(scsicmd->device);
5559 if (h == NULL) /* paranoia */
5560 return FAILED;
e345893b
DB		 5561
5562 if (lockup_detected(h))
5563 return FAILED;
5564
edd16368
SC		 5565 dev = scsicmd->device->hostdata;
5566 if (!dev) {
d604f533 5567 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5568 return FAILED;
5569 }
25163bd5
WS		 5570
5571 /* if controller locked up, we can guarantee command won't complete */
5572 if (lockup_detected(h)) {
2dc127bb
DC		 5573 snprintf(msg, sizeof(msg),
5574 "cmd %d RESET FAILED, lockup detected",
5575 hpsa_get_cmd_index(scsicmd));
73153fe5 5576 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5577 return FAILED;
5578 }
5579
5580 /* this reset request might be the result of a lockup; check */
5581 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5582 snprintf(msg, sizeof(msg),
5583 "cmd %d RESET FAILED, new lockup detected",
5584 hpsa_get_cmd_index(scsicmd));
73153fe5 5585 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5586 return FAILED;
5587 }
5588
d604f533
WS		 5589 /* Do not attempt on controller */
5590 if (is_hba_lunid(dev->scsi3addr))
5591 return SUCCESS;
5592
0b9b7b6e
ST		 5593 if (is_logical_dev_addr_mode(dev->scsi3addr))
5594 reset_type = HPSA_DEVICE_RESET_MSG;
5595 else
5596 reset_type = HPSA_PHYS_TARGET_RESET;
5597
5598 sprintf(msg, "resetting %s",
5599 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5600 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5601
da03ded0 5602 h->reset_in_progress = 1;
25163bd5 5603
edd16368 5604 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5605 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5606 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5607 sprintf(msg, "reset %s %s",
5608 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5609 rc == 0 ? "completed successfully" : "failed");
d604f533 5610 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5611 h->reset_in_progress = 0;
d604f533 5612 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5613}
5614
6cba3f19
SC		 5615static void swizzle_abort_tag(u8 *tag)
5616{
5617 u8 original_tag[8];
5618
5619 memcpy(original_tag, tag, 8);
5620 tag[0] = original_tag[3];
5621 tag[1] = original_tag[2];
5622 tag[2] = original_tag[1];
5623 tag[3] = original_tag[0];
5624 tag[4] = original_tag[7];
5625 tag[5] = original_tag[6];
5626 tag[6] = original_tag[5];
5627 tag[7] = original_tag[4];
5628}
5629
17eb87d2 5630static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5631 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5632{
2b08b3e9 5633 u64 tag;
17eb87d2
ST		 5634 if (c->cmd_type == CMD_IOACCEL1) {
5635 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5636 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5637 tag = le64_to_cpu(cm1->tag);
5638 *tagupper = cpu_to_le32(tag >> 32);
5639 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5640 return;
5641 }
5642 if (c->cmd_type == CMD_IOACCEL2) {
5643 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5644 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5645 /* upper tag not used in ioaccel2 mode */
5646 memset(tagupper, 0, sizeof(*tagupper));
5647 *taglower = cm2->Tag;
54b6e9e9 5648 return;
17eb87d2 5649 }
2b08b3e9
DB		 5650 tag = le64_to_cpu(c->Header.tag);
5651 *tagupper = cpu_to_le32(tag >> 32);
5652 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5653}
5654
75167d2c 5655static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5656 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5657{
5658 int rc = IO_OK;
5659 struct CommandList *c;
5660 struct ErrorInfo *ei;
2b08b3e9 5661 __le32 tagupper, taglower;
75167d2c 5662
45fcb86e 5663 c = cmd_alloc(h);
75167d2c 5664
a2dac136 5665 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5666 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5667 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5668 if (h->needs_abort_tags_swizzled)
6cba3f19 5669 swizzle_abort_tag(&c->Request.CDB[4]);
c448ecfa 5670 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
17eb87d2 5671 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5672 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5673 __func__, tagupper, taglower);
75167d2c
SC		 5674 /* no unmap needed here because no data xfer. */
5675
5676 ei = c->err_info;
5677 switch (ei->CommandStatus) {
5678 case CMD_SUCCESS:
5679 break;
9437ac43
SC		 5680 case CMD_TMF_STATUS:
5681 rc = hpsa_evaluate_tmf_status(h, c);
5682 break;
75167d2c
SC		 5683 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5684 rc = -1;
5685 break;
5686 default:
5687 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5688 __func__, tagupper, taglower);
d1e8beac 5689 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5690 rc = -1;
5691 break;
5692 }
45fcb86e 5693 cmd_free(h, c);
dd0e19f3
ST		 5694 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5695 __func__, tagupper, taglower);
75167d2c
SC		 5696 return rc;
5697}
5698
8be986cc
SC		 5699static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5700 struct CommandList *command_to_abort, int reply_queue)
5701{
5702 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5703 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5704 struct io_accel2_cmd *c2a =
5705 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5706 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5707 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5708
5709 /*
5710 * We're overlaying struct hpsa_tmf_struct on top of something which
5711 * was allocated as a struct io_accel2_cmd, so we better be sure it
5712 * actually fits, and doesn't overrun the error info space.
5713 */
5714 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5715 sizeof(struct io_accel2_cmd));
5716 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5717 offsetof(struct hpsa_tmf_struct, error_len) +
5718 sizeof(ac->error_len));
5719
5720 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5721 c->scsi_cmd = SCSI_CMD_BUSY;
5722
8be986cc
SC		 5723 /* Adjust the DMA address to point to the accelerated command buffer */
5724 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5725 (c->cmdindex * sizeof(struct io_accel2_cmd));
5726 BUG_ON(c->busaddr & 0x0000007F);
5727
5728 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5729 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5730 ac->reply_queue = reply_queue;
5731 ac->tmf = IOACCEL2_TMF_ABORT;
5732 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5733 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5734 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5735 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5736 ac->error_ptr = cpu_to_le64(c->busaddr +
5737 offsetof(struct io_accel2_cmd, error_data));
5738 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5739}
5740
54b6e9e9
ST		 5741/* ioaccel2 path firmware cannot handle abort task requests.
5742 * Change abort requests to physical target reset, and send to the
5743 * address of the physical disk used for the ioaccel 2 command.
5744 * Return 0 on success (IO_OK)
5745 * -1 on failure
5746 */
5747
5748static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5749 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5750{
5751 int rc = IO_OK;
5752 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5753 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5754 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5755 unsigned char *psa = &phys_scsi3addr[0];
5756
5757 /* Get a pointer to the hpsa logical device. */
7fa3030c 5758 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5759 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5760 if (dev == NULL) {
5761 dev_warn(&h->pdev->dev,
5762 "Cannot abort: no device pointer for command.\n");
5763 return -1; /* not abortable */
5764 }
5765
2ba8bfc8
SC		 5766 if (h->raid_offload_debug > 0)
5767 dev_info(&h->pdev->dev,
0d96ef5f 5768 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5769 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5770 "Reset as abort",
2ba8bfc8
SC		 5771 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5772 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5773
54b6e9e9
ST		 5774 if (!dev->offload_enabled) {
5775 dev_warn(&h->pdev->dev,
5776 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5777 return -1; /* not abortable */
5778 }
5779
5780 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5781 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5782 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5783 return -1; /* not abortable */
5784 }
5785
5786 /* send the reset */
2ba8bfc8
SC		 5787 if (h->raid_offload_debug > 0)
5788 dev_info(&h->pdev->dev,
5789 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5790 psa[0], psa[1], psa[2], psa[3],
5791 psa[4], psa[5], psa[6], psa[7]);
d604f533 5792 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5793 if (rc != 0) {
5794 dev_warn(&h->pdev->dev,
5795 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5796 psa[0], psa[1], psa[2], psa[3],
5797 psa[4], psa[5], psa[6], psa[7]);
5798 return rc; /* failed to reset */
5799 }
5800
5801 /* wait for device to recover */
b69324ff 5802 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5803 dev_warn(&h->pdev->dev,
5804 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5805 psa[0], psa[1], psa[2], psa[3],
5806 psa[4], psa[5], psa[6], psa[7]);
5807 return -1; /* failed to recover */
5808 }
5809
5810 /* device recovered */
5811 dev_info(&h->pdev->dev,
5812 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5813 psa[0], psa[1], psa[2], psa[3],
5814 psa[4], psa[5], psa[6], psa[7]);
5815
5816 return rc; /* success */
5817}
5818
8be986cc
SC		 5819static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5820 struct CommandList *abort, int reply_queue)
5821{
5822 int rc = IO_OK;
5823 struct CommandList *c;
5824 __le32 taglower, tagupper;
5825 struct hpsa_scsi_dev_t *dev;
5826 struct io_accel2_cmd *c2;
5827
5828 dev = abort->scsi_cmd->device->hostdata;
5829 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5830 return -1;
5831
5832 c = cmd_alloc(h);
5833 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5834 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
c448ecfa 5835 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
8be986cc
SC		 5836 hpsa_get_tag(h, abort, &taglower, &tagupper);
5837 dev_dbg(&h->pdev->dev,
5838 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5839 __func__, tagupper, taglower);
5840 /* no unmap needed here because no data xfer. */
5841
5842 dev_dbg(&h->pdev->dev,
5843 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5844 __func__, tagupper, taglower, c2->error_data.serv_response);
5845 switch (c2->error_data.serv_response) {
5846 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5847 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5848 rc = 0;
5849 break;
5850 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5851 case IOACCEL2_SERV_RESPONSE_FAILURE:
5852 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5853 rc = -1;
5854 break;
5855 default:
5856 dev_warn(&h->pdev->dev,
5857 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5858 __func__, tagupper, taglower,
5859 c2->error_data.serv_response);
5860 rc = -1;
5861 }
5862 cmd_free(h, c);
5863 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5864 tagupper, taglower);
5865 return rc;
5866}
5867
6cba3f19 5868static int hpsa_send_abort_both_ways(struct ctlr_info *h,
39f3deb2 5869 struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue)
6cba3f19 5870{
8be986cc
SC		 5871 /*
5872 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5873 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5874 * but not all underlying firmware can handle abort TMF.
5875 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5876 */
8be986cc 5877 if (abort->cmd_type == CMD_IOACCEL2) {
39f3deb2
DB		 5878 if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) ||
5879 dev->physical_device)
8be986cc
SC		 5880 return hpsa_send_abort_ioaccel2(h, abort,
5881 reply_queue);
5882 else
39f3deb2
DB		 5883 return hpsa_send_reset_as_abort_ioaccel2(h,
5884 dev->scsi3addr,
25163bd5 5885 abort, reply_queue);
8be986cc 5886 }
39f3deb2 5887 return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue);
25163bd5 5888}
54b6e9e9 5889
25163bd5
WS		 5890/* Find out which reply queue a command was meant to return on */
5891static int hpsa_extract_reply_queue(struct ctlr_info *h,
5892 struct CommandList *c)
5893{
5894 if (c->cmd_type == CMD_IOACCEL2)
5895 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5896 return c->Header.ReplyQueue;
6cba3f19
SC		 5897}
5898
9b5c48c2
SC		 5899/*
5900 * Limit concurrency of abort commands to prevent
5901 * over-subscription of commands
5902 */
5903static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5904{
5905#define ABORT_CMD_WAIT_MSECS 5000
5906 return !wait_event_timeout(h->abort_cmd_wait_queue,
5907 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5908 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5909}
5910
75167d2c
SC		 5911/* Send an abort for the specified command.
5912 * If the device and controller support it,
5913 * send a task abort request.
5914 */
5915static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5916{
5917
a58e7e53 5918 int rc;
75167d2c
SC		 5919 struct ctlr_info *h;
5920 struct hpsa_scsi_dev_t *dev;
5921 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5922 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5923 char msg[256]; /* For debug messaging. */
5924 int ml = 0;
2b08b3e9 5925 __le32 tagupper, taglower;
25163bd5
WS		 5926 int refcount, reply_queue;
5927
5928 if (sc == NULL)
5929 return FAILED;
75167d2c 5930
9b5c48c2
SC		 5931 if (sc->device == NULL)
5932 return FAILED;
5933
75167d2c
SC		 5934 /* Find the controller of the command to be aborted */
5935 h = sdev_to_hba(sc->device);
9b5c48c2 5936 if (h == NULL)
75167d2c
SC		 5937 return FAILED;
5938
25163bd5
WS		 5939 /* Find the device of the command to be aborted */
5940 dev = sc->device->hostdata;
5941 if (!dev) {
5942 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5943 msg);
e345893b 5944 return FAILED;
25163bd5
WS		 5945 }
5946
5947 /* If controller locked up, we can guarantee command won't complete */
5948 if (lockup_detected(h)) {
5949 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5950 "ABORT FAILED, lockup detected");
5951 return FAILED;
5952 }
5953
5954 /* This is a good time to check if controller lockup has occurred */
5955 if (detect_controller_lockup(h)) {
5956 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5957 "ABORT FAILED, new lockup detected");
5958 return FAILED;
5959 }
e345893b 5960
75167d2c
SC		 5961 /* Check that controller supports some kind of task abort */
5962 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5963 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5964 return FAILED;
5965
5966 memset(msg, 0, sizeof(msg));
4b761557 5967 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5968 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5969 sc->device->id, sc->device->lun,
4b761557 5970 "Aborting command", sc);
75167d2c 5971
75167d2c
SC		 5972 /* Get SCSI command to be aborted */
5973 abort = (struct CommandList *) sc->host_scribble;
5974 if (abort == NULL) {
281a7fd0
WS		 5975 /* This can happen if the command already completed. */
5976 return SUCCESS;
5977 }
5978 refcount = atomic_inc_return(&abort->refcount);
5979 if (refcount == 1) { /* Command is done already. */
5980 cmd_free(h, abort);
5981 return SUCCESS;
75167d2c 5982 }
9b5c48c2
SC		 5983
5984 /* Don't bother trying the abort if we know it won't work. */
5985 if (abort->cmd_type != CMD_IOACCEL2 &&
5986 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5987 cmd_free(h, abort);
5988 return FAILED;
5989 }
5990
a58e7e53
WS		 5991 /*
5992 * Check that we're aborting the right command.
5993 * It's possible the CommandList already completed and got re-used.
5994 */
5995 if (abort->scsi_cmd != sc) {
5996 cmd_free(h, abort);
5997 return SUCCESS;
5998 }
5999
6000 abort->abort_pending = true;
17eb87d2 6001 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 6002 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 6003 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 6004 as = abort->scsi_cmd;
75167d2c 6005 if (as != NULL)
4b761557
RE		 6006 ml += sprintf(msg+ml,
6007 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
6008 as->cmd_len, as->cmnd[0], as->cmnd[1],
6009 as->serial_number);
6010 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 6011 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 6012
75167d2c
SC		 6013 /*
6014 * Command is in flight, or possibly already completed
6015 * by the firmware (but not to the scsi mid layer) but we can't
6016 * distinguish which. Send the abort down.
6017 */
9b5c48c2
SC		 6018 if (wait_for_available_abort_cmd(h)) {
6019 dev_warn(&h->pdev->dev,
4b761557
RE		 6020 "%s FAILED, timeout waiting for an abort command to become available.\n",
6021 msg);
9b5c48c2
SC		 6022 cmd_free(h, abort);
6023 return FAILED;
6024 }
39f3deb2 6025 rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue);
9b5c48c2
SC		 6026 atomic_inc(&h->abort_cmds_available);
6027 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 6028 if (rc != 0) {
4b761557 6029 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 6030 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 6031 "FAILED to abort command");
281a7fd0 6032 cmd_free(h, abort);
75167d2c
SC		 6033 return FAILED;
6034 }
4b761557 6035 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 6036 wait_event(h->event_sync_wait_queue,
a58e7e53 6037 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 6038 cmd_free(h, abort);
a58e7e53 6039 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 6040}
6041
73153fe5
WS		 6042/*
6043 * For operations with an associated SCSI command, a command block is allocated
6044 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6045 * block request tag as an index into a table of entries. cmd_tagged_free() is
6046 * the complement, although cmd_free() may be called instead.
6047 */
6048static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6049 struct scsi_cmnd *scmd)
6050{
6051 int idx = hpsa_get_cmd_index(scmd);
6052 struct CommandList *c = h->cmd_pool + idx;
6053
6054 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6055 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6056 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6057 /* The index value comes from the block layer, so if it's out of
6058 * bounds, it's probably not our bug.
6059 */
6060 BUG();
6061 }
6062
6063 atomic_inc(&c->refcount);
6064 if (unlikely(!hpsa_is_cmd_idle(c))) {
6065 /*
6066 * We expect that the SCSI layer will hand us a unique tag
6067 * value. Thus, there should never be a collision here between
6068 * two requests...because if the selected command isn't idle
6069 * then someone is going to be very disappointed.
6070 */
6071 dev_err(&h->pdev->dev,
6072 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6073 idx);
6074 if (c->scsi_cmd != NULL)
6075 scsi_print_command(c->scsi_cmd);
6076 scsi_print_command(scmd);
6077 }
6078
6079 hpsa_cmd_partial_init(h, idx, c);
6080 return c;
6081}
6082
6083static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6084{
6085 /*
6086 * Release our reference to the block. We don't need to do anything
6087 * else to free it, because it is accessed by index. (There's no point
6088 * in checking the result of the decrement, since we cannot guarantee
6089 * that there isn't a concurrent abort which is also accessing it.)
6090 */
6091 (void)atomic_dec(&c->refcount);
6092}
6093
edd16368
SC		 6094/*
6095 * For operations that cannot sleep, a command block is allocated at init,
6096 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6097 * which ones are free or in use. Lock must be held when calling this.
6098 * cmd_free() is the complement.
bf43caf3
RE		 6099 * This function never gives up and returns NULL. If it hangs,
6100 * another thread must call cmd_free() to free some tags.
edd16368 6101 */
281a7fd0 6102
edd16368
SC		 6103static struct CommandList *cmd_alloc(struct ctlr_info *h)
6104{
6105 struct CommandList *c;
360c73bd 6106 int refcount, i;
73153fe5 6107 int offset = 0;
4c413128 6108
33811026
RE		 6109 /*
6110 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6111 * multiple threads could get in here, and one thread could
6112 * be scanning through the list of bits looking for a free
6113 * one, but the free ones are always behind him, and other
6114 * threads sneak in behind him and eat them before he can
6115 * get to them, so that while there is always a free one, a
6116 * very unlucky thread might be starved anyway, never able to
6117 * beat the other threads. In reality, this happens so
6118 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6119 *
6120 * Note that we start allocating commands before the SCSI host structure
6121 * is initialized. Since the search starts at bit zero, this
6122 * all works, since we have at least one command structure available;
6123 * however, it means that the structures with the low indexes have to be
6124 * reserved for driver-initiated requests, while requests from the block
6125 * layer will use the higher indexes.
4c413128 6126 */
edd16368 6127
281a7fd0 6128 for (;;) {
73153fe5
WS		 6129 i = find_next_zero_bit(h->cmd_pool_bits,
6130 HPSA_NRESERVED_CMDS,
6131 offset);
6132 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6133 offset = 0;
6134 continue;
6135 }
6136 c = h->cmd_pool + i;
6137 refcount = atomic_inc_return(&c->refcount);
6138 if (unlikely(refcount > 1)) {
6139 cmd_free(h, c); /* already in use */
73153fe5 6140 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6141 continue;
6142 }
6143 set_bit(i & (BITS_PER_LONG - 1),
6144 h->cmd_pool_bits + (i / BITS_PER_LONG));
6145 break; /* it's ours now. */
6146 }
360c73bd 6147 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6148 return c;
6149}
6150
73153fe5
WS		 6151/*
6152 * This is the complementary operation to cmd_alloc(). Note, however, in some
6153 * corner cases it may also be used to free blocks allocated by
6154 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6155 * the clear-bit is harmless.
6156 */
edd16368
SC		 6157static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6158{
281a7fd0
WS		 6159 if (atomic_dec_and_test(&c->refcount)) {
6160 int i;
edd16368 6161
281a7fd0
WS		 6162 i = c - h->cmd_pool;
6163 clear_bit(i & (BITS_PER_LONG - 1),
6164 h->cmd_pool_bits + (i / BITS_PER_LONG));
6165 }
edd16368
SC		 6166}
6167
edd16368
SC		 6168#ifdef CONFIG_COMPAT
6169
42a91641
DB		 6170static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
6171 void __user *arg)
edd16368
SC		 6172{
6173 IOCTL32_Command_struct __user *arg32 =
6174 (IOCTL32_Command_struct __user *) arg;
6175 IOCTL_Command_struct arg64;
6176 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6177 int err;
6178 u32 cp;
6179
938abd84 6180 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6181 err = 0;
6182 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6183 sizeof(arg64.LUN_info));
6184 err |= copy_from_user(&arg64.Request, &arg32->Request,
6185 sizeof(arg64.Request));
6186 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6187 sizeof(arg64.error_info));
6188 err |= get_user(arg64.buf_size, &arg32->buf_size);
6189 err |= get_user(cp, &arg32->buf);
6190 arg64.buf = compat_ptr(cp);
6191 err |= copy_to_user(p, &arg64, sizeof(arg64));
6192
6193 if (err)
6194 return -EFAULT;
6195
42a91641 6196 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6197 if (err)
6198 return err;
6199 err |= copy_in_user(&arg32->error_info, &p->error_info,
6200 sizeof(arg32->error_info));
6201 if (err)
6202 return -EFAULT;
6203 return err;
6204}
6205
6206static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 6207 int cmd, void __user *arg)
edd16368
SC		 6208{
6209 BIG_IOCTL32_Command_struct __user *arg32 =
6210 (BIG_IOCTL32_Command_struct __user *) arg;
6211 BIG_IOCTL_Command_struct arg64;
6212 BIG_IOCTL_Command_struct __user *p =
6213 compat_alloc_user_space(sizeof(arg64));
6214 int err;
6215 u32 cp;
6216
938abd84 6217 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6218 err = 0;
6219 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6220 sizeof(arg64.LUN_info));
6221 err |= copy_from_user(&arg64.Request, &arg32->Request,
6222 sizeof(arg64.Request));
6223 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6224 sizeof(arg64.error_info));
6225 err |= get_user(arg64.buf_size, &arg32->buf_size);
6226 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6227 err |= get_user(cp, &arg32->buf);
6228 arg64.buf = compat_ptr(cp);
6229 err |= copy_to_user(p, &arg64, sizeof(arg64));
6230
6231 if (err)
6232 return -EFAULT;
6233
42a91641 6234 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6235 if (err)
6236 return err;
6237 err |= copy_in_user(&arg32->error_info, &p->error_info,
6238 sizeof(arg32->error_info));
6239 if (err)
6240 return -EFAULT;
6241 return err;
6242}
71fe75a7 6243
42a91641 6244static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 6245{
6246 switch (cmd) {
6247 case CCISS_GETPCIINFO:
6248 case CCISS_GETINTINFO:
6249 case CCISS_SETINTINFO:
6250 case CCISS_GETNODENAME:
6251 case CCISS_SETNODENAME:
6252 case CCISS_GETHEARTBEAT:
6253 case CCISS_GETBUSTYPES:
6254 case CCISS_GETFIRMVER:
6255 case CCISS_GETDRIVVER:
6256 case CCISS_REVALIDVOLS:
6257 case CCISS_DEREGDISK:
6258 case CCISS_REGNEWDISK:
6259 case CCISS_REGNEWD:
6260 case CCISS_RESCANDISK:
6261 case CCISS_GETLUNINFO:
6262 return hpsa_ioctl(dev, cmd, arg);
6263
6264 case CCISS_PASSTHRU32:
6265 return hpsa_ioctl32_passthru(dev, cmd, arg);
6266 case CCISS_BIG_PASSTHRU32:
6267 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6268
6269 default:
6270 return -ENOIOCTLCMD;
6271 }
6272}
edd16368
SC		 6273#endif
6274
6275static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6276{
6277 struct hpsa_pci_info pciinfo;
6278
6279 if (!argp)
6280 return -EINVAL;
6281 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6282 pciinfo.bus = h->pdev->bus->number;
6283 pciinfo.dev_fn = h->pdev->devfn;
6284 pciinfo.board_id = h->board_id;
6285 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6286 return -EFAULT;
6287 return 0;
6288}
6289
6290static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6291{
6292 DriverVer_type DriverVer;
6293 unsigned char vmaj, vmin, vsubmin;
6294 int rc;
6295
6296 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6297 &vmaj, &vmin, &vsubmin);
6298 if (rc != 3) {
6299 dev_info(&h->pdev->dev, "driver version string '%s' "
6300 "unrecognized.", HPSA_DRIVER_VERSION);
6301 vmaj = 0;
6302 vmin = 0;
6303 vsubmin = 0;
6304 }
6305 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6306 if (!argp)
6307 return -EINVAL;
6308 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6309 return -EFAULT;
6310 return 0;
6311}
6312
6313static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6314{
6315 IOCTL_Command_struct iocommand;
6316 struct CommandList *c;
6317 char *buff = NULL;
50a0decf 6318 u64 temp64;
c1f63c8f 6319 int rc = 0;
edd16368
SC		 6320
6321 if (!argp)
6322 return -EINVAL;
6323 if (!capable(CAP_SYS_RAWIO))
6324 return -EPERM;
6325 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6326 return -EFAULT;
6327 if ((iocommand.buf_size < 1) &&
6328 (iocommand.Request.Type.Direction != XFER_NONE)) {
6329 return -EINVAL;
6330 }
6331 if (iocommand.buf_size > 0) {
6332 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6333 if (buff == NULL)
2dd02d74 6334 return -ENOMEM;
9233fb10 6335 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6336 /* Copy the data into the buffer we created */
6337 if (copy_from_user(buff, iocommand.buf,
6338 iocommand.buf_size)) {
c1f63c8f
SC		 6339 rc = -EFAULT;
6340 goto out_kfree;
b03a7771
SC		 6341 }
6342 } else {
6343 memset(buff, 0, iocommand.buf_size);
edd16368 6344 }
b03a7771 6345 }
45fcb86e 6346 c = cmd_alloc(h);
bf43caf3 6347
edd16368
SC		 6348 /* Fill in the command type */
6349 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6350 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6351 /* Fill in Command Header */
6352 c->Header.ReplyQueue = 0; /* unused in simple mode */
6353 if (iocommand.buf_size > 0) { /* buffer to fill */
6354 c->Header.SGList = 1;
50a0decf 6355 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6356 } else { /* no buffers to fill */
6357 c->Header.SGList = 0;
50a0decf 6358 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6359 }
6360 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6361
6362 /* Fill in Request block */
6363 memcpy(&c->Request, &iocommand.Request,
6364 sizeof(c->Request));
6365
6366 /* Fill in the scatter gather information */
6367 if (iocommand.buf_size > 0) {
50a0decf 6368 temp64 = pci_map_single(h->pdev, buff,
edd16368 6369 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6370 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6371 c->SG[0].Addr = cpu_to_le64(0);
6372 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6373 rc = -ENOMEM;
6374 goto out;
6375 }
50a0decf
SC		 6376 c->SG[0].Addr = cpu_to_le64(temp64);
6377 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6378 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6379 }
c448ecfa
DB		 6380 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6381 DEFAULT_TIMEOUT);
c2dd32e0
SC		 6382 if (iocommand.buf_size > 0)
6383 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6384 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6385 if (rc) {
6386 rc = -EIO;
6387 goto out;
6388 }
edd16368
SC		 6389
6390 /* Copy the error information out */
6391 memcpy(&iocommand.error_info, c->err_info,
6392 sizeof(iocommand.error_info));
6393 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6394 rc = -EFAULT;
6395 goto out;
edd16368 6396 }
9233fb10 6397 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6398 iocommand.buf_size > 0) {
edd16368
SC		 6399 /* Copy the data out of the buffer we created */
6400 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6401 rc = -EFAULT;
6402 goto out;
edd16368
SC		 6403 }
6404 }
c1f63c8f 6405out:
45fcb86e 6406 cmd_free(h, c);
c1f63c8f
SC		 6407out_kfree:
6408 kfree(buff);
6409 return rc;
edd16368
SC		 6410}
6411
6412static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6413{
6414 BIG_IOCTL_Command_struct *ioc;
6415 struct CommandList *c;
6416 unsigned char **buff = NULL;
6417 int *buff_size = NULL;
50a0decf 6418 u64 temp64;
edd16368
SC		 6419 BYTE sg_used = 0;
6420 int status = 0;
01a02ffc
SC		 6421 u32 left;
6422 u32 sz;
edd16368
SC		 6423 BYTE __user *data_ptr;
6424
6425 if (!argp)
6426 return -EINVAL;
6427 if (!capable(CAP_SYS_RAWIO))
6428 return -EPERM;
6429 ioc = (BIG_IOCTL_Command_struct *)
6430 kmalloc(sizeof(*ioc), GFP_KERNEL);
6431 if (!ioc) {
6432 status = -ENOMEM;
6433 goto cleanup1;
6434 }
6435 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6436 status = -EFAULT;
6437 goto cleanup1;
6438 }
6439 if ((ioc->buf_size < 1) &&
6440 (ioc->Request.Type.Direction != XFER_NONE)) {
6441 status = -EINVAL;
6442 goto cleanup1;
6443 }
6444 /* Check kmalloc limits using all SGs */
6445 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6446 status = -EINVAL;
6447 goto cleanup1;
6448 }
d66ae08b 6449 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6450 status = -EINVAL;
6451 goto cleanup1;
6452 }
d66ae08b 6453 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6454 if (!buff) {
6455 status = -ENOMEM;
6456 goto cleanup1;
6457 }
d66ae08b 6458 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6459 if (!buff_size) {
6460 status = -ENOMEM;
6461 goto cleanup1;
6462 }
6463 left = ioc->buf_size;
6464 data_ptr = ioc->buf;
6465 while (left) {
6466 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6467 buff_size[sg_used] = sz;
6468 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6469 if (buff[sg_used] == NULL) {
6470 status = -ENOMEM;
6471 goto cleanup1;
6472 }
9233fb10 6473 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6474 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6475 status = -EFAULT;
edd16368
SC		 6476 goto cleanup1;
6477 }
6478 } else
6479 memset(buff[sg_used], 0, sz);
6480 left -= sz;
6481 data_ptr += sz;
6482 sg_used++;
6483 }
45fcb86e 6484 c = cmd_alloc(h);
bf43caf3 6485
edd16368 6486 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6487 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6488 c->Header.ReplyQueue = 0;
50a0decf
SC		 6489 c->Header.SGList = (u8) sg_used;
6490 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6491 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6492 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6493 if (ioc->buf_size > 0) {
6494 int i;
6495 for (i = 0; i < sg_used; i++) {
50a0decf 6496 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6497 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6498 if (dma_mapping_error(&h->pdev->dev,
6499 (dma_addr_t) temp64)) {
6500 c->SG[i].Addr = cpu_to_le64(0);
6501 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6502 hpsa_pci_unmap(h->pdev, c, i,
6503 PCI_DMA_BIDIRECTIONAL);
6504 status = -ENOMEM;
e2d4a1f6 6505 goto cleanup0;
bcc48ffa 6506 }
50a0decf
SC		 6507 c->SG[i].Addr = cpu_to_le64(temp64);
6508 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6509 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6510 }
50a0decf 6511 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6512 }
c448ecfa
DB		 6513 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
6514 DEFAULT_TIMEOUT);
b03a7771
SC		 6515 if (sg_used)
6516 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6517 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6518 if (status) {
6519 status = -EIO;
6520 goto cleanup0;
6521 }
6522
edd16368
SC		 6523 /* Copy the error information out */
6524 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6525 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6526 status = -EFAULT;
e2d4a1f6 6527 goto cleanup0;
edd16368 6528 }
9233fb10 6529 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6530 int i;
6531
edd16368
SC		 6532 /* Copy the data out of the buffer we created */
6533 BYTE __user *ptr = ioc->buf;
6534 for (i = 0; i < sg_used; i++) {
6535 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6536 status = -EFAULT;
e2d4a1f6 6537 goto cleanup0;
edd16368
SC		 6538 }
6539 ptr += buff_size[i];
6540 }
6541 }
edd16368 6542 status = 0;
e2d4a1f6 6543cleanup0:
45fcb86e 6544 cmd_free(h, c);
edd16368
SC		 6545cleanup1:
6546 if (buff) {
2b08b3e9
DB		 6547 int i;
6548
edd16368
SC		 6549 for (i = 0; i < sg_used; i++)
6550 kfree(buff[i]);
6551 kfree(buff);
6552 }
6553 kfree(buff_size);
6554 kfree(ioc);
6555 return status;
6556}
6557
6558static void check_ioctl_unit_attention(struct ctlr_info *h,
6559 struct CommandList *c)
6560{
6561 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6562 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6563 (void) check_for_unit_attention(h, c);
6564}
0390f0c0 6565
edd16368
SC		 6566/*
6567 * ioctl
6568 */
42a91641 6569static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6570{
6571 struct ctlr_info *h;
6572 void __user *argp = (void __user *)arg;
0390f0c0 6573 int rc;
edd16368
SC		 6574
6575 h = sdev_to_hba(dev);
6576
6577 switch (cmd) {
6578 case CCISS_DEREGDISK:
6579 case CCISS_REGNEWDISK:
6580 case CCISS_REGNEWD:
a08a8471 6581 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6582 return 0;
6583 case CCISS_GETPCIINFO:
6584 return hpsa_getpciinfo_ioctl(h, argp);
6585 case CCISS_GETDRIVVER:
6586 return hpsa_getdrivver_ioctl(h, argp);
6587 case CCISS_PASSTHRU:
34f0c627 6588 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6589 return -EAGAIN;
6590 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6591 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6592 return rc;
edd16368 6593 case CCISS_BIG_PASSTHRU:
34f0c627 6594 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6595 return -EAGAIN;
6596 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6597 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6598 return rc;
edd16368
SC		 6599 default:
6600 return -ENOTTY;
6601 }
6602}
6603
bf43caf3 6604static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6605 u8 reset_type)
64670ac8
SC		 6606{
6607 struct CommandList *c;
6608
6609 c = cmd_alloc(h);
bf43caf3 6610
a2dac136
SC		 6611 /* fill_cmd can't fail here, no data buffer to map */
6612 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6613 RAID_CTLR_LUNID, TYPE_MSG);
6614 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6615 c->waiting = NULL;
6616 enqueue_cmd_and_start_io(h, c);
6617 /* Don't wait for completion, the reset won't complete. Don't free
6618 * the command either. This is the last command we will send before
6619 * re-initializing everything, so it doesn't matter and won't leak.
6620 */
bf43caf3 6621 return;
64670ac8
SC		 6622}
6623
a2dac136 6624static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6625 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6626 int cmd_type)
6627{
6628 int pci_dir = XFER_NONE;
9b5c48c2 6629 u64 tag; /* for commands to be aborted */
edd16368
SC		 6630
6631 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6632 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6633 c->Header.ReplyQueue = 0;
6634 if (buff != NULL && size > 0) {
6635 c->Header.SGList = 1;
50a0decf 6636 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6637 } else {
6638 c->Header.SGList = 0;
50a0decf 6639 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6640 }
edd16368
SC		 6641 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6642
edd16368
SC		 6643 if (cmd_type == TYPE_CMD) {
6644 switch (cmd) {
6645 case HPSA_INQUIRY:
6646 /* are we trying to read a vital product page */
b7bb24eb 6647 if (page_code & VPD_PAGE) {
edd16368 6648 c->Request.CDB[1] = 0x01;
b7bb24eb 6649 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6650 }
6651 c->Request.CDBLen = 6;
a505b86f
SC		 6652 c->Request.type_attr_dir =
6653 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6654 c->Request.Timeout = 0;
6655 c->Request.CDB[0] = HPSA_INQUIRY;
6656 c->Request.CDB[4] = size & 0xFF;
6657 break;
6658 case HPSA_REPORT_LOG:
6659 case HPSA_REPORT_PHYS:
6660 /* Talking to controller so It's a physical command
6661 mode = 00 target = 0. Nothing to write.
6662 */
6663 c->Request.CDBLen = 12;
a505b86f
SC		 6664 c->Request.type_attr_dir =
6665 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6666 c->Request.Timeout = 0;
6667 c->Request.CDB[0] = cmd;
6668 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6669 c->Request.CDB[7] = (size >> 16) & 0xFF;
6670 c->Request.CDB[8] = (size >> 8) & 0xFF;
6671 c->Request.CDB[9] = size & 0xFF;
6672 break;
c2adae44
ST		 6673 case BMIC_SENSE_DIAG_OPTIONS:
6674 c->Request.CDBLen = 16;
6675 c->Request.type_attr_dir =
6676 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6677 c->Request.Timeout = 0;
6678 /* Spec says this should be BMIC_WRITE */
6679 c->Request.CDB[0] = BMIC_READ;
6680 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6681 break;
6682 case BMIC_SET_DIAG_OPTIONS:
6683 c->Request.CDBLen = 16;
6684 c->Request.type_attr_dir =
6685 TYPE_ATTR_DIR(cmd_type,
6686 ATTR_SIMPLE, XFER_WRITE);
6687 c->Request.Timeout = 0;
6688 c->Request.CDB[0] = BMIC_WRITE;
6689 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6690 break;
edd16368
SC		 6691 case HPSA_CACHE_FLUSH:
6692 c->Request.CDBLen = 12;
a505b86f
SC		 6693 c->Request.type_attr_dir =
6694 TYPE_ATTR_DIR(cmd_type,
6695 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6696 c->Request.Timeout = 0;
6697 c->Request.CDB[0] = BMIC_WRITE;
6698 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6699 c->Request.CDB[7] = (size >> 8) & 0xFF;
6700 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6701 break;
6702 case TEST_UNIT_READY:
6703 c->Request.CDBLen = 6;
a505b86f
SC		 6704 c->Request.type_attr_dir =
6705 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6706 c->Request.Timeout = 0;
6707 break;
283b4a9b
SC		 6708 case HPSA_GET_RAID_MAP:
6709 c->Request.CDBLen = 12;
a505b86f
SC		 6710 c->Request.type_attr_dir =
6711 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6712 c->Request.Timeout = 0;
6713 c->Request.CDB[0] = HPSA_CISS_READ;
6714 c->Request.CDB[1] = cmd;
6715 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6716 c->Request.CDB[7] = (size >> 16) & 0xFF;
6717 c->Request.CDB[8] = (size >> 8) & 0xFF;
6718 c->Request.CDB[9] = size & 0xFF;
6719 break;
316b221a
SC		 6720 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6721 c->Request.CDBLen = 10;
a505b86f
SC		 6722 c->Request.type_attr_dir =
6723 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6724 c->Request.Timeout = 0;
6725 c->Request.CDB[0] = BMIC_READ;
6726 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6727 c->Request.CDB[7] = (size >> 16) & 0xFF;
6728 c->Request.CDB[8] = (size >> 8) & 0xFF;
6729 break;
03383736
DB		 6730 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6731 c->Request.CDBLen = 10;
6732 c->Request.type_attr_dir =
6733 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6734 c->Request.Timeout = 0;
6735 c->Request.CDB[0] = BMIC_READ;
6736 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6737 c->Request.CDB[7] = (size >> 16) & 0xFF;
6738 c->Request.CDB[8] = (size >> 8) & 0XFF;
6739 break;
d04e62b9
KB		 6740 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6741 c->Request.CDBLen = 10;
6742 c->Request.type_attr_dir =
6743 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6744 c->Request.Timeout = 0;
6745 c->Request.CDB[0] = BMIC_READ;
6746 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6747 c->Request.CDB[7] = (size >> 16) & 0xFF;
6748 c->Request.CDB[8] = (size >> 8) & 0XFF;
6749 break;
cca8f13b
DB		 6750 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6751 c->Request.CDBLen = 10;
6752 c->Request.type_attr_dir =
6753 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6754 c->Request.Timeout = 0;
6755 c->Request.CDB[0] = BMIC_READ;
6756 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6757 c->Request.CDB[7] = (size >> 16) & 0xFF;
6758 c->Request.CDB[8] = (size >> 8) & 0XFF;
6759 break;
66749d0d
ST		 6760 case BMIC_IDENTIFY_CONTROLLER:
6761 c->Request.CDBLen = 10;
6762 c->Request.type_attr_dir =
6763 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6764 c->Request.Timeout = 0;
6765 c->Request.CDB[0] = BMIC_READ;
6766 c->Request.CDB[1] = 0;
6767 c->Request.CDB[2] = 0;
6768 c->Request.CDB[3] = 0;
6769 c->Request.CDB[4] = 0;
6770 c->Request.CDB[5] = 0;
6771 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6772 c->Request.CDB[7] = (size >> 16) & 0xFF;
6773 c->Request.CDB[8] = (size >> 8) & 0XFF;
6774 c->Request.CDB[9] = 0;
6775 break;
edd16368
SC		 6776 default:
6777 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6778 BUG();
a2dac136 6779 return -1;
edd16368
SC		 6780 }
6781 } else if (cmd_type == TYPE_MSG) {
6782 switch (cmd) {
6783
0b9b7b6e
ST		 6784 case HPSA_PHYS_TARGET_RESET:
6785 c->Request.CDBLen = 16;
6786 c->Request.type_attr_dir =
6787 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6788 c->Request.Timeout = 0; /* Don't time out */
6789 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6790 c->Request.CDB[0] = HPSA_RESET;
6791 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6792 /* Physical target reset needs no control bytes 4-7*/
6793 c->Request.CDB[4] = 0x00;
6794 c->Request.CDB[5] = 0x00;
6795 c->Request.CDB[6] = 0x00;
6796 c->Request.CDB[7] = 0x00;
6797 break;
edd16368
SC		 6798 case HPSA_DEVICE_RESET_MSG:
6799 c->Request.CDBLen = 16;
a505b86f
SC		 6800 c->Request.type_attr_dir =
6801 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6802 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6803 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6804 c->Request.CDB[0] = cmd;
21e89afd 6805 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6806 /* If bytes 4-7 are zero, it means reset the */
6807 /* LunID device */
6808 c->Request.CDB[4] = 0x00;
6809 c->Request.CDB[5] = 0x00;
6810 c->Request.CDB[6] = 0x00;
6811 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6812 break;
6813 case HPSA_ABORT_MSG:
9b5c48c2 6814 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6815 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6816 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6817 tag, c->Header.tag);
75167d2c 6818 c->Request.CDBLen = 16;
a505b86f
SC		 6819 c->Request.type_attr_dir =
6820 TYPE_ATTR_DIR(cmd_type,
6821 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6822 c->Request.Timeout = 0; /* Don't time out */
6823 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6824 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6825 c->Request.CDB[2] = 0x00; /* reserved */
6826 c->Request.CDB[3] = 0x00; /* reserved */
6827 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6828 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6829 c->Request.CDB[12] = 0x00; /* reserved */
6830 c->Request.CDB[13] = 0x00; /* reserved */
6831 c->Request.CDB[14] = 0x00; /* reserved */
6832 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6833 break;
edd16368
SC		 6834 default:
6835 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6836 cmd);
6837 BUG();
6838 }
6839 } else {
6840 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6841 BUG();
6842 }
6843
a505b86f 6844 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6845 case XFER_READ:
6846 pci_dir = PCI_DMA_FROMDEVICE;
6847 break;
6848 case XFER_WRITE:
6849 pci_dir = PCI_DMA_TODEVICE;
6850 break;
6851 case XFER_NONE:
6852 pci_dir = PCI_DMA_NONE;
6853 break;
6854 default:
6855 pci_dir = PCI_DMA_BIDIRECTIONAL;
6856 }
a2dac136
SC		 6857 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6858 return -1;
6859 return 0;
edd16368
SC		 6860}
6861
6862/*
6863 * Map (physical) PCI mem into (virtual) kernel space
6864 */
6865static void __iomem *remap_pci_mem(ulong base, ulong size)
6866{
6867 ulong page_base = ((ulong) base) & PAGE_MASK;
6868 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6869 void __iomem *page_remapped = ioremap_nocache(page_base,
6870 page_offs + size);
edd16368
SC		 6871
6872 return page_remapped ? (page_remapped + page_offs) : NULL;
6873}
6874
254f796b 6875static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6876{
254f796b 6877 return h->access.command_completed(h, q);
edd16368
SC		 6878}
6879
900c5440 6880static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6881{
6882 return h->access.intr_pending(h);
6883}
6884
6885static inline long interrupt_not_for_us(struct ctlr_info *h)
6886{
10f66018
SC		 6887 return (h->access.intr_pending(h) == 0) ||
6888 (h->interrupts_enabled == 0);
edd16368
SC		 6889}
6890
01a02ffc
SC		 6891static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6892 u32 raw_tag)
edd16368
SC		 6893{
6894 if (unlikely(tag_index >= h->nr_cmds)) {
6895 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6896 return 1;
6897 }
6898 return 0;
6899}
6900
5a3d16f5 6901static inline void finish_cmd(struct CommandList *c)
edd16368 6902{
e85c5974 6903 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6904 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6905 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6906 complete_scsi_command(c);
8be986cc 6907 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6908 complete(c->waiting);
a104c99f
SC		 6909}
6910
303932fd 6911/* process completion of an indexed ("direct lookup") command */
1d94f94d 6912static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6913 u32 raw_tag)
6914{
6915 u32 tag_index;
6916 struct CommandList *c;
6917
f2405db8 6918 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6919 if (!bad_tag(h, tag_index, raw_tag)) {
6920 c = h->cmd_pool + tag_index;
6921 finish_cmd(c);
6922 }
303932fd
DB		 6923}
6924
64670ac8
SC		 6925/* Some controllers, like p400, will give us one interrupt
6926 * after a soft reset, even if we turned interrupts off.
6927 * Only need to check for this in the hpsa_xxx_discard_completions
6928 * functions.
6929 */
6930static int ignore_bogus_interrupt(struct ctlr_info *h)
6931{
6932 if (likely(!reset_devices))
6933 return 0;
6934
6935 if (likely(h->interrupts_enabled))
6936 return 0;
6937
6938 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6939 "(known firmware bug.) Ignoring.\n");
6940
6941 return 1;
6942}
6943
254f796b
MG		 6944/*
6945 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6946 * Relies on (h-q[x] == x) being true for x such that
6947 * 0 <= x < MAX_REPLY_QUEUES.
6948 */
6949static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6950{
254f796b
MG		 6951 return container_of((queue - *queue), struct ctlr_info, q[0]);
6952}
6953
6954static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6955{
6956 struct ctlr_info *h = queue_to_hba(queue);
6957 u8 q = *(u8 *) queue;
64670ac8
SC		 6958 u32 raw_tag;
6959
6960 if (ignore_bogus_interrupt(h))
6961 return IRQ_NONE;
6962
6963 if (interrupt_not_for_us(h))
6964 return IRQ_NONE;
a0c12413 6965 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6966 while (interrupt_pending(h)) {
254f796b 6967 raw_tag = get_next_completion(h, q);
64670ac8 6968 while (raw_tag != FIFO_EMPTY)
254f796b 6969 raw_tag = next_command(h, q);
64670ac8 6970 }
64670ac8
SC		 6971 return IRQ_HANDLED;
6972}
6973
254f796b 6974static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6975{
254f796b 6976 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6977 u32 raw_tag;
254f796b 6978 u8 q = *(u8 *) queue;
64670ac8
SC		 6979
6980 if (ignore_bogus_interrupt(h))
6981 return IRQ_NONE;
6982
a0c12413 6983 h->last_intr_timestamp = get_jiffies_64();
254f796b 6984 raw_tag = get_next_completion(h, q);
64670ac8 6985 while (raw_tag != FIFO_EMPTY)
254f796b 6986 raw_tag = next_command(h, q);
64670ac8
SC		 6987 return IRQ_HANDLED;
6988}
6989
254f796b 6990static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6991{
254f796b 6992 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6993 u32 raw_tag;
254f796b 6994 u8 q = *(u8 *) queue;
edd16368
SC		 6995
6996 if (interrupt_not_for_us(h))
6997 return IRQ_NONE;
a0c12413 6998 h->last_intr_timestamp = get_jiffies_64();
10f66018 6999 while (interrupt_pending(h)) {
254f796b 7000 raw_tag = get_next_completion(h, q);
10f66018 7001 while (raw_tag != FIFO_EMPTY) {
f2405db8 7002 process_indexed_cmd(h, raw_tag);
254f796b 7003 raw_tag = next_command(h, q);
10f66018
SC		 7004 }
7005 }
10f66018
SC		 7006 return IRQ_HANDLED;
7007}
7008
254f796b 7009static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 7010{
254f796b 7011 struct ctlr_info *h = queue_to_hba(queue);
10f66018 7012 u32 raw_tag;
254f796b 7013 u8 q = *(u8 *) queue;
10f66018 7014
a0c12413 7015 h->last_intr_timestamp = get_jiffies_64();
254f796b 7016 raw_tag = get_next_completion(h, q);
303932fd 7017 while (raw_tag != FIFO_EMPTY) {
f2405db8 7018 process_indexed_cmd(h, raw_tag);
254f796b 7019 raw_tag = next_command(h, q);
edd16368 7020 }
edd16368
SC		 7021 return IRQ_HANDLED;
7022}
7023
a9a3a273
SC		 7024/* Send a message CDB to the firmware. Careful, this only works
7025 * in simple mode, not performant mode due to the tag lookup.
7026 * We only ever use this immediately after a controller reset.
7027 */
6f039790
GKH		 7028static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
7029 unsigned char type)
edd16368
SC		 7030{
7031 struct Command {
7032 struct CommandListHeader CommandHeader;
7033 struct RequestBlock Request;
7034 struct ErrDescriptor ErrorDescriptor;
7035 };
7036 struct Command *cmd;
7037 static const size_t cmd_sz = sizeof(*cmd) +
7038 sizeof(cmd->ErrorDescriptor);
7039 dma_addr_t paddr64;
2b08b3e9
DB		 7040 __le32 paddr32;
7041 u32 tag;
edd16368
SC		 7042 void __iomem *vaddr;
7043 int i, err;
7044
7045 vaddr = pci_ioremap_bar(pdev, 0);
7046 if (vaddr == NULL)
7047 return -ENOMEM;
7048
7049 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7050 * CCISS commands, so they must be allocated from the lower 4GiB of
7051 * memory.
7052 */
7053 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7054 if (err) {
7055 iounmap(vaddr);
1eaec8f3 7056 return err;
edd16368
SC		 7057 }
7058
7059 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
7060 if (cmd == NULL) {
7061 iounmap(vaddr);
7062 return -ENOMEM;
7063 }
7064
7065 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7066 * although there's no guarantee, we assume that the address is at
7067 * least 4-byte aligned (most likely, it's page-aligned).
7068 */
2b08b3e9 7069 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7070
7071 cmd->CommandHeader.ReplyQueue = 0;
7072 cmd->CommandHeader.SGList = 0;
50a0decf 7073 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7074 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7075 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7076
7077 cmd->Request.CDBLen = 16;
a505b86f
SC		 7078 cmd->Request.type_attr_dir =
7079 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7080 cmd->Request.Timeout = 0; /* Don't time out */
7081 cmd->Request.CDB[0] = opcode;
7082 cmd->Request.CDB[1] = type;
7083 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7084 cmd->ErrorDescriptor.Addr =
2b08b3e9 7085 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7086 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7087
2b08b3e9 7088 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7089
7090 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7091 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7092 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7093 break;
7094 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7095 }
7096
7097 iounmap(vaddr);
7098
7099 /* we leak the DMA buffer here ... no choice since the controller could
7100 * still complete the command.
7101 */
7102 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7103 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7104 opcode, type);
7105 return -ETIMEDOUT;
7106 }
7107
7108 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
7109
7110 if (tag & HPSA_ERROR_BIT) {
7111 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7112 opcode, type);
7113 return -EIO;
7114 }
7115
7116 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7117 opcode, type);
7118 return 0;
7119}
7120
edd16368
SC		 7121#define hpsa_noop(p) hpsa_message(p, 3, 0)
7122
1df8552a 7123static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7124 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7125{
1df8552a
SC		 7126
7127 if (use_doorbell) {
7128 /* For everything after the P600, the PCI power state method
7129 * of resetting the controller doesn't work, so we have this
7130 * other way using the doorbell register.
7131 */
7132 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7133 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7134
00701a96 7135 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7136 * doorbell reset and before any attempt to talk to the board
7137 * at all to ensure that this actually works and doesn't fall
7138 * over in some weird corner cases.
7139 */
00701a96 7140 msleep(10000);
1df8552a
SC		 7141 } else { /* Try to do it the PCI power state way */
7142
7143 /* Quoting from the Open CISS Specification: "The Power
7144 * Management Control/Status Register (CSR) controls the power
7145 * state of the device. The normal operating state is D0,
7146 * CSR=00h. The software off state is D3, CSR=03h. To reset
7147 * the controller, place the interface device in D3 then to D0,
7148 * this causes a secondary PCI reset which will reset the
7149 * controller." */
2662cab8
DB		 7150
7151 int rc = 0;
7152
1df8552a 7153 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7154
1df8552a 7155 /* enter the D3hot power management state */
2662cab8
DB		 7156 rc = pci_set_power_state(pdev, PCI_D3hot);
7157 if (rc)
7158 return rc;
1df8552a
SC		 7159
7160 msleep(500);
7161
7162 /* enter the D0 power management state */
2662cab8
DB		 7163 rc = pci_set_power_state(pdev, PCI_D0);
7164 if (rc)
7165 return rc;
c4853efe
MM		 7166
7167 /*
7168 * The P600 requires a small delay when changing states.
7169 * Otherwise we may think the board did not reset and we bail.
7170 * This for kdump only and is particular to the P600.
7171 */
7172 msleep(500);
1df8552a
SC		 7173 }
7174 return 0;
7175}
7176
6f039790 7177static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7178{
7179 memset(driver_version, 0, len);
f79cfec6 7180 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7181}
7182
6f039790 7183static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7184{
7185 char *driver_version;
7186 int i, size = sizeof(cfgtable->driver_version);
7187
7188 driver_version = kmalloc(size, GFP_KERNEL);
7189 if (!driver_version)
7190 return -ENOMEM;
7191
7192 init_driver_version(driver_version, size);
7193 for (i = 0; i < size; i++)
7194 writeb(driver_version[i], &cfgtable->driver_version[i]);
7195 kfree(driver_version);
7196 return 0;
7197}
7198
6f039790
GKH		 7199static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7200 unsigned char *driver_ver)
580ada3c
SC		 7201{
7202 int i;
7203
7204 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7205 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7206}
7207
6f039790 7208static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7209{
7210
7211 char *driver_ver, *old_driver_ver;
7212 int rc, size = sizeof(cfgtable->driver_version);
7213
7214 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
7215 if (!old_driver_ver)
7216 return -ENOMEM;
7217 driver_ver = old_driver_ver + size;
7218
7219 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7220 * should have been changed, otherwise we know the reset failed.
7221 */
7222 init_driver_version(old_driver_ver, size);
7223 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7224 rc = !memcmp(driver_ver, old_driver_ver, size);
7225 kfree(old_driver_ver);
7226 return rc;
7227}
edd16368 7228/* This does a hard reset of the controller using PCI power management
1df8552a 7229 * states or the using the doorbell register.
edd16368 7230 */
6b6c1cd7 7231static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7232{
1df8552a
SC		 7233 u64 cfg_offset;
7234 u32 cfg_base_addr;
7235 u64 cfg_base_addr_index;
7236 void __iomem *vaddr;
7237 unsigned long paddr;
580ada3c 7238 u32 misc_fw_support;
270d05de 7239 int rc;
1df8552a 7240 struct CfgTable __iomem *cfgtable;
cf0b08d0 7241 u32 use_doorbell;
270d05de 7242 u16 command_register;
edd16368 7243
1df8552a
SC		 7244 /* For controllers as old as the P600, this is very nearly
7245 * the same thing as
edd16368
SC		 7246 *
7247 * pci_save_state(pci_dev);
7248 * pci_set_power_state(pci_dev, PCI_D3hot);
7249 * pci_set_power_state(pci_dev, PCI_D0);
7250 * pci_restore_state(pci_dev);
7251 *
1df8552a
SC		 7252 * For controllers newer than the P600, the pci power state
7253 * method of resetting doesn't work so we have another way
7254 * using the doorbell register.
edd16368 7255 */
18867659 7256
60f923b9
RE		 7257 if (!ctlr_is_resettable(board_id)) {
7258 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7259 return -ENODEV;
7260 }
46380786
SC		 7261
7262 /* if controller is soft- but not hard resettable... */
7263 if (!ctlr_is_hard_resettable(board_id))
7264 return -ENOTSUPP; /* try soft reset later. */
18867659 7265
270d05de
SC		 7266 /* Save the PCI command register */
7267 pci_read_config_word(pdev, 4, &command_register);
270d05de 7268 pci_save_state(pdev);
edd16368 7269
1df8552a
SC		 7270 /* find the first memory BAR, so we can find the cfg table */
7271 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7272 if (rc)
7273 return rc;
7274 vaddr = remap_pci_mem(paddr, 0x250);
7275 if (!vaddr)
7276 return -ENOMEM;
edd16368 7277
1df8552a
SC		 7278 /* find cfgtable in order to check if reset via doorbell is supported */
7279 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7280 &cfg_base_addr_index, &cfg_offset);
7281 if (rc)
7282 goto unmap_vaddr;
7283 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7284 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7285 if (!cfgtable) {
7286 rc = -ENOMEM;
7287 goto unmap_vaddr;
7288 }
580ada3c
SC		 7289 rc = write_driver_ver_to_cfgtable(cfgtable);
7290 if (rc)
03741d95 7291 goto unmap_cfgtable;
edd16368 7292
cf0b08d0
SC		 7293 /* If reset via doorbell register is supported, use that.
7294 * There are two such methods. Favor the newest method.
7295 */
1df8552a 7296 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7297 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7298 if (use_doorbell) {
7299 use_doorbell = DOORBELL_CTLR_RESET2;
7300 } else {
7301 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7302 if (use_doorbell) {
050f7147
SC		 7303 dev_warn(&pdev->dev,
7304 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7305 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7306 goto unmap_cfgtable;
7307 }
7308 }
edd16368 7309
1df8552a
SC		 7310 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7311 if (rc)
7312 goto unmap_cfgtable;
edd16368 7313
270d05de 7314 pci_restore_state(pdev);
270d05de 7315 pci_write_config_word(pdev, 4, command_register);
edd16368 7316
1df8552a
SC		 7317 /* Some devices (notably the HP Smart Array 5i Controller)
7318 need a little pause here */
7319 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7320
fe5389c8
SC		 7321 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7322 if (rc) {
7323 dev_warn(&pdev->dev,
050f7147 7324 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7325 goto unmap_cfgtable;
7326 }
fe5389c8 7327
580ada3c
SC		 7328 rc = controller_reset_failed(vaddr);
7329 if (rc < 0)
7330 goto unmap_cfgtable;
7331 if (rc) {
64670ac8
SC		 7332 dev_warn(&pdev->dev, "Unable to successfully reset "
7333 "controller. Will try soft reset.\n");
7334 rc = -ENOTSUPP;
580ada3c 7335 } else {
64670ac8 7336 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7337 }
7338
7339unmap_cfgtable:
7340 iounmap(cfgtable);
7341
7342unmap_vaddr:
7343 iounmap(vaddr);
7344 return rc;
edd16368
SC		 7345}
7346
7347/*
7348 * We cannot read the structure directly, for portability we must use
7349 * the io functions.
7350 * This is for debug only.
7351 */
42a91641 7352static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7353{
58f8665c 7354#ifdef HPSA_DEBUG
edd16368
SC		 7355 int i;
7356 char temp_name[17];
7357
7358 dev_info(dev, "Controller Configuration information\n");
7359 dev_info(dev, "------------------------------------\n");
7360 for (i = 0; i < 4; i++)
7361 temp_name[i] = readb(&(tb->Signature[i]));
7362 temp_name[4] = '\0';
7363 dev_info(dev, " Signature = %s\n", temp_name);
7364 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7365 dev_info(dev, " Transport methods supported = 0x%x\n",
7366 readl(&(tb->TransportSupport)));
7367 dev_info(dev, " Transport methods active = 0x%x\n",
7368 readl(&(tb->TransportActive)));
7369 dev_info(dev, " Requested transport Method = 0x%x\n",
7370 readl(&(tb->HostWrite.TransportRequest)));
7371 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7372 readl(&(tb->HostWrite.CoalIntDelay)));
7373 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7374 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7375 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7376 readl(&(tb->CmdsOutMax)));
7377 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7378 for (i = 0; i < 16; i++)
7379 temp_name[i] = readb(&(tb->ServerName[i]));
7380 temp_name[16] = '\0';
7381 dev_info(dev, " Server Name = %s\n", temp_name);
7382 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7383 readl(&(tb->HeartBeat)));
edd16368 7384#endif /* HPSA_DEBUG */
58f8665c 7385}
edd16368
SC		 7386
7387static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7388{
7389 int i, offset, mem_type, bar_type;
7390
7391 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7392 return 0;
7393 offset = 0;
7394 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7395 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7396 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7397 offset += 4;
7398 else {
7399 mem_type = pci_resource_flags(pdev, i) &
7400 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7401 switch (mem_type) {
7402 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7403 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7404 offset += 4; /* 32 bit */
7405 break;
7406 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7407 offset += 8;
7408 break;
7409 default: /* reserved in PCI 2.2 */
7410 dev_warn(&pdev->dev,
7411 "base address is invalid\n");
7412 return -1;
7413 break;
7414 }
7415 }
7416 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7417 return i + 1;
7418 }
7419 return -1;
7420}
7421
cc64c817
RE		 7422static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7423{
7424 if (h->msix_vector) {
7425 if (h->pdev->msix_enabled)
7426 pci_disable_msix(h->pdev);
105a3dbc 7427 h->msix_vector = 0;
cc64c817
RE		 7428 } else if (h->msi_vector) {
7429 if (h->pdev->msi_enabled)
7430 pci_disable_msi(h->pdev);
105a3dbc 7431 h->msi_vector = 0;
cc64c817
RE		 7432 }
7433}
7434
edd16368 7435/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7436 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7437 */
6f039790 7438static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7439{
7440#ifdef CONFIG_PCI_MSI
254f796b
MG		 7441 int err, i;
7442 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7443
7444 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7445 hpsa_msix_entries[i].vector = 0;
7446 hpsa_msix_entries[i].entry = i;
7447 }
edd16368
SC		 7448
7449 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7450 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7451 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7452 goto default_int_mode;
55c06c71 7453 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7454 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7455 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7456 if (h->msix_vector > num_online_cpus())
7457 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7458 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7459 1, h->msix_vector);
7460 if (err < 0) {
7461 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7462 h->msix_vector = 0;
7463 goto single_msi_mode;
7464 } else if (err < h->msix_vector) {
55c06c71 7465 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7466 "available\n", err);
edd16368 7467 }
18fce3c4
AG		 7468 h->msix_vector = err;
7469 for (i = 0; i < h->msix_vector; i++)
7470 h->intr[i] = hpsa_msix_entries[i].vector;
7471 return;
edd16368 7472 }
18fce3c4 7473single_msi_mode:
55c06c71 7474 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7475 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7476 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7477 h->msi_vector = 1;
7478 else
55c06c71 7479 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7480 }
7481default_int_mode:
7482#endif /* CONFIG_PCI_MSI */
7483 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7484 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7485}
7486
6f039790 7487static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7488{
7489 int i;
7490 u32 subsystem_vendor_id, subsystem_device_id;
7491
7492 subsystem_vendor_id = pdev->subsystem_vendor;
7493 subsystem_device_id = pdev->subsystem_device;
7494 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7495 subsystem_vendor_id;
7496
7497 for (i = 0; i < ARRAY_SIZE(products); i++)
7498 if (*board_id == products[i].board_id)
7499 return i;
7500
6798cc0a
SC		 7501 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7502 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7503 !hpsa_allow_any) {
e5c880d1
SC		 7504 dev_warn(&pdev->dev, "unrecognized board ID: "
7505 "0x%08x, ignoring.\n", *board_id);
7506 return -ENODEV;
7507 }
7508 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7509}
7510
6f039790
GKH		 7511static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7512 unsigned long *memory_bar)
3a7774ce
SC		 7513{
7514 int i;
7515
7516 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7517 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7518 /* addressing mode bits already removed */
12d2cd47
SC		 7519 *memory_bar = pci_resource_start(pdev, i);
7520 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7521 *memory_bar);
7522 return 0;
7523 }
12d2cd47 7524 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7525 return -ENODEV;
7526}
7527
6f039790
GKH		 7528static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7529 int wait_for_ready)
2c4c8c8b 7530{
fe5389c8 7531 int i, iterations;
2c4c8c8b 7532 u32 scratchpad;
fe5389c8
SC		 7533 if (wait_for_ready)
7534 iterations = HPSA_BOARD_READY_ITERATIONS;
7535 else
7536 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7537
fe5389c8
SC		 7538 for (i = 0; i < iterations; i++) {
7539 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7540 if (wait_for_ready) {
7541 if (scratchpad == HPSA_FIRMWARE_READY)
7542 return 0;
7543 } else {
7544 if (scratchpad != HPSA_FIRMWARE_READY)
7545 return 0;
7546 }
2c4c8c8b
SC		 7547 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7548 }
fe5389c8 7549 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7550 return -ENODEV;
7551}
7552
6f039790
GKH		 7553static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7554 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7555 u64 *cfg_offset)
a51fd47f
SC		 7556{
7557 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7558 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7559 *cfg_base_addr &= (u32) 0x0000ffff;
7560 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7561 if (*cfg_base_addr_index == -1) {
7562 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7563 return -ENODEV;
7564 }
7565 return 0;
7566}
7567
195f2c65
RE		 7568static void hpsa_free_cfgtables(struct ctlr_info *h)
7569{
105a3dbc 7570 if (h->transtable) {
195f2c65 7571 iounmap(h->transtable);
105a3dbc
RE		 7572 h->transtable = NULL;
7573 }
7574 if (h->cfgtable) {
195f2c65 7575 iounmap(h->cfgtable);
105a3dbc
RE		 7576 h->cfgtable = NULL;
7577 }
195f2c65
RE		 7578}
7579
7580/* Find and map CISS config table and transfer table
7581+ * several items must be unmapped (freed) later
7582+ * */
6f039790 7583static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7584{
01a02ffc
SC		 7585 u64 cfg_offset;
7586 u32 cfg_base_addr;
7587 u64 cfg_base_addr_index;
303932fd 7588 u32 trans_offset;
a51fd47f 7589 int rc;
77c4495c 7590
a51fd47f
SC		 7591 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7592 &cfg_base_addr_index, &cfg_offset);
7593 if (rc)
7594 return rc;
77c4495c 7595 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7596 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7597 if (!h->cfgtable) {
7598 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7599 return -ENOMEM;
cd3c81c4 7600 }
580ada3c
SC		 7601 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7602 if (rc)
7603 return rc;
77c4495c 7604 /* Find performant mode table. */
a51fd47f 7605 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7606 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7607 cfg_base_addr_index)+cfg_offset+trans_offset,
7608 sizeof(*h->transtable));
195f2c65
RE		 7609 if (!h->transtable) {
7610 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7611 hpsa_free_cfgtables(h);
77c4495c 7612 return -ENOMEM;
195f2c65 7613 }
77c4495c
SC		 7614 return 0;
7615}
7616
6f039790 7617static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7618{
41ce4c35
SC		 7619#define MIN_MAX_COMMANDS 16
7620 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7621
7622 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7623
7624 /* Limit commands in memory limited kdump scenario. */
7625 if (reset_devices && h->max_commands > 32)
7626 h->max_commands = 32;
7627
41ce4c35
SC		 7628 if (h->max_commands < MIN_MAX_COMMANDS) {
7629 dev_warn(&h->pdev->dev,
7630 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7631 h->max_commands,
7632 MIN_MAX_COMMANDS);
7633 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7634 }
7635}
7636
c7ee65b3
WS		 7637/* If the controller reports that the total max sg entries is greater than 512,
7638 * then we know that chained SG blocks work. (Original smart arrays did not
7639 * support chained SG blocks and would return zero for max sg entries.)
7640 */
7641static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7642{
7643 return h->maxsgentries > 512;
7644}
7645
b93d7536
SC		 7646/* Interrogate the hardware for some limits:
7647 * max commands, max SG elements without chaining, and with chaining,
7648 * SG chain block size, etc.
7649 */
6f039790 7650static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7651{
cba3d38b 7652 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7653 h->nr_cmds = h->max_commands;
b93d7536 7654 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7655 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7656 if (hpsa_supports_chained_sg_blocks(h)) {
7657 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7658 h->max_cmd_sg_entries = 32;
1a63ea6f 7659 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7660 h->maxsgentries--; /* save one for chain pointer */
7661 } else {
c7ee65b3
WS		 7662 /*
7663 * Original smart arrays supported at most 31 s/g entries
7664 * embedded inline in the command (trying to use more
7665 * would lock up the controller)
7666 */
7667 h->max_cmd_sg_entries = 31;
1a63ea6f 7668 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7669 h->chainsize = 0;
b93d7536 7670 }
75167d2c
SC		 7671
7672 /* Find out what task management functions are supported and cache */
7673 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7674 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7675 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7676 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7677 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7678 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7679 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7680}
7681
76c46e49
SC		 7682static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7683{
0fc9fd40 7684 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7685 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7686 return false;
7687 }
7688 return true;
7689}
7690
97a5e98c 7691static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7692{
97a5e98c 7693 u32 driver_support;
f7c39101 7694
97a5e98c 7695 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7696 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7697#ifdef CONFIG_X86
97a5e98c 7698 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7699#endif
28e13446
SC		 7700 driver_support |= ENABLE_UNIT_ATTN;
7701 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7702}
7703
3d0eab67
SC		 7704/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7705 * in a prefetch beyond physical memory.
7706 */
7707static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7708{
7709 u32 dma_prefetch;
7710
7711 if (h->board_id != 0x3225103C)
7712 return;
7713 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7714 dma_prefetch |= 0x8000;
7715 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7716}
7717
c706a795 7718static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7719{
7720 int i;
7721 u32 doorbell_value;
7722 unsigned long flags;
7723 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7724 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7725 spin_lock_irqsave(&h->lock, flags);
7726 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7727 spin_unlock_irqrestore(&h->lock, flags);
7728 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7729 goto done;
76438d08 7730 /* delay and try again */
007e7aa9 7731 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7732 }
c706a795
RE		 7733 return -ENODEV;
7734done:
7735 return 0;
76438d08
SC		 7736}
7737
c706a795 7738static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7739{
7740 int i;
6eaf46fd
SC		 7741 u32 doorbell_value;
7742 unsigned long flags;
eb6b2ae9
SC		 7743
7744 /* under certain very rare conditions, this can take awhile.
7745 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7746 * as we enter this code.)
7747 */
007e7aa9 7748 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7749 if (h->remove_in_progress)
7750 goto done;
6eaf46fd
SC		 7751 spin_lock_irqsave(&h->lock, flags);
7752 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7753 spin_unlock_irqrestore(&h->lock, flags);
382be668 7754 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7755 goto done;
eb6b2ae9 7756 /* delay and try again */
007e7aa9 7757 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7758 }
c706a795
RE		 7759 return -ENODEV;
7760done:
7761 return 0;
3f4336f3
SC		 7762}
7763
c706a795 7764/* return -ENODEV or other reason on error, 0 on success */
6f039790 7765static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7766{
7767 u32 trans_support;
7768
7769 trans_support = readl(&(h->cfgtable->TransportSupport));
7770 if (!(trans_support & SIMPLE_MODE))
7771 return -ENOTSUPP;
7772
7773 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7774
3f4336f3
SC		 7775 /* Update the field, and then ring the doorbell */
7776 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7777 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7778 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7779 if (hpsa_wait_for_mode_change_ack(h))
7780 goto error;
eb6b2ae9 7781 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7782 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7783 goto error;
960a30e7 7784 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7785 return 0;
283b4a9b 7786error:
050f7147 7787 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7788 return -ENODEV;
eb6b2ae9
SC		 7789}
7790
195f2c65
RE		 7791/* free items allocated or mapped by hpsa_pci_init */
7792static void hpsa_free_pci_init(struct ctlr_info *h)
7793{
7794 hpsa_free_cfgtables(h); /* pci_init 4 */
7795 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7796 h->vaddr = NULL;
195f2c65 7797 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7798 /*
7799 * call pci_disable_device before pci_release_regions per
7800 * Documentation/PCI/pci.txt
7801 */
195f2c65 7802 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7803 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7804}
7805
7806/* several items must be freed later */
6f039790 7807static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7808{
eb6b2ae9 7809 int prod_index, err;
edd16368 7810
e5c880d1
SC		 7811 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7812 if (prod_index < 0)
60f923b9 7813 return prod_index;
e5c880d1
SC		 7814 h->product_name = products[prod_index].product_name;
7815 h->access = *(products[prod_index].access);
edd16368 7816
9b5c48c2
SC		 7817 h->needs_abort_tags_swizzled =
7818 ctlr_needs_abort_tags_swizzled(h->board_id);
7819
e5a44df8
MG		 7820 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7821 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7822
55c06c71 7823 err = pci_enable_device(h->pdev);
edd16368 7824 if (err) {
195f2c65 7825 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7826 pci_disable_device(h->pdev);
edd16368
SC		 7827 return err;
7828 }
7829
f79cfec6 7830 err = pci_request_regions(h->pdev, HPSA);
edd16368 7831 if (err) {
55c06c71 7832 dev_err(&h->pdev->dev,
195f2c65 7833 "failed to obtain PCI resources\n");
943a7021
RE		 7834 pci_disable_device(h->pdev);
7835 return err;
edd16368 7836 }
4fa604e1
RE		 7837
7838 pci_set_master(h->pdev);
7839
6b3f4c52 7840 hpsa_interrupt_mode(h);
12d2cd47 7841 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7842 if (err)
195f2c65 7843 goto clean2; /* intmode+region, pci */
edd16368 7844 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7845 if (!h->vaddr) {
195f2c65 7846 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7847 err = -ENOMEM;
195f2c65 7848 goto clean2; /* intmode+region, pci */
204892e9 7849 }
fe5389c8 7850 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7851 if (err)
195f2c65 7852 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7853 err = hpsa_find_cfgtables(h);
7854 if (err)
195f2c65 7855 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7856 hpsa_find_board_params(h);
edd16368 7857
76c46e49 7858 if (!hpsa_CISS_signature_present(h)) {
edd16368 7859 err = -ENODEV;
195f2c65 7860 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7861 }
97a5e98c 7862 hpsa_set_driver_support_bits(h);
3d0eab67 7863 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7864 err = hpsa_enter_simple_mode(h);
7865 if (err)
195f2c65 7866 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7867 return 0;
7868
195f2c65
RE		 7869clean4: /* cfgtables, vaddr, intmode+region, pci */
7870 hpsa_free_cfgtables(h);
7871clean3: /* vaddr, intmode+region, pci */
7872 iounmap(h->vaddr);
105a3dbc 7873 h->vaddr = NULL;
195f2c65
RE		 7874clean2: /* intmode+region, pci */
7875 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7876 /*
7877 * call pci_disable_device before pci_release_regions per
7878 * Documentation/PCI/pci.txt
7879 */
195f2c65 7880 pci_disable_device(h->pdev);
943a7021 7881 pci_release_regions(h->pdev);
edd16368
SC		 7882 return err;
7883}
7884
6f039790 7885static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7886{
7887 int rc;
7888
7889#define HBA_INQUIRY_BYTE_COUNT 64
7890 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7891 if (!h->hba_inquiry_data)
7892 return;
7893 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7894 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7895 if (rc != 0) {
7896 kfree(h->hba_inquiry_data);
7897 h->hba_inquiry_data = NULL;
7898 }
7899}
7900
6b6c1cd7 7901static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7902{
1df8552a 7903 int rc, i;
3b747298 7904 void __iomem *vaddr;
4c2a8c40
SC		 7905
7906 if (!reset_devices)
7907 return 0;
7908
132aa220
TH		 7909 /* kdump kernel is loading, we don't know in which state is
7910 * the pci interface. The dev->enable_cnt is equal zero
7911 * so we call enable+disable, wait a while and switch it on.
7912 */
7913 rc = pci_enable_device(pdev);
7914 if (rc) {
7915 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7916 return -ENODEV;
7917 }
7918 pci_disable_device(pdev);
7919 msleep(260); /* a randomly chosen number */
7920 rc = pci_enable_device(pdev);
7921 if (rc) {
7922 dev_warn(&pdev->dev, "failed to enable device.\n");
7923 return -ENODEV;
7924 }
4fa604e1 7925
859c75ab 7926 pci_set_master(pdev);
4fa604e1 7927
3b747298
TH		 7928 vaddr = pci_ioremap_bar(pdev, 0);
7929 if (vaddr == NULL) {
7930 rc = -ENOMEM;
7931 goto out_disable;
7932 }
7933 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7934 iounmap(vaddr);
7935
1df8552a 7936 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7937 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7938
1df8552a
SC		 7939 /* -ENOTSUPP here means we cannot reset the controller
7940 * but it's already (and still) up and running in
18867659
SC		 7941 * "performant mode". Or, it might be 640x, which can't reset
7942 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7943 */
adf1b3a3 7944 if (rc)
132aa220 7945 goto out_disable;
4c2a8c40
SC		 7946
7947 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7948 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7949 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7950 if (hpsa_noop(pdev) == 0)
7951 break;
7952 else
7953 dev_warn(&pdev->dev, "no-op failed%s\n",
7954 (i < 11 ? "; re-trying" : ""));
7955 }
132aa220
TH		 7956
7957out_disable:
7958
7959 pci_disable_device(pdev);
7960 return rc;
4c2a8c40
SC		 7961}
7962
1fb7c98a
RE		 7963static void hpsa_free_cmd_pool(struct ctlr_info *h)
7964{
7965 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7966 h->cmd_pool_bits = NULL;
7967 if (h->cmd_pool) {
1fb7c98a
RE		 7968 pci_free_consistent(h->pdev,
7969 h->nr_cmds * sizeof(struct CommandList),
7970 h->cmd_pool,
7971 h->cmd_pool_dhandle);
105a3dbc
RE		 7972 h->cmd_pool = NULL;
7973 h->cmd_pool_dhandle = 0;
7974 }
7975 if (h->errinfo_pool) {
1fb7c98a
RE		 7976 pci_free_consistent(h->pdev,
7977 h->nr_cmds * sizeof(struct ErrorInfo),
7978 h->errinfo_pool,
7979 h->errinfo_pool_dhandle);
105a3dbc
RE		 7980 h->errinfo_pool = NULL;
7981 h->errinfo_pool_dhandle = 0;
7982 }
1fb7c98a
RE		 7983}
7984
d37ffbe4 7985static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7986{
7987 h->cmd_pool_bits = kzalloc(
7988 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7989 sizeof(unsigned long), GFP_KERNEL);
7990 h->cmd_pool = pci_alloc_consistent(h->pdev,
7991 h->nr_cmds * sizeof(*h->cmd_pool),
7992 &(h->cmd_pool_dhandle));
7993 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7994 h->nr_cmds * sizeof(*h->errinfo_pool),
7995 &(h->errinfo_pool_dhandle));
7996 if ((h->cmd_pool_bits == NULL)
7997 || (h->cmd_pool == NULL)
7998 || (h->errinfo_pool == NULL)) {
7999 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 8000 goto clean_up;
2e9d1b36 8001 }
360c73bd 8002 hpsa_preinitialize_commands(h);
2e9d1b36 8003 return 0;
2c143342
RE		 8004clean_up:
8005 hpsa_free_cmd_pool(h);
8006 return -ENOMEM;
2e9d1b36
SC		 8007}
8008
41b3cf08
SC		 8009static void hpsa_irq_affinity_hints(struct ctlr_info *h)
8010{
ec429952 8011 int i, cpu;
41b3cf08
SC		 8012
8013 cpu = cpumask_first(cpu_online_mask);
8014 for (i = 0; i < h->msix_vector; i++) {
ec429952 8015 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 8016 cpu = cpumask_next(cpu, cpu_online_mask);
8017 }
8018}
8019
ec501a18
RE		 8020/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
8021static void hpsa_free_irqs(struct ctlr_info *h)
8022{
8023 int i;
8024
8025 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
8026 /* Single reply queue, only one irq to free */
8027 i = h->intr_mode;
8028 irq_set_affinity_hint(h->intr[i], NULL);
8029 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8030 h->q[i] = 0;
ec501a18
RE		 8031 return;
8032 }
8033
8034 for (i = 0; i < h->msix_vector; i++) {
8035 irq_set_affinity_hint(h->intr[i], NULL);
8036 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8037 h->q[i] = 0;
ec501a18 8038 }
a4e17fc1
RE		 8039 for (; i < MAX_REPLY_QUEUES; i++)
8040 h->q[i] = 0;
ec501a18
RE		 8041}
8042
9ee61794
RE		 8043/* returns 0 on success; cleans up and returns -Enn on error */
8044static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 8045 irqreturn_t (*msixhandler)(int, void *),
8046 irqreturn_t (*intxhandler)(int, void *))
8047{
254f796b 8048 int rc, i;
0ae01a32 8049
254f796b
MG		 8050 /*
8051 * initialize h->q[x] = x so that interrupt handlers know which
8052 * queue to process.
8053 */
8054 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8055 h->q[i] = (u8) i;
8056
eee0f03a 8057 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 8058 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 8059 for (i = 0; i < h->msix_vector; i++) {
8b47004a 8060 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 8061 rc = request_irq(h->intr[i], msixhandler,
8b47004a 8062 0, h->intrname[i],
254f796b 8063 &h->q[i]);
a4e17fc1
RE		 8064 if (rc) {
8065 int j;
8066
8067 dev_err(&h->pdev->dev,
8068 "failed to get irq %d for %s\n",
8069 h->intr[i], h->devname);
8070 for (j = 0; j < i; j++) {
8071 free_irq(h->intr[j], &h->q[j]);
8072 h->q[j] = 0;
8073 }
8074 for (; j < MAX_REPLY_QUEUES; j++)
8075 h->q[j] = 0;
8076 return rc;
8077 }
8078 }
41b3cf08 8079 hpsa_irq_affinity_hints(h);
254f796b
MG		 8080 } else {
8081 /* Use single reply pool */
eee0f03a 8082 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 8083 if (h->msix_vector)
8084 sprintf(h->intrname[h->intr_mode],
8085 "%s-msix", h->devname);
8086 else
8087 sprintf(h->intrname[h->intr_mode],
8088 "%s-msi", h->devname);
254f796b 8089 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8090 msixhandler, 0,
8091 h->intrname[h->intr_mode],
254f796b
MG		 8092 &h->q[h->intr_mode]);
8093 } else {
8b47004a
RE		 8094 sprintf(h->intrname[h->intr_mode],
8095 "%s-intx", h->devname);
254f796b 8096 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8097 intxhandler, IRQF_SHARED,
8098 h->intrname[h->intr_mode],
254f796b
MG		 8099 &h->q[h->intr_mode]);
8100 }
105a3dbc 8101 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 8102 }
0ae01a32 8103 if (rc) {
195f2c65 8104 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 8105 h->intr[h->intr_mode], h->devname);
195f2c65 8106 hpsa_free_irqs(h);
0ae01a32
SC		 8107 return -ENODEV;
8108 }
8109 return 0;
8110}
8111
6f039790 8112static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8113{
39c53f55 8114 int rc;
bf43caf3 8115 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8116
8117 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8118 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8119 if (rc) {
64670ac8 8120 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8121 return rc;
64670ac8
SC		 8122 }
8123
8124 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8125 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8126 if (rc) {
64670ac8
SC		 8127 dev_warn(&h->pdev->dev, "Board failed to become ready "
8128 "after soft reset.\n");
39c53f55 8129 return rc;
64670ac8
SC		 8130 }
8131
8132 return 0;
8133}
8134
072b0518
SC		 8135static void hpsa_free_reply_queues(struct ctlr_info *h)
8136{
8137 int i;
8138
8139 for (i = 0; i < h->nreply_queues; i++) {
8140 if (!h->reply_queue[i].head)
8141 continue;
1fb7c98a
RE		 8142 pci_free_consistent(h->pdev,
8143 h->reply_queue_size,
8144 h->reply_queue[i].head,
8145 h->reply_queue[i].busaddr);
072b0518
SC		 8146 h->reply_queue[i].head = NULL;
8147 h->reply_queue[i].busaddr = 0;
8148 }
105a3dbc 8149 h->reply_queue_size = 0;
072b0518
SC		 8150}
8151
0097f0f4
SC		 8152static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8153{
105a3dbc
RE		 8154 hpsa_free_performant_mode(h); /* init_one 7 */
8155 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8156 hpsa_free_cmd_pool(h); /* init_one 5 */
8157 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8158 scsi_host_put(h->scsi_host); /* init_one 3 */
8159 h->scsi_host = NULL; /* init_one 3 */
8160 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8161 free_percpu(h->lockup_detected); /* init_one 2 */
8162 h->lockup_detected = NULL; /* init_one 2 */
8163 if (h->resubmit_wq) {
8164 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8165 h->resubmit_wq = NULL;
8166 }
8167 if (h->rescan_ctlr_wq) {
8168 destroy_workqueue(h->rescan_ctlr_wq);
8169 h->rescan_ctlr_wq = NULL;
8170 }
105a3dbc 8171 kfree(h); /* init_one 1 */
64670ac8
SC		 8172}
8173
a0c12413 8174/* Called when controller lockup detected. */
f2405db8 8175static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8176{
281a7fd0
WS		 8177 int i, refcount;
8178 struct CommandList *c;
25163bd5 8179 int failcount = 0;
a0c12413 8180
080ef1cc 8181 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8182 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8183 c = h->cmd_pool + i;
281a7fd0
WS		 8184 refcount = atomic_inc_return(&c->refcount);
8185 if (refcount > 1) {
25163bd5 8186 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8187 finish_cmd(c);
433b5f4d 8188 atomic_dec(&h->commands_outstanding);
25163bd5 8189 failcount++;
281a7fd0
WS		 8190 }
8191 cmd_free(h, c);
a0c12413 8192 }
25163bd5
WS		 8193 dev_warn(&h->pdev->dev,
8194 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8195}
8196
094963da
SC		 8197static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8198{
c8ed0010 8199 int cpu;
094963da 8200
c8ed0010 8201 for_each_online_cpu(cpu) {
094963da
SC		 8202 u32 *lockup_detected;
8203 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8204 *lockup_detected = value;
094963da
SC		 8205 }
8206 wmb(); /* be sure the per-cpu variables are out to memory */
8207}
8208
a0c12413
SC		 8209static void controller_lockup_detected(struct ctlr_info *h)
8210{
8211 unsigned long flags;
094963da 8212 u32 lockup_detected;
a0c12413 8213
a0c12413
SC		 8214 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8215 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8216 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8217 if (!lockup_detected) {
8218 /* no heartbeat, but controller gave us a zero. */
8219 dev_warn(&h->pdev->dev,
25163bd5
WS		 8220 "lockup detected after %d but scratchpad register is zero\n",
8221 h->heartbeat_sample_interval / HZ);
094963da
SC		 8222 lockup_detected = 0xffffffff;
8223 }
8224 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8225 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8226 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8227 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 8228 pci_disable_device(h->pdev);
f2405db8 8229 fail_all_outstanding_cmds(h);
a0c12413
SC		 8230}
8231
25163bd5 8232static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8233{
8234 u64 now;
8235 u32 heartbeat;
8236 unsigned long flags;
8237
a0c12413
SC		 8238 now = get_jiffies_64();
8239 /* If we've received an interrupt recently, we're ok. */
8240 if (time_after64(h->last_intr_timestamp +
e85c5974 8241 (h->heartbeat_sample_interval), now))
25163bd5 8242 return false;
a0c12413
SC		 8243
8244 /*
8245 * If we've already checked the heartbeat recently, we're ok.
8246 * This could happen if someone sends us a signal. We
8247 * otherwise don't care about signals in this thread.
8248 */
8249 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8250 (h->heartbeat_sample_interval), now))
25163bd5 8251 return false;
a0c12413
SC		 8252
8253 /* If heartbeat has not changed since we last looked, we're not ok. */
8254 spin_lock_irqsave(&h->lock, flags);
8255 heartbeat = readl(&h->cfgtable->HeartBeat);
8256 spin_unlock_irqrestore(&h->lock, flags);
8257 if (h->last_heartbeat == heartbeat) {
8258 controller_lockup_detected(h);
25163bd5 8259 return true;
a0c12413
SC		 8260 }
8261
8262 /* We're ok. */
8263 h->last_heartbeat = heartbeat;
8264 h->last_heartbeat_timestamp = now;
25163bd5 8265 return false;
a0c12413
SC		 8266}
8267
9846590e 8268static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 8269{
8270 int i;
8271 char *event_type;
8272
e4aa3e6a
SC		 8273 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8274 return;
8275
76438d08 8276 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8277 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8278 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8279 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8280 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8281
8282 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8283 event_type = "state change";
8284 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8285 event_type = "configuration change";
8286 /* Stop sending new RAID offload reqs via the IO accelerator */
8287 scsi_block_requests(h->scsi_host);
5323ed74 8288 for (i = 0; i < h->ndevices; i++) {
76438d08 8289 h->dev[i]->offload_enabled = 0;
5323ed74
DB		 8290 h->dev[i]->offload_to_be_enabled = 0;
8291 }
23100dd9 8292 hpsa_drain_accel_commands(h);
76438d08
SC		 8293 /* Set 'accelerator path config change' bit */
8294 dev_warn(&h->pdev->dev,
8295 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8296 h->events, event_type);
8297 writel(h->events, &(h->cfgtable->clear_event_notify));
8298 /* Set the "clear event notify field update" bit 6 */
8299 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8300 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8301 hpsa_wait_for_clear_event_notify_ack(h);
8302 scsi_unblock_requests(h->scsi_host);
8303 } else {
8304 /* Acknowledge controller notification events. */
8305 writel(h->events, &(h->cfgtable->clear_event_notify));
8306 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8307 hpsa_wait_for_clear_event_notify_ack(h);
8308#if 0
8309 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8310 hpsa_wait_for_mode_change_ack(h);
8311#endif
8312 }
9846590e 8313 return;
76438d08
SC		 8314}
8315
8316/* Check a register on the controller to see if there are configuration
8317 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8318 * we should rescan the controller for devices.
8319 * Also check flag for driver-initiated rescan.
76438d08 8320 */
9846590e 8321static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8322{
853633e8
DB		 8323 if (h->drv_req_rescan) {
8324 h->drv_req_rescan = 0;
8325 return 1;
8326 }
8327
76438d08 8328 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8329 return 0;
76438d08
SC		 8330
8331 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8332 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8333}
76438d08 8334
9846590e
SC		 8335/*
8336 * Check if any of the offline devices have become ready
8337 */
8338static int hpsa_offline_devices_ready(struct ctlr_info *h)
8339{
8340 unsigned long flags;
8341 struct offline_device_entry *d;
8342 struct list_head *this, *tmp;
8343
8344 spin_lock_irqsave(&h->offline_device_lock, flags);
8345 list_for_each_safe(this, tmp, &h->offline_device_list) {
8346 d = list_entry(this, struct offline_device_entry,
8347 offline_list);
8348 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8349 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8350 spin_lock_irqsave(&h->offline_device_lock, flags);
8351 list_del(&d->offline_list);
8352 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8353 return 1;
d1fea47c 8354 }
9846590e
SC		 8355 spin_lock_irqsave(&h->offline_device_lock, flags);
8356 }
8357 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8358 return 0;
76438d08
SC		 8359}
8360
34592254
ST		 8361static int hpsa_luns_changed(struct ctlr_info *h)
8362{
8363 int rc = 1; /* assume there are changes */
8364 struct ReportLUNdata *logdev = NULL;
8365
8366 /* if we can't find out if lun data has changed,
8367 * assume that it has.
8368 */
8369
8370 if (!h->lastlogicals)
8371 goto out;
8372
8373 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8374 if (!logdev) {
8375 dev_warn(&h->pdev->dev,
8376 "Out of memory, can't track lun changes.\n");
8377 goto out;
8378 }
8379 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8380 dev_warn(&h->pdev->dev,
8381 "report luns failed, can't track lun changes.\n");
8382 goto out;
8383 }
8384 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8385 dev_info(&h->pdev->dev,
8386 "Lun changes detected.\n");
8387 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8388 goto out;
8389 } else
8390 rc = 0; /* no changes detected. */
8391out:
8392 kfree(logdev);
8393 return rc;
8394}
8395
6636e7f4 8396static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8397{
8398 unsigned long flags;
8a98db73 8399 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8400 struct ctlr_info, rescan_ctlr_work);
8401
8402
8403 if (h->remove_in_progress)
8a98db73 8404 return;
9846590e
SC		 8405
8406 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8407 scsi_host_get(h->scsi_host);
9846590e
SC		 8408 hpsa_ack_ctlr_events(h);
8409 hpsa_scan_start(h->scsi_host);
8410 scsi_host_put(h->scsi_host);
34592254 8411 } else if (h->discovery_polling) {
c2adae44 8412 hpsa_disable_rld_caching(h);
34592254
ST		 8413 if (hpsa_luns_changed(h)) {
8414 struct Scsi_Host *sh = NULL;
8415
8416 dev_info(&h->pdev->dev,
8417 "driver discovery polling rescan.\n");
8418 sh = scsi_host_get(h->scsi_host);
8419 if (sh != NULL) {
8420 hpsa_scan_start(sh);
8421 scsi_host_put(sh);
8422 }
8423 }
9846590e 8424 }
8a98db73 8425 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8426 if (!h->remove_in_progress)
8427 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8428 h->heartbeat_sample_interval);
8429 spin_unlock_irqrestore(&h->lock, flags);
8430}
8431
8432static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8433{
8434 unsigned long flags;
8435 struct ctlr_info *h = container_of(to_delayed_work(work),
8436 struct ctlr_info, monitor_ctlr_work);
8437
8438 detect_controller_lockup(h);
8439 if (lockup_detected(h))
a0c12413 8440 return;
6636e7f4
DB		 8441
8442 spin_lock_irqsave(&h->lock, flags);
8443 if (!h->remove_in_progress)
8444 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8445 h->heartbeat_sample_interval);
8446 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8447}
8448
6636e7f4
DB		 8449static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8450 char *name)
8451{
8452 struct workqueue_struct *wq = NULL;
6636e7f4 8453
397ea9cb 8454 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8455 if (!wq)
8456 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8457
8458 return wq;
8459}
8460
6f039790 8461static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8462{
4c2a8c40 8463 int dac, rc;
edd16368 8464 struct ctlr_info *h;
64670ac8
SC		 8465 int try_soft_reset = 0;
8466 unsigned long flags;
6b6c1cd7 8467 u32 board_id;
edd16368
SC		 8468
8469 if (number_of_controllers == 0)
8470 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8471
6b6c1cd7
TH		 8472 rc = hpsa_lookup_board_id(pdev, &board_id);
8473 if (rc < 0) {
8474 dev_warn(&pdev->dev, "Board ID not found\n");
8475 return rc;
8476 }
8477
8478 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8479 if (rc) {
8480 if (rc != -ENOTSUPP)
8481 return rc;
8482 /* If the reset fails in a particular way (it has no way to do
8483 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8484 * a soft reset once we get the controller configured up to the
8485 * point that it can accept a command.
8486 */
8487 try_soft_reset = 1;
8488 rc = 0;
8489 }
8490
8491reinit_after_soft_reset:
edd16368 8492
303932fd
DB		 8493 /* Command structures must be aligned on a 32-byte boundary because
8494 * the 5 lower bits of the address are used by the hardware. and by
8495 * the driver. See comments in hpsa.h for more info.
8496 */
303932fd 8497 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8498 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8499 if (!h) {
8500 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8501 return -ENOMEM;
105a3dbc 8502 }
edd16368 8503
55c06c71 8504 h->pdev = pdev;
105a3dbc 8505
a9a3a273 8506 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8507 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8508 spin_lock_init(&h->lock);
9846590e 8509 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8510 spin_lock_init(&h->scan_lock);
34f0c627 8511 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8512 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8513
8514 /* Allocate and clear per-cpu variable lockup_detected */
8515 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8516 if (!h->lockup_detected) {
105a3dbc 8517 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8518 rc = -ENOMEM;
2efa5929 8519 goto clean1; /* aer/h */
2a5ac326 8520 }
094963da
SC		 8521 set_lockup_detected_for_all_cpus(h, 0);
8522
55c06c71 8523 rc = hpsa_pci_init(h);
105a3dbc 8524 if (rc)
2946e82b
RE		 8525 goto clean2; /* lu, aer/h */
8526
8527 /* relies on h-> settings made by hpsa_pci_init, including
8528 * interrupt_mode h->intr */
8529 rc = hpsa_scsi_host_alloc(h);
8530 if (rc)
8531 goto clean2_5; /* pci, lu, aer/h */
edd16368 8532
2946e82b 8533 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8534 h->ctlr = number_of_controllers;
8535 number_of_controllers++;
edd16368
SC		 8536
8537 /* configure PCI DMA stuff */
ecd9aad4
SC		 8538 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8539 if (rc == 0) {
edd16368 8540 dac = 1;
ecd9aad4
SC		 8541 } else {
8542 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8543 if (rc == 0) {
8544 dac = 0;
8545 } else {
8546 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8547 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8548 }
edd16368
SC		 8549 }
8550
8551 /* make sure the board interrupts are off */
8552 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8553
105a3dbc
RE		 8554 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8555 if (rc)
2946e82b 8556 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8557 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8558 if (rc)
2946e82b 8559 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8560 rc = hpsa_alloc_sg_chain_blocks(h);
8561 if (rc)
2946e82b 8562 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8563 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8564 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8565 init_waitqueue_head(&h->event_sync_wait_queue);
8566 mutex_init(&h->reset_mutex);
a08a8471 8567 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8568
8569 pci_set_drvdata(pdev, h);
9a41338e 8570 h->ndevices = 0;
2946e82b 8571
9a41338e 8572 spin_lock_init(&h->devlock);
105a3dbc
RE		 8573 rc = hpsa_put_ctlr_into_performant_mode(h);
8574 if (rc)
2946e82b
RE		 8575 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8576
2efa5929
RE		 8577 /* create the resubmit workqueue */
8578 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8579 if (!h->rescan_ctlr_wq) {
8580 rc = -ENOMEM;
8581 goto clean7;
8582 }
8583
8584 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8585 if (!h->resubmit_wq) {
8586 rc = -ENOMEM;
8587 goto clean7; /* aer/h */
8588 }
64670ac8 8589
105a3dbc
RE		 8590 /*
8591 * At this point, the controller is ready to take commands.
64670ac8
SC		 8592 * Now, if reset_devices and the hard reset didn't work, try
8593 * the soft reset and see if that works.
8594 */
8595 if (try_soft_reset) {
8596
8597 /* This is kind of gross. We may or may not get a completion
8598 * from the soft reset command, and if we do, then the value
8599 * from the fifo may or may not be valid. So, we wait 10 secs
8600 * after the reset throwing away any completions we get during
8601 * that time. Unregister the interrupt handler and register
8602 * fake ones to scoop up any residual completions.
8603 */
8604 spin_lock_irqsave(&h->lock, flags);
8605 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8606 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8607 hpsa_free_irqs(h);
9ee61794 8608 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8609 hpsa_intx_discard_completions);
8610 if (rc) {
9ee61794
RE		 8611 dev_warn(&h->pdev->dev,
8612 "Failed to request_irq after soft reset.\n");
d498757c 8613 /*
b2ef480c
RE		 8614 * cannot goto clean7 or free_irqs will be called
8615 * again. Instead, do its work
8616 */
8617 hpsa_free_performant_mode(h); /* clean7 */
8618 hpsa_free_sg_chain_blocks(h); /* clean6 */
8619 hpsa_free_cmd_pool(h); /* clean5 */
8620 /*
8621 * skip hpsa_free_irqs(h) clean4 since that
8622 * was just called before request_irqs failed
d498757c
RE		 8623 */
8624 goto clean3;
64670ac8
SC		 8625 }
8626
8627 rc = hpsa_kdump_soft_reset(h);
8628 if (rc)
8629 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8630 goto clean7;
64670ac8
SC		 8631
8632 dev_info(&h->pdev->dev, "Board READY.\n");
8633 dev_info(&h->pdev->dev,
8634 "Waiting for stale completions to drain.\n");
8635 h->access.set_intr_mask(h, HPSA_INTR_ON);
8636 msleep(10000);
8637 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8638
8639 rc = controller_reset_failed(h->cfgtable);
8640 if (rc)
8641 dev_info(&h->pdev->dev,
8642 "Soft reset appears to have failed.\n");
8643
8644 /* since the controller's reset, we have to go back and re-init
8645 * everything. Easiest to just forget what we've done and do it
8646 * all over again.
8647 */
8648 hpsa_undo_allocations_after_kdump_soft_reset(h);
8649 try_soft_reset = 0;
8650 if (rc)
b2ef480c 8651 /* don't goto clean, we already unallocated */
64670ac8
SC		 8652 return -ENODEV;
8653
8654 goto reinit_after_soft_reset;
8655 }
edd16368 8656
105a3dbc
RE		 8657 /* Enable Accelerated IO path at driver layer */
8658 h->acciopath_status = 1;
34592254
ST		 8659 /* Disable discovery polling.*/
8660 h->discovery_polling = 0;
da0697bd 8661
e863d68e 8662
edd16368
SC		 8663 /* Turn the interrupts on so we can service requests */
8664 h->access.set_intr_mask(h, HPSA_INTR_ON);
8665
339b2b14 8666 hpsa_hba_inquiry(h);
8a98db73 8667
34592254
ST		 8668 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8669 if (!h->lastlogicals)
8670 dev_info(&h->pdev->dev,
8671 "Can't track change to report lun data\n");
8672
cf477237
DB		 8673 /* hook into SCSI subsystem */
8674 rc = hpsa_scsi_add_host(h);
8675 if (rc)
8676 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8677
8a98db73
SC		 8678 /* Monitor the controller for firmware lockups */
8679 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8680 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8681 schedule_delayed_work(&h->monitor_ctlr_work,
8682 h->heartbeat_sample_interval);
6636e7f4
DB		 8683 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8684 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8685 h->heartbeat_sample_interval);
88bf6d62 8686 return 0;
edd16368 8687
2946e82b 8688clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8689 hpsa_free_performant_mode(h);
8690 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8691clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8692 hpsa_free_sg_chain_blocks(h);
2946e82b 8693clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8694 hpsa_free_cmd_pool(h);
2946e82b 8695clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8696 hpsa_free_irqs(h);
2946e82b
RE		 8697clean3: /* shost, pci, lu, aer/h */
8698 scsi_host_put(h->scsi_host);
8699 h->scsi_host = NULL;
8700clean2_5: /* pci, lu, aer/h */
195f2c65 8701 hpsa_free_pci_init(h);
2946e82b 8702clean2: /* lu, aer/h */
105a3dbc
RE		 8703 if (h->lockup_detected) {
8704 free_percpu(h->lockup_detected);
8705 h->lockup_detected = NULL;
8706 }
8707clean1: /* wq/aer/h */
8708 if (h->resubmit_wq) {
080ef1cc 8709 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8710 h->resubmit_wq = NULL;
8711 }
8712 if (h->rescan_ctlr_wq) {
6636e7f4 8713 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8714 h->rescan_ctlr_wq = NULL;
8715 }
edd16368 8716 kfree(h);
ecd9aad4 8717 return rc;
edd16368
SC		 8718}
8719
8720static void hpsa_flush_cache(struct ctlr_info *h)
8721{
8722 char *flush_buf;
8723 struct CommandList *c;
25163bd5 8724 int rc;
702890e3 8725
094963da 8726 if (unlikely(lockup_detected(h)))
702890e3 8727 return;
edd16368
SC		 8728 flush_buf = kzalloc(4, GFP_KERNEL);
8729 if (!flush_buf)
8730 return;
8731
45fcb86e 8732 c = cmd_alloc(h);
bf43caf3 8733
a2dac136
SC		 8734 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8735 RAID_CTLR_LUNID, TYPE_CMD)) {
8736 goto out;
8737 }
25163bd5 8738 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8739 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 8740 if (rc)
8741 goto out;
edd16368 8742 if (c->err_info->CommandStatus != 0)
a2dac136 8743out:
edd16368
SC		 8744 dev_warn(&h->pdev->dev,
8745 "error flushing cache on controller\n");
45fcb86e 8746 cmd_free(h, c);
edd16368
SC		 8747 kfree(flush_buf);
8748}
8749
c2adae44
ST		 8750/* Make controller gather fresh report lun data each time we
8751 * send down a report luns request
8752 */
8753static void hpsa_disable_rld_caching(struct ctlr_info *h)
8754{
8755 u32 *options;
8756 struct CommandList *c;
8757 int rc;
8758
8759 /* Don't bother trying to set diag options if locked up */
8760 if (unlikely(h->lockup_detected))
8761 return;
8762
8763 options = kzalloc(sizeof(*options), GFP_KERNEL);
8764 if (!options) {
8765 dev_err(&h->pdev->dev,
8766 "Error: failed to disable rld caching, during alloc.\n");
8767 return;
8768 }
8769
8770 c = cmd_alloc(h);
8771
8772 /* first, get the current diag options settings */
8773 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8774 RAID_CTLR_LUNID, TYPE_CMD))
8775 goto errout;
8776
8777 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8778 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8779 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8780 goto errout;
8781
8782 /* Now, set the bit for disabling the RLD caching */
8783 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8784
8785 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8786 RAID_CTLR_LUNID, TYPE_CMD))
8787 goto errout;
8788
8789 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8790 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8791 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8792 goto errout;
8793
8794 /* Now verify that it got set: */
8795 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8796 RAID_CTLR_LUNID, TYPE_CMD))
8797 goto errout;
8798
8799 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8800 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 8801 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8802 goto errout;
8803
d8a080c3 8804 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 8805 goto out;
8806
8807errout:
8808 dev_err(&h->pdev->dev,
8809 "Error: failed to disable report lun data caching.\n");
8810out:
8811 cmd_free(h, c);
8812 kfree(options);
8813}
8814
edd16368
SC		 8815static void hpsa_shutdown(struct pci_dev *pdev)
8816{
8817 struct ctlr_info *h;
8818
8819 h = pci_get_drvdata(pdev);
8820 /* Turn board interrupts off and send the flush cache command
8821 * sendcmd will turn off interrupt, and send the flush...
8822 * To write all data in the battery backed cache to disks
8823 */
8824 hpsa_flush_cache(h);
8825 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8826 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8827 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8828}
8829
6f039790 8830static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8831{
8832 int i;
8833
105a3dbc 8834 for (i = 0; i < h->ndevices; i++) {
55e14e76 8835 kfree(h->dev[i]);
105a3dbc
RE		 8836 h->dev[i] = NULL;
8837 }
55e14e76
SC		 8838}
8839
6f039790 8840static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8841{
8842 struct ctlr_info *h;
8a98db73 8843 unsigned long flags;
edd16368
SC		 8844
8845 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8846 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8847 return;
8848 }
8849 h = pci_get_drvdata(pdev);
8a98db73
SC		 8850
8851 /* Get rid of any controller monitoring work items */
8852 spin_lock_irqsave(&h->lock, flags);
8853 h->remove_in_progress = 1;
8a98db73 8854 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8855 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8856 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8857 destroy_workqueue(h->rescan_ctlr_wq);
8858 destroy_workqueue(h->resubmit_wq);
cc64c817 8859
2d041306
DB		 8860 /*
8861 * Call before disabling interrupts.
8862 * scsi_remove_host can trigger I/O operations especially
8863 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8864 * operations which cannot complete and will hang the system.
8865 */
8866 if (h->scsi_host)
8867 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8868 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8869 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8870 hpsa_shutdown(pdev);
cc64c817 8871
105a3dbc
RE		 8872 hpsa_free_device_info(h); /* scan */
8873
2946e82b
RE		 8874 kfree(h->hba_inquiry_data); /* init_one 10 */
8875 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8876 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8877 hpsa_free_performant_mode(h); /* init_one 7 */
8878 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8879 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8880 kfree(h->lastlogicals);
105a3dbc
RE		 8881
8882 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8883
2946e82b
RE		 8884 scsi_host_put(h->scsi_host); /* init_one 3 */
8885 h->scsi_host = NULL; /* init_one 3 */
8886
195f2c65 8887 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8888 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8889
105a3dbc
RE		 8890 free_percpu(h->lockup_detected); /* init_one 2 */
8891 h->lockup_detected = NULL; /* init_one 2 */
8892 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9
KB		 8893
8894 hpsa_delete_sas_host(h);
8895
105a3dbc 8896 kfree(h); /* init_one 1 */
edd16368
SC		 8897}
8898
8899static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8900 __attribute__((unused)) pm_message_t state)
8901{
8902 return -ENOSYS;
8903}
8904
8905static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8906{
8907 return -ENOSYS;
8908}
8909
8910static struct pci_driver hpsa_pci_driver = {
f79cfec6 8911 .name = HPSA,
edd16368 8912 .probe = hpsa_init_one,
6f039790 8913 .remove = hpsa_remove_one,
edd16368
SC		 8914 .id_table = hpsa_pci_device_id, /* id_table */
8915 .shutdown = hpsa_shutdown,
8916 .suspend = hpsa_suspend,
8917 .resume = hpsa_resume,
8918};
8919
303932fd
DB		 8920/* Fill in bucket_map[], given nsgs (the max number of
8921 * scatter gather elements supported) and bucket[],
8922 * which is an array of 8 integers. The bucket[] array
8923 * contains 8 different DMA transfer sizes (in 16
8924 * byte increments) which the controller uses to fetch
8925 * commands. This function fills in bucket_map[], which
8926 * maps a given number of scatter gather elements to one of
8927 * the 8 DMA transfer sizes. The point of it is to allow the
8928 * controller to only do as much DMA as needed to fetch the
8929 * command, with the DMA transfer size encoded in the lower
8930 * bits of the command address.
8931 */
8932static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8933 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8934{
8935 int i, j, b, size;
8936
303932fd
DB		 8937 /* Note, bucket_map must have nsgs+1 entries. */
8938 for (i = 0; i <= nsgs; i++) {
8939 /* Compute size of a command with i SG entries */
e1f7de0c 8940 size = i + min_blocks;
303932fd
DB		 8941 b = num_buckets; /* Assume the biggest bucket */
8942 /* Find the bucket that is just big enough */
e1f7de0c 8943 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8944 if (bucket[j] >= size) {
8945 b = j;
8946 break;
8947 }
8948 }
8949 /* for a command with i SG entries, use bucket b. */
8950 bucket_map[i] = b;
8951 }
8952}
8953
105a3dbc
RE		 8954/*
8955 * return -ENODEV on err, 0 on success (or no action)
8956 * allocates numerous items that must be freed later
8957 */
c706a795 8958static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8959{
6c311b57
SC		 8960 int i;
8961 unsigned long register_value;
e1f7de0c
MG		 8962 unsigned long transMethod = CFGTBL_Trans_Performant |
8963 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8964 CFGTBL_Trans_enable_directed_msix |
8965 (trans_support & (CFGTBL_Trans_io_accel1 |
8966 CFGTBL_Trans_io_accel2));
e1f7de0c 8967 struct access_method access = SA5_performant_access;
def342bd
SC		 8968
8969 /* This is a bit complicated. There are 8 registers on
8970 * the controller which we write to to tell it 8 different
8971 * sizes of commands which there may be. It's a way of
8972 * reducing the DMA done to fetch each command. Encoded into
8973 * each command's tag are 3 bits which communicate to the controller
8974 * which of the eight sizes that command fits within. The size of
8975 * each command depends on how many scatter gather entries there are.
8976 * Each SG entry requires 16 bytes. The eight registers are programmed
8977 * with the number of 16-byte blocks a command of that size requires.
8978 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8979 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8980 * blocks. Note, this only extends to the SG entries contained
8981 * within the command block, and does not extend to chained blocks
8982 * of SG elements. bft[] contains the eight values we write to
8983 * the registers. They are not evenly distributed, but have more
8984 * sizes for small commands, and fewer sizes for larger commands.
8985 */
d66ae08b 8986 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8987#define MIN_IOACCEL2_BFT_ENTRY 5
8988#define HPSA_IOACCEL2_HEADER_SZ 4
8989 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8990 13, 14, 15, 16, 17, 18, 19,
8991 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8992 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8993 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8994 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8995 16 * MIN_IOACCEL2_BFT_ENTRY);
8996 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8997 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8998 /* 5 = 1 s/g entry or 4k
8999 * 6 = 2 s/g entry or 8k
9000 * 8 = 4 s/g entry or 16k
9001 * 10 = 6 s/g entry or 24k
9002 */
303932fd 9003
b3a52e79
SC		 9004 /* If the controller supports either ioaccel method then
9005 * we can also use the RAID stack submit path that does not
9006 * perform the superfluous readl() after each command submission.
9007 */
9008 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
9009 access = SA5_performant_access_no_read;
9010
303932fd 9011 /* Controller spec: zero out this buffer. */
072b0518
SC		 9012 for (i = 0; i < h->nreply_queues; i++)
9013 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 9014
d66ae08b
SC		 9015 bft[7] = SG_ENTRIES_IN_CMD + 4;
9016 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 9017 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 9018 for (i = 0; i < 8; i++)
9019 writel(bft[i], &h->transtable->BlockFetch[i]);
9020
9021 /* size of controller ring buffer */
9022 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 9023 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 9024 writel(0, &h->transtable->RepQCtrAddrLow32);
9025 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9026
9027 for (i = 0; i < h->nreply_queues; i++) {
9028 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9029 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9030 &h->transtable->RepQAddr[i].lower);
9031 }
9032
b9af4937 9033 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9034 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9035 /*
9036 * enable outbound interrupt coalescing in accelerator mode;
9037 */
9038 if (trans_support & CFGTBL_Trans_io_accel1) {
9039 access = SA5_ioaccel_mode1_access;
9040 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9041 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 9042 } else {
9043 if (trans_support & CFGTBL_Trans_io_accel2) {
9044 access = SA5_ioaccel_mode2_access;
9045 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9046 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
9047 }
e1f7de0c 9048 }
303932fd 9049 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9050 if (hpsa_wait_for_mode_change_ack(h)) {
9051 dev_err(&h->pdev->dev,
9052 "performant mode problem - doorbell timeout\n");
9053 return -ENODEV;
9054 }
303932fd
DB		 9055 register_value = readl(&(h->cfgtable->TransportActive));
9056 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9057 dev_err(&h->pdev->dev,
9058 "performant mode problem - transport not active\n");
c706a795 9059 return -ENODEV;
303932fd 9060 }
960a30e7 9061 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9062 h->access = access;
9063 h->transMethod = transMethod;
9064
b9af4937
SC		 9065 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9066 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9067 return 0;
e1f7de0c 9068
b9af4937
SC		 9069 if (trans_support & CFGTBL_Trans_io_accel1) {
9070 /* Set up I/O accelerator mode */
9071 for (i = 0; i < h->nreply_queues; i++) {
9072 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9073 h->reply_queue[i].current_entry =
9074 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9075 }
9076 bft[7] = h->ioaccel_maxsg + 8;
9077 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9078 h->ioaccel1_blockFetchTable);
e1f7de0c 9079
b9af4937 9080 /* initialize all reply queue entries to unused */
072b0518
SC		 9081 for (i = 0; i < h->nreply_queues; i++)
9082 memset(h->reply_queue[i].head,
9083 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9084 h->reply_queue_size);
e1f7de0c 9085
b9af4937
SC		 9086 /* set all the constant fields in the accelerator command
9087 * frames once at init time to save CPU cycles later.
9088 */
9089 for (i = 0; i < h->nr_cmds; i++) {
9090 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9091
9092 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9093 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9094 (i * sizeof(struct ErrorInfo)));
9095 cp->err_info_len = sizeof(struct ErrorInfo);
9096 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9097 cp->host_context_flags =
9098 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9099 cp->timeout_sec = 0;
9100 cp->ReplyQueue = 0;
50a0decf 9101 cp->tag =
f2405db8 9102 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9103 cp->host_addr =
9104 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9105 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9106 }
9107 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9108 u64 cfg_offset, cfg_base_addr_index;
9109 u32 bft2_offset, cfg_base_addr;
9110 int rc;
9111
9112 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9113 &cfg_base_addr_index, &cfg_offset);
9114 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9115 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9116 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9117 4, h->ioaccel2_blockFetchTable);
9118 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9119 BUILD_BUG_ON(offsetof(struct CfgTable,
9120 io_accel_request_size_offset) != 0xb8);
9121 h->ioaccel2_bft2_regs =
9122 remap_pci_mem(pci_resource_start(h->pdev,
9123 cfg_base_addr_index) +
9124 cfg_offset + bft2_offset,
9125 ARRAY_SIZE(bft2) *
9126 sizeof(*h->ioaccel2_bft2_regs));
9127 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9128 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9129 }
b9af4937 9130 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9131 if (hpsa_wait_for_mode_change_ack(h)) {
9132 dev_err(&h->pdev->dev,
9133 "performant mode problem - enabling ioaccel mode\n");
9134 return -ENODEV;
9135 }
9136 return 0;
e1f7de0c
MG		 9137}
9138
1fb7c98a
RE		 9139/* Free ioaccel1 mode command blocks and block fetch table */
9140static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9141{
105a3dbc 9142 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9143 pci_free_consistent(h->pdev,
9144 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9145 h->ioaccel_cmd_pool,
9146 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9147 h->ioaccel_cmd_pool = NULL;
9148 h->ioaccel_cmd_pool_dhandle = 0;
9149 }
1fb7c98a 9150 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9151 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9152}
9153
d37ffbe4
RE		 9154/* Allocate ioaccel1 mode command blocks and block fetch table */
9155static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9156{
283b4a9b
SC		 9157 h->ioaccel_maxsg =
9158 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9159 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9160 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9161
e1f7de0c
MG		 9162 /* Command structures must be aligned on a 128-byte boundary
9163 * because the 7 lower bits of the address are used by the
9164 * hardware.
9165 */
e1f7de0c
MG		 9166 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9167 IOACCEL1_COMMANDLIST_ALIGNMENT);
9168 h->ioaccel_cmd_pool =
9169 pci_alloc_consistent(h->pdev,
9170 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9171 &(h->ioaccel_cmd_pool_dhandle));
9172
9173 h->ioaccel1_blockFetchTable =
283b4a9b 9174 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9175 sizeof(u32)), GFP_KERNEL);
9176
9177 if ((h->ioaccel_cmd_pool == NULL) ||
9178 (h->ioaccel1_blockFetchTable == NULL))
9179 goto clean_up;
9180
9181 memset(h->ioaccel_cmd_pool, 0,
9182 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9183 return 0;
9184
9185clean_up:
1fb7c98a 9186 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9187 return -ENOMEM;
6c311b57
SC		 9188}
9189
1fb7c98a
RE		 9190/* Free ioaccel2 mode command blocks and block fetch table */
9191static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9192{
d9a729f3
WS		 9193 hpsa_free_ioaccel2_sg_chain_blocks(h);
9194
105a3dbc 9195 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9196 pci_free_consistent(h->pdev,
9197 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9198 h->ioaccel2_cmd_pool,
9199 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9200 h->ioaccel2_cmd_pool = NULL;
9201 h->ioaccel2_cmd_pool_dhandle = 0;
9202 }
1fb7c98a 9203 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9204 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9205}
9206
d37ffbe4
RE		 9207/* Allocate ioaccel2 mode command blocks and block fetch table */
9208static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9209{
d9a729f3
WS		 9210 int rc;
9211
aca9012a
SC		 9212 /* Allocate ioaccel2 mode command blocks and block fetch table */
9213
9214 h->ioaccel_maxsg =
9215 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9216 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9217 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9218
aca9012a
SC		 9219 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9220 IOACCEL2_COMMANDLIST_ALIGNMENT);
9221 h->ioaccel2_cmd_pool =
9222 pci_alloc_consistent(h->pdev,
9223 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9224 &(h->ioaccel2_cmd_pool_dhandle));
9225
9226 h->ioaccel2_blockFetchTable =
9227 kmalloc(((h->ioaccel_maxsg + 1) *
9228 sizeof(u32)), GFP_KERNEL);
9229
9230 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9231 (h->ioaccel2_blockFetchTable == NULL)) {
9232 rc = -ENOMEM;
9233 goto clean_up;
9234 }
9235
9236 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9237 if (rc)
aca9012a
SC		 9238 goto clean_up;
9239
9240 memset(h->ioaccel2_cmd_pool, 0,
9241 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9242 return 0;
9243
9244clean_up:
1fb7c98a 9245 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9246 return rc;
aca9012a
SC		 9247}
9248
105a3dbc
RE		 9249/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9250static void hpsa_free_performant_mode(struct ctlr_info *h)
9251{
9252 kfree(h->blockFetchTable);
9253 h->blockFetchTable = NULL;
9254 hpsa_free_reply_queues(h);
9255 hpsa_free_ioaccel1_cmd_and_bft(h);
9256 hpsa_free_ioaccel2_cmd_and_bft(h);
9257}
9258
9259/* return -ENODEV on error, 0 on success (or no action)
9260 * allocates numerous items that must be freed later
9261 */
9262static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9263{
9264 u32 trans_support;
e1f7de0c
MG		 9265 unsigned long transMethod = CFGTBL_Trans_Performant |
9266 CFGTBL_Trans_use_short_tags;
105a3dbc 9267 int i, rc;
6c311b57 9268
02ec19c8 9269 if (hpsa_simple_mode)
105a3dbc 9270 return 0;
02ec19c8 9271
67c99a72 9272 trans_support = readl(&(h->cfgtable->TransportSupport));
9273 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9274 return 0;
67c99a72 9275
e1f7de0c
MG		 9276 /* Check for I/O accelerator mode support */
9277 if (trans_support & CFGTBL_Trans_io_accel1) {
9278 transMethod |= CFGTBL_Trans_io_accel1 |
9279 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9280 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9281 if (rc)
9282 return rc;
9283 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9284 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9285 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9286 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9287 if (rc)
9288 return rc;
e1f7de0c
MG		 9289 }
9290
eee0f03a 9291 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 9292 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9293 /* Performant mode ring buffer and supporting data structures */
072b0518 9294 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9295
254f796b 9296 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 9297 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
9298 h->reply_queue_size,
9299 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 9300 if (!h->reply_queue[i].head) {
9301 rc = -ENOMEM;
9302 goto clean1; /* rq, ioaccel */
9303 }
254f796b
MG		 9304 h->reply_queue[i].size = h->max_commands;
9305 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9306 h->reply_queue[i].current_entry = 0;
9307 }
9308
6c311b57 9309 /* Need a block fetch table for performant mode */
d66ae08b 9310 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9311 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9312 if (!h->blockFetchTable) {
9313 rc = -ENOMEM;
9314 goto clean1; /* rq, ioaccel */
9315 }
6c311b57 9316
105a3dbc
RE		 9317 rc = hpsa_enter_performant_mode(h, trans_support);
9318 if (rc)
9319 goto clean2; /* bft, rq, ioaccel */
9320 return 0;
303932fd 9321
105a3dbc 9322clean2: /* bft, rq, ioaccel */
303932fd 9323 kfree(h->blockFetchTable);
105a3dbc
RE		 9324 h->blockFetchTable = NULL;
9325clean1: /* rq, ioaccel */
9326 hpsa_free_reply_queues(h);
9327 hpsa_free_ioaccel1_cmd_and_bft(h);
9328 hpsa_free_ioaccel2_cmd_and_bft(h);
9329 return rc;
303932fd
DB		 9330}
9331
23100dd9 9332static int is_accelerated_cmd(struct CommandList *c)
76438d08 9333{
23100dd9
SC		 9334 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9335}
9336
9337static void hpsa_drain_accel_commands(struct ctlr_info *h)
9338{
9339 struct CommandList *c = NULL;
f2405db8 9340 int i, accel_cmds_out;
281a7fd0 9341 int refcount;
76438d08 9342
f2405db8 9343 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9344 accel_cmds_out = 0;
f2405db8 9345 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9346 c = h->cmd_pool + i;
281a7fd0
WS		 9347 refcount = atomic_inc_return(&c->refcount);
9348 if (refcount > 1) /* Command is allocated */
9349 accel_cmds_out += is_accelerated_cmd(c);
9350 cmd_free(h, c);
f2405db8 9351 }
23100dd9 9352 if (accel_cmds_out <= 0)
281a7fd0 9353 break;
76438d08
SC		 9354 msleep(100);
9355 } while (1);
9356}
9357
d04e62b9
KB		 9358static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9359 struct hpsa_sas_port *hpsa_sas_port)
9360{
9361 struct hpsa_sas_phy *hpsa_sas_phy;
9362 struct sas_phy *phy;
9363
9364 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9365 if (!hpsa_sas_phy)
9366 return NULL;
9367
9368 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9369 hpsa_sas_port->next_phy_index);
9370 if (!phy) {
9371 kfree(hpsa_sas_phy);
9372 return NULL;
9373 }
9374
9375 hpsa_sas_port->next_phy_index++;
9376 hpsa_sas_phy->phy = phy;
9377 hpsa_sas_phy->parent_port = hpsa_sas_port;
9378
9379 return hpsa_sas_phy;
9380}
9381
9382static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9383{
9384 struct sas_phy *phy = hpsa_sas_phy->phy;
9385
9386 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
9387 sas_phy_free(phy);
9388 if (hpsa_sas_phy->added_to_port)
9389 list_del(&hpsa_sas_phy->phy_list_entry);
9390 kfree(hpsa_sas_phy);
9391}
9392
9393static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9394{
9395 int rc;
9396 struct hpsa_sas_port *hpsa_sas_port;
9397 struct sas_phy *phy;
9398 struct sas_identify *identify;
9399
9400 hpsa_sas_port = hpsa_sas_phy->parent_port;
9401 phy = hpsa_sas_phy->phy;
9402
9403 identify = &phy->identify;
9404 memset(identify, 0, sizeof(*identify));
9405 identify->sas_address = hpsa_sas_port->sas_address;
9406 identify->device_type = SAS_END_DEVICE;
9407 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9408 identify->target_port_protocols = SAS_PROTOCOL_STP;
9409 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9410 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9411 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9412 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9413 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9414
9415 rc = sas_phy_add(hpsa_sas_phy->phy);
9416 if (rc)
9417 return rc;
9418
9419 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9420 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9421 &hpsa_sas_port->phy_list_head);
9422 hpsa_sas_phy->added_to_port = true;
9423
9424 return 0;
9425}
9426
9427static int
9428 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9429 struct sas_rphy *rphy)
9430{
9431 struct sas_identify *identify;
9432
9433 identify = &rphy->identify;
9434 identify->sas_address = hpsa_sas_port->sas_address;
9435 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9436 identify->target_port_protocols = SAS_PROTOCOL_STP;
9437
9438 return sas_rphy_add(rphy);
9439}
9440
9441static struct hpsa_sas_port
9442 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9443 u64 sas_address)
9444{
9445 int rc;
9446 struct hpsa_sas_port *hpsa_sas_port;
9447 struct sas_port *port;
9448
9449 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9450 if (!hpsa_sas_port)
9451 return NULL;
9452
9453 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9454 hpsa_sas_port->parent_node = hpsa_sas_node;
9455
9456 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9457 if (!port)
9458 goto free_hpsa_port;
9459
9460 rc = sas_port_add(port);
9461 if (rc)
9462 goto free_sas_port;
9463
9464 hpsa_sas_port->port = port;
9465 hpsa_sas_port->sas_address = sas_address;
9466 list_add_tail(&hpsa_sas_port->port_list_entry,
9467 &hpsa_sas_node->port_list_head);
9468
9469 return hpsa_sas_port;
9470
9471free_sas_port:
9472 sas_port_free(port);
9473free_hpsa_port:
9474 kfree(hpsa_sas_port);
9475
9476 return NULL;
9477}
9478
9479static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9480{
9481 struct hpsa_sas_phy *hpsa_sas_phy;
9482 struct hpsa_sas_phy *next;
9483
9484 list_for_each_entry_safe(hpsa_sas_phy, next,
9485 &hpsa_sas_port->phy_list_head, phy_list_entry)
9486 hpsa_free_sas_phy(hpsa_sas_phy);
9487
9488 sas_port_delete(hpsa_sas_port->port);
9489 list_del(&hpsa_sas_port->port_list_entry);
9490 kfree(hpsa_sas_port);
9491}
9492
9493static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9494{
9495 struct hpsa_sas_node *hpsa_sas_node;
9496
9497 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9498 if (hpsa_sas_node) {
9499 hpsa_sas_node->parent_dev = parent_dev;
9500 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9501 }
9502
9503 return hpsa_sas_node;
9504}
9505
9506static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9507{
9508 struct hpsa_sas_port *hpsa_sas_port;
9509 struct hpsa_sas_port *next;
9510
9511 if (!hpsa_sas_node)
9512 return;
9513
9514 list_for_each_entry_safe(hpsa_sas_port, next,
9515 &hpsa_sas_node->port_list_head, port_list_entry)
9516 hpsa_free_sas_port(hpsa_sas_port);
9517
9518 kfree(hpsa_sas_node);
9519}
9520
9521static struct hpsa_scsi_dev_t
9522 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9523 struct sas_rphy *rphy)
9524{
9525 int i;
9526 struct hpsa_scsi_dev_t *device;
9527
9528 for (i = 0; i < h->ndevices; i++) {
9529 device = h->dev[i];
9530 if (!device->sas_port)
9531 continue;
9532 if (device->sas_port->rphy == rphy)
9533 return device;
9534 }
9535
9536 return NULL;
9537}
9538
9539static int hpsa_add_sas_host(struct ctlr_info *h)
9540{
9541 int rc;
9542 struct device *parent_dev;
9543 struct hpsa_sas_node *hpsa_sas_node;
9544 struct hpsa_sas_port *hpsa_sas_port;
9545 struct hpsa_sas_phy *hpsa_sas_phy;
9546
9547 parent_dev = &h->scsi_host->shost_gendev;
9548
9549 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9550 if (!hpsa_sas_node)
9551 return -ENOMEM;
9552
9553 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9554 if (!hpsa_sas_port) {
9555 rc = -ENODEV;
9556 goto free_sas_node;
9557 }
9558
9559 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9560 if (!hpsa_sas_phy) {
9561 rc = -ENODEV;
9562 goto free_sas_port;
9563 }
9564
9565 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9566 if (rc)
9567 goto free_sas_phy;
9568
9569 h->sas_host = hpsa_sas_node;
9570
9571 return 0;
9572
9573free_sas_phy:
9574 hpsa_free_sas_phy(hpsa_sas_phy);
9575free_sas_port:
9576 hpsa_free_sas_port(hpsa_sas_port);
9577free_sas_node:
9578 hpsa_free_sas_node(hpsa_sas_node);
9579
9580 return rc;
9581}
9582
9583static void hpsa_delete_sas_host(struct ctlr_info *h)
9584{
9585 hpsa_free_sas_node(h->sas_host);
9586}
9587
9588static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9589 struct hpsa_scsi_dev_t *device)
9590{
9591 int rc;
9592 struct hpsa_sas_port *hpsa_sas_port;
9593 struct sas_rphy *rphy;
9594
9595 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9596 if (!hpsa_sas_port)
9597 return -ENOMEM;
9598
9599 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9600 if (!rphy) {
9601 rc = -ENODEV;
9602 goto free_sas_port;
9603 }
9604
9605 hpsa_sas_port->rphy = rphy;
9606 device->sas_port = hpsa_sas_port;
9607
9608 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9609 if (rc)
9610 goto free_sas_port;
9611
9612 return 0;
9613
9614free_sas_port:
9615 hpsa_free_sas_port(hpsa_sas_port);
9616 device->sas_port = NULL;
9617
9618 return rc;
9619}
9620
9621static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9622{
9623 if (device->sas_port) {
9624 hpsa_free_sas_port(device->sas_port);
9625 device->sas_port = NULL;
9626 }
9627}
9628
9629static int
9630hpsa_sas_get_linkerrors(struct sas_phy *phy)
9631{
9632 return 0;
9633}
9634
9635static int
9636hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9637{
aa105695 9638 *identifier = 0;
d04e62b9
KB		 9639 return 0;
9640}
9641
9642static int
9643hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9644{
9645 return -ENXIO;
9646}
9647
9648static int
9649hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9650{
9651 return 0;
9652}
9653
9654static int
9655hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9656{
9657 return 0;
9658}
9659
9660static int
9661hpsa_sas_phy_setup(struct sas_phy *phy)
9662{
9663 return 0;
9664}
9665
9666static void
9667hpsa_sas_phy_release(struct sas_phy *phy)
9668{
9669}
9670
9671static int
9672hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9673{
9674 return -EINVAL;
9675}
9676
9677/* SMP = Serial Management Protocol */
9678static int
9679hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
9680struct request *req)
9681{
9682 return -EINVAL;
9683}
9684
9685static struct sas_function_template hpsa_sas_transport_functions = {
9686 .get_linkerrors = hpsa_sas_get_linkerrors,
9687 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9688 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9689 .phy_reset = hpsa_sas_phy_reset,
9690 .phy_enable = hpsa_sas_phy_enable,
9691 .phy_setup = hpsa_sas_phy_setup,
9692 .phy_release = hpsa_sas_phy_release,
9693 .set_phy_speed = hpsa_sas_phy_speed,
9694 .smp_handler = hpsa_sas_smp_handler,
9695};
9696
edd16368
SC		 9697/*
9698 * This is it. Register the PCI driver information for the cards we control
9699 * the OS will call our registered routines when it finds one of our cards.
9700 */
9701static int __init hpsa_init(void)
9702{
d04e62b9
KB		 9703 int rc;
9704
9705 hpsa_sas_transport_template =
9706 sas_attach_transport(&hpsa_sas_transport_functions);
9707 if (!hpsa_sas_transport_template)
9708 return -ENODEV;
9709
9710 rc = pci_register_driver(&hpsa_pci_driver);
9711
9712 if (rc)
9713 sas_release_transport(hpsa_sas_transport_template);
9714
9715 return rc;
edd16368
SC		 9716}
9717
9718static void __exit hpsa_cleanup(void)
9719{
9720 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9721 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9722}
9723
e1f7de0c
MG		 9724static void __attribute__((unused)) verify_offsets(void)
9725{
dd0e19f3
ST		 9726#define VERIFY_OFFSET(member, offset) \
9727 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9728
9729 VERIFY_OFFSET(structure_size, 0);
9730 VERIFY_OFFSET(volume_blk_size, 4);
9731 VERIFY_OFFSET(volume_blk_cnt, 8);
9732 VERIFY_OFFSET(phys_blk_shift, 16);
9733 VERIFY_OFFSET(parity_rotation_shift, 17);
9734 VERIFY_OFFSET(strip_size, 18);
9735 VERIFY_OFFSET(disk_starting_blk, 20);
9736 VERIFY_OFFSET(disk_blk_cnt, 28);
9737 VERIFY_OFFSET(data_disks_per_row, 36);
9738 VERIFY_OFFSET(metadata_disks_per_row, 38);
9739 VERIFY_OFFSET(row_cnt, 40);
9740 VERIFY_OFFSET(layout_map_count, 42);
9741 VERIFY_OFFSET(flags, 44);
9742 VERIFY_OFFSET(dekindex, 46);
9743 /* VERIFY_OFFSET(reserved, 48 */
9744 VERIFY_OFFSET(data, 64);
9745
9746#undef VERIFY_OFFSET
9747
b66cc250
MM		 9748#define VERIFY_OFFSET(member, offset) \
9749 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9750
9751 VERIFY_OFFSET(IU_type, 0);
9752 VERIFY_OFFSET(direction, 1);
9753 VERIFY_OFFSET(reply_queue, 2);
9754 /* VERIFY_OFFSET(reserved1, 3); */
9755 VERIFY_OFFSET(scsi_nexus, 4);
9756 VERIFY_OFFSET(Tag, 8);
9757 VERIFY_OFFSET(cdb, 16);
9758 VERIFY_OFFSET(cciss_lun, 32);
9759 VERIFY_OFFSET(data_len, 40);
9760 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9761 VERIFY_OFFSET(sg_count, 45);
9762 /* VERIFY_OFFSET(reserved3 */
9763 VERIFY_OFFSET(err_ptr, 48);
9764 VERIFY_OFFSET(err_len, 56);
9765 /* VERIFY_OFFSET(reserved4 */
9766 VERIFY_OFFSET(sg, 64);
9767
9768#undef VERIFY_OFFSET
9769
e1f7de0c
MG		 9770#define VERIFY_OFFSET(member, offset) \
9771 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9772
9773 VERIFY_OFFSET(dev_handle, 0x00);
9774 VERIFY_OFFSET(reserved1, 0x02);
9775 VERIFY_OFFSET(function, 0x03);
9776 VERIFY_OFFSET(reserved2, 0x04);
9777 VERIFY_OFFSET(err_info, 0x0C);
9778 VERIFY_OFFSET(reserved3, 0x10);
9779 VERIFY_OFFSET(err_info_len, 0x12);
9780 VERIFY_OFFSET(reserved4, 0x13);
9781 VERIFY_OFFSET(sgl_offset, 0x14);
9782 VERIFY_OFFSET(reserved5, 0x15);
9783 VERIFY_OFFSET(transfer_len, 0x1C);
9784 VERIFY_OFFSET(reserved6, 0x20);
9785 VERIFY_OFFSET(io_flags, 0x24);
9786 VERIFY_OFFSET(reserved7, 0x26);
9787 VERIFY_OFFSET(LUN, 0x34);
9788 VERIFY_OFFSET(control, 0x3C);
9789 VERIFY_OFFSET(CDB, 0x40);
9790 VERIFY_OFFSET(reserved8, 0x50);
9791 VERIFY_OFFSET(host_context_flags, 0x60);
9792 VERIFY_OFFSET(timeout_sec, 0x62);
9793 VERIFY_OFFSET(ReplyQueue, 0x64);
9794 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9795 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9796 VERIFY_OFFSET(host_addr, 0x70);
9797 VERIFY_OFFSET(CISS_LUN, 0x78);
9798 VERIFY_OFFSET(SG, 0x78 + 8);
9799#undef VERIFY_OFFSET
9800}
9801
edd16368
SC		 9802module_init(hpsa_init);
9803module_exit(hpsa_cleanup);
ubuntu-bionic-kernel mirror