]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/scsi/hpsa.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
hpsa: use per-cpu variable for lockup_detected
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
094963da 51#include <linux/percpu.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 57#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 128 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
132 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 133 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 134 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 135 {0,}
136};
137
138MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
139
140/* board_id = Subsystem Device ID & Vendor ID
141 * product = Marketing Name for the board
142 * access = Address of the struct of function pointers
143 */
144static struct board_type products[] = {
edd16368
SC		 145 {0x3241103C, "Smart Array P212", &SA5_access},
146 {0x3243103C, "Smart Array P410", &SA5_access},
147 {0x3245103C, "Smart Array P410i", &SA5_access},
148 {0x3247103C, "Smart Array P411", &SA5_access},
149 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 150 {0x324A103C, "Smart Array P712m", &SA5_access},
151 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 152 {0x3350103C, "Smart Array P222", &SA5_access},
153 {0x3351103C, "Smart Array P420", &SA5_access},
154 {0x3352103C, "Smart Array P421", &SA5_access},
155 {0x3353103C, "Smart Array P822", &SA5_access},
156 {0x3354103C, "Smart Array P420i", &SA5_access},
157 {0x3355103C, "Smart Array P220i", &SA5_access},
158 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 159 {0x1921103C, "Smart Array P830i", &SA5_access},
160 {0x1922103C, "Smart Array P430", &SA5_access},
161 {0x1923103C, "Smart Array P431", &SA5_access},
162 {0x1924103C, "Smart Array P830", &SA5_access},
163 {0x1926103C, "Smart Array P731m", &SA5_access},
164 {0x1928103C, "Smart Array P230i", &SA5_access},
165 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 166 {0x21BD103C, "Smart Array", &SA5_access},
167 {0x21BE103C, "Smart Array", &SA5_access},
168 {0x21BF103C, "Smart Array", &SA5_access},
169 {0x21C0103C, "Smart Array", &SA5_access},
170 {0x21C1103C, "Smart Array", &SA5_access},
171 {0x21C2103C, "Smart Array", &SA5_access},
172 {0x21C3103C, "Smart Array", &SA5_access},
173 {0x21C4103C, "Smart Array", &SA5_access},
174 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 175 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 176 {0x21C7103C, "Smart Array", &SA5_access},
177 {0x21C8103C, "Smart Array", &SA5_access},
178 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 179 {0x21CA103C, "Smart Array", &SA5_access},
180 {0x21CB103C, "Smart Array", &SA5_access},
181 {0x21CC103C, "Smart Array", &SA5_access},
182 {0x21CD103C, "Smart Array", &SA5_access},
183 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 184 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
185 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
186 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
187 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
188 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 189 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
190};
191
192static int number_of_controllers;
193
10f66018
SC		 194static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
195static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 196static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
197static void start_io(struct ctlr_info *h);
198
199#ifdef CONFIG_COMPAT
200static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
201#endif
202
203static void cmd_free(struct ctlr_info *h, struct CommandList *c);
204static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
205static struct CommandList *cmd_alloc(struct ctlr_info *h);
206static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 207static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 208 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 209 int cmd_type);
b7bb24eb 210#define VPD_PAGE (1 << 8)
edd16368 211
f281233d 212static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 213static void hpsa_scan_start(struct Scsi_Host *);
214static int hpsa_scan_finished(struct Scsi_Host *sh,
215 unsigned long elapsed_time);
667e23d4
SC		 216static int hpsa_change_queue_depth(struct scsi_device *sdev,
217 int qdepth, int reason);
edd16368
SC		 218
219static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 220static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 221static int hpsa_slave_alloc(struct scsi_device *sdev);
222static void hpsa_slave_destroy(struct scsi_device *sdev);
223
edd16368 224static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 225static int check_for_unit_attention(struct ctlr_info *h,
226 struct CommandList *c);
227static void check_ioctl_unit_attention(struct ctlr_info *h,
228 struct CommandList *c);
303932fd
DB		 229/* performant mode helper functions */
230static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 231 int nsgs, int min_blocks, int *bucket_map);
6f039790 232static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 233static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 234static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
235 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
236 u64 *cfg_offset);
237static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
238 unsigned long *memory_bar);
239static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
240static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
241 int wait_for_ready);
75167d2c 242static inline void finish_cmd(struct CommandList *c);
283b4a9b 243static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 244#define BOARD_NOT_READY 0
245#define BOARD_READY 1
23100dd9 246static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 247static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 248static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
249 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
250 u8 *scsi3addr);
edd16368 251
edd16368
SC		 252static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
253{
254 unsigned long *priv = shost_priv(sdev->host);
255 return (struct ctlr_info *) *priv;
256}
257
a23513e8
SC		 258static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
259{
260 unsigned long *priv = shost_priv(sh);
261 return (struct ctlr_info *) *priv;
262}
263
edd16368
SC		 264static int check_for_unit_attention(struct ctlr_info *h,
265 struct CommandList *c)
266{
267 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
268 return 0;
269
270 switch (c->err_info->SenseInfo[12]) {
271 case STATE_CHANGED:
f79cfec6 272 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 273 "detected, command retried\n", h->ctlr);
274 break;
275 case LUN_FAILED:
f79cfec6 276 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 277 "detected, action required\n", h->ctlr);
278 break;
279 case REPORT_LUNS_CHANGED:
f79cfec6 280 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 281 "changed, action required\n", h->ctlr);
edd16368 282 /*
4f4eb9f1
ST		 283 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
284 * target (array) devices.
edd16368
SC		 285 */
286 break;
287 case POWER_OR_RESET:
f79cfec6 288 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 289 "or device reset detected\n", h->ctlr);
290 break;
291 case UNIT_ATTENTION_CLEARED:
f79cfec6 292 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 293 "cleared by another initiator\n", h->ctlr);
294 break;
295 default:
f79cfec6 296 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 297 "unit attention detected\n", h->ctlr);
298 break;
299 }
300 return 1;
301}
302
852af20a
MB		 303static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
304{
305 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
306 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
307 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
308 return 0;
309 dev_warn(&h->pdev->dev, HPSA "device busy");
310 return 1;
311}
312
da0697bd
ST		 313static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
314 struct device_attribute *attr,
315 const char *buf, size_t count)
316{
317 int status, len;
318 struct ctlr_info *h;
319 struct Scsi_Host *shost = class_to_shost(dev);
320 char tmpbuf[10];
321
322 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
323 return -EACCES;
324 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
325 strncpy(tmpbuf, buf, len);
326 tmpbuf[len] = '\0';
327 if (sscanf(tmpbuf, "%d", &status) != 1)
328 return -EINVAL;
329 h = shost_to_hba(shost);
330 h->acciopath_status = !!status;
331 dev_warn(&h->pdev->dev,
332 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
333 h->acciopath_status ? "enabled" : "disabled");
334 return count;
335}
336
2ba8bfc8
SC		 337static ssize_t host_store_raid_offload_debug(struct device *dev,
338 struct device_attribute *attr,
339 const char *buf, size_t count)
340{
341 int debug_level, len;
342 struct ctlr_info *h;
343 struct Scsi_Host *shost = class_to_shost(dev);
344 char tmpbuf[10];
345
346 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
347 return -EACCES;
348 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
349 strncpy(tmpbuf, buf, len);
350 tmpbuf[len] = '\0';
351 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
352 return -EINVAL;
353 if (debug_level < 0)
354 debug_level = 0;
355 h = shost_to_hba(shost);
356 h->raid_offload_debug = debug_level;
357 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
358 h->raid_offload_debug);
359 return count;
360}
361
edd16368
SC		 362static ssize_t host_store_rescan(struct device *dev,
363 struct device_attribute *attr,
364 const char *buf, size_t count)
365{
366 struct ctlr_info *h;
367 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 368 h = shost_to_hba(shost);
31468401 369 hpsa_scan_start(h->scsi_host);
edd16368
SC		 370 return count;
371}
372
d28ce020
SC		 373static ssize_t host_show_firmware_revision(struct device *dev,
374 struct device_attribute *attr, char *buf)
375{
376 struct ctlr_info *h;
377 struct Scsi_Host *shost = class_to_shost(dev);
378 unsigned char *fwrev;
379
380 h = shost_to_hba(shost);
381 if (!h->hba_inquiry_data)
382 return 0;
383 fwrev = &h->hba_inquiry_data[32];
384 return snprintf(buf, 20, "%c%c%c%c\n",
385 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
386}
387
94a13649
SC		 388static ssize_t host_show_commands_outstanding(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 struct Scsi_Host *shost = class_to_shost(dev);
392 struct ctlr_info *h = shost_to_hba(shost);
393
394 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
395}
396
745a7a25
SC		 397static ssize_t host_show_transport_mode(struct device *dev,
398 struct device_attribute *attr, char *buf)
399{
400 struct ctlr_info *h;
401 struct Scsi_Host *shost = class_to_shost(dev);
402
403 h = shost_to_hba(shost);
404 return snprintf(buf, 20, "%s\n",
960a30e7 405 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 406 "performant" : "simple");
407}
408
da0697bd
ST		 409static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
410 struct device_attribute *attr, char *buf)
411{
412 struct ctlr_info *h;
413 struct Scsi_Host *shost = class_to_shost(dev);
414
415 h = shost_to_hba(shost);
416 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
417 (h->acciopath_status == 1) ? "enabled" : "disabled");
418}
419
46380786 420/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 421static u32 unresettable_controller[] = {
422 0x324a103C, /* Smart Array P712m */
423 0x324b103C, /* SmartArray P711m */
424 0x3223103C, /* Smart Array P800 */
425 0x3234103C, /* Smart Array P400 */
426 0x3235103C, /* Smart Array P400i */
427 0x3211103C, /* Smart Array E200i */
428 0x3212103C, /* Smart Array E200 */
429 0x3213103C, /* Smart Array E200i */
430 0x3214103C, /* Smart Array E200i */
431 0x3215103C, /* Smart Array E200i */
432 0x3237103C, /* Smart Array E500 */
433 0x323D103C, /* Smart Array P700m */
7af0abbc 434 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 435 0x409C0E11, /* Smart Array 6400 */
436 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 437 0x40700E11, /* Smart Array 5300 */
438 0x40820E11, /* Smart Array 532 */
439 0x40830E11, /* Smart Array 5312 */
440 0x409A0E11, /* Smart Array 641 */
441 0x409B0E11, /* Smart Array 642 */
442 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 443};
444
46380786
SC		 445/* List of controllers which cannot even be soft reset */
446static u32 soft_unresettable_controller[] = {
7af0abbc 447 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 448 0x40700E11, /* Smart Array 5300 */
449 0x40820E11, /* Smart Array 532 */
450 0x40830E11, /* Smart Array 5312 */
451 0x409A0E11, /* Smart Array 641 */
452 0x409B0E11, /* Smart Array 642 */
453 0x40910E11, /* Smart Array 6i */
46380786
SC		 454 /* Exclude 640x boards. These are two pci devices in one slot
455 * which share a battery backed cache module. One controls the
456 * cache, the other accesses the cache through the one that controls
457 * it. If we reset the one controlling the cache, the other will
458 * likely not be happy. Just forbid resetting this conjoined mess.
459 * The 640x isn't really supported by hpsa anyway.
460 */
461 0x409C0E11, /* Smart Array 6400 */
462 0x409D0E11, /* Smart Array 6400 EM */
463};
464
465static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 466{
467 int i;
468
469 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 470 if (unresettable_controller[i] == board_id)
471 return 0;
472 return 1;
473}
474
475static int ctlr_is_soft_resettable(u32 board_id)
476{
477 int i;
478
479 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
480 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 481 return 0;
482 return 1;
483}
484
46380786
SC		 485static int ctlr_is_resettable(u32 board_id)
486{
487 return ctlr_is_hard_resettable(board_id) ||
488 ctlr_is_soft_resettable(board_id);
489}
490
941b1cda
SC		 491static ssize_t host_show_resettable(struct device *dev,
492 struct device_attribute *attr, char *buf)
493{
494 struct ctlr_info *h;
495 struct Scsi_Host *shost = class_to_shost(dev);
496
497 h = shost_to_hba(shost);
46380786 498 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 499}
500
edd16368
SC		 501static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
502{
503 return (scsi3addr[3] & 0xC0) == 0x40;
504}
505
506static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 507 "1(ADM)", "UNKNOWN"
edd16368 508};
6b80b18f
ST		 509#define HPSA_RAID_0 0
510#define HPSA_RAID_4 1
511#define HPSA_RAID_1 2 /* also used for RAID 10 */
512#define HPSA_RAID_5 3 /* also used for RAID 50 */
513#define HPSA_RAID_51 4
514#define HPSA_RAID_6 5 /* also used for RAID 60 */
515#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 516#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
517
518static ssize_t raid_level_show(struct device *dev,
519 struct device_attribute *attr, char *buf)
520{
521 ssize_t l = 0;
82a72c0a 522 unsigned char rlevel;
edd16368
SC		 523 struct ctlr_info *h;
524 struct scsi_device *sdev;
525 struct hpsa_scsi_dev_t *hdev;
526 unsigned long flags;
527
528 sdev = to_scsi_device(dev);
529 h = sdev_to_hba(sdev);
530 spin_lock_irqsave(&h->lock, flags);
531 hdev = sdev->hostdata;
532 if (!hdev) {
533 spin_unlock_irqrestore(&h->lock, flags);
534 return -ENODEV;
535 }
536
537 /* Is this even a logical drive? */
538 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
539 spin_unlock_irqrestore(&h->lock, flags);
540 l = snprintf(buf, PAGE_SIZE, "N/A\n");
541 return l;
542 }
543
544 rlevel = hdev->raid_level;
545 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 546 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 547 rlevel = RAID_UNKNOWN;
548 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
549 return l;
550}
551
552static ssize_t lunid_show(struct device *dev,
553 struct device_attribute *attr, char *buf)
554{
555 struct ctlr_info *h;
556 struct scsi_device *sdev;
557 struct hpsa_scsi_dev_t *hdev;
558 unsigned long flags;
559 unsigned char lunid[8];
560
561 sdev = to_scsi_device(dev);
562 h = sdev_to_hba(sdev);
563 spin_lock_irqsave(&h->lock, flags);
564 hdev = sdev->hostdata;
565 if (!hdev) {
566 spin_unlock_irqrestore(&h->lock, flags);
567 return -ENODEV;
568 }
569 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
570 spin_unlock_irqrestore(&h->lock, flags);
571 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
572 lunid[0], lunid[1], lunid[2], lunid[3],
573 lunid[4], lunid[5], lunid[6], lunid[7]);
574}
575
576static ssize_t unique_id_show(struct device *dev,
577 struct device_attribute *attr, char *buf)
578{
579 struct ctlr_info *h;
580 struct scsi_device *sdev;
581 struct hpsa_scsi_dev_t *hdev;
582 unsigned long flags;
583 unsigned char sn[16];
584
585 sdev = to_scsi_device(dev);
586 h = sdev_to_hba(sdev);
587 spin_lock_irqsave(&h->lock, flags);
588 hdev = sdev->hostdata;
589 if (!hdev) {
590 spin_unlock_irqrestore(&h->lock, flags);
591 return -ENODEV;
592 }
593 memcpy(sn, hdev->device_id, sizeof(sn));
594 spin_unlock_irqrestore(&h->lock, flags);
595 return snprintf(buf, 16 * 2 + 2,
596 "%02X%02X%02X%02X%02X%02X%02X%02X"
597 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
598 sn[0], sn[1], sn[2], sn[3],
599 sn[4], sn[5], sn[6], sn[7],
600 sn[8], sn[9], sn[10], sn[11],
601 sn[12], sn[13], sn[14], sn[15]);
602}
603
c1988684
ST		 604static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
605 struct device_attribute *attr, char *buf)
606{
607 struct ctlr_info *h;
608 struct scsi_device *sdev;
609 struct hpsa_scsi_dev_t *hdev;
610 unsigned long flags;
611 int offload_enabled;
612
613 sdev = to_scsi_device(dev);
614 h = sdev_to_hba(sdev);
615 spin_lock_irqsave(&h->lock, flags);
616 hdev = sdev->hostdata;
617 if (!hdev) {
618 spin_unlock_irqrestore(&h->lock, flags);
619 return -ENODEV;
620 }
621 offload_enabled = hdev->offload_enabled;
622 spin_unlock_irqrestore(&h->lock, flags);
623 return snprintf(buf, 20, "%d\n", offload_enabled);
624}
625
3f5eac3a
SC		 626static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
627static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
628static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
629static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 630static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
631 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 632static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
633 host_show_hp_ssd_smart_path_status,
634 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 635static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
636 host_store_raid_offload_debug);
3f5eac3a
SC		 637static DEVICE_ATTR(firmware_revision, S_IRUGO,
638 host_show_firmware_revision, NULL);
639static DEVICE_ATTR(commands_outstanding, S_IRUGO,
640 host_show_commands_outstanding, NULL);
641static DEVICE_ATTR(transport_mode, S_IRUGO,
642 host_show_transport_mode, NULL);
941b1cda
SC		 643static DEVICE_ATTR(resettable, S_IRUGO,
644 host_show_resettable, NULL);
3f5eac3a
SC		 645
646static struct device_attribute *hpsa_sdev_attrs[] = {
647 &dev_attr_raid_level,
648 &dev_attr_lunid,
649 &dev_attr_unique_id,
c1988684 650 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 651 NULL,
652};
653
654static struct device_attribute *hpsa_shost_attrs[] = {
655 &dev_attr_rescan,
656 &dev_attr_firmware_revision,
657 &dev_attr_commands_outstanding,
658 &dev_attr_transport_mode,
941b1cda 659 &dev_attr_resettable,
da0697bd 660 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 661 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 662 NULL,
663};
664
665static struct scsi_host_template hpsa_driver_template = {
666 .module = THIS_MODULE,
f79cfec6
SC		 667 .name = HPSA,
668 .proc_name = HPSA,
3f5eac3a
SC		 669 .queuecommand = hpsa_scsi_queue_command,
670 .scan_start = hpsa_scan_start,
671 .scan_finished = hpsa_scan_finished,
672 .change_queue_depth = hpsa_change_queue_depth,
673 .this_id = -1,
674 .use_clustering = ENABLE_CLUSTERING,
75167d2c 675 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 676 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
677 .ioctl = hpsa_ioctl,
678 .slave_alloc = hpsa_slave_alloc,
679 .slave_destroy = hpsa_slave_destroy,
680#ifdef CONFIG_COMPAT
681 .compat_ioctl = hpsa_compat_ioctl,
682#endif
683 .sdev_attrs = hpsa_sdev_attrs,
684 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 685 .max_sectors = 8192,
54b2b50c 686 .no_write_same = 1,
3f5eac3a
SC		 687};
688
689
690/* Enqueuing and dequeuing functions for cmdlists. */
691static inline void addQ(struct list_head *list, struct CommandList *c)
692{
693 list_add_tail(&c->list, list);
694}
695
254f796b 696static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 697{
698 u32 a;
072b0518 699 struct reply_queue_buffer *rq = &h->reply_queue[q];
e16a33ad 700 unsigned long flags;
3f5eac3a 701
e1f7de0c
MG		 702 if (h->transMethod & CFGTBL_Trans_io_accel1)
703 return h->access.command_completed(h, q);
704
3f5eac3a 705 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 706 return h->access.command_completed(h, q);
3f5eac3a 707
254f796b
MG		 708 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
709 a = rq->head[rq->current_entry];
710 rq->current_entry++;
e16a33ad 711 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 712 h->commands_outstanding--;
e16a33ad 713 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 714 } else {
715 a = FIFO_EMPTY;
716 }
717 /* Check for wraparound */
254f796b
MG		 718 if (rq->current_entry == h->max_commands) {
719 rq->current_entry = 0;
720 rq->wraparound ^= 1;
3f5eac3a
SC		 721 }
722 return a;
723}
724
c349775e
ST		 725/*
726 * There are some special bits in the bus address of the
727 * command that we have to set for the controller to know
728 * how to process the command:
729 *
730 * Normal performant mode:
731 * bit 0: 1 means performant mode, 0 means simple mode.
732 * bits 1-3 = block fetch table entry
733 * bits 4-6 = command type (== 0)
734 *
735 * ioaccel1 mode:
736 * bit 0 = "performant mode" bit.
737 * bits 1-3 = block fetch table entry
738 * bits 4-6 = command type (== 110)
739 * (command type is needed because ioaccel1 mode
740 * commands are submitted through the same register as normal
741 * mode commands, so this is how the controller knows whether
742 * the command is normal mode or ioaccel1 mode.)
743 *
744 * ioaccel2 mode:
745 * bit 0 = "performant mode" bit.
746 * bits 1-4 = block fetch table entry (note extra bit)
747 * bits 4-6 = not needed, because ioaccel2 mode has
748 * a separate special register for submitting commands.
749 */
750
3f5eac3a
SC		 751/* set_performant_mode: Modify the tag for cciss performant
752 * set bit 0 for pull model, bits 3-1 for block fetch
753 * register number
754 */
755static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
756{
254f796b 757 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 758 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 759 if (likely(h->msix_vector > 0))
254f796b 760 c->Header.ReplyQueue =
804a5cb5 761 raw_smp_processor_id() % h->nreply_queues;
254f796b 762 }
3f5eac3a
SC		 763}
764
c349775e
ST		 765static void set_ioaccel1_performant_mode(struct ctlr_info *h,
766 struct CommandList *c)
767{
768 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
769
770 /* Tell the controller to post the reply to the queue for this
771 * processor. This seems to give the best I/O throughput.
772 */
773 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
774 /* Set the bits in the address sent down to include:
775 * - performant mode bit (bit 0)
776 * - pull count (bits 1-3)
777 * - command type (bits 4-6)
778 */
779 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
780 IOACCEL1_BUSADDR_CMDTYPE;
781}
782
783static void set_ioaccel2_performant_mode(struct ctlr_info *h,
784 struct CommandList *c)
785{
786 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
787
788 /* Tell the controller to post the reply to the queue for this
789 * processor. This seems to give the best I/O throughput.
790 */
791 cp->reply_queue = smp_processor_id() % h->nreply_queues;
792 /* Set the bits in the address sent down to include:
793 * - performant mode bit not used in ioaccel mode 2
794 * - pull count (bits 0-3)
795 * - command type isn't needed for ioaccel2
796 */
797 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
798}
799
e85c5974
SC		 800static int is_firmware_flash_cmd(u8 *cdb)
801{
802 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
803}
804
805/*
806 * During firmware flash, the heartbeat register may not update as frequently
807 * as it should. So we dial down lockup detection during firmware flash. and
808 * dial it back up when firmware flash completes.
809 */
810#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
811#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
812static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
813 struct CommandList *c)
814{
815 if (!is_firmware_flash_cmd(c->Request.CDB))
816 return;
817 atomic_inc(&h->firmware_flash_in_progress);
818 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
819}
820
821static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
822 struct CommandList *c)
823{
824 if (is_firmware_flash_cmd(c->Request.CDB) &&
825 atomic_dec_and_test(&h->firmware_flash_in_progress))
826 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
827}
828
3f5eac3a
SC		 829static void enqueue_cmd_and_start_io(struct ctlr_info *h,
830 struct CommandList *c)
831{
832 unsigned long flags;
833
c349775e
ST		 834 switch (c->cmd_type) {
835 case CMD_IOACCEL1:
836 set_ioaccel1_performant_mode(h, c);
837 break;
838 case CMD_IOACCEL2:
839 set_ioaccel2_performant_mode(h, c);
840 break;
841 default:
842 set_performant_mode(h, c);
843 }
e85c5974 844 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 845 spin_lock_irqsave(&h->lock, flags);
846 addQ(&h->reqQ, c);
847 h->Qdepth++;
3f5eac3a 848 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 849 start_io(h);
3f5eac3a
SC		 850}
851
852static inline void removeQ(struct CommandList *c)
853{
854 if (WARN_ON(list_empty(&c->list)))
855 return;
856 list_del_init(&c->list);
857}
858
859static inline int is_hba_lunid(unsigned char scsi3addr[])
860{
861 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
862}
863
864static inline int is_scsi_rev_5(struct ctlr_info *h)
865{
866 if (!h->hba_inquiry_data)
867 return 0;
868 if ((h->hba_inquiry_data[2] & 0x07) == 5)
869 return 1;
870 return 0;
871}
872
edd16368
SC		 873static int hpsa_find_target_lun(struct ctlr_info *h,
874 unsigned char scsi3addr[], int bus, int *target, int *lun)
875{
876 /* finds an unused bus, target, lun for a new physical device
877 * assumes h->devlock is held
878 */
879 int i, found = 0;
cfe5badc 880 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 881
263d9401 882 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 883
884 for (i = 0; i < h->ndevices; i++) {
885 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 886 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 887 }
888
263d9401
AM		 889 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
890 if (i < HPSA_MAX_DEVICES) {
891 /* *bus = 1; */
892 *target = i;
893 *lun = 0;
894 found = 1;
edd16368
SC		 895 }
896 return !found;
897}
898
899/* Add an entry into h->dev[] array. */
900static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
901 struct hpsa_scsi_dev_t *device,
902 struct hpsa_scsi_dev_t *added[], int *nadded)
903{
904 /* assumes h->devlock is held */
905 int n = h->ndevices;
906 int i;
907 unsigned char addr1[8], addr2[8];
908 struct hpsa_scsi_dev_t *sd;
909
cfe5badc 910 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 911 dev_err(&h->pdev->dev, "too many devices, some will be "
912 "inaccessible.\n");
913 return -1;
914 }
915
916 /* physical devices do not have lun or target assigned until now. */
917 if (device->lun != -1)
918 /* Logical device, lun is already assigned. */
919 goto lun_assigned;
920
921 /* If this device a non-zero lun of a multi-lun device
922 * byte 4 of the 8-byte LUN addr will contain the logical
923 * unit no, zero otherise.
924 */
925 if (device->scsi3addr[4] == 0) {
926 /* This is not a non-zero lun of a multi-lun device */
927 if (hpsa_find_target_lun(h, device->scsi3addr,
928 device->bus, &device->target, &device->lun) != 0)
929 return -1;
930 goto lun_assigned;
931 }
932
933 /* This is a non-zero lun of a multi-lun device.
934 * Search through our list and find the device which
935 * has the same 8 byte LUN address, excepting byte 4.
936 * Assign the same bus and target for this new LUN.
937 * Use the logical unit number from the firmware.
938 */
939 memcpy(addr1, device->scsi3addr, 8);
940 addr1[4] = 0;
941 for (i = 0; i < n; i++) {
942 sd = h->dev[i];
943 memcpy(addr2, sd->scsi3addr, 8);
944 addr2[4] = 0;
945 /* differ only in byte 4? */
946 if (memcmp(addr1, addr2, 8) == 0) {
947 device->bus = sd->bus;
948 device->target = sd->target;
949 device->lun = device->scsi3addr[4];
950 break;
951 }
952 }
953 if (device->lun == -1) {
954 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
955 " suspect firmware bug or unsupported hardware "
956 "configuration.\n");
957 return -1;
958 }
959
960lun_assigned:
961
962 h->dev[n] = device;
963 h->ndevices++;
964 added[*nadded] = device;
965 (*nadded)++;
966
967 /* initially, (before registering with scsi layer) we don't
968 * know our hostno and we don't want to print anything first
969 * time anyway (the scsi layer's inquiries will show that info)
970 */
971 /* if (hostno != -1) */
972 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
973 scsi_device_type(device->devtype), hostno,
974 device->bus, device->target, device->lun);
975 return 0;
976}
977
bd9244f7
ST		 978/* Update an entry in h->dev[] array. */
979static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
980 int entry, struct hpsa_scsi_dev_t *new_entry)
981{
982 /* assumes h->devlock is held */
983 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
984
985 /* Raid level changed. */
986 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 987
988 /* Raid offload parameters changed. */
989 h->dev[entry]->offload_config = new_entry->offload_config;
990 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 991 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
992 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
993 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 994
bd9244f7
ST		 995 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
996 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
997 new_entry->target, new_entry->lun);
998}
999
2a8ccf31
SC		 1000/* Replace an entry from h->dev[] array. */
1001static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1002 int entry, struct hpsa_scsi_dev_t *new_entry,
1003 struct hpsa_scsi_dev_t *added[], int *nadded,
1004 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1005{
1006 /* assumes h->devlock is held */
cfe5badc 1007 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1008 removed[*nremoved] = h->dev[entry];
1009 (*nremoved)++;
01350d05
SC		 1010
1011 /*
1012 * New physical devices won't have target/lun assigned yet
1013 * so we need to preserve the values in the slot we are replacing.
1014 */
1015 if (new_entry->target == -1) {
1016 new_entry->target = h->dev[entry]->target;
1017 new_entry->lun = h->dev[entry]->lun;
1018 }
1019
2a8ccf31
SC		 1020 h->dev[entry] = new_entry;
1021 added[*nadded] = new_entry;
1022 (*nadded)++;
1023 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1024 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1025 new_entry->target, new_entry->lun);
1026}
1027
edd16368
SC		 1028/* Remove an entry from h->dev[] array. */
1029static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1030 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1031{
1032 /* assumes h->devlock is held */
1033 int i;
1034 struct hpsa_scsi_dev_t *sd;
1035
cfe5badc 1036 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1037
1038 sd = h->dev[entry];
1039 removed[*nremoved] = h->dev[entry];
1040 (*nremoved)++;
1041
1042 for (i = entry; i < h->ndevices-1; i++)
1043 h->dev[i] = h->dev[i+1];
1044 h->ndevices--;
1045 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1046 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1047 sd->lun);
1048}
1049
1050#define SCSI3ADDR_EQ(a, b) ( \
1051 (a)[7] == (b)[7] && \
1052 (a)[6] == (b)[6] && \
1053 (a)[5] == (b)[5] && \
1054 (a)[4] == (b)[4] && \
1055 (a)[3] == (b)[3] && \
1056 (a)[2] == (b)[2] && \
1057 (a)[1] == (b)[1] && \
1058 (a)[0] == (b)[0])
1059
1060static void fixup_botched_add(struct ctlr_info *h,
1061 struct hpsa_scsi_dev_t *added)
1062{
1063 /* called when scsi_add_device fails in order to re-adjust
1064 * h->dev[] to match the mid layer's view.
1065 */
1066 unsigned long flags;
1067 int i, j;
1068
1069 spin_lock_irqsave(&h->lock, flags);
1070 for (i = 0; i < h->ndevices; i++) {
1071 if (h->dev[i] == added) {
1072 for (j = i; j < h->ndevices-1; j++)
1073 h->dev[j] = h->dev[j+1];
1074 h->ndevices--;
1075 break;
1076 }
1077 }
1078 spin_unlock_irqrestore(&h->lock, flags);
1079 kfree(added);
1080}
1081
1082static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1083 struct hpsa_scsi_dev_t *dev2)
1084{
edd16368
SC		 1085 /* we compare everything except lun and target as these
1086 * are not yet assigned. Compare parts likely
1087 * to differ first
1088 */
1089 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1090 sizeof(dev1->scsi3addr)) != 0)
1091 return 0;
1092 if (memcmp(dev1->device_id, dev2->device_id,
1093 sizeof(dev1->device_id)) != 0)
1094 return 0;
1095 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1096 return 0;
1097 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1098 return 0;
edd16368
SC		 1099 if (dev1->devtype != dev2->devtype)
1100 return 0;
edd16368
SC		 1101 if (dev1->bus != dev2->bus)
1102 return 0;
1103 return 1;
1104}
1105
bd9244f7
ST		 1106static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1107 struct hpsa_scsi_dev_t *dev2)
1108{
1109 /* Device attributes that can change, but don't mean
1110 * that the device is a different device, nor that the OS
1111 * needs to be told anything about the change.
1112 */
1113 if (dev1->raid_level != dev2->raid_level)
1114 return 1;
250fb125
SC		 1115 if (dev1->offload_config != dev2->offload_config)
1116 return 1;
1117 if (dev1->offload_enabled != dev2->offload_enabled)
1118 return 1;
bd9244f7
ST		 1119 return 0;
1120}
1121
edd16368
SC		 1122/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1123 * and return needle location in *index. If scsi3addr matches, but not
1124 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1125 * location in *index.
1126 * In the case of a minor device attribute change, such as RAID level, just
1127 * return DEVICE_UPDATED, along with the updated device's location in index.
1128 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1129 */
1130static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1131 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1132 int *index)
1133{
1134 int i;
1135#define DEVICE_NOT_FOUND 0
1136#define DEVICE_CHANGED 1
1137#define DEVICE_SAME 2
bd9244f7 1138#define DEVICE_UPDATED 3
edd16368 1139 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1140 if (haystack[i] == NULL) /* previously removed. */
1141 continue;
edd16368
SC		 1142 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1143 *index = i;
bd9244f7
ST		 1144 if (device_is_the_same(needle, haystack[i])) {
1145 if (device_updated(needle, haystack[i]))
1146 return DEVICE_UPDATED;
edd16368 1147 return DEVICE_SAME;
bd9244f7 1148 } else {
9846590e
SC		 1149 /* Keep offline devices offline */
1150 if (needle->volume_offline)
1151 return DEVICE_NOT_FOUND;
edd16368 1152 return DEVICE_CHANGED;
bd9244f7 1153 }
edd16368
SC		 1154 }
1155 }
1156 *index = -1;
1157 return DEVICE_NOT_FOUND;
1158}
1159
9846590e
SC		 1160static void hpsa_monitor_offline_device(struct ctlr_info *h,
1161 unsigned char scsi3addr[])
1162{
1163 struct offline_device_entry *device;
1164 unsigned long flags;
1165
1166 /* Check to see if device is already on the list */
1167 spin_lock_irqsave(&h->offline_device_lock, flags);
1168 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1169 if (memcmp(device->scsi3addr, scsi3addr,
1170 sizeof(device->scsi3addr)) == 0) {
1171 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1172 return;
1173 }
1174 }
1175 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1176
1177 /* Device is not on the list, add it. */
1178 device = kmalloc(sizeof(*device), GFP_KERNEL);
1179 if (!device) {
1180 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1181 return;
1182 }
1183 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1184 spin_lock_irqsave(&h->offline_device_lock, flags);
1185 list_add_tail(&device->offline_list, &h->offline_device_list);
1186 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1187}
1188
1189/* Print a message explaining various offline volume states */
1190static void hpsa_show_volume_status(struct ctlr_info *h,
1191 struct hpsa_scsi_dev_t *sd)
1192{
1193 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1194 dev_info(&h->pdev->dev,
1195 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1196 h->scsi_host->host_no,
1197 sd->bus, sd->target, sd->lun);
1198 switch (sd->volume_offline) {
1199 case HPSA_LV_OK:
1200 break;
1201 case HPSA_LV_UNDERGOING_ERASE:
1202 dev_info(&h->pdev->dev,
1203 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1204 h->scsi_host->host_no,
1205 sd->bus, sd->target, sd->lun);
1206 break;
1207 case HPSA_LV_UNDERGOING_RPI:
1208 dev_info(&h->pdev->dev,
1209 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1210 h->scsi_host->host_no,
1211 sd->bus, sd->target, sd->lun);
1212 break;
1213 case HPSA_LV_PENDING_RPI:
1214 dev_info(&h->pdev->dev,
1215 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1216 h->scsi_host->host_no,
1217 sd->bus, sd->target, sd->lun);
1218 break;
1219 case HPSA_LV_ENCRYPTED_NO_KEY:
1220 dev_info(&h->pdev->dev,
1221 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1222 h->scsi_host->host_no,
1223 sd->bus, sd->target, sd->lun);
1224 break;
1225 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1226 dev_info(&h->pdev->dev,
1227 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1228 h->scsi_host->host_no,
1229 sd->bus, sd->target, sd->lun);
1230 break;
1231 case HPSA_LV_UNDERGOING_ENCRYPTION:
1232 dev_info(&h->pdev->dev,
1233 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1234 h->scsi_host->host_no,
1235 sd->bus, sd->target, sd->lun);
1236 break;
1237 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1238 dev_info(&h->pdev->dev,
1239 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1240 h->scsi_host->host_no,
1241 sd->bus, sd->target, sd->lun);
1242 break;
1243 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1244 dev_info(&h->pdev->dev,
1245 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1246 h->scsi_host->host_no,
1247 sd->bus, sd->target, sd->lun);
1248 break;
1249 case HPSA_LV_PENDING_ENCRYPTION:
1250 dev_info(&h->pdev->dev,
1251 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1252 h->scsi_host->host_no,
1253 sd->bus, sd->target, sd->lun);
1254 break;
1255 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1256 dev_info(&h->pdev->dev,
1257 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1258 h->scsi_host->host_no,
1259 sd->bus, sd->target, sd->lun);
1260 break;
1261 }
1262}
1263
4967bd3e 1264static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1265 struct hpsa_scsi_dev_t *sd[], int nsds)
1266{
1267 /* sd contains scsi3 addresses and devtypes, and inquiry
1268 * data. This function takes what's in sd to be the current
1269 * reality and updates h->dev[] to reflect that reality.
1270 */
1271 int i, entry, device_change, changes = 0;
1272 struct hpsa_scsi_dev_t *csd;
1273 unsigned long flags;
1274 struct hpsa_scsi_dev_t **added, **removed;
1275 int nadded, nremoved;
1276 struct Scsi_Host *sh = NULL;
1277
cfe5badc
ST		 1278 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1279 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1280
1281 if (!added || !removed) {
1282 dev_warn(&h->pdev->dev, "out of memory in "
1283 "adjust_hpsa_scsi_table\n");
1284 goto free_and_out;
1285 }
1286
1287 spin_lock_irqsave(&h->devlock, flags);
1288
1289 /* find any devices in h->dev[] that are not in
1290 * sd[] and remove them from h->dev[], and for any
1291 * devices which have changed, remove the old device
1292 * info and add the new device info.
bd9244f7
ST		 1293 * If minor device attributes change, just update
1294 * the existing device structure.
edd16368
SC		 1295 */
1296 i = 0;
1297 nremoved = 0;
1298 nadded = 0;
1299 while (i < h->ndevices) {
1300 csd = h->dev[i];
1301 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1302 if (device_change == DEVICE_NOT_FOUND) {
1303 changes++;
1304 hpsa_scsi_remove_entry(h, hostno, i,
1305 removed, &nremoved);
1306 continue; /* remove ^^^, hence i not incremented */
1307 } else if (device_change == DEVICE_CHANGED) {
1308 changes++;
2a8ccf31
SC		 1309 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1310 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1311 /* Set it to NULL to prevent it from being freed
1312 * at the bottom of hpsa_update_scsi_devices()
1313 */
1314 sd[entry] = NULL;
bd9244f7
ST		 1315 } else if (device_change == DEVICE_UPDATED) {
1316 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1317 }
1318 i++;
1319 }
1320
1321 /* Now, make sure every device listed in sd[] is also
1322 * listed in h->dev[], adding them if they aren't found
1323 */
1324
1325 for (i = 0; i < nsds; i++) {
1326 if (!sd[i]) /* if already added above. */
1327 continue;
9846590e
SC		 1328
1329 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1330 * as the SCSI mid-layer does not handle such devices well.
1331 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1332 * at 160Hz, and prevents the system from coming up.
1333 */
1334 if (sd[i]->volume_offline) {
1335 hpsa_show_volume_status(h, sd[i]);
1336 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1337 h->scsi_host->host_no,
1338 sd[i]->bus, sd[i]->target, sd[i]->lun);
1339 continue;
1340 }
1341
edd16368
SC		 1342 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1343 h->ndevices, &entry);
1344 if (device_change == DEVICE_NOT_FOUND) {
1345 changes++;
1346 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1347 added, &nadded) != 0)
1348 break;
1349 sd[i] = NULL; /* prevent from being freed later. */
1350 } else if (device_change == DEVICE_CHANGED) {
1351 /* should never happen... */
1352 changes++;
1353 dev_warn(&h->pdev->dev,
1354 "device unexpectedly changed.\n");
1355 /* but if it does happen, we just ignore that device */
1356 }
1357 }
1358 spin_unlock_irqrestore(&h->devlock, flags);
1359
9846590e
SC		 1360 /* Monitor devices which are in one of several NOT READY states to be
1361 * brought online later. This must be done without holding h->devlock,
1362 * so don't touch h->dev[]
1363 */
1364 for (i = 0; i < nsds; i++) {
1365 if (!sd[i]) /* if already added above. */
1366 continue;
1367 if (sd[i]->volume_offline)
1368 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1369 }
1370
edd16368
SC		 1371 /* Don't notify scsi mid layer of any changes the first time through
1372 * (or if there are no changes) scsi_scan_host will do it later the
1373 * first time through.
1374 */
1375 if (hostno == -1 || !changes)
1376 goto free_and_out;
1377
1378 sh = h->scsi_host;
1379 /* Notify scsi mid layer of any removed devices */
1380 for (i = 0; i < nremoved; i++) {
1381 struct scsi_device *sdev =
1382 scsi_device_lookup(sh, removed[i]->bus,
1383 removed[i]->target, removed[i]->lun);
1384 if (sdev != NULL) {
1385 scsi_remove_device(sdev);
1386 scsi_device_put(sdev);
1387 } else {
1388 /* We don't expect to get here.
1389 * future cmds to this device will get selection
1390 * timeout as if the device was gone.
1391 */
1392 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1393 " for removal.", hostno, removed[i]->bus,
1394 removed[i]->target, removed[i]->lun);
1395 }
1396 kfree(removed[i]);
1397 removed[i] = NULL;
1398 }
1399
1400 /* Notify scsi mid layer of any added devices */
1401 for (i = 0; i < nadded; i++) {
1402 if (scsi_add_device(sh, added[i]->bus,
1403 added[i]->target, added[i]->lun) == 0)
1404 continue;
1405 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1406 "device not added.\n", hostno, added[i]->bus,
1407 added[i]->target, added[i]->lun);
1408 /* now we have to remove it from h->dev,
1409 * since it didn't get added to scsi mid layer
1410 */
1411 fixup_botched_add(h, added[i]);
1412 }
1413
1414free_and_out:
1415 kfree(added);
1416 kfree(removed);
edd16368
SC		 1417}
1418
1419/*
9e03aa2f 1420 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1421 * Assume's h->devlock is held.
1422 */
1423static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1424 int bus, int target, int lun)
1425{
1426 int i;
1427 struct hpsa_scsi_dev_t *sd;
1428
1429 for (i = 0; i < h->ndevices; i++) {
1430 sd = h->dev[i];
1431 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1432 return sd;
1433 }
1434 return NULL;
1435}
1436
1437/* link sdev->hostdata to our per-device structure. */
1438static int hpsa_slave_alloc(struct scsi_device *sdev)
1439{
1440 struct hpsa_scsi_dev_t *sd;
1441 unsigned long flags;
1442 struct ctlr_info *h;
1443
1444 h = sdev_to_hba(sdev);
1445 spin_lock_irqsave(&h->devlock, flags);
1446 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1447 sdev_id(sdev), sdev->lun);
1448 if (sd != NULL)
1449 sdev->hostdata = sd;
1450 spin_unlock_irqrestore(&h->devlock, flags);
1451 return 0;
1452}
1453
1454static void hpsa_slave_destroy(struct scsi_device *sdev)
1455{
bcc44255 1456 /* nothing to do. */
edd16368
SC		 1457}
1458
33a2ffce
SC		 1459static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1460{
1461 int i;
1462
1463 if (!h->cmd_sg_list)
1464 return;
1465 for (i = 0; i < h->nr_cmds; i++) {
1466 kfree(h->cmd_sg_list[i]);
1467 h->cmd_sg_list[i] = NULL;
1468 }
1469 kfree(h->cmd_sg_list);
1470 h->cmd_sg_list = NULL;
1471}
1472
1473static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1474{
1475 int i;
1476
1477 if (h->chainsize <= 0)
1478 return 0;
1479
1480 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1481 GFP_KERNEL);
1482 if (!h->cmd_sg_list)
1483 return -ENOMEM;
1484 for (i = 0; i < h->nr_cmds; i++) {
1485 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1486 h->chainsize, GFP_KERNEL);
1487 if (!h->cmd_sg_list[i])
1488 goto clean;
1489 }
1490 return 0;
1491
1492clean:
1493 hpsa_free_sg_chain_blocks(h);
1494 return -ENOMEM;
1495}
1496
e2bea6df 1497static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1498 struct CommandList *c)
1499{
1500 struct SGDescriptor *chain_sg, *chain_block;
1501 u64 temp64;
1502
1503 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1504 chain_block = h->cmd_sg_list[c->cmdindex];
1505 chain_sg->Ext = HPSA_SG_CHAIN;
1506 chain_sg->Len = sizeof(*chain_sg) *
1507 (c->Header.SGTotal - h->max_cmd_sg_entries);
1508 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1509 PCI_DMA_TODEVICE);
e2bea6df
SC		 1510 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1511 /* prevent subsequent unmapping */
1512 chain_sg->Addr.lower = 0;
1513 chain_sg->Addr.upper = 0;
1514 return -1;
1515 }
33a2ffce
SC		 1516 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1517 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1518 return 0;
33a2ffce
SC		 1519}
1520
1521static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1522 struct CommandList *c)
1523{
1524 struct SGDescriptor *chain_sg;
1525 union u64bit temp64;
1526
1527 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1528 return;
1529
1530 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1531 temp64.val32.lower = chain_sg->Addr.lower;
1532 temp64.val32.upper = chain_sg->Addr.upper;
1533 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1534}
1535
a09c1441
ST		 1536
1537/* Decode the various types of errors on ioaccel2 path.
1538 * Return 1 for any error that should generate a RAID path retry.
1539 * Return 0 for errors that don't require a RAID path retry.
1540 */
1541static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1542 struct CommandList *c,
1543 struct scsi_cmnd *cmd,
1544 struct io_accel2_cmd *c2)
1545{
1546 int data_len;
a09c1441 1547 int retry = 0;
c349775e
ST		 1548
1549 switch (c2->error_data.serv_response) {
1550 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1551 switch (c2->error_data.status) {
1552 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1553 break;
1554 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1555 dev_warn(&h->pdev->dev,
1556 "%s: task complete with check condition.\n",
1557 "HP SSD Smart Path");
1558 if (c2->error_data.data_present !=
1559 IOACCEL2_SENSE_DATA_PRESENT)
1560 break;
1561 /* copy the sense data */
1562 data_len = c2->error_data.sense_data_len;
1563 if (data_len > SCSI_SENSE_BUFFERSIZE)
1564 data_len = SCSI_SENSE_BUFFERSIZE;
1565 if (data_len > sizeof(c2->error_data.sense_data_buff))
1566 data_len =
1567 sizeof(c2->error_data.sense_data_buff);
1568 memcpy(cmd->sense_buffer,
1569 c2->error_data.sense_data_buff, data_len);
1570 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1571 retry = 1;
c349775e
ST		 1572 break;
1573 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1574 dev_warn(&h->pdev->dev,
1575 "%s: task complete with BUSY status.\n",
1576 "HP SSD Smart Path");
a09c1441 1577 retry = 1;
c349775e
ST		 1578 break;
1579 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1580 dev_warn(&h->pdev->dev,
1581 "%s: task complete with reservation conflict.\n",
1582 "HP SSD Smart Path");
a09c1441 1583 retry = 1;
c349775e
ST		 1584 break;
1585 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1586 /* Make scsi midlayer do unlimited retries */
1587 cmd->result = DID_IMM_RETRY << 16;
1588 break;
1589 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1590 dev_warn(&h->pdev->dev,
1591 "%s: task complete with aborted status.\n",
1592 "HP SSD Smart Path");
a09c1441 1593 retry = 1;
c349775e
ST		 1594 break;
1595 default:
1596 dev_warn(&h->pdev->dev,
1597 "%s: task complete with unrecognized status: 0x%02x\n",
1598 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1599 retry = 1;
c349775e
ST		 1600 break;
1601 }
1602 break;
1603 case IOACCEL2_SERV_RESPONSE_FAILURE:
1604 /* don't expect to get here. */
1605 dev_warn(&h->pdev->dev,
1606 "unexpected delivery or target failure, status = 0x%02x\n",
1607 c2->error_data.status);
a09c1441 1608 retry = 1;
c349775e
ST		 1609 break;
1610 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1611 break;
1612 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1613 break;
1614 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1615 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1616 retry = 1;
c349775e
ST		 1617 break;
1618 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1619 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1620 break;
1621 default:
1622 dev_warn(&h->pdev->dev,
1623 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1624 "HP SSD Smart Path",
1625 c2->error_data.serv_response);
1626 retry = 1;
c349775e
ST		 1627 break;
1628 }
a09c1441
ST		 1629
1630 return retry; /* retry on raid path? */
c349775e
ST		 1631}
1632
1633static void process_ioaccel2_completion(struct ctlr_info *h,
1634 struct CommandList *c, struct scsi_cmnd *cmd,
1635 struct hpsa_scsi_dev_t *dev)
1636{
1637 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1638 int raid_retry = 0;
c349775e
ST		 1639
1640 /* check for good status */
1641 if (likely(c2->error_data.serv_response == 0 &&
1642 c2->error_data.status == 0)) {
1643 cmd_free(h, c);
1644 cmd->scsi_done(cmd);
1645 return;
1646 }
1647
1648 /* Any RAID offload error results in retry which will use
1649 * the normal I/O path so the controller can handle whatever's
1650 * wrong.
1651 */
1652 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1653 c2->error_data.serv_response ==
1654 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1655 if (c2->error_data.status ==
1656 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1657 dev_warn(&h->pdev->dev,
1658 "%s: Path is unavailable, retrying on standard path.\n",
1659 "HP SSD Smart Path");
1660 else
c349775e 1661 dev_warn(&h->pdev->dev,
a09c1441 1662 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1663 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1664
c349775e 1665 dev->offload_enabled = 0;
e863d68e 1666 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1667 cmd->result = DID_SOFT_ERROR << 16;
1668 cmd_free(h, c);
1669 cmd->scsi_done(cmd);
1670 return;
1671 }
a09c1441
ST		 1672 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1673 /* If error found, disable Smart Path, schedule a rescan,
1674 * and force a retry on the standard path.
1675 */
1676 if (raid_retry) {
1677 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1678 "HP SSD Smart Path");
1679 dev->offload_enabled = 0; /* Disable Smart Path */
1680 h->drv_req_rescan = 1; /* schedule controller rescan */
1681 cmd->result = DID_SOFT_ERROR << 16;
1682 }
c349775e
ST		 1683 cmd_free(h, c);
1684 cmd->scsi_done(cmd);
1685}
1686
1fb011fb 1687static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1688{
1689 struct scsi_cmnd *cmd;
1690 struct ctlr_info *h;
1691 struct ErrorInfo *ei;
283b4a9b 1692 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1693
1694 unsigned char sense_key;
1695 unsigned char asc; /* additional sense code */
1696 unsigned char ascq; /* additional sense code qualifier */
db111e18 1697 unsigned long sense_data_size;
edd16368
SC		 1698
1699 ei = cp->err_info;
1700 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1701 h = cp->h;
283b4a9b 1702 dev = cmd->device->hostdata;
edd16368
SC		 1703
1704 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1705 if ((cp->cmd_type == CMD_SCSI) &&
1706 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1707 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1708
1709 cmd->result = (DID_OK << 16); /* host byte */
1710 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1711
1712 if (cp->cmd_type == CMD_IOACCEL2)
1713 return process_ioaccel2_completion(h, cp, cmd, dev);
1714
5512672f 1715 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1716
1717 /* copy the sense data whether we need to or not. */
db111e18
SC		 1718 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1719 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1720 else
1721 sense_data_size = sizeof(ei->SenseInfo);
1722 if (ei->SenseLen < sense_data_size)
1723 sense_data_size = ei->SenseLen;
1724
1725 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1726 scsi_set_resid(cmd, ei->ResidualCnt);
1727
1728 if (ei->CommandStatus == 0) {
edd16368 1729 cmd_free(h, cp);
2cc5bfaf 1730 cmd->scsi_done(cmd);
edd16368
SC		 1731 return;
1732 }
1733
e1f7de0c
MG		 1734 /* For I/O accelerator commands, copy over some fields to the normal
1735 * CISS header used below for error handling.
1736 */
1737 if (cp->cmd_type == CMD_IOACCEL1) {
1738 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1739 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1740 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1741 cp->Header.Tag.lower = c->Tag.lower;
1742 cp->Header.Tag.upper = c->Tag.upper;
1743 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1744 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1745
1746 /* Any RAID offload error results in retry which will use
1747 * the normal I/O path so the controller can handle whatever's
1748 * wrong.
1749 */
1750 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1751 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1752 dev->offload_enabled = 0;
1753 cmd->result = DID_SOFT_ERROR << 16;
1754 cmd_free(h, cp);
1755 cmd->scsi_done(cmd);
1756 return;
1757 }
e1f7de0c
MG		 1758 }
1759
edd16368
SC		 1760 /* an error has occurred */
1761 switch (ei->CommandStatus) {
1762
1763 case CMD_TARGET_STATUS:
1764 if (ei->ScsiStatus) {
1765 /* Get sense key */
1766 sense_key = 0xf & ei->SenseInfo[2];
1767 /* Get additional sense code */
1768 asc = ei->SenseInfo[12];
1769 /* Get addition sense code qualifier */
1770 ascq = ei->SenseInfo[13];
1771 }
1772
1773 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1774 if (check_for_unit_attention(h, cp))
edd16368 1775 break;
edd16368
SC		 1776 if (sense_key == ILLEGAL_REQUEST) {
1777 /*
1778 * SCSI REPORT_LUNS is commonly unsupported on
1779 * Smart Array. Suppress noisy complaint.
1780 */
1781 if (cp->Request.CDB[0] == REPORT_LUNS)
1782 break;
1783
1784 /* If ASC/ASCQ indicate Logical Unit
1785 * Not Supported condition,
1786 */
1787 if ((asc == 0x25) && (ascq == 0x0)) {
1788 dev_warn(&h->pdev->dev, "cp %p "
1789 "has check condition\n", cp);
1790 break;
1791 }
1792 }
1793
1794 if (sense_key == NOT_READY) {
1795 /* If Sense is Not Ready, Logical Unit
1796 * Not ready, Manual Intervention
1797 * required
1798 */
1799 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1800 dev_warn(&h->pdev->dev, "cp %p "
1801 "has check condition: unit "
1802 "not ready, manual "
1803 "intervention required\n", cp);
1804 break;
1805 }
1806 }
1d3b3609
MG		 1807 if (sense_key == ABORTED_COMMAND) {
1808 /* Aborted command is retryable */
1809 dev_warn(&h->pdev->dev, "cp %p "
1810 "has check condition: aborted command: "
1811 "ASC: 0x%x, ASCQ: 0x%x\n",
1812 cp, asc, ascq);
2e311fba 1813 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1814 break;
1815 }
edd16368 1816 /* Must be some other type of check condition */
21b8e4ef 1817 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1818 "unknown type: "
1819 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1820 "Returning result: 0x%x, "
1821 "cmd=[%02x %02x %02x %02x %02x "
807be732 1822 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1823 "%02x %02x %02x %02x %02x]\n",
1824 cp, sense_key, asc, ascq,
1825 cmd->result,
1826 cmd->cmnd[0], cmd->cmnd[1],
1827 cmd->cmnd[2], cmd->cmnd[3],
1828 cmd->cmnd[4], cmd->cmnd[5],
1829 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1830 cmd->cmnd[8], cmd->cmnd[9],
1831 cmd->cmnd[10], cmd->cmnd[11],
1832 cmd->cmnd[12], cmd->cmnd[13],
1833 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1834 break;
1835 }
1836
1837
1838 /* Problem was not a check condition
1839 * Pass it up to the upper layers...
1840 */
1841 if (ei->ScsiStatus) {
1842 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1843 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1844 "Returning result: 0x%x\n",
1845 cp, ei->ScsiStatus,
1846 sense_key, asc, ascq,
1847 cmd->result);
1848 } else { /* scsi status is zero??? How??? */
1849 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1850 "Returning no connection.\n", cp),
1851
1852 /* Ordinarily, this case should never happen,
1853 * but there is a bug in some released firmware
1854 * revisions that allows it to happen if, for
1855 * example, a 4100 backplane loses power and
1856 * the tape drive is in it. We assume that
1857 * it's a fatal error of some kind because we
1858 * can't show that it wasn't. We will make it
1859 * look like selection timeout since that is
1860 * the most common reason for this to occur,
1861 * and it's severe enough.
1862 */
1863
1864 cmd->result = DID_NO_CONNECT << 16;
1865 }
1866 break;
1867
1868 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1869 break;
1870 case CMD_DATA_OVERRUN:
1871 dev_warn(&h->pdev->dev, "cp %p has"
1872 " completed with data overrun "
1873 "reported\n", cp);
1874 break;
1875 case CMD_INVALID: {
1876 /* print_bytes(cp, sizeof(*cp), 1, 0);
1877 print_cmd(cp); */
1878 /* We get CMD_INVALID if you address a non-existent device
1879 * instead of a selection timeout (no response). You will
1880 * see this if you yank out a drive, then try to access it.
1881 * This is kind of a shame because it means that any other
1882 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1883 * missing target. */
1884 cmd->result = DID_NO_CONNECT << 16;
1885 }
1886 break;
1887 case CMD_PROTOCOL_ERR:
256d0eaa 1888 cmd->result = DID_ERROR << 16;
edd16368 1889 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1890 "protocol error\n", cp);
edd16368
SC		 1891 break;
1892 case CMD_HARDWARE_ERR:
1893 cmd->result = DID_ERROR << 16;
1894 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1895 break;
1896 case CMD_CONNECTION_LOST:
1897 cmd->result = DID_ERROR << 16;
1898 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1899 break;
1900 case CMD_ABORTED:
1901 cmd->result = DID_ABORT << 16;
1902 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1903 cp, ei->ScsiStatus);
1904 break;
1905 case CMD_ABORT_FAILED:
1906 cmd->result = DID_ERROR << 16;
1907 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1908 break;
1909 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1910 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1911 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1912 "abort\n", cp);
1913 break;
1914 case CMD_TIMEOUT:
1915 cmd->result = DID_TIME_OUT << 16;
1916 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1917 break;
1d5e2ed0
SC		 1918 case CMD_UNABORTABLE:
1919 cmd->result = DID_ERROR << 16;
1920 dev_warn(&h->pdev->dev, "Command unabortable\n");
1921 break;
283b4a9b
SC		 1922 case CMD_IOACCEL_DISABLED:
1923 /* This only handles the direct pass-through case since RAID
1924 * offload is handled above. Just attempt a retry.
1925 */
1926 cmd->result = DID_SOFT_ERROR << 16;
1927 dev_warn(&h->pdev->dev,
1928 "cp %p had HP SSD Smart Path error\n", cp);
1929 break;
edd16368
SC		 1930 default:
1931 cmd->result = DID_ERROR << 16;
1932 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1933 cp, ei->CommandStatus);
1934 }
edd16368 1935 cmd_free(h, cp);
2cc5bfaf 1936 cmd->scsi_done(cmd);
edd16368
SC		 1937}
1938
edd16368
SC		 1939static void hpsa_pci_unmap(struct pci_dev *pdev,
1940 struct CommandList *c, int sg_used, int data_direction)
1941{
1942 int i;
1943 union u64bit addr64;
1944
1945 for (i = 0; i < sg_used; i++) {
1946 addr64.val32.lower = c->SG[i].Addr.lower;
1947 addr64.val32.upper = c->SG[i].Addr.upper;
1948 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1949 data_direction);
1950 }
1951}
1952
a2dac136 1953static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1954 struct CommandList *cp,
1955 unsigned char *buf,
1956 size_t buflen,
1957 int data_direction)
1958{
01a02ffc 1959 u64 addr64;
edd16368
SC		 1960
1961 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1962 cp->Header.SGList = 0;
1963 cp->Header.SGTotal = 0;
a2dac136 1964 return 0;
edd16368
SC		 1965 }
1966
01a02ffc 1967 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1968 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1969 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1970 cp->Header.SGList = 0;
1971 cp->Header.SGTotal = 0;
a2dac136 1972 return -1;
eceaae18 1973 }
edd16368 1974 cp->SG[0].Addr.lower =
01a02ffc 1975 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1976 cp->SG[0].Addr.upper =
01a02ffc 1977 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1978 cp->SG[0].Len = buflen;
e1d9cbfa 1979 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1980 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1981 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1982 return 0;
edd16368
SC		 1983}
1984
1985static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1986 struct CommandList *c)
1987{
1988 DECLARE_COMPLETION_ONSTACK(wait);
1989
1990 c->waiting = &wait;
1991 enqueue_cmd_and_start_io(h, c);
1992 wait_for_completion(&wait);
1993}
1994
094963da
SC		 1995static u32 lockup_detected(struct ctlr_info *h)
1996{
1997 int cpu;
1998 u32 rc, *lockup_detected;
1999
2000 cpu = get_cpu();
2001 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2002 rc = *lockup_detected;
2003 put_cpu();
2004 return rc;
2005}
2006
a0c12413
SC		 2007static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
2008 struct CommandList *c)
2009{
a0c12413 2010 /* If controller lockup detected, fake a hardware error. */
094963da 2011 if (unlikely(lockup_detected(h)))
a0c12413 2012 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 2013 else
a0c12413 2014 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 2015}
2016
9c2fc160 2017#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 2018static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2019 struct CommandList *c, int data_direction)
2020{
9c2fc160 2021 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2022
2023 do {
7630abd0 2024 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2025 hpsa_scsi_do_simple_cmd_core(h, c);
2026 retry_count++;
9c2fc160
SC		 2027 if (retry_count > 3) {
2028 msleep(backoff_time);
2029 if (backoff_time < 1000)
2030 backoff_time *= 2;
2031 }
852af20a 2032 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2033 check_for_busy(h, c)) &&
2034 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2035 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2036}
2037
d1e8beac
SC		 2038static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2039 struct CommandList *c)
edd16368 2040{
d1e8beac
SC		 2041 const u8 *cdb = c->Request.CDB;
2042 const u8 *lun = c->Header.LUN.LunAddrBytes;
2043
2044 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2045 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2046 txt, lun[0], lun[1], lun[2], lun[3],
2047 lun[4], lun[5], lun[6], lun[7],
2048 cdb[0], cdb[1], cdb[2], cdb[3],
2049 cdb[4], cdb[5], cdb[6], cdb[7],
2050 cdb[8], cdb[9], cdb[10], cdb[11],
2051 cdb[12], cdb[13], cdb[14], cdb[15]);
2052}
2053
2054static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2055 struct CommandList *cp)
2056{
2057 const struct ErrorInfo *ei = cp->err_info;
edd16368 2058 struct device *d = &cp->h->pdev->dev;
d1e8beac 2059 const u8 *sd = ei->SenseInfo;
edd16368 2060
edd16368
SC		 2061 switch (ei->CommandStatus) {
2062 case CMD_TARGET_STATUS:
d1e8beac
SC		 2063 hpsa_print_cmd(h, "SCSI status", cp);
2064 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2065 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2066 sd[2] & 0x0f, sd[12], sd[13]);
2067 else
2068 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2069 if (ei->ScsiStatus == 0)
2070 dev_warn(d, "SCSI status is abnormally zero. "
2071 "(probably indicates selection timeout "
2072 "reported incorrectly due to a known "
2073 "firmware bug, circa July, 2001.)\n");
2074 break;
2075 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2076 break;
2077 case CMD_DATA_OVERRUN:
d1e8beac 2078 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2079 break;
2080 case CMD_INVALID: {
2081 /* controller unfortunately reports SCSI passthru's
2082 * to non-existent targets as invalid commands.
2083 */
d1e8beac
SC		 2084 hpsa_print_cmd(h, "invalid command", cp);
2085 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2086 }
2087 break;
2088 case CMD_PROTOCOL_ERR:
d1e8beac 2089 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2090 break;
2091 case CMD_HARDWARE_ERR:
d1e8beac 2092 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2093 break;
2094 case CMD_CONNECTION_LOST:
d1e8beac 2095 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2096 break;
2097 case CMD_ABORTED:
d1e8beac 2098 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2099 break;
2100 case CMD_ABORT_FAILED:
d1e8beac 2101 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2102 break;
2103 case CMD_UNSOLICITED_ABORT:
d1e8beac 2104 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2105 break;
2106 case CMD_TIMEOUT:
d1e8beac 2107 hpsa_print_cmd(h, "timed out", cp);
edd16368 2108 break;
1d5e2ed0 2109 case CMD_UNABORTABLE:
d1e8beac 2110 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2111 break;
edd16368 2112 default:
d1e8beac
SC		 2113 hpsa_print_cmd(h, "unknown status", cp);
2114 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2115 ei->CommandStatus);
2116 }
2117}
2118
2119static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2120 u16 page, unsigned char *buf,
edd16368
SC		 2121 unsigned char bufsize)
2122{
2123 int rc = IO_OK;
2124 struct CommandList *c;
2125 struct ErrorInfo *ei;
2126
2127 c = cmd_special_alloc(h);
2128
2129 if (c == NULL) { /* trouble... */
2130 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2131 return -ENOMEM;
edd16368
SC		 2132 }
2133
a2dac136
SC		 2134 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2135 page, scsi3addr, TYPE_CMD)) {
2136 rc = -1;
2137 goto out;
2138 }
edd16368
SC		 2139 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2140 ei = c->err_info;
2141 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2142 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2143 rc = -1;
2144 }
a2dac136 2145out:
edd16368
SC		 2146 cmd_special_free(h, c);
2147 return rc;
2148}
2149
316b221a
SC		 2150static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2151 unsigned char *scsi3addr, unsigned char page,
2152 struct bmic_controller_parameters *buf, size_t bufsize)
2153{
2154 int rc = IO_OK;
2155 struct CommandList *c;
2156 struct ErrorInfo *ei;
2157
2158 c = cmd_special_alloc(h);
2159
2160 if (c == NULL) { /* trouble... */
2161 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2162 return -ENOMEM;
2163 }
2164
2165 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2166 page, scsi3addr, TYPE_CMD)) {
2167 rc = -1;
2168 goto out;
2169 }
2170 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2171 ei = c->err_info;
2172 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2173 hpsa_scsi_interpret_error(h, c);
2174 rc = -1;
2175 }
2176out:
2177 cmd_special_free(h, c);
2178 return rc;
2179 }
2180
bf711ac6
ST		 2181static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2182 u8 reset_type)
edd16368
SC		 2183{
2184 int rc = IO_OK;
2185 struct CommandList *c;
2186 struct ErrorInfo *ei;
2187
2188 c = cmd_special_alloc(h);
2189
2190 if (c == NULL) { /* trouble... */
2191 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2192 return -ENOMEM;
edd16368
SC		 2193 }
2194
a2dac136 2195 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2196 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2197 scsi3addr, TYPE_MSG);
2198 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2199 hpsa_scsi_do_simple_cmd_core(h, c);
2200 /* no unmap needed here because no data xfer. */
2201
2202 ei = c->err_info;
2203 if (ei->CommandStatus != 0) {
d1e8beac 2204 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2205 rc = -1;
2206 }
2207 cmd_special_free(h, c);
2208 return rc;
2209}
2210
2211static void hpsa_get_raid_level(struct ctlr_info *h,
2212 unsigned char *scsi3addr, unsigned char *raid_level)
2213{
2214 int rc;
2215 unsigned char *buf;
2216
2217 *raid_level = RAID_UNKNOWN;
2218 buf = kzalloc(64, GFP_KERNEL);
2219 if (!buf)
2220 return;
b7bb24eb 2221 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2222 if (rc == 0)
2223 *raid_level = buf[8];
2224 if (*raid_level > RAID_UNKNOWN)
2225 *raid_level = RAID_UNKNOWN;
2226 kfree(buf);
2227 return;
2228}
2229
283b4a9b
SC		 2230#define HPSA_MAP_DEBUG
2231#ifdef HPSA_MAP_DEBUG
2232static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2233 struct raid_map_data *map_buff)
2234{
2235 struct raid_map_disk_data *dd = &map_buff->data[0];
2236 int map, row, col;
2237 u16 map_cnt, row_cnt, disks_per_row;
2238
2239 if (rc != 0)
2240 return;
2241
2ba8bfc8
SC		 2242 /* Show details only if debugging has been activated. */
2243 if (h->raid_offload_debug < 2)
2244 return;
2245
283b4a9b
SC		 2246 dev_info(&h->pdev->dev, "structure_size = %u\n",
2247 le32_to_cpu(map_buff->structure_size));
2248 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2249 le32_to_cpu(map_buff->volume_blk_size));
2250 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2251 le64_to_cpu(map_buff->volume_blk_cnt));
2252 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2253 map_buff->phys_blk_shift);
2254 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2255 map_buff->parity_rotation_shift);
2256 dev_info(&h->pdev->dev, "strip_size = %u\n",
2257 le16_to_cpu(map_buff->strip_size));
2258 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2259 le64_to_cpu(map_buff->disk_starting_blk));
2260 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2261 le64_to_cpu(map_buff->disk_blk_cnt));
2262 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2263 le16_to_cpu(map_buff->data_disks_per_row));
2264 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2265 le16_to_cpu(map_buff->metadata_disks_per_row));
2266 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2267 le16_to_cpu(map_buff->row_cnt));
2268 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2269 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2270 dev_info(&h->pdev->dev, "flags = %u\n",
2271 le16_to_cpu(map_buff->flags));
2272 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2273 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2274 else
2275 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2276 dev_info(&h->pdev->dev, "dekindex = %u\n",
2277 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2278
2279 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2280 for (map = 0; map < map_cnt; map++) {
2281 dev_info(&h->pdev->dev, "Map%u:\n", map);
2282 row_cnt = le16_to_cpu(map_buff->row_cnt);
2283 for (row = 0; row < row_cnt; row++) {
2284 dev_info(&h->pdev->dev, " Row%u:\n", row);
2285 disks_per_row =
2286 le16_to_cpu(map_buff->data_disks_per_row);
2287 for (col = 0; col < disks_per_row; col++, dd++)
2288 dev_info(&h->pdev->dev,
2289 " D%02u: h=0x%04x xor=%u,%u\n",
2290 col, dd->ioaccel_handle,
2291 dd->xor_mult[0], dd->xor_mult[1]);
2292 disks_per_row =
2293 le16_to_cpu(map_buff->metadata_disks_per_row);
2294 for (col = 0; col < disks_per_row; col++, dd++)
2295 dev_info(&h->pdev->dev,
2296 " M%02u: h=0x%04x xor=%u,%u\n",
2297 col, dd->ioaccel_handle,
2298 dd->xor_mult[0], dd->xor_mult[1]);
2299 }
2300 }
2301}
2302#else
2303static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2304 __attribute__((unused)) int rc,
2305 __attribute__((unused)) struct raid_map_data *map_buff)
2306{
2307}
2308#endif
2309
2310static int hpsa_get_raid_map(struct ctlr_info *h,
2311 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2312{
2313 int rc = 0;
2314 struct CommandList *c;
2315 struct ErrorInfo *ei;
2316
2317 c = cmd_special_alloc(h);
2318 if (c == NULL) {
2319 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2320 return -ENOMEM;
2321 }
2322 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2323 sizeof(this_device->raid_map), 0,
2324 scsi3addr, TYPE_CMD)) {
2325 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2326 cmd_special_free(h, c);
2327 return -ENOMEM;
2328 }
2329 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2330 ei = c->err_info;
2331 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2332 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2333 cmd_special_free(h, c);
2334 return -1;
2335 }
2336 cmd_special_free(h, c);
2337
2338 /* @todo in the future, dynamically allocate RAID map memory */
2339 if (le32_to_cpu(this_device->raid_map.structure_size) >
2340 sizeof(this_device->raid_map)) {
2341 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2342 rc = -1;
2343 }
2344 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2345 return rc;
2346}
2347
1b70150a
SC		 2348static int hpsa_vpd_page_supported(struct ctlr_info *h,
2349 unsigned char scsi3addr[], u8 page)
2350{
2351 int rc;
2352 int i;
2353 int pages;
2354 unsigned char *buf, bufsize;
2355
2356 buf = kzalloc(256, GFP_KERNEL);
2357 if (!buf)
2358 return 0;
2359
2360 /* Get the size of the page list first */
2361 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2362 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2363 buf, HPSA_VPD_HEADER_SZ);
2364 if (rc != 0)
2365 goto exit_unsupported;
2366 pages = buf[3];
2367 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2368 bufsize = pages + HPSA_VPD_HEADER_SZ;
2369 else
2370 bufsize = 255;
2371
2372 /* Get the whole VPD page list */
2373 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2374 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2375 buf, bufsize);
2376 if (rc != 0)
2377 goto exit_unsupported;
2378
2379 pages = buf[3];
2380 for (i = 1; i <= pages; i++)
2381 if (buf[3 + i] == page)
2382 goto exit_supported;
2383exit_unsupported:
2384 kfree(buf);
2385 return 0;
2386exit_supported:
2387 kfree(buf);
2388 return 1;
2389}
2390
283b4a9b
SC		 2391static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2392 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2393{
2394 int rc;
2395 unsigned char *buf;
2396 u8 ioaccel_status;
2397
2398 this_device->offload_config = 0;
2399 this_device->offload_enabled = 0;
2400
2401 buf = kzalloc(64, GFP_KERNEL);
2402 if (!buf)
2403 return;
1b70150a
SC		 2404 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2405 goto out;
283b4a9b 2406 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2407 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2408 if (rc != 0)
2409 goto out;
2410
2411#define IOACCEL_STATUS_BYTE 4
2412#define OFFLOAD_CONFIGURED_BIT 0x01
2413#define OFFLOAD_ENABLED_BIT 0x02
2414 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2415 this_device->offload_config =
2416 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2417 if (this_device->offload_config) {
2418 this_device->offload_enabled =
2419 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2420 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2421 this_device->offload_enabled = 0;
2422 }
2423out:
2424 kfree(buf);
2425 return;
2426}
2427
edd16368
SC		 2428/* Get the device id from inquiry page 0x83 */
2429static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2430 unsigned char *device_id, int buflen)
2431{
2432 int rc;
2433 unsigned char *buf;
2434
2435 if (buflen > 16)
2436 buflen = 16;
2437 buf = kzalloc(64, GFP_KERNEL);
2438 if (!buf)
2439 return -1;
b7bb24eb 2440 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2441 if (rc == 0)
2442 memcpy(device_id, &buf[8], buflen);
2443 kfree(buf);
2444 return rc != 0;
2445}
2446
2447static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2448 struct ReportLUNdata *buf, int bufsize,
2449 int extended_response)
2450{
2451 int rc = IO_OK;
2452 struct CommandList *c;
2453 unsigned char scsi3addr[8];
2454 struct ErrorInfo *ei;
2455
2456 c = cmd_special_alloc(h);
2457 if (c == NULL) { /* trouble... */
2458 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2459 return -1;
2460 }
e89c0ae7
SC		 2461 /* address the controller */
2462 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2463 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2464 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2465 rc = -1;
2466 goto out;
2467 }
edd16368
SC		 2468 if (extended_response)
2469 c->Request.CDB[1] = extended_response;
2470 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2471 ei = c->err_info;
2472 if (ei->CommandStatus != 0 &&
2473 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2474 hpsa_scsi_interpret_error(h, c);
edd16368 2475 rc = -1;
283b4a9b
SC		 2476 } else {
2477 if (buf->extended_response_flag != extended_response) {
2478 dev_err(&h->pdev->dev,
2479 "report luns requested format %u, got %u\n",
2480 extended_response,
2481 buf->extended_response_flag);
2482 rc = -1;
2483 }
edd16368 2484 }
a2dac136 2485out:
edd16368
SC		 2486 cmd_special_free(h, c);
2487 return rc;
2488}
2489
2490static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2491 struct ReportLUNdata *buf,
2492 int bufsize, int extended_response)
2493{
2494 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2495}
2496
2497static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2498 struct ReportLUNdata *buf, int bufsize)
2499{
2500 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2501}
2502
2503static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2504 int bus, int target, int lun)
2505{
2506 device->bus = bus;
2507 device->target = target;
2508 device->lun = lun;
2509}
2510
9846590e
SC		 2511/* Use VPD inquiry to get details of volume status */
2512static int hpsa_get_volume_status(struct ctlr_info *h,
2513 unsigned char scsi3addr[])
2514{
2515 int rc;
2516 int status;
2517 int size;
2518 unsigned char *buf;
2519
2520 buf = kzalloc(64, GFP_KERNEL);
2521 if (!buf)
2522 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2523
2524 /* Does controller have VPD for logical volume status? */
2525 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) {
2526 dev_warn(&h->pdev->dev, "Logical volume status VPD page is unsupported.\n");
2527 goto exit_failed;
2528 }
2529
2530 /* Get the size of the VPD return buffer */
2531 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2532 buf, HPSA_VPD_HEADER_SZ);
2533 if (rc != 0) {
2534 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2535 goto exit_failed;
2536 }
2537 size = buf[3];
2538
2539 /* Now get the whole VPD buffer */
2540 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2541 buf, size + HPSA_VPD_HEADER_SZ);
2542 if (rc != 0) {
2543 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2544 goto exit_failed;
2545 }
2546 status = buf[4]; /* status byte */
2547
2548 kfree(buf);
2549 return status;
2550exit_failed:
2551 kfree(buf);
2552 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2553}
2554
2555/* Determine offline status of a volume.
2556 * Return either:
2557 * 0 (not offline)
2558 * -1 (offline for unknown reasons)
2559 * # (integer code indicating one of several NOT READY states
2560 * describing why a volume is to be kept offline)
2561 */
2562static unsigned char hpsa_volume_offline(struct ctlr_info *h,
2563 unsigned char scsi3addr[])
2564{
2565 struct CommandList *c;
2566 unsigned char *sense, sense_key, asc, ascq;
2567 int ldstat = 0;
2568 u16 cmd_status;
2569 u8 scsi_status;
2570#define ASC_LUN_NOT_READY 0x04
2571#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2572#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2573
2574 c = cmd_alloc(h);
2575 if (!c)
2576 return 0;
2577 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2578 hpsa_scsi_do_simple_cmd_core(h, c);
2579 sense = c->err_info->SenseInfo;
2580 sense_key = sense[2];
2581 asc = sense[12];
2582 ascq = sense[13];
2583 cmd_status = c->err_info->CommandStatus;
2584 scsi_status = c->err_info->ScsiStatus;
2585 cmd_free(h, c);
2586 /* Is the volume 'not ready'? */
2587 if (cmd_status != CMD_TARGET_STATUS ||
2588 scsi_status != SAM_STAT_CHECK_CONDITION ||
2589 sense_key != NOT_READY ||
2590 asc != ASC_LUN_NOT_READY) {
2591 return 0;
2592 }
2593
2594 /* Determine the reason for not ready state */
2595 ldstat = hpsa_get_volume_status(h, scsi3addr);
2596
2597 /* Keep volume offline in certain cases: */
2598 switch (ldstat) {
2599 case HPSA_LV_UNDERGOING_ERASE:
2600 case HPSA_LV_UNDERGOING_RPI:
2601 case HPSA_LV_PENDING_RPI:
2602 case HPSA_LV_ENCRYPTED_NO_KEY:
2603 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2604 case HPSA_LV_UNDERGOING_ENCRYPTION:
2605 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2606 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2607 return ldstat;
2608 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2609 /* If VPD status page isn't available,
2610 * use ASC/ASCQ to determine state
2611 */
2612 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2613 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2614 return ldstat;
2615 break;
2616 default:
2617 break;
2618 }
2619 return 0;
2620}
2621
edd16368 2622static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2623 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2624 unsigned char *is_OBDR_device)
edd16368 2625{
0b0e1d6c
SC		 2626
2627#define OBDR_SIG_OFFSET 43
2628#define OBDR_TAPE_SIG "$DR-10"
2629#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2630#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2631
ea6d3bc3 2632 unsigned char *inq_buff;
0b0e1d6c 2633 unsigned char *obdr_sig;
edd16368 2634
ea6d3bc3 2635 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2636 if (!inq_buff)
2637 goto bail_out;
2638
edd16368
SC		 2639 /* Do an inquiry to the device to see what it is. */
2640 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2641 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2642 /* Inquiry failed (msg printed already) */
2643 dev_err(&h->pdev->dev,
2644 "hpsa_update_device_info: inquiry failed\n");
2645 goto bail_out;
2646 }
2647
edd16368
SC		 2648 this_device->devtype = (inq_buff[0] & 0x1f);
2649 memcpy(this_device->scsi3addr, scsi3addr, 8);
2650 memcpy(this_device->vendor, &inq_buff[8],
2651 sizeof(this_device->vendor));
2652 memcpy(this_device->model, &inq_buff[16],
2653 sizeof(this_device->model));
edd16368
SC		 2654 memset(this_device->device_id, 0,
2655 sizeof(this_device->device_id));
2656 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2657 sizeof(this_device->device_id));
2658
2659 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2660 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2661 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2662 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2663 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
9846590e
SC		 2664 this_device->volume_offline =
2665 hpsa_volume_offline(h, scsi3addr);
283b4a9b 2666 } else {
edd16368 2667 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2668 this_device->offload_config = 0;
2669 this_device->offload_enabled = 0;
9846590e 2670 this_device->volume_offline = 0;
283b4a9b 2671 }
edd16368 2672
0b0e1d6c
SC		 2673 if (is_OBDR_device) {
2674 /* See if this is a One-Button-Disaster-Recovery device
2675 * by looking for "$DR-10" at offset 43 in inquiry data.
2676 */
2677 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2678 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2679 strncmp(obdr_sig, OBDR_TAPE_SIG,
2680 OBDR_SIG_LEN) == 0);
2681 }
2682
edd16368
SC		 2683 kfree(inq_buff);
2684 return 0;
2685
2686bail_out:
2687 kfree(inq_buff);
2688 return 1;
2689}
2690
4f4eb9f1 2691static unsigned char *ext_target_model[] = {
edd16368
SC		 2692 "MSA2012",
2693 "MSA2024",
2694 "MSA2312",
2695 "MSA2324",
fda38518 2696 "P2000 G3 SAS",
e06c8e5c 2697 "MSA 2040 SAS",
edd16368
SC		 2698 NULL,
2699};
2700
4f4eb9f1 2701static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2702{
2703 int i;
2704
4f4eb9f1
ST		 2705 for (i = 0; ext_target_model[i]; i++)
2706 if (strncmp(device->model, ext_target_model[i],
2707 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2708 return 1;
2709 return 0;
2710}
2711
2712/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2713 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2714 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2715 * Logical drive target and lun are assigned at this time, but
2716 * physical device lun and target assignment are deferred (assigned
2717 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2718 */
2719static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2720 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2721{
1f310bde
SC		 2722 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2723
2724 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2725 /* physical device, target and lun filled in later */
edd16368 2726 if (is_hba_lunid(lunaddrbytes))
1f310bde 2727 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2728 else
1f310bde
SC		 2729 /* defer target, lun assignment for physical devices */
2730 hpsa_set_bus_target_lun(device, 2, -1, -1);
2731 return;
2732 }
2733 /* It's a logical device */
4f4eb9f1
ST		 2734 if (is_ext_target(h, device)) {
2735 /* external target way, put logicals on bus 1
1f310bde
SC		 2736 * and match target/lun numbers box
2737 * reports, other smart array, bus 0, target 0, match lunid
2738 */
2739 hpsa_set_bus_target_lun(device,
2740 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2741 return;
edd16368 2742 }
1f310bde 2743 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2744}
2745
2746/*
2747 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2748 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2749 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2750 * it for some reason. *tmpdevice is the target we're adding,
2751 * this_device is a pointer into the current element of currentsd[]
2752 * that we're building up in update_scsi_devices(), below.
2753 * lunzerobits is a bitmap that tracks which targets already have a
2754 * lun 0 assigned.
2755 * Returns 1 if an enclosure was added, 0 if not.
2756 */
4f4eb9f1 2757static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2758 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2759 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2760 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2761{
2762 unsigned char scsi3addr[8];
2763
1f310bde 2764 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2765 return 0; /* There is already a lun 0 on this target. */
2766
2767 if (!is_logical_dev_addr_mode(lunaddrbytes))
2768 return 0; /* It's the logical targets that may lack lun 0. */
2769
4f4eb9f1
ST		 2770 if (!is_ext_target(h, tmpdevice))
2771 return 0; /* Only external target devices have this problem. */
edd16368 2772
1f310bde 2773 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2774 return 0;
2775
c4f8a299 2776 memset(scsi3addr, 0, 8);
1f310bde 2777 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2778 if (is_hba_lunid(scsi3addr))
2779 return 0; /* Don't add the RAID controller here. */
2780
339b2b14
SC		 2781 if (is_scsi_rev_5(h))
2782 return 0; /* p1210m doesn't need to do this. */
2783
4f4eb9f1 2784 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2785 dev_warn(&h->pdev->dev, "Maximum number of external "
2786 "target devices exceeded. Check your hardware "
edd16368
SC		 2787 "configuration.");
2788 return 0;
2789 }
2790
0b0e1d6c 2791 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2792 return 0;
4f4eb9f1 2793 (*n_ext_target_devs)++;
1f310bde
SC		 2794 hpsa_set_bus_target_lun(this_device,
2795 tmpdevice->bus, tmpdevice->target, 0);
2796 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2797 return 1;
2798}
2799
54b6e9e9
ST		 2800/*
2801 * Get address of physical disk used for an ioaccel2 mode command:
2802 * 1. Extract ioaccel2 handle from the command.
2803 * 2. Find a matching ioaccel2 handle from list of physical disks.
2804 * 3. Return:
2805 * 1 and set scsi3addr to address of matching physical
2806 * 0 if no matching physical disk was found.
2807 */
2808static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2809 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2810{
2811 struct ReportExtendedLUNdata *physicals = NULL;
2812 int responsesize = 24; /* size of physical extended response */
2813 int extended = 2; /* flag forces reporting 'other dev info'. */
2814 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2815 u32 nphysicals = 0; /* number of reported physical devs */
2816 int found = 0; /* found match (1) or not (0) */
2817 u32 find; /* handle we need to match */
2818 int i;
2819 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2820 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2821 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2822 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2823 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2824
2825 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2826 return 0; /* no match */
2827
2828 /* point to the ioaccel2 device handle */
2829 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2830 if (c2a == NULL)
2831 return 0; /* no match */
2832
2833 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2834 if (scmd == NULL)
2835 return 0; /* no match */
2836
2837 d = scmd->device->hostdata;
2838 if (d == NULL)
2839 return 0; /* no match */
2840
2841 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2842 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2843 find = c2a->scsi_nexus;
2844
2ba8bfc8
SC		 2845 if (h->raid_offload_debug > 0)
2846 dev_info(&h->pdev->dev,
2847 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2848 __func__, scsi_nexus,
2849 d->device_id[0], d->device_id[1], d->device_id[2],
2850 d->device_id[3], d->device_id[4], d->device_id[5],
2851 d->device_id[6], d->device_id[7], d->device_id[8],
2852 d->device_id[9], d->device_id[10], d->device_id[11],
2853 d->device_id[12], d->device_id[13], d->device_id[14],
2854 d->device_id[15]);
2855
54b6e9e9
ST		 2856 /* Get the list of physical devices */
2857 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2858 if (physicals == NULL)
2859 return 0;
54b6e9e9
ST		 2860 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2861 reportsize, extended)) {
2862 dev_err(&h->pdev->dev,
2863 "Can't lookup %s device handle: report physical LUNs failed.\n",
2864 "HP SSD Smart Path");
2865 kfree(physicals);
2866 return 0;
2867 }
2868 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2869 responsesize;
2870
2871
2872 /* find ioaccel2 handle in list of physicals: */
2873 for (i = 0; i < nphysicals; i++) {
2874 /* handle is in bytes 28-31 of each lun */
2875 if (memcmp(&((struct ReportExtendedLUNdata *)
2876 physicals)->LUN[i][20], &find, 4) != 0) {
2877 continue; /* didn't match */
2878 }
2879 found = 1;
2880 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2881 physicals)->LUN[i][0], 8);
2ba8bfc8
SC		 2882 if (h->raid_offload_debug > 0)
2883 dev_info(&h->pdev->dev,
2884 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2885 __func__, find,
2886 ((struct ReportExtendedLUNdata *)
2887 physicals)->LUN[i][20],
2888 scsi3addr[0], scsi3addr[1], scsi3addr[2],
2889 scsi3addr[3], scsi3addr[4], scsi3addr[5],
2890 scsi3addr[6], scsi3addr[7]);
54b6e9e9
ST		 2891 break; /* found it */
2892 }
2893
2894 kfree(physicals);
2895 if (found)
2896 return 1;
2897 else
2898 return 0;
2899
2900}
edd16368
SC		 2901/*
2902 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2903 * logdev. The number of luns in physdev and logdev are returned in
2904 * *nphysicals and *nlogicals, respectively.
2905 * Returns 0 on success, -1 otherwise.
2906 */
2907static int hpsa_gather_lun_info(struct ctlr_info *h,
2908 int reportlunsize,
283b4a9b 2909 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2910 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2911{
283b4a9b
SC		 2912 int physical_entry_size = 8;
2913
2914 *physical_mode = 0;
2915
2916 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2917 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2918 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2919 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2920 physical_entry_size = 24;
2921 }
a93aa1fe 2922 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2923 *physical_mode)) {
edd16368
SC		 2924 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2925 return -1;
2926 }
283b4a9b
SC		 2927 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2928 physical_entry_size;
edd16368
SC		 2929 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2930 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2931 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2932 *nphysicals - HPSA_MAX_PHYS_LUN);
2933 *nphysicals = HPSA_MAX_PHYS_LUN;
2934 }
2935 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2936 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2937 return -1;
2938 }
6df1e954 2939 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2940 /* Reject Logicals in excess of our max capability. */
2941 if (*nlogicals > HPSA_MAX_LUN) {
2942 dev_warn(&h->pdev->dev,
2943 "maximum logical LUNs (%d) exceeded. "
2944 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2945 *nlogicals - HPSA_MAX_LUN);
2946 *nlogicals = HPSA_MAX_LUN;
2947 }
2948 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2949 dev_warn(&h->pdev->dev,
2950 "maximum logical + physical LUNs (%d) exceeded. "
2951 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2952 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2953 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2954 }
2955 return 0;
2956}
2957
339b2b14 2958u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2959 int nphysicals, int nlogicals,
2960 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2961 struct ReportLUNdata *logdev_list)
2962{
2963 /* Helper function, figure out where the LUN ID info is coming from
2964 * given index i, lists of physical and logical devices, where in
2965 * the list the raid controller is supposed to appear (first or last)
2966 */
2967
2968 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2969 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2970
2971 if (i == raid_ctlr_position)
2972 return RAID_CTLR_LUNID;
2973
2974 if (i < logicals_start)
2975 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2976
2977 if (i < last_device)
2978 return &logdev_list->LUN[i - nphysicals -
2979 (raid_ctlr_position == 0)][0];
2980 BUG();
2981 return NULL;
2982}
2983
316b221a
SC		 2984static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2985{
2986 int rc;
6e8e8088 2987 int hba_mode_enabled;
316b221a
SC		 2988 struct bmic_controller_parameters *ctlr_params;
2989 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2990 GFP_KERNEL);
2991
2992 if (!ctlr_params)
96444fbb 2993 return -ENOMEM;
316b221a
SC		 2994 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2995 sizeof(struct bmic_controller_parameters));
96444fbb 2996 if (rc) {
316b221a 2997 kfree(ctlr_params);
96444fbb 2998 return rc;
316b221a 2999 }
6e8e8088
JH		 3000
3001 hba_mode_enabled =
3002 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3003 kfree(ctlr_params);
3004 return hba_mode_enabled;
316b221a
SC		 3005}
3006
edd16368
SC		 3007static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3008{
3009 /* the idea here is we could get notified
3010 * that some devices have changed, so we do a report
3011 * physical luns and report logical luns cmd, and adjust
3012 * our list of devices accordingly.
3013 *
3014 * The scsi3addr's of devices won't change so long as the
3015 * adapter is not reset. That means we can rescan and
3016 * tell which devices we already know about, vs. new
3017 * devices, vs. disappearing devices.
3018 */
a93aa1fe 3019 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3020 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 3021 u32 nphysicals = 0;
3022 u32 nlogicals = 0;
283b4a9b 3023 int physical_mode = 0;
01a02ffc 3024 u32 ndev_allocated = 0;
edd16368
SC		 3025 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3026 int ncurrent = 0;
283b4a9b 3027 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 3028 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3029 int raid_ctlr_position;
2bbf5c7f 3030 int rescan_hba_mode;
aca4a520 3031 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3032
cfe5badc 3033 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 3034 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
3035 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 3036 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
3037
0b0e1d6c 3038 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 3039 dev_err(&h->pdev->dev, "out of memory\n");
3040 goto out;
3041 }
3042 memset(lunzerobits, 0, sizeof(lunzerobits));
3043
316b221a 3044 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3045 if (rescan_hba_mode < 0)
3046 goto out;
316b221a
SC		 3047
3048 if (!h->hba_mode_enabled && rescan_hba_mode)
3049 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3050 else if (h->hba_mode_enabled && !rescan_hba_mode)
3051 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3052
3053 h->hba_mode_enabled = rescan_hba_mode;
3054
a93aa1fe
MG		 3055 if (hpsa_gather_lun_info(h, reportlunsize,
3056 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 3057 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 3058 goto out;
3059
aca4a520
ST		 3060 /* We might see up to the maximum number of logical and physical disks
3061 * plus external target devices, and a device for the local RAID
3062 * controller.
edd16368 3063 */
aca4a520 3064 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3065
3066 /* Allocate the per device structures */
3067 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3068 if (i >= HPSA_MAX_DEVICES) {
3069 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3070 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3071 ndevs_to_allocate - HPSA_MAX_DEVICES);
3072 break;
3073 }
3074
edd16368
SC		 3075 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3076 if (!currentsd[i]) {
3077 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3078 __FILE__, __LINE__);
3079 goto out;
3080 }
3081 ndev_allocated++;
3082 }
3083
339b2b14
SC		 3084 if (unlikely(is_scsi_rev_5(h)))
3085 raid_ctlr_position = 0;
3086 else
3087 raid_ctlr_position = nphysicals + nlogicals;
3088
edd16368 3089 /* adjust our table of devices */
4f4eb9f1 3090 n_ext_target_devs = 0;
edd16368 3091 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3092 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3093
3094 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3095 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3096 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3097 /* skip masked physical devices. */
339b2b14
SC		 3098 if (lunaddrbytes[3] & 0xC0 &&
3099 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3100 continue;
3101
3102 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3103 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3104 &is_OBDR))
edd16368 3105 continue; /* skip it if we can't talk to it. */
1f310bde 3106 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3107 this_device = currentsd[ncurrent];
3108
3109 /*
4f4eb9f1 3110 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3111 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3112 * is nonetheless an enclosure device there. We have to
3113 * present that otherwise linux won't find anything if
3114 * there is no lun 0.
3115 */
4f4eb9f1 3116 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3117 lunaddrbytes, lunzerobits,
4f4eb9f1 3118 &n_ext_target_devs)) {
edd16368
SC		 3119 ncurrent++;
3120 this_device = currentsd[ncurrent];
3121 }
3122
3123 *this_device = *tmpdevice;
edd16368
SC		 3124
3125 switch (this_device->devtype) {
0b0e1d6c 3126 case TYPE_ROM:
edd16368
SC		 3127 /* We don't *really* support actual CD-ROM devices,
3128 * just "One Button Disaster Recovery" tape drive
3129 * which temporarily pretends to be a CD-ROM drive.
3130 * So we check that the device is really an OBDR tape
3131 * device by checking for "$DR-10" in bytes 43-48 of
3132 * the inquiry data.
3133 */
0b0e1d6c
SC		 3134 if (is_OBDR)
3135 ncurrent++;
edd16368
SC		 3136 break;
3137 case TYPE_DISK:
316b221a
SC		 3138 if (h->hba_mode_enabled) {
3139 /* never use raid mapper in HBA mode */
3140 this_device->offload_enabled = 0;
3141 ncurrent++;
3142 break;
3143 } else if (h->acciopath_status) {
3144 if (i >= nphysicals) {
3145 ncurrent++;
3146 break;
3147 }
3148 } else {
3149 if (i < nphysicals)
3150 break;
283b4a9b 3151 ncurrent++;
edd16368 3152 break;
283b4a9b
SC		 3153 }
3154 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3155 memcpy(&this_device->ioaccel_handle,
3156 &lunaddrbytes[20],
3157 sizeof(this_device->ioaccel_handle));
3158 ncurrent++;
3159 }
edd16368
SC		 3160 break;
3161 case TYPE_TAPE:
3162 case TYPE_MEDIUM_CHANGER:
3163 ncurrent++;
3164 break;
3165 case TYPE_RAID:
3166 /* Only present the Smartarray HBA as a RAID controller.
3167 * If it's a RAID controller other than the HBA itself
3168 * (an external RAID controller, MSA500 or similar)
3169 * don't present it.
3170 */
3171 if (!is_hba_lunid(lunaddrbytes))
3172 break;
3173 ncurrent++;
3174 break;
3175 default:
3176 break;
3177 }
cfe5badc 3178 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3179 break;
3180 }
3181 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3182out:
3183 kfree(tmpdevice);
3184 for (i = 0; i < ndev_allocated; i++)
3185 kfree(currentsd[i]);
3186 kfree(currentsd);
edd16368
SC		 3187 kfree(physdev_list);
3188 kfree(logdev_list);
edd16368
SC		 3189}
3190
3191/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3192 * dma mapping and fills in the scatter gather entries of the
3193 * hpsa command, cp.
3194 */
33a2ffce 3195static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3196 struct CommandList *cp,
3197 struct scsi_cmnd *cmd)
3198{
3199 unsigned int len;
3200 struct scatterlist *sg;
01a02ffc 3201 u64 addr64;
33a2ffce
SC		 3202 int use_sg, i, sg_index, chained;
3203 struct SGDescriptor *curr_sg;
edd16368 3204
33a2ffce 3205 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3206
3207 use_sg = scsi_dma_map(cmd);
3208 if (use_sg < 0)
3209 return use_sg;
3210
3211 if (!use_sg)
3212 goto sglist_finished;
3213
33a2ffce
SC		 3214 curr_sg = cp->SG;
3215 chained = 0;
3216 sg_index = 0;
edd16368 3217 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3218 if (i == h->max_cmd_sg_entries - 1 &&
3219 use_sg > h->max_cmd_sg_entries) {
3220 chained = 1;
3221 curr_sg = h->cmd_sg_list[cp->cmdindex];
3222 sg_index = 0;
3223 }
01a02ffc 3224 addr64 = (u64) sg_dma_address(sg);
edd16368 3225 len = sg_dma_len(sg);
33a2ffce
SC		 3226 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3227 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3228 curr_sg->Len = len;
e1d9cbfa 3229 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 3230 curr_sg++;
3231 }
3232
3233 if (use_sg + chained > h->maxSG)
3234 h->maxSG = use_sg + chained;
3235
3236 if (chained) {
3237 cp->Header.SGList = h->max_cmd_sg_entries;
3238 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 3239 if (hpsa_map_sg_chain_block(h, cp)) {
3240 scsi_dma_unmap(cmd);
3241 return -1;
3242 }
33a2ffce 3243 return 0;
edd16368
SC		 3244 }
3245
3246sglist_finished:
3247
01a02ffc
SC		 3248 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3249 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 3250 return 0;
3251}
3252
283b4a9b
SC		 3253#define IO_ACCEL_INELIGIBLE (1)
3254static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3255{
3256 int is_write = 0;
3257 u32 block;
3258 u32 block_cnt;
3259
3260 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3261 switch (cdb[0]) {
3262 case WRITE_6:
3263 case WRITE_12:
3264 is_write = 1;
3265 case READ_6:
3266 case READ_12:
3267 if (*cdb_len == 6) {
3268 block = (((u32) cdb[2]) << 8) | cdb[3];
3269 block_cnt = cdb[4];
3270 } else {
3271 BUG_ON(*cdb_len != 12);
3272 block = (((u32) cdb[2]) << 24) |
3273 (((u32) cdb[3]) << 16) |
3274 (((u32) cdb[4]) << 8) |
3275 cdb[5];
3276 block_cnt =
3277 (((u32) cdb[6]) << 24) |
3278 (((u32) cdb[7]) << 16) |
3279 (((u32) cdb[8]) << 8) |
3280 cdb[9];
3281 }
3282 if (block_cnt > 0xffff)
3283 return IO_ACCEL_INELIGIBLE;
3284
3285 cdb[0] = is_write ? WRITE_10 : READ_10;
3286 cdb[1] = 0;
3287 cdb[2] = (u8) (block >> 24);
3288 cdb[3] = (u8) (block >> 16);
3289 cdb[4] = (u8) (block >> 8);
3290 cdb[5] = (u8) (block);
3291 cdb[6] = 0;
3292 cdb[7] = (u8) (block_cnt >> 8);
3293 cdb[8] = (u8) (block_cnt);
3294 cdb[9] = 0;
3295 *cdb_len = 10;
3296 break;
3297 }
3298 return 0;
3299}
3300
c349775e 3301static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3302 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3303 u8 *scsi3addr)
e1f7de0c
MG		 3304{
3305 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3306 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3307 unsigned int len;
3308 unsigned int total_len = 0;
3309 struct scatterlist *sg;
3310 u64 addr64;
3311 int use_sg, i;
3312 struct SGDescriptor *curr_sg;
3313 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3314
283b4a9b
SC		 3315 /* TODO: implement chaining support */
3316 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3317 return IO_ACCEL_INELIGIBLE;
3318
e1f7de0c
MG		 3319 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3320
283b4a9b
SC		 3321 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3322 return IO_ACCEL_INELIGIBLE;
3323
e1f7de0c
MG		 3324 c->cmd_type = CMD_IOACCEL1;
3325
3326 /* Adjust the DMA address to point to the accelerated command buffer */
3327 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3328 (c->cmdindex * sizeof(*cp));
3329 BUG_ON(c->busaddr & 0x0000007F);
3330
3331 use_sg = scsi_dma_map(cmd);
3332 if (use_sg < 0)
3333 return use_sg;
3334
3335 if (use_sg) {
3336 curr_sg = cp->SG;
3337 scsi_for_each_sg(cmd, sg, use_sg, i) {
3338 addr64 = (u64) sg_dma_address(sg);
3339 len = sg_dma_len(sg);
3340 total_len += len;
3341 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3342 curr_sg->Addr.upper =
3343 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3344 curr_sg->Len = len;
3345
3346 if (i == (scsi_sg_count(cmd) - 1))
3347 curr_sg->Ext = HPSA_SG_LAST;
3348 else
3349 curr_sg->Ext = 0; /* we are not chaining */
3350 curr_sg++;
3351 }
3352
3353 switch (cmd->sc_data_direction) {
3354 case DMA_TO_DEVICE:
3355 control |= IOACCEL1_CONTROL_DATA_OUT;
3356 break;
3357 case DMA_FROM_DEVICE:
3358 control |= IOACCEL1_CONTROL_DATA_IN;
3359 break;
3360 case DMA_NONE:
3361 control |= IOACCEL1_CONTROL_NODATAXFER;
3362 break;
3363 default:
3364 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3365 cmd->sc_data_direction);
3366 BUG();
3367 break;
3368 }
3369 } else {
3370 control |= IOACCEL1_CONTROL_NODATAXFER;
3371 }
3372
c349775e 3373 c->Header.SGList = use_sg;
e1f7de0c 3374 /* Fill out the command structure to submit */
283b4a9b 3375 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3376 cp->transfer_len = total_len;
3377 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3378 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3379 cp->control = control;
283b4a9b
SC		 3380 memcpy(cp->CDB, cdb, cdb_len);
3381 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3382 /* Tag was already set at init time. */
283b4a9b 3383 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3384 return 0;
3385}
edd16368 3386
283b4a9b
SC		 3387/*
3388 * Queue a command directly to a device behind the controller using the
3389 * I/O accelerator path.
3390 */
3391static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3392 struct CommandList *c)
3393{
3394 struct scsi_cmnd *cmd = c->scsi_cmd;
3395 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3396
3397 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3398 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3399}
3400
dd0e19f3
ST		 3401/*
3402 * Set encryption parameters for the ioaccel2 request
3403 */
3404static void set_encrypt_ioaccel2(struct ctlr_info *h,
3405 struct CommandList *c, struct io_accel2_cmd *cp)
3406{
3407 struct scsi_cmnd *cmd = c->scsi_cmd;
3408 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3409 struct raid_map_data *map = &dev->raid_map;
3410 u64 first_block;
3411
3412 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3413
3414 /* Are we doing encryption on this device */
3415 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3416 return;
3417 /* Set the data encryption key index. */
3418 cp->dekindex = map->dekindex;
3419
3420 /* Set the encryption enable flag, encoded into direction field. */
3421 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3422
3423 /* Set encryption tweak values based on logical block address
3424 * If block size is 512, tweak value is LBA.
3425 * For other block sizes, tweak is (LBA * block size)/ 512)
3426 */
3427 switch (cmd->cmnd[0]) {
3428 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3429 case WRITE_6:
3430 case READ_6:
3431 if (map->volume_blk_size == 512) {
3432 cp->tweak_lower =
3433 (((u32) cmd->cmnd[2]) << 8) |
3434 cmd->cmnd[3];
3435 cp->tweak_upper = 0;
3436 } else {
3437 first_block =
3438 (((u64) cmd->cmnd[2]) << 8) |
3439 cmd->cmnd[3];
3440 first_block = (first_block * map->volume_blk_size)/512;
3441 cp->tweak_lower = (u32)first_block;
3442 cp->tweak_upper = (u32)(first_block >> 32);
3443 }
3444 break;
3445 case WRITE_10:
3446 case READ_10:
3447 if (map->volume_blk_size == 512) {
3448 cp->tweak_lower =
3449 (((u32) cmd->cmnd[2]) << 24) |
3450 (((u32) cmd->cmnd[3]) << 16) |
3451 (((u32) cmd->cmnd[4]) << 8) |
3452 cmd->cmnd[5];
3453 cp->tweak_upper = 0;
3454 } else {
3455 first_block =
3456 (((u64) cmd->cmnd[2]) << 24) |
3457 (((u64) cmd->cmnd[3]) << 16) |
3458 (((u64) cmd->cmnd[4]) << 8) |
3459 cmd->cmnd[5];
3460 first_block = (first_block * map->volume_blk_size)/512;
3461 cp->tweak_lower = (u32)first_block;
3462 cp->tweak_upper = (u32)(first_block >> 32);
3463 }
3464 break;
3465 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3466 case WRITE_12:
3467 case READ_12:
3468 if (map->volume_blk_size == 512) {
3469 cp->tweak_lower =
3470 (((u32) cmd->cmnd[2]) << 24) |
3471 (((u32) cmd->cmnd[3]) << 16) |
3472 (((u32) cmd->cmnd[4]) << 8) |
3473 cmd->cmnd[5];
3474 cp->tweak_upper = 0;
3475 } else {
3476 first_block =
3477 (((u64) cmd->cmnd[2]) << 24) |
3478 (((u64) cmd->cmnd[3]) << 16) |
3479 (((u64) cmd->cmnd[4]) << 8) |
3480 cmd->cmnd[5];
3481 first_block = (first_block * map->volume_blk_size)/512;
3482 cp->tweak_lower = (u32)first_block;
3483 cp->tweak_upper = (u32)(first_block >> 32);
3484 }
3485 break;
3486 case WRITE_16:
3487 case READ_16:
3488 if (map->volume_blk_size == 512) {
3489 cp->tweak_lower =
3490 (((u32) cmd->cmnd[6]) << 24) |
3491 (((u32) cmd->cmnd[7]) << 16) |
3492 (((u32) cmd->cmnd[8]) << 8) |
3493 cmd->cmnd[9];
3494 cp->tweak_upper =
3495 (((u32) cmd->cmnd[2]) << 24) |
3496 (((u32) cmd->cmnd[3]) << 16) |
3497 (((u32) cmd->cmnd[4]) << 8) |
3498 cmd->cmnd[5];
3499 } else {
3500 first_block =
3501 (((u64) cmd->cmnd[2]) << 56) |
3502 (((u64) cmd->cmnd[3]) << 48) |
3503 (((u64) cmd->cmnd[4]) << 40) |
3504 (((u64) cmd->cmnd[5]) << 32) |
3505 (((u64) cmd->cmnd[6]) << 24) |
3506 (((u64) cmd->cmnd[7]) << 16) |
3507 (((u64) cmd->cmnd[8]) << 8) |
3508 cmd->cmnd[9];
3509 first_block = (first_block * map->volume_blk_size)/512;
3510 cp->tweak_lower = (u32)first_block;
3511 cp->tweak_upper = (u32)(first_block >> 32);
3512 }
3513 break;
3514 default:
3515 dev_err(&h->pdev->dev,
3516 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3517 __func__);
3518 BUG();
3519 break;
3520 }
3521}
3522
c349775e
ST		 3523static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3524 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3525 u8 *scsi3addr)
3526{
3527 struct scsi_cmnd *cmd = c->scsi_cmd;
3528 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3529 struct ioaccel2_sg_element *curr_sg;
3530 int use_sg, i;
3531 struct scatterlist *sg;
3532 u64 addr64;
3533 u32 len;
3534 u32 total_len = 0;
3535
3536 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3537 return IO_ACCEL_INELIGIBLE;
3538
3539 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3540 return IO_ACCEL_INELIGIBLE;
3541 c->cmd_type = CMD_IOACCEL2;
3542 /* Adjust the DMA address to point to the accelerated command buffer */
3543 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3544 (c->cmdindex * sizeof(*cp));
3545 BUG_ON(c->busaddr & 0x0000007F);
3546
3547 memset(cp, 0, sizeof(*cp));
3548 cp->IU_type = IOACCEL2_IU_TYPE;
3549
3550 use_sg = scsi_dma_map(cmd);
3551 if (use_sg < 0)
3552 return use_sg;
3553
3554 if (use_sg) {
3555 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3556 curr_sg = cp->sg;
3557 scsi_for_each_sg(cmd, sg, use_sg, i) {
3558 addr64 = (u64) sg_dma_address(sg);
3559 len = sg_dma_len(sg);
3560 total_len += len;
3561 curr_sg->address = cpu_to_le64(addr64);
3562 curr_sg->length = cpu_to_le32(len);
3563 curr_sg->reserved[0] = 0;
3564 curr_sg->reserved[1] = 0;
3565 curr_sg->reserved[2] = 0;
3566 curr_sg->chain_indicator = 0;
3567 curr_sg++;
3568 }
3569
3570 switch (cmd->sc_data_direction) {
3571 case DMA_TO_DEVICE:
dd0e19f3
ST		 3572 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3573 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3574 break;
3575 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3576 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3577 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3578 break;
3579 case DMA_NONE:
dd0e19f3
ST		 3580 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3581 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3582 break;
3583 default:
3584 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3585 cmd->sc_data_direction);
3586 BUG();
3587 break;
3588 }
3589 } else {
dd0e19f3
ST		 3590 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3591 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3592 }
dd0e19f3
ST		 3593
3594 /* Set encryption parameters, if necessary */
3595 set_encrypt_ioaccel2(h, c, cp);
3596
c349775e 3597 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3598 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3599 DIRECT_LOOKUP_BIT;
3600 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3601
3602 /* fill in sg elements */
3603 cp->sg_count = (u8) use_sg;
3604
3605 cp->data_len = cpu_to_le32(total_len);
3606 cp->err_ptr = cpu_to_le64(c->busaddr +
3607 offsetof(struct io_accel2_cmd, error_data));
3608 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3609
3610 enqueue_cmd_and_start_io(h, c);
3611 return 0;
3612}
3613
3614/*
3615 * Queue a command to the correct I/O accelerator path.
3616 */
3617static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3618 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3619 u8 *scsi3addr)
3620{
3621 if (h->transMethod & CFGTBL_Trans_io_accel1)
3622 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3623 cdb, cdb_len, scsi3addr);
3624 else
3625 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3626 cdb, cdb_len, scsi3addr);
3627}
3628
6b80b18f
ST		 3629static void raid_map_helper(struct raid_map_data *map,
3630 int offload_to_mirror, u32 *map_index, u32 *current_group)
3631{
3632 if (offload_to_mirror == 0) {
3633 /* use physical disk in the first mirrored group. */
3634 *map_index %= map->data_disks_per_row;
3635 return;
3636 }
3637 do {
3638 /* determine mirror group that *map_index indicates */
3639 *current_group = *map_index / map->data_disks_per_row;
3640 if (offload_to_mirror == *current_group)
3641 continue;
3642 if (*current_group < (map->layout_map_count - 1)) {
3643 /* select map index from next group */
3644 *map_index += map->data_disks_per_row;
3645 (*current_group)++;
3646 } else {
3647 /* select map index from first group */
3648 *map_index %= map->data_disks_per_row;
3649 *current_group = 0;
3650 }
3651 } while (offload_to_mirror != *current_group);
3652}
3653
283b4a9b
SC		 3654/*
3655 * Attempt to perform offload RAID mapping for a logical volume I/O.
3656 */
3657static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3658 struct CommandList *c)
3659{
3660 struct scsi_cmnd *cmd = c->scsi_cmd;
3661 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3662 struct raid_map_data *map = &dev->raid_map;
3663 struct raid_map_disk_data *dd = &map->data[0];
3664 int is_write = 0;
3665 u32 map_index;
3666 u64 first_block, last_block;
3667 u32 block_cnt;
3668 u32 blocks_per_row;
3669 u64 first_row, last_row;
3670 u32 first_row_offset, last_row_offset;
3671 u32 first_column, last_column;
6b80b18f
ST		 3672 u64 r0_first_row, r0_last_row;
3673 u32 r5or6_blocks_per_row;
3674 u64 r5or6_first_row, r5or6_last_row;
3675 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3676 u32 r5or6_first_column, r5or6_last_column;
3677 u32 total_disks_per_row;
3678 u32 stripesize;
3679 u32 first_group, last_group, current_group;
283b4a9b
SC		 3680 u32 map_row;
3681 u32 disk_handle;
3682 u64 disk_block;
3683 u32 disk_block_cnt;
3684 u8 cdb[16];
3685 u8 cdb_len;
3686#if BITS_PER_LONG == 32
3687 u64 tmpdiv;
3688#endif
6b80b18f 3689 int offload_to_mirror;
283b4a9b
SC		 3690
3691 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3692
3693 /* check for valid opcode, get LBA and block count */
3694 switch (cmd->cmnd[0]) {
3695 case WRITE_6:
3696 is_write = 1;
3697 case READ_6:
3698 first_block =
3699 (((u64) cmd->cmnd[2]) << 8) |
3700 cmd->cmnd[3];
3701 block_cnt = cmd->cmnd[4];
3702 break;
3703 case WRITE_10:
3704 is_write = 1;
3705 case READ_10:
3706 first_block =
3707 (((u64) cmd->cmnd[2]) << 24) |
3708 (((u64) cmd->cmnd[3]) << 16) |
3709 (((u64) cmd->cmnd[4]) << 8) |
3710 cmd->cmnd[5];
3711 block_cnt =
3712 (((u32) cmd->cmnd[7]) << 8) |
3713 cmd->cmnd[8];
3714 break;
3715 case WRITE_12:
3716 is_write = 1;
3717 case READ_12:
3718 first_block =
3719 (((u64) cmd->cmnd[2]) << 24) |
3720 (((u64) cmd->cmnd[3]) << 16) |
3721 (((u64) cmd->cmnd[4]) << 8) |
3722 cmd->cmnd[5];
3723 block_cnt =
3724 (((u32) cmd->cmnd[6]) << 24) |
3725 (((u32) cmd->cmnd[7]) << 16) |
3726 (((u32) cmd->cmnd[8]) << 8) |
3727 cmd->cmnd[9];
3728 break;
3729 case WRITE_16:
3730 is_write = 1;
3731 case READ_16:
3732 first_block =
3733 (((u64) cmd->cmnd[2]) << 56) |
3734 (((u64) cmd->cmnd[3]) << 48) |
3735 (((u64) cmd->cmnd[4]) << 40) |
3736 (((u64) cmd->cmnd[5]) << 32) |
3737 (((u64) cmd->cmnd[6]) << 24) |
3738 (((u64) cmd->cmnd[7]) << 16) |
3739 (((u64) cmd->cmnd[8]) << 8) |
3740 cmd->cmnd[9];
3741 block_cnt =
3742 (((u32) cmd->cmnd[10]) << 24) |
3743 (((u32) cmd->cmnd[11]) << 16) |
3744 (((u32) cmd->cmnd[12]) << 8) |
3745 cmd->cmnd[13];
3746 break;
3747 default:
3748 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3749 }
3750 BUG_ON(block_cnt == 0);
3751 last_block = first_block + block_cnt - 1;
3752
3753 /* check for write to non-RAID-0 */
3754 if (is_write && dev->raid_level != 0)
3755 return IO_ACCEL_INELIGIBLE;
3756
3757 /* check for invalid block or wraparound */
3758 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3759 return IO_ACCEL_INELIGIBLE;
3760
3761 /* calculate stripe information for the request */
3762 blocks_per_row = map->data_disks_per_row * map->strip_size;
3763#if BITS_PER_LONG == 32
3764 tmpdiv = first_block;
3765 (void) do_div(tmpdiv, blocks_per_row);
3766 first_row = tmpdiv;
3767 tmpdiv = last_block;
3768 (void) do_div(tmpdiv, blocks_per_row);
3769 last_row = tmpdiv;
3770 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3771 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3772 tmpdiv = first_row_offset;
3773 (void) do_div(tmpdiv, map->strip_size);
3774 first_column = tmpdiv;
3775 tmpdiv = last_row_offset;
3776 (void) do_div(tmpdiv, map->strip_size);
3777 last_column = tmpdiv;
3778#else
3779 first_row = first_block / blocks_per_row;
3780 last_row = last_block / blocks_per_row;
3781 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3782 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3783 first_column = first_row_offset / map->strip_size;
3784 last_column = last_row_offset / map->strip_size;
3785#endif
3786
3787 /* if this isn't a single row/column then give to the controller */
3788 if ((first_row != last_row) || (first_column != last_column))
3789 return IO_ACCEL_INELIGIBLE;
3790
3791 /* proceeding with driver mapping */
6b80b18f
ST		 3792 total_disks_per_row = map->data_disks_per_row +
3793 map->metadata_disks_per_row;
283b4a9b
SC		 3794 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3795 map->row_cnt;
6b80b18f
ST		 3796 map_index = (map_row * total_disks_per_row) + first_column;
3797
3798 switch (dev->raid_level) {
3799 case HPSA_RAID_0:
3800 break; /* nothing special to do */
3801 case HPSA_RAID_1:
3802 /* Handles load balance across RAID 1 members.
3803 * (2-drive R1 and R10 with even # of drives.)
3804 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3805 */
6b80b18f 3806 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3807 if (dev->offload_to_mirror)
3808 map_index += map->data_disks_per_row;
3809 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3810 break;
3811 case HPSA_RAID_ADM:
3812 /* Handles N-way mirrors (R1-ADM)
3813 * and R10 with # of drives divisible by 3.)
3814 */
3815 BUG_ON(map->layout_map_count != 3);
3816
3817 offload_to_mirror = dev->offload_to_mirror;
3818 raid_map_helper(map, offload_to_mirror,
3819 &map_index, &current_group);
3820 /* set mirror group to use next time */
3821 offload_to_mirror =
3822 (offload_to_mirror >= map->layout_map_count - 1)
3823 ? 0 : offload_to_mirror + 1;
3824 /* FIXME: remove after debug/dev */
3825 BUG_ON(offload_to_mirror >= map->layout_map_count);
3826 dev_warn(&h->pdev->dev,
3827 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3828 map_index, offload_to_mirror);
3829 dev->offload_to_mirror = offload_to_mirror;
3830 /* Avoid direct use of dev->offload_to_mirror within this
3831 * function since multiple threads might simultaneously
3832 * increment it beyond the range of dev->layout_map_count -1.
3833 */
3834 break;
3835 case HPSA_RAID_5:
3836 case HPSA_RAID_6:
3837 if (map->layout_map_count <= 1)
3838 break;
3839
3840 /* Verify first and last block are in same RAID group */
3841 r5or6_blocks_per_row =
3842 map->strip_size * map->data_disks_per_row;
3843 BUG_ON(r5or6_blocks_per_row == 0);
3844 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3845#if BITS_PER_LONG == 32
3846 tmpdiv = first_block;
3847 first_group = do_div(tmpdiv, stripesize);
3848 tmpdiv = first_group;
3849 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3850 first_group = tmpdiv;
3851 tmpdiv = last_block;
3852 last_group = do_div(tmpdiv, stripesize);
3853 tmpdiv = last_group;
3854 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3855 last_group = tmpdiv;
3856#else
3857 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3858 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3859#endif
000ff7c2 3860 if (first_group != last_group)
6b80b18f
ST		 3861 return IO_ACCEL_INELIGIBLE;
3862
3863 /* Verify request is in a single row of RAID 5/6 */
3864#if BITS_PER_LONG == 32
3865 tmpdiv = first_block;
3866 (void) do_div(tmpdiv, stripesize);
3867 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3868 tmpdiv = last_block;
3869 (void) do_div(tmpdiv, stripesize);
3870 r5or6_last_row = r0_last_row = tmpdiv;
3871#else
3872 first_row = r5or6_first_row = r0_first_row =
3873 first_block / stripesize;
3874 r5or6_last_row = r0_last_row = last_block / stripesize;
3875#endif
3876 if (r5or6_first_row != r5or6_last_row)
3877 return IO_ACCEL_INELIGIBLE;
3878
3879
3880 /* Verify request is in a single column */
3881#if BITS_PER_LONG == 32
3882 tmpdiv = first_block;
3883 first_row_offset = do_div(tmpdiv, stripesize);
3884 tmpdiv = first_row_offset;
3885 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3886 r5or6_first_row_offset = first_row_offset;
3887 tmpdiv = last_block;
3888 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3889 tmpdiv = r5or6_last_row_offset;
3890 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3891 tmpdiv = r5or6_first_row_offset;
3892 (void) do_div(tmpdiv, map->strip_size);
3893 first_column = r5or6_first_column = tmpdiv;
3894 tmpdiv = r5or6_last_row_offset;
3895 (void) do_div(tmpdiv, map->strip_size);
3896 r5or6_last_column = tmpdiv;
3897#else
3898 first_row_offset = r5or6_first_row_offset =
3899 (u32)((first_block % stripesize) %
3900 r5or6_blocks_per_row);
3901
3902 r5or6_last_row_offset =
3903 (u32)((last_block % stripesize) %
3904 r5or6_blocks_per_row);
3905
3906 first_column = r5or6_first_column =
3907 r5or6_first_row_offset / map->strip_size;
3908 r5or6_last_column =
3909 r5or6_last_row_offset / map->strip_size;
3910#endif
3911 if (r5or6_first_column != r5or6_last_column)
3912 return IO_ACCEL_INELIGIBLE;
3913
3914 /* Request is eligible */
3915 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3916 map->row_cnt;
3917
3918 map_index = (first_group *
3919 (map->row_cnt * total_disks_per_row)) +
3920 (map_row * total_disks_per_row) + first_column;
3921 break;
3922 default:
3923 return IO_ACCEL_INELIGIBLE;
283b4a9b 3924 }
6b80b18f 3925
283b4a9b
SC		 3926 disk_handle = dd[map_index].ioaccel_handle;
3927 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3928 (first_row_offset - (first_column * map->strip_size));
3929 disk_block_cnt = block_cnt;
3930
3931 /* handle differing logical/physical block sizes */
3932 if (map->phys_blk_shift) {
3933 disk_block <<= map->phys_blk_shift;
3934 disk_block_cnt <<= map->phys_blk_shift;
3935 }
3936 BUG_ON(disk_block_cnt > 0xffff);
3937
3938 /* build the new CDB for the physical disk I/O */
3939 if (disk_block > 0xffffffff) {
3940 cdb[0] = is_write ? WRITE_16 : READ_16;
3941 cdb[1] = 0;
3942 cdb[2] = (u8) (disk_block >> 56);
3943 cdb[3] = (u8) (disk_block >> 48);
3944 cdb[4] = (u8) (disk_block >> 40);
3945 cdb[5] = (u8) (disk_block >> 32);
3946 cdb[6] = (u8) (disk_block >> 24);
3947 cdb[7] = (u8) (disk_block >> 16);
3948 cdb[8] = (u8) (disk_block >> 8);
3949 cdb[9] = (u8) (disk_block);
3950 cdb[10] = (u8) (disk_block_cnt >> 24);
3951 cdb[11] = (u8) (disk_block_cnt >> 16);
3952 cdb[12] = (u8) (disk_block_cnt >> 8);
3953 cdb[13] = (u8) (disk_block_cnt);
3954 cdb[14] = 0;
3955 cdb[15] = 0;
3956 cdb_len = 16;
3957 } else {
3958 cdb[0] = is_write ? WRITE_10 : READ_10;
3959 cdb[1] = 0;
3960 cdb[2] = (u8) (disk_block >> 24);
3961 cdb[3] = (u8) (disk_block >> 16);
3962 cdb[4] = (u8) (disk_block >> 8);
3963 cdb[5] = (u8) (disk_block);
3964 cdb[6] = 0;
3965 cdb[7] = (u8) (disk_block_cnt >> 8);
3966 cdb[8] = (u8) (disk_block_cnt);
3967 cdb[9] = 0;
3968 cdb_len = 10;
3969 }
3970 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3971 dev->scsi3addr);
3972}
3973
f281233d 3974static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3975 void (*done)(struct scsi_cmnd *))
3976{
3977 struct ctlr_info *h;
3978 struct hpsa_scsi_dev_t *dev;
3979 unsigned char scsi3addr[8];
3980 struct CommandList *c;
283b4a9b 3981 int rc = 0;
edd16368
SC		 3982
3983 /* Get the ptr to our adapter structure out of cmd->host. */
3984 h = sdev_to_hba(cmd->device);
3985 dev = cmd->device->hostdata;
3986 if (!dev) {
3987 cmd->result = DID_NO_CONNECT << 16;
3988 done(cmd);
3989 return 0;
3990 }
3991 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3992
094963da 3993 if (unlikely(lockup_detected(h))) {
a0c12413
SC		 3994 cmd->result = DID_ERROR << 16;
3995 done(cmd);
3996 return 0;
3997 }
e16a33ad 3998 c = cmd_alloc(h);
edd16368
SC		 3999 if (c == NULL) { /* trouble... */
4000 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4001 return SCSI_MLQUEUE_HOST_BUSY;
4002 }
4003
4004 /* Fill in the command list header */
4005
4006 cmd->scsi_done = done; /* save this for use by completion code */
4007
4008 /* save c in case we have to abort it */
4009 cmd->host_scribble = (unsigned char *) c;
4010
4011 c->cmd_type = CMD_SCSI;
4012 c->scsi_cmd = cmd;
e1f7de0c 4013
283b4a9b
SC		 4014 /* Call alternate submit routine for I/O accelerated commands.
4015 * Retries always go down the normal I/O path.
4016 */
4017 if (likely(cmd->retries == 0 &&
da0697bd
ST		 4018 cmd->request->cmd_type == REQ_TYPE_FS &&
4019 h->acciopath_status)) {
283b4a9b
SC		 4020 if (dev->offload_enabled) {
4021 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4022 if (rc == 0)
4023 return 0; /* Sent on ioaccel path */
4024 if (rc < 0) { /* scsi_dma_map failed. */
4025 cmd_free(h, c);
4026 return SCSI_MLQUEUE_HOST_BUSY;
4027 }
4028 } else if (dev->ioaccel_handle) {
4029 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4030 if (rc == 0)
4031 return 0; /* Sent on direct map path */
4032 if (rc < 0) { /* scsi_dma_map failed. */
4033 cmd_free(h, c);
4034 return SCSI_MLQUEUE_HOST_BUSY;
4035 }
4036 }
4037 }
e1f7de0c 4038
edd16368
SC		 4039 c->Header.ReplyQueue = 0; /* unused in simple mode */
4040 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 4041 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
4042 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 4043
4044 /* Fill in the request block... */
4045
4046 c->Request.Timeout = 0;
4047 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4048 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4049 c->Request.CDBLen = cmd->cmd_len;
4050 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
4051 c->Request.Type.Type = TYPE_CMD;
4052 c->Request.Type.Attribute = ATTR_SIMPLE;
4053 switch (cmd->sc_data_direction) {
4054 case DMA_TO_DEVICE:
4055 c->Request.Type.Direction = XFER_WRITE;
4056 break;
4057 case DMA_FROM_DEVICE:
4058 c->Request.Type.Direction = XFER_READ;
4059 break;
4060 case DMA_NONE:
4061 c->Request.Type.Direction = XFER_NONE;
4062 break;
4063 case DMA_BIDIRECTIONAL:
4064 /* This can happen if a buggy application does a scsi passthru
4065 * and sets both inlen and outlen to non-zero. ( see
4066 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4067 */
4068
4069 c->Request.Type.Direction = XFER_RSVD;
4070 /* This is technically wrong, and hpsa controllers should
4071 * reject it with CMD_INVALID, which is the most correct
4072 * response, but non-fibre backends appear to let it
4073 * slide by, and give the same results as if this field
4074 * were set correctly. Either way is acceptable for
4075 * our purposes here.
4076 */
4077
4078 break;
4079
4080 default:
4081 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4082 cmd->sc_data_direction);
4083 BUG();
4084 break;
4085 }
4086
33a2ffce 4087 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4088 cmd_free(h, c);
4089 return SCSI_MLQUEUE_HOST_BUSY;
4090 }
4091 enqueue_cmd_and_start_io(h, c);
4092 /* the cmd'll come back via intr handler in complete_scsi_command() */
4093 return 0;
4094}
4095
f281233d
JG		 4096static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
4097
5f389360
SC		 4098static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4099{
4100 unsigned long flags;
4101
4102 /*
4103 * Don't let rescans be initiated on a controller known
4104 * to be locked up. If the controller locks up *during*
4105 * a rescan, that thread is probably hosed, but at least
4106 * we can prevent new rescan threads from piling up on a
4107 * locked up controller.
4108 */
094963da 4109 if (unlikely(lockup_detected(h))) {
5f389360
SC		 4110 spin_lock_irqsave(&h->scan_lock, flags);
4111 h->scan_finished = 1;
4112 wake_up_all(&h->scan_wait_queue);
4113 spin_unlock_irqrestore(&h->scan_lock, flags);
4114 return 1;
4115 }
5f389360
SC		 4116 return 0;
4117}
4118
a08a8471
SC		 4119static void hpsa_scan_start(struct Scsi_Host *sh)
4120{
4121 struct ctlr_info *h = shost_to_hba(sh);
4122 unsigned long flags;
4123
5f389360
SC		 4124 if (do_not_scan_if_controller_locked_up(h))
4125 return;
4126
a08a8471
SC		 4127 /* wait until any scan already in progress is finished. */
4128 while (1) {
4129 spin_lock_irqsave(&h->scan_lock, flags);
4130 if (h->scan_finished)
4131 break;
4132 spin_unlock_irqrestore(&h->scan_lock, flags);
4133 wait_event(h->scan_wait_queue, h->scan_finished);
4134 /* Note: We don't need to worry about a race between this
4135 * thread and driver unload because the midlayer will
4136 * have incremented the reference count, so unload won't
4137 * happen if we're in here.
4138 */
4139 }
4140 h->scan_finished = 0; /* mark scan as in progress */
4141 spin_unlock_irqrestore(&h->scan_lock, flags);
4142
5f389360
SC		 4143 if (do_not_scan_if_controller_locked_up(h))
4144 return;
4145
a08a8471
SC		 4146 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4147
4148 spin_lock_irqsave(&h->scan_lock, flags);
4149 h->scan_finished = 1; /* mark scan as finished. */
4150 wake_up_all(&h->scan_wait_queue);
4151 spin_unlock_irqrestore(&h->scan_lock, flags);
4152}
4153
4154static int hpsa_scan_finished(struct Scsi_Host *sh,
4155 unsigned long elapsed_time)
4156{
4157 struct ctlr_info *h = shost_to_hba(sh);
4158 unsigned long flags;
4159 int finished;
4160
4161 spin_lock_irqsave(&h->scan_lock, flags);
4162 finished = h->scan_finished;
4163 spin_unlock_irqrestore(&h->scan_lock, flags);
4164 return finished;
4165}
4166
667e23d4
SC		 4167static int hpsa_change_queue_depth(struct scsi_device *sdev,
4168 int qdepth, int reason)
4169{
4170 struct ctlr_info *h = sdev_to_hba(sdev);
4171
4172 if (reason != SCSI_QDEPTH_DEFAULT)
4173 return -ENOTSUPP;
4174
4175 if (qdepth < 1)
4176 qdepth = 1;
4177 else
4178 if (qdepth > h->nr_cmds)
4179 qdepth = h->nr_cmds;
4180 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4181 return sdev->queue_depth;
4182}
4183
edd16368
SC		 4184static void hpsa_unregister_scsi(struct ctlr_info *h)
4185{
4186 /* we are being forcibly unloaded, and may not refuse. */
4187 scsi_remove_host(h->scsi_host);
4188 scsi_host_put(h->scsi_host);
4189 h->scsi_host = NULL;
4190}
4191
4192static int hpsa_register_scsi(struct ctlr_info *h)
4193{
b705690d
SC		 4194 struct Scsi_Host *sh;
4195 int error;
edd16368 4196
b705690d
SC		 4197 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4198 if (sh == NULL)
4199 goto fail;
4200
4201 sh->io_port = 0;
4202 sh->n_io_port = 0;
4203 sh->this_id = -1;
4204 sh->max_channel = 3;
4205 sh->max_cmd_len = MAX_COMMAND_SIZE;
4206 sh->max_lun = HPSA_MAX_LUN;
4207 sh->max_id = HPSA_MAX_LUN;
4208 sh->can_queue = h->nr_cmds;
316b221a
SC		 4209 if (h->hba_mode_enabled)
4210 sh->cmd_per_lun = 7;
4211 else
4212 sh->cmd_per_lun = h->nr_cmds;
b705690d
SC		 4213 sh->sg_tablesize = h->maxsgentries;
4214 h->scsi_host = sh;
4215 sh->hostdata[0] = (unsigned long) h;
4216 sh->irq = h->intr[h->intr_mode];
4217 sh->unique_id = sh->irq;
4218 error = scsi_add_host(sh, &h->pdev->dev);
4219 if (error)
4220 goto fail_host_put;
4221 scsi_scan_host(sh);
4222 return 0;
4223
4224 fail_host_put:
4225 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4226 " failed for controller %d\n", __func__, h->ctlr);
4227 scsi_host_put(sh);
4228 return error;
4229 fail:
4230 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4231 " failed for controller %d\n", __func__, h->ctlr);
4232 return -ENOMEM;
edd16368
SC		 4233}
4234
4235static int wait_for_device_to_become_ready(struct ctlr_info *h,
4236 unsigned char lunaddr[])
4237{
8919358e 4238 int rc;
edd16368
SC		 4239 int count = 0;
4240 int waittime = 1; /* seconds */
4241 struct CommandList *c;
4242
4243 c = cmd_special_alloc(h);
4244 if (!c) {
4245 dev_warn(&h->pdev->dev, "out of memory in "
4246 "wait_for_device_to_become_ready.\n");
4247 return IO_ERROR;
4248 }
4249
4250 /* Send test unit ready until device ready, or give up. */
4251 while (count < HPSA_TUR_RETRY_LIMIT) {
4252
4253 /* Wait for a bit. do this first, because if we send
4254 * the TUR right away, the reset will just abort it.
4255 */
4256 msleep(1000 * waittime);
4257 count++;
8919358e 4258 rc = 0; /* Device ready. */
edd16368
SC		 4259
4260 /* Increase wait time with each try, up to a point. */
4261 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4262 waittime = waittime * 2;
4263
a2dac136
SC		 4264 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4265 (void) fill_cmd(c, TEST_UNIT_READY, h,
4266 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4267 hpsa_scsi_do_simple_cmd_core(h, c);
4268 /* no unmap needed here because no data xfer. */
4269
4270 if (c->err_info->CommandStatus == CMD_SUCCESS)
4271 break;
4272
4273 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4274 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4275 (c->err_info->SenseInfo[2] == NO_SENSE ||
4276 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4277 break;
4278
4279 dev_warn(&h->pdev->dev, "waiting %d secs "
4280 "for device to become ready.\n", waittime);
4281 rc = 1; /* device not ready. */
4282 }
4283
4284 if (rc)
4285 dev_warn(&h->pdev->dev, "giving up on device.\n");
4286 else
4287 dev_warn(&h->pdev->dev, "device is ready.\n");
4288
4289 cmd_special_free(h, c);
4290 return rc;
4291}
4292
4293/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4294 * complaining. Doing a host- or bus-reset can't do anything good here.
4295 */
4296static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4297{
4298 int rc;
4299 struct ctlr_info *h;
4300 struct hpsa_scsi_dev_t *dev;
4301
4302 /* find the controller to which the command to be aborted was sent */
4303 h = sdev_to_hba(scsicmd->device);
4304 if (h == NULL) /* paranoia */
4305 return FAILED;
edd16368
SC		 4306 dev = scsicmd->device->hostdata;
4307 if (!dev) {
4308 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4309 "device lookup failed.\n");
4310 return FAILED;
4311 }
d416b0c7
SC		 4312 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4313 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4314 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4315 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4316 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4317 return SUCCESS;
4318
4319 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4320 return FAILED;
4321}
4322
6cba3f19
SC		 4323static void swizzle_abort_tag(u8 *tag)
4324{
4325 u8 original_tag[8];
4326
4327 memcpy(original_tag, tag, 8);
4328 tag[0] = original_tag[3];
4329 tag[1] = original_tag[2];
4330 tag[2] = original_tag[1];
4331 tag[3] = original_tag[0];
4332 tag[4] = original_tag[7];
4333 tag[5] = original_tag[6];
4334 tag[6] = original_tag[5];
4335 tag[7] = original_tag[4];
4336}
4337
17eb87d2
ST		 4338static void hpsa_get_tag(struct ctlr_info *h,
4339 struct CommandList *c, u32 *taglower, u32 *tagupper)
4340{
4341 if (c->cmd_type == CMD_IOACCEL1) {
4342 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4343 &h->ioaccel_cmd_pool[c->cmdindex];
4344 *tagupper = cm1->Tag.upper;
4345 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4346 return;
4347 }
4348 if (c->cmd_type == CMD_IOACCEL2) {
4349 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4350 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4351 /* upper tag not used in ioaccel2 mode */
4352 memset(tagupper, 0, sizeof(*tagupper));
4353 *taglower = cm2->Tag;
54b6e9e9 4354 return;
17eb87d2 4355 }
54b6e9e9
ST		 4356 *tagupper = c->Header.Tag.upper;
4357 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4358}
4359
54b6e9e9 4360
75167d2c 4361static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4362 struct CommandList *abort, int swizzle)
75167d2c
SC		 4363{
4364 int rc = IO_OK;
4365 struct CommandList *c;
4366 struct ErrorInfo *ei;
17eb87d2 4367 u32 tagupper, taglower;
75167d2c
SC		 4368
4369 c = cmd_special_alloc(h);
4370 if (c == NULL) { /* trouble... */
4371 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4372 return -ENOMEM;
4373 }
4374
a2dac136
SC		 4375 /* fill_cmd can't fail here, no buffer to map */
4376 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4377 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4378 if (swizzle)
4379 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4380 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4381 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4382 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4383 __func__, tagupper, taglower);
75167d2c
SC		 4384 /* no unmap needed here because no data xfer. */
4385
4386 ei = c->err_info;
4387 switch (ei->CommandStatus) {
4388 case CMD_SUCCESS:
4389 break;
4390 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4391 rc = -1;
4392 break;
4393 default:
4394 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4395 __func__, tagupper, taglower);
d1e8beac 4396 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4397 rc = -1;
4398 break;
4399 }
4400 cmd_special_free(h, c);
dd0e19f3
ST		 4401 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4402 __func__, tagupper, taglower);
75167d2c
SC		 4403 return rc;
4404}
4405
4406/*
4407 * hpsa_find_cmd_in_queue
4408 *
4409 * Used to determine whether a command (find) is still present
4410 * in queue_head. Optionally excludes the last element of queue_head.
4411 *
4412 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4413 * not yet been submitted, and so can be aborted by the driver without
4414 * sending an abort to the hardware.
4415 *
4416 * Returns pointer to command if found in queue, NULL otherwise.
4417 */
4418static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4419 struct scsi_cmnd *find, struct list_head *queue_head)
4420{
4421 unsigned long flags;
4422 struct CommandList *c = NULL; /* ptr into cmpQ */
4423
4424 if (!find)
4425 return 0;
4426 spin_lock_irqsave(&h->lock, flags);
4427 list_for_each_entry(c, queue_head, list) {
4428 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4429 continue;
4430 if (c->scsi_cmd == find) {
4431 spin_unlock_irqrestore(&h->lock, flags);
4432 return c;
4433 }
4434 }
4435 spin_unlock_irqrestore(&h->lock, flags);
4436 return NULL;
4437}
4438
6cba3f19
SC		 4439static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4440 u8 *tag, struct list_head *queue_head)
4441{
4442 unsigned long flags;
4443 struct CommandList *c;
4444
4445 spin_lock_irqsave(&h->lock, flags);
4446 list_for_each_entry(c, queue_head, list) {
4447 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4448 continue;
4449 spin_unlock_irqrestore(&h->lock, flags);
4450 return c;
4451 }
4452 spin_unlock_irqrestore(&h->lock, flags);
4453 return NULL;
4454}
4455
54b6e9e9
ST		 4456/* ioaccel2 path firmware cannot handle abort task requests.
4457 * Change abort requests to physical target reset, and send to the
4458 * address of the physical disk used for the ioaccel 2 command.
4459 * Return 0 on success (IO_OK)
4460 * -1 on failure
4461 */
4462
4463static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4464 unsigned char *scsi3addr, struct CommandList *abort)
4465{
4466 int rc = IO_OK;
4467 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4468 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4469 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4470 unsigned char *psa = &phys_scsi3addr[0];
4471
4472 /* Get a pointer to the hpsa logical device. */
4473 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4474 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4475 if (dev == NULL) {
4476 dev_warn(&h->pdev->dev,
4477 "Cannot abort: no device pointer for command.\n");
4478 return -1; /* not abortable */
4479 }
4480
2ba8bfc8
SC		 4481 if (h->raid_offload_debug > 0)
4482 dev_info(&h->pdev->dev,
4483 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4484 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4485 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4486 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4487
54b6e9e9
ST		 4488 if (!dev->offload_enabled) {
4489 dev_warn(&h->pdev->dev,
4490 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4491 return -1; /* not abortable */
4492 }
4493
4494 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4495 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4496 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4497 return -1; /* not abortable */
4498 }
4499
4500 /* send the reset */
2ba8bfc8
SC		 4501 if (h->raid_offload_debug > 0)
4502 dev_info(&h->pdev->dev,
4503 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4504 psa[0], psa[1], psa[2], psa[3],
4505 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4506 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4507 if (rc != 0) {
4508 dev_warn(&h->pdev->dev,
4509 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4510 psa[0], psa[1], psa[2], psa[3],
4511 psa[4], psa[5], psa[6], psa[7]);
4512 return rc; /* failed to reset */
4513 }
4514
4515 /* wait for device to recover */
4516 if (wait_for_device_to_become_ready(h, psa) != 0) {
4517 dev_warn(&h->pdev->dev,
4518 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4519 psa[0], psa[1], psa[2], psa[3],
4520 psa[4], psa[5], psa[6], psa[7]);
4521 return -1; /* failed to recover */
4522 }
4523
4524 /* device recovered */
4525 dev_info(&h->pdev->dev,
4526 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4527 psa[0], psa[1], psa[2], psa[3],
4528 psa[4], psa[5], psa[6], psa[7]);
4529
4530 return rc; /* success */
4531}
4532
6cba3f19
SC		 4533/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4534 * tell which kind we're dealing with, so we send the abort both ways. There
4535 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4536 * way we construct our tags but we check anyway in case the assumptions which
4537 * make this true someday become false.
4538 */
4539static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4540 unsigned char *scsi3addr, struct CommandList *abort)
4541{
4542 u8 swizzled_tag[8];
4543 struct CommandList *c;
4544 int rc = 0, rc2 = 0;
4545
54b6e9e9
ST		 4546 /* ioccelerator mode 2 commands should be aborted via the
4547 * accelerated path, since RAID path is unaware of these commands,
4548 * but underlying firmware can't handle abort TMF.
4549 * Change abort to physical device reset.
4550 */
4551 if (abort->cmd_type == CMD_IOACCEL2)
4552 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4553
6cba3f19
SC		 4554 /* we do not expect to find the swizzled tag in our queue, but
4555 * check anyway just to be sure the assumptions which make this
4556 * the case haven't become wrong.
4557 */
4558 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4559 swizzle_abort_tag(swizzled_tag);
4560 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4561 if (c != NULL) {
4562 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4563 return hpsa_send_abort(h, scsi3addr, abort, 0);
4564 }
4565 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4566
4567 /* if the command is still in our queue, we can't conclude that it was
4568 * aborted (it might have just completed normally) but in any case
4569 * we don't need to try to abort it another way.
4570 */
4571 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4572 if (c)
4573 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4574 return rc && rc2;
4575}
4576
75167d2c
SC		 4577/* Send an abort for the specified command.
4578 * If the device and controller support it,
4579 * send a task abort request.
4580 */
4581static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4582{
4583
4584 int i, rc;
4585 struct ctlr_info *h;
4586 struct hpsa_scsi_dev_t *dev;
4587 struct CommandList *abort; /* pointer to command to be aborted */
4588 struct CommandList *found;
4589 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4590 char msg[256]; /* For debug messaging. */
4591 int ml = 0;
17eb87d2 4592 u32 tagupper, taglower;
75167d2c
SC		 4593
4594 /* Find the controller of the command to be aborted */
4595 h = sdev_to_hba(sc->device);
4596 if (WARN(h == NULL,
4597 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4598 return FAILED;
4599
4600 /* Check that controller supports some kind of task abort */
4601 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4602 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4603 return FAILED;
4604
4605 memset(msg, 0, sizeof(msg));
4606 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4607 h->scsi_host->host_no, sc->device->channel,
4608 sc->device->id, sc->device->lun);
4609
4610 /* Find the device of the command to be aborted */
4611 dev = sc->device->hostdata;
4612 if (!dev) {
4613 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4614 msg);
4615 return FAILED;
4616 }
4617
4618 /* Get SCSI command to be aborted */
4619 abort = (struct CommandList *) sc->host_scribble;
4620 if (abort == NULL) {
4621 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4622 msg);
4623 return FAILED;
4624 }
17eb87d2
ST		 4625 hpsa_get_tag(h, abort, &taglower, &tagupper);
4626 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4627 as = (struct scsi_cmnd *) abort->scsi_cmd;
4628 if (as != NULL)
4629 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4630 as->cmnd[0], as->serial_number);
4631 dev_dbg(&h->pdev->dev, "%s\n", msg);
4632 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4633 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4634
4635 /* Search reqQ to See if command is queued but not submitted,
4636 * if so, complete the command with aborted status and remove
4637 * it from the reqQ.
4638 */
4639 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4640 if (found) {
4641 found->err_info->CommandStatus = CMD_ABORTED;
4642 finish_cmd(found);
4643 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4644 msg);
4645 return SUCCESS;
4646 }
4647
4648 /* not in reqQ, if also not in cmpQ, must have already completed */
4649 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4650 if (!found) {
d6ebd0f7 4651 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4652 msg);
4653 return SUCCESS;
4654 }
4655
4656 /*
4657 * Command is in flight, or possibly already completed
4658 * by the firmware (but not to the scsi mid layer) but we can't
4659 * distinguish which. Send the abort down.
4660 */
6cba3f19 4661 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4662 if (rc != 0) {
4663 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4664 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4665 h->scsi_host->host_no,
4666 dev->bus, dev->target, dev->lun);
4667 return FAILED;
4668 }
4669 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4670
4671 /* If the abort(s) above completed and actually aborted the
4672 * command, then the command to be aborted should already be
4673 * completed. If not, wait around a bit more to see if they
4674 * manage to complete normally.
4675 */
4676#define ABORT_COMPLETE_WAIT_SECS 30
4677 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4678 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4679 if (!found)
4680 return SUCCESS;
4681 msleep(100);
4682 }
4683 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4684 msg, ABORT_COMPLETE_WAIT_SECS);
4685 return FAILED;
4686}
4687
4688
edd16368
SC		 4689/*
4690 * For operations that cannot sleep, a command block is allocated at init,
4691 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4692 * which ones are free or in use. Lock must be held when calling this.
4693 * cmd_free() is the complement.
4694 */
4695static struct CommandList *cmd_alloc(struct ctlr_info *h)
4696{
4697 struct CommandList *c;
4698 int i;
4699 union u64bit temp64;
4700 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4701 unsigned long flags;
edd16368 4702
e16a33ad 4703 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4704 do {
4705 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4706 if (i == h->nr_cmds) {
4707 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4708 return NULL;
e16a33ad 4709 }
edd16368
SC		 4710 } while (test_and_set_bit
4711 (i & (BITS_PER_LONG - 1),
4712 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4713 spin_unlock_irqrestore(&h->lock, flags);
4714
edd16368
SC		 4715 c = h->cmd_pool + i;
4716 memset(c, 0, sizeof(*c));
4717 cmd_dma_handle = h->cmd_pool_dhandle
4718 + i * sizeof(*c);
4719 c->err_info = h->errinfo_pool + i;
4720 memset(c->err_info, 0, sizeof(*c->err_info));
4721 err_dma_handle = h->errinfo_pool_dhandle
4722 + i * sizeof(*c->err_info);
edd16368
SC		 4723
4724 c->cmdindex = i;
4725
9e0fc764 4726 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4727 c->busaddr = (u32) cmd_dma_handle;
4728 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4729 c->ErrDesc.Addr.lower = temp64.val32.lower;
4730 c->ErrDesc.Addr.upper = temp64.val32.upper;
4731 c->ErrDesc.Len = sizeof(*c->err_info);
4732
4733 c->h = h;
4734 return c;
4735}
4736
4737/* For operations that can wait for kmalloc to possibly sleep,
4738 * this routine can be called. Lock need not be held to call
4739 * cmd_special_alloc. cmd_special_free() is the complement.
4740 */
4741static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4742{
4743 struct CommandList *c;
4744 union u64bit temp64;
4745 dma_addr_t cmd_dma_handle, err_dma_handle;
4746
4747 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4748 if (c == NULL)
4749 return NULL;
4750 memset(c, 0, sizeof(*c));
4751
e1f7de0c 4752 c->cmd_type = CMD_SCSI;
edd16368
SC		 4753 c->cmdindex = -1;
4754
4755 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4756 &err_dma_handle);
4757
4758 if (c->err_info == NULL) {
4759 pci_free_consistent(h->pdev,
4760 sizeof(*c), c, cmd_dma_handle);
4761 return NULL;
4762 }
4763 memset(c->err_info, 0, sizeof(*c->err_info));
4764
9e0fc764 4765 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4766 c->busaddr = (u32) cmd_dma_handle;
4767 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4768 c->ErrDesc.Addr.lower = temp64.val32.lower;
4769 c->ErrDesc.Addr.upper = temp64.val32.upper;
4770 c->ErrDesc.Len = sizeof(*c->err_info);
4771
4772 c->h = h;
4773 return c;
4774}
4775
4776static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4777{
4778 int i;
e16a33ad 4779 unsigned long flags;
edd16368
SC		 4780
4781 i = c - h->cmd_pool;
e16a33ad 4782 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4783 clear_bit(i & (BITS_PER_LONG - 1),
4784 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4785 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4786}
4787
4788static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4789{
4790 union u64bit temp64;
4791
4792 temp64.val32.lower = c->ErrDesc.Addr.lower;
4793 temp64.val32.upper = c->ErrDesc.Addr.upper;
4794 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4795 c->err_info, (dma_addr_t) temp64.val);
4796 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4797 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4798}
4799
4800#ifdef CONFIG_COMPAT
4801
edd16368
SC		 4802static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4803{
4804 IOCTL32_Command_struct __user *arg32 =
4805 (IOCTL32_Command_struct __user *) arg;
4806 IOCTL_Command_struct arg64;
4807 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4808 int err;
4809 u32 cp;
4810
938abd84 4811 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4812 err = 0;
4813 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4814 sizeof(arg64.LUN_info));
4815 err |= copy_from_user(&arg64.Request, &arg32->Request,
4816 sizeof(arg64.Request));
4817 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4818 sizeof(arg64.error_info));
4819 err |= get_user(arg64.buf_size, &arg32->buf_size);
4820 err |= get_user(cp, &arg32->buf);
4821 arg64.buf = compat_ptr(cp);
4822 err |= copy_to_user(p, &arg64, sizeof(arg64));
4823
4824 if (err)
4825 return -EFAULT;
4826
e39eeaed 4827 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4828 if (err)
4829 return err;
4830 err |= copy_in_user(&arg32->error_info, &p->error_info,
4831 sizeof(arg32->error_info));
4832 if (err)
4833 return -EFAULT;
4834 return err;
4835}
4836
4837static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4838 int cmd, void *arg)
4839{
4840 BIG_IOCTL32_Command_struct __user *arg32 =
4841 (BIG_IOCTL32_Command_struct __user *) arg;
4842 BIG_IOCTL_Command_struct arg64;
4843 BIG_IOCTL_Command_struct __user *p =
4844 compat_alloc_user_space(sizeof(arg64));
4845 int err;
4846 u32 cp;
4847
938abd84 4848 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4849 err = 0;
4850 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4851 sizeof(arg64.LUN_info));
4852 err |= copy_from_user(&arg64.Request, &arg32->Request,
4853 sizeof(arg64.Request));
4854 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4855 sizeof(arg64.error_info));
4856 err |= get_user(arg64.buf_size, &arg32->buf_size);
4857 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4858 err |= get_user(cp, &arg32->buf);
4859 arg64.buf = compat_ptr(cp);
4860 err |= copy_to_user(p, &arg64, sizeof(arg64));
4861
4862 if (err)
4863 return -EFAULT;
4864
e39eeaed 4865 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4866 if (err)
4867 return err;
4868 err |= copy_in_user(&arg32->error_info, &p->error_info,
4869 sizeof(arg32->error_info));
4870 if (err)
4871 return -EFAULT;
4872 return err;
4873}
71fe75a7
SC		 4874
4875static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4876{
4877 switch (cmd) {
4878 case CCISS_GETPCIINFO:
4879 case CCISS_GETINTINFO:
4880 case CCISS_SETINTINFO:
4881 case CCISS_GETNODENAME:
4882 case CCISS_SETNODENAME:
4883 case CCISS_GETHEARTBEAT:
4884 case CCISS_GETBUSTYPES:
4885 case CCISS_GETFIRMVER:
4886 case CCISS_GETDRIVVER:
4887 case CCISS_REVALIDVOLS:
4888 case CCISS_DEREGDISK:
4889 case CCISS_REGNEWDISK:
4890 case CCISS_REGNEWD:
4891 case CCISS_RESCANDISK:
4892 case CCISS_GETLUNINFO:
4893 return hpsa_ioctl(dev, cmd, arg);
4894
4895 case CCISS_PASSTHRU32:
4896 return hpsa_ioctl32_passthru(dev, cmd, arg);
4897 case CCISS_BIG_PASSTHRU32:
4898 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4899
4900 default:
4901 return -ENOIOCTLCMD;
4902 }
4903}
edd16368
SC		 4904#endif
4905
4906static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4907{
4908 struct hpsa_pci_info pciinfo;
4909
4910 if (!argp)
4911 return -EINVAL;
4912 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4913 pciinfo.bus = h->pdev->bus->number;
4914 pciinfo.dev_fn = h->pdev->devfn;
4915 pciinfo.board_id = h->board_id;
4916 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4917 return -EFAULT;
4918 return 0;
4919}
4920
4921static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4922{
4923 DriverVer_type DriverVer;
4924 unsigned char vmaj, vmin, vsubmin;
4925 int rc;
4926
4927 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4928 &vmaj, &vmin, &vsubmin);
4929 if (rc != 3) {
4930 dev_info(&h->pdev->dev, "driver version string '%s' "
4931 "unrecognized.", HPSA_DRIVER_VERSION);
4932 vmaj = 0;
4933 vmin = 0;
4934 vsubmin = 0;
4935 }
4936 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4937 if (!argp)
4938 return -EINVAL;
4939 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4940 return -EFAULT;
4941 return 0;
4942}
4943
4944static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4945{
4946 IOCTL_Command_struct iocommand;
4947 struct CommandList *c;
4948 char *buff = NULL;
4949 union u64bit temp64;
c1f63c8f 4950 int rc = 0;
edd16368
SC		 4951
4952 if (!argp)
4953 return -EINVAL;
4954 if (!capable(CAP_SYS_RAWIO))
4955 return -EPERM;
4956 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4957 return -EFAULT;
4958 if ((iocommand.buf_size < 1) &&
4959 (iocommand.Request.Type.Direction != XFER_NONE)) {
4960 return -EINVAL;
4961 }
4962 if (iocommand.buf_size > 0) {
4963 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4964 if (buff == NULL)
4965 return -EFAULT;
9233fb10 4966 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4967 /* Copy the data into the buffer we created */
4968 if (copy_from_user(buff, iocommand.buf,
4969 iocommand.buf_size)) {
c1f63c8f
SC		 4970 rc = -EFAULT;
4971 goto out_kfree;
b03a7771
SC		 4972 }
4973 } else {
4974 memset(buff, 0, iocommand.buf_size);
edd16368 4975 }
b03a7771 4976 }
edd16368
SC		 4977 c = cmd_special_alloc(h);
4978 if (c == NULL) {
c1f63c8f
SC		 4979 rc = -ENOMEM;
4980 goto out_kfree;
edd16368
SC		 4981 }
4982 /* Fill in the command type */
4983 c->cmd_type = CMD_IOCTL_PEND;
4984 /* Fill in Command Header */
4985 c->Header.ReplyQueue = 0; /* unused in simple mode */
4986 if (iocommand.buf_size > 0) { /* buffer to fill */
4987 c->Header.SGList = 1;
4988 c->Header.SGTotal = 1;
4989 } else { /* no buffers to fill */
4990 c->Header.SGList = 0;
4991 c->Header.SGTotal = 0;
4992 }
4993 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4994 /* use the kernel address the cmd block for tag */
4995 c->Header.Tag.lower = c->busaddr;
4996
4997 /* Fill in Request block */
4998 memcpy(&c->Request, &iocommand.Request,
4999 sizeof(c->Request));
5000
5001 /* Fill in the scatter gather information */
5002 if (iocommand.buf_size > 0) {
5003 temp64.val = pci_map_single(h->pdev, buff,
5004 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5005 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5006 c->SG[0].Addr.lower = 0;
5007 c->SG[0].Addr.upper = 0;
5008 c->SG[0].Len = 0;
5009 rc = -ENOMEM;
5010 goto out;
5011 }
edd16368
SC		 5012 c->SG[0].Addr.lower = temp64.val32.lower;
5013 c->SG[0].Addr.upper = temp64.val32.upper;
5014 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 5015 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 5016 }
a0c12413 5017 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 5018 if (iocommand.buf_size > 0)
5019 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5020 check_ioctl_unit_attention(h, c);
5021
5022 /* Copy the error information out */
5023 memcpy(&iocommand.error_info, c->err_info,
5024 sizeof(iocommand.error_info));
5025 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5026 rc = -EFAULT;
5027 goto out;
edd16368 5028 }
9233fb10 5029 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5030 iocommand.buf_size > 0) {
edd16368
SC		 5031 /* Copy the data out of the buffer we created */
5032 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5033 rc = -EFAULT;
5034 goto out;
edd16368
SC		 5035 }
5036 }
c1f63c8f 5037out:
edd16368 5038 cmd_special_free(h, c);
c1f63c8f
SC		 5039out_kfree:
5040 kfree(buff);
5041 return rc;
edd16368
SC		 5042}
5043
5044static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5045{
5046 BIG_IOCTL_Command_struct *ioc;
5047 struct CommandList *c;
5048 unsigned char **buff = NULL;
5049 int *buff_size = NULL;
5050 union u64bit temp64;
5051 BYTE sg_used = 0;
5052 int status = 0;
5053 int i;
01a02ffc
SC		 5054 u32 left;
5055 u32 sz;
edd16368
SC		 5056 BYTE __user *data_ptr;
5057
5058 if (!argp)
5059 return -EINVAL;
5060 if (!capable(CAP_SYS_RAWIO))
5061 return -EPERM;
5062 ioc = (BIG_IOCTL_Command_struct *)
5063 kmalloc(sizeof(*ioc), GFP_KERNEL);
5064 if (!ioc) {
5065 status = -ENOMEM;
5066 goto cleanup1;
5067 }
5068 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5069 status = -EFAULT;
5070 goto cleanup1;
5071 }
5072 if ((ioc->buf_size < 1) &&
5073 (ioc->Request.Type.Direction != XFER_NONE)) {
5074 status = -EINVAL;
5075 goto cleanup1;
5076 }
5077 /* Check kmalloc limits using all SGs */
5078 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5079 status = -EINVAL;
5080 goto cleanup1;
5081 }
d66ae08b 5082 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5083 status = -EINVAL;
5084 goto cleanup1;
5085 }
d66ae08b 5086 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5087 if (!buff) {
5088 status = -ENOMEM;
5089 goto cleanup1;
5090 }
d66ae08b 5091 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5092 if (!buff_size) {
5093 status = -ENOMEM;
5094 goto cleanup1;
5095 }
5096 left = ioc->buf_size;
5097 data_ptr = ioc->buf;
5098 while (left) {
5099 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5100 buff_size[sg_used] = sz;
5101 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5102 if (buff[sg_used] == NULL) {
5103 status = -ENOMEM;
5104 goto cleanup1;
5105 }
9233fb10 5106 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368
SC		 5107 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
5108 status = -ENOMEM;
5109 goto cleanup1;
5110 }
5111 } else
5112 memset(buff[sg_used], 0, sz);
5113 left -= sz;
5114 data_ptr += sz;
5115 sg_used++;
5116 }
5117 c = cmd_special_alloc(h);
5118 if (c == NULL) {
5119 status = -ENOMEM;
5120 goto cleanup1;
5121 }
5122 c->cmd_type = CMD_IOCTL_PEND;
5123 c->Header.ReplyQueue = 0;
b03a7771 5124 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 5125 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
5126 c->Header.Tag.lower = c->busaddr;
5127 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5128 if (ioc->buf_size > 0) {
5129 int i;
5130 for (i = 0; i < sg_used; i++) {
5131 temp64.val = pci_map_single(h->pdev, buff[i],
5132 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5133 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5134 c->SG[i].Addr.lower = 0;
5135 c->SG[i].Addr.upper = 0;
5136 c->SG[i].Len = 0;
5137 hpsa_pci_unmap(h->pdev, c, i,
5138 PCI_DMA_BIDIRECTIONAL);
5139 status = -ENOMEM;
e2d4a1f6 5140 goto cleanup0;
bcc48ffa 5141 }
edd16368
SC		 5142 c->SG[i].Addr.lower = temp64.val32.lower;
5143 c->SG[i].Addr.upper = temp64.val32.upper;
5144 c->SG[i].Len = buff_size[i];
e1d9cbfa 5145 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 5146 }
5147 }
a0c12413 5148 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5149 if (sg_used)
5150 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5151 check_ioctl_unit_attention(h, c);
5152 /* Copy the error information out */
5153 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5154 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5155 status = -EFAULT;
e2d4a1f6 5156 goto cleanup0;
edd16368 5157 }
9233fb10 5158 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
edd16368
SC		 5159 /* Copy the data out of the buffer we created */
5160 BYTE __user *ptr = ioc->buf;
5161 for (i = 0; i < sg_used; i++) {
5162 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5163 status = -EFAULT;
e2d4a1f6 5164 goto cleanup0;
edd16368
SC		 5165 }
5166 ptr += buff_size[i];
5167 }
5168 }
edd16368 5169 status = 0;
e2d4a1f6
SC		 5170cleanup0:
5171 cmd_special_free(h, c);
edd16368
SC		 5172cleanup1:
5173 if (buff) {
5174 for (i = 0; i < sg_used; i++)
5175 kfree(buff[i]);
5176 kfree(buff);
5177 }
5178 kfree(buff_size);
5179 kfree(ioc);
5180 return status;
5181}
5182
5183static void check_ioctl_unit_attention(struct ctlr_info *h,
5184 struct CommandList *c)
5185{
5186 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5187 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5188 (void) check_for_unit_attention(h, c);
5189}
0390f0c0
SC		 5190
5191static int increment_passthru_count(struct ctlr_info *h)
5192{
5193 unsigned long flags;
5194
5195 spin_lock_irqsave(&h->passthru_count_lock, flags);
5196 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5197 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5198 return -1;
5199 }
5200 h->passthru_count++;
5201 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5202 return 0;
5203}
5204
5205static void decrement_passthru_count(struct ctlr_info *h)
5206{
5207 unsigned long flags;
5208
5209 spin_lock_irqsave(&h->passthru_count_lock, flags);
5210 if (h->passthru_count <= 0) {
5211 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5212 /* not expecting to get here. */
5213 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5214 return;
5215 }
5216 h->passthru_count--;
5217 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5218}
5219
edd16368
SC		 5220/*
5221 * ioctl
5222 */
5223static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
5224{
5225 struct ctlr_info *h;
5226 void __user *argp = (void __user *)arg;
0390f0c0 5227 int rc;
edd16368
SC		 5228
5229 h = sdev_to_hba(dev);
5230
5231 switch (cmd) {
5232 case CCISS_DEREGDISK:
5233 case CCISS_REGNEWDISK:
5234 case CCISS_REGNEWD:
a08a8471 5235 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5236 return 0;
5237 case CCISS_GETPCIINFO:
5238 return hpsa_getpciinfo_ioctl(h, argp);
5239 case CCISS_GETDRIVVER:
5240 return hpsa_getdrivver_ioctl(h, argp);
5241 case CCISS_PASSTHRU:
0390f0c0
SC		 5242 if (increment_passthru_count(h))
5243 return -EAGAIN;
5244 rc = hpsa_passthru_ioctl(h, argp);
5245 decrement_passthru_count(h);
5246 return rc;
edd16368 5247 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5248 if (increment_passthru_count(h))
5249 return -EAGAIN;
5250 rc = hpsa_big_passthru_ioctl(h, argp);
5251 decrement_passthru_count(h);
5252 return rc;
edd16368
SC		 5253 default:
5254 return -ENOTTY;
5255 }
5256}
5257
6f039790
GKH		 5258static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5259 u8 reset_type)
64670ac8
SC		 5260{
5261 struct CommandList *c;
5262
5263 c = cmd_alloc(h);
5264 if (!c)
5265 return -ENOMEM;
a2dac136
SC		 5266 /* fill_cmd can't fail here, no data buffer to map */
5267 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5268 RAID_CTLR_LUNID, TYPE_MSG);
5269 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5270 c->waiting = NULL;
5271 enqueue_cmd_and_start_io(h, c);
5272 /* Don't wait for completion, the reset won't complete. Don't free
5273 * the command either. This is the last command we will send before
5274 * re-initializing everything, so it doesn't matter and won't leak.
5275 */
5276 return 0;
5277}
5278
a2dac136 5279static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5280 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5281 int cmd_type)
5282{
5283 int pci_dir = XFER_NONE;
75167d2c 5284 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5285
5286 c->cmd_type = CMD_IOCTL_PEND;
5287 c->Header.ReplyQueue = 0;
5288 if (buff != NULL && size > 0) {
5289 c->Header.SGList = 1;
5290 c->Header.SGTotal = 1;
5291 } else {
5292 c->Header.SGList = 0;
5293 c->Header.SGTotal = 0;
5294 }
5295 c->Header.Tag.lower = c->busaddr;
5296 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5297
5298 c->Request.Type.Type = cmd_type;
5299 if (cmd_type == TYPE_CMD) {
5300 switch (cmd) {
5301 case HPSA_INQUIRY:
5302 /* are we trying to read a vital product page */
b7bb24eb 5303 if (page_code & VPD_PAGE) {
edd16368 5304 c->Request.CDB[1] = 0x01;
b7bb24eb 5305 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5306 }
5307 c->Request.CDBLen = 6;
5308 c->Request.Type.Attribute = ATTR_SIMPLE;
5309 c->Request.Type.Direction = XFER_READ;
5310 c->Request.Timeout = 0;
5311 c->Request.CDB[0] = HPSA_INQUIRY;
5312 c->Request.CDB[4] = size & 0xFF;
5313 break;
5314 case HPSA_REPORT_LOG:
5315 case HPSA_REPORT_PHYS:
5316 /* Talking to controller so It's a physical command
5317 mode = 00 target = 0. Nothing to write.
5318 */
5319 c->Request.CDBLen = 12;
5320 c->Request.Type.Attribute = ATTR_SIMPLE;
5321 c->Request.Type.Direction = XFER_READ;
5322 c->Request.Timeout = 0;
5323 c->Request.CDB[0] = cmd;
5324 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5325 c->Request.CDB[7] = (size >> 16) & 0xFF;
5326 c->Request.CDB[8] = (size >> 8) & 0xFF;
5327 c->Request.CDB[9] = size & 0xFF;
5328 break;
edd16368
SC		 5329 case HPSA_CACHE_FLUSH:
5330 c->Request.CDBLen = 12;
5331 c->Request.Type.Attribute = ATTR_SIMPLE;
5332 c->Request.Type.Direction = XFER_WRITE;
5333 c->Request.Timeout = 0;
5334 c->Request.CDB[0] = BMIC_WRITE;
5335 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5336 c->Request.CDB[7] = (size >> 8) & 0xFF;
5337 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5338 break;
5339 case TEST_UNIT_READY:
5340 c->Request.CDBLen = 6;
5341 c->Request.Type.Attribute = ATTR_SIMPLE;
5342 c->Request.Type.Direction = XFER_NONE;
5343 c->Request.Timeout = 0;
5344 break;
283b4a9b
SC		 5345 case HPSA_GET_RAID_MAP:
5346 c->Request.CDBLen = 12;
5347 c->Request.Type.Attribute = ATTR_SIMPLE;
5348 c->Request.Type.Direction = XFER_READ;
5349 c->Request.Timeout = 0;
5350 c->Request.CDB[0] = HPSA_CISS_READ;
5351 c->Request.CDB[1] = cmd;
5352 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5353 c->Request.CDB[7] = (size >> 16) & 0xFF;
5354 c->Request.CDB[8] = (size >> 8) & 0xFF;
5355 c->Request.CDB[9] = size & 0xFF;
5356 break;
316b221a
SC		 5357 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5358 c->Request.CDBLen = 10;
5359 c->Request.Type.Attribute = ATTR_SIMPLE;
5360 c->Request.Type.Direction = XFER_READ;
5361 c->Request.Timeout = 0;
5362 c->Request.CDB[0] = BMIC_READ;
5363 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5364 c->Request.CDB[7] = (size >> 16) & 0xFF;
5365 c->Request.CDB[8] = (size >> 8) & 0xFF;
5366 break;
edd16368
SC		 5367 default:
5368 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5369 BUG();
a2dac136 5370 return -1;
edd16368
SC		 5371 }
5372 } else if (cmd_type == TYPE_MSG) {
5373 switch (cmd) {
5374
5375 case HPSA_DEVICE_RESET_MSG:
5376 c->Request.CDBLen = 16;
5377 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5378 c->Request.Type.Attribute = ATTR_SIMPLE;
5379 c->Request.Type.Direction = XFER_NONE;
5380 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5381 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5382 c->Request.CDB[0] = cmd;
21e89afd 5383 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5384 /* If bytes 4-7 are zero, it means reset the */
5385 /* LunID device */
5386 c->Request.CDB[4] = 0x00;
5387 c->Request.CDB[5] = 0x00;
5388 c->Request.CDB[6] = 0x00;
5389 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5390 break;
5391 case HPSA_ABORT_MSG:
5392 a = buff; /* point to command to be aborted */
5393 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5394 a->Header.Tag.upper, a->Header.Tag.lower,
5395 c->Header.Tag.upper, c->Header.Tag.lower);
5396 c->Request.CDBLen = 16;
5397 c->Request.Type.Type = TYPE_MSG;
5398 c->Request.Type.Attribute = ATTR_SIMPLE;
5399 c->Request.Type.Direction = XFER_WRITE;
5400 c->Request.Timeout = 0; /* Don't time out */
5401 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5402 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5403 c->Request.CDB[2] = 0x00; /* reserved */
5404 c->Request.CDB[3] = 0x00; /* reserved */
5405 /* Tag to abort goes in CDB[4]-CDB[11] */
5406 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5407 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5408 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5409 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5410 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5411 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5412 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5413 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5414 c->Request.CDB[12] = 0x00; /* reserved */
5415 c->Request.CDB[13] = 0x00; /* reserved */
5416 c->Request.CDB[14] = 0x00; /* reserved */
5417 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5418 break;
edd16368
SC		 5419 default:
5420 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5421 cmd);
5422 BUG();
5423 }
5424 } else {
5425 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5426 BUG();
5427 }
5428
5429 switch (c->Request.Type.Direction) {
5430 case XFER_READ:
5431 pci_dir = PCI_DMA_FROMDEVICE;
5432 break;
5433 case XFER_WRITE:
5434 pci_dir = PCI_DMA_TODEVICE;
5435 break;
5436 case XFER_NONE:
5437 pci_dir = PCI_DMA_NONE;
5438 break;
5439 default:
5440 pci_dir = PCI_DMA_BIDIRECTIONAL;
5441 }
a2dac136
SC		 5442 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5443 return -1;
5444 return 0;
edd16368
SC		 5445}
5446
5447/*
5448 * Map (physical) PCI mem into (virtual) kernel space
5449 */
5450static void __iomem *remap_pci_mem(ulong base, ulong size)
5451{
5452 ulong page_base = ((ulong) base) & PAGE_MASK;
5453 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5454 void __iomem *page_remapped = ioremap_nocache(page_base,
5455 page_offs + size);
edd16368
SC		 5456
5457 return page_remapped ? (page_remapped + page_offs) : NULL;
5458}
5459
5460/* Takes cmds off the submission queue and sends them to the hardware,
5461 * then puts them on the queue of cmds waiting for completion.
5462 */
5463static void start_io(struct ctlr_info *h)
5464{
5465 struct CommandList *c;
e16a33ad 5466 unsigned long flags;
edd16368 5467
e16a33ad 5468 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 5469 while (!list_empty(&h->reqQ)) {
5470 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5471 /* can't do anything if fifo is full */
5472 if ((h->access.fifo_full(h))) {
396883e2 5473 h->fifo_recently_full = 1;
edd16368
SC		 5474 dev_warn(&h->pdev->dev, "fifo full\n");
5475 break;
5476 }
396883e2 5477 h->fifo_recently_full = 0;
edd16368
SC		 5478
5479 /* Get the first entry from the Request Q */
5480 removeQ(c);
5481 h->Qdepth--;
5482
edd16368
SC		 5483 /* Put job onto the completed Q */
5484 addQ(&h->cmpQ, c);
e16a33ad
MG		 5485
5486 /* Must increment commands_outstanding before unlocking
5487 * and submitting to avoid race checking for fifo full
5488 * condition.
5489 */
5490 h->commands_outstanding++;
e16a33ad
MG		 5491
5492 /* Tell the controller execute command */
5493 spin_unlock_irqrestore(&h->lock, flags);
5494 h->access.submit_command(h, c);
5495 spin_lock_irqsave(&h->lock, flags);
edd16368 5496 }
e16a33ad 5497 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5498}
5499
254f796b 5500static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5501{
254f796b 5502 return h->access.command_completed(h, q);
edd16368
SC		 5503}
5504
900c5440 5505static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5506{
5507 return h->access.intr_pending(h);
5508}
5509
5510static inline long interrupt_not_for_us(struct ctlr_info *h)
5511{
10f66018
SC		 5512 return (h->access.intr_pending(h) == 0) ||
5513 (h->interrupts_enabled == 0);
edd16368
SC		 5514}
5515
01a02ffc
SC		 5516static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5517 u32 raw_tag)
edd16368
SC		 5518{
5519 if (unlikely(tag_index >= h->nr_cmds)) {
5520 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5521 return 1;
5522 }
5523 return 0;
5524}
5525
5a3d16f5 5526static inline void finish_cmd(struct CommandList *c)
edd16368 5527{
e16a33ad 5528 unsigned long flags;
396883e2
SC		 5529 int io_may_be_stalled = 0;
5530 struct ctlr_info *h = c->h;
e16a33ad 5531
396883e2 5532 spin_lock_irqsave(&h->lock, flags);
edd16368 5533 removeQ(c);
396883e2
SC		 5534
5535 /*
5536 * Check for possibly stalled i/o.
5537 *
5538 * If a fifo_full condition is encountered, requests will back up
5539 * in h->reqQ. This queue is only emptied out by start_io which is
5540 * only called when a new i/o request comes in. If no i/o's are
5541 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5542 * start_io from here if we detect such a danger.
5543 *
5544 * Normally, we shouldn't hit this case, but pounding on the
5545 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5546 * commands_outstanding is low. We want to avoid calling
5547 * start_io from in here as much as possible, and esp. don't
5548 * want to get in a cycle where we call start_io every time
5549 * through here.
5550 */
5551 if (unlikely(h->fifo_recently_full) &&
5552 h->commands_outstanding < 5)
5553 io_may_be_stalled = 1;
5554
5555 spin_unlock_irqrestore(&h->lock, flags);
5556
e85c5974 5557 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5558 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5559 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5560 complete_scsi_command(c);
edd16368
SC		 5561 else if (c->cmd_type == CMD_IOCTL_PEND)
5562 complete(c->waiting);
396883e2
SC		 5563 if (unlikely(io_may_be_stalled))
5564 start_io(h);
edd16368
SC		 5565}
5566
a104c99f
SC		 5567static inline u32 hpsa_tag_contains_index(u32 tag)
5568{
a104c99f
SC		 5569 return tag & DIRECT_LOOKUP_BIT;
5570}
5571
5572static inline u32 hpsa_tag_to_index(u32 tag)
5573{
a104c99f
SC		 5574 return tag >> DIRECT_LOOKUP_SHIFT;
5575}
5576
a9a3a273
SC		 5577
5578static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5579{
a9a3a273
SC		 5580#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5581#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5582 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5583 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5584 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5585}
5586
303932fd 5587/* process completion of an indexed ("direct lookup") command */
1d94f94d 5588static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5589 u32 raw_tag)
5590{
5591 u32 tag_index;
5592 struct CommandList *c;
5593
5594 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5595 if (!bad_tag(h, tag_index, raw_tag)) {
5596 c = h->cmd_pool + tag_index;
5597 finish_cmd(c);
5598 }
303932fd
DB		 5599}
5600
5601/* process completion of a non-indexed command */
1d94f94d 5602static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5603 u32 raw_tag)
5604{
5605 u32 tag;
5606 struct CommandList *c = NULL;
e16a33ad 5607 unsigned long flags;
303932fd 5608
a9a3a273 5609 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5610 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5611 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5612 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5613 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5614 finish_cmd(c);
1d94f94d 5615 return;
303932fd
DB		 5616 }
5617 }
e16a33ad 5618 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5619 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5620}
5621
64670ac8
SC		 5622/* Some controllers, like p400, will give us one interrupt
5623 * after a soft reset, even if we turned interrupts off.
5624 * Only need to check for this in the hpsa_xxx_discard_completions
5625 * functions.
5626 */
5627static int ignore_bogus_interrupt(struct ctlr_info *h)
5628{
5629 if (likely(!reset_devices))
5630 return 0;
5631
5632 if (likely(h->interrupts_enabled))
5633 return 0;
5634
5635 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5636 "(known firmware bug.) Ignoring.\n");
5637
5638 return 1;
5639}
5640
254f796b
MG		 5641/*
5642 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5643 * Relies on (h-q[x] == x) being true for x such that
5644 * 0 <= x < MAX_REPLY_QUEUES.
5645 */
5646static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5647{
254f796b
MG		 5648 return container_of((queue - *queue), struct ctlr_info, q[0]);
5649}
5650
5651static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5652{
5653 struct ctlr_info *h = queue_to_hba(queue);
5654 u8 q = *(u8 *) queue;
64670ac8
SC		 5655 u32 raw_tag;
5656
5657 if (ignore_bogus_interrupt(h))
5658 return IRQ_NONE;
5659
5660 if (interrupt_not_for_us(h))
5661 return IRQ_NONE;
a0c12413 5662 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5663 while (interrupt_pending(h)) {
254f796b 5664 raw_tag = get_next_completion(h, q);
64670ac8 5665 while (raw_tag != FIFO_EMPTY)
254f796b 5666 raw_tag = next_command(h, q);
64670ac8 5667 }
64670ac8
SC		 5668 return IRQ_HANDLED;
5669}
5670
254f796b 5671static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5672{
254f796b 5673 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5674 u32 raw_tag;
254f796b 5675 u8 q = *(u8 *) queue;
64670ac8
SC		 5676
5677 if (ignore_bogus_interrupt(h))
5678 return IRQ_NONE;
5679
a0c12413 5680 h->last_intr_timestamp = get_jiffies_64();
254f796b 5681 raw_tag = get_next_completion(h, q);
64670ac8 5682 while (raw_tag != FIFO_EMPTY)
254f796b 5683 raw_tag = next_command(h, q);
64670ac8
SC		 5684 return IRQ_HANDLED;
5685}
5686
254f796b 5687static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5688{
254f796b 5689 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5690 u32 raw_tag;
254f796b 5691 u8 q = *(u8 *) queue;
edd16368
SC		 5692
5693 if (interrupt_not_for_us(h))
5694 return IRQ_NONE;
a0c12413 5695 h->last_intr_timestamp = get_jiffies_64();
10f66018 5696 while (interrupt_pending(h)) {
254f796b 5697 raw_tag = get_next_completion(h, q);
10f66018 5698 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5699 if (likely(hpsa_tag_contains_index(raw_tag)))
5700 process_indexed_cmd(h, raw_tag);
10f66018 5701 else
1d94f94d 5702 process_nonindexed_cmd(h, raw_tag);
254f796b 5703 raw_tag = next_command(h, q);
10f66018
SC		 5704 }
5705 }
10f66018
SC		 5706 return IRQ_HANDLED;
5707}
5708
254f796b 5709static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5710{
254f796b 5711 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5712 u32 raw_tag;
254f796b 5713 u8 q = *(u8 *) queue;
10f66018 5714
a0c12413 5715 h->last_intr_timestamp = get_jiffies_64();
254f796b 5716 raw_tag = get_next_completion(h, q);
303932fd 5717 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5718 if (likely(hpsa_tag_contains_index(raw_tag)))
5719 process_indexed_cmd(h, raw_tag);
303932fd 5720 else
1d94f94d 5721 process_nonindexed_cmd(h, raw_tag);
254f796b 5722 raw_tag = next_command(h, q);
edd16368 5723 }
edd16368
SC		 5724 return IRQ_HANDLED;
5725}
5726
a9a3a273
SC		 5727/* Send a message CDB to the firmware. Careful, this only works
5728 * in simple mode, not performant mode due to the tag lookup.
5729 * We only ever use this immediately after a controller reset.
5730 */
6f039790
GKH		 5731static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5732 unsigned char type)
edd16368
SC		 5733{
5734 struct Command {
5735 struct CommandListHeader CommandHeader;
5736 struct RequestBlock Request;
5737 struct ErrDescriptor ErrorDescriptor;
5738 };
5739 struct Command *cmd;
5740 static const size_t cmd_sz = sizeof(*cmd) +
5741 sizeof(cmd->ErrorDescriptor);
5742 dma_addr_t paddr64;
5743 uint32_t paddr32, tag;
5744 void __iomem *vaddr;
5745 int i, err;
5746
5747 vaddr = pci_ioremap_bar(pdev, 0);
5748 if (vaddr == NULL)
5749 return -ENOMEM;
5750
5751 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5752 * CCISS commands, so they must be allocated from the lower 4GiB of
5753 * memory.
5754 */
5755 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5756 if (err) {
5757 iounmap(vaddr);
5758 return -ENOMEM;
5759 }
5760
5761 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5762 if (cmd == NULL) {
5763 iounmap(vaddr);
5764 return -ENOMEM;
5765 }
5766
5767 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5768 * although there's no guarantee, we assume that the address is at
5769 * least 4-byte aligned (most likely, it's page-aligned).
5770 */
5771 paddr32 = paddr64;
5772
5773 cmd->CommandHeader.ReplyQueue = 0;
5774 cmd->CommandHeader.SGList = 0;
5775 cmd->CommandHeader.SGTotal = 0;
5776 cmd->CommandHeader.Tag.lower = paddr32;
5777 cmd->CommandHeader.Tag.upper = 0;
5778 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5779
5780 cmd->Request.CDBLen = 16;
5781 cmd->Request.Type.Type = TYPE_MSG;
5782 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5783 cmd->Request.Type.Direction = XFER_NONE;
5784 cmd->Request.Timeout = 0; /* Don't time out */
5785 cmd->Request.CDB[0] = opcode;
5786 cmd->Request.CDB[1] = type;
5787 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5788 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5789 cmd->ErrorDescriptor.Addr.upper = 0;
5790 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5791
5792 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5793
5794 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5795 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5796 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5797 break;
5798 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5799 }
5800
5801 iounmap(vaddr);
5802
5803 /* we leak the DMA buffer here ... no choice since the controller could
5804 * still complete the command.
5805 */
5806 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5807 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5808 opcode, type);
5809 return -ETIMEDOUT;
5810 }
5811
5812 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5813
5814 if (tag & HPSA_ERROR_BIT) {
5815 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5816 opcode, type);
5817 return -EIO;
5818 }
5819
5820 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5821 opcode, type);
5822 return 0;
5823}
5824
edd16368
SC		 5825#define hpsa_noop(p) hpsa_message(p, 3, 0)
5826
1df8552a 5827static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5828 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5829{
5830 u16 pmcsr;
5831 int pos;
5832
5833 if (use_doorbell) {
5834 /* For everything after the P600, the PCI power state method
5835 * of resetting the controller doesn't work, so we have this
5836 * other way using the doorbell register.
5837 */
5838 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5839 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5840
00701a96 5841 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5842 * doorbell reset and before any attempt to talk to the board
5843 * at all to ensure that this actually works and doesn't fall
5844 * over in some weird corner cases.
5845 */
00701a96 5846 msleep(10000);
1df8552a
SC		 5847 } else { /* Try to do it the PCI power state way */
5848
5849 /* Quoting from the Open CISS Specification: "The Power
5850 * Management Control/Status Register (CSR) controls the power
5851 * state of the device. The normal operating state is D0,
5852 * CSR=00h. The software off state is D3, CSR=03h. To reset
5853 * the controller, place the interface device in D3 then to D0,
5854 * this causes a secondary PCI reset which will reset the
5855 * controller." */
5856
5857 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5858 if (pos == 0) {
5859 dev_err(&pdev->dev,
5860 "hpsa_reset_controller: "
5861 "PCI PM not supported\n");
5862 return -ENODEV;
5863 }
5864 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5865 /* enter the D3hot power management state */
5866 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5867 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5868 pmcsr |= PCI_D3hot;
5869 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5870
5871 msleep(500);
5872
5873 /* enter the D0 power management state */
5874 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5875 pmcsr |= PCI_D0;
5876 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5877
5878 /*
5879 * The P600 requires a small delay when changing states.
5880 * Otherwise we may think the board did not reset and we bail.
5881 * This for kdump only and is particular to the P600.
5882 */
5883 msleep(500);
1df8552a
SC		 5884 }
5885 return 0;
5886}
5887
6f039790 5888static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5889{
5890 memset(driver_version, 0, len);
f79cfec6 5891 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5892}
5893
6f039790 5894static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5895{
5896 char *driver_version;
5897 int i, size = sizeof(cfgtable->driver_version);
5898
5899 driver_version = kmalloc(size, GFP_KERNEL);
5900 if (!driver_version)
5901 return -ENOMEM;
5902
5903 init_driver_version(driver_version, size);
5904 for (i = 0; i < size; i++)
5905 writeb(driver_version[i], &cfgtable->driver_version[i]);
5906 kfree(driver_version);
5907 return 0;
5908}
5909
6f039790
GKH		 5910static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5911 unsigned char *driver_ver)
580ada3c
SC		 5912{
5913 int i;
5914
5915 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5916 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5917}
5918
6f039790 5919static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5920{
5921
5922 char *driver_ver, *old_driver_ver;
5923 int rc, size = sizeof(cfgtable->driver_version);
5924
5925 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5926 if (!old_driver_ver)
5927 return -ENOMEM;
5928 driver_ver = old_driver_ver + size;
5929
5930 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5931 * should have been changed, otherwise we know the reset failed.
5932 */
5933 init_driver_version(old_driver_ver, size);
5934 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5935 rc = !memcmp(driver_ver, old_driver_ver, size);
5936 kfree(old_driver_ver);
5937 return rc;
5938}
edd16368 5939/* This does a hard reset of the controller using PCI power management
1df8552a 5940 * states or the using the doorbell register.
edd16368 5941 */
6f039790 5942static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5943{
1df8552a
SC		 5944 u64 cfg_offset;
5945 u32 cfg_base_addr;
5946 u64 cfg_base_addr_index;
5947 void __iomem *vaddr;
5948 unsigned long paddr;
580ada3c 5949 u32 misc_fw_support;
270d05de 5950 int rc;
1df8552a 5951 struct CfgTable __iomem *cfgtable;
cf0b08d0 5952 u32 use_doorbell;
18867659 5953 u32 board_id;
270d05de 5954 u16 command_register;
edd16368 5955
1df8552a
SC		 5956 /* For controllers as old as the P600, this is very nearly
5957 * the same thing as
edd16368
SC		 5958 *
5959 * pci_save_state(pci_dev);
5960 * pci_set_power_state(pci_dev, PCI_D3hot);
5961 * pci_set_power_state(pci_dev, PCI_D0);
5962 * pci_restore_state(pci_dev);
5963 *
1df8552a
SC		 5964 * For controllers newer than the P600, the pci power state
5965 * method of resetting doesn't work so we have another way
5966 * using the doorbell register.
edd16368 5967 */
18867659 5968
25c1e56a 5969 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5970 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5971 dev_warn(&pdev->dev, "Not resetting device.\n");
5972 return -ENODEV;
5973 }
46380786
SC		 5974
5975 /* if controller is soft- but not hard resettable... */
5976 if (!ctlr_is_hard_resettable(board_id))
5977 return -ENOTSUPP; /* try soft reset later. */
18867659 5978
270d05de
SC		 5979 /* Save the PCI command register */
5980 pci_read_config_word(pdev, 4, &command_register);
5981 /* Turn the board off. This is so that later pci_restore_state()
5982 * won't turn the board on before the rest of config space is ready.
5983 */
5984 pci_disable_device(pdev);
5985 pci_save_state(pdev);
edd16368 5986
1df8552a
SC		 5987 /* find the first memory BAR, so we can find the cfg table */
5988 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5989 if (rc)
5990 return rc;
5991 vaddr = remap_pci_mem(paddr, 0x250);
5992 if (!vaddr)
5993 return -ENOMEM;
edd16368 5994
1df8552a
SC		 5995 /* find cfgtable in order to check if reset via doorbell is supported */
5996 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5997 &cfg_base_addr_index, &cfg_offset);
5998 if (rc)
5999 goto unmap_vaddr;
6000 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6001 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6002 if (!cfgtable) {
6003 rc = -ENOMEM;
6004 goto unmap_vaddr;
6005 }
580ada3c
SC		 6006 rc = write_driver_ver_to_cfgtable(cfgtable);
6007 if (rc)
6008 goto unmap_vaddr;
edd16368 6009
cf0b08d0
SC		 6010 /* If reset via doorbell register is supported, use that.
6011 * There are two such methods. Favor the newest method.
6012 */
1df8552a 6013 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6014 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6015 if (use_doorbell) {
6016 use_doorbell = DOORBELL_CTLR_RESET2;
6017 } else {
6018 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6019 if (use_doorbell) {
fba63097
MM		 6020 dev_warn(&pdev->dev, "Soft reset not supported. "
6021 "Firmware update is required.\n");
64670ac8 6022 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6023 goto unmap_cfgtable;
6024 }
6025 }
edd16368 6026
1df8552a
SC		 6027 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6028 if (rc)
6029 goto unmap_cfgtable;
edd16368 6030
270d05de
SC		 6031 pci_restore_state(pdev);
6032 rc = pci_enable_device(pdev);
6033 if (rc) {
6034 dev_warn(&pdev->dev, "failed to enable device.\n");
6035 goto unmap_cfgtable;
edd16368 6036 }
270d05de 6037 pci_write_config_word(pdev, 4, command_register);
edd16368 6038
1df8552a
SC		 6039 /* Some devices (notably the HP Smart Array 5i Controller)
6040 need a little pause here */
6041 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6042
fe5389c8
SC		 6043 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6044 if (rc) {
6045 dev_warn(&pdev->dev,
64670ac8
SC		 6046 "failed waiting for board to become ready "
6047 "after hard reset\n");
fe5389c8
SC		 6048 goto unmap_cfgtable;
6049 }
fe5389c8 6050
580ada3c
SC		 6051 rc = controller_reset_failed(vaddr);
6052 if (rc < 0)
6053 goto unmap_cfgtable;
6054 if (rc) {
64670ac8
SC		 6055 dev_warn(&pdev->dev, "Unable to successfully reset "
6056 "controller. Will try soft reset.\n");
6057 rc = -ENOTSUPP;
580ada3c 6058 } else {
64670ac8 6059 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6060 }
6061
6062unmap_cfgtable:
6063 iounmap(cfgtable);
6064
6065unmap_vaddr:
6066 iounmap(vaddr);
6067 return rc;
edd16368
SC		 6068}
6069
6070/*
6071 * We cannot read the structure directly, for portability we must use
6072 * the io functions.
6073 * This is for debug only.
6074 */
edd16368
SC		 6075static void print_cfg_table(struct device *dev, struct CfgTable *tb)
6076{
58f8665c 6077#ifdef HPSA_DEBUG
edd16368
SC		 6078 int i;
6079 char temp_name[17];
6080
6081 dev_info(dev, "Controller Configuration information\n");
6082 dev_info(dev, "------------------------------------\n");
6083 for (i = 0; i < 4; i++)
6084 temp_name[i] = readb(&(tb->Signature[i]));
6085 temp_name[4] = '\0';
6086 dev_info(dev, " Signature = %s\n", temp_name);
6087 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6088 dev_info(dev, " Transport methods supported = 0x%x\n",
6089 readl(&(tb->TransportSupport)));
6090 dev_info(dev, " Transport methods active = 0x%x\n",
6091 readl(&(tb->TransportActive)));
6092 dev_info(dev, " Requested transport Method = 0x%x\n",
6093 readl(&(tb->HostWrite.TransportRequest)));
6094 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6095 readl(&(tb->HostWrite.CoalIntDelay)));
6096 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6097 readl(&(tb->HostWrite.CoalIntCount)));
6098 dev_info(dev, " Max outstanding commands = 0x%d\n",
6099 readl(&(tb->CmdsOutMax)));
6100 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6101 for (i = 0; i < 16; i++)
6102 temp_name[i] = readb(&(tb->ServerName[i]));
6103 temp_name[16] = '\0';
6104 dev_info(dev, " Server Name = %s\n", temp_name);
6105 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6106 readl(&(tb->HeartBeat)));
edd16368 6107#endif /* HPSA_DEBUG */
58f8665c 6108}
edd16368
SC		 6109
6110static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6111{
6112 int i, offset, mem_type, bar_type;
6113
6114 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6115 return 0;
6116 offset = 0;
6117 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6118 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6119 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6120 offset += 4;
6121 else {
6122 mem_type = pci_resource_flags(pdev, i) &
6123 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6124 switch (mem_type) {
6125 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6126 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6127 offset += 4; /* 32 bit */
6128 break;
6129 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6130 offset += 8;
6131 break;
6132 default: /* reserved in PCI 2.2 */
6133 dev_warn(&pdev->dev,
6134 "base address is invalid\n");
6135 return -1;
6136 break;
6137 }
6138 }
6139 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6140 return i + 1;
6141 }
6142 return -1;
6143}
6144
6145/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6146 * controllers that are capable. If not, we use IO-APIC mode.
6147 */
6148
6f039790 6149static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6150{
6151#ifdef CONFIG_PCI_MSI
254f796b
MG		 6152 int err, i;
6153 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6154
6155 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6156 hpsa_msix_entries[i].vector = 0;
6157 hpsa_msix_entries[i].entry = i;
6158 }
edd16368
SC		 6159
6160 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6161 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6162 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6163 goto default_int_mode;
55c06c71
SC		 6164 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6165 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6166 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6167 if (h->msix_vector > num_online_cpus())
6168 h->msix_vector = num_online_cpus();
254f796b 6169 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 6170 h->msix_vector);
edd16368 6171 if (err > 0) {
55c06c71 6172 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6173 "available\n", err);
eee0f03a
HR		 6174 h->msix_vector = err;
6175 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
6176 h->msix_vector);
6177 }
6178 if (!err) {
6179 for (i = 0; i < h->msix_vector; i++)
6180 h->intr[i] = hpsa_msix_entries[i].vector;
6181 return;
edd16368 6182 } else {
55c06c71 6183 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 6184 err);
eee0f03a 6185 h->msix_vector = 0;
edd16368
SC		 6186 goto default_int_mode;
6187 }
6188 }
55c06c71
SC		 6189 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6190 dev_info(&h->pdev->dev, "MSI\n");
6191 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6192 h->msi_vector = 1;
6193 else
55c06c71 6194 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6195 }
6196default_int_mode:
6197#endif /* CONFIG_PCI_MSI */
6198 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6199 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6200}
6201
6f039790 6202static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6203{
6204 int i;
6205 u32 subsystem_vendor_id, subsystem_device_id;
6206
6207 subsystem_vendor_id = pdev->subsystem_vendor;
6208 subsystem_device_id = pdev->subsystem_device;
6209 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6210 subsystem_vendor_id;
6211
6212 for (i = 0; i < ARRAY_SIZE(products); i++)
6213 if (*board_id == products[i].board_id)
6214 return i;
6215
6798cc0a
SC		 6216 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6217 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6218 !hpsa_allow_any) {
e5c880d1
SC		 6219 dev_warn(&pdev->dev, "unrecognized board ID: "
6220 "0x%08x, ignoring.\n", *board_id);
6221 return -ENODEV;
6222 }
6223 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6224}
6225
6f039790
GKH		 6226static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6227 unsigned long *memory_bar)
3a7774ce
SC		 6228{
6229 int i;
6230
6231 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6232 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6233 /* addressing mode bits already removed */
12d2cd47
SC		 6234 *memory_bar = pci_resource_start(pdev, i);
6235 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6236 *memory_bar);
6237 return 0;
6238 }
12d2cd47 6239 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6240 return -ENODEV;
6241}
6242
6f039790
GKH		 6243static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6244 int wait_for_ready)
2c4c8c8b 6245{
fe5389c8 6246 int i, iterations;
2c4c8c8b 6247 u32 scratchpad;
fe5389c8
SC		 6248 if (wait_for_ready)
6249 iterations = HPSA_BOARD_READY_ITERATIONS;
6250 else
6251 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6252
fe5389c8
SC		 6253 for (i = 0; i < iterations; i++) {
6254 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6255 if (wait_for_ready) {
6256 if (scratchpad == HPSA_FIRMWARE_READY)
6257 return 0;
6258 } else {
6259 if (scratchpad != HPSA_FIRMWARE_READY)
6260 return 0;
6261 }
2c4c8c8b
SC		 6262 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6263 }
fe5389c8 6264 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6265 return -ENODEV;
6266}
6267
6f039790
GKH		 6268static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6269 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6270 u64 *cfg_offset)
a51fd47f
SC		 6271{
6272 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6273 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6274 *cfg_base_addr &= (u32) 0x0000ffff;
6275 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6276 if (*cfg_base_addr_index == -1) {
6277 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6278 return -ENODEV;
6279 }
6280 return 0;
6281}
6282
6f039790 6283static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6284{
01a02ffc
SC		 6285 u64 cfg_offset;
6286 u32 cfg_base_addr;
6287 u64 cfg_base_addr_index;
303932fd 6288 u32 trans_offset;
a51fd47f 6289 int rc;
77c4495c 6290
a51fd47f
SC		 6291 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6292 &cfg_base_addr_index, &cfg_offset);
6293 if (rc)
6294 return rc;
77c4495c 6295 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6296 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6297 if (!h->cfgtable)
6298 return -ENOMEM;
580ada3c
SC		 6299 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6300 if (rc)
6301 return rc;
77c4495c 6302 /* Find performant mode table. */
a51fd47f 6303 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6304 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6305 cfg_base_addr_index)+cfg_offset+trans_offset,
6306 sizeof(*h->transtable));
6307 if (!h->transtable)
6308 return -ENOMEM;
6309 return 0;
6310}
6311
6f039790 6312static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6313{
6314 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6315
6316 /* Limit commands in memory limited kdump scenario. */
6317 if (reset_devices && h->max_commands > 32)
6318 h->max_commands = 32;
6319
cba3d38b
SC		 6320 if (h->max_commands < 16) {
6321 dev_warn(&h->pdev->dev, "Controller reports "
6322 "max supported commands of %d, an obvious lie. "
6323 "Using 16. Ensure that firmware is up to date.\n",
6324 h->max_commands);
6325 h->max_commands = 16;
6326 }
6327}
6328
b93d7536
SC		 6329/* Interrogate the hardware for some limits:
6330 * max commands, max SG elements without chaining, and with chaining,
6331 * SG chain block size, etc.
6332 */
6f039790 6333static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6334{
cba3d38b 6335 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6336 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6337 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6338 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6339 /*
6340 * Limit in-command s/g elements to 32 save dma'able memory.
6341 * Howvever spec says if 0, use 31
6342 */
6343 h->max_cmd_sg_entries = 31;
6344 if (h->maxsgentries > 512) {
6345 h->max_cmd_sg_entries = 32;
6346 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
6347 h->maxsgentries--; /* save one for chain pointer */
6348 } else {
6349 h->maxsgentries = 31; /* default to traditional values */
6350 h->chainsize = 0;
6351 }
75167d2c
SC		 6352
6353 /* Find out what task management functions are supported and cache */
6354 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6355 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6356 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6357 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6358 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6359}
6360
76c46e49
SC		 6361static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6362{
0fc9fd40 6363 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6364 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6365 return false;
6366 }
6367 return true;
6368}
6369
97a5e98c 6370static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6371{
97a5e98c 6372 u32 driver_support;
f7c39101 6373
28e13446
SC		 6374#ifdef CONFIG_X86
6375 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6376 driver_support = readl(&(h->cfgtable->driver_support));
6377 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6378#endif
28e13446
SC		 6379 driver_support |= ENABLE_UNIT_ATTN;
6380 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6381}
6382
3d0eab67
SC		 6383/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6384 * in a prefetch beyond physical memory.
6385 */
6386static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6387{
6388 u32 dma_prefetch;
6389
6390 if (h->board_id != 0x3225103C)
6391 return;
6392 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6393 dma_prefetch |= 0x8000;
6394 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6395}
6396
76438d08
SC		 6397static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6398{
6399 int i;
6400 u32 doorbell_value;
6401 unsigned long flags;
6402 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6403 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6404 spin_lock_irqsave(&h->lock, flags);
6405 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6406 spin_unlock_irqrestore(&h->lock, flags);
6407 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6408 break;
6409 /* delay and try again */
6410 msleep(20);
6411 }
6412}
6413
6f039790 6414static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6415{
6416 int i;
6eaf46fd
SC		 6417 u32 doorbell_value;
6418 unsigned long flags;
eb6b2ae9
SC		 6419
6420 /* under certain very rare conditions, this can take awhile.
6421 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6422 * as we enter this code.)
6423 */
6424 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6425 spin_lock_irqsave(&h->lock, flags);
6426 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6427 spin_unlock_irqrestore(&h->lock, flags);
382be668 6428 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6429 break;
6430 /* delay and try again */
60d3f5b0 6431 usleep_range(10000, 20000);
eb6b2ae9 6432 }
3f4336f3
SC		 6433}
6434
6f039790 6435static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6436{
6437 u32 trans_support;
6438
6439 trans_support = readl(&(h->cfgtable->TransportSupport));
6440 if (!(trans_support & SIMPLE_MODE))
6441 return -ENOTSUPP;
6442
6443 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6444
3f4336f3
SC		 6445 /* Update the field, and then ring the doorbell */
6446 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6447 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6448 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6449 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6450 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6451 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6452 goto error;
960a30e7 6453 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6454 return 0;
283b4a9b
SC		 6455error:
6456 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6457 return -ENODEV;
eb6b2ae9
SC		 6458}
6459
6f039790 6460static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6461{
eb6b2ae9 6462 int prod_index, err;
edd16368 6463
e5c880d1
SC		 6464 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6465 if (prod_index < 0)
6466 return -ENODEV;
6467 h->product_name = products[prod_index].product_name;
6468 h->access = *(products[prod_index].access);
edd16368 6469
e5a44df8
MG		 6470 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6471 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6472
55c06c71 6473 err = pci_enable_device(h->pdev);
edd16368 6474 if (err) {
55c06c71 6475 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6476 return err;
6477 }
6478
5cb460a6
SC		 6479 /* Enable bus mastering (pci_disable_device may disable this) */
6480 pci_set_master(h->pdev);
6481
f79cfec6 6482 err = pci_request_regions(h->pdev, HPSA);
edd16368 6483 if (err) {
55c06c71
SC		 6484 dev_err(&h->pdev->dev,
6485 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6486 return err;
6487 }
6b3f4c52 6488 hpsa_interrupt_mode(h);
12d2cd47 6489 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6490 if (err)
edd16368 6491 goto err_out_free_res;
edd16368 6492 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6493 if (!h->vaddr) {
6494 err = -ENOMEM;
6495 goto err_out_free_res;
6496 }
fe5389c8 6497 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6498 if (err)
edd16368 6499 goto err_out_free_res;
77c4495c
SC		 6500 err = hpsa_find_cfgtables(h);
6501 if (err)
edd16368 6502 goto err_out_free_res;
b93d7536 6503 hpsa_find_board_params(h);
edd16368 6504
76c46e49 6505 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6506 err = -ENODEV;
6507 goto err_out_free_res;
6508 }
97a5e98c 6509 hpsa_set_driver_support_bits(h);
3d0eab67 6510 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6511 err = hpsa_enter_simple_mode(h);
6512 if (err)
edd16368 6513 goto err_out_free_res;
edd16368
SC		 6514 return 0;
6515
6516err_out_free_res:
204892e9
SC		 6517 if (h->transtable)
6518 iounmap(h->transtable);
6519 if (h->cfgtable)
6520 iounmap(h->cfgtable);
6521 if (h->vaddr)
6522 iounmap(h->vaddr);
f0bd0b68 6523 pci_disable_device(h->pdev);
55c06c71 6524 pci_release_regions(h->pdev);
edd16368
SC		 6525 return err;
6526}
6527
6f039790 6528static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6529{
6530 int rc;
6531
6532#define HBA_INQUIRY_BYTE_COUNT 64
6533 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6534 if (!h->hba_inquiry_data)
6535 return;
6536 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6537 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6538 if (rc != 0) {
6539 kfree(h->hba_inquiry_data);
6540 h->hba_inquiry_data = NULL;
6541 }
6542}
6543
6f039790 6544static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6545{
1df8552a 6546 int rc, i;
4c2a8c40
SC		 6547
6548 if (!reset_devices)
6549 return 0;
6550
1df8552a
SC		 6551 /* Reset the controller with a PCI power-cycle or via doorbell */
6552 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6553
1df8552a
SC		 6554 /* -ENOTSUPP here means we cannot reset the controller
6555 * but it's already (and still) up and running in
18867659
SC		 6556 * "performant mode". Or, it might be 640x, which can't reset
6557 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6558 */
6559 if (rc == -ENOTSUPP)
64670ac8 6560 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6561 if (rc)
6562 return -ENODEV;
4c2a8c40
SC		 6563
6564 /* Now try to get the controller to respond to a no-op */
2b870cb3 6565 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6566 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6567 if (hpsa_noop(pdev) == 0)
6568 break;
6569 else
6570 dev_warn(&pdev->dev, "no-op failed%s\n",
6571 (i < 11 ? "; re-trying" : ""));
6572 }
6573 return 0;
6574}
6575
6f039790 6576static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6577{
6578 h->cmd_pool_bits = kzalloc(
6579 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6580 sizeof(unsigned long), GFP_KERNEL);
6581 h->cmd_pool = pci_alloc_consistent(h->pdev,
6582 h->nr_cmds * sizeof(*h->cmd_pool),
6583 &(h->cmd_pool_dhandle));
6584 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6585 h->nr_cmds * sizeof(*h->errinfo_pool),
6586 &(h->errinfo_pool_dhandle));
6587 if ((h->cmd_pool_bits == NULL)
6588 || (h->cmd_pool == NULL)
6589 || (h->errinfo_pool == NULL)) {
6590 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6591 return -ENOMEM;
6592 }
6593 return 0;
6594}
6595
6596static void hpsa_free_cmd_pool(struct ctlr_info *h)
6597{
6598 kfree(h->cmd_pool_bits);
6599 if (h->cmd_pool)
6600 pci_free_consistent(h->pdev,
6601 h->nr_cmds * sizeof(struct CommandList),
6602 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6603 if (h->ioaccel2_cmd_pool)
6604 pci_free_consistent(h->pdev,
6605 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6606 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6607 if (h->errinfo_pool)
6608 pci_free_consistent(h->pdev,
6609 h->nr_cmds * sizeof(struct ErrorInfo),
6610 h->errinfo_pool,
6611 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6612 if (h->ioaccel_cmd_pool)
6613 pci_free_consistent(h->pdev,
6614 h->nr_cmds * sizeof(struct io_accel1_cmd),
6615 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6616}
6617
41b3cf08
SC		 6618static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6619{
6620 int i, cpu, rc;
6621
6622 cpu = cpumask_first(cpu_online_mask);
6623 for (i = 0; i < h->msix_vector; i++) {
6624 rc = irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
6625 cpu = cpumask_next(cpu, cpu_online_mask);
6626 }
6627}
6628
0ae01a32
SC		 6629static int hpsa_request_irq(struct ctlr_info *h,
6630 irqreturn_t (*msixhandler)(int, void *),
6631 irqreturn_t (*intxhandler)(int, void *))
6632{
254f796b 6633 int rc, i;
0ae01a32 6634
254f796b
MG		 6635 /*
6636 * initialize h->q[x] = x so that interrupt handlers know which
6637 * queue to process.
6638 */
6639 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6640 h->q[i] = (u8) i;
6641
eee0f03a 6642 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6643 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6644 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6645 rc = request_irq(h->intr[i], msixhandler,
6646 0, h->devname,
6647 &h->q[i]);
41b3cf08 6648 hpsa_irq_affinity_hints(h);
254f796b
MG		 6649 } else {
6650 /* Use single reply pool */
eee0f03a 6651 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6652 rc = request_irq(h->intr[h->intr_mode],
6653 msixhandler, 0, h->devname,
6654 &h->q[h->intr_mode]);
6655 } else {
6656 rc = request_irq(h->intr[h->intr_mode],
6657 intxhandler, IRQF_SHARED, h->devname,
6658 &h->q[h->intr_mode]);
6659 }
6660 }
0ae01a32
SC		 6661 if (rc) {
6662 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6663 h->intr[h->intr_mode], h->devname);
6664 return -ENODEV;
6665 }
6666 return 0;
6667}
6668
6f039790 6669static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6670{
6671 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6672 HPSA_RESET_TYPE_CONTROLLER)) {
6673 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6674 return -EIO;
6675 }
6676
6677 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6678 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6679 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6680 return -1;
6681 }
6682
6683 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6684 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6685 dev_warn(&h->pdev->dev, "Board failed to become ready "
6686 "after soft reset.\n");
6687 return -1;
6688 }
6689
6690 return 0;
6691}
6692
254f796b
MG		 6693static void free_irqs(struct ctlr_info *h)
6694{
6695 int i;
6696
6697 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6698 /* Single reply queue, only one irq to free */
6699 i = h->intr_mode;
41b3cf08 6700 irq_set_affinity_hint(h->intr[i], NULL);
254f796b
MG		 6701 free_irq(h->intr[i], &h->q[i]);
6702 return;
6703 }
6704
41b3cf08
SC		 6705 for (i = 0; i < h->msix_vector; i++) {
6706 irq_set_affinity_hint(h->intr[i], NULL);
254f796b 6707 free_irq(h->intr[i], &h->q[i]);
41b3cf08 6708 }
254f796b
MG		 6709}
6710
0097f0f4 6711static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6712{
254f796b 6713 free_irqs(h);
64670ac8 6714#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6715 if (h->msix_vector) {
6716 if (h->pdev->msix_enabled)
6717 pci_disable_msix(h->pdev);
6718 } else if (h->msi_vector) {
6719 if (h->pdev->msi_enabled)
6720 pci_disable_msi(h->pdev);
6721 }
64670ac8 6722#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6723}
6724
072b0518
SC		 6725static void hpsa_free_reply_queues(struct ctlr_info *h)
6726{
6727 int i;
6728
6729 for (i = 0; i < h->nreply_queues; i++) {
6730 if (!h->reply_queue[i].head)
6731 continue;
6732 pci_free_consistent(h->pdev, h->reply_queue_size,
6733 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6734 h->reply_queue[i].head = NULL;
6735 h->reply_queue[i].busaddr = 0;
6736 }
6737}
6738
0097f0f4
SC		 6739static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6740{
6741 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6742 hpsa_free_sg_chain_blocks(h);
6743 hpsa_free_cmd_pool(h);
e1f7de0c 6744 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6745 kfree(h->blockFetchTable);
072b0518 6746 hpsa_free_reply_queues(h);
64670ac8
SC		 6747 if (h->vaddr)
6748 iounmap(h->vaddr);
6749 if (h->transtable)
6750 iounmap(h->transtable);
6751 if (h->cfgtable)
6752 iounmap(h->cfgtable);
6753 pci_release_regions(h->pdev);
6754 kfree(h);
6755}
6756
a0c12413
SC		 6757/* Called when controller lockup detected. */
6758static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6759{
6760 struct CommandList *c = NULL;
6761
6762 assert_spin_locked(&h->lock);
6763 /* Mark all outstanding commands as failed and complete them. */
6764 while (!list_empty(list)) {
6765 c = list_entry(list->next, struct CommandList, list);
6766 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6767 finish_cmd(c);
a0c12413
SC		 6768 }
6769}
6770
094963da
SC		 6771static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6772{
6773 int i, cpu;
6774
6775 cpu = cpumask_first(cpu_online_mask);
6776 for (i = 0; i < num_online_cpus(); i++) {
6777 u32 *lockup_detected;
6778 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6779 *lockup_detected = value;
6780 cpu = cpumask_next(cpu, cpu_online_mask);
6781 }
6782 wmb(); /* be sure the per-cpu variables are out to memory */
6783}
6784
a0c12413
SC		 6785static void controller_lockup_detected(struct ctlr_info *h)
6786{
6787 unsigned long flags;
094963da 6788 u32 lockup_detected;
a0c12413 6789
a0c12413
SC		 6790 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6791 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6792 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6793 if (!lockup_detected) {
6794 /* no heartbeat, but controller gave us a zero. */
6795 dev_warn(&h->pdev->dev,
6796 "lockup detected but scratchpad register is zero\n");
6797 lockup_detected = 0xffffffff;
6798 }
6799 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6800 spin_unlock_irqrestore(&h->lock, flags);
6801 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6802 lockup_detected);
a0c12413
SC		 6803 pci_disable_device(h->pdev);
6804 spin_lock_irqsave(&h->lock, flags);
6805 fail_all_cmds_on_list(h, &h->cmpQ);
6806 fail_all_cmds_on_list(h, &h->reqQ);
6807 spin_unlock_irqrestore(&h->lock, flags);
6808}
6809
a0c12413
SC		 6810static void detect_controller_lockup(struct ctlr_info *h)
6811{
6812 u64 now;
6813 u32 heartbeat;
6814 unsigned long flags;
6815
a0c12413
SC		 6816 now = get_jiffies_64();
6817 /* If we've received an interrupt recently, we're ok. */
6818 if (time_after64(h->last_intr_timestamp +
e85c5974 6819 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6820 return;
6821
6822 /*
6823 * If we've already checked the heartbeat recently, we're ok.
6824 * This could happen if someone sends us a signal. We
6825 * otherwise don't care about signals in this thread.
6826 */
6827 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6828 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6829 return;
6830
6831 /* If heartbeat has not changed since we last looked, we're not ok. */
6832 spin_lock_irqsave(&h->lock, flags);
6833 heartbeat = readl(&h->cfgtable->HeartBeat);
6834 spin_unlock_irqrestore(&h->lock, flags);
6835 if (h->last_heartbeat == heartbeat) {
6836 controller_lockup_detected(h);
6837 return;
6838 }
6839
6840 /* We're ok. */
6841 h->last_heartbeat = heartbeat;
6842 h->last_heartbeat_timestamp = now;
6843}
6844
9846590e 6845static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6846{
6847 int i;
6848 char *event_type;
6849
e863d68e
ST		 6850 /* Clear the driver-requested rescan flag */
6851 h->drv_req_rescan = 0;
6852
76438d08 6853 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6854 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6855 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6856 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6857 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6858
6859 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6860 event_type = "state change";
6861 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6862 event_type = "configuration change";
6863 /* Stop sending new RAID offload reqs via the IO accelerator */
6864 scsi_block_requests(h->scsi_host);
6865 for (i = 0; i < h->ndevices; i++)
6866 h->dev[i]->offload_enabled = 0;
23100dd9 6867 hpsa_drain_accel_commands(h);
76438d08
SC		 6868 /* Set 'accelerator path config change' bit */
6869 dev_warn(&h->pdev->dev,
6870 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6871 h->events, event_type);
6872 writel(h->events, &(h->cfgtable->clear_event_notify));
6873 /* Set the "clear event notify field update" bit 6 */
6874 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6875 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6876 hpsa_wait_for_clear_event_notify_ack(h);
6877 scsi_unblock_requests(h->scsi_host);
6878 } else {
6879 /* Acknowledge controller notification events. */
6880 writel(h->events, &(h->cfgtable->clear_event_notify));
6881 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6882 hpsa_wait_for_clear_event_notify_ack(h);
6883#if 0
6884 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6885 hpsa_wait_for_mode_change_ack(h);
6886#endif
6887 }
9846590e 6888 return;
76438d08
SC		 6889}
6890
6891/* Check a register on the controller to see if there are configuration
6892 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6893 * we should rescan the controller for devices.
6894 * Also check flag for driver-initiated rescan.
76438d08 6895 */
9846590e 6896static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6897{
9846590e
SC		 6898 if (h->drv_req_rescan)
6899 return 1;
6900
76438d08 6901 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6902 return 0;
76438d08
SC		 6903
6904 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6905 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6906}
76438d08 6907
9846590e
SC		 6908/*
6909 * Check if any of the offline devices have become ready
6910 */
6911static int hpsa_offline_devices_ready(struct ctlr_info *h)
6912{
6913 unsigned long flags;
6914 struct offline_device_entry *d;
6915 struct list_head *this, *tmp;
6916
6917 spin_lock_irqsave(&h->offline_device_lock, flags);
6918 list_for_each_safe(this, tmp, &h->offline_device_list) {
6919 d = list_entry(this, struct offline_device_entry,
6920 offline_list);
6921 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6922 if (!hpsa_volume_offline(h, d->scsi3addr))
6923 return 1;
6924 spin_lock_irqsave(&h->offline_device_lock, flags);
6925 }
6926 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6927 return 0;
76438d08
SC		 6928}
6929
9846590e 6930
8a98db73 6931static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6932{
6933 unsigned long flags;
8a98db73
SC		 6934 struct ctlr_info *h = container_of(to_delayed_work(work),
6935 struct ctlr_info, monitor_ctlr_work);
6936 detect_controller_lockup(h);
094963da 6937 if (lockup_detected(h))
8a98db73 6938 return;
9846590e
SC		 6939
6940 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6941 scsi_host_get(h->scsi_host);
6942 h->drv_req_rescan = 0;
6943 hpsa_ack_ctlr_events(h);
6944 hpsa_scan_start(h->scsi_host);
6945 scsi_host_put(h->scsi_host);
6946 }
6947
8a98db73
SC		 6948 spin_lock_irqsave(&h->lock, flags);
6949 if (h->remove_in_progress) {
6950 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6951 return;
6952 }
8a98db73
SC		 6953 schedule_delayed_work(&h->monitor_ctlr_work,
6954 h->heartbeat_sample_interval);
6955 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6956}
6957
6f039790 6958static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6959{
4c2a8c40 6960 int dac, rc;
edd16368 6961 struct ctlr_info *h;
64670ac8
SC		 6962 int try_soft_reset = 0;
6963 unsigned long flags;
edd16368
SC		 6964
6965 if (number_of_controllers == 0)
6966 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6967
4c2a8c40 6968 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6969 if (rc) {
6970 if (rc != -ENOTSUPP)
6971 return rc;
6972 /* If the reset fails in a particular way (it has no way to do
6973 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6974 * a soft reset once we get the controller configured up to the
6975 * point that it can accept a command.
6976 */
6977 try_soft_reset = 1;
6978 rc = 0;
6979 }
6980
6981reinit_after_soft_reset:
edd16368 6982
303932fd
DB		 6983 /* Command structures must be aligned on a 32-byte boundary because
6984 * the 5 lower bits of the address are used by the hardware. and by
6985 * the driver. See comments in hpsa.h for more info.
6986 */
303932fd 6987 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6988 h = kzalloc(sizeof(*h), GFP_KERNEL);
6989 if (!h)
ecd9aad4 6990 return -ENOMEM;
edd16368 6991
55c06c71 6992 h->pdev = pdev;
a9a3a273 6993 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6994 INIT_LIST_HEAD(&h->cmpQ);
6995 INIT_LIST_HEAD(&h->reqQ);
9846590e 6996 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6997 spin_lock_init(&h->lock);
9846590e 6998 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6999 spin_lock_init(&h->scan_lock);
0390f0c0 7000 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 7001
7002 /* Allocate and clear per-cpu variable lockup_detected */
7003 h->lockup_detected = alloc_percpu(u32);
7004 if (!h->lockup_detected)
7005 goto clean1;
7006 set_lockup_detected_for_all_cpus(h, 0);
7007
55c06c71 7008 rc = hpsa_pci_init(h);
ecd9aad4 7009 if (rc != 0)
edd16368
SC		 7010 goto clean1;
7011
f79cfec6 7012 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7013 h->ctlr = number_of_controllers;
7014 number_of_controllers++;
edd16368
SC		 7015
7016 /* configure PCI DMA stuff */
ecd9aad4
SC		 7017 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7018 if (rc == 0) {
edd16368 7019 dac = 1;
ecd9aad4
SC		 7020 } else {
7021 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7022 if (rc == 0) {
7023 dac = 0;
7024 } else {
7025 dev_err(&pdev->dev, "no suitable DMA available\n");
7026 goto clean1;
7027 }
edd16368
SC		 7028 }
7029
7030 /* make sure the board interrupts are off */
7031 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7032
0ae01a32 7033 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7034 goto clean2;
303932fd
DB		 7035 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7036 h->devname, pdev->device,
a9a3a273 7037 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 7038 if (hpsa_allocate_cmd_pool(h))
edd16368 7039 goto clean4;
33a2ffce
SC		 7040 if (hpsa_allocate_sg_chain_blocks(h))
7041 goto clean4;
a08a8471
SC		 7042 init_waitqueue_head(&h->scan_wait_queue);
7043 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7044
7045 pci_set_drvdata(pdev, h);
9a41338e 7046 h->ndevices = 0;
316b221a 7047 h->hba_mode_enabled = 0;
9a41338e
SC		 7048 h->scsi_host = NULL;
7049 spin_lock_init(&h->devlock);
64670ac8
SC		 7050 hpsa_put_ctlr_into_performant_mode(h);
7051
7052 /* At this point, the controller is ready to take commands.
7053 * Now, if reset_devices and the hard reset didn't work, try
7054 * the soft reset and see if that works.
7055 */
7056 if (try_soft_reset) {
7057
7058 /* This is kind of gross. We may or may not get a completion
7059 * from the soft reset command, and if we do, then the value
7060 * from the fifo may or may not be valid. So, we wait 10 secs
7061 * after the reset throwing away any completions we get during
7062 * that time. Unregister the interrupt handler and register
7063 * fake ones to scoop up any residual completions.
7064 */
7065 spin_lock_irqsave(&h->lock, flags);
7066 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7067 spin_unlock_irqrestore(&h->lock, flags);
254f796b 7068 free_irqs(h);
64670ac8
SC		 7069 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
7070 hpsa_intx_discard_completions);
7071 if (rc) {
7072 dev_warn(&h->pdev->dev, "Failed to request_irq after "
7073 "soft reset.\n");
7074 goto clean4;
7075 }
7076
7077 rc = hpsa_kdump_soft_reset(h);
7078 if (rc)
7079 /* Neither hard nor soft reset worked, we're hosed. */
7080 goto clean4;
7081
7082 dev_info(&h->pdev->dev, "Board READY.\n");
7083 dev_info(&h->pdev->dev,
7084 "Waiting for stale completions to drain.\n");
7085 h->access.set_intr_mask(h, HPSA_INTR_ON);
7086 msleep(10000);
7087 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7088
7089 rc = controller_reset_failed(h->cfgtable);
7090 if (rc)
7091 dev_info(&h->pdev->dev,
7092 "Soft reset appears to have failed.\n");
7093
7094 /* since the controller's reset, we have to go back and re-init
7095 * everything. Easiest to just forget what we've done and do it
7096 * all over again.
7097 */
7098 hpsa_undo_allocations_after_kdump_soft_reset(h);
7099 try_soft_reset = 0;
7100 if (rc)
7101 /* don't go to clean4, we already unallocated */
7102 return -ENODEV;
7103
7104 goto reinit_after_soft_reset;
7105 }
edd16368 7106
316b221a
SC		 7107 /* Enable Accelerated IO path at driver layer */
7108 h->acciopath_status = 1;
da0697bd 7109
e863d68e
ST		 7110 h->drv_req_rescan = 0;
7111
edd16368
SC		 7112 /* Turn the interrupts on so we can service requests */
7113 h->access.set_intr_mask(h, HPSA_INTR_ON);
7114
339b2b14 7115 hpsa_hba_inquiry(h);
edd16368 7116 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7117
7118 /* Monitor the controller for firmware lockups */
7119 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7120 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7121 schedule_delayed_work(&h->monitor_ctlr_work,
7122 h->heartbeat_sample_interval);
88bf6d62 7123 return 0;
edd16368
SC		 7124
7125clean4:
33a2ffce 7126 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7127 hpsa_free_cmd_pool(h);
254f796b 7128 free_irqs(h);
edd16368
SC		 7129clean2:
7130clean1:
094963da
SC		 7131 if (h->lockup_detected)
7132 free_percpu(h->lockup_detected);
edd16368 7133 kfree(h);
ecd9aad4 7134 return rc;
edd16368
SC		 7135}
7136
7137static void hpsa_flush_cache(struct ctlr_info *h)
7138{
7139 char *flush_buf;
7140 struct CommandList *c;
702890e3
SC		 7141
7142 /* Don't bother trying to flush the cache if locked up */
094963da 7143 if (unlikely(lockup_detected(h)))
702890e3 7144 return;
edd16368
SC		 7145 flush_buf = kzalloc(4, GFP_KERNEL);
7146 if (!flush_buf)
7147 return;
7148
7149 c = cmd_special_alloc(h);
7150 if (!c) {
7151 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
7152 goto out_of_memory;
7153 }
a2dac136
SC		 7154 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7155 RAID_CTLR_LUNID, TYPE_CMD)) {
7156 goto out;
7157 }
edd16368
SC		 7158 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7159 if (c->err_info->CommandStatus != 0)
a2dac136 7160out:
edd16368
SC		 7161 dev_warn(&h->pdev->dev,
7162 "error flushing cache on controller\n");
7163 cmd_special_free(h, c);
7164out_of_memory:
7165 kfree(flush_buf);
7166}
7167
7168static void hpsa_shutdown(struct pci_dev *pdev)
7169{
7170 struct ctlr_info *h;
7171
7172 h = pci_get_drvdata(pdev);
7173 /* Turn board interrupts off and send the flush cache command
7174 * sendcmd will turn off interrupt, and send the flush...
7175 * To write all data in the battery backed cache to disks
7176 */
7177 hpsa_flush_cache(h);
7178 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7179 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7180}
7181
6f039790 7182static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7183{
7184 int i;
7185
7186 for (i = 0; i < h->ndevices; i++)
7187 kfree(h->dev[i]);
7188}
7189
6f039790 7190static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7191{
7192 struct ctlr_info *h;
8a98db73 7193 unsigned long flags;
edd16368
SC		 7194
7195 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7196 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7197 return;
7198 }
7199 h = pci_get_drvdata(pdev);
8a98db73
SC		 7200
7201 /* Get rid of any controller monitoring work items */
7202 spin_lock_irqsave(&h->lock, flags);
7203 h->remove_in_progress = 1;
7204 cancel_delayed_work(&h->monitor_ctlr_work);
7205 spin_unlock_irqrestore(&h->lock, flags);
7206
edd16368
SC		 7207 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7208 hpsa_shutdown(pdev);
7209 iounmap(h->vaddr);
204892e9
SC		 7210 iounmap(h->transtable);
7211 iounmap(h->cfgtable);
55e14e76 7212 hpsa_free_device_info(h);
33a2ffce 7213 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7214 pci_free_consistent(h->pdev,
7215 h->nr_cmds * sizeof(struct CommandList),
7216 h->cmd_pool, h->cmd_pool_dhandle);
7217 pci_free_consistent(h->pdev,
7218 h->nr_cmds * sizeof(struct ErrorInfo),
7219 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7220 hpsa_free_reply_queues(h);
edd16368 7221 kfree(h->cmd_pool_bits);
303932fd 7222 kfree(h->blockFetchTable);
e1f7de0c 7223 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7224 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7225 kfree(h->hba_inquiry_data);
f0bd0b68 7226 pci_disable_device(pdev);
edd16368 7227 pci_release_regions(pdev);
094963da 7228 free_percpu(h->lockup_detected);
edd16368
SC		 7229 kfree(h);
7230}
7231
7232static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7233 __attribute__((unused)) pm_message_t state)
7234{
7235 return -ENOSYS;
7236}
7237
7238static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7239{
7240 return -ENOSYS;
7241}
7242
7243static struct pci_driver hpsa_pci_driver = {
f79cfec6 7244 .name = HPSA,
edd16368 7245 .probe = hpsa_init_one,
6f039790 7246 .remove = hpsa_remove_one,
edd16368
SC		 7247 .id_table = hpsa_pci_device_id, /* id_table */
7248 .shutdown = hpsa_shutdown,
7249 .suspend = hpsa_suspend,
7250 .resume = hpsa_resume,
7251};
7252
303932fd
DB		 7253/* Fill in bucket_map[], given nsgs (the max number of
7254 * scatter gather elements supported) and bucket[],
7255 * which is an array of 8 integers. The bucket[] array
7256 * contains 8 different DMA transfer sizes (in 16
7257 * byte increments) which the controller uses to fetch
7258 * commands. This function fills in bucket_map[], which
7259 * maps a given number of scatter gather elements to one of
7260 * the 8 DMA transfer sizes. The point of it is to allow the
7261 * controller to only do as much DMA as needed to fetch the
7262 * command, with the DMA transfer size encoded in the lower
7263 * bits of the command address.
7264 */
7265static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7266 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7267{
7268 int i, j, b, size;
7269
303932fd
DB		 7270 /* Note, bucket_map must have nsgs+1 entries. */
7271 for (i = 0; i <= nsgs; i++) {
7272 /* Compute size of a command with i SG entries */
e1f7de0c 7273 size = i + min_blocks;
303932fd
DB		 7274 b = num_buckets; /* Assume the biggest bucket */
7275 /* Find the bucket that is just big enough */
e1f7de0c 7276 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7277 if (bucket[j] >= size) {
7278 b = j;
7279 break;
7280 }
7281 }
7282 /* for a command with i SG entries, use bucket b. */
7283 bucket_map[i] = b;
7284 }
7285}
7286
e1f7de0c 7287static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7288{
6c311b57
SC		 7289 int i;
7290 unsigned long register_value;
e1f7de0c
MG		 7291 unsigned long transMethod = CFGTBL_Trans_Performant |
7292 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7293 CFGTBL_Trans_enable_directed_msix |
7294 (trans_support & (CFGTBL_Trans_io_accel1 |
7295 CFGTBL_Trans_io_accel2));
e1f7de0c 7296 struct access_method access = SA5_performant_access;
def342bd
SC		 7297
7298 /* This is a bit complicated. There are 8 registers on
7299 * the controller which we write to to tell it 8 different
7300 * sizes of commands which there may be. It's a way of
7301 * reducing the DMA done to fetch each command. Encoded into
7302 * each command's tag are 3 bits which communicate to the controller
7303 * which of the eight sizes that command fits within. The size of
7304 * each command depends on how many scatter gather entries there are.
7305 * Each SG entry requires 16 bytes. The eight registers are programmed
7306 * with the number of 16-byte blocks a command of that size requires.
7307 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7308 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7309 * blocks. Note, this only extends to the SG entries contained
7310 * within the command block, and does not extend to chained blocks
7311 * of SG elements. bft[] contains the eight values we write to
7312 * the registers. They are not evenly distributed, but have more
7313 * sizes for small commands, and fewer sizes for larger commands.
7314 */
d66ae08b 7315 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7316#define MIN_IOACCEL2_BFT_ENTRY 5
7317#define HPSA_IOACCEL2_HEADER_SZ 4
7318 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7319 13, 14, 15, 16, 17, 18, 19,
7320 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7321 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7322 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7323 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7324 16 * MIN_IOACCEL2_BFT_ENTRY);
7325 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7326 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7327 /* 5 = 1 s/g entry or 4k
7328 * 6 = 2 s/g entry or 8k
7329 * 8 = 4 s/g entry or 16k
7330 * 10 = 6 s/g entry or 24k
7331 */
303932fd 7332
303932fd 7333 /* Controller spec: zero out this buffer. */
072b0518
SC		 7334 for (i = 0; i < h->nreply_queues; i++)
7335 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7336
d66ae08b
SC		 7337 bft[7] = SG_ENTRIES_IN_CMD + 4;
7338 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7339 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7340 for (i = 0; i < 8; i++)
7341 writel(bft[i], &h->transtable->BlockFetch[i]);
7342
7343 /* size of controller ring buffer */
7344 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7345 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7346 writel(0, &h->transtable->RepQCtrAddrLow32);
7347 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7348
7349 for (i = 0; i < h->nreply_queues; i++) {
7350 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7351 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7352 &h->transtable->RepQAddr[i].lower);
7353 }
7354
b9af4937 7355 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7356 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7357 /*
7358 * enable outbound interrupt coalescing in accelerator mode;
7359 */
7360 if (trans_support & CFGTBL_Trans_io_accel1) {
7361 access = SA5_ioaccel_mode1_access;
7362 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7363 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7364 } else {
7365 if (trans_support & CFGTBL_Trans_io_accel2) {
7366 access = SA5_ioaccel_mode2_access;
7367 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7368 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7369 }
e1f7de0c 7370 }
303932fd 7371 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7372 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7373 register_value = readl(&(h->cfgtable->TransportActive));
7374 if (!(register_value & CFGTBL_Trans_Performant)) {
7375 dev_warn(&h->pdev->dev, "unable to get board into"
7376 " performant mode\n");
7377 return;
7378 }
960a30e7 7379 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7380 h->access = access;
7381 h->transMethod = transMethod;
7382
b9af4937
SC		 7383 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7384 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7385 return;
7386
b9af4937
SC		 7387 if (trans_support & CFGTBL_Trans_io_accel1) {
7388 /* Set up I/O accelerator mode */
7389 for (i = 0; i < h->nreply_queues; i++) {
7390 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7391 h->reply_queue[i].current_entry =
7392 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7393 }
7394 bft[7] = h->ioaccel_maxsg + 8;
7395 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7396 h->ioaccel1_blockFetchTable);
e1f7de0c 7397
b9af4937 7398 /* initialize all reply queue entries to unused */
072b0518
SC		 7399 for (i = 0; i < h->nreply_queues; i++)
7400 memset(h->reply_queue[i].head,
7401 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7402 h->reply_queue_size);
e1f7de0c 7403
b9af4937
SC		 7404 /* set all the constant fields in the accelerator command
7405 * frames once at init time to save CPU cycles later.
7406 */
7407 for (i = 0; i < h->nr_cmds; i++) {
7408 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7409
7410 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7411 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7412 (i * sizeof(struct ErrorInfo)));
7413 cp->err_info_len = sizeof(struct ErrorInfo);
7414 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7415 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7416 cp->timeout_sec = 0;
7417 cp->ReplyQueue = 0;
7418 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
7419 DIRECT_LOOKUP_BIT;
7420 cp->Tag.upper = 0;
7421 cp->host_addr.lower =
7422 (u32) (h->ioaccel_cmd_pool_dhandle +
7423 (i * sizeof(struct io_accel1_cmd)));
7424 cp->host_addr.upper = 0;
7425 }
7426 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7427 u64 cfg_offset, cfg_base_addr_index;
7428 u32 bft2_offset, cfg_base_addr;
7429 int rc;
7430
7431 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7432 &cfg_base_addr_index, &cfg_offset);
7433 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7434 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7435 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7436 4, h->ioaccel2_blockFetchTable);
7437 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7438 BUILD_BUG_ON(offsetof(struct CfgTable,
7439 io_accel_request_size_offset) != 0xb8);
7440 h->ioaccel2_bft2_regs =
7441 remap_pci_mem(pci_resource_start(h->pdev,
7442 cfg_base_addr_index) +
7443 cfg_offset + bft2_offset,
7444 ARRAY_SIZE(bft2) *
7445 sizeof(*h->ioaccel2_bft2_regs));
7446 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7447 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7448 }
b9af4937
SC		 7449 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7450 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7451}
7452
7453static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7454{
283b4a9b
SC		 7455 h->ioaccel_maxsg =
7456 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7457 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7458 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7459
e1f7de0c
MG		 7460 /* Command structures must be aligned on a 128-byte boundary
7461 * because the 7 lower bits of the address are used by the
7462 * hardware.
7463 */
e1f7de0c
MG		 7464 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7465 IOACCEL1_COMMANDLIST_ALIGNMENT);
7466 h->ioaccel_cmd_pool =
7467 pci_alloc_consistent(h->pdev,
7468 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7469 &(h->ioaccel_cmd_pool_dhandle));
7470
7471 h->ioaccel1_blockFetchTable =
283b4a9b 7472 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7473 sizeof(u32)), GFP_KERNEL);
7474
7475 if ((h->ioaccel_cmd_pool == NULL) ||
7476 (h->ioaccel1_blockFetchTable == NULL))
7477 goto clean_up;
7478
7479 memset(h->ioaccel_cmd_pool, 0,
7480 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7481 return 0;
7482
7483clean_up:
7484 if (h->ioaccel_cmd_pool)
7485 pci_free_consistent(h->pdev,
7486 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7487 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7488 kfree(h->ioaccel1_blockFetchTable);
7489 return 1;
6c311b57
SC		 7490}
7491
aca9012a
SC		 7492static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7493{
7494 /* Allocate ioaccel2 mode command blocks and block fetch table */
7495
7496 h->ioaccel_maxsg =
7497 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7498 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7499 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7500
aca9012a
SC		 7501 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7502 IOACCEL2_COMMANDLIST_ALIGNMENT);
7503 h->ioaccel2_cmd_pool =
7504 pci_alloc_consistent(h->pdev,
7505 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7506 &(h->ioaccel2_cmd_pool_dhandle));
7507
7508 h->ioaccel2_blockFetchTable =
7509 kmalloc(((h->ioaccel_maxsg + 1) *
7510 sizeof(u32)), GFP_KERNEL);
7511
7512 if ((h->ioaccel2_cmd_pool == NULL) ||
7513 (h->ioaccel2_blockFetchTable == NULL))
7514 goto clean_up;
7515
7516 memset(h->ioaccel2_cmd_pool, 0,
7517 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7518 return 0;
7519
7520clean_up:
7521 if (h->ioaccel2_cmd_pool)
7522 pci_free_consistent(h->pdev,
7523 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7524 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7525 kfree(h->ioaccel2_blockFetchTable);
7526 return 1;
7527}
7528
6f039790 7529static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7530{
7531 u32 trans_support;
e1f7de0c
MG		 7532 unsigned long transMethod = CFGTBL_Trans_Performant |
7533 CFGTBL_Trans_use_short_tags;
254f796b 7534 int i;
6c311b57 7535
02ec19c8
SC		 7536 if (hpsa_simple_mode)
7537 return;
7538
67c99a72 7539 trans_support = readl(&(h->cfgtable->TransportSupport));
7540 if (!(trans_support & PERFORMANT_MODE))
7541 return;
7542
e1f7de0c
MG		 7543 /* Check for I/O accelerator mode support */
7544 if (trans_support & CFGTBL_Trans_io_accel1) {
7545 transMethod |= CFGTBL_Trans_io_accel1 |
7546 CFGTBL_Trans_enable_directed_msix;
7547 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7548 goto clean_up;
aca9012a
SC		 7549 } else {
7550 if (trans_support & CFGTBL_Trans_io_accel2) {
7551 transMethod |= CFGTBL_Trans_io_accel2 |
7552 CFGTBL_Trans_enable_directed_msix;
7553 if (ioaccel2_alloc_cmds_and_bft(h))
7554 goto clean_up;
7555 }
e1f7de0c
MG		 7556 }
7557
eee0f03a 7558 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7559 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7560 /* Performant mode ring buffer and supporting data structures */
072b0518 7561 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7562
254f796b 7563 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7564 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7565 h->reply_queue_size,
7566 &(h->reply_queue[i].busaddr));
7567 if (!h->reply_queue[i].head)
7568 goto clean_up;
254f796b
MG		 7569 h->reply_queue[i].size = h->max_commands;
7570 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7571 h->reply_queue[i].current_entry = 0;
7572 }
7573
6c311b57 7574 /* Need a block fetch table for performant mode */
d66ae08b 7575 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7576 sizeof(u32)), GFP_KERNEL);
072b0518 7577 if (!h->blockFetchTable)
6c311b57
SC		 7578 goto clean_up;
7579
e1f7de0c 7580 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7581 return;
7582
7583clean_up:
072b0518 7584 hpsa_free_reply_queues(h);
303932fd
DB		 7585 kfree(h->blockFetchTable);
7586}
7587
23100dd9 7588static int is_accelerated_cmd(struct CommandList *c)
76438d08 7589{
23100dd9
SC		 7590 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7591}
7592
7593static void hpsa_drain_accel_commands(struct ctlr_info *h)
7594{
7595 struct CommandList *c = NULL;
76438d08 7596 unsigned long flags;
23100dd9 7597 int accel_cmds_out;
76438d08
SC		 7598
7599 do { /* wait for all outstanding commands to drain out */
23100dd9 7600 accel_cmds_out = 0;
76438d08 7601 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7602 list_for_each_entry(c, &h->cmpQ, list)
7603 accel_cmds_out += is_accelerated_cmd(c);
7604 list_for_each_entry(c, &h->reqQ, list)
7605 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7606 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7607 if (accel_cmds_out <= 0)
76438d08
SC		 7608 break;
7609 msleep(100);
7610 } while (1);
7611}
7612
edd16368
SC		 7613/*
7614 * This is it. Register the PCI driver information for the cards we control
7615 * the OS will call our registered routines when it finds one of our cards.
7616 */
7617static int __init hpsa_init(void)
7618{
31468401 7619 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7620}
7621
7622static void __exit hpsa_cleanup(void)
7623{
7624 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7625}
7626
e1f7de0c
MG		 7627static void __attribute__((unused)) verify_offsets(void)
7628{
dd0e19f3
ST		 7629#define VERIFY_OFFSET(member, offset) \
7630 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7631
7632 VERIFY_OFFSET(structure_size, 0);
7633 VERIFY_OFFSET(volume_blk_size, 4);
7634 VERIFY_OFFSET(volume_blk_cnt, 8);
7635 VERIFY_OFFSET(phys_blk_shift, 16);
7636 VERIFY_OFFSET(parity_rotation_shift, 17);
7637 VERIFY_OFFSET(strip_size, 18);
7638 VERIFY_OFFSET(disk_starting_blk, 20);
7639 VERIFY_OFFSET(disk_blk_cnt, 28);
7640 VERIFY_OFFSET(data_disks_per_row, 36);
7641 VERIFY_OFFSET(metadata_disks_per_row, 38);
7642 VERIFY_OFFSET(row_cnt, 40);
7643 VERIFY_OFFSET(layout_map_count, 42);
7644 VERIFY_OFFSET(flags, 44);
7645 VERIFY_OFFSET(dekindex, 46);
7646 /* VERIFY_OFFSET(reserved, 48 */
7647 VERIFY_OFFSET(data, 64);
7648
7649#undef VERIFY_OFFSET
7650
b66cc250
MM		 7651#define VERIFY_OFFSET(member, offset) \
7652 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7653
7654 VERIFY_OFFSET(IU_type, 0);
7655 VERIFY_OFFSET(direction, 1);
7656 VERIFY_OFFSET(reply_queue, 2);
7657 /* VERIFY_OFFSET(reserved1, 3); */
7658 VERIFY_OFFSET(scsi_nexus, 4);
7659 VERIFY_OFFSET(Tag, 8);
7660 VERIFY_OFFSET(cdb, 16);
7661 VERIFY_OFFSET(cciss_lun, 32);
7662 VERIFY_OFFSET(data_len, 40);
7663 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7664 VERIFY_OFFSET(sg_count, 45);
7665 /* VERIFY_OFFSET(reserved3 */
7666 VERIFY_OFFSET(err_ptr, 48);
7667 VERIFY_OFFSET(err_len, 56);
7668 /* VERIFY_OFFSET(reserved4 */
7669 VERIFY_OFFSET(sg, 64);
7670
7671#undef VERIFY_OFFSET
7672
e1f7de0c
MG		 7673#define VERIFY_OFFSET(member, offset) \
7674 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7675
7676 VERIFY_OFFSET(dev_handle, 0x00);
7677 VERIFY_OFFSET(reserved1, 0x02);
7678 VERIFY_OFFSET(function, 0x03);
7679 VERIFY_OFFSET(reserved2, 0x04);
7680 VERIFY_OFFSET(err_info, 0x0C);
7681 VERIFY_OFFSET(reserved3, 0x10);
7682 VERIFY_OFFSET(err_info_len, 0x12);
7683 VERIFY_OFFSET(reserved4, 0x13);
7684 VERIFY_OFFSET(sgl_offset, 0x14);
7685 VERIFY_OFFSET(reserved5, 0x15);
7686 VERIFY_OFFSET(transfer_len, 0x1C);
7687 VERIFY_OFFSET(reserved6, 0x20);
7688 VERIFY_OFFSET(io_flags, 0x24);
7689 VERIFY_OFFSET(reserved7, 0x26);
7690 VERIFY_OFFSET(LUN, 0x34);
7691 VERIFY_OFFSET(control, 0x3C);
7692 VERIFY_OFFSET(CDB, 0x40);
7693 VERIFY_OFFSET(reserved8, 0x50);
7694 VERIFY_OFFSET(host_context_flags, 0x60);
7695 VERIFY_OFFSET(timeout_sec, 0x62);
7696 VERIFY_OFFSET(ReplyQueue, 0x64);
7697 VERIFY_OFFSET(reserved9, 0x65);
7698 VERIFY_OFFSET(Tag, 0x68);
7699 VERIFY_OFFSET(host_addr, 0x70);
7700 VERIFY_OFFSET(CISS_LUN, 0x78);
7701 VERIFY_OFFSET(SG, 0x78 + 8);
7702#undef VERIFY_OFFSET
7703}
7704
edd16368
SC		 7705module_init(hpsa_init);
7706module_exit(hpsa_cleanup);
ubuntu-bionic-kernel mirror