]>
Commit | Line | Data |
---|---|---|
edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
3 | * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/pci.h> | |
e5a44df8 | 26 | #include <linux/pci-aspm.h> |
edd16368 SC |
27 | #include <linux/kernel.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/timer.h> | |
edd16368 SC |
32 | #include <linux/init.h> |
33 | #include <linux/spinlock.h> | |
edd16368 SC |
34 | #include <linux/compat.h> |
35 | #include <linux/blktrace_api.h> | |
36 | #include <linux/uaccess.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/completion.h> | |
40 | #include <linux/moduleparam.h> | |
41 | #include <scsi/scsi.h> | |
42 | #include <scsi/scsi_cmnd.h> | |
43 | #include <scsi/scsi_device.h> | |
44 | #include <scsi/scsi_host.h> | |
667e23d4 | 45 | #include <scsi/scsi_tcq.h> |
edd16368 SC |
46 | #include <linux/cciss_ioctl.h> |
47 | #include <linux/string.h> | |
48 | #include <linux/bitmap.h> | |
60063497 | 49 | #include <linux/atomic.h> |
edd16368 | 50 | #include <linux/kthread.h> |
a0c12413 | 51 | #include <linux/jiffies.h> |
edd16368 SC |
52 | #include "hpsa_cmd.h" |
53 | #include "hpsa.h" | |
54 | ||
55 | /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */ | |
e481cce8 | 56 | #define HPSA_DRIVER_VERSION "3.4.0-1" |
edd16368 | 57 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 58 | #define HPSA "hpsa" |
edd16368 SC |
59 | |
60 | /* How long to wait (in milliseconds) for board to go into simple mode */ | |
61 | #define MAX_CONFIG_WAIT 30000 | |
62 | #define MAX_IOCTL_CONFIG_WAIT 1000 | |
63 | ||
64 | /*define how many times we will try a command because of bus resets */ | |
65 | #define MAX_CMD_RETRIES 3 | |
66 | ||
67 | /* Embedded module documentation macros - see modules.h */ | |
68 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
69 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
70 | HPSA_DRIVER_VERSION); | |
71 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
72 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
73 | MODULE_LICENSE("GPL"); | |
74 | ||
75 | static int hpsa_allow_any; | |
76 | module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR); | |
77 | MODULE_PARM_DESC(hpsa_allow_any, | |
78 | "Allow hpsa driver to access unknown HP Smart Array hardware"); | |
02ec19c8 SC |
79 | static int hpsa_simple_mode; |
80 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
81 | MODULE_PARM_DESC(hpsa_simple_mode, | |
82 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
83 | |
84 | /* define the PCI info for the cards we can control */ | |
85 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
86 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
87 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
88 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
89 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
90 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
91 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
92 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 93 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 94 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
95 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
fe0c9610 MM |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, | |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
7c03b870 | 121 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 122 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
edd16368 SC |
123 | {0,} |
124 | }; | |
125 | ||
126 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
127 | ||
128 | /* board_id = Subsystem Device ID & Vendor ID | |
129 | * product = Marketing Name for the board | |
130 | * access = Address of the struct of function pointers | |
131 | */ | |
132 | static struct board_type products[] = { | |
edd16368 SC |
133 | {0x3241103C, "Smart Array P212", &SA5_access}, |
134 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
135 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
136 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
137 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
138 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
139 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
fe0c9610 MM |
140 | {0x3350103C, "Smart Array P222", &SA5_access}, |
141 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
142 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
143 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
144 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
145 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
146 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
1fd6c8e3 MM |
147 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
148 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
149 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
150 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
151 | {0x1926103C, "Smart Array P731m", &SA5_access}, | |
152 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
153 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
97b9f53d MM |
154 | {0x21BD103C, "Smart Array", &SA5_access}, |
155 | {0x21BE103C, "Smart Array", &SA5_access}, | |
156 | {0x21BF103C, "Smart Array", &SA5_access}, | |
157 | {0x21C0103C, "Smart Array", &SA5_access}, | |
158 | {0x21C1103C, "Smart Array", &SA5_access}, | |
159 | {0x21C2103C, "Smart Array", &SA5_access}, | |
160 | {0x21C3103C, "Smart Array", &SA5_access}, | |
161 | {0x21C4103C, "Smart Array", &SA5_access}, | |
162 | {0x21C5103C, "Smart Array", &SA5_access}, | |
163 | {0x21C7103C, "Smart Array", &SA5_access}, | |
164 | {0x21C8103C, "Smart Array", &SA5_access}, | |
165 | {0x21C9103C, "Smart Array", &SA5_access}, | |
edd16368 SC |
166 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
167 | }; | |
168 | ||
169 | static int number_of_controllers; | |
170 | ||
10f66018 SC |
171 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
172 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
edd16368 SC |
173 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg); |
174 | static void start_io(struct ctlr_info *h); | |
175 | ||
176 | #ifdef CONFIG_COMPAT | |
177 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg); | |
178 | #endif | |
179 | ||
180 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
181 | static void cmd_special_free(struct ctlr_info *h, struct CommandList *c); | |
182 | static struct CommandList *cmd_alloc(struct ctlr_info *h); | |
183 | static struct CommandList *cmd_special_alloc(struct ctlr_info *h); | |
a2dac136 | 184 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
01a02ffc | 185 | void *buff, size_t size, u8 page_code, unsigned char *scsi3addr, |
edd16368 SC |
186 | int cmd_type); |
187 | ||
f281233d | 188 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
189 | static void hpsa_scan_start(struct Scsi_Host *); |
190 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
191 | unsigned long elapsed_time); | |
667e23d4 SC |
192 | static int hpsa_change_queue_depth(struct scsi_device *sdev, |
193 | int qdepth, int reason); | |
edd16368 SC |
194 | |
195 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
75167d2c | 196 | static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd); |
edd16368 SC |
197 | static int hpsa_slave_alloc(struct scsi_device *sdev); |
198 | static void hpsa_slave_destroy(struct scsi_device *sdev); | |
199 | ||
edd16368 | 200 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno); |
edd16368 SC |
201 | static int check_for_unit_attention(struct ctlr_info *h, |
202 | struct CommandList *c); | |
203 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
204 | struct CommandList *c); | |
303932fd DB |
205 | /* performant mode helper functions */ |
206 | static void calc_bucket_map(int *bucket, int num_buckets, | |
e1f7de0c | 207 | int nsgs, int min_blocks, int *bucket_map); |
6f039790 | 208 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); |
254f796b | 209 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
210 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
211 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
212 | u64 *cfg_offset); | |
213 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
214 | unsigned long *memory_bar); | |
215 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id); | |
216 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, | |
217 | int wait_for_ready); | |
75167d2c | 218 | static inline void finish_cmd(struct CommandList *c); |
fe5389c8 SC |
219 | #define BOARD_NOT_READY 0 |
220 | #define BOARD_READY 1 | |
edd16368 | 221 | |
edd16368 SC |
222 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
223 | { | |
224 | unsigned long *priv = shost_priv(sdev->host); | |
225 | return (struct ctlr_info *) *priv; | |
226 | } | |
227 | ||
a23513e8 SC |
228 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
229 | { | |
230 | unsigned long *priv = shost_priv(sh); | |
231 | return (struct ctlr_info *) *priv; | |
232 | } | |
233 | ||
edd16368 SC |
234 | static int check_for_unit_attention(struct ctlr_info *h, |
235 | struct CommandList *c) | |
236 | { | |
237 | if (c->err_info->SenseInfo[2] != UNIT_ATTENTION) | |
238 | return 0; | |
239 | ||
240 | switch (c->err_info->SenseInfo[12]) { | |
241 | case STATE_CHANGED: | |
f79cfec6 | 242 | dev_warn(&h->pdev->dev, HPSA "%d: a state change " |
edd16368 SC |
243 | "detected, command retried\n", h->ctlr); |
244 | break; | |
245 | case LUN_FAILED: | |
f79cfec6 | 246 | dev_warn(&h->pdev->dev, HPSA "%d: LUN failure " |
edd16368 SC |
247 | "detected, action required\n", h->ctlr); |
248 | break; | |
249 | case REPORT_LUNS_CHANGED: | |
f79cfec6 | 250 | dev_warn(&h->pdev->dev, HPSA "%d: report LUN data " |
31468401 | 251 | "changed, action required\n", h->ctlr); |
edd16368 | 252 | /* |
4f4eb9f1 ST |
253 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
254 | * target (array) devices. | |
edd16368 SC |
255 | */ |
256 | break; | |
257 | case POWER_OR_RESET: | |
f79cfec6 | 258 | dev_warn(&h->pdev->dev, HPSA "%d: a power on " |
edd16368 SC |
259 | "or device reset detected\n", h->ctlr); |
260 | break; | |
261 | case UNIT_ATTENTION_CLEARED: | |
f79cfec6 | 262 | dev_warn(&h->pdev->dev, HPSA "%d: unit attention " |
edd16368 SC |
263 | "cleared by another initiator\n", h->ctlr); |
264 | break; | |
265 | default: | |
f79cfec6 | 266 | dev_warn(&h->pdev->dev, HPSA "%d: unknown " |
edd16368 SC |
267 | "unit attention detected\n", h->ctlr); |
268 | break; | |
269 | } | |
270 | return 1; | |
271 | } | |
272 | ||
852af20a MB |
273 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
274 | { | |
275 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
276 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
277 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
278 | return 0; | |
279 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
280 | return 1; | |
281 | } | |
282 | ||
edd16368 SC |
283 | static ssize_t host_store_rescan(struct device *dev, |
284 | struct device_attribute *attr, | |
285 | const char *buf, size_t count) | |
286 | { | |
287 | struct ctlr_info *h; | |
288 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 289 | h = shost_to_hba(shost); |
31468401 | 290 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
291 | return count; |
292 | } | |
293 | ||
d28ce020 SC |
294 | static ssize_t host_show_firmware_revision(struct device *dev, |
295 | struct device_attribute *attr, char *buf) | |
296 | { | |
297 | struct ctlr_info *h; | |
298 | struct Scsi_Host *shost = class_to_shost(dev); | |
299 | unsigned char *fwrev; | |
300 | ||
301 | h = shost_to_hba(shost); | |
302 | if (!h->hba_inquiry_data) | |
303 | return 0; | |
304 | fwrev = &h->hba_inquiry_data[32]; | |
305 | return snprintf(buf, 20, "%c%c%c%c\n", | |
306 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
307 | } | |
308 | ||
94a13649 SC |
309 | static ssize_t host_show_commands_outstanding(struct device *dev, |
310 | struct device_attribute *attr, char *buf) | |
311 | { | |
312 | struct Scsi_Host *shost = class_to_shost(dev); | |
313 | struct ctlr_info *h = shost_to_hba(shost); | |
314 | ||
315 | return snprintf(buf, 20, "%d\n", h->commands_outstanding); | |
316 | } | |
317 | ||
745a7a25 SC |
318 | static ssize_t host_show_transport_mode(struct device *dev, |
319 | struct device_attribute *attr, char *buf) | |
320 | { | |
321 | struct ctlr_info *h; | |
322 | struct Scsi_Host *shost = class_to_shost(dev); | |
323 | ||
324 | h = shost_to_hba(shost); | |
325 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 326 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
327 | "performant" : "simple"); |
328 | } | |
329 | ||
46380786 | 330 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
331 | static u32 unresettable_controller[] = { |
332 | 0x324a103C, /* Smart Array P712m */ | |
333 | 0x324b103C, /* SmartArray P711m */ | |
334 | 0x3223103C, /* Smart Array P800 */ | |
335 | 0x3234103C, /* Smart Array P400 */ | |
336 | 0x3235103C, /* Smart Array P400i */ | |
337 | 0x3211103C, /* Smart Array E200i */ | |
338 | 0x3212103C, /* Smart Array E200 */ | |
339 | 0x3213103C, /* Smart Array E200i */ | |
340 | 0x3214103C, /* Smart Array E200i */ | |
341 | 0x3215103C, /* Smart Array E200i */ | |
342 | 0x3237103C, /* Smart Array E500 */ | |
343 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 344 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
345 | 0x409C0E11, /* Smart Array 6400 */ |
346 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
347 | 0x40700E11, /* Smart Array 5300 */ |
348 | 0x40820E11, /* Smart Array 532 */ | |
349 | 0x40830E11, /* Smart Array 5312 */ | |
350 | 0x409A0E11, /* Smart Array 641 */ | |
351 | 0x409B0E11, /* Smart Array 642 */ | |
352 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
353 | }; |
354 | ||
46380786 SC |
355 | /* List of controllers which cannot even be soft reset */ |
356 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 357 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
358 | 0x40700E11, /* Smart Array 5300 */ |
359 | 0x40820E11, /* Smart Array 532 */ | |
360 | 0x40830E11, /* Smart Array 5312 */ | |
361 | 0x409A0E11, /* Smart Array 641 */ | |
362 | 0x409B0E11, /* Smart Array 642 */ | |
363 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
364 | /* Exclude 640x boards. These are two pci devices in one slot |
365 | * which share a battery backed cache module. One controls the | |
366 | * cache, the other accesses the cache through the one that controls | |
367 | * it. If we reset the one controlling the cache, the other will | |
368 | * likely not be happy. Just forbid resetting this conjoined mess. | |
369 | * The 640x isn't really supported by hpsa anyway. | |
370 | */ | |
371 | 0x409C0E11, /* Smart Array 6400 */ | |
372 | 0x409D0E11, /* Smart Array 6400 EM */ | |
373 | }; | |
374 | ||
375 | static int ctlr_is_hard_resettable(u32 board_id) | |
941b1cda SC |
376 | { |
377 | int i; | |
378 | ||
379 | for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++) | |
46380786 SC |
380 | if (unresettable_controller[i] == board_id) |
381 | return 0; | |
382 | return 1; | |
383 | } | |
384 | ||
385 | static int ctlr_is_soft_resettable(u32 board_id) | |
386 | { | |
387 | int i; | |
388 | ||
389 | for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++) | |
390 | if (soft_unresettable_controller[i] == board_id) | |
941b1cda SC |
391 | return 0; |
392 | return 1; | |
393 | } | |
394 | ||
46380786 SC |
395 | static int ctlr_is_resettable(u32 board_id) |
396 | { | |
397 | return ctlr_is_hard_resettable(board_id) || | |
398 | ctlr_is_soft_resettable(board_id); | |
399 | } | |
400 | ||
941b1cda SC |
401 | static ssize_t host_show_resettable(struct device *dev, |
402 | struct device_attribute *attr, char *buf) | |
403 | { | |
404 | struct ctlr_info *h; | |
405 | struct Scsi_Host *shost = class_to_shost(dev); | |
406 | ||
407 | h = shost_to_hba(shost); | |
46380786 | 408 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
409 | } |
410 | ||
edd16368 SC |
411 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
412 | { | |
413 | return (scsi3addr[3] & 0xC0) == 0x40; | |
414 | } | |
415 | ||
416 | static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG", | |
d82357ea | 417 | "1(ADM)", "UNKNOWN" |
edd16368 SC |
418 | }; |
419 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1) | |
420 | ||
421 | static ssize_t raid_level_show(struct device *dev, | |
422 | struct device_attribute *attr, char *buf) | |
423 | { | |
424 | ssize_t l = 0; | |
82a72c0a | 425 | unsigned char rlevel; |
edd16368 SC |
426 | struct ctlr_info *h; |
427 | struct scsi_device *sdev; | |
428 | struct hpsa_scsi_dev_t *hdev; | |
429 | unsigned long flags; | |
430 | ||
431 | sdev = to_scsi_device(dev); | |
432 | h = sdev_to_hba(sdev); | |
433 | spin_lock_irqsave(&h->lock, flags); | |
434 | hdev = sdev->hostdata; | |
435 | if (!hdev) { | |
436 | spin_unlock_irqrestore(&h->lock, flags); | |
437 | return -ENODEV; | |
438 | } | |
439 | ||
440 | /* Is this even a logical drive? */ | |
441 | if (!is_logical_dev_addr_mode(hdev->scsi3addr)) { | |
442 | spin_unlock_irqrestore(&h->lock, flags); | |
443 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
444 | return l; | |
445 | } | |
446 | ||
447 | rlevel = hdev->raid_level; | |
448 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 449 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
450 | rlevel = RAID_UNKNOWN; |
451 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
452 | return l; | |
453 | } | |
454 | ||
455 | static ssize_t lunid_show(struct device *dev, | |
456 | struct device_attribute *attr, char *buf) | |
457 | { | |
458 | struct ctlr_info *h; | |
459 | struct scsi_device *sdev; | |
460 | struct hpsa_scsi_dev_t *hdev; | |
461 | unsigned long flags; | |
462 | unsigned char lunid[8]; | |
463 | ||
464 | sdev = to_scsi_device(dev); | |
465 | h = sdev_to_hba(sdev); | |
466 | spin_lock_irqsave(&h->lock, flags); | |
467 | hdev = sdev->hostdata; | |
468 | if (!hdev) { | |
469 | spin_unlock_irqrestore(&h->lock, flags); | |
470 | return -ENODEV; | |
471 | } | |
472 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
473 | spin_unlock_irqrestore(&h->lock, flags); | |
474 | return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
475 | lunid[0], lunid[1], lunid[2], lunid[3], | |
476 | lunid[4], lunid[5], lunid[6], lunid[7]); | |
477 | } | |
478 | ||
479 | static ssize_t unique_id_show(struct device *dev, | |
480 | struct device_attribute *attr, char *buf) | |
481 | { | |
482 | struct ctlr_info *h; | |
483 | struct scsi_device *sdev; | |
484 | struct hpsa_scsi_dev_t *hdev; | |
485 | unsigned long flags; | |
486 | unsigned char sn[16]; | |
487 | ||
488 | sdev = to_scsi_device(dev); | |
489 | h = sdev_to_hba(sdev); | |
490 | spin_lock_irqsave(&h->lock, flags); | |
491 | hdev = sdev->hostdata; | |
492 | if (!hdev) { | |
493 | spin_unlock_irqrestore(&h->lock, flags); | |
494 | return -ENODEV; | |
495 | } | |
496 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
497 | spin_unlock_irqrestore(&h->lock, flags); | |
498 | return snprintf(buf, 16 * 2 + 2, | |
499 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
500 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
501 | sn[0], sn[1], sn[2], sn[3], | |
502 | sn[4], sn[5], sn[6], sn[7], | |
503 | sn[8], sn[9], sn[10], sn[11], | |
504 | sn[12], sn[13], sn[14], sn[15]); | |
505 | } | |
506 | ||
3f5eac3a SC |
507 | static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); |
508 | static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); | |
509 | static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); | |
510 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); | |
511 | static DEVICE_ATTR(firmware_revision, S_IRUGO, | |
512 | host_show_firmware_revision, NULL); | |
513 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
514 | host_show_commands_outstanding, NULL); | |
515 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
516 | host_show_transport_mode, NULL); | |
941b1cda SC |
517 | static DEVICE_ATTR(resettable, S_IRUGO, |
518 | host_show_resettable, NULL); | |
3f5eac3a SC |
519 | |
520 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
521 | &dev_attr_raid_level, | |
522 | &dev_attr_lunid, | |
523 | &dev_attr_unique_id, | |
524 | NULL, | |
525 | }; | |
526 | ||
527 | static struct device_attribute *hpsa_shost_attrs[] = { | |
528 | &dev_attr_rescan, | |
529 | &dev_attr_firmware_revision, | |
530 | &dev_attr_commands_outstanding, | |
531 | &dev_attr_transport_mode, | |
941b1cda | 532 | &dev_attr_resettable, |
3f5eac3a SC |
533 | NULL, |
534 | }; | |
535 | ||
536 | static struct scsi_host_template hpsa_driver_template = { | |
537 | .module = THIS_MODULE, | |
f79cfec6 SC |
538 | .name = HPSA, |
539 | .proc_name = HPSA, | |
3f5eac3a SC |
540 | .queuecommand = hpsa_scsi_queue_command, |
541 | .scan_start = hpsa_scan_start, | |
542 | .scan_finished = hpsa_scan_finished, | |
543 | .change_queue_depth = hpsa_change_queue_depth, | |
544 | .this_id = -1, | |
545 | .use_clustering = ENABLE_CLUSTERING, | |
75167d2c | 546 | .eh_abort_handler = hpsa_eh_abort_handler, |
3f5eac3a SC |
547 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
548 | .ioctl = hpsa_ioctl, | |
549 | .slave_alloc = hpsa_slave_alloc, | |
550 | .slave_destroy = hpsa_slave_destroy, | |
551 | #ifdef CONFIG_COMPAT | |
552 | .compat_ioctl = hpsa_compat_ioctl, | |
553 | #endif | |
554 | .sdev_attrs = hpsa_sdev_attrs, | |
555 | .shost_attrs = hpsa_shost_attrs, | |
c0d6a4d1 | 556 | .max_sectors = 8192, |
54b2b50c | 557 | .no_write_same = 1, |
3f5eac3a SC |
558 | }; |
559 | ||
560 | ||
561 | /* Enqueuing and dequeuing functions for cmdlists. */ | |
562 | static inline void addQ(struct list_head *list, struct CommandList *c) | |
563 | { | |
564 | list_add_tail(&c->list, list); | |
565 | } | |
566 | ||
254f796b | 567 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
568 | { |
569 | u32 a; | |
254f796b | 570 | struct reply_pool *rq = &h->reply_queue[q]; |
e16a33ad | 571 | unsigned long flags; |
3f5eac3a | 572 | |
e1f7de0c MG |
573 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
574 | return h->access.command_completed(h, q); | |
575 | ||
3f5eac3a | 576 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 577 | return h->access.command_completed(h, q); |
3f5eac3a | 578 | |
254f796b MG |
579 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
580 | a = rq->head[rq->current_entry]; | |
581 | rq->current_entry++; | |
e16a33ad | 582 | spin_lock_irqsave(&h->lock, flags); |
3f5eac3a | 583 | h->commands_outstanding--; |
e16a33ad | 584 | spin_unlock_irqrestore(&h->lock, flags); |
3f5eac3a SC |
585 | } else { |
586 | a = FIFO_EMPTY; | |
587 | } | |
588 | /* Check for wraparound */ | |
254f796b MG |
589 | if (rq->current_entry == h->max_commands) { |
590 | rq->current_entry = 0; | |
591 | rq->wraparound ^= 1; | |
3f5eac3a SC |
592 | } |
593 | return a; | |
594 | } | |
595 | ||
596 | /* set_performant_mode: Modify the tag for cciss performant | |
597 | * set bit 0 for pull model, bits 3-1 for block fetch | |
598 | * register number | |
599 | */ | |
600 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c) | |
601 | { | |
254f796b | 602 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 603 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
eee0f03a | 604 | if (likely(h->msix_vector > 0)) |
254f796b | 605 | c->Header.ReplyQueue = |
804a5cb5 | 606 | raw_smp_processor_id() % h->nreply_queues; |
254f796b | 607 | } |
3f5eac3a SC |
608 | } |
609 | ||
e85c5974 SC |
610 | static int is_firmware_flash_cmd(u8 *cdb) |
611 | { | |
612 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
613 | } | |
614 | ||
615 | /* | |
616 | * During firmware flash, the heartbeat register may not update as frequently | |
617 | * as it should. So we dial down lockup detection during firmware flash. and | |
618 | * dial it back up when firmware flash completes. | |
619 | */ | |
620 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
621 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
622 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, | |
623 | struct CommandList *c) | |
624 | { | |
625 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
626 | return; | |
627 | atomic_inc(&h->firmware_flash_in_progress); | |
628 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
629 | } | |
630 | ||
631 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
632 | struct CommandList *c) | |
633 | { | |
634 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
635 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
636 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
637 | } | |
638 | ||
3f5eac3a SC |
639 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, |
640 | struct CommandList *c) | |
641 | { | |
642 | unsigned long flags; | |
643 | ||
644 | set_performant_mode(h, c); | |
e85c5974 | 645 | dial_down_lockup_detection_during_fw_flash(h, c); |
3f5eac3a SC |
646 | spin_lock_irqsave(&h->lock, flags); |
647 | addQ(&h->reqQ, c); | |
648 | h->Qdepth++; | |
3f5eac3a | 649 | spin_unlock_irqrestore(&h->lock, flags); |
e16a33ad | 650 | start_io(h); |
3f5eac3a SC |
651 | } |
652 | ||
653 | static inline void removeQ(struct CommandList *c) | |
654 | { | |
655 | if (WARN_ON(list_empty(&c->list))) | |
656 | return; | |
657 | list_del_init(&c->list); | |
658 | } | |
659 | ||
660 | static inline int is_hba_lunid(unsigned char scsi3addr[]) | |
661 | { | |
662 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
663 | } | |
664 | ||
665 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
666 | { | |
667 | if (!h->hba_inquiry_data) | |
668 | return 0; | |
669 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
670 | return 1; | |
671 | return 0; | |
672 | } | |
673 | ||
edd16368 SC |
674 | static int hpsa_find_target_lun(struct ctlr_info *h, |
675 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
676 | { | |
677 | /* finds an unused bus, target, lun for a new physical device | |
678 | * assumes h->devlock is held | |
679 | */ | |
680 | int i, found = 0; | |
cfe5badc | 681 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 682 | |
263d9401 | 683 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
684 | |
685 | for (i = 0; i < h->ndevices; i++) { | |
686 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 687 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
688 | } |
689 | ||
263d9401 AM |
690 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
691 | if (i < HPSA_MAX_DEVICES) { | |
692 | /* *bus = 1; */ | |
693 | *target = i; | |
694 | *lun = 0; | |
695 | found = 1; | |
edd16368 SC |
696 | } |
697 | return !found; | |
698 | } | |
699 | ||
700 | /* Add an entry into h->dev[] array. */ | |
701 | static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno, | |
702 | struct hpsa_scsi_dev_t *device, | |
703 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
704 | { | |
705 | /* assumes h->devlock is held */ | |
706 | int n = h->ndevices; | |
707 | int i; | |
708 | unsigned char addr1[8], addr2[8]; | |
709 | struct hpsa_scsi_dev_t *sd; | |
710 | ||
cfe5badc | 711 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
712 | dev_err(&h->pdev->dev, "too many devices, some will be " |
713 | "inaccessible.\n"); | |
714 | return -1; | |
715 | } | |
716 | ||
717 | /* physical devices do not have lun or target assigned until now. */ | |
718 | if (device->lun != -1) | |
719 | /* Logical device, lun is already assigned. */ | |
720 | goto lun_assigned; | |
721 | ||
722 | /* If this device a non-zero lun of a multi-lun device | |
723 | * byte 4 of the 8-byte LUN addr will contain the logical | |
724 | * unit no, zero otherise. | |
725 | */ | |
726 | if (device->scsi3addr[4] == 0) { | |
727 | /* This is not a non-zero lun of a multi-lun device */ | |
728 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
729 | device->bus, &device->target, &device->lun) != 0) | |
730 | return -1; | |
731 | goto lun_assigned; | |
732 | } | |
733 | ||
734 | /* This is a non-zero lun of a multi-lun device. | |
735 | * Search through our list and find the device which | |
736 | * has the same 8 byte LUN address, excepting byte 4. | |
737 | * Assign the same bus and target for this new LUN. | |
738 | * Use the logical unit number from the firmware. | |
739 | */ | |
740 | memcpy(addr1, device->scsi3addr, 8); | |
741 | addr1[4] = 0; | |
742 | for (i = 0; i < n; i++) { | |
743 | sd = h->dev[i]; | |
744 | memcpy(addr2, sd->scsi3addr, 8); | |
745 | addr2[4] = 0; | |
746 | /* differ only in byte 4? */ | |
747 | if (memcmp(addr1, addr2, 8) == 0) { | |
748 | device->bus = sd->bus; | |
749 | device->target = sd->target; | |
750 | device->lun = device->scsi3addr[4]; | |
751 | break; | |
752 | } | |
753 | } | |
754 | if (device->lun == -1) { | |
755 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
756 | " suspect firmware bug or unsupported hardware " | |
757 | "configuration.\n"); | |
758 | return -1; | |
759 | } | |
760 | ||
761 | lun_assigned: | |
762 | ||
763 | h->dev[n] = device; | |
764 | h->ndevices++; | |
765 | added[*nadded] = device; | |
766 | (*nadded)++; | |
767 | ||
768 | /* initially, (before registering with scsi layer) we don't | |
769 | * know our hostno and we don't want to print anything first | |
770 | * time anyway (the scsi layer's inquiries will show that info) | |
771 | */ | |
772 | /* if (hostno != -1) */ | |
773 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n", | |
774 | scsi_device_type(device->devtype), hostno, | |
775 | device->bus, device->target, device->lun); | |
776 | return 0; | |
777 | } | |
778 | ||
bd9244f7 ST |
779 | /* Update an entry in h->dev[] array. */ |
780 | static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno, | |
781 | int entry, struct hpsa_scsi_dev_t *new_entry) | |
782 | { | |
783 | /* assumes h->devlock is held */ | |
784 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
785 | ||
786 | /* Raid level changed. */ | |
787 | h->dev[entry]->raid_level = new_entry->raid_level; | |
788 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n", | |
789 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
790 | new_entry->target, new_entry->lun); | |
791 | } | |
792 | ||
2a8ccf31 SC |
793 | /* Replace an entry from h->dev[] array. */ |
794 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno, | |
795 | int entry, struct hpsa_scsi_dev_t *new_entry, | |
796 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
797 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
798 | { | |
799 | /* assumes h->devlock is held */ | |
cfe5badc | 800 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
801 | removed[*nremoved] = h->dev[entry]; |
802 | (*nremoved)++; | |
01350d05 SC |
803 | |
804 | /* | |
805 | * New physical devices won't have target/lun assigned yet | |
806 | * so we need to preserve the values in the slot we are replacing. | |
807 | */ | |
808 | if (new_entry->target == -1) { | |
809 | new_entry->target = h->dev[entry]->target; | |
810 | new_entry->lun = h->dev[entry]->lun; | |
811 | } | |
812 | ||
2a8ccf31 SC |
813 | h->dev[entry] = new_entry; |
814 | added[*nadded] = new_entry; | |
815 | (*nadded)++; | |
816 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n", | |
817 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
818 | new_entry->target, new_entry->lun); | |
819 | } | |
820 | ||
edd16368 SC |
821 | /* Remove an entry from h->dev[] array. */ |
822 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry, | |
823 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
824 | { | |
825 | /* assumes h->devlock is held */ | |
826 | int i; | |
827 | struct hpsa_scsi_dev_t *sd; | |
828 | ||
cfe5badc | 829 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
830 | |
831 | sd = h->dev[entry]; | |
832 | removed[*nremoved] = h->dev[entry]; | |
833 | (*nremoved)++; | |
834 | ||
835 | for (i = entry; i < h->ndevices-1; i++) | |
836 | h->dev[i] = h->dev[i+1]; | |
837 | h->ndevices--; | |
838 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n", | |
839 | scsi_device_type(sd->devtype), hostno, sd->bus, sd->target, | |
840 | sd->lun); | |
841 | } | |
842 | ||
843 | #define SCSI3ADDR_EQ(a, b) ( \ | |
844 | (a)[7] == (b)[7] && \ | |
845 | (a)[6] == (b)[6] && \ | |
846 | (a)[5] == (b)[5] && \ | |
847 | (a)[4] == (b)[4] && \ | |
848 | (a)[3] == (b)[3] && \ | |
849 | (a)[2] == (b)[2] && \ | |
850 | (a)[1] == (b)[1] && \ | |
851 | (a)[0] == (b)[0]) | |
852 | ||
853 | static void fixup_botched_add(struct ctlr_info *h, | |
854 | struct hpsa_scsi_dev_t *added) | |
855 | { | |
856 | /* called when scsi_add_device fails in order to re-adjust | |
857 | * h->dev[] to match the mid layer's view. | |
858 | */ | |
859 | unsigned long flags; | |
860 | int i, j; | |
861 | ||
862 | spin_lock_irqsave(&h->lock, flags); | |
863 | for (i = 0; i < h->ndevices; i++) { | |
864 | if (h->dev[i] == added) { | |
865 | for (j = i; j < h->ndevices-1; j++) | |
866 | h->dev[j] = h->dev[j+1]; | |
867 | h->ndevices--; | |
868 | break; | |
869 | } | |
870 | } | |
871 | spin_unlock_irqrestore(&h->lock, flags); | |
872 | kfree(added); | |
873 | } | |
874 | ||
875 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
876 | struct hpsa_scsi_dev_t *dev2) | |
877 | { | |
edd16368 SC |
878 | /* we compare everything except lun and target as these |
879 | * are not yet assigned. Compare parts likely | |
880 | * to differ first | |
881 | */ | |
882 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
883 | sizeof(dev1->scsi3addr)) != 0) | |
884 | return 0; | |
885 | if (memcmp(dev1->device_id, dev2->device_id, | |
886 | sizeof(dev1->device_id)) != 0) | |
887 | return 0; | |
888 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
889 | return 0; | |
890 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
891 | return 0; | |
edd16368 SC |
892 | if (dev1->devtype != dev2->devtype) |
893 | return 0; | |
edd16368 SC |
894 | if (dev1->bus != dev2->bus) |
895 | return 0; | |
896 | return 1; | |
897 | } | |
898 | ||
bd9244f7 ST |
899 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
900 | struct hpsa_scsi_dev_t *dev2) | |
901 | { | |
902 | /* Device attributes that can change, but don't mean | |
903 | * that the device is a different device, nor that the OS | |
904 | * needs to be told anything about the change. | |
905 | */ | |
906 | if (dev1->raid_level != dev2->raid_level) | |
907 | return 1; | |
908 | return 0; | |
909 | } | |
910 | ||
edd16368 SC |
911 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
912 | * and return needle location in *index. If scsi3addr matches, but not | |
913 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
914 | * location in *index. |
915 | * In the case of a minor device attribute change, such as RAID level, just | |
916 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
917 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
918 | */ |
919 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
920 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
921 | int *index) | |
922 | { | |
923 | int i; | |
924 | #define DEVICE_NOT_FOUND 0 | |
925 | #define DEVICE_CHANGED 1 | |
926 | #define DEVICE_SAME 2 | |
bd9244f7 | 927 | #define DEVICE_UPDATED 3 |
edd16368 | 928 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
929 | if (haystack[i] == NULL) /* previously removed. */ |
930 | continue; | |
edd16368 SC |
931 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
932 | *index = i; | |
bd9244f7 ST |
933 | if (device_is_the_same(needle, haystack[i])) { |
934 | if (device_updated(needle, haystack[i])) | |
935 | return DEVICE_UPDATED; | |
edd16368 | 936 | return DEVICE_SAME; |
bd9244f7 | 937 | } else { |
edd16368 | 938 | return DEVICE_CHANGED; |
bd9244f7 | 939 | } |
edd16368 SC |
940 | } |
941 | } | |
942 | *index = -1; | |
943 | return DEVICE_NOT_FOUND; | |
944 | } | |
945 | ||
4967bd3e | 946 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno, |
edd16368 SC |
947 | struct hpsa_scsi_dev_t *sd[], int nsds) |
948 | { | |
949 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
950 | * data. This function takes what's in sd to be the current | |
951 | * reality and updates h->dev[] to reflect that reality. | |
952 | */ | |
953 | int i, entry, device_change, changes = 0; | |
954 | struct hpsa_scsi_dev_t *csd; | |
955 | unsigned long flags; | |
956 | struct hpsa_scsi_dev_t **added, **removed; | |
957 | int nadded, nremoved; | |
958 | struct Scsi_Host *sh = NULL; | |
959 | ||
cfe5badc ST |
960 | added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); |
961 | removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); | |
edd16368 SC |
962 | |
963 | if (!added || !removed) { | |
964 | dev_warn(&h->pdev->dev, "out of memory in " | |
965 | "adjust_hpsa_scsi_table\n"); | |
966 | goto free_and_out; | |
967 | } | |
968 | ||
969 | spin_lock_irqsave(&h->devlock, flags); | |
970 | ||
971 | /* find any devices in h->dev[] that are not in | |
972 | * sd[] and remove them from h->dev[], and for any | |
973 | * devices which have changed, remove the old device | |
974 | * info and add the new device info. | |
bd9244f7 ST |
975 | * If minor device attributes change, just update |
976 | * the existing device structure. | |
edd16368 SC |
977 | */ |
978 | i = 0; | |
979 | nremoved = 0; | |
980 | nadded = 0; | |
981 | while (i < h->ndevices) { | |
982 | csd = h->dev[i]; | |
983 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
984 | if (device_change == DEVICE_NOT_FOUND) { | |
985 | changes++; | |
986 | hpsa_scsi_remove_entry(h, hostno, i, | |
987 | removed, &nremoved); | |
988 | continue; /* remove ^^^, hence i not incremented */ | |
989 | } else if (device_change == DEVICE_CHANGED) { | |
990 | changes++; | |
2a8ccf31 SC |
991 | hpsa_scsi_replace_entry(h, hostno, i, sd[entry], |
992 | added, &nadded, removed, &nremoved); | |
c7f172dc SC |
993 | /* Set it to NULL to prevent it from being freed |
994 | * at the bottom of hpsa_update_scsi_devices() | |
995 | */ | |
996 | sd[entry] = NULL; | |
bd9244f7 ST |
997 | } else if (device_change == DEVICE_UPDATED) { |
998 | hpsa_scsi_update_entry(h, hostno, i, sd[entry]); | |
edd16368 SC |
999 | } |
1000 | i++; | |
1001 | } | |
1002 | ||
1003 | /* Now, make sure every device listed in sd[] is also | |
1004 | * listed in h->dev[], adding them if they aren't found | |
1005 | */ | |
1006 | ||
1007 | for (i = 0; i < nsds; i++) { | |
1008 | if (!sd[i]) /* if already added above. */ | |
1009 | continue; | |
1010 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, | |
1011 | h->ndevices, &entry); | |
1012 | if (device_change == DEVICE_NOT_FOUND) { | |
1013 | changes++; | |
1014 | if (hpsa_scsi_add_entry(h, hostno, sd[i], | |
1015 | added, &nadded) != 0) | |
1016 | break; | |
1017 | sd[i] = NULL; /* prevent from being freed later. */ | |
1018 | } else if (device_change == DEVICE_CHANGED) { | |
1019 | /* should never happen... */ | |
1020 | changes++; | |
1021 | dev_warn(&h->pdev->dev, | |
1022 | "device unexpectedly changed.\n"); | |
1023 | /* but if it does happen, we just ignore that device */ | |
1024 | } | |
1025 | } | |
1026 | spin_unlock_irqrestore(&h->devlock, flags); | |
1027 | ||
1028 | /* Don't notify scsi mid layer of any changes the first time through | |
1029 | * (or if there are no changes) scsi_scan_host will do it later the | |
1030 | * first time through. | |
1031 | */ | |
1032 | if (hostno == -1 || !changes) | |
1033 | goto free_and_out; | |
1034 | ||
1035 | sh = h->scsi_host; | |
1036 | /* Notify scsi mid layer of any removed devices */ | |
1037 | for (i = 0; i < nremoved; i++) { | |
1038 | struct scsi_device *sdev = | |
1039 | scsi_device_lookup(sh, removed[i]->bus, | |
1040 | removed[i]->target, removed[i]->lun); | |
1041 | if (sdev != NULL) { | |
1042 | scsi_remove_device(sdev); | |
1043 | scsi_device_put(sdev); | |
1044 | } else { | |
1045 | /* We don't expect to get here. | |
1046 | * future cmds to this device will get selection | |
1047 | * timeout as if the device was gone. | |
1048 | */ | |
1049 | dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d " | |
1050 | " for removal.", hostno, removed[i]->bus, | |
1051 | removed[i]->target, removed[i]->lun); | |
1052 | } | |
1053 | kfree(removed[i]); | |
1054 | removed[i] = NULL; | |
1055 | } | |
1056 | ||
1057 | /* Notify scsi mid layer of any added devices */ | |
1058 | for (i = 0; i < nadded; i++) { | |
1059 | if (scsi_add_device(sh, added[i]->bus, | |
1060 | added[i]->target, added[i]->lun) == 0) | |
1061 | continue; | |
1062 | dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, " | |
1063 | "device not added.\n", hostno, added[i]->bus, | |
1064 | added[i]->target, added[i]->lun); | |
1065 | /* now we have to remove it from h->dev, | |
1066 | * since it didn't get added to scsi mid layer | |
1067 | */ | |
1068 | fixup_botched_add(h, added[i]); | |
1069 | } | |
1070 | ||
1071 | free_and_out: | |
1072 | kfree(added); | |
1073 | kfree(removed); | |
edd16368 SC |
1074 | } |
1075 | ||
1076 | /* | |
9e03aa2f | 1077 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
1078 | * Assume's h->devlock is held. |
1079 | */ | |
1080 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
1081 | int bus, int target, int lun) | |
1082 | { | |
1083 | int i; | |
1084 | struct hpsa_scsi_dev_t *sd; | |
1085 | ||
1086 | for (i = 0; i < h->ndevices; i++) { | |
1087 | sd = h->dev[i]; | |
1088 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
1089 | return sd; | |
1090 | } | |
1091 | return NULL; | |
1092 | } | |
1093 | ||
1094 | /* link sdev->hostdata to our per-device structure. */ | |
1095 | static int hpsa_slave_alloc(struct scsi_device *sdev) | |
1096 | { | |
1097 | struct hpsa_scsi_dev_t *sd; | |
1098 | unsigned long flags; | |
1099 | struct ctlr_info *h; | |
1100 | ||
1101 | h = sdev_to_hba(sdev); | |
1102 | spin_lock_irqsave(&h->devlock, flags); | |
1103 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), | |
1104 | sdev_id(sdev), sdev->lun); | |
1105 | if (sd != NULL) | |
1106 | sdev->hostdata = sd; | |
1107 | spin_unlock_irqrestore(&h->devlock, flags); | |
1108 | return 0; | |
1109 | } | |
1110 | ||
1111 | static void hpsa_slave_destroy(struct scsi_device *sdev) | |
1112 | { | |
bcc44255 | 1113 | /* nothing to do. */ |
edd16368 SC |
1114 | } |
1115 | ||
33a2ffce SC |
1116 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
1117 | { | |
1118 | int i; | |
1119 | ||
1120 | if (!h->cmd_sg_list) | |
1121 | return; | |
1122 | for (i = 0; i < h->nr_cmds; i++) { | |
1123 | kfree(h->cmd_sg_list[i]); | |
1124 | h->cmd_sg_list[i] = NULL; | |
1125 | } | |
1126 | kfree(h->cmd_sg_list); | |
1127 | h->cmd_sg_list = NULL; | |
1128 | } | |
1129 | ||
1130 | static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h) | |
1131 | { | |
1132 | int i; | |
1133 | ||
1134 | if (h->chainsize <= 0) | |
1135 | return 0; | |
1136 | ||
1137 | h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, | |
1138 | GFP_KERNEL); | |
1139 | if (!h->cmd_sg_list) | |
1140 | return -ENOMEM; | |
1141 | for (i = 0; i < h->nr_cmds; i++) { | |
1142 | h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * | |
1143 | h->chainsize, GFP_KERNEL); | |
1144 | if (!h->cmd_sg_list[i]) | |
1145 | goto clean; | |
1146 | } | |
1147 | return 0; | |
1148 | ||
1149 | clean: | |
1150 | hpsa_free_sg_chain_blocks(h); | |
1151 | return -ENOMEM; | |
1152 | } | |
1153 | ||
e2bea6df | 1154 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
1155 | struct CommandList *c) |
1156 | { | |
1157 | struct SGDescriptor *chain_sg, *chain_block; | |
1158 | u64 temp64; | |
1159 | ||
1160 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
1161 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
1162 | chain_sg->Ext = HPSA_SG_CHAIN; | |
1163 | chain_sg->Len = sizeof(*chain_sg) * | |
1164 | (c->Header.SGTotal - h->max_cmd_sg_entries); | |
1165 | temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len, | |
1166 | PCI_DMA_TODEVICE); | |
e2bea6df SC |
1167 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
1168 | /* prevent subsequent unmapping */ | |
1169 | chain_sg->Addr.lower = 0; | |
1170 | chain_sg->Addr.upper = 0; | |
1171 | return -1; | |
1172 | } | |
33a2ffce SC |
1173 | chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL); |
1174 | chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL); | |
e2bea6df | 1175 | return 0; |
33a2ffce SC |
1176 | } |
1177 | ||
1178 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
1179 | struct CommandList *c) | |
1180 | { | |
1181 | struct SGDescriptor *chain_sg; | |
1182 | union u64bit temp64; | |
1183 | ||
1184 | if (c->Header.SGTotal <= h->max_cmd_sg_entries) | |
1185 | return; | |
1186 | ||
1187 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
1188 | temp64.val32.lower = chain_sg->Addr.lower; | |
1189 | temp64.val32.upper = chain_sg->Addr.upper; | |
1190 | pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE); | |
1191 | } | |
1192 | ||
1fb011fb | 1193 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
1194 | { |
1195 | struct scsi_cmnd *cmd; | |
1196 | struct ctlr_info *h; | |
1197 | struct ErrorInfo *ei; | |
1198 | ||
1199 | unsigned char sense_key; | |
1200 | unsigned char asc; /* additional sense code */ | |
1201 | unsigned char ascq; /* additional sense code qualifier */ | |
db111e18 | 1202 | unsigned long sense_data_size; |
edd16368 SC |
1203 | |
1204 | ei = cp->err_info; | |
1205 | cmd = (struct scsi_cmnd *) cp->scsi_cmd; | |
1206 | h = cp->h; | |
1207 | ||
1208 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c MG |
1209 | if ((cp->cmd_type == CMD_SCSI) && |
1210 | (cp->Header.SGTotal > h->max_cmd_sg_entries)) | |
33a2ffce | 1211 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 SC |
1212 | |
1213 | cmd->result = (DID_OK << 16); /* host byte */ | |
1214 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
5512672f | 1215 | cmd->result |= ei->ScsiStatus; |
edd16368 SC |
1216 | |
1217 | /* copy the sense data whether we need to or not. */ | |
db111e18 SC |
1218 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) |
1219 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
1220 | else | |
1221 | sense_data_size = sizeof(ei->SenseInfo); | |
1222 | if (ei->SenseLen < sense_data_size) | |
1223 | sense_data_size = ei->SenseLen; | |
1224 | ||
1225 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
edd16368 SC |
1226 | scsi_set_resid(cmd, ei->ResidualCnt); |
1227 | ||
1228 | if (ei->CommandStatus == 0) { | |
edd16368 | 1229 | cmd_free(h, cp); |
2cc5bfaf | 1230 | cmd->scsi_done(cmd); |
edd16368 SC |
1231 | return; |
1232 | } | |
1233 | ||
e1f7de0c MG |
1234 | /* For I/O accelerator commands, copy over some fields to the normal |
1235 | * CISS header used below for error handling. | |
1236 | */ | |
1237 | if (cp->cmd_type == CMD_IOACCEL1) { | |
1238 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
1239 | cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd); | |
1240 | cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
1241 | cp->Header.Tag.lower = c->Tag.lower; | |
1242 | cp->Header.Tag.upper = c->Tag.upper; | |
1243 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); | |
1244 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
1245 | } | |
1246 | ||
edd16368 SC |
1247 | /* an error has occurred */ |
1248 | switch (ei->CommandStatus) { | |
1249 | ||
1250 | case CMD_TARGET_STATUS: | |
1251 | if (ei->ScsiStatus) { | |
1252 | /* Get sense key */ | |
1253 | sense_key = 0xf & ei->SenseInfo[2]; | |
1254 | /* Get additional sense code */ | |
1255 | asc = ei->SenseInfo[12]; | |
1256 | /* Get addition sense code qualifier */ | |
1257 | ascq = ei->SenseInfo[13]; | |
1258 | } | |
1259 | ||
1260 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { | |
3ce438df | 1261 | if (check_for_unit_attention(h, cp)) |
edd16368 | 1262 | break; |
edd16368 SC |
1263 | if (sense_key == ILLEGAL_REQUEST) { |
1264 | /* | |
1265 | * SCSI REPORT_LUNS is commonly unsupported on | |
1266 | * Smart Array. Suppress noisy complaint. | |
1267 | */ | |
1268 | if (cp->Request.CDB[0] == REPORT_LUNS) | |
1269 | break; | |
1270 | ||
1271 | /* If ASC/ASCQ indicate Logical Unit | |
1272 | * Not Supported condition, | |
1273 | */ | |
1274 | if ((asc == 0x25) && (ascq == 0x0)) { | |
1275 | dev_warn(&h->pdev->dev, "cp %p " | |
1276 | "has check condition\n", cp); | |
1277 | break; | |
1278 | } | |
1279 | } | |
1280 | ||
1281 | if (sense_key == NOT_READY) { | |
1282 | /* If Sense is Not Ready, Logical Unit | |
1283 | * Not ready, Manual Intervention | |
1284 | * required | |
1285 | */ | |
1286 | if ((asc == 0x04) && (ascq == 0x03)) { | |
edd16368 SC |
1287 | dev_warn(&h->pdev->dev, "cp %p " |
1288 | "has check condition: unit " | |
1289 | "not ready, manual " | |
1290 | "intervention required\n", cp); | |
1291 | break; | |
1292 | } | |
1293 | } | |
1d3b3609 MG |
1294 | if (sense_key == ABORTED_COMMAND) { |
1295 | /* Aborted command is retryable */ | |
1296 | dev_warn(&h->pdev->dev, "cp %p " | |
1297 | "has check condition: aborted command: " | |
1298 | "ASC: 0x%x, ASCQ: 0x%x\n", | |
1299 | cp, asc, ascq); | |
2e311fba | 1300 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 MG |
1301 | break; |
1302 | } | |
edd16368 | 1303 | /* Must be some other type of check condition */ |
21b8e4ef | 1304 | dev_dbg(&h->pdev->dev, "cp %p has check condition: " |
edd16368 SC |
1305 | "unknown type: " |
1306 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
1307 | "Returning result: 0x%x, " | |
1308 | "cmd=[%02x %02x %02x %02x %02x " | |
807be732 | 1309 | "%02x %02x %02x %02x %02x %02x " |
edd16368 SC |
1310 | "%02x %02x %02x %02x %02x]\n", |
1311 | cp, sense_key, asc, ascq, | |
1312 | cmd->result, | |
1313 | cmd->cmnd[0], cmd->cmnd[1], | |
1314 | cmd->cmnd[2], cmd->cmnd[3], | |
1315 | cmd->cmnd[4], cmd->cmnd[5], | |
1316 | cmd->cmnd[6], cmd->cmnd[7], | |
807be732 MM |
1317 | cmd->cmnd[8], cmd->cmnd[9], |
1318 | cmd->cmnd[10], cmd->cmnd[11], | |
1319 | cmd->cmnd[12], cmd->cmnd[13], | |
1320 | cmd->cmnd[14], cmd->cmnd[15]); | |
edd16368 SC |
1321 | break; |
1322 | } | |
1323 | ||
1324 | ||
1325 | /* Problem was not a check condition | |
1326 | * Pass it up to the upper layers... | |
1327 | */ | |
1328 | if (ei->ScsiStatus) { | |
1329 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
1330 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
1331 | "Returning result: 0x%x\n", | |
1332 | cp, ei->ScsiStatus, | |
1333 | sense_key, asc, ascq, | |
1334 | cmd->result); | |
1335 | } else { /* scsi status is zero??? How??? */ | |
1336 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
1337 | "Returning no connection.\n", cp), | |
1338 | ||
1339 | /* Ordinarily, this case should never happen, | |
1340 | * but there is a bug in some released firmware | |
1341 | * revisions that allows it to happen if, for | |
1342 | * example, a 4100 backplane loses power and | |
1343 | * the tape drive is in it. We assume that | |
1344 | * it's a fatal error of some kind because we | |
1345 | * can't show that it wasn't. We will make it | |
1346 | * look like selection timeout since that is | |
1347 | * the most common reason for this to occur, | |
1348 | * and it's severe enough. | |
1349 | */ | |
1350 | ||
1351 | cmd->result = DID_NO_CONNECT << 16; | |
1352 | } | |
1353 | break; | |
1354 | ||
1355 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
1356 | break; | |
1357 | case CMD_DATA_OVERRUN: | |
1358 | dev_warn(&h->pdev->dev, "cp %p has" | |
1359 | " completed with data overrun " | |
1360 | "reported\n", cp); | |
1361 | break; | |
1362 | case CMD_INVALID: { | |
1363 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
1364 | print_cmd(cp); */ | |
1365 | /* We get CMD_INVALID if you address a non-existent device | |
1366 | * instead of a selection timeout (no response). You will | |
1367 | * see this if you yank out a drive, then try to access it. | |
1368 | * This is kind of a shame because it means that any other | |
1369 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
1370 | * missing target. */ | |
1371 | cmd->result = DID_NO_CONNECT << 16; | |
1372 | } | |
1373 | break; | |
1374 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 1375 | cmd->result = DID_ERROR << 16; |
edd16368 | 1376 | dev_warn(&h->pdev->dev, "cp %p has " |
256d0eaa | 1377 | "protocol error\n", cp); |
edd16368 SC |
1378 | break; |
1379 | case CMD_HARDWARE_ERR: | |
1380 | cmd->result = DID_ERROR << 16; | |
1381 | dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp); | |
1382 | break; | |
1383 | case CMD_CONNECTION_LOST: | |
1384 | cmd->result = DID_ERROR << 16; | |
1385 | dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp); | |
1386 | break; | |
1387 | case CMD_ABORTED: | |
1388 | cmd->result = DID_ABORT << 16; | |
1389 | dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n", | |
1390 | cp, ei->ScsiStatus); | |
1391 | break; | |
1392 | case CMD_ABORT_FAILED: | |
1393 | cmd->result = DID_ERROR << 16; | |
1394 | dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp); | |
1395 | break; | |
1396 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 SC |
1397 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
1398 | dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited " | |
edd16368 SC |
1399 | "abort\n", cp); |
1400 | break; | |
1401 | case CMD_TIMEOUT: | |
1402 | cmd->result = DID_TIME_OUT << 16; | |
1403 | dev_warn(&h->pdev->dev, "cp %p timedout\n", cp); | |
1404 | break; | |
1d5e2ed0 SC |
1405 | case CMD_UNABORTABLE: |
1406 | cmd->result = DID_ERROR << 16; | |
1407 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
1408 | break; | |
edd16368 SC |
1409 | default: |
1410 | cmd->result = DID_ERROR << 16; | |
1411 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
1412 | cp, ei->CommandStatus); | |
1413 | } | |
edd16368 | 1414 | cmd_free(h, cp); |
2cc5bfaf | 1415 | cmd->scsi_done(cmd); |
edd16368 SC |
1416 | } |
1417 | ||
edd16368 SC |
1418 | static void hpsa_pci_unmap(struct pci_dev *pdev, |
1419 | struct CommandList *c, int sg_used, int data_direction) | |
1420 | { | |
1421 | int i; | |
1422 | union u64bit addr64; | |
1423 | ||
1424 | for (i = 0; i < sg_used; i++) { | |
1425 | addr64.val32.lower = c->SG[i].Addr.lower; | |
1426 | addr64.val32.upper = c->SG[i].Addr.upper; | |
1427 | pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len, | |
1428 | data_direction); | |
1429 | } | |
1430 | } | |
1431 | ||
a2dac136 | 1432 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
1433 | struct CommandList *cp, |
1434 | unsigned char *buf, | |
1435 | size_t buflen, | |
1436 | int data_direction) | |
1437 | { | |
01a02ffc | 1438 | u64 addr64; |
edd16368 SC |
1439 | |
1440 | if (buflen == 0 || data_direction == PCI_DMA_NONE) { | |
1441 | cp->Header.SGList = 0; | |
1442 | cp->Header.SGTotal = 0; | |
a2dac136 | 1443 | return 0; |
edd16368 SC |
1444 | } |
1445 | ||
01a02ffc | 1446 | addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction); |
eceaae18 | 1447 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 1448 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 SK |
1449 | cp->Header.SGList = 0; |
1450 | cp->Header.SGTotal = 0; | |
a2dac136 | 1451 | return -1; |
eceaae18 | 1452 | } |
edd16368 | 1453 | cp->SG[0].Addr.lower = |
01a02ffc | 1454 | (u32) (addr64 & (u64) 0x00000000FFFFFFFF); |
edd16368 | 1455 | cp->SG[0].Addr.upper = |
01a02ffc | 1456 | (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF); |
edd16368 | 1457 | cp->SG[0].Len = buflen; |
e1d9cbfa | 1458 | cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */ |
01a02ffc SC |
1459 | cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */ |
1460 | cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */ | |
a2dac136 | 1461 | return 0; |
edd16368 SC |
1462 | } |
1463 | ||
1464 | static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
1465 | struct CommandList *c) | |
1466 | { | |
1467 | DECLARE_COMPLETION_ONSTACK(wait); | |
1468 | ||
1469 | c->waiting = &wait; | |
1470 | enqueue_cmd_and_start_io(h, c); | |
1471 | wait_for_completion(&wait); | |
1472 | } | |
1473 | ||
a0c12413 SC |
1474 | static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h, |
1475 | struct CommandList *c) | |
1476 | { | |
1477 | unsigned long flags; | |
1478 | ||
1479 | /* If controller lockup detected, fake a hardware error. */ | |
1480 | spin_lock_irqsave(&h->lock, flags); | |
1481 | if (unlikely(h->lockup_detected)) { | |
1482 | spin_unlock_irqrestore(&h->lock, flags); | |
1483 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; | |
1484 | } else { | |
1485 | spin_unlock_irqrestore(&h->lock, flags); | |
1486 | hpsa_scsi_do_simple_cmd_core(h, c); | |
1487 | } | |
1488 | } | |
1489 | ||
9c2fc160 | 1490 | #define MAX_DRIVER_CMD_RETRIES 25 |
edd16368 SC |
1491 | static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
1492 | struct CommandList *c, int data_direction) | |
1493 | { | |
9c2fc160 | 1494 | int backoff_time = 10, retry_count = 0; |
edd16368 SC |
1495 | |
1496 | do { | |
7630abd0 | 1497 | memset(c->err_info, 0, sizeof(*c->err_info)); |
edd16368 SC |
1498 | hpsa_scsi_do_simple_cmd_core(h, c); |
1499 | retry_count++; | |
9c2fc160 SC |
1500 | if (retry_count > 3) { |
1501 | msleep(backoff_time); | |
1502 | if (backoff_time < 1000) | |
1503 | backoff_time *= 2; | |
1504 | } | |
852af20a | 1505 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
1506 | check_for_busy(h, c)) && |
1507 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 SC |
1508 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
1509 | } | |
1510 | ||
1511 | static void hpsa_scsi_interpret_error(struct CommandList *cp) | |
1512 | { | |
1513 | struct ErrorInfo *ei; | |
1514 | struct device *d = &cp->h->pdev->dev; | |
1515 | ||
1516 | ei = cp->err_info; | |
1517 | switch (ei->CommandStatus) { | |
1518 | case CMD_TARGET_STATUS: | |
1519 | dev_warn(d, "cmd %p has completed with errors\n", cp); | |
1520 | dev_warn(d, "cmd %p has SCSI Status = %x\n", cp, | |
1521 | ei->ScsiStatus); | |
1522 | if (ei->ScsiStatus == 0) | |
1523 | dev_warn(d, "SCSI status is abnormally zero. " | |
1524 | "(probably indicates selection timeout " | |
1525 | "reported incorrectly due to a known " | |
1526 | "firmware bug, circa July, 2001.)\n"); | |
1527 | break; | |
1528 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
1529 | dev_info(d, "UNDERRUN\n"); | |
1530 | break; | |
1531 | case CMD_DATA_OVERRUN: | |
1532 | dev_warn(d, "cp %p has completed with data overrun\n", cp); | |
1533 | break; | |
1534 | case CMD_INVALID: { | |
1535 | /* controller unfortunately reports SCSI passthru's | |
1536 | * to non-existent targets as invalid commands. | |
1537 | */ | |
1538 | dev_warn(d, "cp %p is reported invalid (probably means " | |
1539 | "target device no longer present)\n", cp); | |
1540 | /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0); | |
1541 | print_cmd(cp); */ | |
1542 | } | |
1543 | break; | |
1544 | case CMD_PROTOCOL_ERR: | |
1545 | dev_warn(d, "cp %p has protocol error \n", cp); | |
1546 | break; | |
1547 | case CMD_HARDWARE_ERR: | |
1548 | /* cmd->result = DID_ERROR << 16; */ | |
1549 | dev_warn(d, "cp %p had hardware error\n", cp); | |
1550 | break; | |
1551 | case CMD_CONNECTION_LOST: | |
1552 | dev_warn(d, "cp %p had connection lost\n", cp); | |
1553 | break; | |
1554 | case CMD_ABORTED: | |
1555 | dev_warn(d, "cp %p was aborted\n", cp); | |
1556 | break; | |
1557 | case CMD_ABORT_FAILED: | |
1558 | dev_warn(d, "cp %p reports abort failed\n", cp); | |
1559 | break; | |
1560 | case CMD_UNSOLICITED_ABORT: | |
1561 | dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp); | |
1562 | break; | |
1563 | case CMD_TIMEOUT: | |
1564 | dev_warn(d, "cp %p timed out\n", cp); | |
1565 | break; | |
1d5e2ed0 SC |
1566 | case CMD_UNABORTABLE: |
1567 | dev_warn(d, "Command unabortable\n"); | |
1568 | break; | |
edd16368 SC |
1569 | default: |
1570 | dev_warn(d, "cp %p returned unknown status %x\n", cp, | |
1571 | ei->CommandStatus); | |
1572 | } | |
1573 | } | |
1574 | ||
1575 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, | |
1576 | unsigned char page, unsigned char *buf, | |
1577 | unsigned char bufsize) | |
1578 | { | |
1579 | int rc = IO_OK; | |
1580 | struct CommandList *c; | |
1581 | struct ErrorInfo *ei; | |
1582 | ||
1583 | c = cmd_special_alloc(h); | |
1584 | ||
1585 | if (c == NULL) { /* trouble... */ | |
1586 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
ecd9aad4 | 1587 | return -ENOMEM; |
edd16368 SC |
1588 | } |
1589 | ||
a2dac136 SC |
1590 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
1591 | page, scsi3addr, TYPE_CMD)) { | |
1592 | rc = -1; | |
1593 | goto out; | |
1594 | } | |
edd16368 SC |
1595 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); |
1596 | ei = c->err_info; | |
1597 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
1598 | hpsa_scsi_interpret_error(c); | |
1599 | rc = -1; | |
1600 | } | |
a2dac136 | 1601 | out: |
edd16368 SC |
1602 | cmd_special_free(h, c); |
1603 | return rc; | |
1604 | } | |
1605 | ||
1606 | static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr) | |
1607 | { | |
1608 | int rc = IO_OK; | |
1609 | struct CommandList *c; | |
1610 | struct ErrorInfo *ei; | |
1611 | ||
1612 | c = cmd_special_alloc(h); | |
1613 | ||
1614 | if (c == NULL) { /* trouble... */ | |
1615 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
e9ea04a6 | 1616 | return -ENOMEM; |
edd16368 SC |
1617 | } |
1618 | ||
a2dac136 SC |
1619 | /* fill_cmd can't fail here, no data buffer to map. */ |
1620 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, | |
1621 | NULL, 0, 0, scsi3addr, TYPE_MSG); | |
edd16368 SC |
1622 | hpsa_scsi_do_simple_cmd_core(h, c); |
1623 | /* no unmap needed here because no data xfer. */ | |
1624 | ||
1625 | ei = c->err_info; | |
1626 | if (ei->CommandStatus != 0) { | |
1627 | hpsa_scsi_interpret_error(c); | |
1628 | rc = -1; | |
1629 | } | |
1630 | cmd_special_free(h, c); | |
1631 | return rc; | |
1632 | } | |
1633 | ||
1634 | static void hpsa_get_raid_level(struct ctlr_info *h, | |
1635 | unsigned char *scsi3addr, unsigned char *raid_level) | |
1636 | { | |
1637 | int rc; | |
1638 | unsigned char *buf; | |
1639 | ||
1640 | *raid_level = RAID_UNKNOWN; | |
1641 | buf = kzalloc(64, GFP_KERNEL); | |
1642 | if (!buf) | |
1643 | return; | |
1644 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64); | |
1645 | if (rc == 0) | |
1646 | *raid_level = buf[8]; | |
1647 | if (*raid_level > RAID_UNKNOWN) | |
1648 | *raid_level = RAID_UNKNOWN; | |
1649 | kfree(buf); | |
1650 | return; | |
1651 | } | |
1652 | ||
1653 | /* Get the device id from inquiry page 0x83 */ | |
1654 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
1655 | unsigned char *device_id, int buflen) | |
1656 | { | |
1657 | int rc; | |
1658 | unsigned char *buf; | |
1659 | ||
1660 | if (buflen > 16) | |
1661 | buflen = 16; | |
1662 | buf = kzalloc(64, GFP_KERNEL); | |
1663 | if (!buf) | |
1664 | return -1; | |
1665 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64); | |
1666 | if (rc == 0) | |
1667 | memcpy(device_id, &buf[8], buflen); | |
1668 | kfree(buf); | |
1669 | return rc != 0; | |
1670 | } | |
1671 | ||
1672 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
1673 | struct ReportLUNdata *buf, int bufsize, | |
1674 | int extended_response) | |
1675 | { | |
1676 | int rc = IO_OK; | |
1677 | struct CommandList *c; | |
1678 | unsigned char scsi3addr[8]; | |
1679 | struct ErrorInfo *ei; | |
1680 | ||
1681 | c = cmd_special_alloc(h); | |
1682 | if (c == NULL) { /* trouble... */ | |
1683 | dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
1684 | return -1; | |
1685 | } | |
e89c0ae7 SC |
1686 | /* address the controller */ |
1687 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
1688 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
1689 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
1690 | rc = -1; | |
1691 | goto out; | |
1692 | } | |
edd16368 SC |
1693 | if (extended_response) |
1694 | c->Request.CDB[1] = extended_response; | |
1695 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
1696 | ei = c->err_info; | |
1697 | if (ei->CommandStatus != 0 && | |
1698 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
1699 | hpsa_scsi_interpret_error(c); | |
1700 | rc = -1; | |
1701 | } | |
a2dac136 | 1702 | out: |
edd16368 SC |
1703 | cmd_special_free(h, c); |
1704 | return rc; | |
1705 | } | |
1706 | ||
1707 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
1708 | struct ReportLUNdata *buf, | |
1709 | int bufsize, int extended_response) | |
1710 | { | |
1711 | return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response); | |
1712 | } | |
1713 | ||
1714 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
1715 | struct ReportLUNdata *buf, int bufsize) | |
1716 | { | |
1717 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
1718 | } | |
1719 | ||
1720 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
1721 | int bus, int target, int lun) | |
1722 | { | |
1723 | device->bus = bus; | |
1724 | device->target = target; | |
1725 | device->lun = lun; | |
1726 | } | |
1727 | ||
1728 | static int hpsa_update_device_info(struct ctlr_info *h, | |
0b0e1d6c SC |
1729 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
1730 | unsigned char *is_OBDR_device) | |
edd16368 | 1731 | { |
0b0e1d6c SC |
1732 | |
1733 | #define OBDR_SIG_OFFSET 43 | |
1734 | #define OBDR_TAPE_SIG "$DR-10" | |
1735 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
1736 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
1737 | ||
ea6d3bc3 | 1738 | unsigned char *inq_buff; |
0b0e1d6c | 1739 | unsigned char *obdr_sig; |
edd16368 | 1740 | |
ea6d3bc3 | 1741 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
edd16368 SC |
1742 | if (!inq_buff) |
1743 | goto bail_out; | |
1744 | ||
edd16368 SC |
1745 | /* Do an inquiry to the device to see what it is. */ |
1746 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
1747 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
1748 | /* Inquiry failed (msg printed already) */ | |
1749 | dev_err(&h->pdev->dev, | |
1750 | "hpsa_update_device_info: inquiry failed\n"); | |
1751 | goto bail_out; | |
1752 | } | |
1753 | ||
edd16368 SC |
1754 | this_device->devtype = (inq_buff[0] & 0x1f); |
1755 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
1756 | memcpy(this_device->vendor, &inq_buff[8], | |
1757 | sizeof(this_device->vendor)); | |
1758 | memcpy(this_device->model, &inq_buff[16], | |
1759 | sizeof(this_device->model)); | |
edd16368 SC |
1760 | memset(this_device->device_id, 0, |
1761 | sizeof(this_device->device_id)); | |
1762 | hpsa_get_device_id(h, scsi3addr, this_device->device_id, | |
1763 | sizeof(this_device->device_id)); | |
1764 | ||
1765 | if (this_device->devtype == TYPE_DISK && | |
1766 | is_logical_dev_addr_mode(scsi3addr)) | |
1767 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); | |
1768 | else | |
1769 | this_device->raid_level = RAID_UNKNOWN; | |
1770 | ||
0b0e1d6c SC |
1771 | if (is_OBDR_device) { |
1772 | /* See if this is a One-Button-Disaster-Recovery device | |
1773 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
1774 | */ | |
1775 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
1776 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
1777 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
1778 | OBDR_SIG_LEN) == 0); | |
1779 | } | |
1780 | ||
edd16368 SC |
1781 | kfree(inq_buff); |
1782 | return 0; | |
1783 | ||
1784 | bail_out: | |
1785 | kfree(inq_buff); | |
1786 | return 1; | |
1787 | } | |
1788 | ||
4f4eb9f1 | 1789 | static unsigned char *ext_target_model[] = { |
edd16368 SC |
1790 | "MSA2012", |
1791 | "MSA2024", | |
1792 | "MSA2312", | |
1793 | "MSA2324", | |
fda38518 | 1794 | "P2000 G3 SAS", |
e06c8e5c | 1795 | "MSA 2040 SAS", |
edd16368 SC |
1796 | NULL, |
1797 | }; | |
1798 | ||
4f4eb9f1 | 1799 | static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
edd16368 SC |
1800 | { |
1801 | int i; | |
1802 | ||
4f4eb9f1 ST |
1803 | for (i = 0; ext_target_model[i]; i++) |
1804 | if (strncmp(device->model, ext_target_model[i], | |
1805 | strlen(ext_target_model[i])) == 0) | |
edd16368 SC |
1806 | return 1; |
1807 | return 0; | |
1808 | } | |
1809 | ||
1810 | /* Helper function to assign bus, target, lun mapping of devices. | |
4f4eb9f1 | 1811 | * Puts non-external target logical volumes on bus 0, external target logical |
edd16368 SC |
1812 | * volumes on bus 1, physical devices on bus 2. and the hba on bus 3. |
1813 | * Logical drive target and lun are assigned at this time, but | |
1814 | * physical device lun and target assignment are deferred (assigned | |
1815 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
1816 | */ | |
1817 | static void figure_bus_target_lun(struct ctlr_info *h, | |
1f310bde | 1818 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 1819 | { |
1f310bde SC |
1820 | u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes)); |
1821 | ||
1822 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
1823 | /* physical device, target and lun filled in later */ | |
edd16368 | 1824 | if (is_hba_lunid(lunaddrbytes)) |
1f310bde | 1825 | hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff); |
edd16368 | 1826 | else |
1f310bde SC |
1827 | /* defer target, lun assignment for physical devices */ |
1828 | hpsa_set_bus_target_lun(device, 2, -1, -1); | |
1829 | return; | |
1830 | } | |
1831 | /* It's a logical device */ | |
4f4eb9f1 ST |
1832 | if (is_ext_target(h, device)) { |
1833 | /* external target way, put logicals on bus 1 | |
1f310bde SC |
1834 | * and match target/lun numbers box |
1835 | * reports, other smart array, bus 0, target 0, match lunid | |
1836 | */ | |
1837 | hpsa_set_bus_target_lun(device, | |
1838 | 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff); | |
1839 | return; | |
edd16368 | 1840 | } |
1f310bde | 1841 | hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff); |
edd16368 SC |
1842 | } |
1843 | ||
1844 | /* | |
1845 | * If there is no lun 0 on a target, linux won't find any devices. | |
4f4eb9f1 | 1846 | * For the external targets (arrays), we have to manually detect the enclosure |
edd16368 SC |
1847 | * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report |
1848 | * it for some reason. *tmpdevice is the target we're adding, | |
1849 | * this_device is a pointer into the current element of currentsd[] | |
1850 | * that we're building up in update_scsi_devices(), below. | |
1851 | * lunzerobits is a bitmap that tracks which targets already have a | |
1852 | * lun 0 assigned. | |
1853 | * Returns 1 if an enclosure was added, 0 if not. | |
1854 | */ | |
4f4eb9f1 | 1855 | static int add_ext_target_dev(struct ctlr_info *h, |
edd16368 | 1856 | struct hpsa_scsi_dev_t *tmpdevice, |
01a02ffc | 1857 | struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes, |
4f4eb9f1 | 1858 | unsigned long lunzerobits[], int *n_ext_target_devs) |
edd16368 SC |
1859 | { |
1860 | unsigned char scsi3addr[8]; | |
1861 | ||
1f310bde | 1862 | if (test_bit(tmpdevice->target, lunzerobits)) |
edd16368 SC |
1863 | return 0; /* There is already a lun 0 on this target. */ |
1864 | ||
1865 | if (!is_logical_dev_addr_mode(lunaddrbytes)) | |
1866 | return 0; /* It's the logical targets that may lack lun 0. */ | |
1867 | ||
4f4eb9f1 ST |
1868 | if (!is_ext_target(h, tmpdevice)) |
1869 | return 0; /* Only external target devices have this problem. */ | |
edd16368 | 1870 | |
1f310bde | 1871 | if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */ |
edd16368 SC |
1872 | return 0; |
1873 | ||
c4f8a299 | 1874 | memset(scsi3addr, 0, 8); |
1f310bde | 1875 | scsi3addr[3] = tmpdevice->target; |
edd16368 SC |
1876 | if (is_hba_lunid(scsi3addr)) |
1877 | return 0; /* Don't add the RAID controller here. */ | |
1878 | ||
339b2b14 SC |
1879 | if (is_scsi_rev_5(h)) |
1880 | return 0; /* p1210m doesn't need to do this. */ | |
1881 | ||
4f4eb9f1 | 1882 | if (*n_ext_target_devs >= MAX_EXT_TARGETS) { |
aca4a520 ST |
1883 | dev_warn(&h->pdev->dev, "Maximum number of external " |
1884 | "target devices exceeded. Check your hardware " | |
edd16368 SC |
1885 | "configuration."); |
1886 | return 0; | |
1887 | } | |
1888 | ||
0b0e1d6c | 1889 | if (hpsa_update_device_info(h, scsi3addr, this_device, NULL)) |
edd16368 | 1890 | return 0; |
4f4eb9f1 | 1891 | (*n_ext_target_devs)++; |
1f310bde SC |
1892 | hpsa_set_bus_target_lun(this_device, |
1893 | tmpdevice->bus, tmpdevice->target, 0); | |
1894 | set_bit(tmpdevice->target, lunzerobits); | |
edd16368 SC |
1895 | return 1; |
1896 | } | |
1897 | ||
1898 | /* | |
1899 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
1900 | * logdev. The number of luns in physdev and logdev are returned in | |
1901 | * *nphysicals and *nlogicals, respectively. | |
1902 | * Returns 0 on success, -1 otherwise. | |
1903 | */ | |
1904 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
1905 | int reportlunsize, | |
01a02ffc SC |
1906 | struct ReportLUNdata *physdev, u32 *nphysicals, |
1907 | struct ReportLUNdata *logdev, u32 *nlogicals) | |
edd16368 | 1908 | { |
a93aa1fe MG |
1909 | if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize, |
1910 | HPSA_REPORT_PHYS_EXTENDED)) { | |
edd16368 SC |
1911 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
1912 | return -1; | |
1913 | } | |
a93aa1fe | 1914 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; |
edd16368 SC |
1915 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
1916 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded." | |
1917 | " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
1918 | *nphysicals - HPSA_MAX_PHYS_LUN); | |
1919 | *nphysicals = HPSA_MAX_PHYS_LUN; | |
1920 | } | |
1921 | if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) { | |
1922 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); | |
1923 | return -1; | |
1924 | } | |
6df1e954 | 1925 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
1926 | /* Reject Logicals in excess of our max capability. */ |
1927 | if (*nlogicals > HPSA_MAX_LUN) { | |
1928 | dev_warn(&h->pdev->dev, | |
1929 | "maximum logical LUNs (%d) exceeded. " | |
1930 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
1931 | *nlogicals - HPSA_MAX_LUN); | |
1932 | *nlogicals = HPSA_MAX_LUN; | |
1933 | } | |
1934 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
1935 | dev_warn(&h->pdev->dev, | |
1936 | "maximum logical + physical LUNs (%d) exceeded. " | |
1937 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
1938 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
1939 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
1940 | } | |
1941 | return 0; | |
1942 | } | |
1943 | ||
339b2b14 | 1944 | u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i, |
a93aa1fe MG |
1945 | int nphysicals, int nlogicals, |
1946 | struct ReportExtendedLUNdata *physdev_list, | |
339b2b14 SC |
1947 | struct ReportLUNdata *logdev_list) |
1948 | { | |
1949 | /* Helper function, figure out where the LUN ID info is coming from | |
1950 | * given index i, lists of physical and logical devices, where in | |
1951 | * the list the raid controller is supposed to appear (first or last) | |
1952 | */ | |
1953 | ||
1954 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
1955 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
1956 | ||
1957 | if (i == raid_ctlr_position) | |
1958 | return RAID_CTLR_LUNID; | |
1959 | ||
1960 | if (i < logicals_start) | |
1961 | return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0]; | |
1962 | ||
1963 | if (i < last_device) | |
1964 | return &logdev_list->LUN[i - nphysicals - | |
1965 | (raid_ctlr_position == 0)][0]; | |
1966 | BUG(); | |
1967 | return NULL; | |
1968 | } | |
1969 | ||
edd16368 SC |
1970 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno) |
1971 | { | |
1972 | /* the idea here is we could get notified | |
1973 | * that some devices have changed, so we do a report | |
1974 | * physical luns and report logical luns cmd, and adjust | |
1975 | * our list of devices accordingly. | |
1976 | * | |
1977 | * The scsi3addr's of devices won't change so long as the | |
1978 | * adapter is not reset. That means we can rescan and | |
1979 | * tell which devices we already know about, vs. new | |
1980 | * devices, vs. disappearing devices. | |
1981 | */ | |
a93aa1fe | 1982 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 1983 | struct ReportLUNdata *logdev_list = NULL; |
01a02ffc SC |
1984 | u32 nphysicals = 0; |
1985 | u32 nlogicals = 0; | |
1986 | u32 ndev_allocated = 0; | |
edd16368 SC |
1987 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
1988 | int ncurrent = 0; | |
1989 | int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 8; | |
4f4eb9f1 | 1990 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 1991 | int raid_ctlr_position; |
aca4a520 | 1992 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 1993 | |
cfe5badc | 1994 | currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); |
edd16368 SC |
1995 | physdev_list = kzalloc(reportlunsize, GFP_KERNEL); |
1996 | logdev_list = kzalloc(reportlunsize, GFP_KERNEL); | |
edd16368 SC |
1997 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
1998 | ||
0b0e1d6c | 1999 | if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) { |
edd16368 SC |
2000 | dev_err(&h->pdev->dev, "out of memory\n"); |
2001 | goto out; | |
2002 | } | |
2003 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
2004 | ||
a93aa1fe MG |
2005 | if (hpsa_gather_lun_info(h, reportlunsize, |
2006 | (struct ReportLUNdata *) physdev_list, &nphysicals, | |
edd16368 SC |
2007 | logdev_list, &nlogicals)) |
2008 | goto out; | |
2009 | ||
aca4a520 ST |
2010 | /* We might see up to the maximum number of logical and physical disks |
2011 | * plus external target devices, and a device for the local RAID | |
2012 | * controller. | |
edd16368 | 2013 | */ |
aca4a520 | 2014 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 SC |
2015 | |
2016 | /* Allocate the per device structures */ | |
2017 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
2018 | if (i >= HPSA_MAX_DEVICES) { |
2019 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
2020 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
2021 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
2022 | break; | |
2023 | } | |
2024 | ||
edd16368 SC |
2025 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
2026 | if (!currentsd[i]) { | |
2027 | dev_warn(&h->pdev->dev, "out of memory at %s:%d\n", | |
2028 | __FILE__, __LINE__); | |
2029 | goto out; | |
2030 | } | |
2031 | ndev_allocated++; | |
2032 | } | |
2033 | ||
339b2b14 SC |
2034 | if (unlikely(is_scsi_rev_5(h))) |
2035 | raid_ctlr_position = 0; | |
2036 | else | |
2037 | raid_ctlr_position = nphysicals + nlogicals; | |
2038 | ||
edd16368 | 2039 | /* adjust our table of devices */ |
4f4eb9f1 | 2040 | n_ext_target_devs = 0; |
edd16368 | 2041 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 2042 | u8 *lunaddrbytes, is_OBDR = 0; |
edd16368 SC |
2043 | |
2044 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
2045 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
2046 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
edd16368 | 2047 | /* skip masked physical devices. */ |
339b2b14 SC |
2048 | if (lunaddrbytes[3] & 0xC0 && |
2049 | i < nphysicals + (raid_ctlr_position == 0)) | |
edd16368 SC |
2050 | continue; |
2051 | ||
2052 | /* Get device type, vendor, model, device id */ | |
0b0e1d6c SC |
2053 | if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
2054 | &is_OBDR)) | |
edd16368 | 2055 | continue; /* skip it if we can't talk to it. */ |
1f310bde | 2056 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
edd16368 SC |
2057 | this_device = currentsd[ncurrent]; |
2058 | ||
2059 | /* | |
4f4eb9f1 | 2060 | * For external target devices, we have to insert a LUN 0 which |
edd16368 SC |
2061 | * doesn't show up in CCISS_REPORT_PHYSICAL data, but there |
2062 | * is nonetheless an enclosure device there. We have to | |
2063 | * present that otherwise linux won't find anything if | |
2064 | * there is no lun 0. | |
2065 | */ | |
4f4eb9f1 | 2066 | if (add_ext_target_dev(h, tmpdevice, this_device, |
1f310bde | 2067 | lunaddrbytes, lunzerobits, |
4f4eb9f1 | 2068 | &n_ext_target_devs)) { |
edd16368 SC |
2069 | ncurrent++; |
2070 | this_device = currentsd[ncurrent]; | |
2071 | } | |
2072 | ||
2073 | *this_device = *tmpdevice; | |
edd16368 SC |
2074 | |
2075 | switch (this_device->devtype) { | |
0b0e1d6c | 2076 | case TYPE_ROM: |
edd16368 SC |
2077 | /* We don't *really* support actual CD-ROM devices, |
2078 | * just "One Button Disaster Recovery" tape drive | |
2079 | * which temporarily pretends to be a CD-ROM drive. | |
2080 | * So we check that the device is really an OBDR tape | |
2081 | * device by checking for "$DR-10" in bytes 43-48 of | |
2082 | * the inquiry data. | |
2083 | */ | |
0b0e1d6c SC |
2084 | if (is_OBDR) |
2085 | ncurrent++; | |
edd16368 SC |
2086 | break; |
2087 | case TYPE_DISK: | |
2088 | if (i < nphysicals) | |
2089 | break; | |
e1f7de0c MG |
2090 | memcpy(&this_device->ioaccel_handle, |
2091 | &lunaddrbytes[20], | |
2092 | sizeof(this_device->ioaccel_handle)); | |
edd16368 SC |
2093 | ncurrent++; |
2094 | break; | |
2095 | case TYPE_TAPE: | |
2096 | case TYPE_MEDIUM_CHANGER: | |
2097 | ncurrent++; | |
2098 | break; | |
2099 | case TYPE_RAID: | |
2100 | /* Only present the Smartarray HBA as a RAID controller. | |
2101 | * If it's a RAID controller other than the HBA itself | |
2102 | * (an external RAID controller, MSA500 or similar) | |
2103 | * don't present it. | |
2104 | */ | |
2105 | if (!is_hba_lunid(lunaddrbytes)) | |
2106 | break; | |
2107 | ncurrent++; | |
2108 | break; | |
2109 | default: | |
2110 | break; | |
2111 | } | |
cfe5badc | 2112 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
2113 | break; |
2114 | } | |
2115 | adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent); | |
2116 | out: | |
2117 | kfree(tmpdevice); | |
2118 | for (i = 0; i < ndev_allocated; i++) | |
2119 | kfree(currentsd[i]); | |
2120 | kfree(currentsd); | |
edd16368 SC |
2121 | kfree(physdev_list); |
2122 | kfree(logdev_list); | |
edd16368 SC |
2123 | } |
2124 | ||
2125 | /* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
2126 | * dma mapping and fills in the scatter gather entries of the | |
2127 | * hpsa command, cp. | |
2128 | */ | |
33a2ffce | 2129 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
2130 | struct CommandList *cp, |
2131 | struct scsi_cmnd *cmd) | |
2132 | { | |
2133 | unsigned int len; | |
2134 | struct scatterlist *sg; | |
01a02ffc | 2135 | u64 addr64; |
33a2ffce SC |
2136 | int use_sg, i, sg_index, chained; |
2137 | struct SGDescriptor *curr_sg; | |
edd16368 | 2138 | |
33a2ffce | 2139 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
2140 | |
2141 | use_sg = scsi_dma_map(cmd); | |
2142 | if (use_sg < 0) | |
2143 | return use_sg; | |
2144 | ||
2145 | if (!use_sg) | |
2146 | goto sglist_finished; | |
2147 | ||
33a2ffce SC |
2148 | curr_sg = cp->SG; |
2149 | chained = 0; | |
2150 | sg_index = 0; | |
edd16368 | 2151 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
33a2ffce SC |
2152 | if (i == h->max_cmd_sg_entries - 1 && |
2153 | use_sg > h->max_cmd_sg_entries) { | |
2154 | chained = 1; | |
2155 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
2156 | sg_index = 0; | |
2157 | } | |
01a02ffc | 2158 | addr64 = (u64) sg_dma_address(sg); |
edd16368 | 2159 | len = sg_dma_len(sg); |
33a2ffce SC |
2160 | curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL); |
2161 | curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL); | |
2162 | curr_sg->Len = len; | |
e1d9cbfa | 2163 | curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST; |
33a2ffce SC |
2164 | curr_sg++; |
2165 | } | |
2166 | ||
2167 | if (use_sg + chained > h->maxSG) | |
2168 | h->maxSG = use_sg + chained; | |
2169 | ||
2170 | if (chained) { | |
2171 | cp->Header.SGList = h->max_cmd_sg_entries; | |
2172 | cp->Header.SGTotal = (u16) (use_sg + 1); | |
e2bea6df SC |
2173 | if (hpsa_map_sg_chain_block(h, cp)) { |
2174 | scsi_dma_unmap(cmd); | |
2175 | return -1; | |
2176 | } | |
33a2ffce | 2177 | return 0; |
edd16368 SC |
2178 | } |
2179 | ||
2180 | sglist_finished: | |
2181 | ||
01a02ffc SC |
2182 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
2183 | cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */ | |
edd16368 SC |
2184 | return 0; |
2185 | } | |
2186 | ||
e1f7de0c MG |
2187 | /* |
2188 | * Queue a command to the I/O accelerator path. | |
2189 | * This method does not currently support S/G chaining. | |
2190 | */ | |
2191 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
2192 | struct CommandList *c) | |
2193 | { | |
2194 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
2195 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
2196 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
2197 | unsigned int len; | |
2198 | unsigned int total_len = 0; | |
2199 | struct scatterlist *sg; | |
2200 | u64 addr64; | |
2201 | int use_sg, i; | |
2202 | struct SGDescriptor *curr_sg; | |
2203 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
2204 | ||
2205 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); | |
2206 | ||
2207 | c->cmd_type = CMD_IOACCEL1; | |
2208 | ||
2209 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
2210 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
2211 | (c->cmdindex * sizeof(*cp)); | |
2212 | BUG_ON(c->busaddr & 0x0000007F); | |
2213 | ||
2214 | use_sg = scsi_dma_map(cmd); | |
2215 | if (use_sg < 0) | |
2216 | return use_sg; | |
2217 | ||
2218 | if (use_sg) { | |
2219 | curr_sg = cp->SG; | |
2220 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
2221 | addr64 = (u64) sg_dma_address(sg); | |
2222 | len = sg_dma_len(sg); | |
2223 | total_len += len; | |
2224 | curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL); | |
2225 | curr_sg->Addr.upper = | |
2226 | (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL); | |
2227 | curr_sg->Len = len; | |
2228 | ||
2229 | if (i == (scsi_sg_count(cmd) - 1)) | |
2230 | curr_sg->Ext = HPSA_SG_LAST; | |
2231 | else | |
2232 | curr_sg->Ext = 0; /* we are not chaining */ | |
2233 | curr_sg++; | |
2234 | } | |
2235 | ||
2236 | switch (cmd->sc_data_direction) { | |
2237 | case DMA_TO_DEVICE: | |
2238 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
2239 | break; | |
2240 | case DMA_FROM_DEVICE: | |
2241 | control |= IOACCEL1_CONTROL_DATA_IN; | |
2242 | break; | |
2243 | case DMA_NONE: | |
2244 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
2245 | break; | |
2246 | default: | |
2247 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
2248 | cmd->sc_data_direction); | |
2249 | BUG(); | |
2250 | break; | |
2251 | } | |
2252 | } else { | |
2253 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
2254 | } | |
2255 | ||
2256 | /* Fill out the command structure to submit */ | |
2257 | cp->dev_handle = dev->ioaccel_handle; | |
2258 | cp->transfer_len = total_len; | |
2259 | cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ | | |
2260 | (cmd->cmd_len & IOACCEL1_IOFLAGS_CDBLEN_MASK); | |
2261 | cp->control = control; | |
2262 | memcpy(cp->CDB, cmd->cmnd, cmd->cmd_len); | |
2263 | memcpy(cp->CISS_LUN, dev->scsi3addr, 8); | |
2264 | ||
2265 | /* Tell the controller to post the reply to the queue for this | |
2266 | * processor. This seems to give the best I/O throughput. | |
2267 | */ | |
2268 | cp->ReplyQueue = smp_processor_id() % h->nreply_queues; | |
2269 | ||
2270 | /* Set the bits in the address sent down to include: | |
2271 | * - performant mode bit (bit 0) | |
2272 | * - pull count (bits 1-3) | |
2273 | * - command type (bits 4-6) | |
2274 | */ | |
2275 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[use_sg] << 1) | | |
2276 | IOACCEL1_BUSADDR_CMDTYPE; | |
2277 | ||
2278 | /* execute command (bypassing cmd queue if possible) */ | |
2279 | if (unlikely(h->access.fifo_full(h))) | |
2280 | enqueue_cmd_and_start_io(h, c); | |
2281 | else | |
2282 | h->access.submit_command(h, c); | |
2283 | return 0; | |
2284 | } | |
edd16368 | 2285 | |
f281233d | 2286 | static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd, |
edd16368 SC |
2287 | void (*done)(struct scsi_cmnd *)) |
2288 | { | |
2289 | struct ctlr_info *h; | |
2290 | struct hpsa_scsi_dev_t *dev; | |
2291 | unsigned char scsi3addr[8]; | |
2292 | struct CommandList *c; | |
2293 | unsigned long flags; | |
2294 | ||
2295 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
2296 | h = sdev_to_hba(cmd->device); | |
2297 | dev = cmd->device->hostdata; | |
2298 | if (!dev) { | |
2299 | cmd->result = DID_NO_CONNECT << 16; | |
2300 | done(cmd); | |
2301 | return 0; | |
2302 | } | |
2303 | memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); | |
2304 | ||
edd16368 | 2305 | spin_lock_irqsave(&h->lock, flags); |
a0c12413 SC |
2306 | if (unlikely(h->lockup_detected)) { |
2307 | spin_unlock_irqrestore(&h->lock, flags); | |
2308 | cmd->result = DID_ERROR << 16; | |
2309 | done(cmd); | |
2310 | return 0; | |
2311 | } | |
edd16368 | 2312 | spin_unlock_irqrestore(&h->lock, flags); |
e16a33ad | 2313 | c = cmd_alloc(h); |
edd16368 SC |
2314 | if (c == NULL) { /* trouble... */ |
2315 | dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n"); | |
2316 | return SCSI_MLQUEUE_HOST_BUSY; | |
2317 | } | |
2318 | ||
2319 | /* Fill in the command list header */ | |
2320 | ||
2321 | cmd->scsi_done = done; /* save this for use by completion code */ | |
2322 | ||
2323 | /* save c in case we have to abort it */ | |
2324 | cmd->host_scribble = (unsigned char *) c; | |
2325 | ||
2326 | c->cmd_type = CMD_SCSI; | |
2327 | c->scsi_cmd = cmd; | |
e1f7de0c MG |
2328 | |
2329 | /* Call alternate submit routine for I/O accelerated commands */ | |
2330 | if ((likely(h->transMethod & CFGTBL_Trans_io_accel1)) && | |
2331 | (dev->ioaccel_handle) && | |
2332 | ((cmd->cmnd[0] == READ_10) || (cmd->cmnd[0] == WRITE_10)) && | |
2f6ae5cd SC |
2333 | (scsi_sg_count(cmd) <= IOACCEL1_MAXSGENTRIES) && |
2334 | likely(cmd->request->cmd_type == REQ_TYPE_FS)) | |
e1f7de0c MG |
2335 | return hpsa_scsi_ioaccel_queue_command(h, c); |
2336 | ||
edd16368 SC |
2337 | c->Header.ReplyQueue = 0; /* unused in simple mode */ |
2338 | memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); | |
303932fd DB |
2339 | c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT); |
2340 | c->Header.Tag.lower |= DIRECT_LOOKUP_BIT; | |
edd16368 SC |
2341 | |
2342 | /* Fill in the request block... */ | |
2343 | ||
2344 | c->Request.Timeout = 0; | |
2345 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); | |
2346 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); | |
2347 | c->Request.CDBLen = cmd->cmd_len; | |
2348 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
2349 | c->Request.Type.Type = TYPE_CMD; | |
2350 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
2351 | switch (cmd->sc_data_direction) { | |
2352 | case DMA_TO_DEVICE: | |
2353 | c->Request.Type.Direction = XFER_WRITE; | |
2354 | break; | |
2355 | case DMA_FROM_DEVICE: | |
2356 | c->Request.Type.Direction = XFER_READ; | |
2357 | break; | |
2358 | case DMA_NONE: | |
2359 | c->Request.Type.Direction = XFER_NONE; | |
2360 | break; | |
2361 | case DMA_BIDIRECTIONAL: | |
2362 | /* This can happen if a buggy application does a scsi passthru | |
2363 | * and sets both inlen and outlen to non-zero. ( see | |
2364 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
2365 | */ | |
2366 | ||
2367 | c->Request.Type.Direction = XFER_RSVD; | |
2368 | /* This is technically wrong, and hpsa controllers should | |
2369 | * reject it with CMD_INVALID, which is the most correct | |
2370 | * response, but non-fibre backends appear to let it | |
2371 | * slide by, and give the same results as if this field | |
2372 | * were set correctly. Either way is acceptable for | |
2373 | * our purposes here. | |
2374 | */ | |
2375 | ||
2376 | break; | |
2377 | ||
2378 | default: | |
2379 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
2380 | cmd->sc_data_direction); | |
2381 | BUG(); | |
2382 | break; | |
2383 | } | |
2384 | ||
33a2ffce | 2385 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
edd16368 SC |
2386 | cmd_free(h, c); |
2387 | return SCSI_MLQUEUE_HOST_BUSY; | |
2388 | } | |
2389 | enqueue_cmd_and_start_io(h, c); | |
2390 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
2391 | return 0; | |
2392 | } | |
2393 | ||
f281233d JG |
2394 | static DEF_SCSI_QCMD(hpsa_scsi_queue_command) |
2395 | ||
a08a8471 SC |
2396 | static void hpsa_scan_start(struct Scsi_Host *sh) |
2397 | { | |
2398 | struct ctlr_info *h = shost_to_hba(sh); | |
2399 | unsigned long flags; | |
2400 | ||
2401 | /* wait until any scan already in progress is finished. */ | |
2402 | while (1) { | |
2403 | spin_lock_irqsave(&h->scan_lock, flags); | |
2404 | if (h->scan_finished) | |
2405 | break; | |
2406 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
2407 | wait_event(h->scan_wait_queue, h->scan_finished); | |
2408 | /* Note: We don't need to worry about a race between this | |
2409 | * thread and driver unload because the midlayer will | |
2410 | * have incremented the reference count, so unload won't | |
2411 | * happen if we're in here. | |
2412 | */ | |
2413 | } | |
2414 | h->scan_finished = 0; /* mark scan as in progress */ | |
2415 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
2416 | ||
2417 | hpsa_update_scsi_devices(h, h->scsi_host->host_no); | |
2418 | ||
2419 | spin_lock_irqsave(&h->scan_lock, flags); | |
2420 | h->scan_finished = 1; /* mark scan as finished. */ | |
2421 | wake_up_all(&h->scan_wait_queue); | |
2422 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
2423 | } | |
2424 | ||
2425 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
2426 | unsigned long elapsed_time) | |
2427 | { | |
2428 | struct ctlr_info *h = shost_to_hba(sh); | |
2429 | unsigned long flags; | |
2430 | int finished; | |
2431 | ||
2432 | spin_lock_irqsave(&h->scan_lock, flags); | |
2433 | finished = h->scan_finished; | |
2434 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
2435 | return finished; | |
2436 | } | |
2437 | ||
667e23d4 SC |
2438 | static int hpsa_change_queue_depth(struct scsi_device *sdev, |
2439 | int qdepth, int reason) | |
2440 | { | |
2441 | struct ctlr_info *h = sdev_to_hba(sdev); | |
2442 | ||
2443 | if (reason != SCSI_QDEPTH_DEFAULT) | |
2444 | return -ENOTSUPP; | |
2445 | ||
2446 | if (qdepth < 1) | |
2447 | qdepth = 1; | |
2448 | else | |
2449 | if (qdepth > h->nr_cmds) | |
2450 | qdepth = h->nr_cmds; | |
2451 | scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth); | |
2452 | return sdev->queue_depth; | |
2453 | } | |
2454 | ||
edd16368 SC |
2455 | static void hpsa_unregister_scsi(struct ctlr_info *h) |
2456 | { | |
2457 | /* we are being forcibly unloaded, and may not refuse. */ | |
2458 | scsi_remove_host(h->scsi_host); | |
2459 | scsi_host_put(h->scsi_host); | |
2460 | h->scsi_host = NULL; | |
2461 | } | |
2462 | ||
2463 | static int hpsa_register_scsi(struct ctlr_info *h) | |
2464 | { | |
b705690d SC |
2465 | struct Scsi_Host *sh; |
2466 | int error; | |
edd16368 | 2467 | |
b705690d SC |
2468 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
2469 | if (sh == NULL) | |
2470 | goto fail; | |
2471 | ||
2472 | sh->io_port = 0; | |
2473 | sh->n_io_port = 0; | |
2474 | sh->this_id = -1; | |
2475 | sh->max_channel = 3; | |
2476 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
2477 | sh->max_lun = HPSA_MAX_LUN; | |
2478 | sh->max_id = HPSA_MAX_LUN; | |
2479 | sh->can_queue = h->nr_cmds; | |
2480 | sh->cmd_per_lun = h->nr_cmds; | |
2481 | sh->sg_tablesize = h->maxsgentries; | |
2482 | h->scsi_host = sh; | |
2483 | sh->hostdata[0] = (unsigned long) h; | |
2484 | sh->irq = h->intr[h->intr_mode]; | |
2485 | sh->unique_id = sh->irq; | |
2486 | error = scsi_add_host(sh, &h->pdev->dev); | |
2487 | if (error) | |
2488 | goto fail_host_put; | |
2489 | scsi_scan_host(sh); | |
2490 | return 0; | |
2491 | ||
2492 | fail_host_put: | |
2493 | dev_err(&h->pdev->dev, "%s: scsi_add_host" | |
2494 | " failed for controller %d\n", __func__, h->ctlr); | |
2495 | scsi_host_put(sh); | |
2496 | return error; | |
2497 | fail: | |
2498 | dev_err(&h->pdev->dev, "%s: scsi_host_alloc" | |
2499 | " failed for controller %d\n", __func__, h->ctlr); | |
2500 | return -ENOMEM; | |
edd16368 SC |
2501 | } |
2502 | ||
2503 | static int wait_for_device_to_become_ready(struct ctlr_info *h, | |
2504 | unsigned char lunaddr[]) | |
2505 | { | |
2506 | int rc = 0; | |
2507 | int count = 0; | |
2508 | int waittime = 1; /* seconds */ | |
2509 | struct CommandList *c; | |
2510 | ||
2511 | c = cmd_special_alloc(h); | |
2512 | if (!c) { | |
2513 | dev_warn(&h->pdev->dev, "out of memory in " | |
2514 | "wait_for_device_to_become_ready.\n"); | |
2515 | return IO_ERROR; | |
2516 | } | |
2517 | ||
2518 | /* Send test unit ready until device ready, or give up. */ | |
2519 | while (count < HPSA_TUR_RETRY_LIMIT) { | |
2520 | ||
2521 | /* Wait for a bit. do this first, because if we send | |
2522 | * the TUR right away, the reset will just abort it. | |
2523 | */ | |
2524 | msleep(1000 * waittime); | |
2525 | count++; | |
2526 | ||
2527 | /* Increase wait time with each try, up to a point. */ | |
2528 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
2529 | waittime = waittime * 2; | |
2530 | ||
a2dac136 SC |
2531 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ |
2532 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
2533 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
edd16368 SC |
2534 | hpsa_scsi_do_simple_cmd_core(h, c); |
2535 | /* no unmap needed here because no data xfer. */ | |
2536 | ||
2537 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
2538 | break; | |
2539 | ||
2540 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
2541 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
2542 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
2543 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
2544 | break; | |
2545 | ||
2546 | dev_warn(&h->pdev->dev, "waiting %d secs " | |
2547 | "for device to become ready.\n", waittime); | |
2548 | rc = 1; /* device not ready. */ | |
2549 | } | |
2550 | ||
2551 | if (rc) | |
2552 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
2553 | else | |
2554 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
2555 | ||
2556 | cmd_special_free(h, c); | |
2557 | return rc; | |
2558 | } | |
2559 | ||
2560 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
2561 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
2562 | */ | |
2563 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
2564 | { | |
2565 | int rc; | |
2566 | struct ctlr_info *h; | |
2567 | struct hpsa_scsi_dev_t *dev; | |
2568 | ||
2569 | /* find the controller to which the command to be aborted was sent */ | |
2570 | h = sdev_to_hba(scsicmd->device); | |
2571 | if (h == NULL) /* paranoia */ | |
2572 | return FAILED; | |
edd16368 SC |
2573 | dev = scsicmd->device->hostdata; |
2574 | if (!dev) { | |
2575 | dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: " | |
2576 | "device lookup failed.\n"); | |
2577 | return FAILED; | |
2578 | } | |
d416b0c7 SC |
2579 | dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n", |
2580 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
edd16368 SC |
2581 | /* send a reset to the SCSI LUN which the command was sent to */ |
2582 | rc = hpsa_send_reset(h, dev->scsi3addr); | |
2583 | if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0) | |
2584 | return SUCCESS; | |
2585 | ||
2586 | dev_warn(&h->pdev->dev, "resetting device failed.\n"); | |
2587 | return FAILED; | |
2588 | } | |
2589 | ||
6cba3f19 SC |
2590 | static void swizzle_abort_tag(u8 *tag) |
2591 | { | |
2592 | u8 original_tag[8]; | |
2593 | ||
2594 | memcpy(original_tag, tag, 8); | |
2595 | tag[0] = original_tag[3]; | |
2596 | tag[1] = original_tag[2]; | |
2597 | tag[2] = original_tag[1]; | |
2598 | tag[3] = original_tag[0]; | |
2599 | tag[4] = original_tag[7]; | |
2600 | tag[5] = original_tag[6]; | |
2601 | tag[6] = original_tag[5]; | |
2602 | tag[7] = original_tag[4]; | |
2603 | } | |
2604 | ||
17eb87d2 ST |
2605 | static void hpsa_get_tag(struct ctlr_info *h, |
2606 | struct CommandList *c, u32 *taglower, u32 *tagupper) | |
2607 | { | |
2608 | if (c->cmd_type == CMD_IOACCEL1) { | |
2609 | struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *) | |
2610 | &h->ioaccel_cmd_pool[c->cmdindex]; | |
2611 | *tagupper = cm1->Tag.upper; | |
2612 | *taglower = cm1->Tag.lower; | |
2613 | } else { | |
2614 | *tagupper = c->Header.Tag.upper; | |
2615 | *taglower = c->Header.Tag.lower; | |
2616 | } | |
2617 | } | |
2618 | ||
75167d2c | 2619 | static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr, |
6cba3f19 | 2620 | struct CommandList *abort, int swizzle) |
75167d2c SC |
2621 | { |
2622 | int rc = IO_OK; | |
2623 | struct CommandList *c; | |
2624 | struct ErrorInfo *ei; | |
17eb87d2 | 2625 | u32 tagupper, taglower; |
75167d2c SC |
2626 | |
2627 | c = cmd_special_alloc(h); | |
2628 | if (c == NULL) { /* trouble... */ | |
2629 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
2630 | return -ENOMEM; | |
2631 | } | |
2632 | ||
a2dac136 SC |
2633 | /* fill_cmd can't fail here, no buffer to map */ |
2634 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort, | |
2635 | 0, 0, scsi3addr, TYPE_MSG); | |
6cba3f19 SC |
2636 | if (swizzle) |
2637 | swizzle_abort_tag(&c->Request.CDB[4]); | |
75167d2c | 2638 | hpsa_scsi_do_simple_cmd_core(h, c); |
17eb87d2 | 2639 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
75167d2c | 2640 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n", |
17eb87d2 | 2641 | __func__, tagupper, taglower); |
75167d2c SC |
2642 | /* no unmap needed here because no data xfer. */ |
2643 | ||
2644 | ei = c->err_info; | |
2645 | switch (ei->CommandStatus) { | |
2646 | case CMD_SUCCESS: | |
2647 | break; | |
2648 | case CMD_UNABORTABLE: /* Very common, don't make noise. */ | |
2649 | rc = -1; | |
2650 | break; | |
2651 | default: | |
2652 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n", | |
17eb87d2 | 2653 | __func__, tagupper, taglower); |
75167d2c SC |
2654 | hpsa_scsi_interpret_error(c); |
2655 | rc = -1; | |
2656 | break; | |
2657 | } | |
2658 | cmd_special_free(h, c); | |
2659 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__, | |
2660 | abort->Header.Tag.upper, abort->Header.Tag.lower); | |
2661 | return rc; | |
2662 | } | |
2663 | ||
2664 | /* | |
2665 | * hpsa_find_cmd_in_queue | |
2666 | * | |
2667 | * Used to determine whether a command (find) is still present | |
2668 | * in queue_head. Optionally excludes the last element of queue_head. | |
2669 | * | |
2670 | * This is used to avoid unnecessary aborts. Commands in h->reqQ have | |
2671 | * not yet been submitted, and so can be aborted by the driver without | |
2672 | * sending an abort to the hardware. | |
2673 | * | |
2674 | * Returns pointer to command if found in queue, NULL otherwise. | |
2675 | */ | |
2676 | static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h, | |
2677 | struct scsi_cmnd *find, struct list_head *queue_head) | |
2678 | { | |
2679 | unsigned long flags; | |
2680 | struct CommandList *c = NULL; /* ptr into cmpQ */ | |
2681 | ||
2682 | if (!find) | |
2683 | return 0; | |
2684 | spin_lock_irqsave(&h->lock, flags); | |
2685 | list_for_each_entry(c, queue_head, list) { | |
2686 | if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */ | |
2687 | continue; | |
2688 | if (c->scsi_cmd == find) { | |
2689 | spin_unlock_irqrestore(&h->lock, flags); | |
2690 | return c; | |
2691 | } | |
2692 | } | |
2693 | spin_unlock_irqrestore(&h->lock, flags); | |
2694 | return NULL; | |
2695 | } | |
2696 | ||
6cba3f19 SC |
2697 | static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h, |
2698 | u8 *tag, struct list_head *queue_head) | |
2699 | { | |
2700 | unsigned long flags; | |
2701 | struct CommandList *c; | |
2702 | ||
2703 | spin_lock_irqsave(&h->lock, flags); | |
2704 | list_for_each_entry(c, queue_head, list) { | |
2705 | if (memcmp(&c->Header.Tag, tag, 8) != 0) | |
2706 | continue; | |
2707 | spin_unlock_irqrestore(&h->lock, flags); | |
2708 | return c; | |
2709 | } | |
2710 | spin_unlock_irqrestore(&h->lock, flags); | |
2711 | return NULL; | |
2712 | } | |
2713 | ||
2714 | /* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to | |
2715 | * tell which kind we're dealing with, so we send the abort both ways. There | |
2716 | * shouldn't be any collisions between swizzled and unswizzled tags due to the | |
2717 | * way we construct our tags but we check anyway in case the assumptions which | |
2718 | * make this true someday become false. | |
2719 | */ | |
2720 | static int hpsa_send_abort_both_ways(struct ctlr_info *h, | |
2721 | unsigned char *scsi3addr, struct CommandList *abort) | |
2722 | { | |
2723 | u8 swizzled_tag[8]; | |
2724 | struct CommandList *c; | |
2725 | int rc = 0, rc2 = 0; | |
2726 | ||
2727 | /* we do not expect to find the swizzled tag in our queue, but | |
2728 | * check anyway just to be sure the assumptions which make this | |
2729 | * the case haven't become wrong. | |
2730 | */ | |
2731 | memcpy(swizzled_tag, &abort->Request.CDB[4], 8); | |
2732 | swizzle_abort_tag(swizzled_tag); | |
2733 | c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ); | |
2734 | if (c != NULL) { | |
2735 | dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n"); | |
2736 | return hpsa_send_abort(h, scsi3addr, abort, 0); | |
2737 | } | |
2738 | rc = hpsa_send_abort(h, scsi3addr, abort, 0); | |
2739 | ||
2740 | /* if the command is still in our queue, we can't conclude that it was | |
2741 | * aborted (it might have just completed normally) but in any case | |
2742 | * we don't need to try to abort it another way. | |
2743 | */ | |
2744 | c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ); | |
2745 | if (c) | |
2746 | rc2 = hpsa_send_abort(h, scsi3addr, abort, 1); | |
2747 | return rc && rc2; | |
2748 | } | |
2749 | ||
75167d2c SC |
2750 | /* Send an abort for the specified command. |
2751 | * If the device and controller support it, | |
2752 | * send a task abort request. | |
2753 | */ | |
2754 | static int hpsa_eh_abort_handler(struct scsi_cmnd *sc) | |
2755 | { | |
2756 | ||
2757 | int i, rc; | |
2758 | struct ctlr_info *h; | |
2759 | struct hpsa_scsi_dev_t *dev; | |
2760 | struct CommandList *abort; /* pointer to command to be aborted */ | |
2761 | struct CommandList *found; | |
2762 | struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */ | |
2763 | char msg[256]; /* For debug messaging. */ | |
2764 | int ml = 0; | |
17eb87d2 | 2765 | u32 tagupper, taglower; |
75167d2c SC |
2766 | |
2767 | /* Find the controller of the command to be aborted */ | |
2768 | h = sdev_to_hba(sc->device); | |
2769 | if (WARN(h == NULL, | |
2770 | "ABORT REQUEST FAILED, Controller lookup failed.\n")) | |
2771 | return FAILED; | |
2772 | ||
2773 | /* Check that controller supports some kind of task abort */ | |
2774 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) && | |
2775 | !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
2776 | return FAILED; | |
2777 | ||
2778 | memset(msg, 0, sizeof(msg)); | |
2779 | ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ", | |
2780 | h->scsi_host->host_no, sc->device->channel, | |
2781 | sc->device->id, sc->device->lun); | |
2782 | ||
2783 | /* Find the device of the command to be aborted */ | |
2784 | dev = sc->device->hostdata; | |
2785 | if (!dev) { | |
2786 | dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n", | |
2787 | msg); | |
2788 | return FAILED; | |
2789 | } | |
2790 | ||
2791 | /* Get SCSI command to be aborted */ | |
2792 | abort = (struct CommandList *) sc->host_scribble; | |
2793 | if (abort == NULL) { | |
2794 | dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n", | |
2795 | msg); | |
2796 | return FAILED; | |
2797 | } | |
17eb87d2 ST |
2798 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
2799 | ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower); | |
75167d2c SC |
2800 | as = (struct scsi_cmnd *) abort->scsi_cmd; |
2801 | if (as != NULL) | |
2802 | ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ", | |
2803 | as->cmnd[0], as->serial_number); | |
2804 | dev_dbg(&h->pdev->dev, "%s\n", msg); | |
2805 | dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n", | |
2806 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
2807 | ||
2808 | /* Search reqQ to See if command is queued but not submitted, | |
2809 | * if so, complete the command with aborted status and remove | |
2810 | * it from the reqQ. | |
2811 | */ | |
2812 | found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ); | |
2813 | if (found) { | |
2814 | found->err_info->CommandStatus = CMD_ABORTED; | |
2815 | finish_cmd(found); | |
2816 | dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n", | |
2817 | msg); | |
2818 | return SUCCESS; | |
2819 | } | |
2820 | ||
2821 | /* not in reqQ, if also not in cmpQ, must have already completed */ | |
2822 | found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ); | |
2823 | if (!found) { | |
d6ebd0f7 | 2824 | dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n", |
75167d2c SC |
2825 | msg); |
2826 | return SUCCESS; | |
2827 | } | |
2828 | ||
2829 | /* | |
2830 | * Command is in flight, or possibly already completed | |
2831 | * by the firmware (but not to the scsi mid layer) but we can't | |
2832 | * distinguish which. Send the abort down. | |
2833 | */ | |
6cba3f19 | 2834 | rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort); |
75167d2c SC |
2835 | if (rc != 0) { |
2836 | dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg); | |
2837 | dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n", | |
2838 | h->scsi_host->host_no, | |
2839 | dev->bus, dev->target, dev->lun); | |
2840 | return FAILED; | |
2841 | } | |
2842 | dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg); | |
2843 | ||
2844 | /* If the abort(s) above completed and actually aborted the | |
2845 | * command, then the command to be aborted should already be | |
2846 | * completed. If not, wait around a bit more to see if they | |
2847 | * manage to complete normally. | |
2848 | */ | |
2849 | #define ABORT_COMPLETE_WAIT_SECS 30 | |
2850 | for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) { | |
2851 | found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ); | |
2852 | if (!found) | |
2853 | return SUCCESS; | |
2854 | msleep(100); | |
2855 | } | |
2856 | dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n", | |
2857 | msg, ABORT_COMPLETE_WAIT_SECS); | |
2858 | return FAILED; | |
2859 | } | |
2860 | ||
2861 | ||
edd16368 SC |
2862 | /* |
2863 | * For operations that cannot sleep, a command block is allocated at init, | |
2864 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
2865 | * which ones are free or in use. Lock must be held when calling this. | |
2866 | * cmd_free() is the complement. | |
2867 | */ | |
2868 | static struct CommandList *cmd_alloc(struct ctlr_info *h) | |
2869 | { | |
2870 | struct CommandList *c; | |
2871 | int i; | |
2872 | union u64bit temp64; | |
2873 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
e16a33ad | 2874 | unsigned long flags; |
edd16368 | 2875 | |
e16a33ad | 2876 | spin_lock_irqsave(&h->lock, flags); |
edd16368 SC |
2877 | do { |
2878 | i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds); | |
e16a33ad MG |
2879 | if (i == h->nr_cmds) { |
2880 | spin_unlock_irqrestore(&h->lock, flags); | |
edd16368 | 2881 | return NULL; |
e16a33ad | 2882 | } |
edd16368 SC |
2883 | } while (test_and_set_bit |
2884 | (i & (BITS_PER_LONG - 1), | |
2885 | h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0); | |
e16a33ad MG |
2886 | spin_unlock_irqrestore(&h->lock, flags); |
2887 | ||
edd16368 SC |
2888 | c = h->cmd_pool + i; |
2889 | memset(c, 0, sizeof(*c)); | |
2890 | cmd_dma_handle = h->cmd_pool_dhandle | |
2891 | + i * sizeof(*c); | |
2892 | c->err_info = h->errinfo_pool + i; | |
2893 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
2894 | err_dma_handle = h->errinfo_pool_dhandle | |
2895 | + i * sizeof(*c->err_info); | |
edd16368 SC |
2896 | |
2897 | c->cmdindex = i; | |
2898 | ||
9e0fc764 | 2899 | INIT_LIST_HEAD(&c->list); |
01a02ffc SC |
2900 | c->busaddr = (u32) cmd_dma_handle; |
2901 | temp64.val = (u64) err_dma_handle; | |
edd16368 SC |
2902 | c->ErrDesc.Addr.lower = temp64.val32.lower; |
2903 | c->ErrDesc.Addr.upper = temp64.val32.upper; | |
2904 | c->ErrDesc.Len = sizeof(*c->err_info); | |
2905 | ||
2906 | c->h = h; | |
2907 | return c; | |
2908 | } | |
2909 | ||
2910 | /* For operations that can wait for kmalloc to possibly sleep, | |
2911 | * this routine can be called. Lock need not be held to call | |
2912 | * cmd_special_alloc. cmd_special_free() is the complement. | |
2913 | */ | |
2914 | static struct CommandList *cmd_special_alloc(struct ctlr_info *h) | |
2915 | { | |
2916 | struct CommandList *c; | |
2917 | union u64bit temp64; | |
2918 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
2919 | ||
2920 | c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle); | |
2921 | if (c == NULL) | |
2922 | return NULL; | |
2923 | memset(c, 0, sizeof(*c)); | |
2924 | ||
e1f7de0c | 2925 | c->cmd_type = CMD_SCSI; |
edd16368 SC |
2926 | c->cmdindex = -1; |
2927 | ||
2928 | c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info), | |
2929 | &err_dma_handle); | |
2930 | ||
2931 | if (c->err_info == NULL) { | |
2932 | pci_free_consistent(h->pdev, | |
2933 | sizeof(*c), c, cmd_dma_handle); | |
2934 | return NULL; | |
2935 | } | |
2936 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
2937 | ||
9e0fc764 | 2938 | INIT_LIST_HEAD(&c->list); |
01a02ffc SC |
2939 | c->busaddr = (u32) cmd_dma_handle; |
2940 | temp64.val = (u64) err_dma_handle; | |
edd16368 SC |
2941 | c->ErrDesc.Addr.lower = temp64.val32.lower; |
2942 | c->ErrDesc.Addr.upper = temp64.val32.upper; | |
2943 | c->ErrDesc.Len = sizeof(*c->err_info); | |
2944 | ||
2945 | c->h = h; | |
2946 | return c; | |
2947 | } | |
2948 | ||
2949 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) | |
2950 | { | |
2951 | int i; | |
e16a33ad | 2952 | unsigned long flags; |
edd16368 SC |
2953 | |
2954 | i = c - h->cmd_pool; | |
e16a33ad | 2955 | spin_lock_irqsave(&h->lock, flags); |
edd16368 SC |
2956 | clear_bit(i & (BITS_PER_LONG - 1), |
2957 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
e16a33ad | 2958 | spin_unlock_irqrestore(&h->lock, flags); |
edd16368 SC |
2959 | } |
2960 | ||
2961 | static void cmd_special_free(struct ctlr_info *h, struct CommandList *c) | |
2962 | { | |
2963 | union u64bit temp64; | |
2964 | ||
2965 | temp64.val32.lower = c->ErrDesc.Addr.lower; | |
2966 | temp64.val32.upper = c->ErrDesc.Addr.upper; | |
2967 | pci_free_consistent(h->pdev, sizeof(*c->err_info), | |
2968 | c->err_info, (dma_addr_t) temp64.val); | |
2969 | pci_free_consistent(h->pdev, sizeof(*c), | |
d896f3f3 | 2970 | c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK)); |
edd16368 SC |
2971 | } |
2972 | ||
2973 | #ifdef CONFIG_COMPAT | |
2974 | ||
edd16368 SC |
2975 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg) |
2976 | { | |
2977 | IOCTL32_Command_struct __user *arg32 = | |
2978 | (IOCTL32_Command_struct __user *) arg; | |
2979 | IOCTL_Command_struct arg64; | |
2980 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
2981 | int err; | |
2982 | u32 cp; | |
2983 | ||
938abd84 | 2984 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
2985 | err = 0; |
2986 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
2987 | sizeof(arg64.LUN_info)); | |
2988 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
2989 | sizeof(arg64.Request)); | |
2990 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
2991 | sizeof(arg64.error_info)); | |
2992 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
2993 | err |= get_user(cp, &arg32->buf); | |
2994 | arg64.buf = compat_ptr(cp); | |
2995 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
2996 | ||
2997 | if (err) | |
2998 | return -EFAULT; | |
2999 | ||
e39eeaed | 3000 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p); |
edd16368 SC |
3001 | if (err) |
3002 | return err; | |
3003 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
3004 | sizeof(arg32->error_info)); | |
3005 | if (err) | |
3006 | return -EFAULT; | |
3007 | return err; | |
3008 | } | |
3009 | ||
3010 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
3011 | int cmd, void *arg) | |
3012 | { | |
3013 | BIG_IOCTL32_Command_struct __user *arg32 = | |
3014 | (BIG_IOCTL32_Command_struct __user *) arg; | |
3015 | BIG_IOCTL_Command_struct arg64; | |
3016 | BIG_IOCTL_Command_struct __user *p = | |
3017 | compat_alloc_user_space(sizeof(arg64)); | |
3018 | int err; | |
3019 | u32 cp; | |
3020 | ||
938abd84 | 3021 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
3022 | err = 0; |
3023 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
3024 | sizeof(arg64.LUN_info)); | |
3025 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
3026 | sizeof(arg64.Request)); | |
3027 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
3028 | sizeof(arg64.error_info)); | |
3029 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
3030 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
3031 | err |= get_user(cp, &arg32->buf); | |
3032 | arg64.buf = compat_ptr(cp); | |
3033 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
3034 | ||
3035 | if (err) | |
3036 | return -EFAULT; | |
3037 | ||
e39eeaed | 3038 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p); |
edd16368 SC |
3039 | if (err) |
3040 | return err; | |
3041 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
3042 | sizeof(arg32->error_info)); | |
3043 | if (err) | |
3044 | return -EFAULT; | |
3045 | return err; | |
3046 | } | |
71fe75a7 SC |
3047 | |
3048 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg) | |
3049 | { | |
3050 | switch (cmd) { | |
3051 | case CCISS_GETPCIINFO: | |
3052 | case CCISS_GETINTINFO: | |
3053 | case CCISS_SETINTINFO: | |
3054 | case CCISS_GETNODENAME: | |
3055 | case CCISS_SETNODENAME: | |
3056 | case CCISS_GETHEARTBEAT: | |
3057 | case CCISS_GETBUSTYPES: | |
3058 | case CCISS_GETFIRMVER: | |
3059 | case CCISS_GETDRIVVER: | |
3060 | case CCISS_REVALIDVOLS: | |
3061 | case CCISS_DEREGDISK: | |
3062 | case CCISS_REGNEWDISK: | |
3063 | case CCISS_REGNEWD: | |
3064 | case CCISS_RESCANDISK: | |
3065 | case CCISS_GETLUNINFO: | |
3066 | return hpsa_ioctl(dev, cmd, arg); | |
3067 | ||
3068 | case CCISS_PASSTHRU32: | |
3069 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
3070 | case CCISS_BIG_PASSTHRU32: | |
3071 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
3072 | ||
3073 | default: | |
3074 | return -ENOIOCTLCMD; | |
3075 | } | |
3076 | } | |
edd16368 SC |
3077 | #endif |
3078 | ||
3079 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
3080 | { | |
3081 | struct hpsa_pci_info pciinfo; | |
3082 | ||
3083 | if (!argp) | |
3084 | return -EINVAL; | |
3085 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
3086 | pciinfo.bus = h->pdev->bus->number; | |
3087 | pciinfo.dev_fn = h->pdev->devfn; | |
3088 | pciinfo.board_id = h->board_id; | |
3089 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
3090 | return -EFAULT; | |
3091 | return 0; | |
3092 | } | |
3093 | ||
3094 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
3095 | { | |
3096 | DriverVer_type DriverVer; | |
3097 | unsigned char vmaj, vmin, vsubmin; | |
3098 | int rc; | |
3099 | ||
3100 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
3101 | &vmaj, &vmin, &vsubmin); | |
3102 | if (rc != 3) { | |
3103 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
3104 | "unrecognized.", HPSA_DRIVER_VERSION); | |
3105 | vmaj = 0; | |
3106 | vmin = 0; | |
3107 | vsubmin = 0; | |
3108 | } | |
3109 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
3110 | if (!argp) | |
3111 | return -EINVAL; | |
3112 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
3113 | return -EFAULT; | |
3114 | return 0; | |
3115 | } | |
3116 | ||
3117 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
3118 | { | |
3119 | IOCTL_Command_struct iocommand; | |
3120 | struct CommandList *c; | |
3121 | char *buff = NULL; | |
3122 | union u64bit temp64; | |
c1f63c8f | 3123 | int rc = 0; |
edd16368 SC |
3124 | |
3125 | if (!argp) | |
3126 | return -EINVAL; | |
3127 | if (!capable(CAP_SYS_RAWIO)) | |
3128 | return -EPERM; | |
3129 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
3130 | return -EFAULT; | |
3131 | if ((iocommand.buf_size < 1) && | |
3132 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
3133 | return -EINVAL; | |
3134 | } | |
3135 | if (iocommand.buf_size > 0) { | |
3136 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
3137 | if (buff == NULL) | |
3138 | return -EFAULT; | |
b03a7771 SC |
3139 | if (iocommand.Request.Type.Direction == XFER_WRITE) { |
3140 | /* Copy the data into the buffer we created */ | |
3141 | if (copy_from_user(buff, iocommand.buf, | |
3142 | iocommand.buf_size)) { | |
c1f63c8f SC |
3143 | rc = -EFAULT; |
3144 | goto out_kfree; | |
b03a7771 SC |
3145 | } |
3146 | } else { | |
3147 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 3148 | } |
b03a7771 | 3149 | } |
edd16368 SC |
3150 | c = cmd_special_alloc(h); |
3151 | if (c == NULL) { | |
c1f63c8f SC |
3152 | rc = -ENOMEM; |
3153 | goto out_kfree; | |
edd16368 SC |
3154 | } |
3155 | /* Fill in the command type */ | |
3156 | c->cmd_type = CMD_IOCTL_PEND; | |
3157 | /* Fill in Command Header */ | |
3158 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
3159 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
3160 | c->Header.SGList = 1; | |
3161 | c->Header.SGTotal = 1; | |
3162 | } else { /* no buffers to fill */ | |
3163 | c->Header.SGList = 0; | |
3164 | c->Header.SGTotal = 0; | |
3165 | } | |
3166 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
3167 | /* use the kernel address the cmd block for tag */ | |
3168 | c->Header.Tag.lower = c->busaddr; | |
3169 | ||
3170 | /* Fill in Request block */ | |
3171 | memcpy(&c->Request, &iocommand.Request, | |
3172 | sizeof(c->Request)); | |
3173 | ||
3174 | /* Fill in the scatter gather information */ | |
3175 | if (iocommand.buf_size > 0) { | |
3176 | temp64.val = pci_map_single(h->pdev, buff, | |
3177 | iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); | |
bcc48ffa SC |
3178 | if (dma_mapping_error(&h->pdev->dev, temp64.val)) { |
3179 | c->SG[0].Addr.lower = 0; | |
3180 | c->SG[0].Addr.upper = 0; | |
3181 | c->SG[0].Len = 0; | |
3182 | rc = -ENOMEM; | |
3183 | goto out; | |
3184 | } | |
edd16368 SC |
3185 | c->SG[0].Addr.lower = temp64.val32.lower; |
3186 | c->SG[0].Addr.upper = temp64.val32.upper; | |
3187 | c->SG[0].Len = iocommand.buf_size; | |
e1d9cbfa | 3188 | c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/ |
edd16368 | 3189 | } |
a0c12413 | 3190 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
c2dd32e0 SC |
3191 | if (iocommand.buf_size > 0) |
3192 | hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
3193 | check_ioctl_unit_attention(h, c); |
3194 | ||
3195 | /* Copy the error information out */ | |
3196 | memcpy(&iocommand.error_info, c->err_info, | |
3197 | sizeof(iocommand.error_info)); | |
3198 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
3199 | rc = -EFAULT; |
3200 | goto out; | |
edd16368 | 3201 | } |
b03a7771 SC |
3202 | if (iocommand.Request.Type.Direction == XFER_READ && |
3203 | iocommand.buf_size > 0) { | |
edd16368 SC |
3204 | /* Copy the data out of the buffer we created */ |
3205 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
3206 | rc = -EFAULT; |
3207 | goto out; | |
edd16368 SC |
3208 | } |
3209 | } | |
c1f63c8f | 3210 | out: |
edd16368 | 3211 | cmd_special_free(h, c); |
c1f63c8f SC |
3212 | out_kfree: |
3213 | kfree(buff); | |
3214 | return rc; | |
edd16368 SC |
3215 | } |
3216 | ||
3217 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
3218 | { | |
3219 | BIG_IOCTL_Command_struct *ioc; | |
3220 | struct CommandList *c; | |
3221 | unsigned char **buff = NULL; | |
3222 | int *buff_size = NULL; | |
3223 | union u64bit temp64; | |
3224 | BYTE sg_used = 0; | |
3225 | int status = 0; | |
3226 | int i; | |
01a02ffc SC |
3227 | u32 left; |
3228 | u32 sz; | |
edd16368 SC |
3229 | BYTE __user *data_ptr; |
3230 | ||
3231 | if (!argp) | |
3232 | return -EINVAL; | |
3233 | if (!capable(CAP_SYS_RAWIO)) | |
3234 | return -EPERM; | |
3235 | ioc = (BIG_IOCTL_Command_struct *) | |
3236 | kmalloc(sizeof(*ioc), GFP_KERNEL); | |
3237 | if (!ioc) { | |
3238 | status = -ENOMEM; | |
3239 | goto cleanup1; | |
3240 | } | |
3241 | if (copy_from_user(ioc, argp, sizeof(*ioc))) { | |
3242 | status = -EFAULT; | |
3243 | goto cleanup1; | |
3244 | } | |
3245 | if ((ioc->buf_size < 1) && | |
3246 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
3247 | status = -EINVAL; | |
3248 | goto cleanup1; | |
3249 | } | |
3250 | /* Check kmalloc limits using all SGs */ | |
3251 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
3252 | status = -EINVAL; | |
3253 | goto cleanup1; | |
3254 | } | |
d66ae08b | 3255 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
3256 | status = -EINVAL; |
3257 | goto cleanup1; | |
3258 | } | |
d66ae08b | 3259 | buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); |
edd16368 SC |
3260 | if (!buff) { |
3261 | status = -ENOMEM; | |
3262 | goto cleanup1; | |
3263 | } | |
d66ae08b | 3264 | buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); |
edd16368 SC |
3265 | if (!buff_size) { |
3266 | status = -ENOMEM; | |
3267 | goto cleanup1; | |
3268 | } | |
3269 | left = ioc->buf_size; | |
3270 | data_ptr = ioc->buf; | |
3271 | while (left) { | |
3272 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
3273 | buff_size[sg_used] = sz; | |
3274 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
3275 | if (buff[sg_used] == NULL) { | |
3276 | status = -ENOMEM; | |
3277 | goto cleanup1; | |
3278 | } | |
3279 | if (ioc->Request.Type.Direction == XFER_WRITE) { | |
3280 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { | |
3281 | status = -ENOMEM; | |
3282 | goto cleanup1; | |
3283 | } | |
3284 | } else | |
3285 | memset(buff[sg_used], 0, sz); | |
3286 | left -= sz; | |
3287 | data_ptr += sz; | |
3288 | sg_used++; | |
3289 | } | |
3290 | c = cmd_special_alloc(h); | |
3291 | if (c == NULL) { | |
3292 | status = -ENOMEM; | |
3293 | goto cleanup1; | |
3294 | } | |
3295 | c->cmd_type = CMD_IOCTL_PEND; | |
3296 | c->Header.ReplyQueue = 0; | |
b03a7771 | 3297 | c->Header.SGList = c->Header.SGTotal = sg_used; |
edd16368 SC |
3298 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
3299 | c->Header.Tag.lower = c->busaddr; | |
3300 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); | |
3301 | if (ioc->buf_size > 0) { | |
3302 | int i; | |
3303 | for (i = 0; i < sg_used; i++) { | |
3304 | temp64.val = pci_map_single(h->pdev, buff[i], | |
3305 | buff_size[i], PCI_DMA_BIDIRECTIONAL); | |
bcc48ffa SC |
3306 | if (dma_mapping_error(&h->pdev->dev, temp64.val)) { |
3307 | c->SG[i].Addr.lower = 0; | |
3308 | c->SG[i].Addr.upper = 0; | |
3309 | c->SG[i].Len = 0; | |
3310 | hpsa_pci_unmap(h->pdev, c, i, | |
3311 | PCI_DMA_BIDIRECTIONAL); | |
3312 | status = -ENOMEM; | |
e2d4a1f6 | 3313 | goto cleanup0; |
bcc48ffa | 3314 | } |
edd16368 SC |
3315 | c->SG[i].Addr.lower = temp64.val32.lower; |
3316 | c->SG[i].Addr.upper = temp64.val32.upper; | |
3317 | c->SG[i].Len = buff_size[i]; | |
e1d9cbfa | 3318 | c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST; |
edd16368 SC |
3319 | } |
3320 | } | |
a0c12413 | 3321 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
b03a7771 SC |
3322 | if (sg_used) |
3323 | hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
3324 | check_ioctl_unit_attention(h, c); |
3325 | /* Copy the error information out */ | |
3326 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
3327 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 3328 | status = -EFAULT; |
e2d4a1f6 | 3329 | goto cleanup0; |
edd16368 | 3330 | } |
b03a7771 | 3331 | if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) { |
edd16368 SC |
3332 | /* Copy the data out of the buffer we created */ |
3333 | BYTE __user *ptr = ioc->buf; | |
3334 | for (i = 0; i < sg_used; i++) { | |
3335 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 3336 | status = -EFAULT; |
e2d4a1f6 | 3337 | goto cleanup0; |
edd16368 SC |
3338 | } |
3339 | ptr += buff_size[i]; | |
3340 | } | |
3341 | } | |
edd16368 | 3342 | status = 0; |
e2d4a1f6 SC |
3343 | cleanup0: |
3344 | cmd_special_free(h, c); | |
edd16368 SC |
3345 | cleanup1: |
3346 | if (buff) { | |
3347 | for (i = 0; i < sg_used; i++) | |
3348 | kfree(buff[i]); | |
3349 | kfree(buff); | |
3350 | } | |
3351 | kfree(buff_size); | |
3352 | kfree(ioc); | |
3353 | return status; | |
3354 | } | |
3355 | ||
3356 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
3357 | struct CommandList *c) | |
3358 | { | |
3359 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
3360 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
3361 | (void) check_for_unit_attention(h, c); | |
3362 | } | |
0390f0c0 SC |
3363 | |
3364 | static int increment_passthru_count(struct ctlr_info *h) | |
3365 | { | |
3366 | unsigned long flags; | |
3367 | ||
3368 | spin_lock_irqsave(&h->passthru_count_lock, flags); | |
3369 | if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) { | |
3370 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
3371 | return -1; | |
3372 | } | |
3373 | h->passthru_count++; | |
3374 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
3375 | return 0; | |
3376 | } | |
3377 | ||
3378 | static void decrement_passthru_count(struct ctlr_info *h) | |
3379 | { | |
3380 | unsigned long flags; | |
3381 | ||
3382 | spin_lock_irqsave(&h->passthru_count_lock, flags); | |
3383 | if (h->passthru_count <= 0) { | |
3384 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
3385 | /* not expecting to get here. */ | |
3386 | dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n"); | |
3387 | return; | |
3388 | } | |
3389 | h->passthru_count--; | |
3390 | spin_unlock_irqrestore(&h->passthru_count_lock, flags); | |
3391 | } | |
3392 | ||
edd16368 SC |
3393 | /* |
3394 | * ioctl | |
3395 | */ | |
3396 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg) | |
3397 | { | |
3398 | struct ctlr_info *h; | |
3399 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 3400 | int rc; |
edd16368 SC |
3401 | |
3402 | h = sdev_to_hba(dev); | |
3403 | ||
3404 | switch (cmd) { | |
3405 | case CCISS_DEREGDISK: | |
3406 | case CCISS_REGNEWDISK: | |
3407 | case CCISS_REGNEWD: | |
a08a8471 | 3408 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
3409 | return 0; |
3410 | case CCISS_GETPCIINFO: | |
3411 | return hpsa_getpciinfo_ioctl(h, argp); | |
3412 | case CCISS_GETDRIVVER: | |
3413 | return hpsa_getdrivver_ioctl(h, argp); | |
3414 | case CCISS_PASSTHRU: | |
0390f0c0 SC |
3415 | if (increment_passthru_count(h)) |
3416 | return -EAGAIN; | |
3417 | rc = hpsa_passthru_ioctl(h, argp); | |
3418 | decrement_passthru_count(h); | |
3419 | return rc; | |
edd16368 | 3420 | case CCISS_BIG_PASSTHRU: |
0390f0c0 SC |
3421 | if (increment_passthru_count(h)) |
3422 | return -EAGAIN; | |
3423 | rc = hpsa_big_passthru_ioctl(h, argp); | |
3424 | decrement_passthru_count(h); | |
3425 | return rc; | |
edd16368 SC |
3426 | default: |
3427 | return -ENOTTY; | |
3428 | } | |
3429 | } | |
3430 | ||
6f039790 GKH |
3431 | static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
3432 | u8 reset_type) | |
64670ac8 SC |
3433 | { |
3434 | struct CommandList *c; | |
3435 | ||
3436 | c = cmd_alloc(h); | |
3437 | if (!c) | |
3438 | return -ENOMEM; | |
a2dac136 SC |
3439 | /* fill_cmd can't fail here, no data buffer to map */ |
3440 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
3441 | RAID_CTLR_LUNID, TYPE_MSG); |
3442 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
3443 | c->waiting = NULL; | |
3444 | enqueue_cmd_and_start_io(h, c); | |
3445 | /* Don't wait for completion, the reset won't complete. Don't free | |
3446 | * the command either. This is the last command we will send before | |
3447 | * re-initializing everything, so it doesn't matter and won't leak. | |
3448 | */ | |
3449 | return 0; | |
3450 | } | |
3451 | ||
a2dac136 | 3452 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
01a02ffc | 3453 | void *buff, size_t size, u8 page_code, unsigned char *scsi3addr, |
edd16368 SC |
3454 | int cmd_type) |
3455 | { | |
3456 | int pci_dir = XFER_NONE; | |
75167d2c | 3457 | struct CommandList *a; /* for commands to be aborted */ |
edd16368 SC |
3458 | |
3459 | c->cmd_type = CMD_IOCTL_PEND; | |
3460 | c->Header.ReplyQueue = 0; | |
3461 | if (buff != NULL && size > 0) { | |
3462 | c->Header.SGList = 1; | |
3463 | c->Header.SGTotal = 1; | |
3464 | } else { | |
3465 | c->Header.SGList = 0; | |
3466 | c->Header.SGTotal = 0; | |
3467 | } | |
3468 | c->Header.Tag.lower = c->busaddr; | |
3469 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); | |
3470 | ||
3471 | c->Request.Type.Type = cmd_type; | |
3472 | if (cmd_type == TYPE_CMD) { | |
3473 | switch (cmd) { | |
3474 | case HPSA_INQUIRY: | |
3475 | /* are we trying to read a vital product page */ | |
3476 | if (page_code != 0) { | |
3477 | c->Request.CDB[1] = 0x01; | |
3478 | c->Request.CDB[2] = page_code; | |
3479 | } | |
3480 | c->Request.CDBLen = 6; | |
3481 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3482 | c->Request.Type.Direction = XFER_READ; | |
3483 | c->Request.Timeout = 0; | |
3484 | c->Request.CDB[0] = HPSA_INQUIRY; | |
3485 | c->Request.CDB[4] = size & 0xFF; | |
3486 | break; | |
3487 | case HPSA_REPORT_LOG: | |
3488 | case HPSA_REPORT_PHYS: | |
3489 | /* Talking to controller so It's a physical command | |
3490 | mode = 00 target = 0. Nothing to write. | |
3491 | */ | |
3492 | c->Request.CDBLen = 12; | |
3493 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3494 | c->Request.Type.Direction = XFER_READ; | |
3495 | c->Request.Timeout = 0; | |
3496 | c->Request.CDB[0] = cmd; | |
3497 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
3498 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
3499 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
3500 | c->Request.CDB[9] = size & 0xFF; | |
3501 | break; | |
edd16368 SC |
3502 | case HPSA_CACHE_FLUSH: |
3503 | c->Request.CDBLen = 12; | |
3504 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3505 | c->Request.Type.Direction = XFER_WRITE; | |
3506 | c->Request.Timeout = 0; | |
3507 | c->Request.CDB[0] = BMIC_WRITE; | |
3508 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
3509 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
3510 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
3511 | break; |
3512 | case TEST_UNIT_READY: | |
3513 | c->Request.CDBLen = 6; | |
3514 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3515 | c->Request.Type.Direction = XFER_NONE; | |
3516 | c->Request.Timeout = 0; | |
3517 | break; | |
3518 | default: | |
3519 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
3520 | BUG(); | |
a2dac136 | 3521 | return -1; |
edd16368 SC |
3522 | } |
3523 | } else if (cmd_type == TYPE_MSG) { | |
3524 | switch (cmd) { | |
3525 | ||
3526 | case HPSA_DEVICE_RESET_MSG: | |
3527 | c->Request.CDBLen = 16; | |
3528 | c->Request.Type.Type = 1; /* It is a MSG not a CMD */ | |
3529 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3530 | c->Request.Type.Direction = XFER_NONE; | |
3531 | c->Request.Timeout = 0; /* Don't time out */ | |
64670ac8 SC |
3532 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
3533 | c->Request.CDB[0] = cmd; | |
21e89afd | 3534 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
3535 | /* If bytes 4-7 are zero, it means reset the */ |
3536 | /* LunID device */ | |
3537 | c->Request.CDB[4] = 0x00; | |
3538 | c->Request.CDB[5] = 0x00; | |
3539 | c->Request.CDB[6] = 0x00; | |
3540 | c->Request.CDB[7] = 0x00; | |
75167d2c SC |
3541 | break; |
3542 | case HPSA_ABORT_MSG: | |
3543 | a = buff; /* point to command to be aborted */ | |
3544 | dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n", | |
3545 | a->Header.Tag.upper, a->Header.Tag.lower, | |
3546 | c->Header.Tag.upper, c->Header.Tag.lower); | |
3547 | c->Request.CDBLen = 16; | |
3548 | c->Request.Type.Type = TYPE_MSG; | |
3549 | c->Request.Type.Attribute = ATTR_SIMPLE; | |
3550 | c->Request.Type.Direction = XFER_WRITE; | |
3551 | c->Request.Timeout = 0; /* Don't time out */ | |
3552 | c->Request.CDB[0] = HPSA_TASK_MANAGEMENT; | |
3553 | c->Request.CDB[1] = HPSA_TMF_ABORT_TASK; | |
3554 | c->Request.CDB[2] = 0x00; /* reserved */ | |
3555 | c->Request.CDB[3] = 0x00; /* reserved */ | |
3556 | /* Tag to abort goes in CDB[4]-CDB[11] */ | |
3557 | c->Request.CDB[4] = a->Header.Tag.lower & 0xFF; | |
3558 | c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF; | |
3559 | c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF; | |
3560 | c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF; | |
3561 | c->Request.CDB[8] = a->Header.Tag.upper & 0xFF; | |
3562 | c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF; | |
3563 | c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF; | |
3564 | c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF; | |
3565 | c->Request.CDB[12] = 0x00; /* reserved */ | |
3566 | c->Request.CDB[13] = 0x00; /* reserved */ | |
3567 | c->Request.CDB[14] = 0x00; /* reserved */ | |
3568 | c->Request.CDB[15] = 0x00; /* reserved */ | |
edd16368 | 3569 | break; |
edd16368 SC |
3570 | default: |
3571 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
3572 | cmd); | |
3573 | BUG(); | |
3574 | } | |
3575 | } else { | |
3576 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
3577 | BUG(); | |
3578 | } | |
3579 | ||
3580 | switch (c->Request.Type.Direction) { | |
3581 | case XFER_READ: | |
3582 | pci_dir = PCI_DMA_FROMDEVICE; | |
3583 | break; | |
3584 | case XFER_WRITE: | |
3585 | pci_dir = PCI_DMA_TODEVICE; | |
3586 | break; | |
3587 | case XFER_NONE: | |
3588 | pci_dir = PCI_DMA_NONE; | |
3589 | break; | |
3590 | default: | |
3591 | pci_dir = PCI_DMA_BIDIRECTIONAL; | |
3592 | } | |
a2dac136 SC |
3593 | if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) |
3594 | return -1; | |
3595 | return 0; | |
edd16368 SC |
3596 | } |
3597 | ||
3598 | /* | |
3599 | * Map (physical) PCI mem into (virtual) kernel space | |
3600 | */ | |
3601 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
3602 | { | |
3603 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
3604 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
3605 | void __iomem *page_remapped = ioremap_nocache(page_base, |
3606 | page_offs + size); | |
edd16368 SC |
3607 | |
3608 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
3609 | } | |
3610 | ||
3611 | /* Takes cmds off the submission queue and sends them to the hardware, | |
3612 | * then puts them on the queue of cmds waiting for completion. | |
3613 | */ | |
3614 | static void start_io(struct ctlr_info *h) | |
3615 | { | |
3616 | struct CommandList *c; | |
e16a33ad | 3617 | unsigned long flags; |
edd16368 | 3618 | |
e16a33ad | 3619 | spin_lock_irqsave(&h->lock, flags); |
9e0fc764 SC |
3620 | while (!list_empty(&h->reqQ)) { |
3621 | c = list_entry(h->reqQ.next, struct CommandList, list); | |
edd16368 SC |
3622 | /* can't do anything if fifo is full */ |
3623 | if ((h->access.fifo_full(h))) { | |
396883e2 | 3624 | h->fifo_recently_full = 1; |
edd16368 SC |
3625 | dev_warn(&h->pdev->dev, "fifo full\n"); |
3626 | break; | |
3627 | } | |
396883e2 | 3628 | h->fifo_recently_full = 0; |
edd16368 SC |
3629 | |
3630 | /* Get the first entry from the Request Q */ | |
3631 | removeQ(c); | |
3632 | h->Qdepth--; | |
3633 | ||
edd16368 SC |
3634 | /* Put job onto the completed Q */ |
3635 | addQ(&h->cmpQ, c); | |
e16a33ad MG |
3636 | |
3637 | /* Must increment commands_outstanding before unlocking | |
3638 | * and submitting to avoid race checking for fifo full | |
3639 | * condition. | |
3640 | */ | |
3641 | h->commands_outstanding++; | |
3642 | if (h->commands_outstanding > h->max_outstanding) | |
3643 | h->max_outstanding = h->commands_outstanding; | |
3644 | ||
3645 | /* Tell the controller execute command */ | |
3646 | spin_unlock_irqrestore(&h->lock, flags); | |
3647 | h->access.submit_command(h, c); | |
3648 | spin_lock_irqsave(&h->lock, flags); | |
edd16368 | 3649 | } |
e16a33ad | 3650 | spin_unlock_irqrestore(&h->lock, flags); |
edd16368 SC |
3651 | } |
3652 | ||
254f796b | 3653 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 3654 | { |
254f796b | 3655 | return h->access.command_completed(h, q); |
edd16368 SC |
3656 | } |
3657 | ||
900c5440 | 3658 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
3659 | { |
3660 | return h->access.intr_pending(h); | |
3661 | } | |
3662 | ||
3663 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
3664 | { | |
10f66018 SC |
3665 | return (h->access.intr_pending(h) == 0) || |
3666 | (h->interrupts_enabled == 0); | |
edd16368 SC |
3667 | } |
3668 | ||
01a02ffc SC |
3669 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
3670 | u32 raw_tag) | |
edd16368 SC |
3671 | { |
3672 | if (unlikely(tag_index >= h->nr_cmds)) { | |
3673 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
3674 | return 1; | |
3675 | } | |
3676 | return 0; | |
3677 | } | |
3678 | ||
5a3d16f5 | 3679 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 3680 | { |
e16a33ad | 3681 | unsigned long flags; |
396883e2 SC |
3682 | int io_may_be_stalled = 0; |
3683 | struct ctlr_info *h = c->h; | |
e16a33ad | 3684 | |
396883e2 | 3685 | spin_lock_irqsave(&h->lock, flags); |
edd16368 | 3686 | removeQ(c); |
396883e2 SC |
3687 | |
3688 | /* | |
3689 | * Check for possibly stalled i/o. | |
3690 | * | |
3691 | * If a fifo_full condition is encountered, requests will back up | |
3692 | * in h->reqQ. This queue is only emptied out by start_io which is | |
3693 | * only called when a new i/o request comes in. If no i/o's are | |
3694 | * forthcoming, the i/o's in h->reqQ can get stuck. So we call | |
3695 | * start_io from here if we detect such a danger. | |
3696 | * | |
3697 | * Normally, we shouldn't hit this case, but pounding on the | |
3698 | * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if | |
3699 | * commands_outstanding is low. We want to avoid calling | |
3700 | * start_io from in here as much as possible, and esp. don't | |
3701 | * want to get in a cycle where we call start_io every time | |
3702 | * through here. | |
3703 | */ | |
3704 | if (unlikely(h->fifo_recently_full) && | |
3705 | h->commands_outstanding < 5) | |
3706 | io_may_be_stalled = 1; | |
3707 | ||
3708 | spin_unlock_irqrestore(&h->lock, flags); | |
3709 | ||
e85c5974 | 3710 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
e1f7de0c | 3711 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI)) |
1fb011fb | 3712 | complete_scsi_command(c); |
edd16368 SC |
3713 | else if (c->cmd_type == CMD_IOCTL_PEND) |
3714 | complete(c->waiting); | |
396883e2 SC |
3715 | if (unlikely(io_may_be_stalled)) |
3716 | start_io(h); | |
edd16368 SC |
3717 | } |
3718 | ||
a104c99f SC |
3719 | static inline u32 hpsa_tag_contains_index(u32 tag) |
3720 | { | |
a104c99f SC |
3721 | return tag & DIRECT_LOOKUP_BIT; |
3722 | } | |
3723 | ||
3724 | static inline u32 hpsa_tag_to_index(u32 tag) | |
3725 | { | |
a104c99f SC |
3726 | return tag >> DIRECT_LOOKUP_SHIFT; |
3727 | } | |
3728 | ||
a9a3a273 SC |
3729 | |
3730 | static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag) | |
a104c99f | 3731 | { |
a9a3a273 SC |
3732 | #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1) |
3733 | #define HPSA_SIMPLE_ERROR_BITS 0x03 | |
960a30e7 | 3734 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
a9a3a273 SC |
3735 | return tag & ~HPSA_SIMPLE_ERROR_BITS; |
3736 | return tag & ~HPSA_PERF_ERROR_BITS; | |
a104c99f SC |
3737 | } |
3738 | ||
303932fd | 3739 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 3740 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
3741 | u32 raw_tag) |
3742 | { | |
3743 | u32 tag_index; | |
3744 | struct CommandList *c; | |
3745 | ||
3746 | tag_index = hpsa_tag_to_index(raw_tag); | |
1d94f94d SC |
3747 | if (!bad_tag(h, tag_index, raw_tag)) { |
3748 | c = h->cmd_pool + tag_index; | |
3749 | finish_cmd(c); | |
3750 | } | |
303932fd DB |
3751 | } |
3752 | ||
3753 | /* process completion of a non-indexed command */ | |
1d94f94d | 3754 | static inline void process_nonindexed_cmd(struct ctlr_info *h, |
303932fd DB |
3755 | u32 raw_tag) |
3756 | { | |
3757 | u32 tag; | |
3758 | struct CommandList *c = NULL; | |
e16a33ad | 3759 | unsigned long flags; |
303932fd | 3760 | |
a9a3a273 | 3761 | tag = hpsa_tag_discard_error_bits(h, raw_tag); |
e16a33ad | 3762 | spin_lock_irqsave(&h->lock, flags); |
9e0fc764 | 3763 | list_for_each_entry(c, &h->cmpQ, list) { |
303932fd | 3764 | if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) { |
e16a33ad | 3765 | spin_unlock_irqrestore(&h->lock, flags); |
5a3d16f5 | 3766 | finish_cmd(c); |
1d94f94d | 3767 | return; |
303932fd DB |
3768 | } |
3769 | } | |
e16a33ad | 3770 | spin_unlock_irqrestore(&h->lock, flags); |
303932fd | 3771 | bad_tag(h, h->nr_cmds + 1, raw_tag); |
303932fd DB |
3772 | } |
3773 | ||
64670ac8 SC |
3774 | /* Some controllers, like p400, will give us one interrupt |
3775 | * after a soft reset, even if we turned interrupts off. | |
3776 | * Only need to check for this in the hpsa_xxx_discard_completions | |
3777 | * functions. | |
3778 | */ | |
3779 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
3780 | { | |
3781 | if (likely(!reset_devices)) | |
3782 | return 0; | |
3783 | ||
3784 | if (likely(h->interrupts_enabled)) | |
3785 | return 0; | |
3786 | ||
3787 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
3788 | "(known firmware bug.) Ignoring.\n"); | |
3789 | ||
3790 | return 1; | |
3791 | } | |
3792 | ||
254f796b MG |
3793 | /* |
3794 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
3795 | * Relies on (h-q[x] == x) being true for x such that | |
3796 | * 0 <= x < MAX_REPLY_QUEUES. | |
3797 | */ | |
3798 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 3799 | { |
254f796b MG |
3800 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
3801 | } | |
3802 | ||
3803 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
3804 | { | |
3805 | struct ctlr_info *h = queue_to_hba(queue); | |
3806 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
3807 | u32 raw_tag; |
3808 | ||
3809 | if (ignore_bogus_interrupt(h)) | |
3810 | return IRQ_NONE; | |
3811 | ||
3812 | if (interrupt_not_for_us(h)) | |
3813 | return IRQ_NONE; | |
a0c12413 | 3814 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 3815 | while (interrupt_pending(h)) { |
254f796b | 3816 | raw_tag = get_next_completion(h, q); |
64670ac8 | 3817 | while (raw_tag != FIFO_EMPTY) |
254f796b | 3818 | raw_tag = next_command(h, q); |
64670ac8 | 3819 | } |
64670ac8 SC |
3820 | return IRQ_HANDLED; |
3821 | } | |
3822 | ||
254f796b | 3823 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 3824 | { |
254f796b | 3825 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 3826 | u32 raw_tag; |
254f796b | 3827 | u8 q = *(u8 *) queue; |
64670ac8 SC |
3828 | |
3829 | if (ignore_bogus_interrupt(h)) | |
3830 | return IRQ_NONE; | |
3831 | ||
a0c12413 | 3832 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 3833 | raw_tag = get_next_completion(h, q); |
64670ac8 | 3834 | while (raw_tag != FIFO_EMPTY) |
254f796b | 3835 | raw_tag = next_command(h, q); |
64670ac8 SC |
3836 | return IRQ_HANDLED; |
3837 | } | |
3838 | ||
254f796b | 3839 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 3840 | { |
254f796b | 3841 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 3842 | u32 raw_tag; |
254f796b | 3843 | u8 q = *(u8 *) queue; |
edd16368 SC |
3844 | |
3845 | if (interrupt_not_for_us(h)) | |
3846 | return IRQ_NONE; | |
a0c12413 | 3847 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 3848 | while (interrupt_pending(h)) { |
254f796b | 3849 | raw_tag = get_next_completion(h, q); |
10f66018 | 3850 | while (raw_tag != FIFO_EMPTY) { |
1d94f94d SC |
3851 | if (likely(hpsa_tag_contains_index(raw_tag))) |
3852 | process_indexed_cmd(h, raw_tag); | |
10f66018 | 3853 | else |
1d94f94d | 3854 | process_nonindexed_cmd(h, raw_tag); |
254f796b | 3855 | raw_tag = next_command(h, q); |
10f66018 SC |
3856 | } |
3857 | } | |
10f66018 SC |
3858 | return IRQ_HANDLED; |
3859 | } | |
3860 | ||
254f796b | 3861 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 3862 | { |
254f796b | 3863 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 3864 | u32 raw_tag; |
254f796b | 3865 | u8 q = *(u8 *) queue; |
10f66018 | 3866 | |
a0c12413 | 3867 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 3868 | raw_tag = get_next_completion(h, q); |
303932fd | 3869 | while (raw_tag != FIFO_EMPTY) { |
1d94f94d SC |
3870 | if (likely(hpsa_tag_contains_index(raw_tag))) |
3871 | process_indexed_cmd(h, raw_tag); | |
303932fd | 3872 | else |
1d94f94d | 3873 | process_nonindexed_cmd(h, raw_tag); |
254f796b | 3874 | raw_tag = next_command(h, q); |
edd16368 | 3875 | } |
edd16368 SC |
3876 | return IRQ_HANDLED; |
3877 | } | |
3878 | ||
a9a3a273 SC |
3879 | /* Send a message CDB to the firmware. Careful, this only works |
3880 | * in simple mode, not performant mode due to the tag lookup. | |
3881 | * We only ever use this immediately after a controller reset. | |
3882 | */ | |
6f039790 GKH |
3883 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
3884 | unsigned char type) | |
edd16368 SC |
3885 | { |
3886 | struct Command { | |
3887 | struct CommandListHeader CommandHeader; | |
3888 | struct RequestBlock Request; | |
3889 | struct ErrDescriptor ErrorDescriptor; | |
3890 | }; | |
3891 | struct Command *cmd; | |
3892 | static const size_t cmd_sz = sizeof(*cmd) + | |
3893 | sizeof(cmd->ErrorDescriptor); | |
3894 | dma_addr_t paddr64; | |
3895 | uint32_t paddr32, tag; | |
3896 | void __iomem *vaddr; | |
3897 | int i, err; | |
3898 | ||
3899 | vaddr = pci_ioremap_bar(pdev, 0); | |
3900 | if (vaddr == NULL) | |
3901 | return -ENOMEM; | |
3902 | ||
3903 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
3904 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
3905 | * memory. | |
3906 | */ | |
3907 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
3908 | if (err) { | |
3909 | iounmap(vaddr); | |
3910 | return -ENOMEM; | |
3911 | } | |
3912 | ||
3913 | cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); | |
3914 | if (cmd == NULL) { | |
3915 | iounmap(vaddr); | |
3916 | return -ENOMEM; | |
3917 | } | |
3918 | ||
3919 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
3920 | * although there's no guarantee, we assume that the address is at | |
3921 | * least 4-byte aligned (most likely, it's page-aligned). | |
3922 | */ | |
3923 | paddr32 = paddr64; | |
3924 | ||
3925 | cmd->CommandHeader.ReplyQueue = 0; | |
3926 | cmd->CommandHeader.SGList = 0; | |
3927 | cmd->CommandHeader.SGTotal = 0; | |
3928 | cmd->CommandHeader.Tag.lower = paddr32; | |
3929 | cmd->CommandHeader.Tag.upper = 0; | |
3930 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); | |
3931 | ||
3932 | cmd->Request.CDBLen = 16; | |
3933 | cmd->Request.Type.Type = TYPE_MSG; | |
3934 | cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE; | |
3935 | cmd->Request.Type.Direction = XFER_NONE; | |
3936 | cmd->Request.Timeout = 0; /* Don't time out */ | |
3937 | cmd->Request.CDB[0] = opcode; | |
3938 | cmd->Request.CDB[1] = type; | |
3939 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
3940 | cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd); | |
3941 | cmd->ErrorDescriptor.Addr.upper = 0; | |
3942 | cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo); | |
3943 | ||
3944 | writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET); | |
3945 | ||
3946 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
3947 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
a9a3a273 | 3948 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32) |
edd16368 SC |
3949 | break; |
3950 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
3951 | } | |
3952 | ||
3953 | iounmap(vaddr); | |
3954 | ||
3955 | /* we leak the DMA buffer here ... no choice since the controller could | |
3956 | * still complete the command. | |
3957 | */ | |
3958 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
3959 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
3960 | opcode, type); | |
3961 | return -ETIMEDOUT; | |
3962 | } | |
3963 | ||
3964 | pci_free_consistent(pdev, cmd_sz, cmd, paddr64); | |
3965 | ||
3966 | if (tag & HPSA_ERROR_BIT) { | |
3967 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
3968 | opcode, type); | |
3969 | return -EIO; | |
3970 | } | |
3971 | ||
3972 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
3973 | opcode, type); | |
3974 | return 0; | |
3975 | } | |
3976 | ||
edd16368 SC |
3977 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
3978 | ||
1df8552a | 3979 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
cf0b08d0 | 3980 | void * __iomem vaddr, u32 use_doorbell) |
1df8552a SC |
3981 | { |
3982 | u16 pmcsr; | |
3983 | int pos; | |
3984 | ||
3985 | if (use_doorbell) { | |
3986 | /* For everything after the P600, the PCI power state method | |
3987 | * of resetting the controller doesn't work, so we have this | |
3988 | * other way using the doorbell register. | |
3989 | */ | |
3990 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 3991 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 SC |
3992 | |
3993 | /* PMC hardware guys tell us we need a 5 second delay after | |
3994 | * doorbell reset and before any attempt to talk to the board | |
3995 | * at all to ensure that this actually works and doesn't fall | |
3996 | * over in some weird corner cases. | |
3997 | */ | |
3998 | msleep(5000); | |
1df8552a SC |
3999 | } else { /* Try to do it the PCI power state way */ |
4000 | ||
4001 | /* Quoting from the Open CISS Specification: "The Power | |
4002 | * Management Control/Status Register (CSR) controls the power | |
4003 | * state of the device. The normal operating state is D0, | |
4004 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
4005 | * the controller, place the interface device in D3 then to D0, | |
4006 | * this causes a secondary PCI reset which will reset the | |
4007 | * controller." */ | |
4008 | ||
4009 | pos = pci_find_capability(pdev, PCI_CAP_ID_PM); | |
4010 | if (pos == 0) { | |
4011 | dev_err(&pdev->dev, | |
4012 | "hpsa_reset_controller: " | |
4013 | "PCI PM not supported\n"); | |
4014 | return -ENODEV; | |
4015 | } | |
4016 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); | |
4017 | /* enter the D3hot power management state */ | |
4018 | pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr); | |
4019 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
4020 | pmcsr |= PCI_D3hot; | |
4021 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | |
4022 | ||
4023 | msleep(500); | |
4024 | ||
4025 | /* enter the D0 power management state */ | |
4026 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; | |
4027 | pmcsr |= PCI_D0; | |
4028 | pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr); | |
c4853efe MM |
4029 | |
4030 | /* | |
4031 | * The P600 requires a small delay when changing states. | |
4032 | * Otherwise we may think the board did not reset and we bail. | |
4033 | * This for kdump only and is particular to the P600. | |
4034 | */ | |
4035 | msleep(500); | |
1df8552a SC |
4036 | } |
4037 | return 0; | |
4038 | } | |
4039 | ||
6f039790 | 4040 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
4041 | { |
4042 | memset(driver_version, 0, len); | |
f79cfec6 | 4043 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
4044 | } |
4045 | ||
6f039790 | 4046 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
4047 | { |
4048 | char *driver_version; | |
4049 | int i, size = sizeof(cfgtable->driver_version); | |
4050 | ||
4051 | driver_version = kmalloc(size, GFP_KERNEL); | |
4052 | if (!driver_version) | |
4053 | return -ENOMEM; | |
4054 | ||
4055 | init_driver_version(driver_version, size); | |
4056 | for (i = 0; i < size; i++) | |
4057 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
4058 | kfree(driver_version); | |
4059 | return 0; | |
4060 | } | |
4061 | ||
6f039790 GKH |
4062 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
4063 | unsigned char *driver_ver) | |
580ada3c SC |
4064 | { |
4065 | int i; | |
4066 | ||
4067 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
4068 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
4069 | } | |
4070 | ||
6f039790 | 4071 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
4072 | { |
4073 | ||
4074 | char *driver_ver, *old_driver_ver; | |
4075 | int rc, size = sizeof(cfgtable->driver_version); | |
4076 | ||
4077 | old_driver_ver = kmalloc(2 * size, GFP_KERNEL); | |
4078 | if (!old_driver_ver) | |
4079 | return -ENOMEM; | |
4080 | driver_ver = old_driver_ver + size; | |
4081 | ||
4082 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
4083 | * should have been changed, otherwise we know the reset failed. | |
4084 | */ | |
4085 | init_driver_version(old_driver_ver, size); | |
4086 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
4087 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
4088 | kfree(old_driver_ver); | |
4089 | return rc; | |
4090 | } | |
edd16368 | 4091 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 4092 | * states or the using the doorbell register. |
edd16368 | 4093 | */ |
6f039790 | 4094 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev) |
edd16368 | 4095 | { |
1df8552a SC |
4096 | u64 cfg_offset; |
4097 | u32 cfg_base_addr; | |
4098 | u64 cfg_base_addr_index; | |
4099 | void __iomem *vaddr; | |
4100 | unsigned long paddr; | |
580ada3c | 4101 | u32 misc_fw_support; |
270d05de | 4102 | int rc; |
1df8552a | 4103 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 4104 | u32 use_doorbell; |
18867659 | 4105 | u32 board_id; |
270d05de | 4106 | u16 command_register; |
edd16368 | 4107 | |
1df8552a SC |
4108 | /* For controllers as old as the P600, this is very nearly |
4109 | * the same thing as | |
edd16368 SC |
4110 | * |
4111 | * pci_save_state(pci_dev); | |
4112 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
4113 | * pci_set_power_state(pci_dev, PCI_D0); | |
4114 | * pci_restore_state(pci_dev); | |
4115 | * | |
1df8552a SC |
4116 | * For controllers newer than the P600, the pci power state |
4117 | * method of resetting doesn't work so we have another way | |
4118 | * using the doorbell register. | |
edd16368 | 4119 | */ |
18867659 | 4120 | |
25c1e56a | 4121 | rc = hpsa_lookup_board_id(pdev, &board_id); |
46380786 | 4122 | if (rc < 0 || !ctlr_is_resettable(board_id)) { |
25c1e56a SC |
4123 | dev_warn(&pdev->dev, "Not resetting device.\n"); |
4124 | return -ENODEV; | |
4125 | } | |
46380786 SC |
4126 | |
4127 | /* if controller is soft- but not hard resettable... */ | |
4128 | if (!ctlr_is_hard_resettable(board_id)) | |
4129 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 4130 | |
270d05de SC |
4131 | /* Save the PCI command register */ |
4132 | pci_read_config_word(pdev, 4, &command_register); | |
4133 | /* Turn the board off. This is so that later pci_restore_state() | |
4134 | * won't turn the board on before the rest of config space is ready. | |
4135 | */ | |
4136 | pci_disable_device(pdev); | |
4137 | pci_save_state(pdev); | |
edd16368 | 4138 | |
1df8552a SC |
4139 | /* find the first memory BAR, so we can find the cfg table */ |
4140 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
4141 | if (rc) | |
4142 | return rc; | |
4143 | vaddr = remap_pci_mem(paddr, 0x250); | |
4144 | if (!vaddr) | |
4145 | return -ENOMEM; | |
edd16368 | 4146 | |
1df8552a SC |
4147 | /* find cfgtable in order to check if reset via doorbell is supported */ |
4148 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
4149 | &cfg_base_addr_index, &cfg_offset); | |
4150 | if (rc) | |
4151 | goto unmap_vaddr; | |
4152 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
4153 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
4154 | if (!cfgtable) { | |
4155 | rc = -ENOMEM; | |
4156 | goto unmap_vaddr; | |
4157 | } | |
580ada3c SC |
4158 | rc = write_driver_ver_to_cfgtable(cfgtable); |
4159 | if (rc) | |
4160 | goto unmap_vaddr; | |
edd16368 | 4161 | |
cf0b08d0 SC |
4162 | /* If reset via doorbell register is supported, use that. |
4163 | * There are two such methods. Favor the newest method. | |
4164 | */ | |
1df8552a | 4165 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
4166 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
4167 | if (use_doorbell) { | |
4168 | use_doorbell = DOORBELL_CTLR_RESET2; | |
4169 | } else { | |
4170 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
4171 | if (use_doorbell) { | |
fba63097 MM |
4172 | dev_warn(&pdev->dev, "Soft reset not supported. " |
4173 | "Firmware update is required.\n"); | |
64670ac8 | 4174 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
4175 | goto unmap_cfgtable; |
4176 | } | |
4177 | } | |
edd16368 | 4178 | |
1df8552a SC |
4179 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
4180 | if (rc) | |
4181 | goto unmap_cfgtable; | |
edd16368 | 4182 | |
270d05de SC |
4183 | pci_restore_state(pdev); |
4184 | rc = pci_enable_device(pdev); | |
4185 | if (rc) { | |
4186 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
4187 | goto unmap_cfgtable; | |
edd16368 | 4188 | } |
270d05de | 4189 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 4190 | |
1df8552a SC |
4191 | /* Some devices (notably the HP Smart Array 5i Controller) |
4192 | need a little pause here */ | |
4193 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
4194 | ||
fe5389c8 SC |
4195 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
4196 | if (rc) { | |
4197 | dev_warn(&pdev->dev, | |
64670ac8 SC |
4198 | "failed waiting for board to become ready " |
4199 | "after hard reset\n"); | |
fe5389c8 SC |
4200 | goto unmap_cfgtable; |
4201 | } | |
fe5389c8 | 4202 | |
580ada3c SC |
4203 | rc = controller_reset_failed(vaddr); |
4204 | if (rc < 0) | |
4205 | goto unmap_cfgtable; | |
4206 | if (rc) { | |
64670ac8 SC |
4207 | dev_warn(&pdev->dev, "Unable to successfully reset " |
4208 | "controller. Will try soft reset.\n"); | |
4209 | rc = -ENOTSUPP; | |
580ada3c | 4210 | } else { |
64670ac8 | 4211 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
4212 | } |
4213 | ||
4214 | unmap_cfgtable: | |
4215 | iounmap(cfgtable); | |
4216 | ||
4217 | unmap_vaddr: | |
4218 | iounmap(vaddr); | |
4219 | return rc; | |
edd16368 SC |
4220 | } |
4221 | ||
4222 | /* | |
4223 | * We cannot read the structure directly, for portability we must use | |
4224 | * the io functions. | |
4225 | * This is for debug only. | |
4226 | */ | |
edd16368 SC |
4227 | static void print_cfg_table(struct device *dev, struct CfgTable *tb) |
4228 | { | |
58f8665c | 4229 | #ifdef HPSA_DEBUG |
edd16368 SC |
4230 | int i; |
4231 | char temp_name[17]; | |
4232 | ||
4233 | dev_info(dev, "Controller Configuration information\n"); | |
4234 | dev_info(dev, "------------------------------------\n"); | |
4235 | for (i = 0; i < 4; i++) | |
4236 | temp_name[i] = readb(&(tb->Signature[i])); | |
4237 | temp_name[4] = '\0'; | |
4238 | dev_info(dev, " Signature = %s\n", temp_name); | |
4239 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
4240 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
4241 | readl(&(tb->TransportSupport))); | |
4242 | dev_info(dev, " Transport methods active = 0x%x\n", | |
4243 | readl(&(tb->TransportActive))); | |
4244 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
4245 | readl(&(tb->HostWrite.TransportRequest))); | |
4246 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
4247 | readl(&(tb->HostWrite.CoalIntDelay))); | |
4248 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
4249 | readl(&(tb->HostWrite.CoalIntCount))); | |
4250 | dev_info(dev, " Max outstanding commands = 0x%d\n", | |
4251 | readl(&(tb->CmdsOutMax))); | |
4252 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
4253 | for (i = 0; i < 16; i++) | |
4254 | temp_name[i] = readb(&(tb->ServerName[i])); | |
4255 | temp_name[16] = '\0'; | |
4256 | dev_info(dev, " Server Name = %s\n", temp_name); | |
4257 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
4258 | readl(&(tb->HeartBeat))); | |
edd16368 | 4259 | #endif /* HPSA_DEBUG */ |
58f8665c | 4260 | } |
edd16368 SC |
4261 | |
4262 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
4263 | { | |
4264 | int i, offset, mem_type, bar_type; | |
4265 | ||
4266 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
4267 | return 0; | |
4268 | offset = 0; | |
4269 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
4270 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
4271 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
4272 | offset += 4; | |
4273 | else { | |
4274 | mem_type = pci_resource_flags(pdev, i) & | |
4275 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
4276 | switch (mem_type) { | |
4277 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
4278 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
4279 | offset += 4; /* 32 bit */ | |
4280 | break; | |
4281 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
4282 | offset += 8; | |
4283 | break; | |
4284 | default: /* reserved in PCI 2.2 */ | |
4285 | dev_warn(&pdev->dev, | |
4286 | "base address is invalid\n"); | |
4287 | return -1; | |
4288 | break; | |
4289 | } | |
4290 | } | |
4291 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
4292 | return i + 1; | |
4293 | } | |
4294 | return -1; | |
4295 | } | |
4296 | ||
4297 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on | |
4298 | * controllers that are capable. If not, we use IO-APIC mode. | |
4299 | */ | |
4300 | ||
6f039790 | 4301 | static void hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 SC |
4302 | { |
4303 | #ifdef CONFIG_PCI_MSI | |
254f796b MG |
4304 | int err, i; |
4305 | struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES]; | |
4306 | ||
4307 | for (i = 0; i < MAX_REPLY_QUEUES; i++) { | |
4308 | hpsa_msix_entries[i].vector = 0; | |
4309 | hpsa_msix_entries[i].entry = i; | |
4310 | } | |
edd16368 SC |
4311 | |
4312 | /* Some boards advertise MSI but don't really support it */ | |
6b3f4c52 SC |
4313 | if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) || |
4314 | (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11)) | |
edd16368 | 4315 | goto default_int_mode; |
55c06c71 SC |
4316 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) { |
4317 | dev_info(&h->pdev->dev, "MSIX\n"); | |
eee0f03a | 4318 | h->msix_vector = MAX_REPLY_QUEUES; |
254f796b | 4319 | err = pci_enable_msix(h->pdev, hpsa_msix_entries, |
eee0f03a | 4320 | h->msix_vector); |
edd16368 | 4321 | if (err > 0) { |
55c06c71 | 4322 | dev_warn(&h->pdev->dev, "only %d MSI-X vectors " |
edd16368 | 4323 | "available\n", err); |
eee0f03a HR |
4324 | h->msix_vector = err; |
4325 | err = pci_enable_msix(h->pdev, hpsa_msix_entries, | |
4326 | h->msix_vector); | |
4327 | } | |
4328 | if (!err) { | |
4329 | for (i = 0; i < h->msix_vector; i++) | |
4330 | h->intr[i] = hpsa_msix_entries[i].vector; | |
4331 | return; | |
edd16368 | 4332 | } else { |
55c06c71 | 4333 | dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", |
edd16368 | 4334 | err); |
eee0f03a | 4335 | h->msix_vector = 0; |
edd16368 SC |
4336 | goto default_int_mode; |
4337 | } | |
4338 | } | |
55c06c71 SC |
4339 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) { |
4340 | dev_info(&h->pdev->dev, "MSI\n"); | |
4341 | if (!pci_enable_msi(h->pdev)) | |
edd16368 SC |
4342 | h->msi_vector = 1; |
4343 | else | |
55c06c71 | 4344 | dev_warn(&h->pdev->dev, "MSI init failed\n"); |
edd16368 SC |
4345 | } |
4346 | default_int_mode: | |
4347 | #endif /* CONFIG_PCI_MSI */ | |
4348 | /* if we get here we're going to use the default interrupt mode */ | |
a9a3a273 | 4349 | h->intr[h->intr_mode] = h->pdev->irq; |
edd16368 SC |
4350 | } |
4351 | ||
6f039790 | 4352 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id) |
e5c880d1 SC |
4353 | { |
4354 | int i; | |
4355 | u32 subsystem_vendor_id, subsystem_device_id; | |
4356 | ||
4357 | subsystem_vendor_id = pdev->subsystem_vendor; | |
4358 | subsystem_device_id = pdev->subsystem_device; | |
4359 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
4360 | subsystem_vendor_id; | |
4361 | ||
4362 | for (i = 0; i < ARRAY_SIZE(products); i++) | |
4363 | if (*board_id == products[i].board_id) | |
4364 | return i; | |
4365 | ||
6798cc0a SC |
4366 | if ((subsystem_vendor_id != PCI_VENDOR_ID_HP && |
4367 | subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) || | |
4368 | !hpsa_allow_any) { | |
e5c880d1 SC |
4369 | dev_warn(&pdev->dev, "unrecognized board ID: " |
4370 | "0x%08x, ignoring.\n", *board_id); | |
4371 | return -ENODEV; | |
4372 | } | |
4373 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ | |
4374 | } | |
4375 | ||
6f039790 GKH |
4376 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
4377 | unsigned long *memory_bar) | |
3a7774ce SC |
4378 | { |
4379 | int i; | |
4380 | ||
4381 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 4382 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 4383 | /* addressing mode bits already removed */ |
12d2cd47 SC |
4384 | *memory_bar = pci_resource_start(pdev, i); |
4385 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
4386 | *memory_bar); |
4387 | return 0; | |
4388 | } | |
12d2cd47 | 4389 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
4390 | return -ENODEV; |
4391 | } | |
4392 | ||
6f039790 GKH |
4393 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
4394 | int wait_for_ready) | |
2c4c8c8b | 4395 | { |
fe5389c8 | 4396 | int i, iterations; |
2c4c8c8b | 4397 | u32 scratchpad; |
fe5389c8 SC |
4398 | if (wait_for_ready) |
4399 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
4400 | else | |
4401 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 4402 | |
fe5389c8 SC |
4403 | for (i = 0; i < iterations; i++) { |
4404 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
4405 | if (wait_for_ready) { | |
4406 | if (scratchpad == HPSA_FIRMWARE_READY) | |
4407 | return 0; | |
4408 | } else { | |
4409 | if (scratchpad != HPSA_FIRMWARE_READY) | |
4410 | return 0; | |
4411 | } | |
2c4c8c8b SC |
4412 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
4413 | } | |
fe5389c8 | 4414 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
4415 | return -ENODEV; |
4416 | } | |
4417 | ||
6f039790 GKH |
4418 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
4419 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
4420 | u64 *cfg_offset) | |
a51fd47f SC |
4421 | { |
4422 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
4423 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
4424 | *cfg_base_addr &= (u32) 0x0000ffff; | |
4425 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
4426 | if (*cfg_base_addr_index == -1) { | |
4427 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
4428 | return -ENODEV; | |
4429 | } | |
4430 | return 0; | |
4431 | } | |
4432 | ||
6f039790 | 4433 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 4434 | { |
01a02ffc SC |
4435 | u64 cfg_offset; |
4436 | u32 cfg_base_addr; | |
4437 | u64 cfg_base_addr_index; | |
303932fd | 4438 | u32 trans_offset; |
a51fd47f | 4439 | int rc; |
77c4495c | 4440 | |
a51fd47f SC |
4441 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
4442 | &cfg_base_addr_index, &cfg_offset); | |
4443 | if (rc) | |
4444 | return rc; | |
77c4495c | 4445 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 4446 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
77c4495c SC |
4447 | if (!h->cfgtable) |
4448 | return -ENOMEM; | |
580ada3c SC |
4449 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
4450 | if (rc) | |
4451 | return rc; | |
77c4495c | 4452 | /* Find performant mode table. */ |
a51fd47f | 4453 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
4454 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
4455 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
4456 | sizeof(*h->transtable)); | |
4457 | if (!h->transtable) | |
4458 | return -ENOMEM; | |
4459 | return 0; | |
4460 | } | |
4461 | ||
6f039790 | 4462 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b SC |
4463 | { |
4464 | h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands)); | |
72ceeaec SC |
4465 | |
4466 | /* Limit commands in memory limited kdump scenario. */ | |
4467 | if (reset_devices && h->max_commands > 32) | |
4468 | h->max_commands = 32; | |
4469 | ||
cba3d38b SC |
4470 | if (h->max_commands < 16) { |
4471 | dev_warn(&h->pdev->dev, "Controller reports " | |
4472 | "max supported commands of %d, an obvious lie. " | |
4473 | "Using 16. Ensure that firmware is up to date.\n", | |
4474 | h->max_commands); | |
4475 | h->max_commands = 16; | |
4476 | } | |
4477 | } | |
4478 | ||
b93d7536 SC |
4479 | /* Interrogate the hardware for some limits: |
4480 | * max commands, max SG elements without chaining, and with chaining, | |
4481 | * SG chain block size, etc. | |
4482 | */ | |
6f039790 | 4483 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 4484 | { |
cba3d38b | 4485 | hpsa_get_max_perf_mode_cmds(h); |
b93d7536 SC |
4486 | h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */ |
4487 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); | |
4488 | /* | |
4489 | * Limit in-command s/g elements to 32 save dma'able memory. | |
4490 | * Howvever spec says if 0, use 31 | |
4491 | */ | |
4492 | h->max_cmd_sg_entries = 31; | |
4493 | if (h->maxsgentries > 512) { | |
4494 | h->max_cmd_sg_entries = 32; | |
4495 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1; | |
4496 | h->maxsgentries--; /* save one for chain pointer */ | |
4497 | } else { | |
4498 | h->maxsgentries = 31; /* default to traditional values */ | |
4499 | h->chainsize = 0; | |
4500 | } | |
75167d2c SC |
4501 | |
4502 | /* Find out what task management functions are supported and cache */ | |
4503 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
b93d7536 SC |
4504 | } |
4505 | ||
76c46e49 SC |
4506 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
4507 | { | |
0fc9fd40 | 4508 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
76c46e49 SC |
4509 | dev_warn(&h->pdev->dev, "not a valid CISS config table\n"); |
4510 | return false; | |
4511 | } | |
4512 | return true; | |
4513 | } | |
4514 | ||
97a5e98c | 4515 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 4516 | { |
97a5e98c | 4517 | u32 driver_support; |
f7c39101 | 4518 | |
28e13446 SC |
4519 | #ifdef CONFIG_X86 |
4520 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ | |
97a5e98c SC |
4521 | driver_support = readl(&(h->cfgtable->driver_support)); |
4522 | driver_support |= ENABLE_SCSI_PREFETCH; | |
f7c39101 | 4523 | #endif |
28e13446 SC |
4524 | driver_support |= ENABLE_UNIT_ATTN; |
4525 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
4526 | } |
4527 | ||
3d0eab67 SC |
4528 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
4529 | * in a prefetch beyond physical memory. | |
4530 | */ | |
4531 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
4532 | { | |
4533 | u32 dma_prefetch; | |
4534 | ||
4535 | if (h->board_id != 0x3225103C) | |
4536 | return; | |
4537 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
4538 | dma_prefetch |= 0x8000; | |
4539 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
4540 | } | |
4541 | ||
6f039790 | 4542 | static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
4543 | { |
4544 | int i; | |
6eaf46fd SC |
4545 | u32 doorbell_value; |
4546 | unsigned long flags; | |
eb6b2ae9 SC |
4547 | |
4548 | /* under certain very rare conditions, this can take awhile. | |
4549 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
4550 | * as we enter this code.) | |
4551 | */ | |
4552 | for (i = 0; i < MAX_CONFIG_WAIT; i++) { | |
6eaf46fd SC |
4553 | spin_lock_irqsave(&h->lock, flags); |
4554 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
4555 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 4556 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
eb6b2ae9 SC |
4557 | break; |
4558 | /* delay and try again */ | |
60d3f5b0 | 4559 | usleep_range(10000, 20000); |
eb6b2ae9 | 4560 | } |
3f4336f3 SC |
4561 | } |
4562 | ||
6f039790 | 4563 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
4564 | { |
4565 | u32 trans_support; | |
4566 | ||
4567 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
4568 | if (!(trans_support & SIMPLE_MODE)) | |
4569 | return -ENOTSUPP; | |
4570 | ||
4571 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
4572 | /* Update the field, and then ring the doorbell */ | |
4573 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
4574 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); | |
4575 | hpsa_wait_for_mode_change_ack(h); | |
eb6b2ae9 | 4576 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
eb6b2ae9 SC |
4577 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) { |
4578 | dev_warn(&h->pdev->dev, | |
4579 | "unable to get board into simple mode\n"); | |
4580 | return -ENODEV; | |
4581 | } | |
960a30e7 | 4582 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 SC |
4583 | return 0; |
4584 | } | |
4585 | ||
6f039790 | 4586 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 4587 | { |
eb6b2ae9 | 4588 | int prod_index, err; |
edd16368 | 4589 | |
e5c880d1 SC |
4590 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id); |
4591 | if (prod_index < 0) | |
4592 | return -ENODEV; | |
4593 | h->product_name = products[prod_index].product_name; | |
4594 | h->access = *(products[prod_index].access); | |
edd16368 | 4595 | |
e5a44df8 MG |
4596 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
4597 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
4598 | ||
55c06c71 | 4599 | err = pci_enable_device(h->pdev); |
edd16368 | 4600 | if (err) { |
55c06c71 | 4601 | dev_warn(&h->pdev->dev, "unable to enable PCI device\n"); |
edd16368 SC |
4602 | return err; |
4603 | } | |
4604 | ||
5cb460a6 SC |
4605 | /* Enable bus mastering (pci_disable_device may disable this) */ |
4606 | pci_set_master(h->pdev); | |
4607 | ||
f79cfec6 | 4608 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 4609 | if (err) { |
55c06c71 SC |
4610 | dev_err(&h->pdev->dev, |
4611 | "cannot obtain PCI resources, aborting\n"); | |
edd16368 SC |
4612 | return err; |
4613 | } | |
6b3f4c52 | 4614 | hpsa_interrupt_mode(h); |
12d2cd47 | 4615 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 4616 | if (err) |
edd16368 | 4617 | goto err_out_free_res; |
edd16368 | 4618 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 SC |
4619 | if (!h->vaddr) { |
4620 | err = -ENOMEM; | |
4621 | goto err_out_free_res; | |
4622 | } | |
fe5389c8 | 4623 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 4624 | if (err) |
edd16368 | 4625 | goto err_out_free_res; |
77c4495c SC |
4626 | err = hpsa_find_cfgtables(h); |
4627 | if (err) | |
edd16368 | 4628 | goto err_out_free_res; |
b93d7536 | 4629 | hpsa_find_board_params(h); |
edd16368 | 4630 | |
76c46e49 | 4631 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 SC |
4632 | err = -ENODEV; |
4633 | goto err_out_free_res; | |
4634 | } | |
97a5e98c | 4635 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 4636 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
4637 | err = hpsa_enter_simple_mode(h); |
4638 | if (err) | |
edd16368 | 4639 | goto err_out_free_res; |
edd16368 SC |
4640 | return 0; |
4641 | ||
4642 | err_out_free_res: | |
204892e9 SC |
4643 | if (h->transtable) |
4644 | iounmap(h->transtable); | |
4645 | if (h->cfgtable) | |
4646 | iounmap(h->cfgtable); | |
4647 | if (h->vaddr) | |
4648 | iounmap(h->vaddr); | |
f0bd0b68 | 4649 | pci_disable_device(h->pdev); |
55c06c71 | 4650 | pci_release_regions(h->pdev); |
edd16368 SC |
4651 | return err; |
4652 | } | |
4653 | ||
6f039790 | 4654 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
4655 | { |
4656 | int rc; | |
4657 | ||
4658 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
4659 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
4660 | if (!h->hba_inquiry_data) | |
4661 | return; | |
4662 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
4663 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
4664 | if (rc != 0) { | |
4665 | kfree(h->hba_inquiry_data); | |
4666 | h->hba_inquiry_data = NULL; | |
4667 | } | |
4668 | } | |
4669 | ||
6f039790 | 4670 | static int hpsa_init_reset_devices(struct pci_dev *pdev) |
4c2a8c40 | 4671 | { |
1df8552a | 4672 | int rc, i; |
4c2a8c40 SC |
4673 | |
4674 | if (!reset_devices) | |
4675 | return 0; | |
4676 | ||
1df8552a SC |
4677 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
4678 | rc = hpsa_kdump_hard_reset_controller(pdev); | |
4c2a8c40 | 4679 | |
1df8552a SC |
4680 | /* -ENOTSUPP here means we cannot reset the controller |
4681 | * but it's already (and still) up and running in | |
18867659 SC |
4682 | * "performant mode". Or, it might be 640x, which can't reset |
4683 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a SC |
4684 | */ |
4685 | if (rc == -ENOTSUPP) | |
64670ac8 | 4686 | return rc; /* just try to do the kdump anyhow. */ |
1df8552a SC |
4687 | if (rc) |
4688 | return -ENODEV; | |
4c2a8c40 SC |
4689 | |
4690 | /* Now try to get the controller to respond to a no-op */ | |
2b870cb3 | 4691 | dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
4692 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
4693 | if (hpsa_noop(pdev) == 0) | |
4694 | break; | |
4695 | else | |
4696 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
4697 | (i < 11 ? "; re-trying" : "")); | |
4698 | } | |
4699 | return 0; | |
4700 | } | |
4701 | ||
6f039790 | 4702 | static int hpsa_allocate_cmd_pool(struct ctlr_info *h) |
2e9d1b36 SC |
4703 | { |
4704 | h->cmd_pool_bits = kzalloc( | |
4705 | DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * | |
4706 | sizeof(unsigned long), GFP_KERNEL); | |
4707 | h->cmd_pool = pci_alloc_consistent(h->pdev, | |
4708 | h->nr_cmds * sizeof(*h->cmd_pool), | |
4709 | &(h->cmd_pool_dhandle)); | |
4710 | h->errinfo_pool = pci_alloc_consistent(h->pdev, | |
4711 | h->nr_cmds * sizeof(*h->errinfo_pool), | |
4712 | &(h->errinfo_pool_dhandle)); | |
4713 | if ((h->cmd_pool_bits == NULL) | |
4714 | || (h->cmd_pool == NULL) | |
4715 | || (h->errinfo_pool == NULL)) { | |
4716 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
4717 | return -ENOMEM; | |
4718 | } | |
4719 | return 0; | |
4720 | } | |
4721 | ||
4722 | static void hpsa_free_cmd_pool(struct ctlr_info *h) | |
4723 | { | |
4724 | kfree(h->cmd_pool_bits); | |
4725 | if (h->cmd_pool) | |
4726 | pci_free_consistent(h->pdev, | |
4727 | h->nr_cmds * sizeof(struct CommandList), | |
4728 | h->cmd_pool, h->cmd_pool_dhandle); | |
4729 | if (h->errinfo_pool) | |
4730 | pci_free_consistent(h->pdev, | |
4731 | h->nr_cmds * sizeof(struct ErrorInfo), | |
4732 | h->errinfo_pool, | |
4733 | h->errinfo_pool_dhandle); | |
e1f7de0c MG |
4734 | if (h->ioaccel_cmd_pool) |
4735 | pci_free_consistent(h->pdev, | |
4736 | h->nr_cmds * sizeof(struct io_accel1_cmd), | |
4737 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
2e9d1b36 SC |
4738 | } |
4739 | ||
0ae01a32 SC |
4740 | static int hpsa_request_irq(struct ctlr_info *h, |
4741 | irqreturn_t (*msixhandler)(int, void *), | |
4742 | irqreturn_t (*intxhandler)(int, void *)) | |
4743 | { | |
254f796b | 4744 | int rc, i; |
0ae01a32 | 4745 | |
254f796b MG |
4746 | /* |
4747 | * initialize h->q[x] = x so that interrupt handlers know which | |
4748 | * queue to process. | |
4749 | */ | |
4750 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
4751 | h->q[i] = (u8) i; | |
4752 | ||
eee0f03a | 4753 | if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) { |
254f796b | 4754 | /* If performant mode and MSI-X, use multiple reply queues */ |
eee0f03a | 4755 | for (i = 0; i < h->msix_vector; i++) |
254f796b MG |
4756 | rc = request_irq(h->intr[i], msixhandler, |
4757 | 0, h->devname, | |
4758 | &h->q[i]); | |
4759 | } else { | |
4760 | /* Use single reply pool */ | |
eee0f03a | 4761 | if (h->msix_vector > 0 || h->msi_vector) { |
254f796b MG |
4762 | rc = request_irq(h->intr[h->intr_mode], |
4763 | msixhandler, 0, h->devname, | |
4764 | &h->q[h->intr_mode]); | |
4765 | } else { | |
4766 | rc = request_irq(h->intr[h->intr_mode], | |
4767 | intxhandler, IRQF_SHARED, h->devname, | |
4768 | &h->q[h->intr_mode]); | |
4769 | } | |
4770 | } | |
0ae01a32 SC |
4771 | if (rc) { |
4772 | dev_err(&h->pdev->dev, "unable to get irq %d for %s\n", | |
4773 | h->intr[h->intr_mode], h->devname); | |
4774 | return -ENODEV; | |
4775 | } | |
4776 | return 0; | |
4777 | } | |
4778 | ||
6f039790 | 4779 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 SC |
4780 | { |
4781 | if (hpsa_send_host_reset(h, RAID_CTLR_LUNID, | |
4782 | HPSA_RESET_TYPE_CONTROLLER)) { | |
4783 | dev_warn(&h->pdev->dev, "Resetting array controller failed.\n"); | |
4784 | return -EIO; | |
4785 | } | |
4786 | ||
4787 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
4788 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) { | |
4789 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); | |
4790 | return -1; | |
4791 | } | |
4792 | ||
4793 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
4794 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) { | |
4795 | dev_warn(&h->pdev->dev, "Board failed to become ready " | |
4796 | "after soft reset.\n"); | |
4797 | return -1; | |
4798 | } | |
4799 | ||
4800 | return 0; | |
4801 | } | |
4802 | ||
254f796b MG |
4803 | static void free_irqs(struct ctlr_info *h) |
4804 | { | |
4805 | int i; | |
4806 | ||
4807 | if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) { | |
4808 | /* Single reply queue, only one irq to free */ | |
4809 | i = h->intr_mode; | |
4810 | free_irq(h->intr[i], &h->q[i]); | |
4811 | return; | |
4812 | } | |
4813 | ||
eee0f03a | 4814 | for (i = 0; i < h->msix_vector; i++) |
254f796b MG |
4815 | free_irq(h->intr[i], &h->q[i]); |
4816 | } | |
4817 | ||
0097f0f4 | 4818 | static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h) |
64670ac8 | 4819 | { |
254f796b | 4820 | free_irqs(h); |
64670ac8 | 4821 | #ifdef CONFIG_PCI_MSI |
0097f0f4 SC |
4822 | if (h->msix_vector) { |
4823 | if (h->pdev->msix_enabled) | |
4824 | pci_disable_msix(h->pdev); | |
4825 | } else if (h->msi_vector) { | |
4826 | if (h->pdev->msi_enabled) | |
4827 | pci_disable_msi(h->pdev); | |
4828 | } | |
64670ac8 | 4829 | #endif /* CONFIG_PCI_MSI */ |
0097f0f4 SC |
4830 | } |
4831 | ||
4832 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) | |
4833 | { | |
4834 | hpsa_free_irqs_and_disable_msix(h); | |
64670ac8 SC |
4835 | hpsa_free_sg_chain_blocks(h); |
4836 | hpsa_free_cmd_pool(h); | |
e1f7de0c | 4837 | kfree(h->ioaccel1_blockFetchTable); |
64670ac8 SC |
4838 | kfree(h->blockFetchTable); |
4839 | pci_free_consistent(h->pdev, h->reply_pool_size, | |
4840 | h->reply_pool, h->reply_pool_dhandle); | |
4841 | if (h->vaddr) | |
4842 | iounmap(h->vaddr); | |
4843 | if (h->transtable) | |
4844 | iounmap(h->transtable); | |
4845 | if (h->cfgtable) | |
4846 | iounmap(h->cfgtable); | |
4847 | pci_release_regions(h->pdev); | |
4848 | kfree(h); | |
4849 | } | |
4850 | ||
a0c12413 SC |
4851 | /* Called when controller lockup detected. */ |
4852 | static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list) | |
4853 | { | |
4854 | struct CommandList *c = NULL; | |
4855 | ||
4856 | assert_spin_locked(&h->lock); | |
4857 | /* Mark all outstanding commands as failed and complete them. */ | |
4858 | while (!list_empty(list)) { | |
4859 | c = list_entry(list->next, struct CommandList, list); | |
4860 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; | |
5a3d16f5 | 4861 | finish_cmd(c); |
a0c12413 SC |
4862 | } |
4863 | } | |
4864 | ||
4865 | static void controller_lockup_detected(struct ctlr_info *h) | |
4866 | { | |
4867 | unsigned long flags; | |
4868 | ||
a0c12413 SC |
4869 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
4870 | spin_lock_irqsave(&h->lock, flags); | |
4871 | h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); | |
4872 | spin_unlock_irqrestore(&h->lock, flags); | |
4873 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n", | |
4874 | h->lockup_detected); | |
4875 | pci_disable_device(h->pdev); | |
4876 | spin_lock_irqsave(&h->lock, flags); | |
4877 | fail_all_cmds_on_list(h, &h->cmpQ); | |
4878 | fail_all_cmds_on_list(h, &h->reqQ); | |
4879 | spin_unlock_irqrestore(&h->lock, flags); | |
4880 | } | |
4881 | ||
a0c12413 SC |
4882 | static void detect_controller_lockup(struct ctlr_info *h) |
4883 | { | |
4884 | u64 now; | |
4885 | u32 heartbeat; | |
4886 | unsigned long flags; | |
4887 | ||
a0c12413 SC |
4888 | now = get_jiffies_64(); |
4889 | /* If we've received an interrupt recently, we're ok. */ | |
4890 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 4891 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
4892 | return; |
4893 | ||
4894 | /* | |
4895 | * If we've already checked the heartbeat recently, we're ok. | |
4896 | * This could happen if someone sends us a signal. We | |
4897 | * otherwise don't care about signals in this thread. | |
4898 | */ | |
4899 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 4900 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
4901 | return; |
4902 | ||
4903 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
4904 | spin_lock_irqsave(&h->lock, flags); | |
4905 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
4906 | spin_unlock_irqrestore(&h->lock, flags); | |
4907 | if (h->last_heartbeat == heartbeat) { | |
4908 | controller_lockup_detected(h); | |
4909 | return; | |
4910 | } | |
4911 | ||
4912 | /* We're ok. */ | |
4913 | h->last_heartbeat = heartbeat; | |
4914 | h->last_heartbeat_timestamp = now; | |
4915 | } | |
4916 | ||
8a98db73 | 4917 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) |
a0c12413 SC |
4918 | { |
4919 | unsigned long flags; | |
8a98db73 SC |
4920 | struct ctlr_info *h = container_of(to_delayed_work(work), |
4921 | struct ctlr_info, monitor_ctlr_work); | |
4922 | detect_controller_lockup(h); | |
4923 | if (h->lockup_detected) | |
4924 | return; | |
4925 | spin_lock_irqsave(&h->lock, flags); | |
4926 | if (h->remove_in_progress) { | |
4927 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
4928 | return; |
4929 | } | |
8a98db73 SC |
4930 | schedule_delayed_work(&h->monitor_ctlr_work, |
4931 | h->heartbeat_sample_interval); | |
4932 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
4933 | } |
4934 | ||
6f039790 | 4935 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 4936 | { |
4c2a8c40 | 4937 | int dac, rc; |
edd16368 | 4938 | struct ctlr_info *h; |
64670ac8 SC |
4939 | int try_soft_reset = 0; |
4940 | unsigned long flags; | |
edd16368 SC |
4941 | |
4942 | if (number_of_controllers == 0) | |
4943 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 4944 | |
4c2a8c40 | 4945 | rc = hpsa_init_reset_devices(pdev); |
64670ac8 SC |
4946 | if (rc) { |
4947 | if (rc != -ENOTSUPP) | |
4948 | return rc; | |
4949 | /* If the reset fails in a particular way (it has no way to do | |
4950 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
4951 | * a soft reset once we get the controller configured up to the | |
4952 | * point that it can accept a command. | |
4953 | */ | |
4954 | try_soft_reset = 1; | |
4955 | rc = 0; | |
4956 | } | |
4957 | ||
4958 | reinit_after_soft_reset: | |
edd16368 | 4959 | |
303932fd DB |
4960 | /* Command structures must be aligned on a 32-byte boundary because |
4961 | * the 5 lower bits of the address are used by the hardware. and by | |
4962 | * the driver. See comments in hpsa.h for more info. | |
4963 | */ | |
4964 | #define COMMANDLIST_ALIGNMENT 32 | |
4965 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); | |
edd16368 SC |
4966 | h = kzalloc(sizeof(*h), GFP_KERNEL); |
4967 | if (!h) | |
ecd9aad4 | 4968 | return -ENOMEM; |
edd16368 | 4969 | |
55c06c71 | 4970 | h->pdev = pdev; |
a9a3a273 | 4971 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9e0fc764 SC |
4972 | INIT_LIST_HEAD(&h->cmpQ); |
4973 | INIT_LIST_HEAD(&h->reqQ); | |
6eaf46fd SC |
4974 | spin_lock_init(&h->lock); |
4975 | spin_lock_init(&h->scan_lock); | |
0390f0c0 | 4976 | spin_lock_init(&h->passthru_count_lock); |
55c06c71 | 4977 | rc = hpsa_pci_init(h); |
ecd9aad4 | 4978 | if (rc != 0) |
edd16368 SC |
4979 | goto clean1; |
4980 | ||
f79cfec6 | 4981 | sprintf(h->devname, HPSA "%d", number_of_controllers); |
edd16368 SC |
4982 | h->ctlr = number_of_controllers; |
4983 | number_of_controllers++; | |
edd16368 SC |
4984 | |
4985 | /* configure PCI DMA stuff */ | |
ecd9aad4 SC |
4986 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
4987 | if (rc == 0) { | |
edd16368 | 4988 | dac = 1; |
ecd9aad4 SC |
4989 | } else { |
4990 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
4991 | if (rc == 0) { | |
4992 | dac = 0; | |
4993 | } else { | |
4994 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
4995 | goto clean1; | |
4996 | } | |
edd16368 SC |
4997 | } |
4998 | ||
4999 | /* make sure the board interrupts are off */ | |
5000 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 5001 | |
0ae01a32 | 5002 | if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx)) |
edd16368 | 5003 | goto clean2; |
303932fd DB |
5004 | dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n", |
5005 | h->devname, pdev->device, | |
a9a3a273 | 5006 | h->intr[h->intr_mode], dac ? "" : " not"); |
2e9d1b36 | 5007 | if (hpsa_allocate_cmd_pool(h)) |
edd16368 | 5008 | goto clean4; |
33a2ffce SC |
5009 | if (hpsa_allocate_sg_chain_blocks(h)) |
5010 | goto clean4; | |
a08a8471 SC |
5011 | init_waitqueue_head(&h->scan_wait_queue); |
5012 | h->scan_finished = 1; /* no scan currently in progress */ | |
edd16368 SC |
5013 | |
5014 | pci_set_drvdata(pdev, h); | |
9a41338e SC |
5015 | h->ndevices = 0; |
5016 | h->scsi_host = NULL; | |
5017 | spin_lock_init(&h->devlock); | |
64670ac8 SC |
5018 | hpsa_put_ctlr_into_performant_mode(h); |
5019 | ||
5020 | /* At this point, the controller is ready to take commands. | |
5021 | * Now, if reset_devices and the hard reset didn't work, try | |
5022 | * the soft reset and see if that works. | |
5023 | */ | |
5024 | if (try_soft_reset) { | |
5025 | ||
5026 | /* This is kind of gross. We may or may not get a completion | |
5027 | * from the soft reset command, and if we do, then the value | |
5028 | * from the fifo may or may not be valid. So, we wait 10 secs | |
5029 | * after the reset throwing away any completions we get during | |
5030 | * that time. Unregister the interrupt handler and register | |
5031 | * fake ones to scoop up any residual completions. | |
5032 | */ | |
5033 | spin_lock_irqsave(&h->lock, flags); | |
5034 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
5035 | spin_unlock_irqrestore(&h->lock, flags); | |
254f796b | 5036 | free_irqs(h); |
64670ac8 SC |
5037 | rc = hpsa_request_irq(h, hpsa_msix_discard_completions, |
5038 | hpsa_intx_discard_completions); | |
5039 | if (rc) { | |
5040 | dev_warn(&h->pdev->dev, "Failed to request_irq after " | |
5041 | "soft reset.\n"); | |
5042 | goto clean4; | |
5043 | } | |
5044 | ||
5045 | rc = hpsa_kdump_soft_reset(h); | |
5046 | if (rc) | |
5047 | /* Neither hard nor soft reset worked, we're hosed. */ | |
5048 | goto clean4; | |
5049 | ||
5050 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
5051 | dev_info(&h->pdev->dev, | |
5052 | "Waiting for stale completions to drain.\n"); | |
5053 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
5054 | msleep(10000); | |
5055 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
5056 | ||
5057 | rc = controller_reset_failed(h->cfgtable); | |
5058 | if (rc) | |
5059 | dev_info(&h->pdev->dev, | |
5060 | "Soft reset appears to have failed.\n"); | |
5061 | ||
5062 | /* since the controller's reset, we have to go back and re-init | |
5063 | * everything. Easiest to just forget what we've done and do it | |
5064 | * all over again. | |
5065 | */ | |
5066 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
5067 | try_soft_reset = 0; | |
5068 | if (rc) | |
5069 | /* don't go to clean4, we already unallocated */ | |
5070 | return -ENODEV; | |
5071 | ||
5072 | goto reinit_after_soft_reset; | |
5073 | } | |
edd16368 SC |
5074 | |
5075 | /* Turn the interrupts on so we can service requests */ | |
5076 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
5077 | ||
339b2b14 | 5078 | hpsa_hba_inquiry(h); |
edd16368 | 5079 | hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */ |
8a98db73 SC |
5080 | |
5081 | /* Monitor the controller for firmware lockups */ | |
5082 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
5083 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
5084 | schedule_delayed_work(&h->monitor_ctlr_work, | |
5085 | h->heartbeat_sample_interval); | |
88bf6d62 | 5086 | return 0; |
edd16368 SC |
5087 | |
5088 | clean4: | |
33a2ffce | 5089 | hpsa_free_sg_chain_blocks(h); |
2e9d1b36 | 5090 | hpsa_free_cmd_pool(h); |
254f796b | 5091 | free_irqs(h); |
edd16368 SC |
5092 | clean2: |
5093 | clean1: | |
edd16368 | 5094 | kfree(h); |
ecd9aad4 | 5095 | return rc; |
edd16368 SC |
5096 | } |
5097 | ||
5098 | static void hpsa_flush_cache(struct ctlr_info *h) | |
5099 | { | |
5100 | char *flush_buf; | |
5101 | struct CommandList *c; | |
702890e3 SC |
5102 | unsigned long flags; |
5103 | ||
5104 | /* Don't bother trying to flush the cache if locked up */ | |
5105 | spin_lock_irqsave(&h->lock, flags); | |
5106 | if (unlikely(h->lockup_detected)) { | |
5107 | spin_unlock_irqrestore(&h->lock, flags); | |
5108 | return; | |
5109 | } | |
5110 | spin_unlock_irqrestore(&h->lock, flags); | |
edd16368 SC |
5111 | |
5112 | flush_buf = kzalloc(4, GFP_KERNEL); | |
5113 | if (!flush_buf) | |
5114 | return; | |
5115 | ||
5116 | c = cmd_special_alloc(h); | |
5117 | if (!c) { | |
5118 | dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n"); | |
5119 | goto out_of_memory; | |
5120 | } | |
a2dac136 SC |
5121 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
5122 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
5123 | goto out; | |
5124 | } | |
edd16368 SC |
5125 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE); |
5126 | if (c->err_info->CommandStatus != 0) | |
a2dac136 | 5127 | out: |
edd16368 SC |
5128 | dev_warn(&h->pdev->dev, |
5129 | "error flushing cache on controller\n"); | |
5130 | cmd_special_free(h, c); | |
5131 | out_of_memory: | |
5132 | kfree(flush_buf); | |
5133 | } | |
5134 | ||
5135 | static void hpsa_shutdown(struct pci_dev *pdev) | |
5136 | { | |
5137 | struct ctlr_info *h; | |
5138 | ||
5139 | h = pci_get_drvdata(pdev); | |
5140 | /* Turn board interrupts off and send the flush cache command | |
5141 | * sendcmd will turn off interrupt, and send the flush... | |
5142 | * To write all data in the battery backed cache to disks | |
5143 | */ | |
5144 | hpsa_flush_cache(h); | |
5145 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
0097f0f4 | 5146 | hpsa_free_irqs_and_disable_msix(h); |
edd16368 SC |
5147 | } |
5148 | ||
6f039790 | 5149 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
5150 | { |
5151 | int i; | |
5152 | ||
5153 | for (i = 0; i < h->ndevices; i++) | |
5154 | kfree(h->dev[i]); | |
5155 | } | |
5156 | ||
6f039790 | 5157 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
5158 | { |
5159 | struct ctlr_info *h; | |
8a98db73 | 5160 | unsigned long flags; |
edd16368 SC |
5161 | |
5162 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 5163 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
5164 | return; |
5165 | } | |
5166 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
5167 | |
5168 | /* Get rid of any controller monitoring work items */ | |
5169 | spin_lock_irqsave(&h->lock, flags); | |
5170 | h->remove_in_progress = 1; | |
5171 | cancel_delayed_work(&h->monitor_ctlr_work); | |
5172 | spin_unlock_irqrestore(&h->lock, flags); | |
5173 | ||
edd16368 SC |
5174 | hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */ |
5175 | hpsa_shutdown(pdev); | |
5176 | iounmap(h->vaddr); | |
204892e9 SC |
5177 | iounmap(h->transtable); |
5178 | iounmap(h->cfgtable); | |
55e14e76 | 5179 | hpsa_free_device_info(h); |
33a2ffce | 5180 | hpsa_free_sg_chain_blocks(h); |
edd16368 SC |
5181 | pci_free_consistent(h->pdev, |
5182 | h->nr_cmds * sizeof(struct CommandList), | |
5183 | h->cmd_pool, h->cmd_pool_dhandle); | |
5184 | pci_free_consistent(h->pdev, | |
5185 | h->nr_cmds * sizeof(struct ErrorInfo), | |
5186 | h->errinfo_pool, h->errinfo_pool_dhandle); | |
303932fd DB |
5187 | pci_free_consistent(h->pdev, h->reply_pool_size, |
5188 | h->reply_pool, h->reply_pool_dhandle); | |
edd16368 | 5189 | kfree(h->cmd_pool_bits); |
303932fd | 5190 | kfree(h->blockFetchTable); |
e1f7de0c | 5191 | kfree(h->ioaccel1_blockFetchTable); |
339b2b14 | 5192 | kfree(h->hba_inquiry_data); |
f0bd0b68 | 5193 | pci_disable_device(pdev); |
edd16368 | 5194 | pci_release_regions(pdev); |
edd16368 SC |
5195 | kfree(h); |
5196 | } | |
5197 | ||
5198 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
5199 | __attribute__((unused)) pm_message_t state) | |
5200 | { | |
5201 | return -ENOSYS; | |
5202 | } | |
5203 | ||
5204 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
5205 | { | |
5206 | return -ENOSYS; | |
5207 | } | |
5208 | ||
5209 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 5210 | .name = HPSA, |
edd16368 | 5211 | .probe = hpsa_init_one, |
6f039790 | 5212 | .remove = hpsa_remove_one, |
edd16368 SC |
5213 | .id_table = hpsa_pci_device_id, /* id_table */ |
5214 | .shutdown = hpsa_shutdown, | |
5215 | .suspend = hpsa_suspend, | |
5216 | .resume = hpsa_resume, | |
5217 | }; | |
5218 | ||
303932fd DB |
5219 | /* Fill in bucket_map[], given nsgs (the max number of |
5220 | * scatter gather elements supported) and bucket[], | |
5221 | * which is an array of 8 integers. The bucket[] array | |
5222 | * contains 8 different DMA transfer sizes (in 16 | |
5223 | * byte increments) which the controller uses to fetch | |
5224 | * commands. This function fills in bucket_map[], which | |
5225 | * maps a given number of scatter gather elements to one of | |
5226 | * the 8 DMA transfer sizes. The point of it is to allow the | |
5227 | * controller to only do as much DMA as needed to fetch the | |
5228 | * command, with the DMA transfer size encoded in the lower | |
5229 | * bits of the command address. | |
5230 | */ | |
5231 | static void calc_bucket_map(int bucket[], int num_buckets, | |
e1f7de0c | 5232 | int nsgs, int min_blocks, int *bucket_map) |
303932fd DB |
5233 | { |
5234 | int i, j, b, size; | |
5235 | ||
303932fd DB |
5236 | /* Note, bucket_map must have nsgs+1 entries. */ |
5237 | for (i = 0; i <= nsgs; i++) { | |
5238 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 5239 | size = i + min_blocks; |
303932fd DB |
5240 | b = num_buckets; /* Assume the biggest bucket */ |
5241 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 5242 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
5243 | if (bucket[j] >= size) { |
5244 | b = j; | |
5245 | break; | |
5246 | } | |
5247 | } | |
5248 | /* for a command with i SG entries, use bucket b. */ | |
5249 | bucket_map[i] = b; | |
5250 | } | |
5251 | } | |
5252 | ||
e1f7de0c | 5253 | static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 5254 | { |
6c311b57 SC |
5255 | int i; |
5256 | unsigned long register_value; | |
e1f7de0c MG |
5257 | unsigned long transMethod = CFGTBL_Trans_Performant | |
5258 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
5259 | CFGTBL_Trans_enable_directed_msix | | |
5260 | (trans_support & CFGTBL_Trans_io_accel1); | |
5261 | ||
5262 | struct access_method access = SA5_performant_access; | |
def342bd SC |
5263 | |
5264 | /* This is a bit complicated. There are 8 registers on | |
5265 | * the controller which we write to to tell it 8 different | |
5266 | * sizes of commands which there may be. It's a way of | |
5267 | * reducing the DMA done to fetch each command. Encoded into | |
5268 | * each command's tag are 3 bits which communicate to the controller | |
5269 | * which of the eight sizes that command fits within. The size of | |
5270 | * each command depends on how many scatter gather entries there are. | |
5271 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
5272 | * with the number of 16-byte blocks a command of that size requires. | |
5273 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 5274 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
5275 | * blocks. Note, this only extends to the SG entries contained |
5276 | * within the command block, and does not extend to chained blocks | |
5277 | * of SG elements. bft[] contains the eight values we write to | |
5278 | * the registers. They are not evenly distributed, but have more | |
5279 | * sizes for small commands, and fewer sizes for larger commands. | |
5280 | */ | |
d66ae08b SC |
5281 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
5282 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); | |
303932fd DB |
5283 | /* 5 = 1 s/g entry or 4k |
5284 | * 6 = 2 s/g entry or 8k | |
5285 | * 8 = 4 s/g entry or 16k | |
5286 | * 10 = 6 s/g entry or 24k | |
5287 | */ | |
303932fd | 5288 | |
303932fd DB |
5289 | /* Controller spec: zero out this buffer. */ |
5290 | memset(h->reply_pool, 0, h->reply_pool_size); | |
303932fd | 5291 | |
d66ae08b SC |
5292 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
5293 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 5294 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
5295 | for (i = 0; i < 8; i++) |
5296 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
5297 | ||
5298 | /* size of controller ring buffer */ | |
5299 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 5300 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
5301 | writel(0, &h->transtable->RepQCtrAddrLow32); |
5302 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
5303 | |
5304 | for (i = 0; i < h->nreply_queues; i++) { | |
5305 | writel(0, &h->transtable->RepQAddr[i].upper); | |
5306 | writel(h->reply_pool_dhandle + | |
5307 | (h->max_commands * sizeof(u64) * i), | |
5308 | &h->transtable->RepQAddr[i].lower); | |
5309 | } | |
5310 | ||
e1f7de0c MG |
5311 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
5312 | /* | |
5313 | * enable outbound interrupt coalescing in accelerator mode; | |
5314 | */ | |
5315 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
5316 | access = SA5_ioaccel_mode1_access; | |
5317 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
5318 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
5319 | } | |
303932fd | 5320 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
3f4336f3 | 5321 | hpsa_wait_for_mode_change_ack(h); |
303932fd DB |
5322 | register_value = readl(&(h->cfgtable->TransportActive)); |
5323 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
5324 | dev_warn(&h->pdev->dev, "unable to get board into" | |
5325 | " performant mode\n"); | |
5326 | return; | |
5327 | } | |
960a30e7 | 5328 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
5329 | h->access = access; |
5330 | h->transMethod = transMethod; | |
5331 | ||
5332 | if (!(trans_support & CFGTBL_Trans_io_accel1)) | |
5333 | return; | |
5334 | ||
5335 | /* Set up I/O accelerator mode */ | |
5336 | for (i = 0; i < h->nreply_queues; i++) { | |
5337 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
5338 | h->reply_queue[i].current_entry = | |
5339 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
5340 | } | |
5341 | bft[7] = IOACCEL1_MAXSGENTRIES + 8; | |
5342 | calc_bucket_map(bft, ARRAY_SIZE(bft), IOACCEL1_MAXSGENTRIES, 8, | |
5343 | h->ioaccel1_blockFetchTable); | |
5344 | ||
5345 | /* initialize all reply queue entries to unused */ | |
5346 | memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
5347 | h->reply_pool_size); | |
5348 | ||
5349 | /* set all the constant fields in the accelerator command | |
5350 | * frames once at init time to save CPU cycles later. | |
5351 | */ | |
5352 | for (i = 0; i < h->nr_cmds; i++) { | |
5353 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
5354 | ||
5355 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
5356 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
5357 | (i * sizeof(struct ErrorInfo))); | |
5358 | cp->err_info_len = sizeof(struct ErrorInfo); | |
5359 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
5360 | cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT; | |
5361 | cp->timeout_sec = 0; | |
5362 | cp->ReplyQueue = 0; | |
5363 | cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) | DIRECT_LOOKUP_BIT; | |
5364 | cp->Tag.upper = 0; | |
5365 | cp->host_addr.lower = (u32) (h->ioaccel_cmd_pool_dhandle + | |
5366 | (i * sizeof(struct io_accel1_cmd))); | |
5367 | cp->host_addr.upper = 0; | |
5368 | } | |
5369 | } | |
5370 | ||
5371 | static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h) | |
5372 | { | |
5373 | /* Command structures must be aligned on a 128-byte boundary | |
5374 | * because the 7 lower bits of the address are used by the | |
5375 | * hardware. | |
5376 | */ | |
5377 | #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 | |
5378 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % | |
5379 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
5380 | h->ioaccel_cmd_pool = | |
5381 | pci_alloc_consistent(h->pdev, | |
5382 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
5383 | &(h->ioaccel_cmd_pool_dhandle)); | |
5384 | ||
5385 | h->ioaccel1_blockFetchTable = | |
5386 | kmalloc(((IOACCEL1_MAXSGENTRIES + 1) * | |
5387 | sizeof(u32)), GFP_KERNEL); | |
5388 | ||
5389 | if ((h->ioaccel_cmd_pool == NULL) || | |
5390 | (h->ioaccel1_blockFetchTable == NULL)) | |
5391 | goto clean_up; | |
5392 | ||
5393 | memset(h->ioaccel_cmd_pool, 0, | |
5394 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
5395 | return 0; | |
5396 | ||
5397 | clean_up: | |
5398 | if (h->ioaccel_cmd_pool) | |
5399 | pci_free_consistent(h->pdev, | |
5400 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
5401 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
5402 | kfree(h->ioaccel1_blockFetchTable); | |
5403 | return 1; | |
6c311b57 SC |
5404 | } |
5405 | ||
6f039790 | 5406 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) |
6c311b57 SC |
5407 | { |
5408 | u32 trans_support; | |
e1f7de0c MG |
5409 | unsigned long transMethod = CFGTBL_Trans_Performant | |
5410 | CFGTBL_Trans_use_short_tags; | |
254f796b | 5411 | int i; |
6c311b57 | 5412 | |
02ec19c8 SC |
5413 | if (hpsa_simple_mode) |
5414 | return; | |
5415 | ||
e1f7de0c MG |
5416 | /* Check for I/O accelerator mode support */ |
5417 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
5418 | transMethod |= CFGTBL_Trans_io_accel1 | | |
5419 | CFGTBL_Trans_enable_directed_msix; | |
5420 | if (hpsa_alloc_ioaccel_cmd_and_bft(h)) | |
5421 | goto clean_up; | |
5422 | } | |
5423 | ||
5424 | /* TODO, check that this next line h->nreply_queues is correct */ | |
6c311b57 SC |
5425 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
5426 | if (!(trans_support & PERFORMANT_MODE)) | |
5427 | return; | |
5428 | ||
eee0f03a | 5429 | h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1; |
cba3d38b | 5430 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 5431 | /* Performant mode ring buffer and supporting data structures */ |
254f796b | 5432 | h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues; |
6c311b57 SC |
5433 | h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size, |
5434 | &(h->reply_pool_dhandle)); | |
5435 | ||
254f796b MG |
5436 | for (i = 0; i < h->nreply_queues; i++) { |
5437 | h->reply_queue[i].head = &h->reply_pool[h->max_commands * i]; | |
5438 | h->reply_queue[i].size = h->max_commands; | |
5439 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
5440 | h->reply_queue[i].current_entry = 0; | |
5441 | } | |
5442 | ||
6c311b57 | 5443 | /* Need a block fetch table for performant mode */ |
d66ae08b | 5444 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 SC |
5445 | sizeof(u32)), GFP_KERNEL); |
5446 | ||
5447 | if ((h->reply_pool == NULL) | |
5448 | || (h->blockFetchTable == NULL)) | |
5449 | goto clean_up; | |
5450 | ||
e1f7de0c | 5451 | hpsa_enter_performant_mode(h, trans_support); |
303932fd DB |
5452 | return; |
5453 | ||
5454 | clean_up: | |
5455 | if (h->reply_pool) | |
5456 | pci_free_consistent(h->pdev, h->reply_pool_size, | |
5457 | h->reply_pool, h->reply_pool_dhandle); | |
5458 | kfree(h->blockFetchTable); | |
5459 | } | |
5460 | ||
edd16368 SC |
5461 | /* |
5462 | * This is it. Register the PCI driver information for the cards we control | |
5463 | * the OS will call our registered routines when it finds one of our cards. | |
5464 | */ | |
5465 | static int __init hpsa_init(void) | |
5466 | { | |
31468401 | 5467 | return pci_register_driver(&hpsa_pci_driver); |
edd16368 SC |
5468 | } |
5469 | ||
5470 | static void __exit hpsa_cleanup(void) | |
5471 | { | |
5472 | pci_unregister_driver(&hpsa_pci_driver); | |
edd16368 SC |
5473 | } |
5474 | ||
e1f7de0c MG |
5475 | static void __attribute__((unused)) verify_offsets(void) |
5476 | { | |
5477 | #define VERIFY_OFFSET(member, offset) \ | |
5478 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
5479 | ||
5480 | VERIFY_OFFSET(dev_handle, 0x00); | |
5481 | VERIFY_OFFSET(reserved1, 0x02); | |
5482 | VERIFY_OFFSET(function, 0x03); | |
5483 | VERIFY_OFFSET(reserved2, 0x04); | |
5484 | VERIFY_OFFSET(err_info, 0x0C); | |
5485 | VERIFY_OFFSET(reserved3, 0x10); | |
5486 | VERIFY_OFFSET(err_info_len, 0x12); | |
5487 | VERIFY_OFFSET(reserved4, 0x13); | |
5488 | VERIFY_OFFSET(sgl_offset, 0x14); | |
5489 | VERIFY_OFFSET(reserved5, 0x15); | |
5490 | VERIFY_OFFSET(transfer_len, 0x1C); | |
5491 | VERIFY_OFFSET(reserved6, 0x20); | |
5492 | VERIFY_OFFSET(io_flags, 0x24); | |
5493 | VERIFY_OFFSET(reserved7, 0x26); | |
5494 | VERIFY_OFFSET(LUN, 0x34); | |
5495 | VERIFY_OFFSET(control, 0x3C); | |
5496 | VERIFY_OFFSET(CDB, 0x40); | |
5497 | VERIFY_OFFSET(reserved8, 0x50); | |
5498 | VERIFY_OFFSET(host_context_flags, 0x60); | |
5499 | VERIFY_OFFSET(timeout_sec, 0x62); | |
5500 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
5501 | VERIFY_OFFSET(reserved9, 0x65); | |
5502 | VERIFY_OFFSET(Tag, 0x68); | |
5503 | VERIFY_OFFSET(host_addr, 0x70); | |
5504 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
5505 | VERIFY_OFFSET(SG, 0x78 + 8); | |
5506 | #undef VERIFY_OFFSET | |
5507 | } | |
5508 | ||
edd16368 SC |
5509 | module_init(hpsa_init); |
5510 | module_exit(hpsa_cleanup); |