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hpsa: refactor freeing of resources into more logical functions
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
59/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 60#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 61#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 62#define HPSA "hpsa"
edd16368 63
007e7aa9
RE		 64/* How long to wait for CISS doorbell communication */
65#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
66#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
67#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
68#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 69#define MAX_IOCTL_CONFIG_WAIT 1000
70
71/*define how many times we will try a command because of bus resets */
72#define MAX_CMD_RETRIES 3
73
74/* Embedded module documentation macros - see modules.h */
75MODULE_AUTHOR("Hewlett-Packard Company");
76MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
77 HPSA_DRIVER_VERSION);
78MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
79MODULE_VERSION(HPSA_DRIVER_VERSION);
80MODULE_LICENSE("GPL");
81
82static int hpsa_allow_any;
83module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_allow_any,
85 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 86static int hpsa_simple_mode;
87module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
88MODULE_PARM_DESC(hpsa_simple_mode,
89 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 90
91/* define the PCI info for the cards we can control */
92static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 133 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
137 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 138 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 139 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 140 {0,}
141};
142
143MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
144
145/* board_id = Subsystem Device ID & Vendor ID
146 * product = Marketing Name for the board
147 * access = Address of the struct of function pointers
148 */
149static struct board_type products[] = {
edd16368
SC		 150 {0x3241103C, "Smart Array P212", &SA5_access},
151 {0x3243103C, "Smart Array P410", &SA5_access},
152 {0x3245103C, "Smart Array P410i", &SA5_access},
153 {0x3247103C, "Smart Array P411", &SA5_access},
154 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 155 {0x324A103C, "Smart Array P712m", &SA5_access},
156 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 157 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 158 {0x3350103C, "Smart Array P222", &SA5_access},
159 {0x3351103C, "Smart Array P420", &SA5_access},
160 {0x3352103C, "Smart Array P421", &SA5_access},
161 {0x3353103C, "Smart Array P822", &SA5_access},
162 {0x3354103C, "Smart Array P420i", &SA5_access},
163 {0x3355103C, "Smart Array P220i", &SA5_access},
164 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 165 {0x1921103C, "Smart Array P830i", &SA5_access},
166 {0x1922103C, "Smart Array P430", &SA5_access},
167 {0x1923103C, "Smart Array P431", &SA5_access},
168 {0x1924103C, "Smart Array P830", &SA5_access},
169 {0x1926103C, "Smart Array P731m", &SA5_access},
170 {0x1928103C, "Smart Array P230i", &SA5_access},
171 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 172 {0x21BD103C, "Smart Array P244br", &SA5_access},
173 {0x21BE103C, "Smart Array P741m", &SA5_access},
174 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
175 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 176 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 177 {0x21C2103C, "Smart Array P440", &SA5_access},
178 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 179 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 180 {0x21C5103C, "Smart Array P841", &SA5_access},
181 {0x21C6103C, "Smart HBA H244br", &SA5_access},
182 {0x21C7103C, "Smart HBA H240", &SA5_access},
183 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 184 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 185 {0x21CA103C, "Smart Array P246br", &SA5_access},
186 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 187 {0x21CC103C, "Smart Array", &SA5_access},
188 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 189 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 190 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
191 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
192 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
193 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
194 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 195 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
196};
197
198static int number_of_controllers;
199
10f66018
SC		 200static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
201static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 202static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 203
204#ifdef CONFIG_COMPAT
42a91641
DB		 205static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
206 void __user *arg);
edd16368
SC		 207#endif
208
209static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 210static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 211static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 212 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 213 int cmd_type);
2c143342 214static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 215#define VPD_PAGE (1 << 8)
edd16368 216
f281233d 217static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 218static void hpsa_scan_start(struct Scsi_Host *);
219static int hpsa_scan_finished(struct Scsi_Host *sh,
220 unsigned long elapsed_time);
7c0a0229 221static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 222
223static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 224static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 225static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 226static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 227static void hpsa_slave_destroy(struct scsi_device *sdev);
228
edd16368 229static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 230static int check_for_unit_attention(struct ctlr_info *h,
231 struct CommandList *c);
232static void check_ioctl_unit_attention(struct ctlr_info *h,
233 struct CommandList *c);
303932fd
DB		 234/* performant mode helper functions */
235static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 236 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 237static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
1fb7c98a
RE		 238static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h);
239static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h);
254f796b 240static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 241static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
242 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
243 u64 *cfg_offset);
244static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
245 unsigned long *memory_bar);
246static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
247static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
248 int wait_for_ready);
75167d2c 249static inline void finish_cmd(struct CommandList *c);
c706a795 250static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 251#define BOARD_NOT_READY 0
252#define BOARD_READY 1
23100dd9 253static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 254static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 255static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
256 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 257 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 258static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 259static u32 lockup_detected(struct ctlr_info *h);
260static int detect_controller_lockup(struct ctlr_info *h);
edd16368 261
edd16368
SC		 262static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
263{
264 unsigned long *priv = shost_priv(sdev->host);
265 return (struct ctlr_info *) *priv;
266}
267
a23513e8
SC		 268static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
269{
270 unsigned long *priv = shost_priv(sh);
271 return (struct ctlr_info *) *priv;
272}
273
9437ac43
SC		 274/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
275static void decode_sense_data(const u8 *sense_data, int sense_data_len,
276 u8 *sense_key, u8 *asc, u8 *ascq)
277{
278 struct scsi_sense_hdr sshdr;
279 bool rc;
280
281 *sense_key = -1;
282 *asc = -1;
283 *ascq = -1;
284
285 if (sense_data_len < 1)
286 return;
287
288 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
289 if (rc) {
290 *sense_key = sshdr.sense_key;
291 *asc = sshdr.asc;
292 *ascq = sshdr.ascq;
293 }
294}
295
edd16368
SC		 296static int check_for_unit_attention(struct ctlr_info *h,
297 struct CommandList *c)
298{
9437ac43
SC		 299 u8 sense_key, asc, ascq;
300 int sense_len;
301
302 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
303 sense_len = sizeof(c->err_info->SenseInfo);
304 else
305 sense_len = c->err_info->SenseLen;
306
307 decode_sense_data(c->err_info->SenseInfo, sense_len,
308 &sense_key, &asc, &ascq);
309 if (sense_key != UNIT_ATTENTION || asc == -1)
edd16368
SC		 310 return 0;
311
9437ac43 312 switch (asc) {
edd16368 313 case STATE_CHANGED:
9437ac43
SC		 314 dev_warn(&h->pdev->dev,
315 HPSA "%d: a state change detected, command retried\n",
316 h->ctlr);
edd16368
SC		 317 break;
318 case LUN_FAILED:
7f73695a
SC		 319 dev_warn(&h->pdev->dev,
320 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 321 break;
322 case REPORT_LUNS_CHANGED:
7f73695a
SC		 323 dev_warn(&h->pdev->dev,
324 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 325 /*
4f4eb9f1
ST		 326 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
327 * target (array) devices.
edd16368
SC		 328 */
329 break;
330 case POWER_OR_RESET:
f79cfec6 331 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 332 "or device reset detected\n", h->ctlr);
333 break;
334 case UNIT_ATTENTION_CLEARED:
f79cfec6 335 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 336 "cleared by another initiator\n", h->ctlr);
337 break;
338 default:
f79cfec6 339 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 340 "unit attention detected\n", h->ctlr);
341 break;
342 }
343 return 1;
344}
345
852af20a
MB		 346static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
347{
348 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
349 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
350 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
351 return 0;
352 dev_warn(&h->pdev->dev, HPSA "device busy");
353 return 1;
354}
355
e985c58f
SC		 356static u32 lockup_detected(struct ctlr_info *h);
357static ssize_t host_show_lockup_detected(struct device *dev,
358 struct device_attribute *attr, char *buf)
359{
360 int ld;
361 struct ctlr_info *h;
362 struct Scsi_Host *shost = class_to_shost(dev);
363
364 h = shost_to_hba(shost);
365 ld = lockup_detected(h);
366
367 return sprintf(buf, "ld=%d\n", ld);
368}
369
da0697bd
ST		 370static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
371 struct device_attribute *attr,
372 const char *buf, size_t count)
373{
374 int status, len;
375 struct ctlr_info *h;
376 struct Scsi_Host *shost = class_to_shost(dev);
377 char tmpbuf[10];
378
379 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
380 return -EACCES;
381 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
382 strncpy(tmpbuf, buf, len);
383 tmpbuf[len] = '\0';
384 if (sscanf(tmpbuf, "%d", &status) != 1)
385 return -EINVAL;
386 h = shost_to_hba(shost);
387 h->acciopath_status = !!status;
388 dev_warn(&h->pdev->dev,
389 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
390 h->acciopath_status ? "enabled" : "disabled");
391 return count;
392}
393
2ba8bfc8
SC		 394static ssize_t host_store_raid_offload_debug(struct device *dev,
395 struct device_attribute *attr,
396 const char *buf, size_t count)
397{
398 int debug_level, len;
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401 char tmpbuf[10];
402
403 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
404 return -EACCES;
405 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
406 strncpy(tmpbuf, buf, len);
407 tmpbuf[len] = '\0';
408 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
409 return -EINVAL;
410 if (debug_level < 0)
411 debug_level = 0;
412 h = shost_to_hba(shost);
413 h->raid_offload_debug = debug_level;
414 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
415 h->raid_offload_debug);
416 return count;
417}
418
edd16368
SC		 419static ssize_t host_store_rescan(struct device *dev,
420 struct device_attribute *attr,
421 const char *buf, size_t count)
422{
423 struct ctlr_info *h;
424 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 425 h = shost_to_hba(shost);
31468401 426 hpsa_scan_start(h->scsi_host);
edd16368
SC		 427 return count;
428}
429
d28ce020
SC		 430static ssize_t host_show_firmware_revision(struct device *dev,
431 struct device_attribute *attr, char *buf)
432{
433 struct ctlr_info *h;
434 struct Scsi_Host *shost = class_to_shost(dev);
435 unsigned char *fwrev;
436
437 h = shost_to_hba(shost);
438 if (!h->hba_inquiry_data)
439 return 0;
440 fwrev = &h->hba_inquiry_data[32];
441 return snprintf(buf, 20, "%c%c%c%c\n",
442 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
443}
444
94a13649
SC		 445static ssize_t host_show_commands_outstanding(struct device *dev,
446 struct device_attribute *attr, char *buf)
447{
448 struct Scsi_Host *shost = class_to_shost(dev);
449 struct ctlr_info *h = shost_to_hba(shost);
450
0cbf768e
SC		 451 return snprintf(buf, 20, "%d\n",
452 atomic_read(&h->commands_outstanding));
94a13649
SC		 453}
454
745a7a25
SC		 455static ssize_t host_show_transport_mode(struct device *dev,
456 struct device_attribute *attr, char *buf)
457{
458 struct ctlr_info *h;
459 struct Scsi_Host *shost = class_to_shost(dev);
460
461 h = shost_to_hba(shost);
462 return snprintf(buf, 20, "%s\n",
960a30e7 463 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 464 "performant" : "simple");
465}
466
da0697bd
ST		 467static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
468 struct device_attribute *attr, char *buf)
469{
470 struct ctlr_info *h;
471 struct Scsi_Host *shost = class_to_shost(dev);
472
473 h = shost_to_hba(shost);
474 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
475 (h->acciopath_status == 1) ? "enabled" : "disabled");
476}
477
46380786 478/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 479static u32 unresettable_controller[] = {
480 0x324a103C, /* Smart Array P712m */
9b5c48c2 481 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 482 0x3223103C, /* Smart Array P800 */
483 0x3234103C, /* Smart Array P400 */
484 0x3235103C, /* Smart Array P400i */
485 0x3211103C, /* Smart Array E200i */
486 0x3212103C, /* Smart Array E200 */
487 0x3213103C, /* Smart Array E200i */
488 0x3214103C, /* Smart Array E200i */
489 0x3215103C, /* Smart Array E200i */
490 0x3237103C, /* Smart Array E500 */
491 0x323D103C, /* Smart Array P700m */
7af0abbc 492 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 493 0x409C0E11, /* Smart Array 6400 */
494 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 495 0x40700E11, /* Smart Array 5300 */
496 0x40820E11, /* Smart Array 532 */
497 0x40830E11, /* Smart Array 5312 */
498 0x409A0E11, /* Smart Array 641 */
499 0x409B0E11, /* Smart Array 642 */
500 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 501};
502
46380786
SC		 503/* List of controllers which cannot even be soft reset */
504static u32 soft_unresettable_controller[] = {
7af0abbc 505 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 506 0x40700E11, /* Smart Array 5300 */
507 0x40820E11, /* Smart Array 532 */
508 0x40830E11, /* Smart Array 5312 */
509 0x409A0E11, /* Smart Array 641 */
510 0x409B0E11, /* Smart Array 642 */
511 0x40910E11, /* Smart Array 6i */
46380786
SC		 512 /* Exclude 640x boards. These are two pci devices in one slot
513 * which share a battery backed cache module. One controls the
514 * cache, the other accesses the cache through the one that controls
515 * it. If we reset the one controlling the cache, the other will
516 * likely not be happy. Just forbid resetting this conjoined mess.
517 * The 640x isn't really supported by hpsa anyway.
518 */
519 0x409C0E11, /* Smart Array 6400 */
520 0x409D0E11, /* Smart Array 6400 EM */
521};
522
9b5c48c2
SC		 523static u32 needs_abort_tags_swizzled[] = {
524 0x323D103C, /* Smart Array P700m */
525 0x324a103C, /* Smart Array P712m */
526 0x324b103C, /* SmartArray P711m */
527};
528
529static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 530{
531 int i;
532
9b5c48c2
SC		 533 for (i = 0; i < nelems; i++)
534 if (a[i] == board_id)
535 return 1;
536 return 0;
46380786
SC		 537}
538
9b5c48c2 539static int ctlr_is_hard_resettable(u32 board_id)
46380786 540{
9b5c48c2
SC		 541 return !board_id_in_array(unresettable_controller,
542 ARRAY_SIZE(unresettable_controller), board_id);
543}
46380786 544
9b5c48c2
SC		 545static int ctlr_is_soft_resettable(u32 board_id)
546{
547 return !board_id_in_array(soft_unresettable_controller,
548 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 549}
550
46380786
SC		 551static int ctlr_is_resettable(u32 board_id)
552{
553 return ctlr_is_hard_resettable(board_id) ||
554 ctlr_is_soft_resettable(board_id);
555}
556
9b5c48c2
SC		 557static int ctlr_needs_abort_tags_swizzled(u32 board_id)
558{
559 return board_id_in_array(needs_abort_tags_swizzled,
560 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
561}
562
941b1cda
SC		 563static ssize_t host_show_resettable(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct Scsi_Host *shost = class_to_shost(dev);
568
569 h = shost_to_hba(shost);
46380786 570 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 571}
572
edd16368
SC		 573static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
574{
575 return (scsi3addr[3] & 0xC0) == 0x40;
576}
577
f2ef0ce7
RE		 578static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
579 "1(+0)ADM", "UNKNOWN"
edd16368 580};
6b80b18f
ST		 581#define HPSA_RAID_0 0
582#define HPSA_RAID_4 1
583#define HPSA_RAID_1 2 /* also used for RAID 10 */
584#define HPSA_RAID_5 3 /* also used for RAID 50 */
585#define HPSA_RAID_51 4
586#define HPSA_RAID_6 5 /* also used for RAID 60 */
587#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 588#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
589
590static ssize_t raid_level_show(struct device *dev,
591 struct device_attribute *attr, char *buf)
592{
593 ssize_t l = 0;
82a72c0a 594 unsigned char rlevel;
edd16368
SC		 595 struct ctlr_info *h;
596 struct scsi_device *sdev;
597 struct hpsa_scsi_dev_t *hdev;
598 unsigned long flags;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608
609 /* Is this even a logical drive? */
610 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
611 spin_unlock_irqrestore(&h->lock, flags);
612 l = snprintf(buf, PAGE_SIZE, "N/A\n");
613 return l;
614 }
615
616 rlevel = hdev->raid_level;
617 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 618 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 619 rlevel = RAID_UNKNOWN;
620 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
621 return l;
622}
623
624static ssize_t lunid_show(struct device *dev,
625 struct device_attribute *attr, char *buf)
626{
627 struct ctlr_info *h;
628 struct scsi_device *sdev;
629 struct hpsa_scsi_dev_t *hdev;
630 unsigned long flags;
631 unsigned char lunid[8];
632
633 sdev = to_scsi_device(dev);
634 h = sdev_to_hba(sdev);
635 spin_lock_irqsave(&h->lock, flags);
636 hdev = sdev->hostdata;
637 if (!hdev) {
638 spin_unlock_irqrestore(&h->lock, flags);
639 return -ENODEV;
640 }
641 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
642 spin_unlock_irqrestore(&h->lock, flags);
643 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
644 lunid[0], lunid[1], lunid[2], lunid[3],
645 lunid[4], lunid[5], lunid[6], lunid[7]);
646}
647
648static ssize_t unique_id_show(struct device *dev,
649 struct device_attribute *attr, char *buf)
650{
651 struct ctlr_info *h;
652 struct scsi_device *sdev;
653 struct hpsa_scsi_dev_t *hdev;
654 unsigned long flags;
655 unsigned char sn[16];
656
657 sdev = to_scsi_device(dev);
658 h = sdev_to_hba(sdev);
659 spin_lock_irqsave(&h->lock, flags);
660 hdev = sdev->hostdata;
661 if (!hdev) {
662 spin_unlock_irqrestore(&h->lock, flags);
663 return -ENODEV;
664 }
665 memcpy(sn, hdev->device_id, sizeof(sn));
666 spin_unlock_irqrestore(&h->lock, flags);
667 return snprintf(buf, 16 * 2 + 2,
668 "%02X%02X%02X%02X%02X%02X%02X%02X"
669 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
670 sn[0], sn[1], sn[2], sn[3],
671 sn[4], sn[5], sn[6], sn[7],
672 sn[8], sn[9], sn[10], sn[11],
673 sn[12], sn[13], sn[14], sn[15]);
674}
675
c1988684
ST		 676static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
677 struct device_attribute *attr, char *buf)
678{
679 struct ctlr_info *h;
680 struct scsi_device *sdev;
681 struct hpsa_scsi_dev_t *hdev;
682 unsigned long flags;
683 int offload_enabled;
684
685 sdev = to_scsi_device(dev);
686 h = sdev_to_hba(sdev);
687 spin_lock_irqsave(&h->lock, flags);
688 hdev = sdev->hostdata;
689 if (!hdev) {
690 spin_unlock_irqrestore(&h->lock, flags);
691 return -ENODEV;
692 }
693 offload_enabled = hdev->offload_enabled;
694 spin_unlock_irqrestore(&h->lock, flags);
695 return snprintf(buf, 20, "%d\n", offload_enabled);
696}
697
3f5eac3a
SC		 698static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
699static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
700static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
701static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 702static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
703 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 704static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
705 host_show_hp_ssd_smart_path_status,
706 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 707static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
708 host_store_raid_offload_debug);
3f5eac3a
SC		 709static DEVICE_ATTR(firmware_revision, S_IRUGO,
710 host_show_firmware_revision, NULL);
711static DEVICE_ATTR(commands_outstanding, S_IRUGO,
712 host_show_commands_outstanding, NULL);
713static DEVICE_ATTR(transport_mode, S_IRUGO,
714 host_show_transport_mode, NULL);
941b1cda
SC		 715static DEVICE_ATTR(resettable, S_IRUGO,
716 host_show_resettable, NULL);
e985c58f
SC		 717static DEVICE_ATTR(lockup_detected, S_IRUGO,
718 host_show_lockup_detected, NULL);
3f5eac3a
SC		 719
720static struct device_attribute *hpsa_sdev_attrs[] = {
721 &dev_attr_raid_level,
722 &dev_attr_lunid,
723 &dev_attr_unique_id,
c1988684 724 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 725 &dev_attr_lockup_detected,
3f5eac3a
SC		 726 NULL,
727};
728
729static struct device_attribute *hpsa_shost_attrs[] = {
730 &dev_attr_rescan,
731 &dev_attr_firmware_revision,
732 &dev_attr_commands_outstanding,
733 &dev_attr_transport_mode,
941b1cda 734 &dev_attr_resettable,
da0697bd 735 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 736 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 737 NULL,
738};
739
41ce4c35
SC		 740#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
741 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
742
3f5eac3a
SC		 743static struct scsi_host_template hpsa_driver_template = {
744 .module = THIS_MODULE,
f79cfec6
SC		 745 .name = HPSA,
746 .proc_name = HPSA,
3f5eac3a
SC		 747 .queuecommand = hpsa_scsi_queue_command,
748 .scan_start = hpsa_scan_start,
749 .scan_finished = hpsa_scan_finished,
7c0a0229 750 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 751 .this_id = -1,
752 .use_clustering = ENABLE_CLUSTERING,
75167d2c 753 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 754 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
755 .ioctl = hpsa_ioctl,
756 .slave_alloc = hpsa_slave_alloc,
41ce4c35 757 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 758 .slave_destroy = hpsa_slave_destroy,
759#ifdef CONFIG_COMPAT
760 .compat_ioctl = hpsa_compat_ioctl,
761#endif
762 .sdev_attrs = hpsa_sdev_attrs,
763 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 764 .max_sectors = 8192,
54b2b50c 765 .no_write_same = 1,
3f5eac3a
SC		 766};
767
254f796b 768static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 769{
770 u32 a;
072b0518 771 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 772
e1f7de0c
MG		 773 if (h->transMethod & CFGTBL_Trans_io_accel1)
774 return h->access.command_completed(h, q);
775
3f5eac3a 776 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 777 return h->access.command_completed(h, q);
3f5eac3a 778
254f796b
MG		 779 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
780 a = rq->head[rq->current_entry];
781 rq->current_entry++;
0cbf768e 782 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 783 } else {
784 a = FIFO_EMPTY;
785 }
786 /* Check for wraparound */
254f796b
MG		 787 if (rq->current_entry == h->max_commands) {
788 rq->current_entry = 0;
789 rq->wraparound ^= 1;
3f5eac3a
SC		 790 }
791 return a;
792}
793
c349775e
ST		 794/*
795 * There are some special bits in the bus address of the
796 * command that we have to set for the controller to know
797 * how to process the command:
798 *
799 * Normal performant mode:
800 * bit 0: 1 means performant mode, 0 means simple mode.
801 * bits 1-3 = block fetch table entry
802 * bits 4-6 = command type (== 0)
803 *
804 * ioaccel1 mode:
805 * bit 0 = "performant mode" bit.
806 * bits 1-3 = block fetch table entry
807 * bits 4-6 = command type (== 110)
808 * (command type is needed because ioaccel1 mode
809 * commands are submitted through the same register as normal
810 * mode commands, so this is how the controller knows whether
811 * the command is normal mode or ioaccel1 mode.)
812 *
813 * ioaccel2 mode:
814 * bit 0 = "performant mode" bit.
815 * bits 1-4 = block fetch table entry (note extra bit)
816 * bits 4-6 = not needed, because ioaccel2 mode has
817 * a separate special register for submitting commands.
818 */
819
25163bd5
WS		 820/*
821 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 822 * set bit 0 for pull model, bits 3-1 for block fetch
823 * register number
824 */
25163bd5
WS		 825#define DEFAULT_REPLY_QUEUE (-1)
826static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
827 int reply_queue)
3f5eac3a 828{
254f796b 829 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 830 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 831 if (unlikely(!h->msix_vector))
832 return;
833 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 834 c->Header.ReplyQueue =
804a5cb5 835 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 836 else
837 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 838 }
3f5eac3a
SC		 839}
840
c349775e 841static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 842 struct CommandList *c,
843 int reply_queue)
c349775e
ST		 844{
845 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
846
25163bd5
WS		 847 /*
848 * Tell the controller to post the reply to the queue for this
c349775e
ST		 849 * processor. This seems to give the best I/O throughput.
850 */
25163bd5
WS		 851 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
852 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
853 else
854 cp->ReplyQueue = reply_queue % h->nreply_queues;
855 /*
856 * Set the bits in the address sent down to include:
c349775e
ST		 857 * - performant mode bit (bit 0)
858 * - pull count (bits 1-3)
859 * - command type (bits 4-6)
860 */
861 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
862 IOACCEL1_BUSADDR_CMDTYPE;
863}
864
865static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 866 struct CommandList *c,
867 int reply_queue)
c349775e
ST		 868{
869 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
870
25163bd5
WS		 871 /*
872 * Tell the controller to post the reply to the queue for this
c349775e
ST		 873 * processor. This seems to give the best I/O throughput.
874 */
25163bd5
WS		 875 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
876 cp->reply_queue = smp_processor_id() % h->nreply_queues;
877 else
878 cp->reply_queue = reply_queue % h->nreply_queues;
879 /*
880 * Set the bits in the address sent down to include:
c349775e
ST		 881 * - performant mode bit not used in ioaccel mode 2
882 * - pull count (bits 0-3)
883 * - command type isn't needed for ioaccel2
884 */
885 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
886}
887
e85c5974
SC		 888static int is_firmware_flash_cmd(u8 *cdb)
889{
890 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
891}
892
893/*
894 * During firmware flash, the heartbeat register may not update as frequently
895 * as it should. So we dial down lockup detection during firmware flash. and
896 * dial it back up when firmware flash completes.
897 */
898#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
899#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
900static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
901 struct CommandList *c)
902{
903 if (!is_firmware_flash_cmd(c->Request.CDB))
904 return;
905 atomic_inc(&h->firmware_flash_in_progress);
906 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
907}
908
909static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
910 struct CommandList *c)
911{
912 if (is_firmware_flash_cmd(c->Request.CDB) &&
913 atomic_dec_and_test(&h->firmware_flash_in_progress))
914 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
915}
916
25163bd5
WS		 917static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
918 struct CommandList *c, int reply_queue)
3f5eac3a 919{
c05e8866
SC		 920 dial_down_lockup_detection_during_fw_flash(h, c);
921 atomic_inc(&h->commands_outstanding);
c349775e
ST		 922 switch (c->cmd_type) {
923 case CMD_IOACCEL1:
25163bd5 924 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 925 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 926 break;
927 case CMD_IOACCEL2:
25163bd5 928 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 929 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e
ST		 930 break;
931 default:
25163bd5 932 set_performant_mode(h, c, reply_queue);
c05e8866 933 h->access.submit_command(h, c);
c349775e 934 }
3f5eac3a
SC		 935}
936
25163bd5
WS		 937static void enqueue_cmd_and_start_io(struct ctlr_info *h,
938 struct CommandList *c)
939{
940 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
941}
942
3f5eac3a
SC		 943static inline int is_hba_lunid(unsigned char scsi3addr[])
944{
945 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
946}
947
948static inline int is_scsi_rev_5(struct ctlr_info *h)
949{
950 if (!h->hba_inquiry_data)
951 return 0;
952 if ((h->hba_inquiry_data[2] & 0x07) == 5)
953 return 1;
954 return 0;
955}
956
edd16368
SC		 957static int hpsa_find_target_lun(struct ctlr_info *h,
958 unsigned char scsi3addr[], int bus, int *target, int *lun)
959{
960 /* finds an unused bus, target, lun for a new physical device
961 * assumes h->devlock is held
962 */
963 int i, found = 0;
cfe5badc 964 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 965
263d9401 966 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 967
968 for (i = 0; i < h->ndevices; i++) {
969 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 970 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 971 }
972
263d9401
AM		 973 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
974 if (i < HPSA_MAX_DEVICES) {
975 /* *bus = 1; */
976 *target = i;
977 *lun = 0;
978 found = 1;
edd16368
SC		 979 }
980 return !found;
981}
982
0d96ef5f
WS		 983static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
984 struct hpsa_scsi_dev_t *dev, char *description)
985{
986 dev_printk(level, &h->pdev->dev,
987 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
988 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
989 description,
990 scsi_device_type(dev->devtype),
991 dev->vendor,
992 dev->model,
993 dev->raid_level > RAID_UNKNOWN ?
994 "RAID-?" : raid_label[dev->raid_level],
995 dev->offload_config ? '+' : '-',
996 dev->offload_enabled ? '+' : '-',
997 dev->expose_state);
998}
999
edd16368
SC		 1000/* Add an entry into h->dev[] array. */
1001static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1002 struct hpsa_scsi_dev_t *device,
1003 struct hpsa_scsi_dev_t *added[], int *nadded)
1004{
1005 /* assumes h->devlock is held */
1006 int n = h->ndevices;
1007 int i;
1008 unsigned char addr1[8], addr2[8];
1009 struct hpsa_scsi_dev_t *sd;
1010
cfe5badc 1011 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1012 dev_err(&h->pdev->dev, "too many devices, some will be "
1013 "inaccessible.\n");
1014 return -1;
1015 }
1016
1017 /* physical devices do not have lun or target assigned until now. */
1018 if (device->lun != -1)
1019 /* Logical device, lun is already assigned. */
1020 goto lun_assigned;
1021
1022 /* If this device a non-zero lun of a multi-lun device
1023 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1024 * unit no, zero otherwise.
edd16368
SC		 1025 */
1026 if (device->scsi3addr[4] == 0) {
1027 /* This is not a non-zero lun of a multi-lun device */
1028 if (hpsa_find_target_lun(h, device->scsi3addr,
1029 device->bus, &device->target, &device->lun) != 0)
1030 return -1;
1031 goto lun_assigned;
1032 }
1033
1034 /* This is a non-zero lun of a multi-lun device.
1035 * Search through our list and find the device which
1036 * has the same 8 byte LUN address, excepting byte 4.
1037 * Assign the same bus and target for this new LUN.
1038 * Use the logical unit number from the firmware.
1039 */
1040 memcpy(addr1, device->scsi3addr, 8);
1041 addr1[4] = 0;
1042 for (i = 0; i < n; i++) {
1043 sd = h->dev[i];
1044 memcpy(addr2, sd->scsi3addr, 8);
1045 addr2[4] = 0;
1046 /* differ only in byte 4? */
1047 if (memcmp(addr1, addr2, 8) == 0) {
1048 device->bus = sd->bus;
1049 device->target = sd->target;
1050 device->lun = device->scsi3addr[4];
1051 break;
1052 }
1053 }
1054 if (device->lun == -1) {
1055 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1056 " suspect firmware bug or unsupported hardware "
1057 "configuration.\n");
1058 return -1;
1059 }
1060
1061lun_assigned:
1062
1063 h->dev[n] = device;
1064 h->ndevices++;
1065 added[*nadded] = device;
1066 (*nadded)++;
0d96ef5f
WS		 1067 hpsa_show_dev_msg(KERN_INFO, h, device,
1068 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1069 device->offload_to_be_enabled = device->offload_enabled;
1070 device->offload_enabled = 0;
edd16368
SC		 1071 return 0;
1072}
1073
bd9244f7
ST		 1074/* Update an entry in h->dev[] array. */
1075static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1076 int entry, struct hpsa_scsi_dev_t *new_entry)
1077{
a473d86c 1078 int offload_enabled;
bd9244f7
ST		 1079 /* assumes h->devlock is held */
1080 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1081
1082 /* Raid level changed. */
1083 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1084
03383736
DB		 1085 /* Raid offload parameters changed. Careful about the ordering. */
1086 if (new_entry->offload_config && new_entry->offload_enabled) {
1087 /*
1088 * if drive is newly offload_enabled, we want to copy the
1089 * raid map data first. If previously offload_enabled and
1090 * offload_config were set, raid map data had better be
1091 * the same as it was before. if raid map data is changed
1092 * then it had better be the case that
1093 * h->dev[entry]->offload_enabled is currently 0.
1094 */
1095 h->dev[entry]->raid_map = new_entry->raid_map;
1096 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1097 }
a3144e0b
JH		 1098 if (new_entry->hba_ioaccel_enabled) {
1099 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1100 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1101 }
1102 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1103 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1104 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1105 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1106
41ce4c35
SC		 1107 /*
1108 * We can turn off ioaccel offload now, but need to delay turning
1109 * it on until we can update h->dev[entry]->phys_disk[], but we
1110 * can't do that until all the devices are updated.
1111 */
1112 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1113 if (!new_entry->offload_enabled)
1114 h->dev[entry]->offload_enabled = 0;
1115
a473d86c
RE		 1116 offload_enabled = h->dev[entry]->offload_enabled;
1117 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1118 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1119 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1120}
1121
2a8ccf31
SC		 1122/* Replace an entry from h->dev[] array. */
1123static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1124 int entry, struct hpsa_scsi_dev_t *new_entry,
1125 struct hpsa_scsi_dev_t *added[], int *nadded,
1126 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1127{
1128 /* assumes h->devlock is held */
cfe5badc 1129 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1130 removed[*nremoved] = h->dev[entry];
1131 (*nremoved)++;
01350d05
SC		 1132
1133 /*
1134 * New physical devices won't have target/lun assigned yet
1135 * so we need to preserve the values in the slot we are replacing.
1136 */
1137 if (new_entry->target == -1) {
1138 new_entry->target = h->dev[entry]->target;
1139 new_entry->lun = h->dev[entry]->lun;
1140 }
1141
2a8ccf31
SC		 1142 h->dev[entry] = new_entry;
1143 added[*nadded] = new_entry;
1144 (*nadded)++;
0d96ef5f 1145 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1146 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1147 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1148}
1149
edd16368
SC		 1150/* Remove an entry from h->dev[] array. */
1151static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1152 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1153{
1154 /* assumes h->devlock is held */
1155 int i;
1156 struct hpsa_scsi_dev_t *sd;
1157
cfe5badc 1158 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1159
1160 sd = h->dev[entry];
1161 removed[*nremoved] = h->dev[entry];
1162 (*nremoved)++;
1163
1164 for (i = entry; i < h->ndevices-1; i++)
1165 h->dev[i] = h->dev[i+1];
1166 h->ndevices--;
0d96ef5f 1167 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1168}
1169
1170#define SCSI3ADDR_EQ(a, b) ( \
1171 (a)[7] == (b)[7] && \
1172 (a)[6] == (b)[6] && \
1173 (a)[5] == (b)[5] && \
1174 (a)[4] == (b)[4] && \
1175 (a)[3] == (b)[3] && \
1176 (a)[2] == (b)[2] && \
1177 (a)[1] == (b)[1] && \
1178 (a)[0] == (b)[0])
1179
1180static void fixup_botched_add(struct ctlr_info *h,
1181 struct hpsa_scsi_dev_t *added)
1182{
1183 /* called when scsi_add_device fails in order to re-adjust
1184 * h->dev[] to match the mid layer's view.
1185 */
1186 unsigned long flags;
1187 int i, j;
1188
1189 spin_lock_irqsave(&h->lock, flags);
1190 for (i = 0; i < h->ndevices; i++) {
1191 if (h->dev[i] == added) {
1192 for (j = i; j < h->ndevices-1; j++)
1193 h->dev[j] = h->dev[j+1];
1194 h->ndevices--;
1195 break;
1196 }
1197 }
1198 spin_unlock_irqrestore(&h->lock, flags);
1199 kfree(added);
1200}
1201
1202static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1203 struct hpsa_scsi_dev_t *dev2)
1204{
edd16368
SC		 1205 /* we compare everything except lun and target as these
1206 * are not yet assigned. Compare parts likely
1207 * to differ first
1208 */
1209 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1210 sizeof(dev1->scsi3addr)) != 0)
1211 return 0;
1212 if (memcmp(dev1->device_id, dev2->device_id,
1213 sizeof(dev1->device_id)) != 0)
1214 return 0;
1215 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1216 return 0;
1217 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1218 return 0;
edd16368
SC		 1219 if (dev1->devtype != dev2->devtype)
1220 return 0;
edd16368
SC		 1221 if (dev1->bus != dev2->bus)
1222 return 0;
1223 return 1;
1224}
1225
bd9244f7
ST		 1226static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1227 struct hpsa_scsi_dev_t *dev2)
1228{
1229 /* Device attributes that can change, but don't mean
1230 * that the device is a different device, nor that the OS
1231 * needs to be told anything about the change.
1232 */
1233 if (dev1->raid_level != dev2->raid_level)
1234 return 1;
250fb125
SC		 1235 if (dev1->offload_config != dev2->offload_config)
1236 return 1;
1237 if (dev1->offload_enabled != dev2->offload_enabled)
1238 return 1;
03383736
DB		 1239 if (dev1->queue_depth != dev2->queue_depth)
1240 return 1;
bd9244f7
ST		 1241 return 0;
1242}
1243
edd16368
SC		 1244/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1245 * and return needle location in *index. If scsi3addr matches, but not
1246 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1247 * location in *index.
1248 * In the case of a minor device attribute change, such as RAID level, just
1249 * return DEVICE_UPDATED, along with the updated device's location in index.
1250 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1251 */
1252static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1253 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1254 int *index)
1255{
1256 int i;
1257#define DEVICE_NOT_FOUND 0
1258#define DEVICE_CHANGED 1
1259#define DEVICE_SAME 2
bd9244f7 1260#define DEVICE_UPDATED 3
edd16368 1261 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1262 if (haystack[i] == NULL) /* previously removed. */
1263 continue;
edd16368
SC		 1264 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1265 *index = i;
bd9244f7
ST		 1266 if (device_is_the_same(needle, haystack[i])) {
1267 if (device_updated(needle, haystack[i]))
1268 return DEVICE_UPDATED;
edd16368 1269 return DEVICE_SAME;
bd9244f7 1270 } else {
9846590e
SC		 1271 /* Keep offline devices offline */
1272 if (needle->volume_offline)
1273 return DEVICE_NOT_FOUND;
edd16368 1274 return DEVICE_CHANGED;
bd9244f7 1275 }
edd16368
SC		 1276 }
1277 }
1278 *index = -1;
1279 return DEVICE_NOT_FOUND;
1280}
1281
9846590e
SC		 1282static void hpsa_monitor_offline_device(struct ctlr_info *h,
1283 unsigned char scsi3addr[])
1284{
1285 struct offline_device_entry *device;
1286 unsigned long flags;
1287
1288 /* Check to see if device is already on the list */
1289 spin_lock_irqsave(&h->offline_device_lock, flags);
1290 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1291 if (memcmp(device->scsi3addr, scsi3addr,
1292 sizeof(device->scsi3addr)) == 0) {
1293 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1294 return;
1295 }
1296 }
1297 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1298
1299 /* Device is not on the list, add it. */
1300 device = kmalloc(sizeof(*device), GFP_KERNEL);
1301 if (!device) {
1302 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1303 return;
1304 }
1305 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1306 spin_lock_irqsave(&h->offline_device_lock, flags);
1307 list_add_tail(&device->offline_list, &h->offline_device_list);
1308 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1309}
1310
1311/* Print a message explaining various offline volume states */
1312static void hpsa_show_volume_status(struct ctlr_info *h,
1313 struct hpsa_scsi_dev_t *sd)
1314{
1315 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1316 dev_info(&h->pdev->dev,
1317 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1318 h->scsi_host->host_no,
1319 sd->bus, sd->target, sd->lun);
1320 switch (sd->volume_offline) {
1321 case HPSA_LV_OK:
1322 break;
1323 case HPSA_LV_UNDERGOING_ERASE:
1324 dev_info(&h->pdev->dev,
1325 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1326 h->scsi_host->host_no,
1327 sd->bus, sd->target, sd->lun);
1328 break;
1329 case HPSA_LV_UNDERGOING_RPI:
1330 dev_info(&h->pdev->dev,
1331 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1332 h->scsi_host->host_no,
1333 sd->bus, sd->target, sd->lun);
1334 break;
1335 case HPSA_LV_PENDING_RPI:
1336 dev_info(&h->pdev->dev,
1337 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1338 h->scsi_host->host_no,
1339 sd->bus, sd->target, sd->lun);
1340 break;
1341 case HPSA_LV_ENCRYPTED_NO_KEY:
1342 dev_info(&h->pdev->dev,
1343 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1344 h->scsi_host->host_no,
1345 sd->bus, sd->target, sd->lun);
1346 break;
1347 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1348 dev_info(&h->pdev->dev,
1349 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1350 h->scsi_host->host_no,
1351 sd->bus, sd->target, sd->lun);
1352 break;
1353 case HPSA_LV_UNDERGOING_ENCRYPTION:
1354 dev_info(&h->pdev->dev,
1355 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1356 h->scsi_host->host_no,
1357 sd->bus, sd->target, sd->lun);
1358 break;
1359 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1360 dev_info(&h->pdev->dev,
1361 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1362 h->scsi_host->host_no,
1363 sd->bus, sd->target, sd->lun);
1364 break;
1365 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1366 dev_info(&h->pdev->dev,
1367 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1368 h->scsi_host->host_no,
1369 sd->bus, sd->target, sd->lun);
1370 break;
1371 case HPSA_LV_PENDING_ENCRYPTION:
1372 dev_info(&h->pdev->dev,
1373 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1374 h->scsi_host->host_no,
1375 sd->bus, sd->target, sd->lun);
1376 break;
1377 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1378 dev_info(&h->pdev->dev,
1379 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1380 h->scsi_host->host_no,
1381 sd->bus, sd->target, sd->lun);
1382 break;
1383 }
1384}
1385
03383736
DB		 1386/*
1387 * Figure the list of physical drive pointers for a logical drive with
1388 * raid offload configured.
1389 */
1390static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1391 struct hpsa_scsi_dev_t *dev[], int ndevices,
1392 struct hpsa_scsi_dev_t *logical_drive)
1393{
1394 struct raid_map_data *map = &logical_drive->raid_map;
1395 struct raid_map_disk_data *dd = &map->data[0];
1396 int i, j;
1397 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1398 le16_to_cpu(map->metadata_disks_per_row);
1399 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1400 le16_to_cpu(map->layout_map_count) *
1401 total_disks_per_row;
1402 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1403 total_disks_per_row;
1404 int qdepth;
1405
1406 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1407 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1408
1409 qdepth = 0;
1410 for (i = 0; i < nraid_map_entries; i++) {
1411 logical_drive->phys_disk[i] = NULL;
1412 if (!logical_drive->offload_config)
1413 continue;
1414 for (j = 0; j < ndevices; j++) {
1415 if (dev[j]->devtype != TYPE_DISK)
1416 continue;
1417 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1418 continue;
1419 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1420 continue;
1421
1422 logical_drive->phys_disk[i] = dev[j];
1423 if (i < nphys_disk)
1424 qdepth = min(h->nr_cmds, qdepth +
1425 logical_drive->phys_disk[i]->queue_depth);
1426 break;
1427 }
1428
1429 /*
1430 * This can happen if a physical drive is removed and
1431 * the logical drive is degraded. In that case, the RAID
1432 * map data will refer to a physical disk which isn't actually
1433 * present. And in that case offload_enabled should already
1434 * be 0, but we'll turn it off here just in case
1435 */
1436 if (!logical_drive->phys_disk[i]) {
1437 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1438 logical_drive->offload_to_be_enabled = 0;
1439 logical_drive->queue_depth = 8;
03383736
DB		 1440 }
1441 }
1442 if (nraid_map_entries)
1443 /*
1444 * This is correct for reads, too high for full stripe writes,
1445 * way too high for partial stripe writes
1446 */
1447 logical_drive->queue_depth = qdepth;
1448 else
1449 logical_drive->queue_depth = h->nr_cmds;
1450}
1451
1452static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1453 struct hpsa_scsi_dev_t *dev[], int ndevices)
1454{
1455 int i;
1456
1457 for (i = 0; i < ndevices; i++) {
1458 if (dev[i]->devtype != TYPE_DISK)
1459 continue;
1460 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1461 continue;
41ce4c35
SC		 1462
1463 /*
1464 * If offload is currently enabled, the RAID map and
1465 * phys_disk[] assignment *better* not be changing
1466 * and since it isn't changing, we do not need to
1467 * update it.
1468 */
1469 if (dev[i]->offload_enabled)
1470 continue;
1471
03383736
DB		 1472 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1473 }
1474}
1475
4967bd3e 1476static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1477 struct hpsa_scsi_dev_t *sd[], int nsds)
1478{
1479 /* sd contains scsi3 addresses and devtypes, and inquiry
1480 * data. This function takes what's in sd to be the current
1481 * reality and updates h->dev[] to reflect that reality.
1482 */
1483 int i, entry, device_change, changes = 0;
1484 struct hpsa_scsi_dev_t *csd;
1485 unsigned long flags;
1486 struct hpsa_scsi_dev_t **added, **removed;
1487 int nadded, nremoved;
1488 struct Scsi_Host *sh = NULL;
1489
cfe5badc
ST		 1490 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1491 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1492
1493 if (!added || !removed) {
1494 dev_warn(&h->pdev->dev, "out of memory in "
1495 "adjust_hpsa_scsi_table\n");
1496 goto free_and_out;
1497 }
1498
1499 spin_lock_irqsave(&h->devlock, flags);
1500
1501 /* find any devices in h->dev[] that are not in
1502 * sd[] and remove them from h->dev[], and for any
1503 * devices which have changed, remove the old device
1504 * info and add the new device info.
bd9244f7
ST		 1505 * If minor device attributes change, just update
1506 * the existing device structure.
edd16368
SC		 1507 */
1508 i = 0;
1509 nremoved = 0;
1510 nadded = 0;
1511 while (i < h->ndevices) {
1512 csd = h->dev[i];
1513 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1514 if (device_change == DEVICE_NOT_FOUND) {
1515 changes++;
1516 hpsa_scsi_remove_entry(h, hostno, i,
1517 removed, &nremoved);
1518 continue; /* remove ^^^, hence i not incremented */
1519 } else if (device_change == DEVICE_CHANGED) {
1520 changes++;
2a8ccf31
SC		 1521 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1522 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1523 /* Set it to NULL to prevent it from being freed
1524 * at the bottom of hpsa_update_scsi_devices()
1525 */
1526 sd[entry] = NULL;
bd9244f7
ST		 1527 } else if (device_change == DEVICE_UPDATED) {
1528 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1529 }
1530 i++;
1531 }
1532
1533 /* Now, make sure every device listed in sd[] is also
1534 * listed in h->dev[], adding them if they aren't found
1535 */
1536
1537 for (i = 0; i < nsds; i++) {
1538 if (!sd[i]) /* if already added above. */
1539 continue;
9846590e
SC		 1540
1541 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1542 * as the SCSI mid-layer does not handle such devices well.
1543 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1544 * at 160Hz, and prevents the system from coming up.
1545 */
1546 if (sd[i]->volume_offline) {
1547 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1548 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1549 continue;
1550 }
1551
edd16368
SC		 1552 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1553 h->ndevices, &entry);
1554 if (device_change == DEVICE_NOT_FOUND) {
1555 changes++;
1556 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1557 added, &nadded) != 0)
1558 break;
1559 sd[i] = NULL; /* prevent from being freed later. */
1560 } else if (device_change == DEVICE_CHANGED) {
1561 /* should never happen... */
1562 changes++;
1563 dev_warn(&h->pdev->dev,
1564 "device unexpectedly changed.\n");
1565 /* but if it does happen, we just ignore that device */
1566 }
1567 }
41ce4c35
SC		 1568 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1569
1570 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1571 * any logical drives that need it enabled.
1572 */
1573 for (i = 0; i < h->ndevices; i++)
1574 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1575
edd16368
SC		 1576 spin_unlock_irqrestore(&h->devlock, flags);
1577
9846590e
SC		 1578 /* Monitor devices which are in one of several NOT READY states to be
1579 * brought online later. This must be done without holding h->devlock,
1580 * so don't touch h->dev[]
1581 */
1582 for (i = 0; i < nsds; i++) {
1583 if (!sd[i]) /* if already added above. */
1584 continue;
1585 if (sd[i]->volume_offline)
1586 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1587 }
1588
edd16368
SC		 1589 /* Don't notify scsi mid layer of any changes the first time through
1590 * (or if there are no changes) scsi_scan_host will do it later the
1591 * first time through.
1592 */
1593 if (hostno == -1 || !changes)
1594 goto free_and_out;
1595
1596 sh = h->scsi_host;
1597 /* Notify scsi mid layer of any removed devices */
1598 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1599 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1600 struct scsi_device *sdev =
1601 scsi_device_lookup(sh, removed[i]->bus,
1602 removed[i]->target, removed[i]->lun);
1603 if (sdev != NULL) {
1604 scsi_remove_device(sdev);
1605 scsi_device_put(sdev);
1606 } else {
1607 /*
1608 * We don't expect to get here.
1609 * future cmds to this device will get selection
1610 * timeout as if the device was gone.
1611 */
0d96ef5f
WS		 1612 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1613 "didn't find device for removal.");
41ce4c35 1614 }
edd16368
SC		 1615 }
1616 kfree(removed[i]);
1617 removed[i] = NULL;
1618 }
1619
1620 /* Notify scsi mid layer of any added devices */
1621 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1622 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1623 continue;
edd16368
SC		 1624 if (scsi_add_device(sh, added[i]->bus,
1625 added[i]->target, added[i]->lun) == 0)
1626 continue;
0d96ef5f
WS		 1627 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1628 "addition failed, device not added.");
edd16368
SC		 1629 /* now we have to remove it from h->dev,
1630 * since it didn't get added to scsi mid layer
1631 */
1632 fixup_botched_add(h, added[i]);
1633 }
1634
1635free_and_out:
1636 kfree(added);
1637 kfree(removed);
edd16368
SC		 1638}
1639
1640/*
9e03aa2f 1641 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1642 * Assume's h->devlock is held.
1643 */
1644static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1645 int bus, int target, int lun)
1646{
1647 int i;
1648 struct hpsa_scsi_dev_t *sd;
1649
1650 for (i = 0; i < h->ndevices; i++) {
1651 sd = h->dev[i];
1652 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1653 return sd;
1654 }
1655 return NULL;
1656}
1657
edd16368
SC		 1658static int hpsa_slave_alloc(struct scsi_device *sdev)
1659{
1660 struct hpsa_scsi_dev_t *sd;
1661 unsigned long flags;
1662 struct ctlr_info *h;
1663
1664 h = sdev_to_hba(sdev);
1665 spin_lock_irqsave(&h->devlock, flags);
1666 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1667 sdev_id(sdev), sdev->lun);
41ce4c35 1668 if (likely(sd)) {
03383736 1669 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1670 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1671 } else
1672 sdev->hostdata = NULL;
edd16368
SC		 1673 spin_unlock_irqrestore(&h->devlock, flags);
1674 return 0;
1675}
1676
41ce4c35
SC		 1677/* configure scsi device based on internal per-device structure */
1678static int hpsa_slave_configure(struct scsi_device *sdev)
1679{
1680 struct hpsa_scsi_dev_t *sd;
1681 int queue_depth;
1682
1683 sd = sdev->hostdata;
1684 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1685
1686 if (sd)
1687 queue_depth = sd->queue_depth != 0 ?
1688 sd->queue_depth : sdev->host->can_queue;
1689 else
1690 queue_depth = sdev->host->can_queue;
1691
1692 scsi_change_queue_depth(sdev, queue_depth);
1693
1694 return 0;
1695}
1696
edd16368
SC		 1697static void hpsa_slave_destroy(struct scsi_device *sdev)
1698{
bcc44255 1699 /* nothing to do. */
edd16368
SC		 1700}
1701
33a2ffce
SC		 1702static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1703{
1704 int i;
1705
1706 if (!h->cmd_sg_list)
1707 return;
1708 for (i = 0; i < h->nr_cmds; i++) {
1709 kfree(h->cmd_sg_list[i]);
1710 h->cmd_sg_list[i] = NULL;
1711 }
1712 kfree(h->cmd_sg_list);
1713 h->cmd_sg_list = NULL;
1714}
1715
1716static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1717{
1718 int i;
1719
1720 if (h->chainsize <= 0)
1721 return 0;
1722
1723 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1724 GFP_KERNEL);
3d4e6af8
RE		 1725 if (!h->cmd_sg_list) {
1726 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1727 return -ENOMEM;
3d4e6af8 1728 }
33a2ffce
SC		 1729 for (i = 0; i < h->nr_cmds; i++) {
1730 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1731 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1732 if (!h->cmd_sg_list[i]) {
1733 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1734 goto clean;
3d4e6af8 1735 }
33a2ffce
SC		 1736 }
1737 return 0;
1738
1739clean:
1740 hpsa_free_sg_chain_blocks(h);
1741 return -ENOMEM;
1742}
1743
e2bea6df 1744static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1745 struct CommandList *c)
1746{
1747 struct SGDescriptor *chain_sg, *chain_block;
1748 u64 temp64;
50a0decf 1749 u32 chain_len;
33a2ffce
SC		 1750
1751 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1752 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1753 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1754 chain_len = sizeof(*chain_sg) *
2b08b3e9 1755 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1756 chain_sg->Len = cpu_to_le32(chain_len);
1757 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1758 PCI_DMA_TODEVICE);
e2bea6df
SC		 1759 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1760 /* prevent subsequent unmapping */
50a0decf 1761 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1762 return -1;
1763 }
50a0decf 1764 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1765 return 0;
33a2ffce
SC		 1766}
1767
1768static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1769 struct CommandList *c)
1770{
1771 struct SGDescriptor *chain_sg;
33a2ffce 1772
50a0decf 1773 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1774 return;
1775
1776 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1777 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1778 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1779}
1780
a09c1441
ST		 1781
1782/* Decode the various types of errors on ioaccel2 path.
1783 * Return 1 for any error that should generate a RAID path retry.
1784 * Return 0 for errors that don't require a RAID path retry.
1785 */
1786static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1787 struct CommandList *c,
1788 struct scsi_cmnd *cmd,
1789 struct io_accel2_cmd *c2)
1790{
1791 int data_len;
a09c1441 1792 int retry = 0;
c349775e
ST		 1793
1794 switch (c2->error_data.serv_response) {
1795 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1796 switch (c2->error_data.status) {
1797 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1798 break;
1799 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1800 dev_warn(&h->pdev->dev,
1801 "%s: task complete with check condition.\n",
1802 "HP SSD Smart Path");
ee6b1889 1803 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1804 if (c2->error_data.data_present !=
ee6b1889
SC		 1805 IOACCEL2_SENSE_DATA_PRESENT) {
1806 memset(cmd->sense_buffer, 0,
1807 SCSI_SENSE_BUFFERSIZE);
c349775e 1808 break;
ee6b1889 1809 }
c349775e
ST		 1810 /* copy the sense data */
1811 data_len = c2->error_data.sense_data_len;
1812 if (data_len > SCSI_SENSE_BUFFERSIZE)
1813 data_len = SCSI_SENSE_BUFFERSIZE;
1814 if (data_len > sizeof(c2->error_data.sense_data_buff))
1815 data_len =
1816 sizeof(c2->error_data.sense_data_buff);
1817 memcpy(cmd->sense_buffer,
1818 c2->error_data.sense_data_buff, data_len);
a09c1441 1819 retry = 1;
c349775e
ST		 1820 break;
1821 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1822 dev_warn(&h->pdev->dev,
1823 "%s: task complete with BUSY status.\n",
1824 "HP SSD Smart Path");
a09c1441 1825 retry = 1;
c349775e
ST		 1826 break;
1827 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1828 dev_warn(&h->pdev->dev,
1829 "%s: task complete with reservation conflict.\n",
1830 "HP SSD Smart Path");
a09c1441 1831 retry = 1;
c349775e
ST		 1832 break;
1833 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1834 retry = 1;
c349775e
ST		 1835 break;
1836 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1837 dev_warn(&h->pdev->dev,
1838 "%s: task complete with aborted status.\n",
1839 "HP SSD Smart Path");
a09c1441 1840 retry = 1;
c349775e
ST		 1841 break;
1842 default:
1843 dev_warn(&h->pdev->dev,
1844 "%s: task complete with unrecognized status: 0x%02x\n",
1845 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1846 retry = 1;
c349775e
ST		 1847 break;
1848 }
1849 break;
1850 case IOACCEL2_SERV_RESPONSE_FAILURE:
1851 /* don't expect to get here. */
1852 dev_warn(&h->pdev->dev,
1853 "unexpected delivery or target failure, status = 0x%02x\n",
1854 c2->error_data.status);
a09c1441 1855 retry = 1;
c349775e
ST		 1856 break;
1857 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1858 break;
1859 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1860 break;
1861 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1862 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1863 retry = 1;
c349775e
ST		 1864 break;
1865 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1866 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1867 break;
1868 default:
1869 dev_warn(&h->pdev->dev,
1870 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1871 "HP SSD Smart Path",
1872 c2->error_data.serv_response);
1873 retry = 1;
c349775e
ST		 1874 break;
1875 }
a09c1441
ST		 1876
1877 return retry; /* retry on raid path? */
c349775e
ST		 1878}
1879
1880static void process_ioaccel2_completion(struct ctlr_info *h,
1881 struct CommandList *c, struct scsi_cmnd *cmd,
1882 struct hpsa_scsi_dev_t *dev)
1883{
1884 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1885
1886 /* check for good status */
1887 if (likely(c2->error_data.serv_response == 0 &&
1888 c2->error_data.status == 0)) {
1889 cmd_free(h, c);
1890 cmd->scsi_done(cmd);
1891 return;
1892 }
1893
1894 /* Any RAID offload error results in retry which will use
1895 * the normal I/O path so the controller can handle whatever's
1896 * wrong.
1897 */
1898 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1899 c2->error_data.serv_response ==
1900 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1901 if (c2->error_data.status ==
1902 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1903 dev->offload_enabled = 0;
1904 goto retry_cmd;
a09c1441 1905 }
080ef1cc
DB		 1906
1907 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1908 goto retry_cmd;
1909
c349775e
ST		 1910 cmd_free(h, c);
1911 cmd->scsi_done(cmd);
080ef1cc
DB		 1912 return;
1913
1914retry_cmd:
1915 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1916 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1917}
1918
9437ac43
SC		 1919/* Returns 0 on success, < 0 otherwise. */
1920static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
1921 struct CommandList *cp)
1922{
1923 u8 tmf_status = cp->err_info->ScsiStatus;
1924
1925 switch (tmf_status) {
1926 case CISS_TMF_COMPLETE:
1927 /*
1928 * CISS_TMF_COMPLETE never happens, instead,
1929 * ei->CommandStatus == 0 for this case.
1930 */
1931 case CISS_TMF_SUCCESS:
1932 return 0;
1933 case CISS_TMF_INVALID_FRAME:
1934 case CISS_TMF_NOT_SUPPORTED:
1935 case CISS_TMF_FAILED:
1936 case CISS_TMF_WRONG_LUN:
1937 case CISS_TMF_OVERLAPPED_TAG:
1938 break;
1939 default:
1940 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
1941 tmf_status);
1942 break;
1943 }
1944 return -tmf_status;
1945}
1946
1fb011fb 1947static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1948{
1949 struct scsi_cmnd *cmd;
1950 struct ctlr_info *h;
1951 struct ErrorInfo *ei;
283b4a9b 1952 struct hpsa_scsi_dev_t *dev;
edd16368 1953
9437ac43
SC		 1954 u8 sense_key;
1955 u8 asc; /* additional sense code */
1956 u8 ascq; /* additional sense code qualifier */
db111e18 1957 unsigned long sense_data_size;
edd16368
SC		 1958
1959 ei = cp->err_info;
7fa3030c 1960 cmd = cp->scsi_cmd;
edd16368 1961 h = cp->h;
283b4a9b 1962 dev = cmd->device->hostdata;
edd16368
SC		 1963
1964 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1965 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1966 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1967 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1968
1969 cmd->result = (DID_OK << 16); /* host byte */
1970 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 1971
03383736
DB		 1972 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
1973 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
1974
25163bd5
WS		 1975 /*
1976 * We check for lockup status here as it may be set for
1977 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
1978 * fail_all_oustanding_cmds()
1979 */
1980 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
1981 /* DID_NO_CONNECT will prevent a retry */
1982 cmd->result = DID_NO_CONNECT << 16;
1983 cmd_free(h, cp);
1984 cmd->scsi_done(cmd);
1985 return;
1986 }
1987
c349775e
ST		 1988 if (cp->cmd_type == CMD_IOACCEL2)
1989 return process_ioaccel2_completion(h, cp, cmd, dev);
1990
6aa4c361
RE		 1991 scsi_set_resid(cmd, ei->ResidualCnt);
1992 if (ei->CommandStatus == 0) {
03383736
DB		 1993 if (cp->cmd_type == CMD_IOACCEL1)
1994 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 1995 cmd_free(h, cp);
1996 cmd->scsi_done(cmd);
1997 return;
1998 }
1999
e1f7de0c
MG		 2000 /* For I/O accelerator commands, copy over some fields to the normal
2001 * CISS header used below for error handling.
2002 */
2003 if (cp->cmd_type == CMD_IOACCEL1) {
2004 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2005 cp->Header.SGList = scsi_sg_count(cmd);
2006 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2007 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2008 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2009 cp->Header.tag = c->tag;
e1f7de0c
MG		 2010 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2011 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2012
2013 /* Any RAID offload error results in retry which will use
2014 * the normal I/O path so the controller can handle whatever's
2015 * wrong.
2016 */
2017 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2018 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2019 dev->offload_enabled = 0;
080ef1cc
DB		 2020 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
2021 queue_work_on(raw_smp_processor_id(),
2022 h->resubmit_wq, &cp->work);
283b4a9b
SC		 2023 return;
2024 }
e1f7de0c
MG		 2025 }
2026
edd16368
SC		 2027 /* an error has occurred */
2028 switch (ei->CommandStatus) {
2029
2030 case CMD_TARGET_STATUS:
9437ac43
SC		 2031 cmd->result |= ei->ScsiStatus;
2032 /* copy the sense data */
2033 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2034 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2035 else
2036 sense_data_size = sizeof(ei->SenseInfo);
2037 if (ei->SenseLen < sense_data_size)
2038 sense_data_size = ei->SenseLen;
2039 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2040 if (ei->ScsiStatus)
2041 decode_sense_data(ei->SenseInfo, sense_data_size,
2042 &sense_key, &asc, &ascq);
edd16368 2043 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2044 if (sense_key == ABORTED_COMMAND) {
2e311fba 2045 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2046 break;
2047 }
edd16368
SC		 2048 break;
2049 }
edd16368
SC		 2050 /* Problem was not a check condition
2051 * Pass it up to the upper layers...
2052 */
2053 if (ei->ScsiStatus) {
2054 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2055 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2056 "Returning result: 0x%x\n",
2057 cp, ei->ScsiStatus,
2058 sense_key, asc, ascq,
2059 cmd->result);
2060 } else { /* scsi status is zero??? How??? */
2061 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2062 "Returning no connection.\n", cp),
2063
2064 /* Ordinarily, this case should never happen,
2065 * but there is a bug in some released firmware
2066 * revisions that allows it to happen if, for
2067 * example, a 4100 backplane loses power and
2068 * the tape drive is in it. We assume that
2069 * it's a fatal error of some kind because we
2070 * can't show that it wasn't. We will make it
2071 * look like selection timeout since that is
2072 * the most common reason for this to occur,
2073 * and it's severe enough.
2074 */
2075
2076 cmd->result = DID_NO_CONNECT << 16;
2077 }
2078 break;
2079
2080 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2081 break;
2082 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2083 dev_warn(&h->pdev->dev,
2084 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2085 break;
2086 case CMD_INVALID: {
2087 /* print_bytes(cp, sizeof(*cp), 1, 0);
2088 print_cmd(cp); */
2089 /* We get CMD_INVALID if you address a non-existent device
2090 * instead of a selection timeout (no response). You will
2091 * see this if you yank out a drive, then try to access it.
2092 * This is kind of a shame because it means that any other
2093 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2094 * missing target. */
2095 cmd->result = DID_NO_CONNECT << 16;
2096 }
2097 break;
2098 case CMD_PROTOCOL_ERR:
256d0eaa 2099 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2100 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2101 cp->Request.CDB);
edd16368
SC		 2102 break;
2103 case CMD_HARDWARE_ERR:
2104 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2105 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2106 cp->Request.CDB);
edd16368
SC		 2107 break;
2108 case CMD_CONNECTION_LOST:
2109 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2110 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2111 cp->Request.CDB);
edd16368
SC		 2112 break;
2113 case CMD_ABORTED:
2114 cmd->result = DID_ABORT << 16;
f42e81e1
SC		 2115 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2116 cp->Request.CDB, ei->ScsiStatus);
edd16368
SC		 2117 break;
2118 case CMD_ABORT_FAILED:
2119 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2120 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2121 cp->Request.CDB);
edd16368
SC		 2122 break;
2123 case CMD_UNSOLICITED_ABORT:
f6e76055 2124 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2125 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2126 cp->Request.CDB);
edd16368
SC		 2127 break;
2128 case CMD_TIMEOUT:
2129 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2130 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2131 cp->Request.CDB);
edd16368 2132 break;
1d5e2ed0
SC		 2133 case CMD_UNABORTABLE:
2134 cmd->result = DID_ERROR << 16;
2135 dev_warn(&h->pdev->dev, "Command unabortable\n");
2136 break;
9437ac43
SC		 2137 case CMD_TMF_STATUS:
2138 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2139 cmd->result = DID_ERROR << 16;
2140 break;
283b4a9b
SC		 2141 case CMD_IOACCEL_DISABLED:
2142 /* This only handles the direct pass-through case since RAID
2143 * offload is handled above. Just attempt a retry.
2144 */
2145 cmd->result = DID_SOFT_ERROR << 16;
2146 dev_warn(&h->pdev->dev,
2147 "cp %p had HP SSD Smart Path error\n", cp);
2148 break;
edd16368
SC		 2149 default:
2150 cmd->result = DID_ERROR << 16;
2151 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2152 cp, ei->CommandStatus);
2153 }
edd16368 2154 cmd_free(h, cp);
2cc5bfaf 2155 cmd->scsi_done(cmd);
edd16368
SC		 2156}
2157
edd16368
SC		 2158static void hpsa_pci_unmap(struct pci_dev *pdev,
2159 struct CommandList *c, int sg_used, int data_direction)
2160{
2161 int i;
edd16368 2162
50a0decf
SC		 2163 for (i = 0; i < sg_used; i++)
2164 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2165 le32_to_cpu(c->SG[i].Len),
2166 data_direction);
edd16368
SC		 2167}
2168
a2dac136 2169static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2170 struct CommandList *cp,
2171 unsigned char *buf,
2172 size_t buflen,
2173 int data_direction)
2174{
01a02ffc 2175 u64 addr64;
edd16368
SC		 2176
2177 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2178 cp->Header.SGList = 0;
50a0decf 2179 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2180 return 0;
edd16368
SC		 2181 }
2182
50a0decf 2183 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2184 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2185 /* Prevent subsequent unmap of something never mapped */
eceaae18 2186 cp->Header.SGList = 0;
50a0decf 2187 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2188 return -1;
eceaae18 2189 }
50a0decf
SC		 2190 cp->SG[0].Addr = cpu_to_le64(addr64);
2191 cp->SG[0].Len = cpu_to_le32(buflen);
2192 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2193 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2194 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2195 return 0;
edd16368
SC		 2196}
2197
25163bd5
WS		 2198#define NO_TIMEOUT ((unsigned long) -1)
2199#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2200static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2201 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2202{
2203 DECLARE_COMPLETION_ONSTACK(wait);
2204
2205 c->waiting = &wait;
25163bd5
WS		 2206 __enqueue_cmd_and_start_io(h, c, reply_queue);
2207 if (timeout_msecs == NO_TIMEOUT) {
2208 /* TODO: get rid of this no-timeout thing */
2209 wait_for_completion_io(&wait);
2210 return IO_OK;
2211 }
2212 if (!wait_for_completion_io_timeout(&wait,
2213 msecs_to_jiffies(timeout_msecs))) {
2214 dev_warn(&h->pdev->dev, "Command timed out.\n");
2215 return -ETIMEDOUT;
2216 }
2217 return IO_OK;
2218}
2219
2220static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2221 int reply_queue, unsigned long timeout_msecs)
2222{
2223 if (unlikely(lockup_detected(h))) {
2224 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2225 return IO_OK;
2226 }
2227 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2228}
2229
094963da
SC		 2230static u32 lockup_detected(struct ctlr_info *h)
2231{
2232 int cpu;
2233 u32 rc, *lockup_detected;
2234
2235 cpu = get_cpu();
2236 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2237 rc = *lockup_detected;
2238 put_cpu();
2239 return rc;
2240}
2241
9c2fc160 2242#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2243static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2244 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2245{
9c2fc160 2246 int backoff_time = 10, retry_count = 0;
25163bd5 2247 int rc;
edd16368
SC		 2248
2249 do {
7630abd0 2250 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2251 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2252 timeout_msecs);
2253 if (rc)
2254 break;
edd16368 2255 retry_count++;
9c2fc160
SC		 2256 if (retry_count > 3) {
2257 msleep(backoff_time);
2258 if (backoff_time < 1000)
2259 backoff_time *= 2;
2260 }
852af20a 2261 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2262 check_for_busy(h, c)) &&
2263 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2264 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2265 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2266 rc = -EIO;
2267 return rc;
edd16368
SC		 2268}
2269
d1e8beac
SC		 2270static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2271 struct CommandList *c)
edd16368 2272{
d1e8beac
SC		 2273 const u8 *cdb = c->Request.CDB;
2274 const u8 *lun = c->Header.LUN.LunAddrBytes;
2275
2276 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2277 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2278 txt, lun[0], lun[1], lun[2], lun[3],
2279 lun[4], lun[5], lun[6], lun[7],
2280 cdb[0], cdb[1], cdb[2], cdb[3],
2281 cdb[4], cdb[5], cdb[6], cdb[7],
2282 cdb[8], cdb[9], cdb[10], cdb[11],
2283 cdb[12], cdb[13], cdb[14], cdb[15]);
2284}
2285
2286static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2287 struct CommandList *cp)
2288{
2289 const struct ErrorInfo *ei = cp->err_info;
edd16368 2290 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2291 u8 sense_key, asc, ascq;
2292 int sense_len;
edd16368 2293
edd16368
SC		 2294 switch (ei->CommandStatus) {
2295 case CMD_TARGET_STATUS:
9437ac43
SC		 2296 if (ei->SenseLen > sizeof(ei->SenseInfo))
2297 sense_len = sizeof(ei->SenseInfo);
2298 else
2299 sense_len = ei->SenseLen;
2300 decode_sense_data(ei->SenseInfo, sense_len,
2301 &sense_key, &asc, &ascq);
d1e8beac
SC		 2302 hpsa_print_cmd(h, "SCSI status", cp);
2303 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2304 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2305 sense_key, asc, ascq);
d1e8beac 2306 else
9437ac43 2307 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2308 if (ei->ScsiStatus == 0)
2309 dev_warn(d, "SCSI status is abnormally zero. "
2310 "(probably indicates selection timeout "
2311 "reported incorrectly due to a known "
2312 "firmware bug, circa July, 2001.)\n");
2313 break;
2314 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2315 break;
2316 case CMD_DATA_OVERRUN:
d1e8beac 2317 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2318 break;
2319 case CMD_INVALID: {
2320 /* controller unfortunately reports SCSI passthru's
2321 * to non-existent targets as invalid commands.
2322 */
d1e8beac
SC		 2323 hpsa_print_cmd(h, "invalid command", cp);
2324 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2325 }
2326 break;
2327 case CMD_PROTOCOL_ERR:
d1e8beac 2328 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2329 break;
2330 case CMD_HARDWARE_ERR:
d1e8beac 2331 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2332 break;
2333 case CMD_CONNECTION_LOST:
d1e8beac 2334 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2335 break;
2336 case CMD_ABORTED:
d1e8beac 2337 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2338 break;
2339 case CMD_ABORT_FAILED:
d1e8beac 2340 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2341 break;
2342 case CMD_UNSOLICITED_ABORT:
d1e8beac 2343 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2344 break;
2345 case CMD_TIMEOUT:
d1e8beac 2346 hpsa_print_cmd(h, "timed out", cp);
edd16368 2347 break;
1d5e2ed0 2348 case CMD_UNABORTABLE:
d1e8beac 2349 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2350 break;
25163bd5
WS		 2351 case CMD_CTLR_LOCKUP:
2352 hpsa_print_cmd(h, "controller lockup detected", cp);
2353 break;
edd16368 2354 default:
d1e8beac
SC		 2355 hpsa_print_cmd(h, "unknown status", cp);
2356 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2357 ei->CommandStatus);
2358 }
2359}
2360
2361static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2362 u16 page, unsigned char *buf,
edd16368
SC		 2363 unsigned char bufsize)
2364{
2365 int rc = IO_OK;
2366 struct CommandList *c;
2367 struct ErrorInfo *ei;
2368
45fcb86e 2369 c = cmd_alloc(h);
edd16368 2370
574f05d3 2371 if (c == NULL) {
45fcb86e 2372 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2373 return -ENOMEM;
edd16368
SC		 2374 }
2375
a2dac136
SC		 2376 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2377 page, scsi3addr, TYPE_CMD)) {
2378 rc = -1;
2379 goto out;
2380 }
25163bd5
WS		 2381 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2382 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2383 if (rc)
2384 goto out;
edd16368
SC		 2385 ei = c->err_info;
2386 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2387 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2388 rc = -1;
2389 }
a2dac136 2390out:
45fcb86e 2391 cmd_free(h, c);
edd16368
SC		 2392 return rc;
2393}
2394
316b221a
SC		 2395static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2396 unsigned char *scsi3addr, unsigned char page,
2397 struct bmic_controller_parameters *buf, size_t bufsize)
2398{
2399 int rc = IO_OK;
2400 struct CommandList *c;
2401 struct ErrorInfo *ei;
2402
45fcb86e 2403 c = cmd_alloc(h);
316b221a 2404 if (c == NULL) { /* trouble... */
45fcb86e 2405 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2406 return -ENOMEM;
2407 }
2408
2409 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2410 page, scsi3addr, TYPE_CMD)) {
2411 rc = -1;
2412 goto out;
2413 }
25163bd5
WS		 2414 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2415 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2416 if (rc)
2417 goto out;
316b221a
SC		 2418 ei = c->err_info;
2419 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2420 hpsa_scsi_interpret_error(h, c);
2421 rc = -1;
2422 }
2423out:
45fcb86e 2424 cmd_free(h, c);
316b221a
SC		 2425 return rc;
2426 }
2427
bf711ac6 2428static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2429 u8 reset_type, int reply_queue)
edd16368
SC		 2430{
2431 int rc = IO_OK;
2432 struct CommandList *c;
2433 struct ErrorInfo *ei;
2434
45fcb86e 2435 c = cmd_alloc(h);
edd16368
SC		 2436
2437 if (c == NULL) { /* trouble... */
45fcb86e 2438 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2439 return -ENOMEM;
edd16368
SC		 2440 }
2441
a2dac136 2442 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2443 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2444 scsi3addr, TYPE_MSG);
2445 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2446 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2447 if (rc) {
2448 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2449 goto out;
2450 }
edd16368
SC		 2451 /* no unmap needed here because no data xfer. */
2452
2453 ei = c->err_info;
2454 if (ei->CommandStatus != 0) {
d1e8beac 2455 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2456 rc = -1;
2457 }
25163bd5 2458out:
45fcb86e 2459 cmd_free(h, c);
edd16368
SC		 2460 return rc;
2461}
2462
2463static void hpsa_get_raid_level(struct ctlr_info *h,
2464 unsigned char *scsi3addr, unsigned char *raid_level)
2465{
2466 int rc;
2467 unsigned char *buf;
2468
2469 *raid_level = RAID_UNKNOWN;
2470 buf = kzalloc(64, GFP_KERNEL);
2471 if (!buf)
2472 return;
b7bb24eb 2473 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2474 if (rc == 0)
2475 *raid_level = buf[8];
2476 if (*raid_level > RAID_UNKNOWN)
2477 *raid_level = RAID_UNKNOWN;
2478 kfree(buf);
2479 return;
2480}
2481
283b4a9b
SC		 2482#define HPSA_MAP_DEBUG
2483#ifdef HPSA_MAP_DEBUG
2484static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2485 struct raid_map_data *map_buff)
2486{
2487 struct raid_map_disk_data *dd = &map_buff->data[0];
2488 int map, row, col;
2489 u16 map_cnt, row_cnt, disks_per_row;
2490
2491 if (rc != 0)
2492 return;
2493
2ba8bfc8
SC		 2494 /* Show details only if debugging has been activated. */
2495 if (h->raid_offload_debug < 2)
2496 return;
2497
283b4a9b
SC		 2498 dev_info(&h->pdev->dev, "structure_size = %u\n",
2499 le32_to_cpu(map_buff->structure_size));
2500 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2501 le32_to_cpu(map_buff->volume_blk_size));
2502 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2503 le64_to_cpu(map_buff->volume_blk_cnt));
2504 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2505 map_buff->phys_blk_shift);
2506 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2507 map_buff->parity_rotation_shift);
2508 dev_info(&h->pdev->dev, "strip_size = %u\n",
2509 le16_to_cpu(map_buff->strip_size));
2510 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2511 le64_to_cpu(map_buff->disk_starting_blk));
2512 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2513 le64_to_cpu(map_buff->disk_blk_cnt));
2514 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2515 le16_to_cpu(map_buff->data_disks_per_row));
2516 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2517 le16_to_cpu(map_buff->metadata_disks_per_row));
2518 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2519 le16_to_cpu(map_buff->row_cnt));
2520 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2521 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2522 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2523 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2524 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2525 le16_to_cpu(map_buff->flags) &
2526 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2527 dev_info(&h->pdev->dev, "dekindex = %u\n",
2528 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2529 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2530 for (map = 0; map < map_cnt; map++) {
2531 dev_info(&h->pdev->dev, "Map%u:\n", map);
2532 row_cnt = le16_to_cpu(map_buff->row_cnt);
2533 for (row = 0; row < row_cnt; row++) {
2534 dev_info(&h->pdev->dev, " Row%u:\n", row);
2535 disks_per_row =
2536 le16_to_cpu(map_buff->data_disks_per_row);
2537 for (col = 0; col < disks_per_row; col++, dd++)
2538 dev_info(&h->pdev->dev,
2539 " D%02u: h=0x%04x xor=%u,%u\n",
2540 col, dd->ioaccel_handle,
2541 dd->xor_mult[0], dd->xor_mult[1]);
2542 disks_per_row =
2543 le16_to_cpu(map_buff->metadata_disks_per_row);
2544 for (col = 0; col < disks_per_row; col++, dd++)
2545 dev_info(&h->pdev->dev,
2546 " M%02u: h=0x%04x xor=%u,%u\n",
2547 col, dd->ioaccel_handle,
2548 dd->xor_mult[0], dd->xor_mult[1]);
2549 }
2550 }
2551}
2552#else
2553static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2554 __attribute__((unused)) int rc,
2555 __attribute__((unused)) struct raid_map_data *map_buff)
2556{
2557}
2558#endif
2559
2560static int hpsa_get_raid_map(struct ctlr_info *h,
2561 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2562{
2563 int rc = 0;
2564 struct CommandList *c;
2565 struct ErrorInfo *ei;
2566
45fcb86e 2567 c = cmd_alloc(h);
283b4a9b 2568 if (c == NULL) {
45fcb86e 2569 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2570 return -ENOMEM;
2571 }
2572 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2573 sizeof(this_device->raid_map), 0,
2574 scsi3addr, TYPE_CMD)) {
2575 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
25163bd5
WS		 2576 rc = -ENOMEM;
2577 goto out;
283b4a9b 2578 }
25163bd5
WS		 2579 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2580 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2581 if (rc)
2582 goto out;
283b4a9b
SC		 2583 ei = c->err_info;
2584 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2585 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2586 rc = -1;
2587 goto out;
283b4a9b 2588 }
45fcb86e 2589 cmd_free(h, c);
283b4a9b
SC		 2590
2591 /* @todo in the future, dynamically allocate RAID map memory */
2592 if (le32_to_cpu(this_device->raid_map.structure_size) >
2593 sizeof(this_device->raid_map)) {
2594 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2595 rc = -1;
2596 }
2597 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2598 return rc;
25163bd5
WS		 2599out:
2600 cmd_free(h, c);
2601 return rc;
283b4a9b
SC		 2602}
2603
03383736
DB		 2604static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2605 unsigned char scsi3addr[], u16 bmic_device_index,
2606 struct bmic_identify_physical_device *buf, size_t bufsize)
2607{
2608 int rc = IO_OK;
2609 struct CommandList *c;
2610 struct ErrorInfo *ei;
2611
2612 c = cmd_alloc(h);
2613 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2614 0, RAID_CTLR_LUNID, TYPE_CMD);
2615 if (rc)
2616 goto out;
2617
2618 c->Request.CDB[2] = bmic_device_index & 0xff;
2619 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2620
25163bd5
WS		 2621 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2622 NO_TIMEOUT);
03383736
DB		 2623 ei = c->err_info;
2624 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2625 hpsa_scsi_interpret_error(h, c);
2626 rc = -1;
2627 }
2628out:
2629 cmd_free(h, c);
2630 return rc;
2631}
2632
1b70150a
SC		 2633static int hpsa_vpd_page_supported(struct ctlr_info *h,
2634 unsigned char scsi3addr[], u8 page)
2635{
2636 int rc;
2637 int i;
2638 int pages;
2639 unsigned char *buf, bufsize;
2640
2641 buf = kzalloc(256, GFP_KERNEL);
2642 if (!buf)
2643 return 0;
2644
2645 /* Get the size of the page list first */
2646 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2647 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2648 buf, HPSA_VPD_HEADER_SZ);
2649 if (rc != 0)
2650 goto exit_unsupported;
2651 pages = buf[3];
2652 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2653 bufsize = pages + HPSA_VPD_HEADER_SZ;
2654 else
2655 bufsize = 255;
2656
2657 /* Get the whole VPD page list */
2658 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2659 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2660 buf, bufsize);
2661 if (rc != 0)
2662 goto exit_unsupported;
2663
2664 pages = buf[3];
2665 for (i = 1; i <= pages; i++)
2666 if (buf[3 + i] == page)
2667 goto exit_supported;
2668exit_unsupported:
2669 kfree(buf);
2670 return 0;
2671exit_supported:
2672 kfree(buf);
2673 return 1;
2674}
2675
283b4a9b
SC		 2676static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2677 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2678{
2679 int rc;
2680 unsigned char *buf;
2681 u8 ioaccel_status;
2682
2683 this_device->offload_config = 0;
2684 this_device->offload_enabled = 0;
41ce4c35 2685 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2686
2687 buf = kzalloc(64, GFP_KERNEL);
2688 if (!buf)
2689 return;
1b70150a
SC		 2690 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2691 goto out;
283b4a9b 2692 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2693 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2694 if (rc != 0)
2695 goto out;
2696
2697#define IOACCEL_STATUS_BYTE 4
2698#define OFFLOAD_CONFIGURED_BIT 0x01
2699#define OFFLOAD_ENABLED_BIT 0x02
2700 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2701 this_device->offload_config =
2702 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2703 if (this_device->offload_config) {
2704 this_device->offload_enabled =
2705 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2706 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2707 this_device->offload_enabled = 0;
2708 }
41ce4c35 2709 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 2710out:
2711 kfree(buf);
2712 return;
2713}
2714
edd16368
SC		 2715/* Get the device id from inquiry page 0x83 */
2716static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2717 unsigned char *device_id, int buflen)
2718{
2719 int rc;
2720 unsigned char *buf;
2721
2722 if (buflen > 16)
2723 buflen = 16;
2724 buf = kzalloc(64, GFP_KERNEL);
2725 if (!buf)
a84d794d 2726 return -ENOMEM;
b7bb24eb 2727 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2728 if (rc == 0)
2729 memcpy(device_id, &buf[8], buflen);
2730 kfree(buf);
2731 return rc != 0;
2732}
2733
2734static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2735 void *buf, int bufsize,
edd16368
SC		 2736 int extended_response)
2737{
2738 int rc = IO_OK;
2739 struct CommandList *c;
2740 unsigned char scsi3addr[8];
2741 struct ErrorInfo *ei;
2742
45fcb86e 2743 c = cmd_alloc(h);
edd16368 2744 if (c == NULL) { /* trouble... */
45fcb86e 2745 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2746 return -1;
2747 }
e89c0ae7
SC		 2748 /* address the controller */
2749 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2750 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2751 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2752 rc = -1;
2753 goto out;
2754 }
edd16368
SC		 2755 if (extended_response)
2756 c->Request.CDB[1] = extended_response;
25163bd5
WS		 2757 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2758 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2759 if (rc)
2760 goto out;
edd16368
SC		 2761 ei = c->err_info;
2762 if (ei->CommandStatus != 0 &&
2763 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2764 hpsa_scsi_interpret_error(h, c);
edd16368 2765 rc = -1;
283b4a9b 2766 } else {
03383736
DB		 2767 struct ReportLUNdata *rld = buf;
2768
2769 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2770 dev_err(&h->pdev->dev,
2771 "report luns requested format %u, got %u\n",
2772 extended_response,
03383736 2773 rld->extended_response_flag);
283b4a9b
SC		 2774 rc = -1;
2775 }
edd16368 2776 }
a2dac136 2777out:
45fcb86e 2778 cmd_free(h, c);
edd16368
SC		 2779 return rc;
2780}
2781
2782static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2783 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2784{
03383736
DB		 2785 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2786 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2787}
2788
2789static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2790 struct ReportLUNdata *buf, int bufsize)
2791{
2792 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2793}
2794
2795static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2796 int bus, int target, int lun)
2797{
2798 device->bus = bus;
2799 device->target = target;
2800 device->lun = lun;
2801}
2802
9846590e
SC		 2803/* Use VPD inquiry to get details of volume status */
2804static int hpsa_get_volume_status(struct ctlr_info *h,
2805 unsigned char scsi3addr[])
2806{
2807 int rc;
2808 int status;
2809 int size;
2810 unsigned char *buf;
2811
2812 buf = kzalloc(64, GFP_KERNEL);
2813 if (!buf)
2814 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2815
2816 /* Does controller have VPD for logical volume status? */
24a4b078 2817 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2818 goto exit_failed;
9846590e
SC		 2819
2820 /* Get the size of the VPD return buffer */
2821 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2822 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2823 if (rc != 0)
9846590e 2824 goto exit_failed;
9846590e
SC		 2825 size = buf[3];
2826
2827 /* Now get the whole VPD buffer */
2828 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2829 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2830 if (rc != 0)
9846590e 2831 goto exit_failed;
9846590e
SC		 2832 status = buf[4]; /* status byte */
2833
2834 kfree(buf);
2835 return status;
2836exit_failed:
2837 kfree(buf);
2838 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2839}
2840
2841/* Determine offline status of a volume.
2842 * Return either:
2843 * 0 (not offline)
67955ba3 2844 * 0xff (offline for unknown reasons)
9846590e
SC		 2845 * # (integer code indicating one of several NOT READY states
2846 * describing why a volume is to be kept offline)
2847 */
67955ba3 2848static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2849 unsigned char scsi3addr[])
2850{
2851 struct CommandList *c;
9437ac43
SC		 2852 unsigned char *sense;
2853 u8 sense_key, asc, ascq;
2854 int sense_len;
25163bd5 2855 int rc, ldstat = 0;
9846590e
SC		 2856 u16 cmd_status;
2857 u8 scsi_status;
2858#define ASC_LUN_NOT_READY 0x04
2859#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2860#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2861
2862 c = cmd_alloc(h);
2863 if (!c)
2864 return 0;
2865 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 2866 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2867 if (rc) {
2868 cmd_free(h, c);
2869 return 0;
2870 }
9846590e 2871 sense = c->err_info->SenseInfo;
9437ac43
SC		 2872 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
2873 sense_len = sizeof(c->err_info->SenseInfo);
2874 else
2875 sense_len = c->err_info->SenseLen;
2876 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 2877 cmd_status = c->err_info->CommandStatus;
2878 scsi_status = c->err_info->ScsiStatus;
2879 cmd_free(h, c);
2880 /* Is the volume 'not ready'? */
2881 if (cmd_status != CMD_TARGET_STATUS ||
2882 scsi_status != SAM_STAT_CHECK_CONDITION ||
2883 sense_key != NOT_READY ||
2884 asc != ASC_LUN_NOT_READY) {
2885 return 0;
2886 }
2887
2888 /* Determine the reason for not ready state */
2889 ldstat = hpsa_get_volume_status(h, scsi3addr);
2890
2891 /* Keep volume offline in certain cases: */
2892 switch (ldstat) {
2893 case HPSA_LV_UNDERGOING_ERASE:
2894 case HPSA_LV_UNDERGOING_RPI:
2895 case HPSA_LV_PENDING_RPI:
2896 case HPSA_LV_ENCRYPTED_NO_KEY:
2897 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2898 case HPSA_LV_UNDERGOING_ENCRYPTION:
2899 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2900 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2901 return ldstat;
2902 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2903 /* If VPD status page isn't available,
2904 * use ASC/ASCQ to determine state
2905 */
2906 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2907 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2908 return ldstat;
2909 break;
2910 default:
2911 break;
2912 }
2913 return 0;
2914}
2915
9b5c48c2
SC		 2916/*
2917 * Find out if a logical device supports aborts by simply trying one.
2918 * Smart Array may claim not to support aborts on logical drives, but
2919 * if a MSA2000 * is connected, the drives on that will be presented
2920 * by the Smart Array as logical drives, and aborts may be sent to
2921 * those devices successfully. So the simplest way to find out is
2922 * to simply try an abort and see how the device responds.
2923 */
2924static int hpsa_device_supports_aborts(struct ctlr_info *h,
2925 unsigned char *scsi3addr)
2926{
2927 struct CommandList *c;
2928 struct ErrorInfo *ei;
2929 int rc = 0;
2930
2931 u64 tag = (u64) -1; /* bogus tag */
2932
2933 /* Assume that physical devices support aborts */
2934 if (!is_logical_dev_addr_mode(scsi3addr))
2935 return 1;
2936
2937 c = cmd_alloc(h);
2938 if (!c)
2939 return -ENOMEM;
2940 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
2941 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2942 /* no unmap needed here because no data xfer. */
2943 ei = c->err_info;
2944 switch (ei->CommandStatus) {
2945 case CMD_INVALID:
2946 rc = 0;
2947 break;
2948 case CMD_UNABORTABLE:
2949 case CMD_ABORT_FAILED:
2950 rc = 1;
2951 break;
9437ac43
SC		 2952 case CMD_TMF_STATUS:
2953 rc = hpsa_evaluate_tmf_status(h, c);
2954 break;
9b5c48c2
SC		 2955 default:
2956 rc = 0;
2957 break;
2958 }
2959 cmd_free(h, c);
2960 return rc;
2961}
2962
edd16368 2963static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2964 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2965 unsigned char *is_OBDR_device)
edd16368 2966{
0b0e1d6c
SC		 2967
2968#define OBDR_SIG_OFFSET 43
2969#define OBDR_TAPE_SIG "$DR-10"
2970#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2971#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2972
ea6d3bc3 2973 unsigned char *inq_buff;
0b0e1d6c 2974 unsigned char *obdr_sig;
edd16368 2975
ea6d3bc3 2976 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2977 if (!inq_buff)
2978 goto bail_out;
2979
edd16368
SC		 2980 /* Do an inquiry to the device to see what it is. */
2981 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2982 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2983 /* Inquiry failed (msg printed already) */
2984 dev_err(&h->pdev->dev,
2985 "hpsa_update_device_info: inquiry failed\n");
2986 goto bail_out;
2987 }
2988
edd16368
SC		 2989 this_device->devtype = (inq_buff[0] & 0x1f);
2990 memcpy(this_device->scsi3addr, scsi3addr, 8);
2991 memcpy(this_device->vendor, &inq_buff[8],
2992 sizeof(this_device->vendor));
2993 memcpy(this_device->model, &inq_buff[16],
2994 sizeof(this_device->model));
edd16368
SC		 2995 memset(this_device->device_id, 0,
2996 sizeof(this_device->device_id));
2997 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2998 sizeof(this_device->device_id));
2999
3000 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3001 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3002 int volume_offline;
3003
edd16368 3004 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3005 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3006 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3007 volume_offline = hpsa_volume_offline(h, scsi3addr);
3008 if (volume_offline < 0 || volume_offline > 0xff)
3009 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3010 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3011 } else {
edd16368 3012 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3013 this_device->offload_config = 0;
3014 this_device->offload_enabled = 0;
41ce4c35 3015 this_device->offload_to_be_enabled = 0;
a3144e0b 3016 this_device->hba_ioaccel_enabled = 0;
9846590e 3017 this_device->volume_offline = 0;
03383736 3018 this_device->queue_depth = h->nr_cmds;
283b4a9b 3019 }
edd16368 3020
0b0e1d6c
SC		 3021 if (is_OBDR_device) {
3022 /* See if this is a One-Button-Disaster-Recovery device
3023 * by looking for "$DR-10" at offset 43 in inquiry data.
3024 */
3025 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3026 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3027 strncmp(obdr_sig, OBDR_TAPE_SIG,
3028 OBDR_SIG_LEN) == 0);
3029 }
edd16368
SC		 3030 kfree(inq_buff);
3031 return 0;
3032
3033bail_out:
3034 kfree(inq_buff);
3035 return 1;
3036}
3037
9b5c48c2
SC		 3038static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3039 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3040{
3041 unsigned long flags;
3042 int rc, entry;
3043 /*
3044 * See if this device supports aborts. If we already know
3045 * the device, we already know if it supports aborts, otherwise
3046 * we have to find out if it supports aborts by trying one.
3047 */
3048 spin_lock_irqsave(&h->devlock, flags);
3049 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3050 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3051 entry >= 0 && entry < h->ndevices) {
3052 dev->supports_aborts = h->dev[entry]->supports_aborts;
3053 spin_unlock_irqrestore(&h->devlock, flags);
3054 } else {
3055 spin_unlock_irqrestore(&h->devlock, flags);
3056 dev->supports_aborts =
3057 hpsa_device_supports_aborts(h, scsi3addr);
3058 if (dev->supports_aborts < 0)
3059 dev->supports_aborts = 0;
3060 }
3061}
3062
4f4eb9f1 3063static unsigned char *ext_target_model[] = {
edd16368
SC		 3064 "MSA2012",
3065 "MSA2024",
3066 "MSA2312",
3067 "MSA2324",
fda38518 3068 "P2000 G3 SAS",
e06c8e5c 3069 "MSA 2040 SAS",
edd16368
SC		 3070 NULL,
3071};
3072
4f4eb9f1 3073static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3074{
3075 int i;
3076
4f4eb9f1
ST		 3077 for (i = 0; ext_target_model[i]; i++)
3078 if (strncmp(device->model, ext_target_model[i],
3079 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3080 return 1;
3081 return 0;
3082}
3083
3084/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3085 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3086 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3087 * Logical drive target and lun are assigned at this time, but
3088 * physical device lun and target assignment are deferred (assigned
3089 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3090 */
3091static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3092 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3093{
1f310bde
SC		 3094 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3095
3096 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3097 /* physical device, target and lun filled in later */
edd16368 3098 if (is_hba_lunid(lunaddrbytes))
1f310bde 3099 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3100 else
1f310bde
SC		 3101 /* defer target, lun assignment for physical devices */
3102 hpsa_set_bus_target_lun(device, 2, -1, -1);
3103 return;
3104 }
3105 /* It's a logical device */
4f4eb9f1
ST		 3106 if (is_ext_target(h, device)) {
3107 /* external target way, put logicals on bus 1
1f310bde
SC		 3108 * and match target/lun numbers box
3109 * reports, other smart array, bus 0, target 0, match lunid
3110 */
3111 hpsa_set_bus_target_lun(device,
3112 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3113 return;
edd16368 3114 }
1f310bde 3115 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3116}
3117
3118/*
3119 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3120 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3121 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3122 * it for some reason. *tmpdevice is the target we're adding,
3123 * this_device is a pointer into the current element of currentsd[]
3124 * that we're building up in update_scsi_devices(), below.
3125 * lunzerobits is a bitmap that tracks which targets already have a
3126 * lun 0 assigned.
3127 * Returns 1 if an enclosure was added, 0 if not.
3128 */
4f4eb9f1 3129static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3130 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3131 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3132 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3133{
3134 unsigned char scsi3addr[8];
3135
1f310bde 3136 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3137 return 0; /* There is already a lun 0 on this target. */
3138
3139 if (!is_logical_dev_addr_mode(lunaddrbytes))
3140 return 0; /* It's the logical targets that may lack lun 0. */
3141
4f4eb9f1
ST		 3142 if (!is_ext_target(h, tmpdevice))
3143 return 0; /* Only external target devices have this problem. */
edd16368 3144
1f310bde 3145 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3146 return 0;
3147
c4f8a299 3148 memset(scsi3addr, 0, 8);
1f310bde 3149 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3150 if (is_hba_lunid(scsi3addr))
3151 return 0; /* Don't add the RAID controller here. */
3152
339b2b14
SC		 3153 if (is_scsi_rev_5(h))
3154 return 0; /* p1210m doesn't need to do this. */
3155
4f4eb9f1 3156 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3157 dev_warn(&h->pdev->dev, "Maximum number of external "
3158 "target devices exceeded. Check your hardware "
edd16368
SC		 3159 "configuration.");
3160 return 0;
3161 }
3162
0b0e1d6c 3163 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3164 return 0;
4f4eb9f1 3165 (*n_ext_target_devs)++;
1f310bde
SC		 3166 hpsa_set_bus_target_lun(this_device,
3167 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3168 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3169 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3170 return 1;
3171}
3172
54b6e9e9
ST		 3173/*
3174 * Get address of physical disk used for an ioaccel2 mode command:
3175 * 1. Extract ioaccel2 handle from the command.
3176 * 2. Find a matching ioaccel2 handle from list of physical disks.
3177 * 3. Return:
3178 * 1 and set scsi3addr to address of matching physical
3179 * 0 if no matching physical disk was found.
3180 */
3181static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3182 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3183{
41ce4c35
SC		 3184 struct io_accel2_cmd *c2 =
3185 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3186 unsigned long flags;
54b6e9e9 3187 int i;
54b6e9e9 3188
41ce4c35
SC		 3189 spin_lock_irqsave(&h->devlock, flags);
3190 for (i = 0; i < h->ndevices; i++)
3191 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3192 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3193 sizeof(h->dev[i]->scsi3addr));
3194 spin_unlock_irqrestore(&h->devlock, flags);
3195 return 1;
3196 }
3197 spin_unlock_irqrestore(&h->devlock, flags);
3198 return 0;
54b6e9e9 3199}
41ce4c35 3200
edd16368
SC		 3201/*
3202 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3203 * logdev. The number of luns in physdev and logdev are returned in
3204 * *nphysicals and *nlogicals, respectively.
3205 * Returns 0 on success, -1 otherwise.
3206 */
3207static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3208 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3209 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3210{
03383736 3211 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3212 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3213 return -1;
3214 }
03383736 3215 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3216 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3217 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3218 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3219 *nphysicals = HPSA_MAX_PHYS_LUN;
3220 }
03383736 3221 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3222 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3223 return -1;
3224 }
6df1e954 3225 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3226 /* Reject Logicals in excess of our max capability. */
3227 if (*nlogicals > HPSA_MAX_LUN) {
3228 dev_warn(&h->pdev->dev,
3229 "maximum logical LUNs (%d) exceeded. "
3230 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3231 *nlogicals - HPSA_MAX_LUN);
3232 *nlogicals = HPSA_MAX_LUN;
3233 }
3234 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3235 dev_warn(&h->pdev->dev,
3236 "maximum logical + physical LUNs (%d) exceeded. "
3237 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3238 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3239 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3240 }
3241 return 0;
3242}
3243
42a91641
DB		 3244static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3245 int i, int nphysicals, int nlogicals,
a93aa1fe 3246 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3247 struct ReportLUNdata *logdev_list)
3248{
3249 /* Helper function, figure out where the LUN ID info is coming from
3250 * given index i, lists of physical and logical devices, where in
3251 * the list the raid controller is supposed to appear (first or last)
3252 */
3253
3254 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3255 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3256
3257 if (i == raid_ctlr_position)
3258 return RAID_CTLR_LUNID;
3259
3260 if (i < logicals_start)
d5b5d964
SC		 3261 return &physdev_list->LUN[i -
3262 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3263
3264 if (i < last_device)
3265 return &logdev_list->LUN[i - nphysicals -
3266 (raid_ctlr_position == 0)][0];
3267 BUG();
3268 return NULL;
3269}
3270
316b221a
SC		 3271static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3272{
3273 int rc;
6e8e8088 3274 int hba_mode_enabled;
316b221a
SC		 3275 struct bmic_controller_parameters *ctlr_params;
3276 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3277 GFP_KERNEL);
3278
3279 if (!ctlr_params)
96444fbb 3280 return -ENOMEM;
316b221a
SC		 3281 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3282 sizeof(struct bmic_controller_parameters));
96444fbb 3283 if (rc) {
316b221a 3284 kfree(ctlr_params);
96444fbb 3285 return rc;
316b221a 3286 }
6e8e8088
JH		 3287
3288 hba_mode_enabled =
3289 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3290 kfree(ctlr_params);
3291 return hba_mode_enabled;
316b221a
SC		 3292}
3293
03383736
DB		 3294/* get physical drive ioaccel handle and queue depth */
3295static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3296 struct hpsa_scsi_dev_t *dev,
3297 u8 *lunaddrbytes,
3298 struct bmic_identify_physical_device *id_phys)
3299{
3300 int rc;
3301 struct ext_report_lun_entry *rle =
3302 (struct ext_report_lun_entry *) lunaddrbytes;
3303
3304 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3305 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3306 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3307 memset(id_phys, 0, sizeof(*id_phys));
3308 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3309 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3310 sizeof(*id_phys));
3311 if (!rc)
3312 /* Reserve space for FW operations */
3313#define DRIVE_CMDS_RESERVED_FOR_FW 2
3314#define DRIVE_QUEUE_DEPTH 7
3315 dev->queue_depth =
3316 le16_to_cpu(id_phys->current_queue_depth_limit) -
3317 DRIVE_CMDS_RESERVED_FOR_FW;
3318 else
3319 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3320 atomic_set(&dev->ioaccel_cmds_out, 0);
3321}
3322
edd16368
SC		 3323static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3324{
3325 /* the idea here is we could get notified
3326 * that some devices have changed, so we do a report
3327 * physical luns and report logical luns cmd, and adjust
3328 * our list of devices accordingly.
3329 *
3330 * The scsi3addr's of devices won't change so long as the
3331 * adapter is not reset. That means we can rescan and
3332 * tell which devices we already know about, vs. new
3333 * devices, vs. disappearing devices.
3334 */
a93aa1fe 3335 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3336 struct ReportLUNdata *logdev_list = NULL;
03383736 3337 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3338 u32 nphysicals = 0;
3339 u32 nlogicals = 0;
3340 u32 ndev_allocated = 0;
edd16368
SC		 3341 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3342 int ncurrent = 0;
4f4eb9f1 3343 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3344 int raid_ctlr_position;
2bbf5c7f 3345 int rescan_hba_mode;
aca4a520 3346 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3347
cfe5badc 3348 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3349 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3350 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3351 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3352 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3353
03383736
DB		 3354 if (!currentsd || !physdev_list || !logdev_list ||
3355 !tmpdevice || !id_phys) {
edd16368
SC		 3356 dev_err(&h->pdev->dev, "out of memory\n");
3357 goto out;
3358 }
3359 memset(lunzerobits, 0, sizeof(lunzerobits));
3360
316b221a 3361 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3362 if (rescan_hba_mode < 0)
3363 goto out;
316b221a
SC		 3364
3365 if (!h->hba_mode_enabled && rescan_hba_mode)
3366 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3367 else if (h->hba_mode_enabled && !rescan_hba_mode)
3368 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3369
3370 h->hba_mode_enabled = rescan_hba_mode;
3371
03383736
DB		 3372 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3373 logdev_list, &nlogicals))
edd16368
SC		 3374 goto out;
3375
aca4a520
ST		 3376 /* We might see up to the maximum number of logical and physical disks
3377 * plus external target devices, and a device for the local RAID
3378 * controller.
edd16368 3379 */
aca4a520 3380 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3381
3382 /* Allocate the per device structures */
3383 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3384 if (i >= HPSA_MAX_DEVICES) {
3385 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3386 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3387 ndevs_to_allocate - HPSA_MAX_DEVICES);
3388 break;
3389 }
3390
edd16368
SC		 3391 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3392 if (!currentsd[i]) {
3393 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3394 __FILE__, __LINE__);
3395 goto out;
3396 }
3397 ndev_allocated++;
3398 }
3399
8645291b 3400 if (is_scsi_rev_5(h))
339b2b14
SC		 3401 raid_ctlr_position = 0;
3402 else
3403 raid_ctlr_position = nphysicals + nlogicals;
3404
edd16368 3405 /* adjust our table of devices */
4f4eb9f1 3406 n_ext_target_devs = 0;
edd16368 3407 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3408 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3409
3410 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3411 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3412 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3413
3414 /* skip masked non-disk devices */
3415 if (MASKED_DEVICE(lunaddrbytes))
3416 if (i < nphysicals + (raid_ctlr_position == 0) &&
3417 NON_DISK_PHYS_DEV(lunaddrbytes))
3418 continue;
edd16368
SC		 3419
3420 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3421 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3422 &is_OBDR))
edd16368 3423 continue; /* skip it if we can't talk to it. */
1f310bde 3424 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3425 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3426 this_device = currentsd[ncurrent];
3427
3428 /*
4f4eb9f1 3429 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3430 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3431 * is nonetheless an enclosure device there. We have to
3432 * present that otherwise linux won't find anything if
3433 * there is no lun 0.
3434 */
4f4eb9f1 3435 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3436 lunaddrbytes, lunzerobits,
4f4eb9f1 3437 &n_ext_target_devs)) {
edd16368
SC		 3438 ncurrent++;
3439 this_device = currentsd[ncurrent];
3440 }
3441
3442 *this_device = *tmpdevice;
edd16368 3443
41ce4c35
SC		 3444 /* do not expose masked devices */
3445 if (MASKED_DEVICE(lunaddrbytes) &&
3446 i < nphysicals + (raid_ctlr_position == 0)) {
3447 if (h->hba_mode_enabled)
3448 dev_warn(&h->pdev->dev,
3449 "Masked physical device detected\n");
3450 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3451 } else {
3452 this_device->expose_state =
3453 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3454 }
3455
edd16368 3456 switch (this_device->devtype) {
0b0e1d6c 3457 case TYPE_ROM:
edd16368
SC		 3458 /* We don't *really* support actual CD-ROM devices,
3459 * just "One Button Disaster Recovery" tape drive
3460 * which temporarily pretends to be a CD-ROM drive.
3461 * So we check that the device is really an OBDR tape
3462 * device by checking for "$DR-10" in bytes 43-48 of
3463 * the inquiry data.
3464 */
0b0e1d6c
SC		 3465 if (is_OBDR)
3466 ncurrent++;
edd16368
SC		 3467 break;
3468 case TYPE_DISK:
ecf418d1 3469 if (i >= nphysicals) {
316b221a
SC		 3470 ncurrent++;
3471 break;
283b4a9b 3472 }
ecf418d1
JH		 3473
3474 if (h->hba_mode_enabled)
3475 /* never use raid mapper in HBA mode */
3476 this_device->offload_enabled = 0;
3477 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3478 h->transMethod & CFGTBL_Trans_io_accel2))
3479 break;
3480
3481 hpsa_get_ioaccel_drive_info(h, this_device,
3482 lunaddrbytes, id_phys);
3483 atomic_set(&this_device->ioaccel_cmds_out, 0);
3484 ncurrent++;
edd16368
SC		 3485 break;
3486 case TYPE_TAPE:
3487 case TYPE_MEDIUM_CHANGER:
3488 ncurrent++;
3489 break;
41ce4c35
SC		 3490 case TYPE_ENCLOSURE:
3491 if (h->hba_mode_enabled)
3492 ncurrent++;
3493 break;
edd16368
SC		 3494 case TYPE_RAID:
3495 /* Only present the Smartarray HBA as a RAID controller.
3496 * If it's a RAID controller other than the HBA itself
3497 * (an external RAID controller, MSA500 or similar)
3498 * don't present it.
3499 */
3500 if (!is_hba_lunid(lunaddrbytes))
3501 break;
3502 ncurrent++;
3503 break;
3504 default:
3505 break;
3506 }
cfe5badc 3507 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3508 break;
3509 }
3510 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3511out:
3512 kfree(tmpdevice);
3513 for (i = 0; i < ndev_allocated; i++)
3514 kfree(currentsd[i]);
3515 kfree(currentsd);
edd16368
SC		 3516 kfree(physdev_list);
3517 kfree(logdev_list);
03383736 3518 kfree(id_phys);
edd16368
SC		 3519}
3520
ec5cbf04
WS		 3521static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3522 struct scatterlist *sg)
3523{
3524 u64 addr64 = (u64) sg_dma_address(sg);
3525 unsigned int len = sg_dma_len(sg);
3526
3527 desc->Addr = cpu_to_le64(addr64);
3528 desc->Len = cpu_to_le32(len);
3529 desc->Ext = 0;
3530}
3531
c7ee65b3
WS		 3532/*
3533 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3534 * dma mapping and fills in the scatter gather entries of the
3535 * hpsa command, cp.
3536 */
33a2ffce 3537static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3538 struct CommandList *cp,
3539 struct scsi_cmnd *cmd)
3540{
edd16368 3541 struct scatterlist *sg;
33a2ffce
SC		 3542 int use_sg, i, sg_index, chained;
3543 struct SGDescriptor *curr_sg;
edd16368 3544
33a2ffce 3545 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3546
3547 use_sg = scsi_dma_map(cmd);
3548 if (use_sg < 0)
3549 return use_sg;
3550
3551 if (!use_sg)
3552 goto sglist_finished;
3553
33a2ffce
SC		 3554 curr_sg = cp->SG;
3555 chained = 0;
3556 sg_index = 0;
edd16368 3557 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3558 if (i == h->max_cmd_sg_entries - 1 &&
3559 use_sg > h->max_cmd_sg_entries) {
3560 chained = 1;
3561 curr_sg = h->cmd_sg_list[cp->cmdindex];
3562 sg_index = 0;
3563 }
ec5cbf04 3564 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3565 curr_sg++;
3566 }
ec5cbf04
WS		 3567
3568 /* Back the pointer up to the last entry and mark it as "last". */
50a0decf 3569 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3570
3571 if (use_sg + chained > h->maxSG)
3572 h->maxSG = use_sg + chained;
3573
3574 if (chained) {
3575 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3576 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3577 if (hpsa_map_sg_chain_block(h, cp)) {
3578 scsi_dma_unmap(cmd);
3579 return -1;
3580 }
33a2ffce 3581 return 0;
edd16368
SC		 3582 }
3583
3584sglist_finished:
3585
01a02ffc 3586 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3587 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3588 return 0;
3589}
3590
283b4a9b
SC		 3591#define IO_ACCEL_INELIGIBLE (1)
3592static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3593{
3594 int is_write = 0;
3595 u32 block;
3596 u32 block_cnt;
3597
3598 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3599 switch (cdb[0]) {
3600 case WRITE_6:
3601 case WRITE_12:
3602 is_write = 1;
3603 case READ_6:
3604 case READ_12:
3605 if (*cdb_len == 6) {
3606 block = (((u32) cdb[2]) << 8) | cdb[3];
3607 block_cnt = cdb[4];
3608 } else {
3609 BUG_ON(*cdb_len != 12);
3610 block = (((u32) cdb[2]) << 24) |
3611 (((u32) cdb[3]) << 16) |
3612 (((u32) cdb[4]) << 8) |
3613 cdb[5];
3614 block_cnt =
3615 (((u32) cdb[6]) << 24) |
3616 (((u32) cdb[7]) << 16) |
3617 (((u32) cdb[8]) << 8) |
3618 cdb[9];
3619 }
3620 if (block_cnt > 0xffff)
3621 return IO_ACCEL_INELIGIBLE;
3622
3623 cdb[0] = is_write ? WRITE_10 : READ_10;
3624 cdb[1] = 0;
3625 cdb[2] = (u8) (block >> 24);
3626 cdb[3] = (u8) (block >> 16);
3627 cdb[4] = (u8) (block >> 8);
3628 cdb[5] = (u8) (block);
3629 cdb[6] = 0;
3630 cdb[7] = (u8) (block_cnt >> 8);
3631 cdb[8] = (u8) (block_cnt);
3632 cdb[9] = 0;
3633 *cdb_len = 10;
3634 break;
3635 }
3636 return 0;
3637}
3638
c349775e 3639static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3640 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3641 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3642{
3643 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3644 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3645 unsigned int len;
3646 unsigned int total_len = 0;
3647 struct scatterlist *sg;
3648 u64 addr64;
3649 int use_sg, i;
3650 struct SGDescriptor *curr_sg;
3651 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3652
283b4a9b 3653 /* TODO: implement chaining support */
03383736
DB		 3654 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3655 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3656 return IO_ACCEL_INELIGIBLE;
03383736 3657 }
283b4a9b 3658
e1f7de0c
MG		 3659 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3660
03383736
DB		 3661 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3662 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3663 return IO_ACCEL_INELIGIBLE;
03383736 3664 }
283b4a9b 3665
e1f7de0c
MG		 3666 c->cmd_type = CMD_IOACCEL1;
3667
3668 /* Adjust the DMA address to point to the accelerated command buffer */
3669 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3670 (c->cmdindex * sizeof(*cp));
3671 BUG_ON(c->busaddr & 0x0000007F);
3672
3673 use_sg = scsi_dma_map(cmd);
03383736
DB		 3674 if (use_sg < 0) {
3675 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3676 return use_sg;
03383736 3677 }
e1f7de0c
MG		 3678
3679 if (use_sg) {
3680 curr_sg = cp->SG;
3681 scsi_for_each_sg(cmd, sg, use_sg, i) {
3682 addr64 = (u64) sg_dma_address(sg);
3683 len = sg_dma_len(sg);
3684 total_len += len;
50a0decf
SC		 3685 curr_sg->Addr = cpu_to_le64(addr64);
3686 curr_sg->Len = cpu_to_le32(len);
3687 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3688 curr_sg++;
3689 }
50a0decf 3690 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3691
3692 switch (cmd->sc_data_direction) {
3693 case DMA_TO_DEVICE:
3694 control |= IOACCEL1_CONTROL_DATA_OUT;
3695 break;
3696 case DMA_FROM_DEVICE:
3697 control |= IOACCEL1_CONTROL_DATA_IN;
3698 break;
3699 case DMA_NONE:
3700 control |= IOACCEL1_CONTROL_NODATAXFER;
3701 break;
3702 default:
3703 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3704 cmd->sc_data_direction);
3705 BUG();
3706 break;
3707 }
3708 } else {
3709 control |= IOACCEL1_CONTROL_NODATAXFER;
3710 }
3711
c349775e 3712 c->Header.SGList = use_sg;
e1f7de0c 3713 /* Fill out the command structure to submit */
2b08b3e9
DB		 3714 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3715 cp->transfer_len = cpu_to_le32(total_len);
3716 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3717 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3718 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3719 memcpy(cp->CDB, cdb, cdb_len);
3720 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3721 /* Tag was already set at init time. */
283b4a9b 3722 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3723 return 0;
3724}
edd16368 3725
283b4a9b
SC		 3726/*
3727 * Queue a command directly to a device behind the controller using the
3728 * I/O accelerator path.
3729 */
3730static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3731 struct CommandList *c)
3732{
3733 struct scsi_cmnd *cmd = c->scsi_cmd;
3734 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3735
03383736
DB		 3736 c->phys_disk = dev;
3737
283b4a9b 3738 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3739 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3740}
3741
dd0e19f3
ST		 3742/*
3743 * Set encryption parameters for the ioaccel2 request
3744 */
3745static void set_encrypt_ioaccel2(struct ctlr_info *h,
3746 struct CommandList *c, struct io_accel2_cmd *cp)
3747{
3748 struct scsi_cmnd *cmd = c->scsi_cmd;
3749 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3750 struct raid_map_data *map = &dev->raid_map;
3751 u64 first_block;
3752
dd0e19f3 3753 /* Are we doing encryption on this device */
2b08b3e9 3754 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3755 return;
3756 /* Set the data encryption key index. */
3757 cp->dekindex = map->dekindex;
3758
3759 /* Set the encryption enable flag, encoded into direction field. */
3760 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3761
3762 /* Set encryption tweak values based on logical block address
3763 * If block size is 512, tweak value is LBA.
3764 * For other block sizes, tweak is (LBA * block size)/ 512)
3765 */
3766 switch (cmd->cmnd[0]) {
3767 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3768 case WRITE_6:
3769 case READ_6:
2b08b3e9 3770 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3771 break;
3772 case WRITE_10:
3773 case READ_10:
dd0e19f3
ST		 3774 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3775 case WRITE_12:
3776 case READ_12:
2b08b3e9 3777 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3778 break;
3779 case WRITE_16:
3780 case READ_16:
2b08b3e9 3781 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3782 break;
3783 default:
3784 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3785 "ERROR: %s: size (0x%x) not supported for encryption\n",
3786 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3787 BUG();
3788 break;
3789 }
2b08b3e9
DB		 3790
3791 if (le32_to_cpu(map->volume_blk_size) != 512)
3792 first_block = first_block *
3793 le32_to_cpu(map->volume_blk_size)/512;
3794
3795 cp->tweak_lower = cpu_to_le32(first_block);
3796 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3797}
3798
c349775e
ST		 3799static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3800 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3801 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3802{
3803 struct scsi_cmnd *cmd = c->scsi_cmd;
3804 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3805 struct ioaccel2_sg_element *curr_sg;
3806 int use_sg, i;
3807 struct scatterlist *sg;
3808 u64 addr64;
3809 u32 len;
3810 u32 total_len = 0;
3811
03383736
DB		 3812 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3813 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3814 return IO_ACCEL_INELIGIBLE;
03383736 3815 }
c349775e 3816
03383736
DB		 3817 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3818 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3819 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3820 }
3821
c349775e
ST		 3822 c->cmd_type = CMD_IOACCEL2;
3823 /* Adjust the DMA address to point to the accelerated command buffer */
3824 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3825 (c->cmdindex * sizeof(*cp));
3826 BUG_ON(c->busaddr & 0x0000007F);
3827
3828 memset(cp, 0, sizeof(*cp));
3829 cp->IU_type = IOACCEL2_IU_TYPE;
3830
3831 use_sg = scsi_dma_map(cmd);
03383736
DB		 3832 if (use_sg < 0) {
3833 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3834 return use_sg;
03383736 3835 }
c349775e
ST		 3836
3837 if (use_sg) {
3838 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3839 curr_sg = cp->sg;
3840 scsi_for_each_sg(cmd, sg, use_sg, i) {
3841 addr64 = (u64) sg_dma_address(sg);
3842 len = sg_dma_len(sg);
3843 total_len += len;
3844 curr_sg->address = cpu_to_le64(addr64);
3845 curr_sg->length = cpu_to_le32(len);
3846 curr_sg->reserved[0] = 0;
3847 curr_sg->reserved[1] = 0;
3848 curr_sg->reserved[2] = 0;
3849 curr_sg->chain_indicator = 0;
3850 curr_sg++;
3851 }
3852
3853 switch (cmd->sc_data_direction) {
3854 case DMA_TO_DEVICE:
dd0e19f3
ST		 3855 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3856 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3857 break;
3858 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3859 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3860 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3861 break;
3862 case DMA_NONE:
dd0e19f3
ST		 3863 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3864 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3865 break;
3866 default:
3867 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3868 cmd->sc_data_direction);
3869 BUG();
3870 break;
3871 }
3872 } else {
dd0e19f3
ST		 3873 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3874 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3875 }
dd0e19f3
ST		 3876
3877 /* Set encryption parameters, if necessary */
3878 set_encrypt_ioaccel2(h, c, cp);
3879
2b08b3e9 3880 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3881 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3882 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3883
3884 /* fill in sg elements */
3885 cp->sg_count = (u8) use_sg;
3886
3887 cp->data_len = cpu_to_le32(total_len);
3888 cp->err_ptr = cpu_to_le64(c->busaddr +
3889 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3890 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3891
3892 enqueue_cmd_and_start_io(h, c);
3893 return 0;
3894}
3895
3896/*
3897 * Queue a command to the correct I/O accelerator path.
3898 */
3899static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3900 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3901 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 3902{
03383736
DB		 3903 /* Try to honor the device's queue depth */
3904 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
3905 phys_disk->queue_depth) {
3906 atomic_dec(&phys_disk->ioaccel_cmds_out);
3907 return IO_ACCEL_INELIGIBLE;
3908 }
c349775e
ST		 3909 if (h->transMethod & CFGTBL_Trans_io_accel1)
3910 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 3911 cdb, cdb_len, scsi3addr,
3912 phys_disk);
c349775e
ST		 3913 else
3914 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 3915 cdb, cdb_len, scsi3addr,
3916 phys_disk);
c349775e
ST		 3917}
3918
6b80b18f
ST		 3919static void raid_map_helper(struct raid_map_data *map,
3920 int offload_to_mirror, u32 *map_index, u32 *current_group)
3921{
3922 if (offload_to_mirror == 0) {
3923 /* use physical disk in the first mirrored group. */
2b08b3e9 3924 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3925 return;
3926 }
3927 do {
3928 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3929 *current_group = *map_index /
3930 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3931 if (offload_to_mirror == *current_group)
3932 continue;
2b08b3e9 3933 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3934 /* select map index from next group */
2b08b3e9 3935 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3936 (*current_group)++;
3937 } else {
3938 /* select map index from first group */
2b08b3e9 3939 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3940 *current_group = 0;
3941 }
3942 } while (offload_to_mirror != *current_group);
3943}
3944
283b4a9b
SC		 3945/*
3946 * Attempt to perform offload RAID mapping for a logical volume I/O.
3947 */
3948static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3949 struct CommandList *c)
3950{
3951 struct scsi_cmnd *cmd = c->scsi_cmd;
3952 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3953 struct raid_map_data *map = &dev->raid_map;
3954 struct raid_map_disk_data *dd = &map->data[0];
3955 int is_write = 0;
3956 u32 map_index;
3957 u64 first_block, last_block;
3958 u32 block_cnt;
3959 u32 blocks_per_row;
3960 u64 first_row, last_row;
3961 u32 first_row_offset, last_row_offset;
3962 u32 first_column, last_column;
6b80b18f
ST		 3963 u64 r0_first_row, r0_last_row;
3964 u32 r5or6_blocks_per_row;
3965 u64 r5or6_first_row, r5or6_last_row;
3966 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3967 u32 r5or6_first_column, r5or6_last_column;
3968 u32 total_disks_per_row;
3969 u32 stripesize;
3970 u32 first_group, last_group, current_group;
283b4a9b
SC		 3971 u32 map_row;
3972 u32 disk_handle;
3973 u64 disk_block;
3974 u32 disk_block_cnt;
3975 u8 cdb[16];
3976 u8 cdb_len;
2b08b3e9 3977 u16 strip_size;
283b4a9b
SC		 3978#if BITS_PER_LONG == 32
3979 u64 tmpdiv;
3980#endif
6b80b18f 3981 int offload_to_mirror;
283b4a9b 3982
283b4a9b
SC		 3983 /* check for valid opcode, get LBA and block count */
3984 switch (cmd->cmnd[0]) {
3985 case WRITE_6:
3986 is_write = 1;
3987 case READ_6:
3988 first_block =
3989 (((u64) cmd->cmnd[2]) << 8) |
3990 cmd->cmnd[3];
3991 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3992 if (block_cnt == 0)
3993 block_cnt = 256;
283b4a9b
SC		 3994 break;
3995 case WRITE_10:
3996 is_write = 1;
3997 case READ_10:
3998 first_block =
3999 (((u64) cmd->cmnd[2]) << 24) |
4000 (((u64) cmd->cmnd[3]) << 16) |
4001 (((u64) cmd->cmnd[4]) << 8) |
4002 cmd->cmnd[5];
4003 block_cnt =
4004 (((u32) cmd->cmnd[7]) << 8) |
4005 cmd->cmnd[8];
4006 break;
4007 case WRITE_12:
4008 is_write = 1;
4009 case READ_12:
4010 first_block =
4011 (((u64) cmd->cmnd[2]) << 24) |
4012 (((u64) cmd->cmnd[3]) << 16) |
4013 (((u64) cmd->cmnd[4]) << 8) |
4014 cmd->cmnd[5];
4015 block_cnt =
4016 (((u32) cmd->cmnd[6]) << 24) |
4017 (((u32) cmd->cmnd[7]) << 16) |
4018 (((u32) cmd->cmnd[8]) << 8) |
4019 cmd->cmnd[9];
4020 break;
4021 case WRITE_16:
4022 is_write = 1;
4023 case READ_16:
4024 first_block =
4025 (((u64) cmd->cmnd[2]) << 56) |
4026 (((u64) cmd->cmnd[3]) << 48) |
4027 (((u64) cmd->cmnd[4]) << 40) |
4028 (((u64) cmd->cmnd[5]) << 32) |
4029 (((u64) cmd->cmnd[6]) << 24) |
4030 (((u64) cmd->cmnd[7]) << 16) |
4031 (((u64) cmd->cmnd[8]) << 8) |
4032 cmd->cmnd[9];
4033 block_cnt =
4034 (((u32) cmd->cmnd[10]) << 24) |
4035 (((u32) cmd->cmnd[11]) << 16) |
4036 (((u32) cmd->cmnd[12]) << 8) |
4037 cmd->cmnd[13];
4038 break;
4039 default:
4040 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4041 }
283b4a9b
SC		 4042 last_block = first_block + block_cnt - 1;
4043
4044 /* check for write to non-RAID-0 */
4045 if (is_write && dev->raid_level != 0)
4046 return IO_ACCEL_INELIGIBLE;
4047
4048 /* check for invalid block or wraparound */
2b08b3e9
DB		 4049 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4050 last_block < first_block)
283b4a9b
SC		 4051 return IO_ACCEL_INELIGIBLE;
4052
4053 /* calculate stripe information for the request */
2b08b3e9
DB		 4054 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4055 le16_to_cpu(map->strip_size);
4056 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4057#if BITS_PER_LONG == 32
4058 tmpdiv = first_block;
4059 (void) do_div(tmpdiv, blocks_per_row);
4060 first_row = tmpdiv;
4061 tmpdiv = last_block;
4062 (void) do_div(tmpdiv, blocks_per_row);
4063 last_row = tmpdiv;
4064 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4065 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4066 tmpdiv = first_row_offset;
2b08b3e9 4067 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4068 first_column = tmpdiv;
4069 tmpdiv = last_row_offset;
2b08b3e9 4070 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4071 last_column = tmpdiv;
4072#else
4073 first_row = first_block / blocks_per_row;
4074 last_row = last_block / blocks_per_row;
4075 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4076 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4077 first_column = first_row_offset / strip_size;
4078 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4079#endif
4080
4081 /* if this isn't a single row/column then give to the controller */
4082 if ((first_row != last_row) || (first_column != last_column))
4083 return IO_ACCEL_INELIGIBLE;
4084
4085 /* proceeding with driver mapping */
2b08b3e9
DB		 4086 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4087 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4088 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4089 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4090 map_index = (map_row * total_disks_per_row) + first_column;
4091
4092 switch (dev->raid_level) {
4093 case HPSA_RAID_0:
4094 break; /* nothing special to do */
4095 case HPSA_RAID_1:
4096 /* Handles load balance across RAID 1 members.
4097 * (2-drive R1 and R10 with even # of drives.)
4098 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4099 */
2b08b3e9 4100 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4101 if (dev->offload_to_mirror)
2b08b3e9 4102 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4103 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4104 break;
4105 case HPSA_RAID_ADM:
4106 /* Handles N-way mirrors (R1-ADM)
4107 * and R10 with # of drives divisible by 3.)
4108 */
2b08b3e9 4109 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4110
4111 offload_to_mirror = dev->offload_to_mirror;
4112 raid_map_helper(map, offload_to_mirror,
4113 &map_index, &current_group);
4114 /* set mirror group to use next time */
4115 offload_to_mirror =
2b08b3e9
DB		 4116 (offload_to_mirror >=
4117 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4118 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4119 dev->offload_to_mirror = offload_to_mirror;
4120 /* Avoid direct use of dev->offload_to_mirror within this
4121 * function since multiple threads might simultaneously
4122 * increment it beyond the range of dev->layout_map_count -1.
4123 */
4124 break;
4125 case HPSA_RAID_5:
4126 case HPSA_RAID_6:
2b08b3e9 4127 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4128 break;
4129
4130 /* Verify first and last block are in same RAID group */
4131 r5or6_blocks_per_row =
2b08b3e9
DB		 4132 le16_to_cpu(map->strip_size) *
4133 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4134 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4135 stripesize = r5or6_blocks_per_row *
4136 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4137#if BITS_PER_LONG == 32
4138 tmpdiv = first_block;
4139 first_group = do_div(tmpdiv, stripesize);
4140 tmpdiv = first_group;
4141 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4142 first_group = tmpdiv;
4143 tmpdiv = last_block;
4144 last_group = do_div(tmpdiv, stripesize);
4145 tmpdiv = last_group;
4146 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4147 last_group = tmpdiv;
4148#else
4149 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4150 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4151#endif
000ff7c2 4152 if (first_group != last_group)
6b80b18f
ST		 4153 return IO_ACCEL_INELIGIBLE;
4154
4155 /* Verify request is in a single row of RAID 5/6 */
4156#if BITS_PER_LONG == 32
4157 tmpdiv = first_block;
4158 (void) do_div(tmpdiv, stripesize);
4159 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4160 tmpdiv = last_block;
4161 (void) do_div(tmpdiv, stripesize);
4162 r5or6_last_row = r0_last_row = tmpdiv;
4163#else
4164 first_row = r5or6_first_row = r0_first_row =
4165 first_block / stripesize;
4166 r5or6_last_row = r0_last_row = last_block / stripesize;
4167#endif
4168 if (r5or6_first_row != r5or6_last_row)
4169 return IO_ACCEL_INELIGIBLE;
4170
4171
4172 /* Verify request is in a single column */
4173#if BITS_PER_LONG == 32
4174 tmpdiv = first_block;
4175 first_row_offset = do_div(tmpdiv, stripesize);
4176 tmpdiv = first_row_offset;
4177 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4178 r5or6_first_row_offset = first_row_offset;
4179 tmpdiv = last_block;
4180 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4181 tmpdiv = r5or6_last_row_offset;
4182 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4183 tmpdiv = r5or6_first_row_offset;
4184 (void) do_div(tmpdiv, map->strip_size);
4185 first_column = r5or6_first_column = tmpdiv;
4186 tmpdiv = r5or6_last_row_offset;
4187 (void) do_div(tmpdiv, map->strip_size);
4188 r5or6_last_column = tmpdiv;
4189#else
4190 first_row_offset = r5or6_first_row_offset =
4191 (u32)((first_block % stripesize) %
4192 r5or6_blocks_per_row);
4193
4194 r5or6_last_row_offset =
4195 (u32)((last_block % stripesize) %
4196 r5or6_blocks_per_row);
4197
4198 first_column = r5or6_first_column =
2b08b3e9 4199 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4200 r5or6_last_column =
2b08b3e9 4201 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4202#endif
4203 if (r5or6_first_column != r5or6_last_column)
4204 return IO_ACCEL_INELIGIBLE;
4205
4206 /* Request is eligible */
4207 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4208 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4209
4210 map_index = (first_group *
2b08b3e9 4211 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4212 (map_row * total_disks_per_row) + first_column;
4213 break;
4214 default:
4215 return IO_ACCEL_INELIGIBLE;
283b4a9b 4216 }
6b80b18f 4217
07543e0c
SC		 4218 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4219 return IO_ACCEL_INELIGIBLE;
4220
03383736
DB		 4221 c->phys_disk = dev->phys_disk[map_index];
4222
283b4a9b 4223 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4224 disk_block = le64_to_cpu(map->disk_starting_blk) +
4225 first_row * le16_to_cpu(map->strip_size) +
4226 (first_row_offset - first_column *
4227 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4228 disk_block_cnt = block_cnt;
4229
4230 /* handle differing logical/physical block sizes */
4231 if (map->phys_blk_shift) {
4232 disk_block <<= map->phys_blk_shift;
4233 disk_block_cnt <<= map->phys_blk_shift;
4234 }
4235 BUG_ON(disk_block_cnt > 0xffff);
4236
4237 /* build the new CDB for the physical disk I/O */
4238 if (disk_block > 0xffffffff) {
4239 cdb[0] = is_write ? WRITE_16 : READ_16;
4240 cdb[1] = 0;
4241 cdb[2] = (u8) (disk_block >> 56);
4242 cdb[3] = (u8) (disk_block >> 48);
4243 cdb[4] = (u8) (disk_block >> 40);
4244 cdb[5] = (u8) (disk_block >> 32);
4245 cdb[6] = (u8) (disk_block >> 24);
4246 cdb[7] = (u8) (disk_block >> 16);
4247 cdb[8] = (u8) (disk_block >> 8);
4248 cdb[9] = (u8) (disk_block);
4249 cdb[10] = (u8) (disk_block_cnt >> 24);
4250 cdb[11] = (u8) (disk_block_cnt >> 16);
4251 cdb[12] = (u8) (disk_block_cnt >> 8);
4252 cdb[13] = (u8) (disk_block_cnt);
4253 cdb[14] = 0;
4254 cdb[15] = 0;
4255 cdb_len = 16;
4256 } else {
4257 cdb[0] = is_write ? WRITE_10 : READ_10;
4258 cdb[1] = 0;
4259 cdb[2] = (u8) (disk_block >> 24);
4260 cdb[3] = (u8) (disk_block >> 16);
4261 cdb[4] = (u8) (disk_block >> 8);
4262 cdb[5] = (u8) (disk_block);
4263 cdb[6] = 0;
4264 cdb[7] = (u8) (disk_block_cnt >> 8);
4265 cdb[8] = (u8) (disk_block_cnt);
4266 cdb[9] = 0;
4267 cdb_len = 10;
4268 }
4269 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4270 dev->scsi3addr,
4271 dev->phys_disk[map_index]);
283b4a9b
SC		 4272}
4273
25163bd5
WS		 4274/*
4275 * Submit commands down the "normal" RAID stack path
4276 * All callers to hpsa_ciss_submit must check lockup_detected
4277 * beforehand, before (opt.) and after calling cmd_alloc
4278 */
574f05d3
SC		 4279static int hpsa_ciss_submit(struct ctlr_info *h,
4280 struct CommandList *c, struct scsi_cmnd *cmd,
4281 unsigned char scsi3addr[])
edd16368 4282{
edd16368 4283 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4284 c->cmd_type = CMD_SCSI;
4285 c->scsi_cmd = cmd;
4286 c->Header.ReplyQueue = 0; /* unused in simple mode */
4287 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4288 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4289
4290 /* Fill in the request block... */
4291
4292 c->Request.Timeout = 0;
edd16368
SC		 4293 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4294 c->Request.CDBLen = cmd->cmd_len;
4295 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4296 switch (cmd->sc_data_direction) {
4297 case DMA_TO_DEVICE:
a505b86f
SC		 4298 c->Request.type_attr_dir =
4299 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4300 break;
4301 case DMA_FROM_DEVICE:
a505b86f
SC		 4302 c->Request.type_attr_dir =
4303 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4304 break;
4305 case DMA_NONE:
a505b86f
SC		 4306 c->Request.type_attr_dir =
4307 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4308 break;
4309 case DMA_BIDIRECTIONAL:
4310 /* This can happen if a buggy application does a scsi passthru
4311 * and sets both inlen and outlen to non-zero. ( see
4312 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4313 */
4314
a505b86f
SC		 4315 c->Request.type_attr_dir =
4316 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4317 /* This is technically wrong, and hpsa controllers should
4318 * reject it with CMD_INVALID, which is the most correct
4319 * response, but non-fibre backends appear to let it
4320 * slide by, and give the same results as if this field
4321 * were set correctly. Either way is acceptable for
4322 * our purposes here.
4323 */
4324
4325 break;
4326
4327 default:
4328 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4329 cmd->sc_data_direction);
4330 BUG();
4331 break;
4332 }
4333
33a2ffce 4334 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4335 cmd_free(h, c);
4336 return SCSI_MLQUEUE_HOST_BUSY;
4337 }
4338 enqueue_cmd_and_start_io(h, c);
4339 /* the cmd'll come back via intr handler in complete_scsi_command() */
4340 return 0;
4341}
4342
360c73bd
SC		 4343static void hpsa_cmd_init(struct ctlr_info *h, int index,
4344 struct CommandList *c)
4345{
4346 dma_addr_t cmd_dma_handle, err_dma_handle;
4347
4348 /* Zero out all of commandlist except the last field, refcount */
4349 memset(c, 0, offsetof(struct CommandList, refcount));
4350 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4351 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4352 c->err_info = h->errinfo_pool + index;
4353 memset(c->err_info, 0, sizeof(*c->err_info));
4354 err_dma_handle = h->errinfo_pool_dhandle
4355 + index * sizeof(*c->err_info);
4356 c->cmdindex = index;
4357 c->busaddr = (u32) cmd_dma_handle;
4358 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4359 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4360 c->h = h;
4361}
4362
4363static void hpsa_preinitialize_commands(struct ctlr_info *h)
4364{
4365 int i;
4366
4367 for (i = 0; i < h->nr_cmds; i++) {
4368 struct CommandList *c = h->cmd_pool + i;
4369
4370 hpsa_cmd_init(h, i, c);
4371 atomic_set(&c->refcount, 0);
4372 }
4373}
4374
4375static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4376 struct CommandList *c)
4377{
4378 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4379
4380 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4381 memset(c->err_info, 0, sizeof(*c->err_info));
4382 c->busaddr = (u32) cmd_dma_handle;
4383}
4384
592a0ad5
WS		 4385static int hpsa_ioaccel_submit(struct ctlr_info *h,
4386 struct CommandList *c, struct scsi_cmnd *cmd,
4387 unsigned char *scsi3addr)
4388{
4389 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4390 int rc = IO_ACCEL_INELIGIBLE;
4391
4392 cmd->host_scribble = (unsigned char *) c;
4393
4394 if (dev->offload_enabled) {
4395 hpsa_cmd_init(h, c->cmdindex, c);
4396 c->cmd_type = CMD_SCSI;
4397 c->scsi_cmd = cmd;
4398 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4399 if (rc < 0) /* scsi_dma_map failed. */
4400 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4401 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4402 hpsa_cmd_init(h, c->cmdindex, c);
4403 c->cmd_type = CMD_SCSI;
4404 c->scsi_cmd = cmd;
4405 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4406 if (rc < 0) /* scsi_dma_map failed. */
4407 rc = SCSI_MLQUEUE_HOST_BUSY;
4408 }
4409 return rc;
4410}
4411
080ef1cc
DB		 4412static void hpsa_command_resubmit_worker(struct work_struct *work)
4413{
4414 struct scsi_cmnd *cmd;
4415 struct hpsa_scsi_dev_t *dev;
4416 struct CommandList *c =
4417 container_of(work, struct CommandList, work);
4418
4419 cmd = c->scsi_cmd;
4420 dev = cmd->device->hostdata;
4421 if (!dev) {
4422 cmd->result = DID_NO_CONNECT << 16;
592a0ad5 4423 cmd_free(c->h, c);
080ef1cc
DB		 4424 cmd->scsi_done(cmd);
4425 return;
4426 }
592a0ad5
WS		 4427 if (c->cmd_type == CMD_IOACCEL2) {
4428 struct ctlr_info *h = c->h;
4429 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4430 int rc;
4431
4432 if (c2->error_data.serv_response ==
4433 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4434 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4435 if (rc == 0)
4436 return;
4437 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4438 /*
4439 * If we get here, it means dma mapping failed.
4440 * Try again via scsi mid layer, which will
4441 * then get SCSI_MLQUEUE_HOST_BUSY.
4442 */
4443 cmd->result = DID_IMM_RETRY << 16;
4444 cmd->scsi_done(cmd);
4445 cmd_free(h, c); /* FIX-ME: on merge, change
4446 * to cmd_tagged_free() and
4447 * ultimately to
4448 * hpsa_cmd_free_and_done(). */
4449 return;
4450 }
4451 /* else, fall thru and resubmit down CISS path */
4452 }
4453 }
360c73bd 4454 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4455 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4456 /*
4457 * If we get here, it means dma mapping failed. Try
4458 * again via scsi mid layer, which will then get
4459 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4460 *
4461 * hpsa_ciss_submit will have already freed c
4462 * if it encountered a dma mapping failure.
080ef1cc
DB		 4463 */
4464 cmd->result = DID_IMM_RETRY << 16;
4465 cmd->scsi_done(cmd);
4466 }
4467}
4468
574f05d3
SC		 4469/* Running in struct Scsi_Host->host_lock less mode */
4470static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4471{
4472 struct ctlr_info *h;
4473 struct hpsa_scsi_dev_t *dev;
4474 unsigned char scsi3addr[8];
4475 struct CommandList *c;
4476 int rc = 0;
4477
4478 /* Get the ptr to our adapter structure out of cmd->host. */
4479 h = sdev_to_hba(cmd->device);
4480 dev = cmd->device->hostdata;
4481 if (!dev) {
4482 cmd->result = DID_NO_CONNECT << 16;
4483 cmd->scsi_done(cmd);
4484 return 0;
4485 }
4486 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4487
4488 if (unlikely(lockup_detected(h))) {
25163bd5 4489 cmd->result = DID_NO_CONNECT << 16;
574f05d3
SC		 4490 cmd->scsi_done(cmd);
4491 return 0;
4492 }
4493 c = cmd_alloc(h);
4494 if (c == NULL) { /* trouble... */
4495 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4496 return SCSI_MLQUEUE_HOST_BUSY;
4497 }
407863cb 4498 if (unlikely(lockup_detected(h))) {
25163bd5 4499 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4500 cmd_free(h, c);
4501 cmd->scsi_done(cmd);
4502 return 0;
4503 }
574f05d3 4504
407863cb
SC		 4505 /*
4506 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4507 * Retries always go down the normal I/O path.
4508 */
4509 if (likely(cmd->retries == 0 &&
4510 cmd->request->cmd_type == REQ_TYPE_FS &&
4511 h->acciopath_status)) {
592a0ad5
WS		 4512 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4513 if (rc == 0)
4514 return 0;
4515 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4516 cmd_free(h, c); /* FIX-ME: on merge, change to
4517 * cmd_tagged_free(), and ultimately
4518 * to hpsa_cmd_resolve_and_free(). */
4519 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4520 }
4521 }
4522 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4523}
4524
8ebc9248 4525static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4526{
4527 unsigned long flags;
4528
8ebc9248
WS		 4529 spin_lock_irqsave(&h->scan_lock, flags);
4530 h->scan_finished = 1;
4531 wake_up_all(&h->scan_wait_queue);
4532 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4533}
4534
a08a8471
SC		 4535static void hpsa_scan_start(struct Scsi_Host *sh)
4536{
4537 struct ctlr_info *h = shost_to_hba(sh);
4538 unsigned long flags;
4539
8ebc9248
WS		 4540 /*
4541 * Don't let rescans be initiated on a controller known to be locked
4542 * up. If the controller locks up *during* a rescan, that thread is
4543 * probably hosed, but at least we can prevent new rescan threads from
4544 * piling up on a locked up controller.
4545 */
4546 if (unlikely(lockup_detected(h)))
4547 return hpsa_scan_complete(h);
5f389360 4548
a08a8471
SC		 4549 /* wait until any scan already in progress is finished. */
4550 while (1) {
4551 spin_lock_irqsave(&h->scan_lock, flags);
4552 if (h->scan_finished)
4553 break;
4554 spin_unlock_irqrestore(&h->scan_lock, flags);
4555 wait_event(h->scan_wait_queue, h->scan_finished);
4556 /* Note: We don't need to worry about a race between this
4557 * thread and driver unload because the midlayer will
4558 * have incremented the reference count, so unload won't
4559 * happen if we're in here.
4560 */
4561 }
4562 h->scan_finished = 0; /* mark scan as in progress */
4563 spin_unlock_irqrestore(&h->scan_lock, flags);
4564
8ebc9248
WS		 4565 if (unlikely(lockup_detected(h)))
4566 return hpsa_scan_complete(h);
5f389360 4567
a08a8471
SC		 4568 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4569
8ebc9248 4570 hpsa_scan_complete(h);
a08a8471
SC		 4571}
4572
7c0a0229
DB		 4573static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4574{
03383736
DB		 4575 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4576
4577 if (!logical_drive)
4578 return -ENODEV;
7c0a0229
DB		 4579
4580 if (qdepth < 1)
4581 qdepth = 1;
03383736
DB		 4582 else if (qdepth > logical_drive->queue_depth)
4583 qdepth = logical_drive->queue_depth;
4584
4585 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4586}
4587
a08a8471
SC		 4588static int hpsa_scan_finished(struct Scsi_Host *sh,
4589 unsigned long elapsed_time)
4590{
4591 struct ctlr_info *h = shost_to_hba(sh);
4592 unsigned long flags;
4593 int finished;
4594
4595 spin_lock_irqsave(&h->scan_lock, flags);
4596 finished = h->scan_finished;
4597 spin_unlock_irqrestore(&h->scan_lock, flags);
4598 return finished;
4599}
4600
edd16368
SC		 4601static void hpsa_unregister_scsi(struct ctlr_info *h)
4602{
4603 /* we are being forcibly unloaded, and may not refuse. */
4604 scsi_remove_host(h->scsi_host);
4605 scsi_host_put(h->scsi_host);
4606 h->scsi_host = NULL;
4607}
4608
4609static int hpsa_register_scsi(struct ctlr_info *h)
4610{
b705690d
SC		 4611 struct Scsi_Host *sh;
4612 int error;
edd16368 4613
b705690d
SC		 4614 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4615 if (sh == NULL)
4616 goto fail;
4617
4618 sh->io_port = 0;
4619 sh->n_io_port = 0;
4620 sh->this_id = -1;
4621 sh->max_channel = 3;
4622 sh->max_cmd_len = MAX_COMMAND_SIZE;
4623 sh->max_lun = HPSA_MAX_LUN;
4624 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4625 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4626 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4627 sh->sg_tablesize = h->maxsgentries;
4628 h->scsi_host = sh;
4629 sh->hostdata[0] = (unsigned long) h;
4630 sh->irq = h->intr[h->intr_mode];
4631 sh->unique_id = sh->irq;
4632 error = scsi_add_host(sh, &h->pdev->dev);
4633 if (error)
4634 goto fail_host_put;
4635 scsi_scan_host(sh);
4636 return 0;
4637
4638 fail_host_put:
4639 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4640 " failed for controller %d\n", __func__, h->ctlr);
4641 scsi_host_put(sh);
4642 return error;
4643 fail:
4644 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4645 " failed for controller %d\n", __func__, h->ctlr);
4646 return -ENOMEM;
edd16368
SC		 4647}
4648
4649static int wait_for_device_to_become_ready(struct ctlr_info *h,
4650 unsigned char lunaddr[])
4651{
8919358e 4652 int rc;
edd16368
SC		 4653 int count = 0;
4654 int waittime = 1; /* seconds */
4655 struct CommandList *c;
4656
45fcb86e 4657 c = cmd_alloc(h);
edd16368
SC		 4658 if (!c) {
4659 dev_warn(&h->pdev->dev, "out of memory in "
4660 "wait_for_device_to_become_ready.\n");
4661 return IO_ERROR;
4662 }
4663
4664 /* Send test unit ready until device ready, or give up. */
4665 while (count < HPSA_TUR_RETRY_LIMIT) {
4666
4667 /* Wait for a bit. do this first, because if we send
4668 * the TUR right away, the reset will just abort it.
4669 */
4670 msleep(1000 * waittime);
4671 count++;
8919358e 4672 rc = 0; /* Device ready. */
edd16368
SC		 4673
4674 /* Increase wait time with each try, up to a point. */
4675 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4676 waittime = waittime * 2;
4677
a2dac136
SC		 4678 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4679 (void) fill_cmd(c, TEST_UNIT_READY, h,
4680 NULL, 0, 0, lunaddr, TYPE_CMD);
25163bd5
WS		 4681 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
4682 NO_TIMEOUT);
4683 if (rc)
4684 goto do_it_again;
edd16368
SC		 4685 /* no unmap needed here because no data xfer. */
4686
4687 if (c->err_info->CommandStatus == CMD_SUCCESS)
4688 break;
4689
4690 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4691 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4692 (c->err_info->SenseInfo[2] == NO_SENSE ||
4693 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4694 break;
25163bd5 4695do_it_again:
edd16368
SC		 4696 dev_warn(&h->pdev->dev, "waiting %d secs "
4697 "for device to become ready.\n", waittime);
4698 rc = 1; /* device not ready. */
4699 }
4700
4701 if (rc)
4702 dev_warn(&h->pdev->dev, "giving up on device.\n");
4703 else
4704 dev_warn(&h->pdev->dev, "device is ready.\n");
4705
45fcb86e 4706 cmd_free(h, c);
edd16368
SC		 4707 return rc;
4708}
4709
4710/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4711 * complaining. Doing a host- or bus-reset can't do anything good here.
4712 */
4713static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4714{
4715 int rc;
4716 struct ctlr_info *h;
4717 struct hpsa_scsi_dev_t *dev;
4718
4719 /* find the controller to which the command to be aborted was sent */
4720 h = sdev_to_hba(scsicmd->device);
4721 if (h == NULL) /* paranoia */
4722 return FAILED;
e345893b
DB		 4723
4724 if (lockup_detected(h))
4725 return FAILED;
4726
edd16368
SC		 4727 dev = scsicmd->device->hostdata;
4728 if (!dev) {
4729 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4730 "device lookup failed.\n");
4731 return FAILED;
4732 }
25163bd5
WS		 4733
4734 /* if controller locked up, we can guarantee command won't complete */
4735 if (lockup_detected(h)) {
4736 dev_warn(&h->pdev->dev,
4737 "scsi %d:%d:%d:%d RESET FAILED, lockup detected\n",
4738 h->scsi_host->host_no, dev->bus, dev->target,
4739 dev->lun);
4740 return FAILED;
4741 }
4742
4743 /* this reset request might be the result of a lockup; check */
4744 if (detect_controller_lockup(h)) {
4745 dev_warn(&h->pdev->dev,
4746 "scsi %d:%d:%d:%d RESET FAILED, new lockup detected\n",
4747 h->scsi_host->host_no, dev->bus, dev->target,
4748 dev->lun);
4749 return FAILED;
4750 }
4751
4752 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
4753
edd16368 4754 /* send a reset to the SCSI LUN which the command was sent to */
25163bd5
WS		 4755 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
4756 DEFAULT_REPLY_QUEUE);
edd16368
SC		 4757 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4758 return SUCCESS;
4759
25163bd5
WS		 4760 dev_warn(&h->pdev->dev,
4761 "scsi %d:%d:%d:%d reset failed\n",
4762 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 4763 return FAILED;
4764}
4765
6cba3f19
SC		 4766static void swizzle_abort_tag(u8 *tag)
4767{
4768 u8 original_tag[8];
4769
4770 memcpy(original_tag, tag, 8);
4771 tag[0] = original_tag[3];
4772 tag[1] = original_tag[2];
4773 tag[2] = original_tag[1];
4774 tag[3] = original_tag[0];
4775 tag[4] = original_tag[7];
4776 tag[5] = original_tag[6];
4777 tag[6] = original_tag[5];
4778 tag[7] = original_tag[4];
4779}
4780
17eb87d2 4781static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4782 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4783{
2b08b3e9 4784 u64 tag;
17eb87d2
ST		 4785 if (c->cmd_type == CMD_IOACCEL1) {
4786 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4787 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4788 tag = le64_to_cpu(cm1->tag);
4789 *tagupper = cpu_to_le32(tag >> 32);
4790 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4791 return;
4792 }
4793 if (c->cmd_type == CMD_IOACCEL2) {
4794 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4795 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4796 /* upper tag not used in ioaccel2 mode */
4797 memset(tagupper, 0, sizeof(*tagupper));
4798 *taglower = cm2->Tag;
54b6e9e9 4799 return;
17eb87d2 4800 }
2b08b3e9
DB		 4801 tag = le64_to_cpu(c->Header.tag);
4802 *tagupper = cpu_to_le32(tag >> 32);
4803 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4804}
4805
75167d2c 4806static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 4807 struct CommandList *abort, int reply_queue)
75167d2c
SC		 4808{
4809 int rc = IO_OK;
4810 struct CommandList *c;
4811 struct ErrorInfo *ei;
2b08b3e9 4812 __le32 tagupper, taglower;
75167d2c 4813
45fcb86e 4814 c = cmd_alloc(h);
75167d2c 4815 if (c == NULL) { /* trouble... */
45fcb86e 4816 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4817 return -ENOMEM;
4818 }
4819
a2dac136 4820 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 4821 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 4822 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 4823 if (h->needs_abort_tags_swizzled)
6cba3f19 4824 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 4825 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 4826 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4827 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 4828 __func__, tagupper, taglower);
75167d2c
SC		 4829 /* no unmap needed here because no data xfer. */
4830
4831 ei = c->err_info;
4832 switch (ei->CommandStatus) {
4833 case CMD_SUCCESS:
4834 break;
9437ac43
SC		 4835 case CMD_TMF_STATUS:
4836 rc = hpsa_evaluate_tmf_status(h, c);
4837 break;
75167d2c
SC		 4838 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4839 rc = -1;
4840 break;
4841 default:
4842 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4843 __func__, tagupper, taglower);
d1e8beac 4844 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4845 rc = -1;
4846 break;
4847 }
45fcb86e 4848 cmd_free(h, c);
dd0e19f3
ST		 4849 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4850 __func__, tagupper, taglower);
75167d2c
SC		 4851 return rc;
4852}
4853
54b6e9e9
ST		 4854/* ioaccel2 path firmware cannot handle abort task requests.
4855 * Change abort requests to physical target reset, and send to the
4856 * address of the physical disk used for the ioaccel 2 command.
4857 * Return 0 on success (IO_OK)
4858 * -1 on failure
4859 */
4860
4861static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 4862 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 4863{
4864 int rc = IO_OK;
4865 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4866 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4867 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4868 unsigned char *psa = &phys_scsi3addr[0];
4869
4870 /* Get a pointer to the hpsa logical device. */
7fa3030c 4871 scmd = abort->scsi_cmd;
54b6e9e9
ST		 4872 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4873 if (dev == NULL) {
4874 dev_warn(&h->pdev->dev,
4875 "Cannot abort: no device pointer for command.\n");
4876 return -1; /* not abortable */
4877 }
4878
2ba8bfc8
SC		 4879 if (h->raid_offload_debug > 0)
4880 dev_info(&h->pdev->dev,
0d96ef5f 4881 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 4882 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 4883 "Reset as abort",
2ba8bfc8
SC		 4884 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4885 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4886
54b6e9e9
ST		 4887 if (!dev->offload_enabled) {
4888 dev_warn(&h->pdev->dev,
4889 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4890 return -1; /* not abortable */
4891 }
4892
4893 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4894 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4895 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4896 return -1; /* not abortable */
4897 }
4898
4899 /* send the reset */
2ba8bfc8
SC		 4900 if (h->raid_offload_debug > 0)
4901 dev_info(&h->pdev->dev,
4902 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4903 psa[0], psa[1], psa[2], psa[3],
4904 psa[4], psa[5], psa[6], psa[7]);
25163bd5 4905 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 4906 if (rc != 0) {
4907 dev_warn(&h->pdev->dev,
4908 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4909 psa[0], psa[1], psa[2], psa[3],
4910 psa[4], psa[5], psa[6], psa[7]);
4911 return rc; /* failed to reset */
4912 }
4913
4914 /* wait for device to recover */
4915 if (wait_for_device_to_become_ready(h, psa) != 0) {
4916 dev_warn(&h->pdev->dev,
4917 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4918 psa[0], psa[1], psa[2], psa[3],
4919 psa[4], psa[5], psa[6], psa[7]);
4920 return -1; /* failed to recover */
4921 }
4922
4923 /* device recovered */
4924 dev_info(&h->pdev->dev,
4925 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4926 psa[0], psa[1], psa[2], psa[3],
4927 psa[4], psa[5], psa[6], psa[7]);
4928
4929 return rc; /* success */
4930}
4931
6cba3f19 4932static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 4933 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 4934{
54b6e9e9
ST		 4935 /* ioccelerator mode 2 commands should be aborted via the
4936 * accelerated path, since RAID path is unaware of these commands,
4937 * but underlying firmware can't handle abort TMF.
4938 * Change abort to physical device reset.
4939 */
4940 if (abort->cmd_type == CMD_IOACCEL2)
25163bd5
WS		 4941 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
4942 abort, reply_queue);
9b5c48c2 4943 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 4944}
54b6e9e9 4945
25163bd5
WS		 4946/* Find out which reply queue a command was meant to return on */
4947static int hpsa_extract_reply_queue(struct ctlr_info *h,
4948 struct CommandList *c)
4949{
4950 if (c->cmd_type == CMD_IOACCEL2)
4951 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
4952 return c->Header.ReplyQueue;
6cba3f19
SC		 4953}
4954
9b5c48c2
SC		 4955/*
4956 * Limit concurrency of abort commands to prevent
4957 * over-subscription of commands
4958 */
4959static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
4960{
4961#define ABORT_CMD_WAIT_MSECS 5000
4962 return !wait_event_timeout(h->abort_cmd_wait_queue,
4963 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
4964 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
4965}
4966
75167d2c
SC		 4967/* Send an abort for the specified command.
4968 * If the device and controller support it,
4969 * send a task abort request.
4970 */
4971static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4972{
4973
4974 int i, rc;
4975 struct ctlr_info *h;
4976 struct hpsa_scsi_dev_t *dev;
4977 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4978 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4979 char msg[256]; /* For debug messaging. */
4980 int ml = 0;
2b08b3e9 4981 __le32 tagupper, taglower;
25163bd5
WS		 4982 int refcount, reply_queue;
4983
4984 if (sc == NULL)
4985 return FAILED;
75167d2c 4986
9b5c48c2
SC		 4987 if (sc->device == NULL)
4988 return FAILED;
4989
75167d2c
SC		 4990 /* Find the controller of the command to be aborted */
4991 h = sdev_to_hba(sc->device);
9b5c48c2 4992 if (h == NULL)
75167d2c
SC		 4993 return FAILED;
4994
25163bd5
WS		 4995 /* Find the device of the command to be aborted */
4996 dev = sc->device->hostdata;
4997 if (!dev) {
4998 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4999 msg);
e345893b 5000 return FAILED;
25163bd5
WS		 5001 }
5002
5003 /* If controller locked up, we can guarantee command won't complete */
5004 if (lockup_detected(h)) {
5005 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5006 "ABORT FAILED, lockup detected");
5007 return FAILED;
5008 }
5009
5010 /* This is a good time to check if controller lockup has occurred */
5011 if (detect_controller_lockup(h)) {
5012 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5013 "ABORT FAILED, new lockup detected");
5014 return FAILED;
5015 }
e345893b 5016
75167d2c
SC		 5017 /* Check that controller supports some kind of task abort */
5018 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5019 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5020 return FAILED;
5021
5022 memset(msg, 0, sizeof(msg));
0d96ef5f 5023 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s",
75167d2c 5024 h->scsi_host->host_no, sc->device->channel,
0d96ef5f
WS		 5025 sc->device->id, sc->device->lun,
5026 "Aborting command");
75167d2c 5027
75167d2c
SC		 5028 /* Get SCSI command to be aborted */
5029 abort = (struct CommandList *) sc->host_scribble;
5030 if (abort == NULL) {
281a7fd0
WS		 5031 /* This can happen if the command already completed. */
5032 return SUCCESS;
5033 }
5034 refcount = atomic_inc_return(&abort->refcount);
5035 if (refcount == 1) { /* Command is done already. */
5036 cmd_free(h, abort);
5037 return SUCCESS;
75167d2c 5038 }
9b5c48c2
SC		 5039
5040 /* Don't bother trying the abort if we know it won't work. */
5041 if (abort->cmd_type != CMD_IOACCEL2 &&
5042 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5043 cmd_free(h, abort);
5044 return FAILED;
5045 }
5046
17eb87d2 5047 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5048 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5049 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5050 as = abort->scsi_cmd;
75167d2c
SC		 5051 if (as != NULL)
5052 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
5053 as->cmnd[0], as->serial_number);
5054 dev_dbg(&h->pdev->dev, "%s\n", msg);
0d96ef5f 5055 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
75167d2c
SC		 5056 /*
5057 * Command is in flight, or possibly already completed
5058 * by the firmware (but not to the scsi mid layer) but we can't
5059 * distinguish which. Send the abort down.
5060 */
9b5c48c2
SC		 5061 if (wait_for_available_abort_cmd(h)) {
5062 dev_warn(&h->pdev->dev,
5063 "Timed out waiting for an abort command to become available.\n");
5064 cmd_free(h, abort);
5065 return FAILED;
5066 }
25163bd5 5067 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5068 atomic_inc(&h->abort_cmds_available);
5069 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5070 if (rc != 0) {
0d96ef5f
WS		 5071 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5072 "FAILED to abort command");
281a7fd0 5073 cmd_free(h, abort);
75167d2c
SC		 5074 return FAILED;
5075 }
5076 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
5077
5078 /* If the abort(s) above completed and actually aborted the
5079 * command, then the command to be aborted should already be
5080 * completed. If not, wait around a bit more to see if they
5081 * manage to complete normally.
5082 */
5083#define ABORT_COMPLETE_WAIT_SECS 30
5084 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 5085 refcount = atomic_read(&abort->refcount);
5086 if (refcount < 2) {
5087 cmd_free(h, abort);
75167d2c 5088 return SUCCESS;
281a7fd0
WS		 5089 } else {
5090 msleep(100);
5091 }
75167d2c
SC		 5092 }
5093 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
5094 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 5095 cmd_free(h, abort);
75167d2c
SC		 5096 return FAILED;
5097}
5098
edd16368
SC		 5099/*
5100 * For operations that cannot sleep, a command block is allocated at init,
5101 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5102 * which ones are free or in use. Lock must be held when calling this.
5103 * cmd_free() is the complement.
5104 */
281a7fd0 5105
edd16368
SC		 5106static struct CommandList *cmd_alloc(struct ctlr_info *h)
5107{
5108 struct CommandList *c;
360c73bd 5109 int refcount, i;
33811026 5110 unsigned long offset;
4c413128 5111
33811026
RE		 5112 /*
5113 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5114 * multiple threads could get in here, and one thread could
5115 * be scanning through the list of bits looking for a free
5116 * one, but the free ones are always behind him, and other
5117 * threads sneak in behind him and eat them before he can
5118 * get to them, so that while there is always a free one, a
5119 * very unlucky thread might be starved anyway, never able to
5120 * beat the other threads. In reality, this happens so
5121 * infrequently as to be indistinguishable from never.
5122 */
edd16368 5123
33811026 5124 offset = h->last_allocation; /* benignly racy */
281a7fd0
WS		 5125 for (;;) {
5126 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
5127 if (unlikely(i == h->nr_cmds)) {
5128 offset = 0;
5129 continue;
5130 }
5131 c = h->cmd_pool + i;
5132 refcount = atomic_inc_return(&c->refcount);
5133 if (unlikely(refcount > 1)) {
5134 cmd_free(h, c); /* already in use */
5135 offset = (i + 1) % h->nr_cmds;
5136 continue;
5137 }
5138 set_bit(i & (BITS_PER_LONG - 1),
5139 h->cmd_pool_bits + (i / BITS_PER_LONG));
5140 break; /* it's ours now. */
5141 }
33811026 5142 h->last_allocation = i; /* benignly racy */
360c73bd 5143 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5144 return c;
5145}
5146
edd16368
SC		 5147static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5148{
281a7fd0
WS		 5149 if (atomic_dec_and_test(&c->refcount)) {
5150 int i;
edd16368 5151
281a7fd0
WS		 5152 i = c - h->cmd_pool;
5153 clear_bit(i & (BITS_PER_LONG - 1),
5154 h->cmd_pool_bits + (i / BITS_PER_LONG));
5155 }
edd16368
SC		 5156}
5157
edd16368
SC		 5158#ifdef CONFIG_COMPAT
5159
42a91641
DB		 5160static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5161 void __user *arg)
edd16368
SC		 5162{
5163 IOCTL32_Command_struct __user *arg32 =
5164 (IOCTL32_Command_struct __user *) arg;
5165 IOCTL_Command_struct arg64;
5166 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5167 int err;
5168 u32 cp;
5169
938abd84 5170 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5171 err = 0;
5172 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5173 sizeof(arg64.LUN_info));
5174 err |= copy_from_user(&arg64.Request, &arg32->Request,
5175 sizeof(arg64.Request));
5176 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5177 sizeof(arg64.error_info));
5178 err |= get_user(arg64.buf_size, &arg32->buf_size);
5179 err |= get_user(cp, &arg32->buf);
5180 arg64.buf = compat_ptr(cp);
5181 err |= copy_to_user(p, &arg64, sizeof(arg64));
5182
5183 if (err)
5184 return -EFAULT;
5185
42a91641 5186 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5187 if (err)
5188 return err;
5189 err |= copy_in_user(&arg32->error_info, &p->error_info,
5190 sizeof(arg32->error_info));
5191 if (err)
5192 return -EFAULT;
5193 return err;
5194}
5195
5196static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5197 int cmd, void __user *arg)
edd16368
SC		 5198{
5199 BIG_IOCTL32_Command_struct __user *arg32 =
5200 (BIG_IOCTL32_Command_struct __user *) arg;
5201 BIG_IOCTL_Command_struct arg64;
5202 BIG_IOCTL_Command_struct __user *p =
5203 compat_alloc_user_space(sizeof(arg64));
5204 int err;
5205 u32 cp;
5206
938abd84 5207 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5208 err = 0;
5209 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5210 sizeof(arg64.LUN_info));
5211 err |= copy_from_user(&arg64.Request, &arg32->Request,
5212 sizeof(arg64.Request));
5213 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5214 sizeof(arg64.error_info));
5215 err |= get_user(arg64.buf_size, &arg32->buf_size);
5216 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5217 err |= get_user(cp, &arg32->buf);
5218 arg64.buf = compat_ptr(cp);
5219 err |= copy_to_user(p, &arg64, sizeof(arg64));
5220
5221 if (err)
5222 return -EFAULT;
5223
42a91641 5224 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5225 if (err)
5226 return err;
5227 err |= copy_in_user(&arg32->error_info, &p->error_info,
5228 sizeof(arg32->error_info));
5229 if (err)
5230 return -EFAULT;
5231 return err;
5232}
71fe75a7 5233
42a91641 5234static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5235{
5236 switch (cmd) {
5237 case CCISS_GETPCIINFO:
5238 case CCISS_GETINTINFO:
5239 case CCISS_SETINTINFO:
5240 case CCISS_GETNODENAME:
5241 case CCISS_SETNODENAME:
5242 case CCISS_GETHEARTBEAT:
5243 case CCISS_GETBUSTYPES:
5244 case CCISS_GETFIRMVER:
5245 case CCISS_GETDRIVVER:
5246 case CCISS_REVALIDVOLS:
5247 case CCISS_DEREGDISK:
5248 case CCISS_REGNEWDISK:
5249 case CCISS_REGNEWD:
5250 case CCISS_RESCANDISK:
5251 case CCISS_GETLUNINFO:
5252 return hpsa_ioctl(dev, cmd, arg);
5253
5254 case CCISS_PASSTHRU32:
5255 return hpsa_ioctl32_passthru(dev, cmd, arg);
5256 case CCISS_BIG_PASSTHRU32:
5257 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5258
5259 default:
5260 return -ENOIOCTLCMD;
5261 }
5262}
edd16368
SC		 5263#endif
5264
5265static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5266{
5267 struct hpsa_pci_info pciinfo;
5268
5269 if (!argp)
5270 return -EINVAL;
5271 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5272 pciinfo.bus = h->pdev->bus->number;
5273 pciinfo.dev_fn = h->pdev->devfn;
5274 pciinfo.board_id = h->board_id;
5275 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5276 return -EFAULT;
5277 return 0;
5278}
5279
5280static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5281{
5282 DriverVer_type DriverVer;
5283 unsigned char vmaj, vmin, vsubmin;
5284 int rc;
5285
5286 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5287 &vmaj, &vmin, &vsubmin);
5288 if (rc != 3) {
5289 dev_info(&h->pdev->dev, "driver version string '%s' "
5290 "unrecognized.", HPSA_DRIVER_VERSION);
5291 vmaj = 0;
5292 vmin = 0;
5293 vsubmin = 0;
5294 }
5295 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5296 if (!argp)
5297 return -EINVAL;
5298 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5299 return -EFAULT;
5300 return 0;
5301}
5302
5303static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5304{
5305 IOCTL_Command_struct iocommand;
5306 struct CommandList *c;
5307 char *buff = NULL;
50a0decf 5308 u64 temp64;
c1f63c8f 5309 int rc = 0;
edd16368
SC		 5310
5311 if (!argp)
5312 return -EINVAL;
5313 if (!capable(CAP_SYS_RAWIO))
5314 return -EPERM;
5315 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5316 return -EFAULT;
5317 if ((iocommand.buf_size < 1) &&
5318 (iocommand.Request.Type.Direction != XFER_NONE)) {
5319 return -EINVAL;
5320 }
5321 if (iocommand.buf_size > 0) {
5322 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5323 if (buff == NULL)
5324 return -EFAULT;
9233fb10 5325 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5326 /* Copy the data into the buffer we created */
5327 if (copy_from_user(buff, iocommand.buf,
5328 iocommand.buf_size)) {
c1f63c8f
SC		 5329 rc = -EFAULT;
5330 goto out_kfree;
b03a7771
SC		 5331 }
5332 } else {
5333 memset(buff, 0, iocommand.buf_size);
edd16368 5334 }
b03a7771 5335 }
45fcb86e 5336 c = cmd_alloc(h);
edd16368 5337 if (c == NULL) {
c1f63c8f
SC		 5338 rc = -ENOMEM;
5339 goto out_kfree;
edd16368
SC		 5340 }
5341 /* Fill in the command type */
5342 c->cmd_type = CMD_IOCTL_PEND;
5343 /* Fill in Command Header */
5344 c->Header.ReplyQueue = 0; /* unused in simple mode */
5345 if (iocommand.buf_size > 0) { /* buffer to fill */
5346 c->Header.SGList = 1;
50a0decf 5347 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5348 } else { /* no buffers to fill */
5349 c->Header.SGList = 0;
50a0decf 5350 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5351 }
5352 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5353
5354 /* Fill in Request block */
5355 memcpy(&c->Request, &iocommand.Request,
5356 sizeof(c->Request));
5357
5358 /* Fill in the scatter gather information */
5359 if (iocommand.buf_size > 0) {
50a0decf 5360 temp64 = pci_map_single(h->pdev, buff,
edd16368 5361 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5362 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5363 c->SG[0].Addr = cpu_to_le64(0);
5364 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5365 rc = -ENOMEM;
5366 goto out;
5367 }
50a0decf
SC		 5368 c->SG[0].Addr = cpu_to_le64(temp64);
5369 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5370 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5371 }
25163bd5 5372 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5373 if (iocommand.buf_size > 0)
5374 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5375 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5376 if (rc) {
5377 rc = -EIO;
5378 goto out;
5379 }
edd16368
SC		 5380
5381 /* Copy the error information out */
5382 memcpy(&iocommand.error_info, c->err_info,
5383 sizeof(iocommand.error_info));
5384 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5385 rc = -EFAULT;
5386 goto out;
edd16368 5387 }
9233fb10 5388 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5389 iocommand.buf_size > 0) {
edd16368
SC		 5390 /* Copy the data out of the buffer we created */
5391 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5392 rc = -EFAULT;
5393 goto out;
edd16368
SC		 5394 }
5395 }
c1f63c8f 5396out:
45fcb86e 5397 cmd_free(h, c);
c1f63c8f
SC		 5398out_kfree:
5399 kfree(buff);
5400 return rc;
edd16368
SC		 5401}
5402
5403static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5404{
5405 BIG_IOCTL_Command_struct *ioc;
5406 struct CommandList *c;
5407 unsigned char **buff = NULL;
5408 int *buff_size = NULL;
50a0decf 5409 u64 temp64;
edd16368
SC		 5410 BYTE sg_used = 0;
5411 int status = 0;
01a02ffc
SC		 5412 u32 left;
5413 u32 sz;
edd16368
SC		 5414 BYTE __user *data_ptr;
5415
5416 if (!argp)
5417 return -EINVAL;
5418 if (!capable(CAP_SYS_RAWIO))
5419 return -EPERM;
5420 ioc = (BIG_IOCTL_Command_struct *)
5421 kmalloc(sizeof(*ioc), GFP_KERNEL);
5422 if (!ioc) {
5423 status = -ENOMEM;
5424 goto cleanup1;
5425 }
5426 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5427 status = -EFAULT;
5428 goto cleanup1;
5429 }
5430 if ((ioc->buf_size < 1) &&
5431 (ioc->Request.Type.Direction != XFER_NONE)) {
5432 status = -EINVAL;
5433 goto cleanup1;
5434 }
5435 /* Check kmalloc limits using all SGs */
5436 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5437 status = -EINVAL;
5438 goto cleanup1;
5439 }
d66ae08b 5440 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5441 status = -EINVAL;
5442 goto cleanup1;
5443 }
d66ae08b 5444 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5445 if (!buff) {
5446 status = -ENOMEM;
5447 goto cleanup1;
5448 }
d66ae08b 5449 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5450 if (!buff_size) {
5451 status = -ENOMEM;
5452 goto cleanup1;
5453 }
5454 left = ioc->buf_size;
5455 data_ptr = ioc->buf;
5456 while (left) {
5457 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5458 buff_size[sg_used] = sz;
5459 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5460 if (buff[sg_used] == NULL) {
5461 status = -ENOMEM;
5462 goto cleanup1;
5463 }
9233fb10 5464 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5465 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5466 status = -EFAULT;
edd16368
SC		 5467 goto cleanup1;
5468 }
5469 } else
5470 memset(buff[sg_used], 0, sz);
5471 left -= sz;
5472 data_ptr += sz;
5473 sg_used++;
5474 }
45fcb86e 5475 c = cmd_alloc(h);
edd16368
SC		 5476 if (c == NULL) {
5477 status = -ENOMEM;
5478 goto cleanup1;
5479 }
5480 c->cmd_type = CMD_IOCTL_PEND;
5481 c->Header.ReplyQueue = 0;
50a0decf
SC		 5482 c->Header.SGList = (u8) sg_used;
5483 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5484 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5485 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5486 if (ioc->buf_size > 0) {
5487 int i;
5488 for (i = 0; i < sg_used; i++) {
50a0decf 5489 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5490 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5491 if (dma_mapping_error(&h->pdev->dev,
5492 (dma_addr_t) temp64)) {
5493 c->SG[i].Addr = cpu_to_le64(0);
5494 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5495 hpsa_pci_unmap(h->pdev, c, i,
5496 PCI_DMA_BIDIRECTIONAL);
5497 status = -ENOMEM;
e2d4a1f6 5498 goto cleanup0;
bcc48ffa 5499 }
50a0decf
SC		 5500 c->SG[i].Addr = cpu_to_le64(temp64);
5501 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5502 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5503 }
50a0decf 5504 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5505 }
25163bd5 5506 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 5507 if (sg_used)
5508 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 5509 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5510 if (status) {
5511 status = -EIO;
5512 goto cleanup0;
5513 }
5514
edd16368
SC		 5515 /* Copy the error information out */
5516 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5517 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5518 status = -EFAULT;
e2d4a1f6 5519 goto cleanup0;
edd16368 5520 }
9233fb10 5521 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5522 int i;
5523
edd16368
SC		 5524 /* Copy the data out of the buffer we created */
5525 BYTE __user *ptr = ioc->buf;
5526 for (i = 0; i < sg_used; i++) {
5527 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5528 status = -EFAULT;
e2d4a1f6 5529 goto cleanup0;
edd16368
SC		 5530 }
5531 ptr += buff_size[i];
5532 }
5533 }
edd16368 5534 status = 0;
e2d4a1f6 5535cleanup0:
45fcb86e 5536 cmd_free(h, c);
edd16368
SC		 5537cleanup1:
5538 if (buff) {
2b08b3e9
DB		 5539 int i;
5540
edd16368
SC		 5541 for (i = 0; i < sg_used; i++)
5542 kfree(buff[i]);
5543 kfree(buff);
5544 }
5545 kfree(buff_size);
5546 kfree(ioc);
5547 return status;
5548}
5549
5550static void check_ioctl_unit_attention(struct ctlr_info *h,
5551 struct CommandList *c)
5552{
5553 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5554 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5555 (void) check_for_unit_attention(h, c);
5556}
0390f0c0 5557
edd16368
SC		 5558/*
5559 * ioctl
5560 */
42a91641 5561static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5562{
5563 struct ctlr_info *h;
5564 void __user *argp = (void __user *)arg;
0390f0c0 5565 int rc;
edd16368
SC		 5566
5567 h = sdev_to_hba(dev);
5568
5569 switch (cmd) {
5570 case CCISS_DEREGDISK:
5571 case CCISS_REGNEWDISK:
5572 case CCISS_REGNEWD:
a08a8471 5573 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5574 return 0;
5575 case CCISS_GETPCIINFO:
5576 return hpsa_getpciinfo_ioctl(h, argp);
5577 case CCISS_GETDRIVVER:
5578 return hpsa_getdrivver_ioctl(h, argp);
5579 case CCISS_PASSTHRU:
34f0c627 5580 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5581 return -EAGAIN;
5582 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 5583 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5584 return rc;
edd16368 5585 case CCISS_BIG_PASSTHRU:
34f0c627 5586 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5587 return -EAGAIN;
5588 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 5589 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5590 return rc;
edd16368
SC		 5591 default:
5592 return -ENOTTY;
5593 }
5594}
5595
6f039790
GKH		 5596static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5597 u8 reset_type)
64670ac8
SC		 5598{
5599 struct CommandList *c;
5600
5601 c = cmd_alloc(h);
5602 if (!c)
5603 return -ENOMEM;
a2dac136
SC		 5604 /* fill_cmd can't fail here, no data buffer to map */
5605 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5606 RAID_CTLR_LUNID, TYPE_MSG);
5607 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5608 c->waiting = NULL;
5609 enqueue_cmd_and_start_io(h, c);
5610 /* Don't wait for completion, the reset won't complete. Don't free
5611 * the command either. This is the last command we will send before
5612 * re-initializing everything, so it doesn't matter and won't leak.
5613 */
5614 return 0;
5615}
5616
a2dac136 5617static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5618 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5619 int cmd_type)
5620{
5621 int pci_dir = XFER_NONE;
9b5c48c2 5622 u64 tag; /* for commands to be aborted */
edd16368
SC		 5623
5624 c->cmd_type = CMD_IOCTL_PEND;
5625 c->Header.ReplyQueue = 0;
5626 if (buff != NULL && size > 0) {
5627 c->Header.SGList = 1;
50a0decf 5628 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5629 } else {
5630 c->Header.SGList = 0;
50a0decf 5631 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5632 }
edd16368
SC		 5633 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5634
edd16368
SC		 5635 if (cmd_type == TYPE_CMD) {
5636 switch (cmd) {
5637 case HPSA_INQUIRY:
5638 /* are we trying to read a vital product page */
b7bb24eb 5639 if (page_code & VPD_PAGE) {
edd16368 5640 c->Request.CDB[1] = 0x01;
b7bb24eb 5641 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5642 }
5643 c->Request.CDBLen = 6;
a505b86f
SC		 5644 c->Request.type_attr_dir =
5645 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5646 c->Request.Timeout = 0;
5647 c->Request.CDB[0] = HPSA_INQUIRY;
5648 c->Request.CDB[4] = size & 0xFF;
5649 break;
5650 case HPSA_REPORT_LOG:
5651 case HPSA_REPORT_PHYS:
5652 /* Talking to controller so It's a physical command
5653 mode = 00 target = 0. Nothing to write.
5654 */
5655 c->Request.CDBLen = 12;
a505b86f
SC		 5656 c->Request.type_attr_dir =
5657 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5658 c->Request.Timeout = 0;
5659 c->Request.CDB[0] = cmd;
5660 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5661 c->Request.CDB[7] = (size >> 16) & 0xFF;
5662 c->Request.CDB[8] = (size >> 8) & 0xFF;
5663 c->Request.CDB[9] = size & 0xFF;
5664 break;
edd16368
SC		 5665 case HPSA_CACHE_FLUSH:
5666 c->Request.CDBLen = 12;
a505b86f
SC		 5667 c->Request.type_attr_dir =
5668 TYPE_ATTR_DIR(cmd_type,
5669 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5670 c->Request.Timeout = 0;
5671 c->Request.CDB[0] = BMIC_WRITE;
5672 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5673 c->Request.CDB[7] = (size >> 8) & 0xFF;
5674 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5675 break;
5676 case TEST_UNIT_READY:
5677 c->Request.CDBLen = 6;
a505b86f
SC		 5678 c->Request.type_attr_dir =
5679 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5680 c->Request.Timeout = 0;
5681 break;
283b4a9b
SC		 5682 case HPSA_GET_RAID_MAP:
5683 c->Request.CDBLen = 12;
a505b86f
SC		 5684 c->Request.type_attr_dir =
5685 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5686 c->Request.Timeout = 0;
5687 c->Request.CDB[0] = HPSA_CISS_READ;
5688 c->Request.CDB[1] = cmd;
5689 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5690 c->Request.CDB[7] = (size >> 16) & 0xFF;
5691 c->Request.CDB[8] = (size >> 8) & 0xFF;
5692 c->Request.CDB[9] = size & 0xFF;
5693 break;
316b221a
SC		 5694 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5695 c->Request.CDBLen = 10;
a505b86f
SC		 5696 c->Request.type_attr_dir =
5697 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5698 c->Request.Timeout = 0;
5699 c->Request.CDB[0] = BMIC_READ;
5700 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5701 c->Request.CDB[7] = (size >> 16) & 0xFF;
5702 c->Request.CDB[8] = (size >> 8) & 0xFF;
5703 break;
03383736
DB		 5704 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5705 c->Request.CDBLen = 10;
5706 c->Request.type_attr_dir =
5707 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5708 c->Request.Timeout = 0;
5709 c->Request.CDB[0] = BMIC_READ;
5710 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5711 c->Request.CDB[7] = (size >> 16) & 0xFF;
5712 c->Request.CDB[8] = (size >> 8) & 0XFF;
5713 break;
edd16368
SC		 5714 default:
5715 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5716 BUG();
a2dac136 5717 return -1;
edd16368
SC		 5718 }
5719 } else if (cmd_type == TYPE_MSG) {
5720 switch (cmd) {
5721
5722 case HPSA_DEVICE_RESET_MSG:
5723 c->Request.CDBLen = 16;
a505b86f
SC		 5724 c->Request.type_attr_dir =
5725 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5726 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5727 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5728 c->Request.CDB[0] = cmd;
21e89afd 5729 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5730 /* If bytes 4-7 are zero, it means reset the */
5731 /* LunID device */
5732 c->Request.CDB[4] = 0x00;
5733 c->Request.CDB[5] = 0x00;
5734 c->Request.CDB[6] = 0x00;
5735 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5736 break;
5737 case HPSA_ABORT_MSG:
9b5c48c2 5738 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 5739 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 5740 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
5741 tag, c->Header.tag);
75167d2c 5742 c->Request.CDBLen = 16;
a505b86f
SC		 5743 c->Request.type_attr_dir =
5744 TYPE_ATTR_DIR(cmd_type,
5745 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5746 c->Request.Timeout = 0; /* Don't time out */
5747 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5748 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5749 c->Request.CDB[2] = 0x00; /* reserved */
5750 c->Request.CDB[3] = 0x00; /* reserved */
5751 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 5752 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 5753 c->Request.CDB[12] = 0x00; /* reserved */
5754 c->Request.CDB[13] = 0x00; /* reserved */
5755 c->Request.CDB[14] = 0x00; /* reserved */
5756 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5757 break;
edd16368
SC		 5758 default:
5759 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5760 cmd);
5761 BUG();
5762 }
5763 } else {
5764 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5765 BUG();
5766 }
5767
a505b86f 5768 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5769 case XFER_READ:
5770 pci_dir = PCI_DMA_FROMDEVICE;
5771 break;
5772 case XFER_WRITE:
5773 pci_dir = PCI_DMA_TODEVICE;
5774 break;
5775 case XFER_NONE:
5776 pci_dir = PCI_DMA_NONE;
5777 break;
5778 default:
5779 pci_dir = PCI_DMA_BIDIRECTIONAL;
5780 }
a2dac136
SC		 5781 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5782 return -1;
5783 return 0;
edd16368
SC		 5784}
5785
5786/*
5787 * Map (physical) PCI mem into (virtual) kernel space
5788 */
5789static void __iomem *remap_pci_mem(ulong base, ulong size)
5790{
5791 ulong page_base = ((ulong) base) & PAGE_MASK;
5792 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5793 void __iomem *page_remapped = ioremap_nocache(page_base,
5794 page_offs + size);
edd16368
SC		 5795
5796 return page_remapped ? (page_remapped + page_offs) : NULL;
5797}
5798
254f796b 5799static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5800{
254f796b 5801 return h->access.command_completed(h, q);
edd16368
SC		 5802}
5803
900c5440 5804static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5805{
5806 return h->access.intr_pending(h);
5807}
5808
5809static inline long interrupt_not_for_us(struct ctlr_info *h)
5810{
10f66018
SC		 5811 return (h->access.intr_pending(h) == 0) ||
5812 (h->interrupts_enabled == 0);
edd16368
SC		 5813}
5814
01a02ffc
SC		 5815static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5816 u32 raw_tag)
edd16368
SC		 5817{
5818 if (unlikely(tag_index >= h->nr_cmds)) {
5819 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5820 return 1;
5821 }
5822 return 0;
5823}
5824
5a3d16f5 5825static inline void finish_cmd(struct CommandList *c)
edd16368 5826{
e85c5974 5827 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5828 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5829 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5830 complete_scsi_command(c);
edd16368
SC		 5831 else if (c->cmd_type == CMD_IOCTL_PEND)
5832 complete(c->waiting);
a104c99f
SC		 5833}
5834
a9a3a273
SC		 5835
5836static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5837{
a9a3a273
SC		 5838#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5839#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5840 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5841 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5842 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5843}
5844
303932fd 5845/* process completion of an indexed ("direct lookup") command */
1d94f94d 5846static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5847 u32 raw_tag)
5848{
5849 u32 tag_index;
5850 struct CommandList *c;
5851
f2405db8 5852 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5853 if (!bad_tag(h, tag_index, raw_tag)) {
5854 c = h->cmd_pool + tag_index;
5855 finish_cmd(c);
5856 }
303932fd
DB		 5857}
5858
64670ac8
SC		 5859/* Some controllers, like p400, will give us one interrupt
5860 * after a soft reset, even if we turned interrupts off.
5861 * Only need to check for this in the hpsa_xxx_discard_completions
5862 * functions.
5863 */
5864static int ignore_bogus_interrupt(struct ctlr_info *h)
5865{
5866 if (likely(!reset_devices))
5867 return 0;
5868
5869 if (likely(h->interrupts_enabled))
5870 return 0;
5871
5872 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5873 "(known firmware bug.) Ignoring.\n");
5874
5875 return 1;
5876}
5877
254f796b
MG		 5878/*
5879 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5880 * Relies on (h-q[x] == x) being true for x such that
5881 * 0 <= x < MAX_REPLY_QUEUES.
5882 */
5883static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5884{
254f796b
MG		 5885 return container_of((queue - *queue), struct ctlr_info, q[0]);
5886}
5887
5888static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5889{
5890 struct ctlr_info *h = queue_to_hba(queue);
5891 u8 q = *(u8 *) queue;
64670ac8
SC		 5892 u32 raw_tag;
5893
5894 if (ignore_bogus_interrupt(h))
5895 return IRQ_NONE;
5896
5897 if (interrupt_not_for_us(h))
5898 return IRQ_NONE;
a0c12413 5899 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5900 while (interrupt_pending(h)) {
254f796b 5901 raw_tag = get_next_completion(h, q);
64670ac8 5902 while (raw_tag != FIFO_EMPTY)
254f796b 5903 raw_tag = next_command(h, q);
64670ac8 5904 }
64670ac8
SC		 5905 return IRQ_HANDLED;
5906}
5907
254f796b 5908static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5909{
254f796b 5910 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5911 u32 raw_tag;
254f796b 5912 u8 q = *(u8 *) queue;
64670ac8
SC		 5913
5914 if (ignore_bogus_interrupt(h))
5915 return IRQ_NONE;
5916
a0c12413 5917 h->last_intr_timestamp = get_jiffies_64();
254f796b 5918 raw_tag = get_next_completion(h, q);
64670ac8 5919 while (raw_tag != FIFO_EMPTY)
254f796b 5920 raw_tag = next_command(h, q);
64670ac8
SC		 5921 return IRQ_HANDLED;
5922}
5923
254f796b 5924static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5925{
254f796b 5926 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5927 u32 raw_tag;
254f796b 5928 u8 q = *(u8 *) queue;
edd16368
SC		 5929
5930 if (interrupt_not_for_us(h))
5931 return IRQ_NONE;
a0c12413 5932 h->last_intr_timestamp = get_jiffies_64();
10f66018 5933 while (interrupt_pending(h)) {
254f796b 5934 raw_tag = get_next_completion(h, q);
10f66018 5935 while (raw_tag != FIFO_EMPTY) {
f2405db8 5936 process_indexed_cmd(h, raw_tag);
254f796b 5937 raw_tag = next_command(h, q);
10f66018
SC		 5938 }
5939 }
10f66018
SC		 5940 return IRQ_HANDLED;
5941}
5942
254f796b 5943static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5944{
254f796b 5945 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5946 u32 raw_tag;
254f796b 5947 u8 q = *(u8 *) queue;
10f66018 5948
a0c12413 5949 h->last_intr_timestamp = get_jiffies_64();
254f796b 5950 raw_tag = get_next_completion(h, q);
303932fd 5951 while (raw_tag != FIFO_EMPTY) {
f2405db8 5952 process_indexed_cmd(h, raw_tag);
254f796b 5953 raw_tag = next_command(h, q);
edd16368 5954 }
edd16368
SC		 5955 return IRQ_HANDLED;
5956}
5957
a9a3a273
SC		 5958/* Send a message CDB to the firmware. Careful, this only works
5959 * in simple mode, not performant mode due to the tag lookup.
5960 * We only ever use this immediately after a controller reset.
5961 */
6f039790
GKH		 5962static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5963 unsigned char type)
edd16368
SC		 5964{
5965 struct Command {
5966 struct CommandListHeader CommandHeader;
5967 struct RequestBlock Request;
5968 struct ErrDescriptor ErrorDescriptor;
5969 };
5970 struct Command *cmd;
5971 static const size_t cmd_sz = sizeof(*cmd) +
5972 sizeof(cmd->ErrorDescriptor);
5973 dma_addr_t paddr64;
2b08b3e9
DB		 5974 __le32 paddr32;
5975 u32 tag;
edd16368
SC		 5976 void __iomem *vaddr;
5977 int i, err;
5978
5979 vaddr = pci_ioremap_bar(pdev, 0);
5980 if (vaddr == NULL)
5981 return -ENOMEM;
5982
5983 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5984 * CCISS commands, so they must be allocated from the lower 4GiB of
5985 * memory.
5986 */
5987 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5988 if (err) {
5989 iounmap(vaddr);
1eaec8f3 5990 return err;
edd16368
SC		 5991 }
5992
5993 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5994 if (cmd == NULL) {
5995 iounmap(vaddr);
5996 return -ENOMEM;
5997 }
5998
5999 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6000 * although there's no guarantee, we assume that the address is at
6001 * least 4-byte aligned (most likely, it's page-aligned).
6002 */
2b08b3e9 6003 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6004
6005 cmd->CommandHeader.ReplyQueue = 0;
6006 cmd->CommandHeader.SGList = 0;
50a0decf 6007 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6008 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6009 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6010
6011 cmd->Request.CDBLen = 16;
a505b86f
SC		 6012 cmd->Request.type_attr_dir =
6013 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6014 cmd->Request.Timeout = 0; /* Don't time out */
6015 cmd->Request.CDB[0] = opcode;
6016 cmd->Request.CDB[1] = type;
6017 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6018 cmd->ErrorDescriptor.Addr =
2b08b3e9 6019 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6020 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6021
2b08b3e9 6022 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6023
6024 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6025 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6026 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6027 break;
6028 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6029 }
6030
6031 iounmap(vaddr);
6032
6033 /* we leak the DMA buffer here ... no choice since the controller could
6034 * still complete the command.
6035 */
6036 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6037 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6038 opcode, type);
6039 return -ETIMEDOUT;
6040 }
6041
6042 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6043
6044 if (tag & HPSA_ERROR_BIT) {
6045 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6046 opcode, type);
6047 return -EIO;
6048 }
6049
6050 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6051 opcode, type);
6052 return 0;
6053}
6054
edd16368
SC		 6055#define hpsa_noop(p) hpsa_message(p, 3, 0)
6056
1df8552a 6057static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6058 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6059{
1df8552a
SC		 6060
6061 if (use_doorbell) {
6062 /* For everything after the P600, the PCI power state method
6063 * of resetting the controller doesn't work, so we have this
6064 * other way using the doorbell register.
6065 */
6066 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6067 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6068
00701a96 6069 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6070 * doorbell reset and before any attempt to talk to the board
6071 * at all to ensure that this actually works and doesn't fall
6072 * over in some weird corner cases.
6073 */
00701a96 6074 msleep(10000);
1df8552a
SC		 6075 } else { /* Try to do it the PCI power state way */
6076
6077 /* Quoting from the Open CISS Specification: "The Power
6078 * Management Control/Status Register (CSR) controls the power
6079 * state of the device. The normal operating state is D0,
6080 * CSR=00h. The software off state is D3, CSR=03h. To reset
6081 * the controller, place the interface device in D3 then to D0,
6082 * this causes a secondary PCI reset which will reset the
6083 * controller." */
2662cab8
DB		 6084
6085 int rc = 0;
6086
1df8552a 6087 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6088
1df8552a 6089 /* enter the D3hot power management state */
2662cab8
DB		 6090 rc = pci_set_power_state(pdev, PCI_D3hot);
6091 if (rc)
6092 return rc;
1df8552a
SC		 6093
6094 msleep(500);
6095
6096 /* enter the D0 power management state */
2662cab8
DB		 6097 rc = pci_set_power_state(pdev, PCI_D0);
6098 if (rc)
6099 return rc;
c4853efe
MM		 6100
6101 /*
6102 * The P600 requires a small delay when changing states.
6103 * Otherwise we may think the board did not reset and we bail.
6104 * This for kdump only and is particular to the P600.
6105 */
6106 msleep(500);
1df8552a
SC		 6107 }
6108 return 0;
6109}
6110
6f039790 6111static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6112{
6113 memset(driver_version, 0, len);
f79cfec6 6114 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6115}
6116
6f039790 6117static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6118{
6119 char *driver_version;
6120 int i, size = sizeof(cfgtable->driver_version);
6121
6122 driver_version = kmalloc(size, GFP_KERNEL);
6123 if (!driver_version)
6124 return -ENOMEM;
6125
6126 init_driver_version(driver_version, size);
6127 for (i = 0; i < size; i++)
6128 writeb(driver_version[i], &cfgtable->driver_version[i]);
6129 kfree(driver_version);
6130 return 0;
6131}
6132
6f039790
GKH		 6133static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6134 unsigned char *driver_ver)
580ada3c
SC		 6135{
6136 int i;
6137
6138 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6139 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6140}
6141
6f039790 6142static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6143{
6144
6145 char *driver_ver, *old_driver_ver;
6146 int rc, size = sizeof(cfgtable->driver_version);
6147
6148 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6149 if (!old_driver_ver)
6150 return -ENOMEM;
6151 driver_ver = old_driver_ver + size;
6152
6153 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6154 * should have been changed, otherwise we know the reset failed.
6155 */
6156 init_driver_version(old_driver_ver, size);
6157 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6158 rc = !memcmp(driver_ver, old_driver_ver, size);
6159 kfree(old_driver_ver);
6160 return rc;
6161}
edd16368 6162/* This does a hard reset of the controller using PCI power management
1df8552a 6163 * states or the using the doorbell register.
edd16368 6164 */
6b6c1cd7 6165static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6166{
1df8552a
SC		 6167 u64 cfg_offset;
6168 u32 cfg_base_addr;
6169 u64 cfg_base_addr_index;
6170 void __iomem *vaddr;
6171 unsigned long paddr;
580ada3c 6172 u32 misc_fw_support;
270d05de 6173 int rc;
1df8552a 6174 struct CfgTable __iomem *cfgtable;
cf0b08d0 6175 u32 use_doorbell;
270d05de 6176 u16 command_register;
edd16368 6177
1df8552a
SC		 6178 /* For controllers as old as the P600, this is very nearly
6179 * the same thing as
edd16368
SC		 6180 *
6181 * pci_save_state(pci_dev);
6182 * pci_set_power_state(pci_dev, PCI_D3hot);
6183 * pci_set_power_state(pci_dev, PCI_D0);
6184 * pci_restore_state(pci_dev);
6185 *
1df8552a
SC		 6186 * For controllers newer than the P600, the pci power state
6187 * method of resetting doesn't work so we have another way
6188 * using the doorbell register.
edd16368 6189 */
18867659 6190
60f923b9
RE		 6191 if (!ctlr_is_resettable(board_id)) {
6192 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6193 return -ENODEV;
6194 }
46380786
SC		 6195
6196 /* if controller is soft- but not hard resettable... */
6197 if (!ctlr_is_hard_resettable(board_id))
6198 return -ENOTSUPP; /* try soft reset later. */
18867659 6199
270d05de
SC		 6200 /* Save the PCI command register */
6201 pci_read_config_word(pdev, 4, &command_register);
270d05de 6202 pci_save_state(pdev);
edd16368 6203
1df8552a
SC		 6204 /* find the first memory BAR, so we can find the cfg table */
6205 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6206 if (rc)
6207 return rc;
6208 vaddr = remap_pci_mem(paddr, 0x250);
6209 if (!vaddr)
6210 return -ENOMEM;
edd16368 6211
1df8552a
SC		 6212 /* find cfgtable in order to check if reset via doorbell is supported */
6213 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6214 &cfg_base_addr_index, &cfg_offset);
6215 if (rc)
6216 goto unmap_vaddr;
6217 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6218 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6219 if (!cfgtable) {
6220 rc = -ENOMEM;
6221 goto unmap_vaddr;
6222 }
580ada3c
SC		 6223 rc = write_driver_ver_to_cfgtable(cfgtable);
6224 if (rc)
03741d95 6225 goto unmap_cfgtable;
edd16368 6226
cf0b08d0
SC		 6227 /* If reset via doorbell register is supported, use that.
6228 * There are two such methods. Favor the newest method.
6229 */
1df8552a 6230 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6231 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6232 if (use_doorbell) {
6233 use_doorbell = DOORBELL_CTLR_RESET2;
6234 } else {
6235 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6236 if (use_doorbell) {
050f7147
SC		 6237 dev_warn(&pdev->dev,
6238 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6239 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6240 goto unmap_cfgtable;
6241 }
6242 }
edd16368 6243
1df8552a
SC		 6244 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6245 if (rc)
6246 goto unmap_cfgtable;
edd16368 6247
270d05de 6248 pci_restore_state(pdev);
270d05de 6249 pci_write_config_word(pdev, 4, command_register);
edd16368 6250
1df8552a
SC		 6251 /* Some devices (notably the HP Smart Array 5i Controller)
6252 need a little pause here */
6253 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6254
fe5389c8
SC		 6255 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6256 if (rc) {
6257 dev_warn(&pdev->dev,
050f7147 6258 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6259 goto unmap_cfgtable;
6260 }
fe5389c8 6261
580ada3c
SC		 6262 rc = controller_reset_failed(vaddr);
6263 if (rc < 0)
6264 goto unmap_cfgtable;
6265 if (rc) {
64670ac8
SC		 6266 dev_warn(&pdev->dev, "Unable to successfully reset "
6267 "controller. Will try soft reset.\n");
6268 rc = -ENOTSUPP;
580ada3c 6269 } else {
64670ac8 6270 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6271 }
6272
6273unmap_cfgtable:
6274 iounmap(cfgtable);
6275
6276unmap_vaddr:
6277 iounmap(vaddr);
6278 return rc;
edd16368
SC		 6279}
6280
6281/*
6282 * We cannot read the structure directly, for portability we must use
6283 * the io functions.
6284 * This is for debug only.
6285 */
42a91641 6286static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6287{
58f8665c 6288#ifdef HPSA_DEBUG
edd16368
SC		 6289 int i;
6290 char temp_name[17];
6291
6292 dev_info(dev, "Controller Configuration information\n");
6293 dev_info(dev, "------------------------------------\n");
6294 for (i = 0; i < 4; i++)
6295 temp_name[i] = readb(&(tb->Signature[i]));
6296 temp_name[4] = '\0';
6297 dev_info(dev, " Signature = %s\n", temp_name);
6298 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6299 dev_info(dev, " Transport methods supported = 0x%x\n",
6300 readl(&(tb->TransportSupport)));
6301 dev_info(dev, " Transport methods active = 0x%x\n",
6302 readl(&(tb->TransportActive)));
6303 dev_info(dev, " Requested transport Method = 0x%x\n",
6304 readl(&(tb->HostWrite.TransportRequest)));
6305 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6306 readl(&(tb->HostWrite.CoalIntDelay)));
6307 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6308 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6309 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6310 readl(&(tb->CmdsOutMax)));
6311 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6312 for (i = 0; i < 16; i++)
6313 temp_name[i] = readb(&(tb->ServerName[i]));
6314 temp_name[16] = '\0';
6315 dev_info(dev, " Server Name = %s\n", temp_name);
6316 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6317 readl(&(tb->HeartBeat)));
edd16368 6318#endif /* HPSA_DEBUG */
58f8665c 6319}
edd16368
SC		 6320
6321static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6322{
6323 int i, offset, mem_type, bar_type;
6324
6325 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6326 return 0;
6327 offset = 0;
6328 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6329 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6330 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6331 offset += 4;
6332 else {
6333 mem_type = pci_resource_flags(pdev, i) &
6334 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6335 switch (mem_type) {
6336 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6337 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6338 offset += 4; /* 32 bit */
6339 break;
6340 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6341 offset += 8;
6342 break;
6343 default: /* reserved in PCI 2.2 */
6344 dev_warn(&pdev->dev,
6345 "base address is invalid\n");
6346 return -1;
6347 break;
6348 }
6349 }
6350 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6351 return i + 1;
6352 }
6353 return -1;
6354}
6355
cc64c817
RE		 6356static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6357{
6358 if (h->msix_vector) {
6359 if (h->pdev->msix_enabled)
6360 pci_disable_msix(h->pdev);
6361 } else if (h->msi_vector) {
6362 if (h->pdev->msi_enabled)
6363 pci_disable_msi(h->pdev);
6364 }
6365}
6366
edd16368 6367/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6368 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6369 */
6f039790 6370static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6371{
6372#ifdef CONFIG_PCI_MSI
254f796b
MG		 6373 int err, i;
6374 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6375
6376 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6377 hpsa_msix_entries[i].vector = 0;
6378 hpsa_msix_entries[i].entry = i;
6379 }
edd16368
SC		 6380
6381 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6382 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6383 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6384 goto default_int_mode;
55c06c71 6385 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6386 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6387 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6388 if (h->msix_vector > num_online_cpus())
6389 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6390 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6391 1, h->msix_vector);
6392 if (err < 0) {
6393 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6394 h->msix_vector = 0;
6395 goto single_msi_mode;
6396 } else if (err < h->msix_vector) {
55c06c71 6397 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6398 "available\n", err);
edd16368 6399 }
18fce3c4
AG		 6400 h->msix_vector = err;
6401 for (i = 0; i < h->msix_vector; i++)
6402 h->intr[i] = hpsa_msix_entries[i].vector;
6403 return;
edd16368 6404 }
18fce3c4 6405single_msi_mode:
55c06c71 6406 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6407 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6408 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6409 h->msi_vector = 1;
6410 else
55c06c71 6411 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6412 }
6413default_int_mode:
6414#endif /* CONFIG_PCI_MSI */
6415 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6416 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6417}
6418
6f039790 6419static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6420{
6421 int i;
6422 u32 subsystem_vendor_id, subsystem_device_id;
6423
6424 subsystem_vendor_id = pdev->subsystem_vendor;
6425 subsystem_device_id = pdev->subsystem_device;
6426 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6427 subsystem_vendor_id;
6428
6429 for (i = 0; i < ARRAY_SIZE(products); i++)
6430 if (*board_id == products[i].board_id)
6431 return i;
6432
6798cc0a
SC		 6433 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6434 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6435 !hpsa_allow_any) {
e5c880d1
SC		 6436 dev_warn(&pdev->dev, "unrecognized board ID: "
6437 "0x%08x, ignoring.\n", *board_id);
6438 return -ENODEV;
6439 }
6440 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6441}
6442
6f039790
GKH		 6443static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6444 unsigned long *memory_bar)
3a7774ce
SC		 6445{
6446 int i;
6447
6448 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6449 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6450 /* addressing mode bits already removed */
12d2cd47
SC		 6451 *memory_bar = pci_resource_start(pdev, i);
6452 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6453 *memory_bar);
6454 return 0;
6455 }
12d2cd47 6456 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6457 return -ENODEV;
6458}
6459
6f039790
GKH		 6460static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6461 int wait_for_ready)
2c4c8c8b 6462{
fe5389c8 6463 int i, iterations;
2c4c8c8b 6464 u32 scratchpad;
fe5389c8
SC		 6465 if (wait_for_ready)
6466 iterations = HPSA_BOARD_READY_ITERATIONS;
6467 else
6468 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6469
fe5389c8
SC		 6470 for (i = 0; i < iterations; i++) {
6471 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6472 if (wait_for_ready) {
6473 if (scratchpad == HPSA_FIRMWARE_READY)
6474 return 0;
6475 } else {
6476 if (scratchpad != HPSA_FIRMWARE_READY)
6477 return 0;
6478 }
2c4c8c8b
SC		 6479 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6480 }
fe5389c8 6481 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6482 return -ENODEV;
6483}
6484
6f039790
GKH		 6485static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6486 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6487 u64 *cfg_offset)
a51fd47f
SC		 6488{
6489 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6490 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6491 *cfg_base_addr &= (u32) 0x0000ffff;
6492 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6493 if (*cfg_base_addr_index == -1) {
6494 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6495 return -ENODEV;
6496 }
6497 return 0;
6498}
6499
195f2c65
RE		 6500static void hpsa_free_cfgtables(struct ctlr_info *h)
6501{
6502 if (h->transtable)
6503 iounmap(h->transtable);
6504 if (h->cfgtable)
6505 iounmap(h->cfgtable);
6506}
6507
6508/* Find and map CISS config table and transfer table
6509+ * several items must be unmapped (freed) later
6510+ * */
6f039790 6511static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6512{
01a02ffc
SC		 6513 u64 cfg_offset;
6514 u32 cfg_base_addr;
6515 u64 cfg_base_addr_index;
303932fd 6516 u32 trans_offset;
a51fd47f 6517 int rc;
77c4495c 6518
a51fd47f
SC		 6519 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6520 &cfg_base_addr_index, &cfg_offset);
6521 if (rc)
6522 return rc;
77c4495c 6523 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6524 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6525 if (!h->cfgtable) {
6526 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6527 return -ENOMEM;
cd3c81c4 6528 }
580ada3c
SC		 6529 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6530 if (rc)
6531 return rc;
77c4495c 6532 /* Find performant mode table. */
a51fd47f 6533 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6534 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6535 cfg_base_addr_index)+cfg_offset+trans_offset,
6536 sizeof(*h->transtable));
195f2c65
RE		 6537 if (!h->transtable) {
6538 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
6539 hpsa_free_cfgtables(h);
77c4495c 6540 return -ENOMEM;
195f2c65 6541 }
77c4495c
SC		 6542 return 0;
6543}
6544
6f039790 6545static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 6546{
41ce4c35
SC		 6547#define MIN_MAX_COMMANDS 16
6548 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
6549
6550 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 6551
6552 /* Limit commands in memory limited kdump scenario. */
6553 if (reset_devices && h->max_commands > 32)
6554 h->max_commands = 32;
6555
41ce4c35
SC		 6556 if (h->max_commands < MIN_MAX_COMMANDS) {
6557 dev_warn(&h->pdev->dev,
6558 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
6559 h->max_commands,
6560 MIN_MAX_COMMANDS);
6561 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 6562 }
6563}
6564
c7ee65b3
WS		 6565/* If the controller reports that the total max sg entries is greater than 512,
6566 * then we know that chained SG blocks work. (Original smart arrays did not
6567 * support chained SG blocks and would return zero for max sg entries.)
6568 */
6569static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6570{
6571 return h->maxsgentries > 512;
6572}
6573
b93d7536
SC		 6574/* Interrogate the hardware for some limits:
6575 * max commands, max SG elements without chaining, and with chaining,
6576 * SG chain block size, etc.
6577 */
6f039790 6578static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6579{
cba3d38b 6580 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6581 h->nr_cmds = h->max_commands;
b93d7536 6582 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6583 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6584 if (hpsa_supports_chained_sg_blocks(h)) {
6585 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6586 h->max_cmd_sg_entries = 32;
1a63ea6f 6587 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6588 h->maxsgentries--; /* save one for chain pointer */
6589 } else {
c7ee65b3
WS		 6590 /*
6591 * Original smart arrays supported at most 31 s/g entries
6592 * embedded inline in the command (trying to use more
6593 * would lock up the controller)
6594 */
6595 h->max_cmd_sg_entries = 31;
1a63ea6f 6596 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6597 h->chainsize = 0;
b93d7536 6598 }
75167d2c
SC		 6599
6600 /* Find out what task management functions are supported and cache */
6601 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6602 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6603 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6604 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6605 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6606}
6607
76c46e49
SC		 6608static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6609{
0fc9fd40 6610 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6611 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6612 return false;
6613 }
6614 return true;
6615}
6616
97a5e98c 6617static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6618{
97a5e98c 6619 u32 driver_support;
f7c39101 6620
97a5e98c 6621 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6622 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6623#ifdef CONFIG_X86
97a5e98c 6624 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6625#endif
28e13446
SC		 6626 driver_support |= ENABLE_UNIT_ATTN;
6627 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6628}
6629
3d0eab67
SC		 6630/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6631 * in a prefetch beyond physical memory.
6632 */
6633static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6634{
6635 u32 dma_prefetch;
6636
6637 if (h->board_id != 0x3225103C)
6638 return;
6639 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6640 dma_prefetch |= 0x8000;
6641 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6642}
6643
c706a795 6644static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 6645{
6646 int i;
6647 u32 doorbell_value;
6648 unsigned long flags;
6649 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 6650 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 6651 spin_lock_irqsave(&h->lock, flags);
6652 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6653 spin_unlock_irqrestore(&h->lock, flags);
6654 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 6655 goto done;
76438d08 6656 /* delay and try again */
007e7aa9 6657 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 6658 }
c706a795
RE		 6659 return -ENODEV;
6660done:
6661 return 0;
76438d08
SC		 6662}
6663
c706a795 6664static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6665{
6666 int i;
6eaf46fd
SC		 6667 u32 doorbell_value;
6668 unsigned long flags;
eb6b2ae9
SC		 6669
6670 /* under certain very rare conditions, this can take awhile.
6671 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6672 * as we enter this code.)
6673 */
007e7aa9 6674 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 6675 if (h->remove_in_progress)
6676 goto done;
6eaf46fd
SC		 6677 spin_lock_irqsave(&h->lock, flags);
6678 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6679 spin_unlock_irqrestore(&h->lock, flags);
382be668 6680 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 6681 goto done;
eb6b2ae9 6682 /* delay and try again */
007e7aa9 6683 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 6684 }
c706a795
RE		 6685 return -ENODEV;
6686done:
6687 return 0;
3f4336f3
SC		 6688}
6689
c706a795 6690/* return -ENODEV or other reason on error, 0 on success */
6f039790 6691static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6692{
6693 u32 trans_support;
6694
6695 trans_support = readl(&(h->cfgtable->TransportSupport));
6696 if (!(trans_support & SIMPLE_MODE))
6697 return -ENOTSUPP;
6698
6699 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6700
3f4336f3
SC		 6701 /* Update the field, and then ring the doorbell */
6702 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6703 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 6704 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 6705 if (hpsa_wait_for_mode_change_ack(h))
6706 goto error;
eb6b2ae9 6707 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6708 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6709 goto error;
960a30e7 6710 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6711 return 0;
283b4a9b 6712error:
050f7147 6713 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6714 return -ENODEV;
eb6b2ae9
SC		 6715}
6716
195f2c65
RE		 6717/* free items allocated or mapped by hpsa_pci_init */
6718static void hpsa_free_pci_init(struct ctlr_info *h)
6719{
6720 hpsa_free_cfgtables(h); /* pci_init 4 */
6721 iounmap(h->vaddr); /* pci_init 3 */
6722 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
6723 pci_release_regions(h->pdev); /* pci_init 2 */
6724 pci_disable_device(h->pdev); /* pci_init 1 */
6725}
6726
6727/* several items must be freed later */
6f039790 6728static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6729{
eb6b2ae9 6730 int prod_index, err;
edd16368 6731
e5c880d1
SC		 6732 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6733 if (prod_index < 0)
60f923b9 6734 return prod_index;
e5c880d1
SC		 6735 h->product_name = products[prod_index].product_name;
6736 h->access = *(products[prod_index].access);
edd16368 6737
9b5c48c2
SC		 6738 h->needs_abort_tags_swizzled =
6739 ctlr_needs_abort_tags_swizzled(h->board_id);
6740
e5a44df8
MG		 6741 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6742 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6743
55c06c71 6744 err = pci_enable_device(h->pdev);
edd16368 6745 if (err) {
195f2c65 6746 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
edd16368
SC		 6747 return err;
6748 }
6749
f79cfec6 6750 err = pci_request_regions(h->pdev, HPSA);
edd16368 6751 if (err) {
55c06c71 6752 dev_err(&h->pdev->dev,
195f2c65
RE		 6753 "failed to obtain PCI resources\n");
6754 goto clean1; /* pci */
edd16368 6755 }
4fa604e1
RE		 6756
6757 pci_set_master(h->pdev);
6758
6b3f4c52 6759 hpsa_interrupt_mode(h);
12d2cd47 6760 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6761 if (err)
195f2c65 6762 goto clean2; /* intmode+region, pci */
edd16368 6763 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 6764 if (!h->vaddr) {
195f2c65 6765 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 6766 err = -ENOMEM;
195f2c65 6767 goto clean2; /* intmode+region, pci */
204892e9 6768 }
fe5389c8 6769 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6770 if (err)
195f2c65 6771 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 6772 err = hpsa_find_cfgtables(h);
6773 if (err)
195f2c65 6774 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 6775 hpsa_find_board_params(h);
edd16368 6776
76c46e49 6777 if (!hpsa_CISS_signature_present(h)) {
edd16368 6778 err = -ENODEV;
195f2c65 6779 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 6780 }
97a5e98c 6781 hpsa_set_driver_support_bits(h);
3d0eab67 6782 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6783 err = hpsa_enter_simple_mode(h);
6784 if (err)
195f2c65 6785 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 6786 return 0;
6787
195f2c65
RE		 6788clean4: /* cfgtables, vaddr, intmode+region, pci */
6789 hpsa_free_cfgtables(h);
6790clean3: /* vaddr, intmode+region, pci */
6791 iounmap(h->vaddr);
6792clean2: /* intmode+region, pci */
6793 hpsa_disable_interrupt_mode(h);
55c06c71 6794 pci_release_regions(h->pdev);
195f2c65
RE		 6795clean1: /* pci */
6796 pci_disable_device(h->pdev);
edd16368
SC		 6797 return err;
6798}
6799
6f039790 6800static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6801{
6802 int rc;
6803
6804#define HBA_INQUIRY_BYTE_COUNT 64
6805 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6806 if (!h->hba_inquiry_data)
6807 return;
6808 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6809 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6810 if (rc != 0) {
6811 kfree(h->hba_inquiry_data);
6812 h->hba_inquiry_data = NULL;
6813 }
6814}
6815
6b6c1cd7 6816static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 6817{
1df8552a 6818 int rc, i;
3b747298 6819 void __iomem *vaddr;
4c2a8c40
SC		 6820
6821 if (!reset_devices)
6822 return 0;
6823
132aa220
TH		 6824 /* kdump kernel is loading, we don't know in which state is
6825 * the pci interface. The dev->enable_cnt is equal zero
6826 * so we call enable+disable, wait a while and switch it on.
6827 */
6828 rc = pci_enable_device(pdev);
6829 if (rc) {
6830 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6831 return -ENODEV;
6832 }
6833 pci_disable_device(pdev);
6834 msleep(260); /* a randomly chosen number */
6835 rc = pci_enable_device(pdev);
6836 if (rc) {
6837 dev_warn(&pdev->dev, "failed to enable device.\n");
6838 return -ENODEV;
6839 }
4fa604e1 6840
859c75ab 6841 pci_set_master(pdev);
4fa604e1 6842
3b747298
TH		 6843 vaddr = pci_ioremap_bar(pdev, 0);
6844 if (vaddr == NULL) {
6845 rc = -ENOMEM;
6846 goto out_disable;
6847 }
6848 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6849 iounmap(vaddr);
6850
1df8552a 6851 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 6852 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 6853
1df8552a
SC		 6854 /* -ENOTSUPP here means we cannot reset the controller
6855 * but it's already (and still) up and running in
18867659
SC		 6856 * "performant mode". Or, it might be 640x, which can't reset
6857 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6858 */
adf1b3a3 6859 if (rc)
132aa220 6860 goto out_disable;
4c2a8c40
SC		 6861
6862 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6863 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6864 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6865 if (hpsa_noop(pdev) == 0)
6866 break;
6867 else
6868 dev_warn(&pdev->dev, "no-op failed%s\n",
6869 (i < 11 ? "; re-trying" : ""));
6870 }
132aa220
TH		 6871
6872out_disable:
6873
6874 pci_disable_device(pdev);
6875 return rc;
4c2a8c40
SC		 6876}
6877
1fb7c98a
RE		 6878static void hpsa_free_cmd_pool(struct ctlr_info *h)
6879{
6880 kfree(h->cmd_pool_bits);
6881 if (h->cmd_pool)
6882 pci_free_consistent(h->pdev,
6883 h->nr_cmds * sizeof(struct CommandList),
6884 h->cmd_pool,
6885 h->cmd_pool_dhandle);
6886 if (h->errinfo_pool)
6887 pci_free_consistent(h->pdev,
6888 h->nr_cmds * sizeof(struct ErrorInfo),
6889 h->errinfo_pool,
6890 h->errinfo_pool_dhandle);
6891}
6892
d37ffbe4 6893static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6894{
6895 h->cmd_pool_bits = kzalloc(
6896 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6897 sizeof(unsigned long), GFP_KERNEL);
6898 h->cmd_pool = pci_alloc_consistent(h->pdev,
6899 h->nr_cmds * sizeof(*h->cmd_pool),
6900 &(h->cmd_pool_dhandle));
6901 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6902 h->nr_cmds * sizeof(*h->errinfo_pool),
6903 &(h->errinfo_pool_dhandle));
6904 if ((h->cmd_pool_bits == NULL)
6905 || (h->cmd_pool == NULL)
6906 || (h->errinfo_pool == NULL)) {
6907 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6908 goto clean_up;
2e9d1b36 6909 }
360c73bd 6910 hpsa_preinitialize_commands(h);
2e9d1b36 6911 return 0;
2c143342
RE		 6912clean_up:
6913 hpsa_free_cmd_pool(h);
6914 return -ENOMEM;
2e9d1b36
SC		 6915}
6916
41b3cf08
SC		 6917static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6918{
ec429952 6919 int i, cpu;
41b3cf08
SC		 6920
6921 cpu = cpumask_first(cpu_online_mask);
6922 for (i = 0; i < h->msix_vector; i++) {
ec429952 6923 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6924 cpu = cpumask_next(cpu, cpu_online_mask);
6925 }
6926}
6927
ec501a18
RE		 6928/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6929static void hpsa_free_irqs(struct ctlr_info *h)
6930{
6931 int i;
6932
6933 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6934 /* Single reply queue, only one irq to free */
6935 i = h->intr_mode;
6936 irq_set_affinity_hint(h->intr[i], NULL);
6937 free_irq(h->intr[i], &h->q[i]);
6938 return;
6939 }
6940
6941 for (i = 0; i < h->msix_vector; i++) {
6942 irq_set_affinity_hint(h->intr[i], NULL);
6943 free_irq(h->intr[i], &h->q[i]);
6944 }
a4e17fc1
RE		 6945 for (; i < MAX_REPLY_QUEUES; i++)
6946 h->q[i] = 0;
ec501a18
RE		 6947}
6948
9ee61794
RE		 6949/* returns 0 on success; cleans up and returns -Enn on error */
6950static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6951 irqreturn_t (*msixhandler)(int, void *),
6952 irqreturn_t (*intxhandler)(int, void *))
6953{
254f796b 6954 int rc, i;
0ae01a32 6955
254f796b
MG		 6956 /*
6957 * initialize h->q[x] = x so that interrupt handlers know which
6958 * queue to process.
6959 */
6960 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6961 h->q[i] = (u8) i;
6962
eee0f03a 6963 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6964 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6965 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6966 rc = request_irq(h->intr[i], msixhandler,
6967 0, h->devname,
6968 &h->q[i]);
a4e17fc1
RE		 6969 if (rc) {
6970 int j;
6971
6972 dev_err(&h->pdev->dev,
6973 "failed to get irq %d for %s\n",
6974 h->intr[i], h->devname);
6975 for (j = 0; j < i; j++) {
6976 free_irq(h->intr[j], &h->q[j]);
6977 h->q[j] = 0;
6978 }
6979 for (; j < MAX_REPLY_QUEUES; j++)
6980 h->q[j] = 0;
6981 return rc;
6982 }
6983 }
41b3cf08 6984 hpsa_irq_affinity_hints(h);
254f796b
MG		 6985 } else {
6986 /* Use single reply pool */
eee0f03a 6987 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6988 rc = request_irq(h->intr[h->intr_mode],
6989 msixhandler, 0, h->devname,
6990 &h->q[h->intr_mode]);
6991 } else {
6992 rc = request_irq(h->intr[h->intr_mode],
6993 intxhandler, IRQF_SHARED, h->devname,
6994 &h->q[h->intr_mode]);
6995 }
6996 }
0ae01a32 6997 if (rc) {
195f2c65 6998 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 6999 h->intr[h->intr_mode], h->devname);
195f2c65 7000 hpsa_free_irqs(h);
0ae01a32
SC		 7001 return -ENODEV;
7002 }
7003 return 0;
7004}
7005
6f039790 7006static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 7007{
7008 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
7009 HPSA_RESET_TYPE_CONTROLLER)) {
7010 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
7011 return -EIO;
7012 }
7013
7014 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
7015 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
7016 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
7017 return -1;
7018 }
7019
7020 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
7021 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
7022 dev_warn(&h->pdev->dev, "Board failed to become ready "
7023 "after soft reset.\n");
7024 return -1;
7025 }
7026
7027 return 0;
7028}
7029
072b0518
SC		 7030static void hpsa_free_reply_queues(struct ctlr_info *h)
7031{
7032 int i;
7033
7034 for (i = 0; i < h->nreply_queues; i++) {
7035 if (!h->reply_queue[i].head)
7036 continue;
1fb7c98a
RE		 7037 pci_free_consistent(h->pdev,
7038 h->reply_queue_size,
7039 h->reply_queue[i].head,
7040 h->reply_queue[i].busaddr);
072b0518
SC		 7041 h->reply_queue[i].head = NULL;
7042 h->reply_queue[i].busaddr = 0;
7043 }
7044}
7045
0097f0f4
SC		 7046static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7047{
cc64c817 7048 hpsa_free_irqs(h);
64670ac8
SC		 7049 hpsa_free_sg_chain_blocks(h);
7050 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7051 kfree(h->blockFetchTable); /* perf 2 */
7052 hpsa_free_reply_queues(h); /* perf 1 */
7053 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7054 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
195f2c65
RE		 7055 hpsa_free_cfgtables(h); /* pci_init 4 */
7056 iounmap(h->vaddr); /* pci_init 3 */
7057 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
132aa220 7058 pci_disable_device(h->pdev);
195f2c65 7059 pci_release_regions(h->pdev); /* pci_init 2 */
64670ac8
SC		 7060 kfree(h);
7061}
7062
a0c12413 7063/* Called when controller lockup detected. */
f2405db8 7064static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7065{
281a7fd0
WS		 7066 int i, refcount;
7067 struct CommandList *c;
25163bd5 7068 int failcount = 0;
a0c12413 7069
080ef1cc 7070 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7071 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7072 c = h->cmd_pool + i;
281a7fd0
WS		 7073 refcount = atomic_inc_return(&c->refcount);
7074 if (refcount > 1) {
25163bd5 7075 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7076 finish_cmd(c);
433b5f4d 7077 atomic_dec(&h->commands_outstanding);
25163bd5 7078 failcount++;
281a7fd0
WS		 7079 }
7080 cmd_free(h, c);
a0c12413 7081 }
25163bd5
WS		 7082 dev_warn(&h->pdev->dev,
7083 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7084}
7085
094963da
SC		 7086static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7087{
c8ed0010 7088 int cpu;
094963da 7089
c8ed0010 7090 for_each_online_cpu(cpu) {
094963da
SC		 7091 u32 *lockup_detected;
7092 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7093 *lockup_detected = value;
094963da
SC		 7094 }
7095 wmb(); /* be sure the per-cpu variables are out to memory */
7096}
7097
a0c12413
SC		 7098static void controller_lockup_detected(struct ctlr_info *h)
7099{
7100 unsigned long flags;
094963da 7101 u32 lockup_detected;
a0c12413 7102
a0c12413
SC		 7103 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7104 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7105 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7106 if (!lockup_detected) {
7107 /* no heartbeat, but controller gave us a zero. */
7108 dev_warn(&h->pdev->dev,
25163bd5
WS		 7109 "lockup detected after %d but scratchpad register is zero\n",
7110 h->heartbeat_sample_interval / HZ);
094963da
SC		 7111 lockup_detected = 0xffffffff;
7112 }
7113 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7114 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7115 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7116 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7117 pci_disable_device(h->pdev);
f2405db8 7118 fail_all_outstanding_cmds(h);
a0c12413
SC		 7119}
7120
25163bd5 7121static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7122{
7123 u64 now;
7124 u32 heartbeat;
7125 unsigned long flags;
7126
a0c12413
SC		 7127 now = get_jiffies_64();
7128 /* If we've received an interrupt recently, we're ok. */
7129 if (time_after64(h->last_intr_timestamp +
e85c5974 7130 (h->heartbeat_sample_interval), now))
25163bd5 7131 return false;
a0c12413
SC		 7132
7133 /*
7134 * If we've already checked the heartbeat recently, we're ok.
7135 * This could happen if someone sends us a signal. We
7136 * otherwise don't care about signals in this thread.
7137 */
7138 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7139 (h->heartbeat_sample_interval), now))
25163bd5 7140 return false;
a0c12413
SC		 7141
7142 /* If heartbeat has not changed since we last looked, we're not ok. */
7143 spin_lock_irqsave(&h->lock, flags);
7144 heartbeat = readl(&h->cfgtable->HeartBeat);
7145 spin_unlock_irqrestore(&h->lock, flags);
7146 if (h->last_heartbeat == heartbeat) {
7147 controller_lockup_detected(h);
25163bd5 7148 return true;
a0c12413
SC		 7149 }
7150
7151 /* We're ok. */
7152 h->last_heartbeat = heartbeat;
7153 h->last_heartbeat_timestamp = now;
25163bd5 7154 return false;
a0c12413
SC		 7155}
7156
9846590e 7157static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7158{
7159 int i;
7160 char *event_type;
7161
e4aa3e6a
SC		 7162 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7163 return;
7164
76438d08 7165 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7166 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7167 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7168 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7169 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7170
7171 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7172 event_type = "state change";
7173 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7174 event_type = "configuration change";
7175 /* Stop sending new RAID offload reqs via the IO accelerator */
7176 scsi_block_requests(h->scsi_host);
7177 for (i = 0; i < h->ndevices; i++)
7178 h->dev[i]->offload_enabled = 0;
23100dd9 7179 hpsa_drain_accel_commands(h);
76438d08
SC		 7180 /* Set 'accelerator path config change' bit */
7181 dev_warn(&h->pdev->dev,
7182 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7183 h->events, event_type);
7184 writel(h->events, &(h->cfgtable->clear_event_notify));
7185 /* Set the "clear event notify field update" bit 6 */
7186 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7187 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7188 hpsa_wait_for_clear_event_notify_ack(h);
7189 scsi_unblock_requests(h->scsi_host);
7190 } else {
7191 /* Acknowledge controller notification events. */
7192 writel(h->events, &(h->cfgtable->clear_event_notify));
7193 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7194 hpsa_wait_for_clear_event_notify_ack(h);
7195#if 0
7196 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7197 hpsa_wait_for_mode_change_ack(h);
7198#endif
7199 }
9846590e 7200 return;
76438d08
SC		 7201}
7202
7203/* Check a register on the controller to see if there are configuration
7204 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7205 * we should rescan the controller for devices.
7206 * Also check flag for driver-initiated rescan.
76438d08 7207 */
9846590e 7208static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7209{
7210 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7211 return 0;
76438d08
SC		 7212
7213 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7214 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7215}
76438d08 7216
9846590e
SC		 7217/*
7218 * Check if any of the offline devices have become ready
7219 */
7220static int hpsa_offline_devices_ready(struct ctlr_info *h)
7221{
7222 unsigned long flags;
7223 struct offline_device_entry *d;
7224 struct list_head *this, *tmp;
7225
7226 spin_lock_irqsave(&h->offline_device_lock, flags);
7227 list_for_each_safe(this, tmp, &h->offline_device_list) {
7228 d = list_entry(this, struct offline_device_entry,
7229 offline_list);
7230 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7231 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7232 spin_lock_irqsave(&h->offline_device_lock, flags);
7233 list_del(&d->offline_list);
7234 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7235 return 1;
d1fea47c 7236 }
9846590e
SC		 7237 spin_lock_irqsave(&h->offline_device_lock, flags);
7238 }
7239 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7240 return 0;
76438d08
SC		 7241}
7242
6636e7f4 7243static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7244{
7245 unsigned long flags;
8a98db73 7246 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7247 struct ctlr_info, rescan_ctlr_work);
7248
7249
7250 if (h->remove_in_progress)
8a98db73 7251 return;
9846590e
SC		 7252
7253 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7254 scsi_host_get(h->scsi_host);
9846590e
SC		 7255 hpsa_ack_ctlr_events(h);
7256 hpsa_scan_start(h->scsi_host);
7257 scsi_host_put(h->scsi_host);
7258 }
8a98db73 7259 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7260 if (!h->remove_in_progress)
7261 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7262 h->heartbeat_sample_interval);
7263 spin_unlock_irqrestore(&h->lock, flags);
7264}
7265
7266static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7267{
7268 unsigned long flags;
7269 struct ctlr_info *h = container_of(to_delayed_work(work),
7270 struct ctlr_info, monitor_ctlr_work);
7271
7272 detect_controller_lockup(h);
7273 if (lockup_detected(h))
a0c12413 7274 return;
6636e7f4
DB		 7275
7276 spin_lock_irqsave(&h->lock, flags);
7277 if (!h->remove_in_progress)
7278 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7279 h->heartbeat_sample_interval);
7280 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7281}
7282
6636e7f4
DB		 7283static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7284 char *name)
7285{
7286 struct workqueue_struct *wq = NULL;
6636e7f4 7287
397ea9cb 7288 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7289 if (!wq)
7290 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7291
7292 return wq;
7293}
7294
6f039790 7295static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7296{
4c2a8c40 7297 int dac, rc;
edd16368 7298 struct ctlr_info *h;
64670ac8
SC		 7299 int try_soft_reset = 0;
7300 unsigned long flags;
6b6c1cd7 7301 u32 board_id;
edd16368
SC		 7302
7303 if (number_of_controllers == 0)
7304 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7305
6b6c1cd7
TH		 7306 rc = hpsa_lookup_board_id(pdev, &board_id);
7307 if (rc < 0) {
7308 dev_warn(&pdev->dev, "Board ID not found\n");
7309 return rc;
7310 }
7311
7312 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7313 if (rc) {
7314 if (rc != -ENOTSUPP)
7315 return rc;
7316 /* If the reset fails in a particular way (it has no way to do
7317 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7318 * a soft reset once we get the controller configured up to the
7319 * point that it can accept a command.
7320 */
7321 try_soft_reset = 1;
7322 rc = 0;
7323 }
7324
7325reinit_after_soft_reset:
edd16368 7326
303932fd
DB		 7327 /* Command structures must be aligned on a 32-byte boundary because
7328 * the 5 lower bits of the address are used by the hardware. and by
7329 * the driver. See comments in hpsa.h for more info.
7330 */
303932fd 7331 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 7332 h = kzalloc(sizeof(*h), GFP_KERNEL);
7333 if (!h)
ecd9aad4 7334 return -ENOMEM;
edd16368 7335
55c06c71 7336 h->pdev = pdev;
a9a3a273 7337 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7338 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7339 spin_lock_init(&h->lock);
9846590e 7340 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7341 spin_lock_init(&h->scan_lock);
34f0c627 7342 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7343 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da 7344
6636e7f4
DB		 7345 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
7346 if (!h->rescan_ctlr_wq) {
7347 rc = -ENOMEM;
7348 goto clean1;
7349 }
7350
7351 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
080ef1cc 7352 if (!h->resubmit_wq) {
080ef1cc
DB		 7353 rc = -ENOMEM;
7354 goto clean1;
7355 }
6636e7f4 7356
094963da
SC		 7357 /* Allocate and clear per-cpu variable lockup_detected */
7358 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 7359 if (!h->lockup_detected) {
7360 rc = -ENOMEM;
094963da 7361 goto clean1;
2a5ac326 7362 }
094963da
SC		 7363 set_lockup_detected_for_all_cpus(h, 0);
7364
55c06c71 7365 rc = hpsa_pci_init(h);
ecd9aad4 7366 if (rc != 0)
edd16368
SC		 7367 goto clean1;
7368
f79cfec6 7369 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7370 h->ctlr = number_of_controllers;
7371 number_of_controllers++;
edd16368
SC		 7372
7373 /* configure PCI DMA stuff */
ecd9aad4
SC		 7374 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7375 if (rc == 0) {
edd16368 7376 dac = 1;
ecd9aad4
SC		 7377 } else {
7378 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7379 if (rc == 0) {
7380 dac = 0;
7381 } else {
7382 dev_err(&pdev->dev, "no suitable DMA available\n");
195f2c65 7383 goto clean2;
ecd9aad4 7384 }
edd16368
SC		 7385 }
7386
7387 /* make sure the board interrupts are off */
7388 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7389
9ee61794 7390 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7391 goto clean2;
303932fd
DB		 7392 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7393 h->devname, pdev->device,
a9a3a273 7394 h->intr[h->intr_mode], dac ? "" : " not");
d37ffbe4 7395 rc = hpsa_alloc_cmd_pool(h);
8947fd10
RE		 7396 if (rc)
7397 goto clean2_and_free_irqs;
33a2ffce
SC		 7398 if (hpsa_allocate_sg_chain_blocks(h))
7399 goto clean4;
a08a8471 7400 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7401 init_waitqueue_head(&h->abort_cmd_wait_queue);
a08a8471 7402 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7403
7404 pci_set_drvdata(pdev, h);
9a41338e 7405 h->ndevices = 0;
316b221a 7406 h->hba_mode_enabled = 0;
9a41338e
SC		 7407 h->scsi_host = NULL;
7408 spin_lock_init(&h->devlock);
64670ac8
SC		 7409 hpsa_put_ctlr_into_performant_mode(h);
7410
7411 /* At this point, the controller is ready to take commands.
7412 * Now, if reset_devices and the hard reset didn't work, try
7413 * the soft reset and see if that works.
7414 */
7415 if (try_soft_reset) {
7416
7417 /* This is kind of gross. We may or may not get a completion
7418 * from the soft reset command, and if we do, then the value
7419 * from the fifo may or may not be valid. So, we wait 10 secs
7420 * after the reset throwing away any completions we get during
7421 * that time. Unregister the interrupt handler and register
7422 * fake ones to scoop up any residual completions.
7423 */
7424 spin_lock_irqsave(&h->lock, flags);
7425 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7426 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 7427 hpsa_free_irqs(h);
9ee61794 7428 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 7429 hpsa_intx_discard_completions);
7430 if (rc) {
9ee61794
RE		 7431 dev_warn(&h->pdev->dev,
7432 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 7433 goto clean4;
7434 }
7435
7436 rc = hpsa_kdump_soft_reset(h);
7437 if (rc)
7438 /* Neither hard nor soft reset worked, we're hosed. */
7439 goto clean4;
7440
7441 dev_info(&h->pdev->dev, "Board READY.\n");
7442 dev_info(&h->pdev->dev,
7443 "Waiting for stale completions to drain.\n");
7444 h->access.set_intr_mask(h, HPSA_INTR_ON);
7445 msleep(10000);
7446 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7447
7448 rc = controller_reset_failed(h->cfgtable);
7449 if (rc)
7450 dev_info(&h->pdev->dev,
7451 "Soft reset appears to have failed.\n");
7452
7453 /* since the controller's reset, we have to go back and re-init
7454 * everything. Easiest to just forget what we've done and do it
7455 * all over again.
7456 */
7457 hpsa_undo_allocations_after_kdump_soft_reset(h);
7458 try_soft_reset = 0;
7459 if (rc)
7460 /* don't go to clean4, we already unallocated */
7461 return -ENODEV;
7462
7463 goto reinit_after_soft_reset;
7464 }
edd16368 7465
316b221a
SC		 7466 /* Enable Accelerated IO path at driver layer */
7467 h->acciopath_status = 1;
da0697bd 7468
e863d68e 7469
edd16368
SC		 7470 /* Turn the interrupts on so we can service requests */
7471 h->access.set_intr_mask(h, HPSA_INTR_ON);
7472
339b2b14 7473 hpsa_hba_inquiry(h);
4a4384ce
SC		 7474 rc = hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
7475 if (rc)
7476 goto clean4;
8a98db73
SC		 7477
7478 /* Monitor the controller for firmware lockups */
7479 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7480 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7481 schedule_delayed_work(&h->monitor_ctlr_work,
7482 h->heartbeat_sample_interval);
6636e7f4
DB		 7483 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
7484 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7485 h->heartbeat_sample_interval);
88bf6d62 7486 return 0;
edd16368
SC		 7487
7488clean4:
33a2ffce 7489 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7490 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7491 hpsa_free_ioaccel1_cmd_and_bft(h);
7492 hpsa_free_ioaccel2_cmd_and_bft(h);
8947fd10 7493clean2_and_free_irqs:
ec501a18 7494 hpsa_free_irqs(h);
edd16368 7495clean2:
195f2c65 7496 hpsa_free_pci_init(h);
edd16368 7497clean1:
080ef1cc
DB		 7498 if (h->resubmit_wq)
7499 destroy_workqueue(h->resubmit_wq);
6636e7f4
DB		 7500 if (h->rescan_ctlr_wq)
7501 destroy_workqueue(h->rescan_ctlr_wq);
094963da
SC		 7502 if (h->lockup_detected)
7503 free_percpu(h->lockup_detected);
edd16368 7504 kfree(h);
ecd9aad4 7505 return rc;
edd16368
SC		 7506}
7507
7508static void hpsa_flush_cache(struct ctlr_info *h)
7509{
7510 char *flush_buf;
7511 struct CommandList *c;
25163bd5 7512 int rc;
702890e3
SC		 7513
7514 /* Don't bother trying to flush the cache if locked up */
25163bd5 7515 /* FIXME not necessary if do_simple_cmd does the check */
094963da 7516 if (unlikely(lockup_detected(h)))
702890e3 7517 return;
edd16368
SC		 7518 flush_buf = kzalloc(4, GFP_KERNEL);
7519 if (!flush_buf)
7520 return;
7521
45fcb86e 7522 c = cmd_alloc(h);
edd16368 7523 if (!c) {
45fcb86e 7524 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7525 goto out_of_memory;
7526 }
a2dac136
SC		 7527 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7528 RAID_CTLR_LUNID, TYPE_CMD)) {
7529 goto out;
7530 }
25163bd5
WS		 7531 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
7532 PCI_DMA_TODEVICE, NO_TIMEOUT);
7533 if (rc)
7534 goto out;
edd16368 7535 if (c->err_info->CommandStatus != 0)
a2dac136 7536out:
edd16368
SC		 7537 dev_warn(&h->pdev->dev,
7538 "error flushing cache on controller\n");
45fcb86e 7539 cmd_free(h, c);
edd16368
SC		 7540out_of_memory:
7541 kfree(flush_buf);
7542}
7543
7544static void hpsa_shutdown(struct pci_dev *pdev)
7545{
7546 struct ctlr_info *h;
7547
7548 h = pci_get_drvdata(pdev);
7549 /* Turn board interrupts off and send the flush cache command
7550 * sendcmd will turn off interrupt, and send the flush...
7551 * To write all data in the battery backed cache to disks
7552 */
7553 hpsa_flush_cache(h);
7554 h->access.set_intr_mask(h, HPSA_INTR_OFF);
cc64c817
RE		 7555 hpsa_free_irqs(h);
7556 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 7557}
7558
6f039790 7559static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7560{
7561 int i;
7562
7563 for (i = 0; i < h->ndevices; i++)
7564 kfree(h->dev[i]);
7565}
7566
6f039790 7567static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7568{
7569 struct ctlr_info *h;
8a98db73 7570 unsigned long flags;
edd16368
SC		 7571
7572 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7573 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7574 return;
7575 }
7576 h = pci_get_drvdata(pdev);
8a98db73
SC		 7577
7578 /* Get rid of any controller monitoring work items */
7579 spin_lock_irqsave(&h->lock, flags);
7580 h->remove_in_progress = 1;
8a98db73 7581 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 7582 cancel_delayed_work_sync(&h->monitor_ctlr_work);
7583 cancel_delayed_work_sync(&h->rescan_ctlr_work);
7584 destroy_workqueue(h->rescan_ctlr_wq);
7585 destroy_workqueue(h->resubmit_wq);
edd16368 7586 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
cc64c817 7587
195f2c65
RE		 7588 /* includes hpsa_free_irqs */
7589 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 7590 hpsa_shutdown(pdev);
cc64c817 7591
55e14e76 7592 hpsa_free_device_info(h);
33a2ffce 7593 hpsa_free_sg_chain_blocks(h);
1fb7c98a
RE		 7594 kfree(h->blockFetchTable); /* perf 2 */
7595 hpsa_free_reply_queues(h); /* perf 1 */
7596 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7597 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
7598 hpsa_free_cmd_pool(h); /* init_one 5 */
339b2b14 7599 kfree(h->hba_inquiry_data);
195f2c65
RE		 7600
7601 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
7602 hpsa_free_pci_init(h);
7603
094963da 7604 free_percpu(h->lockup_detected);
edd16368
SC		 7605 kfree(h);
7606}
7607
7608static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7609 __attribute__((unused)) pm_message_t state)
7610{
7611 return -ENOSYS;
7612}
7613
7614static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7615{
7616 return -ENOSYS;
7617}
7618
7619static struct pci_driver hpsa_pci_driver = {
f79cfec6 7620 .name = HPSA,
edd16368 7621 .probe = hpsa_init_one,
6f039790 7622 .remove = hpsa_remove_one,
edd16368
SC		 7623 .id_table = hpsa_pci_device_id, /* id_table */
7624 .shutdown = hpsa_shutdown,
7625 .suspend = hpsa_suspend,
7626 .resume = hpsa_resume,
7627};
7628
303932fd
DB		 7629/* Fill in bucket_map[], given nsgs (the max number of
7630 * scatter gather elements supported) and bucket[],
7631 * which is an array of 8 integers. The bucket[] array
7632 * contains 8 different DMA transfer sizes (in 16
7633 * byte increments) which the controller uses to fetch
7634 * commands. This function fills in bucket_map[], which
7635 * maps a given number of scatter gather elements to one of
7636 * the 8 DMA transfer sizes. The point of it is to allow the
7637 * controller to only do as much DMA as needed to fetch the
7638 * command, with the DMA transfer size encoded in the lower
7639 * bits of the command address.
7640 */
7641static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7642 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7643{
7644 int i, j, b, size;
7645
303932fd
DB		 7646 /* Note, bucket_map must have nsgs+1 entries. */
7647 for (i = 0; i <= nsgs; i++) {
7648 /* Compute size of a command with i SG entries */
e1f7de0c 7649 size = i + min_blocks;
303932fd
DB		 7650 b = num_buckets; /* Assume the biggest bucket */
7651 /* Find the bucket that is just big enough */
e1f7de0c 7652 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7653 if (bucket[j] >= size) {
7654 b = j;
7655 break;
7656 }
7657 }
7658 /* for a command with i SG entries, use bucket b. */
7659 bucket_map[i] = b;
7660 }
7661}
7662
c706a795
RE		 7663/* return -ENODEV or other reason on error, 0 on success */
7664static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7665{
6c311b57
SC		 7666 int i;
7667 unsigned long register_value;
e1f7de0c
MG		 7668 unsigned long transMethod = CFGTBL_Trans_Performant |
7669 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7670 CFGTBL_Trans_enable_directed_msix |
7671 (trans_support & (CFGTBL_Trans_io_accel1 |
7672 CFGTBL_Trans_io_accel2));
e1f7de0c 7673 struct access_method access = SA5_performant_access;
def342bd
SC		 7674
7675 /* This is a bit complicated. There are 8 registers on
7676 * the controller which we write to to tell it 8 different
7677 * sizes of commands which there may be. It's a way of
7678 * reducing the DMA done to fetch each command. Encoded into
7679 * each command's tag are 3 bits which communicate to the controller
7680 * which of the eight sizes that command fits within. The size of
7681 * each command depends on how many scatter gather entries there are.
7682 * Each SG entry requires 16 bytes. The eight registers are programmed
7683 * with the number of 16-byte blocks a command of that size requires.
7684 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7685 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7686 * blocks. Note, this only extends to the SG entries contained
7687 * within the command block, and does not extend to chained blocks
7688 * of SG elements. bft[] contains the eight values we write to
7689 * the registers. They are not evenly distributed, but have more
7690 * sizes for small commands, and fewer sizes for larger commands.
7691 */
d66ae08b 7692 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7693#define MIN_IOACCEL2_BFT_ENTRY 5
7694#define HPSA_IOACCEL2_HEADER_SZ 4
7695 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7696 13, 14, 15, 16, 17, 18, 19,
7697 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7698 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7699 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7700 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7701 16 * MIN_IOACCEL2_BFT_ENTRY);
7702 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7703 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7704 /* 5 = 1 s/g entry or 4k
7705 * 6 = 2 s/g entry or 8k
7706 * 8 = 4 s/g entry or 16k
7707 * 10 = 6 s/g entry or 24k
7708 */
303932fd 7709
b3a52e79
SC		 7710 /* If the controller supports either ioaccel method then
7711 * we can also use the RAID stack submit path that does not
7712 * perform the superfluous readl() after each command submission.
7713 */
7714 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7715 access = SA5_performant_access_no_read;
7716
303932fd 7717 /* Controller spec: zero out this buffer. */
072b0518
SC		 7718 for (i = 0; i < h->nreply_queues; i++)
7719 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7720
d66ae08b
SC		 7721 bft[7] = SG_ENTRIES_IN_CMD + 4;
7722 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7723 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7724 for (i = 0; i < 8; i++)
7725 writel(bft[i], &h->transtable->BlockFetch[i]);
7726
7727 /* size of controller ring buffer */
7728 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7729 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7730 writel(0, &h->transtable->RepQCtrAddrLow32);
7731 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7732
7733 for (i = 0; i < h->nreply_queues; i++) {
7734 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7735 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7736 &h->transtable->RepQAddr[i].lower);
7737 }
7738
b9af4937 7739 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7740 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7741 /*
7742 * enable outbound interrupt coalescing in accelerator mode;
7743 */
7744 if (trans_support & CFGTBL_Trans_io_accel1) {
7745 access = SA5_ioaccel_mode1_access;
7746 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7747 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7748 } else {
7749 if (trans_support & CFGTBL_Trans_io_accel2) {
7750 access = SA5_ioaccel_mode2_access;
7751 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7752 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7753 }
e1f7de0c 7754 }
303932fd 7755 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7756 if (hpsa_wait_for_mode_change_ack(h)) {
7757 dev_err(&h->pdev->dev,
7758 "performant mode problem - doorbell timeout\n");
7759 return -ENODEV;
7760 }
303932fd
DB		 7761 register_value = readl(&(h->cfgtable->TransportActive));
7762 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7763 dev_err(&h->pdev->dev,
7764 "performant mode problem - transport not active\n");
c706a795 7765 return -ENODEV;
303932fd 7766 }
960a30e7 7767 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7768 h->access = access;
7769 h->transMethod = transMethod;
7770
b9af4937
SC		 7771 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7772 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 7773 return 0;
e1f7de0c 7774
b9af4937
SC		 7775 if (trans_support & CFGTBL_Trans_io_accel1) {
7776 /* Set up I/O accelerator mode */
7777 for (i = 0; i < h->nreply_queues; i++) {
7778 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7779 h->reply_queue[i].current_entry =
7780 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7781 }
7782 bft[7] = h->ioaccel_maxsg + 8;
7783 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7784 h->ioaccel1_blockFetchTable);
e1f7de0c 7785
b9af4937 7786 /* initialize all reply queue entries to unused */
072b0518
SC		 7787 for (i = 0; i < h->nreply_queues; i++)
7788 memset(h->reply_queue[i].head,
7789 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7790 h->reply_queue_size);
e1f7de0c 7791
b9af4937
SC		 7792 /* set all the constant fields in the accelerator command
7793 * frames once at init time to save CPU cycles later.
7794 */
7795 for (i = 0; i < h->nr_cmds; i++) {
7796 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7797
7798 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7799 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7800 (i * sizeof(struct ErrorInfo)));
7801 cp->err_info_len = sizeof(struct ErrorInfo);
7802 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7803 cp->host_context_flags =
7804 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7805 cp->timeout_sec = 0;
7806 cp->ReplyQueue = 0;
50a0decf 7807 cp->tag =
f2405db8 7808 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7809 cp->host_addr =
7810 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7811 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7812 }
7813 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7814 u64 cfg_offset, cfg_base_addr_index;
7815 u32 bft2_offset, cfg_base_addr;
7816 int rc;
7817
7818 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7819 &cfg_base_addr_index, &cfg_offset);
7820 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7821 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7822 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7823 4, h->ioaccel2_blockFetchTable);
7824 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7825 BUILD_BUG_ON(offsetof(struct CfgTable,
7826 io_accel_request_size_offset) != 0xb8);
7827 h->ioaccel2_bft2_regs =
7828 remap_pci_mem(pci_resource_start(h->pdev,
7829 cfg_base_addr_index) +
7830 cfg_offset + bft2_offset,
7831 ARRAY_SIZE(bft2) *
7832 sizeof(*h->ioaccel2_bft2_regs));
7833 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7834 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7835 }
b9af4937 7836 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7837 if (hpsa_wait_for_mode_change_ack(h)) {
7838 dev_err(&h->pdev->dev,
7839 "performant mode problem - enabling ioaccel mode\n");
7840 return -ENODEV;
7841 }
7842 return 0;
e1f7de0c
MG		 7843}
7844
1fb7c98a
RE		 7845/* Free ioaccel1 mode command blocks and block fetch table */
7846static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
7847{
7848 if (h->ioaccel_cmd_pool)
7849 pci_free_consistent(h->pdev,
7850 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7851 h->ioaccel_cmd_pool,
7852 h->ioaccel_cmd_pool_dhandle);
7853 kfree(h->ioaccel1_blockFetchTable);
7854}
7855
d37ffbe4
RE		 7856/* Allocate ioaccel1 mode command blocks and block fetch table */
7857static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 7858{
283b4a9b
SC		 7859 h->ioaccel_maxsg =
7860 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7861 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7862 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7863
e1f7de0c
MG		 7864 /* Command structures must be aligned on a 128-byte boundary
7865 * because the 7 lower bits of the address are used by the
7866 * hardware.
7867 */
e1f7de0c
MG		 7868 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7869 IOACCEL1_COMMANDLIST_ALIGNMENT);
7870 h->ioaccel_cmd_pool =
7871 pci_alloc_consistent(h->pdev,
7872 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7873 &(h->ioaccel_cmd_pool_dhandle));
7874
7875 h->ioaccel1_blockFetchTable =
283b4a9b 7876 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7877 sizeof(u32)), GFP_KERNEL);
7878
7879 if ((h->ioaccel_cmd_pool == NULL) ||
7880 (h->ioaccel1_blockFetchTable == NULL))
7881 goto clean_up;
7882
7883 memset(h->ioaccel_cmd_pool, 0,
7884 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7885 return 0;
7886
7887clean_up:
1fb7c98a 7888 hpsa_free_ioaccel1_cmd_and_bft(h);
e1f7de0c 7889 return 1;
6c311b57
SC		 7890}
7891
1fb7c98a
RE		 7892/* Free ioaccel2 mode command blocks and block fetch table */
7893static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
7894{
7895 if (h->ioaccel2_cmd_pool)
7896 pci_free_consistent(h->pdev,
7897 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7898 h->ioaccel2_cmd_pool,
7899 h->ioaccel2_cmd_pool_dhandle);
7900 kfree(h->ioaccel2_blockFetchTable);
7901}
7902
d37ffbe4
RE		 7903/* Allocate ioaccel2 mode command blocks and block fetch table */
7904static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a
SC		 7905{
7906 /* Allocate ioaccel2 mode command blocks and block fetch table */
7907
7908 h->ioaccel_maxsg =
7909 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7910 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7911 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7912
aca9012a
SC		 7913 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7914 IOACCEL2_COMMANDLIST_ALIGNMENT);
7915 h->ioaccel2_cmd_pool =
7916 pci_alloc_consistent(h->pdev,
7917 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7918 &(h->ioaccel2_cmd_pool_dhandle));
7919
7920 h->ioaccel2_blockFetchTable =
7921 kmalloc(((h->ioaccel_maxsg + 1) *
7922 sizeof(u32)), GFP_KERNEL);
7923
7924 if ((h->ioaccel2_cmd_pool == NULL) ||
7925 (h->ioaccel2_blockFetchTable == NULL))
7926 goto clean_up;
7927
7928 memset(h->ioaccel2_cmd_pool, 0,
7929 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7930 return 0;
7931
7932clean_up:
1fb7c98a 7933 hpsa_free_ioaccel2_cmd_and_bft(h);
aca9012a
SC		 7934 return 1;
7935}
7936
6f039790 7937static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7938{
7939 u32 trans_support;
e1f7de0c
MG		 7940 unsigned long transMethod = CFGTBL_Trans_Performant |
7941 CFGTBL_Trans_use_short_tags;
254f796b 7942 int i;
6c311b57 7943
02ec19c8
SC		 7944 if (hpsa_simple_mode)
7945 return;
7946
67c99a72 7947 trans_support = readl(&(h->cfgtable->TransportSupport));
7948 if (!(trans_support & PERFORMANT_MODE))
7949 return;
7950
e1f7de0c
MG		 7951 /* Check for I/O accelerator mode support */
7952 if (trans_support & CFGTBL_Trans_io_accel1) {
7953 transMethod |= CFGTBL_Trans_io_accel1 |
7954 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 7955 if (hpsa_alloc_ioaccel1_cmd_and_bft(h))
e1f7de0c 7956 goto clean_up;
aca9012a
SC		 7957 } else {
7958 if (trans_support & CFGTBL_Trans_io_accel2) {
7959 transMethod |= CFGTBL_Trans_io_accel2 |
7960 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 7961 if (hpsa_alloc_ioaccel2_cmd_and_bft(h))
aca9012a
SC		 7962 goto clean_up;
7963 }
e1f7de0c
MG		 7964 }
7965
eee0f03a 7966 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7967 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7968 /* Performant mode ring buffer and supporting data structures */
072b0518 7969 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7970
254f796b 7971 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7972 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7973 h->reply_queue_size,
7974 &(h->reply_queue[i].busaddr));
7975 if (!h->reply_queue[i].head)
7976 goto clean_up;
254f796b
MG		 7977 h->reply_queue[i].size = h->max_commands;
7978 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7979 h->reply_queue[i].current_entry = 0;
7980 }
7981
6c311b57 7982 /* Need a block fetch table for performant mode */
d66ae08b 7983 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7984 sizeof(u32)), GFP_KERNEL);
072b0518 7985 if (!h->blockFetchTable)
6c311b57
SC		 7986 goto clean_up;
7987
e1f7de0c 7988 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7989 return;
7990
7991clean_up:
072b0518 7992 hpsa_free_reply_queues(h);
303932fd
DB		 7993 kfree(h->blockFetchTable);
7994}
7995
23100dd9 7996static int is_accelerated_cmd(struct CommandList *c)
76438d08 7997{
23100dd9
SC		 7998 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7999}
8000
8001static void hpsa_drain_accel_commands(struct ctlr_info *h)
8002{
8003 struct CommandList *c = NULL;
f2405db8 8004 int i, accel_cmds_out;
281a7fd0 8005 int refcount;
76438d08 8006
f2405db8 8007 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8008 accel_cmds_out = 0;
f2405db8 8009 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8010 c = h->cmd_pool + i;
281a7fd0
WS		 8011 refcount = atomic_inc_return(&c->refcount);
8012 if (refcount > 1) /* Command is allocated */
8013 accel_cmds_out += is_accelerated_cmd(c);
8014 cmd_free(h, c);
f2405db8 8015 }
23100dd9 8016 if (accel_cmds_out <= 0)
281a7fd0 8017 break;
76438d08
SC		 8018 msleep(100);
8019 } while (1);
8020}
8021
edd16368
SC		 8022/*
8023 * This is it. Register the PCI driver information for the cards we control
8024 * the OS will call our registered routines when it finds one of our cards.
8025 */
8026static int __init hpsa_init(void)
8027{
31468401 8028 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8029}
8030
8031static void __exit hpsa_cleanup(void)
8032{
8033 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8034}
8035
e1f7de0c
MG		 8036static void __attribute__((unused)) verify_offsets(void)
8037{
dd0e19f3
ST		 8038#define VERIFY_OFFSET(member, offset) \
8039 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8040
8041 VERIFY_OFFSET(structure_size, 0);
8042 VERIFY_OFFSET(volume_blk_size, 4);
8043 VERIFY_OFFSET(volume_blk_cnt, 8);
8044 VERIFY_OFFSET(phys_blk_shift, 16);
8045 VERIFY_OFFSET(parity_rotation_shift, 17);
8046 VERIFY_OFFSET(strip_size, 18);
8047 VERIFY_OFFSET(disk_starting_blk, 20);
8048 VERIFY_OFFSET(disk_blk_cnt, 28);
8049 VERIFY_OFFSET(data_disks_per_row, 36);
8050 VERIFY_OFFSET(metadata_disks_per_row, 38);
8051 VERIFY_OFFSET(row_cnt, 40);
8052 VERIFY_OFFSET(layout_map_count, 42);
8053 VERIFY_OFFSET(flags, 44);
8054 VERIFY_OFFSET(dekindex, 46);
8055 /* VERIFY_OFFSET(reserved, 48 */
8056 VERIFY_OFFSET(data, 64);
8057
8058#undef VERIFY_OFFSET
8059
b66cc250
MM		 8060#define VERIFY_OFFSET(member, offset) \
8061 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8062
8063 VERIFY_OFFSET(IU_type, 0);
8064 VERIFY_OFFSET(direction, 1);
8065 VERIFY_OFFSET(reply_queue, 2);
8066 /* VERIFY_OFFSET(reserved1, 3); */
8067 VERIFY_OFFSET(scsi_nexus, 4);
8068 VERIFY_OFFSET(Tag, 8);
8069 VERIFY_OFFSET(cdb, 16);
8070 VERIFY_OFFSET(cciss_lun, 32);
8071 VERIFY_OFFSET(data_len, 40);
8072 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8073 VERIFY_OFFSET(sg_count, 45);
8074 /* VERIFY_OFFSET(reserved3 */
8075 VERIFY_OFFSET(err_ptr, 48);
8076 VERIFY_OFFSET(err_len, 56);
8077 /* VERIFY_OFFSET(reserved4 */
8078 VERIFY_OFFSET(sg, 64);
8079
8080#undef VERIFY_OFFSET
8081
e1f7de0c
MG		 8082#define VERIFY_OFFSET(member, offset) \
8083 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8084
8085 VERIFY_OFFSET(dev_handle, 0x00);
8086 VERIFY_OFFSET(reserved1, 0x02);
8087 VERIFY_OFFSET(function, 0x03);
8088 VERIFY_OFFSET(reserved2, 0x04);
8089 VERIFY_OFFSET(err_info, 0x0C);
8090 VERIFY_OFFSET(reserved3, 0x10);
8091 VERIFY_OFFSET(err_info_len, 0x12);
8092 VERIFY_OFFSET(reserved4, 0x13);
8093 VERIFY_OFFSET(sgl_offset, 0x14);
8094 VERIFY_OFFSET(reserved5, 0x15);
8095 VERIFY_OFFSET(transfer_len, 0x1C);
8096 VERIFY_OFFSET(reserved6, 0x20);
8097 VERIFY_OFFSET(io_flags, 0x24);
8098 VERIFY_OFFSET(reserved7, 0x26);
8099 VERIFY_OFFSET(LUN, 0x34);
8100 VERIFY_OFFSET(control, 0x3C);
8101 VERIFY_OFFSET(CDB, 0x40);
8102 VERIFY_OFFSET(reserved8, 0x50);
8103 VERIFY_OFFSET(host_context_flags, 0x60);
8104 VERIFY_OFFSET(timeout_sec, 0x62);
8105 VERIFY_OFFSET(ReplyQueue, 0x64);
8106 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8107 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8108 VERIFY_OFFSET(host_addr, 0x70);
8109 VERIFY_OFFSET(CISS_LUN, 0x78);
8110 VERIFY_OFFSET(SG, 0x78 + 8);
8111#undef VERIFY_OFFSET
8112}
8113
edd16368
SC		 8114module_init(hpsa_init);
8115module_exit(hpsa_cleanup);
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