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hpsa: fix race between abort handler and main i/o path
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
2b08b3e9 53#include <asm/unaligned.h>
283b4a9b 54#include <asm/div64.h>
edd16368
SC		 55#include "hpsa_cmd.h"
56#include "hpsa.h"
57
58/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 59#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 60#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 61#define HPSA "hpsa"
edd16368
SC		 62
63/* How long to wait (in milliseconds) for board to go into simple mode */
64#define MAX_CONFIG_WAIT 30000
65#define MAX_IOCTL_CONFIG_WAIT 1000
66
67/*define how many times we will try a command because of bus resets */
68#define MAX_CMD_RETRIES 3
69
70/* Embedded module documentation macros - see modules.h */
71MODULE_AUTHOR("Hewlett-Packard Company");
72MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
73 HPSA_DRIVER_VERSION);
74MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
75MODULE_VERSION(HPSA_DRIVER_VERSION);
76MODULE_LICENSE("GPL");
77
78static int hpsa_allow_any;
79module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
80MODULE_PARM_DESC(hpsa_allow_any,
81 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 82static int hpsa_simple_mode;
83module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_simple_mode,
85 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 86
87/* define the PCI info for the cards we can control */
88static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
132 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
133 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 134 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 135 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 136 {0,}
137};
138
139MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
140
141/* board_id = Subsystem Device ID & Vendor ID
142 * product = Marketing Name for the board
143 * access = Address of the struct of function pointers
144 */
145static struct board_type products[] = {
edd16368
SC		 146 {0x3241103C, "Smart Array P212", &SA5_access},
147 {0x3243103C, "Smart Array P410", &SA5_access},
148 {0x3245103C, "Smart Array P410i", &SA5_access},
149 {0x3247103C, "Smart Array P411", &SA5_access},
150 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 151 {0x324A103C, "Smart Array P712m", &SA5_access},
152 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 153 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 154 {0x3350103C, "Smart Array P222", &SA5_access},
155 {0x3351103C, "Smart Array P420", &SA5_access},
156 {0x3352103C, "Smart Array P421", &SA5_access},
157 {0x3353103C, "Smart Array P822", &SA5_access},
158 {0x3354103C, "Smart Array P420i", &SA5_access},
159 {0x3355103C, "Smart Array P220i", &SA5_access},
160 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 161 {0x1921103C, "Smart Array P830i", &SA5_access},
162 {0x1922103C, "Smart Array P430", &SA5_access},
163 {0x1923103C, "Smart Array P431", &SA5_access},
164 {0x1924103C, "Smart Array P830", &SA5_access},
165 {0x1926103C, "Smart Array P731m", &SA5_access},
166 {0x1928103C, "Smart Array P230i", &SA5_access},
167 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 168 {0x21BD103C, "Smart Array", &SA5_access},
169 {0x21BE103C, "Smart Array", &SA5_access},
170 {0x21BF103C, "Smart Array", &SA5_access},
171 {0x21C0103C, "Smart Array", &SA5_access},
172 {0x21C1103C, "Smart Array", &SA5_access},
173 {0x21C2103C, "Smart Array", &SA5_access},
174 {0x21C3103C, "Smart Array", &SA5_access},
175 {0x21C4103C, "Smart Array", &SA5_access},
176 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 177 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 178 {0x21C7103C, "Smart Array", &SA5_access},
179 {0x21C8103C, "Smart Array", &SA5_access},
180 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 181 {0x21CA103C, "Smart Array", &SA5_access},
182 {0x21CB103C, "Smart Array", &SA5_access},
183 {0x21CC103C, "Smart Array", &SA5_access},
184 {0x21CD103C, "Smart Array", &SA5_access},
185 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 186 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
187 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
188 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
189 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
190 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 191 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
192};
193
194static int number_of_controllers;
195
10f66018
SC		 196static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
197static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 198static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 199
200#ifdef CONFIG_COMPAT
42a91641
DB		 201static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
202 void __user *arg);
edd16368
SC		 203#endif
204
205static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 206static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 207static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 208 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 209 int cmd_type);
2c143342 210static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 211#define VPD_PAGE (1 << 8)
edd16368 212
f281233d 213static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 214static void hpsa_scan_start(struct Scsi_Host *);
215static int hpsa_scan_finished(struct Scsi_Host *sh,
216 unsigned long elapsed_time);
7c0a0229 217static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 218
219static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 220static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 221static int hpsa_slave_alloc(struct scsi_device *sdev);
222static void hpsa_slave_destroy(struct scsi_device *sdev);
223
edd16368 224static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 225static int check_for_unit_attention(struct ctlr_info *h,
226 struct CommandList *c);
227static void check_ioctl_unit_attention(struct ctlr_info *h,
228 struct CommandList *c);
303932fd
DB		 229/* performant mode helper functions */
230static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 231 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 232static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 233static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 234static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
235 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
236 u64 *cfg_offset);
237static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
238 unsigned long *memory_bar);
239static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
240static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
241 int wait_for_ready);
75167d2c 242static inline void finish_cmd(struct CommandList *c);
283b4a9b 243static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 244#define BOARD_NOT_READY 0
245#define BOARD_READY 1
23100dd9 246static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 247static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 248static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
249 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 250 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 251static void hpsa_command_resubmit_worker(struct work_struct *work);
edd16368 252
edd16368
SC		 253static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
254{
255 unsigned long *priv = shost_priv(sdev->host);
256 return (struct ctlr_info *) *priv;
257}
258
a23513e8
SC		 259static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
260{
261 unsigned long *priv = shost_priv(sh);
262 return (struct ctlr_info *) *priv;
263}
264
edd16368
SC		 265static int check_for_unit_attention(struct ctlr_info *h,
266 struct CommandList *c)
267{
268 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
269 return 0;
270
271 switch (c->err_info->SenseInfo[12]) {
272 case STATE_CHANGED:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 274 "detected, command retried\n", h->ctlr);
275 break;
276 case LUN_FAILED:
7f73695a
SC		 277 dev_warn(&h->pdev->dev,
278 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 279 break;
280 case REPORT_LUNS_CHANGED:
7f73695a
SC		 281 dev_warn(&h->pdev->dev,
282 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 283 /*
4f4eb9f1
ST		 284 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
285 * target (array) devices.
edd16368
SC		 286 */
287 break;
288 case POWER_OR_RESET:
f79cfec6 289 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 290 "or device reset detected\n", h->ctlr);
291 break;
292 case UNIT_ATTENTION_CLEARED:
f79cfec6 293 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 294 "cleared by another initiator\n", h->ctlr);
295 break;
296 default:
f79cfec6 297 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 298 "unit attention detected\n", h->ctlr);
299 break;
300 }
301 return 1;
302}
303
852af20a
MB		 304static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
305{
306 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
307 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
308 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
309 return 0;
310 dev_warn(&h->pdev->dev, HPSA "device busy");
311 return 1;
312}
313
da0697bd
ST		 314static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 int status, len;
319 struct ctlr_info *h;
320 struct Scsi_Host *shost = class_to_shost(dev);
321 char tmpbuf[10];
322
323 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
324 return -EACCES;
325 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
326 strncpy(tmpbuf, buf, len);
327 tmpbuf[len] = '\0';
328 if (sscanf(tmpbuf, "%d", &status) != 1)
329 return -EINVAL;
330 h = shost_to_hba(shost);
331 h->acciopath_status = !!status;
332 dev_warn(&h->pdev->dev,
333 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
334 h->acciopath_status ? "enabled" : "disabled");
335 return count;
336}
337
2ba8bfc8
SC		 338static ssize_t host_store_raid_offload_debug(struct device *dev,
339 struct device_attribute *attr,
340 const char *buf, size_t count)
341{
342 int debug_level, len;
343 struct ctlr_info *h;
344 struct Scsi_Host *shost = class_to_shost(dev);
345 char tmpbuf[10];
346
347 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
348 return -EACCES;
349 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
350 strncpy(tmpbuf, buf, len);
351 tmpbuf[len] = '\0';
352 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
353 return -EINVAL;
354 if (debug_level < 0)
355 debug_level = 0;
356 h = shost_to_hba(shost);
357 h->raid_offload_debug = debug_level;
358 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
359 h->raid_offload_debug);
360 return count;
361}
362
edd16368
SC		 363static ssize_t host_store_rescan(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366{
367 struct ctlr_info *h;
368 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 369 h = shost_to_hba(shost);
31468401 370 hpsa_scan_start(h->scsi_host);
edd16368
SC		 371 return count;
372}
373
d28ce020
SC		 374static ssize_t host_show_firmware_revision(struct device *dev,
375 struct device_attribute *attr, char *buf)
376{
377 struct ctlr_info *h;
378 struct Scsi_Host *shost = class_to_shost(dev);
379 unsigned char *fwrev;
380
381 h = shost_to_hba(shost);
382 if (!h->hba_inquiry_data)
383 return 0;
384 fwrev = &h->hba_inquiry_data[32];
385 return snprintf(buf, 20, "%c%c%c%c\n",
386 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
387}
388
94a13649
SC		 389static ssize_t host_show_commands_outstanding(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 struct Scsi_Host *shost = class_to_shost(dev);
393 struct ctlr_info *h = shost_to_hba(shost);
394
0cbf768e
SC		 395 return snprintf(buf, 20, "%d\n",
396 atomic_read(&h->commands_outstanding));
94a13649
SC		 397}
398
745a7a25
SC		 399static ssize_t host_show_transport_mode(struct device *dev,
400 struct device_attribute *attr, char *buf)
401{
402 struct ctlr_info *h;
403 struct Scsi_Host *shost = class_to_shost(dev);
404
405 h = shost_to_hba(shost);
406 return snprintf(buf, 20, "%s\n",
960a30e7 407 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 408 "performant" : "simple");
409}
410
da0697bd
ST		 411static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
412 struct device_attribute *attr, char *buf)
413{
414 struct ctlr_info *h;
415 struct Scsi_Host *shost = class_to_shost(dev);
416
417 h = shost_to_hba(shost);
418 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
419 (h->acciopath_status == 1) ? "enabled" : "disabled");
420}
421
46380786 422/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 423static u32 unresettable_controller[] = {
424 0x324a103C, /* Smart Array P712m */
425 0x324b103C, /* SmartArray P711m */
426 0x3223103C, /* Smart Array P800 */
427 0x3234103C, /* Smart Array P400 */
428 0x3235103C, /* Smart Array P400i */
429 0x3211103C, /* Smart Array E200i */
430 0x3212103C, /* Smart Array E200 */
431 0x3213103C, /* Smart Array E200i */
432 0x3214103C, /* Smart Array E200i */
433 0x3215103C, /* Smart Array E200i */
434 0x3237103C, /* Smart Array E500 */
435 0x323D103C, /* Smart Array P700m */
7af0abbc 436 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 437 0x409C0E11, /* Smart Array 6400 */
438 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 439 0x40700E11, /* Smart Array 5300 */
440 0x40820E11, /* Smart Array 532 */
441 0x40830E11, /* Smart Array 5312 */
442 0x409A0E11, /* Smart Array 641 */
443 0x409B0E11, /* Smart Array 642 */
444 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 445};
446
46380786
SC		 447/* List of controllers which cannot even be soft reset */
448static u32 soft_unresettable_controller[] = {
7af0abbc 449 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 450 0x40700E11, /* Smart Array 5300 */
451 0x40820E11, /* Smart Array 532 */
452 0x40830E11, /* Smart Array 5312 */
453 0x409A0E11, /* Smart Array 641 */
454 0x409B0E11, /* Smart Array 642 */
455 0x40910E11, /* Smart Array 6i */
46380786
SC		 456 /* Exclude 640x boards. These are two pci devices in one slot
457 * which share a battery backed cache module. One controls the
458 * cache, the other accesses the cache through the one that controls
459 * it. If we reset the one controlling the cache, the other will
460 * likely not be happy. Just forbid resetting this conjoined mess.
461 * The 640x isn't really supported by hpsa anyway.
462 */
463 0x409C0E11, /* Smart Array 6400 */
464 0x409D0E11, /* Smart Array 6400 EM */
465};
466
467static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 468{
469 int i;
470
471 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 472 if (unresettable_controller[i] == board_id)
473 return 0;
474 return 1;
475}
476
477static int ctlr_is_soft_resettable(u32 board_id)
478{
479 int i;
480
481 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
482 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 483 return 0;
484 return 1;
485}
486
46380786
SC		 487static int ctlr_is_resettable(u32 board_id)
488{
489 return ctlr_is_hard_resettable(board_id) ||
490 ctlr_is_soft_resettable(board_id);
491}
492
941b1cda
SC		 493static ssize_t host_show_resettable(struct device *dev,
494 struct device_attribute *attr, char *buf)
495{
496 struct ctlr_info *h;
497 struct Scsi_Host *shost = class_to_shost(dev);
498
499 h = shost_to_hba(shost);
46380786 500 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 501}
502
edd16368
SC		 503static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
504{
505 return (scsi3addr[3] & 0xC0) == 0x40;
506}
507
f2ef0ce7
RE		 508static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
509 "1(+0)ADM", "UNKNOWN"
edd16368 510};
6b80b18f
ST		 511#define HPSA_RAID_0 0
512#define HPSA_RAID_4 1
513#define HPSA_RAID_1 2 /* also used for RAID 10 */
514#define HPSA_RAID_5 3 /* also used for RAID 50 */
515#define HPSA_RAID_51 4
516#define HPSA_RAID_6 5 /* also used for RAID 60 */
517#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 518#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
519
520static ssize_t raid_level_show(struct device *dev,
521 struct device_attribute *attr, char *buf)
522{
523 ssize_t l = 0;
82a72c0a 524 unsigned char rlevel;
edd16368
SC		 525 struct ctlr_info *h;
526 struct scsi_device *sdev;
527 struct hpsa_scsi_dev_t *hdev;
528 unsigned long flags;
529
530 sdev = to_scsi_device(dev);
531 h = sdev_to_hba(sdev);
532 spin_lock_irqsave(&h->lock, flags);
533 hdev = sdev->hostdata;
534 if (!hdev) {
535 spin_unlock_irqrestore(&h->lock, flags);
536 return -ENODEV;
537 }
538
539 /* Is this even a logical drive? */
540 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
541 spin_unlock_irqrestore(&h->lock, flags);
542 l = snprintf(buf, PAGE_SIZE, "N/A\n");
543 return l;
544 }
545
546 rlevel = hdev->raid_level;
547 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 548 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 549 rlevel = RAID_UNKNOWN;
550 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
551 return l;
552}
553
554static ssize_t lunid_show(struct device *dev,
555 struct device_attribute *attr, char *buf)
556{
557 struct ctlr_info *h;
558 struct scsi_device *sdev;
559 struct hpsa_scsi_dev_t *hdev;
560 unsigned long flags;
561 unsigned char lunid[8];
562
563 sdev = to_scsi_device(dev);
564 h = sdev_to_hba(sdev);
565 spin_lock_irqsave(&h->lock, flags);
566 hdev = sdev->hostdata;
567 if (!hdev) {
568 spin_unlock_irqrestore(&h->lock, flags);
569 return -ENODEV;
570 }
571 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
572 spin_unlock_irqrestore(&h->lock, flags);
573 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
574 lunid[0], lunid[1], lunid[2], lunid[3],
575 lunid[4], lunid[5], lunid[6], lunid[7]);
576}
577
578static ssize_t unique_id_show(struct device *dev,
579 struct device_attribute *attr, char *buf)
580{
581 struct ctlr_info *h;
582 struct scsi_device *sdev;
583 struct hpsa_scsi_dev_t *hdev;
584 unsigned long flags;
585 unsigned char sn[16];
586
587 sdev = to_scsi_device(dev);
588 h = sdev_to_hba(sdev);
589 spin_lock_irqsave(&h->lock, flags);
590 hdev = sdev->hostdata;
591 if (!hdev) {
592 spin_unlock_irqrestore(&h->lock, flags);
593 return -ENODEV;
594 }
595 memcpy(sn, hdev->device_id, sizeof(sn));
596 spin_unlock_irqrestore(&h->lock, flags);
597 return snprintf(buf, 16 * 2 + 2,
598 "%02X%02X%02X%02X%02X%02X%02X%02X"
599 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
600 sn[0], sn[1], sn[2], sn[3],
601 sn[4], sn[5], sn[6], sn[7],
602 sn[8], sn[9], sn[10], sn[11],
603 sn[12], sn[13], sn[14], sn[15]);
604}
605
c1988684
ST		 606static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
607 struct device_attribute *attr, char *buf)
608{
609 struct ctlr_info *h;
610 struct scsi_device *sdev;
611 struct hpsa_scsi_dev_t *hdev;
612 unsigned long flags;
613 int offload_enabled;
614
615 sdev = to_scsi_device(dev);
616 h = sdev_to_hba(sdev);
617 spin_lock_irqsave(&h->lock, flags);
618 hdev = sdev->hostdata;
619 if (!hdev) {
620 spin_unlock_irqrestore(&h->lock, flags);
621 return -ENODEV;
622 }
623 offload_enabled = hdev->offload_enabled;
624 spin_unlock_irqrestore(&h->lock, flags);
625 return snprintf(buf, 20, "%d\n", offload_enabled);
626}
627
3f5eac3a
SC		 628static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
629static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
630static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
631static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 632static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
633 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 634static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
635 host_show_hp_ssd_smart_path_status,
636 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 637static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
638 host_store_raid_offload_debug);
3f5eac3a
SC		 639static DEVICE_ATTR(firmware_revision, S_IRUGO,
640 host_show_firmware_revision, NULL);
641static DEVICE_ATTR(commands_outstanding, S_IRUGO,
642 host_show_commands_outstanding, NULL);
643static DEVICE_ATTR(transport_mode, S_IRUGO,
644 host_show_transport_mode, NULL);
941b1cda
SC		 645static DEVICE_ATTR(resettable, S_IRUGO,
646 host_show_resettable, NULL);
3f5eac3a
SC		 647
648static struct device_attribute *hpsa_sdev_attrs[] = {
649 &dev_attr_raid_level,
650 &dev_attr_lunid,
651 &dev_attr_unique_id,
c1988684 652 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 653 NULL,
654};
655
656static struct device_attribute *hpsa_shost_attrs[] = {
657 &dev_attr_rescan,
658 &dev_attr_firmware_revision,
659 &dev_attr_commands_outstanding,
660 &dev_attr_transport_mode,
941b1cda 661 &dev_attr_resettable,
da0697bd 662 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 663 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 664 NULL,
665};
666
667static struct scsi_host_template hpsa_driver_template = {
668 .module = THIS_MODULE,
f79cfec6
SC		 669 .name = HPSA,
670 .proc_name = HPSA,
3f5eac3a
SC		 671 .queuecommand = hpsa_scsi_queue_command,
672 .scan_start = hpsa_scan_start,
673 .scan_finished = hpsa_scan_finished,
7c0a0229 674 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 675 .this_id = -1,
676 .use_clustering = ENABLE_CLUSTERING,
75167d2c 677 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 678 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
679 .ioctl = hpsa_ioctl,
680 .slave_alloc = hpsa_slave_alloc,
681 .slave_destroy = hpsa_slave_destroy,
682#ifdef CONFIG_COMPAT
683 .compat_ioctl = hpsa_compat_ioctl,
684#endif
685 .sdev_attrs = hpsa_sdev_attrs,
686 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 687 .max_sectors = 8192,
54b2b50c 688 .no_write_same = 1,
3f5eac3a
SC		 689};
690
254f796b 691static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 692{
693 u32 a;
072b0518 694 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 695
e1f7de0c
MG		 696 if (h->transMethod & CFGTBL_Trans_io_accel1)
697 return h->access.command_completed(h, q);
698
3f5eac3a 699 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 700 return h->access.command_completed(h, q);
3f5eac3a 701
254f796b
MG		 702 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
703 a = rq->head[rq->current_entry];
704 rq->current_entry++;
0cbf768e 705 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 706 } else {
707 a = FIFO_EMPTY;
708 }
709 /* Check for wraparound */
254f796b
MG		 710 if (rq->current_entry == h->max_commands) {
711 rq->current_entry = 0;
712 rq->wraparound ^= 1;
3f5eac3a
SC		 713 }
714 return a;
715}
716
c349775e
ST		 717/*
718 * There are some special bits in the bus address of the
719 * command that we have to set for the controller to know
720 * how to process the command:
721 *
722 * Normal performant mode:
723 * bit 0: 1 means performant mode, 0 means simple mode.
724 * bits 1-3 = block fetch table entry
725 * bits 4-6 = command type (== 0)
726 *
727 * ioaccel1 mode:
728 * bit 0 = "performant mode" bit.
729 * bits 1-3 = block fetch table entry
730 * bits 4-6 = command type (== 110)
731 * (command type is needed because ioaccel1 mode
732 * commands are submitted through the same register as normal
733 * mode commands, so this is how the controller knows whether
734 * the command is normal mode or ioaccel1 mode.)
735 *
736 * ioaccel2 mode:
737 * bit 0 = "performant mode" bit.
738 * bits 1-4 = block fetch table entry (note extra bit)
739 * bits 4-6 = not needed, because ioaccel2 mode has
740 * a separate special register for submitting commands.
741 */
742
3f5eac3a
SC		 743/* set_performant_mode: Modify the tag for cciss performant
744 * set bit 0 for pull model, bits 3-1 for block fetch
745 * register number
746 */
747static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
748{
254f796b 749 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 750 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 751 if (likely(h->msix_vector > 0))
254f796b 752 c->Header.ReplyQueue =
804a5cb5 753 raw_smp_processor_id() % h->nreply_queues;
254f796b 754 }
3f5eac3a
SC		 755}
756
c349775e
ST		 757static void set_ioaccel1_performant_mode(struct ctlr_info *h,
758 struct CommandList *c)
759{
760 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
761
762 /* Tell the controller to post the reply to the queue for this
763 * processor. This seems to give the best I/O throughput.
764 */
765 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
766 /* Set the bits in the address sent down to include:
767 * - performant mode bit (bit 0)
768 * - pull count (bits 1-3)
769 * - command type (bits 4-6)
770 */
771 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
772 IOACCEL1_BUSADDR_CMDTYPE;
773}
774
775static void set_ioaccel2_performant_mode(struct ctlr_info *h,
776 struct CommandList *c)
777{
778 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
779
780 /* Tell the controller to post the reply to the queue for this
781 * processor. This seems to give the best I/O throughput.
782 */
783 cp->reply_queue = smp_processor_id() % h->nreply_queues;
784 /* Set the bits in the address sent down to include:
785 * - performant mode bit not used in ioaccel mode 2
786 * - pull count (bits 0-3)
787 * - command type isn't needed for ioaccel2
788 */
789 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
790}
791
e85c5974
SC		 792static int is_firmware_flash_cmd(u8 *cdb)
793{
794 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
795}
796
797/*
798 * During firmware flash, the heartbeat register may not update as frequently
799 * as it should. So we dial down lockup detection during firmware flash. and
800 * dial it back up when firmware flash completes.
801 */
802#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
803#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
804static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
805 struct CommandList *c)
806{
807 if (!is_firmware_flash_cmd(c->Request.CDB))
808 return;
809 atomic_inc(&h->firmware_flash_in_progress);
810 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
811}
812
813static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
814 struct CommandList *c)
815{
816 if (is_firmware_flash_cmd(c->Request.CDB) &&
817 atomic_dec_and_test(&h->firmware_flash_in_progress))
818 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
819}
820
3f5eac3a
SC		 821static void enqueue_cmd_and_start_io(struct ctlr_info *h,
822 struct CommandList *c)
823{
c349775e
ST		 824 switch (c->cmd_type) {
825 case CMD_IOACCEL1:
826 set_ioaccel1_performant_mode(h, c);
827 break;
828 case CMD_IOACCEL2:
829 set_ioaccel2_performant_mode(h, c);
830 break;
831 default:
832 set_performant_mode(h, c);
833 }
e85c5974 834 dial_down_lockup_detection_during_fw_flash(h, c);
f2405db8
DB		 835 atomic_inc(&h->commands_outstanding);
836 h->access.submit_command(h, c);
3f5eac3a
SC		 837}
838
839static inline int is_hba_lunid(unsigned char scsi3addr[])
840{
841 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
842}
843
844static inline int is_scsi_rev_5(struct ctlr_info *h)
845{
846 if (!h->hba_inquiry_data)
847 return 0;
848 if ((h->hba_inquiry_data[2] & 0x07) == 5)
849 return 1;
850 return 0;
851}
852
edd16368
SC		 853static int hpsa_find_target_lun(struct ctlr_info *h,
854 unsigned char scsi3addr[], int bus, int *target, int *lun)
855{
856 /* finds an unused bus, target, lun for a new physical device
857 * assumes h->devlock is held
858 */
859 int i, found = 0;
cfe5badc 860 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 861
263d9401 862 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 863
864 for (i = 0; i < h->ndevices; i++) {
865 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 866 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 867 }
868
263d9401
AM		 869 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
870 if (i < HPSA_MAX_DEVICES) {
871 /* *bus = 1; */
872 *target = i;
873 *lun = 0;
874 found = 1;
edd16368
SC		 875 }
876 return !found;
877}
878
879/* Add an entry into h->dev[] array. */
880static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
881 struct hpsa_scsi_dev_t *device,
882 struct hpsa_scsi_dev_t *added[], int *nadded)
883{
884 /* assumes h->devlock is held */
885 int n = h->ndevices;
886 int i;
887 unsigned char addr1[8], addr2[8];
888 struct hpsa_scsi_dev_t *sd;
889
cfe5badc 890 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 891 dev_err(&h->pdev->dev, "too many devices, some will be "
892 "inaccessible.\n");
893 return -1;
894 }
895
896 /* physical devices do not have lun or target assigned until now. */
897 if (device->lun != -1)
898 /* Logical device, lun is already assigned. */
899 goto lun_assigned;
900
901 /* If this device a non-zero lun of a multi-lun device
902 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 903 * unit no, zero otherwise.
edd16368
SC		 904 */
905 if (device->scsi3addr[4] == 0) {
906 /* This is not a non-zero lun of a multi-lun device */
907 if (hpsa_find_target_lun(h, device->scsi3addr,
908 device->bus, &device->target, &device->lun) != 0)
909 return -1;
910 goto lun_assigned;
911 }
912
913 /* This is a non-zero lun of a multi-lun device.
914 * Search through our list and find the device which
915 * has the same 8 byte LUN address, excepting byte 4.
916 * Assign the same bus and target for this new LUN.
917 * Use the logical unit number from the firmware.
918 */
919 memcpy(addr1, device->scsi3addr, 8);
920 addr1[4] = 0;
921 for (i = 0; i < n; i++) {
922 sd = h->dev[i];
923 memcpy(addr2, sd->scsi3addr, 8);
924 addr2[4] = 0;
925 /* differ only in byte 4? */
926 if (memcmp(addr1, addr2, 8) == 0) {
927 device->bus = sd->bus;
928 device->target = sd->target;
929 device->lun = device->scsi3addr[4];
930 break;
931 }
932 }
933 if (device->lun == -1) {
934 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
935 " suspect firmware bug or unsupported hardware "
936 "configuration.\n");
937 return -1;
938 }
939
940lun_assigned:
941
942 h->dev[n] = device;
943 h->ndevices++;
944 added[*nadded] = device;
945 (*nadded)++;
946
947 /* initially, (before registering with scsi layer) we don't
948 * know our hostno and we don't want to print anything first
949 * time anyway (the scsi layer's inquiries will show that info)
950 */
951 /* if (hostno != -1) */
952 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
953 scsi_device_type(device->devtype), hostno,
954 device->bus, device->target, device->lun);
955 return 0;
956}
957
bd9244f7
ST		 958/* Update an entry in h->dev[] array. */
959static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
960 int entry, struct hpsa_scsi_dev_t *new_entry)
961{
962 /* assumes h->devlock is held */
963 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
964
965 /* Raid level changed. */
966 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 967
03383736
DB		 968 /* Raid offload parameters changed. Careful about the ordering. */
969 if (new_entry->offload_config && new_entry->offload_enabled) {
970 /*
971 * if drive is newly offload_enabled, we want to copy the
972 * raid map data first. If previously offload_enabled and
973 * offload_config were set, raid map data had better be
974 * the same as it was before. if raid map data is changed
975 * then it had better be the case that
976 * h->dev[entry]->offload_enabled is currently 0.
977 */
978 h->dev[entry]->raid_map = new_entry->raid_map;
979 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
980 wmb(); /* ensure raid map updated prior to ->offload_enabled */
981 }
250fb125 982 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 983 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736
DB		 984 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
985 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 986
bd9244f7
ST		 987 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
988 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
989 new_entry->target, new_entry->lun);
990}
991
2a8ccf31
SC		 992/* Replace an entry from h->dev[] array. */
993static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
994 int entry, struct hpsa_scsi_dev_t *new_entry,
995 struct hpsa_scsi_dev_t *added[], int *nadded,
996 struct hpsa_scsi_dev_t *removed[], int *nremoved)
997{
998 /* assumes h->devlock is held */
cfe5badc 999 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1000 removed[*nremoved] = h->dev[entry];
1001 (*nremoved)++;
01350d05
SC		 1002
1003 /*
1004 * New physical devices won't have target/lun assigned yet
1005 * so we need to preserve the values in the slot we are replacing.
1006 */
1007 if (new_entry->target == -1) {
1008 new_entry->target = h->dev[entry]->target;
1009 new_entry->lun = h->dev[entry]->lun;
1010 }
1011
2a8ccf31
SC		 1012 h->dev[entry] = new_entry;
1013 added[*nadded] = new_entry;
1014 (*nadded)++;
1015 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1016 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1017 new_entry->target, new_entry->lun);
1018}
1019
edd16368
SC		 1020/* Remove an entry from h->dev[] array. */
1021static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1022 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1023{
1024 /* assumes h->devlock is held */
1025 int i;
1026 struct hpsa_scsi_dev_t *sd;
1027
cfe5badc 1028 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1029
1030 sd = h->dev[entry];
1031 removed[*nremoved] = h->dev[entry];
1032 (*nremoved)++;
1033
1034 for (i = entry; i < h->ndevices-1; i++)
1035 h->dev[i] = h->dev[i+1];
1036 h->ndevices--;
1037 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1038 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1039 sd->lun);
1040}
1041
1042#define SCSI3ADDR_EQ(a, b) ( \
1043 (a)[7] == (b)[7] && \
1044 (a)[6] == (b)[6] && \
1045 (a)[5] == (b)[5] && \
1046 (a)[4] == (b)[4] && \
1047 (a)[3] == (b)[3] && \
1048 (a)[2] == (b)[2] && \
1049 (a)[1] == (b)[1] && \
1050 (a)[0] == (b)[0])
1051
1052static void fixup_botched_add(struct ctlr_info *h,
1053 struct hpsa_scsi_dev_t *added)
1054{
1055 /* called when scsi_add_device fails in order to re-adjust
1056 * h->dev[] to match the mid layer's view.
1057 */
1058 unsigned long flags;
1059 int i, j;
1060
1061 spin_lock_irqsave(&h->lock, flags);
1062 for (i = 0; i < h->ndevices; i++) {
1063 if (h->dev[i] == added) {
1064 for (j = i; j < h->ndevices-1; j++)
1065 h->dev[j] = h->dev[j+1];
1066 h->ndevices--;
1067 break;
1068 }
1069 }
1070 spin_unlock_irqrestore(&h->lock, flags);
1071 kfree(added);
1072}
1073
1074static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1075 struct hpsa_scsi_dev_t *dev2)
1076{
edd16368
SC		 1077 /* we compare everything except lun and target as these
1078 * are not yet assigned. Compare parts likely
1079 * to differ first
1080 */
1081 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1082 sizeof(dev1->scsi3addr)) != 0)
1083 return 0;
1084 if (memcmp(dev1->device_id, dev2->device_id,
1085 sizeof(dev1->device_id)) != 0)
1086 return 0;
1087 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1088 return 0;
1089 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1090 return 0;
edd16368
SC		 1091 if (dev1->devtype != dev2->devtype)
1092 return 0;
edd16368
SC		 1093 if (dev1->bus != dev2->bus)
1094 return 0;
1095 return 1;
1096}
1097
bd9244f7
ST		 1098static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1099 struct hpsa_scsi_dev_t *dev2)
1100{
1101 /* Device attributes that can change, but don't mean
1102 * that the device is a different device, nor that the OS
1103 * needs to be told anything about the change.
1104 */
1105 if (dev1->raid_level != dev2->raid_level)
1106 return 1;
250fb125
SC		 1107 if (dev1->offload_config != dev2->offload_config)
1108 return 1;
1109 if (dev1->offload_enabled != dev2->offload_enabled)
1110 return 1;
03383736
DB		 1111 if (dev1->queue_depth != dev2->queue_depth)
1112 return 1;
bd9244f7
ST		 1113 return 0;
1114}
1115
edd16368
SC		 1116/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1117 * and return needle location in *index. If scsi3addr matches, but not
1118 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1119 * location in *index.
1120 * In the case of a minor device attribute change, such as RAID level, just
1121 * return DEVICE_UPDATED, along with the updated device's location in index.
1122 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1123 */
1124static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1125 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1126 int *index)
1127{
1128 int i;
1129#define DEVICE_NOT_FOUND 0
1130#define DEVICE_CHANGED 1
1131#define DEVICE_SAME 2
bd9244f7 1132#define DEVICE_UPDATED 3
edd16368 1133 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1134 if (haystack[i] == NULL) /* previously removed. */
1135 continue;
edd16368
SC		 1136 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1137 *index = i;
bd9244f7
ST		 1138 if (device_is_the_same(needle, haystack[i])) {
1139 if (device_updated(needle, haystack[i]))
1140 return DEVICE_UPDATED;
edd16368 1141 return DEVICE_SAME;
bd9244f7 1142 } else {
9846590e
SC		 1143 /* Keep offline devices offline */
1144 if (needle->volume_offline)
1145 return DEVICE_NOT_FOUND;
edd16368 1146 return DEVICE_CHANGED;
bd9244f7 1147 }
edd16368
SC		 1148 }
1149 }
1150 *index = -1;
1151 return DEVICE_NOT_FOUND;
1152}
1153
9846590e
SC		 1154static void hpsa_monitor_offline_device(struct ctlr_info *h,
1155 unsigned char scsi3addr[])
1156{
1157 struct offline_device_entry *device;
1158 unsigned long flags;
1159
1160 /* Check to see if device is already on the list */
1161 spin_lock_irqsave(&h->offline_device_lock, flags);
1162 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1163 if (memcmp(device->scsi3addr, scsi3addr,
1164 sizeof(device->scsi3addr)) == 0) {
1165 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1166 return;
1167 }
1168 }
1169 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1170
1171 /* Device is not on the list, add it. */
1172 device = kmalloc(sizeof(*device), GFP_KERNEL);
1173 if (!device) {
1174 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1175 return;
1176 }
1177 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1178 spin_lock_irqsave(&h->offline_device_lock, flags);
1179 list_add_tail(&device->offline_list, &h->offline_device_list);
1180 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1181}
1182
1183/* Print a message explaining various offline volume states */
1184static void hpsa_show_volume_status(struct ctlr_info *h,
1185 struct hpsa_scsi_dev_t *sd)
1186{
1187 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1188 dev_info(&h->pdev->dev,
1189 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1190 h->scsi_host->host_no,
1191 sd->bus, sd->target, sd->lun);
1192 switch (sd->volume_offline) {
1193 case HPSA_LV_OK:
1194 break;
1195 case HPSA_LV_UNDERGOING_ERASE:
1196 dev_info(&h->pdev->dev,
1197 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1198 h->scsi_host->host_no,
1199 sd->bus, sd->target, sd->lun);
1200 break;
1201 case HPSA_LV_UNDERGOING_RPI:
1202 dev_info(&h->pdev->dev,
1203 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1204 h->scsi_host->host_no,
1205 sd->bus, sd->target, sd->lun);
1206 break;
1207 case HPSA_LV_PENDING_RPI:
1208 dev_info(&h->pdev->dev,
1209 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1210 h->scsi_host->host_no,
1211 sd->bus, sd->target, sd->lun);
1212 break;
1213 case HPSA_LV_ENCRYPTED_NO_KEY:
1214 dev_info(&h->pdev->dev,
1215 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1216 h->scsi_host->host_no,
1217 sd->bus, sd->target, sd->lun);
1218 break;
1219 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1220 dev_info(&h->pdev->dev,
1221 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1222 h->scsi_host->host_no,
1223 sd->bus, sd->target, sd->lun);
1224 break;
1225 case HPSA_LV_UNDERGOING_ENCRYPTION:
1226 dev_info(&h->pdev->dev,
1227 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1228 h->scsi_host->host_no,
1229 sd->bus, sd->target, sd->lun);
1230 break;
1231 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1232 dev_info(&h->pdev->dev,
1233 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1234 h->scsi_host->host_no,
1235 sd->bus, sd->target, sd->lun);
1236 break;
1237 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1238 dev_info(&h->pdev->dev,
1239 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1240 h->scsi_host->host_no,
1241 sd->bus, sd->target, sd->lun);
1242 break;
1243 case HPSA_LV_PENDING_ENCRYPTION:
1244 dev_info(&h->pdev->dev,
1245 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1246 h->scsi_host->host_no,
1247 sd->bus, sd->target, sd->lun);
1248 break;
1249 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1250 dev_info(&h->pdev->dev,
1251 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1252 h->scsi_host->host_no,
1253 sd->bus, sd->target, sd->lun);
1254 break;
1255 }
1256}
1257
03383736
DB		 1258/*
1259 * Figure the list of physical drive pointers for a logical drive with
1260 * raid offload configured.
1261 */
1262static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1263 struct hpsa_scsi_dev_t *dev[], int ndevices,
1264 struct hpsa_scsi_dev_t *logical_drive)
1265{
1266 struct raid_map_data *map = &logical_drive->raid_map;
1267 struct raid_map_disk_data *dd = &map->data[0];
1268 int i, j;
1269 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1270 le16_to_cpu(map->metadata_disks_per_row);
1271 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1272 le16_to_cpu(map->layout_map_count) *
1273 total_disks_per_row;
1274 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1275 total_disks_per_row;
1276 int qdepth;
1277
1278 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1279 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1280
1281 qdepth = 0;
1282 for (i = 0; i < nraid_map_entries; i++) {
1283 logical_drive->phys_disk[i] = NULL;
1284 if (!logical_drive->offload_config)
1285 continue;
1286 for (j = 0; j < ndevices; j++) {
1287 if (dev[j]->devtype != TYPE_DISK)
1288 continue;
1289 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1290 continue;
1291 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1292 continue;
1293
1294 logical_drive->phys_disk[i] = dev[j];
1295 if (i < nphys_disk)
1296 qdepth = min(h->nr_cmds, qdepth +
1297 logical_drive->phys_disk[i]->queue_depth);
1298 break;
1299 }
1300
1301 /*
1302 * This can happen if a physical drive is removed and
1303 * the logical drive is degraded. In that case, the RAID
1304 * map data will refer to a physical disk which isn't actually
1305 * present. And in that case offload_enabled should already
1306 * be 0, but we'll turn it off here just in case
1307 */
1308 if (!logical_drive->phys_disk[i]) {
1309 logical_drive->offload_enabled = 0;
1310 logical_drive->queue_depth = h->nr_cmds;
1311 }
1312 }
1313 if (nraid_map_entries)
1314 /*
1315 * This is correct for reads, too high for full stripe writes,
1316 * way too high for partial stripe writes
1317 */
1318 logical_drive->queue_depth = qdepth;
1319 else
1320 logical_drive->queue_depth = h->nr_cmds;
1321}
1322
1323static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1324 struct hpsa_scsi_dev_t *dev[], int ndevices)
1325{
1326 int i;
1327
1328 for (i = 0; i < ndevices; i++) {
1329 if (dev[i]->devtype != TYPE_DISK)
1330 continue;
1331 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1332 continue;
1333 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1334 }
1335}
1336
4967bd3e 1337static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1338 struct hpsa_scsi_dev_t *sd[], int nsds)
1339{
1340 /* sd contains scsi3 addresses and devtypes, and inquiry
1341 * data. This function takes what's in sd to be the current
1342 * reality and updates h->dev[] to reflect that reality.
1343 */
1344 int i, entry, device_change, changes = 0;
1345 struct hpsa_scsi_dev_t *csd;
1346 unsigned long flags;
1347 struct hpsa_scsi_dev_t **added, **removed;
1348 int nadded, nremoved;
1349 struct Scsi_Host *sh = NULL;
1350
cfe5badc
ST		 1351 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1352 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1353
1354 if (!added || !removed) {
1355 dev_warn(&h->pdev->dev, "out of memory in "
1356 "adjust_hpsa_scsi_table\n");
1357 goto free_and_out;
1358 }
1359
1360 spin_lock_irqsave(&h->devlock, flags);
1361
1362 /* find any devices in h->dev[] that are not in
1363 * sd[] and remove them from h->dev[], and for any
1364 * devices which have changed, remove the old device
1365 * info and add the new device info.
bd9244f7
ST		 1366 * If minor device attributes change, just update
1367 * the existing device structure.
edd16368
SC		 1368 */
1369 i = 0;
1370 nremoved = 0;
1371 nadded = 0;
1372 while (i < h->ndevices) {
1373 csd = h->dev[i];
1374 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1375 if (device_change == DEVICE_NOT_FOUND) {
1376 changes++;
1377 hpsa_scsi_remove_entry(h, hostno, i,
1378 removed, &nremoved);
1379 continue; /* remove ^^^, hence i not incremented */
1380 } else if (device_change == DEVICE_CHANGED) {
1381 changes++;
2a8ccf31
SC		 1382 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1383 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1384 /* Set it to NULL to prevent it from being freed
1385 * at the bottom of hpsa_update_scsi_devices()
1386 */
1387 sd[entry] = NULL;
bd9244f7
ST		 1388 } else if (device_change == DEVICE_UPDATED) {
1389 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1390 }
1391 i++;
1392 }
1393
1394 /* Now, make sure every device listed in sd[] is also
1395 * listed in h->dev[], adding them if they aren't found
1396 */
1397
1398 for (i = 0; i < nsds; i++) {
1399 if (!sd[i]) /* if already added above. */
1400 continue;
9846590e
SC		 1401
1402 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1403 * as the SCSI mid-layer does not handle such devices well.
1404 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1405 * at 160Hz, and prevents the system from coming up.
1406 */
1407 if (sd[i]->volume_offline) {
1408 hpsa_show_volume_status(h, sd[i]);
1409 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1410 h->scsi_host->host_no,
1411 sd[i]->bus, sd[i]->target, sd[i]->lun);
1412 continue;
1413 }
1414
edd16368
SC		 1415 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1416 h->ndevices, &entry);
1417 if (device_change == DEVICE_NOT_FOUND) {
1418 changes++;
1419 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1420 added, &nadded) != 0)
1421 break;
1422 sd[i] = NULL; /* prevent from being freed later. */
1423 } else if (device_change == DEVICE_CHANGED) {
1424 /* should never happen... */
1425 changes++;
1426 dev_warn(&h->pdev->dev,
1427 "device unexpectedly changed.\n");
1428 /* but if it does happen, we just ignore that device */
1429 }
1430 }
1431 spin_unlock_irqrestore(&h->devlock, flags);
1432
9846590e
SC		 1433 /* Monitor devices which are in one of several NOT READY states to be
1434 * brought online later. This must be done without holding h->devlock,
1435 * so don't touch h->dev[]
1436 */
1437 for (i = 0; i < nsds; i++) {
1438 if (!sd[i]) /* if already added above. */
1439 continue;
1440 if (sd[i]->volume_offline)
1441 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1442 }
1443
edd16368
SC		 1444 /* Don't notify scsi mid layer of any changes the first time through
1445 * (or if there are no changes) scsi_scan_host will do it later the
1446 * first time through.
1447 */
1448 if (hostno == -1 || !changes)
1449 goto free_and_out;
1450
1451 sh = h->scsi_host;
1452 /* Notify scsi mid layer of any removed devices */
1453 for (i = 0; i < nremoved; i++) {
1454 struct scsi_device *sdev =
1455 scsi_device_lookup(sh, removed[i]->bus,
1456 removed[i]->target, removed[i]->lun);
1457 if (sdev != NULL) {
1458 scsi_remove_device(sdev);
1459 scsi_device_put(sdev);
1460 } else {
1461 /* We don't expect to get here.
1462 * future cmds to this device will get selection
1463 * timeout as if the device was gone.
1464 */
1465 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1466 " for removal.", hostno, removed[i]->bus,
1467 removed[i]->target, removed[i]->lun);
1468 }
1469 kfree(removed[i]);
1470 removed[i] = NULL;
1471 }
1472
1473 /* Notify scsi mid layer of any added devices */
1474 for (i = 0; i < nadded; i++) {
1475 if (scsi_add_device(sh, added[i]->bus,
1476 added[i]->target, added[i]->lun) == 0)
1477 continue;
1478 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1479 "device not added.\n", hostno, added[i]->bus,
1480 added[i]->target, added[i]->lun);
1481 /* now we have to remove it from h->dev,
1482 * since it didn't get added to scsi mid layer
1483 */
1484 fixup_botched_add(h, added[i]);
1485 }
1486
1487free_and_out:
1488 kfree(added);
1489 kfree(removed);
edd16368
SC		 1490}
1491
1492/*
9e03aa2f 1493 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1494 * Assume's h->devlock is held.
1495 */
1496static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1497 int bus, int target, int lun)
1498{
1499 int i;
1500 struct hpsa_scsi_dev_t *sd;
1501
1502 for (i = 0; i < h->ndevices; i++) {
1503 sd = h->dev[i];
1504 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1505 return sd;
1506 }
1507 return NULL;
1508}
1509
1510/* link sdev->hostdata to our per-device structure. */
1511static int hpsa_slave_alloc(struct scsi_device *sdev)
1512{
1513 struct hpsa_scsi_dev_t *sd;
1514 unsigned long flags;
1515 struct ctlr_info *h;
1516
1517 h = sdev_to_hba(sdev);
1518 spin_lock_irqsave(&h->devlock, flags);
1519 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1520 sdev_id(sdev), sdev->lun);
03383736 1521 if (sd != NULL) {
edd16368 1522 sdev->hostdata = sd;
03383736
DB		 1523 if (sd->queue_depth)
1524 scsi_change_queue_depth(sdev, sd->queue_depth);
1525 atomic_set(&sd->ioaccel_cmds_out, 0);
1526 }
edd16368
SC		 1527 spin_unlock_irqrestore(&h->devlock, flags);
1528 return 0;
1529}
1530
1531static void hpsa_slave_destroy(struct scsi_device *sdev)
1532{
bcc44255 1533 /* nothing to do. */
edd16368
SC		 1534}
1535
33a2ffce
SC		 1536static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1537{
1538 int i;
1539
1540 if (!h->cmd_sg_list)
1541 return;
1542 for (i = 0; i < h->nr_cmds; i++) {
1543 kfree(h->cmd_sg_list[i]);
1544 h->cmd_sg_list[i] = NULL;
1545 }
1546 kfree(h->cmd_sg_list);
1547 h->cmd_sg_list = NULL;
1548}
1549
1550static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1551{
1552 int i;
1553
1554 if (h->chainsize <= 0)
1555 return 0;
1556
1557 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1558 GFP_KERNEL);
3d4e6af8
RE		 1559 if (!h->cmd_sg_list) {
1560 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1561 return -ENOMEM;
3d4e6af8 1562 }
33a2ffce
SC		 1563 for (i = 0; i < h->nr_cmds; i++) {
1564 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1565 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1566 if (!h->cmd_sg_list[i]) {
1567 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1568 goto clean;
3d4e6af8 1569 }
33a2ffce
SC		 1570 }
1571 return 0;
1572
1573clean:
1574 hpsa_free_sg_chain_blocks(h);
1575 return -ENOMEM;
1576}
1577
e2bea6df 1578static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1579 struct CommandList *c)
1580{
1581 struct SGDescriptor *chain_sg, *chain_block;
1582 u64 temp64;
50a0decf 1583 u32 chain_len;
33a2ffce
SC		 1584
1585 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1586 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1587 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1588 chain_len = sizeof(*chain_sg) *
2b08b3e9 1589 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1590 chain_sg->Len = cpu_to_le32(chain_len);
1591 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1592 PCI_DMA_TODEVICE);
e2bea6df
SC		 1593 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1594 /* prevent subsequent unmapping */
50a0decf 1595 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1596 return -1;
1597 }
50a0decf 1598 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1599 return 0;
33a2ffce
SC		 1600}
1601
1602static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1603 struct CommandList *c)
1604{
1605 struct SGDescriptor *chain_sg;
33a2ffce 1606
50a0decf 1607 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1608 return;
1609
1610 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1611 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1612 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1613}
1614
a09c1441
ST		 1615
1616/* Decode the various types of errors on ioaccel2 path.
1617 * Return 1 for any error that should generate a RAID path retry.
1618 * Return 0 for errors that don't require a RAID path retry.
1619 */
1620static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1621 struct CommandList *c,
1622 struct scsi_cmnd *cmd,
1623 struct io_accel2_cmd *c2)
1624{
1625 int data_len;
a09c1441 1626 int retry = 0;
c349775e
ST		 1627
1628 switch (c2->error_data.serv_response) {
1629 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1630 switch (c2->error_data.status) {
1631 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1632 break;
1633 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1634 dev_warn(&h->pdev->dev,
1635 "%s: task complete with check condition.\n",
1636 "HP SSD Smart Path");
ee6b1889 1637 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1638 if (c2->error_data.data_present !=
ee6b1889
SC		 1639 IOACCEL2_SENSE_DATA_PRESENT) {
1640 memset(cmd->sense_buffer, 0,
1641 SCSI_SENSE_BUFFERSIZE);
c349775e 1642 break;
ee6b1889 1643 }
c349775e
ST		 1644 /* copy the sense data */
1645 data_len = c2->error_data.sense_data_len;
1646 if (data_len > SCSI_SENSE_BUFFERSIZE)
1647 data_len = SCSI_SENSE_BUFFERSIZE;
1648 if (data_len > sizeof(c2->error_data.sense_data_buff))
1649 data_len =
1650 sizeof(c2->error_data.sense_data_buff);
1651 memcpy(cmd->sense_buffer,
1652 c2->error_data.sense_data_buff, data_len);
a09c1441 1653 retry = 1;
c349775e
ST		 1654 break;
1655 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1656 dev_warn(&h->pdev->dev,
1657 "%s: task complete with BUSY status.\n",
1658 "HP SSD Smart Path");
a09c1441 1659 retry = 1;
c349775e
ST		 1660 break;
1661 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1662 dev_warn(&h->pdev->dev,
1663 "%s: task complete with reservation conflict.\n",
1664 "HP SSD Smart Path");
a09c1441 1665 retry = 1;
c349775e
ST		 1666 break;
1667 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1668 /* Make scsi midlayer do unlimited retries */
1669 cmd->result = DID_IMM_RETRY << 16;
1670 break;
1671 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1672 dev_warn(&h->pdev->dev,
1673 "%s: task complete with aborted status.\n",
1674 "HP SSD Smart Path");
a09c1441 1675 retry = 1;
c349775e
ST		 1676 break;
1677 default:
1678 dev_warn(&h->pdev->dev,
1679 "%s: task complete with unrecognized status: 0x%02x\n",
1680 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1681 retry = 1;
c349775e
ST		 1682 break;
1683 }
1684 break;
1685 case IOACCEL2_SERV_RESPONSE_FAILURE:
1686 /* don't expect to get here. */
1687 dev_warn(&h->pdev->dev,
1688 "unexpected delivery or target failure, status = 0x%02x\n",
1689 c2->error_data.status);
a09c1441 1690 retry = 1;
c349775e
ST		 1691 break;
1692 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1693 break;
1694 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1695 break;
1696 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1697 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1698 retry = 1;
c349775e
ST		 1699 break;
1700 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1701 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1702 break;
1703 default:
1704 dev_warn(&h->pdev->dev,
1705 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1706 "HP SSD Smart Path",
1707 c2->error_data.serv_response);
1708 retry = 1;
c349775e
ST		 1709 break;
1710 }
a09c1441
ST		 1711
1712 return retry; /* retry on raid path? */
c349775e
ST		 1713}
1714
1715static void process_ioaccel2_completion(struct ctlr_info *h,
1716 struct CommandList *c, struct scsi_cmnd *cmd,
1717 struct hpsa_scsi_dev_t *dev)
1718{
1719 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1720
1721 /* check for good status */
1722 if (likely(c2->error_data.serv_response == 0 &&
1723 c2->error_data.status == 0)) {
1724 cmd_free(h, c);
1725 cmd->scsi_done(cmd);
1726 return;
1727 }
1728
1729 /* Any RAID offload error results in retry which will use
1730 * the normal I/O path so the controller can handle whatever's
1731 * wrong.
1732 */
1733 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1734 c2->error_data.serv_response ==
1735 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1736 if (c2->error_data.status ==
1737 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1738 dev->offload_enabled = 0;
1739 goto retry_cmd;
a09c1441 1740 }
080ef1cc
DB		 1741
1742 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1743 goto retry_cmd;
1744
c349775e
ST		 1745 cmd_free(h, c);
1746 cmd->scsi_done(cmd);
080ef1cc
DB		 1747 return;
1748
1749retry_cmd:
1750 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1751 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1752}
1753
1fb011fb 1754static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1755{
1756 struct scsi_cmnd *cmd;
1757 struct ctlr_info *h;
1758 struct ErrorInfo *ei;
283b4a9b 1759 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1760
1761 unsigned char sense_key;
1762 unsigned char asc; /* additional sense code */
1763 unsigned char ascq; /* additional sense code qualifier */
db111e18 1764 unsigned long sense_data_size;
edd16368
SC		 1765
1766 ei = cp->err_info;
1767 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1768 h = cp->h;
283b4a9b 1769 dev = cmd->device->hostdata;
edd16368
SC		 1770
1771 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 1772 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 1773 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 1774 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1775
1776 cmd->result = (DID_OK << 16); /* host byte */
1777 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 1778
03383736
DB		 1779 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
1780 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
1781
c349775e
ST		 1782 if (cp->cmd_type == CMD_IOACCEL2)
1783 return process_ioaccel2_completion(h, cp, cmd, dev);
1784
5512672f 1785 cmd->result |= ei->ScsiStatus;
edd16368 1786
6aa4c361
RE		 1787 scsi_set_resid(cmd, ei->ResidualCnt);
1788 if (ei->CommandStatus == 0) {
03383736
DB		 1789 if (cp->cmd_type == CMD_IOACCEL1)
1790 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 1791 cmd_free(h, cp);
1792 cmd->scsi_done(cmd);
1793 return;
1794 }
1795
1796 /* copy the sense data */
db111e18
SC		 1797 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1798 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1799 else
1800 sense_data_size = sizeof(ei->SenseInfo);
1801 if (ei->SenseLen < sense_data_size)
1802 sense_data_size = ei->SenseLen;
1803
1804 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1805
e1f7de0c
MG		 1806 /* For I/O accelerator commands, copy over some fields to the normal
1807 * CISS header used below for error handling.
1808 */
1809 if (cp->cmd_type == CMD_IOACCEL1) {
1810 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 1811 cp->Header.SGList = scsi_sg_count(cmd);
1812 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
1813 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
1814 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1815 cp->Header.tag = c->tag;
e1f7de0c
MG		 1816 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1817 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1818
1819 /* Any RAID offload error results in retry which will use
1820 * the normal I/O path so the controller can handle whatever's
1821 * wrong.
1822 */
1823 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1824 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1825 dev->offload_enabled = 0;
080ef1cc
DB		 1826 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
1827 queue_work_on(raw_smp_processor_id(),
1828 h->resubmit_wq, &cp->work);
283b4a9b
SC		 1829 return;
1830 }
e1f7de0c
MG		 1831 }
1832
edd16368
SC		 1833 /* an error has occurred */
1834 switch (ei->CommandStatus) {
1835
1836 case CMD_TARGET_STATUS:
1837 if (ei->ScsiStatus) {
1838 /* Get sense key */
1839 sense_key = 0xf & ei->SenseInfo[2];
1840 /* Get additional sense code */
1841 asc = ei->SenseInfo[12];
1842 /* Get addition sense code qualifier */
1843 ascq = ei->SenseInfo[13];
1844 }
edd16368 1845 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1846 if (sense_key == ABORTED_COMMAND) {
2e311fba 1847 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1848 break;
1849 }
edd16368
SC		 1850 break;
1851 }
edd16368
SC		 1852 /* Problem was not a check condition
1853 * Pass it up to the upper layers...
1854 */
1855 if (ei->ScsiStatus) {
1856 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1857 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1858 "Returning result: 0x%x\n",
1859 cp, ei->ScsiStatus,
1860 sense_key, asc, ascq,
1861 cmd->result);
1862 } else { /* scsi status is zero??? How??? */
1863 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1864 "Returning no connection.\n", cp),
1865
1866 /* Ordinarily, this case should never happen,
1867 * but there is a bug in some released firmware
1868 * revisions that allows it to happen if, for
1869 * example, a 4100 backplane loses power and
1870 * the tape drive is in it. We assume that
1871 * it's a fatal error of some kind because we
1872 * can't show that it wasn't. We will make it
1873 * look like selection timeout since that is
1874 * the most common reason for this to occur,
1875 * and it's severe enough.
1876 */
1877
1878 cmd->result = DID_NO_CONNECT << 16;
1879 }
1880 break;
1881
1882 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1883 break;
1884 case CMD_DATA_OVERRUN:
1885 dev_warn(&h->pdev->dev, "cp %p has"
1886 " completed with data overrun "
1887 "reported\n", cp);
1888 break;
1889 case CMD_INVALID: {
1890 /* print_bytes(cp, sizeof(*cp), 1, 0);
1891 print_cmd(cp); */
1892 /* We get CMD_INVALID if you address a non-existent device
1893 * instead of a selection timeout (no response). You will
1894 * see this if you yank out a drive, then try to access it.
1895 * This is kind of a shame because it means that any other
1896 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1897 * missing target. */
1898 cmd->result = DID_NO_CONNECT << 16;
1899 }
1900 break;
1901 case CMD_PROTOCOL_ERR:
256d0eaa 1902 cmd->result = DID_ERROR << 16;
edd16368 1903 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1904 "protocol error\n", cp);
edd16368
SC		 1905 break;
1906 case CMD_HARDWARE_ERR:
1907 cmd->result = DID_ERROR << 16;
1908 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1909 break;
1910 case CMD_CONNECTION_LOST:
1911 cmd->result = DID_ERROR << 16;
1912 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1913 break;
1914 case CMD_ABORTED:
1915 cmd->result = DID_ABORT << 16;
1916 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1917 cp, ei->ScsiStatus);
1918 break;
1919 case CMD_ABORT_FAILED:
1920 cmd->result = DID_ERROR << 16;
1921 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1922 break;
1923 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1924 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1925 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1926 "abort\n", cp);
1927 break;
1928 case CMD_TIMEOUT:
1929 cmd->result = DID_TIME_OUT << 16;
1930 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1931 break;
1d5e2ed0
SC		 1932 case CMD_UNABORTABLE:
1933 cmd->result = DID_ERROR << 16;
1934 dev_warn(&h->pdev->dev, "Command unabortable\n");
1935 break;
283b4a9b
SC		 1936 case CMD_IOACCEL_DISABLED:
1937 /* This only handles the direct pass-through case since RAID
1938 * offload is handled above. Just attempt a retry.
1939 */
1940 cmd->result = DID_SOFT_ERROR << 16;
1941 dev_warn(&h->pdev->dev,
1942 "cp %p had HP SSD Smart Path error\n", cp);
1943 break;
edd16368
SC		 1944 default:
1945 cmd->result = DID_ERROR << 16;
1946 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1947 cp, ei->CommandStatus);
1948 }
edd16368 1949 cmd_free(h, cp);
2cc5bfaf 1950 cmd->scsi_done(cmd);
edd16368
SC		 1951}
1952
edd16368
SC		 1953static void hpsa_pci_unmap(struct pci_dev *pdev,
1954 struct CommandList *c, int sg_used, int data_direction)
1955{
1956 int i;
edd16368 1957
50a0decf
SC		 1958 for (i = 0; i < sg_used; i++)
1959 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
1960 le32_to_cpu(c->SG[i].Len),
1961 data_direction);
edd16368
SC		 1962}
1963
a2dac136 1964static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1965 struct CommandList *cp,
1966 unsigned char *buf,
1967 size_t buflen,
1968 int data_direction)
1969{
01a02ffc 1970 u64 addr64;
edd16368
SC		 1971
1972 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1973 cp->Header.SGList = 0;
50a0decf 1974 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1975 return 0;
edd16368
SC		 1976 }
1977
50a0decf 1978 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1979 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1980 /* Prevent subsequent unmap of something never mapped */
eceaae18 1981 cp->Header.SGList = 0;
50a0decf 1982 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1983 return -1;
eceaae18 1984 }
50a0decf
SC		 1985 cp->SG[0].Addr = cpu_to_le64(addr64);
1986 cp->SG[0].Len = cpu_to_le32(buflen);
1987 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
1988 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
1989 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 1990 return 0;
edd16368
SC		 1991}
1992
1993static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1994 struct CommandList *c)
1995{
1996 DECLARE_COMPLETION_ONSTACK(wait);
1997
1998 c->waiting = &wait;
1999 enqueue_cmd_and_start_io(h, c);
2000 wait_for_completion(&wait);
2001}
2002
094963da
SC		 2003static u32 lockup_detected(struct ctlr_info *h)
2004{
2005 int cpu;
2006 u32 rc, *lockup_detected;
2007
2008 cpu = get_cpu();
2009 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2010 rc = *lockup_detected;
2011 put_cpu();
2012 return rc;
2013}
2014
a0c12413
SC		 2015static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
2016 struct CommandList *c)
2017{
a0c12413 2018 /* If controller lockup detected, fake a hardware error. */
094963da 2019 if (unlikely(lockup_detected(h)))
a0c12413 2020 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 2021 else
a0c12413 2022 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 2023}
2024
9c2fc160 2025#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 2026static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2027 struct CommandList *c, int data_direction)
2028{
9c2fc160 2029 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2030
2031 do {
7630abd0 2032 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2033 hpsa_scsi_do_simple_cmd_core(h, c);
2034 retry_count++;
9c2fc160
SC		 2035 if (retry_count > 3) {
2036 msleep(backoff_time);
2037 if (backoff_time < 1000)
2038 backoff_time *= 2;
2039 }
852af20a 2040 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2041 check_for_busy(h, c)) &&
2042 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2043 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2044}
2045
d1e8beac
SC		 2046static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2047 struct CommandList *c)
edd16368 2048{
d1e8beac
SC		 2049 const u8 *cdb = c->Request.CDB;
2050 const u8 *lun = c->Header.LUN.LunAddrBytes;
2051
2052 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2053 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2054 txt, lun[0], lun[1], lun[2], lun[3],
2055 lun[4], lun[5], lun[6], lun[7],
2056 cdb[0], cdb[1], cdb[2], cdb[3],
2057 cdb[4], cdb[5], cdb[6], cdb[7],
2058 cdb[8], cdb[9], cdb[10], cdb[11],
2059 cdb[12], cdb[13], cdb[14], cdb[15]);
2060}
2061
2062static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2063 struct CommandList *cp)
2064{
2065 const struct ErrorInfo *ei = cp->err_info;
edd16368 2066 struct device *d = &cp->h->pdev->dev;
d1e8beac 2067 const u8 *sd = ei->SenseInfo;
edd16368 2068
edd16368
SC		 2069 switch (ei->CommandStatus) {
2070 case CMD_TARGET_STATUS:
d1e8beac
SC		 2071 hpsa_print_cmd(h, "SCSI status", cp);
2072 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2073 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2074 sd[2] & 0x0f, sd[12], sd[13]);
2075 else
2076 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2077 if (ei->ScsiStatus == 0)
2078 dev_warn(d, "SCSI status is abnormally zero. "
2079 "(probably indicates selection timeout "
2080 "reported incorrectly due to a known "
2081 "firmware bug, circa July, 2001.)\n");
2082 break;
2083 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2084 break;
2085 case CMD_DATA_OVERRUN:
d1e8beac 2086 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2087 break;
2088 case CMD_INVALID: {
2089 /* controller unfortunately reports SCSI passthru's
2090 * to non-existent targets as invalid commands.
2091 */
d1e8beac
SC		 2092 hpsa_print_cmd(h, "invalid command", cp);
2093 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2094 }
2095 break;
2096 case CMD_PROTOCOL_ERR:
d1e8beac 2097 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2098 break;
2099 case CMD_HARDWARE_ERR:
d1e8beac 2100 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2101 break;
2102 case CMD_CONNECTION_LOST:
d1e8beac 2103 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2104 break;
2105 case CMD_ABORTED:
d1e8beac 2106 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2107 break;
2108 case CMD_ABORT_FAILED:
d1e8beac 2109 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2110 break;
2111 case CMD_UNSOLICITED_ABORT:
d1e8beac 2112 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2113 break;
2114 case CMD_TIMEOUT:
d1e8beac 2115 hpsa_print_cmd(h, "timed out", cp);
edd16368 2116 break;
1d5e2ed0 2117 case CMD_UNABORTABLE:
d1e8beac 2118 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2119 break;
edd16368 2120 default:
d1e8beac
SC		 2121 hpsa_print_cmd(h, "unknown status", cp);
2122 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2123 ei->CommandStatus);
2124 }
2125}
2126
2127static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2128 u16 page, unsigned char *buf,
edd16368
SC		 2129 unsigned char bufsize)
2130{
2131 int rc = IO_OK;
2132 struct CommandList *c;
2133 struct ErrorInfo *ei;
2134
45fcb86e 2135 c = cmd_alloc(h);
edd16368 2136
574f05d3 2137 if (c == NULL) {
45fcb86e 2138 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2139 return -ENOMEM;
edd16368
SC		 2140 }
2141
a2dac136
SC		 2142 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2143 page, scsi3addr, TYPE_CMD)) {
2144 rc = -1;
2145 goto out;
2146 }
edd16368
SC		 2147 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2148 ei = c->err_info;
2149 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2150 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2151 rc = -1;
2152 }
a2dac136 2153out:
45fcb86e 2154 cmd_free(h, c);
edd16368
SC		 2155 return rc;
2156}
2157
316b221a
SC		 2158static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2159 unsigned char *scsi3addr, unsigned char page,
2160 struct bmic_controller_parameters *buf, size_t bufsize)
2161{
2162 int rc = IO_OK;
2163 struct CommandList *c;
2164 struct ErrorInfo *ei;
2165
45fcb86e 2166 c = cmd_alloc(h);
316b221a 2167 if (c == NULL) { /* trouble... */
45fcb86e 2168 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2169 return -ENOMEM;
2170 }
2171
2172 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2173 page, scsi3addr, TYPE_CMD)) {
2174 rc = -1;
2175 goto out;
2176 }
2177 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2178 ei = c->err_info;
2179 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2180 hpsa_scsi_interpret_error(h, c);
2181 rc = -1;
2182 }
2183out:
45fcb86e 2184 cmd_free(h, c);
316b221a
SC		 2185 return rc;
2186 }
2187
bf711ac6
ST		 2188static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2189 u8 reset_type)
edd16368
SC		 2190{
2191 int rc = IO_OK;
2192 struct CommandList *c;
2193 struct ErrorInfo *ei;
2194
45fcb86e 2195 c = cmd_alloc(h);
edd16368
SC		 2196
2197 if (c == NULL) { /* trouble... */
45fcb86e 2198 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2199 return -ENOMEM;
edd16368
SC		 2200 }
2201
a2dac136 2202 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2203 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2204 scsi3addr, TYPE_MSG);
2205 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2206 hpsa_scsi_do_simple_cmd_core(h, c);
2207 /* no unmap needed here because no data xfer. */
2208
2209 ei = c->err_info;
2210 if (ei->CommandStatus != 0) {
d1e8beac 2211 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2212 rc = -1;
2213 }
45fcb86e 2214 cmd_free(h, c);
edd16368
SC		 2215 return rc;
2216}
2217
2218static void hpsa_get_raid_level(struct ctlr_info *h,
2219 unsigned char *scsi3addr, unsigned char *raid_level)
2220{
2221 int rc;
2222 unsigned char *buf;
2223
2224 *raid_level = RAID_UNKNOWN;
2225 buf = kzalloc(64, GFP_KERNEL);
2226 if (!buf)
2227 return;
b7bb24eb 2228 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2229 if (rc == 0)
2230 *raid_level = buf[8];
2231 if (*raid_level > RAID_UNKNOWN)
2232 *raid_level = RAID_UNKNOWN;
2233 kfree(buf);
2234 return;
2235}
2236
283b4a9b
SC		 2237#define HPSA_MAP_DEBUG
2238#ifdef HPSA_MAP_DEBUG
2239static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2240 struct raid_map_data *map_buff)
2241{
2242 struct raid_map_disk_data *dd = &map_buff->data[0];
2243 int map, row, col;
2244 u16 map_cnt, row_cnt, disks_per_row;
2245
2246 if (rc != 0)
2247 return;
2248
2ba8bfc8
SC		 2249 /* Show details only if debugging has been activated. */
2250 if (h->raid_offload_debug < 2)
2251 return;
2252
283b4a9b
SC		 2253 dev_info(&h->pdev->dev, "structure_size = %u\n",
2254 le32_to_cpu(map_buff->structure_size));
2255 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2256 le32_to_cpu(map_buff->volume_blk_size));
2257 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2258 le64_to_cpu(map_buff->volume_blk_cnt));
2259 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2260 map_buff->phys_blk_shift);
2261 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2262 map_buff->parity_rotation_shift);
2263 dev_info(&h->pdev->dev, "strip_size = %u\n",
2264 le16_to_cpu(map_buff->strip_size));
2265 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2266 le64_to_cpu(map_buff->disk_starting_blk));
2267 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2268 le64_to_cpu(map_buff->disk_blk_cnt));
2269 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2270 le16_to_cpu(map_buff->data_disks_per_row));
2271 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2272 le16_to_cpu(map_buff->metadata_disks_per_row));
2273 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2274 le16_to_cpu(map_buff->row_cnt));
2275 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2276 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2277 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2278 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2279 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2280 le16_to_cpu(map_buff->flags) &
2281 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2282 dev_info(&h->pdev->dev, "dekindex = %u\n",
2283 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2284 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2285 for (map = 0; map < map_cnt; map++) {
2286 dev_info(&h->pdev->dev, "Map%u:\n", map);
2287 row_cnt = le16_to_cpu(map_buff->row_cnt);
2288 for (row = 0; row < row_cnt; row++) {
2289 dev_info(&h->pdev->dev, " Row%u:\n", row);
2290 disks_per_row =
2291 le16_to_cpu(map_buff->data_disks_per_row);
2292 for (col = 0; col < disks_per_row; col++, dd++)
2293 dev_info(&h->pdev->dev,
2294 " D%02u: h=0x%04x xor=%u,%u\n",
2295 col, dd->ioaccel_handle,
2296 dd->xor_mult[0], dd->xor_mult[1]);
2297 disks_per_row =
2298 le16_to_cpu(map_buff->metadata_disks_per_row);
2299 for (col = 0; col < disks_per_row; col++, dd++)
2300 dev_info(&h->pdev->dev,
2301 " M%02u: h=0x%04x xor=%u,%u\n",
2302 col, dd->ioaccel_handle,
2303 dd->xor_mult[0], dd->xor_mult[1]);
2304 }
2305 }
2306}
2307#else
2308static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2309 __attribute__((unused)) int rc,
2310 __attribute__((unused)) struct raid_map_data *map_buff)
2311{
2312}
2313#endif
2314
2315static int hpsa_get_raid_map(struct ctlr_info *h,
2316 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2317{
2318 int rc = 0;
2319 struct CommandList *c;
2320 struct ErrorInfo *ei;
2321
45fcb86e 2322 c = cmd_alloc(h);
283b4a9b 2323 if (c == NULL) {
45fcb86e 2324 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2325 return -ENOMEM;
2326 }
2327 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2328 sizeof(this_device->raid_map), 0,
2329 scsi3addr, TYPE_CMD)) {
2330 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
45fcb86e 2331 cmd_free(h, c);
283b4a9b
SC		 2332 return -ENOMEM;
2333 }
2334 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2335 ei = c->err_info;
2336 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2337 hpsa_scsi_interpret_error(h, c);
45fcb86e 2338 cmd_free(h, c);
283b4a9b
SC		 2339 return -1;
2340 }
45fcb86e 2341 cmd_free(h, c);
283b4a9b
SC		 2342
2343 /* @todo in the future, dynamically allocate RAID map memory */
2344 if (le32_to_cpu(this_device->raid_map.structure_size) >
2345 sizeof(this_device->raid_map)) {
2346 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2347 rc = -1;
2348 }
2349 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2350 return rc;
2351}
2352
03383736
DB		 2353static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2354 unsigned char scsi3addr[], u16 bmic_device_index,
2355 struct bmic_identify_physical_device *buf, size_t bufsize)
2356{
2357 int rc = IO_OK;
2358 struct CommandList *c;
2359 struct ErrorInfo *ei;
2360
2361 c = cmd_alloc(h);
2362 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2363 0, RAID_CTLR_LUNID, TYPE_CMD);
2364 if (rc)
2365 goto out;
2366
2367 c->Request.CDB[2] = bmic_device_index & 0xff;
2368 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2369
2370 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2371 ei = c->err_info;
2372 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2373 hpsa_scsi_interpret_error(h, c);
2374 rc = -1;
2375 }
2376out:
2377 cmd_free(h, c);
2378 return rc;
2379}
2380
1b70150a
SC		 2381static int hpsa_vpd_page_supported(struct ctlr_info *h,
2382 unsigned char scsi3addr[], u8 page)
2383{
2384 int rc;
2385 int i;
2386 int pages;
2387 unsigned char *buf, bufsize;
2388
2389 buf = kzalloc(256, GFP_KERNEL);
2390 if (!buf)
2391 return 0;
2392
2393 /* Get the size of the page list first */
2394 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2395 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2396 buf, HPSA_VPD_HEADER_SZ);
2397 if (rc != 0)
2398 goto exit_unsupported;
2399 pages = buf[3];
2400 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2401 bufsize = pages + HPSA_VPD_HEADER_SZ;
2402 else
2403 bufsize = 255;
2404
2405 /* Get the whole VPD page list */
2406 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2407 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2408 buf, bufsize);
2409 if (rc != 0)
2410 goto exit_unsupported;
2411
2412 pages = buf[3];
2413 for (i = 1; i <= pages; i++)
2414 if (buf[3 + i] == page)
2415 goto exit_supported;
2416exit_unsupported:
2417 kfree(buf);
2418 return 0;
2419exit_supported:
2420 kfree(buf);
2421 return 1;
2422}
2423
283b4a9b
SC		 2424static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2425 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2426{
2427 int rc;
2428 unsigned char *buf;
2429 u8 ioaccel_status;
2430
2431 this_device->offload_config = 0;
2432 this_device->offload_enabled = 0;
2433
2434 buf = kzalloc(64, GFP_KERNEL);
2435 if (!buf)
2436 return;
1b70150a
SC		 2437 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2438 goto out;
283b4a9b 2439 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2440 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2441 if (rc != 0)
2442 goto out;
2443
2444#define IOACCEL_STATUS_BYTE 4
2445#define OFFLOAD_CONFIGURED_BIT 0x01
2446#define OFFLOAD_ENABLED_BIT 0x02
2447 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2448 this_device->offload_config =
2449 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2450 if (this_device->offload_config) {
2451 this_device->offload_enabled =
2452 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2453 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2454 this_device->offload_enabled = 0;
2455 }
2456out:
2457 kfree(buf);
2458 return;
2459}
2460
edd16368
SC		 2461/* Get the device id from inquiry page 0x83 */
2462static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2463 unsigned char *device_id, int buflen)
2464{
2465 int rc;
2466 unsigned char *buf;
2467
2468 if (buflen > 16)
2469 buflen = 16;
2470 buf = kzalloc(64, GFP_KERNEL);
2471 if (!buf)
a84d794d 2472 return -ENOMEM;
b7bb24eb 2473 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2474 if (rc == 0)
2475 memcpy(device_id, &buf[8], buflen);
2476 kfree(buf);
2477 return rc != 0;
2478}
2479
2480static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2481 void *buf, int bufsize,
edd16368
SC		 2482 int extended_response)
2483{
2484 int rc = IO_OK;
2485 struct CommandList *c;
2486 unsigned char scsi3addr[8];
2487 struct ErrorInfo *ei;
2488
45fcb86e 2489 c = cmd_alloc(h);
edd16368 2490 if (c == NULL) { /* trouble... */
45fcb86e 2491 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2492 return -1;
2493 }
e89c0ae7
SC		 2494 /* address the controller */
2495 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2496 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2497 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2498 rc = -1;
2499 goto out;
2500 }
edd16368
SC		 2501 if (extended_response)
2502 c->Request.CDB[1] = extended_response;
2503 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2504 ei = c->err_info;
2505 if (ei->CommandStatus != 0 &&
2506 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2507 hpsa_scsi_interpret_error(h, c);
edd16368 2508 rc = -1;
283b4a9b 2509 } else {
03383736
DB		 2510 struct ReportLUNdata *rld = buf;
2511
2512 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2513 dev_err(&h->pdev->dev,
2514 "report luns requested format %u, got %u\n",
2515 extended_response,
03383736 2516 rld->extended_response_flag);
283b4a9b
SC		 2517 rc = -1;
2518 }
edd16368 2519 }
a2dac136 2520out:
45fcb86e 2521 cmd_free(h, c);
edd16368
SC		 2522 return rc;
2523}
2524
2525static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2526 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2527{
03383736
DB		 2528 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2529 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2530}
2531
2532static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2533 struct ReportLUNdata *buf, int bufsize)
2534{
2535 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2536}
2537
2538static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2539 int bus, int target, int lun)
2540{
2541 device->bus = bus;
2542 device->target = target;
2543 device->lun = lun;
2544}
2545
9846590e
SC		 2546/* Use VPD inquiry to get details of volume status */
2547static int hpsa_get_volume_status(struct ctlr_info *h,
2548 unsigned char scsi3addr[])
2549{
2550 int rc;
2551 int status;
2552 int size;
2553 unsigned char *buf;
2554
2555 buf = kzalloc(64, GFP_KERNEL);
2556 if (!buf)
2557 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2558
2559 /* Does controller have VPD for logical volume status? */
24a4b078 2560 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2561 goto exit_failed;
9846590e
SC		 2562
2563 /* Get the size of the VPD return buffer */
2564 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2565 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2566 if (rc != 0)
9846590e 2567 goto exit_failed;
9846590e
SC		 2568 size = buf[3];
2569
2570 /* Now get the whole VPD buffer */
2571 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2572 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2573 if (rc != 0)
9846590e 2574 goto exit_failed;
9846590e
SC		 2575 status = buf[4]; /* status byte */
2576
2577 kfree(buf);
2578 return status;
2579exit_failed:
2580 kfree(buf);
2581 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2582}
2583
2584/* Determine offline status of a volume.
2585 * Return either:
2586 * 0 (not offline)
67955ba3 2587 * 0xff (offline for unknown reasons)
9846590e
SC		 2588 * # (integer code indicating one of several NOT READY states
2589 * describing why a volume is to be kept offline)
2590 */
67955ba3 2591static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2592 unsigned char scsi3addr[])
2593{
2594 struct CommandList *c;
2595 unsigned char *sense, sense_key, asc, ascq;
2596 int ldstat = 0;
2597 u16 cmd_status;
2598 u8 scsi_status;
2599#define ASC_LUN_NOT_READY 0x04
2600#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2601#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2602
2603 c = cmd_alloc(h);
2604 if (!c)
2605 return 0;
2606 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2607 hpsa_scsi_do_simple_cmd_core(h, c);
2608 sense = c->err_info->SenseInfo;
2609 sense_key = sense[2];
2610 asc = sense[12];
2611 ascq = sense[13];
2612 cmd_status = c->err_info->CommandStatus;
2613 scsi_status = c->err_info->ScsiStatus;
2614 cmd_free(h, c);
2615 /* Is the volume 'not ready'? */
2616 if (cmd_status != CMD_TARGET_STATUS ||
2617 scsi_status != SAM_STAT_CHECK_CONDITION ||
2618 sense_key != NOT_READY ||
2619 asc != ASC_LUN_NOT_READY) {
2620 return 0;
2621 }
2622
2623 /* Determine the reason for not ready state */
2624 ldstat = hpsa_get_volume_status(h, scsi3addr);
2625
2626 /* Keep volume offline in certain cases: */
2627 switch (ldstat) {
2628 case HPSA_LV_UNDERGOING_ERASE:
2629 case HPSA_LV_UNDERGOING_RPI:
2630 case HPSA_LV_PENDING_RPI:
2631 case HPSA_LV_ENCRYPTED_NO_KEY:
2632 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2633 case HPSA_LV_UNDERGOING_ENCRYPTION:
2634 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2635 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2636 return ldstat;
2637 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2638 /* If VPD status page isn't available,
2639 * use ASC/ASCQ to determine state
2640 */
2641 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2642 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2643 return ldstat;
2644 break;
2645 default:
2646 break;
2647 }
2648 return 0;
2649}
2650
edd16368 2651static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2652 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2653 unsigned char *is_OBDR_device)
edd16368 2654{
0b0e1d6c
SC		 2655
2656#define OBDR_SIG_OFFSET 43
2657#define OBDR_TAPE_SIG "$DR-10"
2658#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2659#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2660
ea6d3bc3 2661 unsigned char *inq_buff;
0b0e1d6c 2662 unsigned char *obdr_sig;
edd16368 2663
ea6d3bc3 2664 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2665 if (!inq_buff)
2666 goto bail_out;
2667
edd16368
SC		 2668 /* Do an inquiry to the device to see what it is. */
2669 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2670 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2671 /* Inquiry failed (msg printed already) */
2672 dev_err(&h->pdev->dev,
2673 "hpsa_update_device_info: inquiry failed\n");
2674 goto bail_out;
2675 }
2676
edd16368
SC		 2677 this_device->devtype = (inq_buff[0] & 0x1f);
2678 memcpy(this_device->scsi3addr, scsi3addr, 8);
2679 memcpy(this_device->vendor, &inq_buff[8],
2680 sizeof(this_device->vendor));
2681 memcpy(this_device->model, &inq_buff[16],
2682 sizeof(this_device->model));
edd16368
SC		 2683 memset(this_device->device_id, 0,
2684 sizeof(this_device->device_id));
2685 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2686 sizeof(this_device->device_id));
2687
2688 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2689 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2690 int volume_offline;
2691
edd16368 2692 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2693 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2694 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2695 volume_offline = hpsa_volume_offline(h, scsi3addr);
2696 if (volume_offline < 0 || volume_offline > 0xff)
2697 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2698 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2699 } else {
edd16368 2700 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2701 this_device->offload_config = 0;
2702 this_device->offload_enabled = 0;
9846590e 2703 this_device->volume_offline = 0;
03383736 2704 this_device->queue_depth = h->nr_cmds;
283b4a9b 2705 }
edd16368 2706
0b0e1d6c
SC		 2707 if (is_OBDR_device) {
2708 /* See if this is a One-Button-Disaster-Recovery device
2709 * by looking for "$DR-10" at offset 43 in inquiry data.
2710 */
2711 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2712 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2713 strncmp(obdr_sig, OBDR_TAPE_SIG,
2714 OBDR_SIG_LEN) == 0);
2715 }
2716
edd16368
SC		 2717 kfree(inq_buff);
2718 return 0;
2719
2720bail_out:
2721 kfree(inq_buff);
2722 return 1;
2723}
2724
4f4eb9f1 2725static unsigned char *ext_target_model[] = {
edd16368
SC		 2726 "MSA2012",
2727 "MSA2024",
2728 "MSA2312",
2729 "MSA2324",
fda38518 2730 "P2000 G3 SAS",
e06c8e5c 2731 "MSA 2040 SAS",
edd16368
SC		 2732 NULL,
2733};
2734
4f4eb9f1 2735static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2736{
2737 int i;
2738
4f4eb9f1
ST		 2739 for (i = 0; ext_target_model[i]; i++)
2740 if (strncmp(device->model, ext_target_model[i],
2741 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2742 return 1;
2743 return 0;
2744}
2745
2746/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2747 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2748 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2749 * Logical drive target and lun are assigned at this time, but
2750 * physical device lun and target assignment are deferred (assigned
2751 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2752 */
2753static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2754 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2755{
1f310bde
SC		 2756 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2757
2758 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2759 /* physical device, target and lun filled in later */
edd16368 2760 if (is_hba_lunid(lunaddrbytes))
1f310bde 2761 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2762 else
1f310bde
SC		 2763 /* defer target, lun assignment for physical devices */
2764 hpsa_set_bus_target_lun(device, 2, -1, -1);
2765 return;
2766 }
2767 /* It's a logical device */
4f4eb9f1
ST		 2768 if (is_ext_target(h, device)) {
2769 /* external target way, put logicals on bus 1
1f310bde
SC		 2770 * and match target/lun numbers box
2771 * reports, other smart array, bus 0, target 0, match lunid
2772 */
2773 hpsa_set_bus_target_lun(device,
2774 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2775 return;
edd16368 2776 }
1f310bde 2777 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2778}
2779
2780/*
2781 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2782 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2783 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2784 * it for some reason. *tmpdevice is the target we're adding,
2785 * this_device is a pointer into the current element of currentsd[]
2786 * that we're building up in update_scsi_devices(), below.
2787 * lunzerobits is a bitmap that tracks which targets already have a
2788 * lun 0 assigned.
2789 * Returns 1 if an enclosure was added, 0 if not.
2790 */
4f4eb9f1 2791static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2792 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2793 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2794 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2795{
2796 unsigned char scsi3addr[8];
2797
1f310bde 2798 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2799 return 0; /* There is already a lun 0 on this target. */
2800
2801 if (!is_logical_dev_addr_mode(lunaddrbytes))
2802 return 0; /* It's the logical targets that may lack lun 0. */
2803
4f4eb9f1
ST		 2804 if (!is_ext_target(h, tmpdevice))
2805 return 0; /* Only external target devices have this problem. */
edd16368 2806
1f310bde 2807 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2808 return 0;
2809
c4f8a299 2810 memset(scsi3addr, 0, 8);
1f310bde 2811 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2812 if (is_hba_lunid(scsi3addr))
2813 return 0; /* Don't add the RAID controller here. */
2814
339b2b14
SC		 2815 if (is_scsi_rev_5(h))
2816 return 0; /* p1210m doesn't need to do this. */
2817
4f4eb9f1 2818 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2819 dev_warn(&h->pdev->dev, "Maximum number of external "
2820 "target devices exceeded. Check your hardware "
edd16368
SC		 2821 "configuration.");
2822 return 0;
2823 }
2824
0b0e1d6c 2825 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2826 return 0;
4f4eb9f1 2827 (*n_ext_target_devs)++;
1f310bde
SC		 2828 hpsa_set_bus_target_lun(this_device,
2829 tmpdevice->bus, tmpdevice->target, 0);
2830 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2831 return 1;
2832}
2833
54b6e9e9
ST		 2834/*
2835 * Get address of physical disk used for an ioaccel2 mode command:
2836 * 1. Extract ioaccel2 handle from the command.
2837 * 2. Find a matching ioaccel2 handle from list of physical disks.
2838 * 3. Return:
2839 * 1 and set scsi3addr to address of matching physical
2840 * 0 if no matching physical disk was found.
2841 */
2842static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2843 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2844{
2845 struct ReportExtendedLUNdata *physicals = NULL;
2846 int responsesize = 24; /* size of physical extended response */
54b6e9e9
ST		 2847 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2848 u32 nphysicals = 0; /* number of reported physical devs */
2849 int found = 0; /* found match (1) or not (0) */
2850 u32 find; /* handle we need to match */
2851 int i;
2852 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2853 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2854 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2b08b3e9
DB		 2855 __le32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2856 __le32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
54b6e9e9
ST		 2857
2858 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2859 return 0; /* no match */
2860
2861 /* point to the ioaccel2 device handle */
2862 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2863 if (c2a == NULL)
2864 return 0; /* no match */
2865
2866 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2867 if (scmd == NULL)
2868 return 0; /* no match */
2869
2870 d = scmd->device->hostdata;
2871 if (d == NULL)
2872 return 0; /* no match */
2873
50a0decf 2874 it_nexus = cpu_to_le32(d->ioaccel_handle);
2b08b3e9
DB		 2875 scsi_nexus = c2a->scsi_nexus;
2876 find = le32_to_cpu(c2a->scsi_nexus);
54b6e9e9 2877
2ba8bfc8
SC		 2878 if (h->raid_offload_debug > 0)
2879 dev_info(&h->pdev->dev,
2880 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2881 __func__, scsi_nexus,
2882 d->device_id[0], d->device_id[1], d->device_id[2],
2883 d->device_id[3], d->device_id[4], d->device_id[5],
2884 d->device_id[6], d->device_id[7], d->device_id[8],
2885 d->device_id[9], d->device_id[10], d->device_id[11],
2886 d->device_id[12], d->device_id[13], d->device_id[14],
2887 d->device_id[15]);
2888
54b6e9e9
ST		 2889 /* Get the list of physical devices */
2890 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2891 if (physicals == NULL)
2892 return 0;
03383736 2893 if (hpsa_scsi_do_report_phys_luns(h, physicals, reportsize)) {
54b6e9e9
ST		 2894 dev_err(&h->pdev->dev,
2895 "Can't lookup %s device handle: report physical LUNs failed.\n",
2896 "HP SSD Smart Path");
2897 kfree(physicals);
2898 return 0;
2899 }
2900 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2901 responsesize;
2902
54b6e9e9
ST		 2903 /* find ioaccel2 handle in list of physicals: */
2904 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2905 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2906
54b6e9e9 2907 /* handle is in bytes 28-31 of each lun */
d5b5d964 2908 if (entry->ioaccel_handle != find)
54b6e9e9 2909 continue; /* didn't match */
54b6e9e9 2910 found = 1;
d5b5d964 2911 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2912 if (h->raid_offload_debug > 0)
2913 dev_info(&h->pdev->dev,
d5b5d964 2914 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2915 __func__, find,
d5b5d964 2916 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2917 break; /* found it */
2918 }
2919
2920 kfree(physicals);
2921 if (found)
2922 return 1;
2923 else
2924 return 0;
2925
2926}
edd16368
SC		 2927/*
2928 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2929 * logdev. The number of luns in physdev and logdev are returned in
2930 * *nphysicals and *nlogicals, respectively.
2931 * Returns 0 on success, -1 otherwise.
2932 */
2933static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 2934 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 2935 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2936{
03383736 2937 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 2938 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2939 return -1;
2940 }
03383736 2941 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 2942 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 2943 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
2944 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 2945 *nphysicals = HPSA_MAX_PHYS_LUN;
2946 }
03383736 2947 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 2948 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2949 return -1;
2950 }
6df1e954 2951 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2952 /* Reject Logicals in excess of our max capability. */
2953 if (*nlogicals > HPSA_MAX_LUN) {
2954 dev_warn(&h->pdev->dev,
2955 "maximum logical LUNs (%d) exceeded. "
2956 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2957 *nlogicals - HPSA_MAX_LUN);
2958 *nlogicals = HPSA_MAX_LUN;
2959 }
2960 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2961 dev_warn(&h->pdev->dev,
2962 "maximum logical + physical LUNs (%d) exceeded. "
2963 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2964 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2965 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2966 }
2967 return 0;
2968}
2969
42a91641
DB		 2970static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
2971 int i, int nphysicals, int nlogicals,
a93aa1fe 2972 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2973 struct ReportLUNdata *logdev_list)
2974{
2975 /* Helper function, figure out where the LUN ID info is coming from
2976 * given index i, lists of physical and logical devices, where in
2977 * the list the raid controller is supposed to appear (first or last)
2978 */
2979
2980 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2981 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2982
2983 if (i == raid_ctlr_position)
2984 return RAID_CTLR_LUNID;
2985
2986 if (i < logicals_start)
d5b5d964
SC		 2987 return &physdev_list->LUN[i -
2988 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2989
2990 if (i < last_device)
2991 return &logdev_list->LUN[i - nphysicals -
2992 (raid_ctlr_position == 0)][0];
2993 BUG();
2994 return NULL;
2995}
2996
316b221a
SC		 2997static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2998{
2999 int rc;
6e8e8088 3000 int hba_mode_enabled;
316b221a
SC		 3001 struct bmic_controller_parameters *ctlr_params;
3002 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3003 GFP_KERNEL);
3004
3005 if (!ctlr_params)
96444fbb 3006 return -ENOMEM;
316b221a
SC		 3007 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3008 sizeof(struct bmic_controller_parameters));
96444fbb 3009 if (rc) {
316b221a 3010 kfree(ctlr_params);
96444fbb 3011 return rc;
316b221a 3012 }
6e8e8088
JH		 3013
3014 hba_mode_enabled =
3015 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3016 kfree(ctlr_params);
3017 return hba_mode_enabled;
316b221a
SC		 3018}
3019
03383736
DB		 3020/* get physical drive ioaccel handle and queue depth */
3021static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3022 struct hpsa_scsi_dev_t *dev,
3023 u8 *lunaddrbytes,
3024 struct bmic_identify_physical_device *id_phys)
3025{
3026 int rc;
3027 struct ext_report_lun_entry *rle =
3028 (struct ext_report_lun_entry *) lunaddrbytes;
3029
3030 dev->ioaccel_handle = rle->ioaccel_handle;
3031 memset(id_phys, 0, sizeof(*id_phys));
3032 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3033 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3034 sizeof(*id_phys));
3035 if (!rc)
3036 /* Reserve space for FW operations */
3037#define DRIVE_CMDS_RESERVED_FOR_FW 2
3038#define DRIVE_QUEUE_DEPTH 7
3039 dev->queue_depth =
3040 le16_to_cpu(id_phys->current_queue_depth_limit) -
3041 DRIVE_CMDS_RESERVED_FOR_FW;
3042 else
3043 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3044 atomic_set(&dev->ioaccel_cmds_out, 0);
3045}
3046
edd16368
SC		 3047static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3048{
3049 /* the idea here is we could get notified
3050 * that some devices have changed, so we do a report
3051 * physical luns and report logical luns cmd, and adjust
3052 * our list of devices accordingly.
3053 *
3054 * The scsi3addr's of devices won't change so long as the
3055 * adapter is not reset. That means we can rescan and
3056 * tell which devices we already know about, vs. new
3057 * devices, vs. disappearing devices.
3058 */
a93aa1fe 3059 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3060 struct ReportLUNdata *logdev_list = NULL;
03383736 3061 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3062 u32 nphysicals = 0;
3063 u32 nlogicals = 0;
3064 u32 ndev_allocated = 0;
edd16368
SC		 3065 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3066 int ncurrent = 0;
4f4eb9f1 3067 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3068 int raid_ctlr_position;
2bbf5c7f 3069 int rescan_hba_mode;
aca4a520 3070 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3071
cfe5badc 3072 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3073 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3074 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3075 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3076 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3077
03383736
DB		 3078 if (!currentsd || !physdev_list || !logdev_list ||
3079 !tmpdevice || !id_phys) {
edd16368
SC		 3080 dev_err(&h->pdev->dev, "out of memory\n");
3081 goto out;
3082 }
3083 memset(lunzerobits, 0, sizeof(lunzerobits));
3084
316b221a 3085 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3086 if (rescan_hba_mode < 0)
3087 goto out;
316b221a
SC		 3088
3089 if (!h->hba_mode_enabled && rescan_hba_mode)
3090 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3091 else if (h->hba_mode_enabled && !rescan_hba_mode)
3092 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3093
3094 h->hba_mode_enabled = rescan_hba_mode;
3095
03383736
DB		 3096 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3097 logdev_list, &nlogicals))
edd16368
SC		 3098 goto out;
3099
aca4a520
ST		 3100 /* We might see up to the maximum number of logical and physical disks
3101 * plus external target devices, and a device for the local RAID
3102 * controller.
edd16368 3103 */
aca4a520 3104 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3105
3106 /* Allocate the per device structures */
3107 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3108 if (i >= HPSA_MAX_DEVICES) {
3109 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3110 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3111 ndevs_to_allocate - HPSA_MAX_DEVICES);
3112 break;
3113 }
3114
edd16368
SC		 3115 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3116 if (!currentsd[i]) {
3117 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3118 __FILE__, __LINE__);
3119 goto out;
3120 }
3121 ndev_allocated++;
3122 }
3123
8645291b 3124 if (is_scsi_rev_5(h))
339b2b14
SC		 3125 raid_ctlr_position = 0;
3126 else
3127 raid_ctlr_position = nphysicals + nlogicals;
3128
edd16368 3129 /* adjust our table of devices */
4f4eb9f1 3130 n_ext_target_devs = 0;
edd16368 3131 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3132 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3133
3134 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3135 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3136 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3137 /* skip masked physical devices. */
339b2b14
SC		 3138 if (lunaddrbytes[3] & 0xC0 &&
3139 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3140 continue;
3141
3142 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3143 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3144 &is_OBDR))
edd16368 3145 continue; /* skip it if we can't talk to it. */
1f310bde 3146 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3147 this_device = currentsd[ncurrent];
3148
3149 /*
4f4eb9f1 3150 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3151 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3152 * is nonetheless an enclosure device there. We have to
3153 * present that otherwise linux won't find anything if
3154 * there is no lun 0.
3155 */
4f4eb9f1 3156 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3157 lunaddrbytes, lunzerobits,
4f4eb9f1 3158 &n_ext_target_devs)) {
edd16368
SC		 3159 ncurrent++;
3160 this_device = currentsd[ncurrent];
3161 }
3162
3163 *this_device = *tmpdevice;
edd16368
SC		 3164
3165 switch (this_device->devtype) {
0b0e1d6c 3166 case TYPE_ROM:
edd16368
SC		 3167 /* We don't *really* support actual CD-ROM devices,
3168 * just "One Button Disaster Recovery" tape drive
3169 * which temporarily pretends to be a CD-ROM drive.
3170 * So we check that the device is really an OBDR tape
3171 * device by checking for "$DR-10" in bytes 43-48 of
3172 * the inquiry data.
3173 */
0b0e1d6c
SC		 3174 if (is_OBDR)
3175 ncurrent++;
edd16368
SC		 3176 break;
3177 case TYPE_DISK:
316b221a
SC		 3178 if (h->hba_mode_enabled) {
3179 /* never use raid mapper in HBA mode */
3180 this_device->offload_enabled = 0;
3181 ncurrent++;
3182 break;
3183 } else if (h->acciopath_status) {
3184 if (i >= nphysicals) {
3185 ncurrent++;
3186 break;
3187 }
3188 } else {
3189 if (i < nphysicals)
3190 break;
283b4a9b 3191 ncurrent++;
edd16368 3192 break;
283b4a9b 3193 }
03383736
DB		 3194 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
3195 h->transMethod & CFGTBL_Trans_io_accel2) {
3196 hpsa_get_ioaccel_drive_info(h, this_device,
3197 lunaddrbytes, id_phys);
3198 atomic_set(&this_device->ioaccel_cmds_out, 0);
283b4a9b
SC		 3199 ncurrent++;
3200 }
edd16368
SC		 3201 break;
3202 case TYPE_TAPE:
3203 case TYPE_MEDIUM_CHANGER:
3204 ncurrent++;
3205 break;
3206 case TYPE_RAID:
3207 /* Only present the Smartarray HBA as a RAID controller.
3208 * If it's a RAID controller other than the HBA itself
3209 * (an external RAID controller, MSA500 or similar)
3210 * don't present it.
3211 */
3212 if (!is_hba_lunid(lunaddrbytes))
3213 break;
3214 ncurrent++;
3215 break;
3216 default:
3217 break;
3218 }
cfe5badc 3219 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3220 break;
3221 }
03383736 3222 hpsa_update_log_drive_phys_drive_ptrs(h, currentsd, ncurrent);
edd16368
SC		 3223 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3224out:
3225 kfree(tmpdevice);
3226 for (i = 0; i < ndev_allocated; i++)
3227 kfree(currentsd[i]);
3228 kfree(currentsd);
edd16368
SC		 3229 kfree(physdev_list);
3230 kfree(logdev_list);
03383736 3231 kfree(id_phys);
edd16368
SC		 3232}
3233
c7ee65b3
WS		 3234/*
3235 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3236 * dma mapping and fills in the scatter gather entries of the
3237 * hpsa command, cp.
3238 */
33a2ffce 3239static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3240 struct CommandList *cp,
3241 struct scsi_cmnd *cmd)
3242{
3243 unsigned int len;
3244 struct scatterlist *sg;
01a02ffc 3245 u64 addr64;
33a2ffce
SC		 3246 int use_sg, i, sg_index, chained;
3247 struct SGDescriptor *curr_sg;
edd16368 3248
33a2ffce 3249 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3250
3251 use_sg = scsi_dma_map(cmd);
3252 if (use_sg < 0)
3253 return use_sg;
3254
3255 if (!use_sg)
3256 goto sglist_finished;
3257
33a2ffce
SC		 3258 curr_sg = cp->SG;
3259 chained = 0;
3260 sg_index = 0;
edd16368 3261 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3262 if (i == h->max_cmd_sg_entries - 1 &&
3263 use_sg > h->max_cmd_sg_entries) {
3264 chained = 1;
3265 curr_sg = h->cmd_sg_list[cp->cmdindex];
3266 sg_index = 0;
3267 }
01a02ffc 3268 addr64 = (u64) sg_dma_address(sg);
edd16368 3269 len = sg_dma_len(sg);
50a0decf
SC		 3270 curr_sg->Addr = cpu_to_le64(addr64);
3271 curr_sg->Len = cpu_to_le32(len);
3272 curr_sg->Ext = cpu_to_le32(0);
33a2ffce
SC		 3273 curr_sg++;
3274 }
50a0decf 3275 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3276
3277 if (use_sg + chained > h->maxSG)
3278 h->maxSG = use_sg + chained;
3279
3280 if (chained) {
3281 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3282 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3283 if (hpsa_map_sg_chain_block(h, cp)) {
3284 scsi_dma_unmap(cmd);
3285 return -1;
3286 }
33a2ffce 3287 return 0;
edd16368
SC		 3288 }
3289
3290sglist_finished:
3291
01a02ffc 3292 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3293 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3294 return 0;
3295}
3296
283b4a9b
SC		 3297#define IO_ACCEL_INELIGIBLE (1)
3298static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3299{
3300 int is_write = 0;
3301 u32 block;
3302 u32 block_cnt;
3303
3304 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3305 switch (cdb[0]) {
3306 case WRITE_6:
3307 case WRITE_12:
3308 is_write = 1;
3309 case READ_6:
3310 case READ_12:
3311 if (*cdb_len == 6) {
3312 block = (((u32) cdb[2]) << 8) | cdb[3];
3313 block_cnt = cdb[4];
3314 } else {
3315 BUG_ON(*cdb_len != 12);
3316 block = (((u32) cdb[2]) << 24) |
3317 (((u32) cdb[3]) << 16) |
3318 (((u32) cdb[4]) << 8) |
3319 cdb[5];
3320 block_cnt =
3321 (((u32) cdb[6]) << 24) |
3322 (((u32) cdb[7]) << 16) |
3323 (((u32) cdb[8]) << 8) |
3324 cdb[9];
3325 }
3326 if (block_cnt > 0xffff)
3327 return IO_ACCEL_INELIGIBLE;
3328
3329 cdb[0] = is_write ? WRITE_10 : READ_10;
3330 cdb[1] = 0;
3331 cdb[2] = (u8) (block >> 24);
3332 cdb[3] = (u8) (block >> 16);
3333 cdb[4] = (u8) (block >> 8);
3334 cdb[5] = (u8) (block);
3335 cdb[6] = 0;
3336 cdb[7] = (u8) (block_cnt >> 8);
3337 cdb[8] = (u8) (block_cnt);
3338 cdb[9] = 0;
3339 *cdb_len = 10;
3340 break;
3341 }
3342 return 0;
3343}
3344
c349775e 3345static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3346 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3347 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3348{
3349 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3350 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3351 unsigned int len;
3352 unsigned int total_len = 0;
3353 struct scatterlist *sg;
3354 u64 addr64;
3355 int use_sg, i;
3356 struct SGDescriptor *curr_sg;
3357 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3358
283b4a9b 3359 /* TODO: implement chaining support */
03383736
DB		 3360 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3361 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3362 return IO_ACCEL_INELIGIBLE;
03383736 3363 }
283b4a9b 3364
e1f7de0c
MG		 3365 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3366
03383736
DB		 3367 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3368 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3369 return IO_ACCEL_INELIGIBLE;
03383736 3370 }
283b4a9b 3371
e1f7de0c
MG		 3372 c->cmd_type = CMD_IOACCEL1;
3373
3374 /* Adjust the DMA address to point to the accelerated command buffer */
3375 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3376 (c->cmdindex * sizeof(*cp));
3377 BUG_ON(c->busaddr & 0x0000007F);
3378
3379 use_sg = scsi_dma_map(cmd);
03383736
DB		 3380 if (use_sg < 0) {
3381 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3382 return use_sg;
03383736 3383 }
e1f7de0c
MG		 3384
3385 if (use_sg) {
3386 curr_sg = cp->SG;
3387 scsi_for_each_sg(cmd, sg, use_sg, i) {
3388 addr64 = (u64) sg_dma_address(sg);
3389 len = sg_dma_len(sg);
3390 total_len += len;
50a0decf
SC		 3391 curr_sg->Addr = cpu_to_le64(addr64);
3392 curr_sg->Len = cpu_to_le32(len);
3393 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3394 curr_sg++;
3395 }
50a0decf 3396 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3397
3398 switch (cmd->sc_data_direction) {
3399 case DMA_TO_DEVICE:
3400 control |= IOACCEL1_CONTROL_DATA_OUT;
3401 break;
3402 case DMA_FROM_DEVICE:
3403 control |= IOACCEL1_CONTROL_DATA_IN;
3404 break;
3405 case DMA_NONE:
3406 control |= IOACCEL1_CONTROL_NODATAXFER;
3407 break;
3408 default:
3409 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3410 cmd->sc_data_direction);
3411 BUG();
3412 break;
3413 }
3414 } else {
3415 control |= IOACCEL1_CONTROL_NODATAXFER;
3416 }
3417
c349775e 3418 c->Header.SGList = use_sg;
e1f7de0c 3419 /* Fill out the command structure to submit */
2b08b3e9
DB		 3420 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3421 cp->transfer_len = cpu_to_le32(total_len);
3422 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3423 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3424 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3425 memcpy(cp->CDB, cdb, cdb_len);
3426 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3427 /* Tag was already set at init time. */
283b4a9b 3428 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3429 return 0;
3430}
edd16368 3431
283b4a9b
SC		 3432/*
3433 * Queue a command directly to a device behind the controller using the
3434 * I/O accelerator path.
3435 */
3436static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3437 struct CommandList *c)
3438{
3439 struct scsi_cmnd *cmd = c->scsi_cmd;
3440 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3441
03383736
DB		 3442 c->phys_disk = dev;
3443
283b4a9b 3444 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3445 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3446}
3447
dd0e19f3
ST		 3448/*
3449 * Set encryption parameters for the ioaccel2 request
3450 */
3451static void set_encrypt_ioaccel2(struct ctlr_info *h,
3452 struct CommandList *c, struct io_accel2_cmd *cp)
3453{
3454 struct scsi_cmnd *cmd = c->scsi_cmd;
3455 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3456 struct raid_map_data *map = &dev->raid_map;
3457 u64 first_block;
3458
3459 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3460
3461 /* Are we doing encryption on this device */
2b08b3e9 3462 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3463 return;
3464 /* Set the data encryption key index. */
3465 cp->dekindex = map->dekindex;
3466
3467 /* Set the encryption enable flag, encoded into direction field. */
3468 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3469
3470 /* Set encryption tweak values based on logical block address
3471 * If block size is 512, tweak value is LBA.
3472 * For other block sizes, tweak is (LBA * block size)/ 512)
3473 */
3474 switch (cmd->cmnd[0]) {
3475 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3476 case WRITE_6:
3477 case READ_6:
2b08b3e9 3478 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3479 break;
3480 case WRITE_10:
3481 case READ_10:
dd0e19f3
ST		 3482 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3483 case WRITE_12:
3484 case READ_12:
2b08b3e9 3485 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3486 break;
3487 case WRITE_16:
3488 case READ_16:
2b08b3e9 3489 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3490 break;
3491 default:
3492 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3493 "ERROR: %s: size (0x%x) not supported for encryption\n",
3494 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3495 BUG();
3496 break;
3497 }
2b08b3e9
DB		 3498
3499 if (le32_to_cpu(map->volume_blk_size) != 512)
3500 first_block = first_block *
3501 le32_to_cpu(map->volume_blk_size)/512;
3502
3503 cp->tweak_lower = cpu_to_le32(first_block);
3504 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3505}
3506
c349775e
ST		 3507static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3508 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3509 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3510{
3511 struct scsi_cmnd *cmd = c->scsi_cmd;
3512 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3513 struct ioaccel2_sg_element *curr_sg;
3514 int use_sg, i;
3515 struct scatterlist *sg;
3516 u64 addr64;
3517 u32 len;
3518 u32 total_len = 0;
3519
03383736
DB		 3520 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3521 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3522 return IO_ACCEL_INELIGIBLE;
03383736 3523 }
c349775e 3524
03383736
DB		 3525 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3526 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3527 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3528 }
3529
c349775e
ST		 3530 c->cmd_type = CMD_IOACCEL2;
3531 /* Adjust the DMA address to point to the accelerated command buffer */
3532 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3533 (c->cmdindex * sizeof(*cp));
3534 BUG_ON(c->busaddr & 0x0000007F);
3535
3536 memset(cp, 0, sizeof(*cp));
3537 cp->IU_type = IOACCEL2_IU_TYPE;
3538
3539 use_sg = scsi_dma_map(cmd);
03383736
DB		 3540 if (use_sg < 0) {
3541 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3542 return use_sg;
03383736 3543 }
c349775e
ST		 3544
3545 if (use_sg) {
3546 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3547 curr_sg = cp->sg;
3548 scsi_for_each_sg(cmd, sg, use_sg, i) {
3549 addr64 = (u64) sg_dma_address(sg);
3550 len = sg_dma_len(sg);
3551 total_len += len;
3552 curr_sg->address = cpu_to_le64(addr64);
3553 curr_sg->length = cpu_to_le32(len);
3554 curr_sg->reserved[0] = 0;
3555 curr_sg->reserved[1] = 0;
3556 curr_sg->reserved[2] = 0;
3557 curr_sg->chain_indicator = 0;
3558 curr_sg++;
3559 }
3560
3561 switch (cmd->sc_data_direction) {
3562 case DMA_TO_DEVICE:
dd0e19f3
ST		 3563 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3564 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3565 break;
3566 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3567 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3568 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3569 break;
3570 case DMA_NONE:
dd0e19f3
ST		 3571 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3572 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3573 break;
3574 default:
3575 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3576 cmd->sc_data_direction);
3577 BUG();
3578 break;
3579 }
3580 } else {
dd0e19f3
ST		 3581 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3582 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3583 }
dd0e19f3
ST		 3584
3585 /* Set encryption parameters, if necessary */
3586 set_encrypt_ioaccel2(h, c, cp);
3587
2b08b3e9 3588 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3589 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3590 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3591
3592 /* fill in sg elements */
3593 cp->sg_count = (u8) use_sg;
3594
3595 cp->data_len = cpu_to_le32(total_len);
3596 cp->err_ptr = cpu_to_le64(c->busaddr +
3597 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3598 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3599
3600 enqueue_cmd_and_start_io(h, c);
3601 return 0;
3602}
3603
3604/*
3605 * Queue a command to the correct I/O accelerator path.
3606 */
3607static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3608 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3609 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 3610{
03383736
DB		 3611 /* Try to honor the device's queue depth */
3612 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
3613 phys_disk->queue_depth) {
3614 atomic_dec(&phys_disk->ioaccel_cmds_out);
3615 return IO_ACCEL_INELIGIBLE;
3616 }
c349775e
ST		 3617 if (h->transMethod & CFGTBL_Trans_io_accel1)
3618 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 3619 cdb, cdb_len, scsi3addr,
3620 phys_disk);
c349775e
ST		 3621 else
3622 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 3623 cdb, cdb_len, scsi3addr,
3624 phys_disk);
c349775e
ST		 3625}
3626
6b80b18f
ST		 3627static void raid_map_helper(struct raid_map_data *map,
3628 int offload_to_mirror, u32 *map_index, u32 *current_group)
3629{
3630 if (offload_to_mirror == 0) {
3631 /* use physical disk in the first mirrored group. */
2b08b3e9 3632 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3633 return;
3634 }
3635 do {
3636 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 3637 *current_group = *map_index /
3638 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3639 if (offload_to_mirror == *current_group)
3640 continue;
2b08b3e9 3641 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 3642 /* select map index from next group */
2b08b3e9 3643 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3644 (*current_group)++;
3645 } else {
3646 /* select map index from first group */
2b08b3e9 3647 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 3648 *current_group = 0;
3649 }
3650 } while (offload_to_mirror != *current_group);
3651}
3652
283b4a9b
SC		 3653/*
3654 * Attempt to perform offload RAID mapping for a logical volume I/O.
3655 */
3656static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3657 struct CommandList *c)
3658{
3659 struct scsi_cmnd *cmd = c->scsi_cmd;
3660 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3661 struct raid_map_data *map = &dev->raid_map;
3662 struct raid_map_disk_data *dd = &map->data[0];
3663 int is_write = 0;
3664 u32 map_index;
3665 u64 first_block, last_block;
3666 u32 block_cnt;
3667 u32 blocks_per_row;
3668 u64 first_row, last_row;
3669 u32 first_row_offset, last_row_offset;
3670 u32 first_column, last_column;
6b80b18f
ST		 3671 u64 r0_first_row, r0_last_row;
3672 u32 r5or6_blocks_per_row;
3673 u64 r5or6_first_row, r5or6_last_row;
3674 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3675 u32 r5or6_first_column, r5or6_last_column;
3676 u32 total_disks_per_row;
3677 u32 stripesize;
3678 u32 first_group, last_group, current_group;
283b4a9b
SC		 3679 u32 map_row;
3680 u32 disk_handle;
3681 u64 disk_block;
3682 u32 disk_block_cnt;
3683 u8 cdb[16];
3684 u8 cdb_len;
2b08b3e9 3685 u16 strip_size;
283b4a9b
SC		 3686#if BITS_PER_LONG == 32
3687 u64 tmpdiv;
3688#endif
6b80b18f 3689 int offload_to_mirror;
283b4a9b
SC		 3690
3691 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3692
3693 /* check for valid opcode, get LBA and block count */
3694 switch (cmd->cmnd[0]) {
3695 case WRITE_6:
3696 is_write = 1;
3697 case READ_6:
3698 first_block =
3699 (((u64) cmd->cmnd[2]) << 8) |
3700 cmd->cmnd[3];
3701 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3702 if (block_cnt == 0)
3703 block_cnt = 256;
283b4a9b
SC		 3704 break;
3705 case WRITE_10:
3706 is_write = 1;
3707 case READ_10:
3708 first_block =
3709 (((u64) cmd->cmnd[2]) << 24) |
3710 (((u64) cmd->cmnd[3]) << 16) |
3711 (((u64) cmd->cmnd[4]) << 8) |
3712 cmd->cmnd[5];
3713 block_cnt =
3714 (((u32) cmd->cmnd[7]) << 8) |
3715 cmd->cmnd[8];
3716 break;
3717 case WRITE_12:
3718 is_write = 1;
3719 case READ_12:
3720 first_block =
3721 (((u64) cmd->cmnd[2]) << 24) |
3722 (((u64) cmd->cmnd[3]) << 16) |
3723 (((u64) cmd->cmnd[4]) << 8) |
3724 cmd->cmnd[5];
3725 block_cnt =
3726 (((u32) cmd->cmnd[6]) << 24) |
3727 (((u32) cmd->cmnd[7]) << 16) |
3728 (((u32) cmd->cmnd[8]) << 8) |
3729 cmd->cmnd[9];
3730 break;
3731 case WRITE_16:
3732 is_write = 1;
3733 case READ_16:
3734 first_block =
3735 (((u64) cmd->cmnd[2]) << 56) |
3736 (((u64) cmd->cmnd[3]) << 48) |
3737 (((u64) cmd->cmnd[4]) << 40) |
3738 (((u64) cmd->cmnd[5]) << 32) |
3739 (((u64) cmd->cmnd[6]) << 24) |
3740 (((u64) cmd->cmnd[7]) << 16) |
3741 (((u64) cmd->cmnd[8]) << 8) |
3742 cmd->cmnd[9];
3743 block_cnt =
3744 (((u32) cmd->cmnd[10]) << 24) |
3745 (((u32) cmd->cmnd[11]) << 16) |
3746 (((u32) cmd->cmnd[12]) << 8) |
3747 cmd->cmnd[13];
3748 break;
3749 default:
3750 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3751 }
283b4a9b
SC		 3752 last_block = first_block + block_cnt - 1;
3753
3754 /* check for write to non-RAID-0 */
3755 if (is_write && dev->raid_level != 0)
3756 return IO_ACCEL_INELIGIBLE;
3757
3758 /* check for invalid block or wraparound */
2b08b3e9
DB		 3759 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
3760 last_block < first_block)
283b4a9b
SC		 3761 return IO_ACCEL_INELIGIBLE;
3762
3763 /* calculate stripe information for the request */
2b08b3e9
DB		 3764 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
3765 le16_to_cpu(map->strip_size);
3766 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 3767#if BITS_PER_LONG == 32
3768 tmpdiv = first_block;
3769 (void) do_div(tmpdiv, blocks_per_row);
3770 first_row = tmpdiv;
3771 tmpdiv = last_block;
3772 (void) do_div(tmpdiv, blocks_per_row);
3773 last_row = tmpdiv;
3774 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3775 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3776 tmpdiv = first_row_offset;
2b08b3e9 3777 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3778 first_column = tmpdiv;
3779 tmpdiv = last_row_offset;
2b08b3e9 3780 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 3781 last_column = tmpdiv;
3782#else
3783 first_row = first_block / blocks_per_row;
3784 last_row = last_block / blocks_per_row;
3785 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3786 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 3787 first_column = first_row_offset / strip_size;
3788 last_column = last_row_offset / strip_size;
283b4a9b
SC		 3789#endif
3790
3791 /* if this isn't a single row/column then give to the controller */
3792 if ((first_row != last_row) || (first_column != last_column))
3793 return IO_ACCEL_INELIGIBLE;
3794
3795 /* proceeding with driver mapping */
2b08b3e9
DB		 3796 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
3797 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 3798 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3799 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3800 map_index = (map_row * total_disks_per_row) + first_column;
3801
3802 switch (dev->raid_level) {
3803 case HPSA_RAID_0:
3804 break; /* nothing special to do */
3805 case HPSA_RAID_1:
3806 /* Handles load balance across RAID 1 members.
3807 * (2-drive R1 and R10 with even # of drives.)
3808 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3809 */
2b08b3e9 3810 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 3811 if (dev->offload_to_mirror)
2b08b3e9 3812 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 3813 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3814 break;
3815 case HPSA_RAID_ADM:
3816 /* Handles N-way mirrors (R1-ADM)
3817 * and R10 with # of drives divisible by 3.)
3818 */
2b08b3e9 3819 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 3820
3821 offload_to_mirror = dev->offload_to_mirror;
3822 raid_map_helper(map, offload_to_mirror,
3823 &map_index, &current_group);
3824 /* set mirror group to use next time */
3825 offload_to_mirror =
2b08b3e9
DB		 3826 (offload_to_mirror >=
3827 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 3828 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 3829 dev->offload_to_mirror = offload_to_mirror;
3830 /* Avoid direct use of dev->offload_to_mirror within this
3831 * function since multiple threads might simultaneously
3832 * increment it beyond the range of dev->layout_map_count -1.
3833 */
3834 break;
3835 case HPSA_RAID_5:
3836 case HPSA_RAID_6:
2b08b3e9 3837 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 3838 break;
3839
3840 /* Verify first and last block are in same RAID group */
3841 r5or6_blocks_per_row =
2b08b3e9
DB		 3842 le16_to_cpu(map->strip_size) *
3843 le16_to_cpu(map->data_disks_per_row);
6b80b18f 3844 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 3845 stripesize = r5or6_blocks_per_row *
3846 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 3847#if BITS_PER_LONG == 32
3848 tmpdiv = first_block;
3849 first_group = do_div(tmpdiv, stripesize);
3850 tmpdiv = first_group;
3851 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3852 first_group = tmpdiv;
3853 tmpdiv = last_block;
3854 last_group = do_div(tmpdiv, stripesize);
3855 tmpdiv = last_group;
3856 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3857 last_group = tmpdiv;
3858#else
3859 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3860 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3861#endif
000ff7c2 3862 if (first_group != last_group)
6b80b18f
ST		 3863 return IO_ACCEL_INELIGIBLE;
3864
3865 /* Verify request is in a single row of RAID 5/6 */
3866#if BITS_PER_LONG == 32
3867 tmpdiv = first_block;
3868 (void) do_div(tmpdiv, stripesize);
3869 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3870 tmpdiv = last_block;
3871 (void) do_div(tmpdiv, stripesize);
3872 r5or6_last_row = r0_last_row = tmpdiv;
3873#else
3874 first_row = r5or6_first_row = r0_first_row =
3875 first_block / stripesize;
3876 r5or6_last_row = r0_last_row = last_block / stripesize;
3877#endif
3878 if (r5or6_first_row != r5or6_last_row)
3879 return IO_ACCEL_INELIGIBLE;
3880
3881
3882 /* Verify request is in a single column */
3883#if BITS_PER_LONG == 32
3884 tmpdiv = first_block;
3885 first_row_offset = do_div(tmpdiv, stripesize);
3886 tmpdiv = first_row_offset;
3887 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3888 r5or6_first_row_offset = first_row_offset;
3889 tmpdiv = last_block;
3890 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3891 tmpdiv = r5or6_last_row_offset;
3892 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3893 tmpdiv = r5or6_first_row_offset;
3894 (void) do_div(tmpdiv, map->strip_size);
3895 first_column = r5or6_first_column = tmpdiv;
3896 tmpdiv = r5or6_last_row_offset;
3897 (void) do_div(tmpdiv, map->strip_size);
3898 r5or6_last_column = tmpdiv;
3899#else
3900 first_row_offset = r5or6_first_row_offset =
3901 (u32)((first_block % stripesize) %
3902 r5or6_blocks_per_row);
3903
3904 r5or6_last_row_offset =
3905 (u32)((last_block % stripesize) %
3906 r5or6_blocks_per_row);
3907
3908 first_column = r5or6_first_column =
2b08b3e9 3909 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 3910 r5or6_last_column =
2b08b3e9 3911 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 3912#endif
3913 if (r5or6_first_column != r5or6_last_column)
3914 return IO_ACCEL_INELIGIBLE;
3915
3916 /* Request is eligible */
3917 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 3918 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 3919
3920 map_index = (first_group *
2b08b3e9 3921 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 3922 (map_row * total_disks_per_row) + first_column;
3923 break;
3924 default:
3925 return IO_ACCEL_INELIGIBLE;
283b4a9b 3926 }
6b80b18f 3927
03383736
DB		 3928 c->phys_disk = dev->phys_disk[map_index];
3929
283b4a9b 3930 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 3931 disk_block = le64_to_cpu(map->disk_starting_blk) +
3932 first_row * le16_to_cpu(map->strip_size) +
3933 (first_row_offset - first_column *
3934 le16_to_cpu(map->strip_size));
283b4a9b
SC		 3935 disk_block_cnt = block_cnt;
3936
3937 /* handle differing logical/physical block sizes */
3938 if (map->phys_blk_shift) {
3939 disk_block <<= map->phys_blk_shift;
3940 disk_block_cnt <<= map->phys_blk_shift;
3941 }
3942 BUG_ON(disk_block_cnt > 0xffff);
3943
3944 /* build the new CDB for the physical disk I/O */
3945 if (disk_block > 0xffffffff) {
3946 cdb[0] = is_write ? WRITE_16 : READ_16;
3947 cdb[1] = 0;
3948 cdb[2] = (u8) (disk_block >> 56);
3949 cdb[3] = (u8) (disk_block >> 48);
3950 cdb[4] = (u8) (disk_block >> 40);
3951 cdb[5] = (u8) (disk_block >> 32);
3952 cdb[6] = (u8) (disk_block >> 24);
3953 cdb[7] = (u8) (disk_block >> 16);
3954 cdb[8] = (u8) (disk_block >> 8);
3955 cdb[9] = (u8) (disk_block);
3956 cdb[10] = (u8) (disk_block_cnt >> 24);
3957 cdb[11] = (u8) (disk_block_cnt >> 16);
3958 cdb[12] = (u8) (disk_block_cnt >> 8);
3959 cdb[13] = (u8) (disk_block_cnt);
3960 cdb[14] = 0;
3961 cdb[15] = 0;
3962 cdb_len = 16;
3963 } else {
3964 cdb[0] = is_write ? WRITE_10 : READ_10;
3965 cdb[1] = 0;
3966 cdb[2] = (u8) (disk_block >> 24);
3967 cdb[3] = (u8) (disk_block >> 16);
3968 cdb[4] = (u8) (disk_block >> 8);
3969 cdb[5] = (u8) (disk_block);
3970 cdb[6] = 0;
3971 cdb[7] = (u8) (disk_block_cnt >> 8);
3972 cdb[8] = (u8) (disk_block_cnt);
3973 cdb[9] = 0;
3974 cdb_len = 10;
3975 }
3976 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 3977 dev->scsi3addr,
3978 dev->phys_disk[map_index]);
283b4a9b
SC		 3979}
3980
574f05d3
SC		 3981/* Submit commands down the "normal" RAID stack path */
3982static int hpsa_ciss_submit(struct ctlr_info *h,
3983 struct CommandList *c, struct scsi_cmnd *cmd,
3984 unsigned char scsi3addr[])
edd16368 3985{
edd16368 3986 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 3987 c->cmd_type = CMD_SCSI;
3988 c->scsi_cmd = cmd;
3989 c->Header.ReplyQueue = 0; /* unused in simple mode */
3990 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 3991 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 3992
3993 /* Fill in the request block... */
3994
3995 c->Request.Timeout = 0;
3996 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3997 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3998 c->Request.CDBLen = cmd->cmd_len;
3999 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4000 switch (cmd->sc_data_direction) {
4001 case DMA_TO_DEVICE:
a505b86f
SC		 4002 c->Request.type_attr_dir =
4003 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4004 break;
4005 case DMA_FROM_DEVICE:
a505b86f
SC		 4006 c->Request.type_attr_dir =
4007 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4008 break;
4009 case DMA_NONE:
a505b86f
SC		 4010 c->Request.type_attr_dir =
4011 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4012 break;
4013 case DMA_BIDIRECTIONAL:
4014 /* This can happen if a buggy application does a scsi passthru
4015 * and sets both inlen and outlen to non-zero. ( see
4016 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4017 */
4018
a505b86f
SC		 4019 c->Request.type_attr_dir =
4020 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4021 /* This is technically wrong, and hpsa controllers should
4022 * reject it with CMD_INVALID, which is the most correct
4023 * response, but non-fibre backends appear to let it
4024 * slide by, and give the same results as if this field
4025 * were set correctly. Either way is acceptable for
4026 * our purposes here.
4027 */
4028
4029 break;
4030
4031 default:
4032 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4033 cmd->sc_data_direction);
4034 BUG();
4035 break;
4036 }
4037
33a2ffce 4038 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4039 cmd_free(h, c);
4040 return SCSI_MLQUEUE_HOST_BUSY;
4041 }
4042 enqueue_cmd_and_start_io(h, c);
4043 /* the cmd'll come back via intr handler in complete_scsi_command() */
4044 return 0;
4045}
4046
080ef1cc
DB		 4047static void hpsa_command_resubmit_worker(struct work_struct *work)
4048{
4049 struct scsi_cmnd *cmd;
4050 struct hpsa_scsi_dev_t *dev;
4051 struct CommandList *c =
4052 container_of(work, struct CommandList, work);
4053
4054 cmd = c->scsi_cmd;
4055 dev = cmd->device->hostdata;
4056 if (!dev) {
4057 cmd->result = DID_NO_CONNECT << 16;
4058 cmd->scsi_done(cmd);
4059 return;
4060 }
4061 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4062 /*
4063 * If we get here, it means dma mapping failed. Try
4064 * again via scsi mid layer, which will then get
4065 * SCSI_MLQUEUE_HOST_BUSY.
4066 */
4067 cmd->result = DID_IMM_RETRY << 16;
4068 cmd->scsi_done(cmd);
4069 }
4070}
4071
574f05d3
SC		 4072/* Running in struct Scsi_Host->host_lock less mode */
4073static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4074{
4075 struct ctlr_info *h;
4076 struct hpsa_scsi_dev_t *dev;
4077 unsigned char scsi3addr[8];
4078 struct CommandList *c;
4079 int rc = 0;
4080
4081 /* Get the ptr to our adapter structure out of cmd->host. */
4082 h = sdev_to_hba(cmd->device);
4083 dev = cmd->device->hostdata;
4084 if (!dev) {
4085 cmd->result = DID_NO_CONNECT << 16;
4086 cmd->scsi_done(cmd);
4087 return 0;
4088 }
4089 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4090
4091 if (unlikely(lockup_detected(h))) {
4092 cmd->result = DID_ERROR << 16;
4093 cmd->scsi_done(cmd);
4094 return 0;
4095 }
4096 c = cmd_alloc(h);
4097 if (c == NULL) { /* trouble... */
4098 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4099 return SCSI_MLQUEUE_HOST_BUSY;
4100 }
4101
4102 /* Call alternate submit routine for I/O accelerated commands.
4103 * Retries always go down the normal I/O path.
4104 */
4105 if (likely(cmd->retries == 0 &&
4106 cmd->request->cmd_type == REQ_TYPE_FS &&
4107 h->acciopath_status)) {
4108
4109 cmd->host_scribble = (unsigned char *) c;
4110 c->cmd_type = CMD_SCSI;
4111 c->scsi_cmd = cmd;
4112
4113 if (dev->offload_enabled) {
4114 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4115 if (rc == 0)
4116 return 0; /* Sent on ioaccel path */
4117 if (rc < 0) { /* scsi_dma_map failed. */
4118 cmd_free(h, c);
4119 return SCSI_MLQUEUE_HOST_BUSY;
4120 }
4121 } else if (dev->ioaccel_handle) {
4122 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4123 if (rc == 0)
4124 return 0; /* Sent on direct map path */
4125 if (rc < 0) { /* scsi_dma_map failed. */
4126 cmd_free(h, c);
4127 return SCSI_MLQUEUE_HOST_BUSY;
4128 }
4129 }
4130 }
4131 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4132}
4133
5f389360
SC		 4134static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4135{
4136 unsigned long flags;
4137
4138 /*
4139 * Don't let rescans be initiated on a controller known
4140 * to be locked up. If the controller locks up *during*
4141 * a rescan, that thread is probably hosed, but at least
4142 * we can prevent new rescan threads from piling up on a
4143 * locked up controller.
4144 */
094963da 4145 if (unlikely(lockup_detected(h))) {
5f389360
SC		 4146 spin_lock_irqsave(&h->scan_lock, flags);
4147 h->scan_finished = 1;
4148 wake_up_all(&h->scan_wait_queue);
4149 spin_unlock_irqrestore(&h->scan_lock, flags);
4150 return 1;
4151 }
5f389360
SC		 4152 return 0;
4153}
4154
a08a8471
SC		 4155static void hpsa_scan_start(struct Scsi_Host *sh)
4156{
4157 struct ctlr_info *h = shost_to_hba(sh);
4158 unsigned long flags;
4159
5f389360
SC		 4160 if (do_not_scan_if_controller_locked_up(h))
4161 return;
4162
a08a8471
SC		 4163 /* wait until any scan already in progress is finished. */
4164 while (1) {
4165 spin_lock_irqsave(&h->scan_lock, flags);
4166 if (h->scan_finished)
4167 break;
4168 spin_unlock_irqrestore(&h->scan_lock, flags);
4169 wait_event(h->scan_wait_queue, h->scan_finished);
4170 /* Note: We don't need to worry about a race between this
4171 * thread and driver unload because the midlayer will
4172 * have incremented the reference count, so unload won't
4173 * happen if we're in here.
4174 */
4175 }
4176 h->scan_finished = 0; /* mark scan as in progress */
4177 spin_unlock_irqrestore(&h->scan_lock, flags);
4178
5f389360
SC		 4179 if (do_not_scan_if_controller_locked_up(h))
4180 return;
4181
a08a8471
SC		 4182 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4183
4184 spin_lock_irqsave(&h->scan_lock, flags);
4185 h->scan_finished = 1; /* mark scan as finished. */
4186 wake_up_all(&h->scan_wait_queue);
4187 spin_unlock_irqrestore(&h->scan_lock, flags);
4188}
4189
7c0a0229
DB		 4190static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4191{
03383736
DB		 4192 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4193
4194 if (!logical_drive)
4195 return -ENODEV;
7c0a0229
DB		 4196
4197 if (qdepth < 1)
4198 qdepth = 1;
03383736
DB		 4199 else if (qdepth > logical_drive->queue_depth)
4200 qdepth = logical_drive->queue_depth;
4201
4202 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4203}
4204
a08a8471
SC		 4205static int hpsa_scan_finished(struct Scsi_Host *sh,
4206 unsigned long elapsed_time)
4207{
4208 struct ctlr_info *h = shost_to_hba(sh);
4209 unsigned long flags;
4210 int finished;
4211
4212 spin_lock_irqsave(&h->scan_lock, flags);
4213 finished = h->scan_finished;
4214 spin_unlock_irqrestore(&h->scan_lock, flags);
4215 return finished;
4216}
4217
edd16368
SC		 4218static void hpsa_unregister_scsi(struct ctlr_info *h)
4219{
4220 /* we are being forcibly unloaded, and may not refuse. */
4221 scsi_remove_host(h->scsi_host);
4222 scsi_host_put(h->scsi_host);
4223 h->scsi_host = NULL;
4224}
4225
4226static int hpsa_register_scsi(struct ctlr_info *h)
4227{
b705690d
SC		 4228 struct Scsi_Host *sh;
4229 int error;
edd16368 4230
b705690d
SC		 4231 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4232 if (sh == NULL)
4233 goto fail;
4234
4235 sh->io_port = 0;
4236 sh->n_io_port = 0;
4237 sh->this_id = -1;
4238 sh->max_channel = 3;
4239 sh->max_cmd_len = MAX_COMMAND_SIZE;
4240 sh->max_lun = HPSA_MAX_LUN;
4241 sh->max_id = HPSA_MAX_LUN;
d54c5c24
SC		 4242 sh->can_queue = h->nr_cmds -
4243 HPSA_CMDS_RESERVED_FOR_ABORTS -
4244 HPSA_CMDS_RESERVED_FOR_DRIVER -
4245 HPSA_MAX_CONCURRENT_PASSTHRUS;
03383736 4246 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4247 sh->sg_tablesize = h->maxsgentries;
4248 h->scsi_host = sh;
4249 sh->hostdata[0] = (unsigned long) h;
4250 sh->irq = h->intr[h->intr_mode];
4251 sh->unique_id = sh->irq;
4252 error = scsi_add_host(sh, &h->pdev->dev);
4253 if (error)
4254 goto fail_host_put;
4255 scsi_scan_host(sh);
4256 return 0;
4257
4258 fail_host_put:
4259 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4260 " failed for controller %d\n", __func__, h->ctlr);
4261 scsi_host_put(sh);
4262 return error;
4263 fail:
4264 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4265 " failed for controller %d\n", __func__, h->ctlr);
4266 return -ENOMEM;
edd16368
SC		 4267}
4268
4269static int wait_for_device_to_become_ready(struct ctlr_info *h,
4270 unsigned char lunaddr[])
4271{
8919358e 4272 int rc;
edd16368
SC		 4273 int count = 0;
4274 int waittime = 1; /* seconds */
4275 struct CommandList *c;
4276
45fcb86e 4277 c = cmd_alloc(h);
edd16368
SC		 4278 if (!c) {
4279 dev_warn(&h->pdev->dev, "out of memory in "
4280 "wait_for_device_to_become_ready.\n");
4281 return IO_ERROR;
4282 }
4283
4284 /* Send test unit ready until device ready, or give up. */
4285 while (count < HPSA_TUR_RETRY_LIMIT) {
4286
4287 /* Wait for a bit. do this first, because if we send
4288 * the TUR right away, the reset will just abort it.
4289 */
4290 msleep(1000 * waittime);
4291 count++;
8919358e 4292 rc = 0; /* Device ready. */
edd16368
SC		 4293
4294 /* Increase wait time with each try, up to a point. */
4295 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4296 waittime = waittime * 2;
4297
a2dac136
SC		 4298 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4299 (void) fill_cmd(c, TEST_UNIT_READY, h,
4300 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4301 hpsa_scsi_do_simple_cmd_core(h, c);
4302 /* no unmap needed here because no data xfer. */
4303
4304 if (c->err_info->CommandStatus == CMD_SUCCESS)
4305 break;
4306
4307 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4308 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4309 (c->err_info->SenseInfo[2] == NO_SENSE ||
4310 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4311 break;
4312
4313 dev_warn(&h->pdev->dev, "waiting %d secs "
4314 "for device to become ready.\n", waittime);
4315 rc = 1; /* device not ready. */
4316 }
4317
4318 if (rc)
4319 dev_warn(&h->pdev->dev, "giving up on device.\n");
4320 else
4321 dev_warn(&h->pdev->dev, "device is ready.\n");
4322
45fcb86e 4323 cmd_free(h, c);
edd16368
SC		 4324 return rc;
4325}
4326
4327/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4328 * complaining. Doing a host- or bus-reset can't do anything good here.
4329 */
4330static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4331{
4332 int rc;
4333 struct ctlr_info *h;
4334 struct hpsa_scsi_dev_t *dev;
4335
4336 /* find the controller to which the command to be aborted was sent */
4337 h = sdev_to_hba(scsicmd->device);
4338 if (h == NULL) /* paranoia */
4339 return FAILED;
edd16368
SC		 4340 dev = scsicmd->device->hostdata;
4341 if (!dev) {
4342 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4343 "device lookup failed.\n");
4344 return FAILED;
4345 }
d416b0c7
SC		 4346 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4347 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4348 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4349 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4350 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4351 return SUCCESS;
4352
4353 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4354 return FAILED;
4355}
4356
6cba3f19
SC		 4357static void swizzle_abort_tag(u8 *tag)
4358{
4359 u8 original_tag[8];
4360
4361 memcpy(original_tag, tag, 8);
4362 tag[0] = original_tag[3];
4363 tag[1] = original_tag[2];
4364 tag[2] = original_tag[1];
4365 tag[3] = original_tag[0];
4366 tag[4] = original_tag[7];
4367 tag[5] = original_tag[6];
4368 tag[6] = original_tag[5];
4369 tag[7] = original_tag[4];
4370}
4371
17eb87d2 4372static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4373 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4374{
2b08b3e9 4375 u64 tag;
17eb87d2
ST		 4376 if (c->cmd_type == CMD_IOACCEL1) {
4377 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4378 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4379 tag = le64_to_cpu(cm1->tag);
4380 *tagupper = cpu_to_le32(tag >> 32);
4381 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4382 return;
4383 }
4384 if (c->cmd_type == CMD_IOACCEL2) {
4385 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4386 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4387 /* upper tag not used in ioaccel2 mode */
4388 memset(tagupper, 0, sizeof(*tagupper));
4389 *taglower = cm2->Tag;
54b6e9e9 4390 return;
17eb87d2 4391 }
2b08b3e9
DB		 4392 tag = le64_to_cpu(c->Header.tag);
4393 *tagupper = cpu_to_le32(tag >> 32);
4394 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4395}
4396
75167d2c 4397static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4398 struct CommandList *abort, int swizzle)
75167d2c
SC		 4399{
4400 int rc = IO_OK;
4401 struct CommandList *c;
4402 struct ErrorInfo *ei;
2b08b3e9 4403 __le32 tagupper, taglower;
75167d2c 4404
45fcb86e 4405 c = cmd_alloc(h);
75167d2c 4406 if (c == NULL) { /* trouble... */
45fcb86e 4407 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4408 return -ENOMEM;
4409 }
4410
a2dac136
SC		 4411 /* fill_cmd can't fail here, no buffer to map */
4412 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4413 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4414 if (swizzle)
4415 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4416 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4417 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4418 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4419 __func__, tagupper, taglower);
75167d2c
SC		 4420 /* no unmap needed here because no data xfer. */
4421
4422 ei = c->err_info;
4423 switch (ei->CommandStatus) {
4424 case CMD_SUCCESS:
4425 break;
4426 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4427 rc = -1;
4428 break;
4429 default:
4430 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4431 __func__, tagupper, taglower);
d1e8beac 4432 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4433 rc = -1;
4434 break;
4435 }
45fcb86e 4436 cmd_free(h, c);
dd0e19f3
ST		 4437 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4438 __func__, tagupper, taglower);
75167d2c
SC		 4439 return rc;
4440}
4441
54b6e9e9
ST		 4442/* ioaccel2 path firmware cannot handle abort task requests.
4443 * Change abort requests to physical target reset, and send to the
4444 * address of the physical disk used for the ioaccel 2 command.
4445 * Return 0 on success (IO_OK)
4446 * -1 on failure
4447 */
4448
4449static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4450 unsigned char *scsi3addr, struct CommandList *abort)
4451{
4452 int rc = IO_OK;
4453 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4454 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4455 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4456 unsigned char *psa = &phys_scsi3addr[0];
4457
4458 /* Get a pointer to the hpsa logical device. */
4459 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4460 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4461 if (dev == NULL) {
4462 dev_warn(&h->pdev->dev,
4463 "Cannot abort: no device pointer for command.\n");
4464 return -1; /* not abortable */
4465 }
4466
2ba8bfc8
SC		 4467 if (h->raid_offload_debug > 0)
4468 dev_info(&h->pdev->dev,
4469 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4470 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4471 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4472 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4473
54b6e9e9
ST		 4474 if (!dev->offload_enabled) {
4475 dev_warn(&h->pdev->dev,
4476 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4477 return -1; /* not abortable */
4478 }
4479
4480 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4481 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4482 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4483 return -1; /* not abortable */
4484 }
4485
4486 /* send the reset */
2ba8bfc8
SC		 4487 if (h->raid_offload_debug > 0)
4488 dev_info(&h->pdev->dev,
4489 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4490 psa[0], psa[1], psa[2], psa[3],
4491 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4492 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4493 if (rc != 0) {
4494 dev_warn(&h->pdev->dev,
4495 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4496 psa[0], psa[1], psa[2], psa[3],
4497 psa[4], psa[5], psa[6], psa[7]);
4498 return rc; /* failed to reset */
4499 }
4500
4501 /* wait for device to recover */
4502 if (wait_for_device_to_become_ready(h, psa) != 0) {
4503 dev_warn(&h->pdev->dev,
4504 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4505 psa[0], psa[1], psa[2], psa[3],
4506 psa[4], psa[5], psa[6], psa[7]);
4507 return -1; /* failed to recover */
4508 }
4509
4510 /* device recovered */
4511 dev_info(&h->pdev->dev,
4512 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4513 psa[0], psa[1], psa[2], psa[3],
4514 psa[4], psa[5], psa[6], psa[7]);
4515
4516 return rc; /* success */
4517}
4518
6cba3f19
SC		 4519/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4520 * tell which kind we're dealing with, so we send the abort both ways. There
4521 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4522 * way we construct our tags but we check anyway in case the assumptions which
4523 * make this true someday become false.
4524 */
4525static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4526 unsigned char *scsi3addr, struct CommandList *abort)
4527{
54b6e9e9
ST		 4528 /* ioccelerator mode 2 commands should be aborted via the
4529 * accelerated path, since RAID path is unaware of these commands,
4530 * but underlying firmware can't handle abort TMF.
4531 * Change abort to physical device reset.
4532 */
4533 if (abort->cmd_type == CMD_IOACCEL2)
4534 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4535
f2405db8
DB		 4536 return hpsa_send_abort(h, scsi3addr, abort, 0) &&
4537 hpsa_send_abort(h, scsi3addr, abort, 1);
6cba3f19
SC		 4538}
4539
75167d2c
SC		 4540/* Send an abort for the specified command.
4541 * If the device and controller support it,
4542 * send a task abort request.
4543 */
4544static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4545{
4546
4547 int i, rc;
4548 struct ctlr_info *h;
4549 struct hpsa_scsi_dev_t *dev;
4550 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 4551 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4552 char msg[256]; /* For debug messaging. */
4553 int ml = 0;
2b08b3e9 4554 __le32 tagupper, taglower;
281a7fd0 4555 int refcount;
75167d2c
SC		 4556
4557 /* Find the controller of the command to be aborted */
4558 h = sdev_to_hba(sc->device);
4559 if (WARN(h == NULL,
4560 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4561 return FAILED;
4562
4563 /* Check that controller supports some kind of task abort */
4564 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4565 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4566 return FAILED;
4567
4568 memset(msg, 0, sizeof(msg));
9cb78c16 4569 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ",
75167d2c
SC		 4570 h->scsi_host->host_no, sc->device->channel,
4571 sc->device->id, sc->device->lun);
4572
4573 /* Find the device of the command to be aborted */
4574 dev = sc->device->hostdata;
4575 if (!dev) {
4576 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4577 msg);
4578 return FAILED;
4579 }
4580
4581 /* Get SCSI command to be aborted */
4582 abort = (struct CommandList *) sc->host_scribble;
4583 if (abort == NULL) {
281a7fd0
WS		 4584 /* This can happen if the command already completed. */
4585 return SUCCESS;
4586 }
4587 refcount = atomic_inc_return(&abort->refcount);
4588 if (refcount == 1) { /* Command is done already. */
4589 cmd_free(h, abort);
4590 return SUCCESS;
75167d2c 4591 }
17eb87d2
ST		 4592 hpsa_get_tag(h, abort, &taglower, &tagupper);
4593 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4594 as = (struct scsi_cmnd *) abort->scsi_cmd;
4595 if (as != NULL)
4596 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4597 as->cmnd[0], as->serial_number);
4598 dev_dbg(&h->pdev->dev, "%s\n", msg);
4599 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4600 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
75167d2c
SC		 4601 /*
4602 * Command is in flight, or possibly already completed
4603 * by the firmware (but not to the scsi mid layer) but we can't
4604 * distinguish which. Send the abort down.
4605 */
6cba3f19 4606 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4607 if (rc != 0) {
4608 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4609 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4610 h->scsi_host->host_no,
4611 dev->bus, dev->target, dev->lun);
281a7fd0 4612 cmd_free(h, abort);
75167d2c
SC		 4613 return FAILED;
4614 }
4615 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4616
4617 /* If the abort(s) above completed and actually aborted the
4618 * command, then the command to be aborted should already be
4619 * completed. If not, wait around a bit more to see if they
4620 * manage to complete normally.
4621 */
4622#define ABORT_COMPLETE_WAIT_SECS 30
4623 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 4624 refcount = atomic_read(&abort->refcount);
4625 if (refcount < 2) {
4626 cmd_free(h, abort);
75167d2c 4627 return SUCCESS;
281a7fd0
WS		 4628 } else {
4629 msleep(100);
4630 }
75167d2c
SC		 4631 }
4632 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4633 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 4634 cmd_free(h, abort);
75167d2c
SC		 4635 return FAILED;
4636}
4637
edd16368
SC		 4638/*
4639 * For operations that cannot sleep, a command block is allocated at init,
4640 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4641 * which ones are free or in use. Lock must be held when calling this.
4642 * cmd_free() is the complement.
4643 */
281a7fd0 4644
edd16368
SC		 4645static struct CommandList *cmd_alloc(struct ctlr_info *h)
4646{
4647 struct CommandList *c;
4648 int i;
4649 union u64bit temp64;
4650 dma_addr_t cmd_dma_handle, err_dma_handle;
281a7fd0
WS		 4651 int refcount;
4652 unsigned long offset = 0;
4c413128
SC		 4653
4654 /* There is some *extremely* small but non-zero chance that that
4655 * multiple threads could get in here, and one thread could
4656 * be scanning through the list of bits looking for a free
4657 * one, but the free ones are always behind him, and other
4658 * threads sneak in behind him and eat them before he can
4659 * get to them, so that while there is always a free one, a
4660 * very unlucky thread might be starved anyway, never able to
4661 * beat the other threads. In reality, this happens so
4662 * infrequently as to be indistinguishable from never.
4663 */
edd16368 4664
281a7fd0
WS		 4665 for (;;) {
4666 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
4667 if (unlikely(i == h->nr_cmds)) {
4668 offset = 0;
4669 continue;
4670 }
4671 c = h->cmd_pool + i;
4672 refcount = atomic_inc_return(&c->refcount);
4673 if (unlikely(refcount > 1)) {
4674 cmd_free(h, c); /* already in use */
4675 offset = (i + 1) % h->nr_cmds;
4676 continue;
4677 }
4678 set_bit(i & (BITS_PER_LONG - 1),
4679 h->cmd_pool_bits + (i / BITS_PER_LONG));
4680 break; /* it's ours now. */
4681 }
4682
4683 /* Zero out all of commandlist except the last field, refcount */
4684 memset(c, 0, offsetof(struct CommandList, refcount));
4685 c->Header.tag = cpu_to_le64((u64) (i << DIRECT_LOOKUP_SHIFT));
f2405db8 4686 cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(*c);
edd16368
SC		 4687 c->err_info = h->errinfo_pool + i;
4688 memset(c->err_info, 0, sizeof(*c->err_info));
4689 err_dma_handle = h->errinfo_pool_dhandle
4690 + i * sizeof(*c->err_info);
edd16368
SC		 4691
4692 c->cmdindex = i;
4693
01a02ffc
SC		 4694 c->busaddr = (u32) cmd_dma_handle;
4695 temp64.val = (u64) err_dma_handle;
281a7fd0
WS		 4696 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4697 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
edd16368
SC		 4698
4699 c->h = h;
4700 return c;
4701}
4702
edd16368
SC		 4703static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4704{
281a7fd0
WS		 4705 if (atomic_dec_and_test(&c->refcount)) {
4706 int i;
edd16368 4707
281a7fd0
WS		 4708 i = c - h->cmd_pool;
4709 clear_bit(i & (BITS_PER_LONG - 1),
4710 h->cmd_pool_bits + (i / BITS_PER_LONG));
4711 }
edd16368
SC		 4712}
4713
edd16368
SC		 4714#ifdef CONFIG_COMPAT
4715
42a91641
DB		 4716static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4717 void __user *arg)
edd16368
SC		 4718{
4719 IOCTL32_Command_struct __user *arg32 =
4720 (IOCTL32_Command_struct __user *) arg;
4721 IOCTL_Command_struct arg64;
4722 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4723 int err;
4724 u32 cp;
4725
938abd84 4726 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4727 err = 0;
4728 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4729 sizeof(arg64.LUN_info));
4730 err |= copy_from_user(&arg64.Request, &arg32->Request,
4731 sizeof(arg64.Request));
4732 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4733 sizeof(arg64.error_info));
4734 err |= get_user(arg64.buf_size, &arg32->buf_size);
4735 err |= get_user(cp, &arg32->buf);
4736 arg64.buf = compat_ptr(cp);
4737 err |= copy_to_user(p, &arg64, sizeof(arg64));
4738
4739 if (err)
4740 return -EFAULT;
4741
42a91641 4742 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 4743 if (err)
4744 return err;
4745 err |= copy_in_user(&arg32->error_info, &p->error_info,
4746 sizeof(arg32->error_info));
4747 if (err)
4748 return -EFAULT;
4749 return err;
4750}
4751
4752static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 4753 int cmd, void __user *arg)
edd16368
SC		 4754{
4755 BIG_IOCTL32_Command_struct __user *arg32 =
4756 (BIG_IOCTL32_Command_struct __user *) arg;
4757 BIG_IOCTL_Command_struct arg64;
4758 BIG_IOCTL_Command_struct __user *p =
4759 compat_alloc_user_space(sizeof(arg64));
4760 int err;
4761 u32 cp;
4762
938abd84 4763 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4764 err = 0;
4765 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4766 sizeof(arg64.LUN_info));
4767 err |= copy_from_user(&arg64.Request, &arg32->Request,
4768 sizeof(arg64.Request));
4769 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4770 sizeof(arg64.error_info));
4771 err |= get_user(arg64.buf_size, &arg32->buf_size);
4772 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4773 err |= get_user(cp, &arg32->buf);
4774 arg64.buf = compat_ptr(cp);
4775 err |= copy_to_user(p, &arg64, sizeof(arg64));
4776
4777 if (err)
4778 return -EFAULT;
4779
42a91641 4780 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 4781 if (err)
4782 return err;
4783 err |= copy_in_user(&arg32->error_info, &p->error_info,
4784 sizeof(arg32->error_info));
4785 if (err)
4786 return -EFAULT;
4787 return err;
4788}
71fe75a7 4789
42a91641 4790static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 4791{
4792 switch (cmd) {
4793 case CCISS_GETPCIINFO:
4794 case CCISS_GETINTINFO:
4795 case CCISS_SETINTINFO:
4796 case CCISS_GETNODENAME:
4797 case CCISS_SETNODENAME:
4798 case CCISS_GETHEARTBEAT:
4799 case CCISS_GETBUSTYPES:
4800 case CCISS_GETFIRMVER:
4801 case CCISS_GETDRIVVER:
4802 case CCISS_REVALIDVOLS:
4803 case CCISS_DEREGDISK:
4804 case CCISS_REGNEWDISK:
4805 case CCISS_REGNEWD:
4806 case CCISS_RESCANDISK:
4807 case CCISS_GETLUNINFO:
4808 return hpsa_ioctl(dev, cmd, arg);
4809
4810 case CCISS_PASSTHRU32:
4811 return hpsa_ioctl32_passthru(dev, cmd, arg);
4812 case CCISS_BIG_PASSTHRU32:
4813 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4814
4815 default:
4816 return -ENOIOCTLCMD;
4817 }
4818}
edd16368
SC		 4819#endif
4820
4821static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4822{
4823 struct hpsa_pci_info pciinfo;
4824
4825 if (!argp)
4826 return -EINVAL;
4827 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4828 pciinfo.bus = h->pdev->bus->number;
4829 pciinfo.dev_fn = h->pdev->devfn;
4830 pciinfo.board_id = h->board_id;
4831 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4832 return -EFAULT;
4833 return 0;
4834}
4835
4836static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4837{
4838 DriverVer_type DriverVer;
4839 unsigned char vmaj, vmin, vsubmin;
4840 int rc;
4841
4842 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4843 &vmaj, &vmin, &vsubmin);
4844 if (rc != 3) {
4845 dev_info(&h->pdev->dev, "driver version string '%s' "
4846 "unrecognized.", HPSA_DRIVER_VERSION);
4847 vmaj = 0;
4848 vmin = 0;
4849 vsubmin = 0;
4850 }
4851 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4852 if (!argp)
4853 return -EINVAL;
4854 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4855 return -EFAULT;
4856 return 0;
4857}
4858
4859static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4860{
4861 IOCTL_Command_struct iocommand;
4862 struct CommandList *c;
4863 char *buff = NULL;
50a0decf 4864 u64 temp64;
c1f63c8f 4865 int rc = 0;
edd16368
SC		 4866
4867 if (!argp)
4868 return -EINVAL;
4869 if (!capable(CAP_SYS_RAWIO))
4870 return -EPERM;
4871 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4872 return -EFAULT;
4873 if ((iocommand.buf_size < 1) &&
4874 (iocommand.Request.Type.Direction != XFER_NONE)) {
4875 return -EINVAL;
4876 }
4877 if (iocommand.buf_size > 0) {
4878 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4879 if (buff == NULL)
4880 return -EFAULT;
9233fb10 4881 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4882 /* Copy the data into the buffer we created */
4883 if (copy_from_user(buff, iocommand.buf,
4884 iocommand.buf_size)) {
c1f63c8f
SC		 4885 rc = -EFAULT;
4886 goto out_kfree;
b03a7771
SC		 4887 }
4888 } else {
4889 memset(buff, 0, iocommand.buf_size);
edd16368 4890 }
b03a7771 4891 }
45fcb86e 4892 c = cmd_alloc(h);
edd16368 4893 if (c == NULL) {
c1f63c8f
SC		 4894 rc = -ENOMEM;
4895 goto out_kfree;
edd16368
SC		 4896 }
4897 /* Fill in the command type */
4898 c->cmd_type = CMD_IOCTL_PEND;
4899 /* Fill in Command Header */
4900 c->Header.ReplyQueue = 0; /* unused in simple mode */
4901 if (iocommand.buf_size > 0) { /* buffer to fill */
4902 c->Header.SGList = 1;
50a0decf 4903 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4904 } else { /* no buffers to fill */
4905 c->Header.SGList = 0;
50a0decf 4906 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 4907 }
4908 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 4909
4910 /* Fill in Request block */
4911 memcpy(&c->Request, &iocommand.Request,
4912 sizeof(c->Request));
4913
4914 /* Fill in the scatter gather information */
4915 if (iocommand.buf_size > 0) {
50a0decf 4916 temp64 = pci_map_single(h->pdev, buff,
edd16368 4917 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4918 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
4919 c->SG[0].Addr = cpu_to_le64(0);
4920 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 4921 rc = -ENOMEM;
4922 goto out;
4923 }
50a0decf
SC		 4924 c->SG[0].Addr = cpu_to_le64(temp64);
4925 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
4926 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 4927 }
a0c12413 4928 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4929 if (iocommand.buf_size > 0)
4930 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4931 check_ioctl_unit_attention(h, c);
4932
4933 /* Copy the error information out */
4934 memcpy(&iocommand.error_info, c->err_info,
4935 sizeof(iocommand.error_info));
4936 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4937 rc = -EFAULT;
4938 goto out;
edd16368 4939 }
9233fb10 4940 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 4941 iocommand.buf_size > 0) {
edd16368
SC		 4942 /* Copy the data out of the buffer we created */
4943 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4944 rc = -EFAULT;
4945 goto out;
edd16368
SC		 4946 }
4947 }
c1f63c8f 4948out:
45fcb86e 4949 cmd_free(h, c);
c1f63c8f
SC		 4950out_kfree:
4951 kfree(buff);
4952 return rc;
edd16368
SC		 4953}
4954
4955static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4956{
4957 BIG_IOCTL_Command_struct *ioc;
4958 struct CommandList *c;
4959 unsigned char **buff = NULL;
4960 int *buff_size = NULL;
50a0decf 4961 u64 temp64;
edd16368
SC		 4962 BYTE sg_used = 0;
4963 int status = 0;
01a02ffc
SC		 4964 u32 left;
4965 u32 sz;
edd16368
SC		 4966 BYTE __user *data_ptr;
4967
4968 if (!argp)
4969 return -EINVAL;
4970 if (!capable(CAP_SYS_RAWIO))
4971 return -EPERM;
4972 ioc = (BIG_IOCTL_Command_struct *)
4973 kmalloc(sizeof(*ioc), GFP_KERNEL);
4974 if (!ioc) {
4975 status = -ENOMEM;
4976 goto cleanup1;
4977 }
4978 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4979 status = -EFAULT;
4980 goto cleanup1;
4981 }
4982 if ((ioc->buf_size < 1) &&
4983 (ioc->Request.Type.Direction != XFER_NONE)) {
4984 status = -EINVAL;
4985 goto cleanup1;
4986 }
4987 /* Check kmalloc limits using all SGs */
4988 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4989 status = -EINVAL;
4990 goto cleanup1;
4991 }
d66ae08b 4992 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4993 status = -EINVAL;
4994 goto cleanup1;
4995 }
d66ae08b 4996 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4997 if (!buff) {
4998 status = -ENOMEM;
4999 goto cleanup1;
5000 }
d66ae08b 5001 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5002 if (!buff_size) {
5003 status = -ENOMEM;
5004 goto cleanup1;
5005 }
5006 left = ioc->buf_size;
5007 data_ptr = ioc->buf;
5008 while (left) {
5009 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5010 buff_size[sg_used] = sz;
5011 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5012 if (buff[sg_used] == NULL) {
5013 status = -ENOMEM;
5014 goto cleanup1;
5015 }
9233fb10 5016 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5017 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5018 status = -EFAULT;
edd16368
SC		 5019 goto cleanup1;
5020 }
5021 } else
5022 memset(buff[sg_used], 0, sz);
5023 left -= sz;
5024 data_ptr += sz;
5025 sg_used++;
5026 }
45fcb86e 5027 c = cmd_alloc(h);
edd16368
SC		 5028 if (c == NULL) {
5029 status = -ENOMEM;
5030 goto cleanup1;
5031 }
5032 c->cmd_type = CMD_IOCTL_PEND;
5033 c->Header.ReplyQueue = 0;
50a0decf
SC		 5034 c->Header.SGList = (u8) sg_used;
5035 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5036 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5037 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5038 if (ioc->buf_size > 0) {
5039 int i;
5040 for (i = 0; i < sg_used; i++) {
50a0decf 5041 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5042 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5043 if (dma_mapping_error(&h->pdev->dev,
5044 (dma_addr_t) temp64)) {
5045 c->SG[i].Addr = cpu_to_le64(0);
5046 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5047 hpsa_pci_unmap(h->pdev, c, i,
5048 PCI_DMA_BIDIRECTIONAL);
5049 status = -ENOMEM;
e2d4a1f6 5050 goto cleanup0;
bcc48ffa 5051 }
50a0decf
SC		 5052 c->SG[i].Addr = cpu_to_le64(temp64);
5053 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5054 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5055 }
50a0decf 5056 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5057 }
a0c12413 5058 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5059 if (sg_used)
5060 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5061 check_ioctl_unit_attention(h, c);
5062 /* Copy the error information out */
5063 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5064 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5065 status = -EFAULT;
e2d4a1f6 5066 goto cleanup0;
edd16368 5067 }
9233fb10 5068 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5069 int i;
5070
edd16368
SC		 5071 /* Copy the data out of the buffer we created */
5072 BYTE __user *ptr = ioc->buf;
5073 for (i = 0; i < sg_used; i++) {
5074 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5075 status = -EFAULT;
e2d4a1f6 5076 goto cleanup0;
edd16368
SC		 5077 }
5078 ptr += buff_size[i];
5079 }
5080 }
edd16368 5081 status = 0;
e2d4a1f6 5082cleanup0:
45fcb86e 5083 cmd_free(h, c);
edd16368
SC		 5084cleanup1:
5085 if (buff) {
2b08b3e9
DB		 5086 int i;
5087
edd16368
SC		 5088 for (i = 0; i < sg_used; i++)
5089 kfree(buff[i]);
5090 kfree(buff);
5091 }
5092 kfree(buff_size);
5093 kfree(ioc);
5094 return status;
5095}
5096
5097static void check_ioctl_unit_attention(struct ctlr_info *h,
5098 struct CommandList *c)
5099{
5100 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5101 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5102 (void) check_for_unit_attention(h, c);
5103}
0390f0c0
SC		 5104
5105static int increment_passthru_count(struct ctlr_info *h)
5106{
5107 unsigned long flags;
5108
5109 spin_lock_irqsave(&h->passthru_count_lock, flags);
5110 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5111 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5112 return -1;
5113 }
5114 h->passthru_count++;
5115 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5116 return 0;
5117}
5118
5119static void decrement_passthru_count(struct ctlr_info *h)
5120{
5121 unsigned long flags;
5122
5123 spin_lock_irqsave(&h->passthru_count_lock, flags);
5124 if (h->passthru_count <= 0) {
5125 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5126 /* not expecting to get here. */
5127 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5128 return;
5129 }
5130 h->passthru_count--;
5131 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5132}
5133
edd16368
SC		 5134/*
5135 * ioctl
5136 */
42a91641 5137static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5138{
5139 struct ctlr_info *h;
5140 void __user *argp = (void __user *)arg;
0390f0c0 5141 int rc;
edd16368
SC		 5142
5143 h = sdev_to_hba(dev);
5144
5145 switch (cmd) {
5146 case CCISS_DEREGDISK:
5147 case CCISS_REGNEWDISK:
5148 case CCISS_REGNEWD:
a08a8471 5149 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5150 return 0;
5151 case CCISS_GETPCIINFO:
5152 return hpsa_getpciinfo_ioctl(h, argp);
5153 case CCISS_GETDRIVVER:
5154 return hpsa_getdrivver_ioctl(h, argp);
5155 case CCISS_PASSTHRU:
0390f0c0
SC		 5156 if (increment_passthru_count(h))
5157 return -EAGAIN;
5158 rc = hpsa_passthru_ioctl(h, argp);
5159 decrement_passthru_count(h);
5160 return rc;
edd16368 5161 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5162 if (increment_passthru_count(h))
5163 return -EAGAIN;
5164 rc = hpsa_big_passthru_ioctl(h, argp);
5165 decrement_passthru_count(h);
5166 return rc;
edd16368
SC		 5167 default:
5168 return -ENOTTY;
5169 }
5170}
5171
6f039790
GKH		 5172static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5173 u8 reset_type)
64670ac8
SC		 5174{
5175 struct CommandList *c;
5176
5177 c = cmd_alloc(h);
5178 if (!c)
5179 return -ENOMEM;
a2dac136
SC		 5180 /* fill_cmd can't fail here, no data buffer to map */
5181 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5182 RAID_CTLR_LUNID, TYPE_MSG);
5183 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5184 c->waiting = NULL;
5185 enqueue_cmd_and_start_io(h, c);
5186 /* Don't wait for completion, the reset won't complete. Don't free
5187 * the command either. This is the last command we will send before
5188 * re-initializing everything, so it doesn't matter and won't leak.
5189 */
5190 return 0;
5191}
5192
a2dac136 5193static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5194 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5195 int cmd_type)
5196{
5197 int pci_dir = XFER_NONE;
75167d2c 5198 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5199
5200 c->cmd_type = CMD_IOCTL_PEND;
5201 c->Header.ReplyQueue = 0;
5202 if (buff != NULL && size > 0) {
5203 c->Header.SGList = 1;
50a0decf 5204 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5205 } else {
5206 c->Header.SGList = 0;
50a0decf 5207 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5208 }
edd16368
SC		 5209 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5210
edd16368
SC		 5211 if (cmd_type == TYPE_CMD) {
5212 switch (cmd) {
5213 case HPSA_INQUIRY:
5214 /* are we trying to read a vital product page */
b7bb24eb 5215 if (page_code & VPD_PAGE) {
edd16368 5216 c->Request.CDB[1] = 0x01;
b7bb24eb 5217 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5218 }
5219 c->Request.CDBLen = 6;
a505b86f
SC		 5220 c->Request.type_attr_dir =
5221 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5222 c->Request.Timeout = 0;
5223 c->Request.CDB[0] = HPSA_INQUIRY;
5224 c->Request.CDB[4] = size & 0xFF;
5225 break;
5226 case HPSA_REPORT_LOG:
5227 case HPSA_REPORT_PHYS:
5228 /* Talking to controller so It's a physical command
5229 mode = 00 target = 0. Nothing to write.
5230 */
5231 c->Request.CDBLen = 12;
a505b86f
SC		 5232 c->Request.type_attr_dir =
5233 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5234 c->Request.Timeout = 0;
5235 c->Request.CDB[0] = cmd;
5236 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5237 c->Request.CDB[7] = (size >> 16) & 0xFF;
5238 c->Request.CDB[8] = (size >> 8) & 0xFF;
5239 c->Request.CDB[9] = size & 0xFF;
5240 break;
edd16368
SC		 5241 case HPSA_CACHE_FLUSH:
5242 c->Request.CDBLen = 12;
a505b86f
SC		 5243 c->Request.type_attr_dir =
5244 TYPE_ATTR_DIR(cmd_type,
5245 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5246 c->Request.Timeout = 0;
5247 c->Request.CDB[0] = BMIC_WRITE;
5248 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5249 c->Request.CDB[7] = (size >> 8) & 0xFF;
5250 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5251 break;
5252 case TEST_UNIT_READY:
5253 c->Request.CDBLen = 6;
a505b86f
SC		 5254 c->Request.type_attr_dir =
5255 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5256 c->Request.Timeout = 0;
5257 break;
283b4a9b
SC		 5258 case HPSA_GET_RAID_MAP:
5259 c->Request.CDBLen = 12;
a505b86f
SC		 5260 c->Request.type_attr_dir =
5261 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5262 c->Request.Timeout = 0;
5263 c->Request.CDB[0] = HPSA_CISS_READ;
5264 c->Request.CDB[1] = cmd;
5265 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5266 c->Request.CDB[7] = (size >> 16) & 0xFF;
5267 c->Request.CDB[8] = (size >> 8) & 0xFF;
5268 c->Request.CDB[9] = size & 0xFF;
5269 break;
316b221a
SC		 5270 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5271 c->Request.CDBLen = 10;
a505b86f
SC		 5272 c->Request.type_attr_dir =
5273 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5274 c->Request.Timeout = 0;
5275 c->Request.CDB[0] = BMIC_READ;
5276 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5277 c->Request.CDB[7] = (size >> 16) & 0xFF;
5278 c->Request.CDB[8] = (size >> 8) & 0xFF;
5279 break;
03383736
DB		 5280 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5281 c->Request.CDBLen = 10;
5282 c->Request.type_attr_dir =
5283 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5284 c->Request.Timeout = 0;
5285 c->Request.CDB[0] = BMIC_READ;
5286 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5287 c->Request.CDB[7] = (size >> 16) & 0xFF;
5288 c->Request.CDB[8] = (size >> 8) & 0XFF;
5289 break;
edd16368
SC		 5290 default:
5291 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5292 BUG();
a2dac136 5293 return -1;
edd16368
SC		 5294 }
5295 } else if (cmd_type == TYPE_MSG) {
5296 switch (cmd) {
5297
5298 case HPSA_DEVICE_RESET_MSG:
5299 c->Request.CDBLen = 16;
a505b86f
SC		 5300 c->Request.type_attr_dir =
5301 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5302 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5303 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5304 c->Request.CDB[0] = cmd;
21e89afd 5305 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5306 /* If bytes 4-7 are zero, it means reset the */
5307 /* LunID device */
5308 c->Request.CDB[4] = 0x00;
5309 c->Request.CDB[5] = 0x00;
5310 c->Request.CDB[6] = 0x00;
5311 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5312 break;
5313 case HPSA_ABORT_MSG:
5314 a = buff; /* point to command to be aborted */
2b08b3e9
DB		 5315 dev_dbg(&h->pdev->dev,
5316 "Abort Tag:0x%016llx request Tag:0x%016llx",
50a0decf 5317 a->Header.tag, c->Header.tag);
75167d2c 5318 c->Request.CDBLen = 16;
a505b86f
SC		 5319 c->Request.type_attr_dir =
5320 TYPE_ATTR_DIR(cmd_type,
5321 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5322 c->Request.Timeout = 0; /* Don't time out */
5323 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5324 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5325 c->Request.CDB[2] = 0x00; /* reserved */
5326 c->Request.CDB[3] = 0x00; /* reserved */
5327 /* Tag to abort goes in CDB[4]-CDB[11] */
2b08b3e9
DB		 5328 memcpy(&c->Request.CDB[4], &a->Header.tag,
5329 sizeof(a->Header.tag));
75167d2c
SC		 5330 c->Request.CDB[12] = 0x00; /* reserved */
5331 c->Request.CDB[13] = 0x00; /* reserved */
5332 c->Request.CDB[14] = 0x00; /* reserved */
5333 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5334 break;
edd16368
SC		 5335 default:
5336 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5337 cmd);
5338 BUG();
5339 }
5340 } else {
5341 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5342 BUG();
5343 }
5344
a505b86f 5345 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5346 case XFER_READ:
5347 pci_dir = PCI_DMA_FROMDEVICE;
5348 break;
5349 case XFER_WRITE:
5350 pci_dir = PCI_DMA_TODEVICE;
5351 break;
5352 case XFER_NONE:
5353 pci_dir = PCI_DMA_NONE;
5354 break;
5355 default:
5356 pci_dir = PCI_DMA_BIDIRECTIONAL;
5357 }
a2dac136
SC		 5358 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5359 return -1;
5360 return 0;
edd16368
SC		 5361}
5362
5363/*
5364 * Map (physical) PCI mem into (virtual) kernel space
5365 */
5366static void __iomem *remap_pci_mem(ulong base, ulong size)
5367{
5368 ulong page_base = ((ulong) base) & PAGE_MASK;
5369 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5370 void __iomem *page_remapped = ioremap_nocache(page_base,
5371 page_offs + size);
edd16368
SC		 5372
5373 return page_remapped ? (page_remapped + page_offs) : NULL;
5374}
5375
254f796b 5376static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5377{
254f796b 5378 return h->access.command_completed(h, q);
edd16368
SC		 5379}
5380
900c5440 5381static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5382{
5383 return h->access.intr_pending(h);
5384}
5385
5386static inline long interrupt_not_for_us(struct ctlr_info *h)
5387{
10f66018
SC		 5388 return (h->access.intr_pending(h) == 0) ||
5389 (h->interrupts_enabled == 0);
edd16368
SC		 5390}
5391
01a02ffc
SC		 5392static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5393 u32 raw_tag)
edd16368
SC		 5394{
5395 if (unlikely(tag_index >= h->nr_cmds)) {
5396 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5397 return 1;
5398 }
5399 return 0;
5400}
5401
5a3d16f5 5402static inline void finish_cmd(struct CommandList *c)
edd16368 5403{
e85c5974 5404 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5405 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5406 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5407 complete_scsi_command(c);
edd16368
SC		 5408 else if (c->cmd_type == CMD_IOCTL_PEND)
5409 complete(c->waiting);
a104c99f
SC		 5410}
5411
a9a3a273
SC		 5412
5413static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5414{
a9a3a273
SC		 5415#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5416#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5417 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5418 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5419 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5420}
5421
303932fd 5422/* process completion of an indexed ("direct lookup") command */
1d94f94d 5423static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5424 u32 raw_tag)
5425{
5426 u32 tag_index;
5427 struct CommandList *c;
5428
f2405db8 5429 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5430 if (!bad_tag(h, tag_index, raw_tag)) {
5431 c = h->cmd_pool + tag_index;
5432 finish_cmd(c);
5433 }
303932fd
DB		 5434}
5435
64670ac8
SC		 5436/* Some controllers, like p400, will give us one interrupt
5437 * after a soft reset, even if we turned interrupts off.
5438 * Only need to check for this in the hpsa_xxx_discard_completions
5439 * functions.
5440 */
5441static int ignore_bogus_interrupt(struct ctlr_info *h)
5442{
5443 if (likely(!reset_devices))
5444 return 0;
5445
5446 if (likely(h->interrupts_enabled))
5447 return 0;
5448
5449 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5450 "(known firmware bug.) Ignoring.\n");
5451
5452 return 1;
5453}
5454
254f796b
MG		 5455/*
5456 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5457 * Relies on (h-q[x] == x) being true for x such that
5458 * 0 <= x < MAX_REPLY_QUEUES.
5459 */
5460static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5461{
254f796b
MG		 5462 return container_of((queue - *queue), struct ctlr_info, q[0]);
5463}
5464
5465static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5466{
5467 struct ctlr_info *h = queue_to_hba(queue);
5468 u8 q = *(u8 *) queue;
64670ac8
SC		 5469 u32 raw_tag;
5470
5471 if (ignore_bogus_interrupt(h))
5472 return IRQ_NONE;
5473
5474 if (interrupt_not_for_us(h))
5475 return IRQ_NONE;
a0c12413 5476 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5477 while (interrupt_pending(h)) {
254f796b 5478 raw_tag = get_next_completion(h, q);
64670ac8 5479 while (raw_tag != FIFO_EMPTY)
254f796b 5480 raw_tag = next_command(h, q);
64670ac8 5481 }
64670ac8
SC		 5482 return IRQ_HANDLED;
5483}
5484
254f796b 5485static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5486{
254f796b 5487 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5488 u32 raw_tag;
254f796b 5489 u8 q = *(u8 *) queue;
64670ac8
SC		 5490
5491 if (ignore_bogus_interrupt(h))
5492 return IRQ_NONE;
5493
a0c12413 5494 h->last_intr_timestamp = get_jiffies_64();
254f796b 5495 raw_tag = get_next_completion(h, q);
64670ac8 5496 while (raw_tag != FIFO_EMPTY)
254f796b 5497 raw_tag = next_command(h, q);
64670ac8
SC		 5498 return IRQ_HANDLED;
5499}
5500
254f796b 5501static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5502{
254f796b 5503 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5504 u32 raw_tag;
254f796b 5505 u8 q = *(u8 *) queue;
edd16368
SC		 5506
5507 if (interrupt_not_for_us(h))
5508 return IRQ_NONE;
a0c12413 5509 h->last_intr_timestamp = get_jiffies_64();
10f66018 5510 while (interrupt_pending(h)) {
254f796b 5511 raw_tag = get_next_completion(h, q);
10f66018 5512 while (raw_tag != FIFO_EMPTY) {
f2405db8 5513 process_indexed_cmd(h, raw_tag);
254f796b 5514 raw_tag = next_command(h, q);
10f66018
SC		 5515 }
5516 }
10f66018
SC		 5517 return IRQ_HANDLED;
5518}
5519
254f796b 5520static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5521{
254f796b 5522 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5523 u32 raw_tag;
254f796b 5524 u8 q = *(u8 *) queue;
10f66018 5525
a0c12413 5526 h->last_intr_timestamp = get_jiffies_64();
254f796b 5527 raw_tag = get_next_completion(h, q);
303932fd 5528 while (raw_tag != FIFO_EMPTY) {
f2405db8 5529 process_indexed_cmd(h, raw_tag);
254f796b 5530 raw_tag = next_command(h, q);
edd16368 5531 }
edd16368
SC		 5532 return IRQ_HANDLED;
5533}
5534
a9a3a273
SC		 5535/* Send a message CDB to the firmware. Careful, this only works
5536 * in simple mode, not performant mode due to the tag lookup.
5537 * We only ever use this immediately after a controller reset.
5538 */
6f039790
GKH		 5539static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5540 unsigned char type)
edd16368
SC		 5541{
5542 struct Command {
5543 struct CommandListHeader CommandHeader;
5544 struct RequestBlock Request;
5545 struct ErrDescriptor ErrorDescriptor;
5546 };
5547 struct Command *cmd;
5548 static const size_t cmd_sz = sizeof(*cmd) +
5549 sizeof(cmd->ErrorDescriptor);
5550 dma_addr_t paddr64;
2b08b3e9
DB		 5551 __le32 paddr32;
5552 u32 tag;
edd16368
SC		 5553 void __iomem *vaddr;
5554 int i, err;
5555
5556 vaddr = pci_ioremap_bar(pdev, 0);
5557 if (vaddr == NULL)
5558 return -ENOMEM;
5559
5560 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5561 * CCISS commands, so they must be allocated from the lower 4GiB of
5562 * memory.
5563 */
5564 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5565 if (err) {
5566 iounmap(vaddr);
1eaec8f3 5567 return err;
edd16368
SC		 5568 }
5569
5570 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5571 if (cmd == NULL) {
5572 iounmap(vaddr);
5573 return -ENOMEM;
5574 }
5575
5576 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5577 * although there's no guarantee, we assume that the address is at
5578 * least 4-byte aligned (most likely, it's page-aligned).
5579 */
2b08b3e9 5580 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 5581
5582 cmd->CommandHeader.ReplyQueue = 0;
5583 cmd->CommandHeader.SGList = 0;
50a0decf 5584 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 5585 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 5586 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5587
5588 cmd->Request.CDBLen = 16;
a505b86f
SC		 5589 cmd->Request.type_attr_dir =
5590 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5591 cmd->Request.Timeout = 0; /* Don't time out */
5592 cmd->Request.CDB[0] = opcode;
5593 cmd->Request.CDB[1] = type;
5594 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 5595 cmd->ErrorDescriptor.Addr =
2b08b3e9 5596 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 5597 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 5598
2b08b3e9 5599 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 5600
5601 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5602 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 5603 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 5604 break;
5605 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5606 }
5607
5608 iounmap(vaddr);
5609
5610 /* we leak the DMA buffer here ... no choice since the controller could
5611 * still complete the command.
5612 */
5613 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5614 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5615 opcode, type);
5616 return -ETIMEDOUT;
5617 }
5618
5619 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5620
5621 if (tag & HPSA_ERROR_BIT) {
5622 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5623 opcode, type);
5624 return -EIO;
5625 }
5626
5627 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5628 opcode, type);
5629 return 0;
5630}
5631
edd16368
SC		 5632#define hpsa_noop(p) hpsa_message(p, 3, 0)
5633
1df8552a 5634static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5635 void __iomem *vaddr, u32 use_doorbell)
1df8552a 5636{
1df8552a
SC		 5637
5638 if (use_doorbell) {
5639 /* For everything after the P600, the PCI power state method
5640 * of resetting the controller doesn't work, so we have this
5641 * other way using the doorbell register.
5642 */
5643 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5644 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5645
00701a96 5646 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5647 * doorbell reset and before any attempt to talk to the board
5648 * at all to ensure that this actually works and doesn't fall
5649 * over in some weird corner cases.
5650 */
00701a96 5651 msleep(10000);
1df8552a
SC		 5652 } else { /* Try to do it the PCI power state way */
5653
5654 /* Quoting from the Open CISS Specification: "The Power
5655 * Management Control/Status Register (CSR) controls the power
5656 * state of the device. The normal operating state is D0,
5657 * CSR=00h. The software off state is D3, CSR=03h. To reset
5658 * the controller, place the interface device in D3 then to D0,
5659 * this causes a secondary PCI reset which will reset the
5660 * controller." */
2662cab8
DB		 5661
5662 int rc = 0;
5663
1df8552a 5664 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 5665
1df8552a 5666 /* enter the D3hot power management state */
2662cab8
DB		 5667 rc = pci_set_power_state(pdev, PCI_D3hot);
5668 if (rc)
5669 return rc;
1df8552a
SC		 5670
5671 msleep(500);
5672
5673 /* enter the D0 power management state */
2662cab8
DB		 5674 rc = pci_set_power_state(pdev, PCI_D0);
5675 if (rc)
5676 return rc;
c4853efe
MM		 5677
5678 /*
5679 * The P600 requires a small delay when changing states.
5680 * Otherwise we may think the board did not reset and we bail.
5681 * This for kdump only and is particular to the P600.
5682 */
5683 msleep(500);
1df8552a
SC		 5684 }
5685 return 0;
5686}
5687
6f039790 5688static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5689{
5690 memset(driver_version, 0, len);
f79cfec6 5691 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5692}
5693
6f039790 5694static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5695{
5696 char *driver_version;
5697 int i, size = sizeof(cfgtable->driver_version);
5698
5699 driver_version = kmalloc(size, GFP_KERNEL);
5700 if (!driver_version)
5701 return -ENOMEM;
5702
5703 init_driver_version(driver_version, size);
5704 for (i = 0; i < size; i++)
5705 writeb(driver_version[i], &cfgtable->driver_version[i]);
5706 kfree(driver_version);
5707 return 0;
5708}
5709
6f039790
GKH		 5710static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5711 unsigned char *driver_ver)
580ada3c
SC		 5712{
5713 int i;
5714
5715 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5716 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5717}
5718
6f039790 5719static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5720{
5721
5722 char *driver_ver, *old_driver_ver;
5723 int rc, size = sizeof(cfgtable->driver_version);
5724
5725 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5726 if (!old_driver_ver)
5727 return -ENOMEM;
5728 driver_ver = old_driver_ver + size;
5729
5730 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5731 * should have been changed, otherwise we know the reset failed.
5732 */
5733 init_driver_version(old_driver_ver, size);
5734 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5735 rc = !memcmp(driver_ver, old_driver_ver, size);
5736 kfree(old_driver_ver);
5737 return rc;
5738}
edd16368 5739/* This does a hard reset of the controller using PCI power management
1df8552a 5740 * states or the using the doorbell register.
edd16368 5741 */
6f039790 5742static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5743{
1df8552a
SC		 5744 u64 cfg_offset;
5745 u32 cfg_base_addr;
5746 u64 cfg_base_addr_index;
5747 void __iomem *vaddr;
5748 unsigned long paddr;
580ada3c 5749 u32 misc_fw_support;
270d05de 5750 int rc;
1df8552a 5751 struct CfgTable __iomem *cfgtable;
cf0b08d0 5752 u32 use_doorbell;
18867659 5753 u32 board_id;
270d05de 5754 u16 command_register;
edd16368 5755
1df8552a
SC		 5756 /* For controllers as old as the P600, this is very nearly
5757 * the same thing as
edd16368
SC		 5758 *
5759 * pci_save_state(pci_dev);
5760 * pci_set_power_state(pci_dev, PCI_D3hot);
5761 * pci_set_power_state(pci_dev, PCI_D0);
5762 * pci_restore_state(pci_dev);
5763 *
1df8552a
SC		 5764 * For controllers newer than the P600, the pci power state
5765 * method of resetting doesn't work so we have another way
5766 * using the doorbell register.
edd16368 5767 */
18867659 5768
25c1e56a 5769 rc = hpsa_lookup_board_id(pdev, &board_id);
60f923b9
RE		 5770 if (rc < 0) {
5771 dev_warn(&pdev->dev, "Board ID not found\n");
5772 return rc;
5773 }
5774 if (!ctlr_is_resettable(board_id)) {
5775 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 5776 return -ENODEV;
5777 }
46380786
SC		 5778
5779 /* if controller is soft- but not hard resettable... */
5780 if (!ctlr_is_hard_resettable(board_id))
5781 return -ENOTSUPP; /* try soft reset later. */
18867659 5782
270d05de
SC		 5783 /* Save the PCI command register */
5784 pci_read_config_word(pdev, 4, &command_register);
270d05de 5785 pci_save_state(pdev);
edd16368 5786
1df8552a
SC		 5787 /* find the first memory BAR, so we can find the cfg table */
5788 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5789 if (rc)
5790 return rc;
5791 vaddr = remap_pci_mem(paddr, 0x250);
5792 if (!vaddr)
5793 return -ENOMEM;
edd16368 5794
1df8552a
SC		 5795 /* find cfgtable in order to check if reset via doorbell is supported */
5796 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5797 &cfg_base_addr_index, &cfg_offset);
5798 if (rc)
5799 goto unmap_vaddr;
5800 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5801 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5802 if (!cfgtable) {
5803 rc = -ENOMEM;
5804 goto unmap_vaddr;
5805 }
580ada3c
SC		 5806 rc = write_driver_ver_to_cfgtable(cfgtable);
5807 if (rc)
03741d95 5808 goto unmap_cfgtable;
edd16368 5809
cf0b08d0
SC		 5810 /* If reset via doorbell register is supported, use that.
5811 * There are two such methods. Favor the newest method.
5812 */
1df8552a 5813 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5814 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5815 if (use_doorbell) {
5816 use_doorbell = DOORBELL_CTLR_RESET2;
5817 } else {
5818 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5819 if (use_doorbell) {
050f7147
SC		 5820 dev_warn(&pdev->dev,
5821 "Soft reset not supported. Firmware update is required.\n");
64670ac8 5822 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5823 goto unmap_cfgtable;
5824 }
5825 }
edd16368 5826
1df8552a
SC		 5827 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5828 if (rc)
5829 goto unmap_cfgtable;
edd16368 5830
270d05de 5831 pci_restore_state(pdev);
270d05de 5832 pci_write_config_word(pdev, 4, command_register);
edd16368 5833
1df8552a
SC		 5834 /* Some devices (notably the HP Smart Array 5i Controller)
5835 need a little pause here */
5836 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5837
fe5389c8
SC		 5838 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5839 if (rc) {
5840 dev_warn(&pdev->dev,
050f7147 5841 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 5842 goto unmap_cfgtable;
5843 }
fe5389c8 5844
580ada3c
SC		 5845 rc = controller_reset_failed(vaddr);
5846 if (rc < 0)
5847 goto unmap_cfgtable;
5848 if (rc) {
64670ac8
SC		 5849 dev_warn(&pdev->dev, "Unable to successfully reset "
5850 "controller. Will try soft reset.\n");
5851 rc = -ENOTSUPP;
580ada3c 5852 } else {
64670ac8 5853 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5854 }
5855
5856unmap_cfgtable:
5857 iounmap(cfgtable);
5858
5859unmap_vaddr:
5860 iounmap(vaddr);
5861 return rc;
edd16368
SC		 5862}
5863
5864/*
5865 * We cannot read the structure directly, for portability we must use
5866 * the io functions.
5867 * This is for debug only.
5868 */
42a91641 5869static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 5870{
58f8665c 5871#ifdef HPSA_DEBUG
edd16368
SC		 5872 int i;
5873 char temp_name[17];
5874
5875 dev_info(dev, "Controller Configuration information\n");
5876 dev_info(dev, "------------------------------------\n");
5877 for (i = 0; i < 4; i++)
5878 temp_name[i] = readb(&(tb->Signature[i]));
5879 temp_name[4] = '\0';
5880 dev_info(dev, " Signature = %s\n", temp_name);
5881 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5882 dev_info(dev, " Transport methods supported = 0x%x\n",
5883 readl(&(tb->TransportSupport)));
5884 dev_info(dev, " Transport methods active = 0x%x\n",
5885 readl(&(tb->TransportActive)));
5886 dev_info(dev, " Requested transport Method = 0x%x\n",
5887 readl(&(tb->HostWrite.TransportRequest)));
5888 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5889 readl(&(tb->HostWrite.CoalIntDelay)));
5890 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5891 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 5892 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 5893 readl(&(tb->CmdsOutMax)));
5894 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5895 for (i = 0; i < 16; i++)
5896 temp_name[i] = readb(&(tb->ServerName[i]));
5897 temp_name[16] = '\0';
5898 dev_info(dev, " Server Name = %s\n", temp_name);
5899 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5900 readl(&(tb->HeartBeat)));
edd16368 5901#endif /* HPSA_DEBUG */
58f8665c 5902}
edd16368
SC		 5903
5904static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5905{
5906 int i, offset, mem_type, bar_type;
5907
5908 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5909 return 0;
5910 offset = 0;
5911 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5912 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5913 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5914 offset += 4;
5915 else {
5916 mem_type = pci_resource_flags(pdev, i) &
5917 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5918 switch (mem_type) {
5919 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5920 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5921 offset += 4; /* 32 bit */
5922 break;
5923 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5924 offset += 8;
5925 break;
5926 default: /* reserved in PCI 2.2 */
5927 dev_warn(&pdev->dev,
5928 "base address is invalid\n");
5929 return -1;
5930 break;
5931 }
5932 }
5933 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5934 return i + 1;
5935 }
5936 return -1;
5937}
5938
5939/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 5940 * controllers that are capable. If not, we use legacy INTx mode.
edd16368
SC		 5941 */
5942
6f039790 5943static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5944{
5945#ifdef CONFIG_PCI_MSI
254f796b
MG		 5946 int err, i;
5947 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5948
5949 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5950 hpsa_msix_entries[i].vector = 0;
5951 hpsa_msix_entries[i].entry = i;
5952 }
edd16368
SC		 5953
5954 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5955 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5956 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5957 goto default_int_mode;
55c06c71 5958 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 5959 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 5960 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 5961 if (h->msix_vector > num_online_cpus())
5962 h->msix_vector = num_online_cpus();
18fce3c4
AG		 5963 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
5964 1, h->msix_vector);
5965 if (err < 0) {
5966 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
5967 h->msix_vector = 0;
5968 goto single_msi_mode;
5969 } else if (err < h->msix_vector) {
55c06c71 5970 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5971 "available\n", err);
edd16368 5972 }
18fce3c4
AG		 5973 h->msix_vector = err;
5974 for (i = 0; i < h->msix_vector; i++)
5975 h->intr[i] = hpsa_msix_entries[i].vector;
5976 return;
edd16368 5977 }
18fce3c4 5978single_msi_mode:
55c06c71 5979 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 5980 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 5981 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5982 h->msi_vector = 1;
5983 else
55c06c71 5984 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5985 }
5986default_int_mode:
5987#endif /* CONFIG_PCI_MSI */
5988 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5989 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5990}
5991
6f039790 5992static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5993{
5994 int i;
5995 u32 subsystem_vendor_id, subsystem_device_id;
5996
5997 subsystem_vendor_id = pdev->subsystem_vendor;
5998 subsystem_device_id = pdev->subsystem_device;
5999 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6000 subsystem_vendor_id;
6001
6002 for (i = 0; i < ARRAY_SIZE(products); i++)
6003 if (*board_id == products[i].board_id)
6004 return i;
6005
6798cc0a
SC		 6006 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6007 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6008 !hpsa_allow_any) {
e5c880d1
SC		 6009 dev_warn(&pdev->dev, "unrecognized board ID: "
6010 "0x%08x, ignoring.\n", *board_id);
6011 return -ENODEV;
6012 }
6013 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6014}
6015
6f039790
GKH		 6016static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6017 unsigned long *memory_bar)
3a7774ce
SC		 6018{
6019 int i;
6020
6021 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6022 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6023 /* addressing mode bits already removed */
12d2cd47
SC		 6024 *memory_bar = pci_resource_start(pdev, i);
6025 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6026 *memory_bar);
6027 return 0;
6028 }
12d2cd47 6029 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6030 return -ENODEV;
6031}
6032
6f039790
GKH		 6033static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6034 int wait_for_ready)
2c4c8c8b 6035{
fe5389c8 6036 int i, iterations;
2c4c8c8b 6037 u32 scratchpad;
fe5389c8
SC		 6038 if (wait_for_ready)
6039 iterations = HPSA_BOARD_READY_ITERATIONS;
6040 else
6041 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6042
fe5389c8
SC		 6043 for (i = 0; i < iterations; i++) {
6044 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6045 if (wait_for_ready) {
6046 if (scratchpad == HPSA_FIRMWARE_READY)
6047 return 0;
6048 } else {
6049 if (scratchpad != HPSA_FIRMWARE_READY)
6050 return 0;
6051 }
2c4c8c8b
SC		 6052 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6053 }
fe5389c8 6054 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6055 return -ENODEV;
6056}
6057
6f039790
GKH		 6058static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6059 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6060 u64 *cfg_offset)
a51fd47f
SC		 6061{
6062 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6063 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6064 *cfg_base_addr &= (u32) 0x0000ffff;
6065 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6066 if (*cfg_base_addr_index == -1) {
6067 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6068 return -ENODEV;
6069 }
6070 return 0;
6071}
6072
6f039790 6073static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6074{
01a02ffc
SC		 6075 u64 cfg_offset;
6076 u32 cfg_base_addr;
6077 u64 cfg_base_addr_index;
303932fd 6078 u32 trans_offset;
a51fd47f 6079 int rc;
77c4495c 6080
a51fd47f
SC		 6081 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6082 &cfg_base_addr_index, &cfg_offset);
6083 if (rc)
6084 return rc;
77c4495c 6085 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6086 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6087 if (!h->cfgtable) {
6088 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6089 return -ENOMEM;
cd3c81c4 6090 }
580ada3c
SC		 6091 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6092 if (rc)
6093 return rc;
77c4495c 6094 /* Find performant mode table. */
a51fd47f 6095 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6096 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6097 cfg_base_addr_index)+cfg_offset+trans_offset,
6098 sizeof(*h->transtable));
6099 if (!h->transtable)
6100 return -ENOMEM;
6101 return 0;
6102}
6103
6f039790 6104static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6105{
6106 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6107
6108 /* Limit commands in memory limited kdump scenario. */
6109 if (reset_devices && h->max_commands > 32)
6110 h->max_commands = 32;
6111
cba3d38b
SC		 6112 if (h->max_commands < 16) {
6113 dev_warn(&h->pdev->dev, "Controller reports "
6114 "max supported commands of %d, an obvious lie. "
6115 "Using 16. Ensure that firmware is up to date.\n",
6116 h->max_commands);
6117 h->max_commands = 16;
6118 }
6119}
6120
c7ee65b3
WS		 6121/* If the controller reports that the total max sg entries is greater than 512,
6122 * then we know that chained SG blocks work. (Original smart arrays did not
6123 * support chained SG blocks and would return zero for max sg entries.)
6124 */
6125static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6126{
6127 return h->maxsgentries > 512;
6128}
6129
b93d7536
SC		 6130/* Interrogate the hardware for some limits:
6131 * max commands, max SG elements without chaining, and with chaining,
6132 * SG chain block size, etc.
6133 */
6f039790 6134static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6135{
cba3d38b 6136 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6137 h->nr_cmds = h->max_commands;
b93d7536 6138 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6139 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6140 if (hpsa_supports_chained_sg_blocks(h)) {
6141 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6142 h->max_cmd_sg_entries = 32;
1a63ea6f 6143 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6144 h->maxsgentries--; /* save one for chain pointer */
6145 } else {
c7ee65b3
WS		 6146 /*
6147 * Original smart arrays supported at most 31 s/g entries
6148 * embedded inline in the command (trying to use more
6149 * would lock up the controller)
6150 */
6151 h->max_cmd_sg_entries = 31;
1a63ea6f 6152 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6153 h->chainsize = 0;
b93d7536 6154 }
75167d2c
SC		 6155
6156 /* Find out what task management functions are supported and cache */
6157 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6158 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6159 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6160 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6161 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6162}
6163
76c46e49
SC		 6164static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6165{
0fc9fd40 6166 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6167 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6168 return false;
6169 }
6170 return true;
6171}
6172
97a5e98c 6173static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6174{
97a5e98c 6175 u32 driver_support;
f7c39101 6176
97a5e98c 6177 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6178 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6179#ifdef CONFIG_X86
97a5e98c 6180 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6181#endif
28e13446
SC		 6182 driver_support |= ENABLE_UNIT_ATTN;
6183 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6184}
6185
3d0eab67
SC		 6186/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6187 * in a prefetch beyond physical memory.
6188 */
6189static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6190{
6191 u32 dma_prefetch;
6192
6193 if (h->board_id != 0x3225103C)
6194 return;
6195 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6196 dma_prefetch |= 0x8000;
6197 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6198}
6199
76438d08
SC		 6200static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6201{
6202 int i;
6203 u32 doorbell_value;
6204 unsigned long flags;
6205 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6206 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6207 spin_lock_irqsave(&h->lock, flags);
6208 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6209 spin_unlock_irqrestore(&h->lock, flags);
6210 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6211 break;
6212 /* delay and try again */
6213 msleep(20);
6214 }
6215}
6216
6f039790 6217static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6218{
6219 int i;
6eaf46fd
SC		 6220 u32 doorbell_value;
6221 unsigned long flags;
eb6b2ae9
SC		 6222
6223 /* under certain very rare conditions, this can take awhile.
6224 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6225 * as we enter this code.)
6226 */
6227 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6228 spin_lock_irqsave(&h->lock, flags);
6229 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6230 spin_unlock_irqrestore(&h->lock, flags);
382be668 6231 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6232 break;
6233 /* delay and try again */
60d3f5b0 6234 usleep_range(10000, 20000);
eb6b2ae9 6235 }
3f4336f3
SC		 6236}
6237
6f039790 6238static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6239{
6240 u32 trans_support;
6241
6242 trans_support = readl(&(h->cfgtable->TransportSupport));
6243 if (!(trans_support & SIMPLE_MODE))
6244 return -ENOTSUPP;
6245
6246 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6247
3f4336f3
SC		 6248 /* Update the field, and then ring the doorbell */
6249 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6250 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6251 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6252 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6253 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6254 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6255 goto error;
960a30e7 6256 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6257 return 0;
283b4a9b 6258error:
050f7147 6259 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6260 return -ENODEV;
eb6b2ae9
SC		 6261}
6262
6f039790 6263static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6264{
eb6b2ae9 6265 int prod_index, err;
edd16368 6266
e5c880d1
SC		 6267 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6268 if (prod_index < 0)
60f923b9 6269 return prod_index;
e5c880d1
SC		 6270 h->product_name = products[prod_index].product_name;
6271 h->access = *(products[prod_index].access);
edd16368 6272
e5a44df8
MG		 6273 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6274 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6275
55c06c71 6276 err = pci_enable_device(h->pdev);
edd16368 6277 if (err) {
55c06c71 6278 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6279 return err;
6280 }
6281
f79cfec6 6282 err = pci_request_regions(h->pdev, HPSA);
edd16368 6283 if (err) {
55c06c71
SC		 6284 dev_err(&h->pdev->dev,
6285 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6286 return err;
6287 }
4fa604e1
RE		 6288
6289 pci_set_master(h->pdev);
6290
6b3f4c52 6291 hpsa_interrupt_mode(h);
12d2cd47 6292 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6293 if (err)
edd16368 6294 goto err_out_free_res;
edd16368 6295 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6296 if (!h->vaddr) {
6297 err = -ENOMEM;
6298 goto err_out_free_res;
6299 }
fe5389c8 6300 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6301 if (err)
edd16368 6302 goto err_out_free_res;
77c4495c
SC		 6303 err = hpsa_find_cfgtables(h);
6304 if (err)
edd16368 6305 goto err_out_free_res;
b93d7536 6306 hpsa_find_board_params(h);
edd16368 6307
76c46e49 6308 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6309 err = -ENODEV;
6310 goto err_out_free_res;
6311 }
97a5e98c 6312 hpsa_set_driver_support_bits(h);
3d0eab67 6313 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6314 err = hpsa_enter_simple_mode(h);
6315 if (err)
edd16368 6316 goto err_out_free_res;
edd16368
SC		 6317 return 0;
6318
6319err_out_free_res:
204892e9
SC		 6320 if (h->transtable)
6321 iounmap(h->transtable);
6322 if (h->cfgtable)
6323 iounmap(h->cfgtable);
6324 if (h->vaddr)
6325 iounmap(h->vaddr);
f0bd0b68 6326 pci_disable_device(h->pdev);
55c06c71 6327 pci_release_regions(h->pdev);
edd16368
SC		 6328 return err;
6329}
6330
6f039790 6331static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6332{
6333 int rc;
6334
6335#define HBA_INQUIRY_BYTE_COUNT 64
6336 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6337 if (!h->hba_inquiry_data)
6338 return;
6339 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6340 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6341 if (rc != 0) {
6342 kfree(h->hba_inquiry_data);
6343 h->hba_inquiry_data = NULL;
6344 }
6345}
6346
6f039790 6347static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6348{
1df8552a 6349 int rc, i;
3b747298 6350 void __iomem *vaddr;
4c2a8c40
SC		 6351
6352 if (!reset_devices)
6353 return 0;
6354
132aa220
TH		 6355 /* kdump kernel is loading, we don't know in which state is
6356 * the pci interface. The dev->enable_cnt is equal zero
6357 * so we call enable+disable, wait a while and switch it on.
6358 */
6359 rc = pci_enable_device(pdev);
6360 if (rc) {
6361 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6362 return -ENODEV;
6363 }
6364 pci_disable_device(pdev);
6365 msleep(260); /* a randomly chosen number */
6366 rc = pci_enable_device(pdev);
6367 if (rc) {
6368 dev_warn(&pdev->dev, "failed to enable device.\n");
6369 return -ENODEV;
6370 }
4fa604e1 6371
859c75ab 6372 pci_set_master(pdev);
4fa604e1 6373
3b747298
TH		 6374 vaddr = pci_ioremap_bar(pdev, 0);
6375 if (vaddr == NULL) {
6376 rc = -ENOMEM;
6377 goto out_disable;
6378 }
6379 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6380 iounmap(vaddr);
6381
1df8552a
SC		 6382 /* Reset the controller with a PCI power-cycle or via doorbell */
6383 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6384
1df8552a
SC		 6385 /* -ENOTSUPP here means we cannot reset the controller
6386 * but it's already (and still) up and running in
18867659
SC		 6387 * "performant mode". Or, it might be 640x, which can't reset
6388 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6389 */
adf1b3a3 6390 if (rc)
132aa220 6391 goto out_disable;
4c2a8c40
SC		 6392
6393 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6394 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6395 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6396 if (hpsa_noop(pdev) == 0)
6397 break;
6398 else
6399 dev_warn(&pdev->dev, "no-op failed%s\n",
6400 (i < 11 ? "; re-trying" : ""));
6401 }
132aa220
TH		 6402
6403out_disable:
6404
6405 pci_disable_device(pdev);
6406 return rc;
4c2a8c40
SC		 6407}
6408
6f039790 6409static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6410{
6411 h->cmd_pool_bits = kzalloc(
6412 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6413 sizeof(unsigned long), GFP_KERNEL);
6414 h->cmd_pool = pci_alloc_consistent(h->pdev,
6415 h->nr_cmds * sizeof(*h->cmd_pool),
6416 &(h->cmd_pool_dhandle));
6417 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6418 h->nr_cmds * sizeof(*h->errinfo_pool),
6419 &(h->errinfo_pool_dhandle));
6420 if ((h->cmd_pool_bits == NULL)
6421 || (h->cmd_pool == NULL)
6422 || (h->errinfo_pool == NULL)) {
6423 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 6424 goto clean_up;
2e9d1b36
SC		 6425 }
6426 return 0;
2c143342
RE		 6427clean_up:
6428 hpsa_free_cmd_pool(h);
6429 return -ENOMEM;
2e9d1b36
SC		 6430}
6431
6432static void hpsa_free_cmd_pool(struct ctlr_info *h)
6433{
6434 kfree(h->cmd_pool_bits);
6435 if (h->cmd_pool)
6436 pci_free_consistent(h->pdev,
6437 h->nr_cmds * sizeof(struct CommandList),
6438 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6439 if (h->ioaccel2_cmd_pool)
6440 pci_free_consistent(h->pdev,
6441 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6442 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6443 if (h->errinfo_pool)
6444 pci_free_consistent(h->pdev,
6445 h->nr_cmds * sizeof(struct ErrorInfo),
6446 h->errinfo_pool,
6447 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6448 if (h->ioaccel_cmd_pool)
6449 pci_free_consistent(h->pdev,
6450 h->nr_cmds * sizeof(struct io_accel1_cmd),
6451 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6452}
6453
41b3cf08
SC		 6454static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6455{
ec429952 6456 int i, cpu;
41b3cf08
SC		 6457
6458 cpu = cpumask_first(cpu_online_mask);
6459 for (i = 0; i < h->msix_vector; i++) {
ec429952 6460 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 6461 cpu = cpumask_next(cpu, cpu_online_mask);
6462 }
6463}
6464
ec501a18
RE		 6465/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
6466static void hpsa_free_irqs(struct ctlr_info *h)
6467{
6468 int i;
6469
6470 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6471 /* Single reply queue, only one irq to free */
6472 i = h->intr_mode;
6473 irq_set_affinity_hint(h->intr[i], NULL);
6474 free_irq(h->intr[i], &h->q[i]);
6475 return;
6476 }
6477
6478 for (i = 0; i < h->msix_vector; i++) {
6479 irq_set_affinity_hint(h->intr[i], NULL);
6480 free_irq(h->intr[i], &h->q[i]);
6481 }
a4e17fc1
RE		 6482 for (; i < MAX_REPLY_QUEUES; i++)
6483 h->q[i] = 0;
ec501a18
RE		 6484}
6485
9ee61794
RE		 6486/* returns 0 on success; cleans up and returns -Enn on error */
6487static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 6488 irqreturn_t (*msixhandler)(int, void *),
6489 irqreturn_t (*intxhandler)(int, void *))
6490{
254f796b 6491 int rc, i;
0ae01a32 6492
254f796b
MG		 6493 /*
6494 * initialize h->q[x] = x so that interrupt handlers know which
6495 * queue to process.
6496 */
6497 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6498 h->q[i] = (u8) i;
6499
eee0f03a 6500 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6501 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 6502 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 6503 rc = request_irq(h->intr[i], msixhandler,
6504 0, h->devname,
6505 &h->q[i]);
a4e17fc1
RE		 6506 if (rc) {
6507 int j;
6508
6509 dev_err(&h->pdev->dev,
6510 "failed to get irq %d for %s\n",
6511 h->intr[i], h->devname);
6512 for (j = 0; j < i; j++) {
6513 free_irq(h->intr[j], &h->q[j]);
6514 h->q[j] = 0;
6515 }
6516 for (; j < MAX_REPLY_QUEUES; j++)
6517 h->q[j] = 0;
6518 return rc;
6519 }
6520 }
41b3cf08 6521 hpsa_irq_affinity_hints(h);
254f796b
MG		 6522 } else {
6523 /* Use single reply pool */
eee0f03a 6524 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6525 rc = request_irq(h->intr[h->intr_mode],
6526 msixhandler, 0, h->devname,
6527 &h->q[h->intr_mode]);
6528 } else {
6529 rc = request_irq(h->intr[h->intr_mode],
6530 intxhandler, IRQF_SHARED, h->devname,
6531 &h->q[h->intr_mode]);
6532 }
6533 }
0ae01a32
SC		 6534 if (rc) {
6535 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6536 h->intr[h->intr_mode], h->devname);
6537 return -ENODEV;
6538 }
6539 return 0;
6540}
6541
6f039790 6542static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6543{
6544 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6545 HPSA_RESET_TYPE_CONTROLLER)) {
6546 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6547 return -EIO;
6548 }
6549
6550 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6551 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6552 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6553 return -1;
6554 }
6555
6556 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6557 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6558 dev_warn(&h->pdev->dev, "Board failed to become ready "
6559 "after soft reset.\n");
6560 return -1;
6561 }
6562
6563 return 0;
6564}
6565
0097f0f4 6566static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6567{
ec501a18 6568 hpsa_free_irqs(h);
64670ac8 6569#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6570 if (h->msix_vector) {
6571 if (h->pdev->msix_enabled)
6572 pci_disable_msix(h->pdev);
6573 } else if (h->msi_vector) {
6574 if (h->pdev->msi_enabled)
6575 pci_disable_msi(h->pdev);
6576 }
64670ac8 6577#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6578}
6579
072b0518
SC		 6580static void hpsa_free_reply_queues(struct ctlr_info *h)
6581{
6582 int i;
6583
6584 for (i = 0; i < h->nreply_queues; i++) {
6585 if (!h->reply_queue[i].head)
6586 continue;
6587 pci_free_consistent(h->pdev, h->reply_queue_size,
6588 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6589 h->reply_queue[i].head = NULL;
6590 h->reply_queue[i].busaddr = 0;
6591 }
6592}
6593
0097f0f4
SC		 6594static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6595{
6596 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6597 hpsa_free_sg_chain_blocks(h);
6598 hpsa_free_cmd_pool(h);
e1f7de0c 6599 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6600 kfree(h->blockFetchTable);
072b0518 6601 hpsa_free_reply_queues(h);
64670ac8
SC		 6602 if (h->vaddr)
6603 iounmap(h->vaddr);
6604 if (h->transtable)
6605 iounmap(h->transtable);
6606 if (h->cfgtable)
6607 iounmap(h->cfgtable);
132aa220 6608 pci_disable_device(h->pdev);
64670ac8
SC		 6609 pci_release_regions(h->pdev);
6610 kfree(h);
6611}
6612
a0c12413 6613/* Called when controller lockup detected. */
f2405db8 6614static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 6615{
281a7fd0
WS		 6616 int i, refcount;
6617 struct CommandList *c;
a0c12413 6618
080ef1cc 6619 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 6620 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 6621 c = h->cmd_pool + i;
281a7fd0
WS		 6622 refcount = atomic_inc_return(&c->refcount);
6623 if (refcount > 1) {
6624 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
6625 finish_cmd(c);
6626 }
6627 cmd_free(h, c);
a0c12413
SC		 6628 }
6629}
6630
094963da
SC		 6631static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6632{
6633 int i, cpu;
6634
6635 cpu = cpumask_first(cpu_online_mask);
6636 for (i = 0; i < num_online_cpus(); i++) {
6637 u32 *lockup_detected;
6638 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6639 *lockup_detected = value;
6640 cpu = cpumask_next(cpu, cpu_online_mask);
6641 }
6642 wmb(); /* be sure the per-cpu variables are out to memory */
6643}
6644
a0c12413
SC		 6645static void controller_lockup_detected(struct ctlr_info *h)
6646{
6647 unsigned long flags;
094963da 6648 u32 lockup_detected;
a0c12413 6649
a0c12413
SC		 6650 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6651 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6652 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6653 if (!lockup_detected) {
6654 /* no heartbeat, but controller gave us a zero. */
6655 dev_warn(&h->pdev->dev,
6656 "lockup detected but scratchpad register is zero\n");
6657 lockup_detected = 0xffffffff;
6658 }
6659 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6660 spin_unlock_irqrestore(&h->lock, flags);
6661 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6662 lockup_detected);
a0c12413 6663 pci_disable_device(h->pdev);
f2405db8 6664 fail_all_outstanding_cmds(h);
a0c12413
SC		 6665}
6666
a0c12413
SC		 6667static void detect_controller_lockup(struct ctlr_info *h)
6668{
6669 u64 now;
6670 u32 heartbeat;
6671 unsigned long flags;
6672
a0c12413
SC		 6673 now = get_jiffies_64();
6674 /* If we've received an interrupt recently, we're ok. */
6675 if (time_after64(h->last_intr_timestamp +
e85c5974 6676 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6677 return;
6678
6679 /*
6680 * If we've already checked the heartbeat recently, we're ok.
6681 * This could happen if someone sends us a signal. We
6682 * otherwise don't care about signals in this thread.
6683 */
6684 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6685 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6686 return;
6687
6688 /* If heartbeat has not changed since we last looked, we're not ok. */
6689 spin_lock_irqsave(&h->lock, flags);
6690 heartbeat = readl(&h->cfgtable->HeartBeat);
6691 spin_unlock_irqrestore(&h->lock, flags);
6692 if (h->last_heartbeat == heartbeat) {
6693 controller_lockup_detected(h);
6694 return;
6695 }
6696
6697 /* We're ok. */
6698 h->last_heartbeat = heartbeat;
6699 h->last_heartbeat_timestamp = now;
6700}
6701
9846590e 6702static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6703{
6704 int i;
6705 char *event_type;
6706
6707 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6708 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6709 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6710 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6711 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6712
6713 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6714 event_type = "state change";
6715 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6716 event_type = "configuration change";
6717 /* Stop sending new RAID offload reqs via the IO accelerator */
6718 scsi_block_requests(h->scsi_host);
6719 for (i = 0; i < h->ndevices; i++)
6720 h->dev[i]->offload_enabled = 0;
23100dd9 6721 hpsa_drain_accel_commands(h);
76438d08
SC		 6722 /* Set 'accelerator path config change' bit */
6723 dev_warn(&h->pdev->dev,
6724 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6725 h->events, event_type);
6726 writel(h->events, &(h->cfgtable->clear_event_notify));
6727 /* Set the "clear event notify field update" bit 6 */
6728 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6729 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6730 hpsa_wait_for_clear_event_notify_ack(h);
6731 scsi_unblock_requests(h->scsi_host);
6732 } else {
6733 /* Acknowledge controller notification events. */
6734 writel(h->events, &(h->cfgtable->clear_event_notify));
6735 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6736 hpsa_wait_for_clear_event_notify_ack(h);
6737#if 0
6738 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6739 hpsa_wait_for_mode_change_ack(h);
6740#endif
6741 }
9846590e 6742 return;
76438d08
SC		 6743}
6744
6745/* Check a register on the controller to see if there are configuration
6746 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6747 * we should rescan the controller for devices.
6748 * Also check flag for driver-initiated rescan.
76438d08 6749 */
9846590e 6750static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 6751{
6752 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6753 return 0;
76438d08
SC		 6754
6755 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6756 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6757}
76438d08 6758
9846590e
SC		 6759/*
6760 * Check if any of the offline devices have become ready
6761 */
6762static int hpsa_offline_devices_ready(struct ctlr_info *h)
6763{
6764 unsigned long flags;
6765 struct offline_device_entry *d;
6766 struct list_head *this, *tmp;
6767
6768 spin_lock_irqsave(&h->offline_device_lock, flags);
6769 list_for_each_safe(this, tmp, &h->offline_device_list) {
6770 d = list_entry(this, struct offline_device_entry,
6771 offline_list);
6772 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 6773 if (!hpsa_volume_offline(h, d->scsi3addr)) {
6774 spin_lock_irqsave(&h->offline_device_lock, flags);
6775 list_del(&d->offline_list);
6776 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 6777 return 1;
d1fea47c 6778 }
9846590e
SC		 6779 spin_lock_irqsave(&h->offline_device_lock, flags);
6780 }
6781 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6782 return 0;
76438d08
SC		 6783}
6784
9846590e 6785
8a98db73 6786static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6787{
6788 unsigned long flags;
8a98db73
SC		 6789 struct ctlr_info *h = container_of(to_delayed_work(work),
6790 struct ctlr_info, monitor_ctlr_work);
6791 detect_controller_lockup(h);
094963da 6792 if (lockup_detected(h))
8a98db73 6793 return;
9846590e
SC		 6794
6795 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6796 scsi_host_get(h->scsi_host);
9846590e
SC		 6797 hpsa_ack_ctlr_events(h);
6798 hpsa_scan_start(h->scsi_host);
6799 scsi_host_put(h->scsi_host);
6800 }
6801
8a98db73
SC		 6802 spin_lock_irqsave(&h->lock, flags);
6803 if (h->remove_in_progress) {
6804 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6805 return;
6806 }
8a98db73
SC		 6807 schedule_delayed_work(&h->monitor_ctlr_work,
6808 h->heartbeat_sample_interval);
6809 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6810}
6811
6f039790 6812static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6813{
4c2a8c40 6814 int dac, rc;
edd16368 6815 struct ctlr_info *h;
64670ac8
SC		 6816 int try_soft_reset = 0;
6817 unsigned long flags;
edd16368
SC		 6818
6819 if (number_of_controllers == 0)
6820 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6821
4c2a8c40 6822 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6823 if (rc) {
6824 if (rc != -ENOTSUPP)
6825 return rc;
6826 /* If the reset fails in a particular way (it has no way to do
6827 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6828 * a soft reset once we get the controller configured up to the
6829 * point that it can accept a command.
6830 */
6831 try_soft_reset = 1;
6832 rc = 0;
6833 }
6834
6835reinit_after_soft_reset:
edd16368 6836
303932fd
DB		 6837 /* Command structures must be aligned on a 32-byte boundary because
6838 * the 5 lower bits of the address are used by the hardware. and by
6839 * the driver. See comments in hpsa.h for more info.
6840 */
303932fd 6841 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6842 h = kzalloc(sizeof(*h), GFP_KERNEL);
6843 if (!h)
ecd9aad4 6844 return -ENOMEM;
edd16368 6845
55c06c71 6846 h->pdev = pdev;
a9a3a273 6847 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 6848 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6849 spin_lock_init(&h->lock);
9846590e 6850 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6851 spin_lock_init(&h->scan_lock);
0390f0c0 6852 spin_lock_init(&h->passthru_count_lock);
094963da 6853
080ef1cc
DB		 6854 h->resubmit_wq = alloc_workqueue("hpsa", WQ_MEM_RECLAIM, 0);
6855 if (!h->resubmit_wq) {
6856 dev_err(&h->pdev->dev, "Failed to allocate work queue\n");
6857 rc = -ENOMEM;
6858 goto clean1;
6859 }
094963da
SC		 6860 /* Allocate and clear per-cpu variable lockup_detected */
6861 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 6862 if (!h->lockup_detected) {
6863 rc = -ENOMEM;
094963da 6864 goto clean1;
2a5ac326 6865 }
094963da
SC		 6866 set_lockup_detected_for_all_cpus(h, 0);
6867
55c06c71 6868 rc = hpsa_pci_init(h);
ecd9aad4 6869 if (rc != 0)
edd16368
SC		 6870 goto clean1;
6871
f79cfec6 6872 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6873 h->ctlr = number_of_controllers;
6874 number_of_controllers++;
edd16368
SC		 6875
6876 /* configure PCI DMA stuff */
ecd9aad4
SC		 6877 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6878 if (rc == 0) {
edd16368 6879 dac = 1;
ecd9aad4
SC		 6880 } else {
6881 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6882 if (rc == 0) {
6883 dac = 0;
6884 } else {
6885 dev_err(&pdev->dev, "no suitable DMA available\n");
6886 goto clean1;
6887 }
edd16368
SC		 6888 }
6889
6890 /* make sure the board interrupts are off */
6891 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6892
9ee61794 6893 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6894 goto clean2;
303932fd
DB		 6895 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6896 h->devname, pdev->device,
a9a3a273 6897 h->intr[h->intr_mode], dac ? "" : " not");
8947fd10
RE		 6898 rc = hpsa_allocate_cmd_pool(h);
6899 if (rc)
6900 goto clean2_and_free_irqs;
33a2ffce
SC		 6901 if (hpsa_allocate_sg_chain_blocks(h))
6902 goto clean4;
a08a8471
SC		 6903 init_waitqueue_head(&h->scan_wait_queue);
6904 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6905
6906 pci_set_drvdata(pdev, h);
9a41338e 6907 h->ndevices = 0;
316b221a 6908 h->hba_mode_enabled = 0;
9a41338e
SC		 6909 h->scsi_host = NULL;
6910 spin_lock_init(&h->devlock);
64670ac8
SC		 6911 hpsa_put_ctlr_into_performant_mode(h);
6912
6913 /* At this point, the controller is ready to take commands.
6914 * Now, if reset_devices and the hard reset didn't work, try
6915 * the soft reset and see if that works.
6916 */
6917 if (try_soft_reset) {
6918
6919 /* This is kind of gross. We may or may not get a completion
6920 * from the soft reset command, and if we do, then the value
6921 * from the fifo may or may not be valid. So, we wait 10 secs
6922 * after the reset throwing away any completions we get during
6923 * that time. Unregister the interrupt handler and register
6924 * fake ones to scoop up any residual completions.
6925 */
6926 spin_lock_irqsave(&h->lock, flags);
6927 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6928 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 6929 hpsa_free_irqs(h);
9ee61794 6930 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 6931 hpsa_intx_discard_completions);
6932 if (rc) {
9ee61794
RE		 6933 dev_warn(&h->pdev->dev,
6934 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 6935 goto clean4;
6936 }
6937
6938 rc = hpsa_kdump_soft_reset(h);
6939 if (rc)
6940 /* Neither hard nor soft reset worked, we're hosed. */
6941 goto clean4;
6942
6943 dev_info(&h->pdev->dev, "Board READY.\n");
6944 dev_info(&h->pdev->dev,
6945 "Waiting for stale completions to drain.\n");
6946 h->access.set_intr_mask(h, HPSA_INTR_ON);
6947 msleep(10000);
6948 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6949
6950 rc = controller_reset_failed(h->cfgtable);
6951 if (rc)
6952 dev_info(&h->pdev->dev,
6953 "Soft reset appears to have failed.\n");
6954
6955 /* since the controller's reset, we have to go back and re-init
6956 * everything. Easiest to just forget what we've done and do it
6957 * all over again.
6958 */
6959 hpsa_undo_allocations_after_kdump_soft_reset(h);
6960 try_soft_reset = 0;
6961 if (rc)
6962 /* don't go to clean4, we already unallocated */
6963 return -ENODEV;
6964
6965 goto reinit_after_soft_reset;
6966 }
edd16368 6967
316b221a
SC		 6968 /* Enable Accelerated IO path at driver layer */
6969 h->acciopath_status = 1;
da0697bd 6970
e863d68e 6971
edd16368
SC		 6972 /* Turn the interrupts on so we can service requests */
6973 h->access.set_intr_mask(h, HPSA_INTR_ON);
6974
339b2b14 6975 hpsa_hba_inquiry(h);
edd16368 6976 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6977
6978 /* Monitor the controller for firmware lockups */
6979 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6980 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6981 schedule_delayed_work(&h->monitor_ctlr_work,
6982 h->heartbeat_sample_interval);
88bf6d62 6983 return 0;
edd16368
SC		 6984
6985clean4:
33a2ffce 6986 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6987 hpsa_free_cmd_pool(h);
8947fd10 6988clean2_and_free_irqs:
ec501a18 6989 hpsa_free_irqs(h);
edd16368
SC		 6990clean2:
6991clean1:
080ef1cc
DB		 6992 if (h->resubmit_wq)
6993 destroy_workqueue(h->resubmit_wq);
094963da
SC		 6994 if (h->lockup_detected)
6995 free_percpu(h->lockup_detected);
edd16368 6996 kfree(h);
ecd9aad4 6997 return rc;
edd16368
SC		 6998}
6999
7000static void hpsa_flush_cache(struct ctlr_info *h)
7001{
7002 char *flush_buf;
7003 struct CommandList *c;
702890e3
SC		 7004
7005 /* Don't bother trying to flush the cache if locked up */
094963da 7006 if (unlikely(lockup_detected(h)))
702890e3 7007 return;
edd16368
SC		 7008 flush_buf = kzalloc(4, GFP_KERNEL);
7009 if (!flush_buf)
7010 return;
7011
45fcb86e 7012 c = cmd_alloc(h);
edd16368 7013 if (!c) {
45fcb86e 7014 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7015 goto out_of_memory;
7016 }
a2dac136
SC		 7017 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7018 RAID_CTLR_LUNID, TYPE_CMD)) {
7019 goto out;
7020 }
edd16368
SC		 7021 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7022 if (c->err_info->CommandStatus != 0)
a2dac136 7023out:
edd16368
SC		 7024 dev_warn(&h->pdev->dev,
7025 "error flushing cache on controller\n");
45fcb86e 7026 cmd_free(h, c);
edd16368
SC		 7027out_of_memory:
7028 kfree(flush_buf);
7029}
7030
7031static void hpsa_shutdown(struct pci_dev *pdev)
7032{
7033 struct ctlr_info *h;
7034
7035 h = pci_get_drvdata(pdev);
7036 /* Turn board interrupts off and send the flush cache command
7037 * sendcmd will turn off interrupt, and send the flush...
7038 * To write all data in the battery backed cache to disks
7039 */
7040 hpsa_flush_cache(h);
7041 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7042 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7043}
7044
6f039790 7045static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7046{
7047 int i;
7048
7049 for (i = 0; i < h->ndevices; i++)
7050 kfree(h->dev[i]);
7051}
7052
6f039790 7053static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7054{
7055 struct ctlr_info *h;
8a98db73 7056 unsigned long flags;
edd16368
SC		 7057
7058 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7059 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7060 return;
7061 }
7062 h = pci_get_drvdata(pdev);
8a98db73
SC		 7063
7064 /* Get rid of any controller monitoring work items */
7065 spin_lock_irqsave(&h->lock, flags);
7066 h->remove_in_progress = 1;
7067 cancel_delayed_work(&h->monitor_ctlr_work);
7068 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 7069 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7070 hpsa_shutdown(pdev);
080ef1cc 7071 destroy_workqueue(h->resubmit_wq);
edd16368 7072 iounmap(h->vaddr);
204892e9
SC		 7073 iounmap(h->transtable);
7074 iounmap(h->cfgtable);
55e14e76 7075 hpsa_free_device_info(h);
33a2ffce 7076 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7077 pci_free_consistent(h->pdev,
7078 h->nr_cmds * sizeof(struct CommandList),
7079 h->cmd_pool, h->cmd_pool_dhandle);
7080 pci_free_consistent(h->pdev,
7081 h->nr_cmds * sizeof(struct ErrorInfo),
7082 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7083 hpsa_free_reply_queues(h);
edd16368 7084 kfree(h->cmd_pool_bits);
303932fd 7085 kfree(h->blockFetchTable);
e1f7de0c 7086 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7087 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7088 kfree(h->hba_inquiry_data);
f0bd0b68 7089 pci_disable_device(pdev);
edd16368 7090 pci_release_regions(pdev);
094963da 7091 free_percpu(h->lockup_detected);
edd16368
SC		 7092 kfree(h);
7093}
7094
7095static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7096 __attribute__((unused)) pm_message_t state)
7097{
7098 return -ENOSYS;
7099}
7100
7101static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7102{
7103 return -ENOSYS;
7104}
7105
7106static struct pci_driver hpsa_pci_driver = {
f79cfec6 7107 .name = HPSA,
edd16368 7108 .probe = hpsa_init_one,
6f039790 7109 .remove = hpsa_remove_one,
edd16368
SC		 7110 .id_table = hpsa_pci_device_id, /* id_table */
7111 .shutdown = hpsa_shutdown,
7112 .suspend = hpsa_suspend,
7113 .resume = hpsa_resume,
7114};
7115
303932fd
DB		 7116/* Fill in bucket_map[], given nsgs (the max number of
7117 * scatter gather elements supported) and bucket[],
7118 * which is an array of 8 integers. The bucket[] array
7119 * contains 8 different DMA transfer sizes (in 16
7120 * byte increments) which the controller uses to fetch
7121 * commands. This function fills in bucket_map[], which
7122 * maps a given number of scatter gather elements to one of
7123 * the 8 DMA transfer sizes. The point of it is to allow the
7124 * controller to only do as much DMA as needed to fetch the
7125 * command, with the DMA transfer size encoded in the lower
7126 * bits of the command address.
7127 */
7128static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7129 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7130{
7131 int i, j, b, size;
7132
303932fd
DB		 7133 /* Note, bucket_map must have nsgs+1 entries. */
7134 for (i = 0; i <= nsgs; i++) {
7135 /* Compute size of a command with i SG entries */
e1f7de0c 7136 size = i + min_blocks;
303932fd
DB		 7137 b = num_buckets; /* Assume the biggest bucket */
7138 /* Find the bucket that is just big enough */
e1f7de0c 7139 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7140 if (bucket[j] >= size) {
7141 b = j;
7142 break;
7143 }
7144 }
7145 /* for a command with i SG entries, use bucket b. */
7146 bucket_map[i] = b;
7147 }
7148}
7149
e1f7de0c 7150static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7151{
6c311b57
SC		 7152 int i;
7153 unsigned long register_value;
e1f7de0c
MG		 7154 unsigned long transMethod = CFGTBL_Trans_Performant |
7155 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7156 CFGTBL_Trans_enable_directed_msix |
7157 (trans_support & (CFGTBL_Trans_io_accel1 |
7158 CFGTBL_Trans_io_accel2));
e1f7de0c 7159 struct access_method access = SA5_performant_access;
def342bd
SC		 7160
7161 /* This is a bit complicated. There are 8 registers on
7162 * the controller which we write to to tell it 8 different
7163 * sizes of commands which there may be. It's a way of
7164 * reducing the DMA done to fetch each command. Encoded into
7165 * each command's tag are 3 bits which communicate to the controller
7166 * which of the eight sizes that command fits within. The size of
7167 * each command depends on how many scatter gather entries there are.
7168 * Each SG entry requires 16 bytes. The eight registers are programmed
7169 * with the number of 16-byte blocks a command of that size requires.
7170 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7171 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7172 * blocks. Note, this only extends to the SG entries contained
7173 * within the command block, and does not extend to chained blocks
7174 * of SG elements. bft[] contains the eight values we write to
7175 * the registers. They are not evenly distributed, but have more
7176 * sizes for small commands, and fewer sizes for larger commands.
7177 */
d66ae08b 7178 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7179#define MIN_IOACCEL2_BFT_ENTRY 5
7180#define HPSA_IOACCEL2_HEADER_SZ 4
7181 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7182 13, 14, 15, 16, 17, 18, 19,
7183 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7184 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7185 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7186 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7187 16 * MIN_IOACCEL2_BFT_ENTRY);
7188 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7189 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7190 /* 5 = 1 s/g entry or 4k
7191 * 6 = 2 s/g entry or 8k
7192 * 8 = 4 s/g entry or 16k
7193 * 10 = 6 s/g entry or 24k
7194 */
303932fd 7195
b3a52e79
SC		 7196 /* If the controller supports either ioaccel method then
7197 * we can also use the RAID stack submit path that does not
7198 * perform the superfluous readl() after each command submission.
7199 */
7200 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7201 access = SA5_performant_access_no_read;
7202
303932fd 7203 /* Controller spec: zero out this buffer. */
072b0518
SC		 7204 for (i = 0; i < h->nreply_queues; i++)
7205 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7206
d66ae08b
SC		 7207 bft[7] = SG_ENTRIES_IN_CMD + 4;
7208 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7209 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7210 for (i = 0; i < 8; i++)
7211 writel(bft[i], &h->transtable->BlockFetch[i]);
7212
7213 /* size of controller ring buffer */
7214 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7215 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7216 writel(0, &h->transtable->RepQCtrAddrLow32);
7217 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7218
7219 for (i = 0; i < h->nreply_queues; i++) {
7220 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7221 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7222 &h->transtable->RepQAddr[i].lower);
7223 }
7224
b9af4937 7225 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7226 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7227 /*
7228 * enable outbound interrupt coalescing in accelerator mode;
7229 */
7230 if (trans_support & CFGTBL_Trans_io_accel1) {
7231 access = SA5_ioaccel_mode1_access;
7232 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7233 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7234 } else {
7235 if (trans_support & CFGTBL_Trans_io_accel2) {
7236 access = SA5_ioaccel_mode2_access;
7237 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7238 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7239 }
e1f7de0c 7240 }
303932fd 7241 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7242 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7243 register_value = readl(&(h->cfgtable->TransportActive));
7244 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7245 dev_err(&h->pdev->dev,
7246 "performant mode problem - transport not active\n");
303932fd
DB		 7247 return;
7248 }
960a30e7 7249 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7250 h->access = access;
7251 h->transMethod = transMethod;
7252
b9af4937
SC		 7253 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7254 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7255 return;
7256
b9af4937
SC		 7257 if (trans_support & CFGTBL_Trans_io_accel1) {
7258 /* Set up I/O accelerator mode */
7259 for (i = 0; i < h->nreply_queues; i++) {
7260 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7261 h->reply_queue[i].current_entry =
7262 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7263 }
7264 bft[7] = h->ioaccel_maxsg + 8;
7265 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7266 h->ioaccel1_blockFetchTable);
e1f7de0c 7267
b9af4937 7268 /* initialize all reply queue entries to unused */
072b0518
SC		 7269 for (i = 0; i < h->nreply_queues; i++)
7270 memset(h->reply_queue[i].head,
7271 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7272 h->reply_queue_size);
e1f7de0c 7273
b9af4937
SC		 7274 /* set all the constant fields in the accelerator command
7275 * frames once at init time to save CPU cycles later.
7276 */
7277 for (i = 0; i < h->nr_cmds; i++) {
7278 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7279
7280 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7281 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7282 (i * sizeof(struct ErrorInfo)));
7283 cp->err_info_len = sizeof(struct ErrorInfo);
7284 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7285 cp->host_context_flags =
7286 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7287 cp->timeout_sec = 0;
7288 cp->ReplyQueue = 0;
50a0decf 7289 cp->tag =
f2405db8 7290 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7291 cp->host_addr =
7292 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7293 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7294 }
7295 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7296 u64 cfg_offset, cfg_base_addr_index;
7297 u32 bft2_offset, cfg_base_addr;
7298 int rc;
7299
7300 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7301 &cfg_base_addr_index, &cfg_offset);
7302 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7303 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7304 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7305 4, h->ioaccel2_blockFetchTable);
7306 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7307 BUILD_BUG_ON(offsetof(struct CfgTable,
7308 io_accel_request_size_offset) != 0xb8);
7309 h->ioaccel2_bft2_regs =
7310 remap_pci_mem(pci_resource_start(h->pdev,
7311 cfg_base_addr_index) +
7312 cfg_offset + bft2_offset,
7313 ARRAY_SIZE(bft2) *
7314 sizeof(*h->ioaccel2_bft2_regs));
7315 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7316 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7317 }
b9af4937
SC		 7318 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7319 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7320}
7321
7322static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7323{
283b4a9b
SC		 7324 h->ioaccel_maxsg =
7325 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7326 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7327 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7328
e1f7de0c
MG		 7329 /* Command structures must be aligned on a 128-byte boundary
7330 * because the 7 lower bits of the address are used by the
7331 * hardware.
7332 */
e1f7de0c
MG		 7333 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7334 IOACCEL1_COMMANDLIST_ALIGNMENT);
7335 h->ioaccel_cmd_pool =
7336 pci_alloc_consistent(h->pdev,
7337 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7338 &(h->ioaccel_cmd_pool_dhandle));
7339
7340 h->ioaccel1_blockFetchTable =
283b4a9b 7341 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7342 sizeof(u32)), GFP_KERNEL);
7343
7344 if ((h->ioaccel_cmd_pool == NULL) ||
7345 (h->ioaccel1_blockFetchTable == NULL))
7346 goto clean_up;
7347
7348 memset(h->ioaccel_cmd_pool, 0,
7349 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7350 return 0;
7351
7352clean_up:
7353 if (h->ioaccel_cmd_pool)
7354 pci_free_consistent(h->pdev,
7355 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7356 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7357 kfree(h->ioaccel1_blockFetchTable);
7358 return 1;
6c311b57
SC		 7359}
7360
aca9012a
SC		 7361static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7362{
7363 /* Allocate ioaccel2 mode command blocks and block fetch table */
7364
7365 h->ioaccel_maxsg =
7366 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7367 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7368 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7369
aca9012a
SC		 7370 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7371 IOACCEL2_COMMANDLIST_ALIGNMENT);
7372 h->ioaccel2_cmd_pool =
7373 pci_alloc_consistent(h->pdev,
7374 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7375 &(h->ioaccel2_cmd_pool_dhandle));
7376
7377 h->ioaccel2_blockFetchTable =
7378 kmalloc(((h->ioaccel_maxsg + 1) *
7379 sizeof(u32)), GFP_KERNEL);
7380
7381 if ((h->ioaccel2_cmd_pool == NULL) ||
7382 (h->ioaccel2_blockFetchTable == NULL))
7383 goto clean_up;
7384
7385 memset(h->ioaccel2_cmd_pool, 0,
7386 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7387 return 0;
7388
7389clean_up:
7390 if (h->ioaccel2_cmd_pool)
7391 pci_free_consistent(h->pdev,
7392 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7393 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7394 kfree(h->ioaccel2_blockFetchTable);
7395 return 1;
7396}
7397
6f039790 7398static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7399{
7400 u32 trans_support;
e1f7de0c
MG		 7401 unsigned long transMethod = CFGTBL_Trans_Performant |
7402 CFGTBL_Trans_use_short_tags;
254f796b 7403 int i;
6c311b57 7404
02ec19c8
SC		 7405 if (hpsa_simple_mode)
7406 return;
7407
67c99a72 7408 trans_support = readl(&(h->cfgtable->TransportSupport));
7409 if (!(trans_support & PERFORMANT_MODE))
7410 return;
7411
e1f7de0c
MG		 7412 /* Check for I/O accelerator mode support */
7413 if (trans_support & CFGTBL_Trans_io_accel1) {
7414 transMethod |= CFGTBL_Trans_io_accel1 |
7415 CFGTBL_Trans_enable_directed_msix;
7416 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7417 goto clean_up;
aca9012a
SC		 7418 } else {
7419 if (trans_support & CFGTBL_Trans_io_accel2) {
7420 transMethod |= CFGTBL_Trans_io_accel2 |
7421 CFGTBL_Trans_enable_directed_msix;
7422 if (ioaccel2_alloc_cmds_and_bft(h))
7423 goto clean_up;
7424 }
e1f7de0c
MG		 7425 }
7426
eee0f03a 7427 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7428 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7429 /* Performant mode ring buffer and supporting data structures */
072b0518 7430 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7431
254f796b 7432 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7433 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7434 h->reply_queue_size,
7435 &(h->reply_queue[i].busaddr));
7436 if (!h->reply_queue[i].head)
7437 goto clean_up;
254f796b
MG		 7438 h->reply_queue[i].size = h->max_commands;
7439 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7440 h->reply_queue[i].current_entry = 0;
7441 }
7442
6c311b57 7443 /* Need a block fetch table for performant mode */
d66ae08b 7444 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7445 sizeof(u32)), GFP_KERNEL);
072b0518 7446 if (!h->blockFetchTable)
6c311b57
SC		 7447 goto clean_up;
7448
e1f7de0c 7449 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7450 return;
7451
7452clean_up:
072b0518 7453 hpsa_free_reply_queues(h);
303932fd
DB		 7454 kfree(h->blockFetchTable);
7455}
7456
23100dd9 7457static int is_accelerated_cmd(struct CommandList *c)
76438d08 7458{
23100dd9
SC		 7459 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7460}
7461
7462static void hpsa_drain_accel_commands(struct ctlr_info *h)
7463{
7464 struct CommandList *c = NULL;
f2405db8 7465 int i, accel_cmds_out;
281a7fd0 7466 int refcount;
76438d08 7467
f2405db8 7468 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 7469 accel_cmds_out = 0;
f2405db8 7470 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7471 c = h->cmd_pool + i;
281a7fd0
WS		 7472 refcount = atomic_inc_return(&c->refcount);
7473 if (refcount > 1) /* Command is allocated */
7474 accel_cmds_out += is_accelerated_cmd(c);
7475 cmd_free(h, c);
f2405db8 7476 }
23100dd9 7477 if (accel_cmds_out <= 0)
281a7fd0 7478 break;
76438d08
SC		 7479 msleep(100);
7480 } while (1);
7481}
7482
edd16368
SC		 7483/*
7484 * This is it. Register the PCI driver information for the cards we control
7485 * the OS will call our registered routines when it finds one of our cards.
7486 */
7487static int __init hpsa_init(void)
7488{
31468401 7489 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7490}
7491
7492static void __exit hpsa_cleanup(void)
7493{
7494 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7495}
7496
e1f7de0c
MG		 7497static void __attribute__((unused)) verify_offsets(void)
7498{
dd0e19f3
ST		 7499#define VERIFY_OFFSET(member, offset) \
7500 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7501
7502 VERIFY_OFFSET(structure_size, 0);
7503 VERIFY_OFFSET(volume_blk_size, 4);
7504 VERIFY_OFFSET(volume_blk_cnt, 8);
7505 VERIFY_OFFSET(phys_blk_shift, 16);
7506 VERIFY_OFFSET(parity_rotation_shift, 17);
7507 VERIFY_OFFSET(strip_size, 18);
7508 VERIFY_OFFSET(disk_starting_blk, 20);
7509 VERIFY_OFFSET(disk_blk_cnt, 28);
7510 VERIFY_OFFSET(data_disks_per_row, 36);
7511 VERIFY_OFFSET(metadata_disks_per_row, 38);
7512 VERIFY_OFFSET(row_cnt, 40);
7513 VERIFY_OFFSET(layout_map_count, 42);
7514 VERIFY_OFFSET(flags, 44);
7515 VERIFY_OFFSET(dekindex, 46);
7516 /* VERIFY_OFFSET(reserved, 48 */
7517 VERIFY_OFFSET(data, 64);
7518
7519#undef VERIFY_OFFSET
7520
b66cc250
MM		 7521#define VERIFY_OFFSET(member, offset) \
7522 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7523
7524 VERIFY_OFFSET(IU_type, 0);
7525 VERIFY_OFFSET(direction, 1);
7526 VERIFY_OFFSET(reply_queue, 2);
7527 /* VERIFY_OFFSET(reserved1, 3); */
7528 VERIFY_OFFSET(scsi_nexus, 4);
7529 VERIFY_OFFSET(Tag, 8);
7530 VERIFY_OFFSET(cdb, 16);
7531 VERIFY_OFFSET(cciss_lun, 32);
7532 VERIFY_OFFSET(data_len, 40);
7533 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7534 VERIFY_OFFSET(sg_count, 45);
7535 /* VERIFY_OFFSET(reserved3 */
7536 VERIFY_OFFSET(err_ptr, 48);
7537 VERIFY_OFFSET(err_len, 56);
7538 /* VERIFY_OFFSET(reserved4 */
7539 VERIFY_OFFSET(sg, 64);
7540
7541#undef VERIFY_OFFSET
7542
e1f7de0c
MG		 7543#define VERIFY_OFFSET(member, offset) \
7544 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7545
7546 VERIFY_OFFSET(dev_handle, 0x00);
7547 VERIFY_OFFSET(reserved1, 0x02);
7548 VERIFY_OFFSET(function, 0x03);
7549 VERIFY_OFFSET(reserved2, 0x04);
7550 VERIFY_OFFSET(err_info, 0x0C);
7551 VERIFY_OFFSET(reserved3, 0x10);
7552 VERIFY_OFFSET(err_info_len, 0x12);
7553 VERIFY_OFFSET(reserved4, 0x13);
7554 VERIFY_OFFSET(sgl_offset, 0x14);
7555 VERIFY_OFFSET(reserved5, 0x15);
7556 VERIFY_OFFSET(transfer_len, 0x1C);
7557 VERIFY_OFFSET(reserved6, 0x20);
7558 VERIFY_OFFSET(io_flags, 0x24);
7559 VERIFY_OFFSET(reserved7, 0x26);
7560 VERIFY_OFFSET(LUN, 0x34);
7561 VERIFY_OFFSET(control, 0x3C);
7562 VERIFY_OFFSET(CDB, 0x40);
7563 VERIFY_OFFSET(reserved8, 0x50);
7564 VERIFY_OFFSET(host_context_flags, 0x60);
7565 VERIFY_OFFSET(timeout_sec, 0x62);
7566 VERIFY_OFFSET(ReplyQueue, 0x64);
7567 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7568 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7569 VERIFY_OFFSET(host_addr, 0x70);
7570 VERIFY_OFFSET(CISS_LUN, 0x78);
7571 VERIFY_OFFSET(SG, 0x78 + 8);
7572#undef VERIFY_OFFSET
7573}
7574
edd16368
SC		 7575module_init(hpsa_init);
7576module_exit(hpsa_cleanup);
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