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[SCSI] hpsa: add ioaccell mode 1 RAID offload support.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
edd16368 223
edd16368
SC		 224static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
225{
226 unsigned long *priv = shost_priv(sdev->host);
227 return (struct ctlr_info *) *priv;
228}
229
a23513e8
SC		 230static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
231{
232 unsigned long *priv = shost_priv(sh);
233 return (struct ctlr_info *) *priv;
234}
235
edd16368
SC		 236static int check_for_unit_attention(struct ctlr_info *h,
237 struct CommandList *c)
238{
239 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
240 return 0;
241
242 switch (c->err_info->SenseInfo[12]) {
243 case STATE_CHANGED:
f79cfec6 244 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 245 "detected, command retried\n", h->ctlr);
246 break;
247 case LUN_FAILED:
f79cfec6 248 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 249 "detected, action required\n", h->ctlr);
250 break;
251 case REPORT_LUNS_CHANGED:
f79cfec6 252 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 253 "changed, action required\n", h->ctlr);
edd16368 254 /*
4f4eb9f1
ST		 255 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
256 * target (array) devices.
edd16368
SC		 257 */
258 break;
259 case POWER_OR_RESET:
f79cfec6 260 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 261 "or device reset detected\n", h->ctlr);
262 break;
263 case UNIT_ATTENTION_CLEARED:
f79cfec6 264 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 265 "cleared by another initiator\n", h->ctlr);
266 break;
267 default:
f79cfec6 268 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 269 "unit attention detected\n", h->ctlr);
270 break;
271 }
272 return 1;
273}
274
852af20a
MB		 275static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
276{
277 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
278 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
279 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
280 return 0;
281 dev_warn(&h->pdev->dev, HPSA "device busy");
282 return 1;
283}
284
edd16368
SC		 285static ssize_t host_store_rescan(struct device *dev,
286 struct device_attribute *attr,
287 const char *buf, size_t count)
288{
289 struct ctlr_info *h;
290 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 291 h = shost_to_hba(shost);
31468401 292 hpsa_scan_start(h->scsi_host);
edd16368
SC		 293 return count;
294}
295
d28ce020
SC		 296static ssize_t host_show_firmware_revision(struct device *dev,
297 struct device_attribute *attr, char *buf)
298{
299 struct ctlr_info *h;
300 struct Scsi_Host *shost = class_to_shost(dev);
301 unsigned char *fwrev;
302
303 h = shost_to_hba(shost);
304 if (!h->hba_inquiry_data)
305 return 0;
306 fwrev = &h->hba_inquiry_data[32];
307 return snprintf(buf, 20, "%c%c%c%c\n",
308 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
309}
310
94a13649
SC		 311static ssize_t host_show_commands_outstanding(struct device *dev,
312 struct device_attribute *attr, char *buf)
313{
314 struct Scsi_Host *shost = class_to_shost(dev);
315 struct ctlr_info *h = shost_to_hba(shost);
316
317 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
318}
319
745a7a25
SC		 320static ssize_t host_show_transport_mode(struct device *dev,
321 struct device_attribute *attr, char *buf)
322{
323 struct ctlr_info *h;
324 struct Scsi_Host *shost = class_to_shost(dev);
325
326 h = shost_to_hba(shost);
327 return snprintf(buf, 20, "%s\n",
960a30e7 328 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 329 "performant" : "simple");
330}
331
46380786 332/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 333static u32 unresettable_controller[] = {
334 0x324a103C, /* Smart Array P712m */
335 0x324b103C, /* SmartArray P711m */
336 0x3223103C, /* Smart Array P800 */
337 0x3234103C, /* Smart Array P400 */
338 0x3235103C, /* Smart Array P400i */
339 0x3211103C, /* Smart Array E200i */
340 0x3212103C, /* Smart Array E200 */
341 0x3213103C, /* Smart Array E200i */
342 0x3214103C, /* Smart Array E200i */
343 0x3215103C, /* Smart Array E200i */
344 0x3237103C, /* Smart Array E500 */
345 0x323D103C, /* Smart Array P700m */
7af0abbc 346 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 347 0x409C0E11, /* Smart Array 6400 */
348 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 349 0x40700E11, /* Smart Array 5300 */
350 0x40820E11, /* Smart Array 532 */
351 0x40830E11, /* Smart Array 5312 */
352 0x409A0E11, /* Smart Array 641 */
353 0x409B0E11, /* Smart Array 642 */
354 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 355};
356
46380786
SC		 357/* List of controllers which cannot even be soft reset */
358static u32 soft_unresettable_controller[] = {
7af0abbc 359 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 360 0x40700E11, /* Smart Array 5300 */
361 0x40820E11, /* Smart Array 532 */
362 0x40830E11, /* Smart Array 5312 */
363 0x409A0E11, /* Smart Array 641 */
364 0x409B0E11, /* Smart Array 642 */
365 0x40910E11, /* Smart Array 6i */
46380786
SC		 366 /* Exclude 640x boards. These are two pci devices in one slot
367 * which share a battery backed cache module. One controls the
368 * cache, the other accesses the cache through the one that controls
369 * it. If we reset the one controlling the cache, the other will
370 * likely not be happy. Just forbid resetting this conjoined mess.
371 * The 640x isn't really supported by hpsa anyway.
372 */
373 0x409C0E11, /* Smart Array 6400 */
374 0x409D0E11, /* Smart Array 6400 EM */
375};
376
377static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 378{
379 int i;
380
381 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 382 if (unresettable_controller[i] == board_id)
383 return 0;
384 return 1;
385}
386
387static int ctlr_is_soft_resettable(u32 board_id)
388{
389 int i;
390
391 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
392 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 393 return 0;
394 return 1;
395}
396
46380786
SC		 397static int ctlr_is_resettable(u32 board_id)
398{
399 return ctlr_is_hard_resettable(board_id) ||
400 ctlr_is_soft_resettable(board_id);
401}
402
941b1cda
SC		 403static ssize_t host_show_resettable(struct device *dev,
404 struct device_attribute *attr, char *buf)
405{
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408
409 h = shost_to_hba(shost);
46380786 410 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 411}
412
edd16368
SC		 413static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
414{
415 return (scsi3addr[3] & 0xC0) == 0x40;
416}
417
418static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 419 "1(ADM)", "UNKNOWN"
edd16368
SC		 420};
421#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
422
423static ssize_t raid_level_show(struct device *dev,
424 struct device_attribute *attr, char *buf)
425{
426 ssize_t l = 0;
82a72c0a 427 unsigned char rlevel;
edd16368
SC		 428 struct ctlr_info *h;
429 struct scsi_device *sdev;
430 struct hpsa_scsi_dev_t *hdev;
431 unsigned long flags;
432
433 sdev = to_scsi_device(dev);
434 h = sdev_to_hba(sdev);
435 spin_lock_irqsave(&h->lock, flags);
436 hdev = sdev->hostdata;
437 if (!hdev) {
438 spin_unlock_irqrestore(&h->lock, flags);
439 return -ENODEV;
440 }
441
442 /* Is this even a logical drive? */
443 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
444 spin_unlock_irqrestore(&h->lock, flags);
445 l = snprintf(buf, PAGE_SIZE, "N/A\n");
446 return l;
447 }
448
449 rlevel = hdev->raid_level;
450 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 451 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 452 rlevel = RAID_UNKNOWN;
453 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
454 return l;
455}
456
457static ssize_t lunid_show(struct device *dev,
458 struct device_attribute *attr, char *buf)
459{
460 struct ctlr_info *h;
461 struct scsi_device *sdev;
462 struct hpsa_scsi_dev_t *hdev;
463 unsigned long flags;
464 unsigned char lunid[8];
465
466 sdev = to_scsi_device(dev);
467 h = sdev_to_hba(sdev);
468 spin_lock_irqsave(&h->lock, flags);
469 hdev = sdev->hostdata;
470 if (!hdev) {
471 spin_unlock_irqrestore(&h->lock, flags);
472 return -ENODEV;
473 }
474 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
475 spin_unlock_irqrestore(&h->lock, flags);
476 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
477 lunid[0], lunid[1], lunid[2], lunid[3],
478 lunid[4], lunid[5], lunid[6], lunid[7]);
479}
480
481static ssize_t unique_id_show(struct device *dev,
482 struct device_attribute *attr, char *buf)
483{
484 struct ctlr_info *h;
485 struct scsi_device *sdev;
486 struct hpsa_scsi_dev_t *hdev;
487 unsigned long flags;
488 unsigned char sn[16];
489
490 sdev = to_scsi_device(dev);
491 h = sdev_to_hba(sdev);
492 spin_lock_irqsave(&h->lock, flags);
493 hdev = sdev->hostdata;
494 if (!hdev) {
495 spin_unlock_irqrestore(&h->lock, flags);
496 return -ENODEV;
497 }
498 memcpy(sn, hdev->device_id, sizeof(sn));
499 spin_unlock_irqrestore(&h->lock, flags);
500 return snprintf(buf, 16 * 2 + 2,
501 "%02X%02X%02X%02X%02X%02X%02X%02X"
502 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
503 sn[0], sn[1], sn[2], sn[3],
504 sn[4], sn[5], sn[6], sn[7],
505 sn[8], sn[9], sn[10], sn[11],
506 sn[12], sn[13], sn[14], sn[15]);
507}
508
3f5eac3a
SC		 509static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
510static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
511static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
512static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
513static DEVICE_ATTR(firmware_revision, S_IRUGO,
514 host_show_firmware_revision, NULL);
515static DEVICE_ATTR(commands_outstanding, S_IRUGO,
516 host_show_commands_outstanding, NULL);
517static DEVICE_ATTR(transport_mode, S_IRUGO,
518 host_show_transport_mode, NULL);
941b1cda
SC		 519static DEVICE_ATTR(resettable, S_IRUGO,
520 host_show_resettable, NULL);
3f5eac3a
SC		 521
522static struct device_attribute *hpsa_sdev_attrs[] = {
523 &dev_attr_raid_level,
524 &dev_attr_lunid,
525 &dev_attr_unique_id,
526 NULL,
527};
528
529static struct device_attribute *hpsa_shost_attrs[] = {
530 &dev_attr_rescan,
531 &dev_attr_firmware_revision,
532 &dev_attr_commands_outstanding,
533 &dev_attr_transport_mode,
941b1cda 534 &dev_attr_resettable,
3f5eac3a
SC		 535 NULL,
536};
537
538static struct scsi_host_template hpsa_driver_template = {
539 .module = THIS_MODULE,
f79cfec6
SC		 540 .name = HPSA,
541 .proc_name = HPSA,
3f5eac3a
SC		 542 .queuecommand = hpsa_scsi_queue_command,
543 .scan_start = hpsa_scan_start,
544 .scan_finished = hpsa_scan_finished,
545 .change_queue_depth = hpsa_change_queue_depth,
546 .this_id = -1,
547 .use_clustering = ENABLE_CLUSTERING,
75167d2c 548 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 549 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
550 .ioctl = hpsa_ioctl,
551 .slave_alloc = hpsa_slave_alloc,
552 .slave_destroy = hpsa_slave_destroy,
553#ifdef CONFIG_COMPAT
554 .compat_ioctl = hpsa_compat_ioctl,
555#endif
556 .sdev_attrs = hpsa_sdev_attrs,
557 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 558 .max_sectors = 8192,
54b2b50c 559 .no_write_same = 1,
3f5eac3a
SC		 560};
561
562
563/* Enqueuing and dequeuing functions for cmdlists. */
564static inline void addQ(struct list_head *list, struct CommandList *c)
565{
566 list_add_tail(&c->list, list);
567}
568
254f796b 569static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 570{
571 u32 a;
254f796b 572 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 573 unsigned long flags;
3f5eac3a 574
e1f7de0c
MG		 575 if (h->transMethod & CFGTBL_Trans_io_accel1)
576 return h->access.command_completed(h, q);
577
3f5eac3a 578 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 579 return h->access.command_completed(h, q);
3f5eac3a 580
254f796b
MG		 581 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
582 a = rq->head[rq->current_entry];
583 rq->current_entry++;
e16a33ad 584 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 585 h->commands_outstanding--;
e16a33ad 586 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 587 } else {
588 a = FIFO_EMPTY;
589 }
590 /* Check for wraparound */
254f796b
MG		 591 if (rq->current_entry == h->max_commands) {
592 rq->current_entry = 0;
593 rq->wraparound ^= 1;
3f5eac3a
SC		 594 }
595 return a;
596}
597
598/* set_performant_mode: Modify the tag for cciss performant
599 * set bit 0 for pull model, bits 3-1 for block fetch
600 * register number
601 */
602static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
603{
254f796b 604 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 605 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 606 if (likely(h->msix_vector > 0))
254f796b 607 c->Header.ReplyQueue =
804a5cb5 608 raw_smp_processor_id() % h->nreply_queues;
254f796b 609 }
3f5eac3a
SC		 610}
611
e85c5974
SC		 612static int is_firmware_flash_cmd(u8 *cdb)
613{
614 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
615}
616
617/*
618 * During firmware flash, the heartbeat register may not update as frequently
619 * as it should. So we dial down lockup detection during firmware flash. and
620 * dial it back up when firmware flash completes.
621 */
622#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
623#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
624static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
625 struct CommandList *c)
626{
627 if (!is_firmware_flash_cmd(c->Request.CDB))
628 return;
629 atomic_inc(&h->firmware_flash_in_progress);
630 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
631}
632
633static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
634 struct CommandList *c)
635{
636 if (is_firmware_flash_cmd(c->Request.CDB) &&
637 atomic_dec_and_test(&h->firmware_flash_in_progress))
638 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
639}
640
3f5eac3a
SC		 641static void enqueue_cmd_and_start_io(struct ctlr_info *h,
642 struct CommandList *c)
643{
644 unsigned long flags;
645
646 set_performant_mode(h, c);
e85c5974 647 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 648 spin_lock_irqsave(&h->lock, flags);
649 addQ(&h->reqQ, c);
650 h->Qdepth++;
3f5eac3a 651 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 652 start_io(h);
3f5eac3a
SC		 653}
654
655static inline void removeQ(struct CommandList *c)
656{
657 if (WARN_ON(list_empty(&c->list)))
658 return;
659 list_del_init(&c->list);
660}
661
662static inline int is_hba_lunid(unsigned char scsi3addr[])
663{
664 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
665}
666
667static inline int is_scsi_rev_5(struct ctlr_info *h)
668{
669 if (!h->hba_inquiry_data)
670 return 0;
671 if ((h->hba_inquiry_data[2] & 0x07) == 5)
672 return 1;
673 return 0;
674}
675
edd16368
SC		 676static int hpsa_find_target_lun(struct ctlr_info *h,
677 unsigned char scsi3addr[], int bus, int *target, int *lun)
678{
679 /* finds an unused bus, target, lun for a new physical device
680 * assumes h->devlock is held
681 */
682 int i, found = 0;
cfe5badc 683 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 684
263d9401 685 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 686
687 for (i = 0; i < h->ndevices; i++) {
688 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 689 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 690 }
691
263d9401
AM		 692 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
693 if (i < HPSA_MAX_DEVICES) {
694 /* *bus = 1; */
695 *target = i;
696 *lun = 0;
697 found = 1;
edd16368
SC		 698 }
699 return !found;
700}
701
702/* Add an entry into h->dev[] array. */
703static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
704 struct hpsa_scsi_dev_t *device,
705 struct hpsa_scsi_dev_t *added[], int *nadded)
706{
707 /* assumes h->devlock is held */
708 int n = h->ndevices;
709 int i;
710 unsigned char addr1[8], addr2[8];
711 struct hpsa_scsi_dev_t *sd;
712
cfe5badc 713 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 714 dev_err(&h->pdev->dev, "too many devices, some will be "
715 "inaccessible.\n");
716 return -1;
717 }
718
719 /* physical devices do not have lun or target assigned until now. */
720 if (device->lun != -1)
721 /* Logical device, lun is already assigned. */
722 goto lun_assigned;
723
724 /* If this device a non-zero lun of a multi-lun device
725 * byte 4 of the 8-byte LUN addr will contain the logical
726 * unit no, zero otherise.
727 */
728 if (device->scsi3addr[4] == 0) {
729 /* This is not a non-zero lun of a multi-lun device */
730 if (hpsa_find_target_lun(h, device->scsi3addr,
731 device->bus, &device->target, &device->lun) != 0)
732 return -1;
733 goto lun_assigned;
734 }
735
736 /* This is a non-zero lun of a multi-lun device.
737 * Search through our list and find the device which
738 * has the same 8 byte LUN address, excepting byte 4.
739 * Assign the same bus and target for this new LUN.
740 * Use the logical unit number from the firmware.
741 */
742 memcpy(addr1, device->scsi3addr, 8);
743 addr1[4] = 0;
744 for (i = 0; i < n; i++) {
745 sd = h->dev[i];
746 memcpy(addr2, sd->scsi3addr, 8);
747 addr2[4] = 0;
748 /* differ only in byte 4? */
749 if (memcmp(addr1, addr2, 8) == 0) {
750 device->bus = sd->bus;
751 device->target = sd->target;
752 device->lun = device->scsi3addr[4];
753 break;
754 }
755 }
756 if (device->lun == -1) {
757 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
758 " suspect firmware bug or unsupported hardware "
759 "configuration.\n");
760 return -1;
761 }
762
763lun_assigned:
764
765 h->dev[n] = device;
766 h->ndevices++;
767 added[*nadded] = device;
768 (*nadded)++;
769
770 /* initially, (before registering with scsi layer) we don't
771 * know our hostno and we don't want to print anything first
772 * time anyway (the scsi layer's inquiries will show that info)
773 */
774 /* if (hostno != -1) */
775 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
776 scsi_device_type(device->devtype), hostno,
777 device->bus, device->target, device->lun);
778 return 0;
779}
780
bd9244f7
ST		 781/* Update an entry in h->dev[] array. */
782static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
783 int entry, struct hpsa_scsi_dev_t *new_entry)
784{
785 /* assumes h->devlock is held */
786 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
787
788 /* Raid level changed. */
789 h->dev[entry]->raid_level = new_entry->raid_level;
790 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
791 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
792 new_entry->target, new_entry->lun);
793}
794
2a8ccf31
SC		 795/* Replace an entry from h->dev[] array. */
796static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
797 int entry, struct hpsa_scsi_dev_t *new_entry,
798 struct hpsa_scsi_dev_t *added[], int *nadded,
799 struct hpsa_scsi_dev_t *removed[], int *nremoved)
800{
801 /* assumes h->devlock is held */
cfe5badc 802 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 803 removed[*nremoved] = h->dev[entry];
804 (*nremoved)++;
01350d05
SC		 805
806 /*
807 * New physical devices won't have target/lun assigned yet
808 * so we need to preserve the values in the slot we are replacing.
809 */
810 if (new_entry->target == -1) {
811 new_entry->target = h->dev[entry]->target;
812 new_entry->lun = h->dev[entry]->lun;
813 }
814
2a8ccf31
SC		 815 h->dev[entry] = new_entry;
816 added[*nadded] = new_entry;
817 (*nadded)++;
818 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
819 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
820 new_entry->target, new_entry->lun);
821}
822
edd16368
SC		 823/* Remove an entry from h->dev[] array. */
824static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
825 struct hpsa_scsi_dev_t *removed[], int *nremoved)
826{
827 /* assumes h->devlock is held */
828 int i;
829 struct hpsa_scsi_dev_t *sd;
830
cfe5badc 831 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 832
833 sd = h->dev[entry];
834 removed[*nremoved] = h->dev[entry];
835 (*nremoved)++;
836
837 for (i = entry; i < h->ndevices-1; i++)
838 h->dev[i] = h->dev[i+1];
839 h->ndevices--;
840 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
841 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
842 sd->lun);
843}
844
845#define SCSI3ADDR_EQ(a, b) ( \
846 (a)[7] == (b)[7] && \
847 (a)[6] == (b)[6] && \
848 (a)[5] == (b)[5] && \
849 (a)[4] == (b)[4] && \
850 (a)[3] == (b)[3] && \
851 (a)[2] == (b)[2] && \
852 (a)[1] == (b)[1] && \
853 (a)[0] == (b)[0])
854
855static void fixup_botched_add(struct ctlr_info *h,
856 struct hpsa_scsi_dev_t *added)
857{
858 /* called when scsi_add_device fails in order to re-adjust
859 * h->dev[] to match the mid layer's view.
860 */
861 unsigned long flags;
862 int i, j;
863
864 spin_lock_irqsave(&h->lock, flags);
865 for (i = 0; i < h->ndevices; i++) {
866 if (h->dev[i] == added) {
867 for (j = i; j < h->ndevices-1; j++)
868 h->dev[j] = h->dev[j+1];
869 h->ndevices--;
870 break;
871 }
872 }
873 spin_unlock_irqrestore(&h->lock, flags);
874 kfree(added);
875}
876
877static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
878 struct hpsa_scsi_dev_t *dev2)
879{
edd16368
SC		 880 /* we compare everything except lun and target as these
881 * are not yet assigned. Compare parts likely
882 * to differ first
883 */
884 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
885 sizeof(dev1->scsi3addr)) != 0)
886 return 0;
887 if (memcmp(dev1->device_id, dev2->device_id,
888 sizeof(dev1->device_id)) != 0)
889 return 0;
890 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
891 return 0;
892 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
893 return 0;
edd16368
SC		 894 if (dev1->devtype != dev2->devtype)
895 return 0;
edd16368
SC		 896 if (dev1->bus != dev2->bus)
897 return 0;
898 return 1;
899}
900
bd9244f7
ST		 901static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
902 struct hpsa_scsi_dev_t *dev2)
903{
904 /* Device attributes that can change, but don't mean
905 * that the device is a different device, nor that the OS
906 * needs to be told anything about the change.
907 */
908 if (dev1->raid_level != dev2->raid_level)
909 return 1;
910 return 0;
911}
912
edd16368
SC		 913/* Find needle in haystack. If exact match found, return DEVICE_SAME,
914 * and return needle location in *index. If scsi3addr matches, but not
915 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 916 * location in *index.
917 * In the case of a minor device attribute change, such as RAID level, just
918 * return DEVICE_UPDATED, along with the updated device's location in index.
919 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 920 */
921static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
922 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
923 int *index)
924{
925 int i;
926#define DEVICE_NOT_FOUND 0
927#define DEVICE_CHANGED 1
928#define DEVICE_SAME 2
bd9244f7 929#define DEVICE_UPDATED 3
edd16368 930 for (i = 0; i < haystack_size; i++) {
23231048
SC		 931 if (haystack[i] == NULL) /* previously removed. */
932 continue;
edd16368
SC		 933 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
934 *index = i;
bd9244f7
ST		 935 if (device_is_the_same(needle, haystack[i])) {
936 if (device_updated(needle, haystack[i]))
937 return DEVICE_UPDATED;
edd16368 938 return DEVICE_SAME;
bd9244f7 939 } else {
edd16368 940 return DEVICE_CHANGED;
bd9244f7 941 }
edd16368
SC		 942 }
943 }
944 *index = -1;
945 return DEVICE_NOT_FOUND;
946}
947
4967bd3e 948static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 949 struct hpsa_scsi_dev_t *sd[], int nsds)
950{
951 /* sd contains scsi3 addresses and devtypes, and inquiry
952 * data. This function takes what's in sd to be the current
953 * reality and updates h->dev[] to reflect that reality.
954 */
955 int i, entry, device_change, changes = 0;
956 struct hpsa_scsi_dev_t *csd;
957 unsigned long flags;
958 struct hpsa_scsi_dev_t **added, **removed;
959 int nadded, nremoved;
960 struct Scsi_Host *sh = NULL;
961
cfe5badc
ST		 962 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
963 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 964
965 if (!added || !removed) {
966 dev_warn(&h->pdev->dev, "out of memory in "
967 "adjust_hpsa_scsi_table\n");
968 goto free_and_out;
969 }
970
971 spin_lock_irqsave(&h->devlock, flags);
972
973 /* find any devices in h->dev[] that are not in
974 * sd[] and remove them from h->dev[], and for any
975 * devices which have changed, remove the old device
976 * info and add the new device info.
bd9244f7
ST		 977 * If minor device attributes change, just update
978 * the existing device structure.
edd16368
SC		 979 */
980 i = 0;
981 nremoved = 0;
982 nadded = 0;
983 while (i < h->ndevices) {
984 csd = h->dev[i];
985 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
986 if (device_change == DEVICE_NOT_FOUND) {
987 changes++;
988 hpsa_scsi_remove_entry(h, hostno, i,
989 removed, &nremoved);
990 continue; /* remove ^^^, hence i not incremented */
991 } else if (device_change == DEVICE_CHANGED) {
992 changes++;
2a8ccf31
SC		 993 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
994 added, &nadded, removed, &nremoved);
c7f172dc
SC		 995 /* Set it to NULL to prevent it from being freed
996 * at the bottom of hpsa_update_scsi_devices()
997 */
998 sd[entry] = NULL;
bd9244f7
ST		 999 } else if (device_change == DEVICE_UPDATED) {
1000 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1001 }
1002 i++;
1003 }
1004
1005 /* Now, make sure every device listed in sd[] is also
1006 * listed in h->dev[], adding them if they aren't found
1007 */
1008
1009 for (i = 0; i < nsds; i++) {
1010 if (!sd[i]) /* if already added above. */
1011 continue;
1012 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1013 h->ndevices, &entry);
1014 if (device_change == DEVICE_NOT_FOUND) {
1015 changes++;
1016 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1017 added, &nadded) != 0)
1018 break;
1019 sd[i] = NULL; /* prevent from being freed later. */
1020 } else if (device_change == DEVICE_CHANGED) {
1021 /* should never happen... */
1022 changes++;
1023 dev_warn(&h->pdev->dev,
1024 "device unexpectedly changed.\n");
1025 /* but if it does happen, we just ignore that device */
1026 }
1027 }
1028 spin_unlock_irqrestore(&h->devlock, flags);
1029
1030 /* Don't notify scsi mid layer of any changes the first time through
1031 * (or if there are no changes) scsi_scan_host will do it later the
1032 * first time through.
1033 */
1034 if (hostno == -1 || !changes)
1035 goto free_and_out;
1036
1037 sh = h->scsi_host;
1038 /* Notify scsi mid layer of any removed devices */
1039 for (i = 0; i < nremoved; i++) {
1040 struct scsi_device *sdev =
1041 scsi_device_lookup(sh, removed[i]->bus,
1042 removed[i]->target, removed[i]->lun);
1043 if (sdev != NULL) {
1044 scsi_remove_device(sdev);
1045 scsi_device_put(sdev);
1046 } else {
1047 /* We don't expect to get here.
1048 * future cmds to this device will get selection
1049 * timeout as if the device was gone.
1050 */
1051 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1052 " for removal.", hostno, removed[i]->bus,
1053 removed[i]->target, removed[i]->lun);
1054 }
1055 kfree(removed[i]);
1056 removed[i] = NULL;
1057 }
1058
1059 /* Notify scsi mid layer of any added devices */
1060 for (i = 0; i < nadded; i++) {
1061 if (scsi_add_device(sh, added[i]->bus,
1062 added[i]->target, added[i]->lun) == 0)
1063 continue;
1064 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1065 "device not added.\n", hostno, added[i]->bus,
1066 added[i]->target, added[i]->lun);
1067 /* now we have to remove it from h->dev,
1068 * since it didn't get added to scsi mid layer
1069 */
1070 fixup_botched_add(h, added[i]);
1071 }
1072
1073free_and_out:
1074 kfree(added);
1075 kfree(removed);
edd16368
SC		 1076}
1077
1078/*
9e03aa2f 1079 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1080 * Assume's h->devlock is held.
1081 */
1082static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1083 int bus, int target, int lun)
1084{
1085 int i;
1086 struct hpsa_scsi_dev_t *sd;
1087
1088 for (i = 0; i < h->ndevices; i++) {
1089 sd = h->dev[i];
1090 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1091 return sd;
1092 }
1093 return NULL;
1094}
1095
1096/* link sdev->hostdata to our per-device structure. */
1097static int hpsa_slave_alloc(struct scsi_device *sdev)
1098{
1099 struct hpsa_scsi_dev_t *sd;
1100 unsigned long flags;
1101 struct ctlr_info *h;
1102
1103 h = sdev_to_hba(sdev);
1104 spin_lock_irqsave(&h->devlock, flags);
1105 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1106 sdev_id(sdev), sdev->lun);
1107 if (sd != NULL)
1108 sdev->hostdata = sd;
1109 spin_unlock_irqrestore(&h->devlock, flags);
1110 return 0;
1111}
1112
1113static void hpsa_slave_destroy(struct scsi_device *sdev)
1114{
bcc44255 1115 /* nothing to do. */
edd16368
SC		 1116}
1117
33a2ffce
SC		 1118static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1119{
1120 int i;
1121
1122 if (!h->cmd_sg_list)
1123 return;
1124 for (i = 0; i < h->nr_cmds; i++) {
1125 kfree(h->cmd_sg_list[i]);
1126 h->cmd_sg_list[i] = NULL;
1127 }
1128 kfree(h->cmd_sg_list);
1129 h->cmd_sg_list = NULL;
1130}
1131
1132static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1133{
1134 int i;
1135
1136 if (h->chainsize <= 0)
1137 return 0;
1138
1139 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1140 GFP_KERNEL);
1141 if (!h->cmd_sg_list)
1142 return -ENOMEM;
1143 for (i = 0; i < h->nr_cmds; i++) {
1144 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1145 h->chainsize, GFP_KERNEL);
1146 if (!h->cmd_sg_list[i])
1147 goto clean;
1148 }
1149 return 0;
1150
1151clean:
1152 hpsa_free_sg_chain_blocks(h);
1153 return -ENOMEM;
1154}
1155
e2bea6df 1156static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1157 struct CommandList *c)
1158{
1159 struct SGDescriptor *chain_sg, *chain_block;
1160 u64 temp64;
1161
1162 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1163 chain_block = h->cmd_sg_list[c->cmdindex];
1164 chain_sg->Ext = HPSA_SG_CHAIN;
1165 chain_sg->Len = sizeof(*chain_sg) *
1166 (c->Header.SGTotal - h->max_cmd_sg_entries);
1167 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1168 PCI_DMA_TODEVICE);
e2bea6df
SC		 1169 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1170 /* prevent subsequent unmapping */
1171 chain_sg->Addr.lower = 0;
1172 chain_sg->Addr.upper = 0;
1173 return -1;
1174 }
33a2ffce
SC		 1175 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1176 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1177 return 0;
33a2ffce
SC		 1178}
1179
1180static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1181 struct CommandList *c)
1182{
1183 struct SGDescriptor *chain_sg;
1184 union u64bit temp64;
1185
1186 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1187 return;
1188
1189 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1190 temp64.val32.lower = chain_sg->Addr.lower;
1191 temp64.val32.upper = chain_sg->Addr.upper;
1192 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1193}
1194
1fb011fb 1195static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1196{
1197 struct scsi_cmnd *cmd;
1198 struct ctlr_info *h;
1199 struct ErrorInfo *ei;
283b4a9b 1200 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1201
1202 unsigned char sense_key;
1203 unsigned char asc; /* additional sense code */
1204 unsigned char ascq; /* additional sense code qualifier */
db111e18 1205 unsigned long sense_data_size;
edd16368
SC		 1206
1207 ei = cp->err_info;
1208 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1209 h = cp->h;
283b4a9b 1210 dev = cmd->device->hostdata;
edd16368
SC		 1211
1212 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1213 if ((cp->cmd_type == CMD_SCSI) &&
1214 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1215 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1216
1217 cmd->result = (DID_OK << 16); /* host byte */
1218 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
5512672f 1219 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1220
1221 /* copy the sense data whether we need to or not. */
db111e18
SC		 1222 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1223 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1224 else
1225 sense_data_size = sizeof(ei->SenseInfo);
1226 if (ei->SenseLen < sense_data_size)
1227 sense_data_size = ei->SenseLen;
1228
1229 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1230 scsi_set_resid(cmd, ei->ResidualCnt);
1231
1232 if (ei->CommandStatus == 0) {
edd16368 1233 cmd_free(h, cp);
2cc5bfaf 1234 cmd->scsi_done(cmd);
edd16368
SC		 1235 return;
1236 }
1237
e1f7de0c
MG		 1238 /* For I/O accelerator commands, copy over some fields to the normal
1239 * CISS header used below for error handling.
1240 */
1241 if (cp->cmd_type == CMD_IOACCEL1) {
1242 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1243 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1244 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1245 cp->Header.Tag.lower = c->Tag.lower;
1246 cp->Header.Tag.upper = c->Tag.upper;
1247 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1248 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1249
1250 /* Any RAID offload error results in retry which will use
1251 * the normal I/O path so the controller can handle whatever's
1252 * wrong.
1253 */
1254 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1255 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1256 dev->offload_enabled = 0;
1257 cmd->result = DID_SOFT_ERROR << 16;
1258 cmd_free(h, cp);
1259 cmd->scsi_done(cmd);
1260 return;
1261 }
e1f7de0c
MG		 1262 }
1263
edd16368
SC		 1264 /* an error has occurred */
1265 switch (ei->CommandStatus) {
1266
1267 case CMD_TARGET_STATUS:
1268 if (ei->ScsiStatus) {
1269 /* Get sense key */
1270 sense_key = 0xf & ei->SenseInfo[2];
1271 /* Get additional sense code */
1272 asc = ei->SenseInfo[12];
1273 /* Get addition sense code qualifier */
1274 ascq = ei->SenseInfo[13];
1275 }
1276
1277 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1278 if (check_for_unit_attention(h, cp))
edd16368 1279 break;
edd16368
SC		 1280 if (sense_key == ILLEGAL_REQUEST) {
1281 /*
1282 * SCSI REPORT_LUNS is commonly unsupported on
1283 * Smart Array. Suppress noisy complaint.
1284 */
1285 if (cp->Request.CDB[0] == REPORT_LUNS)
1286 break;
1287
1288 /* If ASC/ASCQ indicate Logical Unit
1289 * Not Supported condition,
1290 */
1291 if ((asc == 0x25) && (ascq == 0x0)) {
1292 dev_warn(&h->pdev->dev, "cp %p "
1293 "has check condition\n", cp);
1294 break;
1295 }
1296 }
1297
1298 if (sense_key == NOT_READY) {
1299 /* If Sense is Not Ready, Logical Unit
1300 * Not ready, Manual Intervention
1301 * required
1302 */
1303 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1304 dev_warn(&h->pdev->dev, "cp %p "
1305 "has check condition: unit "
1306 "not ready, manual "
1307 "intervention required\n", cp);
1308 break;
1309 }
1310 }
1d3b3609
MG		 1311 if (sense_key == ABORTED_COMMAND) {
1312 /* Aborted command is retryable */
1313 dev_warn(&h->pdev->dev, "cp %p "
1314 "has check condition: aborted command: "
1315 "ASC: 0x%x, ASCQ: 0x%x\n",
1316 cp, asc, ascq);
2e311fba 1317 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1318 break;
1319 }
edd16368 1320 /* Must be some other type of check condition */
21b8e4ef 1321 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1322 "unknown type: "
1323 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1324 "Returning result: 0x%x, "
1325 "cmd=[%02x %02x %02x %02x %02x "
807be732 1326 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1327 "%02x %02x %02x %02x %02x]\n",
1328 cp, sense_key, asc, ascq,
1329 cmd->result,
1330 cmd->cmnd[0], cmd->cmnd[1],
1331 cmd->cmnd[2], cmd->cmnd[3],
1332 cmd->cmnd[4], cmd->cmnd[5],
1333 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1334 cmd->cmnd[8], cmd->cmnd[9],
1335 cmd->cmnd[10], cmd->cmnd[11],
1336 cmd->cmnd[12], cmd->cmnd[13],
1337 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1338 break;
1339 }
1340
1341
1342 /* Problem was not a check condition
1343 * Pass it up to the upper layers...
1344 */
1345 if (ei->ScsiStatus) {
1346 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1347 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1348 "Returning result: 0x%x\n",
1349 cp, ei->ScsiStatus,
1350 sense_key, asc, ascq,
1351 cmd->result);
1352 } else { /* scsi status is zero??? How??? */
1353 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1354 "Returning no connection.\n", cp),
1355
1356 /* Ordinarily, this case should never happen,
1357 * but there is a bug in some released firmware
1358 * revisions that allows it to happen if, for
1359 * example, a 4100 backplane loses power and
1360 * the tape drive is in it. We assume that
1361 * it's a fatal error of some kind because we
1362 * can't show that it wasn't. We will make it
1363 * look like selection timeout since that is
1364 * the most common reason for this to occur,
1365 * and it's severe enough.
1366 */
1367
1368 cmd->result = DID_NO_CONNECT << 16;
1369 }
1370 break;
1371
1372 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1373 break;
1374 case CMD_DATA_OVERRUN:
1375 dev_warn(&h->pdev->dev, "cp %p has"
1376 " completed with data overrun "
1377 "reported\n", cp);
1378 break;
1379 case CMD_INVALID: {
1380 /* print_bytes(cp, sizeof(*cp), 1, 0);
1381 print_cmd(cp); */
1382 /* We get CMD_INVALID if you address a non-existent device
1383 * instead of a selection timeout (no response). You will
1384 * see this if you yank out a drive, then try to access it.
1385 * This is kind of a shame because it means that any other
1386 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1387 * missing target. */
1388 cmd->result = DID_NO_CONNECT << 16;
1389 }
1390 break;
1391 case CMD_PROTOCOL_ERR:
256d0eaa 1392 cmd->result = DID_ERROR << 16;
edd16368 1393 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1394 "protocol error\n", cp);
edd16368
SC		 1395 break;
1396 case CMD_HARDWARE_ERR:
1397 cmd->result = DID_ERROR << 16;
1398 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1399 break;
1400 case CMD_CONNECTION_LOST:
1401 cmd->result = DID_ERROR << 16;
1402 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1403 break;
1404 case CMD_ABORTED:
1405 cmd->result = DID_ABORT << 16;
1406 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1407 cp, ei->ScsiStatus);
1408 break;
1409 case CMD_ABORT_FAILED:
1410 cmd->result = DID_ERROR << 16;
1411 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1412 break;
1413 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1414 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1415 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1416 "abort\n", cp);
1417 break;
1418 case CMD_TIMEOUT:
1419 cmd->result = DID_TIME_OUT << 16;
1420 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1421 break;
1d5e2ed0
SC		 1422 case CMD_UNABORTABLE:
1423 cmd->result = DID_ERROR << 16;
1424 dev_warn(&h->pdev->dev, "Command unabortable\n");
1425 break;
283b4a9b
SC		 1426 case CMD_IOACCEL_DISABLED:
1427 /* This only handles the direct pass-through case since RAID
1428 * offload is handled above. Just attempt a retry.
1429 */
1430 cmd->result = DID_SOFT_ERROR << 16;
1431 dev_warn(&h->pdev->dev,
1432 "cp %p had HP SSD Smart Path error\n", cp);
1433 break;
edd16368
SC		 1434 default:
1435 cmd->result = DID_ERROR << 16;
1436 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1437 cp, ei->CommandStatus);
1438 }
edd16368 1439 cmd_free(h, cp);
2cc5bfaf 1440 cmd->scsi_done(cmd);
edd16368
SC		 1441}
1442
edd16368
SC		 1443static void hpsa_pci_unmap(struct pci_dev *pdev,
1444 struct CommandList *c, int sg_used, int data_direction)
1445{
1446 int i;
1447 union u64bit addr64;
1448
1449 for (i = 0; i < sg_used; i++) {
1450 addr64.val32.lower = c->SG[i].Addr.lower;
1451 addr64.val32.upper = c->SG[i].Addr.upper;
1452 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1453 data_direction);
1454 }
1455}
1456
a2dac136 1457static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1458 struct CommandList *cp,
1459 unsigned char *buf,
1460 size_t buflen,
1461 int data_direction)
1462{
01a02ffc 1463 u64 addr64;
edd16368
SC		 1464
1465 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1466 cp->Header.SGList = 0;
1467 cp->Header.SGTotal = 0;
a2dac136 1468 return 0;
edd16368
SC		 1469 }
1470
01a02ffc 1471 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1472 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1473 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1474 cp->Header.SGList = 0;
1475 cp->Header.SGTotal = 0;
a2dac136 1476 return -1;
eceaae18 1477 }
edd16368 1478 cp->SG[0].Addr.lower =
01a02ffc 1479 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1480 cp->SG[0].Addr.upper =
01a02ffc 1481 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1482 cp->SG[0].Len = buflen;
e1d9cbfa 1483 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1484 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1485 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1486 return 0;
edd16368
SC		 1487}
1488
1489static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1490 struct CommandList *c)
1491{
1492 DECLARE_COMPLETION_ONSTACK(wait);
1493
1494 c->waiting = &wait;
1495 enqueue_cmd_and_start_io(h, c);
1496 wait_for_completion(&wait);
1497}
1498
a0c12413
SC		 1499static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1500 struct CommandList *c)
1501{
1502 unsigned long flags;
1503
1504 /* If controller lockup detected, fake a hardware error. */
1505 spin_lock_irqsave(&h->lock, flags);
1506 if (unlikely(h->lockup_detected)) {
1507 spin_unlock_irqrestore(&h->lock, flags);
1508 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1509 } else {
1510 spin_unlock_irqrestore(&h->lock, flags);
1511 hpsa_scsi_do_simple_cmd_core(h, c);
1512 }
1513}
1514
9c2fc160 1515#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1516static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1517 struct CommandList *c, int data_direction)
1518{
9c2fc160 1519 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1520
1521 do {
7630abd0 1522 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1523 hpsa_scsi_do_simple_cmd_core(h, c);
1524 retry_count++;
9c2fc160
SC		 1525 if (retry_count > 3) {
1526 msleep(backoff_time);
1527 if (backoff_time < 1000)
1528 backoff_time *= 2;
1529 }
852af20a 1530 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1531 check_for_busy(h, c)) &&
1532 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1533 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1534}
1535
1536static void hpsa_scsi_interpret_error(struct CommandList *cp)
1537{
1538 struct ErrorInfo *ei;
1539 struct device *d = &cp->h->pdev->dev;
1540
1541 ei = cp->err_info;
1542 switch (ei->CommandStatus) {
1543 case CMD_TARGET_STATUS:
1544 dev_warn(d, "cmd %p has completed with errors\n", cp);
1545 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1546 ei->ScsiStatus);
1547 if (ei->ScsiStatus == 0)
1548 dev_warn(d, "SCSI status is abnormally zero. "
1549 "(probably indicates selection timeout "
1550 "reported incorrectly due to a known "
1551 "firmware bug, circa July, 2001.)\n");
1552 break;
1553 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1554 dev_info(d, "UNDERRUN\n");
1555 break;
1556 case CMD_DATA_OVERRUN:
1557 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1558 break;
1559 case CMD_INVALID: {
1560 /* controller unfortunately reports SCSI passthru's
1561 * to non-existent targets as invalid commands.
1562 */
1563 dev_warn(d, "cp %p is reported invalid (probably means "
1564 "target device no longer present)\n", cp);
1565 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1566 print_cmd(cp); */
1567 }
1568 break;
1569 case CMD_PROTOCOL_ERR:
1570 dev_warn(d, "cp %p has protocol error \n", cp);
1571 break;
1572 case CMD_HARDWARE_ERR:
1573 /* cmd->result = DID_ERROR << 16; */
1574 dev_warn(d, "cp %p had hardware error\n", cp);
1575 break;
1576 case CMD_CONNECTION_LOST:
1577 dev_warn(d, "cp %p had connection lost\n", cp);
1578 break;
1579 case CMD_ABORTED:
1580 dev_warn(d, "cp %p was aborted\n", cp);
1581 break;
1582 case CMD_ABORT_FAILED:
1583 dev_warn(d, "cp %p reports abort failed\n", cp);
1584 break;
1585 case CMD_UNSOLICITED_ABORT:
1586 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1587 break;
1588 case CMD_TIMEOUT:
1589 dev_warn(d, "cp %p timed out\n", cp);
1590 break;
1d5e2ed0
SC		 1591 case CMD_UNABORTABLE:
1592 dev_warn(d, "Command unabortable\n");
1593 break;
edd16368
SC		 1594 default:
1595 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1596 ei->CommandStatus);
1597 }
1598}
1599
1600static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1601 unsigned char page, unsigned char *buf,
1602 unsigned char bufsize)
1603{
1604 int rc = IO_OK;
1605 struct CommandList *c;
1606 struct ErrorInfo *ei;
1607
1608 c = cmd_special_alloc(h);
1609
1610 if (c == NULL) { /* trouble... */
1611 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1612 return -ENOMEM;
edd16368
SC		 1613 }
1614
a2dac136
SC		 1615 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1616 page, scsi3addr, TYPE_CMD)) {
1617 rc = -1;
1618 goto out;
1619 }
edd16368
SC		 1620 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1621 ei = c->err_info;
1622 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1623 hpsa_scsi_interpret_error(c);
1624 rc = -1;
1625 }
a2dac136 1626out:
edd16368
SC		 1627 cmd_special_free(h, c);
1628 return rc;
1629}
1630
1631static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
1632{
1633 int rc = IO_OK;
1634 struct CommandList *c;
1635 struct ErrorInfo *ei;
1636
1637 c = cmd_special_alloc(h);
1638
1639 if (c == NULL) { /* trouble... */
1640 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1641 return -ENOMEM;
edd16368
SC		 1642 }
1643
a2dac136
SC		 1644 /* fill_cmd can't fail here, no data buffer to map. */
1645 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h,
1646 NULL, 0, 0, scsi3addr, TYPE_MSG);
edd16368
SC		 1647 hpsa_scsi_do_simple_cmd_core(h, c);
1648 /* no unmap needed here because no data xfer. */
1649
1650 ei = c->err_info;
1651 if (ei->CommandStatus != 0) {
1652 hpsa_scsi_interpret_error(c);
1653 rc = -1;
1654 }
1655 cmd_special_free(h, c);
1656 return rc;
1657}
1658
1659static void hpsa_get_raid_level(struct ctlr_info *h,
1660 unsigned char *scsi3addr, unsigned char *raid_level)
1661{
1662 int rc;
1663 unsigned char *buf;
1664
1665 *raid_level = RAID_UNKNOWN;
1666 buf = kzalloc(64, GFP_KERNEL);
1667 if (!buf)
1668 return;
1669 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1670 if (rc == 0)
1671 *raid_level = buf[8];
1672 if (*raid_level > RAID_UNKNOWN)
1673 *raid_level = RAID_UNKNOWN;
1674 kfree(buf);
1675 return;
1676}
1677
283b4a9b
SC		 1678#define HPSA_MAP_DEBUG
1679#ifdef HPSA_MAP_DEBUG
1680static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1681 struct raid_map_data *map_buff)
1682{
1683 struct raid_map_disk_data *dd = &map_buff->data[0];
1684 int map, row, col;
1685 u16 map_cnt, row_cnt, disks_per_row;
1686
1687 if (rc != 0)
1688 return;
1689
1690 dev_info(&h->pdev->dev, "structure_size = %u\n",
1691 le32_to_cpu(map_buff->structure_size));
1692 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1693 le32_to_cpu(map_buff->volume_blk_size));
1694 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1695 le64_to_cpu(map_buff->volume_blk_cnt));
1696 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1697 map_buff->phys_blk_shift);
1698 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1699 map_buff->parity_rotation_shift);
1700 dev_info(&h->pdev->dev, "strip_size = %u\n",
1701 le16_to_cpu(map_buff->strip_size));
1702 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1703 le64_to_cpu(map_buff->disk_starting_blk));
1704 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1705 le64_to_cpu(map_buff->disk_blk_cnt));
1706 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1707 le16_to_cpu(map_buff->data_disks_per_row));
1708 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1709 le16_to_cpu(map_buff->metadata_disks_per_row));
1710 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1711 le16_to_cpu(map_buff->row_cnt));
1712 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1713 le16_to_cpu(map_buff->layout_map_count));
1714
1715 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1716 for (map = 0; map < map_cnt; map++) {
1717 dev_info(&h->pdev->dev, "Map%u:\n", map);
1718 row_cnt = le16_to_cpu(map_buff->row_cnt);
1719 for (row = 0; row < row_cnt; row++) {
1720 dev_info(&h->pdev->dev, " Row%u:\n", row);
1721 disks_per_row =
1722 le16_to_cpu(map_buff->data_disks_per_row);
1723 for (col = 0; col < disks_per_row; col++, dd++)
1724 dev_info(&h->pdev->dev,
1725 " D%02u: h=0x%04x xor=%u,%u\n",
1726 col, dd->ioaccel_handle,
1727 dd->xor_mult[0], dd->xor_mult[1]);
1728 disks_per_row =
1729 le16_to_cpu(map_buff->metadata_disks_per_row);
1730 for (col = 0; col < disks_per_row; col++, dd++)
1731 dev_info(&h->pdev->dev,
1732 " M%02u: h=0x%04x xor=%u,%u\n",
1733 col, dd->ioaccel_handle,
1734 dd->xor_mult[0], dd->xor_mult[1]);
1735 }
1736 }
1737}
1738#else
1739static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
1740 __attribute__((unused)) int rc,
1741 __attribute__((unused)) struct raid_map_data *map_buff)
1742{
1743}
1744#endif
1745
1746static int hpsa_get_raid_map(struct ctlr_info *h,
1747 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1748{
1749 int rc = 0;
1750 struct CommandList *c;
1751 struct ErrorInfo *ei;
1752
1753 c = cmd_special_alloc(h);
1754 if (c == NULL) {
1755 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1756 return -ENOMEM;
1757 }
1758 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
1759 sizeof(this_device->raid_map), 0,
1760 scsi3addr, TYPE_CMD)) {
1761 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
1762 cmd_special_free(h, c);
1763 return -ENOMEM;
1764 }
1765 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1766 ei = c->err_info;
1767 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1768 hpsa_scsi_interpret_error(c);
1769 cmd_special_free(h, c);
1770 return -1;
1771 }
1772 cmd_special_free(h, c);
1773
1774 /* @todo in the future, dynamically allocate RAID map memory */
1775 if (le32_to_cpu(this_device->raid_map.structure_size) >
1776 sizeof(this_device->raid_map)) {
1777 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
1778 rc = -1;
1779 }
1780 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
1781 return rc;
1782}
1783
1784static void hpsa_get_ioaccel_status(struct ctlr_info *h,
1785 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1786{
1787 int rc;
1788 unsigned char *buf;
1789 u8 ioaccel_status;
1790
1791 this_device->offload_config = 0;
1792 this_device->offload_enabled = 0;
1793
1794 buf = kzalloc(64, GFP_KERNEL);
1795 if (!buf)
1796 return;
1797 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
1798 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
1799 if (rc != 0)
1800 goto out;
1801
1802#define IOACCEL_STATUS_BYTE 4
1803#define OFFLOAD_CONFIGURED_BIT 0x01
1804#define OFFLOAD_ENABLED_BIT 0x02
1805 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
1806 this_device->offload_config =
1807 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
1808 if (this_device->offload_config) {
1809 this_device->offload_enabled =
1810 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
1811 if (hpsa_get_raid_map(h, scsi3addr, this_device))
1812 this_device->offload_enabled = 0;
1813 }
1814out:
1815 kfree(buf);
1816 return;
1817}
1818
edd16368
SC		 1819/* Get the device id from inquiry page 0x83 */
1820static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
1821 unsigned char *device_id, int buflen)
1822{
1823 int rc;
1824 unsigned char *buf;
1825
1826 if (buflen > 16)
1827 buflen = 16;
1828 buf = kzalloc(64, GFP_KERNEL);
1829 if (!buf)
1830 return -1;
1831 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
1832 if (rc == 0)
1833 memcpy(device_id, &buf[8], buflen);
1834 kfree(buf);
1835 return rc != 0;
1836}
1837
1838static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
1839 struct ReportLUNdata *buf, int bufsize,
1840 int extended_response)
1841{
1842 int rc = IO_OK;
1843 struct CommandList *c;
1844 unsigned char scsi3addr[8];
1845 struct ErrorInfo *ei;
1846
1847 c = cmd_special_alloc(h);
1848 if (c == NULL) { /* trouble... */
1849 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1850 return -1;
1851 }
e89c0ae7
SC		 1852 /* address the controller */
1853 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 1854 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
1855 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
1856 rc = -1;
1857 goto out;
1858 }
edd16368
SC		 1859 if (extended_response)
1860 c->Request.CDB[1] = extended_response;
1861 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1862 ei = c->err_info;
1863 if (ei->CommandStatus != 0 &&
1864 ei->CommandStatus != CMD_DATA_UNDERRUN) {
1865 hpsa_scsi_interpret_error(c);
1866 rc = -1;
283b4a9b
SC		 1867 } else {
1868 if (buf->extended_response_flag != extended_response) {
1869 dev_err(&h->pdev->dev,
1870 "report luns requested format %u, got %u\n",
1871 extended_response,
1872 buf->extended_response_flag);
1873 rc = -1;
1874 }
edd16368 1875 }
a2dac136 1876out:
edd16368
SC		 1877 cmd_special_free(h, c);
1878 return rc;
1879}
1880
1881static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
1882 struct ReportLUNdata *buf,
1883 int bufsize, int extended_response)
1884{
1885 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
1886}
1887
1888static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
1889 struct ReportLUNdata *buf, int bufsize)
1890{
1891 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
1892}
1893
1894static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
1895 int bus, int target, int lun)
1896{
1897 device->bus = bus;
1898 device->target = target;
1899 device->lun = lun;
1900}
1901
1902static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 1903 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
1904 unsigned char *is_OBDR_device)
edd16368 1905{
0b0e1d6c
SC		 1906
1907#define OBDR_SIG_OFFSET 43
1908#define OBDR_TAPE_SIG "$DR-10"
1909#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
1910#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
1911
ea6d3bc3 1912 unsigned char *inq_buff;
0b0e1d6c 1913 unsigned char *obdr_sig;
edd16368 1914
ea6d3bc3 1915 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 1916 if (!inq_buff)
1917 goto bail_out;
1918
edd16368
SC		 1919 /* Do an inquiry to the device to see what it is. */
1920 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
1921 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
1922 /* Inquiry failed (msg printed already) */
1923 dev_err(&h->pdev->dev,
1924 "hpsa_update_device_info: inquiry failed\n");
1925 goto bail_out;
1926 }
1927
edd16368
SC		 1928 this_device->devtype = (inq_buff[0] & 0x1f);
1929 memcpy(this_device->scsi3addr, scsi3addr, 8);
1930 memcpy(this_device->vendor, &inq_buff[8],
1931 sizeof(this_device->vendor));
1932 memcpy(this_device->model, &inq_buff[16],
1933 sizeof(this_device->model));
edd16368
SC		 1934 memset(this_device->device_id, 0,
1935 sizeof(this_device->device_id));
1936 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
1937 sizeof(this_device->device_id));
1938
1939 if (this_device->devtype == TYPE_DISK &&
283b4a9b 1940 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 1941 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 1942 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
1943 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
1944 } else {
edd16368 1945 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 1946 this_device->offload_config = 0;
1947 this_device->offload_enabled = 0;
1948 }
edd16368 1949
0b0e1d6c
SC		 1950 if (is_OBDR_device) {
1951 /* See if this is a One-Button-Disaster-Recovery device
1952 * by looking for "$DR-10" at offset 43 in inquiry data.
1953 */
1954 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
1955 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
1956 strncmp(obdr_sig, OBDR_TAPE_SIG,
1957 OBDR_SIG_LEN) == 0);
1958 }
1959
edd16368
SC		 1960 kfree(inq_buff);
1961 return 0;
1962
1963bail_out:
1964 kfree(inq_buff);
1965 return 1;
1966}
1967
4f4eb9f1 1968static unsigned char *ext_target_model[] = {
edd16368
SC		 1969 "MSA2012",
1970 "MSA2024",
1971 "MSA2312",
1972 "MSA2324",
fda38518 1973 "P2000 G3 SAS",
e06c8e5c 1974 "MSA 2040 SAS",
edd16368
SC		 1975 NULL,
1976};
1977
4f4eb9f1 1978static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 1979{
1980 int i;
1981
4f4eb9f1
ST		 1982 for (i = 0; ext_target_model[i]; i++)
1983 if (strncmp(device->model, ext_target_model[i],
1984 strlen(ext_target_model[i])) == 0)
edd16368
SC		 1985 return 1;
1986 return 0;
1987}
1988
1989/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 1990 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 1991 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
1992 * Logical drive target and lun are assigned at this time, but
1993 * physical device lun and target assignment are deferred (assigned
1994 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
1995 */
1996static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 1997 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 1998{
1f310bde
SC		 1999 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2000
2001 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2002 /* physical device, target and lun filled in later */
edd16368 2003 if (is_hba_lunid(lunaddrbytes))
1f310bde 2004 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2005 else
1f310bde
SC		 2006 /* defer target, lun assignment for physical devices */
2007 hpsa_set_bus_target_lun(device, 2, -1, -1);
2008 return;
2009 }
2010 /* It's a logical device */
4f4eb9f1
ST		 2011 if (is_ext_target(h, device)) {
2012 /* external target way, put logicals on bus 1
1f310bde
SC		 2013 * and match target/lun numbers box
2014 * reports, other smart array, bus 0, target 0, match lunid
2015 */
2016 hpsa_set_bus_target_lun(device,
2017 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2018 return;
edd16368 2019 }
1f310bde 2020 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2021}
2022
2023/*
2024 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2025 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2026 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2027 * it for some reason. *tmpdevice is the target we're adding,
2028 * this_device is a pointer into the current element of currentsd[]
2029 * that we're building up in update_scsi_devices(), below.
2030 * lunzerobits is a bitmap that tracks which targets already have a
2031 * lun 0 assigned.
2032 * Returns 1 if an enclosure was added, 0 if not.
2033 */
4f4eb9f1 2034static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2035 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2036 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2037 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2038{
2039 unsigned char scsi3addr[8];
2040
1f310bde 2041 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2042 return 0; /* There is already a lun 0 on this target. */
2043
2044 if (!is_logical_dev_addr_mode(lunaddrbytes))
2045 return 0; /* It's the logical targets that may lack lun 0. */
2046
4f4eb9f1
ST		 2047 if (!is_ext_target(h, tmpdevice))
2048 return 0; /* Only external target devices have this problem. */
edd16368 2049
1f310bde 2050 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2051 return 0;
2052
c4f8a299 2053 memset(scsi3addr, 0, 8);
1f310bde 2054 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2055 if (is_hba_lunid(scsi3addr))
2056 return 0; /* Don't add the RAID controller here. */
2057
339b2b14
SC		 2058 if (is_scsi_rev_5(h))
2059 return 0; /* p1210m doesn't need to do this. */
2060
4f4eb9f1 2061 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2062 dev_warn(&h->pdev->dev, "Maximum number of external "
2063 "target devices exceeded. Check your hardware "
edd16368
SC		 2064 "configuration.");
2065 return 0;
2066 }
2067
0b0e1d6c 2068 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2069 return 0;
4f4eb9f1 2070 (*n_ext_target_devs)++;
1f310bde
SC		 2071 hpsa_set_bus_target_lun(this_device,
2072 tmpdevice->bus, tmpdevice->target, 0);
2073 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2074 return 1;
2075}
2076
2077/*
2078 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2079 * logdev. The number of luns in physdev and logdev are returned in
2080 * *nphysicals and *nlogicals, respectively.
2081 * Returns 0 on success, -1 otherwise.
2082 */
2083static int hpsa_gather_lun_info(struct ctlr_info *h,
2084 int reportlunsize,
283b4a9b 2085 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2086 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2087{
283b4a9b
SC		 2088 int physical_entry_size = 8;
2089
2090 *physical_mode = 0;
2091
2092 /* For I/O accelerator mode we need to read physical device handles */
2093 if (h->transMethod & CFGTBL_Trans_io_accel1) {
2094 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2095 physical_entry_size = 24;
2096 }
a93aa1fe 2097 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2098 *physical_mode)) {
edd16368
SC		 2099 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2100 return -1;
2101 }
283b4a9b
SC		 2102 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2103 physical_entry_size;
edd16368
SC		 2104 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2105 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2106 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2107 *nphysicals - HPSA_MAX_PHYS_LUN);
2108 *nphysicals = HPSA_MAX_PHYS_LUN;
2109 }
2110 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2111 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2112 return -1;
2113 }
6df1e954 2114 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2115 /* Reject Logicals in excess of our max capability. */
2116 if (*nlogicals > HPSA_MAX_LUN) {
2117 dev_warn(&h->pdev->dev,
2118 "maximum logical LUNs (%d) exceeded. "
2119 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2120 *nlogicals - HPSA_MAX_LUN);
2121 *nlogicals = HPSA_MAX_LUN;
2122 }
2123 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2124 dev_warn(&h->pdev->dev,
2125 "maximum logical + physical LUNs (%d) exceeded. "
2126 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2127 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2128 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2129 }
2130 return 0;
2131}
2132
339b2b14 2133u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2134 int nphysicals, int nlogicals,
2135 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2136 struct ReportLUNdata *logdev_list)
2137{
2138 /* Helper function, figure out where the LUN ID info is coming from
2139 * given index i, lists of physical and logical devices, where in
2140 * the list the raid controller is supposed to appear (first or last)
2141 */
2142
2143 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2144 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2145
2146 if (i == raid_ctlr_position)
2147 return RAID_CTLR_LUNID;
2148
2149 if (i < logicals_start)
2150 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2151
2152 if (i < last_device)
2153 return &logdev_list->LUN[i - nphysicals -
2154 (raid_ctlr_position == 0)][0];
2155 BUG();
2156 return NULL;
2157}
2158
edd16368
SC		 2159static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2160{
2161 /* the idea here is we could get notified
2162 * that some devices have changed, so we do a report
2163 * physical luns and report logical luns cmd, and adjust
2164 * our list of devices accordingly.
2165 *
2166 * The scsi3addr's of devices won't change so long as the
2167 * adapter is not reset. That means we can rescan and
2168 * tell which devices we already know about, vs. new
2169 * devices, vs. disappearing devices.
2170 */
a93aa1fe 2171 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2172 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2173 u32 nphysicals = 0;
2174 u32 nlogicals = 0;
283b4a9b 2175 int physical_mode = 0;
01a02ffc 2176 u32 ndev_allocated = 0;
edd16368
SC		 2177 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2178 int ncurrent = 0;
283b4a9b 2179 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2180 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2181 int raid_ctlr_position;
aca4a520 2182 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2183
cfe5badc 2184 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2185 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2186 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2187 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2188
0b0e1d6c 2189 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2190 dev_err(&h->pdev->dev, "out of memory\n");
2191 goto out;
2192 }
2193 memset(lunzerobits, 0, sizeof(lunzerobits));
2194
a93aa1fe
MG		 2195 if (hpsa_gather_lun_info(h, reportlunsize,
2196 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2197 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2198 goto out;
2199
aca4a520
ST		 2200 /* We might see up to the maximum number of logical and physical disks
2201 * plus external target devices, and a device for the local RAID
2202 * controller.
edd16368 2203 */
aca4a520 2204 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2205
2206 /* Allocate the per device structures */
2207 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2208 if (i >= HPSA_MAX_DEVICES) {
2209 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2210 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2211 ndevs_to_allocate - HPSA_MAX_DEVICES);
2212 break;
2213 }
2214
edd16368
SC		 2215 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2216 if (!currentsd[i]) {
2217 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2218 __FILE__, __LINE__);
2219 goto out;
2220 }
2221 ndev_allocated++;
2222 }
2223
339b2b14
SC		 2224 if (unlikely(is_scsi_rev_5(h)))
2225 raid_ctlr_position = 0;
2226 else
2227 raid_ctlr_position = nphysicals + nlogicals;
2228
edd16368 2229 /* adjust our table of devices */
4f4eb9f1 2230 n_ext_target_devs = 0;
edd16368 2231 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2232 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2233
2234 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2235 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2236 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2237 /* skip masked physical devices. */
339b2b14
SC		 2238 if (lunaddrbytes[3] & 0xC0 &&
2239 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2240 continue;
2241
2242 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2243 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2244 &is_OBDR))
edd16368 2245 continue; /* skip it if we can't talk to it. */
1f310bde 2246 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2247 this_device = currentsd[ncurrent];
2248
2249 /*
4f4eb9f1 2250 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2251 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2252 * is nonetheless an enclosure device there. We have to
2253 * present that otherwise linux won't find anything if
2254 * there is no lun 0.
2255 */
4f4eb9f1 2256 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2257 lunaddrbytes, lunzerobits,
4f4eb9f1 2258 &n_ext_target_devs)) {
edd16368
SC		 2259 ncurrent++;
2260 this_device = currentsd[ncurrent];
2261 }
2262
2263 *this_device = *tmpdevice;
edd16368
SC		 2264
2265 switch (this_device->devtype) {
0b0e1d6c 2266 case TYPE_ROM:
edd16368
SC		 2267 /* We don't *really* support actual CD-ROM devices,
2268 * just "One Button Disaster Recovery" tape drive
2269 * which temporarily pretends to be a CD-ROM drive.
2270 * So we check that the device is really an OBDR tape
2271 * device by checking for "$DR-10" in bytes 43-48 of
2272 * the inquiry data.
2273 */
0b0e1d6c
SC		 2274 if (is_OBDR)
2275 ncurrent++;
edd16368
SC		 2276 break;
2277 case TYPE_DISK:
283b4a9b
SC		 2278 if (i >= nphysicals) {
2279 ncurrent++;
edd16368 2280 break;
283b4a9b
SC		 2281 }
2282 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2283 memcpy(&this_device->ioaccel_handle,
2284 &lunaddrbytes[20],
2285 sizeof(this_device->ioaccel_handle));
2286 ncurrent++;
2287 }
edd16368
SC		 2288 break;
2289 case TYPE_TAPE:
2290 case TYPE_MEDIUM_CHANGER:
2291 ncurrent++;
2292 break;
2293 case TYPE_RAID:
2294 /* Only present the Smartarray HBA as a RAID controller.
2295 * If it's a RAID controller other than the HBA itself
2296 * (an external RAID controller, MSA500 or similar)
2297 * don't present it.
2298 */
2299 if (!is_hba_lunid(lunaddrbytes))
2300 break;
2301 ncurrent++;
2302 break;
2303 default:
2304 break;
2305 }
cfe5badc 2306 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2307 break;
2308 }
2309 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2310out:
2311 kfree(tmpdevice);
2312 for (i = 0; i < ndev_allocated; i++)
2313 kfree(currentsd[i]);
2314 kfree(currentsd);
edd16368
SC		 2315 kfree(physdev_list);
2316 kfree(logdev_list);
edd16368
SC		 2317}
2318
2319/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2320 * dma mapping and fills in the scatter gather entries of the
2321 * hpsa command, cp.
2322 */
33a2ffce 2323static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2324 struct CommandList *cp,
2325 struct scsi_cmnd *cmd)
2326{
2327 unsigned int len;
2328 struct scatterlist *sg;
01a02ffc 2329 u64 addr64;
33a2ffce
SC		 2330 int use_sg, i, sg_index, chained;
2331 struct SGDescriptor *curr_sg;
edd16368 2332
33a2ffce 2333 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2334
2335 use_sg = scsi_dma_map(cmd);
2336 if (use_sg < 0)
2337 return use_sg;
2338
2339 if (!use_sg)
2340 goto sglist_finished;
2341
33a2ffce
SC		 2342 curr_sg = cp->SG;
2343 chained = 0;
2344 sg_index = 0;
edd16368 2345 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2346 if (i == h->max_cmd_sg_entries - 1 &&
2347 use_sg > h->max_cmd_sg_entries) {
2348 chained = 1;
2349 curr_sg = h->cmd_sg_list[cp->cmdindex];
2350 sg_index = 0;
2351 }
01a02ffc 2352 addr64 = (u64) sg_dma_address(sg);
edd16368 2353 len = sg_dma_len(sg);
33a2ffce
SC		 2354 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2355 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2356 curr_sg->Len = len;
e1d9cbfa 2357 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2358 curr_sg++;
2359 }
2360
2361 if (use_sg + chained > h->maxSG)
2362 h->maxSG = use_sg + chained;
2363
2364 if (chained) {
2365 cp->Header.SGList = h->max_cmd_sg_entries;
2366 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2367 if (hpsa_map_sg_chain_block(h, cp)) {
2368 scsi_dma_unmap(cmd);
2369 return -1;
2370 }
33a2ffce 2371 return 0;
edd16368
SC		 2372 }
2373
2374sglist_finished:
2375
01a02ffc
SC		 2376 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2377 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2378 return 0;
2379}
2380
283b4a9b
SC		 2381#define IO_ACCEL_INELIGIBLE (1)
2382static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2383{
2384 int is_write = 0;
2385 u32 block;
2386 u32 block_cnt;
2387
2388 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2389 switch (cdb[0]) {
2390 case WRITE_6:
2391 case WRITE_12:
2392 is_write = 1;
2393 case READ_6:
2394 case READ_12:
2395 if (*cdb_len == 6) {
2396 block = (((u32) cdb[2]) << 8) | cdb[3];
2397 block_cnt = cdb[4];
2398 } else {
2399 BUG_ON(*cdb_len != 12);
2400 block = (((u32) cdb[2]) << 24) |
2401 (((u32) cdb[3]) << 16) |
2402 (((u32) cdb[4]) << 8) |
2403 cdb[5];
2404 block_cnt =
2405 (((u32) cdb[6]) << 24) |
2406 (((u32) cdb[7]) << 16) |
2407 (((u32) cdb[8]) << 8) |
2408 cdb[9];
2409 }
2410 if (block_cnt > 0xffff)
2411 return IO_ACCEL_INELIGIBLE;
2412
2413 cdb[0] = is_write ? WRITE_10 : READ_10;
2414 cdb[1] = 0;
2415 cdb[2] = (u8) (block >> 24);
2416 cdb[3] = (u8) (block >> 16);
2417 cdb[4] = (u8) (block >> 8);
2418 cdb[5] = (u8) (block);
2419 cdb[6] = 0;
2420 cdb[7] = (u8) (block_cnt >> 8);
2421 cdb[8] = (u8) (block_cnt);
2422 cdb[9] = 0;
2423 *cdb_len = 10;
2424 break;
2425 }
2426 return 0;
2427}
2428
e1f7de0c
MG		 2429/*
2430 * Queue a command to the I/O accelerator path.
e1f7de0c
MG		 2431 */
2432static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2433 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2434 u8 *scsi3addr)
e1f7de0c
MG		 2435{
2436 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2437 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2438 unsigned int len;
2439 unsigned int total_len = 0;
2440 struct scatterlist *sg;
2441 u64 addr64;
2442 int use_sg, i;
2443 struct SGDescriptor *curr_sg;
2444 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2445
283b4a9b
SC		 2446 /* TODO: implement chaining support */
2447 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2448 return IO_ACCEL_INELIGIBLE;
2449
e1f7de0c
MG		 2450 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2451
283b4a9b
SC		 2452 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2453 return IO_ACCEL_INELIGIBLE;
2454
e1f7de0c
MG		 2455 c->cmd_type = CMD_IOACCEL1;
2456
2457 /* Adjust the DMA address to point to the accelerated command buffer */
2458 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2459 (c->cmdindex * sizeof(*cp));
2460 BUG_ON(c->busaddr & 0x0000007F);
2461
2462 use_sg = scsi_dma_map(cmd);
2463 if (use_sg < 0)
2464 return use_sg;
2465
2466 if (use_sg) {
2467 curr_sg = cp->SG;
2468 scsi_for_each_sg(cmd, sg, use_sg, i) {
2469 addr64 = (u64) sg_dma_address(sg);
2470 len = sg_dma_len(sg);
2471 total_len += len;
2472 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2473 curr_sg->Addr.upper =
2474 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2475 curr_sg->Len = len;
2476
2477 if (i == (scsi_sg_count(cmd) - 1))
2478 curr_sg->Ext = HPSA_SG_LAST;
2479 else
2480 curr_sg->Ext = 0; /* we are not chaining */
2481 curr_sg++;
2482 }
2483
2484 switch (cmd->sc_data_direction) {
2485 case DMA_TO_DEVICE:
2486 control |= IOACCEL1_CONTROL_DATA_OUT;
2487 break;
2488 case DMA_FROM_DEVICE:
2489 control |= IOACCEL1_CONTROL_DATA_IN;
2490 break;
2491 case DMA_NONE:
2492 control |= IOACCEL1_CONTROL_NODATAXFER;
2493 break;
2494 default:
2495 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2496 cmd->sc_data_direction);
2497 BUG();
2498 break;
2499 }
2500 } else {
2501 control |= IOACCEL1_CONTROL_NODATAXFER;
2502 }
2503
2504 /* Fill out the command structure to submit */
283b4a9b 2505 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2506 cp->transfer_len = total_len;
2507 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2508 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2509 cp->control = control;
283b4a9b
SC		 2510 memcpy(cp->CDB, cdb, cdb_len);
2511 memcpy(cp->CISS_LUN, scsi3addr, 8);
e1f7de0c
MG		 2512
2513 /* Tell the controller to post the reply to the queue for this
2514 * processor. This seems to give the best I/O throughput.
2515 */
2516 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
2517
2518 /* Set the bits in the address sent down to include:
2519 * - performant mode bit (bit 0)
2520 * - pull count (bits 1-3)
2521 * - command type (bits 4-6)
2522 */
2523 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[use_sg] << 1) |
2524 IOACCEL1_BUSADDR_CMDTYPE;
283b4a9b 2525 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2526 return 0;
2527}
edd16368 2528
283b4a9b
SC		 2529/*
2530 * Queue a command directly to a device behind the controller using the
2531 * I/O accelerator path.
2532 */
2533static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2534 struct CommandList *c)
2535{
2536 struct scsi_cmnd *cmd = c->scsi_cmd;
2537 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2538
2539 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2540 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2541}
2542
2543/*
2544 * Attempt to perform offload RAID mapping for a logical volume I/O.
2545 */
2546static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
2547 struct CommandList *c)
2548{
2549 struct scsi_cmnd *cmd = c->scsi_cmd;
2550 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2551 struct raid_map_data *map = &dev->raid_map;
2552 struct raid_map_disk_data *dd = &map->data[0];
2553 int is_write = 0;
2554 u32 map_index;
2555 u64 first_block, last_block;
2556 u32 block_cnt;
2557 u32 blocks_per_row;
2558 u64 first_row, last_row;
2559 u32 first_row_offset, last_row_offset;
2560 u32 first_column, last_column;
2561 u32 map_row;
2562 u32 disk_handle;
2563 u64 disk_block;
2564 u32 disk_block_cnt;
2565 u8 cdb[16];
2566 u8 cdb_len;
2567#if BITS_PER_LONG == 32
2568 u64 tmpdiv;
2569#endif
2570
2571 BUG_ON(!(dev->offload_config && dev->offload_enabled));
2572
2573 /* check for valid opcode, get LBA and block count */
2574 switch (cmd->cmnd[0]) {
2575 case WRITE_6:
2576 is_write = 1;
2577 case READ_6:
2578 first_block =
2579 (((u64) cmd->cmnd[2]) << 8) |
2580 cmd->cmnd[3];
2581 block_cnt = cmd->cmnd[4];
2582 break;
2583 case WRITE_10:
2584 is_write = 1;
2585 case READ_10:
2586 first_block =
2587 (((u64) cmd->cmnd[2]) << 24) |
2588 (((u64) cmd->cmnd[3]) << 16) |
2589 (((u64) cmd->cmnd[4]) << 8) |
2590 cmd->cmnd[5];
2591 block_cnt =
2592 (((u32) cmd->cmnd[7]) << 8) |
2593 cmd->cmnd[8];
2594 break;
2595 case WRITE_12:
2596 is_write = 1;
2597 case READ_12:
2598 first_block =
2599 (((u64) cmd->cmnd[2]) << 24) |
2600 (((u64) cmd->cmnd[3]) << 16) |
2601 (((u64) cmd->cmnd[4]) << 8) |
2602 cmd->cmnd[5];
2603 block_cnt =
2604 (((u32) cmd->cmnd[6]) << 24) |
2605 (((u32) cmd->cmnd[7]) << 16) |
2606 (((u32) cmd->cmnd[8]) << 8) |
2607 cmd->cmnd[9];
2608 break;
2609 case WRITE_16:
2610 is_write = 1;
2611 case READ_16:
2612 first_block =
2613 (((u64) cmd->cmnd[2]) << 56) |
2614 (((u64) cmd->cmnd[3]) << 48) |
2615 (((u64) cmd->cmnd[4]) << 40) |
2616 (((u64) cmd->cmnd[5]) << 32) |
2617 (((u64) cmd->cmnd[6]) << 24) |
2618 (((u64) cmd->cmnd[7]) << 16) |
2619 (((u64) cmd->cmnd[8]) << 8) |
2620 cmd->cmnd[9];
2621 block_cnt =
2622 (((u32) cmd->cmnd[10]) << 24) |
2623 (((u32) cmd->cmnd[11]) << 16) |
2624 (((u32) cmd->cmnd[12]) << 8) |
2625 cmd->cmnd[13];
2626 break;
2627 default:
2628 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
2629 }
2630 BUG_ON(block_cnt == 0);
2631 last_block = first_block + block_cnt - 1;
2632
2633 /* check for write to non-RAID-0 */
2634 if (is_write && dev->raid_level != 0)
2635 return IO_ACCEL_INELIGIBLE;
2636
2637 /* check for invalid block or wraparound */
2638 if (last_block >= map->volume_blk_cnt || last_block < first_block)
2639 return IO_ACCEL_INELIGIBLE;
2640
2641 /* calculate stripe information for the request */
2642 blocks_per_row = map->data_disks_per_row * map->strip_size;
2643#if BITS_PER_LONG == 32
2644 tmpdiv = first_block;
2645 (void) do_div(tmpdiv, blocks_per_row);
2646 first_row = tmpdiv;
2647 tmpdiv = last_block;
2648 (void) do_div(tmpdiv, blocks_per_row);
2649 last_row = tmpdiv;
2650 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2651 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2652 tmpdiv = first_row_offset;
2653 (void) do_div(tmpdiv, map->strip_size);
2654 first_column = tmpdiv;
2655 tmpdiv = last_row_offset;
2656 (void) do_div(tmpdiv, map->strip_size);
2657 last_column = tmpdiv;
2658#else
2659 first_row = first_block / blocks_per_row;
2660 last_row = last_block / blocks_per_row;
2661 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2662 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2663 first_column = first_row_offset / map->strip_size;
2664 last_column = last_row_offset / map->strip_size;
2665#endif
2666
2667 /* if this isn't a single row/column then give to the controller */
2668 if ((first_row != last_row) || (first_column != last_column))
2669 return IO_ACCEL_INELIGIBLE;
2670
2671 /* proceeding with driver mapping */
2672 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2673 map->row_cnt;
2674 map_index = (map_row * (map->data_disks_per_row +
2675 map->metadata_disks_per_row)) + first_column;
2676 if (dev->raid_level == 2) {
2677 /* simple round-robin balancing of RAID 1+0 reads across
2678 * primary and mirror members. this is appropriate for SSD
2679 * but not optimal for HDD.
2680 */
2681 if (dev->offload_to_mirror)
2682 map_index += map->data_disks_per_row;
2683 dev->offload_to_mirror = !dev->offload_to_mirror;
2684 }
2685 disk_handle = dd[map_index].ioaccel_handle;
2686 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
2687 (first_row_offset - (first_column * map->strip_size));
2688 disk_block_cnt = block_cnt;
2689
2690 /* handle differing logical/physical block sizes */
2691 if (map->phys_blk_shift) {
2692 disk_block <<= map->phys_blk_shift;
2693 disk_block_cnt <<= map->phys_blk_shift;
2694 }
2695 BUG_ON(disk_block_cnt > 0xffff);
2696
2697 /* build the new CDB for the physical disk I/O */
2698 if (disk_block > 0xffffffff) {
2699 cdb[0] = is_write ? WRITE_16 : READ_16;
2700 cdb[1] = 0;
2701 cdb[2] = (u8) (disk_block >> 56);
2702 cdb[3] = (u8) (disk_block >> 48);
2703 cdb[4] = (u8) (disk_block >> 40);
2704 cdb[5] = (u8) (disk_block >> 32);
2705 cdb[6] = (u8) (disk_block >> 24);
2706 cdb[7] = (u8) (disk_block >> 16);
2707 cdb[8] = (u8) (disk_block >> 8);
2708 cdb[9] = (u8) (disk_block);
2709 cdb[10] = (u8) (disk_block_cnt >> 24);
2710 cdb[11] = (u8) (disk_block_cnt >> 16);
2711 cdb[12] = (u8) (disk_block_cnt >> 8);
2712 cdb[13] = (u8) (disk_block_cnt);
2713 cdb[14] = 0;
2714 cdb[15] = 0;
2715 cdb_len = 16;
2716 } else {
2717 cdb[0] = is_write ? WRITE_10 : READ_10;
2718 cdb[1] = 0;
2719 cdb[2] = (u8) (disk_block >> 24);
2720 cdb[3] = (u8) (disk_block >> 16);
2721 cdb[4] = (u8) (disk_block >> 8);
2722 cdb[5] = (u8) (disk_block);
2723 cdb[6] = 0;
2724 cdb[7] = (u8) (disk_block_cnt >> 8);
2725 cdb[8] = (u8) (disk_block_cnt);
2726 cdb[9] = 0;
2727 cdb_len = 10;
2728 }
2729 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
2730 dev->scsi3addr);
2731}
2732
f281233d 2733static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 2734 void (*done)(struct scsi_cmnd *))
2735{
2736 struct ctlr_info *h;
2737 struct hpsa_scsi_dev_t *dev;
2738 unsigned char scsi3addr[8];
2739 struct CommandList *c;
2740 unsigned long flags;
283b4a9b 2741 int rc = 0;
edd16368
SC		 2742
2743 /* Get the ptr to our adapter structure out of cmd->host. */
2744 h = sdev_to_hba(cmd->device);
2745 dev = cmd->device->hostdata;
2746 if (!dev) {
2747 cmd->result = DID_NO_CONNECT << 16;
2748 done(cmd);
2749 return 0;
2750 }
2751 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
2752
edd16368 2753 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 2754 if (unlikely(h->lockup_detected)) {
2755 spin_unlock_irqrestore(&h->lock, flags);
2756 cmd->result = DID_ERROR << 16;
2757 done(cmd);
2758 return 0;
2759 }
edd16368 2760 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 2761 c = cmd_alloc(h);
edd16368
SC		 2762 if (c == NULL) { /* trouble... */
2763 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
2764 return SCSI_MLQUEUE_HOST_BUSY;
2765 }
2766
2767 /* Fill in the command list header */
2768
2769 cmd->scsi_done = done; /* save this for use by completion code */
2770
2771 /* save c in case we have to abort it */
2772 cmd->host_scribble = (unsigned char *) c;
2773
2774 c->cmd_type = CMD_SCSI;
2775 c->scsi_cmd = cmd;
e1f7de0c 2776
283b4a9b
SC		 2777 /* Call alternate submit routine for I/O accelerated commands.
2778 * Retries always go down the normal I/O path.
2779 */
2780 if (likely(cmd->retries == 0 &&
2781 cmd->request->cmd_type == REQ_TYPE_FS)) {
2782 if (dev->offload_enabled) {
2783 rc = hpsa_scsi_ioaccel_raid_map(h, c);
2784 if (rc == 0)
2785 return 0; /* Sent on ioaccel path */
2786 if (rc < 0) { /* scsi_dma_map failed. */
2787 cmd_free(h, c);
2788 return SCSI_MLQUEUE_HOST_BUSY;
2789 }
2790 } else if (dev->ioaccel_handle) {
2791 rc = hpsa_scsi_ioaccel_direct_map(h, c);
2792 if (rc == 0)
2793 return 0; /* Sent on direct map path */
2794 if (rc < 0) { /* scsi_dma_map failed. */
2795 cmd_free(h, c);
2796 return SCSI_MLQUEUE_HOST_BUSY;
2797 }
2798 }
2799 }
e1f7de0c 2800
edd16368
SC		 2801 c->Header.ReplyQueue = 0; /* unused in simple mode */
2802 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 2803 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
2804 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 2805
2806 /* Fill in the request block... */
2807
2808 c->Request.Timeout = 0;
2809 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
2810 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
2811 c->Request.CDBLen = cmd->cmd_len;
2812 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
2813 c->Request.Type.Type = TYPE_CMD;
2814 c->Request.Type.Attribute = ATTR_SIMPLE;
2815 switch (cmd->sc_data_direction) {
2816 case DMA_TO_DEVICE:
2817 c->Request.Type.Direction = XFER_WRITE;
2818 break;
2819 case DMA_FROM_DEVICE:
2820 c->Request.Type.Direction = XFER_READ;
2821 break;
2822 case DMA_NONE:
2823 c->Request.Type.Direction = XFER_NONE;
2824 break;
2825 case DMA_BIDIRECTIONAL:
2826 /* This can happen if a buggy application does a scsi passthru
2827 * and sets both inlen and outlen to non-zero. ( see
2828 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
2829 */
2830
2831 c->Request.Type.Direction = XFER_RSVD;
2832 /* This is technically wrong, and hpsa controllers should
2833 * reject it with CMD_INVALID, which is the most correct
2834 * response, but non-fibre backends appear to let it
2835 * slide by, and give the same results as if this field
2836 * were set correctly. Either way is acceptable for
2837 * our purposes here.
2838 */
2839
2840 break;
2841
2842 default:
2843 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2844 cmd->sc_data_direction);
2845 BUG();
2846 break;
2847 }
2848
33a2ffce 2849 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 2850 cmd_free(h, c);
2851 return SCSI_MLQUEUE_HOST_BUSY;
2852 }
2853 enqueue_cmd_and_start_io(h, c);
2854 /* the cmd'll come back via intr handler in complete_scsi_command() */
2855 return 0;
2856}
2857
f281233d
JG		 2858static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
2859
a08a8471
SC		 2860static void hpsa_scan_start(struct Scsi_Host *sh)
2861{
2862 struct ctlr_info *h = shost_to_hba(sh);
2863 unsigned long flags;
2864
2865 /* wait until any scan already in progress is finished. */
2866 while (1) {
2867 spin_lock_irqsave(&h->scan_lock, flags);
2868 if (h->scan_finished)
2869 break;
2870 spin_unlock_irqrestore(&h->scan_lock, flags);
2871 wait_event(h->scan_wait_queue, h->scan_finished);
2872 /* Note: We don't need to worry about a race between this
2873 * thread and driver unload because the midlayer will
2874 * have incremented the reference count, so unload won't
2875 * happen if we're in here.
2876 */
2877 }
2878 h->scan_finished = 0; /* mark scan as in progress */
2879 spin_unlock_irqrestore(&h->scan_lock, flags);
2880
2881 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
2882
2883 spin_lock_irqsave(&h->scan_lock, flags);
2884 h->scan_finished = 1; /* mark scan as finished. */
2885 wake_up_all(&h->scan_wait_queue);
2886 spin_unlock_irqrestore(&h->scan_lock, flags);
2887}
2888
2889static int hpsa_scan_finished(struct Scsi_Host *sh,
2890 unsigned long elapsed_time)
2891{
2892 struct ctlr_info *h = shost_to_hba(sh);
2893 unsigned long flags;
2894 int finished;
2895
2896 spin_lock_irqsave(&h->scan_lock, flags);
2897 finished = h->scan_finished;
2898 spin_unlock_irqrestore(&h->scan_lock, flags);
2899 return finished;
2900}
2901
667e23d4
SC		 2902static int hpsa_change_queue_depth(struct scsi_device *sdev,
2903 int qdepth, int reason)
2904{
2905 struct ctlr_info *h = sdev_to_hba(sdev);
2906
2907 if (reason != SCSI_QDEPTH_DEFAULT)
2908 return -ENOTSUPP;
2909
2910 if (qdepth < 1)
2911 qdepth = 1;
2912 else
2913 if (qdepth > h->nr_cmds)
2914 qdepth = h->nr_cmds;
2915 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
2916 return sdev->queue_depth;
2917}
2918
edd16368
SC		 2919static void hpsa_unregister_scsi(struct ctlr_info *h)
2920{
2921 /* we are being forcibly unloaded, and may not refuse. */
2922 scsi_remove_host(h->scsi_host);
2923 scsi_host_put(h->scsi_host);
2924 h->scsi_host = NULL;
2925}
2926
2927static int hpsa_register_scsi(struct ctlr_info *h)
2928{
b705690d
SC		 2929 struct Scsi_Host *sh;
2930 int error;
edd16368 2931
b705690d
SC		 2932 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2933 if (sh == NULL)
2934 goto fail;
2935
2936 sh->io_port = 0;
2937 sh->n_io_port = 0;
2938 sh->this_id = -1;
2939 sh->max_channel = 3;
2940 sh->max_cmd_len = MAX_COMMAND_SIZE;
2941 sh->max_lun = HPSA_MAX_LUN;
2942 sh->max_id = HPSA_MAX_LUN;
2943 sh->can_queue = h->nr_cmds;
2944 sh->cmd_per_lun = h->nr_cmds;
2945 sh->sg_tablesize = h->maxsgentries;
2946 h->scsi_host = sh;
2947 sh->hostdata[0] = (unsigned long) h;
2948 sh->irq = h->intr[h->intr_mode];
2949 sh->unique_id = sh->irq;
2950 error = scsi_add_host(sh, &h->pdev->dev);
2951 if (error)
2952 goto fail_host_put;
2953 scsi_scan_host(sh);
2954 return 0;
2955
2956 fail_host_put:
2957 dev_err(&h->pdev->dev, "%s: scsi_add_host"
2958 " failed for controller %d\n", __func__, h->ctlr);
2959 scsi_host_put(sh);
2960 return error;
2961 fail:
2962 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
2963 " failed for controller %d\n", __func__, h->ctlr);
2964 return -ENOMEM;
edd16368
SC		 2965}
2966
2967static int wait_for_device_to_become_ready(struct ctlr_info *h,
2968 unsigned char lunaddr[])
2969{
2970 int rc = 0;
2971 int count = 0;
2972 int waittime = 1; /* seconds */
2973 struct CommandList *c;
2974
2975 c = cmd_special_alloc(h);
2976 if (!c) {
2977 dev_warn(&h->pdev->dev, "out of memory in "
2978 "wait_for_device_to_become_ready.\n");
2979 return IO_ERROR;
2980 }
2981
2982 /* Send test unit ready until device ready, or give up. */
2983 while (count < HPSA_TUR_RETRY_LIMIT) {
2984
2985 /* Wait for a bit. do this first, because if we send
2986 * the TUR right away, the reset will just abort it.
2987 */
2988 msleep(1000 * waittime);
2989 count++;
2990
2991 /* Increase wait time with each try, up to a point. */
2992 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
2993 waittime = waittime * 2;
2994
a2dac136
SC		 2995 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
2996 (void) fill_cmd(c, TEST_UNIT_READY, h,
2997 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 2998 hpsa_scsi_do_simple_cmd_core(h, c);
2999 /* no unmap needed here because no data xfer. */
3000
3001 if (c->err_info->CommandStatus == CMD_SUCCESS)
3002 break;
3003
3004 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3005 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3006 (c->err_info->SenseInfo[2] == NO_SENSE ||
3007 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3008 break;
3009
3010 dev_warn(&h->pdev->dev, "waiting %d secs "
3011 "for device to become ready.\n", waittime);
3012 rc = 1; /* device not ready. */
3013 }
3014
3015 if (rc)
3016 dev_warn(&h->pdev->dev, "giving up on device.\n");
3017 else
3018 dev_warn(&h->pdev->dev, "device is ready.\n");
3019
3020 cmd_special_free(h, c);
3021 return rc;
3022}
3023
3024/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3025 * complaining. Doing a host- or bus-reset can't do anything good here.
3026 */
3027static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3028{
3029 int rc;
3030 struct ctlr_info *h;
3031 struct hpsa_scsi_dev_t *dev;
3032
3033 /* find the controller to which the command to be aborted was sent */
3034 h = sdev_to_hba(scsicmd->device);
3035 if (h == NULL) /* paranoia */
3036 return FAILED;
edd16368
SC		 3037 dev = scsicmd->device->hostdata;
3038 if (!dev) {
3039 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3040 "device lookup failed.\n");
3041 return FAILED;
3042 }
d416b0c7
SC		 3043 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3044 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 3045 /* send a reset to the SCSI LUN which the command was sent to */
3046 rc = hpsa_send_reset(h, dev->scsi3addr);
3047 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3048 return SUCCESS;
3049
3050 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3051 return FAILED;
3052}
3053
6cba3f19
SC		 3054static void swizzle_abort_tag(u8 *tag)
3055{
3056 u8 original_tag[8];
3057
3058 memcpy(original_tag, tag, 8);
3059 tag[0] = original_tag[3];
3060 tag[1] = original_tag[2];
3061 tag[2] = original_tag[1];
3062 tag[3] = original_tag[0];
3063 tag[4] = original_tag[7];
3064 tag[5] = original_tag[6];
3065 tag[6] = original_tag[5];
3066 tag[7] = original_tag[4];
3067}
3068
17eb87d2
ST		 3069static void hpsa_get_tag(struct ctlr_info *h,
3070 struct CommandList *c, u32 *taglower, u32 *tagupper)
3071{
3072 if (c->cmd_type == CMD_IOACCEL1) {
3073 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3074 &h->ioaccel_cmd_pool[c->cmdindex];
3075 *tagupper = cm1->Tag.upper;
3076 *taglower = cm1->Tag.lower;
3077 } else {
3078 *tagupper = c->Header.Tag.upper;
3079 *taglower = c->Header.Tag.lower;
3080 }
3081}
3082
75167d2c 3083static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3084 struct CommandList *abort, int swizzle)
75167d2c
SC		 3085{
3086 int rc = IO_OK;
3087 struct CommandList *c;
3088 struct ErrorInfo *ei;
17eb87d2 3089 u32 tagupper, taglower;
75167d2c
SC		 3090
3091 c = cmd_special_alloc(h);
3092 if (c == NULL) { /* trouble... */
3093 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3094 return -ENOMEM;
3095 }
3096
a2dac136
SC		 3097 /* fill_cmd can't fail here, no buffer to map */
3098 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3099 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3100 if (swizzle)
3101 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3102 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3103 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3104 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3105 __func__, tagupper, taglower);
75167d2c
SC		 3106 /* no unmap needed here because no data xfer. */
3107
3108 ei = c->err_info;
3109 switch (ei->CommandStatus) {
3110 case CMD_SUCCESS:
3111 break;
3112 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3113 rc = -1;
3114 break;
3115 default:
3116 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3117 __func__, tagupper, taglower);
75167d2c
SC		 3118 hpsa_scsi_interpret_error(c);
3119 rc = -1;
3120 break;
3121 }
3122 cmd_special_free(h, c);
3123 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3124 abort->Header.Tag.upper, abort->Header.Tag.lower);
3125 return rc;
3126}
3127
3128/*
3129 * hpsa_find_cmd_in_queue
3130 *
3131 * Used to determine whether a command (find) is still present
3132 * in queue_head. Optionally excludes the last element of queue_head.
3133 *
3134 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3135 * not yet been submitted, and so can be aborted by the driver without
3136 * sending an abort to the hardware.
3137 *
3138 * Returns pointer to command if found in queue, NULL otherwise.
3139 */
3140static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3141 struct scsi_cmnd *find, struct list_head *queue_head)
3142{
3143 unsigned long flags;
3144 struct CommandList *c = NULL; /* ptr into cmpQ */
3145
3146 if (!find)
3147 return 0;
3148 spin_lock_irqsave(&h->lock, flags);
3149 list_for_each_entry(c, queue_head, list) {
3150 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3151 continue;
3152 if (c->scsi_cmd == find) {
3153 spin_unlock_irqrestore(&h->lock, flags);
3154 return c;
3155 }
3156 }
3157 spin_unlock_irqrestore(&h->lock, flags);
3158 return NULL;
3159}
3160
6cba3f19
SC		 3161static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3162 u8 *tag, struct list_head *queue_head)
3163{
3164 unsigned long flags;
3165 struct CommandList *c;
3166
3167 spin_lock_irqsave(&h->lock, flags);
3168 list_for_each_entry(c, queue_head, list) {
3169 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3170 continue;
3171 spin_unlock_irqrestore(&h->lock, flags);
3172 return c;
3173 }
3174 spin_unlock_irqrestore(&h->lock, flags);
3175 return NULL;
3176}
3177
3178/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3179 * tell which kind we're dealing with, so we send the abort both ways. There
3180 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3181 * way we construct our tags but we check anyway in case the assumptions which
3182 * make this true someday become false.
3183 */
3184static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3185 unsigned char *scsi3addr, struct CommandList *abort)
3186{
3187 u8 swizzled_tag[8];
3188 struct CommandList *c;
3189 int rc = 0, rc2 = 0;
3190
3191 /* we do not expect to find the swizzled tag in our queue, but
3192 * check anyway just to be sure the assumptions which make this
3193 * the case haven't become wrong.
3194 */
3195 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3196 swizzle_abort_tag(swizzled_tag);
3197 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3198 if (c != NULL) {
3199 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3200 return hpsa_send_abort(h, scsi3addr, abort, 0);
3201 }
3202 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3203
3204 /* if the command is still in our queue, we can't conclude that it was
3205 * aborted (it might have just completed normally) but in any case
3206 * we don't need to try to abort it another way.
3207 */
3208 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3209 if (c)
3210 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3211 return rc && rc2;
3212}
3213
75167d2c
SC		 3214/* Send an abort for the specified command.
3215 * If the device and controller support it,
3216 * send a task abort request.
3217 */
3218static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3219{
3220
3221 int i, rc;
3222 struct ctlr_info *h;
3223 struct hpsa_scsi_dev_t *dev;
3224 struct CommandList *abort; /* pointer to command to be aborted */
3225 struct CommandList *found;
3226 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3227 char msg[256]; /* For debug messaging. */
3228 int ml = 0;
17eb87d2 3229 u32 tagupper, taglower;
75167d2c
SC		 3230
3231 /* Find the controller of the command to be aborted */
3232 h = sdev_to_hba(sc->device);
3233 if (WARN(h == NULL,
3234 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3235 return FAILED;
3236
3237 /* Check that controller supports some kind of task abort */
3238 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3239 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3240 return FAILED;
3241
3242 memset(msg, 0, sizeof(msg));
3243 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3244 h->scsi_host->host_no, sc->device->channel,
3245 sc->device->id, sc->device->lun);
3246
3247 /* Find the device of the command to be aborted */
3248 dev = sc->device->hostdata;
3249 if (!dev) {
3250 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3251 msg);
3252 return FAILED;
3253 }
3254
3255 /* Get SCSI command to be aborted */
3256 abort = (struct CommandList *) sc->host_scribble;
3257 if (abort == NULL) {
3258 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3259 msg);
3260 return FAILED;
3261 }
17eb87d2
ST		 3262 hpsa_get_tag(h, abort, &taglower, &tagupper);
3263 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3264 as = (struct scsi_cmnd *) abort->scsi_cmd;
3265 if (as != NULL)
3266 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3267 as->cmnd[0], as->serial_number);
3268 dev_dbg(&h->pdev->dev, "%s\n", msg);
3269 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3270 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3271
3272 /* Search reqQ to See if command is queued but not submitted,
3273 * if so, complete the command with aborted status and remove
3274 * it from the reqQ.
3275 */
3276 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3277 if (found) {
3278 found->err_info->CommandStatus = CMD_ABORTED;
3279 finish_cmd(found);
3280 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3281 msg);
3282 return SUCCESS;
3283 }
3284
3285 /* not in reqQ, if also not in cmpQ, must have already completed */
3286 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3287 if (!found) {
d6ebd0f7 3288 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 3289 msg);
3290 return SUCCESS;
3291 }
3292
3293 /*
3294 * Command is in flight, or possibly already completed
3295 * by the firmware (but not to the scsi mid layer) but we can't
3296 * distinguish which. Send the abort down.
3297 */
6cba3f19 3298 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 3299 if (rc != 0) {
3300 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
3301 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
3302 h->scsi_host->host_no,
3303 dev->bus, dev->target, dev->lun);
3304 return FAILED;
3305 }
3306 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
3307
3308 /* If the abort(s) above completed and actually aborted the
3309 * command, then the command to be aborted should already be
3310 * completed. If not, wait around a bit more to see if they
3311 * manage to complete normally.
3312 */
3313#define ABORT_COMPLETE_WAIT_SECS 30
3314 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
3315 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3316 if (!found)
3317 return SUCCESS;
3318 msleep(100);
3319 }
3320 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
3321 msg, ABORT_COMPLETE_WAIT_SECS);
3322 return FAILED;
3323}
3324
3325
edd16368
SC		 3326/*
3327 * For operations that cannot sleep, a command block is allocated at init,
3328 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
3329 * which ones are free or in use. Lock must be held when calling this.
3330 * cmd_free() is the complement.
3331 */
3332static struct CommandList *cmd_alloc(struct ctlr_info *h)
3333{
3334 struct CommandList *c;
3335 int i;
3336 union u64bit temp64;
3337 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 3338 unsigned long flags;
edd16368 3339
e16a33ad 3340 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3341 do {
3342 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 3343 if (i == h->nr_cmds) {
3344 spin_unlock_irqrestore(&h->lock, flags);
edd16368 3345 return NULL;
e16a33ad 3346 }
edd16368
SC		 3347 } while (test_and_set_bit
3348 (i & (BITS_PER_LONG - 1),
3349 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 3350 spin_unlock_irqrestore(&h->lock, flags);
3351
edd16368
SC		 3352 c = h->cmd_pool + i;
3353 memset(c, 0, sizeof(*c));
3354 cmd_dma_handle = h->cmd_pool_dhandle
3355 + i * sizeof(*c);
3356 c->err_info = h->errinfo_pool + i;
3357 memset(c->err_info, 0, sizeof(*c->err_info));
3358 err_dma_handle = h->errinfo_pool_dhandle
3359 + i * sizeof(*c->err_info);
edd16368
SC		 3360
3361 c->cmdindex = i;
3362
9e0fc764 3363 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3364 c->busaddr = (u32) cmd_dma_handle;
3365 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3366 c->ErrDesc.Addr.lower = temp64.val32.lower;
3367 c->ErrDesc.Addr.upper = temp64.val32.upper;
3368 c->ErrDesc.Len = sizeof(*c->err_info);
3369
3370 c->h = h;
3371 return c;
3372}
3373
3374/* For operations that can wait for kmalloc to possibly sleep,
3375 * this routine can be called. Lock need not be held to call
3376 * cmd_special_alloc. cmd_special_free() is the complement.
3377 */
3378static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
3379{
3380 struct CommandList *c;
3381 union u64bit temp64;
3382 dma_addr_t cmd_dma_handle, err_dma_handle;
3383
3384 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
3385 if (c == NULL)
3386 return NULL;
3387 memset(c, 0, sizeof(*c));
3388
e1f7de0c 3389 c->cmd_type = CMD_SCSI;
edd16368
SC		 3390 c->cmdindex = -1;
3391
3392 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
3393 &err_dma_handle);
3394
3395 if (c->err_info == NULL) {
3396 pci_free_consistent(h->pdev,
3397 sizeof(*c), c, cmd_dma_handle);
3398 return NULL;
3399 }
3400 memset(c->err_info, 0, sizeof(*c->err_info));
3401
9e0fc764 3402 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3403 c->busaddr = (u32) cmd_dma_handle;
3404 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3405 c->ErrDesc.Addr.lower = temp64.val32.lower;
3406 c->ErrDesc.Addr.upper = temp64.val32.upper;
3407 c->ErrDesc.Len = sizeof(*c->err_info);
3408
3409 c->h = h;
3410 return c;
3411}
3412
3413static void cmd_free(struct ctlr_info *h, struct CommandList *c)
3414{
3415 int i;
e16a33ad 3416 unsigned long flags;
edd16368
SC		 3417
3418 i = c - h->cmd_pool;
e16a33ad 3419 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3420 clear_bit(i & (BITS_PER_LONG - 1),
3421 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 3422 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 3423}
3424
3425static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
3426{
3427 union u64bit temp64;
3428
3429 temp64.val32.lower = c->ErrDesc.Addr.lower;
3430 temp64.val32.upper = c->ErrDesc.Addr.upper;
3431 pci_free_consistent(h->pdev, sizeof(*c->err_info),
3432 c->err_info, (dma_addr_t) temp64.val);
3433 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 3434 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 3435}
3436
3437#ifdef CONFIG_COMPAT
3438
edd16368
SC		 3439static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
3440{
3441 IOCTL32_Command_struct __user *arg32 =
3442 (IOCTL32_Command_struct __user *) arg;
3443 IOCTL_Command_struct arg64;
3444 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
3445 int err;
3446 u32 cp;
3447
938abd84 3448 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3449 err = 0;
3450 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3451 sizeof(arg64.LUN_info));
3452 err |= copy_from_user(&arg64.Request, &arg32->Request,
3453 sizeof(arg64.Request));
3454 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3455 sizeof(arg64.error_info));
3456 err |= get_user(arg64.buf_size, &arg32->buf_size);
3457 err |= get_user(cp, &arg32->buf);
3458 arg64.buf = compat_ptr(cp);
3459 err |= copy_to_user(p, &arg64, sizeof(arg64));
3460
3461 if (err)
3462 return -EFAULT;
3463
e39eeaed 3464 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 3465 if (err)
3466 return err;
3467 err |= copy_in_user(&arg32->error_info, &p->error_info,
3468 sizeof(arg32->error_info));
3469 if (err)
3470 return -EFAULT;
3471 return err;
3472}
3473
3474static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
3475 int cmd, void *arg)
3476{
3477 BIG_IOCTL32_Command_struct __user *arg32 =
3478 (BIG_IOCTL32_Command_struct __user *) arg;
3479 BIG_IOCTL_Command_struct arg64;
3480 BIG_IOCTL_Command_struct __user *p =
3481 compat_alloc_user_space(sizeof(arg64));
3482 int err;
3483 u32 cp;
3484
938abd84 3485 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3486 err = 0;
3487 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3488 sizeof(arg64.LUN_info));
3489 err |= copy_from_user(&arg64.Request, &arg32->Request,
3490 sizeof(arg64.Request));
3491 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3492 sizeof(arg64.error_info));
3493 err |= get_user(arg64.buf_size, &arg32->buf_size);
3494 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
3495 err |= get_user(cp, &arg32->buf);
3496 arg64.buf = compat_ptr(cp);
3497 err |= copy_to_user(p, &arg64, sizeof(arg64));
3498
3499 if (err)
3500 return -EFAULT;
3501
e39eeaed 3502 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 3503 if (err)
3504 return err;
3505 err |= copy_in_user(&arg32->error_info, &p->error_info,
3506 sizeof(arg32->error_info));
3507 if (err)
3508 return -EFAULT;
3509 return err;
3510}
71fe75a7
SC		 3511
3512static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
3513{
3514 switch (cmd) {
3515 case CCISS_GETPCIINFO:
3516 case CCISS_GETINTINFO:
3517 case CCISS_SETINTINFO:
3518 case CCISS_GETNODENAME:
3519 case CCISS_SETNODENAME:
3520 case CCISS_GETHEARTBEAT:
3521 case CCISS_GETBUSTYPES:
3522 case CCISS_GETFIRMVER:
3523 case CCISS_GETDRIVVER:
3524 case CCISS_REVALIDVOLS:
3525 case CCISS_DEREGDISK:
3526 case CCISS_REGNEWDISK:
3527 case CCISS_REGNEWD:
3528 case CCISS_RESCANDISK:
3529 case CCISS_GETLUNINFO:
3530 return hpsa_ioctl(dev, cmd, arg);
3531
3532 case CCISS_PASSTHRU32:
3533 return hpsa_ioctl32_passthru(dev, cmd, arg);
3534 case CCISS_BIG_PASSTHRU32:
3535 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
3536
3537 default:
3538 return -ENOIOCTLCMD;
3539 }
3540}
edd16368
SC		 3541#endif
3542
3543static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
3544{
3545 struct hpsa_pci_info pciinfo;
3546
3547 if (!argp)
3548 return -EINVAL;
3549 pciinfo.domain = pci_domain_nr(h->pdev->bus);
3550 pciinfo.bus = h->pdev->bus->number;
3551 pciinfo.dev_fn = h->pdev->devfn;
3552 pciinfo.board_id = h->board_id;
3553 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
3554 return -EFAULT;
3555 return 0;
3556}
3557
3558static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
3559{
3560 DriverVer_type DriverVer;
3561 unsigned char vmaj, vmin, vsubmin;
3562 int rc;
3563
3564 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
3565 &vmaj, &vmin, &vsubmin);
3566 if (rc != 3) {
3567 dev_info(&h->pdev->dev, "driver version string '%s' "
3568 "unrecognized.", HPSA_DRIVER_VERSION);
3569 vmaj = 0;
3570 vmin = 0;
3571 vsubmin = 0;
3572 }
3573 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
3574 if (!argp)
3575 return -EINVAL;
3576 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
3577 return -EFAULT;
3578 return 0;
3579}
3580
3581static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
3582{
3583 IOCTL_Command_struct iocommand;
3584 struct CommandList *c;
3585 char *buff = NULL;
3586 union u64bit temp64;
c1f63c8f 3587 int rc = 0;
edd16368
SC		 3588
3589 if (!argp)
3590 return -EINVAL;
3591 if (!capable(CAP_SYS_RAWIO))
3592 return -EPERM;
3593 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
3594 return -EFAULT;
3595 if ((iocommand.buf_size < 1) &&
3596 (iocommand.Request.Type.Direction != XFER_NONE)) {
3597 return -EINVAL;
3598 }
3599 if (iocommand.buf_size > 0) {
3600 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
3601 if (buff == NULL)
3602 return -EFAULT;
b03a7771
SC		 3603 if (iocommand.Request.Type.Direction == XFER_WRITE) {
3604 /* Copy the data into the buffer we created */
3605 if (copy_from_user(buff, iocommand.buf,
3606 iocommand.buf_size)) {
c1f63c8f
SC		 3607 rc = -EFAULT;
3608 goto out_kfree;
b03a7771
SC		 3609 }
3610 } else {
3611 memset(buff, 0, iocommand.buf_size);
edd16368 3612 }
b03a7771 3613 }
edd16368
SC		 3614 c = cmd_special_alloc(h);
3615 if (c == NULL) {
c1f63c8f
SC		 3616 rc = -ENOMEM;
3617 goto out_kfree;
edd16368
SC		 3618 }
3619 /* Fill in the command type */
3620 c->cmd_type = CMD_IOCTL_PEND;
3621 /* Fill in Command Header */
3622 c->Header.ReplyQueue = 0; /* unused in simple mode */
3623 if (iocommand.buf_size > 0) { /* buffer to fill */
3624 c->Header.SGList = 1;
3625 c->Header.SGTotal = 1;
3626 } else { /* no buffers to fill */
3627 c->Header.SGList = 0;
3628 c->Header.SGTotal = 0;
3629 }
3630 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
3631 /* use the kernel address the cmd block for tag */
3632 c->Header.Tag.lower = c->busaddr;
3633
3634 /* Fill in Request block */
3635 memcpy(&c->Request, &iocommand.Request,
3636 sizeof(c->Request));
3637
3638 /* Fill in the scatter gather information */
3639 if (iocommand.buf_size > 0) {
3640 temp64.val = pci_map_single(h->pdev, buff,
3641 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 3642 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3643 c->SG[0].Addr.lower = 0;
3644 c->SG[0].Addr.upper = 0;
3645 c->SG[0].Len = 0;
3646 rc = -ENOMEM;
3647 goto out;
3648 }
edd16368
SC		 3649 c->SG[0].Addr.lower = temp64.val32.lower;
3650 c->SG[0].Addr.upper = temp64.val32.upper;
3651 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 3652 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 3653 }
a0c12413 3654 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 3655 if (iocommand.buf_size > 0)
3656 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 3657 check_ioctl_unit_attention(h, c);
3658
3659 /* Copy the error information out */
3660 memcpy(&iocommand.error_info, c->err_info,
3661 sizeof(iocommand.error_info));
3662 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 3663 rc = -EFAULT;
3664 goto out;
edd16368 3665 }
b03a7771
SC		 3666 if (iocommand.Request.Type.Direction == XFER_READ &&
3667 iocommand.buf_size > 0) {
edd16368
SC		 3668 /* Copy the data out of the buffer we created */
3669 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 3670 rc = -EFAULT;
3671 goto out;
edd16368
SC		 3672 }
3673 }
c1f63c8f 3674out:
edd16368 3675 cmd_special_free(h, c);
c1f63c8f
SC		 3676out_kfree:
3677 kfree(buff);
3678 return rc;
edd16368
SC		 3679}
3680
3681static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
3682{
3683 BIG_IOCTL_Command_struct *ioc;
3684 struct CommandList *c;
3685 unsigned char **buff = NULL;
3686 int *buff_size = NULL;
3687 union u64bit temp64;
3688 BYTE sg_used = 0;
3689 int status = 0;
3690 int i;
01a02ffc
SC		 3691 u32 left;
3692 u32 sz;
edd16368
SC		 3693 BYTE __user *data_ptr;
3694
3695 if (!argp)
3696 return -EINVAL;
3697 if (!capable(CAP_SYS_RAWIO))
3698 return -EPERM;
3699 ioc = (BIG_IOCTL_Command_struct *)
3700 kmalloc(sizeof(*ioc), GFP_KERNEL);
3701 if (!ioc) {
3702 status = -ENOMEM;
3703 goto cleanup1;
3704 }
3705 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
3706 status = -EFAULT;
3707 goto cleanup1;
3708 }
3709 if ((ioc->buf_size < 1) &&
3710 (ioc->Request.Type.Direction != XFER_NONE)) {
3711 status = -EINVAL;
3712 goto cleanup1;
3713 }
3714 /* Check kmalloc limits using all SGs */
3715 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
3716 status = -EINVAL;
3717 goto cleanup1;
3718 }
d66ae08b 3719 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 3720 status = -EINVAL;
3721 goto cleanup1;
3722 }
d66ae08b 3723 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 3724 if (!buff) {
3725 status = -ENOMEM;
3726 goto cleanup1;
3727 }
d66ae08b 3728 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 3729 if (!buff_size) {
3730 status = -ENOMEM;
3731 goto cleanup1;
3732 }
3733 left = ioc->buf_size;
3734 data_ptr = ioc->buf;
3735 while (left) {
3736 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
3737 buff_size[sg_used] = sz;
3738 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
3739 if (buff[sg_used] == NULL) {
3740 status = -ENOMEM;
3741 goto cleanup1;
3742 }
3743 if (ioc->Request.Type.Direction == XFER_WRITE) {
3744 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
3745 status = -ENOMEM;
3746 goto cleanup1;
3747 }
3748 } else
3749 memset(buff[sg_used], 0, sz);
3750 left -= sz;
3751 data_ptr += sz;
3752 sg_used++;
3753 }
3754 c = cmd_special_alloc(h);
3755 if (c == NULL) {
3756 status = -ENOMEM;
3757 goto cleanup1;
3758 }
3759 c->cmd_type = CMD_IOCTL_PEND;
3760 c->Header.ReplyQueue = 0;
b03a7771 3761 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 3762 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
3763 c->Header.Tag.lower = c->busaddr;
3764 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
3765 if (ioc->buf_size > 0) {
3766 int i;
3767 for (i = 0; i < sg_used; i++) {
3768 temp64.val = pci_map_single(h->pdev, buff[i],
3769 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 3770 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3771 c->SG[i].Addr.lower = 0;
3772 c->SG[i].Addr.upper = 0;
3773 c->SG[i].Len = 0;
3774 hpsa_pci_unmap(h->pdev, c, i,
3775 PCI_DMA_BIDIRECTIONAL);
3776 status = -ENOMEM;
e2d4a1f6 3777 goto cleanup0;
bcc48ffa 3778 }
edd16368
SC		 3779 c->SG[i].Addr.lower = temp64.val32.lower;
3780 c->SG[i].Addr.upper = temp64.val32.upper;
3781 c->SG[i].Len = buff_size[i];
e1d9cbfa 3782 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 3783 }
3784 }
a0c12413 3785 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 3786 if (sg_used)
3787 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 3788 check_ioctl_unit_attention(h, c);
3789 /* Copy the error information out */
3790 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
3791 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 3792 status = -EFAULT;
e2d4a1f6 3793 goto cleanup0;
edd16368 3794 }
b03a7771 3795 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 3796 /* Copy the data out of the buffer we created */
3797 BYTE __user *ptr = ioc->buf;
3798 for (i = 0; i < sg_used; i++) {
3799 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 3800 status = -EFAULT;
e2d4a1f6 3801 goto cleanup0;
edd16368
SC		 3802 }
3803 ptr += buff_size[i];
3804 }
3805 }
edd16368 3806 status = 0;
e2d4a1f6
SC		 3807cleanup0:
3808 cmd_special_free(h, c);
edd16368
SC		 3809cleanup1:
3810 if (buff) {
3811 for (i = 0; i < sg_used; i++)
3812 kfree(buff[i]);
3813 kfree(buff);
3814 }
3815 kfree(buff_size);
3816 kfree(ioc);
3817 return status;
3818}
3819
3820static void check_ioctl_unit_attention(struct ctlr_info *h,
3821 struct CommandList *c)
3822{
3823 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3824 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
3825 (void) check_for_unit_attention(h, c);
3826}
0390f0c0
SC		 3827
3828static int increment_passthru_count(struct ctlr_info *h)
3829{
3830 unsigned long flags;
3831
3832 spin_lock_irqsave(&h->passthru_count_lock, flags);
3833 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
3834 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3835 return -1;
3836 }
3837 h->passthru_count++;
3838 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3839 return 0;
3840}
3841
3842static void decrement_passthru_count(struct ctlr_info *h)
3843{
3844 unsigned long flags;
3845
3846 spin_lock_irqsave(&h->passthru_count_lock, flags);
3847 if (h->passthru_count <= 0) {
3848 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3849 /* not expecting to get here. */
3850 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
3851 return;
3852 }
3853 h->passthru_count--;
3854 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
3855}
3856
edd16368
SC		 3857/*
3858 * ioctl
3859 */
3860static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
3861{
3862 struct ctlr_info *h;
3863 void __user *argp = (void __user *)arg;
0390f0c0 3864 int rc;
edd16368
SC		 3865
3866 h = sdev_to_hba(dev);
3867
3868 switch (cmd) {
3869 case CCISS_DEREGDISK:
3870 case CCISS_REGNEWDISK:
3871 case CCISS_REGNEWD:
a08a8471 3872 hpsa_scan_start(h->scsi_host);
edd16368
SC		 3873 return 0;
3874 case CCISS_GETPCIINFO:
3875 return hpsa_getpciinfo_ioctl(h, argp);
3876 case CCISS_GETDRIVVER:
3877 return hpsa_getdrivver_ioctl(h, argp);
3878 case CCISS_PASSTHRU:
0390f0c0
SC		 3879 if (increment_passthru_count(h))
3880 return -EAGAIN;
3881 rc = hpsa_passthru_ioctl(h, argp);
3882 decrement_passthru_count(h);
3883 return rc;
edd16368 3884 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 3885 if (increment_passthru_count(h))
3886 return -EAGAIN;
3887 rc = hpsa_big_passthru_ioctl(h, argp);
3888 decrement_passthru_count(h);
3889 return rc;
edd16368
SC		 3890 default:
3891 return -ENOTTY;
3892 }
3893}
3894
6f039790
GKH		 3895static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
3896 u8 reset_type)
64670ac8
SC		 3897{
3898 struct CommandList *c;
3899
3900 c = cmd_alloc(h);
3901 if (!c)
3902 return -ENOMEM;
a2dac136
SC		 3903 /* fill_cmd can't fail here, no data buffer to map */
3904 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 3905 RAID_CTLR_LUNID, TYPE_MSG);
3906 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
3907 c->waiting = NULL;
3908 enqueue_cmd_and_start_io(h, c);
3909 /* Don't wait for completion, the reset won't complete. Don't free
3910 * the command either. This is the last command we will send before
3911 * re-initializing everything, so it doesn't matter and won't leak.
3912 */
3913 return 0;
3914}
3915
a2dac136 3916static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 3917 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 3918 int cmd_type)
3919{
3920 int pci_dir = XFER_NONE;
75167d2c 3921 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 3922
3923 c->cmd_type = CMD_IOCTL_PEND;
3924 c->Header.ReplyQueue = 0;
3925 if (buff != NULL && size > 0) {
3926 c->Header.SGList = 1;
3927 c->Header.SGTotal = 1;
3928 } else {
3929 c->Header.SGList = 0;
3930 c->Header.SGTotal = 0;
3931 }
3932 c->Header.Tag.lower = c->busaddr;
3933 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
3934
3935 c->Request.Type.Type = cmd_type;
3936 if (cmd_type == TYPE_CMD) {
3937 switch (cmd) {
3938 case HPSA_INQUIRY:
3939 /* are we trying to read a vital product page */
3940 if (page_code != 0) {
3941 c->Request.CDB[1] = 0x01;
3942 c->Request.CDB[2] = page_code;
3943 }
3944 c->Request.CDBLen = 6;
3945 c->Request.Type.Attribute = ATTR_SIMPLE;
3946 c->Request.Type.Direction = XFER_READ;
3947 c->Request.Timeout = 0;
3948 c->Request.CDB[0] = HPSA_INQUIRY;
3949 c->Request.CDB[4] = size & 0xFF;
3950 break;
3951 case HPSA_REPORT_LOG:
3952 case HPSA_REPORT_PHYS:
3953 /* Talking to controller so It's a physical command
3954 mode = 00 target = 0. Nothing to write.
3955 */
3956 c->Request.CDBLen = 12;
3957 c->Request.Type.Attribute = ATTR_SIMPLE;
3958 c->Request.Type.Direction = XFER_READ;
3959 c->Request.Timeout = 0;
3960 c->Request.CDB[0] = cmd;
3961 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
3962 c->Request.CDB[7] = (size >> 16) & 0xFF;
3963 c->Request.CDB[8] = (size >> 8) & 0xFF;
3964 c->Request.CDB[9] = size & 0xFF;
3965 break;
edd16368
SC		 3966 case HPSA_CACHE_FLUSH:
3967 c->Request.CDBLen = 12;
3968 c->Request.Type.Attribute = ATTR_SIMPLE;
3969 c->Request.Type.Direction = XFER_WRITE;
3970 c->Request.Timeout = 0;
3971 c->Request.CDB[0] = BMIC_WRITE;
3972 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 3973 c->Request.CDB[7] = (size >> 8) & 0xFF;
3974 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 3975 break;
3976 case TEST_UNIT_READY:
3977 c->Request.CDBLen = 6;
3978 c->Request.Type.Attribute = ATTR_SIMPLE;
3979 c->Request.Type.Direction = XFER_NONE;
3980 c->Request.Timeout = 0;
3981 break;
283b4a9b
SC		 3982 case HPSA_GET_RAID_MAP:
3983 c->Request.CDBLen = 12;
3984 c->Request.Type.Attribute = ATTR_SIMPLE;
3985 c->Request.Type.Direction = XFER_READ;
3986 c->Request.Timeout = 0;
3987 c->Request.CDB[0] = HPSA_CISS_READ;
3988 c->Request.CDB[1] = cmd;
3989 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
3990 c->Request.CDB[7] = (size >> 16) & 0xFF;
3991 c->Request.CDB[8] = (size >> 8) & 0xFF;
3992 c->Request.CDB[9] = size & 0xFF;
3993 break;
edd16368
SC		 3994 default:
3995 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
3996 BUG();
a2dac136 3997 return -1;
edd16368
SC		 3998 }
3999 } else if (cmd_type == TYPE_MSG) {
4000 switch (cmd) {
4001
4002 case HPSA_DEVICE_RESET_MSG:
4003 c->Request.CDBLen = 16;
4004 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4005 c->Request.Type.Attribute = ATTR_SIMPLE;
4006 c->Request.Type.Direction = XFER_NONE;
4007 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4008 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4009 c->Request.CDB[0] = cmd;
21e89afd 4010 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4011 /* If bytes 4-7 are zero, it means reset the */
4012 /* LunID device */
4013 c->Request.CDB[4] = 0x00;
4014 c->Request.CDB[5] = 0x00;
4015 c->Request.CDB[6] = 0x00;
4016 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4017 break;
4018 case HPSA_ABORT_MSG:
4019 a = buff; /* point to command to be aborted */
4020 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4021 a->Header.Tag.upper, a->Header.Tag.lower,
4022 c->Header.Tag.upper, c->Header.Tag.lower);
4023 c->Request.CDBLen = 16;
4024 c->Request.Type.Type = TYPE_MSG;
4025 c->Request.Type.Attribute = ATTR_SIMPLE;
4026 c->Request.Type.Direction = XFER_WRITE;
4027 c->Request.Timeout = 0; /* Don't time out */
4028 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4029 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4030 c->Request.CDB[2] = 0x00; /* reserved */
4031 c->Request.CDB[3] = 0x00; /* reserved */
4032 /* Tag to abort goes in CDB[4]-CDB[11] */
4033 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4034 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4035 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4036 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4037 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4038 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4039 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4040 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4041 c->Request.CDB[12] = 0x00; /* reserved */
4042 c->Request.CDB[13] = 0x00; /* reserved */
4043 c->Request.CDB[14] = 0x00; /* reserved */
4044 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4045 break;
edd16368
SC		 4046 default:
4047 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4048 cmd);
4049 BUG();
4050 }
4051 } else {
4052 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4053 BUG();
4054 }
4055
4056 switch (c->Request.Type.Direction) {
4057 case XFER_READ:
4058 pci_dir = PCI_DMA_FROMDEVICE;
4059 break;
4060 case XFER_WRITE:
4061 pci_dir = PCI_DMA_TODEVICE;
4062 break;
4063 case XFER_NONE:
4064 pci_dir = PCI_DMA_NONE;
4065 break;
4066 default:
4067 pci_dir = PCI_DMA_BIDIRECTIONAL;
4068 }
a2dac136
SC		 4069 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4070 return -1;
4071 return 0;
edd16368
SC		 4072}
4073
4074/*
4075 * Map (physical) PCI mem into (virtual) kernel space
4076 */
4077static void __iomem *remap_pci_mem(ulong base, ulong size)
4078{
4079 ulong page_base = ((ulong) base) & PAGE_MASK;
4080 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4081 void __iomem *page_remapped = ioremap_nocache(page_base,
4082 page_offs + size);
edd16368
SC		 4083
4084 return page_remapped ? (page_remapped + page_offs) : NULL;
4085}
4086
4087/* Takes cmds off the submission queue and sends them to the hardware,
4088 * then puts them on the queue of cmds waiting for completion.
4089 */
4090static void start_io(struct ctlr_info *h)
4091{
4092 struct CommandList *c;
e16a33ad 4093 unsigned long flags;
edd16368 4094
e16a33ad 4095 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4096 while (!list_empty(&h->reqQ)) {
4097 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4098 /* can't do anything if fifo is full */
4099 if ((h->access.fifo_full(h))) {
396883e2 4100 h->fifo_recently_full = 1;
edd16368
SC		 4101 dev_warn(&h->pdev->dev, "fifo full\n");
4102 break;
4103 }
396883e2 4104 h->fifo_recently_full = 0;
edd16368
SC		 4105
4106 /* Get the first entry from the Request Q */
4107 removeQ(c);
4108 h->Qdepth--;
4109
edd16368
SC		 4110 /* Put job onto the completed Q */
4111 addQ(&h->cmpQ, c);
e16a33ad
MG		 4112
4113 /* Must increment commands_outstanding before unlocking
4114 * and submitting to avoid race checking for fifo full
4115 * condition.
4116 */
4117 h->commands_outstanding++;
4118 if (h->commands_outstanding > h->max_outstanding)
4119 h->max_outstanding = h->commands_outstanding;
4120
4121 /* Tell the controller execute command */
4122 spin_unlock_irqrestore(&h->lock, flags);
4123 h->access.submit_command(h, c);
4124 spin_lock_irqsave(&h->lock, flags);
edd16368 4125 }
e16a33ad 4126 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4127}
4128
254f796b 4129static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4130{
254f796b 4131 return h->access.command_completed(h, q);
edd16368
SC		 4132}
4133
900c5440 4134static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4135{
4136 return h->access.intr_pending(h);
4137}
4138
4139static inline long interrupt_not_for_us(struct ctlr_info *h)
4140{
10f66018
SC		 4141 return (h->access.intr_pending(h) == 0) ||
4142 (h->interrupts_enabled == 0);
edd16368
SC		 4143}
4144
01a02ffc
SC		 4145static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4146 u32 raw_tag)
edd16368
SC		 4147{
4148 if (unlikely(tag_index >= h->nr_cmds)) {
4149 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4150 return 1;
4151 }
4152 return 0;
4153}
4154
5a3d16f5 4155static inline void finish_cmd(struct CommandList *c)
edd16368 4156{
e16a33ad 4157 unsigned long flags;
396883e2
SC		 4158 int io_may_be_stalled = 0;
4159 struct ctlr_info *h = c->h;
e16a33ad 4160
396883e2 4161 spin_lock_irqsave(&h->lock, flags);
edd16368 4162 removeQ(c);
396883e2
SC		 4163
4164 /*
4165 * Check for possibly stalled i/o.
4166 *
4167 * If a fifo_full condition is encountered, requests will back up
4168 * in h->reqQ. This queue is only emptied out by start_io which is
4169 * only called when a new i/o request comes in. If no i/o's are
4170 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4171 * start_io from here if we detect such a danger.
4172 *
4173 * Normally, we shouldn't hit this case, but pounding on the
4174 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4175 * commands_outstanding is low. We want to avoid calling
4176 * start_io from in here as much as possible, and esp. don't
4177 * want to get in a cycle where we call start_io every time
4178 * through here.
4179 */
4180 if (unlikely(h->fifo_recently_full) &&
4181 h->commands_outstanding < 5)
4182 io_may_be_stalled = 1;
4183
4184 spin_unlock_irqrestore(&h->lock, flags);
4185
e85c5974 4186 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
e1f7de0c 4187 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI))
1fb011fb 4188 complete_scsi_command(c);
edd16368
SC		 4189 else if (c->cmd_type == CMD_IOCTL_PEND)
4190 complete(c->waiting);
396883e2
SC		 4191 if (unlikely(io_may_be_stalled))
4192 start_io(h);
edd16368
SC		 4193}
4194
a104c99f
SC		 4195static inline u32 hpsa_tag_contains_index(u32 tag)
4196{
a104c99f
SC		 4197 return tag & DIRECT_LOOKUP_BIT;
4198}
4199
4200static inline u32 hpsa_tag_to_index(u32 tag)
4201{
a104c99f
SC		 4202 return tag >> DIRECT_LOOKUP_SHIFT;
4203}
4204
a9a3a273
SC		 4205
4206static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4207{
a9a3a273
SC		 4208#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4209#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4210 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4211 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4212 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4213}
4214
303932fd 4215/* process completion of an indexed ("direct lookup") command */
1d94f94d 4216static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4217 u32 raw_tag)
4218{
4219 u32 tag_index;
4220 struct CommandList *c;
4221
4222 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4223 if (!bad_tag(h, tag_index, raw_tag)) {
4224 c = h->cmd_pool + tag_index;
4225 finish_cmd(c);
4226 }
303932fd
DB		 4227}
4228
4229/* process completion of a non-indexed command */
1d94f94d 4230static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4231 u32 raw_tag)
4232{
4233 u32 tag;
4234 struct CommandList *c = NULL;
e16a33ad 4235 unsigned long flags;
303932fd 4236
a9a3a273 4237 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4238 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4239 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4240 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4241 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4242 finish_cmd(c);
1d94f94d 4243 return;
303932fd
DB		 4244 }
4245 }
e16a33ad 4246 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4247 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4248}
4249
64670ac8
SC		 4250/* Some controllers, like p400, will give us one interrupt
4251 * after a soft reset, even if we turned interrupts off.
4252 * Only need to check for this in the hpsa_xxx_discard_completions
4253 * functions.
4254 */
4255static int ignore_bogus_interrupt(struct ctlr_info *h)
4256{
4257 if (likely(!reset_devices))
4258 return 0;
4259
4260 if (likely(h->interrupts_enabled))
4261 return 0;
4262
4263 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4264 "(known firmware bug.) Ignoring.\n");
4265
4266 return 1;
4267}
4268
254f796b
MG		 4269/*
4270 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4271 * Relies on (h-q[x] == x) being true for x such that
4272 * 0 <= x < MAX_REPLY_QUEUES.
4273 */
4274static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4275{
254f796b
MG		 4276 return container_of((queue - *queue), struct ctlr_info, q[0]);
4277}
4278
4279static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4280{
4281 struct ctlr_info *h = queue_to_hba(queue);
4282 u8 q = *(u8 *) queue;
64670ac8
SC		 4283 u32 raw_tag;
4284
4285 if (ignore_bogus_interrupt(h))
4286 return IRQ_NONE;
4287
4288 if (interrupt_not_for_us(h))
4289 return IRQ_NONE;
a0c12413 4290 h->last_intr_timestamp = get_jiffies_64();
64670ac8 4291 while (interrupt_pending(h)) {
254f796b 4292 raw_tag = get_next_completion(h, q);
64670ac8 4293 while (raw_tag != FIFO_EMPTY)
254f796b 4294 raw_tag = next_command(h, q);
64670ac8 4295 }
64670ac8
SC		 4296 return IRQ_HANDLED;
4297}
4298
254f796b 4299static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 4300{
254f796b 4301 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 4302 u32 raw_tag;
254f796b 4303 u8 q = *(u8 *) queue;
64670ac8
SC		 4304
4305 if (ignore_bogus_interrupt(h))
4306 return IRQ_NONE;
4307
a0c12413 4308 h->last_intr_timestamp = get_jiffies_64();
254f796b 4309 raw_tag = get_next_completion(h, q);
64670ac8 4310 while (raw_tag != FIFO_EMPTY)
254f796b 4311 raw_tag = next_command(h, q);
64670ac8
SC		 4312 return IRQ_HANDLED;
4313}
4314
254f796b 4315static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 4316{
254f796b 4317 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 4318 u32 raw_tag;
254f796b 4319 u8 q = *(u8 *) queue;
edd16368
SC		 4320
4321 if (interrupt_not_for_us(h))
4322 return IRQ_NONE;
a0c12413 4323 h->last_intr_timestamp = get_jiffies_64();
10f66018 4324 while (interrupt_pending(h)) {
254f796b 4325 raw_tag = get_next_completion(h, q);
10f66018 4326 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4327 if (likely(hpsa_tag_contains_index(raw_tag)))
4328 process_indexed_cmd(h, raw_tag);
10f66018 4329 else
1d94f94d 4330 process_nonindexed_cmd(h, raw_tag);
254f796b 4331 raw_tag = next_command(h, q);
10f66018
SC		 4332 }
4333 }
10f66018
SC		 4334 return IRQ_HANDLED;
4335}
4336
254f796b 4337static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 4338{
254f796b 4339 struct ctlr_info *h = queue_to_hba(queue);
10f66018 4340 u32 raw_tag;
254f796b 4341 u8 q = *(u8 *) queue;
10f66018 4342
a0c12413 4343 h->last_intr_timestamp = get_jiffies_64();
254f796b 4344 raw_tag = get_next_completion(h, q);
303932fd 4345 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4346 if (likely(hpsa_tag_contains_index(raw_tag)))
4347 process_indexed_cmd(h, raw_tag);
303932fd 4348 else
1d94f94d 4349 process_nonindexed_cmd(h, raw_tag);
254f796b 4350 raw_tag = next_command(h, q);
edd16368 4351 }
edd16368
SC		 4352 return IRQ_HANDLED;
4353}
4354
a9a3a273
SC		 4355/* Send a message CDB to the firmware. Careful, this only works
4356 * in simple mode, not performant mode due to the tag lookup.
4357 * We only ever use this immediately after a controller reset.
4358 */
6f039790
GKH		 4359static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
4360 unsigned char type)
edd16368
SC		 4361{
4362 struct Command {
4363 struct CommandListHeader CommandHeader;
4364 struct RequestBlock Request;
4365 struct ErrDescriptor ErrorDescriptor;
4366 };
4367 struct Command *cmd;
4368 static const size_t cmd_sz = sizeof(*cmd) +
4369 sizeof(cmd->ErrorDescriptor);
4370 dma_addr_t paddr64;
4371 uint32_t paddr32, tag;
4372 void __iomem *vaddr;
4373 int i, err;
4374
4375 vaddr = pci_ioremap_bar(pdev, 0);
4376 if (vaddr == NULL)
4377 return -ENOMEM;
4378
4379 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4380 * CCISS commands, so they must be allocated from the lower 4GiB of
4381 * memory.
4382 */
4383 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4384 if (err) {
4385 iounmap(vaddr);
4386 return -ENOMEM;
4387 }
4388
4389 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4390 if (cmd == NULL) {
4391 iounmap(vaddr);
4392 return -ENOMEM;
4393 }
4394
4395 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4396 * although there's no guarantee, we assume that the address is at
4397 * least 4-byte aligned (most likely, it's page-aligned).
4398 */
4399 paddr32 = paddr64;
4400
4401 cmd->CommandHeader.ReplyQueue = 0;
4402 cmd->CommandHeader.SGList = 0;
4403 cmd->CommandHeader.SGTotal = 0;
4404 cmd->CommandHeader.Tag.lower = paddr32;
4405 cmd->CommandHeader.Tag.upper = 0;
4406 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4407
4408 cmd->Request.CDBLen = 16;
4409 cmd->Request.Type.Type = TYPE_MSG;
4410 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4411 cmd->Request.Type.Direction = XFER_NONE;
4412 cmd->Request.Timeout = 0; /* Don't time out */
4413 cmd->Request.CDB[0] = opcode;
4414 cmd->Request.CDB[1] = type;
4415 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
4416 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
4417 cmd->ErrorDescriptor.Addr.upper = 0;
4418 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
4419
4420 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4421
4422 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
4423 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 4424 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 4425 break;
4426 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
4427 }
4428
4429 iounmap(vaddr);
4430
4431 /* we leak the DMA buffer here ... no choice since the controller could
4432 * still complete the command.
4433 */
4434 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
4435 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
4436 opcode, type);
4437 return -ETIMEDOUT;
4438 }
4439
4440 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4441
4442 if (tag & HPSA_ERROR_BIT) {
4443 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4444 opcode, type);
4445 return -EIO;
4446 }
4447
4448 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4449 opcode, type);
4450 return 0;
4451}
4452
edd16368
SC		 4453#define hpsa_noop(p) hpsa_message(p, 3, 0)
4454
1df8552a 4455static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 4456 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 4457{
4458 u16 pmcsr;
4459 int pos;
4460
4461 if (use_doorbell) {
4462 /* For everything after the P600, the PCI power state method
4463 * of resetting the controller doesn't work, so we have this
4464 * other way using the doorbell register.
4465 */
4466 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 4467 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 4468
4469 /* PMC hardware guys tell us we need a 5 second delay after
4470 * doorbell reset and before any attempt to talk to the board
4471 * at all to ensure that this actually works and doesn't fall
4472 * over in some weird corner cases.
4473 */
4474 msleep(5000);
1df8552a
SC		 4475 } else { /* Try to do it the PCI power state way */
4476
4477 /* Quoting from the Open CISS Specification: "The Power
4478 * Management Control/Status Register (CSR) controls the power
4479 * state of the device. The normal operating state is D0,
4480 * CSR=00h. The software off state is D3, CSR=03h. To reset
4481 * the controller, place the interface device in D3 then to D0,
4482 * this causes a secondary PCI reset which will reset the
4483 * controller." */
4484
4485 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4486 if (pos == 0) {
4487 dev_err(&pdev->dev,
4488 "hpsa_reset_controller: "
4489 "PCI PM not supported\n");
4490 return -ENODEV;
4491 }
4492 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4493 /* enter the D3hot power management state */
4494 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4495 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4496 pmcsr |= PCI_D3hot;
4497 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4498
4499 msleep(500);
4500
4501 /* enter the D0 power management state */
4502 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4503 pmcsr |= PCI_D0;
4504 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 4505
4506 /*
4507 * The P600 requires a small delay when changing states.
4508 * Otherwise we may think the board did not reset and we bail.
4509 * This for kdump only and is particular to the P600.
4510 */
4511 msleep(500);
1df8552a
SC		 4512 }
4513 return 0;
4514}
4515
6f039790 4516static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 4517{
4518 memset(driver_version, 0, len);
f79cfec6 4519 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 4520}
4521
6f039790 4522static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4523{
4524 char *driver_version;
4525 int i, size = sizeof(cfgtable->driver_version);
4526
4527 driver_version = kmalloc(size, GFP_KERNEL);
4528 if (!driver_version)
4529 return -ENOMEM;
4530
4531 init_driver_version(driver_version, size);
4532 for (i = 0; i < size; i++)
4533 writeb(driver_version[i], &cfgtable->driver_version[i]);
4534 kfree(driver_version);
4535 return 0;
4536}
4537
6f039790
GKH		 4538static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
4539 unsigned char *driver_ver)
580ada3c
SC		 4540{
4541 int i;
4542
4543 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4544 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4545}
4546
6f039790 4547static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4548{
4549
4550 char *driver_ver, *old_driver_ver;
4551 int rc, size = sizeof(cfgtable->driver_version);
4552
4553 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4554 if (!old_driver_ver)
4555 return -ENOMEM;
4556 driver_ver = old_driver_ver + size;
4557
4558 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4559 * should have been changed, otherwise we know the reset failed.
4560 */
4561 init_driver_version(old_driver_ver, size);
4562 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4563 rc = !memcmp(driver_ver, old_driver_ver, size);
4564 kfree(old_driver_ver);
4565 return rc;
4566}
edd16368 4567/* This does a hard reset of the controller using PCI power management
1df8552a 4568 * states or the using the doorbell register.
edd16368 4569 */
6f039790 4570static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 4571{
1df8552a
SC		 4572 u64 cfg_offset;
4573 u32 cfg_base_addr;
4574 u64 cfg_base_addr_index;
4575 void __iomem *vaddr;
4576 unsigned long paddr;
580ada3c 4577 u32 misc_fw_support;
270d05de 4578 int rc;
1df8552a 4579 struct CfgTable __iomem *cfgtable;
cf0b08d0 4580 u32 use_doorbell;
18867659 4581 u32 board_id;
270d05de 4582 u16 command_register;
edd16368 4583
1df8552a
SC		 4584 /* For controllers as old as the P600, this is very nearly
4585 * the same thing as
edd16368
SC		 4586 *
4587 * pci_save_state(pci_dev);
4588 * pci_set_power_state(pci_dev, PCI_D3hot);
4589 * pci_set_power_state(pci_dev, PCI_D0);
4590 * pci_restore_state(pci_dev);
4591 *
1df8552a
SC		 4592 * For controllers newer than the P600, the pci power state
4593 * method of resetting doesn't work so we have another way
4594 * using the doorbell register.
edd16368 4595 */
18867659 4596
25c1e56a 4597 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 4598 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 4599 dev_warn(&pdev->dev, "Not resetting device.\n");
4600 return -ENODEV;
4601 }
46380786
SC		 4602
4603 /* if controller is soft- but not hard resettable... */
4604 if (!ctlr_is_hard_resettable(board_id))
4605 return -ENOTSUPP; /* try soft reset later. */
18867659 4606
270d05de
SC		 4607 /* Save the PCI command register */
4608 pci_read_config_word(pdev, 4, &command_register);
4609 /* Turn the board off. This is so that later pci_restore_state()
4610 * won't turn the board on before the rest of config space is ready.
4611 */
4612 pci_disable_device(pdev);
4613 pci_save_state(pdev);
edd16368 4614
1df8552a
SC		 4615 /* find the first memory BAR, so we can find the cfg table */
4616 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
4617 if (rc)
4618 return rc;
4619 vaddr = remap_pci_mem(paddr, 0x250);
4620 if (!vaddr)
4621 return -ENOMEM;
edd16368 4622
1df8552a
SC		 4623 /* find cfgtable in order to check if reset via doorbell is supported */
4624 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4625 &cfg_base_addr_index, &cfg_offset);
4626 if (rc)
4627 goto unmap_vaddr;
4628 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4629 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4630 if (!cfgtable) {
4631 rc = -ENOMEM;
4632 goto unmap_vaddr;
4633 }
580ada3c
SC		 4634 rc = write_driver_ver_to_cfgtable(cfgtable);
4635 if (rc)
4636 goto unmap_vaddr;
edd16368 4637
cf0b08d0
SC		 4638 /* If reset via doorbell register is supported, use that.
4639 * There are two such methods. Favor the newest method.
4640 */
1df8552a 4641 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 4642 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4643 if (use_doorbell) {
4644 use_doorbell = DOORBELL_CTLR_RESET2;
4645 } else {
4646 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
4647 if (use_doorbell) {
fba63097
MM		 4648 dev_warn(&pdev->dev, "Soft reset not supported. "
4649 "Firmware update is required.\n");
64670ac8 4650 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 4651 goto unmap_cfgtable;
4652 }
4653 }
edd16368 4654
1df8552a
SC		 4655 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
4656 if (rc)
4657 goto unmap_cfgtable;
edd16368 4658
270d05de
SC		 4659 pci_restore_state(pdev);
4660 rc = pci_enable_device(pdev);
4661 if (rc) {
4662 dev_warn(&pdev->dev, "failed to enable device.\n");
4663 goto unmap_cfgtable;
edd16368 4664 }
270d05de 4665 pci_write_config_word(pdev, 4, command_register);
edd16368 4666
1df8552a
SC		 4667 /* Some devices (notably the HP Smart Array 5i Controller)
4668 need a little pause here */
4669 msleep(HPSA_POST_RESET_PAUSE_MSECS);
4670
fe5389c8
SC		 4671 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
4672 if (rc) {
4673 dev_warn(&pdev->dev,
64670ac8
SC		 4674 "failed waiting for board to become ready "
4675 "after hard reset\n");
fe5389c8
SC		 4676 goto unmap_cfgtable;
4677 }
fe5389c8 4678
580ada3c
SC		 4679 rc = controller_reset_failed(vaddr);
4680 if (rc < 0)
4681 goto unmap_cfgtable;
4682 if (rc) {
64670ac8
SC		 4683 dev_warn(&pdev->dev, "Unable to successfully reset "
4684 "controller. Will try soft reset.\n");
4685 rc = -ENOTSUPP;
580ada3c 4686 } else {
64670ac8 4687 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 4688 }
4689
4690unmap_cfgtable:
4691 iounmap(cfgtable);
4692
4693unmap_vaddr:
4694 iounmap(vaddr);
4695 return rc;
edd16368
SC		 4696}
4697
4698/*
4699 * We cannot read the structure directly, for portability we must use
4700 * the io functions.
4701 * This is for debug only.
4702 */
edd16368
SC		 4703static void print_cfg_table(struct device *dev, struct CfgTable *tb)
4704{
58f8665c 4705#ifdef HPSA_DEBUG
edd16368
SC		 4706 int i;
4707 char temp_name[17];
4708
4709 dev_info(dev, "Controller Configuration information\n");
4710 dev_info(dev, "------------------------------------\n");
4711 for (i = 0; i < 4; i++)
4712 temp_name[i] = readb(&(tb->Signature[i]));
4713 temp_name[4] = '\0';
4714 dev_info(dev, " Signature = %s\n", temp_name);
4715 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
4716 dev_info(dev, " Transport methods supported = 0x%x\n",
4717 readl(&(tb->TransportSupport)));
4718 dev_info(dev, " Transport methods active = 0x%x\n",
4719 readl(&(tb->TransportActive)));
4720 dev_info(dev, " Requested transport Method = 0x%x\n",
4721 readl(&(tb->HostWrite.TransportRequest)));
4722 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
4723 readl(&(tb->HostWrite.CoalIntDelay)));
4724 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
4725 readl(&(tb->HostWrite.CoalIntCount)));
4726 dev_info(dev, " Max outstanding commands = 0x%d\n",
4727 readl(&(tb->CmdsOutMax)));
4728 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
4729 for (i = 0; i < 16; i++)
4730 temp_name[i] = readb(&(tb->ServerName[i]));
4731 temp_name[16] = '\0';
4732 dev_info(dev, " Server Name = %s\n", temp_name);
4733 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
4734 readl(&(tb->HeartBeat)));
edd16368 4735#endif /* HPSA_DEBUG */
58f8665c 4736}
edd16368
SC		 4737
4738static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
4739{
4740 int i, offset, mem_type, bar_type;
4741
4742 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
4743 return 0;
4744 offset = 0;
4745 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
4746 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
4747 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
4748 offset += 4;
4749 else {
4750 mem_type = pci_resource_flags(pdev, i) &
4751 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
4752 switch (mem_type) {
4753 case PCI_BASE_ADDRESS_MEM_TYPE_32:
4754 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
4755 offset += 4; /* 32 bit */
4756 break;
4757 case PCI_BASE_ADDRESS_MEM_TYPE_64:
4758 offset += 8;
4759 break;
4760 default: /* reserved in PCI 2.2 */
4761 dev_warn(&pdev->dev,
4762 "base address is invalid\n");
4763 return -1;
4764 break;
4765 }
4766 }
4767 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
4768 return i + 1;
4769 }
4770 return -1;
4771}
4772
4773/* If MSI/MSI-X is supported by the kernel we will try to enable it on
4774 * controllers that are capable. If not, we use IO-APIC mode.
4775 */
4776
6f039790 4777static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 4778{
4779#ifdef CONFIG_PCI_MSI
254f796b
MG		 4780 int err, i;
4781 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
4782
4783 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
4784 hpsa_msix_entries[i].vector = 0;
4785 hpsa_msix_entries[i].entry = i;
4786 }
edd16368
SC		 4787
4788 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 4789 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
4790 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 4791 goto default_int_mode;
55c06c71
SC		 4792 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
4793 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 4794 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 4795 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 4796 h->msix_vector);
edd16368 4797 if (err > 0) {
55c06c71 4798 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 4799 "available\n", err);
eee0f03a
HR		 4800 h->msix_vector = err;
4801 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
4802 h->msix_vector);
4803 }
4804 if (!err) {
4805 for (i = 0; i < h->msix_vector; i++)
4806 h->intr[i] = hpsa_msix_entries[i].vector;
4807 return;
edd16368 4808 } else {
55c06c71 4809 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 4810 err);
eee0f03a 4811 h->msix_vector = 0;
edd16368
SC		 4812 goto default_int_mode;
4813 }
4814 }
55c06c71
SC		 4815 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
4816 dev_info(&h->pdev->dev, "MSI\n");
4817 if (!pci_enable_msi(h->pdev))
edd16368
SC		 4818 h->msi_vector = 1;
4819 else
55c06c71 4820 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 4821 }
4822default_int_mode:
4823#endif /* CONFIG_PCI_MSI */
4824 /* if we get here we're going to use the default interrupt mode */
a9a3a273 4825 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 4826}
4827
6f039790 4828static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 4829{
4830 int i;
4831 u32 subsystem_vendor_id, subsystem_device_id;
4832
4833 subsystem_vendor_id = pdev->subsystem_vendor;
4834 subsystem_device_id = pdev->subsystem_device;
4835 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
4836 subsystem_vendor_id;
4837
4838 for (i = 0; i < ARRAY_SIZE(products); i++)
4839 if (*board_id == products[i].board_id)
4840 return i;
4841
6798cc0a
SC		 4842 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
4843 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
4844 !hpsa_allow_any) {
e5c880d1
SC		 4845 dev_warn(&pdev->dev, "unrecognized board ID: "
4846 "0x%08x, ignoring.\n", *board_id);
4847 return -ENODEV;
4848 }
4849 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
4850}
4851
6f039790
GKH		 4852static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
4853 unsigned long *memory_bar)
3a7774ce
SC		 4854{
4855 int i;
4856
4857 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 4858 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 4859 /* addressing mode bits already removed */
12d2cd47
SC		 4860 *memory_bar = pci_resource_start(pdev, i);
4861 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 4862 *memory_bar);
4863 return 0;
4864 }
12d2cd47 4865 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 4866 return -ENODEV;
4867}
4868
6f039790
GKH		 4869static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
4870 int wait_for_ready)
2c4c8c8b 4871{
fe5389c8 4872 int i, iterations;
2c4c8c8b 4873 u32 scratchpad;
fe5389c8
SC		 4874 if (wait_for_ready)
4875 iterations = HPSA_BOARD_READY_ITERATIONS;
4876 else
4877 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 4878
fe5389c8
SC		 4879 for (i = 0; i < iterations; i++) {
4880 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
4881 if (wait_for_ready) {
4882 if (scratchpad == HPSA_FIRMWARE_READY)
4883 return 0;
4884 } else {
4885 if (scratchpad != HPSA_FIRMWARE_READY)
4886 return 0;
4887 }
2c4c8c8b
SC		 4888 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
4889 }
fe5389c8 4890 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 4891 return -ENODEV;
4892}
4893
6f039790
GKH		 4894static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
4895 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
4896 u64 *cfg_offset)
a51fd47f
SC		 4897{
4898 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
4899 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
4900 *cfg_base_addr &= (u32) 0x0000ffff;
4901 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
4902 if (*cfg_base_addr_index == -1) {
4903 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
4904 return -ENODEV;
4905 }
4906 return 0;
4907}
4908
6f039790 4909static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 4910{
01a02ffc
SC		 4911 u64 cfg_offset;
4912 u32 cfg_base_addr;
4913 u64 cfg_base_addr_index;
303932fd 4914 u32 trans_offset;
a51fd47f 4915 int rc;
77c4495c 4916
a51fd47f
SC		 4917 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
4918 &cfg_base_addr_index, &cfg_offset);
4919 if (rc)
4920 return rc;
77c4495c 4921 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 4922 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 4923 if (!h->cfgtable)
4924 return -ENOMEM;
580ada3c
SC		 4925 rc = write_driver_ver_to_cfgtable(h->cfgtable);
4926 if (rc)
4927 return rc;
77c4495c 4928 /* Find performant mode table. */
a51fd47f 4929 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 4930 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
4931 cfg_base_addr_index)+cfg_offset+trans_offset,
4932 sizeof(*h->transtable));
4933 if (!h->transtable)
4934 return -ENOMEM;
4935 return 0;
4936}
4937
6f039790 4938static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 4939{
4940 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 4941
4942 /* Limit commands in memory limited kdump scenario. */
4943 if (reset_devices && h->max_commands > 32)
4944 h->max_commands = 32;
4945
cba3d38b
SC		 4946 if (h->max_commands < 16) {
4947 dev_warn(&h->pdev->dev, "Controller reports "
4948 "max supported commands of %d, an obvious lie. "
4949 "Using 16. Ensure that firmware is up to date.\n",
4950 h->max_commands);
4951 h->max_commands = 16;
4952 }
4953}
4954
b93d7536
SC		 4955/* Interrogate the hardware for some limits:
4956 * max commands, max SG elements without chaining, and with chaining,
4957 * SG chain block size, etc.
4958 */
6f039790 4959static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 4960{
cba3d38b 4961 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 4962 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
4963 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 4964 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 4965 /*
4966 * Limit in-command s/g elements to 32 save dma'able memory.
4967 * Howvever spec says if 0, use 31
4968 */
4969 h->max_cmd_sg_entries = 31;
4970 if (h->maxsgentries > 512) {
4971 h->max_cmd_sg_entries = 32;
4972 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
4973 h->maxsgentries--; /* save one for chain pointer */
4974 } else {
4975 h->maxsgentries = 31; /* default to traditional values */
4976 h->chainsize = 0;
4977 }
75167d2c
SC		 4978
4979 /* Find out what task management functions are supported and cache */
4980 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
b93d7536
SC		 4981}
4982
76c46e49
SC		 4983static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
4984{
0fc9fd40 4985 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 4986 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
4987 return false;
4988 }
4989 return true;
4990}
4991
97a5e98c 4992static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 4993{
97a5e98c 4994 u32 driver_support;
f7c39101 4995
28e13446
SC		 4996#ifdef CONFIG_X86
4997 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 4998 driver_support = readl(&(h->cfgtable->driver_support));
4999 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5000#endif
28e13446
SC		 5001 driver_support |= ENABLE_UNIT_ATTN;
5002 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5003}
5004
3d0eab67
SC		 5005/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5006 * in a prefetch beyond physical memory.
5007 */
5008static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5009{
5010 u32 dma_prefetch;
5011
5012 if (h->board_id != 0x3225103C)
5013 return;
5014 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5015 dma_prefetch |= 0x8000;
5016 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5017}
5018
6f039790 5019static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5020{
5021 int i;
6eaf46fd
SC		 5022 u32 doorbell_value;
5023 unsigned long flags;
eb6b2ae9
SC		 5024
5025 /* under certain very rare conditions, this can take awhile.
5026 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5027 * as we enter this code.)
5028 */
5029 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5030 spin_lock_irqsave(&h->lock, flags);
5031 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5032 spin_unlock_irqrestore(&h->lock, flags);
382be668 5033 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5034 break;
5035 /* delay and try again */
60d3f5b0 5036 usleep_range(10000, 20000);
eb6b2ae9 5037 }
3f4336f3
SC		 5038}
5039
6f039790 5040static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5041{
5042 u32 trans_support;
5043
5044 trans_support = readl(&(h->cfgtable->TransportSupport));
5045 if (!(trans_support & SIMPLE_MODE))
5046 return -ENOTSUPP;
5047
5048 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5049
3f4336f3
SC		 5050 /* Update the field, and then ring the doorbell */
5051 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
5052 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5053 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5054 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5055 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5056 goto error;
960a30e7 5057 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5058 return 0;
283b4a9b
SC		 5059error:
5060 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5061 return -ENODEV;
eb6b2ae9
SC		 5062}
5063
6f039790 5064static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5065{
eb6b2ae9 5066 int prod_index, err;
edd16368 5067
e5c880d1
SC		 5068 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5069 if (prod_index < 0)
5070 return -ENODEV;
5071 h->product_name = products[prod_index].product_name;
5072 h->access = *(products[prod_index].access);
edd16368 5073
e5a44df8
MG		 5074 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5075 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5076
55c06c71 5077 err = pci_enable_device(h->pdev);
edd16368 5078 if (err) {
55c06c71 5079 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5080 return err;
5081 }
5082
5cb460a6
SC		 5083 /* Enable bus mastering (pci_disable_device may disable this) */
5084 pci_set_master(h->pdev);
5085
f79cfec6 5086 err = pci_request_regions(h->pdev, HPSA);
edd16368 5087 if (err) {
55c06c71
SC		 5088 dev_err(&h->pdev->dev,
5089 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5090 return err;
5091 }
6b3f4c52 5092 hpsa_interrupt_mode(h);
12d2cd47 5093 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5094 if (err)
edd16368 5095 goto err_out_free_res;
edd16368 5096 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5097 if (!h->vaddr) {
5098 err = -ENOMEM;
5099 goto err_out_free_res;
5100 }
fe5389c8 5101 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5102 if (err)
edd16368 5103 goto err_out_free_res;
77c4495c
SC		 5104 err = hpsa_find_cfgtables(h);
5105 if (err)
edd16368 5106 goto err_out_free_res;
b93d7536 5107 hpsa_find_board_params(h);
edd16368 5108
76c46e49 5109 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5110 err = -ENODEV;
5111 goto err_out_free_res;
5112 }
97a5e98c 5113 hpsa_set_driver_support_bits(h);
3d0eab67 5114 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5115 err = hpsa_enter_simple_mode(h);
5116 if (err)
edd16368 5117 goto err_out_free_res;
edd16368
SC		 5118 return 0;
5119
5120err_out_free_res:
204892e9
SC		 5121 if (h->transtable)
5122 iounmap(h->transtable);
5123 if (h->cfgtable)
5124 iounmap(h->cfgtable);
5125 if (h->vaddr)
5126 iounmap(h->vaddr);
f0bd0b68 5127 pci_disable_device(h->pdev);
55c06c71 5128 pci_release_regions(h->pdev);
edd16368
SC		 5129 return err;
5130}
5131
6f039790 5132static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5133{
5134 int rc;
5135
5136#define HBA_INQUIRY_BYTE_COUNT 64
5137 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5138 if (!h->hba_inquiry_data)
5139 return;
5140 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5141 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5142 if (rc != 0) {
5143 kfree(h->hba_inquiry_data);
5144 h->hba_inquiry_data = NULL;
5145 }
5146}
5147
6f039790 5148static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5149{
1df8552a 5150 int rc, i;
4c2a8c40
SC		 5151
5152 if (!reset_devices)
5153 return 0;
5154
1df8552a
SC		 5155 /* Reset the controller with a PCI power-cycle or via doorbell */
5156 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5157
1df8552a
SC		 5158 /* -ENOTSUPP here means we cannot reset the controller
5159 * but it's already (and still) up and running in
18867659
SC		 5160 * "performant mode". Or, it might be 640x, which can't reset
5161 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5162 */
5163 if (rc == -ENOTSUPP)
64670ac8 5164 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5165 if (rc)
5166 return -ENODEV;
4c2a8c40
SC		 5167
5168 /* Now try to get the controller to respond to a no-op */
2b870cb3 5169 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5170 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5171 if (hpsa_noop(pdev) == 0)
5172 break;
5173 else
5174 dev_warn(&pdev->dev, "no-op failed%s\n",
5175 (i < 11 ? "; re-trying" : ""));
5176 }
5177 return 0;
5178}
5179
6f039790 5180static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5181{
5182 h->cmd_pool_bits = kzalloc(
5183 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5184 sizeof(unsigned long), GFP_KERNEL);
5185 h->cmd_pool = pci_alloc_consistent(h->pdev,
5186 h->nr_cmds * sizeof(*h->cmd_pool),
5187 &(h->cmd_pool_dhandle));
5188 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5189 h->nr_cmds * sizeof(*h->errinfo_pool),
5190 &(h->errinfo_pool_dhandle));
5191 if ((h->cmd_pool_bits == NULL)
5192 || (h->cmd_pool == NULL)
5193 || (h->errinfo_pool == NULL)) {
5194 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5195 return -ENOMEM;
5196 }
5197 return 0;
5198}
5199
5200static void hpsa_free_cmd_pool(struct ctlr_info *h)
5201{
5202 kfree(h->cmd_pool_bits);
5203 if (h->cmd_pool)
5204 pci_free_consistent(h->pdev,
5205 h->nr_cmds * sizeof(struct CommandList),
5206 h->cmd_pool, h->cmd_pool_dhandle);
5207 if (h->errinfo_pool)
5208 pci_free_consistent(h->pdev,
5209 h->nr_cmds * sizeof(struct ErrorInfo),
5210 h->errinfo_pool,
5211 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5212 if (h->ioaccel_cmd_pool)
5213 pci_free_consistent(h->pdev,
5214 h->nr_cmds * sizeof(struct io_accel1_cmd),
5215 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5216}
5217
0ae01a32
SC		 5218static int hpsa_request_irq(struct ctlr_info *h,
5219 irqreturn_t (*msixhandler)(int, void *),
5220 irqreturn_t (*intxhandler)(int, void *))
5221{
254f796b 5222 int rc, i;
0ae01a32 5223
254f796b
MG		 5224 /*
5225 * initialize h->q[x] = x so that interrupt handlers know which
5226 * queue to process.
5227 */
5228 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5229 h->q[i] = (u8) i;
5230
eee0f03a 5231 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5232 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5233 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5234 rc = request_irq(h->intr[i], msixhandler,
5235 0, h->devname,
5236 &h->q[i]);
5237 } else {
5238 /* Use single reply pool */
eee0f03a 5239 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5240 rc = request_irq(h->intr[h->intr_mode],
5241 msixhandler, 0, h->devname,
5242 &h->q[h->intr_mode]);
5243 } else {
5244 rc = request_irq(h->intr[h->intr_mode],
5245 intxhandler, IRQF_SHARED, h->devname,
5246 &h->q[h->intr_mode]);
5247 }
5248 }
0ae01a32
SC		 5249 if (rc) {
5250 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5251 h->intr[h->intr_mode], h->devname);
5252 return -ENODEV;
5253 }
5254 return 0;
5255}
5256
6f039790 5257static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5258{
5259 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
5260 HPSA_RESET_TYPE_CONTROLLER)) {
5261 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
5262 return -EIO;
5263 }
5264
5265 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
5266 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
5267 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
5268 return -1;
5269 }
5270
5271 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
5272 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
5273 dev_warn(&h->pdev->dev, "Board failed to become ready "
5274 "after soft reset.\n");
5275 return -1;
5276 }
5277
5278 return 0;
5279}
5280
254f796b
MG		 5281static void free_irqs(struct ctlr_info *h)
5282{
5283 int i;
5284
5285 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
5286 /* Single reply queue, only one irq to free */
5287 i = h->intr_mode;
5288 free_irq(h->intr[i], &h->q[i]);
5289 return;
5290 }
5291
eee0f03a 5292 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5293 free_irq(h->intr[i], &h->q[i]);
5294}
5295
0097f0f4 5296static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 5297{
254f796b 5298 free_irqs(h);
64670ac8 5299#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 5300 if (h->msix_vector) {
5301 if (h->pdev->msix_enabled)
5302 pci_disable_msix(h->pdev);
5303 } else if (h->msi_vector) {
5304 if (h->pdev->msi_enabled)
5305 pci_disable_msi(h->pdev);
5306 }
64670ac8 5307#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 5308}
5309
5310static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
5311{
5312 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 5313 hpsa_free_sg_chain_blocks(h);
5314 hpsa_free_cmd_pool(h);
e1f7de0c 5315 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 5316 kfree(h->blockFetchTable);
5317 pci_free_consistent(h->pdev, h->reply_pool_size,
5318 h->reply_pool, h->reply_pool_dhandle);
5319 if (h->vaddr)
5320 iounmap(h->vaddr);
5321 if (h->transtable)
5322 iounmap(h->transtable);
5323 if (h->cfgtable)
5324 iounmap(h->cfgtable);
5325 pci_release_regions(h->pdev);
5326 kfree(h);
5327}
5328
a0c12413
SC		 5329/* Called when controller lockup detected. */
5330static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
5331{
5332 struct CommandList *c = NULL;
5333
5334 assert_spin_locked(&h->lock);
5335 /* Mark all outstanding commands as failed and complete them. */
5336 while (!list_empty(list)) {
5337 c = list_entry(list->next, struct CommandList, list);
5338 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 5339 finish_cmd(c);
a0c12413
SC		 5340 }
5341}
5342
5343static void controller_lockup_detected(struct ctlr_info *h)
5344{
5345 unsigned long flags;
5346
a0c12413
SC		 5347 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5348 spin_lock_irqsave(&h->lock, flags);
5349 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
5350 spin_unlock_irqrestore(&h->lock, flags);
5351 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
5352 h->lockup_detected);
5353 pci_disable_device(h->pdev);
5354 spin_lock_irqsave(&h->lock, flags);
5355 fail_all_cmds_on_list(h, &h->cmpQ);
5356 fail_all_cmds_on_list(h, &h->reqQ);
5357 spin_unlock_irqrestore(&h->lock, flags);
5358}
5359
a0c12413
SC		 5360static void detect_controller_lockup(struct ctlr_info *h)
5361{
5362 u64 now;
5363 u32 heartbeat;
5364 unsigned long flags;
5365
a0c12413
SC		 5366 now = get_jiffies_64();
5367 /* If we've received an interrupt recently, we're ok. */
5368 if (time_after64(h->last_intr_timestamp +
e85c5974 5369 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5370 return;
5371
5372 /*
5373 * If we've already checked the heartbeat recently, we're ok.
5374 * This could happen if someone sends us a signal. We
5375 * otherwise don't care about signals in this thread.
5376 */
5377 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 5378 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5379 return;
5380
5381 /* If heartbeat has not changed since we last looked, we're not ok. */
5382 spin_lock_irqsave(&h->lock, flags);
5383 heartbeat = readl(&h->cfgtable->HeartBeat);
5384 spin_unlock_irqrestore(&h->lock, flags);
5385 if (h->last_heartbeat == heartbeat) {
5386 controller_lockup_detected(h);
5387 return;
5388 }
5389
5390 /* We're ok. */
5391 h->last_heartbeat = heartbeat;
5392 h->last_heartbeat_timestamp = now;
5393}
5394
8a98db73 5395static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 5396{
5397 unsigned long flags;
8a98db73
SC		 5398 struct ctlr_info *h = container_of(to_delayed_work(work),
5399 struct ctlr_info, monitor_ctlr_work);
5400 detect_controller_lockup(h);
5401 if (h->lockup_detected)
5402 return;
5403 spin_lock_irqsave(&h->lock, flags);
5404 if (h->remove_in_progress) {
5405 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5406 return;
5407 }
8a98db73
SC		 5408 schedule_delayed_work(&h->monitor_ctlr_work,
5409 h->heartbeat_sample_interval);
5410 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5411}
5412
6f039790 5413static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 5414{
4c2a8c40 5415 int dac, rc;
edd16368 5416 struct ctlr_info *h;
64670ac8
SC		 5417 int try_soft_reset = 0;
5418 unsigned long flags;
edd16368
SC		 5419
5420 if (number_of_controllers == 0)
5421 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 5422
4c2a8c40 5423 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 5424 if (rc) {
5425 if (rc != -ENOTSUPP)
5426 return rc;
5427 /* If the reset fails in a particular way (it has no way to do
5428 * a proper hard reset, so returns -ENOTSUPP) we can try to do
5429 * a soft reset once we get the controller configured up to the
5430 * point that it can accept a command.
5431 */
5432 try_soft_reset = 1;
5433 rc = 0;
5434 }
5435
5436reinit_after_soft_reset:
edd16368 5437
303932fd
DB		 5438 /* Command structures must be aligned on a 32-byte boundary because
5439 * the 5 lower bits of the address are used by the hardware. and by
5440 * the driver. See comments in hpsa.h for more info.
5441 */
283b4a9b 5442#define COMMANDLIST_ALIGNMENT 128
303932fd 5443 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 5444 h = kzalloc(sizeof(*h), GFP_KERNEL);
5445 if (!h)
ecd9aad4 5446 return -ENOMEM;
edd16368 5447
55c06c71 5448 h->pdev = pdev;
a9a3a273 5449 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 5450 INIT_LIST_HEAD(&h->cmpQ);
5451 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 5452 spin_lock_init(&h->lock);
5453 spin_lock_init(&h->scan_lock);
0390f0c0 5454 spin_lock_init(&h->passthru_count_lock);
55c06c71 5455 rc = hpsa_pci_init(h);
ecd9aad4 5456 if (rc != 0)
edd16368
SC		 5457 goto clean1;
5458
f79cfec6 5459 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 5460 h->ctlr = number_of_controllers;
5461 number_of_controllers++;
edd16368
SC		 5462
5463 /* configure PCI DMA stuff */
ecd9aad4
SC		 5464 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
5465 if (rc == 0) {
edd16368 5466 dac = 1;
ecd9aad4
SC		 5467 } else {
5468 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5469 if (rc == 0) {
5470 dac = 0;
5471 } else {
5472 dev_err(&pdev->dev, "no suitable DMA available\n");
5473 goto clean1;
5474 }
edd16368
SC		 5475 }
5476
5477 /* make sure the board interrupts are off */
5478 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 5479
0ae01a32 5480 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 5481 goto clean2;
303932fd
DB		 5482 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
5483 h->devname, pdev->device,
a9a3a273 5484 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 5485 if (hpsa_allocate_cmd_pool(h))
edd16368 5486 goto clean4;
33a2ffce
SC		 5487 if (hpsa_allocate_sg_chain_blocks(h))
5488 goto clean4;
a08a8471
SC		 5489 init_waitqueue_head(&h->scan_wait_queue);
5490 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 5491
5492 pci_set_drvdata(pdev, h);
9a41338e
SC		 5493 h->ndevices = 0;
5494 h->scsi_host = NULL;
5495 spin_lock_init(&h->devlock);
64670ac8
SC		 5496 hpsa_put_ctlr_into_performant_mode(h);
5497
5498 /* At this point, the controller is ready to take commands.
5499 * Now, if reset_devices and the hard reset didn't work, try
5500 * the soft reset and see if that works.
5501 */
5502 if (try_soft_reset) {
5503
5504 /* This is kind of gross. We may or may not get a completion
5505 * from the soft reset command, and if we do, then the value
5506 * from the fifo may or may not be valid. So, we wait 10 secs
5507 * after the reset throwing away any completions we get during
5508 * that time. Unregister the interrupt handler and register
5509 * fake ones to scoop up any residual completions.
5510 */
5511 spin_lock_irqsave(&h->lock, flags);
5512 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5513 spin_unlock_irqrestore(&h->lock, flags);
254f796b 5514 free_irqs(h);
64670ac8
SC		 5515 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
5516 hpsa_intx_discard_completions);
5517 if (rc) {
5518 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5519 "soft reset.\n");
5520 goto clean4;
5521 }
5522
5523 rc = hpsa_kdump_soft_reset(h);
5524 if (rc)
5525 /* Neither hard nor soft reset worked, we're hosed. */
5526 goto clean4;
5527
5528 dev_info(&h->pdev->dev, "Board READY.\n");
5529 dev_info(&h->pdev->dev,
5530 "Waiting for stale completions to drain.\n");
5531 h->access.set_intr_mask(h, HPSA_INTR_ON);
5532 msleep(10000);
5533 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5534
5535 rc = controller_reset_failed(h->cfgtable);
5536 if (rc)
5537 dev_info(&h->pdev->dev,
5538 "Soft reset appears to have failed.\n");
5539
5540 /* since the controller's reset, we have to go back and re-init
5541 * everything. Easiest to just forget what we've done and do it
5542 * all over again.
5543 */
5544 hpsa_undo_allocations_after_kdump_soft_reset(h);
5545 try_soft_reset = 0;
5546 if (rc)
5547 /* don't go to clean4, we already unallocated */
5548 return -ENODEV;
5549
5550 goto reinit_after_soft_reset;
5551 }
edd16368
SC		 5552
5553 /* Turn the interrupts on so we can service requests */
5554 h->access.set_intr_mask(h, HPSA_INTR_ON);
5555
339b2b14 5556 hpsa_hba_inquiry(h);
edd16368 5557 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 5558
5559 /* Monitor the controller for firmware lockups */
5560 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
5561 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
5562 schedule_delayed_work(&h->monitor_ctlr_work,
5563 h->heartbeat_sample_interval);
88bf6d62 5564 return 0;
edd16368
SC		 5565
5566clean4:
33a2ffce 5567 hpsa_free_sg_chain_blocks(h);
2e9d1b36 5568 hpsa_free_cmd_pool(h);
254f796b 5569 free_irqs(h);
edd16368
SC		 5570clean2:
5571clean1:
edd16368 5572 kfree(h);
ecd9aad4 5573 return rc;
edd16368
SC		 5574}
5575
5576static void hpsa_flush_cache(struct ctlr_info *h)
5577{
5578 char *flush_buf;
5579 struct CommandList *c;
702890e3
SC		 5580 unsigned long flags;
5581
5582 /* Don't bother trying to flush the cache if locked up */
5583 spin_lock_irqsave(&h->lock, flags);
5584 if (unlikely(h->lockup_detected)) {
5585 spin_unlock_irqrestore(&h->lock, flags);
5586 return;
5587 }
5588 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5589
5590 flush_buf = kzalloc(4, GFP_KERNEL);
5591 if (!flush_buf)
5592 return;
5593
5594 c = cmd_special_alloc(h);
5595 if (!c) {
5596 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
5597 goto out_of_memory;
5598 }
a2dac136
SC		 5599 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
5600 RAID_CTLR_LUNID, TYPE_CMD)) {
5601 goto out;
5602 }
edd16368
SC		 5603 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
5604 if (c->err_info->CommandStatus != 0)
a2dac136 5605out:
edd16368
SC		 5606 dev_warn(&h->pdev->dev,
5607 "error flushing cache on controller\n");
5608 cmd_special_free(h, c);
5609out_of_memory:
5610 kfree(flush_buf);
5611}
5612
5613static void hpsa_shutdown(struct pci_dev *pdev)
5614{
5615 struct ctlr_info *h;
5616
5617 h = pci_get_drvdata(pdev);
5618 /* Turn board interrupts off and send the flush cache command
5619 * sendcmd will turn off interrupt, and send the flush...
5620 * To write all data in the battery backed cache to disks
5621 */
5622 hpsa_flush_cache(h);
5623 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 5624 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 5625}
5626
6f039790 5627static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 5628{
5629 int i;
5630
5631 for (i = 0; i < h->ndevices; i++)
5632 kfree(h->dev[i]);
5633}
5634
6f039790 5635static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 5636{
5637 struct ctlr_info *h;
8a98db73 5638 unsigned long flags;
edd16368
SC		 5639
5640 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 5641 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 5642 return;
5643 }
5644 h = pci_get_drvdata(pdev);
8a98db73
SC		 5645
5646 /* Get rid of any controller monitoring work items */
5647 spin_lock_irqsave(&h->lock, flags);
5648 h->remove_in_progress = 1;
5649 cancel_delayed_work(&h->monitor_ctlr_work);
5650 spin_unlock_irqrestore(&h->lock, flags);
5651
edd16368
SC		 5652 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
5653 hpsa_shutdown(pdev);
5654 iounmap(h->vaddr);
204892e9
SC		 5655 iounmap(h->transtable);
5656 iounmap(h->cfgtable);
55e14e76 5657 hpsa_free_device_info(h);
33a2ffce 5658 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 5659 pci_free_consistent(h->pdev,
5660 h->nr_cmds * sizeof(struct CommandList),
5661 h->cmd_pool, h->cmd_pool_dhandle);
5662 pci_free_consistent(h->pdev,
5663 h->nr_cmds * sizeof(struct ErrorInfo),
5664 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 5665 pci_free_consistent(h->pdev, h->reply_pool_size,
5666 h->reply_pool, h->reply_pool_dhandle);
edd16368 5667 kfree(h->cmd_pool_bits);
303932fd 5668 kfree(h->blockFetchTable);
e1f7de0c 5669 kfree(h->ioaccel1_blockFetchTable);
339b2b14 5670 kfree(h->hba_inquiry_data);
f0bd0b68 5671 pci_disable_device(pdev);
edd16368 5672 pci_release_regions(pdev);
edd16368
SC		 5673 kfree(h);
5674}
5675
5676static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
5677 __attribute__((unused)) pm_message_t state)
5678{
5679 return -ENOSYS;
5680}
5681
5682static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
5683{
5684 return -ENOSYS;
5685}
5686
5687static struct pci_driver hpsa_pci_driver = {
f79cfec6 5688 .name = HPSA,
edd16368 5689 .probe = hpsa_init_one,
6f039790 5690 .remove = hpsa_remove_one,
edd16368
SC		 5691 .id_table = hpsa_pci_device_id, /* id_table */
5692 .shutdown = hpsa_shutdown,
5693 .suspend = hpsa_suspend,
5694 .resume = hpsa_resume,
5695};
5696
303932fd
DB		 5697/* Fill in bucket_map[], given nsgs (the max number of
5698 * scatter gather elements supported) and bucket[],
5699 * which is an array of 8 integers. The bucket[] array
5700 * contains 8 different DMA transfer sizes (in 16
5701 * byte increments) which the controller uses to fetch
5702 * commands. This function fills in bucket_map[], which
5703 * maps a given number of scatter gather elements to one of
5704 * the 8 DMA transfer sizes. The point of it is to allow the
5705 * controller to only do as much DMA as needed to fetch the
5706 * command, with the DMA transfer size encoded in the lower
5707 * bits of the command address.
5708 */
5709static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 5710 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 5711{
5712 int i, j, b, size;
5713
303932fd
DB		 5714 /* Note, bucket_map must have nsgs+1 entries. */
5715 for (i = 0; i <= nsgs; i++) {
5716 /* Compute size of a command with i SG entries */
e1f7de0c 5717 size = i + min_blocks;
303932fd
DB		 5718 b = num_buckets; /* Assume the biggest bucket */
5719 /* Find the bucket that is just big enough */
e1f7de0c 5720 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 5721 if (bucket[j] >= size) {
5722 b = j;
5723 break;
5724 }
5725 }
5726 /* for a command with i SG entries, use bucket b. */
5727 bucket_map[i] = b;
5728 }
5729}
5730
e1f7de0c 5731static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 5732{
6c311b57
SC		 5733 int i;
5734 unsigned long register_value;
e1f7de0c
MG		 5735 unsigned long transMethod = CFGTBL_Trans_Performant |
5736 (trans_support & CFGTBL_Trans_use_short_tags) |
5737 CFGTBL_Trans_enable_directed_msix |
5738 (trans_support & CFGTBL_Trans_io_accel1);
5739
5740 struct access_method access = SA5_performant_access;
def342bd
SC		 5741
5742 /* This is a bit complicated. There are 8 registers on
5743 * the controller which we write to to tell it 8 different
5744 * sizes of commands which there may be. It's a way of
5745 * reducing the DMA done to fetch each command. Encoded into
5746 * each command's tag are 3 bits which communicate to the controller
5747 * which of the eight sizes that command fits within. The size of
5748 * each command depends on how many scatter gather entries there are.
5749 * Each SG entry requires 16 bytes. The eight registers are programmed
5750 * with the number of 16-byte blocks a command of that size requires.
5751 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 5752 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 5753 * blocks. Note, this only extends to the SG entries contained
5754 * within the command block, and does not extend to chained blocks
5755 * of SG elements. bft[] contains the eight values we write to
5756 * the registers. They are not evenly distributed, but have more
5757 * sizes for small commands, and fewer sizes for larger commands.
5758 */
d66ae08b
SC		 5759 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
5760 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 5761 /* 5 = 1 s/g entry or 4k
5762 * 6 = 2 s/g entry or 8k
5763 * 8 = 4 s/g entry or 16k
5764 * 10 = 6 s/g entry or 24k
5765 */
303932fd 5766
303932fd
DB		 5767 /* Controller spec: zero out this buffer. */
5768 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 5769
d66ae08b
SC		 5770 bft[7] = SG_ENTRIES_IN_CMD + 4;
5771 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 5772 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 5773 for (i = 0; i < 8; i++)
5774 writel(bft[i], &h->transtable->BlockFetch[i]);
5775
5776 /* size of controller ring buffer */
5777 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 5778 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 5779 writel(0, &h->transtable->RepQCtrAddrLow32);
5780 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 5781
5782 for (i = 0; i < h->nreply_queues; i++) {
5783 writel(0, &h->transtable->RepQAddr[i].upper);
5784 writel(h->reply_pool_dhandle +
5785 (h->max_commands * sizeof(u64) * i),
5786 &h->transtable->RepQAddr[i].lower);
5787 }
5788
e1f7de0c
MG		 5789 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
5790 /*
5791 * enable outbound interrupt coalescing in accelerator mode;
5792 */
5793 if (trans_support & CFGTBL_Trans_io_accel1) {
5794 access = SA5_ioaccel_mode1_access;
5795 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
5796 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
5797 }
303932fd 5798 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 5799 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 5800 register_value = readl(&(h->cfgtable->TransportActive));
5801 if (!(register_value & CFGTBL_Trans_Performant)) {
5802 dev_warn(&h->pdev->dev, "unable to get board into"
5803 " performant mode\n");
5804 return;
5805 }
960a30e7 5806 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 5807 h->access = access;
5808 h->transMethod = transMethod;
5809
5810 if (!(trans_support & CFGTBL_Trans_io_accel1))
5811 return;
5812
5813 /* Set up I/O accelerator mode */
5814 for (i = 0; i < h->nreply_queues; i++) {
5815 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
5816 h->reply_queue[i].current_entry =
5817 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
5818 }
283b4a9b
SC		 5819 bft[7] = h->ioaccel_maxsg + 8;
5820 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
e1f7de0c
MG		 5821 h->ioaccel1_blockFetchTable);
5822
5823 /* initialize all reply queue entries to unused */
5824 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
5825 h->reply_pool_size);
5826
5827 /* set all the constant fields in the accelerator command
5828 * frames once at init time to save CPU cycles later.
5829 */
5830 for (i = 0; i < h->nr_cmds; i++) {
5831 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
5832
5833 cp->function = IOACCEL1_FUNCTION_SCSIIO;
5834 cp->err_info = (u32) (h->errinfo_pool_dhandle +
5835 (i * sizeof(struct ErrorInfo)));
5836 cp->err_info_len = sizeof(struct ErrorInfo);
5837 cp->sgl_offset = IOACCEL1_SGLOFFSET;
5838 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
5839 cp->timeout_sec = 0;
5840 cp->ReplyQueue = 0;
5841 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) | DIRECT_LOOKUP_BIT;
5842 cp->Tag.upper = 0;
5843 cp->host_addr.lower = (u32) (h->ioaccel_cmd_pool_dhandle +
5844 (i * sizeof(struct io_accel1_cmd)));
5845 cp->host_addr.upper = 0;
5846 }
5847}
5848
5849static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
5850{
283b4a9b
SC		 5851 h->ioaccel_maxsg =
5852 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
5853 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
5854 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
5855
e1f7de0c
MG		 5856 /* Command structures must be aligned on a 128-byte boundary
5857 * because the 7 lower bits of the address are used by the
5858 * hardware.
5859 */
5860#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
5861 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
5862 IOACCEL1_COMMANDLIST_ALIGNMENT);
5863 h->ioaccel_cmd_pool =
5864 pci_alloc_consistent(h->pdev,
5865 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
5866 &(h->ioaccel_cmd_pool_dhandle));
5867
5868 h->ioaccel1_blockFetchTable =
283b4a9b 5869 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 5870 sizeof(u32)), GFP_KERNEL);
5871
5872 if ((h->ioaccel_cmd_pool == NULL) ||
5873 (h->ioaccel1_blockFetchTable == NULL))
5874 goto clean_up;
5875
5876 memset(h->ioaccel_cmd_pool, 0,
5877 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
5878 return 0;
5879
5880clean_up:
5881 if (h->ioaccel_cmd_pool)
5882 pci_free_consistent(h->pdev,
5883 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
5884 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
5885 kfree(h->ioaccel1_blockFetchTable);
5886 return 1;
6c311b57
SC		 5887}
5888
6f039790 5889static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 5890{
5891 u32 trans_support;
e1f7de0c
MG		 5892 unsigned long transMethod = CFGTBL_Trans_Performant |
5893 CFGTBL_Trans_use_short_tags;
254f796b 5894 int i;
6c311b57 5895
02ec19c8
SC		 5896 if (hpsa_simple_mode)
5897 return;
5898
e1f7de0c
MG		 5899 /* Check for I/O accelerator mode support */
5900 if (trans_support & CFGTBL_Trans_io_accel1) {
5901 transMethod |= CFGTBL_Trans_io_accel1 |
5902 CFGTBL_Trans_enable_directed_msix;
5903 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
5904 goto clean_up;
5905 }
5906
5907 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 5908 trans_support = readl(&(h->cfgtable->TransportSupport));
5909 if (!(trans_support & PERFORMANT_MODE))
5910 return;
5911
eee0f03a 5912 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 5913 hpsa_get_max_perf_mode_cmds(h);
6c311b57 5914 /* Performant mode ring buffer and supporting data structures */
254f796b 5915 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 5916 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
5917 &(h->reply_pool_dhandle));
5918
254f796b
MG		 5919 for (i = 0; i < h->nreply_queues; i++) {
5920 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
5921 h->reply_queue[i].size = h->max_commands;
5922 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
5923 h->reply_queue[i].current_entry = 0;
5924 }
5925
6c311b57 5926 /* Need a block fetch table for performant mode */
d66ae08b 5927 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 5928 sizeof(u32)), GFP_KERNEL);
5929
5930 if ((h->reply_pool == NULL)
5931 || (h->blockFetchTable == NULL))
5932 goto clean_up;
5933
e1f7de0c 5934 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 5935 return;
5936
5937clean_up:
5938 if (h->reply_pool)
5939 pci_free_consistent(h->pdev, h->reply_pool_size,
5940 h->reply_pool, h->reply_pool_dhandle);
5941 kfree(h->blockFetchTable);
5942}
5943
edd16368
SC		 5944/*
5945 * This is it. Register the PCI driver information for the cards we control
5946 * the OS will call our registered routines when it finds one of our cards.
5947 */
5948static int __init hpsa_init(void)
5949{
31468401 5950 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 5951}
5952
5953static void __exit hpsa_cleanup(void)
5954{
5955 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 5956}
5957
e1f7de0c
MG		 5958static void __attribute__((unused)) verify_offsets(void)
5959{
5960#define VERIFY_OFFSET(member, offset) \
5961 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
5962
5963 VERIFY_OFFSET(dev_handle, 0x00);
5964 VERIFY_OFFSET(reserved1, 0x02);
5965 VERIFY_OFFSET(function, 0x03);
5966 VERIFY_OFFSET(reserved2, 0x04);
5967 VERIFY_OFFSET(err_info, 0x0C);
5968 VERIFY_OFFSET(reserved3, 0x10);
5969 VERIFY_OFFSET(err_info_len, 0x12);
5970 VERIFY_OFFSET(reserved4, 0x13);
5971 VERIFY_OFFSET(sgl_offset, 0x14);
5972 VERIFY_OFFSET(reserved5, 0x15);
5973 VERIFY_OFFSET(transfer_len, 0x1C);
5974 VERIFY_OFFSET(reserved6, 0x20);
5975 VERIFY_OFFSET(io_flags, 0x24);
5976 VERIFY_OFFSET(reserved7, 0x26);
5977 VERIFY_OFFSET(LUN, 0x34);
5978 VERIFY_OFFSET(control, 0x3C);
5979 VERIFY_OFFSET(CDB, 0x40);
5980 VERIFY_OFFSET(reserved8, 0x50);
5981 VERIFY_OFFSET(host_context_flags, 0x60);
5982 VERIFY_OFFSET(timeout_sec, 0x62);
5983 VERIFY_OFFSET(ReplyQueue, 0x64);
5984 VERIFY_OFFSET(reserved9, 0x65);
5985 VERIFY_OFFSET(Tag, 0x68);
5986 VERIFY_OFFSET(host_addr, 0x70);
5987 VERIFY_OFFSET(CISS_LUN, 0x78);
5988 VERIFY_OFFSET(SG, 0x78 + 8);
5989#undef VERIFY_OFFSET
5990}
5991
edd16368
SC		 5992module_init(hpsa_init);
5993module_exit(hpsa_cleanup);
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