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hpsa: change devtype to unsigned
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
b48d9804 233#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 234
f281233d 235static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 236static void hpsa_scan_start(struct Scsi_Host *);
237static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
7c0a0229 239static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 240
241static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 242static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 243static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 244static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 245static void hpsa_slave_destroy(struct scsi_device *sdev);
246
8aa60681 247static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 248static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
303932fd
DB		 252/* performant mode helper functions */
253static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 254 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 255static void hpsa_free_performant_mode(struct ctlr_info *h);
256static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 257static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 258static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
75167d2c 266static inline void finish_cmd(struct CommandList *c);
c706a795 267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 268#define BOARD_NOT_READY 0
269#define BOARD_READY 1
23100dd9 270static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 271static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 272static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 275static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 276static u32 lockup_detected(struct ctlr_info *h);
277static int detect_controller_lockup(struct ctlr_info *h);
8270b862 278static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 279
edd16368
SC		 280static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
281{
282 unsigned long *priv = shost_priv(sdev->host);
283 return (struct ctlr_info *) *priv;
284}
285
a23513e8
SC		 286static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
287{
288 unsigned long *priv = shost_priv(sh);
289 return (struct ctlr_info *) *priv;
290}
291
a58e7e53
WS		 292static inline bool hpsa_is_cmd_idle(struct CommandList *c)
293{
294 return c->scsi_cmd == SCSI_CMD_IDLE;
295}
296
d604f533
WS		 297static inline bool hpsa_is_pending_event(struct CommandList *c)
298{
299 return c->abort_pending || c->reset_pending;
300}
301
9437ac43
SC		 302/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
303static void decode_sense_data(const u8 *sense_data, int sense_data_len,
304 u8 *sense_key, u8 *asc, u8 *ascq)
305{
306 struct scsi_sense_hdr sshdr;
307 bool rc;
308
309 *sense_key = -1;
310 *asc = -1;
311 *ascq = -1;
312
313 if (sense_data_len < 1)
314 return;
315
316 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
317 if (rc) {
318 *sense_key = sshdr.sense_key;
319 *asc = sshdr.asc;
320 *ascq = sshdr.ascq;
321 }
322}
323
edd16368
SC		 324static int check_for_unit_attention(struct ctlr_info *h,
325 struct CommandList *c)
326{
9437ac43
SC		 327 u8 sense_key, asc, ascq;
328 int sense_len;
329
330 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
331 sense_len = sizeof(c->err_info->SenseInfo);
332 else
333 sense_len = c->err_info->SenseLen;
334
335 decode_sense_data(c->err_info->SenseInfo, sense_len,
336 &sense_key, &asc, &ascq);
81c27557 337 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 338 return 0;
339
9437ac43 340 switch (asc) {
edd16368 341 case STATE_CHANGED:
9437ac43 342 dev_warn(&h->pdev->dev,
2946e82b
RE		 343 "%s: a state change detected, command retried\n",
344 h->devname);
edd16368
SC		 345 break;
346 case LUN_FAILED:
7f73695a 347 dev_warn(&h->pdev->dev,
2946e82b 348 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 349 break;
350 case REPORT_LUNS_CHANGED:
7f73695a 351 dev_warn(&h->pdev->dev,
2946e82b 352 "%s: report LUN data changed\n", h->devname);
edd16368 353 /*
4f4eb9f1
ST		 354 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
355 * target (array) devices.
edd16368
SC		 356 */
357 break;
358 case POWER_OR_RESET:
2946e82b
RE		 359 dev_warn(&h->pdev->dev,
360 "%s: a power on or device reset detected\n",
361 h->devname);
edd16368
SC		 362 break;
363 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 364 dev_warn(&h->pdev->dev,
365 "%s: unit attention cleared by another initiator\n",
366 h->devname);
edd16368
SC		 367 break;
368 default:
2946e82b
RE		 369 dev_warn(&h->pdev->dev,
370 "%s: unknown unit attention detected\n",
371 h->devname);
edd16368
SC		 372 break;
373 }
374 return 1;
375}
376
852af20a
MB		 377static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
378{
379 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
380 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
381 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
382 return 0;
383 dev_warn(&h->pdev->dev, HPSA "device busy");
384 return 1;
385}
386
e985c58f
SC		 387static u32 lockup_detected(struct ctlr_info *h);
388static ssize_t host_show_lockup_detected(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 int ld;
392 struct ctlr_info *h;
393 struct Scsi_Host *shost = class_to_shost(dev);
394
395 h = shost_to_hba(shost);
396 ld = lockup_detected(h);
397
398 return sprintf(buf, "ld=%d\n", ld);
399}
400
da0697bd
ST		 401static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
402 struct device_attribute *attr,
403 const char *buf, size_t count)
404{
405 int status, len;
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408 char tmpbuf[10];
409
410 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
411 return -EACCES;
412 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
413 strncpy(tmpbuf, buf, len);
414 tmpbuf[len] = '\0';
415 if (sscanf(tmpbuf, "%d", &status) != 1)
416 return -EINVAL;
417 h = shost_to_hba(shost);
418 h->acciopath_status = !!status;
419 dev_warn(&h->pdev->dev,
420 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
421 h->acciopath_status ? "enabled" : "disabled");
422 return count;
423}
424
2ba8bfc8
SC		 425static ssize_t host_store_raid_offload_debug(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf, size_t count)
428{
429 int debug_level, len;
430 struct ctlr_info *h;
431 struct Scsi_Host *shost = class_to_shost(dev);
432 char tmpbuf[10];
433
434 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
435 return -EACCES;
436 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
437 strncpy(tmpbuf, buf, len);
438 tmpbuf[len] = '\0';
439 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
440 return -EINVAL;
441 if (debug_level < 0)
442 debug_level = 0;
443 h = shost_to_hba(shost);
444 h->raid_offload_debug = debug_level;
445 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
446 h->raid_offload_debug);
447 return count;
448}
449
edd16368
SC		 450static ssize_t host_store_rescan(struct device *dev,
451 struct device_attribute *attr,
452 const char *buf, size_t count)
453{
454 struct ctlr_info *h;
455 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 456 h = shost_to_hba(shost);
31468401 457 hpsa_scan_start(h->scsi_host);
edd16368
SC		 458 return count;
459}
460
d28ce020
SC		 461static ssize_t host_show_firmware_revision(struct device *dev,
462 struct device_attribute *attr, char *buf)
463{
464 struct ctlr_info *h;
465 struct Scsi_Host *shost = class_to_shost(dev);
466 unsigned char *fwrev;
467
468 h = shost_to_hba(shost);
469 if (!h->hba_inquiry_data)
470 return 0;
471 fwrev = &h->hba_inquiry_data[32];
472 return snprintf(buf, 20, "%c%c%c%c\n",
473 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
474}
475
94a13649
SC		 476static ssize_t host_show_commands_outstanding(struct device *dev,
477 struct device_attribute *attr, char *buf)
478{
479 struct Scsi_Host *shost = class_to_shost(dev);
480 struct ctlr_info *h = shost_to_hba(shost);
481
0cbf768e
SC		 482 return snprintf(buf, 20, "%d\n",
483 atomic_read(&h->commands_outstanding));
94a13649
SC		 484}
485
745a7a25
SC		 486static ssize_t host_show_transport_mode(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct Scsi_Host *shost = class_to_shost(dev);
491
492 h = shost_to_hba(shost);
493 return snprintf(buf, 20, "%s\n",
960a30e7 494 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 495 "performant" : "simple");
496}
497
da0697bd
ST		 498static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
499 struct device_attribute *attr, char *buf)
500{
501 struct ctlr_info *h;
502 struct Scsi_Host *shost = class_to_shost(dev);
503
504 h = shost_to_hba(shost);
505 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
506 (h->acciopath_status == 1) ? "enabled" : "disabled");
507}
508
46380786 509/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 510static u32 unresettable_controller[] = {
511 0x324a103C, /* Smart Array P712m */
9b5c48c2 512 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 513 0x3223103C, /* Smart Array P800 */
514 0x3234103C, /* Smart Array P400 */
515 0x3235103C, /* Smart Array P400i */
516 0x3211103C, /* Smart Array E200i */
517 0x3212103C, /* Smart Array E200 */
518 0x3213103C, /* Smart Array E200i */
519 0x3214103C, /* Smart Array E200i */
520 0x3215103C, /* Smart Array E200i */
521 0x3237103C, /* Smart Array E500 */
522 0x323D103C, /* Smart Array P700m */
7af0abbc 523 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 524 0x409C0E11, /* Smart Array 6400 */
525 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 532};
533
46380786
SC		 534/* List of controllers which cannot even be soft reset */
535static u32 soft_unresettable_controller[] = {
7af0abbc 536 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 537 0x40700E11, /* Smart Array 5300 */
538 0x40820E11, /* Smart Array 532 */
539 0x40830E11, /* Smart Array 5312 */
540 0x409A0E11, /* Smart Array 641 */
541 0x409B0E11, /* Smart Array 642 */
542 0x40910E11, /* Smart Array 6i */
46380786
SC		 543 /* Exclude 640x boards. These are two pci devices in one slot
544 * which share a battery backed cache module. One controls the
545 * cache, the other accesses the cache through the one that controls
546 * it. If we reset the one controlling the cache, the other will
547 * likely not be happy. Just forbid resetting this conjoined mess.
548 * The 640x isn't really supported by hpsa anyway.
549 */
550 0x409C0E11, /* Smart Array 6400 */
551 0x409D0E11, /* Smart Array 6400 EM */
552};
553
9b5c48c2
SC		 554static u32 needs_abort_tags_swizzled[] = {
555 0x323D103C, /* Smart Array P700m */
556 0x324a103C, /* Smart Array P712m */
557 0x324b103C, /* SmartArray P711m */
558};
559
560static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 561{
562 int i;
563
9b5c48c2
SC		 564 for (i = 0; i < nelems; i++)
565 if (a[i] == board_id)
566 return 1;
567 return 0;
46380786
SC		 568}
569
9b5c48c2 570static int ctlr_is_hard_resettable(u32 board_id)
46380786 571{
9b5c48c2
SC		 572 return !board_id_in_array(unresettable_controller,
573 ARRAY_SIZE(unresettable_controller), board_id);
574}
46380786 575
9b5c48c2
SC		 576static int ctlr_is_soft_resettable(u32 board_id)
577{
578 return !board_id_in_array(soft_unresettable_controller,
579 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 580}
581
46380786
SC		 582static int ctlr_is_resettable(u32 board_id)
583{
584 return ctlr_is_hard_resettable(board_id) ||
585 ctlr_is_soft_resettable(board_id);
586}
587
9b5c48c2
SC		 588static int ctlr_needs_abort_tags_swizzled(u32 board_id)
589{
590 return board_id_in_array(needs_abort_tags_swizzled,
591 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
592}
593
941b1cda
SC		 594static ssize_t host_show_resettable(struct device *dev,
595 struct device_attribute *attr, char *buf)
596{
597 struct ctlr_info *h;
598 struct Scsi_Host *shost = class_to_shost(dev);
599
600 h = shost_to_hba(shost);
46380786 601 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 602}
603
edd16368
SC		 604static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
605{
606 return (scsi3addr[3] & 0xC0) == 0x40;
607}
608
f2ef0ce7
RE		 609static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
610 "1(+0)ADM", "UNKNOWN"
edd16368 611};
6b80b18f
ST		 612#define HPSA_RAID_0 0
613#define HPSA_RAID_4 1
614#define HPSA_RAID_1 2 /* also used for RAID 10 */
615#define HPSA_RAID_5 3 /* also used for RAID 50 */
616#define HPSA_RAID_51 4
617#define HPSA_RAID_6 5 /* also used for RAID 60 */
618#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 619#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
620
621static ssize_t raid_level_show(struct device *dev,
622 struct device_attribute *attr, char *buf)
623{
624 ssize_t l = 0;
82a72c0a 625 unsigned char rlevel;
edd16368
SC		 626 struct ctlr_info *h;
627 struct scsi_device *sdev;
628 struct hpsa_scsi_dev_t *hdev;
629 unsigned long flags;
630
631 sdev = to_scsi_device(dev);
632 h = sdev_to_hba(sdev);
633 spin_lock_irqsave(&h->lock, flags);
634 hdev = sdev->hostdata;
635 if (!hdev) {
636 spin_unlock_irqrestore(&h->lock, flags);
637 return -ENODEV;
638 }
639
640 /* Is this even a logical drive? */
641 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
642 spin_unlock_irqrestore(&h->lock, flags);
643 l = snprintf(buf, PAGE_SIZE, "N/A\n");
644 return l;
645 }
646
647 rlevel = hdev->raid_level;
648 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 649 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 650 rlevel = RAID_UNKNOWN;
651 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
652 return l;
653}
654
655static ssize_t lunid_show(struct device *dev,
656 struct device_attribute *attr, char *buf)
657{
658 struct ctlr_info *h;
659 struct scsi_device *sdev;
660 struct hpsa_scsi_dev_t *hdev;
661 unsigned long flags;
662 unsigned char lunid[8];
663
664 sdev = to_scsi_device(dev);
665 h = sdev_to_hba(sdev);
666 spin_lock_irqsave(&h->lock, flags);
667 hdev = sdev->hostdata;
668 if (!hdev) {
669 spin_unlock_irqrestore(&h->lock, flags);
670 return -ENODEV;
671 }
672 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
673 spin_unlock_irqrestore(&h->lock, flags);
674 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
675 lunid[0], lunid[1], lunid[2], lunid[3],
676 lunid[4], lunid[5], lunid[6], lunid[7]);
677}
678
679static ssize_t unique_id_show(struct device *dev,
680 struct device_attribute *attr, char *buf)
681{
682 struct ctlr_info *h;
683 struct scsi_device *sdev;
684 struct hpsa_scsi_dev_t *hdev;
685 unsigned long flags;
686 unsigned char sn[16];
687
688 sdev = to_scsi_device(dev);
689 h = sdev_to_hba(sdev);
690 spin_lock_irqsave(&h->lock, flags);
691 hdev = sdev->hostdata;
692 if (!hdev) {
693 spin_unlock_irqrestore(&h->lock, flags);
694 return -ENODEV;
695 }
696 memcpy(sn, hdev->device_id, sizeof(sn));
697 spin_unlock_irqrestore(&h->lock, flags);
698 return snprintf(buf, 16 * 2 + 2,
699 "%02X%02X%02X%02X%02X%02X%02X%02X"
700 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
701 sn[0], sn[1], sn[2], sn[3],
702 sn[4], sn[5], sn[6], sn[7],
703 sn[8], sn[9], sn[10], sn[11],
704 sn[12], sn[13], sn[14], sn[15]);
705}
706
c1988684
ST		 707static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
708 struct device_attribute *attr, char *buf)
709{
710 struct ctlr_info *h;
711 struct scsi_device *sdev;
712 struct hpsa_scsi_dev_t *hdev;
713 unsigned long flags;
714 int offload_enabled;
715
716 sdev = to_scsi_device(dev);
717 h = sdev_to_hba(sdev);
718 spin_lock_irqsave(&h->lock, flags);
719 hdev = sdev->hostdata;
720 if (!hdev) {
721 spin_unlock_irqrestore(&h->lock, flags);
722 return -ENODEV;
723 }
724 offload_enabled = hdev->offload_enabled;
725 spin_unlock_irqrestore(&h->lock, flags);
726 return snprintf(buf, 20, "%d\n", offload_enabled);
727}
728
8270b862
JH		 729#define MAX_PATHS 8
730#define PATH_STRING_LEN 50
731
732static ssize_t path_info_show(struct device *dev,
733 struct device_attribute *attr, char *buf)
734{
735 struct ctlr_info *h;
736 struct scsi_device *sdev;
737 struct hpsa_scsi_dev_t *hdev;
738 unsigned long flags;
739 int i;
740 int output_len = 0;
741 u8 box;
742 u8 bay;
743 u8 path_map_index = 0;
744 char *active;
745 unsigned char phys_connector[2];
746 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
747
748 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
749 sdev = to_scsi_device(dev);
750 h = sdev_to_hba(sdev);
751 spin_lock_irqsave(&h->devlock, flags);
752 hdev = sdev->hostdata;
753 if (!hdev) {
754 spin_unlock_irqrestore(&h->devlock, flags);
755 return -ENODEV;
756 }
757
758 bay = hdev->bay;
759 for (i = 0; i < MAX_PATHS; i++) {
760 path_map_index = 1<<i;
761 if (i == hdev->active_path_index)
762 active = "Active";
763 else if (hdev->path_map & path_map_index)
764 active = "Inactive";
765 else
766 continue;
767
768 output_len = snprintf(path[i],
769 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
770 h->scsi_host->host_no,
771 hdev->bus, hdev->target, hdev->lun,
772 scsi_device_type(hdev->devtype));
773
774 if (is_ext_target(h, hdev) ||
775 (hdev->devtype == TYPE_RAID) ||
776 is_logical_dev_addr_mode(hdev->scsi3addr)) {
777 output_len += snprintf(path[i] + output_len,
778 PATH_STRING_LEN, "%s\n",
779 active);
780 continue;
781 }
782
783 box = hdev->box[i];
784 memcpy(&phys_connector, &hdev->phys_connector[i],
785 sizeof(phys_connector));
786 if (phys_connector[0] < '0')
787 phys_connector[0] = '0';
788 if (phys_connector[1] < '0')
789 phys_connector[1] = '0';
790 if (hdev->phys_connector[i] > 0)
791 output_len += snprintf(path[i] + output_len,
792 PATH_STRING_LEN,
793 "PORT: %.2s ",
794 phys_connector);
b9092b79
KB		 795 if (hdev->devtype == TYPE_DISK &&
796 hdev->expose_state != HPSA_DO_NOT_EXPOSE) {
8270b862
JH		 797 if (box == 0 || box == 0xFF) {
798 output_len += snprintf(path[i] + output_len,
799 PATH_STRING_LEN,
800 "BAY: %hhu %s\n",
801 bay, active);
802 } else {
803 output_len += snprintf(path[i] + output_len,
804 PATH_STRING_LEN,
805 "BOX: %hhu BAY: %hhu %s\n",
806 box, bay, active);
807 }
808 } else if (box != 0 && box != 0xFF) {
809 output_len += snprintf(path[i] + output_len,
810 PATH_STRING_LEN, "BOX: %hhu %s\n",
811 box, active);
812 } else
813 output_len += snprintf(path[i] + output_len,
814 PATH_STRING_LEN, "%s\n", active);
815 }
816
817 spin_unlock_irqrestore(&h->devlock, flags);
818 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
819 path[0], path[1], path[2], path[3],
820 path[4], path[5], path[6], path[7]);
821}
822
3f5eac3a
SC		 823static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
824static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
825static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
826static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 827static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
828 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 829static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 830static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
831 host_show_hp_ssd_smart_path_status,
832 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 833static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
834 host_store_raid_offload_debug);
3f5eac3a
SC		 835static DEVICE_ATTR(firmware_revision, S_IRUGO,
836 host_show_firmware_revision, NULL);
837static DEVICE_ATTR(commands_outstanding, S_IRUGO,
838 host_show_commands_outstanding, NULL);
839static DEVICE_ATTR(transport_mode, S_IRUGO,
840 host_show_transport_mode, NULL);
941b1cda
SC		 841static DEVICE_ATTR(resettable, S_IRUGO,
842 host_show_resettable, NULL);
e985c58f
SC		 843static DEVICE_ATTR(lockup_detected, S_IRUGO,
844 host_show_lockup_detected, NULL);
3f5eac3a
SC		 845
846static struct device_attribute *hpsa_sdev_attrs[] = {
847 &dev_attr_raid_level,
848 &dev_attr_lunid,
849 &dev_attr_unique_id,
c1988684 850 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 851 &dev_attr_path_info,
e985c58f 852 &dev_attr_lockup_detected,
3f5eac3a
SC		 853 NULL,
854};
855
856static struct device_attribute *hpsa_shost_attrs[] = {
857 &dev_attr_rescan,
858 &dev_attr_firmware_revision,
859 &dev_attr_commands_outstanding,
860 &dev_attr_transport_mode,
941b1cda 861 &dev_attr_resettable,
da0697bd 862 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 863 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 864 NULL,
865};
866
41ce4c35
SC		 867#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
868 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
869
3f5eac3a
SC		 870static struct scsi_host_template hpsa_driver_template = {
871 .module = THIS_MODULE,
f79cfec6
SC		 872 .name = HPSA,
873 .proc_name = HPSA,
3f5eac3a
SC		 874 .queuecommand = hpsa_scsi_queue_command,
875 .scan_start = hpsa_scan_start,
876 .scan_finished = hpsa_scan_finished,
7c0a0229 877 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 878 .this_id = -1,
879 .use_clustering = ENABLE_CLUSTERING,
75167d2c 880 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 881 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
882 .ioctl = hpsa_ioctl,
883 .slave_alloc = hpsa_slave_alloc,
41ce4c35 884 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 885 .slave_destroy = hpsa_slave_destroy,
886#ifdef CONFIG_COMPAT
887 .compat_ioctl = hpsa_compat_ioctl,
888#endif
889 .sdev_attrs = hpsa_sdev_attrs,
890 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 891 .max_sectors = 8192,
54b2b50c 892 .no_write_same = 1,
3f5eac3a
SC		 893};
894
254f796b 895static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 896{
897 u32 a;
072b0518 898 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 899
e1f7de0c
MG		 900 if (h->transMethod & CFGTBL_Trans_io_accel1)
901 return h->access.command_completed(h, q);
902
3f5eac3a 903 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 904 return h->access.command_completed(h, q);
3f5eac3a 905
254f796b
MG		 906 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
907 a = rq->head[rq->current_entry];
908 rq->current_entry++;
0cbf768e 909 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 910 } else {
911 a = FIFO_EMPTY;
912 }
913 /* Check for wraparound */
254f796b
MG		 914 if (rq->current_entry == h->max_commands) {
915 rq->current_entry = 0;
916 rq->wraparound ^= 1;
3f5eac3a
SC		 917 }
918 return a;
919}
920
c349775e
ST		 921/*
922 * There are some special bits in the bus address of the
923 * command that we have to set for the controller to know
924 * how to process the command:
925 *
926 * Normal performant mode:
927 * bit 0: 1 means performant mode, 0 means simple mode.
928 * bits 1-3 = block fetch table entry
929 * bits 4-6 = command type (== 0)
930 *
931 * ioaccel1 mode:
932 * bit 0 = "performant mode" bit.
933 * bits 1-3 = block fetch table entry
934 * bits 4-6 = command type (== 110)
935 * (command type is needed because ioaccel1 mode
936 * commands are submitted through the same register as normal
937 * mode commands, so this is how the controller knows whether
938 * the command is normal mode or ioaccel1 mode.)
939 *
940 * ioaccel2 mode:
941 * bit 0 = "performant mode" bit.
942 * bits 1-4 = block fetch table entry (note extra bit)
943 * bits 4-6 = not needed, because ioaccel2 mode has
944 * a separate special register for submitting commands.
945 */
946
25163bd5
WS		 947/*
948 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 949 * set bit 0 for pull model, bits 3-1 for block fetch
950 * register number
951 */
25163bd5
WS		 952#define DEFAULT_REPLY_QUEUE (-1)
953static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
954 int reply_queue)
3f5eac3a 955{
254f796b 956 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 957 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 958 if (unlikely(!h->msix_vector))
959 return;
960 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 961 c->Header.ReplyQueue =
804a5cb5 962 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 963 else
964 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 965 }
3f5eac3a
SC		 966}
967
c349775e 968static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 969 struct CommandList *c,
970 int reply_queue)
c349775e
ST		 971{
972 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
973
25163bd5
WS		 974 /*
975 * Tell the controller to post the reply to the queue for this
c349775e
ST		 976 * processor. This seems to give the best I/O throughput.
977 */
25163bd5
WS		 978 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
979 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
980 else
981 cp->ReplyQueue = reply_queue % h->nreply_queues;
982 /*
983 * Set the bits in the address sent down to include:
c349775e
ST		 984 * - performant mode bit (bit 0)
985 * - pull count (bits 1-3)
986 * - command type (bits 4-6)
987 */
988 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
989 IOACCEL1_BUSADDR_CMDTYPE;
990}
991
8be986cc
SC		 992static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
993 struct CommandList *c,
994 int reply_queue)
995{
996 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
997 &h->ioaccel2_cmd_pool[c->cmdindex];
998
999 /* Tell the controller to post the reply to the queue for this
1000 * processor. This seems to give the best I/O throughput.
1001 */
1002 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1003 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1004 else
1005 cp->reply_queue = reply_queue % h->nreply_queues;
1006 /* Set the bits in the address sent down to include:
1007 * - performant mode bit not used in ioaccel mode 2
1008 * - pull count (bits 0-3)
1009 * - command type isn't needed for ioaccel2
1010 */
1011 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1012}
1013
c349775e 1014static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1015 struct CommandList *c,
1016 int reply_queue)
c349775e
ST		 1017{
1018 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1019
25163bd5
WS		 1020 /*
1021 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1022 * processor. This seems to give the best I/O throughput.
1023 */
25163bd5
WS		 1024 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1025 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1026 else
1027 cp->reply_queue = reply_queue % h->nreply_queues;
1028 /*
1029 * Set the bits in the address sent down to include:
c349775e
ST		 1030 * - performant mode bit not used in ioaccel mode 2
1031 * - pull count (bits 0-3)
1032 * - command type isn't needed for ioaccel2
1033 */
1034 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1035}
1036
e85c5974
SC		 1037static int is_firmware_flash_cmd(u8 *cdb)
1038{
1039 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1040}
1041
1042/*
1043 * During firmware flash, the heartbeat register may not update as frequently
1044 * as it should. So we dial down lockup detection during firmware flash. and
1045 * dial it back up when firmware flash completes.
1046 */
1047#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1048#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1049static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1050 struct CommandList *c)
1051{
1052 if (!is_firmware_flash_cmd(c->Request.CDB))
1053 return;
1054 atomic_inc(&h->firmware_flash_in_progress);
1055 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1056}
1057
1058static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1059 struct CommandList *c)
1060{
1061 if (is_firmware_flash_cmd(c->Request.CDB) &&
1062 atomic_dec_and_test(&h->firmware_flash_in_progress))
1063 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1064}
1065
25163bd5
WS		 1066static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1067 struct CommandList *c, int reply_queue)
3f5eac3a 1068{
c05e8866
SC		 1069 dial_down_lockup_detection_during_fw_flash(h, c);
1070 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1071 switch (c->cmd_type) {
1072 case CMD_IOACCEL1:
25163bd5 1073 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1074 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1075 break;
1076 case CMD_IOACCEL2:
25163bd5 1077 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1078 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1079 break;
8be986cc
SC		 1080 case IOACCEL2_TMF:
1081 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1082 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1083 break;
c349775e 1084 default:
25163bd5 1085 set_performant_mode(h, c, reply_queue);
c05e8866 1086 h->access.submit_command(h, c);
c349775e 1087 }
3f5eac3a
SC		 1088}
1089
a58e7e53 1090static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1091{
d604f533 1092 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1093 return finish_cmd(c);
1094
25163bd5
WS		 1095 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1096}
1097
3f5eac3a
SC		 1098static inline int is_hba_lunid(unsigned char scsi3addr[])
1099{
1100 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1101}
1102
1103static inline int is_scsi_rev_5(struct ctlr_info *h)
1104{
1105 if (!h->hba_inquiry_data)
1106 return 0;
1107 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1108 return 1;
1109 return 0;
1110}
1111
edd16368
SC		 1112static int hpsa_find_target_lun(struct ctlr_info *h,
1113 unsigned char scsi3addr[], int bus, int *target, int *lun)
1114{
1115 /* finds an unused bus, target, lun for a new physical device
1116 * assumes h->devlock is held
1117 */
1118 int i, found = 0;
cfe5badc 1119 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1120
263d9401 1121 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1122
1123 for (i = 0; i < h->ndevices; i++) {
1124 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1125 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1126 }
1127
263d9401
AM		 1128 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1129 if (i < HPSA_MAX_DEVICES) {
1130 /* *bus = 1; */
1131 *target = i;
1132 *lun = 0;
1133 found = 1;
edd16368
SC		 1134 }
1135 return !found;
1136}
1137
0d96ef5f
WS		 1138static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1139 struct hpsa_scsi_dev_t *dev, char *description)
1140{
1141 dev_printk(level, &h->pdev->dev,
1142 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1143 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1144 description,
1145 scsi_device_type(dev->devtype),
1146 dev->vendor,
1147 dev->model,
1148 dev->raid_level > RAID_UNKNOWN ?
1149 "RAID-?" : raid_label[dev->raid_level],
1150 dev->offload_config ? '+' : '-',
1151 dev->offload_enabled ? '+' : '-',
1152 dev->expose_state);
1153}
1154
edd16368 1155/* Add an entry into h->dev[] array. */
8aa60681 1156static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1157 struct hpsa_scsi_dev_t *device,
1158 struct hpsa_scsi_dev_t *added[], int *nadded)
1159{
1160 /* assumes h->devlock is held */
1161 int n = h->ndevices;
1162 int i;
1163 unsigned char addr1[8], addr2[8];
1164 struct hpsa_scsi_dev_t *sd;
1165
cfe5badc 1166 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1167 dev_err(&h->pdev->dev, "too many devices, some will be "
1168 "inaccessible.\n");
1169 return -1;
1170 }
1171
1172 /* physical devices do not have lun or target assigned until now. */
1173 if (device->lun != -1)
1174 /* Logical device, lun is already assigned. */
1175 goto lun_assigned;
1176
1177 /* If this device a non-zero lun of a multi-lun device
1178 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1179 * unit no, zero otherwise.
edd16368
SC		 1180 */
1181 if (device->scsi3addr[4] == 0) {
1182 /* This is not a non-zero lun of a multi-lun device */
1183 if (hpsa_find_target_lun(h, device->scsi3addr,
1184 device->bus, &device->target, &device->lun) != 0)
1185 return -1;
1186 goto lun_assigned;
1187 }
1188
1189 /* This is a non-zero lun of a multi-lun device.
1190 * Search through our list and find the device which
9a4178b7 1191 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1192 * Assign the same bus and target for this new LUN.
1193 * Use the logical unit number from the firmware.
1194 */
1195 memcpy(addr1, device->scsi3addr, 8);
1196 addr1[4] = 0;
9a4178b7 1197 addr1[5] = 0;
edd16368
SC		 1198 for (i = 0; i < n; i++) {
1199 sd = h->dev[i];
1200 memcpy(addr2, sd->scsi3addr, 8);
1201 addr2[4] = 0;
9a4178b7 1202 addr2[5] = 0;
1203 /* differ only in byte 4 and 5? */
edd16368
SC		 1204 if (memcmp(addr1, addr2, 8) == 0) {
1205 device->bus = sd->bus;
1206 device->target = sd->target;
1207 device->lun = device->scsi3addr[4];
1208 break;
1209 }
1210 }
1211 if (device->lun == -1) {
1212 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1213 " suspect firmware bug or unsupported hardware "
1214 "configuration.\n");
1215 return -1;
1216 }
1217
1218lun_assigned:
1219
1220 h->dev[n] = device;
1221 h->ndevices++;
1222 added[*nadded] = device;
1223 (*nadded)++;
0d96ef5f
WS		 1224 hpsa_show_dev_msg(KERN_INFO, h, device,
1225 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1226 device->offload_to_be_enabled = device->offload_enabled;
1227 device->offload_enabled = 0;
edd16368
SC		 1228 return 0;
1229}
1230
bd9244f7 1231/* Update an entry in h->dev[] array. */
8aa60681 1232static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1233 int entry, struct hpsa_scsi_dev_t *new_entry)
1234{
a473d86c 1235 int offload_enabled;
bd9244f7
ST		 1236 /* assumes h->devlock is held */
1237 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1238
1239 /* Raid level changed. */
1240 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1241
03383736
DB		 1242 /* Raid offload parameters changed. Careful about the ordering. */
1243 if (new_entry->offload_config && new_entry->offload_enabled) {
1244 /*
1245 * if drive is newly offload_enabled, we want to copy the
1246 * raid map data first. If previously offload_enabled and
1247 * offload_config were set, raid map data had better be
1248 * the same as it was before. if raid map data is changed
1249 * then it had better be the case that
1250 * h->dev[entry]->offload_enabled is currently 0.
1251 */
1252 h->dev[entry]->raid_map = new_entry->raid_map;
1253 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1254 }
a3144e0b
JH		 1255 if (new_entry->hba_ioaccel_enabled) {
1256 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1257 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1258 }
1259 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1260 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1261 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1262 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1263
41ce4c35
SC		 1264 /*
1265 * We can turn off ioaccel offload now, but need to delay turning
1266 * it on until we can update h->dev[entry]->phys_disk[], but we
1267 * can't do that until all the devices are updated.
1268 */
1269 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1270 if (!new_entry->offload_enabled)
1271 h->dev[entry]->offload_enabled = 0;
1272
a473d86c
RE		 1273 offload_enabled = h->dev[entry]->offload_enabled;
1274 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1275 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1276 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1277}
1278
2a8ccf31 1279/* Replace an entry from h->dev[] array. */
8aa60681 1280static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1281 int entry, struct hpsa_scsi_dev_t *new_entry,
1282 struct hpsa_scsi_dev_t *added[], int *nadded,
1283 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1284{
1285 /* assumes h->devlock is held */
cfe5badc 1286 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1287 removed[*nremoved] = h->dev[entry];
1288 (*nremoved)++;
01350d05
SC		 1289
1290 /*
1291 * New physical devices won't have target/lun assigned yet
1292 * so we need to preserve the values in the slot we are replacing.
1293 */
1294 if (new_entry->target == -1) {
1295 new_entry->target = h->dev[entry]->target;
1296 new_entry->lun = h->dev[entry]->lun;
1297 }
1298
2a8ccf31
SC		 1299 h->dev[entry] = new_entry;
1300 added[*nadded] = new_entry;
1301 (*nadded)++;
0d96ef5f 1302 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1303 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1304 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1305}
1306
edd16368 1307/* Remove an entry from h->dev[] array. */
8aa60681 1308static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1309 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1310{
1311 /* assumes h->devlock is held */
1312 int i;
1313 struct hpsa_scsi_dev_t *sd;
1314
cfe5badc 1315 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1316
1317 sd = h->dev[entry];
1318 removed[*nremoved] = h->dev[entry];
1319 (*nremoved)++;
1320
1321 for (i = entry; i < h->ndevices-1; i++)
1322 h->dev[i] = h->dev[i+1];
1323 h->ndevices--;
0d96ef5f 1324 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1325}
1326
1327#define SCSI3ADDR_EQ(a, b) ( \
1328 (a)[7] == (b)[7] && \
1329 (a)[6] == (b)[6] && \
1330 (a)[5] == (b)[5] && \
1331 (a)[4] == (b)[4] && \
1332 (a)[3] == (b)[3] && \
1333 (a)[2] == (b)[2] && \
1334 (a)[1] == (b)[1] && \
1335 (a)[0] == (b)[0])
1336
1337static void fixup_botched_add(struct ctlr_info *h,
1338 struct hpsa_scsi_dev_t *added)
1339{
1340 /* called when scsi_add_device fails in order to re-adjust
1341 * h->dev[] to match the mid layer's view.
1342 */
1343 unsigned long flags;
1344 int i, j;
1345
1346 spin_lock_irqsave(&h->lock, flags);
1347 for (i = 0; i < h->ndevices; i++) {
1348 if (h->dev[i] == added) {
1349 for (j = i; j < h->ndevices-1; j++)
1350 h->dev[j] = h->dev[j+1];
1351 h->ndevices--;
1352 break;
1353 }
1354 }
1355 spin_unlock_irqrestore(&h->lock, flags);
1356 kfree(added);
1357}
1358
1359static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1360 struct hpsa_scsi_dev_t *dev2)
1361{
edd16368
SC		 1362 /* we compare everything except lun and target as these
1363 * are not yet assigned. Compare parts likely
1364 * to differ first
1365 */
1366 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1367 sizeof(dev1->scsi3addr)) != 0)
1368 return 0;
1369 if (memcmp(dev1->device_id, dev2->device_id,
1370 sizeof(dev1->device_id)) != 0)
1371 return 0;
1372 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1373 return 0;
1374 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1375 return 0;
edd16368
SC		 1376 if (dev1->devtype != dev2->devtype)
1377 return 0;
edd16368
SC		 1378 if (dev1->bus != dev2->bus)
1379 return 0;
1380 return 1;
1381}
1382
bd9244f7
ST		 1383static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1384 struct hpsa_scsi_dev_t *dev2)
1385{
1386 /* Device attributes that can change, but don't mean
1387 * that the device is a different device, nor that the OS
1388 * needs to be told anything about the change.
1389 */
1390 if (dev1->raid_level != dev2->raid_level)
1391 return 1;
250fb125
SC		 1392 if (dev1->offload_config != dev2->offload_config)
1393 return 1;
1394 if (dev1->offload_enabled != dev2->offload_enabled)
1395 return 1;
93849508
DB		 1396 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1397 if (dev1->queue_depth != dev2->queue_depth)
1398 return 1;
bd9244f7
ST		 1399 return 0;
1400}
1401
edd16368
SC		 1402/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1403 * and return needle location in *index. If scsi3addr matches, but not
1404 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1405 * location in *index.
1406 * In the case of a minor device attribute change, such as RAID level, just
1407 * return DEVICE_UPDATED, along with the updated device's location in index.
1408 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1409 */
1410static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1411 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1412 int *index)
1413{
1414 int i;
1415#define DEVICE_NOT_FOUND 0
1416#define DEVICE_CHANGED 1
1417#define DEVICE_SAME 2
bd9244f7 1418#define DEVICE_UPDATED 3
edd16368 1419 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1420 if (haystack[i] == NULL) /* previously removed. */
1421 continue;
edd16368
SC		 1422 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1423 *index = i;
bd9244f7
ST		 1424 if (device_is_the_same(needle, haystack[i])) {
1425 if (device_updated(needle, haystack[i]))
1426 return DEVICE_UPDATED;
edd16368 1427 return DEVICE_SAME;
bd9244f7 1428 } else {
9846590e
SC		 1429 /* Keep offline devices offline */
1430 if (needle->volume_offline)
1431 return DEVICE_NOT_FOUND;
edd16368 1432 return DEVICE_CHANGED;
bd9244f7 1433 }
edd16368
SC		 1434 }
1435 }
1436 *index = -1;
1437 return DEVICE_NOT_FOUND;
1438}
1439
9846590e
SC		 1440static void hpsa_monitor_offline_device(struct ctlr_info *h,
1441 unsigned char scsi3addr[])
1442{
1443 struct offline_device_entry *device;
1444 unsigned long flags;
1445
1446 /* Check to see if device is already on the list */
1447 spin_lock_irqsave(&h->offline_device_lock, flags);
1448 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1449 if (memcmp(device->scsi3addr, scsi3addr,
1450 sizeof(device->scsi3addr)) == 0) {
1451 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1452 return;
1453 }
1454 }
1455 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1456
1457 /* Device is not on the list, add it. */
1458 device = kmalloc(sizeof(*device), GFP_KERNEL);
1459 if (!device) {
1460 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1461 return;
1462 }
1463 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1464 spin_lock_irqsave(&h->offline_device_lock, flags);
1465 list_add_tail(&device->offline_list, &h->offline_device_list);
1466 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1467}
1468
1469/* Print a message explaining various offline volume states */
1470static void hpsa_show_volume_status(struct ctlr_info *h,
1471 struct hpsa_scsi_dev_t *sd)
1472{
1473 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1474 dev_info(&h->pdev->dev,
1475 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1476 h->scsi_host->host_no,
1477 sd->bus, sd->target, sd->lun);
1478 switch (sd->volume_offline) {
1479 case HPSA_LV_OK:
1480 break;
1481 case HPSA_LV_UNDERGOING_ERASE:
1482 dev_info(&h->pdev->dev,
1483 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1484 h->scsi_host->host_no,
1485 sd->bus, sd->target, sd->lun);
1486 break;
5ca01204
SB		 1487 case HPSA_LV_NOT_AVAILABLE:
1488 dev_info(&h->pdev->dev,
1489 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1490 h->scsi_host->host_no,
1491 sd->bus, sd->target, sd->lun);
1492 break;
9846590e
SC		 1493 case HPSA_LV_UNDERGOING_RPI:
1494 dev_info(&h->pdev->dev,
5ca01204 1495 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1496 h->scsi_host->host_no,
1497 sd->bus, sd->target, sd->lun);
1498 break;
1499 case HPSA_LV_PENDING_RPI:
1500 dev_info(&h->pdev->dev,
5ca01204
SB		 1501 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1502 h->scsi_host->host_no,
1503 sd->bus, sd->target, sd->lun);
9846590e
SC		 1504 break;
1505 case HPSA_LV_ENCRYPTED_NO_KEY:
1506 dev_info(&h->pdev->dev,
1507 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1508 h->scsi_host->host_no,
1509 sd->bus, sd->target, sd->lun);
1510 break;
1511 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1512 dev_info(&h->pdev->dev,
1513 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1514 h->scsi_host->host_no,
1515 sd->bus, sd->target, sd->lun);
1516 break;
1517 case HPSA_LV_UNDERGOING_ENCRYPTION:
1518 dev_info(&h->pdev->dev,
1519 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1520 h->scsi_host->host_no,
1521 sd->bus, sd->target, sd->lun);
1522 break;
1523 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1524 dev_info(&h->pdev->dev,
1525 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1526 h->scsi_host->host_no,
1527 sd->bus, sd->target, sd->lun);
1528 break;
1529 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1530 dev_info(&h->pdev->dev,
1531 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1532 h->scsi_host->host_no,
1533 sd->bus, sd->target, sd->lun);
1534 break;
1535 case HPSA_LV_PENDING_ENCRYPTION:
1536 dev_info(&h->pdev->dev,
1537 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1538 h->scsi_host->host_no,
1539 sd->bus, sd->target, sd->lun);
1540 break;
1541 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1542 dev_info(&h->pdev->dev,
1543 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1544 h->scsi_host->host_no,
1545 sd->bus, sd->target, sd->lun);
1546 break;
1547 }
1548}
1549
03383736
DB		 1550/*
1551 * Figure the list of physical drive pointers for a logical drive with
1552 * raid offload configured.
1553 */
1554static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1555 struct hpsa_scsi_dev_t *dev[], int ndevices,
1556 struct hpsa_scsi_dev_t *logical_drive)
1557{
1558 struct raid_map_data *map = &logical_drive->raid_map;
1559 struct raid_map_disk_data *dd = &map->data[0];
1560 int i, j;
1561 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1562 le16_to_cpu(map->metadata_disks_per_row);
1563 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1564 le16_to_cpu(map->layout_map_count) *
1565 total_disks_per_row;
1566 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1567 total_disks_per_row;
1568 int qdepth;
1569
1570 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1571 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1572
d604f533
WS		 1573 logical_drive->nphysical_disks = nraid_map_entries;
1574
03383736
DB		 1575 qdepth = 0;
1576 for (i = 0; i < nraid_map_entries; i++) {
1577 logical_drive->phys_disk[i] = NULL;
1578 if (!logical_drive->offload_config)
1579 continue;
1580 for (j = 0; j < ndevices; j++) {
1581 if (dev[j]->devtype != TYPE_DISK)
1582 continue;
1583 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1584 continue;
1585 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1586 continue;
1587
1588 logical_drive->phys_disk[i] = dev[j];
1589 if (i < nphys_disk)
1590 qdepth = min(h->nr_cmds, qdepth +
1591 logical_drive->phys_disk[i]->queue_depth);
1592 break;
1593 }
1594
1595 /*
1596 * This can happen if a physical drive is removed and
1597 * the logical drive is degraded. In that case, the RAID
1598 * map data will refer to a physical disk which isn't actually
1599 * present. And in that case offload_enabled should already
1600 * be 0, but we'll turn it off here just in case
1601 */
1602 if (!logical_drive->phys_disk[i]) {
1603 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1604 logical_drive->offload_to_be_enabled = 0;
1605 logical_drive->queue_depth = 8;
03383736
DB		 1606 }
1607 }
1608 if (nraid_map_entries)
1609 /*
1610 * This is correct for reads, too high for full stripe writes,
1611 * way too high for partial stripe writes
1612 */
1613 logical_drive->queue_depth = qdepth;
1614 else
1615 logical_drive->queue_depth = h->nr_cmds;
1616}
1617
1618static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1619 struct hpsa_scsi_dev_t *dev[], int ndevices)
1620{
1621 int i;
1622
1623 for (i = 0; i < ndevices; i++) {
1624 if (dev[i]->devtype != TYPE_DISK)
1625 continue;
1626 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1627 continue;
41ce4c35
SC		 1628
1629 /*
1630 * If offload is currently enabled, the RAID map and
1631 * phys_disk[] assignment *better* not be changing
1632 * and since it isn't changing, we do not need to
1633 * update it.
1634 */
1635 if (dev[i]->offload_enabled)
1636 continue;
1637
03383736
DB		 1638 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1639 }
1640}
1641
8aa60681 1642static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1643 struct hpsa_scsi_dev_t *sd[], int nsds)
1644{
1645 /* sd contains scsi3 addresses and devtypes, and inquiry
1646 * data. This function takes what's in sd to be the current
1647 * reality and updates h->dev[] to reflect that reality.
1648 */
1649 int i, entry, device_change, changes = 0;
1650 struct hpsa_scsi_dev_t *csd;
1651 unsigned long flags;
1652 struct hpsa_scsi_dev_t **added, **removed;
1653 int nadded, nremoved;
1654 struct Scsi_Host *sh = NULL;
1655
cfe5badc
ST		 1656 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1657 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1658
1659 if (!added || !removed) {
1660 dev_warn(&h->pdev->dev, "out of memory in "
1661 "adjust_hpsa_scsi_table\n");
1662 goto free_and_out;
1663 }
1664
1665 spin_lock_irqsave(&h->devlock, flags);
1666
1667 /* find any devices in h->dev[] that are not in
1668 * sd[] and remove them from h->dev[], and for any
1669 * devices which have changed, remove the old device
1670 * info and add the new device info.
bd9244f7
ST		 1671 * If minor device attributes change, just update
1672 * the existing device structure.
edd16368
SC		 1673 */
1674 i = 0;
1675 nremoved = 0;
1676 nadded = 0;
1677 while (i < h->ndevices) {
1678 csd = h->dev[i];
1679 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1680 if (device_change == DEVICE_NOT_FOUND) {
1681 changes++;
8aa60681 1682 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1683 continue; /* remove ^^^, hence i not incremented */
1684 } else if (device_change == DEVICE_CHANGED) {
1685 changes++;
8aa60681 1686 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1687 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1688 /* Set it to NULL to prevent it from being freed
1689 * at the bottom of hpsa_update_scsi_devices()
1690 */
1691 sd[entry] = NULL;
bd9244f7 1692 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1693 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1694 }
1695 i++;
1696 }
1697
1698 /* Now, make sure every device listed in sd[] is also
1699 * listed in h->dev[], adding them if they aren't found
1700 */
1701
1702 for (i = 0; i < nsds; i++) {
1703 if (!sd[i]) /* if already added above. */
1704 continue;
9846590e
SC		 1705
1706 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1707 * as the SCSI mid-layer does not handle such devices well.
1708 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1709 * at 160Hz, and prevents the system from coming up.
1710 */
1711 if (sd[i]->volume_offline) {
1712 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1713 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1714 continue;
1715 }
1716
edd16368
SC		 1717 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1718 h->ndevices, &entry);
1719 if (device_change == DEVICE_NOT_FOUND) {
1720 changes++;
8aa60681 1721 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1722 break;
1723 sd[i] = NULL; /* prevent from being freed later. */
1724 } else if (device_change == DEVICE_CHANGED) {
1725 /* should never happen... */
1726 changes++;
1727 dev_warn(&h->pdev->dev,
1728 "device unexpectedly changed.\n");
1729 /* but if it does happen, we just ignore that device */
1730 }
1731 }
41ce4c35
SC		 1732 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1733
1734 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1735 * any logical drives that need it enabled.
1736 */
1737 for (i = 0; i < h->ndevices; i++)
1738 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1739
edd16368
SC		 1740 spin_unlock_irqrestore(&h->devlock, flags);
1741
9846590e
SC		 1742 /* Monitor devices which are in one of several NOT READY states to be
1743 * brought online later. This must be done without holding h->devlock,
1744 * so don't touch h->dev[]
1745 */
1746 for (i = 0; i < nsds; i++) {
1747 if (!sd[i]) /* if already added above. */
1748 continue;
1749 if (sd[i]->volume_offline)
1750 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1751 }
1752
edd16368
SC		 1753 /* Don't notify scsi mid layer of any changes the first time through
1754 * (or if there are no changes) scsi_scan_host will do it later the
1755 * first time through.
1756 */
8aa60681 1757 if (!changes)
edd16368
SC		 1758 goto free_and_out;
1759
1760 sh = h->scsi_host;
1761 /* Notify scsi mid layer of any removed devices */
1762 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1763 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1764 struct scsi_device *sdev =
1765 scsi_device_lookup(sh, removed[i]->bus,
1766 removed[i]->target, removed[i]->lun);
1767 if (sdev != NULL) {
1768 scsi_remove_device(sdev);
1769 scsi_device_put(sdev);
1770 } else {
1771 /*
1772 * We don't expect to get here.
1773 * future cmds to this device will get selection
1774 * timeout as if the device was gone.
1775 */
0d96ef5f
WS		 1776 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1777 "didn't find device for removal.");
41ce4c35 1778 }
edd16368
SC		 1779 }
1780 kfree(removed[i]);
1781 removed[i] = NULL;
1782 }
1783
1784 /* Notify scsi mid layer of any added devices */
1785 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1786 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1787 continue;
edd16368
SC		 1788 if (scsi_add_device(sh, added[i]->bus,
1789 added[i]->target, added[i]->lun) == 0)
1790 continue;
0d96ef5f
WS		 1791 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1792 "addition failed, device not added.");
edd16368
SC		 1793 /* now we have to remove it from h->dev,
1794 * since it didn't get added to scsi mid layer
1795 */
1796 fixup_botched_add(h, added[i]);
105a3dbc 1797 added[i] = NULL;
edd16368
SC		 1798 }
1799
1800free_and_out:
1801 kfree(added);
1802 kfree(removed);
edd16368
SC		 1803}
1804
1805/*
9e03aa2f 1806 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1807 * Assume's h->devlock is held.
1808 */
1809static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1810 int bus, int target, int lun)
1811{
1812 int i;
1813 struct hpsa_scsi_dev_t *sd;
1814
1815 for (i = 0; i < h->ndevices; i++) {
1816 sd = h->dev[i];
1817 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1818 return sd;
1819 }
1820 return NULL;
1821}
1822
edd16368
SC		 1823static int hpsa_slave_alloc(struct scsi_device *sdev)
1824{
1825 struct hpsa_scsi_dev_t *sd;
1826 unsigned long flags;
1827 struct ctlr_info *h;
1828
1829 h = sdev_to_hba(sdev);
1830 spin_lock_irqsave(&h->devlock, flags);
1831 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1832 sdev_id(sdev), sdev->lun);
41ce4c35 1833 if (likely(sd)) {
03383736 1834 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1835 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1836 } else
1837 sdev->hostdata = NULL;
edd16368
SC		 1838 spin_unlock_irqrestore(&h->devlock, flags);
1839 return 0;
1840}
1841
41ce4c35
SC		 1842/* configure scsi device based on internal per-device structure */
1843static int hpsa_slave_configure(struct scsi_device *sdev)
1844{
1845 struct hpsa_scsi_dev_t *sd;
1846 int queue_depth;
1847
1848 sd = sdev->hostdata;
1849 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1850
1851 if (sd)
1852 queue_depth = sd->queue_depth != 0 ?
1853 sd->queue_depth : sdev->host->can_queue;
1854 else
1855 queue_depth = sdev->host->can_queue;
1856
1857 scsi_change_queue_depth(sdev, queue_depth);
1858
1859 return 0;
1860}
1861
edd16368
SC		 1862static void hpsa_slave_destroy(struct scsi_device *sdev)
1863{
bcc44255 1864 /* nothing to do. */
edd16368
SC		 1865}
1866
d9a729f3
WS		 1867static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1868{
1869 int i;
1870
1871 if (!h->ioaccel2_cmd_sg_list)
1872 return;
1873 for (i = 0; i < h->nr_cmds; i++) {
1874 kfree(h->ioaccel2_cmd_sg_list[i]);
1875 h->ioaccel2_cmd_sg_list[i] = NULL;
1876 }
1877 kfree(h->ioaccel2_cmd_sg_list);
1878 h->ioaccel2_cmd_sg_list = NULL;
1879}
1880
1881static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1882{
1883 int i;
1884
1885 if (h->chainsize <= 0)
1886 return 0;
1887
1888 h->ioaccel2_cmd_sg_list =
1889 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1890 GFP_KERNEL);
1891 if (!h->ioaccel2_cmd_sg_list)
1892 return -ENOMEM;
1893 for (i = 0; i < h->nr_cmds; i++) {
1894 h->ioaccel2_cmd_sg_list[i] =
1895 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1896 h->maxsgentries, GFP_KERNEL);
1897 if (!h->ioaccel2_cmd_sg_list[i])
1898 goto clean;
1899 }
1900 return 0;
1901
1902clean:
1903 hpsa_free_ioaccel2_sg_chain_blocks(h);
1904 return -ENOMEM;
1905}
1906
33a2ffce
SC		 1907static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1908{
1909 int i;
1910
1911 if (!h->cmd_sg_list)
1912 return;
1913 for (i = 0; i < h->nr_cmds; i++) {
1914 kfree(h->cmd_sg_list[i]);
1915 h->cmd_sg_list[i] = NULL;
1916 }
1917 kfree(h->cmd_sg_list);
1918 h->cmd_sg_list = NULL;
1919}
1920
105a3dbc 1921static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1922{
1923 int i;
1924
1925 if (h->chainsize <= 0)
1926 return 0;
1927
1928 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1929 GFP_KERNEL);
3d4e6af8
RE		 1930 if (!h->cmd_sg_list) {
1931 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1932 return -ENOMEM;
3d4e6af8 1933 }
33a2ffce
SC		 1934 for (i = 0; i < h->nr_cmds; i++) {
1935 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1936 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1937 if (!h->cmd_sg_list[i]) {
1938 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1939 goto clean;
3d4e6af8 1940 }
33a2ffce
SC		 1941 }
1942 return 0;
1943
1944clean:
1945 hpsa_free_sg_chain_blocks(h);
1946 return -ENOMEM;
1947}
1948
d9a729f3
WS		 1949static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1950 struct io_accel2_cmd *cp, struct CommandList *c)
1951{
1952 struct ioaccel2_sg_element *chain_block;
1953 u64 temp64;
1954 u32 chain_size;
1955
1956 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1957 chain_size = le32_to_cpu(cp->data_len);
1958 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1959 PCI_DMA_TODEVICE);
1960 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1961 /* prevent subsequent unmapping */
1962 cp->sg->address = 0;
1963 return -1;
1964 }
1965 cp->sg->address = cpu_to_le64(temp64);
1966 return 0;
1967}
1968
1969static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1970 struct io_accel2_cmd *cp)
1971{
1972 struct ioaccel2_sg_element *chain_sg;
1973 u64 temp64;
1974 u32 chain_size;
1975
1976 chain_sg = cp->sg;
1977 temp64 = le64_to_cpu(chain_sg->address);
1978 chain_size = le32_to_cpu(cp->data_len);
1979 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1980}
1981
e2bea6df 1982static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1983 struct CommandList *c)
1984{
1985 struct SGDescriptor *chain_sg, *chain_block;
1986 u64 temp64;
50a0decf 1987 u32 chain_len;
33a2ffce
SC		 1988
1989 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1990 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1991 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1992 chain_len = sizeof(*chain_sg) *
2b08b3e9 1993 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1994 chain_sg->Len = cpu_to_le32(chain_len);
1995 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1996 PCI_DMA_TODEVICE);
e2bea6df
SC		 1997 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1998 /* prevent subsequent unmapping */
50a0decf 1999 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2000 return -1;
2001 }
50a0decf 2002 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2003 return 0;
33a2ffce
SC		 2004}
2005
2006static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2007 struct CommandList *c)
2008{
2009 struct SGDescriptor *chain_sg;
33a2ffce 2010
50a0decf 2011 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2012 return;
2013
2014 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2015 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2016 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2017}
2018
a09c1441
ST		 2019
2020/* Decode the various types of errors on ioaccel2 path.
2021 * Return 1 for any error that should generate a RAID path retry.
2022 * Return 0 for errors that don't require a RAID path retry.
2023 */
2024static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2025 struct CommandList *c,
2026 struct scsi_cmnd *cmd,
2027 struct io_accel2_cmd *c2)
2028{
2029 int data_len;
a09c1441 2030 int retry = 0;
c40820d5 2031 u32 ioaccel2_resid = 0;
c349775e
ST		 2032
2033 switch (c2->error_data.serv_response) {
2034 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2035 switch (c2->error_data.status) {
2036 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2037 break;
2038 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2039 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2040 if (c2->error_data.data_present !=
ee6b1889
SC		 2041 IOACCEL2_SENSE_DATA_PRESENT) {
2042 memset(cmd->sense_buffer, 0,
2043 SCSI_SENSE_BUFFERSIZE);
c349775e 2044 break;
ee6b1889 2045 }
c349775e
ST		 2046 /* copy the sense data */
2047 data_len = c2->error_data.sense_data_len;
2048 if (data_len > SCSI_SENSE_BUFFERSIZE)
2049 data_len = SCSI_SENSE_BUFFERSIZE;
2050 if (data_len > sizeof(c2->error_data.sense_data_buff))
2051 data_len =
2052 sizeof(c2->error_data.sense_data_buff);
2053 memcpy(cmd->sense_buffer,
2054 c2->error_data.sense_data_buff, data_len);
a09c1441 2055 retry = 1;
c349775e
ST		 2056 break;
2057 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2058 retry = 1;
c349775e
ST		 2059 break;
2060 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2061 retry = 1;
c349775e
ST		 2062 break;
2063 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2064 retry = 1;
c349775e
ST		 2065 break;
2066 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2067 retry = 1;
c349775e
ST		 2068 break;
2069 default:
a09c1441 2070 retry = 1;
c349775e
ST		 2071 break;
2072 }
2073 break;
2074 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2075 switch (c2->error_data.status) {
2076 case IOACCEL2_STATUS_SR_IO_ERROR:
2077 case IOACCEL2_STATUS_SR_IO_ABORTED:
2078 case IOACCEL2_STATUS_SR_OVERRUN:
2079 retry = 1;
2080 break;
2081 case IOACCEL2_STATUS_SR_UNDERRUN:
2082 cmd->result = (DID_OK << 16); /* host byte */
2083 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2084 ioaccel2_resid = get_unaligned_le32(
2085 &c2->error_data.resid_cnt[0]);
2086 scsi_set_resid(cmd, ioaccel2_resid);
2087 break;
2088 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2089 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2090 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2091 /* We will get an event from ctlr to trigger rescan */
2092 retry = 1;
2093 break;
2094 default:
2095 retry = 1;
c40820d5 2096 }
c349775e
ST		 2097 break;
2098 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2099 break;
2100 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2101 break;
2102 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2103 retry = 1;
c349775e
ST		 2104 break;
2105 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2106 break;
2107 default:
a09c1441 2108 retry = 1;
c349775e
ST		 2109 break;
2110 }
a09c1441
ST		 2111
2112 return retry; /* retry on raid path? */
c349775e
ST		 2113}
2114
a58e7e53
WS		 2115static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2116 struct CommandList *c)
2117{
d604f533
WS		 2118 bool do_wake = false;
2119
a58e7e53
WS		 2120 /*
2121 * Prevent the following race in the abort handler:
2122 *
2123 * 1. LLD is requested to abort a SCSI command
2124 * 2. The SCSI command completes
2125 * 3. The struct CommandList associated with step 2 is made available
2126 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2127 * 5. Abort handler follows scsi_cmnd->host_scribble and
2128 * finds struct CommandList and tries to aborts it
2129 * Now we have aborted the wrong command.
2130 *
d604f533
WS		 2131 * Reset c->scsi_cmd here so that the abort or reset handler will know
2132 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2133 * waiting for this command, and, if so, wake it.
2134 */
2135 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2136 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2137 if (c->abort_pending) {
d604f533 2138 do_wake = true;
a58e7e53 2139 c->abort_pending = false;
a58e7e53 2140 }
d604f533
WS		 2141 if (c->reset_pending) {
2142 unsigned long flags;
2143 struct hpsa_scsi_dev_t *dev;
2144
2145 /*
2146 * There appears to be a reset pending; lock the lock and
2147 * reconfirm. If so, then decrement the count of outstanding
2148 * commands and wake the reset command if this is the last one.
2149 */
2150 spin_lock_irqsave(&h->lock, flags);
2151 dev = c->reset_pending; /* Re-fetch under the lock. */
2152 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2153 do_wake = true;
2154 c->reset_pending = NULL;
2155 spin_unlock_irqrestore(&h->lock, flags);
2156 }
2157
2158 if (do_wake)
2159 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2160}
2161
73153fe5
WS		 2162static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2163 struct CommandList *c)
2164{
2165 hpsa_cmd_resolve_events(h, c);
2166 cmd_tagged_free(h, c);
2167}
2168
8a0ff92c
WS		 2169static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2170 struct CommandList *c, struct scsi_cmnd *cmd)
2171{
73153fe5 2172 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2173 cmd->scsi_done(cmd);
2174}
2175
2176static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2177{
2178 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2179 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2180}
2181
a58e7e53
WS		 2182static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2183{
2184 cmd->result = DID_ABORT << 16;
2185}
2186
2187static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2188 struct scsi_cmnd *cmd)
2189{
2190 hpsa_set_scsi_cmd_aborted(cmd);
2191 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2192 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2193 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2194}
2195
c349775e
ST		 2196static void process_ioaccel2_completion(struct ctlr_info *h,
2197 struct CommandList *c, struct scsi_cmnd *cmd,
2198 struct hpsa_scsi_dev_t *dev)
2199{
2200 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2201
2202 /* check for good status */
2203 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2204 c2->error_data.status == 0))
2205 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2206
8a0ff92c
WS		 2207 /*
2208 * Any RAID offload error results in retry which will use
c349775e
ST		 2209 * the normal I/O path so the controller can handle whatever's
2210 * wrong.
2211 */
2212 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2213 c2->error_data.serv_response ==
2214 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2215 if (c2->error_data.status ==
2216 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2217 dev->offload_enabled = 0;
8a0ff92c
WS		 2218
2219 return hpsa_retry_cmd(h, c);
a09c1441 2220 }
080ef1cc
DB		 2221
2222 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2223 return hpsa_retry_cmd(h, c);
080ef1cc 2224
8a0ff92c 2225 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2226}
2227
9437ac43
SC		 2228/* Returns 0 on success, < 0 otherwise. */
2229static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2230 struct CommandList *cp)
2231{
2232 u8 tmf_status = cp->err_info->ScsiStatus;
2233
2234 switch (tmf_status) {
2235 case CISS_TMF_COMPLETE:
2236 /*
2237 * CISS_TMF_COMPLETE never happens, instead,
2238 * ei->CommandStatus == 0 for this case.
2239 */
2240 case CISS_TMF_SUCCESS:
2241 return 0;
2242 case CISS_TMF_INVALID_FRAME:
2243 case CISS_TMF_NOT_SUPPORTED:
2244 case CISS_TMF_FAILED:
2245 case CISS_TMF_WRONG_LUN:
2246 case CISS_TMF_OVERLAPPED_TAG:
2247 break;
2248 default:
2249 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2250 tmf_status);
2251 break;
2252 }
2253 return -tmf_status;
2254}
2255
1fb011fb 2256static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2257{
2258 struct scsi_cmnd *cmd;
2259 struct ctlr_info *h;
2260 struct ErrorInfo *ei;
283b4a9b 2261 struct hpsa_scsi_dev_t *dev;
d9a729f3 2262 struct io_accel2_cmd *c2;
edd16368 2263
9437ac43
SC		 2264 u8 sense_key;
2265 u8 asc; /* additional sense code */
2266 u8 ascq; /* additional sense code qualifier */
db111e18 2267 unsigned long sense_data_size;
edd16368
SC		 2268
2269 ei = cp->err_info;
7fa3030c 2270 cmd = cp->scsi_cmd;
edd16368 2271 h = cp->h;
283b4a9b 2272 dev = cmd->device->hostdata;
d9a729f3 2273 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2274
2275 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2276 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2277 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2278 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2279
d9a729f3
WS		 2280 if ((cp->cmd_type == CMD_IOACCEL2) &&
2281 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2282 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2283
edd16368
SC		 2284 cmd->result = (DID_OK << 16); /* host byte */
2285 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2286
03383736
DB		 2287 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2288 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2289
25163bd5
WS		 2290 /*
2291 * We check for lockup status here as it may be set for
2292 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2293 * fail_all_oustanding_cmds()
2294 */
2295 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2296 /* DID_NO_CONNECT will prevent a retry */
2297 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2298 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2299 }
2300
d604f533
WS		 2301 if ((unlikely(hpsa_is_pending_event(cp)))) {
2302 if (cp->reset_pending)
2303 return hpsa_cmd_resolve_and_free(h, cp);
2304 if (cp->abort_pending)
2305 return hpsa_cmd_abort_and_free(h, cp, cmd);
2306 }
2307
c349775e
ST		 2308 if (cp->cmd_type == CMD_IOACCEL2)
2309 return process_ioaccel2_completion(h, cp, cmd, dev);
2310
6aa4c361 2311 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2312 if (ei->CommandStatus == 0)
2313 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2314
e1f7de0c
MG		 2315 /* For I/O accelerator commands, copy over some fields to the normal
2316 * CISS header used below for error handling.
2317 */
2318 if (cp->cmd_type == CMD_IOACCEL1) {
2319 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2320 cp->Header.SGList = scsi_sg_count(cmd);
2321 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2322 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2323 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2324 cp->Header.tag = c->tag;
e1f7de0c
MG		 2325 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2326 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2327
2328 /* Any RAID offload error results in retry which will use
2329 * the normal I/O path so the controller can handle whatever's
2330 * wrong.
2331 */
2332 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2333 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2334 dev->offload_enabled = 0;
d604f533 2335 return hpsa_retry_cmd(h, cp);
283b4a9b 2336 }
e1f7de0c
MG		 2337 }
2338
edd16368
SC		 2339 /* an error has occurred */
2340 switch (ei->CommandStatus) {
2341
2342 case CMD_TARGET_STATUS:
9437ac43
SC		 2343 cmd->result |= ei->ScsiStatus;
2344 /* copy the sense data */
2345 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2346 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2347 else
2348 sense_data_size = sizeof(ei->SenseInfo);
2349 if (ei->SenseLen < sense_data_size)
2350 sense_data_size = ei->SenseLen;
2351 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2352 if (ei->ScsiStatus)
2353 decode_sense_data(ei->SenseInfo, sense_data_size,
2354 &sense_key, &asc, &ascq);
edd16368 2355 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2356 if (sense_key == ABORTED_COMMAND) {
2e311fba 2357 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2358 break;
2359 }
edd16368
SC		 2360 break;
2361 }
edd16368
SC		 2362 /* Problem was not a check condition
2363 * Pass it up to the upper layers...
2364 */
2365 if (ei->ScsiStatus) {
2366 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2367 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2368 "Returning result: 0x%x\n",
2369 cp, ei->ScsiStatus,
2370 sense_key, asc, ascq,
2371 cmd->result);
2372 } else { /* scsi status is zero??? How??? */
2373 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2374 "Returning no connection.\n", cp),
2375
2376 /* Ordinarily, this case should never happen,
2377 * but there is a bug in some released firmware
2378 * revisions that allows it to happen if, for
2379 * example, a 4100 backplane loses power and
2380 * the tape drive is in it. We assume that
2381 * it's a fatal error of some kind because we
2382 * can't show that it wasn't. We will make it
2383 * look like selection timeout since that is
2384 * the most common reason for this to occur,
2385 * and it's severe enough.
2386 */
2387
2388 cmd->result = DID_NO_CONNECT << 16;
2389 }
2390 break;
2391
2392 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2393 break;
2394 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2395 dev_warn(&h->pdev->dev,
2396 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2397 break;
2398 case CMD_INVALID: {
2399 /* print_bytes(cp, sizeof(*cp), 1, 0);
2400 print_cmd(cp); */
2401 /* We get CMD_INVALID if you address a non-existent device
2402 * instead of a selection timeout (no response). You will
2403 * see this if you yank out a drive, then try to access it.
2404 * This is kind of a shame because it means that any other
2405 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2406 * missing target. */
2407 cmd->result = DID_NO_CONNECT << 16;
2408 }
2409 break;
2410 case CMD_PROTOCOL_ERR:
256d0eaa 2411 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2412 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2413 cp->Request.CDB);
edd16368
SC		 2414 break;
2415 case CMD_HARDWARE_ERR:
2416 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2417 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2418 cp->Request.CDB);
edd16368
SC		 2419 break;
2420 case CMD_CONNECTION_LOST:
2421 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2422 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2423 cp->Request.CDB);
edd16368
SC		 2424 break;
2425 case CMD_ABORTED:
a58e7e53
WS		 2426 /* Return now to avoid calling scsi_done(). */
2427 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2428 case CMD_ABORT_FAILED:
2429 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2430 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2431 cp->Request.CDB);
edd16368
SC		 2432 break;
2433 case CMD_UNSOLICITED_ABORT:
f6e76055 2434 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2435 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2436 cp->Request.CDB);
edd16368
SC		 2437 break;
2438 case CMD_TIMEOUT:
2439 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2440 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2441 cp->Request.CDB);
edd16368 2442 break;
1d5e2ed0
SC		 2443 case CMD_UNABORTABLE:
2444 cmd->result = DID_ERROR << 16;
2445 dev_warn(&h->pdev->dev, "Command unabortable\n");
2446 break;
9437ac43
SC		 2447 case CMD_TMF_STATUS:
2448 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2449 cmd->result = DID_ERROR << 16;
2450 break;
283b4a9b
SC		 2451 case CMD_IOACCEL_DISABLED:
2452 /* This only handles the direct pass-through case since RAID
2453 * offload is handled above. Just attempt a retry.
2454 */
2455 cmd->result = DID_SOFT_ERROR << 16;
2456 dev_warn(&h->pdev->dev,
2457 "cp %p had HP SSD Smart Path error\n", cp);
2458 break;
edd16368
SC		 2459 default:
2460 cmd->result = DID_ERROR << 16;
2461 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2462 cp, ei->CommandStatus);
2463 }
8a0ff92c
WS		 2464
2465 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2466}
2467
edd16368
SC		 2468static void hpsa_pci_unmap(struct pci_dev *pdev,
2469 struct CommandList *c, int sg_used, int data_direction)
2470{
2471 int i;
edd16368 2472
50a0decf
SC		 2473 for (i = 0; i < sg_used; i++)
2474 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2475 le32_to_cpu(c->SG[i].Len),
2476 data_direction);
edd16368
SC		 2477}
2478
a2dac136 2479static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2480 struct CommandList *cp,
2481 unsigned char *buf,
2482 size_t buflen,
2483 int data_direction)
2484{
01a02ffc 2485 u64 addr64;
edd16368
SC		 2486
2487 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2488 cp->Header.SGList = 0;
50a0decf 2489 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2490 return 0;
edd16368
SC		 2491 }
2492
50a0decf 2493 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2494 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2495 /* Prevent subsequent unmap of something never mapped */
eceaae18 2496 cp->Header.SGList = 0;
50a0decf 2497 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2498 return -1;
eceaae18 2499 }
50a0decf
SC		 2500 cp->SG[0].Addr = cpu_to_le64(addr64);
2501 cp->SG[0].Len = cpu_to_le32(buflen);
2502 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2503 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2504 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2505 return 0;
edd16368
SC		 2506}
2507
25163bd5
WS		 2508#define NO_TIMEOUT ((unsigned long) -1)
2509#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2510static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2511 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2512{
2513 DECLARE_COMPLETION_ONSTACK(wait);
2514
2515 c->waiting = &wait;
25163bd5
WS		 2516 __enqueue_cmd_and_start_io(h, c, reply_queue);
2517 if (timeout_msecs == NO_TIMEOUT) {
2518 /* TODO: get rid of this no-timeout thing */
2519 wait_for_completion_io(&wait);
2520 return IO_OK;
2521 }
2522 if (!wait_for_completion_io_timeout(&wait,
2523 msecs_to_jiffies(timeout_msecs))) {
2524 dev_warn(&h->pdev->dev, "Command timed out.\n");
2525 return -ETIMEDOUT;
2526 }
2527 return IO_OK;
2528}
2529
2530static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2531 int reply_queue, unsigned long timeout_msecs)
2532{
2533 if (unlikely(lockup_detected(h))) {
2534 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2535 return IO_OK;
2536 }
2537 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2538}
2539
094963da
SC		 2540static u32 lockup_detected(struct ctlr_info *h)
2541{
2542 int cpu;
2543 u32 rc, *lockup_detected;
2544
2545 cpu = get_cpu();
2546 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2547 rc = *lockup_detected;
2548 put_cpu();
2549 return rc;
2550}
2551
9c2fc160 2552#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2553static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2554 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2555{
9c2fc160 2556 int backoff_time = 10, retry_count = 0;
25163bd5 2557 int rc;
edd16368
SC		 2558
2559 do {
7630abd0 2560 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2561 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2562 timeout_msecs);
2563 if (rc)
2564 break;
edd16368 2565 retry_count++;
9c2fc160
SC		 2566 if (retry_count > 3) {
2567 msleep(backoff_time);
2568 if (backoff_time < 1000)
2569 backoff_time *= 2;
2570 }
852af20a 2571 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2572 check_for_busy(h, c)) &&
2573 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2574 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2575 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2576 rc = -EIO;
2577 return rc;
edd16368
SC		 2578}
2579
d1e8beac
SC		 2580static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2581 struct CommandList *c)
edd16368 2582{
d1e8beac
SC		 2583 const u8 *cdb = c->Request.CDB;
2584 const u8 *lun = c->Header.LUN.LunAddrBytes;
2585
2586 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2587 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2588 txt, lun[0], lun[1], lun[2], lun[3],
2589 lun[4], lun[5], lun[6], lun[7],
2590 cdb[0], cdb[1], cdb[2], cdb[3],
2591 cdb[4], cdb[5], cdb[6], cdb[7],
2592 cdb[8], cdb[9], cdb[10], cdb[11],
2593 cdb[12], cdb[13], cdb[14], cdb[15]);
2594}
2595
2596static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2597 struct CommandList *cp)
2598{
2599 const struct ErrorInfo *ei = cp->err_info;
edd16368 2600 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2601 u8 sense_key, asc, ascq;
2602 int sense_len;
edd16368 2603
edd16368
SC		 2604 switch (ei->CommandStatus) {
2605 case CMD_TARGET_STATUS:
9437ac43
SC		 2606 if (ei->SenseLen > sizeof(ei->SenseInfo))
2607 sense_len = sizeof(ei->SenseInfo);
2608 else
2609 sense_len = ei->SenseLen;
2610 decode_sense_data(ei->SenseInfo, sense_len,
2611 &sense_key, &asc, &ascq);
d1e8beac
SC		 2612 hpsa_print_cmd(h, "SCSI status", cp);
2613 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2614 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2615 sense_key, asc, ascq);
d1e8beac 2616 else
9437ac43 2617 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2618 if (ei->ScsiStatus == 0)
2619 dev_warn(d, "SCSI status is abnormally zero. "
2620 "(probably indicates selection timeout "
2621 "reported incorrectly due to a known "
2622 "firmware bug, circa July, 2001.)\n");
2623 break;
2624 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2625 break;
2626 case CMD_DATA_OVERRUN:
d1e8beac 2627 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2628 break;
2629 case CMD_INVALID: {
2630 /* controller unfortunately reports SCSI passthru's
2631 * to non-existent targets as invalid commands.
2632 */
d1e8beac
SC		 2633 hpsa_print_cmd(h, "invalid command", cp);
2634 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2635 }
2636 break;
2637 case CMD_PROTOCOL_ERR:
d1e8beac 2638 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2639 break;
2640 case CMD_HARDWARE_ERR:
d1e8beac 2641 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2642 break;
2643 case CMD_CONNECTION_LOST:
d1e8beac 2644 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2645 break;
2646 case CMD_ABORTED:
d1e8beac 2647 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2648 break;
2649 case CMD_ABORT_FAILED:
d1e8beac 2650 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2651 break;
2652 case CMD_UNSOLICITED_ABORT:
d1e8beac 2653 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2654 break;
2655 case CMD_TIMEOUT:
d1e8beac 2656 hpsa_print_cmd(h, "timed out", cp);
edd16368 2657 break;
1d5e2ed0 2658 case CMD_UNABORTABLE:
d1e8beac 2659 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2660 break;
25163bd5
WS		 2661 case CMD_CTLR_LOCKUP:
2662 hpsa_print_cmd(h, "controller lockup detected", cp);
2663 break;
edd16368 2664 default:
d1e8beac
SC		 2665 hpsa_print_cmd(h, "unknown status", cp);
2666 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2667 ei->CommandStatus);
2668 }
2669}
2670
2671static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2672 u16 page, unsigned char *buf,
edd16368
SC		 2673 unsigned char bufsize)
2674{
2675 int rc = IO_OK;
2676 struct CommandList *c;
2677 struct ErrorInfo *ei;
2678
45fcb86e 2679 c = cmd_alloc(h);
edd16368 2680
a2dac136
SC		 2681 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2682 page, scsi3addr, TYPE_CMD)) {
2683 rc = -1;
2684 goto out;
2685 }
25163bd5
WS		 2686 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2687 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2688 if (rc)
2689 goto out;
edd16368
SC		 2690 ei = c->err_info;
2691 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2692 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2693 rc = -1;
2694 }
a2dac136 2695out:
45fcb86e 2696 cmd_free(h, c);
edd16368
SC		 2697 return rc;
2698}
2699
bf711ac6 2700static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2701 u8 reset_type, int reply_queue)
edd16368
SC		 2702{
2703 int rc = IO_OK;
2704 struct CommandList *c;
2705 struct ErrorInfo *ei;
2706
45fcb86e 2707 c = cmd_alloc(h);
edd16368 2708
edd16368 2709
a2dac136 2710 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2711 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2712 scsi3addr, TYPE_MSG);
2713 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2714 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2715 if (rc) {
2716 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2717 goto out;
2718 }
edd16368
SC		 2719 /* no unmap needed here because no data xfer. */
2720
2721 ei = c->err_info;
2722 if (ei->CommandStatus != 0) {
d1e8beac 2723 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2724 rc = -1;
2725 }
25163bd5 2726out:
45fcb86e 2727 cmd_free(h, c);
edd16368
SC		 2728 return rc;
2729}
2730
d604f533
WS		 2731static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2732 struct hpsa_scsi_dev_t *dev,
2733 unsigned char *scsi3addr)
2734{
2735 int i;
2736 bool match = false;
2737 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2738 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2739
2740 if (hpsa_is_cmd_idle(c))
2741 return false;
2742
2743 switch (c->cmd_type) {
2744 case CMD_SCSI:
2745 case CMD_IOCTL_PEND:
2746 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2747 sizeof(c->Header.LUN.LunAddrBytes));
2748 break;
2749
2750 case CMD_IOACCEL1:
2751 case CMD_IOACCEL2:
2752 if (c->phys_disk == dev) {
2753 /* HBA mode match */
2754 match = true;
2755 } else {
2756 /* Possible RAID mode -- check each phys dev. */
2757 /* FIXME: Do we need to take out a lock here? If
2758 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2759 * instead. */
2760 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2761 /* FIXME: an alternate test might be
2762 *
2763 * match = dev->phys_disk[i]->ioaccel_handle
2764 * == c2->scsi_nexus; */
2765 match = dev->phys_disk[i] == c->phys_disk;
2766 }
2767 }
2768 break;
2769
2770 case IOACCEL2_TMF:
2771 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2772 match = dev->phys_disk[i]->ioaccel_handle ==
2773 le32_to_cpu(ac->it_nexus);
2774 }
2775 break;
2776
2777 case 0: /* The command is in the middle of being initialized. */
2778 match = false;
2779 break;
2780
2781 default:
2782 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2783 c->cmd_type);
2784 BUG();
2785 }
2786
2787 return match;
2788}
2789
2790static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2791 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2792{
2793 int i;
2794 int rc = 0;
2795
2796 /* We can really only handle one reset at a time */
2797 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2798 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2799 return -EINTR;
2800 }
2801
2802 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2803
2804 for (i = 0; i < h->nr_cmds; i++) {
2805 struct CommandList *c = h->cmd_pool + i;
2806 int refcount = atomic_inc_return(&c->refcount);
2807
2808 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2809 unsigned long flags;
2810
2811 /*
2812 * Mark the target command as having a reset pending,
2813 * then lock a lock so that the command cannot complete
2814 * while we're considering it. If the command is not
2815 * idle then count it; otherwise revoke the event.
2816 */
2817 c->reset_pending = dev;
2818 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2819 if (!hpsa_is_cmd_idle(c))
2820 atomic_inc(&dev->reset_cmds_out);
2821 else
2822 c->reset_pending = NULL;
2823 spin_unlock_irqrestore(&h->lock, flags);
2824 }
2825
2826 cmd_free(h, c);
2827 }
2828
2829 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2830 if (!rc)
2831 wait_event(h->event_sync_wait_queue,
2832 atomic_read(&dev->reset_cmds_out) == 0 ||
2833 lockup_detected(h));
2834
2835 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2836 dev_warn(&h->pdev->dev,
2837 "Controller lockup detected during reset wait\n");
2838 rc = -ENODEV;
2839 }
d604f533
WS		 2840
2841 if (unlikely(rc))
2842 atomic_set(&dev->reset_cmds_out, 0);
2843
2844 mutex_unlock(&h->reset_mutex);
2845 return rc;
2846}
2847
edd16368
SC		 2848static void hpsa_get_raid_level(struct ctlr_info *h,
2849 unsigned char *scsi3addr, unsigned char *raid_level)
2850{
2851 int rc;
2852 unsigned char *buf;
2853
2854 *raid_level = RAID_UNKNOWN;
2855 buf = kzalloc(64, GFP_KERNEL);
2856 if (!buf)
2857 return;
b7bb24eb 2858 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2859 if (rc == 0)
2860 *raid_level = buf[8];
2861 if (*raid_level > RAID_UNKNOWN)
2862 *raid_level = RAID_UNKNOWN;
2863 kfree(buf);
2864 return;
2865}
2866
283b4a9b
SC		 2867#define HPSA_MAP_DEBUG
2868#ifdef HPSA_MAP_DEBUG
2869static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2870 struct raid_map_data *map_buff)
2871{
2872 struct raid_map_disk_data *dd = &map_buff->data[0];
2873 int map, row, col;
2874 u16 map_cnt, row_cnt, disks_per_row;
2875
2876 if (rc != 0)
2877 return;
2878
2ba8bfc8
SC		 2879 /* Show details only if debugging has been activated. */
2880 if (h->raid_offload_debug < 2)
2881 return;
2882
283b4a9b
SC		 2883 dev_info(&h->pdev->dev, "structure_size = %u\n",
2884 le32_to_cpu(map_buff->structure_size));
2885 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2886 le32_to_cpu(map_buff->volume_blk_size));
2887 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2888 le64_to_cpu(map_buff->volume_blk_cnt));
2889 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2890 map_buff->phys_blk_shift);
2891 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2892 map_buff->parity_rotation_shift);
2893 dev_info(&h->pdev->dev, "strip_size = %u\n",
2894 le16_to_cpu(map_buff->strip_size));
2895 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2896 le64_to_cpu(map_buff->disk_starting_blk));
2897 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2898 le64_to_cpu(map_buff->disk_blk_cnt));
2899 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2900 le16_to_cpu(map_buff->data_disks_per_row));
2901 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2902 le16_to_cpu(map_buff->metadata_disks_per_row));
2903 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2904 le16_to_cpu(map_buff->row_cnt));
2905 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2906 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2907 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2908 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2909 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2910 le16_to_cpu(map_buff->flags) &
2911 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2912 dev_info(&h->pdev->dev, "dekindex = %u\n",
2913 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2914 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2915 for (map = 0; map < map_cnt; map++) {
2916 dev_info(&h->pdev->dev, "Map%u:\n", map);
2917 row_cnt = le16_to_cpu(map_buff->row_cnt);
2918 for (row = 0; row < row_cnt; row++) {
2919 dev_info(&h->pdev->dev, " Row%u:\n", row);
2920 disks_per_row =
2921 le16_to_cpu(map_buff->data_disks_per_row);
2922 for (col = 0; col < disks_per_row; col++, dd++)
2923 dev_info(&h->pdev->dev,
2924 " D%02u: h=0x%04x xor=%u,%u\n",
2925 col, dd->ioaccel_handle,
2926 dd->xor_mult[0], dd->xor_mult[1]);
2927 disks_per_row =
2928 le16_to_cpu(map_buff->metadata_disks_per_row);
2929 for (col = 0; col < disks_per_row; col++, dd++)
2930 dev_info(&h->pdev->dev,
2931 " M%02u: h=0x%04x xor=%u,%u\n",
2932 col, dd->ioaccel_handle,
2933 dd->xor_mult[0], dd->xor_mult[1]);
2934 }
2935 }
2936}
2937#else
2938static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2939 __attribute__((unused)) int rc,
2940 __attribute__((unused)) struct raid_map_data *map_buff)
2941{
2942}
2943#endif
2944
2945static int hpsa_get_raid_map(struct ctlr_info *h,
2946 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2947{
2948 int rc = 0;
2949 struct CommandList *c;
2950 struct ErrorInfo *ei;
2951
45fcb86e 2952 c = cmd_alloc(h);
bf43caf3 2953
283b4a9b
SC		 2954 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2955 sizeof(this_device->raid_map), 0,
2956 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2957 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2958 cmd_free(h, c);
2959 return -1;
283b4a9b 2960 }
25163bd5
WS		 2961 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2962 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2963 if (rc)
2964 goto out;
283b4a9b
SC		 2965 ei = c->err_info;
2966 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2967 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2968 rc = -1;
2969 goto out;
283b4a9b 2970 }
45fcb86e 2971 cmd_free(h, c);
283b4a9b
SC		 2972
2973 /* @todo in the future, dynamically allocate RAID map memory */
2974 if (le32_to_cpu(this_device->raid_map.structure_size) >
2975 sizeof(this_device->raid_map)) {
2976 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2977 rc = -1;
2978 }
2979 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2980 return rc;
25163bd5
WS		 2981out:
2982 cmd_free(h, c);
2983 return rc;
283b4a9b
SC		 2984}
2985
03383736
DB		 2986static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2987 unsigned char scsi3addr[], u16 bmic_device_index,
2988 struct bmic_identify_physical_device *buf, size_t bufsize)
2989{
2990 int rc = IO_OK;
2991 struct CommandList *c;
2992 struct ErrorInfo *ei;
2993
2994 c = cmd_alloc(h);
2995 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2996 0, RAID_CTLR_LUNID, TYPE_CMD);
2997 if (rc)
2998 goto out;
2999
3000 c->Request.CDB[2] = bmic_device_index & 0xff;
3001 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3002
25163bd5
WS		 3003 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3004 NO_TIMEOUT);
03383736
DB		 3005 ei = c->err_info;
3006 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3007 hpsa_scsi_interpret_error(h, c);
3008 rc = -1;
3009 }
3010out:
3011 cmd_free(h, c);
3012 return rc;
3013}
3014
1b70150a
SC		 3015static int hpsa_vpd_page_supported(struct ctlr_info *h,
3016 unsigned char scsi3addr[], u8 page)
3017{
3018 int rc;
3019 int i;
3020 int pages;
3021 unsigned char *buf, bufsize;
3022
3023 buf = kzalloc(256, GFP_KERNEL);
3024 if (!buf)
3025 return 0;
3026
3027 /* Get the size of the page list first */
3028 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3029 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3030 buf, HPSA_VPD_HEADER_SZ);
3031 if (rc != 0)
3032 goto exit_unsupported;
3033 pages = buf[3];
3034 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3035 bufsize = pages + HPSA_VPD_HEADER_SZ;
3036 else
3037 bufsize = 255;
3038
3039 /* Get the whole VPD page list */
3040 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3041 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3042 buf, bufsize);
3043 if (rc != 0)
3044 goto exit_unsupported;
3045
3046 pages = buf[3];
3047 for (i = 1; i <= pages; i++)
3048 if (buf[3 + i] == page)
3049 goto exit_supported;
3050exit_unsupported:
3051 kfree(buf);
3052 return 0;
3053exit_supported:
3054 kfree(buf);
3055 return 1;
3056}
3057
283b4a9b
SC		 3058static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3059 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3060{
3061 int rc;
3062 unsigned char *buf;
3063 u8 ioaccel_status;
3064
3065 this_device->offload_config = 0;
3066 this_device->offload_enabled = 0;
41ce4c35 3067 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3068
3069 buf = kzalloc(64, GFP_KERNEL);
3070 if (!buf)
3071 return;
1b70150a
SC		 3072 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3073 goto out;
283b4a9b 3074 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3075 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3076 if (rc != 0)
3077 goto out;
3078
3079#define IOACCEL_STATUS_BYTE 4
3080#define OFFLOAD_CONFIGURED_BIT 0x01
3081#define OFFLOAD_ENABLED_BIT 0x02
3082 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3083 this_device->offload_config =
3084 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3085 if (this_device->offload_config) {
3086 this_device->offload_enabled =
3087 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3088 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3089 this_device->offload_enabled = 0;
3090 }
41ce4c35 3091 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3092out:
3093 kfree(buf);
3094 return;
3095}
3096
edd16368
SC		 3097/* Get the device id from inquiry page 0x83 */
3098static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3099 unsigned char *device_id, int buflen)
3100{
3101 int rc;
3102 unsigned char *buf;
3103
3104 if (buflen > 16)
3105 buflen = 16;
3106 buf = kzalloc(64, GFP_KERNEL);
3107 if (!buf)
a84d794d 3108 return -ENOMEM;
b7bb24eb 3109 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3110 if (rc == 0)
3111 memcpy(device_id, &buf[8], buflen);
3112 kfree(buf);
3113 return rc != 0;
3114}
3115
3116static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3117 void *buf, int bufsize,
edd16368
SC		 3118 int extended_response)
3119{
3120 int rc = IO_OK;
3121 struct CommandList *c;
3122 unsigned char scsi3addr[8];
3123 struct ErrorInfo *ei;
3124
45fcb86e 3125 c = cmd_alloc(h);
bf43caf3 3126
e89c0ae7
SC		 3127 /* address the controller */
3128 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3129 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3130 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3131 rc = -1;
3132 goto out;
3133 }
edd16368
SC		 3134 if (extended_response)
3135 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3136 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3137 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3138 if (rc)
3139 goto out;
edd16368
SC		 3140 ei = c->err_info;
3141 if (ei->CommandStatus != 0 &&
3142 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3143 hpsa_scsi_interpret_error(h, c);
edd16368 3144 rc = -1;
283b4a9b 3145 } else {
03383736
DB		 3146 struct ReportLUNdata *rld = buf;
3147
3148 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3149 dev_err(&h->pdev->dev,
3150 "report luns requested format %u, got %u\n",
3151 extended_response,
03383736 3152 rld->extended_response_flag);
283b4a9b
SC		 3153 rc = -1;
3154 }
edd16368 3155 }
a2dac136 3156out:
45fcb86e 3157 cmd_free(h, c);
edd16368
SC		 3158 return rc;
3159}
3160
3161static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3162 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3163{
03383736
DB		 3164 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3165 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3166}
3167
3168static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3169 struct ReportLUNdata *buf, int bufsize)
3170{
3171 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3172}
3173
3174static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3175 int bus, int target, int lun)
3176{
3177 device->bus = bus;
3178 device->target = target;
3179 device->lun = lun;
3180}
3181
9846590e
SC		 3182/* Use VPD inquiry to get details of volume status */
3183static int hpsa_get_volume_status(struct ctlr_info *h,
3184 unsigned char scsi3addr[])
3185{
3186 int rc;
3187 int status;
3188 int size;
3189 unsigned char *buf;
3190
3191 buf = kzalloc(64, GFP_KERNEL);
3192 if (!buf)
3193 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3194
3195 /* Does controller have VPD for logical volume status? */
24a4b078 3196 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3197 goto exit_failed;
9846590e
SC		 3198
3199 /* Get the size of the VPD return buffer */
3200 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3201 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3202 if (rc != 0)
9846590e 3203 goto exit_failed;
9846590e
SC		 3204 size = buf[3];
3205
3206 /* Now get the whole VPD buffer */
3207 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3208 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3209 if (rc != 0)
9846590e 3210 goto exit_failed;
9846590e
SC		 3211 status = buf[4]; /* status byte */
3212
3213 kfree(buf);
3214 return status;
3215exit_failed:
3216 kfree(buf);
3217 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3218}
3219
3220/* Determine offline status of a volume.
3221 * Return either:
3222 * 0 (not offline)
67955ba3 3223 * 0xff (offline for unknown reasons)
9846590e
SC		 3224 * # (integer code indicating one of several NOT READY states
3225 * describing why a volume is to be kept offline)
3226 */
67955ba3 3227static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3228 unsigned char scsi3addr[])
3229{
3230 struct CommandList *c;
9437ac43
SC		 3231 unsigned char *sense;
3232 u8 sense_key, asc, ascq;
3233 int sense_len;
25163bd5 3234 int rc, ldstat = 0;
9846590e
SC		 3235 u16 cmd_status;
3236 u8 scsi_status;
3237#define ASC_LUN_NOT_READY 0x04
3238#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3239#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3240
3241 c = cmd_alloc(h);
bf43caf3 3242
9846590e 3243 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3244 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3245 if (rc) {
3246 cmd_free(h, c);
3247 return 0;
3248 }
9846590e 3249 sense = c->err_info->SenseInfo;
9437ac43
SC		 3250 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3251 sense_len = sizeof(c->err_info->SenseInfo);
3252 else
3253 sense_len = c->err_info->SenseLen;
3254 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3255 cmd_status = c->err_info->CommandStatus;
3256 scsi_status = c->err_info->ScsiStatus;
3257 cmd_free(h, c);
3258 /* Is the volume 'not ready'? */
3259 if (cmd_status != CMD_TARGET_STATUS ||
3260 scsi_status != SAM_STAT_CHECK_CONDITION ||
3261 sense_key != NOT_READY ||
3262 asc != ASC_LUN_NOT_READY) {
3263 return 0;
3264 }
3265
3266 /* Determine the reason for not ready state */
3267 ldstat = hpsa_get_volume_status(h, scsi3addr);
3268
3269 /* Keep volume offline in certain cases: */
3270 switch (ldstat) {
3271 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3272 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3273 case HPSA_LV_UNDERGOING_RPI:
3274 case HPSA_LV_PENDING_RPI:
3275 case HPSA_LV_ENCRYPTED_NO_KEY:
3276 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3277 case HPSA_LV_UNDERGOING_ENCRYPTION:
3278 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3279 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3280 return ldstat;
3281 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3282 /* If VPD status page isn't available,
3283 * use ASC/ASCQ to determine state
3284 */
3285 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3286 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3287 return ldstat;
3288 break;
3289 default:
3290 break;
3291 }
3292 return 0;
3293}
3294
9b5c48c2
SC		 3295/*
3296 * Find out if a logical device supports aborts by simply trying one.
3297 * Smart Array may claim not to support aborts on logical drives, but
3298 * if a MSA2000 * is connected, the drives on that will be presented
3299 * by the Smart Array as logical drives, and aborts may be sent to
3300 * those devices successfully. So the simplest way to find out is
3301 * to simply try an abort and see how the device responds.
3302 */
3303static int hpsa_device_supports_aborts(struct ctlr_info *h,
3304 unsigned char *scsi3addr)
3305{
3306 struct CommandList *c;
3307 struct ErrorInfo *ei;
3308 int rc = 0;
3309
3310 u64 tag = (u64) -1; /* bogus tag */
3311
3312 /* Assume that physical devices support aborts */
3313 if (!is_logical_dev_addr_mode(scsi3addr))
3314 return 1;
3315
3316 c = cmd_alloc(h);
bf43caf3 3317
9b5c48c2
SC		 3318 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3319 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3320 /* no unmap needed here because no data xfer. */
3321 ei = c->err_info;
3322 switch (ei->CommandStatus) {
3323 case CMD_INVALID:
3324 rc = 0;
3325 break;
3326 case CMD_UNABORTABLE:
3327 case CMD_ABORT_FAILED:
3328 rc = 1;
3329 break;
9437ac43
SC		 3330 case CMD_TMF_STATUS:
3331 rc = hpsa_evaluate_tmf_status(h, c);
3332 break;
9b5c48c2
SC		 3333 default:
3334 rc = 0;
3335 break;
3336 }
3337 cmd_free(h, c);
3338 return rc;
3339}
3340
edd16368 3341static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3342 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3343 unsigned char *is_OBDR_device)
edd16368 3344{
0b0e1d6c
SC		 3345
3346#define OBDR_SIG_OFFSET 43
3347#define OBDR_TAPE_SIG "$DR-10"
3348#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3349#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3350
ea6d3bc3 3351 unsigned char *inq_buff;
0b0e1d6c 3352 unsigned char *obdr_sig;
edd16368 3353
ea6d3bc3 3354 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3355 if (!inq_buff)
3356 goto bail_out;
3357
edd16368
SC		 3358 /* Do an inquiry to the device to see what it is. */
3359 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3360 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3361 /* Inquiry failed (msg printed already) */
3362 dev_err(&h->pdev->dev,
3363 "hpsa_update_device_info: inquiry failed\n");
3364 goto bail_out;
3365 }
3366
edd16368
SC		 3367 this_device->devtype = (inq_buff[0] & 0x1f);
3368 memcpy(this_device->scsi3addr, scsi3addr, 8);
3369 memcpy(this_device->vendor, &inq_buff[8],
3370 sizeof(this_device->vendor));
3371 memcpy(this_device->model, &inq_buff[16],
3372 sizeof(this_device->model));
edd16368
SC		 3373 memset(this_device->device_id, 0,
3374 sizeof(this_device->device_id));
3375 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3376 sizeof(this_device->device_id));
3377
3378 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3379 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3380 int volume_offline;
3381
edd16368 3382 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3383 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3384 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3385 volume_offline = hpsa_volume_offline(h, scsi3addr);
3386 if (volume_offline < 0 || volume_offline > 0xff)
3387 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3388 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3389 } else {
edd16368 3390 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3391 this_device->offload_config = 0;
3392 this_device->offload_enabled = 0;
41ce4c35 3393 this_device->offload_to_be_enabled = 0;
a3144e0b 3394 this_device->hba_ioaccel_enabled = 0;
9846590e 3395 this_device->volume_offline = 0;
03383736 3396 this_device->queue_depth = h->nr_cmds;
283b4a9b 3397 }
edd16368 3398
0b0e1d6c
SC		 3399 if (is_OBDR_device) {
3400 /* See if this is a One-Button-Disaster-Recovery device
3401 * by looking for "$DR-10" at offset 43 in inquiry data.
3402 */
3403 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3404 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3405 strncmp(obdr_sig, OBDR_TAPE_SIG,
3406 OBDR_SIG_LEN) == 0);
3407 }
edd16368
SC		 3408 kfree(inq_buff);
3409 return 0;
3410
3411bail_out:
3412 kfree(inq_buff);
3413 return 1;
3414}
3415
9b5c48c2
SC		 3416static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3417 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3418{
3419 unsigned long flags;
3420 int rc, entry;
3421 /*
3422 * See if this device supports aborts. If we already know
3423 * the device, we already know if it supports aborts, otherwise
3424 * we have to find out if it supports aborts by trying one.
3425 */
3426 spin_lock_irqsave(&h->devlock, flags);
3427 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3428 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3429 entry >= 0 && entry < h->ndevices) {
3430 dev->supports_aborts = h->dev[entry]->supports_aborts;
3431 spin_unlock_irqrestore(&h->devlock, flags);
3432 } else {
3433 spin_unlock_irqrestore(&h->devlock, flags);
3434 dev->supports_aborts =
3435 hpsa_device_supports_aborts(h, scsi3addr);
3436 if (dev->supports_aborts < 0)
3437 dev->supports_aborts = 0;
3438 }
3439}
3440
4f4eb9f1 3441static unsigned char *ext_target_model[] = {
edd16368
SC		 3442 "MSA2012",
3443 "MSA2024",
3444 "MSA2312",
3445 "MSA2324",
fda38518 3446 "P2000 G3 SAS",
e06c8e5c 3447 "MSA 2040 SAS",
edd16368
SC		 3448 NULL,
3449};
3450
4f4eb9f1 3451static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3452{
3453 int i;
3454
4f4eb9f1
ST		 3455 for (i = 0; ext_target_model[i]; i++)
3456 if (strncmp(device->model, ext_target_model[i],
3457 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3458 return 1;
3459 return 0;
3460}
3461
3462/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3463 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3464 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3465 * Logical drive target and lun are assigned at this time, but
3466 * physical device lun and target assignment are deferred (assigned
3467 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3468 */
3469static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3470 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3471{
1f310bde
SC		 3472 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3473
3474 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3475 /* physical device, target and lun filled in later */
edd16368 3476 if (is_hba_lunid(lunaddrbytes))
1f310bde 3477 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3478 else
1f310bde
SC		 3479 /* defer target, lun assignment for physical devices */
3480 hpsa_set_bus_target_lun(device, 2, -1, -1);
3481 return;
3482 }
3483 /* It's a logical device */
4f4eb9f1
ST		 3484 if (is_ext_target(h, device)) {
3485 /* external target way, put logicals on bus 1
1f310bde
SC		 3486 * and match target/lun numbers box
3487 * reports, other smart array, bus 0, target 0, match lunid
3488 */
3489 hpsa_set_bus_target_lun(device,
3490 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3491 return;
edd16368 3492 }
1f310bde 3493 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3494}
3495
3496/*
3497 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3498 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3499 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3500 * it for some reason. *tmpdevice is the target we're adding,
3501 * this_device is a pointer into the current element of currentsd[]
3502 * that we're building up in update_scsi_devices(), below.
3503 * lunzerobits is a bitmap that tracks which targets already have a
3504 * lun 0 assigned.
3505 * Returns 1 if an enclosure was added, 0 if not.
3506 */
4f4eb9f1 3507static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3508 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3509 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3510 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3511{
3512 unsigned char scsi3addr[8];
3513
1f310bde 3514 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3515 return 0; /* There is already a lun 0 on this target. */
3516
3517 if (!is_logical_dev_addr_mode(lunaddrbytes))
3518 return 0; /* It's the logical targets that may lack lun 0. */
3519
4f4eb9f1
ST		 3520 if (!is_ext_target(h, tmpdevice))
3521 return 0; /* Only external target devices have this problem. */
edd16368 3522
1f310bde 3523 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3524 return 0;
3525
c4f8a299 3526 memset(scsi3addr, 0, 8);
1f310bde 3527 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3528 if (is_hba_lunid(scsi3addr))
3529 return 0; /* Don't add the RAID controller here. */
3530
339b2b14
SC		 3531 if (is_scsi_rev_5(h))
3532 return 0; /* p1210m doesn't need to do this. */
3533
4f4eb9f1 3534 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3535 dev_warn(&h->pdev->dev, "Maximum number of external "
3536 "target devices exceeded. Check your hardware "
edd16368
SC		 3537 "configuration.");
3538 return 0;
3539 }
3540
0b0e1d6c 3541 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3542 return 0;
4f4eb9f1 3543 (*n_ext_target_devs)++;
1f310bde
SC		 3544 hpsa_set_bus_target_lun(this_device,
3545 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3546 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3547 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3548 return 1;
3549}
3550
54b6e9e9
ST		 3551/*
3552 * Get address of physical disk used for an ioaccel2 mode command:
3553 * 1. Extract ioaccel2 handle from the command.
3554 * 2. Find a matching ioaccel2 handle from list of physical disks.
3555 * 3. Return:
3556 * 1 and set scsi3addr to address of matching physical
3557 * 0 if no matching physical disk was found.
3558 */
3559static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3560 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3561{
41ce4c35
SC		 3562 struct io_accel2_cmd *c2 =
3563 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3564 unsigned long flags;
54b6e9e9 3565 int i;
54b6e9e9 3566
41ce4c35
SC		 3567 spin_lock_irqsave(&h->devlock, flags);
3568 for (i = 0; i < h->ndevices; i++)
3569 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3570 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3571 sizeof(h->dev[i]->scsi3addr));
3572 spin_unlock_irqrestore(&h->devlock, flags);
3573 return 1;
3574 }
3575 spin_unlock_irqrestore(&h->devlock, flags);
3576 return 0;
54b6e9e9 3577}
41ce4c35 3578
edd16368
SC		 3579/*
3580 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3581 * logdev. The number of luns in physdev and logdev are returned in
3582 * *nphysicals and *nlogicals, respectively.
3583 * Returns 0 on success, -1 otherwise.
3584 */
3585static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3586 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3587 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3588{
03383736 3589 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3590 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3591 return -1;
3592 }
03383736 3593 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3594 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3595 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3596 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3597 *nphysicals = HPSA_MAX_PHYS_LUN;
3598 }
03383736 3599 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3600 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3601 return -1;
3602 }
6df1e954 3603 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3604 /* Reject Logicals in excess of our max capability. */
3605 if (*nlogicals > HPSA_MAX_LUN) {
3606 dev_warn(&h->pdev->dev,
3607 "maximum logical LUNs (%d) exceeded. "
3608 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3609 *nlogicals - HPSA_MAX_LUN);
3610 *nlogicals = HPSA_MAX_LUN;
3611 }
3612 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3613 dev_warn(&h->pdev->dev,
3614 "maximum logical + physical LUNs (%d) exceeded. "
3615 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3616 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3617 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3618 }
3619 return 0;
3620}
3621
42a91641
DB		 3622static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3623 int i, int nphysicals, int nlogicals,
a93aa1fe 3624 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3625 struct ReportLUNdata *logdev_list)
3626{
3627 /* Helper function, figure out where the LUN ID info is coming from
3628 * given index i, lists of physical and logical devices, where in
3629 * the list the raid controller is supposed to appear (first or last)
3630 */
3631
3632 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3633 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3634
3635 if (i == raid_ctlr_position)
3636 return RAID_CTLR_LUNID;
3637
3638 if (i < logicals_start)
d5b5d964
SC		 3639 return &physdev_list->LUN[i -
3640 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3641
3642 if (i < last_device)
3643 return &logdev_list->LUN[i - nphysicals -
3644 (raid_ctlr_position == 0)][0];
3645 BUG();
3646 return NULL;
3647}
3648
03383736
DB		 3649/* get physical drive ioaccel handle and queue depth */
3650static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3651 struct hpsa_scsi_dev_t *dev,
3652 u8 *lunaddrbytes,
3653 struct bmic_identify_physical_device *id_phys)
3654{
3655 int rc;
3656 struct ext_report_lun_entry *rle =
3657 (struct ext_report_lun_entry *) lunaddrbytes;
3658
3659 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3660 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3661 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3662 memset(id_phys, 0, sizeof(*id_phys));
3663 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3664 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3665 sizeof(*id_phys));
3666 if (!rc)
3667 /* Reserve space for FW operations */
3668#define DRIVE_CMDS_RESERVED_FOR_FW 2
3669#define DRIVE_QUEUE_DEPTH 7
3670 dev->queue_depth =
3671 le16_to_cpu(id_phys->current_queue_depth_limit) -
3672 DRIVE_CMDS_RESERVED_FOR_FW;
3673 else
3674 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3675}
3676
8270b862
JH		 3677static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
3678 u8 *lunaddrbytes,
3679 struct bmic_identify_physical_device *id_phys)
3680{
3681 if (PHYS_IOACCEL(lunaddrbytes)
3682 && this_device->ioaccel_handle)
3683 this_device->hba_ioaccel_enabled = 1;
3684
3685 memcpy(&this_device->active_path_index,
3686 &id_phys->active_path_number,
3687 sizeof(this_device->active_path_index));
3688 memcpy(&this_device->path_map,
3689 &id_phys->redundant_path_present_map,
3690 sizeof(this_device->path_map));
3691 memcpy(&this_device->box,
3692 &id_phys->alternate_paths_phys_box_on_port,
3693 sizeof(this_device->box));
3694 memcpy(&this_device->phys_connector,
3695 &id_phys->alternate_paths_phys_connector,
3696 sizeof(this_device->phys_connector));
3697 memcpy(&this_device->bay,
3698 &id_phys->phys_bay_in_box,
3699 sizeof(this_device->bay));
3700}
3701
8aa60681 3702static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 3703{
3704 /* the idea here is we could get notified
3705 * that some devices have changed, so we do a report
3706 * physical luns and report logical luns cmd, and adjust
3707 * our list of devices accordingly.
3708 *
3709 * The scsi3addr's of devices won't change so long as the
3710 * adapter is not reset. That means we can rescan and
3711 * tell which devices we already know about, vs. new
3712 * devices, vs. disappearing devices.
3713 */
a93aa1fe 3714 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3715 struct ReportLUNdata *logdev_list = NULL;
03383736 3716 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3717 u32 nphysicals = 0;
3718 u32 nlogicals = 0;
3719 u32 ndev_allocated = 0;
edd16368
SC		 3720 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3721 int ncurrent = 0;
4f4eb9f1 3722 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3723 int raid_ctlr_position;
aca4a520 3724 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3725
cfe5badc 3726 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3727 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3728 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3729 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3730 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3731
03383736
DB		 3732 if (!currentsd || !physdev_list || !logdev_list ||
3733 !tmpdevice || !id_phys) {
edd16368
SC		 3734 dev_err(&h->pdev->dev, "out of memory\n");
3735 goto out;
3736 }
3737 memset(lunzerobits, 0, sizeof(lunzerobits));
3738
03383736
DB		 3739 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3740 logdev_list, &nlogicals))
edd16368
SC		 3741 goto out;
3742
aca4a520
ST		 3743 /* We might see up to the maximum number of logical and physical disks
3744 * plus external target devices, and a device for the local RAID
3745 * controller.
edd16368 3746 */
aca4a520 3747 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3748
3749 /* Allocate the per device structures */
3750 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3751 if (i >= HPSA_MAX_DEVICES) {
3752 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3753 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3754 ndevs_to_allocate - HPSA_MAX_DEVICES);
3755 break;
3756 }
3757
edd16368
SC		 3758 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3759 if (!currentsd[i]) {
3760 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3761 __FILE__, __LINE__);
3762 goto out;
3763 }
3764 ndev_allocated++;
3765 }
3766
8645291b 3767 if (is_scsi_rev_5(h))
339b2b14
SC		 3768 raid_ctlr_position = 0;
3769 else
3770 raid_ctlr_position = nphysicals + nlogicals;
3771
edd16368 3772 /* adjust our table of devices */
4f4eb9f1 3773 n_ext_target_devs = 0;
edd16368 3774 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3775 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3776
3777 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3778 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3779 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3780
3781 /* skip masked non-disk devices */
3782 if (MASKED_DEVICE(lunaddrbytes))
3783 if (i < nphysicals + (raid_ctlr_position == 0) &&
3784 NON_DISK_PHYS_DEV(lunaddrbytes))
3785 continue;
edd16368
SC		 3786
3787 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3788 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3789 &is_OBDR))
edd16368 3790 continue; /* skip it if we can't talk to it. */
1f310bde 3791 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3792 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3793 this_device = currentsd[ncurrent];
3794
3795 /*
4f4eb9f1 3796 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3797 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3798 * is nonetheless an enclosure device there. We have to
3799 * present that otherwise linux won't find anything if
3800 * there is no lun 0.
3801 */
4f4eb9f1 3802 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3803 lunaddrbytes, lunzerobits,
4f4eb9f1 3804 &n_ext_target_devs)) {
edd16368
SC		 3805 ncurrent++;
3806 this_device = currentsd[ncurrent];
3807 }
3808
3809 *this_device = *tmpdevice;
edd16368 3810
41ce4c35
SC		 3811 /* do not expose masked devices */
3812 if (MASKED_DEVICE(lunaddrbytes) &&
3813 i < nphysicals + (raid_ctlr_position == 0)) {
41ce4c35
SC		 3814 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3815 } else {
3816 this_device->expose_state =
3817 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3818 }
3819
edd16368 3820 switch (this_device->devtype) {
0b0e1d6c 3821 case TYPE_ROM:
edd16368
SC		 3822 /* We don't *really* support actual CD-ROM devices,
3823 * just "One Button Disaster Recovery" tape drive
3824 * which temporarily pretends to be a CD-ROM drive.
3825 * So we check that the device is really an OBDR tape
3826 * device by checking for "$DR-10" in bytes 43-48 of
3827 * the inquiry data.
3828 */
0b0e1d6c
SC		 3829 if (is_OBDR)
3830 ncurrent++;
edd16368
SC		 3831 break;
3832 case TYPE_DISK:
b9092b79
KB		 3833 if (i < nphysicals + (raid_ctlr_position == 0)) {
3834 /* The disk is in HBA mode. */
3835 /* Never use RAID mapper in HBA mode. */
ecf418d1 3836 this_device->offload_enabled = 0;
b9092b79
KB		 3837 hpsa_get_ioaccel_drive_info(h, this_device,
3838 lunaddrbytes, id_phys);
3839 hpsa_get_path_info(this_device, lunaddrbytes,
3840 id_phys);
3841 }
ecf418d1 3842 ncurrent++;
edd16368
SC		 3843 break;
3844 case TYPE_TAPE:
3845 case TYPE_MEDIUM_CHANGER:
41ce4c35 3846 case TYPE_ENCLOSURE:
b9092b79 3847 ncurrent++;
41ce4c35 3848 break;
edd16368
SC		 3849 case TYPE_RAID:
3850 /* Only present the Smartarray HBA as a RAID controller.
3851 * If it's a RAID controller other than the HBA itself
3852 * (an external RAID controller, MSA500 or similar)
3853 * don't present it.
3854 */
3855 if (!is_hba_lunid(lunaddrbytes))
3856 break;
3857 ncurrent++;
3858 break;
3859 default:
3860 break;
3861 }
cfe5badc 3862 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3863 break;
3864 }
8aa60681 3865 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 3866out:
3867 kfree(tmpdevice);
3868 for (i = 0; i < ndev_allocated; i++)
3869 kfree(currentsd[i]);
3870 kfree(currentsd);
edd16368
SC		 3871 kfree(physdev_list);
3872 kfree(logdev_list);
03383736 3873 kfree(id_phys);
edd16368
SC		 3874}
3875
ec5cbf04
WS		 3876static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3877 struct scatterlist *sg)
3878{
3879 u64 addr64 = (u64) sg_dma_address(sg);
3880 unsigned int len = sg_dma_len(sg);
3881
3882 desc->Addr = cpu_to_le64(addr64);
3883 desc->Len = cpu_to_le32(len);
3884 desc->Ext = 0;
3885}
3886
c7ee65b3
WS		 3887/*
3888 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3889 * dma mapping and fills in the scatter gather entries of the
3890 * hpsa command, cp.
3891 */
33a2ffce 3892static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3893 struct CommandList *cp,
3894 struct scsi_cmnd *cmd)
3895{
edd16368 3896 struct scatterlist *sg;
b3a7ba7c 3897 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3898 struct SGDescriptor *curr_sg;
edd16368 3899
33a2ffce 3900 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3901
3902 use_sg = scsi_dma_map(cmd);
3903 if (use_sg < 0)
3904 return use_sg;
3905
3906 if (!use_sg)
3907 goto sglist_finished;
3908
b3a7ba7c
WS		 3909 /*
3910 * If the number of entries is greater than the max for a single list,
3911 * then we have a chained list; we will set up all but one entry in the
3912 * first list (the last entry is saved for link information);
3913 * otherwise, we don't have a chained list and we'll set up at each of
3914 * the entries in the one list.
3915 */
33a2ffce 3916 curr_sg = cp->SG;
b3a7ba7c
WS		 3917 chained = use_sg > h->max_cmd_sg_entries;
3918 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3919 last_sg = scsi_sg_count(cmd) - 1;
3920 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3921 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3922 curr_sg++;
3923 }
ec5cbf04 3924
b3a7ba7c
WS		 3925 if (chained) {
3926 /*
3927 * Continue with the chained list. Set curr_sg to the chained
3928 * list. Modify the limit to the total count less the entries
3929 * we've already set up. Resume the scan at the list entry
3930 * where the previous loop left off.
3931 */
3932 curr_sg = h->cmd_sg_list[cp->cmdindex];
3933 sg_limit = use_sg - sg_limit;
3934 for_each_sg(sg, sg, sg_limit, i) {
3935 hpsa_set_sg_descriptor(curr_sg, sg);
3936 curr_sg++;
3937 }
3938 }
3939
ec5cbf04 3940 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3941 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3942
3943 if (use_sg + chained > h->maxSG)
3944 h->maxSG = use_sg + chained;
3945
3946 if (chained) {
3947 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3948 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3949 if (hpsa_map_sg_chain_block(h, cp)) {
3950 scsi_dma_unmap(cmd);
3951 return -1;
3952 }
33a2ffce 3953 return 0;
edd16368
SC		 3954 }
3955
3956sglist_finished:
3957
01a02ffc 3958 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3959 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3960 return 0;
3961}
3962
283b4a9b
SC		 3963#define IO_ACCEL_INELIGIBLE (1)
3964static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3965{
3966 int is_write = 0;
3967 u32 block;
3968 u32 block_cnt;
3969
3970 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3971 switch (cdb[0]) {
3972 case WRITE_6:
3973 case WRITE_12:
3974 is_write = 1;
3975 case READ_6:
3976 case READ_12:
3977 if (*cdb_len == 6) {
3978 block = (((u32) cdb[2]) << 8) | cdb[3];
3979 block_cnt = cdb[4];
3980 } else {
3981 BUG_ON(*cdb_len != 12);
3982 block = (((u32) cdb[2]) << 24) |
3983 (((u32) cdb[3]) << 16) |
3984 (((u32) cdb[4]) << 8) |
3985 cdb[5];
3986 block_cnt =
3987 (((u32) cdb[6]) << 24) |
3988 (((u32) cdb[7]) << 16) |
3989 (((u32) cdb[8]) << 8) |
3990 cdb[9];
3991 }
3992 if (block_cnt > 0xffff)
3993 return IO_ACCEL_INELIGIBLE;
3994
3995 cdb[0] = is_write ? WRITE_10 : READ_10;
3996 cdb[1] = 0;
3997 cdb[2] = (u8) (block >> 24);
3998 cdb[3] = (u8) (block >> 16);
3999 cdb[4] = (u8) (block >> 8);
4000 cdb[5] = (u8) (block);
4001 cdb[6] = 0;
4002 cdb[7] = (u8) (block_cnt >> 8);
4003 cdb[8] = (u8) (block_cnt);
4004 cdb[9] = 0;
4005 *cdb_len = 10;
4006 break;
4007 }
4008 return 0;
4009}
4010
c349775e 4011static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4012 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4013 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4014{
4015 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4016 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4017 unsigned int len;
4018 unsigned int total_len = 0;
4019 struct scatterlist *sg;
4020 u64 addr64;
4021 int use_sg, i;
4022 struct SGDescriptor *curr_sg;
4023 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4024
283b4a9b 4025 /* TODO: implement chaining support */
03383736
DB		 4026 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4027 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4028 return IO_ACCEL_INELIGIBLE;
03383736 4029 }
283b4a9b 4030
e1f7de0c
MG		 4031 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4032
03383736
DB		 4033 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4034 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4035 return IO_ACCEL_INELIGIBLE;
03383736 4036 }
283b4a9b 4037
e1f7de0c
MG		 4038 c->cmd_type = CMD_IOACCEL1;
4039
4040 /* Adjust the DMA address to point to the accelerated command buffer */
4041 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4042 (c->cmdindex * sizeof(*cp));
4043 BUG_ON(c->busaddr & 0x0000007F);
4044
4045 use_sg = scsi_dma_map(cmd);
03383736
DB		 4046 if (use_sg < 0) {
4047 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4048 return use_sg;
03383736 4049 }
e1f7de0c
MG		 4050
4051 if (use_sg) {
4052 curr_sg = cp->SG;
4053 scsi_for_each_sg(cmd, sg, use_sg, i) {
4054 addr64 = (u64) sg_dma_address(sg);
4055 len = sg_dma_len(sg);
4056 total_len += len;
50a0decf
SC		 4057 curr_sg->Addr = cpu_to_le64(addr64);
4058 curr_sg->Len = cpu_to_le32(len);
4059 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4060 curr_sg++;
4061 }
50a0decf 4062 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4063
4064 switch (cmd->sc_data_direction) {
4065 case DMA_TO_DEVICE:
4066 control |= IOACCEL1_CONTROL_DATA_OUT;
4067 break;
4068 case DMA_FROM_DEVICE:
4069 control |= IOACCEL1_CONTROL_DATA_IN;
4070 break;
4071 case DMA_NONE:
4072 control |= IOACCEL1_CONTROL_NODATAXFER;
4073 break;
4074 default:
4075 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4076 cmd->sc_data_direction);
4077 BUG();
4078 break;
4079 }
4080 } else {
4081 control |= IOACCEL1_CONTROL_NODATAXFER;
4082 }
4083
c349775e 4084 c->Header.SGList = use_sg;
e1f7de0c 4085 /* Fill out the command structure to submit */
2b08b3e9
DB		 4086 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4087 cp->transfer_len = cpu_to_le32(total_len);
4088 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4089 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4090 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4091 memcpy(cp->CDB, cdb, cdb_len);
4092 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4093 /* Tag was already set at init time. */
283b4a9b 4094 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4095 return 0;
4096}
edd16368 4097
283b4a9b
SC		 4098/*
4099 * Queue a command directly to a device behind the controller using the
4100 * I/O accelerator path.
4101 */
4102static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4103 struct CommandList *c)
4104{
4105 struct scsi_cmnd *cmd = c->scsi_cmd;
4106 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4107
03383736
DB		 4108 c->phys_disk = dev;
4109
283b4a9b 4110 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4111 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4112}
4113
dd0e19f3
ST		 4114/*
4115 * Set encryption parameters for the ioaccel2 request
4116 */
4117static void set_encrypt_ioaccel2(struct ctlr_info *h,
4118 struct CommandList *c, struct io_accel2_cmd *cp)
4119{
4120 struct scsi_cmnd *cmd = c->scsi_cmd;
4121 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4122 struct raid_map_data *map = &dev->raid_map;
4123 u64 first_block;
4124
dd0e19f3 4125 /* Are we doing encryption on this device */
2b08b3e9 4126 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4127 return;
4128 /* Set the data encryption key index. */
4129 cp->dekindex = map->dekindex;
4130
4131 /* Set the encryption enable flag, encoded into direction field. */
4132 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4133
4134 /* Set encryption tweak values based on logical block address
4135 * If block size is 512, tweak value is LBA.
4136 * For other block sizes, tweak is (LBA * block size)/ 512)
4137 */
4138 switch (cmd->cmnd[0]) {
4139 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4140 case WRITE_6:
4141 case READ_6:
2b08b3e9 4142 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4143 break;
4144 case WRITE_10:
4145 case READ_10:
dd0e19f3
ST		 4146 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4147 case WRITE_12:
4148 case READ_12:
2b08b3e9 4149 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4150 break;
4151 case WRITE_16:
4152 case READ_16:
2b08b3e9 4153 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4154 break;
4155 default:
4156 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4157 "ERROR: %s: size (0x%x) not supported for encryption\n",
4158 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4159 BUG();
4160 break;
4161 }
2b08b3e9
DB		 4162
4163 if (le32_to_cpu(map->volume_blk_size) != 512)
4164 first_block = first_block *
4165 le32_to_cpu(map->volume_blk_size)/512;
4166
4167 cp->tweak_lower = cpu_to_le32(first_block);
4168 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4169}
4170
c349775e
ST		 4171static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4172 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4173 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4174{
4175 struct scsi_cmnd *cmd = c->scsi_cmd;
4176 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4177 struct ioaccel2_sg_element *curr_sg;
4178 int use_sg, i;
4179 struct scatterlist *sg;
4180 u64 addr64;
4181 u32 len;
4182 u32 total_len = 0;
4183
d9a729f3 4184 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4185
03383736
DB		 4186 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4187 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4188 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4189 }
4190
c349775e
ST		 4191 c->cmd_type = CMD_IOACCEL2;
4192 /* Adjust the DMA address to point to the accelerated command buffer */
4193 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4194 (c->cmdindex * sizeof(*cp));
4195 BUG_ON(c->busaddr & 0x0000007F);
4196
4197 memset(cp, 0, sizeof(*cp));
4198 cp->IU_type = IOACCEL2_IU_TYPE;
4199
4200 use_sg = scsi_dma_map(cmd);
03383736
DB		 4201 if (use_sg < 0) {
4202 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4203 return use_sg;
03383736 4204 }
c349775e
ST		 4205
4206 if (use_sg) {
c349775e 4207 curr_sg = cp->sg;
d9a729f3
WS		 4208 if (use_sg > h->ioaccel_maxsg) {
4209 addr64 = le64_to_cpu(
4210 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4211 curr_sg->address = cpu_to_le64(addr64);
4212 curr_sg->length = 0;
4213 curr_sg->reserved[0] = 0;
4214 curr_sg->reserved[1] = 0;
4215 curr_sg->reserved[2] = 0;
4216 curr_sg->chain_indicator = 0x80;
4217
4218 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4219 }
c349775e
ST		 4220 scsi_for_each_sg(cmd, sg, use_sg, i) {
4221 addr64 = (u64) sg_dma_address(sg);
4222 len = sg_dma_len(sg);
4223 total_len += len;
4224 curr_sg->address = cpu_to_le64(addr64);
4225 curr_sg->length = cpu_to_le32(len);
4226 curr_sg->reserved[0] = 0;
4227 curr_sg->reserved[1] = 0;
4228 curr_sg->reserved[2] = 0;
4229 curr_sg->chain_indicator = 0;
4230 curr_sg++;
4231 }
4232
4233 switch (cmd->sc_data_direction) {
4234 case DMA_TO_DEVICE:
dd0e19f3
ST		 4235 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4236 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4237 break;
4238 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4239 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4240 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4241 break;
4242 case DMA_NONE:
dd0e19f3
ST		 4243 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4244 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4245 break;
4246 default:
4247 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4248 cmd->sc_data_direction);
4249 BUG();
4250 break;
4251 }
4252 } else {
dd0e19f3
ST		 4253 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4254 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4255 }
dd0e19f3
ST		 4256
4257 /* Set encryption parameters, if necessary */
4258 set_encrypt_ioaccel2(h, c, cp);
4259
2b08b3e9 4260 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4261 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4262 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4263
c349775e
ST		 4264 cp->data_len = cpu_to_le32(total_len);
4265 cp->err_ptr = cpu_to_le64(c->busaddr +
4266 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4267 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4268
d9a729f3
WS		 4269 /* fill in sg elements */
4270 if (use_sg > h->ioaccel_maxsg) {
4271 cp->sg_count = 1;
4272 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4273 atomic_dec(&phys_disk->ioaccel_cmds_out);
4274 scsi_dma_unmap(cmd);
4275 return -1;
4276 }
4277 } else
4278 cp->sg_count = (u8) use_sg;
4279
c349775e
ST		 4280 enqueue_cmd_and_start_io(h, c);
4281 return 0;
4282}
4283
4284/*
4285 * Queue a command to the correct I/O accelerator path.
4286 */
4287static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4289 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4290{
03383736
DB		 4291 /* Try to honor the device's queue depth */
4292 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4293 phys_disk->queue_depth) {
4294 atomic_dec(&phys_disk->ioaccel_cmds_out);
4295 return IO_ACCEL_INELIGIBLE;
4296 }
c349775e
ST		 4297 if (h->transMethod & CFGTBL_Trans_io_accel1)
4298 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4299 cdb, cdb_len, scsi3addr,
4300 phys_disk);
c349775e
ST		 4301 else
4302 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4303 cdb, cdb_len, scsi3addr,
4304 phys_disk);
c349775e
ST		 4305}
4306
6b80b18f
ST		 4307static void raid_map_helper(struct raid_map_data *map,
4308 int offload_to_mirror, u32 *map_index, u32 *current_group)
4309{
4310 if (offload_to_mirror == 0) {
4311 /* use physical disk in the first mirrored group. */
2b08b3e9 4312 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4313 return;
4314 }
4315 do {
4316 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4317 *current_group = *map_index /
4318 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4319 if (offload_to_mirror == *current_group)
4320 continue;
2b08b3e9 4321 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4322 /* select map index from next group */
2b08b3e9 4323 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4324 (*current_group)++;
4325 } else {
4326 /* select map index from first group */
2b08b3e9 4327 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4328 *current_group = 0;
4329 }
4330 } while (offload_to_mirror != *current_group);
4331}
4332
283b4a9b
SC		 4333/*
4334 * Attempt to perform offload RAID mapping for a logical volume I/O.
4335 */
4336static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4337 struct CommandList *c)
4338{
4339 struct scsi_cmnd *cmd = c->scsi_cmd;
4340 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4341 struct raid_map_data *map = &dev->raid_map;
4342 struct raid_map_disk_data *dd = &map->data[0];
4343 int is_write = 0;
4344 u32 map_index;
4345 u64 first_block, last_block;
4346 u32 block_cnt;
4347 u32 blocks_per_row;
4348 u64 first_row, last_row;
4349 u32 first_row_offset, last_row_offset;
4350 u32 first_column, last_column;
6b80b18f
ST		 4351 u64 r0_first_row, r0_last_row;
4352 u32 r5or6_blocks_per_row;
4353 u64 r5or6_first_row, r5or6_last_row;
4354 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4355 u32 r5or6_first_column, r5or6_last_column;
4356 u32 total_disks_per_row;
4357 u32 stripesize;
4358 u32 first_group, last_group, current_group;
283b4a9b
SC		 4359 u32 map_row;
4360 u32 disk_handle;
4361 u64 disk_block;
4362 u32 disk_block_cnt;
4363 u8 cdb[16];
4364 u8 cdb_len;
2b08b3e9 4365 u16 strip_size;
283b4a9b
SC		 4366#if BITS_PER_LONG == 32
4367 u64 tmpdiv;
4368#endif
6b80b18f 4369 int offload_to_mirror;
283b4a9b 4370
283b4a9b
SC		 4371 /* check for valid opcode, get LBA and block count */
4372 switch (cmd->cmnd[0]) {
4373 case WRITE_6:
4374 is_write = 1;
4375 case READ_6:
4376 first_block =
4377 (((u64) cmd->cmnd[2]) << 8) |
4378 cmd->cmnd[3];
4379 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4380 if (block_cnt == 0)
4381 block_cnt = 256;
283b4a9b
SC		 4382 break;
4383 case WRITE_10:
4384 is_write = 1;
4385 case READ_10:
4386 first_block =
4387 (((u64) cmd->cmnd[2]) << 24) |
4388 (((u64) cmd->cmnd[3]) << 16) |
4389 (((u64) cmd->cmnd[4]) << 8) |
4390 cmd->cmnd[5];
4391 block_cnt =
4392 (((u32) cmd->cmnd[7]) << 8) |
4393 cmd->cmnd[8];
4394 break;
4395 case WRITE_12:
4396 is_write = 1;
4397 case READ_12:
4398 first_block =
4399 (((u64) cmd->cmnd[2]) << 24) |
4400 (((u64) cmd->cmnd[3]) << 16) |
4401 (((u64) cmd->cmnd[4]) << 8) |
4402 cmd->cmnd[5];
4403 block_cnt =
4404 (((u32) cmd->cmnd[6]) << 24) |
4405 (((u32) cmd->cmnd[7]) << 16) |
4406 (((u32) cmd->cmnd[8]) << 8) |
4407 cmd->cmnd[9];
4408 break;
4409 case WRITE_16:
4410 is_write = 1;
4411 case READ_16:
4412 first_block =
4413 (((u64) cmd->cmnd[2]) << 56) |
4414 (((u64) cmd->cmnd[3]) << 48) |
4415 (((u64) cmd->cmnd[4]) << 40) |
4416 (((u64) cmd->cmnd[5]) << 32) |
4417 (((u64) cmd->cmnd[6]) << 24) |
4418 (((u64) cmd->cmnd[7]) << 16) |
4419 (((u64) cmd->cmnd[8]) << 8) |
4420 cmd->cmnd[9];
4421 block_cnt =
4422 (((u32) cmd->cmnd[10]) << 24) |
4423 (((u32) cmd->cmnd[11]) << 16) |
4424 (((u32) cmd->cmnd[12]) << 8) |
4425 cmd->cmnd[13];
4426 break;
4427 default:
4428 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4429 }
283b4a9b
SC		 4430 last_block = first_block + block_cnt - 1;
4431
4432 /* check for write to non-RAID-0 */
4433 if (is_write && dev->raid_level != 0)
4434 return IO_ACCEL_INELIGIBLE;
4435
4436 /* check for invalid block or wraparound */
2b08b3e9
DB		 4437 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4438 last_block < first_block)
283b4a9b
SC		 4439 return IO_ACCEL_INELIGIBLE;
4440
4441 /* calculate stripe information for the request */
2b08b3e9
DB		 4442 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4443 le16_to_cpu(map->strip_size);
4444 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4445#if BITS_PER_LONG == 32
4446 tmpdiv = first_block;
4447 (void) do_div(tmpdiv, blocks_per_row);
4448 first_row = tmpdiv;
4449 tmpdiv = last_block;
4450 (void) do_div(tmpdiv, blocks_per_row);
4451 last_row = tmpdiv;
4452 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4453 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4454 tmpdiv = first_row_offset;
2b08b3e9 4455 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4456 first_column = tmpdiv;
4457 tmpdiv = last_row_offset;
2b08b3e9 4458 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4459 last_column = tmpdiv;
4460#else
4461 first_row = first_block / blocks_per_row;
4462 last_row = last_block / blocks_per_row;
4463 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4464 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4465 first_column = first_row_offset / strip_size;
4466 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4467#endif
4468
4469 /* if this isn't a single row/column then give to the controller */
4470 if ((first_row != last_row) || (first_column != last_column))
4471 return IO_ACCEL_INELIGIBLE;
4472
4473 /* proceeding with driver mapping */
2b08b3e9
DB		 4474 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4475 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4476 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4477 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4478 map_index = (map_row * total_disks_per_row) + first_column;
4479
4480 switch (dev->raid_level) {
4481 case HPSA_RAID_0:
4482 break; /* nothing special to do */
4483 case HPSA_RAID_1:
4484 /* Handles load balance across RAID 1 members.
4485 * (2-drive R1 and R10 with even # of drives.)
4486 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4487 */
2b08b3e9 4488 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4489 if (dev->offload_to_mirror)
2b08b3e9 4490 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4491 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4492 break;
4493 case HPSA_RAID_ADM:
4494 /* Handles N-way mirrors (R1-ADM)
4495 * and R10 with # of drives divisible by 3.)
4496 */
2b08b3e9 4497 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4498
4499 offload_to_mirror = dev->offload_to_mirror;
4500 raid_map_helper(map, offload_to_mirror,
4501 &map_index, &current_group);
4502 /* set mirror group to use next time */
4503 offload_to_mirror =
2b08b3e9
DB		 4504 (offload_to_mirror >=
4505 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4506 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4507 dev->offload_to_mirror = offload_to_mirror;
4508 /* Avoid direct use of dev->offload_to_mirror within this
4509 * function since multiple threads might simultaneously
4510 * increment it beyond the range of dev->layout_map_count -1.
4511 */
4512 break;
4513 case HPSA_RAID_5:
4514 case HPSA_RAID_6:
2b08b3e9 4515 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4516 break;
4517
4518 /* Verify first and last block are in same RAID group */
4519 r5or6_blocks_per_row =
2b08b3e9
DB		 4520 le16_to_cpu(map->strip_size) *
4521 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4522 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4523 stripesize = r5or6_blocks_per_row *
4524 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4525#if BITS_PER_LONG == 32
4526 tmpdiv = first_block;
4527 first_group = do_div(tmpdiv, stripesize);
4528 tmpdiv = first_group;
4529 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4530 first_group = tmpdiv;
4531 tmpdiv = last_block;
4532 last_group = do_div(tmpdiv, stripesize);
4533 tmpdiv = last_group;
4534 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4535 last_group = tmpdiv;
4536#else
4537 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4538 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4539#endif
000ff7c2 4540 if (first_group != last_group)
6b80b18f
ST		 4541 return IO_ACCEL_INELIGIBLE;
4542
4543 /* Verify request is in a single row of RAID 5/6 */
4544#if BITS_PER_LONG == 32
4545 tmpdiv = first_block;
4546 (void) do_div(tmpdiv, stripesize);
4547 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4548 tmpdiv = last_block;
4549 (void) do_div(tmpdiv, stripesize);
4550 r5or6_last_row = r0_last_row = tmpdiv;
4551#else
4552 first_row = r5or6_first_row = r0_first_row =
4553 first_block / stripesize;
4554 r5or6_last_row = r0_last_row = last_block / stripesize;
4555#endif
4556 if (r5or6_first_row != r5or6_last_row)
4557 return IO_ACCEL_INELIGIBLE;
4558
4559
4560 /* Verify request is in a single column */
4561#if BITS_PER_LONG == 32
4562 tmpdiv = first_block;
4563 first_row_offset = do_div(tmpdiv, stripesize);
4564 tmpdiv = first_row_offset;
4565 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4566 r5or6_first_row_offset = first_row_offset;
4567 tmpdiv = last_block;
4568 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4569 tmpdiv = r5or6_last_row_offset;
4570 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4571 tmpdiv = r5or6_first_row_offset;
4572 (void) do_div(tmpdiv, map->strip_size);
4573 first_column = r5or6_first_column = tmpdiv;
4574 tmpdiv = r5or6_last_row_offset;
4575 (void) do_div(tmpdiv, map->strip_size);
4576 r5or6_last_column = tmpdiv;
4577#else
4578 first_row_offset = r5or6_first_row_offset =
4579 (u32)((first_block % stripesize) %
4580 r5or6_blocks_per_row);
4581
4582 r5or6_last_row_offset =
4583 (u32)((last_block % stripesize) %
4584 r5or6_blocks_per_row);
4585
4586 first_column = r5or6_first_column =
2b08b3e9 4587 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4588 r5or6_last_column =
2b08b3e9 4589 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4590#endif
4591 if (r5or6_first_column != r5or6_last_column)
4592 return IO_ACCEL_INELIGIBLE;
4593
4594 /* Request is eligible */
4595 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4596 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4597
4598 map_index = (first_group *
2b08b3e9 4599 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4600 (map_row * total_disks_per_row) + first_column;
4601 break;
4602 default:
4603 return IO_ACCEL_INELIGIBLE;
283b4a9b 4604 }
6b80b18f 4605
07543e0c
SC		 4606 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4607 return IO_ACCEL_INELIGIBLE;
4608
03383736
DB		 4609 c->phys_disk = dev->phys_disk[map_index];
4610
283b4a9b 4611 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4612 disk_block = le64_to_cpu(map->disk_starting_blk) +
4613 first_row * le16_to_cpu(map->strip_size) +
4614 (first_row_offset - first_column *
4615 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4616 disk_block_cnt = block_cnt;
4617
4618 /* handle differing logical/physical block sizes */
4619 if (map->phys_blk_shift) {
4620 disk_block <<= map->phys_blk_shift;
4621 disk_block_cnt <<= map->phys_blk_shift;
4622 }
4623 BUG_ON(disk_block_cnt > 0xffff);
4624
4625 /* build the new CDB for the physical disk I/O */
4626 if (disk_block > 0xffffffff) {
4627 cdb[0] = is_write ? WRITE_16 : READ_16;
4628 cdb[1] = 0;
4629 cdb[2] = (u8) (disk_block >> 56);
4630 cdb[3] = (u8) (disk_block >> 48);
4631 cdb[4] = (u8) (disk_block >> 40);
4632 cdb[5] = (u8) (disk_block >> 32);
4633 cdb[6] = (u8) (disk_block >> 24);
4634 cdb[7] = (u8) (disk_block >> 16);
4635 cdb[8] = (u8) (disk_block >> 8);
4636 cdb[9] = (u8) (disk_block);
4637 cdb[10] = (u8) (disk_block_cnt >> 24);
4638 cdb[11] = (u8) (disk_block_cnt >> 16);
4639 cdb[12] = (u8) (disk_block_cnt >> 8);
4640 cdb[13] = (u8) (disk_block_cnt);
4641 cdb[14] = 0;
4642 cdb[15] = 0;
4643 cdb_len = 16;
4644 } else {
4645 cdb[0] = is_write ? WRITE_10 : READ_10;
4646 cdb[1] = 0;
4647 cdb[2] = (u8) (disk_block >> 24);
4648 cdb[3] = (u8) (disk_block >> 16);
4649 cdb[4] = (u8) (disk_block >> 8);
4650 cdb[5] = (u8) (disk_block);
4651 cdb[6] = 0;
4652 cdb[7] = (u8) (disk_block_cnt >> 8);
4653 cdb[8] = (u8) (disk_block_cnt);
4654 cdb[9] = 0;
4655 cdb_len = 10;
4656 }
4657 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4658 dev->scsi3addr,
4659 dev->phys_disk[map_index]);
283b4a9b
SC		 4660}
4661
25163bd5
WS		 4662/*
4663 * Submit commands down the "normal" RAID stack path
4664 * All callers to hpsa_ciss_submit must check lockup_detected
4665 * beforehand, before (opt.) and after calling cmd_alloc
4666 */
574f05d3
SC		 4667static int hpsa_ciss_submit(struct ctlr_info *h,
4668 struct CommandList *c, struct scsi_cmnd *cmd,
4669 unsigned char scsi3addr[])
edd16368 4670{
edd16368 4671 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4672 c->cmd_type = CMD_SCSI;
4673 c->scsi_cmd = cmd;
4674 c->Header.ReplyQueue = 0; /* unused in simple mode */
4675 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4676 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4677
4678 /* Fill in the request block... */
4679
4680 c->Request.Timeout = 0;
edd16368
SC		 4681 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4682 c->Request.CDBLen = cmd->cmd_len;
4683 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4684 switch (cmd->sc_data_direction) {
4685 case DMA_TO_DEVICE:
a505b86f
SC		 4686 c->Request.type_attr_dir =
4687 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4688 break;
4689 case DMA_FROM_DEVICE:
a505b86f
SC		 4690 c->Request.type_attr_dir =
4691 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4692 break;
4693 case DMA_NONE:
a505b86f
SC		 4694 c->Request.type_attr_dir =
4695 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4696 break;
4697 case DMA_BIDIRECTIONAL:
4698 /* This can happen if a buggy application does a scsi passthru
4699 * and sets both inlen and outlen to non-zero. ( see
4700 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4701 */
4702
a505b86f
SC		 4703 c->Request.type_attr_dir =
4704 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4705 /* This is technically wrong, and hpsa controllers should
4706 * reject it with CMD_INVALID, which is the most correct
4707 * response, but non-fibre backends appear to let it
4708 * slide by, and give the same results as if this field
4709 * were set correctly. Either way is acceptable for
4710 * our purposes here.
4711 */
4712
4713 break;
4714
4715 default:
4716 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4717 cmd->sc_data_direction);
4718 BUG();
4719 break;
4720 }
4721
33a2ffce 4722 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4723 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4724 return SCSI_MLQUEUE_HOST_BUSY;
4725 }
4726 enqueue_cmd_and_start_io(h, c);
4727 /* the cmd'll come back via intr handler in complete_scsi_command() */
4728 return 0;
4729}
4730
360c73bd
SC		 4731static void hpsa_cmd_init(struct ctlr_info *h, int index,
4732 struct CommandList *c)
4733{
4734 dma_addr_t cmd_dma_handle, err_dma_handle;
4735
4736 /* Zero out all of commandlist except the last field, refcount */
4737 memset(c, 0, offsetof(struct CommandList, refcount));
4738 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4739 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4740 c->err_info = h->errinfo_pool + index;
4741 memset(c->err_info, 0, sizeof(*c->err_info));
4742 err_dma_handle = h->errinfo_pool_dhandle
4743 + index * sizeof(*c->err_info);
4744 c->cmdindex = index;
4745 c->busaddr = (u32) cmd_dma_handle;
4746 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4747 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4748 c->h = h;
a58e7e53 4749 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4750}
4751
4752static void hpsa_preinitialize_commands(struct ctlr_info *h)
4753{
4754 int i;
4755
4756 for (i = 0; i < h->nr_cmds; i++) {
4757 struct CommandList *c = h->cmd_pool + i;
4758
4759 hpsa_cmd_init(h, i, c);
4760 atomic_set(&c->refcount, 0);
4761 }
4762}
4763
4764static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4765 struct CommandList *c)
4766{
4767 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4768
73153fe5
WS		 4769 BUG_ON(c->cmdindex != index);
4770
360c73bd
SC		 4771 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4772 memset(c->err_info, 0, sizeof(*c->err_info));
4773 c->busaddr = (u32) cmd_dma_handle;
4774}
4775
592a0ad5
WS		 4776static int hpsa_ioaccel_submit(struct ctlr_info *h,
4777 struct CommandList *c, struct scsi_cmnd *cmd,
4778 unsigned char *scsi3addr)
4779{
4780 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4781 int rc = IO_ACCEL_INELIGIBLE;
4782
4783 cmd->host_scribble = (unsigned char *) c;
4784
4785 if (dev->offload_enabled) {
4786 hpsa_cmd_init(h, c->cmdindex, c);
4787 c->cmd_type = CMD_SCSI;
4788 c->scsi_cmd = cmd;
4789 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4790 if (rc < 0) /* scsi_dma_map failed. */
4791 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4792 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4793 hpsa_cmd_init(h, c->cmdindex, c);
4794 c->cmd_type = CMD_SCSI;
4795 c->scsi_cmd = cmd;
4796 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4797 if (rc < 0) /* scsi_dma_map failed. */
4798 rc = SCSI_MLQUEUE_HOST_BUSY;
4799 }
4800 return rc;
4801}
4802
080ef1cc
DB		 4803static void hpsa_command_resubmit_worker(struct work_struct *work)
4804{
4805 struct scsi_cmnd *cmd;
4806 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4807 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4808
4809 cmd = c->scsi_cmd;
4810 dev = cmd->device->hostdata;
4811 if (!dev) {
4812 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4813 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4814 }
d604f533
WS		 4815 if (c->reset_pending)
4816 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4817 if (c->abort_pending)
4818 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4819 if (c->cmd_type == CMD_IOACCEL2) {
4820 struct ctlr_info *h = c->h;
4821 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4822 int rc;
4823
4824 if (c2->error_data.serv_response ==
4825 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4826 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4827 if (rc == 0)
4828 return;
4829 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4830 /*
4831 * If we get here, it means dma mapping failed.
4832 * Try again via scsi mid layer, which will
4833 * then get SCSI_MLQUEUE_HOST_BUSY.
4834 */
4835 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4836 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4837 }
4838 /* else, fall thru and resubmit down CISS path */
4839 }
4840 }
360c73bd 4841 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4842 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4843 /*
4844 * If we get here, it means dma mapping failed. Try
4845 * again via scsi mid layer, which will then get
4846 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4847 *
4848 * hpsa_ciss_submit will have already freed c
4849 * if it encountered a dma mapping failure.
080ef1cc
DB		 4850 */
4851 cmd->result = DID_IMM_RETRY << 16;
4852 cmd->scsi_done(cmd);
4853 }
4854}
4855
574f05d3
SC		 4856/* Running in struct Scsi_Host->host_lock less mode */
4857static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4858{
4859 struct ctlr_info *h;
4860 struct hpsa_scsi_dev_t *dev;
4861 unsigned char scsi3addr[8];
4862 struct CommandList *c;
4863 int rc = 0;
4864
4865 /* Get the ptr to our adapter structure out of cmd->host. */
4866 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4867
4868 BUG_ON(cmd->request->tag < 0);
4869
574f05d3
SC		 4870 dev = cmd->device->hostdata;
4871 if (!dev) {
4872 cmd->result = DID_NO_CONNECT << 16;
4873 cmd->scsi_done(cmd);
4874 return 0;
4875 }
574f05d3 4876
73153fe5 4877 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4878
407863cb 4879 if (unlikely(lockup_detected(h))) {
25163bd5 4880 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4881 cmd->scsi_done(cmd);
4882 return 0;
4883 }
73153fe5 4884 c = cmd_tagged_alloc(h, cmd);
574f05d3 4885
407863cb
SC		 4886 /*
4887 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4888 * Retries always go down the normal I/O path.
4889 */
4890 if (likely(cmd->retries == 0 &&
4891 cmd->request->cmd_type == REQ_TYPE_FS &&
4892 h->acciopath_status)) {
592a0ad5
WS		 4893 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4894 if (rc == 0)
4895 return 0;
4896 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4897 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4898 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4899 }
4900 }
4901 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4902}
4903
8ebc9248 4904static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4905{
4906 unsigned long flags;
4907
8ebc9248
WS		 4908 spin_lock_irqsave(&h->scan_lock, flags);
4909 h->scan_finished = 1;
4910 wake_up_all(&h->scan_wait_queue);
4911 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4912}
4913
a08a8471
SC		 4914static void hpsa_scan_start(struct Scsi_Host *sh)
4915{
4916 struct ctlr_info *h = shost_to_hba(sh);
4917 unsigned long flags;
4918
8ebc9248
WS		 4919 /*
4920 * Don't let rescans be initiated on a controller known to be locked
4921 * up. If the controller locks up *during* a rescan, that thread is
4922 * probably hosed, but at least we can prevent new rescan threads from
4923 * piling up on a locked up controller.
4924 */
4925 if (unlikely(lockup_detected(h)))
4926 return hpsa_scan_complete(h);
5f389360 4927
a08a8471
SC		 4928 /* wait until any scan already in progress is finished. */
4929 while (1) {
4930 spin_lock_irqsave(&h->scan_lock, flags);
4931 if (h->scan_finished)
4932 break;
4933 spin_unlock_irqrestore(&h->scan_lock, flags);
4934 wait_event(h->scan_wait_queue, h->scan_finished);
4935 /* Note: We don't need to worry about a race between this
4936 * thread and driver unload because the midlayer will
4937 * have incremented the reference count, so unload won't
4938 * happen if we're in here.
4939 */
4940 }
4941 h->scan_finished = 0; /* mark scan as in progress */
4942 spin_unlock_irqrestore(&h->scan_lock, flags);
4943
8ebc9248
WS		 4944 if (unlikely(lockup_detected(h)))
4945 return hpsa_scan_complete(h);
5f389360 4946
8aa60681 4947 hpsa_update_scsi_devices(h);
a08a8471 4948
8ebc9248 4949 hpsa_scan_complete(h);
a08a8471
SC		 4950}
4951
7c0a0229
DB		 4952static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4953{
03383736
DB		 4954 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4955
4956 if (!logical_drive)
4957 return -ENODEV;
7c0a0229
DB		 4958
4959 if (qdepth < 1)
4960 qdepth = 1;
03383736
DB		 4961 else if (qdepth > logical_drive->queue_depth)
4962 qdepth = logical_drive->queue_depth;
4963
4964 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4965}
4966
a08a8471
SC		 4967static int hpsa_scan_finished(struct Scsi_Host *sh,
4968 unsigned long elapsed_time)
4969{
4970 struct ctlr_info *h = shost_to_hba(sh);
4971 unsigned long flags;
4972 int finished;
4973
4974 spin_lock_irqsave(&h->scan_lock, flags);
4975 finished = h->scan_finished;
4976 spin_unlock_irqrestore(&h->scan_lock, flags);
4977 return finished;
4978}
4979
2946e82b 4980static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 4981{
b705690d
SC		 4982 struct Scsi_Host *sh;
4983 int error;
edd16368 4984
b705690d 4985 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 4986 if (sh == NULL) {
4987 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4988 return -ENOMEM;
4989 }
b705690d
SC		 4990
4991 sh->io_port = 0;
4992 sh->n_io_port = 0;
4993 sh->this_id = -1;
4994 sh->max_channel = 3;
4995 sh->max_cmd_len = MAX_COMMAND_SIZE;
4996 sh->max_lun = HPSA_MAX_LUN;
4997 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4998 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4999 sh->cmd_per_lun = sh->can_queue;
b705690d 5000 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5001 sh->hostdata[0] = (unsigned long) h;
5002 sh->irq = h->intr[h->intr_mode];
5003 sh->unique_id = sh->irq;
73153fe5
WS		 5004 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5005 if (error) {
5006 dev_err(&h->pdev->dev,
5007 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5008 __func__, h->ctlr);
2946e82b
RE		 5009 scsi_host_put(sh);
5010 return error;
73153fe5 5011 }
2946e82b 5012 h->scsi_host = sh;
b705690d 5013 return 0;
2946e82b 5014}
b705690d 5015
2946e82b
RE		 5016static int hpsa_scsi_add_host(struct ctlr_info *h)
5017{
5018 int rv;
5019
5020 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5021 if (rv) {
5022 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5023 return rv;
5024 }
5025 scsi_scan_host(h->scsi_host);
5026 return 0;
edd16368
SC		 5027}
5028
73153fe5
WS		 5029/*
5030 * The block layer has already gone to the trouble of picking out a unique,
5031 * small-integer tag for this request. We use an offset from that value as
5032 * an index to select our command block. (The offset allows us to reserve the
5033 * low-numbered entries for our own uses.)
5034 */
5035static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5036{
5037 int idx = scmd->request->tag;
5038
5039 if (idx < 0)
5040 return idx;
5041
5042 /* Offset to leave space for internal cmds. */
5043 return idx += HPSA_NRESERVED_CMDS;
5044}
5045
b69324ff
WS		 5046/*
5047 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5048 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5049 */
5050static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5051 struct CommandList *c, unsigned char lunaddr[],
5052 int reply_queue)
5053{
5054 int rc;
5055
5056 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5057 (void) fill_cmd(c, TEST_UNIT_READY, h,
5058 NULL, 0, 0, lunaddr, TYPE_CMD);
5059 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5060 if (rc)
5061 return rc;
5062 /* no unmap needed here because no data xfer. */
5063
5064 /* Check if the unit is already ready. */
5065 if (c->err_info->CommandStatus == CMD_SUCCESS)
5066 return 0;
5067
5068 /*
5069 * The first command sent after reset will receive "unit attention" to
5070 * indicate that the LUN has been reset...this is actually what we're
5071 * looking for (but, success is good too).
5072 */
5073 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5074 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5075 (c->err_info->SenseInfo[2] == NO_SENSE ||
5076 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5077 return 0;
5078
5079 return 1;
5080}
5081
5082/*
5083 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5084 * returns zero when the unit is ready, and non-zero when giving up.
5085 */
5086static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5087 struct CommandList *c,
5088 unsigned char lunaddr[], int reply_queue)
edd16368 5089{
8919358e 5090 int rc;
edd16368
SC		 5091 int count = 0;
5092 int waittime = 1; /* seconds */
edd16368
SC		 5093
5094 /* Send test unit ready until device ready, or give up. */
b69324ff 5095 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5096
b69324ff
WS		 5097 /*
5098 * Wait for a bit. do this first, because if we send
edd16368
SC		 5099 * the TUR right away, the reset will just abort it.
5100 */
5101 msleep(1000 * waittime);
b69324ff
WS		 5102
5103 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5104 if (!rc)
5105 break;
edd16368
SC		 5106
5107 /* Increase wait time with each try, up to a point. */
5108 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5109 waittime *= 2;
edd16368 5110
b69324ff
WS		 5111 dev_warn(&h->pdev->dev,
5112 "waiting %d secs for device to become ready.\n",
5113 waittime);
5114 }
edd16368 5115
b69324ff
WS		 5116 return rc;
5117}
edd16368 5118
b69324ff
WS		 5119static int wait_for_device_to_become_ready(struct ctlr_info *h,
5120 unsigned char lunaddr[],
5121 int reply_queue)
5122{
5123 int first_queue;
5124 int last_queue;
5125 int rq;
5126 int rc = 0;
5127 struct CommandList *c;
5128
5129 c = cmd_alloc(h);
5130
5131 /*
5132 * If no specific reply queue was requested, then send the TUR
5133 * repeatedly, requesting a reply on each reply queue; otherwise execute
5134 * the loop exactly once using only the specified queue.
5135 */
5136 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5137 first_queue = 0;
5138 last_queue = h->nreply_queues - 1;
5139 } else {
5140 first_queue = reply_queue;
5141 last_queue = reply_queue;
5142 }
5143
5144 for (rq = first_queue; rq <= last_queue; rq++) {
5145 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5146 if (rc)
edd16368 5147 break;
edd16368
SC		 5148 }
5149
5150 if (rc)
5151 dev_warn(&h->pdev->dev, "giving up on device.\n");
5152 else
5153 dev_warn(&h->pdev->dev, "device is ready.\n");
5154
45fcb86e 5155 cmd_free(h, c);
edd16368
SC		 5156 return rc;
5157}
5158
5159/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5160 * complaining. Doing a host- or bus-reset can't do anything good here.
5161 */
5162static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5163{
5164 int rc;
5165 struct ctlr_info *h;
5166 struct hpsa_scsi_dev_t *dev;
2dc127bb 5167 char msg[48];
edd16368
SC		 5168
5169 /* find the controller to which the command to be aborted was sent */
5170 h = sdev_to_hba(scsicmd->device);
5171 if (h == NULL) /* paranoia */
5172 return FAILED;
e345893b
DB		 5173
5174 if (lockup_detected(h))
5175 return FAILED;
5176
edd16368
SC		 5177 dev = scsicmd->device->hostdata;
5178 if (!dev) {
d604f533 5179 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5180 return FAILED;
5181 }
25163bd5
WS		 5182
5183 /* if controller locked up, we can guarantee command won't complete */
5184 if (lockup_detected(h)) {
2dc127bb
DC		 5185 snprintf(msg, sizeof(msg),
5186 "cmd %d RESET FAILED, lockup detected",
5187 hpsa_get_cmd_index(scsicmd));
73153fe5 5188 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5189 return FAILED;
5190 }
5191
5192 /* this reset request might be the result of a lockup; check */
5193 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5194 snprintf(msg, sizeof(msg),
5195 "cmd %d RESET FAILED, new lockup detected",
5196 hpsa_get_cmd_index(scsicmd));
73153fe5 5197 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5198 return FAILED;
5199 }
5200
d604f533
WS		 5201 /* Do not attempt on controller */
5202 if (is_hba_lunid(dev->scsi3addr))
5203 return SUCCESS;
5204
25163bd5
WS		 5205 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5206
edd16368 5207 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5208 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5209 DEFAULT_REPLY_QUEUE);
2dc127bb
DC		 5210 snprintf(msg, sizeof(msg), "reset %s",
5211 rc == 0 ? "completed successfully" : "failed");
d604f533
WS		 5212 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5213 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5214}
5215
6cba3f19
SC		 5216static void swizzle_abort_tag(u8 *tag)
5217{
5218 u8 original_tag[8];
5219
5220 memcpy(original_tag, tag, 8);
5221 tag[0] = original_tag[3];
5222 tag[1] = original_tag[2];
5223 tag[2] = original_tag[1];
5224 tag[3] = original_tag[0];
5225 tag[4] = original_tag[7];
5226 tag[5] = original_tag[6];
5227 tag[6] = original_tag[5];
5228 tag[7] = original_tag[4];
5229}
5230
17eb87d2 5231static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5232 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5233{
2b08b3e9 5234 u64 tag;
17eb87d2
ST		 5235 if (c->cmd_type == CMD_IOACCEL1) {
5236 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5237 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5238 tag = le64_to_cpu(cm1->tag);
5239 *tagupper = cpu_to_le32(tag >> 32);
5240 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5241 return;
5242 }
5243 if (c->cmd_type == CMD_IOACCEL2) {
5244 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5245 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5246 /* upper tag not used in ioaccel2 mode */
5247 memset(tagupper, 0, sizeof(*tagupper));
5248 *taglower = cm2->Tag;
54b6e9e9 5249 return;
17eb87d2 5250 }
2b08b3e9
DB		 5251 tag = le64_to_cpu(c->Header.tag);
5252 *tagupper = cpu_to_le32(tag >> 32);
5253 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5254}
5255
75167d2c 5256static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5257 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5258{
5259 int rc = IO_OK;
5260 struct CommandList *c;
5261 struct ErrorInfo *ei;
2b08b3e9 5262 __le32 tagupper, taglower;
75167d2c 5263
45fcb86e 5264 c = cmd_alloc(h);
75167d2c 5265
a2dac136 5266 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5267 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5268 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5269 if (h->needs_abort_tags_swizzled)
6cba3f19 5270 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5271 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5272 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5273 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5274 __func__, tagupper, taglower);
75167d2c
SC		 5275 /* no unmap needed here because no data xfer. */
5276
5277 ei = c->err_info;
5278 switch (ei->CommandStatus) {
5279 case CMD_SUCCESS:
5280 break;
9437ac43
SC		 5281 case CMD_TMF_STATUS:
5282 rc = hpsa_evaluate_tmf_status(h, c);
5283 break;
75167d2c
SC		 5284 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5285 rc = -1;
5286 break;
5287 default:
5288 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5289 __func__, tagupper, taglower);
d1e8beac 5290 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5291 rc = -1;
5292 break;
5293 }
45fcb86e 5294 cmd_free(h, c);
dd0e19f3
ST		 5295 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5296 __func__, tagupper, taglower);
75167d2c
SC		 5297 return rc;
5298}
5299
8be986cc
SC		 5300static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5301 struct CommandList *command_to_abort, int reply_queue)
5302{
5303 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5304 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5305 struct io_accel2_cmd *c2a =
5306 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5307 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5308 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5309
5310 /*
5311 * We're overlaying struct hpsa_tmf_struct on top of something which
5312 * was allocated as a struct io_accel2_cmd, so we better be sure it
5313 * actually fits, and doesn't overrun the error info space.
5314 */
5315 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5316 sizeof(struct io_accel2_cmd));
5317 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5318 offsetof(struct hpsa_tmf_struct, error_len) +
5319 sizeof(ac->error_len));
5320
5321 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5322 c->scsi_cmd = SCSI_CMD_BUSY;
5323
8be986cc
SC		 5324 /* Adjust the DMA address to point to the accelerated command buffer */
5325 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5326 (c->cmdindex * sizeof(struct io_accel2_cmd));
5327 BUG_ON(c->busaddr & 0x0000007F);
5328
5329 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5330 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5331 ac->reply_queue = reply_queue;
5332 ac->tmf = IOACCEL2_TMF_ABORT;
5333 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5334 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5335 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5336 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5337 ac->error_ptr = cpu_to_le64(c->busaddr +
5338 offsetof(struct io_accel2_cmd, error_data));
5339 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5340}
5341
54b6e9e9
ST		 5342/* ioaccel2 path firmware cannot handle abort task requests.
5343 * Change abort requests to physical target reset, and send to the
5344 * address of the physical disk used for the ioaccel 2 command.
5345 * Return 0 on success (IO_OK)
5346 * -1 on failure
5347 */
5348
5349static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5350 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5351{
5352 int rc = IO_OK;
5353 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5354 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5355 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5356 unsigned char *psa = &phys_scsi3addr[0];
5357
5358 /* Get a pointer to the hpsa logical device. */
7fa3030c 5359 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5360 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5361 if (dev == NULL) {
5362 dev_warn(&h->pdev->dev,
5363 "Cannot abort: no device pointer for command.\n");
5364 return -1; /* not abortable */
5365 }
5366
2ba8bfc8
SC		 5367 if (h->raid_offload_debug > 0)
5368 dev_info(&h->pdev->dev,
0d96ef5f 5369 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5370 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5371 "Reset as abort",
2ba8bfc8
SC		 5372 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5373 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5374
54b6e9e9
ST		 5375 if (!dev->offload_enabled) {
5376 dev_warn(&h->pdev->dev,
5377 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5378 return -1; /* not abortable */
5379 }
5380
5381 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5382 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5383 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5384 return -1; /* not abortable */
5385 }
5386
5387 /* send the reset */
2ba8bfc8
SC		 5388 if (h->raid_offload_debug > 0)
5389 dev_info(&h->pdev->dev,
5390 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5391 psa[0], psa[1], psa[2], psa[3],
5392 psa[4], psa[5], psa[6], psa[7]);
d604f533 5393 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5394 if (rc != 0) {
5395 dev_warn(&h->pdev->dev,
5396 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5397 psa[0], psa[1], psa[2], psa[3],
5398 psa[4], psa[5], psa[6], psa[7]);
5399 return rc; /* failed to reset */
5400 }
5401
5402 /* wait for device to recover */
b69324ff 5403 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5404 dev_warn(&h->pdev->dev,
5405 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5406 psa[0], psa[1], psa[2], psa[3],
5407 psa[4], psa[5], psa[6], psa[7]);
5408 return -1; /* failed to recover */
5409 }
5410
5411 /* device recovered */
5412 dev_info(&h->pdev->dev,
5413 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5414 psa[0], psa[1], psa[2], psa[3],
5415 psa[4], psa[5], psa[6], psa[7]);
5416
5417 return rc; /* success */
5418}
5419
8be986cc
SC		 5420static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5421 struct CommandList *abort, int reply_queue)
5422{
5423 int rc = IO_OK;
5424 struct CommandList *c;
5425 __le32 taglower, tagupper;
5426 struct hpsa_scsi_dev_t *dev;
5427 struct io_accel2_cmd *c2;
5428
5429 dev = abort->scsi_cmd->device->hostdata;
5430 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5431 return -1;
5432
5433 c = cmd_alloc(h);
5434 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5435 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5436 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5437 hpsa_get_tag(h, abort, &taglower, &tagupper);
5438 dev_dbg(&h->pdev->dev,
5439 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5440 __func__, tagupper, taglower);
5441 /* no unmap needed here because no data xfer. */
5442
5443 dev_dbg(&h->pdev->dev,
5444 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5445 __func__, tagupper, taglower, c2->error_data.serv_response);
5446 switch (c2->error_data.serv_response) {
5447 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5448 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5449 rc = 0;
5450 break;
5451 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5452 case IOACCEL2_SERV_RESPONSE_FAILURE:
5453 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5454 rc = -1;
5455 break;
5456 default:
5457 dev_warn(&h->pdev->dev,
5458 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5459 __func__, tagupper, taglower,
5460 c2->error_data.serv_response);
5461 rc = -1;
5462 }
5463 cmd_free(h, c);
5464 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5465 tagupper, taglower);
5466 return rc;
5467}
5468
6cba3f19 5469static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5470 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5471{
8be986cc
SC		 5472 /*
5473 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5474 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5475 * but not all underlying firmware can handle abort TMF.
5476 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5477 */
8be986cc
SC		 5478 if (abort->cmd_type == CMD_IOACCEL2) {
5479 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5480 return hpsa_send_abort_ioaccel2(h, abort,
5481 reply_queue);
5482 else
5483 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5484 abort, reply_queue);
8be986cc 5485 }
9b5c48c2 5486 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5487}
54b6e9e9 5488
25163bd5
WS		 5489/* Find out which reply queue a command was meant to return on */
5490static int hpsa_extract_reply_queue(struct ctlr_info *h,
5491 struct CommandList *c)
5492{
5493 if (c->cmd_type == CMD_IOACCEL2)
5494 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5495 return c->Header.ReplyQueue;
6cba3f19
SC		 5496}
5497
9b5c48c2
SC		 5498/*
5499 * Limit concurrency of abort commands to prevent
5500 * over-subscription of commands
5501 */
5502static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5503{
5504#define ABORT_CMD_WAIT_MSECS 5000
5505 return !wait_event_timeout(h->abort_cmd_wait_queue,
5506 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5507 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5508}
5509
75167d2c
SC		 5510/* Send an abort for the specified command.
5511 * If the device and controller support it,
5512 * send a task abort request.
5513 */
5514static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5515{
5516
a58e7e53 5517 int rc;
75167d2c
SC		 5518 struct ctlr_info *h;
5519 struct hpsa_scsi_dev_t *dev;
5520 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5521 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5522 char msg[256]; /* For debug messaging. */
5523 int ml = 0;
2b08b3e9 5524 __le32 tagupper, taglower;
25163bd5
WS		 5525 int refcount, reply_queue;
5526
5527 if (sc == NULL)
5528 return FAILED;
75167d2c 5529
9b5c48c2
SC		 5530 if (sc->device == NULL)
5531 return FAILED;
5532
75167d2c
SC		 5533 /* Find the controller of the command to be aborted */
5534 h = sdev_to_hba(sc->device);
9b5c48c2 5535 if (h == NULL)
75167d2c
SC		 5536 return FAILED;
5537
25163bd5
WS		 5538 /* Find the device of the command to be aborted */
5539 dev = sc->device->hostdata;
5540 if (!dev) {
5541 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5542 msg);
e345893b 5543 return FAILED;
25163bd5
WS		 5544 }
5545
5546 /* If controller locked up, we can guarantee command won't complete */
5547 if (lockup_detected(h)) {
5548 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5549 "ABORT FAILED, lockup detected");
5550 return FAILED;
5551 }
5552
5553 /* This is a good time to check if controller lockup has occurred */
5554 if (detect_controller_lockup(h)) {
5555 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5556 "ABORT FAILED, new lockup detected");
5557 return FAILED;
5558 }
e345893b 5559
75167d2c
SC		 5560 /* Check that controller supports some kind of task abort */
5561 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5562 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5563 return FAILED;
5564
5565 memset(msg, 0, sizeof(msg));
4b761557 5566 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5567 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5568 sc->device->id, sc->device->lun,
4b761557 5569 "Aborting command", sc);
75167d2c 5570
75167d2c
SC		 5571 /* Get SCSI command to be aborted */
5572 abort = (struct CommandList *) sc->host_scribble;
5573 if (abort == NULL) {
281a7fd0
WS		 5574 /* This can happen if the command already completed. */
5575 return SUCCESS;
5576 }
5577 refcount = atomic_inc_return(&abort->refcount);
5578 if (refcount == 1) { /* Command is done already. */
5579 cmd_free(h, abort);
5580 return SUCCESS;
75167d2c 5581 }
9b5c48c2
SC		 5582
5583 /* Don't bother trying the abort if we know it won't work. */
5584 if (abort->cmd_type != CMD_IOACCEL2 &&
5585 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5586 cmd_free(h, abort);
5587 return FAILED;
5588 }
5589
a58e7e53
WS		 5590 /*
5591 * Check that we're aborting the right command.
5592 * It's possible the CommandList already completed and got re-used.
5593 */
5594 if (abort->scsi_cmd != sc) {
5595 cmd_free(h, abort);
5596 return SUCCESS;
5597 }
5598
5599 abort->abort_pending = true;
17eb87d2 5600 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5601 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5602 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5603 as = abort->scsi_cmd;
75167d2c 5604 if (as != NULL)
4b761557
RE		 5605 ml += sprintf(msg+ml,
5606 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5607 as->cmd_len, as->cmnd[0], as->cmnd[1],
5608 as->serial_number);
5609 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5610 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5611
75167d2c
SC		 5612 /*
5613 * Command is in flight, or possibly already completed
5614 * by the firmware (but not to the scsi mid layer) but we can't
5615 * distinguish which. Send the abort down.
5616 */
9b5c48c2
SC		 5617 if (wait_for_available_abort_cmd(h)) {
5618 dev_warn(&h->pdev->dev,
4b761557
RE		 5619 "%s FAILED, timeout waiting for an abort command to become available.\n",
5620 msg);
9b5c48c2
SC		 5621 cmd_free(h, abort);
5622 return FAILED;
5623 }
25163bd5 5624 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5625 atomic_inc(&h->abort_cmds_available);
5626 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5627 if (rc != 0) {
4b761557 5628 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5629 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5630 "FAILED to abort command");
281a7fd0 5631 cmd_free(h, abort);
75167d2c
SC		 5632 return FAILED;
5633 }
4b761557 5634 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5635 wait_event(h->event_sync_wait_queue,
a58e7e53 5636 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5637 cmd_free(h, abort);
a58e7e53 5638 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5639}
5640
73153fe5
WS		 5641/*
5642 * For operations with an associated SCSI command, a command block is allocated
5643 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5644 * block request tag as an index into a table of entries. cmd_tagged_free() is
5645 * the complement, although cmd_free() may be called instead.
5646 */
5647static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5648 struct scsi_cmnd *scmd)
5649{
5650 int idx = hpsa_get_cmd_index(scmd);
5651 struct CommandList *c = h->cmd_pool + idx;
5652
5653 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5654 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5655 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5656 /* The index value comes from the block layer, so if it's out of
5657 * bounds, it's probably not our bug.
5658 */
5659 BUG();
5660 }
5661
5662 atomic_inc(&c->refcount);
5663 if (unlikely(!hpsa_is_cmd_idle(c))) {
5664 /*
5665 * We expect that the SCSI layer will hand us a unique tag
5666 * value. Thus, there should never be a collision here between
5667 * two requests...because if the selected command isn't idle
5668 * then someone is going to be very disappointed.
5669 */
5670 dev_err(&h->pdev->dev,
5671 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5672 idx);
5673 if (c->scsi_cmd != NULL)
5674 scsi_print_command(c->scsi_cmd);
5675 scsi_print_command(scmd);
5676 }
5677
5678 hpsa_cmd_partial_init(h, idx, c);
5679 return c;
5680}
5681
5682static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5683{
5684 /*
5685 * Release our reference to the block. We don't need to do anything
5686 * else to free it, because it is accessed by index. (There's no point
5687 * in checking the result of the decrement, since we cannot guarantee
5688 * that there isn't a concurrent abort which is also accessing it.)
5689 */
5690 (void)atomic_dec(&c->refcount);
5691}
5692
edd16368
SC		 5693/*
5694 * For operations that cannot sleep, a command block is allocated at init,
5695 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5696 * which ones are free or in use. Lock must be held when calling this.
5697 * cmd_free() is the complement.
bf43caf3
RE		 5698 * This function never gives up and returns NULL. If it hangs,
5699 * another thread must call cmd_free() to free some tags.
edd16368 5700 */
281a7fd0 5701
edd16368
SC		 5702static struct CommandList *cmd_alloc(struct ctlr_info *h)
5703{
5704 struct CommandList *c;
360c73bd 5705 int refcount, i;
73153fe5 5706 int offset = 0;
4c413128 5707
33811026
RE		 5708 /*
5709 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5710 * multiple threads could get in here, and one thread could
5711 * be scanning through the list of bits looking for a free
5712 * one, but the free ones are always behind him, and other
5713 * threads sneak in behind him and eat them before he can
5714 * get to them, so that while there is always a free one, a
5715 * very unlucky thread might be starved anyway, never able to
5716 * beat the other threads. In reality, this happens so
5717 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5718 *
5719 * Note that we start allocating commands before the SCSI host structure
5720 * is initialized. Since the search starts at bit zero, this
5721 * all works, since we have at least one command structure available;
5722 * however, it means that the structures with the low indexes have to be
5723 * reserved for driver-initiated requests, while requests from the block
5724 * layer will use the higher indexes.
4c413128 5725 */
edd16368 5726
281a7fd0 5727 for (;;) {
73153fe5
WS		 5728 i = find_next_zero_bit(h->cmd_pool_bits,
5729 HPSA_NRESERVED_CMDS,
5730 offset);
5731 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5732 offset = 0;
5733 continue;
5734 }
5735 c = h->cmd_pool + i;
5736 refcount = atomic_inc_return(&c->refcount);
5737 if (unlikely(refcount > 1)) {
5738 cmd_free(h, c); /* already in use */
73153fe5 5739 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5740 continue;
5741 }
5742 set_bit(i & (BITS_PER_LONG - 1),
5743 h->cmd_pool_bits + (i / BITS_PER_LONG));
5744 break; /* it's ours now. */
5745 }
360c73bd 5746 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5747 return c;
5748}
5749
73153fe5
WS		 5750/*
5751 * This is the complementary operation to cmd_alloc(). Note, however, in some
5752 * corner cases it may also be used to free blocks allocated by
5753 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5754 * the clear-bit is harmless.
5755 */
edd16368
SC		 5756static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5757{
281a7fd0
WS		 5758 if (atomic_dec_and_test(&c->refcount)) {
5759 int i;
edd16368 5760
281a7fd0
WS		 5761 i = c - h->cmd_pool;
5762 clear_bit(i & (BITS_PER_LONG - 1),
5763 h->cmd_pool_bits + (i / BITS_PER_LONG));
5764 }
edd16368
SC		 5765}
5766
edd16368
SC		 5767#ifdef CONFIG_COMPAT
5768
42a91641
DB		 5769static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5770 void __user *arg)
edd16368
SC		 5771{
5772 IOCTL32_Command_struct __user *arg32 =
5773 (IOCTL32_Command_struct __user *) arg;
5774 IOCTL_Command_struct arg64;
5775 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5776 int err;
5777 u32 cp;
5778
938abd84 5779 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5780 err = 0;
5781 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5782 sizeof(arg64.LUN_info));
5783 err |= copy_from_user(&arg64.Request, &arg32->Request,
5784 sizeof(arg64.Request));
5785 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5786 sizeof(arg64.error_info));
5787 err |= get_user(arg64.buf_size, &arg32->buf_size);
5788 err |= get_user(cp, &arg32->buf);
5789 arg64.buf = compat_ptr(cp);
5790 err |= copy_to_user(p, &arg64, sizeof(arg64));
5791
5792 if (err)
5793 return -EFAULT;
5794
42a91641 5795 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5796 if (err)
5797 return err;
5798 err |= copy_in_user(&arg32->error_info, &p->error_info,
5799 sizeof(arg32->error_info));
5800 if (err)
5801 return -EFAULT;
5802 return err;
5803}
5804
5805static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5806 int cmd, void __user *arg)
edd16368
SC		 5807{
5808 BIG_IOCTL32_Command_struct __user *arg32 =
5809 (BIG_IOCTL32_Command_struct __user *) arg;
5810 BIG_IOCTL_Command_struct arg64;
5811 BIG_IOCTL_Command_struct __user *p =
5812 compat_alloc_user_space(sizeof(arg64));
5813 int err;
5814 u32 cp;
5815
938abd84 5816 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5817 err = 0;
5818 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5819 sizeof(arg64.LUN_info));
5820 err |= copy_from_user(&arg64.Request, &arg32->Request,
5821 sizeof(arg64.Request));
5822 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5823 sizeof(arg64.error_info));
5824 err |= get_user(arg64.buf_size, &arg32->buf_size);
5825 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5826 err |= get_user(cp, &arg32->buf);
5827 arg64.buf = compat_ptr(cp);
5828 err |= copy_to_user(p, &arg64, sizeof(arg64));
5829
5830 if (err)
5831 return -EFAULT;
5832
42a91641 5833 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5834 if (err)
5835 return err;
5836 err |= copy_in_user(&arg32->error_info, &p->error_info,
5837 sizeof(arg32->error_info));
5838 if (err)
5839 return -EFAULT;
5840 return err;
5841}
71fe75a7 5842
42a91641 5843static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5844{
5845 switch (cmd) {
5846 case CCISS_GETPCIINFO:
5847 case CCISS_GETINTINFO:
5848 case CCISS_SETINTINFO:
5849 case CCISS_GETNODENAME:
5850 case CCISS_SETNODENAME:
5851 case CCISS_GETHEARTBEAT:
5852 case CCISS_GETBUSTYPES:
5853 case CCISS_GETFIRMVER:
5854 case CCISS_GETDRIVVER:
5855 case CCISS_REVALIDVOLS:
5856 case CCISS_DEREGDISK:
5857 case CCISS_REGNEWDISK:
5858 case CCISS_REGNEWD:
5859 case CCISS_RESCANDISK:
5860 case CCISS_GETLUNINFO:
5861 return hpsa_ioctl(dev, cmd, arg);
5862
5863 case CCISS_PASSTHRU32:
5864 return hpsa_ioctl32_passthru(dev, cmd, arg);
5865 case CCISS_BIG_PASSTHRU32:
5866 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5867
5868 default:
5869 return -ENOIOCTLCMD;
5870 }
5871}
edd16368
SC		 5872#endif
5873
5874static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5875{
5876 struct hpsa_pci_info pciinfo;
5877
5878 if (!argp)
5879 return -EINVAL;
5880 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5881 pciinfo.bus = h->pdev->bus->number;
5882 pciinfo.dev_fn = h->pdev->devfn;
5883 pciinfo.board_id = h->board_id;
5884 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5885 return -EFAULT;
5886 return 0;
5887}
5888
5889static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5890{
5891 DriverVer_type DriverVer;
5892 unsigned char vmaj, vmin, vsubmin;
5893 int rc;
5894
5895 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5896 &vmaj, &vmin, &vsubmin);
5897 if (rc != 3) {
5898 dev_info(&h->pdev->dev, "driver version string '%s' "
5899 "unrecognized.", HPSA_DRIVER_VERSION);
5900 vmaj = 0;
5901 vmin = 0;
5902 vsubmin = 0;
5903 }
5904 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5905 if (!argp)
5906 return -EINVAL;
5907 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5908 return -EFAULT;
5909 return 0;
5910}
5911
5912static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5913{
5914 IOCTL_Command_struct iocommand;
5915 struct CommandList *c;
5916 char *buff = NULL;
50a0decf 5917 u64 temp64;
c1f63c8f 5918 int rc = 0;
edd16368
SC		 5919
5920 if (!argp)
5921 return -EINVAL;
5922 if (!capable(CAP_SYS_RAWIO))
5923 return -EPERM;
5924 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5925 return -EFAULT;
5926 if ((iocommand.buf_size < 1) &&
5927 (iocommand.Request.Type.Direction != XFER_NONE)) {
5928 return -EINVAL;
5929 }
5930 if (iocommand.buf_size > 0) {
5931 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5932 if (buff == NULL)
2dd02d74 5933 return -ENOMEM;
9233fb10 5934 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5935 /* Copy the data into the buffer we created */
5936 if (copy_from_user(buff, iocommand.buf,
5937 iocommand.buf_size)) {
c1f63c8f
SC		 5938 rc = -EFAULT;
5939 goto out_kfree;
b03a7771
SC		 5940 }
5941 } else {
5942 memset(buff, 0, iocommand.buf_size);
edd16368 5943 }
b03a7771 5944 }
45fcb86e 5945 c = cmd_alloc(h);
bf43caf3 5946
edd16368
SC		 5947 /* Fill in the command type */
5948 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5949 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5950 /* Fill in Command Header */
5951 c->Header.ReplyQueue = 0; /* unused in simple mode */
5952 if (iocommand.buf_size > 0) { /* buffer to fill */
5953 c->Header.SGList = 1;
50a0decf 5954 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5955 } else { /* no buffers to fill */
5956 c->Header.SGList = 0;
50a0decf 5957 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5958 }
5959 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5960
5961 /* Fill in Request block */
5962 memcpy(&c->Request, &iocommand.Request,
5963 sizeof(c->Request));
5964
5965 /* Fill in the scatter gather information */
5966 if (iocommand.buf_size > 0) {
50a0decf 5967 temp64 = pci_map_single(h->pdev, buff,
edd16368 5968 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5969 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5970 c->SG[0].Addr = cpu_to_le64(0);
5971 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5972 rc = -ENOMEM;
5973 goto out;
5974 }
50a0decf
SC		 5975 c->SG[0].Addr = cpu_to_le64(temp64);
5976 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5977 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5978 }
25163bd5 5979 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5980 if (iocommand.buf_size > 0)
5981 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5982 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5983 if (rc) {
5984 rc = -EIO;
5985 goto out;
5986 }
edd16368
SC		 5987
5988 /* Copy the error information out */
5989 memcpy(&iocommand.error_info, c->err_info,
5990 sizeof(iocommand.error_info));
5991 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5992 rc = -EFAULT;
5993 goto out;
edd16368 5994 }
9233fb10 5995 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5996 iocommand.buf_size > 0) {
edd16368
SC		 5997 /* Copy the data out of the buffer we created */
5998 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5999 rc = -EFAULT;
6000 goto out;
edd16368
SC		 6001 }
6002 }
c1f63c8f 6003out:
45fcb86e 6004 cmd_free(h, c);
c1f63c8f
SC		 6005out_kfree:
6006 kfree(buff);
6007 return rc;
edd16368
SC		 6008}
6009
6010static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6011{
6012 BIG_IOCTL_Command_struct *ioc;
6013 struct CommandList *c;
6014 unsigned char **buff = NULL;
6015 int *buff_size = NULL;
50a0decf 6016 u64 temp64;
edd16368
SC		 6017 BYTE sg_used = 0;
6018 int status = 0;
01a02ffc
SC		 6019 u32 left;
6020 u32 sz;
edd16368
SC		 6021 BYTE __user *data_ptr;
6022
6023 if (!argp)
6024 return -EINVAL;
6025 if (!capable(CAP_SYS_RAWIO))
6026 return -EPERM;
6027 ioc = (BIG_IOCTL_Command_struct *)
6028 kmalloc(sizeof(*ioc), GFP_KERNEL);
6029 if (!ioc) {
6030 status = -ENOMEM;
6031 goto cleanup1;
6032 }
6033 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6034 status = -EFAULT;
6035 goto cleanup1;
6036 }
6037 if ((ioc->buf_size < 1) &&
6038 (ioc->Request.Type.Direction != XFER_NONE)) {
6039 status = -EINVAL;
6040 goto cleanup1;
6041 }
6042 /* Check kmalloc limits using all SGs */
6043 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6044 status = -EINVAL;
6045 goto cleanup1;
6046 }
d66ae08b 6047 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6048 status = -EINVAL;
6049 goto cleanup1;
6050 }
d66ae08b 6051 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6052 if (!buff) {
6053 status = -ENOMEM;
6054 goto cleanup1;
6055 }
d66ae08b 6056 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6057 if (!buff_size) {
6058 status = -ENOMEM;
6059 goto cleanup1;
6060 }
6061 left = ioc->buf_size;
6062 data_ptr = ioc->buf;
6063 while (left) {
6064 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6065 buff_size[sg_used] = sz;
6066 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6067 if (buff[sg_used] == NULL) {
6068 status = -ENOMEM;
6069 goto cleanup1;
6070 }
9233fb10 6071 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6072 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6073 status = -EFAULT;
edd16368
SC		 6074 goto cleanup1;
6075 }
6076 } else
6077 memset(buff[sg_used], 0, sz);
6078 left -= sz;
6079 data_ptr += sz;
6080 sg_used++;
6081 }
45fcb86e 6082 c = cmd_alloc(h);
bf43caf3 6083
edd16368 6084 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6085 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6086 c->Header.ReplyQueue = 0;
50a0decf
SC		 6087 c->Header.SGList = (u8) sg_used;
6088 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6089 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6090 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6091 if (ioc->buf_size > 0) {
6092 int i;
6093 for (i = 0; i < sg_used; i++) {
50a0decf 6094 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6095 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6096 if (dma_mapping_error(&h->pdev->dev,
6097 (dma_addr_t) temp64)) {
6098 c->SG[i].Addr = cpu_to_le64(0);
6099 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6100 hpsa_pci_unmap(h->pdev, c, i,
6101 PCI_DMA_BIDIRECTIONAL);
6102 status = -ENOMEM;
e2d4a1f6 6103 goto cleanup0;
bcc48ffa 6104 }
50a0decf
SC		 6105 c->SG[i].Addr = cpu_to_le64(temp64);
6106 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6107 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6108 }
50a0decf 6109 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6110 }
25163bd5 6111 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6112 if (sg_used)
6113 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6114 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6115 if (status) {
6116 status = -EIO;
6117 goto cleanup0;
6118 }
6119
edd16368
SC		 6120 /* Copy the error information out */
6121 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6122 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6123 status = -EFAULT;
e2d4a1f6 6124 goto cleanup0;
edd16368 6125 }
9233fb10 6126 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6127 int i;
6128
edd16368
SC		 6129 /* Copy the data out of the buffer we created */
6130 BYTE __user *ptr = ioc->buf;
6131 for (i = 0; i < sg_used; i++) {
6132 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6133 status = -EFAULT;
e2d4a1f6 6134 goto cleanup0;
edd16368
SC		 6135 }
6136 ptr += buff_size[i];
6137 }
6138 }
edd16368 6139 status = 0;
e2d4a1f6 6140cleanup0:
45fcb86e 6141 cmd_free(h, c);
edd16368
SC		 6142cleanup1:
6143 if (buff) {
2b08b3e9
DB		 6144 int i;
6145
edd16368
SC		 6146 for (i = 0; i < sg_used; i++)
6147 kfree(buff[i]);
6148 kfree(buff);
6149 }
6150 kfree(buff_size);
6151 kfree(ioc);
6152 return status;
6153}
6154
6155static void check_ioctl_unit_attention(struct ctlr_info *h,
6156 struct CommandList *c)
6157{
6158 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6159 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6160 (void) check_for_unit_attention(h, c);
6161}
0390f0c0 6162
edd16368
SC		 6163/*
6164 * ioctl
6165 */
42a91641 6166static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6167{
6168 struct ctlr_info *h;
6169 void __user *argp = (void __user *)arg;
0390f0c0 6170 int rc;
edd16368
SC		 6171
6172 h = sdev_to_hba(dev);
6173
6174 switch (cmd) {
6175 case CCISS_DEREGDISK:
6176 case CCISS_REGNEWDISK:
6177 case CCISS_REGNEWD:
a08a8471 6178 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6179 return 0;
6180 case CCISS_GETPCIINFO:
6181 return hpsa_getpciinfo_ioctl(h, argp);
6182 case CCISS_GETDRIVVER:
6183 return hpsa_getdrivver_ioctl(h, argp);
6184 case CCISS_PASSTHRU:
34f0c627 6185 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6186 return -EAGAIN;
6187 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6188 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6189 return rc;
edd16368 6190 case CCISS_BIG_PASSTHRU:
34f0c627 6191 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6192 return -EAGAIN;
6193 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6194 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6195 return rc;
edd16368
SC		 6196 default:
6197 return -ENOTTY;
6198 }
6199}
6200
bf43caf3 6201static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6202 u8 reset_type)
64670ac8
SC		 6203{
6204 struct CommandList *c;
6205
6206 c = cmd_alloc(h);
bf43caf3 6207
a2dac136
SC		 6208 /* fill_cmd can't fail here, no data buffer to map */
6209 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6210 RAID_CTLR_LUNID, TYPE_MSG);
6211 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6212 c->waiting = NULL;
6213 enqueue_cmd_and_start_io(h, c);
6214 /* Don't wait for completion, the reset won't complete. Don't free
6215 * the command either. This is the last command we will send before
6216 * re-initializing everything, so it doesn't matter and won't leak.
6217 */
bf43caf3 6218 return;
64670ac8
SC		 6219}
6220
a2dac136 6221static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6222 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6223 int cmd_type)
6224{
6225 int pci_dir = XFER_NONE;
9b5c48c2 6226 u64 tag; /* for commands to be aborted */
edd16368
SC		 6227
6228 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6229 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6230 c->Header.ReplyQueue = 0;
6231 if (buff != NULL && size > 0) {
6232 c->Header.SGList = 1;
50a0decf 6233 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6234 } else {
6235 c->Header.SGList = 0;
50a0decf 6236 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6237 }
edd16368
SC		 6238 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6239
edd16368
SC		 6240 if (cmd_type == TYPE_CMD) {
6241 switch (cmd) {
6242 case HPSA_INQUIRY:
6243 /* are we trying to read a vital product page */
b7bb24eb 6244 if (page_code & VPD_PAGE) {
edd16368 6245 c->Request.CDB[1] = 0x01;
b7bb24eb 6246 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6247 }
6248 c->Request.CDBLen = 6;
a505b86f
SC		 6249 c->Request.type_attr_dir =
6250 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6251 c->Request.Timeout = 0;
6252 c->Request.CDB[0] = HPSA_INQUIRY;
6253 c->Request.CDB[4] = size & 0xFF;
6254 break;
6255 case HPSA_REPORT_LOG:
6256 case HPSA_REPORT_PHYS:
6257 /* Talking to controller so It's a physical command
6258 mode = 00 target = 0. Nothing to write.
6259 */
6260 c->Request.CDBLen = 12;
a505b86f
SC		 6261 c->Request.type_attr_dir =
6262 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6263 c->Request.Timeout = 0;
6264 c->Request.CDB[0] = cmd;
6265 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6266 c->Request.CDB[7] = (size >> 16) & 0xFF;
6267 c->Request.CDB[8] = (size >> 8) & 0xFF;
6268 c->Request.CDB[9] = size & 0xFF;
6269 break;
edd16368
SC		 6270 case HPSA_CACHE_FLUSH:
6271 c->Request.CDBLen = 12;
a505b86f
SC		 6272 c->Request.type_attr_dir =
6273 TYPE_ATTR_DIR(cmd_type,
6274 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6275 c->Request.Timeout = 0;
6276 c->Request.CDB[0] = BMIC_WRITE;
6277 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6278 c->Request.CDB[7] = (size >> 8) & 0xFF;
6279 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6280 break;
6281 case TEST_UNIT_READY:
6282 c->Request.CDBLen = 6;
a505b86f
SC		 6283 c->Request.type_attr_dir =
6284 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6285 c->Request.Timeout = 0;
6286 break;
283b4a9b
SC		 6287 case HPSA_GET_RAID_MAP:
6288 c->Request.CDBLen = 12;
a505b86f
SC		 6289 c->Request.type_attr_dir =
6290 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6291 c->Request.Timeout = 0;
6292 c->Request.CDB[0] = HPSA_CISS_READ;
6293 c->Request.CDB[1] = cmd;
6294 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6295 c->Request.CDB[7] = (size >> 16) & 0xFF;
6296 c->Request.CDB[8] = (size >> 8) & 0xFF;
6297 c->Request.CDB[9] = size & 0xFF;
6298 break;
316b221a
SC		 6299 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6300 c->Request.CDBLen = 10;
a505b86f
SC		 6301 c->Request.type_attr_dir =
6302 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6303 c->Request.Timeout = 0;
6304 c->Request.CDB[0] = BMIC_READ;
6305 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6306 c->Request.CDB[7] = (size >> 16) & 0xFF;
6307 c->Request.CDB[8] = (size >> 8) & 0xFF;
6308 break;
03383736
DB		 6309 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6310 c->Request.CDBLen = 10;
6311 c->Request.type_attr_dir =
6312 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6313 c->Request.Timeout = 0;
6314 c->Request.CDB[0] = BMIC_READ;
6315 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6316 c->Request.CDB[7] = (size >> 16) & 0xFF;
6317 c->Request.CDB[8] = (size >> 8) & 0XFF;
6318 break;
edd16368
SC		 6319 default:
6320 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6321 BUG();
a2dac136 6322 return -1;
edd16368
SC		 6323 }
6324 } else if (cmd_type == TYPE_MSG) {
6325 switch (cmd) {
6326
6327 case HPSA_DEVICE_RESET_MSG:
6328 c->Request.CDBLen = 16;
a505b86f
SC		 6329 c->Request.type_attr_dir =
6330 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6331 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6332 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6333 c->Request.CDB[0] = cmd;
21e89afd 6334 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6335 /* If bytes 4-7 are zero, it means reset the */
6336 /* LunID device */
6337 c->Request.CDB[4] = 0x00;
6338 c->Request.CDB[5] = 0x00;
6339 c->Request.CDB[6] = 0x00;
6340 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6341 break;
6342 case HPSA_ABORT_MSG:
9b5c48c2 6343 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6344 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6345 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6346 tag, c->Header.tag);
75167d2c 6347 c->Request.CDBLen = 16;
a505b86f
SC		 6348 c->Request.type_attr_dir =
6349 TYPE_ATTR_DIR(cmd_type,
6350 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6351 c->Request.Timeout = 0; /* Don't time out */
6352 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6353 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6354 c->Request.CDB[2] = 0x00; /* reserved */
6355 c->Request.CDB[3] = 0x00; /* reserved */
6356 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6357 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6358 c->Request.CDB[12] = 0x00; /* reserved */
6359 c->Request.CDB[13] = 0x00; /* reserved */
6360 c->Request.CDB[14] = 0x00; /* reserved */
6361 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6362 break;
edd16368
SC		 6363 default:
6364 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6365 cmd);
6366 BUG();
6367 }
6368 } else {
6369 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6370 BUG();
6371 }
6372
a505b86f 6373 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6374 case XFER_READ:
6375 pci_dir = PCI_DMA_FROMDEVICE;
6376 break;
6377 case XFER_WRITE:
6378 pci_dir = PCI_DMA_TODEVICE;
6379 break;
6380 case XFER_NONE:
6381 pci_dir = PCI_DMA_NONE;
6382 break;
6383 default:
6384 pci_dir = PCI_DMA_BIDIRECTIONAL;
6385 }
a2dac136
SC		 6386 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6387 return -1;
6388 return 0;
edd16368
SC		 6389}
6390
6391/*
6392 * Map (physical) PCI mem into (virtual) kernel space
6393 */
6394static void __iomem *remap_pci_mem(ulong base, ulong size)
6395{
6396 ulong page_base = ((ulong) base) & PAGE_MASK;
6397 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6398 void __iomem *page_remapped = ioremap_nocache(page_base,
6399 page_offs + size);
edd16368
SC		 6400
6401 return page_remapped ? (page_remapped + page_offs) : NULL;
6402}
6403
254f796b 6404static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6405{
254f796b 6406 return h->access.command_completed(h, q);
edd16368
SC		 6407}
6408
900c5440 6409static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6410{
6411 return h->access.intr_pending(h);
6412}
6413
6414static inline long interrupt_not_for_us(struct ctlr_info *h)
6415{
10f66018
SC		 6416 return (h->access.intr_pending(h) == 0) ||
6417 (h->interrupts_enabled == 0);
edd16368
SC		 6418}
6419
01a02ffc
SC		 6420static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6421 u32 raw_tag)
edd16368
SC		 6422{
6423 if (unlikely(tag_index >= h->nr_cmds)) {
6424 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6425 return 1;
6426 }
6427 return 0;
6428}
6429
5a3d16f5 6430static inline void finish_cmd(struct CommandList *c)
edd16368 6431{
e85c5974 6432 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6433 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6434 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6435 complete_scsi_command(c);
8be986cc 6436 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6437 complete(c->waiting);
a104c99f
SC		 6438}
6439
303932fd 6440/* process completion of an indexed ("direct lookup") command */
1d94f94d 6441static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6442 u32 raw_tag)
6443{
6444 u32 tag_index;
6445 struct CommandList *c;
6446
f2405db8 6447 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6448 if (!bad_tag(h, tag_index, raw_tag)) {
6449 c = h->cmd_pool + tag_index;
6450 finish_cmd(c);
6451 }
303932fd
DB		 6452}
6453
64670ac8
SC		 6454/* Some controllers, like p400, will give us one interrupt
6455 * after a soft reset, even if we turned interrupts off.
6456 * Only need to check for this in the hpsa_xxx_discard_completions
6457 * functions.
6458 */
6459static int ignore_bogus_interrupt(struct ctlr_info *h)
6460{
6461 if (likely(!reset_devices))
6462 return 0;
6463
6464 if (likely(h->interrupts_enabled))
6465 return 0;
6466
6467 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6468 "(known firmware bug.) Ignoring.\n");
6469
6470 return 1;
6471}
6472
254f796b
MG		 6473/*
6474 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6475 * Relies on (h-q[x] == x) being true for x such that
6476 * 0 <= x < MAX_REPLY_QUEUES.
6477 */
6478static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6479{
254f796b
MG		 6480 return container_of((queue - *queue), struct ctlr_info, q[0]);
6481}
6482
6483static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6484{
6485 struct ctlr_info *h = queue_to_hba(queue);
6486 u8 q = *(u8 *) queue;
64670ac8
SC		 6487 u32 raw_tag;
6488
6489 if (ignore_bogus_interrupt(h))
6490 return IRQ_NONE;
6491
6492 if (interrupt_not_for_us(h))
6493 return IRQ_NONE;
a0c12413 6494 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6495 while (interrupt_pending(h)) {
254f796b 6496 raw_tag = get_next_completion(h, q);
64670ac8 6497 while (raw_tag != FIFO_EMPTY)
254f796b 6498 raw_tag = next_command(h, q);
64670ac8 6499 }
64670ac8
SC		 6500 return IRQ_HANDLED;
6501}
6502
254f796b 6503static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6504{
254f796b 6505 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6506 u32 raw_tag;
254f796b 6507 u8 q = *(u8 *) queue;
64670ac8
SC		 6508
6509 if (ignore_bogus_interrupt(h))
6510 return IRQ_NONE;
6511
a0c12413 6512 h->last_intr_timestamp = get_jiffies_64();
254f796b 6513 raw_tag = get_next_completion(h, q);
64670ac8 6514 while (raw_tag != FIFO_EMPTY)
254f796b 6515 raw_tag = next_command(h, q);
64670ac8
SC		 6516 return IRQ_HANDLED;
6517}
6518
254f796b 6519static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6520{
254f796b 6521 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6522 u32 raw_tag;
254f796b 6523 u8 q = *(u8 *) queue;
edd16368
SC		 6524
6525 if (interrupt_not_for_us(h))
6526 return IRQ_NONE;
a0c12413 6527 h->last_intr_timestamp = get_jiffies_64();
10f66018 6528 while (interrupt_pending(h)) {
254f796b 6529 raw_tag = get_next_completion(h, q);
10f66018 6530 while (raw_tag != FIFO_EMPTY) {
f2405db8 6531 process_indexed_cmd(h, raw_tag);
254f796b 6532 raw_tag = next_command(h, q);
10f66018
SC		 6533 }
6534 }
10f66018
SC		 6535 return IRQ_HANDLED;
6536}
6537
254f796b 6538static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6539{
254f796b 6540 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6541 u32 raw_tag;
254f796b 6542 u8 q = *(u8 *) queue;
10f66018 6543
a0c12413 6544 h->last_intr_timestamp = get_jiffies_64();
254f796b 6545 raw_tag = get_next_completion(h, q);
303932fd 6546 while (raw_tag != FIFO_EMPTY) {
f2405db8 6547 process_indexed_cmd(h, raw_tag);
254f796b 6548 raw_tag = next_command(h, q);
edd16368 6549 }
edd16368
SC		 6550 return IRQ_HANDLED;
6551}
6552
a9a3a273
SC		 6553/* Send a message CDB to the firmware. Careful, this only works
6554 * in simple mode, not performant mode due to the tag lookup.
6555 * We only ever use this immediately after a controller reset.
6556 */
6f039790
GKH		 6557static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6558 unsigned char type)
edd16368
SC		 6559{
6560 struct Command {
6561 struct CommandListHeader CommandHeader;
6562 struct RequestBlock Request;
6563 struct ErrDescriptor ErrorDescriptor;
6564 };
6565 struct Command *cmd;
6566 static const size_t cmd_sz = sizeof(*cmd) +
6567 sizeof(cmd->ErrorDescriptor);
6568 dma_addr_t paddr64;
2b08b3e9
DB		 6569 __le32 paddr32;
6570 u32 tag;
edd16368
SC		 6571 void __iomem *vaddr;
6572 int i, err;
6573
6574 vaddr = pci_ioremap_bar(pdev, 0);
6575 if (vaddr == NULL)
6576 return -ENOMEM;
6577
6578 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6579 * CCISS commands, so they must be allocated from the lower 4GiB of
6580 * memory.
6581 */
6582 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6583 if (err) {
6584 iounmap(vaddr);
1eaec8f3 6585 return err;
edd16368
SC		 6586 }
6587
6588 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6589 if (cmd == NULL) {
6590 iounmap(vaddr);
6591 return -ENOMEM;
6592 }
6593
6594 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6595 * although there's no guarantee, we assume that the address is at
6596 * least 4-byte aligned (most likely, it's page-aligned).
6597 */
2b08b3e9 6598 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6599
6600 cmd->CommandHeader.ReplyQueue = 0;
6601 cmd->CommandHeader.SGList = 0;
50a0decf 6602 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6603 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6604 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6605
6606 cmd->Request.CDBLen = 16;
a505b86f
SC		 6607 cmd->Request.type_attr_dir =
6608 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6609 cmd->Request.Timeout = 0; /* Don't time out */
6610 cmd->Request.CDB[0] = opcode;
6611 cmd->Request.CDB[1] = type;
6612 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6613 cmd->ErrorDescriptor.Addr =
2b08b3e9 6614 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6615 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6616
2b08b3e9 6617 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6618
6619 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6620 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6621 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6622 break;
6623 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6624 }
6625
6626 iounmap(vaddr);
6627
6628 /* we leak the DMA buffer here ... no choice since the controller could
6629 * still complete the command.
6630 */
6631 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6632 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6633 opcode, type);
6634 return -ETIMEDOUT;
6635 }
6636
6637 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6638
6639 if (tag & HPSA_ERROR_BIT) {
6640 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6641 opcode, type);
6642 return -EIO;
6643 }
6644
6645 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6646 opcode, type);
6647 return 0;
6648}
6649
edd16368
SC		 6650#define hpsa_noop(p) hpsa_message(p, 3, 0)
6651
1df8552a 6652static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6653 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6654{
1df8552a
SC		 6655
6656 if (use_doorbell) {
6657 /* For everything after the P600, the PCI power state method
6658 * of resetting the controller doesn't work, so we have this
6659 * other way using the doorbell register.
6660 */
6661 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6662 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6663
00701a96 6664 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6665 * doorbell reset and before any attempt to talk to the board
6666 * at all to ensure that this actually works and doesn't fall
6667 * over in some weird corner cases.
6668 */
00701a96 6669 msleep(10000);
1df8552a
SC		 6670 } else { /* Try to do it the PCI power state way */
6671
6672 /* Quoting from the Open CISS Specification: "The Power
6673 * Management Control/Status Register (CSR) controls the power
6674 * state of the device. The normal operating state is D0,
6675 * CSR=00h. The software off state is D3, CSR=03h. To reset
6676 * the controller, place the interface device in D3 then to D0,
6677 * this causes a secondary PCI reset which will reset the
6678 * controller." */
2662cab8
DB		 6679
6680 int rc = 0;
6681
1df8552a 6682 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6683
1df8552a 6684 /* enter the D3hot power management state */
2662cab8
DB		 6685 rc = pci_set_power_state(pdev, PCI_D3hot);
6686 if (rc)
6687 return rc;
1df8552a
SC		 6688
6689 msleep(500);
6690
6691 /* enter the D0 power management state */
2662cab8
DB		 6692 rc = pci_set_power_state(pdev, PCI_D0);
6693 if (rc)
6694 return rc;
c4853efe
MM		 6695
6696 /*
6697 * The P600 requires a small delay when changing states.
6698 * Otherwise we may think the board did not reset and we bail.
6699 * This for kdump only and is particular to the P600.
6700 */
6701 msleep(500);
1df8552a
SC		 6702 }
6703 return 0;
6704}
6705
6f039790 6706static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6707{
6708 memset(driver_version, 0, len);
f79cfec6 6709 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6710}
6711
6f039790 6712static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6713{
6714 char *driver_version;
6715 int i, size = sizeof(cfgtable->driver_version);
6716
6717 driver_version = kmalloc(size, GFP_KERNEL);
6718 if (!driver_version)
6719 return -ENOMEM;
6720
6721 init_driver_version(driver_version, size);
6722 for (i = 0; i < size; i++)
6723 writeb(driver_version[i], &cfgtable->driver_version[i]);
6724 kfree(driver_version);
6725 return 0;
6726}
6727
6f039790
GKH		 6728static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6729 unsigned char *driver_ver)
580ada3c
SC		 6730{
6731 int i;
6732
6733 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6734 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6735}
6736
6f039790 6737static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6738{
6739
6740 char *driver_ver, *old_driver_ver;
6741 int rc, size = sizeof(cfgtable->driver_version);
6742
6743 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6744 if (!old_driver_ver)
6745 return -ENOMEM;
6746 driver_ver = old_driver_ver + size;
6747
6748 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6749 * should have been changed, otherwise we know the reset failed.
6750 */
6751 init_driver_version(old_driver_ver, size);
6752 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6753 rc = !memcmp(driver_ver, old_driver_ver, size);
6754 kfree(old_driver_ver);
6755 return rc;
6756}
edd16368 6757/* This does a hard reset of the controller using PCI power management
1df8552a 6758 * states or the using the doorbell register.
edd16368 6759 */
6b6c1cd7 6760static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6761{
1df8552a
SC		 6762 u64 cfg_offset;
6763 u32 cfg_base_addr;
6764 u64 cfg_base_addr_index;
6765 void __iomem *vaddr;
6766 unsigned long paddr;
580ada3c 6767 u32 misc_fw_support;
270d05de 6768 int rc;
1df8552a 6769 struct CfgTable __iomem *cfgtable;
cf0b08d0 6770 u32 use_doorbell;
270d05de 6771 u16 command_register;
edd16368 6772
1df8552a
SC		 6773 /* For controllers as old as the P600, this is very nearly
6774 * the same thing as
edd16368
SC		 6775 *
6776 * pci_save_state(pci_dev);
6777 * pci_set_power_state(pci_dev, PCI_D3hot);
6778 * pci_set_power_state(pci_dev, PCI_D0);
6779 * pci_restore_state(pci_dev);
6780 *
1df8552a
SC		 6781 * For controllers newer than the P600, the pci power state
6782 * method of resetting doesn't work so we have another way
6783 * using the doorbell register.
edd16368 6784 */
18867659 6785
60f923b9
RE		 6786 if (!ctlr_is_resettable(board_id)) {
6787 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6788 return -ENODEV;
6789 }
46380786
SC		 6790
6791 /* if controller is soft- but not hard resettable... */
6792 if (!ctlr_is_hard_resettable(board_id))
6793 return -ENOTSUPP; /* try soft reset later. */
18867659 6794
270d05de
SC		 6795 /* Save the PCI command register */
6796 pci_read_config_word(pdev, 4, &command_register);
270d05de 6797 pci_save_state(pdev);
edd16368 6798
1df8552a
SC		 6799 /* find the first memory BAR, so we can find the cfg table */
6800 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6801 if (rc)
6802 return rc;
6803 vaddr = remap_pci_mem(paddr, 0x250);
6804 if (!vaddr)
6805 return -ENOMEM;
edd16368 6806
1df8552a
SC		 6807 /* find cfgtable in order to check if reset via doorbell is supported */
6808 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6809 &cfg_base_addr_index, &cfg_offset);
6810 if (rc)
6811 goto unmap_vaddr;
6812 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6813 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6814 if (!cfgtable) {
6815 rc = -ENOMEM;
6816 goto unmap_vaddr;
6817 }
580ada3c
SC		 6818 rc = write_driver_ver_to_cfgtable(cfgtable);
6819 if (rc)
03741d95 6820 goto unmap_cfgtable;
edd16368 6821
cf0b08d0
SC		 6822 /* If reset via doorbell register is supported, use that.
6823 * There are two such methods. Favor the newest method.
6824 */
1df8552a 6825 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6826 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6827 if (use_doorbell) {
6828 use_doorbell = DOORBELL_CTLR_RESET2;
6829 } else {
6830 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6831 if (use_doorbell) {
050f7147
SC		 6832 dev_warn(&pdev->dev,
6833 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6834 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6835 goto unmap_cfgtable;
6836 }
6837 }
edd16368 6838
1df8552a
SC		 6839 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6840 if (rc)
6841 goto unmap_cfgtable;
edd16368 6842
270d05de 6843 pci_restore_state(pdev);
270d05de 6844 pci_write_config_word(pdev, 4, command_register);
edd16368 6845
1df8552a
SC		 6846 /* Some devices (notably the HP Smart Array 5i Controller)
6847 need a little pause here */
6848 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6849
fe5389c8
SC		 6850 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6851 if (rc) {
6852 dev_warn(&pdev->dev,
050f7147 6853 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6854 goto unmap_cfgtable;
6855 }
fe5389c8 6856
580ada3c
SC		 6857 rc = controller_reset_failed(vaddr);
6858 if (rc < 0)
6859 goto unmap_cfgtable;
6860 if (rc) {
64670ac8
SC		 6861 dev_warn(&pdev->dev, "Unable to successfully reset "
6862 "controller. Will try soft reset.\n");
6863 rc = -ENOTSUPP;
580ada3c 6864 } else {
64670ac8 6865 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6866 }
6867
6868unmap_cfgtable:
6869 iounmap(cfgtable);
6870
6871unmap_vaddr:
6872 iounmap(vaddr);
6873 return rc;
edd16368
SC		 6874}
6875
6876/*
6877 * We cannot read the structure directly, for portability we must use
6878 * the io functions.
6879 * This is for debug only.
6880 */
42a91641 6881static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6882{
58f8665c 6883#ifdef HPSA_DEBUG
edd16368
SC		 6884 int i;
6885 char temp_name[17];
6886
6887 dev_info(dev, "Controller Configuration information\n");
6888 dev_info(dev, "------------------------------------\n");
6889 for (i = 0; i < 4; i++)
6890 temp_name[i] = readb(&(tb->Signature[i]));
6891 temp_name[4] = '\0';
6892 dev_info(dev, " Signature = %s\n", temp_name);
6893 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6894 dev_info(dev, " Transport methods supported = 0x%x\n",
6895 readl(&(tb->TransportSupport)));
6896 dev_info(dev, " Transport methods active = 0x%x\n",
6897 readl(&(tb->TransportActive)));
6898 dev_info(dev, " Requested transport Method = 0x%x\n",
6899 readl(&(tb->HostWrite.TransportRequest)));
6900 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6901 readl(&(tb->HostWrite.CoalIntDelay)));
6902 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6903 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6904 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6905 readl(&(tb->CmdsOutMax)));
6906 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6907 for (i = 0; i < 16; i++)
6908 temp_name[i] = readb(&(tb->ServerName[i]));
6909 temp_name[16] = '\0';
6910 dev_info(dev, " Server Name = %s\n", temp_name);
6911 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6912 readl(&(tb->HeartBeat)));
edd16368 6913#endif /* HPSA_DEBUG */
58f8665c 6914}
edd16368
SC		 6915
6916static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6917{
6918 int i, offset, mem_type, bar_type;
6919
6920 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6921 return 0;
6922 offset = 0;
6923 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6924 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6925 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6926 offset += 4;
6927 else {
6928 mem_type = pci_resource_flags(pdev, i) &
6929 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6930 switch (mem_type) {
6931 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6932 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6933 offset += 4; /* 32 bit */
6934 break;
6935 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6936 offset += 8;
6937 break;
6938 default: /* reserved in PCI 2.2 */
6939 dev_warn(&pdev->dev,
6940 "base address is invalid\n");
6941 return -1;
6942 break;
6943 }
6944 }
6945 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6946 return i + 1;
6947 }
6948 return -1;
6949}
6950
cc64c817
RE		 6951static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6952{
6953 if (h->msix_vector) {
6954 if (h->pdev->msix_enabled)
6955 pci_disable_msix(h->pdev);
105a3dbc 6956 h->msix_vector = 0;
cc64c817
RE		 6957 } else if (h->msi_vector) {
6958 if (h->pdev->msi_enabled)
6959 pci_disable_msi(h->pdev);
105a3dbc 6960 h->msi_vector = 0;
cc64c817
RE		 6961 }
6962}
6963
edd16368 6964/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6965 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6966 */
6f039790 6967static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6968{
6969#ifdef CONFIG_PCI_MSI
254f796b
MG		 6970 int err, i;
6971 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6972
6973 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6974 hpsa_msix_entries[i].vector = 0;
6975 hpsa_msix_entries[i].entry = i;
6976 }
edd16368
SC		 6977
6978 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6979 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6980 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6981 goto default_int_mode;
55c06c71 6982 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6983 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6984 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6985 if (h->msix_vector > num_online_cpus())
6986 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6987 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6988 1, h->msix_vector);
6989 if (err < 0) {
6990 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6991 h->msix_vector = 0;
6992 goto single_msi_mode;
6993 } else if (err < h->msix_vector) {
55c06c71 6994 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6995 "available\n", err);
edd16368 6996 }
18fce3c4
AG		 6997 h->msix_vector = err;
6998 for (i = 0; i < h->msix_vector; i++)
6999 h->intr[i] = hpsa_msix_entries[i].vector;
7000 return;
edd16368 7001 }
18fce3c4 7002single_msi_mode:
55c06c71 7003 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7004 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7005 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7006 h->msi_vector = 1;
7007 else
55c06c71 7008 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7009 }
7010default_int_mode:
7011#endif /* CONFIG_PCI_MSI */
7012 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7013 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7014}
7015
6f039790 7016static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7017{
7018 int i;
7019 u32 subsystem_vendor_id, subsystem_device_id;
7020
7021 subsystem_vendor_id = pdev->subsystem_vendor;
7022 subsystem_device_id = pdev->subsystem_device;
7023 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7024 subsystem_vendor_id;
7025
7026 for (i = 0; i < ARRAY_SIZE(products); i++)
7027 if (*board_id == products[i].board_id)
7028 return i;
7029
6798cc0a
SC		 7030 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7031 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7032 !hpsa_allow_any) {
e5c880d1
SC		 7033 dev_warn(&pdev->dev, "unrecognized board ID: "
7034 "0x%08x, ignoring.\n", *board_id);
7035 return -ENODEV;
7036 }
7037 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7038}
7039
6f039790
GKH		 7040static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7041 unsigned long *memory_bar)
3a7774ce
SC		 7042{
7043 int i;
7044
7045 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7046 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7047 /* addressing mode bits already removed */
12d2cd47
SC		 7048 *memory_bar = pci_resource_start(pdev, i);
7049 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7050 *memory_bar);
7051 return 0;
7052 }
12d2cd47 7053 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7054 return -ENODEV;
7055}
7056
6f039790
GKH		 7057static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7058 int wait_for_ready)
2c4c8c8b 7059{
fe5389c8 7060 int i, iterations;
2c4c8c8b 7061 u32 scratchpad;
fe5389c8
SC		 7062 if (wait_for_ready)
7063 iterations = HPSA_BOARD_READY_ITERATIONS;
7064 else
7065 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7066
fe5389c8
SC		 7067 for (i = 0; i < iterations; i++) {
7068 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7069 if (wait_for_ready) {
7070 if (scratchpad == HPSA_FIRMWARE_READY)
7071 return 0;
7072 } else {
7073 if (scratchpad != HPSA_FIRMWARE_READY)
7074 return 0;
7075 }
2c4c8c8b
SC		 7076 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7077 }
fe5389c8 7078 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7079 return -ENODEV;
7080}
7081
6f039790
GKH		 7082static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7083 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7084 u64 *cfg_offset)
a51fd47f
SC		 7085{
7086 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7087 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7088 *cfg_base_addr &= (u32) 0x0000ffff;
7089 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7090 if (*cfg_base_addr_index == -1) {
7091 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7092 return -ENODEV;
7093 }
7094 return 0;
7095}
7096
195f2c65
RE		 7097static void hpsa_free_cfgtables(struct ctlr_info *h)
7098{
105a3dbc 7099 if (h->transtable) {
195f2c65 7100 iounmap(h->transtable);
105a3dbc
RE		 7101 h->transtable = NULL;
7102 }
7103 if (h->cfgtable) {
195f2c65 7104 iounmap(h->cfgtable);
105a3dbc
RE		 7105 h->cfgtable = NULL;
7106 }
195f2c65
RE		 7107}
7108
7109/* Find and map CISS config table and transfer table
7110+ * several items must be unmapped (freed) later
7111+ * */
6f039790 7112static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7113{
01a02ffc
SC		 7114 u64 cfg_offset;
7115 u32 cfg_base_addr;
7116 u64 cfg_base_addr_index;
303932fd 7117 u32 trans_offset;
a51fd47f 7118 int rc;
77c4495c 7119
a51fd47f
SC		 7120 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7121 &cfg_base_addr_index, &cfg_offset);
7122 if (rc)
7123 return rc;
77c4495c 7124 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7125 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7126 if (!h->cfgtable) {
7127 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7128 return -ENOMEM;
cd3c81c4 7129 }
580ada3c
SC		 7130 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7131 if (rc)
7132 return rc;
77c4495c 7133 /* Find performant mode table. */
a51fd47f 7134 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7135 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7136 cfg_base_addr_index)+cfg_offset+trans_offset,
7137 sizeof(*h->transtable));
195f2c65
RE		 7138 if (!h->transtable) {
7139 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7140 hpsa_free_cfgtables(h);
77c4495c 7141 return -ENOMEM;
195f2c65 7142 }
77c4495c
SC		 7143 return 0;
7144}
7145
6f039790 7146static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7147{
41ce4c35
SC		 7148#define MIN_MAX_COMMANDS 16
7149 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7150
7151 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7152
7153 /* Limit commands in memory limited kdump scenario. */
7154 if (reset_devices && h->max_commands > 32)
7155 h->max_commands = 32;
7156
41ce4c35
SC		 7157 if (h->max_commands < MIN_MAX_COMMANDS) {
7158 dev_warn(&h->pdev->dev,
7159 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7160 h->max_commands,
7161 MIN_MAX_COMMANDS);
7162 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7163 }
7164}
7165
c7ee65b3
WS		 7166/* If the controller reports that the total max sg entries is greater than 512,
7167 * then we know that chained SG blocks work. (Original smart arrays did not
7168 * support chained SG blocks and would return zero for max sg entries.)
7169 */
7170static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7171{
7172 return h->maxsgentries > 512;
7173}
7174
b93d7536
SC		 7175/* Interrogate the hardware for some limits:
7176 * max commands, max SG elements without chaining, and with chaining,
7177 * SG chain block size, etc.
7178 */
6f039790 7179static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7180{
cba3d38b 7181 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7182 h->nr_cmds = h->max_commands;
b93d7536 7183 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7184 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7185 if (hpsa_supports_chained_sg_blocks(h)) {
7186 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7187 h->max_cmd_sg_entries = 32;
1a63ea6f 7188 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7189 h->maxsgentries--; /* save one for chain pointer */
7190 } else {
c7ee65b3
WS		 7191 /*
7192 * Original smart arrays supported at most 31 s/g entries
7193 * embedded inline in the command (trying to use more
7194 * would lock up the controller)
7195 */
7196 h->max_cmd_sg_entries = 31;
1a63ea6f 7197 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7198 h->chainsize = 0;
b93d7536 7199 }
75167d2c
SC		 7200
7201 /* Find out what task management functions are supported and cache */
7202 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7203 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7204 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7205 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7206 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7207 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7208 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7209}
7210
76c46e49
SC		 7211static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7212{
0fc9fd40 7213 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7214 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7215 return false;
7216 }
7217 return true;
7218}
7219
97a5e98c 7220static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7221{
97a5e98c 7222 u32 driver_support;
f7c39101 7223
97a5e98c 7224 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7225 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7226#ifdef CONFIG_X86
97a5e98c 7227 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7228#endif
28e13446
SC		 7229 driver_support |= ENABLE_UNIT_ATTN;
7230 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7231}
7232
3d0eab67
SC		 7233/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7234 * in a prefetch beyond physical memory.
7235 */
7236static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7237{
7238 u32 dma_prefetch;
7239
7240 if (h->board_id != 0x3225103C)
7241 return;
7242 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7243 dma_prefetch |= 0x8000;
7244 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7245}
7246
c706a795 7247static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7248{
7249 int i;
7250 u32 doorbell_value;
7251 unsigned long flags;
7252 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7253 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7254 spin_lock_irqsave(&h->lock, flags);
7255 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7256 spin_unlock_irqrestore(&h->lock, flags);
7257 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7258 goto done;
76438d08 7259 /* delay and try again */
007e7aa9 7260 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7261 }
c706a795
RE		 7262 return -ENODEV;
7263done:
7264 return 0;
76438d08
SC		 7265}
7266
c706a795 7267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7268{
7269 int i;
6eaf46fd
SC		 7270 u32 doorbell_value;
7271 unsigned long flags;
eb6b2ae9
SC		 7272
7273 /* under certain very rare conditions, this can take awhile.
7274 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7275 * as we enter this code.)
7276 */
007e7aa9 7277 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7278 if (h->remove_in_progress)
7279 goto done;
6eaf46fd
SC		 7280 spin_lock_irqsave(&h->lock, flags);
7281 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7282 spin_unlock_irqrestore(&h->lock, flags);
382be668 7283 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7284 goto done;
eb6b2ae9 7285 /* delay and try again */
007e7aa9 7286 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7287 }
c706a795
RE		 7288 return -ENODEV;
7289done:
7290 return 0;
3f4336f3
SC		 7291}
7292
c706a795 7293/* return -ENODEV or other reason on error, 0 on success */
6f039790 7294static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7295{
7296 u32 trans_support;
7297
7298 trans_support = readl(&(h->cfgtable->TransportSupport));
7299 if (!(trans_support & SIMPLE_MODE))
7300 return -ENOTSUPP;
7301
7302 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7303
3f4336f3
SC		 7304 /* Update the field, and then ring the doorbell */
7305 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7306 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7307 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7308 if (hpsa_wait_for_mode_change_ack(h))
7309 goto error;
eb6b2ae9 7310 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7311 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7312 goto error;
960a30e7 7313 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7314 return 0;
283b4a9b 7315error:
050f7147 7316 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7317 return -ENODEV;
eb6b2ae9
SC		 7318}
7319
195f2c65
RE		 7320/* free items allocated or mapped by hpsa_pci_init */
7321static void hpsa_free_pci_init(struct ctlr_info *h)
7322{
7323 hpsa_free_cfgtables(h); /* pci_init 4 */
7324 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7325 h->vaddr = NULL;
195f2c65 7326 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7327 /*
7328 * call pci_disable_device before pci_release_regions per
7329 * Documentation/PCI/pci.txt
7330 */
195f2c65 7331 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7332 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7333}
7334
7335/* several items must be freed later */
6f039790 7336static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7337{
eb6b2ae9 7338 int prod_index, err;
edd16368 7339
e5c880d1
SC		 7340 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7341 if (prod_index < 0)
60f923b9 7342 return prod_index;
e5c880d1
SC		 7343 h->product_name = products[prod_index].product_name;
7344 h->access = *(products[prod_index].access);
edd16368 7345
9b5c48c2
SC		 7346 h->needs_abort_tags_swizzled =
7347 ctlr_needs_abort_tags_swizzled(h->board_id);
7348
e5a44df8
MG		 7349 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7350 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7351
55c06c71 7352 err = pci_enable_device(h->pdev);
edd16368 7353 if (err) {
195f2c65 7354 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7355 pci_disable_device(h->pdev);
edd16368
SC		 7356 return err;
7357 }
7358
f79cfec6 7359 err = pci_request_regions(h->pdev, HPSA);
edd16368 7360 if (err) {
55c06c71 7361 dev_err(&h->pdev->dev,
195f2c65 7362 "failed to obtain PCI resources\n");
943a7021
RE		 7363 pci_disable_device(h->pdev);
7364 return err;
edd16368 7365 }
4fa604e1
RE		 7366
7367 pci_set_master(h->pdev);
7368
6b3f4c52 7369 hpsa_interrupt_mode(h);
12d2cd47 7370 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7371 if (err)
195f2c65 7372 goto clean2; /* intmode+region, pci */
edd16368 7373 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7374 if (!h->vaddr) {
195f2c65 7375 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7376 err = -ENOMEM;
195f2c65 7377 goto clean2; /* intmode+region, pci */
204892e9 7378 }
fe5389c8 7379 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7380 if (err)
195f2c65 7381 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7382 err = hpsa_find_cfgtables(h);
7383 if (err)
195f2c65 7384 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7385 hpsa_find_board_params(h);
edd16368 7386
76c46e49 7387 if (!hpsa_CISS_signature_present(h)) {
edd16368 7388 err = -ENODEV;
195f2c65 7389 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7390 }
97a5e98c 7391 hpsa_set_driver_support_bits(h);
3d0eab67 7392 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7393 err = hpsa_enter_simple_mode(h);
7394 if (err)
195f2c65 7395 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7396 return 0;
7397
195f2c65
RE		 7398clean4: /* cfgtables, vaddr, intmode+region, pci */
7399 hpsa_free_cfgtables(h);
7400clean3: /* vaddr, intmode+region, pci */
7401 iounmap(h->vaddr);
105a3dbc 7402 h->vaddr = NULL;
195f2c65
RE		 7403clean2: /* intmode+region, pci */
7404 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7405 /*
7406 * call pci_disable_device before pci_release_regions per
7407 * Documentation/PCI/pci.txt
7408 */
195f2c65 7409 pci_disable_device(h->pdev);
943a7021 7410 pci_release_regions(h->pdev);
edd16368
SC		 7411 return err;
7412}
7413
6f039790 7414static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7415{
7416 int rc;
7417
7418#define HBA_INQUIRY_BYTE_COUNT 64
7419 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7420 if (!h->hba_inquiry_data)
7421 return;
7422 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7423 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7424 if (rc != 0) {
7425 kfree(h->hba_inquiry_data);
7426 h->hba_inquiry_data = NULL;
7427 }
7428}
7429
6b6c1cd7 7430static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7431{
1df8552a 7432 int rc, i;
3b747298 7433 void __iomem *vaddr;
4c2a8c40
SC		 7434
7435 if (!reset_devices)
7436 return 0;
7437
132aa220
TH		 7438 /* kdump kernel is loading, we don't know in which state is
7439 * the pci interface. The dev->enable_cnt is equal zero
7440 * so we call enable+disable, wait a while and switch it on.
7441 */
7442 rc = pci_enable_device(pdev);
7443 if (rc) {
7444 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7445 return -ENODEV;
7446 }
7447 pci_disable_device(pdev);
7448 msleep(260); /* a randomly chosen number */
7449 rc = pci_enable_device(pdev);
7450 if (rc) {
7451 dev_warn(&pdev->dev, "failed to enable device.\n");
7452 return -ENODEV;
7453 }
4fa604e1 7454
859c75ab 7455 pci_set_master(pdev);
4fa604e1 7456
3b747298
TH		 7457 vaddr = pci_ioremap_bar(pdev, 0);
7458 if (vaddr == NULL) {
7459 rc = -ENOMEM;
7460 goto out_disable;
7461 }
7462 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7463 iounmap(vaddr);
7464
1df8552a 7465 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7466 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7467
1df8552a
SC		 7468 /* -ENOTSUPP here means we cannot reset the controller
7469 * but it's already (and still) up and running in
18867659
SC		 7470 * "performant mode". Or, it might be 640x, which can't reset
7471 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7472 */
adf1b3a3 7473 if (rc)
132aa220 7474 goto out_disable;
4c2a8c40
SC		 7475
7476 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7477 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7478 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7479 if (hpsa_noop(pdev) == 0)
7480 break;
7481 else
7482 dev_warn(&pdev->dev, "no-op failed%s\n",
7483 (i < 11 ? "; re-trying" : ""));
7484 }
132aa220
TH		 7485
7486out_disable:
7487
7488 pci_disable_device(pdev);
7489 return rc;
4c2a8c40
SC		 7490}
7491
1fb7c98a
RE		 7492static void hpsa_free_cmd_pool(struct ctlr_info *h)
7493{
7494 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7495 h->cmd_pool_bits = NULL;
7496 if (h->cmd_pool) {
1fb7c98a
RE		 7497 pci_free_consistent(h->pdev,
7498 h->nr_cmds * sizeof(struct CommandList),
7499 h->cmd_pool,
7500 h->cmd_pool_dhandle);
105a3dbc
RE		 7501 h->cmd_pool = NULL;
7502 h->cmd_pool_dhandle = 0;
7503 }
7504 if (h->errinfo_pool) {
1fb7c98a
RE		 7505 pci_free_consistent(h->pdev,
7506 h->nr_cmds * sizeof(struct ErrorInfo),
7507 h->errinfo_pool,
7508 h->errinfo_pool_dhandle);
105a3dbc
RE		 7509 h->errinfo_pool = NULL;
7510 h->errinfo_pool_dhandle = 0;
7511 }
1fb7c98a
RE		 7512}
7513
d37ffbe4 7514static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7515{
7516 h->cmd_pool_bits = kzalloc(
7517 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7518 sizeof(unsigned long), GFP_KERNEL);
7519 h->cmd_pool = pci_alloc_consistent(h->pdev,
7520 h->nr_cmds * sizeof(*h->cmd_pool),
7521 &(h->cmd_pool_dhandle));
7522 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7523 h->nr_cmds * sizeof(*h->errinfo_pool),
7524 &(h->errinfo_pool_dhandle));
7525 if ((h->cmd_pool_bits == NULL)
7526 || (h->cmd_pool == NULL)
7527 || (h->errinfo_pool == NULL)) {
7528 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7529 goto clean_up;
2e9d1b36 7530 }
360c73bd 7531 hpsa_preinitialize_commands(h);
2e9d1b36 7532 return 0;
2c143342
RE		 7533clean_up:
7534 hpsa_free_cmd_pool(h);
7535 return -ENOMEM;
2e9d1b36
SC		 7536}
7537
41b3cf08
SC		 7538static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7539{
ec429952 7540 int i, cpu;
41b3cf08
SC		 7541
7542 cpu = cpumask_first(cpu_online_mask);
7543 for (i = 0; i < h->msix_vector; i++) {
ec429952 7544 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7545 cpu = cpumask_next(cpu, cpu_online_mask);
7546 }
7547}
7548
ec501a18
RE		 7549/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7550static void hpsa_free_irqs(struct ctlr_info *h)
7551{
7552 int i;
7553
7554 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7555 /* Single reply queue, only one irq to free */
7556 i = h->intr_mode;
7557 irq_set_affinity_hint(h->intr[i], NULL);
7558 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7559 h->q[i] = 0;
ec501a18
RE		 7560 return;
7561 }
7562
7563 for (i = 0; i < h->msix_vector; i++) {
7564 irq_set_affinity_hint(h->intr[i], NULL);
7565 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7566 h->q[i] = 0;
ec501a18 7567 }
a4e17fc1
RE		 7568 for (; i < MAX_REPLY_QUEUES; i++)
7569 h->q[i] = 0;
ec501a18
RE		 7570}
7571
9ee61794
RE		 7572/* returns 0 on success; cleans up and returns -Enn on error */
7573static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7574 irqreturn_t (*msixhandler)(int, void *),
7575 irqreturn_t (*intxhandler)(int, void *))
7576{
254f796b 7577 int rc, i;
0ae01a32 7578
254f796b
MG		 7579 /*
7580 * initialize h->q[x] = x so that interrupt handlers know which
7581 * queue to process.
7582 */
7583 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7584 h->q[i] = (u8) i;
7585
eee0f03a 7586 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7587 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7588 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7589 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7590 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7591 0, h->intrname[i],
254f796b 7592 &h->q[i]);
a4e17fc1
RE		 7593 if (rc) {
7594 int j;
7595
7596 dev_err(&h->pdev->dev,
7597 "failed to get irq %d for %s\n",
7598 h->intr[i], h->devname);
7599 for (j = 0; j < i; j++) {
7600 free_irq(h->intr[j], &h->q[j]);
7601 h->q[j] = 0;
7602 }
7603 for (; j < MAX_REPLY_QUEUES; j++)
7604 h->q[j] = 0;
7605 return rc;
7606 }
7607 }
41b3cf08 7608 hpsa_irq_affinity_hints(h);
254f796b
MG		 7609 } else {
7610 /* Use single reply pool */
eee0f03a 7611 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7612 if (h->msix_vector)
7613 sprintf(h->intrname[h->intr_mode],
7614 "%s-msix", h->devname);
7615 else
7616 sprintf(h->intrname[h->intr_mode],
7617 "%s-msi", h->devname);
254f796b 7618 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7619 msixhandler, 0,
7620 h->intrname[h->intr_mode],
254f796b
MG		 7621 &h->q[h->intr_mode]);
7622 } else {
8b47004a
RE		 7623 sprintf(h->intrname[h->intr_mode],
7624 "%s-intx", h->devname);
254f796b 7625 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7626 intxhandler, IRQF_SHARED,
7627 h->intrname[h->intr_mode],
254f796b
MG		 7628 &h->q[h->intr_mode]);
7629 }
105a3dbc 7630 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7631 }
0ae01a32 7632 if (rc) {
195f2c65 7633 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7634 h->intr[h->intr_mode], h->devname);
195f2c65 7635 hpsa_free_irqs(h);
0ae01a32
SC		 7636 return -ENODEV;
7637 }
7638 return 0;
7639}
7640
6f039790 7641static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7642{
39c53f55 7643 int rc;
bf43caf3 7644 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7645
7646 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7647 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7648 if (rc) {
64670ac8 7649 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7650 return rc;
64670ac8
SC		 7651 }
7652
7653 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7654 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7655 if (rc) {
64670ac8
SC		 7656 dev_warn(&h->pdev->dev, "Board failed to become ready "
7657 "after soft reset.\n");
39c53f55 7658 return rc;
64670ac8
SC		 7659 }
7660
7661 return 0;
7662}
7663
072b0518
SC		 7664static void hpsa_free_reply_queues(struct ctlr_info *h)
7665{
7666 int i;
7667
7668 for (i = 0; i < h->nreply_queues; i++) {
7669 if (!h->reply_queue[i].head)
7670 continue;
1fb7c98a
RE		 7671 pci_free_consistent(h->pdev,
7672 h->reply_queue_size,
7673 h->reply_queue[i].head,
7674 h->reply_queue[i].busaddr);
072b0518
SC		 7675 h->reply_queue[i].head = NULL;
7676 h->reply_queue[i].busaddr = 0;
7677 }
105a3dbc 7678 h->reply_queue_size = 0;
072b0518
SC		 7679}
7680
0097f0f4
SC		 7681static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7682{
105a3dbc
RE		 7683 hpsa_free_performant_mode(h); /* init_one 7 */
7684 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7685 hpsa_free_cmd_pool(h); /* init_one 5 */
7686 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7687 scsi_host_put(h->scsi_host); /* init_one 3 */
7688 h->scsi_host = NULL; /* init_one 3 */
7689 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7690 free_percpu(h->lockup_detected); /* init_one 2 */
7691 h->lockup_detected = NULL; /* init_one 2 */
7692 if (h->resubmit_wq) {
7693 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7694 h->resubmit_wq = NULL;
7695 }
7696 if (h->rescan_ctlr_wq) {
7697 destroy_workqueue(h->rescan_ctlr_wq);
7698 h->rescan_ctlr_wq = NULL;
7699 }
105a3dbc 7700 kfree(h); /* init_one 1 */
64670ac8
SC		 7701}
7702
a0c12413 7703/* Called when controller lockup detected. */
f2405db8 7704static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7705{
281a7fd0
WS		 7706 int i, refcount;
7707 struct CommandList *c;
25163bd5 7708 int failcount = 0;
a0c12413 7709
080ef1cc 7710 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7711 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7712 c = h->cmd_pool + i;
281a7fd0
WS		 7713 refcount = atomic_inc_return(&c->refcount);
7714 if (refcount > 1) {
25163bd5 7715 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7716 finish_cmd(c);
433b5f4d 7717 atomic_dec(&h->commands_outstanding);
25163bd5 7718 failcount++;
281a7fd0
WS		 7719 }
7720 cmd_free(h, c);
a0c12413 7721 }
25163bd5
WS		 7722 dev_warn(&h->pdev->dev,
7723 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7724}
7725
094963da
SC		 7726static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7727{
c8ed0010 7728 int cpu;
094963da 7729
c8ed0010 7730 for_each_online_cpu(cpu) {
094963da
SC		 7731 u32 *lockup_detected;
7732 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7733 *lockup_detected = value;
094963da
SC		 7734 }
7735 wmb(); /* be sure the per-cpu variables are out to memory */
7736}
7737
a0c12413
SC		 7738static void controller_lockup_detected(struct ctlr_info *h)
7739{
7740 unsigned long flags;
094963da 7741 u32 lockup_detected;
a0c12413 7742
a0c12413
SC		 7743 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7744 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7745 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7746 if (!lockup_detected) {
7747 /* no heartbeat, but controller gave us a zero. */
7748 dev_warn(&h->pdev->dev,
25163bd5
WS		 7749 "lockup detected after %d but scratchpad register is zero\n",
7750 h->heartbeat_sample_interval / HZ);
094963da
SC		 7751 lockup_detected = 0xffffffff;
7752 }
7753 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7754 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7755 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7756 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7757 pci_disable_device(h->pdev);
f2405db8 7758 fail_all_outstanding_cmds(h);
a0c12413
SC		 7759}
7760
25163bd5 7761static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7762{
7763 u64 now;
7764 u32 heartbeat;
7765 unsigned long flags;
7766
a0c12413
SC		 7767 now = get_jiffies_64();
7768 /* If we've received an interrupt recently, we're ok. */
7769 if (time_after64(h->last_intr_timestamp +
e85c5974 7770 (h->heartbeat_sample_interval), now))
25163bd5 7771 return false;
a0c12413
SC		 7772
7773 /*
7774 * If we've already checked the heartbeat recently, we're ok.
7775 * This could happen if someone sends us a signal. We
7776 * otherwise don't care about signals in this thread.
7777 */
7778 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7779 (h->heartbeat_sample_interval), now))
25163bd5 7780 return false;
a0c12413
SC		 7781
7782 /* If heartbeat has not changed since we last looked, we're not ok. */
7783 spin_lock_irqsave(&h->lock, flags);
7784 heartbeat = readl(&h->cfgtable->HeartBeat);
7785 spin_unlock_irqrestore(&h->lock, flags);
7786 if (h->last_heartbeat == heartbeat) {
7787 controller_lockup_detected(h);
25163bd5 7788 return true;
a0c12413
SC		 7789 }
7790
7791 /* We're ok. */
7792 h->last_heartbeat = heartbeat;
7793 h->last_heartbeat_timestamp = now;
25163bd5 7794 return false;
a0c12413
SC		 7795}
7796
9846590e 7797static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7798{
7799 int i;
7800 char *event_type;
7801
e4aa3e6a
SC		 7802 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7803 return;
7804
76438d08 7805 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7806 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7807 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7808 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7809 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7810
7811 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7812 event_type = "state change";
7813 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7814 event_type = "configuration change";
7815 /* Stop sending new RAID offload reqs via the IO accelerator */
7816 scsi_block_requests(h->scsi_host);
7817 for (i = 0; i < h->ndevices; i++)
7818 h->dev[i]->offload_enabled = 0;
23100dd9 7819 hpsa_drain_accel_commands(h);
76438d08
SC		 7820 /* Set 'accelerator path config change' bit */
7821 dev_warn(&h->pdev->dev,
7822 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7823 h->events, event_type);
7824 writel(h->events, &(h->cfgtable->clear_event_notify));
7825 /* Set the "clear event notify field update" bit 6 */
7826 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7827 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7828 hpsa_wait_for_clear_event_notify_ack(h);
7829 scsi_unblock_requests(h->scsi_host);
7830 } else {
7831 /* Acknowledge controller notification events. */
7832 writel(h->events, &(h->cfgtable->clear_event_notify));
7833 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7834 hpsa_wait_for_clear_event_notify_ack(h);
7835#if 0
7836 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7837 hpsa_wait_for_mode_change_ack(h);
7838#endif
7839 }
9846590e 7840 return;
76438d08
SC		 7841}
7842
7843/* Check a register on the controller to see if there are configuration
7844 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7845 * we should rescan the controller for devices.
7846 * Also check flag for driver-initiated rescan.
76438d08 7847 */
9846590e 7848static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7849{
7850 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7851 return 0;
76438d08
SC		 7852
7853 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7854 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7855}
76438d08 7856
9846590e
SC		 7857/*
7858 * Check if any of the offline devices have become ready
7859 */
7860static int hpsa_offline_devices_ready(struct ctlr_info *h)
7861{
7862 unsigned long flags;
7863 struct offline_device_entry *d;
7864 struct list_head *this, *tmp;
7865
7866 spin_lock_irqsave(&h->offline_device_lock, flags);
7867 list_for_each_safe(this, tmp, &h->offline_device_list) {
7868 d = list_entry(this, struct offline_device_entry,
7869 offline_list);
7870 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7871 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7872 spin_lock_irqsave(&h->offline_device_lock, flags);
7873 list_del(&d->offline_list);
7874 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7875 return 1;
d1fea47c 7876 }
9846590e
SC		 7877 spin_lock_irqsave(&h->offline_device_lock, flags);
7878 }
7879 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7880 return 0;
76438d08
SC		 7881}
7882
6636e7f4 7883static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7884{
7885 unsigned long flags;
8a98db73 7886 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7887 struct ctlr_info, rescan_ctlr_work);
7888
7889
7890 if (h->remove_in_progress)
8a98db73 7891 return;
9846590e
SC		 7892
7893 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7894 scsi_host_get(h->scsi_host);
9846590e
SC		 7895 hpsa_ack_ctlr_events(h);
7896 hpsa_scan_start(h->scsi_host);
7897 scsi_host_put(h->scsi_host);
7898 }
8a98db73 7899 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7900 if (!h->remove_in_progress)
7901 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7902 h->heartbeat_sample_interval);
7903 spin_unlock_irqrestore(&h->lock, flags);
7904}
7905
7906static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7907{
7908 unsigned long flags;
7909 struct ctlr_info *h = container_of(to_delayed_work(work),
7910 struct ctlr_info, monitor_ctlr_work);
7911
7912 detect_controller_lockup(h);
7913 if (lockup_detected(h))
a0c12413 7914 return;
6636e7f4
DB		 7915
7916 spin_lock_irqsave(&h->lock, flags);
7917 if (!h->remove_in_progress)
7918 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7919 h->heartbeat_sample_interval);
7920 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7921}
7922
6636e7f4
DB		 7923static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7924 char *name)
7925{
7926 struct workqueue_struct *wq = NULL;
6636e7f4 7927
397ea9cb 7928 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7929 if (!wq)
7930 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7931
7932 return wq;
7933}
7934
6f039790 7935static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7936{
4c2a8c40 7937 int dac, rc;
edd16368 7938 struct ctlr_info *h;
64670ac8
SC		 7939 int try_soft_reset = 0;
7940 unsigned long flags;
6b6c1cd7 7941 u32 board_id;
edd16368
SC		 7942
7943 if (number_of_controllers == 0)
7944 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7945
6b6c1cd7
TH		 7946 rc = hpsa_lookup_board_id(pdev, &board_id);
7947 if (rc < 0) {
7948 dev_warn(&pdev->dev, "Board ID not found\n");
7949 return rc;
7950 }
7951
7952 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7953 if (rc) {
7954 if (rc != -ENOTSUPP)
7955 return rc;
7956 /* If the reset fails in a particular way (it has no way to do
7957 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7958 * a soft reset once we get the controller configured up to the
7959 * point that it can accept a command.
7960 */
7961 try_soft_reset = 1;
7962 rc = 0;
7963 }
7964
7965reinit_after_soft_reset:
edd16368 7966
303932fd
DB		 7967 /* Command structures must be aligned on a 32-byte boundary because
7968 * the 5 lower bits of the address are used by the hardware. and by
7969 * the driver. See comments in hpsa.h for more info.
7970 */
303932fd 7971 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 7972 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 7973 if (!h) {
7974 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 7975 return -ENOMEM;
105a3dbc 7976 }
edd16368 7977
55c06c71 7978 h->pdev = pdev;
105a3dbc 7979
a9a3a273 7980 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7981 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7982 spin_lock_init(&h->lock);
9846590e 7983 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7984 spin_lock_init(&h->scan_lock);
34f0c627 7985 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7986 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 7987
7988 /* Allocate and clear per-cpu variable lockup_detected */
7989 h->lockup_detected = alloc_percpu(u32);
2a5ac326 7990 if (!h->lockup_detected) {
105a3dbc 7991 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 7992 rc = -ENOMEM;
2efa5929 7993 goto clean1; /* aer/h */
2a5ac326 7994 }
094963da
SC		 7995 set_lockup_detected_for_all_cpus(h, 0);
7996
55c06c71 7997 rc = hpsa_pci_init(h);
105a3dbc 7998 if (rc)
2946e82b
RE		 7999 goto clean2; /* lu, aer/h */
8000
8001 /* relies on h-> settings made by hpsa_pci_init, including
8002 * interrupt_mode h->intr */
8003 rc = hpsa_scsi_host_alloc(h);
8004 if (rc)
8005 goto clean2_5; /* pci, lu, aer/h */
edd16368 8006
2946e82b 8007 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8008 h->ctlr = number_of_controllers;
8009 number_of_controllers++;
edd16368
SC		 8010
8011 /* configure PCI DMA stuff */
ecd9aad4
SC		 8012 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8013 if (rc == 0) {
edd16368 8014 dac = 1;
ecd9aad4
SC		 8015 } else {
8016 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8017 if (rc == 0) {
8018 dac = 0;
8019 } else {
8020 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8021 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8022 }
edd16368
SC		 8023 }
8024
8025 /* make sure the board interrupts are off */
8026 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8027
105a3dbc
RE		 8028 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8029 if (rc)
2946e82b 8030 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8031 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8032 if (rc)
2946e82b 8033 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8034 rc = hpsa_alloc_sg_chain_blocks(h);
8035 if (rc)
2946e82b 8036 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8037 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8038 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8039 init_waitqueue_head(&h->event_sync_wait_queue);
8040 mutex_init(&h->reset_mutex);
a08a8471 8041 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8042
8043 pci_set_drvdata(pdev, h);
9a41338e 8044 h->ndevices = 0;
2946e82b 8045
9a41338e 8046 spin_lock_init(&h->devlock);
105a3dbc
RE		 8047 rc = hpsa_put_ctlr_into_performant_mode(h);
8048 if (rc)
2946e82b
RE		 8049 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8050
8051 /* hook into SCSI subsystem */
8052 rc = hpsa_scsi_add_host(h);
8053 if (rc)
8054 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8055
8056 /* create the resubmit workqueue */
8057 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8058 if (!h->rescan_ctlr_wq) {
8059 rc = -ENOMEM;
8060 goto clean7;
8061 }
8062
8063 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8064 if (!h->resubmit_wq) {
8065 rc = -ENOMEM;
8066 goto clean7; /* aer/h */
8067 }
64670ac8 8068
105a3dbc
RE		 8069 /*
8070 * At this point, the controller is ready to take commands.
64670ac8
SC		 8071 * Now, if reset_devices and the hard reset didn't work, try
8072 * the soft reset and see if that works.
8073 */
8074 if (try_soft_reset) {
8075
8076 /* This is kind of gross. We may or may not get a completion
8077 * from the soft reset command, and if we do, then the value
8078 * from the fifo may or may not be valid. So, we wait 10 secs
8079 * after the reset throwing away any completions we get during
8080 * that time. Unregister the interrupt handler and register
8081 * fake ones to scoop up any residual completions.
8082 */
8083 spin_lock_irqsave(&h->lock, flags);
8084 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8085 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8086 hpsa_free_irqs(h);
9ee61794 8087 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8088 hpsa_intx_discard_completions);
8089 if (rc) {
9ee61794
RE		 8090 dev_warn(&h->pdev->dev,
8091 "Failed to request_irq after soft reset.\n");
d498757c 8092 /*
b2ef480c
RE		 8093 * cannot goto clean7 or free_irqs will be called
8094 * again. Instead, do its work
8095 */
8096 hpsa_free_performant_mode(h); /* clean7 */
8097 hpsa_free_sg_chain_blocks(h); /* clean6 */
8098 hpsa_free_cmd_pool(h); /* clean5 */
8099 /*
8100 * skip hpsa_free_irqs(h) clean4 since that
8101 * was just called before request_irqs failed
d498757c
RE		 8102 */
8103 goto clean3;
64670ac8
SC		 8104 }
8105
8106 rc = hpsa_kdump_soft_reset(h);
8107 if (rc)
8108 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8109 goto clean7;
64670ac8
SC		 8110
8111 dev_info(&h->pdev->dev, "Board READY.\n");
8112 dev_info(&h->pdev->dev,
8113 "Waiting for stale completions to drain.\n");
8114 h->access.set_intr_mask(h, HPSA_INTR_ON);
8115 msleep(10000);
8116 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8117
8118 rc = controller_reset_failed(h->cfgtable);
8119 if (rc)
8120 dev_info(&h->pdev->dev,
8121 "Soft reset appears to have failed.\n");
8122
8123 /* since the controller's reset, we have to go back and re-init
8124 * everything. Easiest to just forget what we've done and do it
8125 * all over again.
8126 */
8127 hpsa_undo_allocations_after_kdump_soft_reset(h);
8128 try_soft_reset = 0;
8129 if (rc)
b2ef480c 8130 /* don't goto clean, we already unallocated */
64670ac8
SC		 8131 return -ENODEV;
8132
8133 goto reinit_after_soft_reset;
8134 }
edd16368 8135
105a3dbc
RE		 8136 /* Enable Accelerated IO path at driver layer */
8137 h->acciopath_status = 1;
da0697bd 8138
e863d68e 8139
edd16368
SC		 8140 /* Turn the interrupts on so we can service requests */
8141 h->access.set_intr_mask(h, HPSA_INTR_ON);
8142
339b2b14 8143 hpsa_hba_inquiry(h);
8a98db73
SC		 8144
8145 /* Monitor the controller for firmware lockups */
8146 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8147 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8148 schedule_delayed_work(&h->monitor_ctlr_work,
8149 h->heartbeat_sample_interval);
6636e7f4
DB		 8150 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8151 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8152 h->heartbeat_sample_interval);
88bf6d62 8153 return 0;
edd16368 8154
2946e82b 8155clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8156 hpsa_free_performant_mode(h);
8157 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8158clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8159 hpsa_free_sg_chain_blocks(h);
2946e82b 8160clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8161 hpsa_free_cmd_pool(h);
2946e82b 8162clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8163 hpsa_free_irqs(h);
2946e82b
RE		 8164clean3: /* shost, pci, lu, aer/h */
8165 scsi_host_put(h->scsi_host);
8166 h->scsi_host = NULL;
8167clean2_5: /* pci, lu, aer/h */
195f2c65 8168 hpsa_free_pci_init(h);
2946e82b 8169clean2: /* lu, aer/h */
105a3dbc
RE		 8170 if (h->lockup_detected) {
8171 free_percpu(h->lockup_detected);
8172 h->lockup_detected = NULL;
8173 }
8174clean1: /* wq/aer/h */
8175 if (h->resubmit_wq) {
080ef1cc 8176 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8177 h->resubmit_wq = NULL;
8178 }
8179 if (h->rescan_ctlr_wq) {
6636e7f4 8180 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8181 h->rescan_ctlr_wq = NULL;
8182 }
edd16368 8183 kfree(h);
ecd9aad4 8184 return rc;
edd16368
SC		 8185}
8186
8187static void hpsa_flush_cache(struct ctlr_info *h)
8188{
8189 char *flush_buf;
8190 struct CommandList *c;
25163bd5 8191 int rc;
702890e3 8192
094963da 8193 if (unlikely(lockup_detected(h)))
702890e3 8194 return;
edd16368
SC		 8195 flush_buf = kzalloc(4, GFP_KERNEL);
8196 if (!flush_buf)
8197 return;
8198
45fcb86e 8199 c = cmd_alloc(h);
bf43caf3 8200
a2dac136
SC		 8201 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8202 RAID_CTLR_LUNID, TYPE_CMD)) {
8203 goto out;
8204 }
25163bd5
WS		 8205 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8206 PCI_DMA_TODEVICE, NO_TIMEOUT);
8207 if (rc)
8208 goto out;
edd16368 8209 if (c->err_info->CommandStatus != 0)
a2dac136 8210out:
edd16368
SC		 8211 dev_warn(&h->pdev->dev,
8212 "error flushing cache on controller\n");
45fcb86e 8213 cmd_free(h, c);
edd16368
SC		 8214 kfree(flush_buf);
8215}
8216
8217static void hpsa_shutdown(struct pci_dev *pdev)
8218{
8219 struct ctlr_info *h;
8220
8221 h = pci_get_drvdata(pdev);
8222 /* Turn board interrupts off and send the flush cache command
8223 * sendcmd will turn off interrupt, and send the flush...
8224 * To write all data in the battery backed cache to disks
8225 */
8226 hpsa_flush_cache(h);
8227 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8228 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8229 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8230}
8231
6f039790 8232static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8233{
8234 int i;
8235
105a3dbc 8236 for (i = 0; i < h->ndevices; i++) {
55e14e76 8237 kfree(h->dev[i]);
105a3dbc
RE		 8238 h->dev[i] = NULL;
8239 }
55e14e76
SC		 8240}
8241
6f039790 8242static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8243{
8244 struct ctlr_info *h;
8a98db73 8245 unsigned long flags;
edd16368
SC		 8246
8247 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8248 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8249 return;
8250 }
8251 h = pci_get_drvdata(pdev);
8a98db73
SC		 8252
8253 /* Get rid of any controller monitoring work items */
8254 spin_lock_irqsave(&h->lock, flags);
8255 h->remove_in_progress = 1;
8a98db73 8256 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8257 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8258 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8259 destroy_workqueue(h->rescan_ctlr_wq);
8260 destroy_workqueue(h->resubmit_wq);
cc64c817 8261
2d041306
DB		 8262 /*
8263 * Call before disabling interrupts.
8264 * scsi_remove_host can trigger I/O operations especially
8265 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8266 * operations which cannot complete and will hang the system.
8267 */
8268 if (h->scsi_host)
8269 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8270 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8271 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8272 hpsa_shutdown(pdev);
cc64c817 8273
105a3dbc
RE		 8274 hpsa_free_device_info(h); /* scan */
8275
2946e82b
RE		 8276 kfree(h->hba_inquiry_data); /* init_one 10 */
8277 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8278 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8279 hpsa_free_performant_mode(h); /* init_one 7 */
8280 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8281 hpsa_free_cmd_pool(h); /* init_one 5 */
8282
8283 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8284
2946e82b
RE		 8285 scsi_host_put(h->scsi_host); /* init_one 3 */
8286 h->scsi_host = NULL; /* init_one 3 */
8287
195f2c65 8288 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8289 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8290
105a3dbc
RE		 8291 free_percpu(h->lockup_detected); /* init_one 2 */
8292 h->lockup_detected = NULL; /* init_one 2 */
8293 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8294 kfree(h); /* init_one 1 */
edd16368
SC		 8295}
8296
8297static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8298 __attribute__((unused)) pm_message_t state)
8299{
8300 return -ENOSYS;
8301}
8302
8303static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8304{
8305 return -ENOSYS;
8306}
8307
8308static struct pci_driver hpsa_pci_driver = {
f79cfec6 8309 .name = HPSA,
edd16368 8310 .probe = hpsa_init_one,
6f039790 8311 .remove = hpsa_remove_one,
edd16368
SC		 8312 .id_table = hpsa_pci_device_id, /* id_table */
8313 .shutdown = hpsa_shutdown,
8314 .suspend = hpsa_suspend,
8315 .resume = hpsa_resume,
8316};
8317
303932fd
DB		 8318/* Fill in bucket_map[], given nsgs (the max number of
8319 * scatter gather elements supported) and bucket[],
8320 * which is an array of 8 integers. The bucket[] array
8321 * contains 8 different DMA transfer sizes (in 16
8322 * byte increments) which the controller uses to fetch
8323 * commands. This function fills in bucket_map[], which
8324 * maps a given number of scatter gather elements to one of
8325 * the 8 DMA transfer sizes. The point of it is to allow the
8326 * controller to only do as much DMA as needed to fetch the
8327 * command, with the DMA transfer size encoded in the lower
8328 * bits of the command address.
8329 */
8330static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8331 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8332{
8333 int i, j, b, size;
8334
303932fd
DB		 8335 /* Note, bucket_map must have nsgs+1 entries. */
8336 for (i = 0; i <= nsgs; i++) {
8337 /* Compute size of a command with i SG entries */
e1f7de0c 8338 size = i + min_blocks;
303932fd
DB		 8339 b = num_buckets; /* Assume the biggest bucket */
8340 /* Find the bucket that is just big enough */
e1f7de0c 8341 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8342 if (bucket[j] >= size) {
8343 b = j;
8344 break;
8345 }
8346 }
8347 /* for a command with i SG entries, use bucket b. */
8348 bucket_map[i] = b;
8349 }
8350}
8351
105a3dbc
RE		 8352/*
8353 * return -ENODEV on err, 0 on success (or no action)
8354 * allocates numerous items that must be freed later
8355 */
c706a795 8356static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8357{
6c311b57
SC		 8358 int i;
8359 unsigned long register_value;
e1f7de0c
MG		 8360 unsigned long transMethod = CFGTBL_Trans_Performant |
8361 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8362 CFGTBL_Trans_enable_directed_msix |
8363 (trans_support & (CFGTBL_Trans_io_accel1 |
8364 CFGTBL_Trans_io_accel2));
e1f7de0c 8365 struct access_method access = SA5_performant_access;
def342bd
SC		 8366
8367 /* This is a bit complicated. There are 8 registers on
8368 * the controller which we write to to tell it 8 different
8369 * sizes of commands which there may be. It's a way of
8370 * reducing the DMA done to fetch each command. Encoded into
8371 * each command's tag are 3 bits which communicate to the controller
8372 * which of the eight sizes that command fits within. The size of
8373 * each command depends on how many scatter gather entries there are.
8374 * Each SG entry requires 16 bytes. The eight registers are programmed
8375 * with the number of 16-byte blocks a command of that size requires.
8376 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8377 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8378 * blocks. Note, this only extends to the SG entries contained
8379 * within the command block, and does not extend to chained blocks
8380 * of SG elements. bft[] contains the eight values we write to
8381 * the registers. They are not evenly distributed, but have more
8382 * sizes for small commands, and fewer sizes for larger commands.
8383 */
d66ae08b 8384 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8385#define MIN_IOACCEL2_BFT_ENTRY 5
8386#define HPSA_IOACCEL2_HEADER_SZ 4
8387 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8388 13, 14, 15, 16, 17, 18, 19,
8389 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8390 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8391 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8392 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8393 16 * MIN_IOACCEL2_BFT_ENTRY);
8394 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8395 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8396 /* 5 = 1 s/g entry or 4k
8397 * 6 = 2 s/g entry or 8k
8398 * 8 = 4 s/g entry or 16k
8399 * 10 = 6 s/g entry or 24k
8400 */
303932fd 8401
b3a52e79
SC		 8402 /* If the controller supports either ioaccel method then
8403 * we can also use the RAID stack submit path that does not
8404 * perform the superfluous readl() after each command submission.
8405 */
8406 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8407 access = SA5_performant_access_no_read;
8408
303932fd 8409 /* Controller spec: zero out this buffer. */
072b0518
SC		 8410 for (i = 0; i < h->nreply_queues; i++)
8411 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8412
d66ae08b
SC		 8413 bft[7] = SG_ENTRIES_IN_CMD + 4;
8414 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8415 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8416 for (i = 0; i < 8; i++)
8417 writel(bft[i], &h->transtable->BlockFetch[i]);
8418
8419 /* size of controller ring buffer */
8420 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8421 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8422 writel(0, &h->transtable->RepQCtrAddrLow32);
8423 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8424
8425 for (i = 0; i < h->nreply_queues; i++) {
8426 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8427 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8428 &h->transtable->RepQAddr[i].lower);
8429 }
8430
b9af4937 8431 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8432 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8433 /*
8434 * enable outbound interrupt coalescing in accelerator mode;
8435 */
8436 if (trans_support & CFGTBL_Trans_io_accel1) {
8437 access = SA5_ioaccel_mode1_access;
8438 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8439 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8440 } else {
8441 if (trans_support & CFGTBL_Trans_io_accel2) {
8442 access = SA5_ioaccel_mode2_access;
8443 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8444 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8445 }
e1f7de0c 8446 }
303932fd 8447 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8448 if (hpsa_wait_for_mode_change_ack(h)) {
8449 dev_err(&h->pdev->dev,
8450 "performant mode problem - doorbell timeout\n");
8451 return -ENODEV;
8452 }
303932fd
DB		 8453 register_value = readl(&(h->cfgtable->TransportActive));
8454 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8455 dev_err(&h->pdev->dev,
8456 "performant mode problem - transport not active\n");
c706a795 8457 return -ENODEV;
303932fd 8458 }
960a30e7 8459 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8460 h->access = access;
8461 h->transMethod = transMethod;
8462
b9af4937
SC		 8463 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8464 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8465 return 0;
e1f7de0c 8466
b9af4937
SC		 8467 if (trans_support & CFGTBL_Trans_io_accel1) {
8468 /* Set up I/O accelerator mode */
8469 for (i = 0; i < h->nreply_queues; i++) {
8470 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8471 h->reply_queue[i].current_entry =
8472 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8473 }
8474 bft[7] = h->ioaccel_maxsg + 8;
8475 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8476 h->ioaccel1_blockFetchTable);
e1f7de0c 8477
b9af4937 8478 /* initialize all reply queue entries to unused */
072b0518
SC		 8479 for (i = 0; i < h->nreply_queues; i++)
8480 memset(h->reply_queue[i].head,
8481 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8482 h->reply_queue_size);
e1f7de0c 8483
b9af4937
SC		 8484 /* set all the constant fields in the accelerator command
8485 * frames once at init time to save CPU cycles later.
8486 */
8487 for (i = 0; i < h->nr_cmds; i++) {
8488 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8489
8490 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8491 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8492 (i * sizeof(struct ErrorInfo)));
8493 cp->err_info_len = sizeof(struct ErrorInfo);
8494 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8495 cp->host_context_flags =
8496 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8497 cp->timeout_sec = 0;
8498 cp->ReplyQueue = 0;
50a0decf 8499 cp->tag =
f2405db8 8500 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8501 cp->host_addr =
8502 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8503 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8504 }
8505 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8506 u64 cfg_offset, cfg_base_addr_index;
8507 u32 bft2_offset, cfg_base_addr;
8508 int rc;
8509
8510 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8511 &cfg_base_addr_index, &cfg_offset);
8512 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8513 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8514 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8515 4, h->ioaccel2_blockFetchTable);
8516 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8517 BUILD_BUG_ON(offsetof(struct CfgTable,
8518 io_accel_request_size_offset) != 0xb8);
8519 h->ioaccel2_bft2_regs =
8520 remap_pci_mem(pci_resource_start(h->pdev,
8521 cfg_base_addr_index) +
8522 cfg_offset + bft2_offset,
8523 ARRAY_SIZE(bft2) *
8524 sizeof(*h->ioaccel2_bft2_regs));
8525 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8526 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8527 }
b9af4937 8528 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8529 if (hpsa_wait_for_mode_change_ack(h)) {
8530 dev_err(&h->pdev->dev,
8531 "performant mode problem - enabling ioaccel mode\n");
8532 return -ENODEV;
8533 }
8534 return 0;
e1f7de0c
MG		 8535}
8536
1fb7c98a
RE		 8537/* Free ioaccel1 mode command blocks and block fetch table */
8538static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8539{
105a3dbc 8540 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8541 pci_free_consistent(h->pdev,
8542 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8543 h->ioaccel_cmd_pool,
8544 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8545 h->ioaccel_cmd_pool = NULL;
8546 h->ioaccel_cmd_pool_dhandle = 0;
8547 }
1fb7c98a 8548 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8549 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8550}
8551
d37ffbe4
RE		 8552/* Allocate ioaccel1 mode command blocks and block fetch table */
8553static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8554{
283b4a9b
SC		 8555 h->ioaccel_maxsg =
8556 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8557 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8558 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8559
e1f7de0c
MG		 8560 /* Command structures must be aligned on a 128-byte boundary
8561 * because the 7 lower bits of the address are used by the
8562 * hardware.
8563 */
e1f7de0c
MG		 8564 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8565 IOACCEL1_COMMANDLIST_ALIGNMENT);
8566 h->ioaccel_cmd_pool =
8567 pci_alloc_consistent(h->pdev,
8568 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8569 &(h->ioaccel_cmd_pool_dhandle));
8570
8571 h->ioaccel1_blockFetchTable =
283b4a9b 8572 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8573 sizeof(u32)), GFP_KERNEL);
8574
8575 if ((h->ioaccel_cmd_pool == NULL) ||
8576 (h->ioaccel1_blockFetchTable == NULL))
8577 goto clean_up;
8578
8579 memset(h->ioaccel_cmd_pool, 0,
8580 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8581 return 0;
8582
8583clean_up:
1fb7c98a 8584 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8585 return -ENOMEM;
6c311b57
SC		 8586}
8587
1fb7c98a
RE		 8588/* Free ioaccel2 mode command blocks and block fetch table */
8589static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8590{
d9a729f3
WS		 8591 hpsa_free_ioaccel2_sg_chain_blocks(h);
8592
105a3dbc 8593 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8594 pci_free_consistent(h->pdev,
8595 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8596 h->ioaccel2_cmd_pool,
8597 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8598 h->ioaccel2_cmd_pool = NULL;
8599 h->ioaccel2_cmd_pool_dhandle = 0;
8600 }
1fb7c98a 8601 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8602 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8603}
8604
d37ffbe4
RE		 8605/* Allocate ioaccel2 mode command blocks and block fetch table */
8606static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8607{
d9a729f3
WS		 8608 int rc;
8609
aca9012a
SC		 8610 /* Allocate ioaccel2 mode command blocks and block fetch table */
8611
8612 h->ioaccel_maxsg =
8613 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8614 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8615 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8616
aca9012a
SC		 8617 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8618 IOACCEL2_COMMANDLIST_ALIGNMENT);
8619 h->ioaccel2_cmd_pool =
8620 pci_alloc_consistent(h->pdev,
8621 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8622 &(h->ioaccel2_cmd_pool_dhandle));
8623
8624 h->ioaccel2_blockFetchTable =
8625 kmalloc(((h->ioaccel_maxsg + 1) *
8626 sizeof(u32)), GFP_KERNEL);
8627
8628 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8629 (h->ioaccel2_blockFetchTable == NULL)) {
8630 rc = -ENOMEM;
8631 goto clean_up;
8632 }
8633
8634 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8635 if (rc)
aca9012a
SC		 8636 goto clean_up;
8637
8638 memset(h->ioaccel2_cmd_pool, 0,
8639 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8640 return 0;
8641
8642clean_up:
1fb7c98a 8643 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8644 return rc;
aca9012a
SC		 8645}
8646
105a3dbc
RE		 8647/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8648static void hpsa_free_performant_mode(struct ctlr_info *h)
8649{
8650 kfree(h->blockFetchTable);
8651 h->blockFetchTable = NULL;
8652 hpsa_free_reply_queues(h);
8653 hpsa_free_ioaccel1_cmd_and_bft(h);
8654 hpsa_free_ioaccel2_cmd_and_bft(h);
8655}
8656
8657/* return -ENODEV on error, 0 on success (or no action)
8658 * allocates numerous items that must be freed later
8659 */
8660static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8661{
8662 u32 trans_support;
e1f7de0c
MG		 8663 unsigned long transMethod = CFGTBL_Trans_Performant |
8664 CFGTBL_Trans_use_short_tags;
105a3dbc 8665 int i, rc;
6c311b57 8666
02ec19c8 8667 if (hpsa_simple_mode)
105a3dbc 8668 return 0;
02ec19c8 8669
67c99a72 8670 trans_support = readl(&(h->cfgtable->TransportSupport));
8671 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8672 return 0;
67c99a72 8673
e1f7de0c
MG		 8674 /* Check for I/O accelerator mode support */
8675 if (trans_support & CFGTBL_Trans_io_accel1) {
8676 transMethod |= CFGTBL_Trans_io_accel1 |
8677 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8678 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8679 if (rc)
8680 return rc;
8681 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8682 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8683 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8684 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8685 if (rc)
8686 return rc;
e1f7de0c
MG		 8687 }
8688
eee0f03a 8689 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8690 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8691 /* Performant mode ring buffer and supporting data structures */
072b0518 8692 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8693
254f796b 8694 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8695 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8696 h->reply_queue_size,
8697 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8698 if (!h->reply_queue[i].head) {
8699 rc = -ENOMEM;
8700 goto clean1; /* rq, ioaccel */
8701 }
254f796b
MG		 8702 h->reply_queue[i].size = h->max_commands;
8703 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8704 h->reply_queue[i].current_entry = 0;
8705 }
8706
6c311b57 8707 /* Need a block fetch table for performant mode */
d66ae08b 8708 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8709 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8710 if (!h->blockFetchTable) {
8711 rc = -ENOMEM;
8712 goto clean1; /* rq, ioaccel */
8713 }
6c311b57 8714
105a3dbc
RE		 8715 rc = hpsa_enter_performant_mode(h, trans_support);
8716 if (rc)
8717 goto clean2; /* bft, rq, ioaccel */
8718 return 0;
303932fd 8719
105a3dbc 8720clean2: /* bft, rq, ioaccel */
303932fd 8721 kfree(h->blockFetchTable);
105a3dbc
RE		 8722 h->blockFetchTable = NULL;
8723clean1: /* rq, ioaccel */
8724 hpsa_free_reply_queues(h);
8725 hpsa_free_ioaccel1_cmd_and_bft(h);
8726 hpsa_free_ioaccel2_cmd_and_bft(h);
8727 return rc;
303932fd
DB		 8728}
8729
23100dd9 8730static int is_accelerated_cmd(struct CommandList *c)
76438d08 8731{
23100dd9
SC		 8732 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8733}
8734
8735static void hpsa_drain_accel_commands(struct ctlr_info *h)
8736{
8737 struct CommandList *c = NULL;
f2405db8 8738 int i, accel_cmds_out;
281a7fd0 8739 int refcount;
76438d08 8740
f2405db8 8741 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8742 accel_cmds_out = 0;
f2405db8 8743 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8744 c = h->cmd_pool + i;
281a7fd0
WS		 8745 refcount = atomic_inc_return(&c->refcount);
8746 if (refcount > 1) /* Command is allocated */
8747 accel_cmds_out += is_accelerated_cmd(c);
8748 cmd_free(h, c);
f2405db8 8749 }
23100dd9 8750 if (accel_cmds_out <= 0)
281a7fd0 8751 break;
76438d08
SC		 8752 msleep(100);
8753 } while (1);
8754}
8755
edd16368
SC		 8756/*
8757 * This is it. Register the PCI driver information for the cards we control
8758 * the OS will call our registered routines when it finds one of our cards.
8759 */
8760static int __init hpsa_init(void)
8761{
31468401 8762 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8763}
8764
8765static void __exit hpsa_cleanup(void)
8766{
8767 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8768}
8769
e1f7de0c
MG		 8770static void __attribute__((unused)) verify_offsets(void)
8771{
dd0e19f3
ST		 8772#define VERIFY_OFFSET(member, offset) \
8773 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8774
8775 VERIFY_OFFSET(structure_size, 0);
8776 VERIFY_OFFSET(volume_blk_size, 4);
8777 VERIFY_OFFSET(volume_blk_cnt, 8);
8778 VERIFY_OFFSET(phys_blk_shift, 16);
8779 VERIFY_OFFSET(parity_rotation_shift, 17);
8780 VERIFY_OFFSET(strip_size, 18);
8781 VERIFY_OFFSET(disk_starting_blk, 20);
8782 VERIFY_OFFSET(disk_blk_cnt, 28);
8783 VERIFY_OFFSET(data_disks_per_row, 36);
8784 VERIFY_OFFSET(metadata_disks_per_row, 38);
8785 VERIFY_OFFSET(row_cnt, 40);
8786 VERIFY_OFFSET(layout_map_count, 42);
8787 VERIFY_OFFSET(flags, 44);
8788 VERIFY_OFFSET(dekindex, 46);
8789 /* VERIFY_OFFSET(reserved, 48 */
8790 VERIFY_OFFSET(data, 64);
8791
8792#undef VERIFY_OFFSET
8793
b66cc250
MM		 8794#define VERIFY_OFFSET(member, offset) \
8795 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8796
8797 VERIFY_OFFSET(IU_type, 0);
8798 VERIFY_OFFSET(direction, 1);
8799 VERIFY_OFFSET(reply_queue, 2);
8800 /* VERIFY_OFFSET(reserved1, 3); */
8801 VERIFY_OFFSET(scsi_nexus, 4);
8802 VERIFY_OFFSET(Tag, 8);
8803 VERIFY_OFFSET(cdb, 16);
8804 VERIFY_OFFSET(cciss_lun, 32);
8805 VERIFY_OFFSET(data_len, 40);
8806 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8807 VERIFY_OFFSET(sg_count, 45);
8808 /* VERIFY_OFFSET(reserved3 */
8809 VERIFY_OFFSET(err_ptr, 48);
8810 VERIFY_OFFSET(err_len, 56);
8811 /* VERIFY_OFFSET(reserved4 */
8812 VERIFY_OFFSET(sg, 64);
8813
8814#undef VERIFY_OFFSET
8815
e1f7de0c
MG		 8816#define VERIFY_OFFSET(member, offset) \
8817 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8818
8819 VERIFY_OFFSET(dev_handle, 0x00);
8820 VERIFY_OFFSET(reserved1, 0x02);
8821 VERIFY_OFFSET(function, 0x03);
8822 VERIFY_OFFSET(reserved2, 0x04);
8823 VERIFY_OFFSET(err_info, 0x0C);
8824 VERIFY_OFFSET(reserved3, 0x10);
8825 VERIFY_OFFSET(err_info_len, 0x12);
8826 VERIFY_OFFSET(reserved4, 0x13);
8827 VERIFY_OFFSET(sgl_offset, 0x14);
8828 VERIFY_OFFSET(reserved5, 0x15);
8829 VERIFY_OFFSET(transfer_len, 0x1C);
8830 VERIFY_OFFSET(reserved6, 0x20);
8831 VERIFY_OFFSET(io_flags, 0x24);
8832 VERIFY_OFFSET(reserved7, 0x26);
8833 VERIFY_OFFSET(LUN, 0x34);
8834 VERIFY_OFFSET(control, 0x3C);
8835 VERIFY_OFFSET(CDB, 0x40);
8836 VERIFY_OFFSET(reserved8, 0x50);
8837 VERIFY_OFFSET(host_context_flags, 0x60);
8838 VERIFY_OFFSET(timeout_sec, 0x62);
8839 VERIFY_OFFSET(ReplyQueue, 0x64);
8840 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8841 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8842 VERIFY_OFFSET(host_addr, 0x70);
8843 VERIFY_OFFSET(CISS_LUN, 0x78);
8844 VERIFY_OFFSET(SG, 0x78 + 8);
8845#undef VERIFY_OFFSET
8846}
8847
edd16368
SC		 8848module_init(hpsa_init);
8849module_exit(hpsa_cleanup);
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