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scsi: mptscsih: Remove bogus interpretation of request->ioprio
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
94c7bc31 3 * Copyright 2016 Microsemi Corporation
1358f6dc
DB		 4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
94c7bc31 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
edd16368
SC		 17 *
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <linux/pci.h>
e5a44df8 24#include <linux/pci-aspm.h>
edd16368
SC		 25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/fs.h>
29#include <linux/timer.h>
edd16368
SC		 30#include <linux/init.h>
31#include <linux/spinlock.h>
edd16368
SC		 32#include <linux/compat.h>
33#include <linux/blktrace_api.h>
34#include <linux/uaccess.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/completion.h>
38#include <linux/moduleparam.h>
39#include <scsi/scsi.h>
40#include <scsi/scsi_cmnd.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_host.h>
667e23d4 43#include <scsi/scsi_tcq.h>
9437ac43 44#include <scsi/scsi_eh.h>
d04e62b9 45#include <scsi/scsi_transport_sas.h>
73153fe5 46#include <scsi/scsi_dbg.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
ec2c3aa9
DB		 59/*
60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
61 * with an optional trailing '-' followed by a byte value (0-255).
62 */
ff54aee4 63#define HPSA_DRIVER_VERSION "3.4.16-0"
edd16368 64#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 65#define HPSA "hpsa"
edd16368 66
007e7aa9
RE		 67/* How long to wait for CISS doorbell communication */
68#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
69#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
70#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
71#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 72#define MAX_IOCTL_CONFIG_WAIT 1000
73
74/*define how many times we will try a command because of bus resets */
75#define MAX_CMD_RETRIES 3
76
77/* Embedded module documentation macros - see modules.h */
78MODULE_AUTHOR("Hewlett-Packard Company");
79MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
80 HPSA_DRIVER_VERSION);
81MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
82MODULE_VERSION(HPSA_DRIVER_VERSION);
83MODULE_LICENSE("GPL");
84
85static int hpsa_allow_any;
86module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
87MODULE_PARM_DESC(hpsa_allow_any,
88 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 89static int hpsa_simple_mode;
90module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
91MODULE_PARM_DESC(hpsa_simple_mode,
92 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 93
94/* define the PCI info for the cards we can control */
95static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
135 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
141 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
145 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
146 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 147 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 148 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 149 {0,}
150};
151
152MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
153
154/* board_id = Subsystem Device ID & Vendor ID
155 * product = Marketing Name for the board
156 * access = Address of the struct of function pointers
157 */
158static struct board_type products[] = {
edd16368
SC		 159 {0x3241103C, "Smart Array P212", &SA5_access},
160 {0x3243103C, "Smart Array P410", &SA5_access},
161 {0x3245103C, "Smart Array P410i", &SA5_access},
162 {0x3247103C, "Smart Array P411", &SA5_access},
163 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 164 {0x324A103C, "Smart Array P712m", &SA5_access},
165 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 166 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 167 {0x3350103C, "Smart Array P222", &SA5_access},
168 {0x3351103C, "Smart Array P420", &SA5_access},
169 {0x3352103C, "Smart Array P421", &SA5_access},
170 {0x3353103C, "Smart Array P822", &SA5_access},
171 {0x3354103C, "Smart Array P420i", &SA5_access},
172 {0x3355103C, "Smart Array P220i", &SA5_access},
173 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 174 {0x1921103C, "Smart Array P830i", &SA5_access},
175 {0x1922103C, "Smart Array P430", &SA5_access},
176 {0x1923103C, "Smart Array P431", &SA5_access},
177 {0x1924103C, "Smart Array P830", &SA5_access},
178 {0x1926103C, "Smart Array P731m", &SA5_access},
179 {0x1928103C, "Smart Array P230i", &SA5_access},
180 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 181 {0x21BD103C, "Smart Array P244br", &SA5_access},
182 {0x21BE103C, "Smart Array P741m", &SA5_access},
183 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
184 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 185 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 186 {0x21C2103C, "Smart Array P440", &SA5_access},
187 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 188 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21C5103C, "Smart Array P841", &SA5_access},
190 {0x21C6103C, "Smart HBA H244br", &SA5_access},
191 {0x21C7103C, "Smart HBA H240", &SA5_access},
192 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 193 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 194 {0x21CA103C, "Smart Array P246br", &SA5_access},
195 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 196 {0x21CC103C, "Smart Array", &SA5_access},
197 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 198 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 199 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 200 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
201 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
202 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
203 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
204 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 205 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
206 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
207 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
208 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
209 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 210 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
211};
212
d04e62b9
KB		 213static struct scsi_transport_template *hpsa_sas_transport_template;
214static int hpsa_add_sas_host(struct ctlr_info *h);
215static void hpsa_delete_sas_host(struct ctlr_info *h);
216static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
217 struct hpsa_scsi_dev_t *device);
218static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
219static struct hpsa_scsi_dev_t
220 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
221 struct sas_rphy *rphy);
222
a58e7e53
WS		 223#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
224static const struct scsi_cmnd hpsa_cmd_busy;
225#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
226static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 227static int number_of_controllers;
228
10f66018
SC		 229static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
230static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 231static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 232
233#ifdef CONFIG_COMPAT
42a91641
DB		 234static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
235 void __user *arg);
edd16368
SC		 236#endif
237
238static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 239static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 240static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
241static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
242 struct scsi_cmnd *scmd);
a2dac136 243static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 244 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 245 int cmd_type);
2c143342 246static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 247#define VPD_PAGE (1 << 8)
b48d9804 248#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 249
f281233d 250static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 251static void hpsa_scan_start(struct Scsi_Host *);
252static int hpsa_scan_finished(struct Scsi_Host *sh,
253 unsigned long elapsed_time);
7c0a0229 254static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 255
256static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 257static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 258static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 259static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 260static void hpsa_slave_destroy(struct scsi_device *sdev);
261
8aa60681 262static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 263static int check_for_unit_attention(struct ctlr_info *h,
264 struct CommandList *c);
265static void check_ioctl_unit_attention(struct ctlr_info *h,
266 struct CommandList *c);
303932fd
DB		 267/* performant mode helper functions */
268static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 269 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 270static void hpsa_free_performant_mode(struct ctlr_info *h);
271static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 272static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 273static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
274 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
275 u64 *cfg_offset);
276static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
277 unsigned long *memory_bar);
278static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
279static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
280 int wait_for_ready);
75167d2c 281static inline void finish_cmd(struct CommandList *c);
c706a795 282static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 283#define BOARD_NOT_READY 0
284#define BOARD_READY 1
23100dd9 285static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 286static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 287static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
288 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 289 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 290static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 291static u32 lockup_detected(struct ctlr_info *h);
292static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 293static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 294static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
295 struct ReportExtendedLUNdata *buf, int bufsize);
8383278d
ST		 296static bool hpsa_vpd_page_supported(struct ctlr_info *h,
297 unsigned char scsi3addr[], u8 page);
34592254 298static int hpsa_luns_changed(struct ctlr_info *h);
ba74fdc4
DB		 299static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
300 struct hpsa_scsi_dev_t *dev,
301 unsigned char *scsi3addr);
edd16368 302
edd16368
SC		 303static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
304{
305 unsigned long *priv = shost_priv(sdev->host);
306 return (struct ctlr_info *) *priv;
307}
308
a23513e8
SC		 309static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
310{
311 unsigned long *priv = shost_priv(sh);
312 return (struct ctlr_info *) *priv;
313}
314
a58e7e53
WS		 315static inline bool hpsa_is_cmd_idle(struct CommandList *c)
316{
317 return c->scsi_cmd == SCSI_CMD_IDLE;
318}
319
d604f533
WS		 320static inline bool hpsa_is_pending_event(struct CommandList *c)
321{
322 return c->abort_pending || c->reset_pending;
323}
324
9437ac43
SC		 325/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
326static void decode_sense_data(const u8 *sense_data, int sense_data_len,
327 u8 *sense_key, u8 *asc, u8 *ascq)
328{
329 struct scsi_sense_hdr sshdr;
330 bool rc;
331
332 *sense_key = -1;
333 *asc = -1;
334 *ascq = -1;
335
336 if (sense_data_len < 1)
337 return;
338
339 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
340 if (rc) {
341 *sense_key = sshdr.sense_key;
342 *asc = sshdr.asc;
343 *ascq = sshdr.ascq;
344 }
345}
346
edd16368
SC		 347static int check_for_unit_attention(struct ctlr_info *h,
348 struct CommandList *c)
349{
9437ac43
SC		 350 u8 sense_key, asc, ascq;
351 int sense_len;
352
353 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
354 sense_len = sizeof(c->err_info->SenseInfo);
355 else
356 sense_len = c->err_info->SenseLen;
357
358 decode_sense_data(c->err_info->SenseInfo, sense_len,
359 &sense_key, &asc, &ascq);
81c27557 360 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 361 return 0;
362
9437ac43 363 switch (asc) {
edd16368 364 case STATE_CHANGED:
9437ac43 365 dev_warn(&h->pdev->dev,
2946e82b
RE		 366 "%s: a state change detected, command retried\n",
367 h->devname);
edd16368
SC		 368 break;
369 case LUN_FAILED:
7f73695a 370 dev_warn(&h->pdev->dev,
2946e82b 371 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 372 break;
373 case REPORT_LUNS_CHANGED:
7f73695a 374 dev_warn(&h->pdev->dev,
2946e82b 375 "%s: report LUN data changed\n", h->devname);
edd16368 376 /*
4f4eb9f1
ST		 377 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
378 * target (array) devices.
edd16368
SC		 379 */
380 break;
381 case POWER_OR_RESET:
2946e82b
RE		 382 dev_warn(&h->pdev->dev,
383 "%s: a power on or device reset detected\n",
384 h->devname);
edd16368
SC		 385 break;
386 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 387 dev_warn(&h->pdev->dev,
388 "%s: unit attention cleared by another initiator\n",
389 h->devname);
edd16368
SC		 390 break;
391 default:
2946e82b
RE		 392 dev_warn(&h->pdev->dev,
393 "%s: unknown unit attention detected\n",
394 h->devname);
edd16368
SC		 395 break;
396 }
397 return 1;
398}
399
852af20a
MB		 400static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
401{
402 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
403 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
404 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
405 return 0;
406 dev_warn(&h->pdev->dev, HPSA "device busy");
407 return 1;
408}
409
e985c58f
SC		 410static u32 lockup_detected(struct ctlr_info *h);
411static ssize_t host_show_lockup_detected(struct device *dev,
412 struct device_attribute *attr, char *buf)
413{
414 int ld;
415 struct ctlr_info *h;
416 struct Scsi_Host *shost = class_to_shost(dev);
417
418 h = shost_to_hba(shost);
419 ld = lockup_detected(h);
420
421 return sprintf(buf, "ld=%d\n", ld);
422}
423
da0697bd
ST		 424static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
425 struct device_attribute *attr,
426 const char *buf, size_t count)
427{
428 int status, len;
429 struct ctlr_info *h;
430 struct Scsi_Host *shost = class_to_shost(dev);
431 char tmpbuf[10];
432
433 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
434 return -EACCES;
435 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
436 strncpy(tmpbuf, buf, len);
437 tmpbuf[len] = '\0';
438 if (sscanf(tmpbuf, "%d", &status) != 1)
439 return -EINVAL;
440 h = shost_to_hba(shost);
441 h->acciopath_status = !!status;
442 dev_warn(&h->pdev->dev,
443 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
444 h->acciopath_status ? "enabled" : "disabled");
445 return count;
446}
447
2ba8bfc8
SC		 448static ssize_t host_store_raid_offload_debug(struct device *dev,
449 struct device_attribute *attr,
450 const char *buf, size_t count)
451{
452 int debug_level, len;
453 struct ctlr_info *h;
454 struct Scsi_Host *shost = class_to_shost(dev);
455 char tmpbuf[10];
456
457 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
458 return -EACCES;
459 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
460 strncpy(tmpbuf, buf, len);
461 tmpbuf[len] = '\0';
462 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
463 return -EINVAL;
464 if (debug_level < 0)
465 debug_level = 0;
466 h = shost_to_hba(shost);
467 h->raid_offload_debug = debug_level;
468 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
469 h->raid_offload_debug);
470 return count;
471}
472
edd16368
SC		 473static ssize_t host_store_rescan(struct device *dev,
474 struct device_attribute *attr,
475 const char *buf, size_t count)
476{
477 struct ctlr_info *h;
478 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 479 h = shost_to_hba(shost);
31468401 480 hpsa_scan_start(h->scsi_host);
edd16368
SC		 481 return count;
482}
483
d28ce020
SC		 484static ssize_t host_show_firmware_revision(struct device *dev,
485 struct device_attribute *attr, char *buf)
486{
487 struct ctlr_info *h;
488 struct Scsi_Host *shost = class_to_shost(dev);
489 unsigned char *fwrev;
490
491 h = shost_to_hba(shost);
492 if (!h->hba_inquiry_data)
493 return 0;
494 fwrev = &h->hba_inquiry_data[32];
495 return snprintf(buf, 20, "%c%c%c%c\n",
496 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
497}
498
94a13649
SC		 499static ssize_t host_show_commands_outstanding(struct device *dev,
500 struct device_attribute *attr, char *buf)
501{
502 struct Scsi_Host *shost = class_to_shost(dev);
503 struct ctlr_info *h = shost_to_hba(shost);
504
0cbf768e
SC		 505 return snprintf(buf, 20, "%d\n",
506 atomic_read(&h->commands_outstanding));
94a13649
SC		 507}
508
745a7a25
SC		 509static ssize_t host_show_transport_mode(struct device *dev,
510 struct device_attribute *attr, char *buf)
511{
512 struct ctlr_info *h;
513 struct Scsi_Host *shost = class_to_shost(dev);
514
515 h = shost_to_hba(shost);
516 return snprintf(buf, 20, "%s\n",
960a30e7 517 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 518 "performant" : "simple");
519}
520
da0697bd
ST		 521static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
522 struct device_attribute *attr, char *buf)
523{
524 struct ctlr_info *h;
525 struct Scsi_Host *shost = class_to_shost(dev);
526
527 h = shost_to_hba(shost);
528 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
529 (h->acciopath_status == 1) ? "enabled" : "disabled");
530}
531
46380786 532/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 533static u32 unresettable_controller[] = {
534 0x324a103C, /* Smart Array P712m */
9b5c48c2 535 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 536 0x3223103C, /* Smart Array P800 */
537 0x3234103C, /* Smart Array P400 */
538 0x3235103C, /* Smart Array P400i */
539 0x3211103C, /* Smart Array E200i */
540 0x3212103C, /* Smart Array E200 */
541 0x3213103C, /* Smart Array E200i */
542 0x3214103C, /* Smart Array E200i */
543 0x3215103C, /* Smart Array E200i */
544 0x3237103C, /* Smart Array E500 */
545 0x323D103C, /* Smart Array P700m */
7af0abbc 546 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 547 0x409C0E11, /* Smart Array 6400 */
548 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 549 0x40700E11, /* Smart Array 5300 */
550 0x40820E11, /* Smart Array 532 */
551 0x40830E11, /* Smart Array 5312 */
552 0x409A0E11, /* Smart Array 641 */
553 0x409B0E11, /* Smart Array 642 */
554 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 555};
556
46380786
SC		 557/* List of controllers which cannot even be soft reset */
558static u32 soft_unresettable_controller[] = {
7af0abbc 559 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 560 0x40700E11, /* Smart Array 5300 */
561 0x40820E11, /* Smart Array 532 */
562 0x40830E11, /* Smart Array 5312 */
563 0x409A0E11, /* Smart Array 641 */
564 0x409B0E11, /* Smart Array 642 */
565 0x40910E11, /* Smart Array 6i */
46380786
SC		 566 /* Exclude 640x boards. These are two pci devices in one slot
567 * which share a battery backed cache module. One controls the
568 * cache, the other accesses the cache through the one that controls
569 * it. If we reset the one controlling the cache, the other will
570 * likely not be happy. Just forbid resetting this conjoined mess.
571 * The 640x isn't really supported by hpsa anyway.
572 */
573 0x409C0E11, /* Smart Array 6400 */
574 0x409D0E11, /* Smart Array 6400 EM */
575};
576
9b5c48c2
SC		 577static u32 needs_abort_tags_swizzled[] = {
578 0x323D103C, /* Smart Array P700m */
579 0x324a103C, /* Smart Array P712m */
580 0x324b103C, /* SmartArray P711m */
581};
582
583static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 584{
585 int i;
586
9b5c48c2
SC		 587 for (i = 0; i < nelems; i++)
588 if (a[i] == board_id)
589 return 1;
590 return 0;
46380786
SC		 591}
592
9b5c48c2 593static int ctlr_is_hard_resettable(u32 board_id)
46380786 594{
9b5c48c2
SC		 595 return !board_id_in_array(unresettable_controller,
596 ARRAY_SIZE(unresettable_controller), board_id);
597}
46380786 598
9b5c48c2
SC		 599static int ctlr_is_soft_resettable(u32 board_id)
600{
601 return !board_id_in_array(soft_unresettable_controller,
602 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 603}
604
46380786
SC		 605static int ctlr_is_resettable(u32 board_id)
606{
607 return ctlr_is_hard_resettable(board_id) ||
608 ctlr_is_soft_resettable(board_id);
609}
610
9b5c48c2
SC		 611static int ctlr_needs_abort_tags_swizzled(u32 board_id)
612{
613 return board_id_in_array(needs_abort_tags_swizzled,
614 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
615}
616
941b1cda
SC		 617static ssize_t host_show_resettable(struct device *dev,
618 struct device_attribute *attr, char *buf)
619{
620 struct ctlr_info *h;
621 struct Scsi_Host *shost = class_to_shost(dev);
622
623 h = shost_to_hba(shost);
46380786 624 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 625}
626
edd16368
SC		 627static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
628{
629 return (scsi3addr[3] & 0xC0) == 0x40;
630}
631
f2ef0ce7 632static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 633 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 634};
6b80b18f
ST		 635#define HPSA_RAID_0 0
636#define HPSA_RAID_4 1
637#define HPSA_RAID_1 2 /* also used for RAID 10 */
638#define HPSA_RAID_5 3 /* also used for RAID 50 */
639#define HPSA_RAID_51 4
640#define HPSA_RAID_6 5 /* also used for RAID 60 */
641#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 642#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
643#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 644
f3f01730
KB		 645static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
646{
647 return !device->physical_device;
648}
edd16368
SC		 649
650static ssize_t raid_level_show(struct device *dev,
651 struct device_attribute *attr, char *buf)
652{
653 ssize_t l = 0;
82a72c0a 654 unsigned char rlevel;
edd16368
SC		 655 struct ctlr_info *h;
656 struct scsi_device *sdev;
657 struct hpsa_scsi_dev_t *hdev;
658 unsigned long flags;
659
660 sdev = to_scsi_device(dev);
661 h = sdev_to_hba(sdev);
662 spin_lock_irqsave(&h->lock, flags);
663 hdev = sdev->hostdata;
664 if (!hdev) {
665 spin_unlock_irqrestore(&h->lock, flags);
666 return -ENODEV;
667 }
668
669 /* Is this even a logical drive? */
f3f01730 670 if (!is_logical_device(hdev)) {
edd16368
SC		 671 spin_unlock_irqrestore(&h->lock, flags);
672 l = snprintf(buf, PAGE_SIZE, "N/A\n");
673 return l;
674 }
675
676 rlevel = hdev->raid_level;
677 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 678 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 679 rlevel = RAID_UNKNOWN;
680 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
681 return l;
682}
683
684static ssize_t lunid_show(struct device *dev,
685 struct device_attribute *attr, char *buf)
686{
687 struct ctlr_info *h;
688 struct scsi_device *sdev;
689 struct hpsa_scsi_dev_t *hdev;
690 unsigned long flags;
691 unsigned char lunid[8];
692
693 sdev = to_scsi_device(dev);
694 h = sdev_to_hba(sdev);
695 spin_lock_irqsave(&h->lock, flags);
696 hdev = sdev->hostdata;
697 if (!hdev) {
698 spin_unlock_irqrestore(&h->lock, flags);
699 return -ENODEV;
700 }
701 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
702 spin_unlock_irqrestore(&h->lock, flags);
703 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
704 lunid[0], lunid[1], lunid[2], lunid[3],
705 lunid[4], lunid[5], lunid[6], lunid[7]);
706}
707
708static ssize_t unique_id_show(struct device *dev,
709 struct device_attribute *attr, char *buf)
710{
711 struct ctlr_info *h;
712 struct scsi_device *sdev;
713 struct hpsa_scsi_dev_t *hdev;
714 unsigned long flags;
715 unsigned char sn[16];
716
717 sdev = to_scsi_device(dev);
718 h = sdev_to_hba(sdev);
719 spin_lock_irqsave(&h->lock, flags);
720 hdev = sdev->hostdata;
721 if (!hdev) {
722 spin_unlock_irqrestore(&h->lock, flags);
723 return -ENODEV;
724 }
725 memcpy(sn, hdev->device_id, sizeof(sn));
726 spin_unlock_irqrestore(&h->lock, flags);
727 return snprintf(buf, 16 * 2 + 2,
728 "%02X%02X%02X%02X%02X%02X%02X%02X"
729 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
730 sn[0], sn[1], sn[2], sn[3],
731 sn[4], sn[5], sn[6], sn[7],
732 sn[8], sn[9], sn[10], sn[11],
733 sn[12], sn[13], sn[14], sn[15]);
734}
735
ded1be4a
JH		 736static ssize_t sas_address_show(struct device *dev,
737 struct device_attribute *attr, char *buf)
738{
739 struct ctlr_info *h;
740 struct scsi_device *sdev;
741 struct hpsa_scsi_dev_t *hdev;
742 unsigned long flags;
743 u64 sas_address;
744
745 sdev = to_scsi_device(dev);
746 h = sdev_to_hba(sdev);
747 spin_lock_irqsave(&h->lock, flags);
748 hdev = sdev->hostdata;
749 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
750 spin_unlock_irqrestore(&h->lock, flags);
751 return -ENODEV;
752 }
753 sas_address = hdev->sas_address;
754 spin_unlock_irqrestore(&h->lock, flags);
755
756 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
757}
758
c1988684
ST		 759static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
760 struct device_attribute *attr, char *buf)
761{
762 struct ctlr_info *h;
763 struct scsi_device *sdev;
764 struct hpsa_scsi_dev_t *hdev;
765 unsigned long flags;
766 int offload_enabled;
767
768 sdev = to_scsi_device(dev);
769 h = sdev_to_hba(sdev);
770 spin_lock_irqsave(&h->lock, flags);
771 hdev = sdev->hostdata;
772 if (!hdev) {
773 spin_unlock_irqrestore(&h->lock, flags);
774 return -ENODEV;
775 }
776 offload_enabled = hdev->offload_enabled;
777 spin_unlock_irqrestore(&h->lock, flags);
778 return snprintf(buf, 20, "%d\n", offload_enabled);
779}
780
8270b862 781#define MAX_PATHS 8
8270b862
JH		 782static ssize_t path_info_show(struct device *dev,
783 struct device_attribute *attr, char *buf)
784{
785 struct ctlr_info *h;
786 struct scsi_device *sdev;
787 struct hpsa_scsi_dev_t *hdev;
788 unsigned long flags;
789 int i;
790 int output_len = 0;
791 u8 box;
792 u8 bay;
793 u8 path_map_index = 0;
794 char *active;
795 unsigned char phys_connector[2];
8270b862 796
8270b862
JH		 797 sdev = to_scsi_device(dev);
798 h = sdev_to_hba(sdev);
799 spin_lock_irqsave(&h->devlock, flags);
800 hdev = sdev->hostdata;
801 if (!hdev) {
802 spin_unlock_irqrestore(&h->devlock, flags);
803 return -ENODEV;
804 }
805
806 bay = hdev->bay;
807 for (i = 0; i < MAX_PATHS; i++) {
808 path_map_index = 1<<i;
809 if (i == hdev->active_path_index)
810 active = "Active";
811 else if (hdev->path_map & path_map_index)
812 active = "Inactive";
813 else
814 continue;
815
1faf072c
RV		 816 output_len += scnprintf(buf + output_len,
817 PAGE_SIZE - output_len,
818 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 819 h->scsi_host->host_no,
820 hdev->bus, hdev->target, hdev->lun,
821 scsi_device_type(hdev->devtype));
822
cca8f13b 823 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 824 output_len += scnprintf(buf + output_len,
1faf072c
RV		 825 PAGE_SIZE - output_len,
826 "%s\n", active);
8270b862
JH		 827 continue;
828 }
829
830 box = hdev->box[i];
831 memcpy(&phys_connector, &hdev->phys_connector[i],
832 sizeof(phys_connector));
833 if (phys_connector[0] < '0')
834 phys_connector[0] = '0';
835 if (phys_connector[1] < '0')
836 phys_connector[1] = '0';
cca8f13b 837 output_len += scnprintf(buf + output_len,
1faf072c 838 PAGE_SIZE - output_len,
8270b862
JH		 839 "PORT: %.2s ",
840 phys_connector);
af15ed36
DB		 841 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
842 hdev->expose_device) {
8270b862 843 if (box == 0 || box == 0xFF) {
2708f295 844 output_len += scnprintf(buf + output_len,
1faf072c 845 PAGE_SIZE - output_len,
8270b862
JH		 846 "BAY: %hhu %s\n",
847 bay, active);
848 } else {
2708f295 849 output_len += scnprintf(buf + output_len,
1faf072c 850 PAGE_SIZE - output_len,
8270b862
JH		 851 "BOX: %hhu BAY: %hhu %s\n",
852 box, bay, active);
853 }
854 } else if (box != 0 && box != 0xFF) {
2708f295 855 output_len += scnprintf(buf + output_len,
1faf072c 856 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 857 box, active);
858 } else
2708f295 859 output_len += scnprintf(buf + output_len,
1faf072c 860 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 861 }
862
863 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 864 return output_len;
8270b862
JH		 865}
866
3f5eac3a
SC		 867static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
868static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
869static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
870static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
ded1be4a 871static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL);
c1988684
ST		 872static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
873 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 874static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 875static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
876 host_show_hp_ssd_smart_path_status,
877 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 878static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
879 host_store_raid_offload_debug);
3f5eac3a
SC		 880static DEVICE_ATTR(firmware_revision, S_IRUGO,
881 host_show_firmware_revision, NULL);
882static DEVICE_ATTR(commands_outstanding, S_IRUGO,
883 host_show_commands_outstanding, NULL);
884static DEVICE_ATTR(transport_mode, S_IRUGO,
885 host_show_transport_mode, NULL);
941b1cda
SC		 886static DEVICE_ATTR(resettable, S_IRUGO,
887 host_show_resettable, NULL);
e985c58f
SC		 888static DEVICE_ATTR(lockup_detected, S_IRUGO,
889 host_show_lockup_detected, NULL);
3f5eac3a
SC		 890
891static struct device_attribute *hpsa_sdev_attrs[] = {
892 &dev_attr_raid_level,
893 &dev_attr_lunid,
894 &dev_attr_unique_id,
c1988684 895 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 896 &dev_attr_path_info,
ded1be4a 897 &dev_attr_sas_address,
3f5eac3a
SC		 898 NULL,
899};
900
901static struct device_attribute *hpsa_shost_attrs[] = {
902 &dev_attr_rescan,
903 &dev_attr_firmware_revision,
904 &dev_attr_commands_outstanding,
905 &dev_attr_transport_mode,
941b1cda 906 &dev_attr_resettable,
da0697bd 907 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 908 &dev_attr_raid_offload_debug,
fb53c439 909 &dev_attr_lockup_detected,
3f5eac3a
SC		 910 NULL,
911};
912
41ce4c35
SC		 913#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
914 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
915
3f5eac3a
SC		 916static struct scsi_host_template hpsa_driver_template = {
917 .module = THIS_MODULE,
f79cfec6
SC		 918 .name = HPSA,
919 .proc_name = HPSA,
3f5eac3a
SC		 920 .queuecommand = hpsa_scsi_queue_command,
921 .scan_start = hpsa_scan_start,
922 .scan_finished = hpsa_scan_finished,
7c0a0229 923 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 924 .this_id = -1,
925 .use_clustering = ENABLE_CLUSTERING,
75167d2c 926 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 927 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
928 .ioctl = hpsa_ioctl,
929 .slave_alloc = hpsa_slave_alloc,
41ce4c35 930 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 931 .slave_destroy = hpsa_slave_destroy,
932#ifdef CONFIG_COMPAT
933 .compat_ioctl = hpsa_compat_ioctl,
934#endif
935 .sdev_attrs = hpsa_sdev_attrs,
936 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 937 .max_sectors = 8192,
54b2b50c 938 .no_write_same = 1,
3f5eac3a
SC		 939};
940
254f796b 941static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 942{
943 u32 a;
072b0518 944 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 945
e1f7de0c
MG		 946 if (h->transMethod & CFGTBL_Trans_io_accel1)
947 return h->access.command_completed(h, q);
948
3f5eac3a 949 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 950 return h->access.command_completed(h, q);
3f5eac3a 951
254f796b
MG		 952 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
953 a = rq->head[rq->current_entry];
954 rq->current_entry++;
0cbf768e 955 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 956 } else {
957 a = FIFO_EMPTY;
958 }
959 /* Check for wraparound */
254f796b
MG		 960 if (rq->current_entry == h->max_commands) {
961 rq->current_entry = 0;
962 rq->wraparound ^= 1;
3f5eac3a
SC		 963 }
964 return a;
965}
966
c349775e
ST		 967/*
968 * There are some special bits in the bus address of the
969 * command that we have to set for the controller to know
970 * how to process the command:
971 *
972 * Normal performant mode:
973 * bit 0: 1 means performant mode, 0 means simple mode.
974 * bits 1-3 = block fetch table entry
975 * bits 4-6 = command type (== 0)
976 *
977 * ioaccel1 mode:
978 * bit 0 = "performant mode" bit.
979 * bits 1-3 = block fetch table entry
980 * bits 4-6 = command type (== 110)
981 * (command type is needed because ioaccel1 mode
982 * commands are submitted through the same register as normal
983 * mode commands, so this is how the controller knows whether
984 * the command is normal mode or ioaccel1 mode.)
985 *
986 * ioaccel2 mode:
987 * bit 0 = "performant mode" bit.
988 * bits 1-4 = block fetch table entry (note extra bit)
989 * bits 4-6 = not needed, because ioaccel2 mode has
990 * a separate special register for submitting commands.
991 */
992
25163bd5
WS		 993/*
994 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 995 * set bit 0 for pull model, bits 3-1 for block fetch
996 * register number
997 */
25163bd5
WS		 998#define DEFAULT_REPLY_QUEUE (-1)
999static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
1000 int reply_queue)
3f5eac3a 1001{
254f796b 1002 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 1003 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 1004 if (unlikely(!h->msix_vector))
1005 return;
1006 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 1007 c->Header.ReplyQueue =
804a5cb5 1008 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 1009 else
1010 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 1011 }
3f5eac3a
SC		 1012}
1013
c349775e 1014static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1015 struct CommandList *c,
1016 int reply_queue)
c349775e
ST		 1017{
1018 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
1019
25163bd5
WS		 1020 /*
1021 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1022 * processor. This seems to give the best I/O throughput.
1023 */
25163bd5
WS		 1024 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1025 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
1026 else
1027 cp->ReplyQueue = reply_queue % h->nreply_queues;
1028 /*
1029 * Set the bits in the address sent down to include:
c349775e
ST		 1030 * - performant mode bit (bit 0)
1031 * - pull count (bits 1-3)
1032 * - command type (bits 4-6)
1033 */
1034 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1035 IOACCEL1_BUSADDR_CMDTYPE;
1036}
1037
8be986cc
SC		 1038static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1039 struct CommandList *c,
1040 int reply_queue)
1041{
1042 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1043 &h->ioaccel2_cmd_pool[c->cmdindex];
1044
1045 /* Tell the controller to post the reply to the queue for this
1046 * processor. This seems to give the best I/O throughput.
1047 */
1048 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1049 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1050 else
1051 cp->reply_queue = reply_queue % h->nreply_queues;
1052 /* Set the bits in the address sent down to include:
1053 * - performant mode bit not used in ioaccel mode 2
1054 * - pull count (bits 0-3)
1055 * - command type isn't needed for ioaccel2
1056 */
1057 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1058}
1059
c349775e 1060static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1061 struct CommandList *c,
1062 int reply_queue)
c349775e
ST		 1063{
1064 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1065
25163bd5
WS		 1066 /*
1067 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1068 * processor. This seems to give the best I/O throughput.
1069 */
25163bd5
WS		 1070 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1071 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1072 else
1073 cp->reply_queue = reply_queue % h->nreply_queues;
1074 /*
1075 * Set the bits in the address sent down to include:
c349775e
ST		 1076 * - performant mode bit not used in ioaccel mode 2
1077 * - pull count (bits 0-3)
1078 * - command type isn't needed for ioaccel2
1079 */
1080 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1081}
1082
e85c5974
SC		 1083static int is_firmware_flash_cmd(u8 *cdb)
1084{
1085 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1086}
1087
1088/*
1089 * During firmware flash, the heartbeat register may not update as frequently
1090 * as it should. So we dial down lockup detection during firmware flash. and
1091 * dial it back up when firmware flash completes.
1092 */
1093#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1094#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1095static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1096 struct CommandList *c)
1097{
1098 if (!is_firmware_flash_cmd(c->Request.CDB))
1099 return;
1100 atomic_inc(&h->firmware_flash_in_progress);
1101 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1102}
1103
1104static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1105 struct CommandList *c)
1106{
1107 if (is_firmware_flash_cmd(c->Request.CDB) &&
1108 atomic_dec_and_test(&h->firmware_flash_in_progress))
1109 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1110}
1111
25163bd5
WS		 1112static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1113 struct CommandList *c, int reply_queue)
3f5eac3a 1114{
c05e8866
SC		 1115 dial_down_lockup_detection_during_fw_flash(h, c);
1116 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1117 switch (c->cmd_type) {
1118 case CMD_IOACCEL1:
25163bd5 1119 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1120 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1121 break;
1122 case CMD_IOACCEL2:
25163bd5 1123 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1124 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1125 break;
8be986cc
SC		 1126 case IOACCEL2_TMF:
1127 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1128 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1129 break;
c349775e 1130 default:
25163bd5 1131 set_performant_mode(h, c, reply_queue);
c05e8866 1132 h->access.submit_command(h, c);
c349775e 1133 }
3f5eac3a
SC		 1134}
1135
a58e7e53 1136static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1137{
d604f533 1138 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1139 return finish_cmd(c);
1140
25163bd5
WS		 1141 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1142}
1143
3f5eac3a
SC		 1144static inline int is_hba_lunid(unsigned char scsi3addr[])
1145{
1146 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1147}
1148
1149static inline int is_scsi_rev_5(struct ctlr_info *h)
1150{
1151 if (!h->hba_inquiry_data)
1152 return 0;
1153 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1154 return 1;
1155 return 0;
1156}
1157
edd16368
SC		 1158static int hpsa_find_target_lun(struct ctlr_info *h,
1159 unsigned char scsi3addr[], int bus, int *target, int *lun)
1160{
1161 /* finds an unused bus, target, lun for a new physical device
1162 * assumes h->devlock is held
1163 */
1164 int i, found = 0;
cfe5badc 1165 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1166
263d9401 1167 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1168
1169 for (i = 0; i < h->ndevices; i++) {
1170 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1171 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1172 }
1173
263d9401
AM		 1174 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1175 if (i < HPSA_MAX_DEVICES) {
1176 /* *bus = 1; */
1177 *target = i;
1178 *lun = 0;
1179 found = 1;
edd16368
SC		 1180 }
1181 return !found;
1182}
1183
1d33d85d 1184static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1185 struct hpsa_scsi_dev_t *dev, char *description)
1186{
7c59a0d4
DB		 1187#define LABEL_SIZE 25
1188 char label[LABEL_SIZE];
1189
9975ec9d
DB		 1190 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1191 return;
1192
7c59a0d4
DB		 1193 switch (dev->devtype) {
1194 case TYPE_RAID:
1195 snprintf(label, LABEL_SIZE, "controller");
1196 break;
1197 case TYPE_ENCLOSURE:
1198 snprintf(label, LABEL_SIZE, "enclosure");
1199 break;
1200 case TYPE_DISK:
af15ed36 1201 case TYPE_ZBC:
7c59a0d4
DB		 1202 if (dev->external)
1203 snprintf(label, LABEL_SIZE, "external");
1204 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1205 snprintf(label, LABEL_SIZE, "%s",
1206 raid_label[PHYSICAL_DRIVE]);
1207 else
1208 snprintf(label, LABEL_SIZE, "RAID-%s",
1209 dev->raid_level > RAID_UNKNOWN ? "?" :
1210 raid_label[dev->raid_level]);
1211 break;
1212 case TYPE_ROM:
1213 snprintf(label, LABEL_SIZE, "rom");
1214 break;
1215 case TYPE_TAPE:
1216 snprintf(label, LABEL_SIZE, "tape");
1217 break;
1218 case TYPE_MEDIUM_CHANGER:
1219 snprintf(label, LABEL_SIZE, "changer");
1220 break;
1221 default:
1222 snprintf(label, LABEL_SIZE, "UNKNOWN");
1223 break;
1224 }
1225
0d96ef5f 1226 dev_printk(level, &h->pdev->dev,
7c59a0d4 1227 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1228 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1229 description,
1230 scsi_device_type(dev->devtype),
1231 dev->vendor,
1232 dev->model,
7c59a0d4 1233 label,
0d96ef5f
WS		 1234 dev->offload_config ? '+' : '-',
1235 dev->offload_enabled ? '+' : '-',
2a168208 1236 dev->expose_device);
0d96ef5f
WS		 1237}
1238
edd16368 1239/* Add an entry into h->dev[] array. */
8aa60681 1240static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1241 struct hpsa_scsi_dev_t *device,
1242 struct hpsa_scsi_dev_t *added[], int *nadded)
1243{
1244 /* assumes h->devlock is held */
1245 int n = h->ndevices;
1246 int i;
1247 unsigned char addr1[8], addr2[8];
1248 struct hpsa_scsi_dev_t *sd;
1249
cfe5badc 1250 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1251 dev_err(&h->pdev->dev, "too many devices, some will be "
1252 "inaccessible.\n");
1253 return -1;
1254 }
1255
1256 /* physical devices do not have lun or target assigned until now. */
1257 if (device->lun != -1)
1258 /* Logical device, lun is already assigned. */
1259 goto lun_assigned;
1260
1261 /* If this device a non-zero lun of a multi-lun device
1262 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1263 * unit no, zero otherwise.
edd16368
SC		 1264 */
1265 if (device->scsi3addr[4] == 0) {
1266 /* This is not a non-zero lun of a multi-lun device */
1267 if (hpsa_find_target_lun(h, device->scsi3addr,
1268 device->bus, &device->target, &device->lun) != 0)
1269 return -1;
1270 goto lun_assigned;
1271 }
1272
1273 /* This is a non-zero lun of a multi-lun device.
1274 * Search through our list and find the device which
9a4178b7 1275 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1276 * Assign the same bus and target for this new LUN.
1277 * Use the logical unit number from the firmware.
1278 */
1279 memcpy(addr1, device->scsi3addr, 8);
1280 addr1[4] = 0;
9a4178b7 1281 addr1[5] = 0;
edd16368
SC		 1282 for (i = 0; i < n; i++) {
1283 sd = h->dev[i];
1284 memcpy(addr2, sd->scsi3addr, 8);
1285 addr2[4] = 0;
9a4178b7 1286 addr2[5] = 0;
1287 /* differ only in byte 4 and 5? */
edd16368
SC		 1288 if (memcmp(addr1, addr2, 8) == 0) {
1289 device->bus = sd->bus;
1290 device->target = sd->target;
1291 device->lun = device->scsi3addr[4];
1292 break;
1293 }
1294 }
1295 if (device->lun == -1) {
1296 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1297 " suspect firmware bug or unsupported hardware "
1298 "configuration.\n");
1299 return -1;
1300 }
1301
1302lun_assigned:
1303
1304 h->dev[n] = device;
1305 h->ndevices++;
1306 added[*nadded] = device;
1307 (*nadded)++;
0d96ef5f 1308 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1309 device->expose_device ? "added" : "masked");
a473d86c
RE		 1310 device->offload_to_be_enabled = device->offload_enabled;
1311 device->offload_enabled = 0;
edd16368
SC		 1312 return 0;
1313}
1314
bd9244f7 1315/* Update an entry in h->dev[] array. */
8aa60681 1316static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1317 int entry, struct hpsa_scsi_dev_t *new_entry)
1318{
a473d86c 1319 int offload_enabled;
bd9244f7
ST		 1320 /* assumes h->devlock is held */
1321 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1322
1323 /* Raid level changed. */
1324 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1325
03383736
DB		 1326 /* Raid offload parameters changed. Careful about the ordering. */
1327 if (new_entry->offload_config && new_entry->offload_enabled) {
1328 /*
1329 * if drive is newly offload_enabled, we want to copy the
1330 * raid map data first. If previously offload_enabled and
1331 * offload_config were set, raid map data had better be
1332 * the same as it was before. if raid map data is changed
1333 * then it had better be the case that
1334 * h->dev[entry]->offload_enabled is currently 0.
1335 */
1336 h->dev[entry]->raid_map = new_entry->raid_map;
1337 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1338 }
a3144e0b
JH		 1339 if (new_entry->hba_ioaccel_enabled) {
1340 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1341 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1342 }
1343 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1344 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1345 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1346 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1347
41ce4c35
SC		 1348 /*
1349 * We can turn off ioaccel offload now, but need to delay turning
1350 * it on until we can update h->dev[entry]->phys_disk[], but we
1351 * can't do that until all the devices are updated.
1352 */
1353 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1354 if (!new_entry->offload_enabled)
1355 h->dev[entry]->offload_enabled = 0;
1356
a473d86c
RE		 1357 offload_enabled = h->dev[entry]->offload_enabled;
1358 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1359 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1360 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1361}
1362
2a8ccf31 1363/* Replace an entry from h->dev[] array. */
8aa60681 1364static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1365 int entry, struct hpsa_scsi_dev_t *new_entry,
1366 struct hpsa_scsi_dev_t *added[], int *nadded,
1367 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1368{
1369 /* assumes h->devlock is held */
cfe5badc 1370 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1371 removed[*nremoved] = h->dev[entry];
1372 (*nremoved)++;
01350d05
SC		 1373
1374 /*
1375 * New physical devices won't have target/lun assigned yet
1376 * so we need to preserve the values in the slot we are replacing.
1377 */
1378 if (new_entry->target == -1) {
1379 new_entry->target = h->dev[entry]->target;
1380 new_entry->lun = h->dev[entry]->lun;
1381 }
1382
2a8ccf31
SC		 1383 h->dev[entry] = new_entry;
1384 added[*nadded] = new_entry;
1385 (*nadded)++;
0d96ef5f 1386 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1387 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1388 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1389}
1390
edd16368 1391/* Remove an entry from h->dev[] array. */
8aa60681 1392static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1393 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1394{
1395 /* assumes h->devlock is held */
1396 int i;
1397 struct hpsa_scsi_dev_t *sd;
1398
cfe5badc 1399 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1400
1401 sd = h->dev[entry];
1402 removed[*nremoved] = h->dev[entry];
1403 (*nremoved)++;
1404
1405 for (i = entry; i < h->ndevices-1; i++)
1406 h->dev[i] = h->dev[i+1];
1407 h->ndevices--;
0d96ef5f 1408 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1409}
1410
1411#define SCSI3ADDR_EQ(a, b) ( \
1412 (a)[7] == (b)[7] && \
1413 (a)[6] == (b)[6] && \
1414 (a)[5] == (b)[5] && \
1415 (a)[4] == (b)[4] && \
1416 (a)[3] == (b)[3] && \
1417 (a)[2] == (b)[2] && \
1418 (a)[1] == (b)[1] && \
1419 (a)[0] == (b)[0])
1420
1421static void fixup_botched_add(struct ctlr_info *h,
1422 struct hpsa_scsi_dev_t *added)
1423{
1424 /* called when scsi_add_device fails in order to re-adjust
1425 * h->dev[] to match the mid layer's view.
1426 */
1427 unsigned long flags;
1428 int i, j;
1429
1430 spin_lock_irqsave(&h->lock, flags);
1431 for (i = 0; i < h->ndevices; i++) {
1432 if (h->dev[i] == added) {
1433 for (j = i; j < h->ndevices-1; j++)
1434 h->dev[j] = h->dev[j+1];
1435 h->ndevices--;
1436 break;
1437 }
1438 }
1439 spin_unlock_irqrestore(&h->lock, flags);
1440 kfree(added);
1441}
1442
1443static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1444 struct hpsa_scsi_dev_t *dev2)
1445{
edd16368
SC		 1446 /* we compare everything except lun and target as these
1447 * are not yet assigned. Compare parts likely
1448 * to differ first
1449 */
1450 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1451 sizeof(dev1->scsi3addr)) != 0)
1452 return 0;
1453 if (memcmp(dev1->device_id, dev2->device_id,
1454 sizeof(dev1->device_id)) != 0)
1455 return 0;
1456 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1457 return 0;
1458 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1459 return 0;
edd16368
SC		 1460 if (dev1->devtype != dev2->devtype)
1461 return 0;
edd16368
SC		 1462 if (dev1->bus != dev2->bus)
1463 return 0;
1464 return 1;
1465}
1466
bd9244f7
ST		 1467static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1468 struct hpsa_scsi_dev_t *dev2)
1469{
1470 /* Device attributes that can change, but don't mean
1471 * that the device is a different device, nor that the OS
1472 * needs to be told anything about the change.
1473 */
1474 if (dev1->raid_level != dev2->raid_level)
1475 return 1;
250fb125
SC		 1476 if (dev1->offload_config != dev2->offload_config)
1477 return 1;
1478 if (dev1->offload_enabled != dev2->offload_enabled)
1479 return 1;
93849508
DB		 1480 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1481 if (dev1->queue_depth != dev2->queue_depth)
1482 return 1;
bd9244f7
ST		 1483 return 0;
1484}
1485
edd16368
SC		 1486/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1487 * and return needle location in *index. If scsi3addr matches, but not
1488 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1489 * location in *index.
1490 * In the case of a minor device attribute change, such as RAID level, just
1491 * return DEVICE_UPDATED, along with the updated device's location in index.
1492 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1493 */
1494static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1495 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1496 int *index)
1497{
1498 int i;
1499#define DEVICE_NOT_FOUND 0
1500#define DEVICE_CHANGED 1
1501#define DEVICE_SAME 2
bd9244f7 1502#define DEVICE_UPDATED 3
1d33d85d
DB		 1503 if (needle == NULL)
1504 return DEVICE_NOT_FOUND;
1505
edd16368 1506 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1507 if (haystack[i] == NULL) /* previously removed. */
1508 continue;
edd16368
SC		 1509 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1510 *index = i;
bd9244f7
ST		 1511 if (device_is_the_same(needle, haystack[i])) {
1512 if (device_updated(needle, haystack[i]))
1513 return DEVICE_UPDATED;
edd16368 1514 return DEVICE_SAME;
bd9244f7 1515 } else {
9846590e
SC		 1516 /* Keep offline devices offline */
1517 if (needle->volume_offline)
1518 return DEVICE_NOT_FOUND;
edd16368 1519 return DEVICE_CHANGED;
bd9244f7 1520 }
edd16368
SC		 1521 }
1522 }
1523 *index = -1;
1524 return DEVICE_NOT_FOUND;
1525}
1526
9846590e
SC		 1527static void hpsa_monitor_offline_device(struct ctlr_info *h,
1528 unsigned char scsi3addr[])
1529{
1530 struct offline_device_entry *device;
1531 unsigned long flags;
1532
1533 /* Check to see if device is already on the list */
1534 spin_lock_irqsave(&h->offline_device_lock, flags);
1535 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1536 if (memcmp(device->scsi3addr, scsi3addr,
1537 sizeof(device->scsi3addr)) == 0) {
1538 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1539 return;
1540 }
1541 }
1542 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1543
1544 /* Device is not on the list, add it. */
1545 device = kmalloc(sizeof(*device), GFP_KERNEL);
1546 if (!device) {
1547 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1548 return;
1549 }
1550 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1551 spin_lock_irqsave(&h->offline_device_lock, flags);
1552 list_add_tail(&device->offline_list, &h->offline_device_list);
1553 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1554}
1555
1556/* Print a message explaining various offline volume states */
1557static void hpsa_show_volume_status(struct ctlr_info *h,
1558 struct hpsa_scsi_dev_t *sd)
1559{
1560 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1561 dev_info(&h->pdev->dev,
1562 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1563 h->scsi_host->host_no,
1564 sd->bus, sd->target, sd->lun);
1565 switch (sd->volume_offline) {
1566 case HPSA_LV_OK:
1567 break;
1568 case HPSA_LV_UNDERGOING_ERASE:
1569 dev_info(&h->pdev->dev,
1570 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1571 h->scsi_host->host_no,
1572 sd->bus, sd->target, sd->lun);
1573 break;
5ca01204
SB		 1574 case HPSA_LV_NOT_AVAILABLE:
1575 dev_info(&h->pdev->dev,
1576 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1577 h->scsi_host->host_no,
1578 sd->bus, sd->target, sd->lun);
1579 break;
9846590e
SC		 1580 case HPSA_LV_UNDERGOING_RPI:
1581 dev_info(&h->pdev->dev,
5ca01204 1582 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1583 h->scsi_host->host_no,
1584 sd->bus, sd->target, sd->lun);
1585 break;
1586 case HPSA_LV_PENDING_RPI:
1587 dev_info(&h->pdev->dev,
5ca01204
SB		 1588 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1589 h->scsi_host->host_no,
1590 sd->bus, sd->target, sd->lun);
9846590e
SC		 1591 break;
1592 case HPSA_LV_ENCRYPTED_NO_KEY:
1593 dev_info(&h->pdev->dev,
1594 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1595 h->scsi_host->host_no,
1596 sd->bus, sd->target, sd->lun);
1597 break;
1598 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1599 dev_info(&h->pdev->dev,
1600 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1601 h->scsi_host->host_no,
1602 sd->bus, sd->target, sd->lun);
1603 break;
1604 case HPSA_LV_UNDERGOING_ENCRYPTION:
1605 dev_info(&h->pdev->dev,
1606 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1607 h->scsi_host->host_no,
1608 sd->bus, sd->target, sd->lun);
1609 break;
1610 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1611 dev_info(&h->pdev->dev,
1612 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1613 h->scsi_host->host_no,
1614 sd->bus, sd->target, sd->lun);
1615 break;
1616 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1617 dev_info(&h->pdev->dev,
1618 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1619 h->scsi_host->host_no,
1620 sd->bus, sd->target, sd->lun);
1621 break;
1622 case HPSA_LV_PENDING_ENCRYPTION:
1623 dev_info(&h->pdev->dev,
1624 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1625 h->scsi_host->host_no,
1626 sd->bus, sd->target, sd->lun);
1627 break;
1628 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1629 dev_info(&h->pdev->dev,
1630 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1631 h->scsi_host->host_no,
1632 sd->bus, sd->target, sd->lun);
1633 break;
1634 }
1635}
1636
03383736
DB		 1637/*
1638 * Figure the list of physical drive pointers for a logical drive with
1639 * raid offload configured.
1640 */
1641static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1642 struct hpsa_scsi_dev_t *dev[], int ndevices,
1643 struct hpsa_scsi_dev_t *logical_drive)
1644{
1645 struct raid_map_data *map = &logical_drive->raid_map;
1646 struct raid_map_disk_data *dd = &map->data[0];
1647 int i, j;
1648 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1649 le16_to_cpu(map->metadata_disks_per_row);
1650 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1651 le16_to_cpu(map->layout_map_count) *
1652 total_disks_per_row;
1653 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1654 total_disks_per_row;
1655 int qdepth;
1656
1657 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1658 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1659
d604f533
WS		 1660 logical_drive->nphysical_disks = nraid_map_entries;
1661
03383736
DB		 1662 qdepth = 0;
1663 for (i = 0; i < nraid_map_entries; i++) {
1664 logical_drive->phys_disk[i] = NULL;
1665 if (!logical_drive->offload_config)
1666 continue;
1667 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1668 if (dev[j] == NULL)
1669 continue;
ff615f06
PK		 1670 if (dev[j]->devtype != TYPE_DISK &&
1671 dev[j]->devtype != TYPE_ZBC)
af15ed36 1672 continue;
f3f01730 1673 if (is_logical_device(dev[j]))
03383736
DB		 1674 continue;
1675 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1676 continue;
1677
1678 logical_drive->phys_disk[i] = dev[j];
1679 if (i < nphys_disk)
1680 qdepth = min(h->nr_cmds, qdepth +
1681 logical_drive->phys_disk[i]->queue_depth);
1682 break;
1683 }
1684
1685 /*
1686 * This can happen if a physical drive is removed and
1687 * the logical drive is degraded. In that case, the RAID
1688 * map data will refer to a physical disk which isn't actually
1689 * present. And in that case offload_enabled should already
1690 * be 0, but we'll turn it off here just in case
1691 */
1692 if (!logical_drive->phys_disk[i]) {
1693 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1694 logical_drive->offload_to_be_enabled = 0;
1695 logical_drive->queue_depth = 8;
03383736
DB		 1696 }
1697 }
1698 if (nraid_map_entries)
1699 /*
1700 * This is correct for reads, too high for full stripe writes,
1701 * way too high for partial stripe writes
1702 */
1703 logical_drive->queue_depth = qdepth;
1704 else
1705 logical_drive->queue_depth = h->nr_cmds;
1706}
1707
1708static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1709 struct hpsa_scsi_dev_t *dev[], int ndevices)
1710{
1711 int i;
1712
1713 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1714 if (dev[i] == NULL)
1715 continue;
ff615f06
PK		 1716 if (dev[i]->devtype != TYPE_DISK &&
1717 dev[i]->devtype != TYPE_ZBC)
af15ed36 1718 continue;
f3f01730 1719 if (!is_logical_device(dev[i]))
03383736 1720 continue;
41ce4c35
SC		 1721
1722 /*
1723 * If offload is currently enabled, the RAID map and
1724 * phys_disk[] assignment *better* not be changing
1725 * and since it isn't changing, we do not need to
1726 * update it.
1727 */
1728 if (dev[i]->offload_enabled)
1729 continue;
1730
03383736
DB		 1731 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1732 }
1733}
1734
096ccff4
KB		 1735static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1736{
1737 int rc = 0;
1738
1739 if (!h->scsi_host)
1740 return 1;
1741
d04e62b9
KB		 1742 if (is_logical_device(device)) /* RAID */
1743 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1744 device->target, device->lun);
d04e62b9
KB		 1745 else /* HBA */
1746 rc = hpsa_add_sas_device(h->sas_host, device);
1747
096ccff4
KB		 1748 return rc;
1749}
1750
ba74fdc4
DB		 1751static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
1752 struct hpsa_scsi_dev_t *dev)
1753{
1754 int i;
1755 int count = 0;
1756
1757 for (i = 0; i < h->nr_cmds; i++) {
1758 struct CommandList *c = h->cmd_pool + i;
1759 int refcount = atomic_inc_return(&c->refcount);
1760
1761 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
1762 dev->scsi3addr)) {
1763 unsigned long flags;
1764
1765 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
1766 if (!hpsa_is_cmd_idle(c))
1767 ++count;
1768 spin_unlock_irqrestore(&h->lock, flags);
1769 }
1770
1771 cmd_free(h, c);
1772 }
1773
1774 return count;
1775}
1776
1777static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
1778 struct hpsa_scsi_dev_t *device)
1779{
1780 int cmds = 0;
1781 int waits = 0;
1782
1783 while (1) {
1784 cmds = hpsa_find_outstanding_commands_for_dev(h, device);
1785 if (cmds == 0)
1786 break;
1787 if (++waits > 20)
1788 break;
1789 dev_warn(&h->pdev->dev,
1790 "%s: removing device with %d outstanding commands!\n",
1791 __func__, cmds);
1792 msleep(1000);
1793 }
1794}
1795
096ccff4
KB		 1796static void hpsa_remove_device(struct ctlr_info *h,
1797 struct hpsa_scsi_dev_t *device)
1798{
1799 struct scsi_device *sdev = NULL;
1800
1801 if (!h->scsi_host)
1802 return;
1803
d04e62b9
KB		 1804 if (is_logical_device(device)) { /* RAID */
1805 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1806 device->target, device->lun);
d04e62b9
KB		 1807 if (sdev) {
1808 scsi_remove_device(sdev);
1809 scsi_device_put(sdev);
1810 } else {
1811 /*
1812 * We don't expect to get here. Future commands
1813 * to this device will get a selection timeout as
1814 * if the device were gone.
1815 */
1816 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1817 "didn't find device for removal.");
d04e62b9 1818 }
ba74fdc4
DB		 1819 } else { /* HBA */
1820
1821 device->removed = 1;
1822 hpsa_wait_for_outstanding_commands_for_dev(h, device);
1823
d04e62b9 1824 hpsa_remove_sas_device(device);
ba74fdc4 1825 }
096ccff4
KB		 1826}
1827
8aa60681 1828static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1829 struct hpsa_scsi_dev_t *sd[], int nsds)
1830{
1831 /* sd contains scsi3 addresses and devtypes, and inquiry
1832 * data. This function takes what's in sd to be the current
1833 * reality and updates h->dev[] to reflect that reality.
1834 */
1835 int i, entry, device_change, changes = 0;
1836 struct hpsa_scsi_dev_t *csd;
1837 unsigned long flags;
1838 struct hpsa_scsi_dev_t **added, **removed;
1839 int nadded, nremoved;
edd16368 1840
da03ded0
DB		 1841 /*
1842 * A reset can cause a device status to change
1843 * re-schedule the scan to see what happened.
1844 */
1845 if (h->reset_in_progress) {
1846 h->drv_req_rescan = 1;
1847 return;
1848 }
edd16368 1849
cfe5badc
ST		 1850 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1851 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1852
1853 if (!added || !removed) {
1854 dev_warn(&h->pdev->dev, "out of memory in "
1855 "adjust_hpsa_scsi_table\n");
1856 goto free_and_out;
1857 }
1858
1859 spin_lock_irqsave(&h->devlock, flags);
1860
1861 /* find any devices in h->dev[] that are not in
1862 * sd[] and remove them from h->dev[], and for any
1863 * devices which have changed, remove the old device
1864 * info and add the new device info.
bd9244f7
ST		 1865 * If minor device attributes change, just update
1866 * the existing device structure.
edd16368
SC		 1867 */
1868 i = 0;
1869 nremoved = 0;
1870 nadded = 0;
1871 while (i < h->ndevices) {
1872 csd = h->dev[i];
1873 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1874 if (device_change == DEVICE_NOT_FOUND) {
1875 changes++;
8aa60681 1876 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1877 continue; /* remove ^^^, hence i not incremented */
1878 } else if (device_change == DEVICE_CHANGED) {
1879 changes++;
8aa60681 1880 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1881 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1882 /* Set it to NULL to prevent it from being freed
1883 * at the bottom of hpsa_update_scsi_devices()
1884 */
1885 sd[entry] = NULL;
bd9244f7 1886 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1887 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1888 }
1889 i++;
1890 }
1891
1892 /* Now, make sure every device listed in sd[] is also
1893 * listed in h->dev[], adding them if they aren't found
1894 */
1895
1896 for (i = 0; i < nsds; i++) {
1897 if (!sd[i]) /* if already added above. */
1898 continue;
9846590e
SC		 1899
1900 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1901 * as the SCSI mid-layer does not handle such devices well.
1902 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1903 * at 160Hz, and prevents the system from coming up.
1904 */
1905 if (sd[i]->volume_offline) {
1906 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1907 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1908 continue;
1909 }
1910
edd16368
SC		 1911 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1912 h->ndevices, &entry);
1913 if (device_change == DEVICE_NOT_FOUND) {
1914 changes++;
8aa60681 1915 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1916 break;
1917 sd[i] = NULL; /* prevent from being freed later. */
1918 } else if (device_change == DEVICE_CHANGED) {
1919 /* should never happen... */
1920 changes++;
1921 dev_warn(&h->pdev->dev,
1922 "device unexpectedly changed.\n");
1923 /* but if it does happen, we just ignore that device */
1924 }
1925 }
41ce4c35
SC		 1926 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1927
1928 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1929 * any logical drives that need it enabled.
1930 */
1d33d85d
DB		 1931 for (i = 0; i < h->ndevices; i++) {
1932 if (h->dev[i] == NULL)
1933 continue;
41ce4c35 1934 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1935 }
41ce4c35 1936
edd16368
SC		 1937 spin_unlock_irqrestore(&h->devlock, flags);
1938
9846590e
SC		 1939 /* Monitor devices which are in one of several NOT READY states to be
1940 * brought online later. This must be done without holding h->devlock,
1941 * so don't touch h->dev[]
1942 */
1943 for (i = 0; i < nsds; i++) {
1944 if (!sd[i]) /* if already added above. */
1945 continue;
1946 if (sd[i]->volume_offline)
1947 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1948 }
1949
edd16368
SC		 1950 /* Don't notify scsi mid layer of any changes the first time through
1951 * (or if there are no changes) scsi_scan_host will do it later the
1952 * first time through.
1953 */
8aa60681 1954 if (!changes)
edd16368
SC		 1955 goto free_and_out;
1956
edd16368
SC		 1957 /* Notify scsi mid layer of any removed devices */
1958 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1959 if (removed[i] == NULL)
1960 continue;
096ccff4
KB		 1961 if (removed[i]->expose_device)
1962 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1963 kfree(removed[i]);
1964 removed[i] = NULL;
1965 }
1966
1967 /* Notify scsi mid layer of any added devices */
1968 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1969 int rc = 0;
1970
1d33d85d
DB		 1971 if (added[i] == NULL)
1972 continue;
2a168208 1973 if (!(added[i]->expose_device))
41ce4c35 1974 continue;
096ccff4
KB		 1975 rc = hpsa_add_device(h, added[i]);
1976 if (!rc)
edd16368 1977 continue;
096ccff4
KB		 1978 dev_warn(&h->pdev->dev,
1979 "addition failed %d, device not added.", rc);
edd16368
SC		 1980 /* now we have to remove it from h->dev,
1981 * since it didn't get added to scsi mid layer
1982 */
1983 fixup_botched_add(h, added[i]);
853633e8 1984 h->drv_req_rescan = 1;
edd16368
SC		 1985 }
1986
1987free_and_out:
1988 kfree(added);
1989 kfree(removed);
edd16368
SC		 1990}
1991
1992/*
9e03aa2f 1993 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1994 * Assume's h->devlock is held.
1995 */
1996static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1997 int bus, int target, int lun)
1998{
1999 int i;
2000 struct hpsa_scsi_dev_t *sd;
2001
2002 for (i = 0; i < h->ndevices; i++) {
2003 sd = h->dev[i];
2004 if (sd->bus == bus && sd->target == target && sd->lun == lun)
2005 return sd;
2006 }
2007 return NULL;
2008}
2009
edd16368
SC		 2010static int hpsa_slave_alloc(struct scsi_device *sdev)
2011{
2012 struct hpsa_scsi_dev_t *sd;
2013 unsigned long flags;
2014 struct ctlr_info *h;
2015
2016 h = sdev_to_hba(sdev);
2017 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 2018 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
2019 struct scsi_target *starget;
2020 struct sas_rphy *rphy;
2021
2022 starget = scsi_target(sdev);
2023 rphy = target_to_rphy(starget);
2024 sd = hpsa_find_device_by_sas_rphy(h, rphy);
2025 if (sd) {
2026 sd->target = sdev_id(sdev);
2027 sd->lun = sdev->lun;
2028 }
2029 } else
2030 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
2031 sdev_id(sdev), sdev->lun);
2032
2033 if (sd && sd->expose_device) {
03383736 2034 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 2035 sdev->hostdata = sd;
41ce4c35
SC		 2036 } else
2037 sdev->hostdata = NULL;
edd16368
SC		 2038 spin_unlock_irqrestore(&h->devlock, flags);
2039 return 0;
2040}
2041
41ce4c35
SC		 2042/* configure scsi device based on internal per-device structure */
2043static int hpsa_slave_configure(struct scsi_device *sdev)
2044{
2045 struct hpsa_scsi_dev_t *sd;
2046 int queue_depth;
2047
2048 sd = sdev->hostdata;
2a168208 2049 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 2050
2051 if (sd)
2052 queue_depth = sd->queue_depth != 0 ?
2053 sd->queue_depth : sdev->host->can_queue;
2054 else
2055 queue_depth = sdev->host->can_queue;
2056
2057 scsi_change_queue_depth(sdev, queue_depth);
2058
2059 return 0;
2060}
2061
edd16368
SC		 2062static void hpsa_slave_destroy(struct scsi_device *sdev)
2063{
bcc44255 2064 /* nothing to do. */
edd16368
SC		 2065}
2066
d9a729f3
WS		 2067static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2068{
2069 int i;
2070
2071 if (!h->ioaccel2_cmd_sg_list)
2072 return;
2073 for (i = 0; i < h->nr_cmds; i++) {
2074 kfree(h->ioaccel2_cmd_sg_list[i]);
2075 h->ioaccel2_cmd_sg_list[i] = NULL;
2076 }
2077 kfree(h->ioaccel2_cmd_sg_list);
2078 h->ioaccel2_cmd_sg_list = NULL;
2079}
2080
2081static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2082{
2083 int i;
2084
2085 if (h->chainsize <= 0)
2086 return 0;
2087
2088 h->ioaccel2_cmd_sg_list =
2089 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
2090 GFP_KERNEL);
2091 if (!h->ioaccel2_cmd_sg_list)
2092 return -ENOMEM;
2093 for (i = 0; i < h->nr_cmds; i++) {
2094 h->ioaccel2_cmd_sg_list[i] =
2095 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
2096 h->maxsgentries, GFP_KERNEL);
2097 if (!h->ioaccel2_cmd_sg_list[i])
2098 goto clean;
2099 }
2100 return 0;
2101
2102clean:
2103 hpsa_free_ioaccel2_sg_chain_blocks(h);
2104 return -ENOMEM;
2105}
2106
33a2ffce
SC		 2107static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2108{
2109 int i;
2110
2111 if (!h->cmd_sg_list)
2112 return;
2113 for (i = 0; i < h->nr_cmds; i++) {
2114 kfree(h->cmd_sg_list[i]);
2115 h->cmd_sg_list[i] = NULL;
2116 }
2117 kfree(h->cmd_sg_list);
2118 h->cmd_sg_list = NULL;
2119}
2120
105a3dbc 2121static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2122{
2123 int i;
2124
2125 if (h->chainsize <= 0)
2126 return 0;
2127
2128 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
2129 GFP_KERNEL);
3d4e6af8
RE		 2130 if (!h->cmd_sg_list) {
2131 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 2132 return -ENOMEM;
3d4e6af8 2133 }
33a2ffce
SC		 2134 for (i = 0; i < h->nr_cmds; i++) {
2135 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
2136 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 2137 if (!h->cmd_sg_list[i]) {
2138 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 2139 goto clean;
3d4e6af8 2140 }
33a2ffce
SC		 2141 }
2142 return 0;
2143
2144clean:
2145 hpsa_free_sg_chain_blocks(h);
2146 return -ENOMEM;
2147}
2148
d9a729f3
WS		 2149static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2150 struct io_accel2_cmd *cp, struct CommandList *c)
2151{
2152 struct ioaccel2_sg_element *chain_block;
2153 u64 temp64;
2154 u32 chain_size;
2155
2156 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2157 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2158 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2159 PCI_DMA_TODEVICE);
2160 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2161 /* prevent subsequent unmapping */
2162 cp->sg->address = 0;
2163 return -1;
2164 }
2165 cp->sg->address = cpu_to_le64(temp64);
2166 return 0;
2167}
2168
2169static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2170 struct io_accel2_cmd *cp)
2171{
2172 struct ioaccel2_sg_element *chain_sg;
2173 u64 temp64;
2174 u32 chain_size;
2175
2176 chain_sg = cp->sg;
2177 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2178 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2179 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2180}
2181
e2bea6df 2182static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2183 struct CommandList *c)
2184{
2185 struct SGDescriptor *chain_sg, *chain_block;
2186 u64 temp64;
50a0decf 2187 u32 chain_len;
33a2ffce
SC		 2188
2189 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2190 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2191 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2192 chain_len = sizeof(*chain_sg) *
2b08b3e9 2193 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2194 chain_sg->Len = cpu_to_le32(chain_len);
2195 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2196 PCI_DMA_TODEVICE);
e2bea6df
SC		 2197 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2198 /* prevent subsequent unmapping */
50a0decf 2199 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2200 return -1;
2201 }
50a0decf 2202 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2203 return 0;
33a2ffce
SC		 2204}
2205
2206static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2207 struct CommandList *c)
2208{
2209 struct SGDescriptor *chain_sg;
33a2ffce 2210
50a0decf 2211 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2212 return;
2213
2214 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2215 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2216 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2217}
2218
a09c1441
ST		 2219
2220/* Decode the various types of errors on ioaccel2 path.
2221 * Return 1 for any error that should generate a RAID path retry.
2222 * Return 0 for errors that don't require a RAID path retry.
2223 */
2224static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2225 struct CommandList *c,
2226 struct scsi_cmnd *cmd,
ba74fdc4
DB		 2227 struct io_accel2_cmd *c2,
2228 struct hpsa_scsi_dev_t *dev)
c349775e
ST		 2229{
2230 int data_len;
a09c1441 2231 int retry = 0;
c40820d5 2232 u32 ioaccel2_resid = 0;
c349775e
ST		 2233
2234 switch (c2->error_data.serv_response) {
2235 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2236 switch (c2->error_data.status) {
2237 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2238 break;
2239 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2240 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2241 if (c2->error_data.data_present !=
ee6b1889
SC		 2242 IOACCEL2_SENSE_DATA_PRESENT) {
2243 memset(cmd->sense_buffer, 0,
2244 SCSI_SENSE_BUFFERSIZE);
c349775e 2245 break;
ee6b1889 2246 }
c349775e
ST		 2247 /* copy the sense data */
2248 data_len = c2->error_data.sense_data_len;
2249 if (data_len > SCSI_SENSE_BUFFERSIZE)
2250 data_len = SCSI_SENSE_BUFFERSIZE;
2251 if (data_len > sizeof(c2->error_data.sense_data_buff))
2252 data_len =
2253 sizeof(c2->error_data.sense_data_buff);
2254 memcpy(cmd->sense_buffer,
2255 c2->error_data.sense_data_buff, data_len);
a09c1441 2256 retry = 1;
c349775e
ST		 2257 break;
2258 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2259 retry = 1;
c349775e
ST		 2260 break;
2261 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2262 retry = 1;
c349775e
ST		 2263 break;
2264 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2265 retry = 1;
c349775e
ST		 2266 break;
2267 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2268 retry = 1;
c349775e
ST		 2269 break;
2270 default:
a09c1441 2271 retry = 1;
c349775e
ST		 2272 break;
2273 }
2274 break;
2275 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2276 switch (c2->error_data.status) {
2277 case IOACCEL2_STATUS_SR_IO_ERROR:
2278 case IOACCEL2_STATUS_SR_IO_ABORTED:
2279 case IOACCEL2_STATUS_SR_OVERRUN:
2280 retry = 1;
2281 break;
2282 case IOACCEL2_STATUS_SR_UNDERRUN:
2283 cmd->result = (DID_OK << 16); /* host byte */
2284 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2285 ioaccel2_resid = get_unaligned_le32(
2286 &c2->error_data.resid_cnt[0]);
2287 scsi_set_resid(cmd, ioaccel2_resid);
2288 break;
2289 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2290 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2291 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
ba74fdc4
DB		 2292 /*
2293 * Did an HBA disk disappear? We will eventually
2294 * get a state change event from the controller but
2295 * in the meantime, we need to tell the OS that the
2296 * HBA disk is no longer there and stop I/O
2297 * from going down. This allows the potential re-insert
2298 * of the disk to get the same device node.
2299 */
2300 if (dev->physical_device && dev->expose_device) {
2301 cmd->result = DID_NO_CONNECT << 16;
2302 dev->removed = 1;
2303 h->drv_req_rescan = 1;
2304 dev_warn(&h->pdev->dev,
2305 "%s: device is gone!\n", __func__);
2306 } else
2307 /*
2308 * Retry by sending down the RAID path.
2309 * We will get an event from ctlr to
2310 * trigger rescan regardless.
2311 */
2312 retry = 1;
c40820d5
JH		 2313 break;
2314 default:
2315 retry = 1;
c40820d5 2316 }
c349775e
ST		 2317 break;
2318 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2319 break;
2320 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2321 break;
2322 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2323 retry = 1;
c349775e
ST		 2324 break;
2325 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2326 break;
2327 default:
a09c1441 2328 retry = 1;
c349775e
ST		 2329 break;
2330 }
a09c1441
ST		 2331
2332 return retry; /* retry on raid path? */
c349775e
ST		 2333}
2334
a58e7e53
WS		 2335static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2336 struct CommandList *c)
2337{
d604f533
WS		 2338 bool do_wake = false;
2339
a58e7e53
WS		 2340 /*
2341 * Prevent the following race in the abort handler:
2342 *
2343 * 1. LLD is requested to abort a SCSI command
2344 * 2. The SCSI command completes
2345 * 3. The struct CommandList associated with step 2 is made available
2346 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2347 * 5. Abort handler follows scsi_cmnd->host_scribble and
2348 * finds struct CommandList and tries to aborts it
2349 * Now we have aborted the wrong command.
2350 *
d604f533
WS		 2351 * Reset c->scsi_cmd here so that the abort or reset handler will know
2352 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2353 * waiting for this command, and, if so, wake it.
2354 */
2355 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2356 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2357 if (c->abort_pending) {
d604f533 2358 do_wake = true;
a58e7e53 2359 c->abort_pending = false;
a58e7e53 2360 }
d604f533
WS		 2361 if (c->reset_pending) {
2362 unsigned long flags;
2363 struct hpsa_scsi_dev_t *dev;
2364
2365 /*
2366 * There appears to be a reset pending; lock the lock and
2367 * reconfirm. If so, then decrement the count of outstanding
2368 * commands and wake the reset command if this is the last one.
2369 */
2370 spin_lock_irqsave(&h->lock, flags);
2371 dev = c->reset_pending; /* Re-fetch under the lock. */
2372 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2373 do_wake = true;
2374 c->reset_pending = NULL;
2375 spin_unlock_irqrestore(&h->lock, flags);
2376 }
2377
2378 if (do_wake)
2379 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2380}
2381
73153fe5
WS		 2382static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2383 struct CommandList *c)
2384{
2385 hpsa_cmd_resolve_events(h, c);
2386 cmd_tagged_free(h, c);
2387}
2388
8a0ff92c
WS		 2389static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2390 struct CommandList *c, struct scsi_cmnd *cmd)
2391{
73153fe5 2392 hpsa_cmd_resolve_and_free(h, c);
d49c2077
DB		 2393 if (cmd && cmd->scsi_done)
2394 cmd->scsi_done(cmd);
8a0ff92c
WS		 2395}
2396
2397static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2398{
2399 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2400 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2401}
2402
a58e7e53
WS		 2403static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2404{
2405 cmd->result = DID_ABORT << 16;
2406}
2407
2408static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2409 struct scsi_cmnd *cmd)
2410{
2411 hpsa_set_scsi_cmd_aborted(cmd);
2412 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2413 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2414 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2415}
2416
c349775e
ST		 2417static void process_ioaccel2_completion(struct ctlr_info *h,
2418 struct CommandList *c, struct scsi_cmnd *cmd,
2419 struct hpsa_scsi_dev_t *dev)
2420{
2421 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2422
2423 /* check for good status */
2424 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2425 c2->error_data.status == 0))
2426 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2427
8a0ff92c
WS		 2428 /*
2429 * Any RAID offload error results in retry which will use
c349775e
ST		 2430 * the normal I/O path so the controller can handle whatever's
2431 * wrong.
2432 */
f3f01730 2433 if (is_logical_device(dev) &&
c349775e
ST		 2434 c2->error_data.serv_response ==
2435 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc 2436 if (c2->error_data.status ==
064d1b1d 2437 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
080ef1cc 2438 dev->offload_enabled = 0;
064d1b1d
DB		 2439 dev->offload_to_be_enabled = 0;
2440 }
8a0ff92c
WS		 2441
2442 return hpsa_retry_cmd(h, c);
a09c1441 2443 }
080ef1cc 2444
ba74fdc4 2445 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
8a0ff92c 2446 return hpsa_retry_cmd(h, c);
080ef1cc 2447
8a0ff92c 2448 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2449}
2450
9437ac43
SC		 2451/* Returns 0 on success, < 0 otherwise. */
2452static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2453 struct CommandList *cp)
2454{
2455 u8 tmf_status = cp->err_info->ScsiStatus;
2456
2457 switch (tmf_status) {
2458 case CISS_TMF_COMPLETE:
2459 /*
2460 * CISS_TMF_COMPLETE never happens, instead,
2461 * ei->CommandStatus == 0 for this case.
2462 */
2463 case CISS_TMF_SUCCESS:
2464 return 0;
2465 case CISS_TMF_INVALID_FRAME:
2466 case CISS_TMF_NOT_SUPPORTED:
2467 case CISS_TMF_FAILED:
2468 case CISS_TMF_WRONG_LUN:
2469 case CISS_TMF_OVERLAPPED_TAG:
2470 break;
2471 default:
2472 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2473 tmf_status);
2474 break;
2475 }
2476 return -tmf_status;
2477}
2478
1fb011fb 2479static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2480{
2481 struct scsi_cmnd *cmd;
2482 struct ctlr_info *h;
2483 struct ErrorInfo *ei;
283b4a9b 2484 struct hpsa_scsi_dev_t *dev;
d9a729f3 2485 struct io_accel2_cmd *c2;
edd16368 2486
9437ac43
SC		 2487 u8 sense_key;
2488 u8 asc; /* additional sense code */
2489 u8 ascq; /* additional sense code qualifier */
db111e18 2490 unsigned long sense_data_size;
edd16368
SC		 2491
2492 ei = cp->err_info;
7fa3030c 2493 cmd = cp->scsi_cmd;
edd16368 2494 h = cp->h;
d49c2077
DB		 2495
2496 if (!cmd->device) {
2497 cmd->result = DID_NO_CONNECT << 16;
2498 return hpsa_cmd_free_and_done(h, cp, cmd);
2499 }
2500
283b4a9b 2501 dev = cmd->device->hostdata;
45e596cd
DB		 2502 if (!dev) {
2503 cmd->result = DID_NO_CONNECT << 16;
2504 return hpsa_cmd_free_and_done(h, cp, cmd);
2505 }
d9a729f3 2506 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2507
2508 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2509 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2510 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2511 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2512
d9a729f3
WS		 2513 if ((cp->cmd_type == CMD_IOACCEL2) &&
2514 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2515 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2516
edd16368
SC		 2517 cmd->result = (DID_OK << 16); /* host byte */
2518 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2519
d49c2077
DB		 2520 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) {
2521 if (dev->physical_device && dev->expose_device &&
2522 dev->removed) {
2523 cmd->result = DID_NO_CONNECT << 16;
2524 return hpsa_cmd_free_and_done(h, cp, cmd);
2525 }
2526 if (likely(cp->phys_disk != NULL))
2527 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2528 }
03383736 2529
25163bd5
WS		 2530 /*
2531 * We check for lockup status here as it may be set for
2532 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2533 * fail_all_oustanding_cmds()
2534 */
2535 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2536 /* DID_NO_CONNECT will prevent a retry */
2537 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2538 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2539 }
2540
d604f533
WS		 2541 if ((unlikely(hpsa_is_pending_event(cp)))) {
2542 if (cp->reset_pending)
2543 return hpsa_cmd_resolve_and_free(h, cp);
2544 if (cp->abort_pending)
2545 return hpsa_cmd_abort_and_free(h, cp, cmd);
2546 }
2547
c349775e
ST		 2548 if (cp->cmd_type == CMD_IOACCEL2)
2549 return process_ioaccel2_completion(h, cp, cmd, dev);
2550
6aa4c361 2551 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2552 if (ei->CommandStatus == 0)
2553 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2554
e1f7de0c
MG		 2555 /* For I/O accelerator commands, copy over some fields to the normal
2556 * CISS header used below for error handling.
2557 */
2558 if (cp->cmd_type == CMD_IOACCEL1) {
2559 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2560 cp->Header.SGList = scsi_sg_count(cmd);
2561 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2562 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2563 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2564 cp->Header.tag = c->tag;
e1f7de0c
MG		 2565 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2566 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2567
2568 /* Any RAID offload error results in retry which will use
2569 * the normal I/O path so the controller can handle whatever's
2570 * wrong.
2571 */
f3f01730 2572 if (is_logical_device(dev)) {
283b4a9b
SC		 2573 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2574 dev->offload_enabled = 0;
d604f533 2575 return hpsa_retry_cmd(h, cp);
283b4a9b 2576 }
e1f7de0c
MG		 2577 }
2578
edd16368
SC		 2579 /* an error has occurred */
2580 switch (ei->CommandStatus) {
2581
2582 case CMD_TARGET_STATUS:
9437ac43
SC		 2583 cmd->result |= ei->ScsiStatus;
2584 /* copy the sense data */
2585 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2586 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2587 else
2588 sense_data_size = sizeof(ei->SenseInfo);
2589 if (ei->SenseLen < sense_data_size)
2590 sense_data_size = ei->SenseLen;
2591 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2592 if (ei->ScsiStatus)
2593 decode_sense_data(ei->SenseInfo, sense_data_size,
2594 &sense_key, &asc, &ascq);
edd16368 2595 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2596 if (sense_key == ABORTED_COMMAND) {
2e311fba 2597 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2598 break;
2599 }
edd16368
SC		 2600 break;
2601 }
edd16368
SC		 2602 /* Problem was not a check condition
2603 * Pass it up to the upper layers...
2604 */
2605 if (ei->ScsiStatus) {
2606 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2607 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2608 "Returning result: 0x%x\n",
2609 cp, ei->ScsiStatus,
2610 sense_key, asc, ascq,
2611 cmd->result);
2612 } else { /* scsi status is zero??? How??? */
2613 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2614 "Returning no connection.\n", cp),
2615
2616 /* Ordinarily, this case should never happen,
2617 * but there is a bug in some released firmware
2618 * revisions that allows it to happen if, for
2619 * example, a 4100 backplane loses power and
2620 * the tape drive is in it. We assume that
2621 * it's a fatal error of some kind because we
2622 * can't show that it wasn't. We will make it
2623 * look like selection timeout since that is
2624 * the most common reason for this to occur,
2625 * and it's severe enough.
2626 */
2627
2628 cmd->result = DID_NO_CONNECT << 16;
2629 }
2630 break;
2631
2632 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2633 break;
2634 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2635 dev_warn(&h->pdev->dev,
2636 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2637 break;
2638 case CMD_INVALID: {
2639 /* print_bytes(cp, sizeof(*cp), 1, 0);
2640 print_cmd(cp); */
2641 /* We get CMD_INVALID if you address a non-existent device
2642 * instead of a selection timeout (no response). You will
2643 * see this if you yank out a drive, then try to access it.
2644 * This is kind of a shame because it means that any other
2645 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2646 * missing target. */
2647 cmd->result = DID_NO_CONNECT << 16;
2648 }
2649 break;
2650 case CMD_PROTOCOL_ERR:
256d0eaa 2651 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2652 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2653 cp->Request.CDB);
edd16368
SC		 2654 break;
2655 case CMD_HARDWARE_ERR:
2656 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2657 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2658 cp->Request.CDB);
edd16368
SC		 2659 break;
2660 case CMD_CONNECTION_LOST:
2661 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2662 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2663 cp->Request.CDB);
edd16368
SC		 2664 break;
2665 case CMD_ABORTED:
a58e7e53
WS		 2666 /* Return now to avoid calling scsi_done(). */
2667 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2668 case CMD_ABORT_FAILED:
2669 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2670 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2671 cp->Request.CDB);
edd16368
SC		 2672 break;
2673 case CMD_UNSOLICITED_ABORT:
f6e76055 2674 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2675 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2676 cp->Request.CDB);
edd16368
SC		 2677 break;
2678 case CMD_TIMEOUT:
2679 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2680 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2681 cp->Request.CDB);
edd16368 2682 break;
1d5e2ed0
SC		 2683 case CMD_UNABORTABLE:
2684 cmd->result = DID_ERROR << 16;
2685 dev_warn(&h->pdev->dev, "Command unabortable\n");
2686 break;
9437ac43
SC		 2687 case CMD_TMF_STATUS:
2688 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2689 cmd->result = DID_ERROR << 16;
2690 break;
283b4a9b
SC		 2691 case CMD_IOACCEL_DISABLED:
2692 /* This only handles the direct pass-through case since RAID
2693 * offload is handled above. Just attempt a retry.
2694 */
2695 cmd->result = DID_SOFT_ERROR << 16;
2696 dev_warn(&h->pdev->dev,
2697 "cp %p had HP SSD Smart Path error\n", cp);
2698 break;
edd16368
SC		 2699 default:
2700 cmd->result = DID_ERROR << 16;
2701 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2702 cp, ei->CommandStatus);
2703 }
8a0ff92c
WS		 2704
2705 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2706}
2707
edd16368
SC		 2708static void hpsa_pci_unmap(struct pci_dev *pdev,
2709 struct CommandList *c, int sg_used, int data_direction)
2710{
2711 int i;
edd16368 2712
50a0decf
SC		 2713 for (i = 0; i < sg_used; i++)
2714 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2715 le32_to_cpu(c->SG[i].Len),
2716 data_direction);
edd16368
SC		 2717}
2718
a2dac136 2719static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2720 struct CommandList *cp,
2721 unsigned char *buf,
2722 size_t buflen,
2723 int data_direction)
2724{
01a02ffc 2725 u64 addr64;
edd16368
SC		 2726
2727 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2728 cp->Header.SGList = 0;
50a0decf 2729 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2730 return 0;
edd16368
SC		 2731 }
2732
50a0decf 2733 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2734 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2735 /* Prevent subsequent unmap of something never mapped */
eceaae18 2736 cp->Header.SGList = 0;
50a0decf 2737 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2738 return -1;
eceaae18 2739 }
50a0decf
SC		 2740 cp->SG[0].Addr = cpu_to_le64(addr64);
2741 cp->SG[0].Len = cpu_to_le32(buflen);
2742 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2743 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2744 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2745 return 0;
edd16368
SC		 2746}
2747
25163bd5
WS		 2748#define NO_TIMEOUT ((unsigned long) -1)
2749#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2750static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2751 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2752{
2753 DECLARE_COMPLETION_ONSTACK(wait);
2754
2755 c->waiting = &wait;
25163bd5
WS		 2756 __enqueue_cmd_and_start_io(h, c, reply_queue);
2757 if (timeout_msecs == NO_TIMEOUT) {
2758 /* TODO: get rid of this no-timeout thing */
2759 wait_for_completion_io(&wait);
2760 return IO_OK;
2761 }
2762 if (!wait_for_completion_io_timeout(&wait,
2763 msecs_to_jiffies(timeout_msecs))) {
2764 dev_warn(&h->pdev->dev, "Command timed out.\n");
2765 return -ETIMEDOUT;
2766 }
2767 return IO_OK;
2768}
2769
2770static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2771 int reply_queue, unsigned long timeout_msecs)
2772{
2773 if (unlikely(lockup_detected(h))) {
2774 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2775 return IO_OK;
2776 }
2777 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2778}
2779
094963da
SC		 2780static u32 lockup_detected(struct ctlr_info *h)
2781{
2782 int cpu;
2783 u32 rc, *lockup_detected;
2784
2785 cpu = get_cpu();
2786 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2787 rc = *lockup_detected;
2788 put_cpu();
2789 return rc;
2790}
2791
9c2fc160 2792#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2793static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2794 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2795{
9c2fc160 2796 int backoff_time = 10, retry_count = 0;
25163bd5 2797 int rc;
edd16368
SC		 2798
2799 do {
7630abd0 2800 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2801 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2802 timeout_msecs);
2803 if (rc)
2804 break;
edd16368 2805 retry_count++;
9c2fc160
SC		 2806 if (retry_count > 3) {
2807 msleep(backoff_time);
2808 if (backoff_time < 1000)
2809 backoff_time *= 2;
2810 }
852af20a 2811 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2812 check_for_busy(h, c)) &&
2813 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2814 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2815 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2816 rc = -EIO;
2817 return rc;
edd16368
SC		 2818}
2819
d1e8beac
SC		 2820static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2821 struct CommandList *c)
edd16368 2822{
d1e8beac
SC		 2823 const u8 *cdb = c->Request.CDB;
2824 const u8 *lun = c->Header.LUN.LunAddrBytes;
2825
2826 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2827 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2828 txt, lun[0], lun[1], lun[2], lun[3],
2829 lun[4], lun[5], lun[6], lun[7],
2830 cdb[0], cdb[1], cdb[2], cdb[3],
2831 cdb[4], cdb[5], cdb[6], cdb[7],
2832 cdb[8], cdb[9], cdb[10], cdb[11],
2833 cdb[12], cdb[13], cdb[14], cdb[15]);
2834}
2835
2836static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2837 struct CommandList *cp)
2838{
2839 const struct ErrorInfo *ei = cp->err_info;
edd16368 2840 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2841 u8 sense_key, asc, ascq;
2842 int sense_len;
edd16368 2843
edd16368
SC		 2844 switch (ei->CommandStatus) {
2845 case CMD_TARGET_STATUS:
9437ac43
SC		 2846 if (ei->SenseLen > sizeof(ei->SenseInfo))
2847 sense_len = sizeof(ei->SenseInfo);
2848 else
2849 sense_len = ei->SenseLen;
2850 decode_sense_data(ei->SenseInfo, sense_len,
2851 &sense_key, &asc, &ascq);
d1e8beac
SC		 2852 hpsa_print_cmd(h, "SCSI status", cp);
2853 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2854 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2855 sense_key, asc, ascq);
d1e8beac 2856 else
9437ac43 2857 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2858 if (ei->ScsiStatus == 0)
2859 dev_warn(d, "SCSI status is abnormally zero. "
2860 "(probably indicates selection timeout "
2861 "reported incorrectly due to a known "
2862 "firmware bug, circa July, 2001.)\n");
2863 break;
2864 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2865 break;
2866 case CMD_DATA_OVERRUN:
d1e8beac 2867 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2868 break;
2869 case CMD_INVALID: {
2870 /* controller unfortunately reports SCSI passthru's
2871 * to non-existent targets as invalid commands.
2872 */
d1e8beac
SC		 2873 hpsa_print_cmd(h, "invalid command", cp);
2874 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2875 }
2876 break;
2877 case CMD_PROTOCOL_ERR:
d1e8beac 2878 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2879 break;
2880 case CMD_HARDWARE_ERR:
d1e8beac 2881 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2882 break;
2883 case CMD_CONNECTION_LOST:
d1e8beac 2884 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2885 break;
2886 case CMD_ABORTED:
d1e8beac 2887 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2888 break;
2889 case CMD_ABORT_FAILED:
d1e8beac 2890 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2891 break;
2892 case CMD_UNSOLICITED_ABORT:
d1e8beac 2893 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2894 break;
2895 case CMD_TIMEOUT:
d1e8beac 2896 hpsa_print_cmd(h, "timed out", cp);
edd16368 2897 break;
1d5e2ed0 2898 case CMD_UNABORTABLE:
d1e8beac 2899 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2900 break;
25163bd5
WS		 2901 case CMD_CTLR_LOCKUP:
2902 hpsa_print_cmd(h, "controller lockup detected", cp);
2903 break;
edd16368 2904 default:
d1e8beac
SC		 2905 hpsa_print_cmd(h, "unknown status", cp);
2906 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2907 ei->CommandStatus);
2908 }
2909}
2910
2911static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2912 u16 page, unsigned char *buf,
edd16368
SC		 2913 unsigned char bufsize)
2914{
2915 int rc = IO_OK;
2916 struct CommandList *c;
2917 struct ErrorInfo *ei;
2918
45fcb86e 2919 c = cmd_alloc(h);
edd16368 2920
a2dac136
SC		 2921 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2922 page, scsi3addr, TYPE_CMD)) {
2923 rc = -1;
2924 goto out;
2925 }
25163bd5 2926 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 2927 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 2928 if (rc)
2929 goto out;
edd16368
SC		 2930 ei = c->err_info;
2931 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2932 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2933 rc = -1;
2934 }
a2dac136 2935out:
45fcb86e 2936 cmd_free(h, c);
edd16368
SC		 2937 return rc;
2938}
2939
bf711ac6 2940static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2941 u8 reset_type, int reply_queue)
edd16368
SC		 2942{
2943 int rc = IO_OK;
2944 struct CommandList *c;
2945 struct ErrorInfo *ei;
2946
45fcb86e 2947 c = cmd_alloc(h);
edd16368 2948
edd16368 2949
a2dac136 2950 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2951 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2952 scsi3addr, TYPE_MSG);
c448ecfa 2953 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
25163bd5
WS		 2954 if (rc) {
2955 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2956 goto out;
2957 }
edd16368
SC		 2958 /* no unmap needed here because no data xfer. */
2959
2960 ei = c->err_info;
2961 if (ei->CommandStatus != 0) {
d1e8beac 2962 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2963 rc = -1;
2964 }
25163bd5 2965out:
45fcb86e 2966 cmd_free(h, c);
edd16368
SC		 2967 return rc;
2968}
2969
d604f533
WS		 2970static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2971 struct hpsa_scsi_dev_t *dev,
2972 unsigned char *scsi3addr)
2973{
2974 int i;
2975 bool match = false;
2976 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2977 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2978
2979 if (hpsa_is_cmd_idle(c))
2980 return false;
2981
2982 switch (c->cmd_type) {
2983 case CMD_SCSI:
2984 case CMD_IOCTL_PEND:
2985 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2986 sizeof(c->Header.LUN.LunAddrBytes));
2987 break;
2988
2989 case CMD_IOACCEL1:
2990 case CMD_IOACCEL2:
2991 if (c->phys_disk == dev) {
2992 /* HBA mode match */
2993 match = true;
2994 } else {
2995 /* Possible RAID mode -- check each phys dev. */
2996 /* FIXME: Do we need to take out a lock here? If
2997 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2998 * instead. */
2999 for (i = 0; i < dev->nphysical_disks && !match; i++) {
3000 /* FIXME: an alternate test might be
3001 *
3002 * match = dev->phys_disk[i]->ioaccel_handle
3003 * == c2->scsi_nexus; */
3004 match = dev->phys_disk[i] == c->phys_disk;
3005 }
3006 }
3007 break;
3008
3009 case IOACCEL2_TMF:
3010 for (i = 0; i < dev->nphysical_disks && !match; i++) {
3011 match = dev->phys_disk[i]->ioaccel_handle ==
3012 le32_to_cpu(ac->it_nexus);
3013 }
3014 break;
3015
3016 case 0: /* The command is in the middle of being initialized. */
3017 match = false;
3018 break;
3019
3020 default:
3021 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
3022 c->cmd_type);
3023 BUG();
3024 }
3025
3026 return match;
3027}
3028
3029static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
3030 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
3031{
3032 int i;
3033 int rc = 0;
3034
3035 /* We can really only handle one reset at a time */
3036 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
3037 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
3038 return -EINTR;
3039 }
3040
3041 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
3042
3043 for (i = 0; i < h->nr_cmds; i++) {
3044 struct CommandList *c = h->cmd_pool + i;
3045 int refcount = atomic_inc_return(&c->refcount);
3046
3047 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
3048 unsigned long flags;
3049
3050 /*
3051 * Mark the target command as having a reset pending,
3052 * then lock a lock so that the command cannot complete
3053 * while we're considering it. If the command is not
3054 * idle then count it; otherwise revoke the event.
3055 */
3056 c->reset_pending = dev;
3057 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
3058 if (!hpsa_is_cmd_idle(c))
3059 atomic_inc(&dev->reset_cmds_out);
3060 else
3061 c->reset_pending = NULL;
3062 spin_unlock_irqrestore(&h->lock, flags);
3063 }
3064
3065 cmd_free(h, c);
3066 }
3067
3068 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
3069 if (!rc)
3070 wait_event(h->event_sync_wait_queue,
3071 atomic_read(&dev->reset_cmds_out) == 0 ||
3072 lockup_detected(h));
3073
3074 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 3075 dev_warn(&h->pdev->dev,
3076 "Controller lockup detected during reset wait\n");
3077 rc = -ENODEV;
3078 }
d604f533
WS		 3079
3080 if (unlikely(rc))
3081 atomic_set(&dev->reset_cmds_out, 0);
3082
3083 mutex_unlock(&h->reset_mutex);
3084 return rc;
3085}
3086
edd16368
SC		 3087static void hpsa_get_raid_level(struct ctlr_info *h,
3088 unsigned char *scsi3addr, unsigned char *raid_level)
3089{
3090 int rc;
3091 unsigned char *buf;
3092
3093 *raid_level = RAID_UNKNOWN;
3094 buf = kzalloc(64, GFP_KERNEL);
3095 if (!buf)
3096 return;
8383278d
ST		 3097
3098 if (!hpsa_vpd_page_supported(h, scsi3addr,
3099 HPSA_VPD_LV_DEVICE_GEOMETRY))
3100 goto exit;
3101
3102 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
3103 HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64);
3104
edd16368
SC		 3105 if (rc == 0)
3106 *raid_level = buf[8];
3107 if (*raid_level > RAID_UNKNOWN)
3108 *raid_level = RAID_UNKNOWN;
8383278d 3109exit:
edd16368
SC		 3110 kfree(buf);
3111 return;
3112}
3113
283b4a9b
SC		 3114#define HPSA_MAP_DEBUG
3115#ifdef HPSA_MAP_DEBUG
3116static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
3117 struct raid_map_data *map_buff)
3118{
3119 struct raid_map_disk_data *dd = &map_buff->data[0];
3120 int map, row, col;
3121 u16 map_cnt, row_cnt, disks_per_row;
3122
3123 if (rc != 0)
3124 return;
3125
2ba8bfc8
SC		 3126 /* Show details only if debugging has been activated. */
3127 if (h->raid_offload_debug < 2)
3128 return;
3129
283b4a9b
SC		 3130 dev_info(&h->pdev->dev, "structure_size = %u\n",
3131 le32_to_cpu(map_buff->structure_size));
3132 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3133 le32_to_cpu(map_buff->volume_blk_size));
3134 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3135 le64_to_cpu(map_buff->volume_blk_cnt));
3136 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3137 map_buff->phys_blk_shift);
3138 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3139 map_buff->parity_rotation_shift);
3140 dev_info(&h->pdev->dev, "strip_size = %u\n",
3141 le16_to_cpu(map_buff->strip_size));
3142 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3143 le64_to_cpu(map_buff->disk_starting_blk));
3144 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3145 le64_to_cpu(map_buff->disk_blk_cnt));
3146 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3147 le16_to_cpu(map_buff->data_disks_per_row));
3148 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3149 le16_to_cpu(map_buff->metadata_disks_per_row));
3150 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3151 le16_to_cpu(map_buff->row_cnt));
3152 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3153 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3154 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3155 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 3156 dev_info(&h->pdev->dev, "encrypytion = %s\n",
3157 le16_to_cpu(map_buff->flags) &
3158 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3159 dev_info(&h->pdev->dev, "dekindex = %u\n",
3160 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3161 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3162 for (map = 0; map < map_cnt; map++) {
3163 dev_info(&h->pdev->dev, "Map%u:\n", map);
3164 row_cnt = le16_to_cpu(map_buff->row_cnt);
3165 for (row = 0; row < row_cnt; row++) {
3166 dev_info(&h->pdev->dev, " Row%u:\n", row);
3167 disks_per_row =
3168 le16_to_cpu(map_buff->data_disks_per_row);
3169 for (col = 0; col < disks_per_row; col++, dd++)
3170 dev_info(&h->pdev->dev,
3171 " D%02u: h=0x%04x xor=%u,%u\n",
3172 col, dd->ioaccel_handle,
3173 dd->xor_mult[0], dd->xor_mult[1]);
3174 disks_per_row =
3175 le16_to_cpu(map_buff->metadata_disks_per_row);
3176 for (col = 0; col < disks_per_row; col++, dd++)
3177 dev_info(&h->pdev->dev,
3178 " M%02u: h=0x%04x xor=%u,%u\n",
3179 col, dd->ioaccel_handle,
3180 dd->xor_mult[0], dd->xor_mult[1]);
3181 }
3182 }
3183}
3184#else
3185static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3186 __attribute__((unused)) int rc,
3187 __attribute__((unused)) struct raid_map_data *map_buff)
3188{
3189}
3190#endif
3191
3192static int hpsa_get_raid_map(struct ctlr_info *h,
3193 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3194{
3195 int rc = 0;
3196 struct CommandList *c;
3197 struct ErrorInfo *ei;
3198
45fcb86e 3199 c = cmd_alloc(h);
bf43caf3 3200
283b4a9b
SC		 3201 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3202 sizeof(this_device->raid_map), 0,
3203 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3204 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3205 cmd_free(h, c);
3206 return -1;
283b4a9b 3207 }
25163bd5 3208 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3209 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3210 if (rc)
3211 goto out;
283b4a9b
SC		 3212 ei = c->err_info;
3213 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3214 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3215 rc = -1;
3216 goto out;
283b4a9b 3217 }
45fcb86e 3218 cmd_free(h, c);
283b4a9b
SC		 3219
3220 /* @todo in the future, dynamically allocate RAID map memory */
3221 if (le32_to_cpu(this_device->raid_map.structure_size) >
3222 sizeof(this_device->raid_map)) {
3223 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3224 rc = -1;
3225 }
3226 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3227 return rc;
25163bd5
WS		 3228out:
3229 cmd_free(h, c);
3230 return rc;
283b4a9b
SC		 3231}
3232
d04e62b9
KB		 3233static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3234 unsigned char scsi3addr[], u16 bmic_device_index,
3235 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3236{
3237 int rc = IO_OK;
3238 struct CommandList *c;
3239 struct ErrorInfo *ei;
3240
3241 c = cmd_alloc(h);
3242
3243 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3244 0, RAID_CTLR_LUNID, TYPE_CMD);
3245 if (rc)
3246 goto out;
3247
3248 c->Request.CDB[2] = bmic_device_index & 0xff;
3249 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3250
3251 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3252 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
d04e62b9
KB		 3253 if (rc)
3254 goto out;
3255 ei = c->err_info;
3256 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3257 hpsa_scsi_interpret_error(h, c);
3258 rc = -1;
3259 }
3260out:
3261 cmd_free(h, c);
3262 return rc;
3263}
3264
66749d0d
ST		 3265static int hpsa_bmic_id_controller(struct ctlr_info *h,
3266 struct bmic_identify_controller *buf, size_t bufsize)
3267{
3268 int rc = IO_OK;
3269 struct CommandList *c;
3270 struct ErrorInfo *ei;
3271
3272 c = cmd_alloc(h);
3273
3274 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3275 0, RAID_CTLR_LUNID, TYPE_CMD);
3276 if (rc)
3277 goto out;
3278
3279 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3280 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
66749d0d
ST		 3281 if (rc)
3282 goto out;
3283 ei = c->err_info;
3284 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3285 hpsa_scsi_interpret_error(h, c);
3286 rc = -1;
3287 }
3288out:
3289 cmd_free(h, c);
3290 return rc;
3291}
3292
03383736
DB		 3293static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3294 unsigned char scsi3addr[], u16 bmic_device_index,
3295 struct bmic_identify_physical_device *buf, size_t bufsize)
3296{
3297 int rc = IO_OK;
3298 struct CommandList *c;
3299 struct ErrorInfo *ei;
3300
3301 c = cmd_alloc(h);
3302 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3303 0, RAID_CTLR_LUNID, TYPE_CMD);
3304 if (rc)
3305 goto out;
3306
3307 c->Request.CDB[2] = bmic_device_index & 0xff;
3308 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3309
25163bd5 3310 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3311 DEFAULT_TIMEOUT);
03383736
DB		 3312 ei = c->err_info;
3313 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3314 hpsa_scsi_interpret_error(h, c);
3315 rc = -1;
3316 }
3317out:
3318 cmd_free(h, c);
d04e62b9 3319
03383736
DB		 3320 return rc;
3321}
3322
cca8f13b
DB		 3323/*
3324 * get enclosure information
3325 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3326 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3327 * Uses id_physical_device to determine the box_index.
3328 */
3329static void hpsa_get_enclosure_info(struct ctlr_info *h,
3330 unsigned char *scsi3addr,
3331 struct ReportExtendedLUNdata *rlep, int rle_index,
3332 struct hpsa_scsi_dev_t *encl_dev)
3333{
3334 int rc = -1;
3335 struct CommandList *c = NULL;
3336 struct ErrorInfo *ei = NULL;
3337 struct bmic_sense_storage_box_params *bssbp = NULL;
3338 struct bmic_identify_physical_device *id_phys = NULL;
3339 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3340 u16 bmic_device_index = 0;
3341
3342 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3343
17a9e54a
DB		 3344 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3345 rc = IO_OK;
cca8f13b 3346 goto out;
17a9e54a 3347 }
cca8f13b
DB		 3348
3349 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3350 if (!bssbp)
3351 goto out;
3352
3353 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3354 if (!id_phys)
3355 goto out;
3356
3357 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3358 id_phys, sizeof(*id_phys));
3359 if (rc) {
3360 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3361 __func__, encl_dev->external, bmic_device_index);
3362 goto out;
3363 }
3364
3365 c = cmd_alloc(h);
3366
3367 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3368 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3369
3370 if (rc)
3371 goto out;
3372
3373 if (id_phys->phys_connector[1] == 'E')
3374 c->Request.CDB[5] = id_phys->box_index;
3375 else
3376 c->Request.CDB[5] = 0;
3377
3378 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
c448ecfa 3379 DEFAULT_TIMEOUT);
cca8f13b
DB		 3380 if (rc)
3381 goto out;
3382
3383 ei = c->err_info;
3384 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3385 rc = -1;
3386 goto out;
3387 }
3388
3389 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3390 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3391 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3392
3393 rc = IO_OK;
3394out:
3395 kfree(bssbp);
3396 kfree(id_phys);
3397
3398 if (c)
3399 cmd_free(h, c);
3400
3401 if (rc != IO_OK)
3402 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
3403 "Error, could not get enclosure information\n");
3404}
3405
d04e62b9
KB		 3406static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3407 unsigned char *scsi3addr)
3408{
3409 struct ReportExtendedLUNdata *physdev;
3410 u32 nphysicals;
3411 u64 sa = 0;
3412 int i;
3413
3414 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3415 if (!physdev)
3416 return 0;
3417
3418 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3419 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3420 kfree(physdev);
3421 return 0;
3422 }
3423 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3424
3425 for (i = 0; i < nphysicals; i++)
3426 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3427 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3428 break;
3429 }
3430
3431 kfree(physdev);
3432
3433 return sa;
3434}
3435
3436static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3437 struct hpsa_scsi_dev_t *dev)
3438{
3439 int rc;
3440 u64 sa = 0;
3441
3442 if (is_hba_lunid(scsi3addr)) {
3443 struct bmic_sense_subsystem_info *ssi;
3444
3445 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
3446 if (ssi == NULL) {
3447 dev_warn(&h->pdev->dev,
3448 "%s: out of memory\n", __func__);
3449 return;
3450 }
3451
3452 rc = hpsa_bmic_sense_subsystem_information(h,
3453 scsi3addr, 0, ssi, sizeof(*ssi));
3454 if (rc == 0) {
3455 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3456 h->sas_address = sa;
3457 }
3458
3459 kfree(ssi);
3460 } else
3461 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3462
3463 dev->sas_address = sa;
3464}
3465
3466/* Get a device id from inquiry page 0x83 */
8383278d 3467static bool hpsa_vpd_page_supported(struct ctlr_info *h,
1b70150a
SC		 3468 unsigned char scsi3addr[], u8 page)
3469{
3470 int rc;
3471 int i;
3472 int pages;
3473 unsigned char *buf, bufsize;
3474
3475 buf = kzalloc(256, GFP_KERNEL);
3476 if (!buf)
8383278d 3477 return false;
1b70150a
SC		 3478
3479 /* Get the size of the page list first */
3480 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3481 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3482 buf, HPSA_VPD_HEADER_SZ);
3483 if (rc != 0)
3484 goto exit_unsupported;
3485 pages = buf[3];
3486 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3487 bufsize = pages + HPSA_VPD_HEADER_SZ;
3488 else
3489 bufsize = 255;
3490
3491 /* Get the whole VPD page list */
3492 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3493 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3494 buf, bufsize);
3495 if (rc != 0)
3496 goto exit_unsupported;
3497
3498 pages = buf[3];
3499 for (i = 1; i <= pages; i++)
3500 if (buf[3 + i] == page)
3501 goto exit_supported;
3502exit_unsupported:
3503 kfree(buf);
8383278d 3504 return false;
1b70150a
SC		 3505exit_supported:
3506 kfree(buf);
8383278d 3507 return true;
1b70150a
SC		 3508}
3509
283b4a9b
SC		 3510static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3511 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3512{
3513 int rc;
3514 unsigned char *buf;
3515 u8 ioaccel_status;
3516
3517 this_device->offload_config = 0;
3518 this_device->offload_enabled = 0;
41ce4c35 3519 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3520
3521 buf = kzalloc(64, GFP_KERNEL);
3522 if (!buf)
3523 return;
1b70150a
SC		 3524 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3525 goto out;
283b4a9b 3526 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3527 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3528 if (rc != 0)
3529 goto out;
3530
3531#define IOACCEL_STATUS_BYTE 4
3532#define OFFLOAD_CONFIGURED_BIT 0x01
3533#define OFFLOAD_ENABLED_BIT 0x02
3534 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3535 this_device->offload_config =
3536 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3537 if (this_device->offload_config) {
3538 this_device->offload_enabled =
3539 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3540 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3541 this_device->offload_enabled = 0;
3542 }
41ce4c35 3543 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3544out:
3545 kfree(buf);
3546 return;
3547}
3548
edd16368
SC		 3549/* Get the device id from inquiry page 0x83 */
3550static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3551 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3552{
3553 int rc;
3554 unsigned char *buf;
3555
8383278d
ST		 3556 /* Does controller have VPD for device id? */
3557 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID))
3558 return 1; /* not supported */
3559
edd16368
SC		 3560 buf = kzalloc(64, GFP_KERNEL);
3561 if (!buf)
a84d794d 3562 return -ENOMEM;
8383278d
ST		 3563
3564 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
3565 HPSA_VPD_LV_DEVICE_ID, buf, 64);
3566 if (rc == 0) {
3567 if (buflen > 16)
3568 buflen = 16;
3569 memcpy(device_id, &buf[8], buflen);
3570 }
75d23d89 3571
edd16368 3572 kfree(buf);
75d23d89 3573
8383278d 3574 return rc; /*0 - got id, otherwise, didn't */
edd16368
SC		 3575}
3576
3577static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3578 void *buf, int bufsize,
edd16368
SC		 3579 int extended_response)
3580{
3581 int rc = IO_OK;
3582 struct CommandList *c;
3583 unsigned char scsi3addr[8];
3584 struct ErrorInfo *ei;
3585
45fcb86e 3586 c = cmd_alloc(h);
bf43caf3 3587
e89c0ae7
SC		 3588 /* address the controller */
3589 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3590 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3591 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3592 rc = -1;
3593 goto out;
3594 }
edd16368
SC		 3595 if (extended_response)
3596 c->Request.CDB[1] = extended_response;
25163bd5 3597 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 3598 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 3599 if (rc)
3600 goto out;
edd16368
SC		 3601 ei = c->err_info;
3602 if (ei->CommandStatus != 0 &&
3603 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3604 hpsa_scsi_interpret_error(h, c);
edd16368 3605 rc = -1;
283b4a9b 3606 } else {
03383736
DB		 3607 struct ReportLUNdata *rld = buf;
3608
3609 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3610 dev_err(&h->pdev->dev,
3611 "report luns requested format %u, got %u\n",
3612 extended_response,
03383736 3613 rld->extended_response_flag);
283b4a9b
SC		 3614 rc = -1;
3615 }
edd16368 3616 }
a2dac136 3617out:
45fcb86e 3618 cmd_free(h, c);
edd16368
SC		 3619 return rc;
3620}
3621
3622static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3623 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3624{
03383736
DB		 3625 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3626 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3627}
3628
3629static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3630 struct ReportLUNdata *buf, int bufsize)
3631{
3632 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3633}
3634
3635static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3636 int bus, int target, int lun)
3637{
3638 device->bus = bus;
3639 device->target = target;
3640 device->lun = lun;
3641}
3642
9846590e
SC		 3643/* Use VPD inquiry to get details of volume status */
3644static int hpsa_get_volume_status(struct ctlr_info *h,
3645 unsigned char scsi3addr[])
3646{
3647 int rc;
3648 int status;
3649 int size;
3650 unsigned char *buf;
3651
3652 buf = kzalloc(64, GFP_KERNEL);
3653 if (!buf)
3654 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3655
3656 /* Does controller have VPD for logical volume status? */
24a4b078 3657 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3658 goto exit_failed;
9846590e
SC		 3659
3660 /* Get the size of the VPD return buffer */
3661 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3662 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3663 if (rc != 0)
9846590e 3664 goto exit_failed;
9846590e
SC		 3665 size = buf[3];
3666
3667 /* Now get the whole VPD buffer */
3668 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3669 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3670 if (rc != 0)
9846590e 3671 goto exit_failed;
9846590e
SC		 3672 status = buf[4]; /* status byte */
3673
3674 kfree(buf);
3675 return status;
3676exit_failed:
3677 kfree(buf);
3678 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3679}
3680
3681/* Determine offline status of a volume.
3682 * Return either:
3683 * 0 (not offline)
67955ba3 3684 * 0xff (offline for unknown reasons)
9846590e
SC		 3685 * # (integer code indicating one of several NOT READY states
3686 * describing why a volume is to be kept offline)
3687 */
67955ba3 3688static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3689 unsigned char scsi3addr[])
3690{
3691 struct CommandList *c;
9437ac43
SC		 3692 unsigned char *sense;
3693 u8 sense_key, asc, ascq;
3694 int sense_len;
25163bd5 3695 int rc, ldstat = 0;
9846590e
SC		 3696 u16 cmd_status;
3697 u8 scsi_status;
3698#define ASC_LUN_NOT_READY 0x04
3699#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3700#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3701
3702 c = cmd_alloc(h);
bf43caf3 3703
9846590e 3704 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
c448ecfa
DB		 3705 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3706 DEFAULT_TIMEOUT);
25163bd5
WS		 3707 if (rc) {
3708 cmd_free(h, c);
3709 return 0;
3710 }
9846590e 3711 sense = c->err_info->SenseInfo;
9437ac43
SC		 3712 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3713 sense_len = sizeof(c->err_info->SenseInfo);
3714 else
3715 sense_len = c->err_info->SenseLen;
3716 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3717 cmd_status = c->err_info->CommandStatus;
3718 scsi_status = c->err_info->ScsiStatus;
3719 cmd_free(h, c);
3720 /* Is the volume 'not ready'? */
3721 if (cmd_status != CMD_TARGET_STATUS ||
3722 scsi_status != SAM_STAT_CHECK_CONDITION ||
3723 sense_key != NOT_READY ||
3724 asc != ASC_LUN_NOT_READY) {
3725 return 0;
3726 }
3727
3728 /* Determine the reason for not ready state */
3729 ldstat = hpsa_get_volume_status(h, scsi3addr);
3730
3731 /* Keep volume offline in certain cases: */
3732 switch (ldstat) {
3733 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3734 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3735 case HPSA_LV_UNDERGOING_RPI:
3736 case HPSA_LV_PENDING_RPI:
3737 case HPSA_LV_ENCRYPTED_NO_KEY:
3738 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3739 case HPSA_LV_UNDERGOING_ENCRYPTION:
3740 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3741 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3742 return ldstat;
3743 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3744 /* If VPD status page isn't available,
3745 * use ASC/ASCQ to determine state
3746 */
3747 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3748 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3749 return ldstat;
3750 break;
3751 default:
3752 break;
3753 }
3754 return 0;
3755}
3756
9b5c48c2
SC		 3757/*
3758 * Find out if a logical device supports aborts by simply trying one.
3759 * Smart Array may claim not to support aborts on logical drives, but
3760 * if a MSA2000 * is connected, the drives on that will be presented
3761 * by the Smart Array as logical drives, and aborts may be sent to
3762 * those devices successfully. So the simplest way to find out is
3763 * to simply try an abort and see how the device responds.
3764 */
3765static int hpsa_device_supports_aborts(struct ctlr_info *h,
3766 unsigned char *scsi3addr)
3767{
3768 struct CommandList *c;
3769 struct ErrorInfo *ei;
3770 int rc = 0;
3771
3772 u64 tag = (u64) -1; /* bogus tag */
3773
3774 /* Assume that physical devices support aborts */
3775 if (!is_logical_dev_addr_mode(scsi3addr))
3776 return 1;
3777
3778 c = cmd_alloc(h);
bf43caf3 3779
9b5c48c2 3780 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
c448ecfa
DB		 3781 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3782 DEFAULT_TIMEOUT);
9b5c48c2
SC		 3783 /* no unmap needed here because no data xfer. */
3784 ei = c->err_info;
3785 switch (ei->CommandStatus) {
3786 case CMD_INVALID:
3787 rc = 0;
3788 break;
3789 case CMD_UNABORTABLE:
3790 case CMD_ABORT_FAILED:
3791 rc = 1;
3792 break;
9437ac43
SC		 3793 case CMD_TMF_STATUS:
3794 rc = hpsa_evaluate_tmf_status(h, c);
3795 break;
9b5c48c2
SC		 3796 default:
3797 rc = 0;
3798 break;
3799 }
3800 cmd_free(h, c);
3801 return rc;
3802}
3803
edd16368 3804static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3805 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3806 unsigned char *is_OBDR_device)
edd16368 3807{
0b0e1d6c
SC		 3808
3809#define OBDR_SIG_OFFSET 43
3810#define OBDR_TAPE_SIG "$DR-10"
3811#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3812#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3813
ea6d3bc3 3814 unsigned char *inq_buff;
0b0e1d6c 3815 unsigned char *obdr_sig;
683fc444 3816 int rc = 0;
edd16368 3817
ea6d3bc3 3818 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3819 if (!inq_buff) {
3820 rc = -ENOMEM;
edd16368 3821 goto bail_out;
683fc444 3822 }
edd16368 3823
edd16368
SC		 3824 /* Do an inquiry to the device to see what it is. */
3825 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3826 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3827 /* Inquiry failed (msg printed already) */
3828 dev_err(&h->pdev->dev,
3829 "hpsa_update_device_info: inquiry failed\n");
683fc444 3830 rc = -EIO;
edd16368
SC		 3831 goto bail_out;
3832 }
3833
4af61e4f
DB		 3834 scsi_sanitize_inquiry_string(&inq_buff[8], 8);
3835 scsi_sanitize_inquiry_string(&inq_buff[16], 16);
75d23d89 3836
edd16368
SC		 3837 this_device->devtype = (inq_buff[0] & 0x1f);
3838 memcpy(this_device->scsi3addr, scsi3addr, 8);
3839 memcpy(this_device->vendor, &inq_buff[8],
3840 sizeof(this_device->vendor));
3841 memcpy(this_device->model, &inq_buff[16],
3842 sizeof(this_device->model));
edd16368
SC		 3843 memset(this_device->device_id, 0,
3844 sizeof(this_device->device_id));
8383278d
ST		 3845 if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
3846 sizeof(this_device->device_id)))
3847 dev_err(&h->pdev->dev,
3848 "hpsa%d: %s: can't get device id for host %d:C0:T%d:L%d\t%s\t%.16s\n",
3849 h->ctlr, __func__,
3850 h->scsi_host->host_no,
3851 this_device->target, this_device->lun,
3852 scsi_device_type(this_device->devtype),
3853 this_device->model);
edd16368 3854
af15ed36
DB		 3855 if ((this_device->devtype == TYPE_DISK ||
3856 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3857 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3858 int volume_offline;
3859
edd16368 3860 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3861 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3862 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3863 volume_offline = hpsa_volume_offline(h, scsi3addr);
3864 if (volume_offline < 0 || volume_offline > 0xff)
3865 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3866 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3867 } else {
edd16368 3868 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3869 this_device->offload_config = 0;
3870 this_device->offload_enabled = 0;
41ce4c35 3871 this_device->offload_to_be_enabled = 0;
a3144e0b 3872 this_device->hba_ioaccel_enabled = 0;
9846590e 3873 this_device->volume_offline = 0;
03383736 3874 this_device->queue_depth = h->nr_cmds;
283b4a9b 3875 }
edd16368 3876
0b0e1d6c
SC		 3877 if (is_OBDR_device) {
3878 /* See if this is a One-Button-Disaster-Recovery device
3879 * by looking for "$DR-10" at offset 43 in inquiry data.
3880 */
3881 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3882 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3883 strncmp(obdr_sig, OBDR_TAPE_SIG,
3884 OBDR_SIG_LEN) == 0);
3885 }
edd16368
SC		 3886 kfree(inq_buff);
3887 return 0;
3888
3889bail_out:
3890 kfree(inq_buff);
683fc444 3891 return rc;
edd16368
SC		 3892}
3893
9b5c48c2
SC		 3894static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3895 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3896{
3897 unsigned long flags;
3898 int rc, entry;
3899 /*
3900 * See if this device supports aborts. If we already know
3901 * the device, we already know if it supports aborts, otherwise
3902 * we have to find out if it supports aborts by trying one.
3903 */
3904 spin_lock_irqsave(&h->devlock, flags);
3905 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3906 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3907 entry >= 0 && entry < h->ndevices) {
3908 dev->supports_aborts = h->dev[entry]->supports_aborts;
3909 spin_unlock_irqrestore(&h->devlock, flags);
3910 } else {
3911 spin_unlock_irqrestore(&h->devlock, flags);
3912 dev->supports_aborts =
3913 hpsa_device_supports_aborts(h, scsi3addr);
3914 if (dev->supports_aborts < 0)
3915 dev->supports_aborts = 0;
3916 }
3917}
3918
c795505a
KB		 3919/*
3920 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3921 * Logical drive target and lun are assigned at this time, but
3922 * physical device lun and target assignment are deferred (assigned
3923 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3924*/
edd16368 3925static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3926 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3927{
c795505a 3928 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3929
3930 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3931 /* physical device, target and lun filled in later */
edd16368 3932 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3933 hpsa_set_bus_target_lun(device,
3934 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3935 else
1f310bde 3936 /* defer target, lun assignment for physical devices */
c795505a
KB		 3937 hpsa_set_bus_target_lun(device,
3938 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3939 return;
3940 }
3941 /* It's a logical device */
66749d0d 3942 if (device->external) {
1f310bde 3943 hpsa_set_bus_target_lun(device,
c795505a
KB		 3944 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3945 lunid & 0x00ff);
1f310bde 3946 return;
edd16368 3947 }
c795505a
KB		 3948 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3949 0, lunid & 0x3fff);
edd16368
SC		 3950}
3951
edd16368 3952
54b6e9e9
ST		 3953/*
3954 * Get address of physical disk used for an ioaccel2 mode command:
3955 * 1. Extract ioaccel2 handle from the command.
3956 * 2. Find a matching ioaccel2 handle from list of physical disks.
3957 * 3. Return:
3958 * 1 and set scsi3addr to address of matching physical
3959 * 0 if no matching physical disk was found.
3960 */
3961static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3962 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3963{
41ce4c35
SC		 3964 struct io_accel2_cmd *c2 =
3965 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3966 unsigned long flags;
54b6e9e9 3967 int i;
54b6e9e9 3968
41ce4c35
SC		 3969 spin_lock_irqsave(&h->devlock, flags);
3970 for (i = 0; i < h->ndevices; i++)
3971 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3972 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3973 sizeof(h->dev[i]->scsi3addr));
3974 spin_unlock_irqrestore(&h->devlock, flags);
3975 return 1;
3976 }
3977 spin_unlock_irqrestore(&h->devlock, flags);
3978 return 0;
54b6e9e9 3979}
41ce4c35 3980
66749d0d
ST		 3981static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3982 int i, int nphysicals, int nlocal_logicals)
3983{
3984 /* In report logicals, local logicals are listed first,
3985 * then any externals.
3986 */
3987 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3988
3989 if (i == raid_ctlr_position)
3990 return 0;
3991
3992 if (i < logicals_start)
3993 return 0;
3994
3995 /* i is in logicals range, but still within local logicals */
3996 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3997 return 0;
3998
3999 return 1; /* it's an external lun */
4000}
4001
edd16368
SC		 4002/*
4003 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
4004 * logdev. The number of luns in physdev and logdev are returned in
4005 * *nphysicals and *nlogicals, respectively.
4006 * Returns 0 on success, -1 otherwise.
4007 */
4008static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 4009 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 4010 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 4011{
03383736 4012 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 4013 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
4014 return -1;
4015 }
03383736 4016 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 4017 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 4018 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
4019 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 4020 *nphysicals = HPSA_MAX_PHYS_LUN;
4021 }
03383736 4022 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 4023 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
4024 return -1;
4025 }
6df1e954 4026 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 4027 /* Reject Logicals in excess of our max capability. */
4028 if (*nlogicals > HPSA_MAX_LUN) {
4029 dev_warn(&h->pdev->dev,
4030 "maximum logical LUNs (%d) exceeded. "
4031 "%d LUNs ignored.\n", HPSA_MAX_LUN,
4032 *nlogicals - HPSA_MAX_LUN);
4033 *nlogicals = HPSA_MAX_LUN;
4034 }
4035 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
4036 dev_warn(&h->pdev->dev,
4037 "maximum logical + physical LUNs (%d) exceeded. "
4038 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
4039 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
4040 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
4041 }
4042 return 0;
4043}
4044
42a91641
DB		 4045static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
4046 int i, int nphysicals, int nlogicals,
a93aa1fe 4047 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 4048 struct ReportLUNdata *logdev_list)
4049{
4050 /* Helper function, figure out where the LUN ID info is coming from
4051 * given index i, lists of physical and logical devices, where in
4052 * the list the raid controller is supposed to appear (first or last)
4053 */
4054
4055 int logicals_start = nphysicals + (raid_ctlr_position == 0);
4056 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
4057
4058 if (i == raid_ctlr_position)
4059 return RAID_CTLR_LUNID;
4060
4061 if (i < logicals_start)
d5b5d964
SC		 4062 return &physdev_list->LUN[i -
4063 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 4064
4065 if (i < last_device)
4066 return &logdev_list->LUN[i - nphysicals -
4067 (raid_ctlr_position == 0)][0];
4068 BUG();
4069 return NULL;
4070}
4071
03383736
DB		 4072/* get physical drive ioaccel handle and queue depth */
4073static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
4074 struct hpsa_scsi_dev_t *dev,
f2039b03 4075 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 4076 struct bmic_identify_physical_device *id_phys)
4077{
4078 int rc;
4b6e5597
ST		 4079 struct ext_report_lun_entry *rle;
4080
4081 /*
4082 * external targets don't support BMIC
4083 */
4084 if (dev->external) {
4085 dev->queue_depth = 7;
4086 return;
4087 }
4088
4089 rle = &rlep->LUN[rle_index];
03383736
DB		 4090
4091 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 4092 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 4093 dev->hba_ioaccel_enabled = 1;
03383736 4094 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 4095 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
4096 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 4097 sizeof(*id_phys));
4098 if (!rc)
4099 /* Reserve space for FW operations */
4100#define DRIVE_CMDS_RESERVED_FOR_FW 2
4101#define DRIVE_QUEUE_DEPTH 7
4102 dev->queue_depth =
4103 le16_to_cpu(id_phys->current_queue_depth_limit) -
4104 DRIVE_CMDS_RESERVED_FOR_FW;
4105 else
4106 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 4107}
4108
8270b862 4109static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 4110 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 4111 struct bmic_identify_physical_device *id_phys)
4112{
f2039b03
DB		 4113 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
4114
4115 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 4116 this_device->hba_ioaccel_enabled = 1;
4117
4118 memcpy(&this_device->active_path_index,
4119 &id_phys->active_path_number,
4120 sizeof(this_device->active_path_index));
4121 memcpy(&this_device->path_map,
4122 &id_phys->redundant_path_present_map,
4123 sizeof(this_device->path_map));
4124 memcpy(&this_device->box,
4125 &id_phys->alternate_paths_phys_box_on_port,
4126 sizeof(this_device->box));
4127 memcpy(&this_device->phys_connector,
4128 &id_phys->alternate_paths_phys_connector,
4129 sizeof(this_device->phys_connector));
4130 memcpy(&this_device->bay,
4131 &id_phys->phys_bay_in_box,
4132 sizeof(this_device->bay));
4133}
4134
66749d0d
ST		 4135/* get number of local logical disks. */
4136static int hpsa_set_local_logical_count(struct ctlr_info *h,
4137 struct bmic_identify_controller *id_ctlr,
4138 u32 *nlocals)
4139{
4140 int rc;
4141
4142 if (!id_ctlr) {
4143 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4144 __func__);
4145 return -ENOMEM;
4146 }
4147 memset(id_ctlr, 0, sizeof(*id_ctlr));
4148 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4149 if (!rc)
4150 if (id_ctlr->configured_logical_drive_count < 256)
4151 *nlocals = id_ctlr->configured_logical_drive_count;
4152 else
4153 *nlocals = le16_to_cpu(
4154 id_ctlr->extended_logical_unit_count);
4155 else
4156 *nlocals = -1;
4157 return rc;
4158}
4159
64ce60ca
DB		 4160static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
4161{
4162 struct bmic_identify_physical_device *id_phys;
4163 bool is_spare = false;
4164 int rc;
4165
4166 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
4167 if (!id_phys)
4168 return false;
4169
4170 rc = hpsa_bmic_id_physical_device(h,
4171 lunaddrbytes,
4172 GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
4173 id_phys, sizeof(*id_phys));
4174 if (rc == 0)
4175 is_spare = (id_phys->more_flags >> 6) & 0x01;
4176
4177 kfree(id_phys);
4178 return is_spare;
4179}
4180
4181#define RPL_DEV_FLAG_NON_DISK 0x1
4182#define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
4183#define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
4184
4185#define BMIC_DEVICE_TYPE_ENCLOSURE 6
4186
4187static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
4188 struct ext_report_lun_entry *rle)
4189{
4190 u8 device_flags;
4191 u8 device_type;
4192
4193 if (!MASKED_DEVICE(lunaddrbytes))
4194 return false;
4195
4196 device_flags = rle->device_flags;
4197 device_type = rle->device_type;
4198
4199 if (device_flags & RPL_DEV_FLAG_NON_DISK) {
4200 if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
4201 return false;
4202 return true;
4203 }
4204
4205 if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
4206 return false;
4207
4208 if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
4209 return false;
4210
4211 /*
4212 * Spares may be spun down, we do not want to
4213 * do an Inquiry to a RAID set spare drive as
4214 * that would have them spun up, that is a
4215 * performance hit because I/O to the RAID device
4216 * stops while the spin up occurs which can take
4217 * over 50 seconds.
4218 */
4219 if (hpsa_is_disk_spare(h, lunaddrbytes))
4220 return true;
4221
4222 return false;
4223}
66749d0d 4224
8aa60681 4225static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4226{
4227 /* the idea here is we could get notified
4228 * that some devices have changed, so we do a report
4229 * physical luns and report logical luns cmd, and adjust
4230 * our list of devices accordingly.
4231 *
4232 * The scsi3addr's of devices won't change so long as the
4233 * adapter is not reset. That means we can rescan and
4234 * tell which devices we already know about, vs. new
4235 * devices, vs. disappearing devices.
4236 */
a93aa1fe 4237 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4238 struct ReportLUNdata *logdev_list = NULL;
03383736 4239 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4240 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4241 u32 nphysicals = 0;
4242 u32 nlogicals = 0;
66749d0d 4243 u32 nlocal_logicals = 0;
01a02ffc 4244 u32 ndev_allocated = 0;
edd16368
SC		 4245 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4246 int ncurrent = 0;
4f4eb9f1 4247 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4248 int raid_ctlr_position;
04fa2f44 4249 bool physical_device;
aca4a520 4250 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4251
cfe5badc 4252 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 4253 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4254 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4255 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4256 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4257 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4258
03383736 4259 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4260 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4261 dev_err(&h->pdev->dev, "out of memory\n");
4262 goto out;
4263 }
4264 memset(lunzerobits, 0, sizeof(lunzerobits));
4265
853633e8
DB		 4266 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4267
03383736 4268 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4269 logdev_list, &nlogicals)) {
4270 h->drv_req_rescan = 1;
edd16368 4271 goto out;
853633e8 4272 }
edd16368 4273
66749d0d
ST		 4274 /* Set number of local logicals (non PTRAID) */
4275 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4276 dev_warn(&h->pdev->dev,
4277 "%s: Can't determine number of local logical devices.\n",
4278 __func__);
4279 }
edd16368 4280
aca4a520
ST		 4281 /* We might see up to the maximum number of logical and physical disks
4282 * plus external target devices, and a device for the local RAID
4283 * controller.
edd16368 4284 */
aca4a520 4285 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 4286
4287 /* Allocate the per device structures */
4288 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4289 if (i >= HPSA_MAX_DEVICES) {
4290 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4291 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4292 ndevs_to_allocate - HPSA_MAX_DEVICES);
4293 break;
4294 }
4295
edd16368
SC		 4296 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4297 if (!currentsd[i]) {
4298 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
4299 __FILE__, __LINE__);
853633e8 4300 h->drv_req_rescan = 1;
edd16368
SC		 4301 goto out;
4302 }
4303 ndev_allocated++;
4304 }
4305
8645291b 4306 if (is_scsi_rev_5(h))
339b2b14
SC		 4307 raid_ctlr_position = 0;
4308 else
4309 raid_ctlr_position = nphysicals + nlogicals;
4310
edd16368 4311 /* adjust our table of devices */
4f4eb9f1 4312 n_ext_target_devs = 0;
edd16368 4313 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4314 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4315 int rc = 0;
f2039b03 4316 int phys_dev_index = i - (raid_ctlr_position == 0);
64ce60ca 4317 bool skip_device = false;
edd16368 4318
04fa2f44 4319 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4320
4321 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4322 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4323 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35 4324
86cf7130
DB		 4325 /* Determine if this is a lun from an external target array */
4326 tmpdevice->external =
4327 figure_external_status(h, raid_ctlr_position, i,
4328 nphysicals, nlocal_logicals);
4329
64ce60ca
DB		 4330 /*
4331 * Skip over some devices such as a spare.
4332 */
4333 if (!tmpdevice->external && physical_device) {
4334 skip_device = hpsa_skip_device(h, lunaddrbytes,
4335 &physdev_list->LUN[phys_dev_index]);
4336 if (skip_device)
4337 continue;
4338 }
edd16368
SC		 4339
4340 /* Get device type, vendor, model, device id */
683fc444
DB		 4341 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4342 &is_OBDR);
4343 if (rc == -ENOMEM) {
4344 dev_warn(&h->pdev->dev,
4345 "Out of memory, rescan deferred.\n");
853633e8 4346 h->drv_req_rescan = 1;
683fc444 4347 goto out;
853633e8 4348 }
683fc444
DB		 4349 if (rc) {
4350 dev_warn(&h->pdev->dev,
4351 "Inquiry failed, skipping device.\n");
4352 continue;
4353 }
4354
1f310bde 4355 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 4356 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 4357 this_device = currentsd[ncurrent];
4358
34592254
ST		 4359 /* Turn on discovery_polling if there are ext target devices.
4360 * Event-based change notification is unreliable for those.
edd16368 4361 */
34592254
ST		 4362 if (!h->discovery_polling) {
4363 if (tmpdevice->external) {
4364 h->discovery_polling = 1;
4365 dev_info(&h->pdev->dev,
4366 "External target, activate discovery polling.\n");
4367 }
edd16368
SC		 4368 }
4369
34592254 4370
edd16368 4371 *this_device = *tmpdevice;
04fa2f44 4372 this_device->physical_device = physical_device;
edd16368 4373
04fa2f44
KB		 4374 /*
4375 * Expose all devices except for physical devices that
4376 * are masked.
4377 */
4378 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4379 this_device->expose_device = 0;
4380 else
4381 this_device->expose_device = 1;
41ce4c35 4382
d04e62b9
KB		 4383
4384 /*
4385 * Get the SAS address for physical devices that are exposed.
4386 */
4387 if (this_device->physical_device && this_device->expose_device)
4388 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4389
edd16368 4390 switch (this_device->devtype) {
0b0e1d6c 4391 case TYPE_ROM:
edd16368
SC		 4392 /* We don't *really* support actual CD-ROM devices,
4393 * just "One Button Disaster Recovery" tape drive
4394 * which temporarily pretends to be a CD-ROM drive.
4395 * So we check that the device is really an OBDR tape
4396 * device by checking for "$DR-10" in bytes 43-48 of
4397 * the inquiry data.
4398 */
0b0e1d6c
SC		 4399 if (is_OBDR)
4400 ncurrent++;
edd16368
SC		 4401 break;
4402 case TYPE_DISK:
af15ed36 4403 case TYPE_ZBC:
04fa2f44 4404 if (this_device->physical_device) {
b9092b79
KB		 4405 /* The disk is in HBA mode. */
4406 /* Never use RAID mapper in HBA mode. */
ecf418d1 4407 this_device->offload_enabled = 0;
b9092b79 4408 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4409 physdev_list, phys_dev_index, id_phys);
4410 hpsa_get_path_info(this_device,
4411 physdev_list, phys_dev_index, id_phys);
b9092b79 4412 }
ecf418d1 4413 ncurrent++;
edd16368
SC		 4414 break;
4415 case TYPE_TAPE:
4416 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4417 ncurrent++;
4418 break;
41ce4c35 4419 case TYPE_ENCLOSURE:
17a9e54a
DB		 4420 if (!this_device->external)
4421 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4422 physdev_list, phys_dev_index,
4423 this_device);
b9092b79 4424 ncurrent++;
41ce4c35 4425 break;
edd16368
SC		 4426 case TYPE_RAID:
4427 /* Only present the Smartarray HBA as a RAID controller.
4428 * If it's a RAID controller other than the HBA itself
4429 * (an external RAID controller, MSA500 or similar)
4430 * don't present it.
4431 */
4432 if (!is_hba_lunid(lunaddrbytes))
4433 break;
4434 ncurrent++;
4435 break;
4436 default:
4437 break;
4438 }
cfe5badc 4439 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4440 break;
4441 }
d04e62b9
KB		 4442
4443 if (h->sas_host == NULL) {
4444 int rc = 0;
4445
4446 rc = hpsa_add_sas_host(h);
4447 if (rc) {
4448 dev_warn(&h->pdev->dev,
4449 "Could not add sas host %d\n", rc);
4450 goto out;
4451 }
4452 }
4453
8aa60681 4454 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4455out:
4456 kfree(tmpdevice);
4457 for (i = 0; i < ndev_allocated; i++)
4458 kfree(currentsd[i]);
4459 kfree(currentsd);
edd16368
SC		 4460 kfree(physdev_list);
4461 kfree(logdev_list);
66749d0d 4462 kfree(id_ctlr);
03383736 4463 kfree(id_phys);
edd16368
SC		 4464}
4465
ec5cbf04
WS		 4466static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4467 struct scatterlist *sg)
4468{
4469 u64 addr64 = (u64) sg_dma_address(sg);
4470 unsigned int len = sg_dma_len(sg);
4471
4472 desc->Addr = cpu_to_le64(addr64);
4473 desc->Len = cpu_to_le32(len);
4474 desc->Ext = 0;
4475}
4476
c7ee65b3
WS		 4477/*
4478 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4479 * dma mapping and fills in the scatter gather entries of the
4480 * hpsa command, cp.
4481 */
33a2ffce 4482static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4483 struct CommandList *cp,
4484 struct scsi_cmnd *cmd)
4485{
edd16368 4486 struct scatterlist *sg;
b3a7ba7c 4487 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4488 struct SGDescriptor *curr_sg;
edd16368 4489
33a2ffce 4490 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4491
4492 use_sg = scsi_dma_map(cmd);
4493 if (use_sg < 0)
4494 return use_sg;
4495
4496 if (!use_sg)
4497 goto sglist_finished;
4498
b3a7ba7c
WS		 4499 /*
4500 * If the number of entries is greater than the max for a single list,
4501 * then we have a chained list; we will set up all but one entry in the
4502 * first list (the last entry is saved for link information);
4503 * otherwise, we don't have a chained list and we'll set up at each of
4504 * the entries in the one list.
4505 */
33a2ffce 4506 curr_sg = cp->SG;
b3a7ba7c
WS		 4507 chained = use_sg > h->max_cmd_sg_entries;
4508 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4509 last_sg = scsi_sg_count(cmd) - 1;
4510 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4511 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4512 curr_sg++;
4513 }
ec5cbf04 4514
b3a7ba7c
WS		 4515 if (chained) {
4516 /*
4517 * Continue with the chained list. Set curr_sg to the chained
4518 * list. Modify the limit to the total count less the entries
4519 * we've already set up. Resume the scan at the list entry
4520 * where the previous loop left off.
4521 */
4522 curr_sg = h->cmd_sg_list[cp->cmdindex];
4523 sg_limit = use_sg - sg_limit;
4524 for_each_sg(sg, sg, sg_limit, i) {
4525 hpsa_set_sg_descriptor(curr_sg, sg);
4526 curr_sg++;
4527 }
4528 }
4529
ec5cbf04 4530 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4531 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4532
4533 if (use_sg + chained > h->maxSG)
4534 h->maxSG = use_sg + chained;
4535
4536 if (chained) {
4537 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4538 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4539 if (hpsa_map_sg_chain_block(h, cp)) {
4540 scsi_dma_unmap(cmd);
4541 return -1;
4542 }
33a2ffce 4543 return 0;
edd16368
SC		 4544 }
4545
4546sglist_finished:
4547
01a02ffc 4548 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4549 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4550 return 0;
4551}
4552
283b4a9b
SC		 4553#define IO_ACCEL_INELIGIBLE (1)
4554static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4555{
4556 int is_write = 0;
4557 u32 block;
4558 u32 block_cnt;
4559
4560 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4561 switch (cdb[0]) {
4562 case WRITE_6:
4563 case WRITE_12:
4564 is_write = 1;
4565 case READ_6:
4566 case READ_12:
4567 if (*cdb_len == 6) {
abbada71
MR		 4568 block = (((cdb[1] & 0x1F) << 16) |
4569 (cdb[2] << 8) |
4570 cdb[3]);
283b4a9b 4571 block_cnt = cdb[4];
c8a6c9a6
DB		 4572 if (block_cnt == 0)
4573 block_cnt = 256;
283b4a9b
SC		 4574 } else {
4575 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4576 block = get_unaligned_be32(&cdb[2]);
4577 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4578 }
4579 if (block_cnt > 0xffff)
4580 return IO_ACCEL_INELIGIBLE;
4581
4582 cdb[0] = is_write ? WRITE_10 : READ_10;
4583 cdb[1] = 0;
4584 cdb[2] = (u8) (block >> 24);
4585 cdb[3] = (u8) (block >> 16);
4586 cdb[4] = (u8) (block >> 8);
4587 cdb[5] = (u8) (block);
4588 cdb[6] = 0;
4589 cdb[7] = (u8) (block_cnt >> 8);
4590 cdb[8] = (u8) (block_cnt);
4591 cdb[9] = 0;
4592 *cdb_len = 10;
4593 break;
4594 }
4595 return 0;
4596}
4597
c349775e 4598static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4599 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4600 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4601{
4602 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4603 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4604 unsigned int len;
4605 unsigned int total_len = 0;
4606 struct scatterlist *sg;
4607 u64 addr64;
4608 int use_sg, i;
4609 struct SGDescriptor *curr_sg;
4610 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4611
283b4a9b 4612 /* TODO: implement chaining support */
03383736
DB		 4613 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4614 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4615 return IO_ACCEL_INELIGIBLE;
03383736 4616 }
283b4a9b 4617
e1f7de0c
MG		 4618 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4619
03383736
DB		 4620 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4621 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4622 return IO_ACCEL_INELIGIBLE;
03383736 4623 }
283b4a9b 4624
e1f7de0c
MG		 4625 c->cmd_type = CMD_IOACCEL1;
4626
4627 /* Adjust the DMA address to point to the accelerated command buffer */
4628 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4629 (c->cmdindex * sizeof(*cp));
4630 BUG_ON(c->busaddr & 0x0000007F);
4631
4632 use_sg = scsi_dma_map(cmd);
03383736
DB		 4633 if (use_sg < 0) {
4634 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4635 return use_sg;
03383736 4636 }
e1f7de0c
MG		 4637
4638 if (use_sg) {
4639 curr_sg = cp->SG;
4640 scsi_for_each_sg(cmd, sg, use_sg, i) {
4641 addr64 = (u64) sg_dma_address(sg);
4642 len = sg_dma_len(sg);
4643 total_len += len;
50a0decf
SC		 4644 curr_sg->Addr = cpu_to_le64(addr64);
4645 curr_sg->Len = cpu_to_le32(len);
4646 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4647 curr_sg++;
4648 }
50a0decf 4649 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4650
4651 switch (cmd->sc_data_direction) {
4652 case DMA_TO_DEVICE:
4653 control |= IOACCEL1_CONTROL_DATA_OUT;
4654 break;
4655 case DMA_FROM_DEVICE:
4656 control |= IOACCEL1_CONTROL_DATA_IN;
4657 break;
4658 case DMA_NONE:
4659 control |= IOACCEL1_CONTROL_NODATAXFER;
4660 break;
4661 default:
4662 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4663 cmd->sc_data_direction);
4664 BUG();
4665 break;
4666 }
4667 } else {
4668 control |= IOACCEL1_CONTROL_NODATAXFER;
4669 }
4670
c349775e 4671 c->Header.SGList = use_sg;
e1f7de0c 4672 /* Fill out the command structure to submit */
2b08b3e9
DB		 4673 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4674 cp->transfer_len = cpu_to_le32(total_len);
4675 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4676 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4677 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4678 memcpy(cp->CDB, cdb, cdb_len);
4679 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4680 /* Tag was already set at init time. */
283b4a9b 4681 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4682 return 0;
4683}
edd16368 4684
283b4a9b
SC		 4685/*
4686 * Queue a command directly to a device behind the controller using the
4687 * I/O accelerator path.
4688 */
4689static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4690 struct CommandList *c)
4691{
4692 struct scsi_cmnd *cmd = c->scsi_cmd;
4693 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4694
45e596cd
DB		 4695 if (!dev)
4696 return -1;
4697
03383736
DB		 4698 c->phys_disk = dev;
4699
283b4a9b 4700 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4701 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4702}
4703
dd0e19f3
ST		 4704/*
4705 * Set encryption parameters for the ioaccel2 request
4706 */
4707static void set_encrypt_ioaccel2(struct ctlr_info *h,
4708 struct CommandList *c, struct io_accel2_cmd *cp)
4709{
4710 struct scsi_cmnd *cmd = c->scsi_cmd;
4711 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4712 struct raid_map_data *map = &dev->raid_map;
4713 u64 first_block;
4714
dd0e19f3 4715 /* Are we doing encryption on this device */
2b08b3e9 4716 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4717 return;
4718 /* Set the data encryption key index. */
4719 cp->dekindex = map->dekindex;
4720
4721 /* Set the encryption enable flag, encoded into direction field. */
4722 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4723
4724 /* Set encryption tweak values based on logical block address
4725 * If block size is 512, tweak value is LBA.
4726 * For other block sizes, tweak is (LBA * block size)/ 512)
4727 */
4728 switch (cmd->cmnd[0]) {
4729 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
dd0e19f3 4730 case READ_6:
abbada71
MR		 4731 case WRITE_6:
4732 first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
4733 (cmd->cmnd[2] << 8) |
4734 cmd->cmnd[3]);
dd0e19f3
ST		 4735 break;
4736 case WRITE_10:
4737 case READ_10:
dd0e19f3
ST		 4738 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4739 case WRITE_12:
4740 case READ_12:
2b08b3e9 4741 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4742 break;
4743 case WRITE_16:
4744 case READ_16:
2b08b3e9 4745 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4746 break;
4747 default:
4748 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4749 "ERROR: %s: size (0x%x) not supported for encryption\n",
4750 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4751 BUG();
4752 break;
4753 }
2b08b3e9
DB		 4754
4755 if (le32_to_cpu(map->volume_blk_size) != 512)
4756 first_block = first_block *
4757 le32_to_cpu(map->volume_blk_size)/512;
4758
4759 cp->tweak_lower = cpu_to_le32(first_block);
4760 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4761}
4762
c349775e
ST		 4763static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4764 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4765 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4766{
4767 struct scsi_cmnd *cmd = c->scsi_cmd;
4768 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4769 struct ioaccel2_sg_element *curr_sg;
4770 int use_sg, i;
4771 struct scatterlist *sg;
4772 u64 addr64;
4773 u32 len;
4774 u32 total_len = 0;
4775
45e596cd
DB		 4776 if (!cmd->device)
4777 return -1;
4778
4779 if (!cmd->device->hostdata)
4780 return -1;
4781
d9a729f3 4782 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4783
03383736
DB		 4784 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4785 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4786 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4787 }
4788
c349775e
ST		 4789 c->cmd_type = CMD_IOACCEL2;
4790 /* Adjust the DMA address to point to the accelerated command buffer */
4791 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4792 (c->cmdindex * sizeof(*cp));
4793 BUG_ON(c->busaddr & 0x0000007F);
4794
4795 memset(cp, 0, sizeof(*cp));
4796 cp->IU_type = IOACCEL2_IU_TYPE;
4797
4798 use_sg = scsi_dma_map(cmd);
03383736
DB		 4799 if (use_sg < 0) {
4800 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4801 return use_sg;
03383736 4802 }
c349775e
ST		 4803
4804 if (use_sg) {
c349775e 4805 curr_sg = cp->sg;
d9a729f3
WS		 4806 if (use_sg > h->ioaccel_maxsg) {
4807 addr64 = le64_to_cpu(
4808 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4809 curr_sg->address = cpu_to_le64(addr64);
4810 curr_sg->length = 0;
4811 curr_sg->reserved[0] = 0;
4812 curr_sg->reserved[1] = 0;
4813 curr_sg->reserved[2] = 0;
4814 curr_sg->chain_indicator = 0x80;
4815
4816 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4817 }
c349775e
ST		 4818 scsi_for_each_sg(cmd, sg, use_sg, i) {
4819 addr64 = (u64) sg_dma_address(sg);
4820 len = sg_dma_len(sg);
4821 total_len += len;
4822 curr_sg->address = cpu_to_le64(addr64);
4823 curr_sg->length = cpu_to_le32(len);
4824 curr_sg->reserved[0] = 0;
4825 curr_sg->reserved[1] = 0;
4826 curr_sg->reserved[2] = 0;
4827 curr_sg->chain_indicator = 0;
4828 curr_sg++;
4829 }
4830
4831 switch (cmd->sc_data_direction) {
4832 case DMA_TO_DEVICE:
dd0e19f3
ST		 4833 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4834 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4835 break;
4836 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4837 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4838 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4839 break;
4840 case DMA_NONE:
dd0e19f3
ST		 4841 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4842 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4843 break;
4844 default:
4845 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4846 cmd->sc_data_direction);
4847 BUG();
4848 break;
4849 }
4850 } else {
dd0e19f3
ST		 4851 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4852 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4853 }
dd0e19f3
ST		 4854
4855 /* Set encryption parameters, if necessary */
4856 set_encrypt_ioaccel2(h, c, cp);
4857
2b08b3e9 4858 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4859 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4860 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4861
c349775e
ST		 4862 cp->data_len = cpu_to_le32(total_len);
4863 cp->err_ptr = cpu_to_le64(c->busaddr +
4864 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4865 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4866
d9a729f3
WS		 4867 /* fill in sg elements */
4868 if (use_sg > h->ioaccel_maxsg) {
4869 cp->sg_count = 1;
a736e9b6 4870 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4871 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4872 atomic_dec(&phys_disk->ioaccel_cmds_out);
4873 scsi_dma_unmap(cmd);
4874 return -1;
4875 }
4876 } else
4877 cp->sg_count = (u8) use_sg;
4878
c349775e
ST		 4879 enqueue_cmd_and_start_io(h, c);
4880 return 0;
4881}
4882
4883/*
4884 * Queue a command to the correct I/O accelerator path.
4885 */
4886static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4887 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4888 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4889{
45e596cd
DB		 4890 if (!c->scsi_cmd->device)
4891 return -1;
4892
4893 if (!c->scsi_cmd->device->hostdata)
4894 return -1;
4895
03383736
DB		 4896 /* Try to honor the device's queue depth */
4897 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4898 phys_disk->queue_depth) {
4899 atomic_dec(&phys_disk->ioaccel_cmds_out);
4900 return IO_ACCEL_INELIGIBLE;
4901 }
c349775e
ST		 4902 if (h->transMethod & CFGTBL_Trans_io_accel1)
4903 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4904 cdb, cdb_len, scsi3addr,
4905 phys_disk);
c349775e
ST		 4906 else
4907 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4908 cdb, cdb_len, scsi3addr,
4909 phys_disk);
c349775e
ST		 4910}
4911
6b80b18f
ST		 4912static void raid_map_helper(struct raid_map_data *map,
4913 int offload_to_mirror, u32 *map_index, u32 *current_group)
4914{
4915 if (offload_to_mirror == 0) {
4916 /* use physical disk in the first mirrored group. */
2b08b3e9 4917 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4918 return;
4919 }
4920 do {
4921 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4922 *current_group = *map_index /
4923 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4924 if (offload_to_mirror == *current_group)
4925 continue;
2b08b3e9 4926 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4927 /* select map index from next group */
2b08b3e9 4928 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4929 (*current_group)++;
4930 } else {
4931 /* select map index from first group */
2b08b3e9 4932 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4933 *current_group = 0;
4934 }
4935 } while (offload_to_mirror != *current_group);
4936}
4937
283b4a9b
SC		 4938/*
4939 * Attempt to perform offload RAID mapping for a logical volume I/O.
4940 */
4941static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4942 struct CommandList *c)
4943{
4944 struct scsi_cmnd *cmd = c->scsi_cmd;
4945 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4946 struct raid_map_data *map = &dev->raid_map;
4947 struct raid_map_disk_data *dd = &map->data[0];
4948 int is_write = 0;
4949 u32 map_index;
4950 u64 first_block, last_block;
4951 u32 block_cnt;
4952 u32 blocks_per_row;
4953 u64 first_row, last_row;
4954 u32 first_row_offset, last_row_offset;
4955 u32 first_column, last_column;
6b80b18f
ST		 4956 u64 r0_first_row, r0_last_row;
4957 u32 r5or6_blocks_per_row;
4958 u64 r5or6_first_row, r5or6_last_row;
4959 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4960 u32 r5or6_first_column, r5or6_last_column;
4961 u32 total_disks_per_row;
4962 u32 stripesize;
4963 u32 first_group, last_group, current_group;
283b4a9b
SC		 4964 u32 map_row;
4965 u32 disk_handle;
4966 u64 disk_block;
4967 u32 disk_block_cnt;
4968 u8 cdb[16];
4969 u8 cdb_len;
2b08b3e9 4970 u16 strip_size;
283b4a9b
SC		 4971#if BITS_PER_LONG == 32
4972 u64 tmpdiv;
4973#endif
6b80b18f 4974 int offload_to_mirror;
283b4a9b 4975
45e596cd
DB		 4976 if (!dev)
4977 return -1;
4978
283b4a9b
SC		 4979 /* check for valid opcode, get LBA and block count */
4980 switch (cmd->cmnd[0]) {
4981 case WRITE_6:
4982 is_write = 1;
4983 case READ_6:
abbada71
MR		 4984 first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
4985 (cmd->cmnd[2] << 8) |
4986 cmd->cmnd[3]);
283b4a9b 4987 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4988 if (block_cnt == 0)
4989 block_cnt = 256;
283b4a9b
SC		 4990 break;
4991 case WRITE_10:
4992 is_write = 1;
4993 case READ_10:
4994 first_block =
4995 (((u64) cmd->cmnd[2]) << 24) |
4996 (((u64) cmd->cmnd[3]) << 16) |
4997 (((u64) cmd->cmnd[4]) << 8) |
4998 cmd->cmnd[5];
4999 block_cnt =
5000 (((u32) cmd->cmnd[7]) << 8) |
5001 cmd->cmnd[8];
5002 break;
5003 case WRITE_12:
5004 is_write = 1;
5005 case READ_12:
5006 first_block =
5007 (((u64) cmd->cmnd[2]) << 24) |
5008 (((u64) cmd->cmnd[3]) << 16) |
5009 (((u64) cmd->cmnd[4]) << 8) |
5010 cmd->cmnd[5];
5011 block_cnt =
5012 (((u32) cmd->cmnd[6]) << 24) |
5013 (((u32) cmd->cmnd[7]) << 16) |
5014 (((u32) cmd->cmnd[8]) << 8) |
5015 cmd->cmnd[9];
5016 break;
5017 case WRITE_16:
5018 is_write = 1;
5019 case READ_16:
5020 first_block =
5021 (((u64) cmd->cmnd[2]) << 56) |
5022 (((u64) cmd->cmnd[3]) << 48) |
5023 (((u64) cmd->cmnd[4]) << 40) |
5024 (((u64) cmd->cmnd[5]) << 32) |
5025 (((u64) cmd->cmnd[6]) << 24) |
5026 (((u64) cmd->cmnd[7]) << 16) |
5027 (((u64) cmd->cmnd[8]) << 8) |
5028 cmd->cmnd[9];
5029 block_cnt =
5030 (((u32) cmd->cmnd[10]) << 24) |
5031 (((u32) cmd->cmnd[11]) << 16) |
5032 (((u32) cmd->cmnd[12]) << 8) |
5033 cmd->cmnd[13];
5034 break;
5035 default:
5036 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
5037 }
283b4a9b
SC		 5038 last_block = first_block + block_cnt - 1;
5039
5040 /* check for write to non-RAID-0 */
5041 if (is_write && dev->raid_level != 0)
5042 return IO_ACCEL_INELIGIBLE;
5043
5044 /* check for invalid block or wraparound */
2b08b3e9
DB		 5045 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
5046 last_block < first_block)
283b4a9b
SC		 5047 return IO_ACCEL_INELIGIBLE;
5048
5049 /* calculate stripe information for the request */
2b08b3e9
DB		 5050 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
5051 le16_to_cpu(map->strip_size);
5052 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 5053#if BITS_PER_LONG == 32
5054 tmpdiv = first_block;
5055 (void) do_div(tmpdiv, blocks_per_row);
5056 first_row = tmpdiv;
5057 tmpdiv = last_block;
5058 (void) do_div(tmpdiv, blocks_per_row);
5059 last_row = tmpdiv;
5060 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
5061 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
5062 tmpdiv = first_row_offset;
2b08b3e9 5063 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 5064 first_column = tmpdiv;
5065 tmpdiv = last_row_offset;
2b08b3e9 5066 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 5067 last_column = tmpdiv;
5068#else
5069 first_row = first_block / blocks_per_row;
5070 last_row = last_block / blocks_per_row;
5071 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
5072 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 5073 first_column = first_row_offset / strip_size;
5074 last_column = last_row_offset / strip_size;
283b4a9b
SC		 5075#endif
5076
5077 /* if this isn't a single row/column then give to the controller */
5078 if ((first_row != last_row) || (first_column != last_column))
5079 return IO_ACCEL_INELIGIBLE;
5080
5081 /* proceeding with driver mapping */
2b08b3e9
DB		 5082 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
5083 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 5084 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5085 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5086 map_index = (map_row * total_disks_per_row) + first_column;
5087
5088 switch (dev->raid_level) {
5089 case HPSA_RAID_0:
5090 break; /* nothing special to do */
5091 case HPSA_RAID_1:
5092 /* Handles load balance across RAID 1 members.
5093 * (2-drive R1 and R10 with even # of drives.)
5094 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 5095 */
2b08b3e9 5096 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 5097 if (dev->offload_to_mirror)
2b08b3e9 5098 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 5099 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 5100 break;
5101 case HPSA_RAID_ADM:
5102 /* Handles N-way mirrors (R1-ADM)
5103 * and R10 with # of drives divisible by 3.)
5104 */
2b08b3e9 5105 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 5106
5107 offload_to_mirror = dev->offload_to_mirror;
5108 raid_map_helper(map, offload_to_mirror,
5109 &map_index, &current_group);
5110 /* set mirror group to use next time */
5111 offload_to_mirror =
2b08b3e9
DB		 5112 (offload_to_mirror >=
5113 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 5114 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 5115 dev->offload_to_mirror = offload_to_mirror;
5116 /* Avoid direct use of dev->offload_to_mirror within this
5117 * function since multiple threads might simultaneously
5118 * increment it beyond the range of dev->layout_map_count -1.
5119 */
5120 break;
5121 case HPSA_RAID_5:
5122 case HPSA_RAID_6:
2b08b3e9 5123 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 5124 break;
5125
5126 /* Verify first and last block are in same RAID group */
5127 r5or6_blocks_per_row =
2b08b3e9
DB		 5128 le16_to_cpu(map->strip_size) *
5129 le16_to_cpu(map->data_disks_per_row);
6b80b18f 5130 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 5131 stripesize = r5or6_blocks_per_row *
5132 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 5133#if BITS_PER_LONG == 32
5134 tmpdiv = first_block;
5135 first_group = do_div(tmpdiv, stripesize);
5136 tmpdiv = first_group;
5137 (void) do_div(tmpdiv, r5or6_blocks_per_row);
5138 first_group = tmpdiv;
5139 tmpdiv = last_block;
5140 last_group = do_div(tmpdiv, stripesize);
5141 tmpdiv = last_group;
5142 (void) do_div(tmpdiv, r5or6_blocks_per_row);
5143 last_group = tmpdiv;
5144#else
5145 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
5146 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 5147#endif
000ff7c2 5148 if (first_group != last_group)
6b80b18f
ST		 5149 return IO_ACCEL_INELIGIBLE;
5150
5151 /* Verify request is in a single row of RAID 5/6 */
5152#if BITS_PER_LONG == 32
5153 tmpdiv = first_block;
5154 (void) do_div(tmpdiv, stripesize);
5155 first_row = r5or6_first_row = r0_first_row = tmpdiv;
5156 tmpdiv = last_block;
5157 (void) do_div(tmpdiv, stripesize);
5158 r5or6_last_row = r0_last_row = tmpdiv;
5159#else
5160 first_row = r5or6_first_row = r0_first_row =
5161 first_block / stripesize;
5162 r5or6_last_row = r0_last_row = last_block / stripesize;
5163#endif
5164 if (r5or6_first_row != r5or6_last_row)
5165 return IO_ACCEL_INELIGIBLE;
5166
5167
5168 /* Verify request is in a single column */
5169#if BITS_PER_LONG == 32
5170 tmpdiv = first_block;
5171 first_row_offset = do_div(tmpdiv, stripesize);
5172 tmpdiv = first_row_offset;
5173 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
5174 r5or6_first_row_offset = first_row_offset;
5175 tmpdiv = last_block;
5176 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
5177 tmpdiv = r5or6_last_row_offset;
5178 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
5179 tmpdiv = r5or6_first_row_offset;
5180 (void) do_div(tmpdiv, map->strip_size);
5181 first_column = r5or6_first_column = tmpdiv;
5182 tmpdiv = r5or6_last_row_offset;
5183 (void) do_div(tmpdiv, map->strip_size);
5184 r5or6_last_column = tmpdiv;
5185#else
5186 first_row_offset = r5or6_first_row_offset =
5187 (u32)((first_block % stripesize) %
5188 r5or6_blocks_per_row);
5189
5190 r5or6_last_row_offset =
5191 (u32)((last_block % stripesize) %
5192 r5or6_blocks_per_row);
5193
5194 first_column = r5or6_first_column =
2b08b3e9 5195 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 5196 r5or6_last_column =
2b08b3e9 5197 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 5198#endif
5199 if (r5or6_first_column != r5or6_last_column)
5200 return IO_ACCEL_INELIGIBLE;
5201
5202 /* Request is eligible */
5203 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5204 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5205
5206 map_index = (first_group *
2b08b3e9 5207 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 5208 (map_row * total_disks_per_row) + first_column;
5209 break;
5210 default:
5211 return IO_ACCEL_INELIGIBLE;
283b4a9b 5212 }
6b80b18f 5213
07543e0c
SC		 5214 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
5215 return IO_ACCEL_INELIGIBLE;
5216
03383736 5217 c->phys_disk = dev->phys_disk[map_index];
c3390df4
DB		 5218 if (!c->phys_disk)
5219 return IO_ACCEL_INELIGIBLE;
03383736 5220
283b4a9b 5221 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 5222 disk_block = le64_to_cpu(map->disk_starting_blk) +
5223 first_row * le16_to_cpu(map->strip_size) +
5224 (first_row_offset - first_column *
5225 le16_to_cpu(map->strip_size));
283b4a9b
SC		 5226 disk_block_cnt = block_cnt;
5227
5228 /* handle differing logical/physical block sizes */
5229 if (map->phys_blk_shift) {
5230 disk_block <<= map->phys_blk_shift;
5231 disk_block_cnt <<= map->phys_blk_shift;
5232 }
5233 BUG_ON(disk_block_cnt > 0xffff);
5234
5235 /* build the new CDB for the physical disk I/O */
5236 if (disk_block > 0xffffffff) {
5237 cdb[0] = is_write ? WRITE_16 : READ_16;
5238 cdb[1] = 0;
5239 cdb[2] = (u8) (disk_block >> 56);
5240 cdb[3] = (u8) (disk_block >> 48);
5241 cdb[4] = (u8) (disk_block >> 40);
5242 cdb[5] = (u8) (disk_block >> 32);
5243 cdb[6] = (u8) (disk_block >> 24);
5244 cdb[7] = (u8) (disk_block >> 16);
5245 cdb[8] = (u8) (disk_block >> 8);
5246 cdb[9] = (u8) (disk_block);
5247 cdb[10] = (u8) (disk_block_cnt >> 24);
5248 cdb[11] = (u8) (disk_block_cnt >> 16);
5249 cdb[12] = (u8) (disk_block_cnt >> 8);
5250 cdb[13] = (u8) (disk_block_cnt);
5251 cdb[14] = 0;
5252 cdb[15] = 0;
5253 cdb_len = 16;
5254 } else {
5255 cdb[0] = is_write ? WRITE_10 : READ_10;
5256 cdb[1] = 0;
5257 cdb[2] = (u8) (disk_block >> 24);
5258 cdb[3] = (u8) (disk_block >> 16);
5259 cdb[4] = (u8) (disk_block >> 8);
5260 cdb[5] = (u8) (disk_block);
5261 cdb[6] = 0;
5262 cdb[7] = (u8) (disk_block_cnt >> 8);
5263 cdb[8] = (u8) (disk_block_cnt);
5264 cdb[9] = 0;
5265 cdb_len = 10;
5266 }
5267 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5268 dev->scsi3addr,
5269 dev->phys_disk[map_index]);
283b4a9b
SC		 5270}
5271
25163bd5
WS		 5272/*
5273 * Submit commands down the "normal" RAID stack path
5274 * All callers to hpsa_ciss_submit must check lockup_detected
5275 * beforehand, before (opt.) and after calling cmd_alloc
5276 */
574f05d3
SC		 5277static int hpsa_ciss_submit(struct ctlr_info *h,
5278 struct CommandList *c, struct scsi_cmnd *cmd,
5279 unsigned char scsi3addr[])
edd16368 5280{
edd16368 5281 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5282 c->cmd_type = CMD_SCSI;
5283 c->scsi_cmd = cmd;
5284 c->Header.ReplyQueue = 0; /* unused in simple mode */
5285 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5286 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5287
5288 /* Fill in the request block... */
5289
5290 c->Request.Timeout = 0;
edd16368
SC		 5291 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5292 c->Request.CDBLen = cmd->cmd_len;
5293 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5294 switch (cmd->sc_data_direction) {
5295 case DMA_TO_DEVICE:
a505b86f
SC		 5296 c->Request.type_attr_dir =
5297 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5298 break;
5299 case DMA_FROM_DEVICE:
a505b86f
SC		 5300 c->Request.type_attr_dir =
5301 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5302 break;
5303 case DMA_NONE:
a505b86f
SC		 5304 c->Request.type_attr_dir =
5305 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5306 break;
5307 case DMA_BIDIRECTIONAL:
5308 /* This can happen if a buggy application does a scsi passthru
5309 * and sets both inlen and outlen to non-zero. ( see
5310 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5311 */
5312
a505b86f
SC		 5313 c->Request.type_attr_dir =
5314 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5315 /* This is technically wrong, and hpsa controllers should
5316 * reject it with CMD_INVALID, which is the most correct
5317 * response, but non-fibre backends appear to let it
5318 * slide by, and give the same results as if this field
5319 * were set correctly. Either way is acceptable for
5320 * our purposes here.
5321 */
5322
5323 break;
5324
5325 default:
5326 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5327 cmd->sc_data_direction);
5328 BUG();
5329 break;
5330 }
5331
33a2ffce 5332 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5333 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5334 return SCSI_MLQUEUE_HOST_BUSY;
5335 }
5336 enqueue_cmd_and_start_io(h, c);
5337 /* the cmd'll come back via intr handler in complete_scsi_command() */
5338 return 0;
5339}
5340
360c73bd
SC		 5341static void hpsa_cmd_init(struct ctlr_info *h, int index,
5342 struct CommandList *c)
5343{
5344 dma_addr_t cmd_dma_handle, err_dma_handle;
5345
5346 /* Zero out all of commandlist except the last field, refcount */
5347 memset(c, 0, offsetof(struct CommandList, refcount));
5348 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5349 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5350 c->err_info = h->errinfo_pool + index;
5351 memset(c->err_info, 0, sizeof(*c->err_info));
5352 err_dma_handle = h->errinfo_pool_dhandle
5353 + index * sizeof(*c->err_info);
5354 c->cmdindex = index;
5355 c->busaddr = (u32) cmd_dma_handle;
5356 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5357 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5358 c->h = h;
a58e7e53 5359 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5360}
5361
5362static void hpsa_preinitialize_commands(struct ctlr_info *h)
5363{
5364 int i;
5365
5366 for (i = 0; i < h->nr_cmds; i++) {
5367 struct CommandList *c = h->cmd_pool + i;
5368
5369 hpsa_cmd_init(h, i, c);
5370 atomic_set(&c->refcount, 0);
5371 }
5372}
5373
5374static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5375 struct CommandList *c)
5376{
5377 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5378
73153fe5
WS		 5379 BUG_ON(c->cmdindex != index);
5380
360c73bd
SC		 5381 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5382 memset(c->err_info, 0, sizeof(*c->err_info));
5383 c->busaddr = (u32) cmd_dma_handle;
5384}
5385
592a0ad5
WS		 5386static int hpsa_ioaccel_submit(struct ctlr_info *h,
5387 struct CommandList *c, struct scsi_cmnd *cmd,
5388 unsigned char *scsi3addr)
5389{
5390 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5391 int rc = IO_ACCEL_INELIGIBLE;
5392
45e596cd
DB		 5393 if (!dev)
5394 return SCSI_MLQUEUE_HOST_BUSY;
5395
592a0ad5
WS		 5396 cmd->host_scribble = (unsigned char *) c;
5397
5398 if (dev->offload_enabled) {
5399 hpsa_cmd_init(h, c->cmdindex, c);
5400 c->cmd_type = CMD_SCSI;
5401 c->scsi_cmd = cmd;
5402 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5403 if (rc < 0) /* scsi_dma_map failed. */
5404 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5405 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5406 hpsa_cmd_init(h, c->cmdindex, c);
5407 c->cmd_type = CMD_SCSI;
5408 c->scsi_cmd = cmd;
5409 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5410 if (rc < 0) /* scsi_dma_map failed. */
5411 rc = SCSI_MLQUEUE_HOST_BUSY;
5412 }
5413 return rc;
5414}
5415
080ef1cc
DB		 5416static void hpsa_command_resubmit_worker(struct work_struct *work)
5417{
5418 struct scsi_cmnd *cmd;
5419 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5420 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5421
5422 cmd = c->scsi_cmd;
5423 dev = cmd->device->hostdata;
5424 if (!dev) {
5425 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5426 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5427 }
d604f533
WS		 5428 if (c->reset_pending)
5429 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 5430 if (c->abort_pending)
5431 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 5432 if (c->cmd_type == CMD_IOACCEL2) {
5433 struct ctlr_info *h = c->h;
5434 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5435 int rc;
5436
5437 if (c2->error_data.serv_response ==
5438 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5439 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5440 if (rc == 0)
5441 return;
5442 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5443 /*
5444 * If we get here, it means dma mapping failed.
5445 * Try again via scsi mid layer, which will
5446 * then get SCSI_MLQUEUE_HOST_BUSY.
5447 */
5448 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5449 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5450 }
5451 /* else, fall thru and resubmit down CISS path */
5452 }
5453 }
360c73bd 5454 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5455 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5456 /*
5457 * If we get here, it means dma mapping failed. Try
5458 * again via scsi mid layer, which will then get
5459 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5460 *
5461 * hpsa_ciss_submit will have already freed c
5462 * if it encountered a dma mapping failure.
080ef1cc
DB		 5463 */
5464 cmd->result = DID_IMM_RETRY << 16;
5465 cmd->scsi_done(cmd);
5466 }
5467}
5468
574f05d3
SC		 5469/* Running in struct Scsi_Host->host_lock less mode */
5470static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5471{
5472 struct ctlr_info *h;
5473 struct hpsa_scsi_dev_t *dev;
5474 unsigned char scsi3addr[8];
5475 struct CommandList *c;
5476 int rc = 0;
5477
5478 /* Get the ptr to our adapter structure out of cmd->host. */
5479 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5480
5481 BUG_ON(cmd->request->tag < 0);
5482
574f05d3
SC		 5483 dev = cmd->device->hostdata;
5484 if (!dev) {
ba74fdc4
DB		 5485 cmd->result = NOT_READY << 16; /* host byte */
5486 cmd->scsi_done(cmd);
5487 return 0;
5488 }
5489
5490 if (dev->removed) {
574f05d3
SC		 5491 cmd->result = DID_NO_CONNECT << 16;
5492 cmd->scsi_done(cmd);
5493 return 0;
5494 }
574f05d3 5495
73153fe5 5496 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5497
407863cb 5498 if (unlikely(lockup_detected(h))) {
25163bd5 5499 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5500 cmd->scsi_done(cmd);
5501 return 0;
5502 }
73153fe5 5503 c = cmd_tagged_alloc(h, cmd);
574f05d3 5504
407863cb
SC		 5505 /*
5506 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5507 * Retries always go down the normal I/O path.
5508 */
5509 if (likely(cmd->retries == 0 &&
5510 cmd->request->cmd_type == REQ_TYPE_FS &&
5511 h->acciopath_status)) {
592a0ad5
WS		 5512 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5513 if (rc == 0)
5514 return 0;
5515 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5516 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5517 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5518 }
5519 }
5520 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5521}
5522
8ebc9248 5523static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5524{
5525 unsigned long flags;
5526
8ebc9248
WS		 5527 spin_lock_irqsave(&h->scan_lock, flags);
5528 h->scan_finished = 1;
5529 wake_up_all(&h->scan_wait_queue);
5530 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5531}
5532
a08a8471
SC		 5533static void hpsa_scan_start(struct Scsi_Host *sh)
5534{
5535 struct ctlr_info *h = shost_to_hba(sh);
5536 unsigned long flags;
5537
8ebc9248
WS		 5538 /*
5539 * Don't let rescans be initiated on a controller known to be locked
5540 * up. If the controller locks up *during* a rescan, that thread is
5541 * probably hosed, but at least we can prevent new rescan threads from
5542 * piling up on a locked up controller.
5543 */
5544 if (unlikely(lockup_detected(h)))
5545 return hpsa_scan_complete(h);
5f389360 5546
a08a8471
SC		 5547 /* wait until any scan already in progress is finished. */
5548 while (1) {
5549 spin_lock_irqsave(&h->scan_lock, flags);
5550 if (h->scan_finished)
5551 break;
5552 spin_unlock_irqrestore(&h->scan_lock, flags);
5553 wait_event(h->scan_wait_queue, h->scan_finished);
5554 /* Note: We don't need to worry about a race between this
5555 * thread and driver unload because the midlayer will
5556 * have incremented the reference count, so unload won't
5557 * happen if we're in here.
5558 */
5559 }
5560 h->scan_finished = 0; /* mark scan as in progress */
5561 spin_unlock_irqrestore(&h->scan_lock, flags);
5562
8ebc9248
WS		 5563 if (unlikely(lockup_detected(h)))
5564 return hpsa_scan_complete(h);
5f389360 5565
8aa60681 5566 hpsa_update_scsi_devices(h);
a08a8471 5567
8ebc9248 5568 hpsa_scan_complete(h);
a08a8471
SC		 5569}
5570
7c0a0229
DB		 5571static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5572{
03383736
DB		 5573 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5574
5575 if (!logical_drive)
5576 return -ENODEV;
7c0a0229
DB		 5577
5578 if (qdepth < 1)
5579 qdepth = 1;
03383736
DB		 5580 else if (qdepth > logical_drive->queue_depth)
5581 qdepth = logical_drive->queue_depth;
5582
5583 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5584}
5585
a08a8471
SC		 5586static int hpsa_scan_finished(struct Scsi_Host *sh,
5587 unsigned long elapsed_time)
5588{
5589 struct ctlr_info *h = shost_to_hba(sh);
5590 unsigned long flags;
5591 int finished;
5592
5593 spin_lock_irqsave(&h->scan_lock, flags);
5594 finished = h->scan_finished;
5595 spin_unlock_irqrestore(&h->scan_lock, flags);
5596 return finished;
5597}
5598
2946e82b 5599static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5600{
b705690d 5601 struct Scsi_Host *sh;
edd16368 5602
b705690d 5603 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5604 if (sh == NULL) {
5605 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5606 return -ENOMEM;
5607 }
b705690d
SC		 5608
5609 sh->io_port = 0;
5610 sh->n_io_port = 0;
5611 sh->this_id = -1;
5612 sh->max_channel = 3;
5613 sh->max_cmd_len = MAX_COMMAND_SIZE;
5614 sh->max_lun = HPSA_MAX_LUN;
5615 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5616 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5617 sh->cmd_per_lun = sh->can_queue;
b705690d 5618 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5619 sh->transportt = hpsa_sas_transport_template;
b705690d
SC		 5620 sh->hostdata[0] = (unsigned long) h;
5621 sh->irq = h->intr[h->intr_mode];
5622 sh->unique_id = sh->irq;
64d513ac 5623
2946e82b 5624 h->scsi_host = sh;
b705690d 5625 return 0;
2946e82b 5626}
b705690d 5627
2946e82b
RE		 5628static int hpsa_scsi_add_host(struct ctlr_info *h)
5629{
5630 int rv;
5631
5632 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5633 if (rv) {
5634 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5635 return rv;
5636 }
5637 scsi_scan_host(h->scsi_host);
5638 return 0;
edd16368
SC		 5639}
5640
73153fe5
WS		 5641/*
5642 * The block layer has already gone to the trouble of picking out a unique,
5643 * small-integer tag for this request. We use an offset from that value as
5644 * an index to select our command block. (The offset allows us to reserve the
5645 * low-numbered entries for our own uses.)
5646 */
5647static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5648{
5649 int idx = scmd->request->tag;
5650
5651 if (idx < 0)
5652 return idx;
5653
5654 /* Offset to leave space for internal cmds. */
5655 return idx += HPSA_NRESERVED_CMDS;
5656}
5657
b69324ff
WS		 5658/*
5659 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5660 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5661 */
5662static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5663 struct CommandList *c, unsigned char lunaddr[],
5664 int reply_queue)
5665{
5666 int rc;
5667
5668 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5669 (void) fill_cmd(c, TEST_UNIT_READY, h,
5670 NULL, 0, 0, lunaddr, TYPE_CMD);
c448ecfa 5671 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
b69324ff
WS		 5672 if (rc)
5673 return rc;
5674 /* no unmap needed here because no data xfer. */
5675
5676 /* Check if the unit is already ready. */
5677 if (c->err_info->CommandStatus == CMD_SUCCESS)
5678 return 0;
5679
5680 /*
5681 * The first command sent after reset will receive "unit attention" to
5682 * indicate that the LUN has been reset...this is actually what we're
5683 * looking for (but, success is good too).
5684 */
5685 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5686 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5687 (c->err_info->SenseInfo[2] == NO_SENSE ||
5688 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5689 return 0;
5690
5691 return 1;
5692}
5693
5694/*
5695 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5696 * returns zero when the unit is ready, and non-zero when giving up.
5697 */
5698static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5699 struct CommandList *c,
5700 unsigned char lunaddr[], int reply_queue)
edd16368 5701{
8919358e 5702 int rc;
edd16368
SC		 5703 int count = 0;
5704 int waittime = 1; /* seconds */
edd16368
SC		 5705
5706 /* Send test unit ready until device ready, or give up. */
b69324ff 5707 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5708
b69324ff
WS		 5709 /*
5710 * Wait for a bit. do this first, because if we send
edd16368
SC		 5711 * the TUR right away, the reset will just abort it.
5712 */
5713 msleep(1000 * waittime);
b69324ff
WS		 5714
5715 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5716 if (!rc)
5717 break;
edd16368
SC		 5718
5719 /* Increase wait time with each try, up to a point. */
5720 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5721 waittime *= 2;
edd16368 5722
b69324ff
WS		 5723 dev_warn(&h->pdev->dev,
5724 "waiting %d secs for device to become ready.\n",
5725 waittime);
5726 }
edd16368 5727
b69324ff
WS		 5728 return rc;
5729}
edd16368 5730
b69324ff
WS		 5731static int wait_for_device_to_become_ready(struct ctlr_info *h,
5732 unsigned char lunaddr[],
5733 int reply_queue)
5734{
5735 int first_queue;
5736 int last_queue;
5737 int rq;
5738 int rc = 0;
5739 struct CommandList *c;
5740
5741 c = cmd_alloc(h);
5742
5743 /*
5744 * If no specific reply queue was requested, then send the TUR
5745 * repeatedly, requesting a reply on each reply queue; otherwise execute
5746 * the loop exactly once using only the specified queue.
5747 */
5748 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5749 first_queue = 0;
5750 last_queue = h->nreply_queues - 1;
5751 } else {
5752 first_queue = reply_queue;
5753 last_queue = reply_queue;
5754 }
5755
5756 for (rq = first_queue; rq <= last_queue; rq++) {
5757 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5758 if (rc)
edd16368 5759 break;
edd16368
SC		 5760 }
5761
5762 if (rc)
5763 dev_warn(&h->pdev->dev, "giving up on device.\n");
5764 else
5765 dev_warn(&h->pdev->dev, "device is ready.\n");
5766
45fcb86e 5767 cmd_free(h, c);
edd16368
SC		 5768 return rc;
5769}
5770
5771/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5772 * complaining. Doing a host- or bus-reset can't do anything good here.
5773 */
5774static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5775{
5776 int rc;
5777 struct ctlr_info *h;
5778 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5779 u8 reset_type;
2dc127bb 5780 char msg[48];
edd16368
SC		 5781
5782 /* find the controller to which the command to be aborted was sent */
5783 h = sdev_to_hba(scsicmd->device);
5784 if (h == NULL) /* paranoia */
5785 return FAILED;
e345893b
DB		 5786
5787 if (lockup_detected(h))
5788 return FAILED;
5789
edd16368
SC		 5790 dev = scsicmd->device->hostdata;
5791 if (!dev) {
d604f533 5792 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5793 return FAILED;
5794 }
25163bd5
WS		 5795
5796 /* if controller locked up, we can guarantee command won't complete */
5797 if (lockup_detected(h)) {
2dc127bb
DC		 5798 snprintf(msg, sizeof(msg),
5799 "cmd %d RESET FAILED, lockup detected",
5800 hpsa_get_cmd_index(scsicmd));
73153fe5 5801 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5802 return FAILED;
5803 }
5804
5805 /* this reset request might be the result of a lockup; check */
5806 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5807 snprintf(msg, sizeof(msg),
5808 "cmd %d RESET FAILED, new lockup detected",
5809 hpsa_get_cmd_index(scsicmd));
73153fe5 5810 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5811 return FAILED;
5812 }
5813
d604f533
WS		 5814 /* Do not attempt on controller */
5815 if (is_hba_lunid(dev->scsi3addr))
5816 return SUCCESS;
5817
0b9b7b6e
ST		 5818 if (is_logical_dev_addr_mode(dev->scsi3addr))
5819 reset_type = HPSA_DEVICE_RESET_MSG;
5820 else
5821 reset_type = HPSA_PHYS_TARGET_RESET;
5822
5823 sprintf(msg, "resetting %s",
5824 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5825 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5826
da03ded0 5827 h->reset_in_progress = 1;
25163bd5 5828
edd16368 5829 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5830 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5831 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5832 sprintf(msg, "reset %s %s",
5833 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5834 rc == 0 ? "completed successfully" : "failed");
d604f533 5835 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5836 h->reset_in_progress = 0;
d604f533 5837 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5838}
5839
6cba3f19
SC		 5840static void swizzle_abort_tag(u8 *tag)
5841{
5842 u8 original_tag[8];
5843
5844 memcpy(original_tag, tag, 8);
5845 tag[0] = original_tag[3];
5846 tag[1] = original_tag[2];
5847 tag[2] = original_tag[1];
5848 tag[3] = original_tag[0];
5849 tag[4] = original_tag[7];
5850 tag[5] = original_tag[6];
5851 tag[6] = original_tag[5];
5852 tag[7] = original_tag[4];
5853}
5854
17eb87d2 5855static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5856 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5857{
2b08b3e9 5858 u64 tag;
17eb87d2
ST		 5859 if (c->cmd_type == CMD_IOACCEL1) {
5860 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5861 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5862 tag = le64_to_cpu(cm1->tag);
5863 *tagupper = cpu_to_le32(tag >> 32);
5864 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5865 return;
5866 }
5867 if (c->cmd_type == CMD_IOACCEL2) {
5868 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5869 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5870 /* upper tag not used in ioaccel2 mode */
5871 memset(tagupper, 0, sizeof(*tagupper));
5872 *taglower = cm2->Tag;
54b6e9e9 5873 return;
17eb87d2 5874 }
2b08b3e9
DB		 5875 tag = le64_to_cpu(c->Header.tag);
5876 *tagupper = cpu_to_le32(tag >> 32);
5877 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5878}
5879
75167d2c 5880static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5881 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5882{
5883 int rc = IO_OK;
5884 struct CommandList *c;
5885 struct ErrorInfo *ei;
2b08b3e9 5886 __le32 tagupper, taglower;
75167d2c 5887
45fcb86e 5888 c = cmd_alloc(h);
75167d2c 5889
a2dac136 5890 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5891 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5892 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5893 if (h->needs_abort_tags_swizzled)
6cba3f19 5894 swizzle_abort_tag(&c->Request.CDB[4]);
c448ecfa 5895 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
17eb87d2 5896 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5897 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5898 __func__, tagupper, taglower);
75167d2c
SC		 5899 /* no unmap needed here because no data xfer. */
5900
5901 ei = c->err_info;
5902 switch (ei->CommandStatus) {
5903 case CMD_SUCCESS:
5904 break;
9437ac43
SC		 5905 case CMD_TMF_STATUS:
5906 rc = hpsa_evaluate_tmf_status(h, c);
5907 break;
75167d2c
SC		 5908 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5909 rc = -1;
5910 break;
5911 default:
5912 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5913 __func__, tagupper, taglower);
d1e8beac 5914 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5915 rc = -1;
5916 break;
5917 }
45fcb86e 5918 cmd_free(h, c);
dd0e19f3
ST		 5919 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5920 __func__, tagupper, taglower);
75167d2c
SC		 5921 return rc;
5922}
5923
8be986cc
SC		 5924static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5925 struct CommandList *command_to_abort, int reply_queue)
5926{
5927 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5928 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5929 struct io_accel2_cmd *c2a =
5930 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5931 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5932 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5933
45e596cd
DB		 5934 if (!dev)
5935 return;
5936
8be986cc
SC		 5937 /*
5938 * We're overlaying struct hpsa_tmf_struct on top of something which
5939 * was allocated as a struct io_accel2_cmd, so we better be sure it
5940 * actually fits, and doesn't overrun the error info space.
5941 */
5942 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5943 sizeof(struct io_accel2_cmd));
5944 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5945 offsetof(struct hpsa_tmf_struct, error_len) +
5946 sizeof(ac->error_len));
5947
5948 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5949 c->scsi_cmd = SCSI_CMD_BUSY;
5950
8be986cc
SC		 5951 /* Adjust the DMA address to point to the accelerated command buffer */
5952 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5953 (c->cmdindex * sizeof(struct io_accel2_cmd));
5954 BUG_ON(c->busaddr & 0x0000007F);
5955
5956 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5957 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5958 ac->reply_queue = reply_queue;
5959 ac->tmf = IOACCEL2_TMF_ABORT;
5960 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5961 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5962 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5963 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5964 ac->error_ptr = cpu_to_le64(c->busaddr +
5965 offsetof(struct io_accel2_cmd, error_data));
5966 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5967}
5968
54b6e9e9
ST		 5969/* ioaccel2 path firmware cannot handle abort task requests.
5970 * Change abort requests to physical target reset, and send to the
5971 * address of the physical disk used for the ioaccel 2 command.
5972 * Return 0 on success (IO_OK)
5973 * -1 on failure
5974 */
5975
5976static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5977 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5978{
5979 int rc = IO_OK;
5980 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5981 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5982 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5983 unsigned char *psa = &phys_scsi3addr[0];
5984
5985 /* Get a pointer to the hpsa logical device. */
7fa3030c 5986 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5987 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5988 if (dev == NULL) {
5989 dev_warn(&h->pdev->dev,
5990 "Cannot abort: no device pointer for command.\n");
5991 return -1; /* not abortable */
5992 }
5993
2ba8bfc8
SC		 5994 if (h->raid_offload_debug > 0)
5995 dev_info(&h->pdev->dev,
0d96ef5f 5996 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5997 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5998 "Reset as abort",
2ba8bfc8
SC		 5999 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
6000 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
6001
54b6e9e9
ST		 6002 if (!dev->offload_enabled) {
6003 dev_warn(&h->pdev->dev,
6004 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
6005 return -1; /* not abortable */
6006 }
6007
6008 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
6009 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
6010 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
6011 return -1; /* not abortable */
6012 }
6013
6014 /* send the reset */
2ba8bfc8
SC		 6015 if (h->raid_offload_debug > 0)
6016 dev_info(&h->pdev->dev,
6017 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
6018 psa[0], psa[1], psa[2], psa[3],
6019 psa[4], psa[5], psa[6], psa[7]);
b32ece0f 6020 rc = hpsa_do_reset(h, dev, psa, HPSA_PHYS_TARGET_RESET, reply_queue);
54b6e9e9
ST		 6021 if (rc != 0) {
6022 dev_warn(&h->pdev->dev,
6023 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
6024 psa[0], psa[1], psa[2], psa[3],
6025 psa[4], psa[5], psa[6], psa[7]);
6026 return rc; /* failed to reset */
6027 }
6028
6029 /* wait for device to recover */
b69324ff 6030 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 6031 dev_warn(&h->pdev->dev,
6032 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
6033 psa[0], psa[1], psa[2], psa[3],
6034 psa[4], psa[5], psa[6], psa[7]);
6035 return -1; /* failed to recover */
6036 }
6037
6038 /* device recovered */
6039 dev_info(&h->pdev->dev,
6040 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
6041 psa[0], psa[1], psa[2], psa[3],
6042 psa[4], psa[5], psa[6], psa[7]);
6043
6044 return rc; /* success */
6045}
6046
8be986cc
SC		 6047static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
6048 struct CommandList *abort, int reply_queue)
6049{
6050 int rc = IO_OK;
6051 struct CommandList *c;
6052 __le32 taglower, tagupper;
6053 struct hpsa_scsi_dev_t *dev;
6054 struct io_accel2_cmd *c2;
6055
6056 dev = abort->scsi_cmd->device->hostdata;
45e596cd
DB		 6057 if (!dev)
6058 return -1;
6059
8be986cc
SC		 6060 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
6061 return -1;
6062
6063 c = cmd_alloc(h);
6064 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
6065 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
c448ecfa 6066 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT);
8be986cc
SC		 6067 hpsa_get_tag(h, abort, &taglower, &tagupper);
6068 dev_dbg(&h->pdev->dev,
6069 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
6070 __func__, tagupper, taglower);
6071 /* no unmap needed here because no data xfer. */
6072
6073 dev_dbg(&h->pdev->dev,
6074 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
6075 __func__, tagupper, taglower, c2->error_data.serv_response);
6076 switch (c2->error_data.serv_response) {
6077 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
6078 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
6079 rc = 0;
6080 break;
6081 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
6082 case IOACCEL2_SERV_RESPONSE_FAILURE:
6083 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
6084 rc = -1;
6085 break;
6086 default:
6087 dev_warn(&h->pdev->dev,
6088 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
6089 __func__, tagupper, taglower,
6090 c2->error_data.serv_response);
6091 rc = -1;
6092 }
6093 cmd_free(h, c);
6094 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
6095 tagupper, taglower);
6096 return rc;
6097}
6098
6cba3f19 6099static int hpsa_send_abort_both_ways(struct ctlr_info *h,
39f3deb2 6100 struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue)
6cba3f19 6101{
8be986cc
SC		 6102 /*
6103 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 6104 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 6105 * but not all underlying firmware can handle abort TMF.
6106 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 6107 */
8be986cc 6108 if (abort->cmd_type == CMD_IOACCEL2) {
39f3deb2
DB		 6109 if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) ||
6110 dev->physical_device)
8be986cc
SC		 6111 return hpsa_send_abort_ioaccel2(h, abort,
6112 reply_queue);
6113 else
39f3deb2
DB		 6114 return hpsa_send_reset_as_abort_ioaccel2(h,
6115 dev->scsi3addr,
25163bd5 6116 abort, reply_queue);
8be986cc 6117 }
39f3deb2 6118 return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue);
25163bd5 6119}
54b6e9e9 6120
25163bd5
WS		 6121/* Find out which reply queue a command was meant to return on */
6122static int hpsa_extract_reply_queue(struct ctlr_info *h,
6123 struct CommandList *c)
6124{
6125 if (c->cmd_type == CMD_IOACCEL2)
6126 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
6127 return c->Header.ReplyQueue;
6cba3f19
SC		 6128}
6129
9b5c48c2
SC		 6130/*
6131 * Limit concurrency of abort commands to prevent
6132 * over-subscription of commands
6133 */
6134static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
6135{
6136#define ABORT_CMD_WAIT_MSECS 5000
6137 return !wait_event_timeout(h->abort_cmd_wait_queue,
6138 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
6139 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
6140}
6141
75167d2c
SC		 6142/* Send an abort for the specified command.
6143 * If the device and controller support it,
6144 * send a task abort request.
6145 */
6146static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
6147{
6148
a58e7e53 6149 int rc;
75167d2c
SC		 6150 struct ctlr_info *h;
6151 struct hpsa_scsi_dev_t *dev;
6152 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 6153 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
6154 char msg[256]; /* For debug messaging. */
6155 int ml = 0;
2b08b3e9 6156 __le32 tagupper, taglower;
25163bd5
WS		 6157 int refcount, reply_queue;
6158
6159 if (sc == NULL)
6160 return FAILED;
75167d2c 6161
9b5c48c2
SC		 6162 if (sc->device == NULL)
6163 return FAILED;
6164
75167d2c
SC		 6165 /* Find the controller of the command to be aborted */
6166 h = sdev_to_hba(sc->device);
9b5c48c2 6167 if (h == NULL)
75167d2c
SC		 6168 return FAILED;
6169
25163bd5
WS		 6170 /* Find the device of the command to be aborted */
6171 dev = sc->device->hostdata;
6172 if (!dev) {
6173 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
6174 msg);
e345893b 6175 return FAILED;
25163bd5
WS		 6176 }
6177
6178 /* If controller locked up, we can guarantee command won't complete */
6179 if (lockup_detected(h)) {
6180 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6181 "ABORT FAILED, lockup detected");
6182 return FAILED;
6183 }
6184
6185 /* This is a good time to check if controller lockup has occurred */
6186 if (detect_controller_lockup(h)) {
6187 hpsa_show_dev_msg(KERN_WARNING, h, dev,
6188 "ABORT FAILED, new lockup detected");
6189 return FAILED;
6190 }
e345893b 6191
75167d2c
SC		 6192 /* Check that controller supports some kind of task abort */
6193 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
6194 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6195 return FAILED;
6196
6197 memset(msg, 0, sizeof(msg));
4b761557 6198 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 6199 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 6200 sc->device->id, sc->device->lun,
4b761557 6201 "Aborting command", sc);
75167d2c 6202
75167d2c
SC		 6203 /* Get SCSI command to be aborted */
6204 abort = (struct CommandList *) sc->host_scribble;
6205 if (abort == NULL) {
281a7fd0
WS		 6206 /* This can happen if the command already completed. */
6207 return SUCCESS;
6208 }
6209 refcount = atomic_inc_return(&abort->refcount);
6210 if (refcount == 1) { /* Command is done already. */
6211 cmd_free(h, abort);
6212 return SUCCESS;
75167d2c 6213 }
9b5c48c2
SC		 6214
6215 /* Don't bother trying the abort if we know it won't work. */
6216 if (abort->cmd_type != CMD_IOACCEL2 &&
6217 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
6218 cmd_free(h, abort);
6219 return FAILED;
6220 }
6221
a58e7e53
WS		 6222 /*
6223 * Check that we're aborting the right command.
6224 * It's possible the CommandList already completed and got re-used.
6225 */
6226 if (abort->scsi_cmd != sc) {
6227 cmd_free(h, abort);
6228 return SUCCESS;
6229 }
6230
6231 abort->abort_pending = true;
17eb87d2 6232 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 6233 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 6234 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 6235 as = abort->scsi_cmd;
75167d2c 6236 if (as != NULL)
4b761557
RE		 6237 ml += sprintf(msg+ml,
6238 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
6239 as->cmd_len, as->cmnd[0], as->cmnd[1],
6240 as->serial_number);
6241 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 6242 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 6243
75167d2c
SC		 6244 /*
6245 * Command is in flight, or possibly already completed
6246 * by the firmware (but not to the scsi mid layer) but we can't
6247 * distinguish which. Send the abort down.
6248 */
9b5c48c2
SC		 6249 if (wait_for_available_abort_cmd(h)) {
6250 dev_warn(&h->pdev->dev,
4b761557
RE		 6251 "%s FAILED, timeout waiting for an abort command to become available.\n",
6252 msg);
9b5c48c2
SC		 6253 cmd_free(h, abort);
6254 return FAILED;
6255 }
39f3deb2 6256 rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue);
9b5c48c2
SC		 6257 atomic_inc(&h->abort_cmds_available);
6258 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 6259 if (rc != 0) {
4b761557 6260 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 6261 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 6262 "FAILED to abort command");
281a7fd0 6263 cmd_free(h, abort);
75167d2c
SC		 6264 return FAILED;
6265 }
4b761557 6266 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 6267 wait_event(h->event_sync_wait_queue,
a58e7e53 6268 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 6269 cmd_free(h, abort);
a58e7e53 6270 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 6271}
6272
73153fe5
WS		 6273/*
6274 * For operations with an associated SCSI command, a command block is allocated
6275 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6276 * block request tag as an index into a table of entries. cmd_tagged_free() is
6277 * the complement, although cmd_free() may be called instead.
6278 */
6279static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6280 struct scsi_cmnd *scmd)
6281{
6282 int idx = hpsa_get_cmd_index(scmd);
6283 struct CommandList *c = h->cmd_pool + idx;
6284
6285 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6286 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6287 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6288 /* The index value comes from the block layer, so if it's out of
6289 * bounds, it's probably not our bug.
6290 */
6291 BUG();
6292 }
6293
6294 atomic_inc(&c->refcount);
6295 if (unlikely(!hpsa_is_cmd_idle(c))) {
6296 /*
6297 * We expect that the SCSI layer will hand us a unique tag
6298 * value. Thus, there should never be a collision here between
6299 * two requests...because if the selected command isn't idle
6300 * then someone is going to be very disappointed.
6301 */
6302 dev_err(&h->pdev->dev,
6303 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6304 idx);
6305 if (c->scsi_cmd != NULL)
6306 scsi_print_command(c->scsi_cmd);
6307 scsi_print_command(scmd);
6308 }
6309
6310 hpsa_cmd_partial_init(h, idx, c);
6311 return c;
6312}
6313
6314static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6315{
6316 /*
6317 * Release our reference to the block. We don't need to do anything
6318 * else to free it, because it is accessed by index. (There's no point
6319 * in checking the result of the decrement, since we cannot guarantee
6320 * that there isn't a concurrent abort which is also accessing it.)
6321 */
6322 (void)atomic_dec(&c->refcount);
6323}
6324
edd16368
SC		 6325/*
6326 * For operations that cannot sleep, a command block is allocated at init,
6327 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6328 * which ones are free or in use. Lock must be held when calling this.
6329 * cmd_free() is the complement.
bf43caf3
RE		 6330 * This function never gives up and returns NULL. If it hangs,
6331 * another thread must call cmd_free() to free some tags.
edd16368 6332 */
281a7fd0 6333
edd16368
SC		 6334static struct CommandList *cmd_alloc(struct ctlr_info *h)
6335{
6336 struct CommandList *c;
360c73bd 6337 int refcount, i;
73153fe5 6338 int offset = 0;
4c413128 6339
33811026
RE		 6340 /*
6341 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6342 * multiple threads could get in here, and one thread could
6343 * be scanning through the list of bits looking for a free
6344 * one, but the free ones are always behind him, and other
6345 * threads sneak in behind him and eat them before he can
6346 * get to them, so that while there is always a free one, a
6347 * very unlucky thread might be starved anyway, never able to
6348 * beat the other threads. In reality, this happens so
6349 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6350 *
6351 * Note that we start allocating commands before the SCSI host structure
6352 * is initialized. Since the search starts at bit zero, this
6353 * all works, since we have at least one command structure available;
6354 * however, it means that the structures with the low indexes have to be
6355 * reserved for driver-initiated requests, while requests from the block
6356 * layer will use the higher indexes.
4c413128 6357 */
edd16368 6358
281a7fd0 6359 for (;;) {
73153fe5
WS		 6360 i = find_next_zero_bit(h->cmd_pool_bits,
6361 HPSA_NRESERVED_CMDS,
6362 offset);
6363 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6364 offset = 0;
6365 continue;
6366 }
6367 c = h->cmd_pool + i;
6368 refcount = atomic_inc_return(&c->refcount);
6369 if (unlikely(refcount > 1)) {
6370 cmd_free(h, c); /* already in use */
73153fe5 6371 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6372 continue;
6373 }
6374 set_bit(i & (BITS_PER_LONG - 1),
6375 h->cmd_pool_bits + (i / BITS_PER_LONG));
6376 break; /* it's ours now. */
6377 }
360c73bd 6378 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6379 return c;
6380}
6381
73153fe5
WS		 6382/*
6383 * This is the complementary operation to cmd_alloc(). Note, however, in some
6384 * corner cases it may also be used to free blocks allocated by
6385 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6386 * the clear-bit is harmless.
6387 */
edd16368
SC		 6388static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6389{
281a7fd0
WS		 6390 if (atomic_dec_and_test(&c->refcount)) {
6391 int i;
edd16368 6392
281a7fd0
WS		 6393 i = c - h->cmd_pool;
6394 clear_bit(i & (BITS_PER_LONG - 1),
6395 h->cmd_pool_bits + (i / BITS_PER_LONG));
6396 }
edd16368
SC		 6397}
6398
edd16368
SC		 6399#ifdef CONFIG_COMPAT
6400
42a91641
DB		 6401static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
6402 void __user *arg)
edd16368
SC		 6403{
6404 IOCTL32_Command_struct __user *arg32 =
6405 (IOCTL32_Command_struct __user *) arg;
6406 IOCTL_Command_struct arg64;
6407 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6408 int err;
6409 u32 cp;
6410
938abd84 6411 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6412 err = 0;
6413 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6414 sizeof(arg64.LUN_info));
6415 err |= copy_from_user(&arg64.Request, &arg32->Request,
6416 sizeof(arg64.Request));
6417 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6418 sizeof(arg64.error_info));
6419 err |= get_user(arg64.buf_size, &arg32->buf_size);
6420 err |= get_user(cp, &arg32->buf);
6421 arg64.buf = compat_ptr(cp);
6422 err |= copy_to_user(p, &arg64, sizeof(arg64));
6423
6424 if (err)
6425 return -EFAULT;
6426
42a91641 6427 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6428 if (err)
6429 return err;
6430 err |= copy_in_user(&arg32->error_info, &p->error_info,
6431 sizeof(arg32->error_info));
6432 if (err)
6433 return -EFAULT;
6434 return err;
6435}
6436
6437static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 6438 int cmd, void __user *arg)
edd16368
SC		 6439{
6440 BIG_IOCTL32_Command_struct __user *arg32 =
6441 (BIG_IOCTL32_Command_struct __user *) arg;
6442 BIG_IOCTL_Command_struct arg64;
6443 BIG_IOCTL_Command_struct __user *p =
6444 compat_alloc_user_space(sizeof(arg64));
6445 int err;
6446 u32 cp;
6447
938abd84 6448 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6449 err = 0;
6450 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6451 sizeof(arg64.LUN_info));
6452 err |= copy_from_user(&arg64.Request, &arg32->Request,
6453 sizeof(arg64.Request));
6454 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6455 sizeof(arg64.error_info));
6456 err |= get_user(arg64.buf_size, &arg32->buf_size);
6457 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6458 err |= get_user(cp, &arg32->buf);
6459 arg64.buf = compat_ptr(cp);
6460 err |= copy_to_user(p, &arg64, sizeof(arg64));
6461
6462 if (err)
6463 return -EFAULT;
6464
42a91641 6465 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6466 if (err)
6467 return err;
6468 err |= copy_in_user(&arg32->error_info, &p->error_info,
6469 sizeof(arg32->error_info));
6470 if (err)
6471 return -EFAULT;
6472 return err;
6473}
71fe75a7 6474
42a91641 6475static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 6476{
6477 switch (cmd) {
6478 case CCISS_GETPCIINFO:
6479 case CCISS_GETINTINFO:
6480 case CCISS_SETINTINFO:
6481 case CCISS_GETNODENAME:
6482 case CCISS_SETNODENAME:
6483 case CCISS_GETHEARTBEAT:
6484 case CCISS_GETBUSTYPES:
6485 case CCISS_GETFIRMVER:
6486 case CCISS_GETDRIVVER:
6487 case CCISS_REVALIDVOLS:
6488 case CCISS_DEREGDISK:
6489 case CCISS_REGNEWDISK:
6490 case CCISS_REGNEWD:
6491 case CCISS_RESCANDISK:
6492 case CCISS_GETLUNINFO:
6493 return hpsa_ioctl(dev, cmd, arg);
6494
6495 case CCISS_PASSTHRU32:
6496 return hpsa_ioctl32_passthru(dev, cmd, arg);
6497 case CCISS_BIG_PASSTHRU32:
6498 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6499
6500 default:
6501 return -ENOIOCTLCMD;
6502 }
6503}
edd16368
SC		 6504#endif
6505
6506static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6507{
6508 struct hpsa_pci_info pciinfo;
6509
6510 if (!argp)
6511 return -EINVAL;
6512 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6513 pciinfo.bus = h->pdev->bus->number;
6514 pciinfo.dev_fn = h->pdev->devfn;
6515 pciinfo.board_id = h->board_id;
6516 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6517 return -EFAULT;
6518 return 0;
6519}
6520
6521static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6522{
6523 DriverVer_type DriverVer;
6524 unsigned char vmaj, vmin, vsubmin;
6525 int rc;
6526
6527 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6528 &vmaj, &vmin, &vsubmin);
6529 if (rc != 3) {
6530 dev_info(&h->pdev->dev, "driver version string '%s' "
6531 "unrecognized.", HPSA_DRIVER_VERSION);
6532 vmaj = 0;
6533 vmin = 0;
6534 vsubmin = 0;
6535 }
6536 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6537 if (!argp)
6538 return -EINVAL;
6539 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6540 return -EFAULT;
6541 return 0;
6542}
6543
6544static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6545{
6546 IOCTL_Command_struct iocommand;
6547 struct CommandList *c;
6548 char *buff = NULL;
50a0decf 6549 u64 temp64;
c1f63c8f 6550 int rc = 0;
edd16368
SC		 6551
6552 if (!argp)
6553 return -EINVAL;
6554 if (!capable(CAP_SYS_RAWIO))
6555 return -EPERM;
6556 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6557 return -EFAULT;
6558 if ((iocommand.buf_size < 1) &&
6559 (iocommand.Request.Type.Direction != XFER_NONE)) {
6560 return -EINVAL;
6561 }
6562 if (iocommand.buf_size > 0) {
6563 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6564 if (buff == NULL)
2dd02d74 6565 return -ENOMEM;
9233fb10 6566 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6567 /* Copy the data into the buffer we created */
6568 if (copy_from_user(buff, iocommand.buf,
6569 iocommand.buf_size)) {
c1f63c8f
SC		 6570 rc = -EFAULT;
6571 goto out_kfree;
b03a7771
SC		 6572 }
6573 } else {
6574 memset(buff, 0, iocommand.buf_size);
edd16368 6575 }
b03a7771 6576 }
45fcb86e 6577 c = cmd_alloc(h);
bf43caf3 6578
edd16368
SC		 6579 /* Fill in the command type */
6580 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6581 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6582 /* Fill in Command Header */
6583 c->Header.ReplyQueue = 0; /* unused in simple mode */
6584 if (iocommand.buf_size > 0) { /* buffer to fill */
6585 c->Header.SGList = 1;
50a0decf 6586 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6587 } else { /* no buffers to fill */
6588 c->Header.SGList = 0;
50a0decf 6589 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6590 }
6591 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6592
6593 /* Fill in Request block */
6594 memcpy(&c->Request, &iocommand.Request,
6595 sizeof(c->Request));
6596
6597 /* Fill in the scatter gather information */
6598 if (iocommand.buf_size > 0) {
50a0decf 6599 temp64 = pci_map_single(h->pdev, buff,
edd16368 6600 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6601 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6602 c->SG[0].Addr = cpu_to_le64(0);
6603 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6604 rc = -ENOMEM;
6605 goto out;
6606 }
50a0decf
SC		 6607 c->SG[0].Addr = cpu_to_le64(temp64);
6608 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6609 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6610 }
c448ecfa 6611 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3fb134cb 6612 NO_TIMEOUT);
c2dd32e0
SC		 6613 if (iocommand.buf_size > 0)
6614 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6615 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6616 if (rc) {
6617 rc = -EIO;
6618 goto out;
6619 }
edd16368
SC		 6620
6621 /* Copy the error information out */
6622 memcpy(&iocommand.error_info, c->err_info,
6623 sizeof(iocommand.error_info));
6624 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6625 rc = -EFAULT;
6626 goto out;
edd16368 6627 }
9233fb10 6628 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6629 iocommand.buf_size > 0) {
edd16368
SC		 6630 /* Copy the data out of the buffer we created */
6631 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6632 rc = -EFAULT;
6633 goto out;
edd16368
SC		 6634 }
6635 }
c1f63c8f 6636out:
45fcb86e 6637 cmd_free(h, c);
c1f63c8f
SC		 6638out_kfree:
6639 kfree(buff);
6640 return rc;
edd16368
SC		 6641}
6642
6643static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6644{
6645 BIG_IOCTL_Command_struct *ioc;
6646 struct CommandList *c;
6647 unsigned char **buff = NULL;
6648 int *buff_size = NULL;
50a0decf 6649 u64 temp64;
edd16368
SC		 6650 BYTE sg_used = 0;
6651 int status = 0;
01a02ffc
SC		 6652 u32 left;
6653 u32 sz;
edd16368
SC		 6654 BYTE __user *data_ptr;
6655
6656 if (!argp)
6657 return -EINVAL;
6658 if (!capable(CAP_SYS_RAWIO))
6659 return -EPERM;
6660 ioc = (BIG_IOCTL_Command_struct *)
6661 kmalloc(sizeof(*ioc), GFP_KERNEL);
6662 if (!ioc) {
6663 status = -ENOMEM;
6664 goto cleanup1;
6665 }
6666 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6667 status = -EFAULT;
6668 goto cleanup1;
6669 }
6670 if ((ioc->buf_size < 1) &&
6671 (ioc->Request.Type.Direction != XFER_NONE)) {
6672 status = -EINVAL;
6673 goto cleanup1;
6674 }
6675 /* Check kmalloc limits using all SGs */
6676 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6677 status = -EINVAL;
6678 goto cleanup1;
6679 }
d66ae08b 6680 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6681 status = -EINVAL;
6682 goto cleanup1;
6683 }
d66ae08b 6684 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6685 if (!buff) {
6686 status = -ENOMEM;
6687 goto cleanup1;
6688 }
d66ae08b 6689 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6690 if (!buff_size) {
6691 status = -ENOMEM;
6692 goto cleanup1;
6693 }
6694 left = ioc->buf_size;
6695 data_ptr = ioc->buf;
6696 while (left) {
6697 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6698 buff_size[sg_used] = sz;
6699 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6700 if (buff[sg_used] == NULL) {
6701 status = -ENOMEM;
6702 goto cleanup1;
6703 }
9233fb10 6704 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6705 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6706 status = -EFAULT;
edd16368
SC		 6707 goto cleanup1;
6708 }
6709 } else
6710 memset(buff[sg_used], 0, sz);
6711 left -= sz;
6712 data_ptr += sz;
6713 sg_used++;
6714 }
45fcb86e 6715 c = cmd_alloc(h);
bf43caf3 6716
edd16368 6717 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6718 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6719 c->Header.ReplyQueue = 0;
50a0decf
SC		 6720 c->Header.SGList = (u8) sg_used;
6721 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6722 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6723 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6724 if (ioc->buf_size > 0) {
6725 int i;
6726 for (i = 0; i < sg_used; i++) {
50a0decf 6727 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6728 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6729 if (dma_mapping_error(&h->pdev->dev,
6730 (dma_addr_t) temp64)) {
6731 c->SG[i].Addr = cpu_to_le64(0);
6732 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6733 hpsa_pci_unmap(h->pdev, c, i,
6734 PCI_DMA_BIDIRECTIONAL);
6735 status = -ENOMEM;
e2d4a1f6 6736 goto cleanup0;
bcc48ffa 6737 }
50a0decf
SC		 6738 c->SG[i].Addr = cpu_to_le64(temp64);
6739 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6740 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6741 }
50a0decf 6742 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6743 }
c448ecfa 6744 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3fb134cb 6745 NO_TIMEOUT);
b03a7771
SC		 6746 if (sg_used)
6747 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6748 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6749 if (status) {
6750 status = -EIO;
6751 goto cleanup0;
6752 }
6753
edd16368
SC		 6754 /* Copy the error information out */
6755 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6756 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6757 status = -EFAULT;
e2d4a1f6 6758 goto cleanup0;
edd16368 6759 }
9233fb10 6760 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6761 int i;
6762
edd16368
SC		 6763 /* Copy the data out of the buffer we created */
6764 BYTE __user *ptr = ioc->buf;
6765 for (i = 0; i < sg_used; i++) {
6766 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6767 status = -EFAULT;
e2d4a1f6 6768 goto cleanup0;
edd16368
SC		 6769 }
6770 ptr += buff_size[i];
6771 }
6772 }
edd16368 6773 status = 0;
e2d4a1f6 6774cleanup0:
45fcb86e 6775 cmd_free(h, c);
edd16368
SC		 6776cleanup1:
6777 if (buff) {
2b08b3e9
DB		 6778 int i;
6779
edd16368
SC		 6780 for (i = 0; i < sg_used; i++)
6781 kfree(buff[i]);
6782 kfree(buff);
6783 }
6784 kfree(buff_size);
6785 kfree(ioc);
6786 return status;
6787}
6788
6789static void check_ioctl_unit_attention(struct ctlr_info *h,
6790 struct CommandList *c)
6791{
6792 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6793 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6794 (void) check_for_unit_attention(h, c);
6795}
0390f0c0 6796
edd16368
SC		 6797/*
6798 * ioctl
6799 */
42a91641 6800static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6801{
6802 struct ctlr_info *h;
6803 void __user *argp = (void __user *)arg;
0390f0c0 6804 int rc;
edd16368
SC		 6805
6806 h = sdev_to_hba(dev);
6807
6808 switch (cmd) {
6809 case CCISS_DEREGDISK:
6810 case CCISS_REGNEWDISK:
6811 case CCISS_REGNEWD:
a08a8471 6812 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6813 return 0;
6814 case CCISS_GETPCIINFO:
6815 return hpsa_getpciinfo_ioctl(h, argp);
6816 case CCISS_GETDRIVVER:
6817 return hpsa_getdrivver_ioctl(h, argp);
6818 case CCISS_PASSTHRU:
34f0c627 6819 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6820 return -EAGAIN;
6821 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6822 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6823 return rc;
edd16368 6824 case CCISS_BIG_PASSTHRU:
34f0c627 6825 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6826 return -EAGAIN;
6827 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6828 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6829 return rc;
edd16368
SC		 6830 default:
6831 return -ENOTTY;
6832 }
6833}
6834
bf43caf3 6835static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6836 u8 reset_type)
64670ac8
SC		 6837{
6838 struct CommandList *c;
6839
6840 c = cmd_alloc(h);
bf43caf3 6841
a2dac136
SC		 6842 /* fill_cmd can't fail here, no data buffer to map */
6843 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6844 RAID_CTLR_LUNID, TYPE_MSG);
6845 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6846 c->waiting = NULL;
6847 enqueue_cmd_and_start_io(h, c);
6848 /* Don't wait for completion, the reset won't complete. Don't free
6849 * the command either. This is the last command we will send before
6850 * re-initializing everything, so it doesn't matter and won't leak.
6851 */
bf43caf3 6852 return;
64670ac8
SC		 6853}
6854
a2dac136 6855static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6856 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6857 int cmd_type)
6858{
6859 int pci_dir = XFER_NONE;
9b5c48c2 6860 u64 tag; /* for commands to be aborted */
edd16368
SC		 6861
6862 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6863 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6864 c->Header.ReplyQueue = 0;
6865 if (buff != NULL && size > 0) {
6866 c->Header.SGList = 1;
50a0decf 6867 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6868 } else {
6869 c->Header.SGList = 0;
50a0decf 6870 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6871 }
edd16368
SC		 6872 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6873
edd16368
SC		 6874 if (cmd_type == TYPE_CMD) {
6875 switch (cmd) {
6876 case HPSA_INQUIRY:
6877 /* are we trying to read a vital product page */
b7bb24eb 6878 if (page_code & VPD_PAGE) {
edd16368 6879 c->Request.CDB[1] = 0x01;
b7bb24eb 6880 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6881 }
6882 c->Request.CDBLen = 6;
a505b86f
SC		 6883 c->Request.type_attr_dir =
6884 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6885 c->Request.Timeout = 0;
6886 c->Request.CDB[0] = HPSA_INQUIRY;
6887 c->Request.CDB[4] = size & 0xFF;
6888 break;
6889 case HPSA_REPORT_LOG:
6890 case HPSA_REPORT_PHYS:
6891 /* Talking to controller so It's a physical command
6892 mode = 00 target = 0. Nothing to write.
6893 */
6894 c->Request.CDBLen = 12;
a505b86f
SC		 6895 c->Request.type_attr_dir =
6896 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6897 c->Request.Timeout = 0;
6898 c->Request.CDB[0] = cmd;
6899 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6900 c->Request.CDB[7] = (size >> 16) & 0xFF;
6901 c->Request.CDB[8] = (size >> 8) & 0xFF;
6902 c->Request.CDB[9] = size & 0xFF;
6903 break;
c2adae44
ST		 6904 case BMIC_SENSE_DIAG_OPTIONS:
6905 c->Request.CDBLen = 16;
6906 c->Request.type_attr_dir =
6907 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6908 c->Request.Timeout = 0;
6909 /* Spec says this should be BMIC_WRITE */
6910 c->Request.CDB[0] = BMIC_READ;
6911 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6912 break;
6913 case BMIC_SET_DIAG_OPTIONS:
6914 c->Request.CDBLen = 16;
6915 c->Request.type_attr_dir =
6916 TYPE_ATTR_DIR(cmd_type,
6917 ATTR_SIMPLE, XFER_WRITE);
6918 c->Request.Timeout = 0;
6919 c->Request.CDB[0] = BMIC_WRITE;
6920 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6921 break;
edd16368
SC		 6922 case HPSA_CACHE_FLUSH:
6923 c->Request.CDBLen = 12;
a505b86f
SC		 6924 c->Request.type_attr_dir =
6925 TYPE_ATTR_DIR(cmd_type,
6926 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6927 c->Request.Timeout = 0;
6928 c->Request.CDB[0] = BMIC_WRITE;
6929 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6930 c->Request.CDB[7] = (size >> 8) & 0xFF;
6931 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6932 break;
6933 case TEST_UNIT_READY:
6934 c->Request.CDBLen = 6;
a505b86f
SC		 6935 c->Request.type_attr_dir =
6936 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6937 c->Request.Timeout = 0;
6938 break;
283b4a9b
SC		 6939 case HPSA_GET_RAID_MAP:
6940 c->Request.CDBLen = 12;
a505b86f
SC		 6941 c->Request.type_attr_dir =
6942 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6943 c->Request.Timeout = 0;
6944 c->Request.CDB[0] = HPSA_CISS_READ;
6945 c->Request.CDB[1] = cmd;
6946 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6947 c->Request.CDB[7] = (size >> 16) & 0xFF;
6948 c->Request.CDB[8] = (size >> 8) & 0xFF;
6949 c->Request.CDB[9] = size & 0xFF;
6950 break;
316b221a
SC		 6951 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6952 c->Request.CDBLen = 10;
a505b86f
SC		 6953 c->Request.type_attr_dir =
6954 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6955 c->Request.Timeout = 0;
6956 c->Request.CDB[0] = BMIC_READ;
6957 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6958 c->Request.CDB[7] = (size >> 16) & 0xFF;
6959 c->Request.CDB[8] = (size >> 8) & 0xFF;
6960 break;
03383736
DB		 6961 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6962 c->Request.CDBLen = 10;
6963 c->Request.type_attr_dir =
6964 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6965 c->Request.Timeout = 0;
6966 c->Request.CDB[0] = BMIC_READ;
6967 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6968 c->Request.CDB[7] = (size >> 16) & 0xFF;
6969 c->Request.CDB[8] = (size >> 8) & 0XFF;
6970 break;
d04e62b9
KB		 6971 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6972 c->Request.CDBLen = 10;
6973 c->Request.type_attr_dir =
6974 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6975 c->Request.Timeout = 0;
6976 c->Request.CDB[0] = BMIC_READ;
6977 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6978 c->Request.CDB[7] = (size >> 16) & 0xFF;
6979 c->Request.CDB[8] = (size >> 8) & 0XFF;
6980 break;
cca8f13b
DB		 6981 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6982 c->Request.CDBLen = 10;
6983 c->Request.type_attr_dir =
6984 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6985 c->Request.Timeout = 0;
6986 c->Request.CDB[0] = BMIC_READ;
6987 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6988 c->Request.CDB[7] = (size >> 16) & 0xFF;
6989 c->Request.CDB[8] = (size >> 8) & 0XFF;
6990 break;
66749d0d
ST		 6991 case BMIC_IDENTIFY_CONTROLLER:
6992 c->Request.CDBLen = 10;
6993 c->Request.type_attr_dir =
6994 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6995 c->Request.Timeout = 0;
6996 c->Request.CDB[0] = BMIC_READ;
6997 c->Request.CDB[1] = 0;
6998 c->Request.CDB[2] = 0;
6999 c->Request.CDB[3] = 0;
7000 c->Request.CDB[4] = 0;
7001 c->Request.CDB[5] = 0;
7002 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
7003 c->Request.CDB[7] = (size >> 16) & 0xFF;
7004 c->Request.CDB[8] = (size >> 8) & 0XFF;
7005 c->Request.CDB[9] = 0;
7006 break;
edd16368
SC		 7007 default:
7008 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
7009 BUG();
a2dac136 7010 return -1;
edd16368
SC		 7011 }
7012 } else if (cmd_type == TYPE_MSG) {
7013 switch (cmd) {
7014
0b9b7b6e
ST		 7015 case HPSA_PHYS_TARGET_RESET:
7016 c->Request.CDBLen = 16;
7017 c->Request.type_attr_dir =
7018 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
7019 c->Request.Timeout = 0; /* Don't time out */
7020 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
7021 c->Request.CDB[0] = HPSA_RESET;
7022 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
7023 /* Physical target reset needs no control bytes 4-7*/
7024 c->Request.CDB[4] = 0x00;
7025 c->Request.CDB[5] = 0x00;
7026 c->Request.CDB[6] = 0x00;
7027 c->Request.CDB[7] = 0x00;
7028 break;
edd16368
SC		 7029 case HPSA_DEVICE_RESET_MSG:
7030 c->Request.CDBLen = 16;
a505b86f
SC		 7031 c->Request.type_attr_dir =
7032 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 7033 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 7034 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
7035 c->Request.CDB[0] = cmd;
21e89afd 7036 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 7037 /* If bytes 4-7 are zero, it means reset the */
7038 /* LunID device */
7039 c->Request.CDB[4] = 0x00;
7040 c->Request.CDB[5] = 0x00;
7041 c->Request.CDB[6] = 0x00;
7042 c->Request.CDB[7] = 0x00;
75167d2c
SC		 7043 break;
7044 case HPSA_ABORT_MSG:
9b5c48c2 7045 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 7046 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 7047 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
7048 tag, c->Header.tag);
75167d2c 7049 c->Request.CDBLen = 16;
a505b86f
SC		 7050 c->Request.type_attr_dir =
7051 TYPE_ATTR_DIR(cmd_type,
7052 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 7053 c->Request.Timeout = 0; /* Don't time out */
7054 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
7055 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
7056 c->Request.CDB[2] = 0x00; /* reserved */
7057 c->Request.CDB[3] = 0x00; /* reserved */
7058 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 7059 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 7060 c->Request.CDB[12] = 0x00; /* reserved */
7061 c->Request.CDB[13] = 0x00; /* reserved */
7062 c->Request.CDB[14] = 0x00; /* reserved */
7063 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 7064 break;
edd16368
SC		 7065 default:
7066 dev_warn(&h->pdev->dev, "unknown message type %d\n",
7067 cmd);
7068 BUG();
7069 }
7070 } else {
7071 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
7072 BUG();
7073 }
7074
a505b86f 7075 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 7076 case XFER_READ:
7077 pci_dir = PCI_DMA_FROMDEVICE;
7078 break;
7079 case XFER_WRITE:
7080 pci_dir = PCI_DMA_TODEVICE;
7081 break;
7082 case XFER_NONE:
7083 pci_dir = PCI_DMA_NONE;
7084 break;
7085 default:
7086 pci_dir = PCI_DMA_BIDIRECTIONAL;
7087 }
a2dac136
SC		 7088 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
7089 return -1;
7090 return 0;
edd16368
SC		 7091}
7092
7093/*
7094 * Map (physical) PCI mem into (virtual) kernel space
7095 */
7096static void __iomem *remap_pci_mem(ulong base, ulong size)
7097{
7098 ulong page_base = ((ulong) base) & PAGE_MASK;
7099 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 7100 void __iomem *page_remapped = ioremap_nocache(page_base,
7101 page_offs + size);
edd16368
SC		 7102
7103 return page_remapped ? (page_remapped + page_offs) : NULL;
7104}
7105
254f796b 7106static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 7107{
254f796b 7108 return h->access.command_completed(h, q);
edd16368
SC		 7109}
7110
900c5440 7111static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 7112{
7113 return h->access.intr_pending(h);
7114}
7115
7116static inline long interrupt_not_for_us(struct ctlr_info *h)
7117{
10f66018
SC		 7118 return (h->access.intr_pending(h) == 0) ||
7119 (h->interrupts_enabled == 0);
edd16368
SC		 7120}
7121
01a02ffc
SC		 7122static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
7123 u32 raw_tag)
edd16368
SC		 7124{
7125 if (unlikely(tag_index >= h->nr_cmds)) {
7126 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
7127 return 1;
7128 }
7129 return 0;
7130}
7131
5a3d16f5 7132static inline void finish_cmd(struct CommandList *c)
edd16368 7133{
e85c5974 7134 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 7135 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
7136 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 7137 complete_scsi_command(c);
8be986cc 7138 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 7139 complete(c->waiting);
a104c99f
SC		 7140}
7141
303932fd 7142/* process completion of an indexed ("direct lookup") command */
1d94f94d 7143static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 7144 u32 raw_tag)
7145{
7146 u32 tag_index;
7147 struct CommandList *c;
7148
f2405db8 7149 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 7150 if (!bad_tag(h, tag_index, raw_tag)) {
7151 c = h->cmd_pool + tag_index;
7152 finish_cmd(c);
7153 }
303932fd
DB		 7154}
7155
64670ac8
SC		 7156/* Some controllers, like p400, will give us one interrupt
7157 * after a soft reset, even if we turned interrupts off.
7158 * Only need to check for this in the hpsa_xxx_discard_completions
7159 * functions.
7160 */
7161static int ignore_bogus_interrupt(struct ctlr_info *h)
7162{
7163 if (likely(!reset_devices))
7164 return 0;
7165
7166 if (likely(h->interrupts_enabled))
7167 return 0;
7168
7169 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
7170 "(known firmware bug.) Ignoring.\n");
7171
7172 return 1;
7173}
7174
254f796b
MG		 7175/*
7176 * Convert &h->q[x] (passed to interrupt handlers) back to h.
7177 * Relies on (h-q[x] == x) being true for x such that
7178 * 0 <= x < MAX_REPLY_QUEUES.
7179 */
7180static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 7181{
254f796b
MG		 7182 return container_of((queue - *queue), struct ctlr_info, q[0]);
7183}
7184
7185static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
7186{
7187 struct ctlr_info *h = queue_to_hba(queue);
7188 u8 q = *(u8 *) queue;
64670ac8
SC		 7189 u32 raw_tag;
7190
7191 if (ignore_bogus_interrupt(h))
7192 return IRQ_NONE;
7193
7194 if (interrupt_not_for_us(h))
7195 return IRQ_NONE;
a0c12413 7196 h->last_intr_timestamp = get_jiffies_64();
64670ac8 7197 while (interrupt_pending(h)) {
254f796b 7198 raw_tag = get_next_completion(h, q);
64670ac8 7199 while (raw_tag != FIFO_EMPTY)
254f796b 7200 raw_tag = next_command(h, q);
64670ac8 7201 }
64670ac8
SC		 7202 return IRQ_HANDLED;
7203}
7204
254f796b 7205static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 7206{
254f796b 7207 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 7208 u32 raw_tag;
254f796b 7209 u8 q = *(u8 *) queue;
64670ac8
SC		 7210
7211 if (ignore_bogus_interrupt(h))
7212 return IRQ_NONE;
7213
a0c12413 7214 h->last_intr_timestamp = get_jiffies_64();
254f796b 7215 raw_tag = get_next_completion(h, q);
64670ac8 7216 while (raw_tag != FIFO_EMPTY)
254f796b 7217 raw_tag = next_command(h, q);
64670ac8
SC		 7218 return IRQ_HANDLED;
7219}
7220
254f796b 7221static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 7222{
254f796b 7223 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 7224 u32 raw_tag;
254f796b 7225 u8 q = *(u8 *) queue;
edd16368
SC		 7226
7227 if (interrupt_not_for_us(h))
7228 return IRQ_NONE;
a0c12413 7229 h->last_intr_timestamp = get_jiffies_64();
10f66018 7230 while (interrupt_pending(h)) {
254f796b 7231 raw_tag = get_next_completion(h, q);
10f66018 7232 while (raw_tag != FIFO_EMPTY) {
f2405db8 7233 process_indexed_cmd(h, raw_tag);
254f796b 7234 raw_tag = next_command(h, q);
10f66018
SC		 7235 }
7236 }
10f66018
SC		 7237 return IRQ_HANDLED;
7238}
7239
254f796b 7240static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 7241{
254f796b 7242 struct ctlr_info *h = queue_to_hba(queue);
10f66018 7243 u32 raw_tag;
254f796b 7244 u8 q = *(u8 *) queue;
10f66018 7245
a0c12413 7246 h->last_intr_timestamp = get_jiffies_64();
254f796b 7247 raw_tag = get_next_completion(h, q);
303932fd 7248 while (raw_tag != FIFO_EMPTY) {
f2405db8 7249 process_indexed_cmd(h, raw_tag);
254f796b 7250 raw_tag = next_command(h, q);
edd16368 7251 }
edd16368
SC		 7252 return IRQ_HANDLED;
7253}
7254
a9a3a273
SC		 7255/* Send a message CDB to the firmware. Careful, this only works
7256 * in simple mode, not performant mode due to the tag lookup.
7257 * We only ever use this immediately after a controller reset.
7258 */
6f039790
GKH		 7259static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
7260 unsigned char type)
edd16368
SC		 7261{
7262 struct Command {
7263 struct CommandListHeader CommandHeader;
7264 struct RequestBlock Request;
7265 struct ErrDescriptor ErrorDescriptor;
7266 };
7267 struct Command *cmd;
7268 static const size_t cmd_sz = sizeof(*cmd) +
7269 sizeof(cmd->ErrorDescriptor);
7270 dma_addr_t paddr64;
2b08b3e9
DB		 7271 __le32 paddr32;
7272 u32 tag;
edd16368
SC		 7273 void __iomem *vaddr;
7274 int i, err;
7275
7276 vaddr = pci_ioremap_bar(pdev, 0);
7277 if (vaddr == NULL)
7278 return -ENOMEM;
7279
7280 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7281 * CCISS commands, so they must be allocated from the lower 4GiB of
7282 * memory.
7283 */
7284 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7285 if (err) {
7286 iounmap(vaddr);
1eaec8f3 7287 return err;
edd16368
SC		 7288 }
7289
7290 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
7291 if (cmd == NULL) {
7292 iounmap(vaddr);
7293 return -ENOMEM;
7294 }
7295
7296 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7297 * although there's no guarantee, we assume that the address is at
7298 * least 4-byte aligned (most likely, it's page-aligned).
7299 */
2b08b3e9 7300 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7301
7302 cmd->CommandHeader.ReplyQueue = 0;
7303 cmd->CommandHeader.SGList = 0;
50a0decf 7304 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7305 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7306 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7307
7308 cmd->Request.CDBLen = 16;
a505b86f
SC		 7309 cmd->Request.type_attr_dir =
7310 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7311 cmd->Request.Timeout = 0; /* Don't time out */
7312 cmd->Request.CDB[0] = opcode;
7313 cmd->Request.CDB[1] = type;
7314 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7315 cmd->ErrorDescriptor.Addr =
2b08b3e9 7316 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7317 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7318
2b08b3e9 7319 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7320
7321 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7322 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7323 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7324 break;
7325 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7326 }
7327
7328 iounmap(vaddr);
7329
7330 /* we leak the DMA buffer here ... no choice since the controller could
7331 * still complete the command.
7332 */
7333 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7334 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7335 opcode, type);
7336 return -ETIMEDOUT;
7337 }
7338
7339 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
7340
7341 if (tag & HPSA_ERROR_BIT) {
7342 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7343 opcode, type);
7344 return -EIO;
7345 }
7346
7347 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7348 opcode, type);
7349 return 0;
7350}
7351
edd16368
SC		 7352#define hpsa_noop(p) hpsa_message(p, 3, 0)
7353
1df8552a 7354static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7355 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7356{
1df8552a
SC		 7357
7358 if (use_doorbell) {
7359 /* For everything after the P600, the PCI power state method
7360 * of resetting the controller doesn't work, so we have this
7361 * other way using the doorbell register.
7362 */
7363 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7364 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7365
00701a96 7366 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7367 * doorbell reset and before any attempt to talk to the board
7368 * at all to ensure that this actually works and doesn't fall
7369 * over in some weird corner cases.
7370 */
00701a96 7371 msleep(10000);
1df8552a
SC		 7372 } else { /* Try to do it the PCI power state way */
7373
7374 /* Quoting from the Open CISS Specification: "The Power
7375 * Management Control/Status Register (CSR) controls the power
7376 * state of the device. The normal operating state is D0,
7377 * CSR=00h. The software off state is D3, CSR=03h. To reset
7378 * the controller, place the interface device in D3 then to D0,
7379 * this causes a secondary PCI reset which will reset the
7380 * controller." */
2662cab8
DB		 7381
7382 int rc = 0;
7383
1df8552a 7384 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7385
1df8552a 7386 /* enter the D3hot power management state */
2662cab8
DB		 7387 rc = pci_set_power_state(pdev, PCI_D3hot);
7388 if (rc)
7389 return rc;
1df8552a
SC		 7390
7391 msleep(500);
7392
7393 /* enter the D0 power management state */
2662cab8
DB		 7394 rc = pci_set_power_state(pdev, PCI_D0);
7395 if (rc)
7396 return rc;
c4853efe
MM		 7397
7398 /*
7399 * The P600 requires a small delay when changing states.
7400 * Otherwise we may think the board did not reset and we bail.
7401 * This for kdump only and is particular to the P600.
7402 */
7403 msleep(500);
1df8552a
SC		 7404 }
7405 return 0;
7406}
7407
6f039790 7408static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7409{
7410 memset(driver_version, 0, len);
f79cfec6 7411 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7412}
7413
6f039790 7414static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7415{
7416 char *driver_version;
7417 int i, size = sizeof(cfgtable->driver_version);
7418
7419 driver_version = kmalloc(size, GFP_KERNEL);
7420 if (!driver_version)
7421 return -ENOMEM;
7422
7423 init_driver_version(driver_version, size);
7424 for (i = 0; i < size; i++)
7425 writeb(driver_version[i], &cfgtable->driver_version[i]);
7426 kfree(driver_version);
7427 return 0;
7428}
7429
6f039790
GKH		 7430static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7431 unsigned char *driver_ver)
580ada3c
SC		 7432{
7433 int i;
7434
7435 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7436 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7437}
7438
6f039790 7439static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7440{
7441
7442 char *driver_ver, *old_driver_ver;
7443 int rc, size = sizeof(cfgtable->driver_version);
7444
7445 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
7446 if (!old_driver_ver)
7447 return -ENOMEM;
7448 driver_ver = old_driver_ver + size;
7449
7450 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7451 * should have been changed, otherwise we know the reset failed.
7452 */
7453 init_driver_version(old_driver_ver, size);
7454 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7455 rc = !memcmp(driver_ver, old_driver_ver, size);
7456 kfree(old_driver_ver);
7457 return rc;
7458}
edd16368 7459/* This does a hard reset of the controller using PCI power management
1df8552a 7460 * states or the using the doorbell register.
edd16368 7461 */
6b6c1cd7 7462static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7463{
1df8552a
SC		 7464 u64 cfg_offset;
7465 u32 cfg_base_addr;
7466 u64 cfg_base_addr_index;
7467 void __iomem *vaddr;
7468 unsigned long paddr;
580ada3c 7469 u32 misc_fw_support;
270d05de 7470 int rc;
1df8552a 7471 struct CfgTable __iomem *cfgtable;
cf0b08d0 7472 u32 use_doorbell;
270d05de 7473 u16 command_register;
edd16368 7474
1df8552a
SC		 7475 /* For controllers as old as the P600, this is very nearly
7476 * the same thing as
edd16368
SC		 7477 *
7478 * pci_save_state(pci_dev);
7479 * pci_set_power_state(pci_dev, PCI_D3hot);
7480 * pci_set_power_state(pci_dev, PCI_D0);
7481 * pci_restore_state(pci_dev);
7482 *
1df8552a
SC		 7483 * For controllers newer than the P600, the pci power state
7484 * method of resetting doesn't work so we have another way
7485 * using the doorbell register.
edd16368 7486 */
18867659 7487
60f923b9
RE		 7488 if (!ctlr_is_resettable(board_id)) {
7489 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7490 return -ENODEV;
7491 }
46380786
SC		 7492
7493 /* if controller is soft- but not hard resettable... */
7494 if (!ctlr_is_hard_resettable(board_id))
7495 return -ENOTSUPP; /* try soft reset later. */
18867659 7496
270d05de
SC		 7497 /* Save the PCI command register */
7498 pci_read_config_word(pdev, 4, &command_register);
270d05de 7499 pci_save_state(pdev);
edd16368 7500
1df8552a
SC		 7501 /* find the first memory BAR, so we can find the cfg table */
7502 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7503 if (rc)
7504 return rc;
7505 vaddr = remap_pci_mem(paddr, 0x250);
7506 if (!vaddr)
7507 return -ENOMEM;
edd16368 7508
1df8552a
SC		 7509 /* find cfgtable in order to check if reset via doorbell is supported */
7510 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7511 &cfg_base_addr_index, &cfg_offset);
7512 if (rc)
7513 goto unmap_vaddr;
7514 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7515 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7516 if (!cfgtable) {
7517 rc = -ENOMEM;
7518 goto unmap_vaddr;
7519 }
580ada3c
SC		 7520 rc = write_driver_ver_to_cfgtable(cfgtable);
7521 if (rc)
03741d95 7522 goto unmap_cfgtable;
edd16368 7523
cf0b08d0
SC		 7524 /* If reset via doorbell register is supported, use that.
7525 * There are two such methods. Favor the newest method.
7526 */
1df8552a 7527 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7528 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7529 if (use_doorbell) {
7530 use_doorbell = DOORBELL_CTLR_RESET2;
7531 } else {
7532 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7533 if (use_doorbell) {
050f7147
SC		 7534 dev_warn(&pdev->dev,
7535 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7536 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7537 goto unmap_cfgtable;
7538 }
7539 }
edd16368 7540
1df8552a
SC		 7541 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7542 if (rc)
7543 goto unmap_cfgtable;
edd16368 7544
270d05de 7545 pci_restore_state(pdev);
270d05de 7546 pci_write_config_word(pdev, 4, command_register);
edd16368 7547
1df8552a
SC		 7548 /* Some devices (notably the HP Smart Array 5i Controller)
7549 need a little pause here */
7550 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7551
fe5389c8
SC		 7552 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7553 if (rc) {
7554 dev_warn(&pdev->dev,
050f7147 7555 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7556 goto unmap_cfgtable;
7557 }
fe5389c8 7558
580ada3c
SC		 7559 rc = controller_reset_failed(vaddr);
7560 if (rc < 0)
7561 goto unmap_cfgtable;
7562 if (rc) {
64670ac8
SC		 7563 dev_warn(&pdev->dev, "Unable to successfully reset "
7564 "controller. Will try soft reset.\n");
7565 rc = -ENOTSUPP;
580ada3c 7566 } else {
64670ac8 7567 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7568 }
7569
7570unmap_cfgtable:
7571 iounmap(cfgtable);
7572
7573unmap_vaddr:
7574 iounmap(vaddr);
7575 return rc;
edd16368
SC		 7576}
7577
7578/*
7579 * We cannot read the structure directly, for portability we must use
7580 * the io functions.
7581 * This is for debug only.
7582 */
42a91641 7583static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7584{
58f8665c 7585#ifdef HPSA_DEBUG
edd16368
SC		 7586 int i;
7587 char temp_name[17];
7588
7589 dev_info(dev, "Controller Configuration information\n");
7590 dev_info(dev, "------------------------------------\n");
7591 for (i = 0; i < 4; i++)
7592 temp_name[i] = readb(&(tb->Signature[i]));
7593 temp_name[4] = '\0';
7594 dev_info(dev, " Signature = %s\n", temp_name);
7595 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7596 dev_info(dev, " Transport methods supported = 0x%x\n",
7597 readl(&(tb->TransportSupport)));
7598 dev_info(dev, " Transport methods active = 0x%x\n",
7599 readl(&(tb->TransportActive)));
7600 dev_info(dev, " Requested transport Method = 0x%x\n",
7601 readl(&(tb->HostWrite.TransportRequest)));
7602 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7603 readl(&(tb->HostWrite.CoalIntDelay)));
7604 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7605 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7606 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7607 readl(&(tb->CmdsOutMax)));
7608 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7609 for (i = 0; i < 16; i++)
7610 temp_name[i] = readb(&(tb->ServerName[i]));
7611 temp_name[16] = '\0';
7612 dev_info(dev, " Server Name = %s\n", temp_name);
7613 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7614 readl(&(tb->HeartBeat)));
edd16368 7615#endif /* HPSA_DEBUG */
58f8665c 7616}
edd16368
SC		 7617
7618static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7619{
7620 int i, offset, mem_type, bar_type;
7621
7622 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7623 return 0;
7624 offset = 0;
7625 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7626 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7627 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7628 offset += 4;
7629 else {
7630 mem_type = pci_resource_flags(pdev, i) &
7631 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7632 switch (mem_type) {
7633 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7634 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7635 offset += 4; /* 32 bit */
7636 break;
7637 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7638 offset += 8;
7639 break;
7640 default: /* reserved in PCI 2.2 */
7641 dev_warn(&pdev->dev,
7642 "base address is invalid\n");
7643 return -1;
7644 break;
7645 }
7646 }
7647 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7648 return i + 1;
7649 }
7650 return -1;
7651}
7652
cc64c817
RE		 7653static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7654{
7655 if (h->msix_vector) {
7656 if (h->pdev->msix_enabled)
7657 pci_disable_msix(h->pdev);
105a3dbc 7658 h->msix_vector = 0;
cc64c817
RE		 7659 } else if (h->msi_vector) {
7660 if (h->pdev->msi_enabled)
7661 pci_disable_msi(h->pdev);
105a3dbc 7662 h->msi_vector = 0;
cc64c817
RE		 7663 }
7664}
7665
edd16368 7666/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7667 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7668 */
6f039790 7669static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7670{
7671#ifdef CONFIG_PCI_MSI
254f796b
MG		 7672 int err, i;
7673 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7674
7675 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7676 hpsa_msix_entries[i].vector = 0;
7677 hpsa_msix_entries[i].entry = i;
7678 }
edd16368
SC		 7679
7680 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7681 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7682 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7683 goto default_int_mode;
55c06c71 7684 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7685 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7686 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7687 if (h->msix_vector > num_online_cpus())
7688 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7689 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7690 1, h->msix_vector);
7691 if (err < 0) {
7692 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7693 h->msix_vector = 0;
7694 goto single_msi_mode;
7695 } else if (err < h->msix_vector) {
55c06c71 7696 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7697 "available\n", err);
edd16368 7698 }
18fce3c4
AG		 7699 h->msix_vector = err;
7700 for (i = 0; i < h->msix_vector; i++)
7701 h->intr[i] = hpsa_msix_entries[i].vector;
7702 return;
edd16368 7703 }
18fce3c4 7704single_msi_mode:
55c06c71 7705 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7706 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7707 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7708 h->msi_vector = 1;
7709 else
55c06c71 7710 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7711 }
7712default_int_mode:
7713#endif /* CONFIG_PCI_MSI */
7714 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7715 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7716}
7717
6f039790 7718static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7719{
7720 int i;
7721 u32 subsystem_vendor_id, subsystem_device_id;
7722
7723 subsystem_vendor_id = pdev->subsystem_vendor;
7724 subsystem_device_id = pdev->subsystem_device;
7725 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7726 subsystem_vendor_id;
7727
7728 for (i = 0; i < ARRAY_SIZE(products); i++)
7729 if (*board_id == products[i].board_id)
7730 return i;
7731
6798cc0a
SC		 7732 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7733 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7734 !hpsa_allow_any) {
e5c880d1
SC		 7735 dev_warn(&pdev->dev, "unrecognized board ID: "
7736 "0x%08x, ignoring.\n", *board_id);
7737 return -ENODEV;
7738 }
7739 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7740}
7741
6f039790
GKH		 7742static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7743 unsigned long *memory_bar)
3a7774ce
SC		 7744{
7745 int i;
7746
7747 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7748 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7749 /* addressing mode bits already removed */
12d2cd47
SC		 7750 *memory_bar = pci_resource_start(pdev, i);
7751 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7752 *memory_bar);
7753 return 0;
7754 }
12d2cd47 7755 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7756 return -ENODEV;
7757}
7758
6f039790
GKH		 7759static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7760 int wait_for_ready)
2c4c8c8b 7761{
fe5389c8 7762 int i, iterations;
2c4c8c8b 7763 u32 scratchpad;
fe5389c8
SC		 7764 if (wait_for_ready)
7765 iterations = HPSA_BOARD_READY_ITERATIONS;
7766 else
7767 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7768
fe5389c8
SC		 7769 for (i = 0; i < iterations; i++) {
7770 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7771 if (wait_for_ready) {
7772 if (scratchpad == HPSA_FIRMWARE_READY)
7773 return 0;
7774 } else {
7775 if (scratchpad != HPSA_FIRMWARE_READY)
7776 return 0;
7777 }
2c4c8c8b
SC		 7778 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7779 }
fe5389c8 7780 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7781 return -ENODEV;
7782}
7783
6f039790
GKH		 7784static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7785 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7786 u64 *cfg_offset)
a51fd47f
SC		 7787{
7788 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7789 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7790 *cfg_base_addr &= (u32) 0x0000ffff;
7791 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7792 if (*cfg_base_addr_index == -1) {
7793 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7794 return -ENODEV;
7795 }
7796 return 0;
7797}
7798
195f2c65
RE		 7799static void hpsa_free_cfgtables(struct ctlr_info *h)
7800{
105a3dbc 7801 if (h->transtable) {
195f2c65 7802 iounmap(h->transtable);
105a3dbc
RE		 7803 h->transtable = NULL;
7804 }
7805 if (h->cfgtable) {
195f2c65 7806 iounmap(h->cfgtable);
105a3dbc
RE		 7807 h->cfgtable = NULL;
7808 }
195f2c65
RE		 7809}
7810
7811/* Find and map CISS config table and transfer table
7812+ * several items must be unmapped (freed) later
7813+ * */
6f039790 7814static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7815{
01a02ffc
SC		 7816 u64 cfg_offset;
7817 u32 cfg_base_addr;
7818 u64 cfg_base_addr_index;
303932fd 7819 u32 trans_offset;
a51fd47f 7820 int rc;
77c4495c 7821
a51fd47f
SC		 7822 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7823 &cfg_base_addr_index, &cfg_offset);
7824 if (rc)
7825 return rc;
77c4495c 7826 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7827 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7828 if (!h->cfgtable) {
7829 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7830 return -ENOMEM;
cd3c81c4 7831 }
580ada3c
SC		 7832 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7833 if (rc)
7834 return rc;
77c4495c 7835 /* Find performant mode table. */
a51fd47f 7836 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7837 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7838 cfg_base_addr_index)+cfg_offset+trans_offset,
7839 sizeof(*h->transtable));
195f2c65
RE		 7840 if (!h->transtable) {
7841 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7842 hpsa_free_cfgtables(h);
77c4495c 7843 return -ENOMEM;
195f2c65 7844 }
77c4495c
SC		 7845 return 0;
7846}
7847
6f039790 7848static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7849{
41ce4c35
SC		 7850#define MIN_MAX_COMMANDS 16
7851 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7852
7853 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7854
7855 /* Limit commands in memory limited kdump scenario. */
7856 if (reset_devices && h->max_commands > 32)
7857 h->max_commands = 32;
7858
41ce4c35
SC		 7859 if (h->max_commands < MIN_MAX_COMMANDS) {
7860 dev_warn(&h->pdev->dev,
7861 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7862 h->max_commands,
7863 MIN_MAX_COMMANDS);
7864 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7865 }
7866}
7867
c7ee65b3
WS		 7868/* If the controller reports that the total max sg entries is greater than 512,
7869 * then we know that chained SG blocks work. (Original smart arrays did not
7870 * support chained SG blocks and would return zero for max sg entries.)
7871 */
7872static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7873{
7874 return h->maxsgentries > 512;
7875}
7876
b93d7536
SC		 7877/* Interrogate the hardware for some limits:
7878 * max commands, max SG elements without chaining, and with chaining,
7879 * SG chain block size, etc.
7880 */
6f039790 7881static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7882{
cba3d38b 7883 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7884 h->nr_cmds = h->max_commands;
b93d7536 7885 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7886 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7887 if (hpsa_supports_chained_sg_blocks(h)) {
7888 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7889 h->max_cmd_sg_entries = 32;
1a63ea6f 7890 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7891 h->maxsgentries--; /* save one for chain pointer */
7892 } else {
c7ee65b3
WS		 7893 /*
7894 * Original smart arrays supported at most 31 s/g entries
7895 * embedded inline in the command (trying to use more
7896 * would lock up the controller)
7897 */
7898 h->max_cmd_sg_entries = 31;
1a63ea6f 7899 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7900 h->chainsize = 0;
b93d7536 7901 }
75167d2c
SC		 7902
7903 /* Find out what task management functions are supported and cache */
7904 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7905 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7906 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7907 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7908 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7909 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7910 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7911}
7912
76c46e49
SC		 7913static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7914{
0fc9fd40 7915 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7916 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7917 return false;
7918 }
7919 return true;
7920}
7921
97a5e98c 7922static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7923{
97a5e98c 7924 u32 driver_support;
f7c39101 7925
97a5e98c 7926 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7927 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7928#ifdef CONFIG_X86
97a5e98c 7929 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7930#endif
28e13446
SC		 7931 driver_support |= ENABLE_UNIT_ATTN;
7932 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7933}
7934
3d0eab67
SC		 7935/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7936 * in a prefetch beyond physical memory.
7937 */
7938static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7939{
7940 u32 dma_prefetch;
7941
7942 if (h->board_id != 0x3225103C)
7943 return;
7944 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7945 dma_prefetch |= 0x8000;
7946 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7947}
7948
c706a795 7949static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7950{
7951 int i;
7952 u32 doorbell_value;
7953 unsigned long flags;
7954 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7955 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7956 spin_lock_irqsave(&h->lock, flags);
7957 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7958 spin_unlock_irqrestore(&h->lock, flags);
7959 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7960 goto done;
76438d08 7961 /* delay and try again */
007e7aa9 7962 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7963 }
c706a795
RE		 7964 return -ENODEV;
7965done:
7966 return 0;
76438d08
SC		 7967}
7968
c706a795 7969static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7970{
7971 int i;
6eaf46fd
SC		 7972 u32 doorbell_value;
7973 unsigned long flags;
eb6b2ae9
SC		 7974
7975 /* under certain very rare conditions, this can take awhile.
7976 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7977 * as we enter this code.)
7978 */
007e7aa9 7979 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7980 if (h->remove_in_progress)
7981 goto done;
6eaf46fd
SC		 7982 spin_lock_irqsave(&h->lock, flags);
7983 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7984 spin_unlock_irqrestore(&h->lock, flags);
382be668 7985 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7986 goto done;
eb6b2ae9 7987 /* delay and try again */
007e7aa9 7988 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7989 }
c706a795
RE		 7990 return -ENODEV;
7991done:
7992 return 0;
3f4336f3
SC		 7993}
7994
c706a795 7995/* return -ENODEV or other reason on error, 0 on success */
6f039790 7996static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7997{
7998 u32 trans_support;
7999
8000 trans_support = readl(&(h->cfgtable->TransportSupport));
8001 if (!(trans_support & SIMPLE_MODE))
8002 return -ENOTSUPP;
8003
8004 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 8005
3f4336f3
SC		 8006 /* Update the field, and then ring the doorbell */
8007 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 8008 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 8009 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8010 if (hpsa_wait_for_mode_change_ack(h))
8011 goto error;
eb6b2ae9 8012 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 8013 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
8014 goto error;
960a30e7 8015 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 8016 return 0;
283b4a9b 8017error:
050f7147 8018 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 8019 return -ENODEV;
eb6b2ae9
SC		 8020}
8021
195f2c65
RE		 8022/* free items allocated or mapped by hpsa_pci_init */
8023static void hpsa_free_pci_init(struct ctlr_info *h)
8024{
8025 hpsa_free_cfgtables(h); /* pci_init 4 */
8026 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 8027 h->vaddr = NULL;
195f2c65 8028 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 8029 /*
8030 * call pci_disable_device before pci_release_regions per
8031 * Documentation/PCI/pci.txt
8032 */
195f2c65 8033 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 8034 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 8035}
8036
8037/* several items must be freed later */
6f039790 8038static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 8039{
eb6b2ae9 8040 int prod_index, err;
edd16368 8041
e5c880d1
SC		 8042 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
8043 if (prod_index < 0)
60f923b9 8044 return prod_index;
e5c880d1
SC		 8045 h->product_name = products[prod_index].product_name;
8046 h->access = *(products[prod_index].access);
edd16368 8047
9b5c48c2
SC		 8048 h->needs_abort_tags_swizzled =
8049 ctlr_needs_abort_tags_swizzled(h->board_id);
8050
e5a44df8
MG		 8051 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
8052 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
8053
55c06c71 8054 err = pci_enable_device(h->pdev);
edd16368 8055 if (err) {
195f2c65 8056 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 8057 pci_disable_device(h->pdev);
edd16368
SC		 8058 return err;
8059 }
8060
f79cfec6 8061 err = pci_request_regions(h->pdev, HPSA);
edd16368 8062 if (err) {
55c06c71 8063 dev_err(&h->pdev->dev,
195f2c65 8064 "failed to obtain PCI resources\n");
943a7021
RE		 8065 pci_disable_device(h->pdev);
8066 return err;
edd16368 8067 }
4fa604e1
RE		 8068
8069 pci_set_master(h->pdev);
8070
6b3f4c52 8071 hpsa_interrupt_mode(h);
12d2cd47 8072 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 8073 if (err)
195f2c65 8074 goto clean2; /* intmode+region, pci */
edd16368 8075 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 8076 if (!h->vaddr) {
195f2c65 8077 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 8078 err = -ENOMEM;
195f2c65 8079 goto clean2; /* intmode+region, pci */
204892e9 8080 }
fe5389c8 8081 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 8082 if (err)
195f2c65 8083 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 8084 err = hpsa_find_cfgtables(h);
8085 if (err)
195f2c65 8086 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 8087 hpsa_find_board_params(h);
edd16368 8088
76c46e49 8089 if (!hpsa_CISS_signature_present(h)) {
edd16368 8090 err = -ENODEV;
195f2c65 8091 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 8092 }
97a5e98c 8093 hpsa_set_driver_support_bits(h);
3d0eab67 8094 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 8095 err = hpsa_enter_simple_mode(h);
8096 if (err)
195f2c65 8097 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 8098 return 0;
8099
195f2c65
RE		 8100clean4: /* cfgtables, vaddr, intmode+region, pci */
8101 hpsa_free_cfgtables(h);
8102clean3: /* vaddr, intmode+region, pci */
8103 iounmap(h->vaddr);
105a3dbc 8104 h->vaddr = NULL;
195f2c65
RE		 8105clean2: /* intmode+region, pci */
8106 hpsa_disable_interrupt_mode(h);
943a7021
RE		 8107 /*
8108 * call pci_disable_device before pci_release_regions per
8109 * Documentation/PCI/pci.txt
8110 */
195f2c65 8111 pci_disable_device(h->pdev);
943a7021 8112 pci_release_regions(h->pdev);
edd16368
SC		 8113 return err;
8114}
8115
6f039790 8116static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 8117{
8118 int rc;
8119
8120#define HBA_INQUIRY_BYTE_COUNT 64
8121 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
8122 if (!h->hba_inquiry_data)
8123 return;
8124 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
8125 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
8126 if (rc != 0) {
8127 kfree(h->hba_inquiry_data);
8128 h->hba_inquiry_data = NULL;
8129 }
8130}
8131
6b6c1cd7 8132static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 8133{
1df8552a 8134 int rc, i;
3b747298 8135 void __iomem *vaddr;
4c2a8c40
SC		 8136
8137 if (!reset_devices)
8138 return 0;
8139
132aa220
TH		 8140 /* kdump kernel is loading, we don't know in which state is
8141 * the pci interface. The dev->enable_cnt is equal zero
8142 * so we call enable+disable, wait a while and switch it on.
8143 */
8144 rc = pci_enable_device(pdev);
8145 if (rc) {
8146 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
8147 return -ENODEV;
8148 }
8149 pci_disable_device(pdev);
8150 msleep(260); /* a randomly chosen number */
8151 rc = pci_enable_device(pdev);
8152 if (rc) {
8153 dev_warn(&pdev->dev, "failed to enable device.\n");
8154 return -ENODEV;
8155 }
4fa604e1 8156
859c75ab 8157 pci_set_master(pdev);
4fa604e1 8158
3b747298
TH		 8159 vaddr = pci_ioremap_bar(pdev, 0);
8160 if (vaddr == NULL) {
8161 rc = -ENOMEM;
8162 goto out_disable;
8163 }
8164 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8165 iounmap(vaddr);
8166
1df8552a 8167 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 8168 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 8169
1df8552a
SC		 8170 /* -ENOTSUPP here means we cannot reset the controller
8171 * but it's already (and still) up and running in
18867659
SC		 8172 * "performant mode". Or, it might be 640x, which can't reset
8173 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 8174 */
adf1b3a3 8175 if (rc)
132aa220 8176 goto out_disable;
4c2a8c40
SC		 8177
8178 /* Now try to get the controller to respond to a no-op */
1ba66c9c 8179 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 8180 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
8181 if (hpsa_noop(pdev) == 0)
8182 break;
8183 else
8184 dev_warn(&pdev->dev, "no-op failed%s\n",
8185 (i < 11 ? "; re-trying" : ""));
8186 }
132aa220
TH		 8187
8188out_disable:
8189
8190 pci_disable_device(pdev);
8191 return rc;
4c2a8c40
SC		 8192}
8193
1fb7c98a
RE		 8194static void hpsa_free_cmd_pool(struct ctlr_info *h)
8195{
8196 kfree(h->cmd_pool_bits);
105a3dbc
RE		 8197 h->cmd_pool_bits = NULL;
8198 if (h->cmd_pool) {
1fb7c98a
RE		 8199 pci_free_consistent(h->pdev,
8200 h->nr_cmds * sizeof(struct CommandList),
8201 h->cmd_pool,
8202 h->cmd_pool_dhandle);
105a3dbc
RE		 8203 h->cmd_pool = NULL;
8204 h->cmd_pool_dhandle = 0;
8205 }
8206 if (h->errinfo_pool) {
1fb7c98a
RE		 8207 pci_free_consistent(h->pdev,
8208 h->nr_cmds * sizeof(struct ErrorInfo),
8209 h->errinfo_pool,
8210 h->errinfo_pool_dhandle);
105a3dbc
RE		 8211 h->errinfo_pool = NULL;
8212 h->errinfo_pool_dhandle = 0;
8213 }
1fb7c98a
RE		 8214}
8215
d37ffbe4 8216static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 8217{
8218 h->cmd_pool_bits = kzalloc(
8219 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
8220 sizeof(unsigned long), GFP_KERNEL);
8221 h->cmd_pool = pci_alloc_consistent(h->pdev,
8222 h->nr_cmds * sizeof(*h->cmd_pool),
8223 &(h->cmd_pool_dhandle));
8224 h->errinfo_pool = pci_alloc_consistent(h->pdev,
8225 h->nr_cmds * sizeof(*h->errinfo_pool),
8226 &(h->errinfo_pool_dhandle));
8227 if ((h->cmd_pool_bits == NULL)
8228 || (h->cmd_pool == NULL)
8229 || (h->errinfo_pool == NULL)) {
8230 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 8231 goto clean_up;
2e9d1b36 8232 }
360c73bd 8233 hpsa_preinitialize_commands(h);
2e9d1b36 8234 return 0;
2c143342
RE		 8235clean_up:
8236 hpsa_free_cmd_pool(h);
8237 return -ENOMEM;
2e9d1b36
SC		 8238}
8239
41b3cf08
SC		 8240static void hpsa_irq_affinity_hints(struct ctlr_info *h)
8241{
ec429952 8242 int i, cpu;
41b3cf08
SC		 8243
8244 cpu = cpumask_first(cpu_online_mask);
8245 for (i = 0; i < h->msix_vector; i++) {
ec429952 8246 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 8247 cpu = cpumask_next(cpu, cpu_online_mask);
8248 }
8249}
8250
ec501a18
RE		 8251/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
8252static void hpsa_free_irqs(struct ctlr_info *h)
8253{
8254 int i;
8255
8256 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
8257 /* Single reply queue, only one irq to free */
8258 i = h->intr_mode;
8259 irq_set_affinity_hint(h->intr[i], NULL);
8260 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8261 h->q[i] = 0;
ec501a18
RE		 8262 return;
8263 }
8264
8265 for (i = 0; i < h->msix_vector; i++) {
8266 irq_set_affinity_hint(h->intr[i], NULL);
8267 free_irq(h->intr[i], &h->q[i]);
105a3dbc 8268 h->q[i] = 0;
ec501a18 8269 }
a4e17fc1
RE		 8270 for (; i < MAX_REPLY_QUEUES; i++)
8271 h->q[i] = 0;
ec501a18
RE		 8272}
8273
9ee61794
RE		 8274/* returns 0 on success; cleans up and returns -Enn on error */
8275static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 8276 irqreturn_t (*msixhandler)(int, void *),
8277 irqreturn_t (*intxhandler)(int, void *))
8278{
254f796b 8279 int rc, i;
0ae01a32 8280
254f796b
MG		 8281 /*
8282 * initialize h->q[x] = x so that interrupt handlers know which
8283 * queue to process.
8284 */
8285 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8286 h->q[i] = (u8) i;
8287
eee0f03a 8288 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 8289 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 8290 for (i = 0; i < h->msix_vector; i++) {
8b47004a 8291 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 8292 rc = request_irq(h->intr[i], msixhandler,
8b47004a 8293 0, h->intrname[i],
254f796b 8294 &h->q[i]);
a4e17fc1
RE		 8295 if (rc) {
8296 int j;
8297
8298 dev_err(&h->pdev->dev,
8299 "failed to get irq %d for %s\n",
8300 h->intr[i], h->devname);
8301 for (j = 0; j < i; j++) {
8302 free_irq(h->intr[j], &h->q[j]);
8303 h->q[j] = 0;
8304 }
8305 for (; j < MAX_REPLY_QUEUES; j++)
8306 h->q[j] = 0;
8307 return rc;
8308 }
8309 }
41b3cf08 8310 hpsa_irq_affinity_hints(h);
254f796b
MG		 8311 } else {
8312 /* Use single reply pool */
eee0f03a 8313 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 8314 if (h->msix_vector)
8315 sprintf(h->intrname[h->intr_mode],
8316 "%s-msix", h->devname);
8317 else
8318 sprintf(h->intrname[h->intr_mode],
8319 "%s-msi", h->devname);
254f796b 8320 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8321 msixhandler, 0,
8322 h->intrname[h->intr_mode],
254f796b
MG		 8323 &h->q[h->intr_mode]);
8324 } else {
8b47004a
RE		 8325 sprintf(h->intrname[h->intr_mode],
8326 "%s-intx", h->devname);
254f796b 8327 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 8328 intxhandler, IRQF_SHARED,
8329 h->intrname[h->intr_mode],
254f796b
MG		 8330 &h->q[h->intr_mode]);
8331 }
105a3dbc 8332 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 8333 }
0ae01a32 8334 if (rc) {
195f2c65 8335 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 8336 h->intr[h->intr_mode], h->devname);
195f2c65 8337 hpsa_free_irqs(h);
0ae01a32
SC		 8338 return -ENODEV;
8339 }
8340 return 0;
8341}
8342
6f039790 8343static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8344{
39c53f55 8345 int rc;
bf43caf3 8346 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8347
8348 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8349 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8350 if (rc) {
64670ac8 8351 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8352 return rc;
64670ac8
SC		 8353 }
8354
8355 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8356 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8357 if (rc) {
64670ac8
SC		 8358 dev_warn(&h->pdev->dev, "Board failed to become ready "
8359 "after soft reset.\n");
39c53f55 8360 return rc;
64670ac8
SC		 8361 }
8362
8363 return 0;
8364}
8365
072b0518
SC		 8366static void hpsa_free_reply_queues(struct ctlr_info *h)
8367{
8368 int i;
8369
8370 for (i = 0; i < h->nreply_queues; i++) {
8371 if (!h->reply_queue[i].head)
8372 continue;
1fb7c98a
RE		 8373 pci_free_consistent(h->pdev,
8374 h->reply_queue_size,
8375 h->reply_queue[i].head,
8376 h->reply_queue[i].busaddr);
072b0518
SC		 8377 h->reply_queue[i].head = NULL;
8378 h->reply_queue[i].busaddr = 0;
8379 }
105a3dbc 8380 h->reply_queue_size = 0;
072b0518
SC		 8381}
8382
0097f0f4
SC		 8383static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8384{
105a3dbc
RE		 8385 hpsa_free_performant_mode(h); /* init_one 7 */
8386 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8387 hpsa_free_cmd_pool(h); /* init_one 5 */
8388 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8389 scsi_host_put(h->scsi_host); /* init_one 3 */
8390 h->scsi_host = NULL; /* init_one 3 */
8391 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8392 free_percpu(h->lockup_detected); /* init_one 2 */
8393 h->lockup_detected = NULL; /* init_one 2 */
8394 if (h->resubmit_wq) {
8395 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8396 h->resubmit_wq = NULL;
8397 }
8398 if (h->rescan_ctlr_wq) {
8399 destroy_workqueue(h->rescan_ctlr_wq);
8400 h->rescan_ctlr_wq = NULL;
8401 }
105a3dbc 8402 kfree(h); /* init_one 1 */
64670ac8
SC		 8403}
8404
a0c12413 8405/* Called when controller lockup detected. */
f2405db8 8406static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8407{
281a7fd0
WS		 8408 int i, refcount;
8409 struct CommandList *c;
25163bd5 8410 int failcount = 0;
a0c12413 8411
080ef1cc 8412 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8413 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8414 c = h->cmd_pool + i;
281a7fd0
WS		 8415 refcount = atomic_inc_return(&c->refcount);
8416 if (refcount > 1) {
25163bd5 8417 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8418 finish_cmd(c);
433b5f4d 8419 atomic_dec(&h->commands_outstanding);
25163bd5 8420 failcount++;
281a7fd0
WS		 8421 }
8422 cmd_free(h, c);
a0c12413 8423 }
25163bd5
WS		 8424 dev_warn(&h->pdev->dev,
8425 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8426}
8427
094963da
SC		 8428static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8429{
c8ed0010 8430 int cpu;
094963da 8431
c8ed0010 8432 for_each_online_cpu(cpu) {
094963da
SC		 8433 u32 *lockup_detected;
8434 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8435 *lockup_detected = value;
094963da
SC		 8436 }
8437 wmb(); /* be sure the per-cpu variables are out to memory */
8438}
8439
a0c12413
SC		 8440static void controller_lockup_detected(struct ctlr_info *h)
8441{
8442 unsigned long flags;
094963da 8443 u32 lockup_detected;
a0c12413 8444
a0c12413
SC		 8445 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8446 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8447 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8448 if (!lockup_detected) {
8449 /* no heartbeat, but controller gave us a zero. */
8450 dev_warn(&h->pdev->dev,
25163bd5
WS		 8451 "lockup detected after %d but scratchpad register is zero\n",
8452 h->heartbeat_sample_interval / HZ);
094963da
SC		 8453 lockup_detected = 0xffffffff;
8454 }
8455 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8456 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8457 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8458 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 8459 pci_disable_device(h->pdev);
f2405db8 8460 fail_all_outstanding_cmds(h);
a0c12413
SC		 8461}
8462
25163bd5 8463static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8464{
8465 u64 now;
8466 u32 heartbeat;
8467 unsigned long flags;
8468
a0c12413
SC		 8469 now = get_jiffies_64();
8470 /* If we've received an interrupt recently, we're ok. */
8471 if (time_after64(h->last_intr_timestamp +
e85c5974 8472 (h->heartbeat_sample_interval), now))
25163bd5 8473 return false;
a0c12413
SC		 8474
8475 /*
8476 * If we've already checked the heartbeat recently, we're ok.
8477 * This could happen if someone sends us a signal. We
8478 * otherwise don't care about signals in this thread.
8479 */
8480 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8481 (h->heartbeat_sample_interval), now))
25163bd5 8482 return false;
a0c12413
SC		 8483
8484 /* If heartbeat has not changed since we last looked, we're not ok. */
8485 spin_lock_irqsave(&h->lock, flags);
8486 heartbeat = readl(&h->cfgtable->HeartBeat);
8487 spin_unlock_irqrestore(&h->lock, flags);
8488 if (h->last_heartbeat == heartbeat) {
8489 controller_lockup_detected(h);
25163bd5 8490 return true;
a0c12413
SC		 8491 }
8492
8493 /* We're ok. */
8494 h->last_heartbeat = heartbeat;
8495 h->last_heartbeat_timestamp = now;
25163bd5 8496 return false;
a0c12413
SC		 8497}
8498
9846590e 8499static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 8500{
8501 int i;
8502 char *event_type;
8503
e4aa3e6a
SC		 8504 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8505 return;
8506
76438d08 8507 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8508 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8509 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8510 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8511 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8512
8513 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8514 event_type = "state change";
8515 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8516 event_type = "configuration change";
8517 /* Stop sending new RAID offload reqs via the IO accelerator */
8518 scsi_block_requests(h->scsi_host);
5323ed74 8519 for (i = 0; i < h->ndevices; i++) {
76438d08 8520 h->dev[i]->offload_enabled = 0;
5323ed74
DB		 8521 h->dev[i]->offload_to_be_enabled = 0;
8522 }
23100dd9 8523 hpsa_drain_accel_commands(h);
76438d08
SC		 8524 /* Set 'accelerator path config change' bit */
8525 dev_warn(&h->pdev->dev,
8526 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8527 h->events, event_type);
8528 writel(h->events, &(h->cfgtable->clear_event_notify));
8529 /* Set the "clear event notify field update" bit 6 */
8530 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8531 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8532 hpsa_wait_for_clear_event_notify_ack(h);
8533 scsi_unblock_requests(h->scsi_host);
8534 } else {
8535 /* Acknowledge controller notification events. */
8536 writel(h->events, &(h->cfgtable->clear_event_notify));
8537 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8538 hpsa_wait_for_clear_event_notify_ack(h);
8539#if 0
8540 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8541 hpsa_wait_for_mode_change_ack(h);
8542#endif
8543 }
9846590e 8544 return;
76438d08
SC		 8545}
8546
8547/* Check a register on the controller to see if there are configuration
8548 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8549 * we should rescan the controller for devices.
8550 * Also check flag for driver-initiated rescan.
76438d08 8551 */
9846590e 8552static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8553{
853633e8
DB		 8554 if (h->drv_req_rescan) {
8555 h->drv_req_rescan = 0;
8556 return 1;
8557 }
8558
76438d08 8559 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8560 return 0;
76438d08
SC		 8561
8562 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8563 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8564}
76438d08 8565
9846590e
SC		 8566/*
8567 * Check if any of the offline devices have become ready
8568 */
8569static int hpsa_offline_devices_ready(struct ctlr_info *h)
8570{
8571 unsigned long flags;
8572 struct offline_device_entry *d;
8573 struct list_head *this, *tmp;
8574
8575 spin_lock_irqsave(&h->offline_device_lock, flags);
8576 list_for_each_safe(this, tmp, &h->offline_device_list) {
8577 d = list_entry(this, struct offline_device_entry,
8578 offline_list);
8579 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8580 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8581 spin_lock_irqsave(&h->offline_device_lock, flags);
8582 list_del(&d->offline_list);
8583 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8584 return 1;
d1fea47c 8585 }
9846590e
SC		 8586 spin_lock_irqsave(&h->offline_device_lock, flags);
8587 }
8588 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8589 return 0;
76438d08
SC		 8590}
8591
34592254
ST		 8592static int hpsa_luns_changed(struct ctlr_info *h)
8593{
8594 int rc = 1; /* assume there are changes */
8595 struct ReportLUNdata *logdev = NULL;
8596
8597 /* if we can't find out if lun data has changed,
8598 * assume that it has.
8599 */
8600
8601 if (!h->lastlogicals)
8602 goto out;
8603
8604 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8605 if (!logdev) {
8606 dev_warn(&h->pdev->dev,
8607 "Out of memory, can't track lun changes.\n");
8608 goto out;
8609 }
8610 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8611 dev_warn(&h->pdev->dev,
8612 "report luns failed, can't track lun changes.\n");
8613 goto out;
8614 }
8615 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8616 dev_info(&h->pdev->dev,
8617 "Lun changes detected.\n");
8618 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8619 goto out;
8620 } else
8621 rc = 0; /* no changes detected. */
8622out:
8623 kfree(logdev);
8624 return rc;
8625}
8626
6636e7f4 8627static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8628{
8629 unsigned long flags;
8a98db73 8630 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8631 struct ctlr_info, rescan_ctlr_work);
8632
8633
8634 if (h->remove_in_progress)
8a98db73 8635 return;
9846590e
SC		 8636
8637 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8638 scsi_host_get(h->scsi_host);
9846590e
SC		 8639 hpsa_ack_ctlr_events(h);
8640 hpsa_scan_start(h->scsi_host);
8641 scsi_host_put(h->scsi_host);
34592254 8642 } else if (h->discovery_polling) {
c2adae44 8643 hpsa_disable_rld_caching(h);
34592254
ST		 8644 if (hpsa_luns_changed(h)) {
8645 struct Scsi_Host *sh = NULL;
8646
8647 dev_info(&h->pdev->dev,
8648 "driver discovery polling rescan.\n");
8649 sh = scsi_host_get(h->scsi_host);
8650 if (sh != NULL) {
8651 hpsa_scan_start(sh);
8652 scsi_host_put(sh);
8653 }
8654 }
9846590e 8655 }
8a98db73 8656 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8657 if (!h->remove_in_progress)
8658 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8659 h->heartbeat_sample_interval);
8660 spin_unlock_irqrestore(&h->lock, flags);
8661}
8662
8663static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8664{
8665 unsigned long flags;
8666 struct ctlr_info *h = container_of(to_delayed_work(work),
8667 struct ctlr_info, monitor_ctlr_work);
8668
8669 detect_controller_lockup(h);
8670 if (lockup_detected(h))
a0c12413 8671 return;
6636e7f4
DB		 8672
8673 spin_lock_irqsave(&h->lock, flags);
8674 if (!h->remove_in_progress)
8675 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8676 h->heartbeat_sample_interval);
8677 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8678}
8679
6636e7f4
DB		 8680static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8681 char *name)
8682{
8683 struct workqueue_struct *wq = NULL;
6636e7f4 8684
397ea9cb 8685 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8686 if (!wq)
8687 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8688
8689 return wq;
8690}
8691
6f039790 8692static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8693{
4c2a8c40 8694 int dac, rc;
edd16368 8695 struct ctlr_info *h;
64670ac8
SC		 8696 int try_soft_reset = 0;
8697 unsigned long flags;
6b6c1cd7 8698 u32 board_id;
edd16368
SC		 8699
8700 if (number_of_controllers == 0)
8701 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8702
6b6c1cd7
TH		 8703 rc = hpsa_lookup_board_id(pdev, &board_id);
8704 if (rc < 0) {
8705 dev_warn(&pdev->dev, "Board ID not found\n");
8706 return rc;
8707 }
8708
8709 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8710 if (rc) {
8711 if (rc != -ENOTSUPP)
8712 return rc;
8713 /* If the reset fails in a particular way (it has no way to do
8714 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8715 * a soft reset once we get the controller configured up to the
8716 * point that it can accept a command.
8717 */
8718 try_soft_reset = 1;
8719 rc = 0;
8720 }
8721
8722reinit_after_soft_reset:
edd16368 8723
303932fd
DB		 8724 /* Command structures must be aligned on a 32-byte boundary because
8725 * the 5 lower bits of the address are used by the hardware. and by
8726 * the driver. See comments in hpsa.h for more info.
8727 */
303932fd 8728 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8729 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8730 if (!h) {
8731 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8732 return -ENOMEM;
105a3dbc 8733 }
edd16368 8734
55c06c71 8735 h->pdev = pdev;
105a3dbc 8736
a9a3a273 8737 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8738 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8739 spin_lock_init(&h->lock);
9846590e 8740 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8741 spin_lock_init(&h->scan_lock);
34f0c627 8742 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8743 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8744
8745 /* Allocate and clear per-cpu variable lockup_detected */
8746 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8747 if (!h->lockup_detected) {
105a3dbc 8748 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8749 rc = -ENOMEM;
2efa5929 8750 goto clean1; /* aer/h */
2a5ac326 8751 }
094963da
SC		 8752 set_lockup_detected_for_all_cpus(h, 0);
8753
55c06c71 8754 rc = hpsa_pci_init(h);
105a3dbc 8755 if (rc)
2946e82b
RE		 8756 goto clean2; /* lu, aer/h */
8757
8758 /* relies on h-> settings made by hpsa_pci_init, including
8759 * interrupt_mode h->intr */
8760 rc = hpsa_scsi_host_alloc(h);
8761 if (rc)
8762 goto clean2_5; /* pci, lu, aer/h */
edd16368 8763
2946e82b 8764 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8765 h->ctlr = number_of_controllers;
8766 number_of_controllers++;
edd16368
SC		 8767
8768 /* configure PCI DMA stuff */
ecd9aad4
SC		 8769 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8770 if (rc == 0) {
edd16368 8771 dac = 1;
ecd9aad4
SC		 8772 } else {
8773 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8774 if (rc == 0) {
8775 dac = 0;
8776 } else {
8777 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8778 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8779 }
edd16368
SC		 8780 }
8781
8782 /* make sure the board interrupts are off */
8783 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8784
105a3dbc
RE		 8785 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8786 if (rc)
2946e82b 8787 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8788 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8789 if (rc)
2946e82b 8790 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8791 rc = hpsa_alloc_sg_chain_blocks(h);
8792 if (rc)
2946e82b 8793 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8794 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8795 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8796 init_waitqueue_head(&h->event_sync_wait_queue);
8797 mutex_init(&h->reset_mutex);
a08a8471 8798 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8799
8800 pci_set_drvdata(pdev, h);
9a41338e 8801 h->ndevices = 0;
2946e82b 8802
9a41338e 8803 spin_lock_init(&h->devlock);
105a3dbc
RE		 8804 rc = hpsa_put_ctlr_into_performant_mode(h);
8805 if (rc)
2946e82b
RE		 8806 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8807
2efa5929
RE		 8808 /* create the resubmit workqueue */
8809 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8810 if (!h->rescan_ctlr_wq) {
8811 rc = -ENOMEM;
8812 goto clean7;
8813 }
8814
8815 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8816 if (!h->resubmit_wq) {
8817 rc = -ENOMEM;
8818 goto clean7; /* aer/h */
8819 }
64670ac8 8820
105a3dbc
RE		 8821 /*
8822 * At this point, the controller is ready to take commands.
64670ac8
SC		 8823 * Now, if reset_devices and the hard reset didn't work, try
8824 * the soft reset and see if that works.
8825 */
8826 if (try_soft_reset) {
8827
8828 /* This is kind of gross. We may or may not get a completion
8829 * from the soft reset command, and if we do, then the value
8830 * from the fifo may or may not be valid. So, we wait 10 secs
8831 * after the reset throwing away any completions we get during
8832 * that time. Unregister the interrupt handler and register
8833 * fake ones to scoop up any residual completions.
8834 */
8835 spin_lock_irqsave(&h->lock, flags);
8836 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8837 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8838 hpsa_free_irqs(h);
9ee61794 8839 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8840 hpsa_intx_discard_completions);
8841 if (rc) {
9ee61794
RE		 8842 dev_warn(&h->pdev->dev,
8843 "Failed to request_irq after soft reset.\n");
d498757c 8844 /*
b2ef480c
RE		 8845 * cannot goto clean7 or free_irqs will be called
8846 * again. Instead, do its work
8847 */
8848 hpsa_free_performant_mode(h); /* clean7 */
8849 hpsa_free_sg_chain_blocks(h); /* clean6 */
8850 hpsa_free_cmd_pool(h); /* clean5 */
8851 /*
8852 * skip hpsa_free_irqs(h) clean4 since that
8853 * was just called before request_irqs failed
d498757c
RE		 8854 */
8855 goto clean3;
64670ac8
SC		 8856 }
8857
8858 rc = hpsa_kdump_soft_reset(h);
8859 if (rc)
8860 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8861 goto clean7;
64670ac8
SC		 8862
8863 dev_info(&h->pdev->dev, "Board READY.\n");
8864 dev_info(&h->pdev->dev,
8865 "Waiting for stale completions to drain.\n");
8866 h->access.set_intr_mask(h, HPSA_INTR_ON);
8867 msleep(10000);
8868 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8869
8870 rc = controller_reset_failed(h->cfgtable);
8871 if (rc)
8872 dev_info(&h->pdev->dev,
8873 "Soft reset appears to have failed.\n");
8874
8875 /* since the controller's reset, we have to go back and re-init
8876 * everything. Easiest to just forget what we've done and do it
8877 * all over again.
8878 */
8879 hpsa_undo_allocations_after_kdump_soft_reset(h);
8880 try_soft_reset = 0;
8881 if (rc)
b2ef480c 8882 /* don't goto clean, we already unallocated */
64670ac8
SC		 8883 return -ENODEV;
8884
8885 goto reinit_after_soft_reset;
8886 }
edd16368 8887
105a3dbc
RE		 8888 /* Enable Accelerated IO path at driver layer */
8889 h->acciopath_status = 1;
34592254
ST		 8890 /* Disable discovery polling.*/
8891 h->discovery_polling = 0;
da0697bd 8892
e863d68e 8893
edd16368
SC		 8894 /* Turn the interrupts on so we can service requests */
8895 h->access.set_intr_mask(h, HPSA_INTR_ON);
8896
339b2b14 8897 hpsa_hba_inquiry(h);
8a98db73 8898
34592254
ST		 8899 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8900 if (!h->lastlogicals)
8901 dev_info(&h->pdev->dev,
8902 "Can't track change to report lun data\n");
8903
cf477237
DB		 8904 /* hook into SCSI subsystem */
8905 rc = hpsa_scsi_add_host(h);
8906 if (rc)
8907 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8908
8a98db73
SC		 8909 /* Monitor the controller for firmware lockups */
8910 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8911 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8912 schedule_delayed_work(&h->monitor_ctlr_work,
8913 h->heartbeat_sample_interval);
6636e7f4
DB		 8914 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8915 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8916 h->heartbeat_sample_interval);
88bf6d62 8917 return 0;
edd16368 8918
2946e82b 8919clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8920 hpsa_free_performant_mode(h);
8921 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8922clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8923 hpsa_free_sg_chain_blocks(h);
2946e82b 8924clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8925 hpsa_free_cmd_pool(h);
2946e82b 8926clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8927 hpsa_free_irqs(h);
2946e82b
RE		 8928clean3: /* shost, pci, lu, aer/h */
8929 scsi_host_put(h->scsi_host);
8930 h->scsi_host = NULL;
8931clean2_5: /* pci, lu, aer/h */
195f2c65 8932 hpsa_free_pci_init(h);
2946e82b 8933clean2: /* lu, aer/h */
105a3dbc
RE		 8934 if (h->lockup_detected) {
8935 free_percpu(h->lockup_detected);
8936 h->lockup_detected = NULL;
8937 }
8938clean1: /* wq/aer/h */
8939 if (h->resubmit_wq) {
080ef1cc 8940 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8941 h->resubmit_wq = NULL;
8942 }
8943 if (h->rescan_ctlr_wq) {
6636e7f4 8944 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8945 h->rescan_ctlr_wq = NULL;
8946 }
edd16368 8947 kfree(h);
ecd9aad4 8948 return rc;
edd16368
SC		 8949}
8950
8951static void hpsa_flush_cache(struct ctlr_info *h)
8952{
8953 char *flush_buf;
8954 struct CommandList *c;
25163bd5 8955 int rc;
702890e3 8956
094963da 8957 if (unlikely(lockup_detected(h)))
702890e3 8958 return;
edd16368
SC		 8959 flush_buf = kzalloc(4, GFP_KERNEL);
8960 if (!flush_buf)
8961 return;
8962
45fcb86e 8963 c = cmd_alloc(h);
bf43caf3 8964
a2dac136
SC		 8965 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8966 RAID_CTLR_LUNID, TYPE_CMD)) {
8967 goto out;
8968 }
25163bd5 8969 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 8970 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
25163bd5
WS		 8971 if (rc)
8972 goto out;
edd16368 8973 if (c->err_info->CommandStatus != 0)
a2dac136 8974out:
edd16368
SC		 8975 dev_warn(&h->pdev->dev,
8976 "error flushing cache on controller\n");
45fcb86e 8977 cmd_free(h, c);
edd16368
SC		 8978 kfree(flush_buf);
8979}
8980
c2adae44
ST		 8981/* Make controller gather fresh report lun data each time we
8982 * send down a report luns request
8983 */
8984static void hpsa_disable_rld_caching(struct ctlr_info *h)
8985{
8986 u32 *options;
8987 struct CommandList *c;
8988 int rc;
8989
8990 /* Don't bother trying to set diag options if locked up */
8991 if (unlikely(h->lockup_detected))
8992 return;
8993
8994 options = kzalloc(sizeof(*options), GFP_KERNEL);
8995 if (!options) {
8996 dev_err(&h->pdev->dev,
8997 "Error: failed to disable rld caching, during alloc.\n");
8998 return;
8999 }
9000
9001 c = cmd_alloc(h);
9002
9003 /* first, get the current diag options settings */
9004 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
9005 RAID_CTLR_LUNID, TYPE_CMD))
9006 goto errout;
9007
9008 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 9009 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 9010 if ((rc != 0) || (c->err_info->CommandStatus != 0))
9011 goto errout;
9012
9013 /* Now, set the bit for disabling the RLD caching */
9014 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
9015
9016 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
9017 RAID_CTLR_LUNID, TYPE_CMD))
9018 goto errout;
9019
9020 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 9021 PCI_DMA_TODEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 9022 if ((rc != 0) || (c->err_info->CommandStatus != 0))
9023 goto errout;
9024
9025 /* Now verify that it got set: */
9026 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
9027 RAID_CTLR_LUNID, TYPE_CMD))
9028 goto errout;
9029
9030 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
c448ecfa 9031 PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT);
c2adae44
ST		 9032 if ((rc != 0) || (c->err_info->CommandStatus != 0))
9033 goto errout;
9034
d8a080c3 9035 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 9036 goto out;
9037
9038errout:
9039 dev_err(&h->pdev->dev,
9040 "Error: failed to disable report lun data caching.\n");
9041out:
9042 cmd_free(h, c);
9043 kfree(options);
9044}
9045
edd16368
SC		 9046static void hpsa_shutdown(struct pci_dev *pdev)
9047{
9048 struct ctlr_info *h;
9049
9050 h = pci_get_drvdata(pdev);
9051 /* Turn board interrupts off and send the flush cache command
9052 * sendcmd will turn off interrupt, and send the flush...
9053 * To write all data in the battery backed cache to disks
9054 */
9055 hpsa_flush_cache(h);
9056 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 9057 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 9058 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 9059}
9060
6f039790 9061static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 9062{
9063 int i;
9064
105a3dbc 9065 for (i = 0; i < h->ndevices; i++) {
55e14e76 9066 kfree(h->dev[i]);
105a3dbc
RE		 9067 h->dev[i] = NULL;
9068 }
55e14e76
SC		 9069}
9070
6f039790 9071static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 9072{
9073 struct ctlr_info *h;
8a98db73 9074 unsigned long flags;
edd16368
SC		 9075
9076 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 9077 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 9078 return;
9079 }
9080 h = pci_get_drvdata(pdev);
8a98db73
SC		 9081
9082 /* Get rid of any controller monitoring work items */
9083 spin_lock_irqsave(&h->lock, flags);
9084 h->remove_in_progress = 1;
8a98db73 9085 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 9086 cancel_delayed_work_sync(&h->monitor_ctlr_work);
9087 cancel_delayed_work_sync(&h->rescan_ctlr_work);
9088 destroy_workqueue(h->rescan_ctlr_wq);
9089 destroy_workqueue(h->resubmit_wq);
cc64c817 9090
2d041306
DB		 9091 /*
9092 * Call before disabling interrupts.
9093 * scsi_remove_host can trigger I/O operations especially
9094 * when multipath is enabled. There can be SYNCHRONIZE CACHE
9095 * operations which cannot complete and will hang the system.
9096 */
9097 if (h->scsi_host)
9098 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 9099 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 9100 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 9101 hpsa_shutdown(pdev);
cc64c817 9102
105a3dbc
RE		 9103 hpsa_free_device_info(h); /* scan */
9104
2946e82b
RE		 9105 kfree(h->hba_inquiry_data); /* init_one 10 */
9106 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 9107 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 9108 hpsa_free_performant_mode(h); /* init_one 7 */
9109 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
9110 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 9111 kfree(h->lastlogicals);
105a3dbc
RE		 9112
9113 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 9114
2946e82b
RE		 9115 scsi_host_put(h->scsi_host); /* init_one 3 */
9116 h->scsi_host = NULL; /* init_one 3 */
9117
195f2c65 9118 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 9119 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 9120
105a3dbc
RE		 9121 free_percpu(h->lockup_detected); /* init_one 2 */
9122 h->lockup_detected = NULL; /* init_one 2 */
9123 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9
KB		 9124
9125 hpsa_delete_sas_host(h);
9126
105a3dbc 9127 kfree(h); /* init_one 1 */
edd16368
SC		 9128}
9129
9130static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
9131 __attribute__((unused)) pm_message_t state)
9132{
9133 return -ENOSYS;
9134}
9135
9136static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
9137{
9138 return -ENOSYS;
9139}
9140
9141static struct pci_driver hpsa_pci_driver = {
f79cfec6 9142 .name = HPSA,
edd16368 9143 .probe = hpsa_init_one,
6f039790 9144 .remove = hpsa_remove_one,
edd16368
SC		 9145 .id_table = hpsa_pci_device_id, /* id_table */
9146 .shutdown = hpsa_shutdown,
9147 .suspend = hpsa_suspend,
9148 .resume = hpsa_resume,
9149};
9150
303932fd
DB		 9151/* Fill in bucket_map[], given nsgs (the max number of
9152 * scatter gather elements supported) and bucket[],
9153 * which is an array of 8 integers. The bucket[] array
9154 * contains 8 different DMA transfer sizes (in 16
9155 * byte increments) which the controller uses to fetch
9156 * commands. This function fills in bucket_map[], which
9157 * maps a given number of scatter gather elements to one of
9158 * the 8 DMA transfer sizes. The point of it is to allow the
9159 * controller to only do as much DMA as needed to fetch the
9160 * command, with the DMA transfer size encoded in the lower
9161 * bits of the command address.
9162 */
9163static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 9164 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 9165{
9166 int i, j, b, size;
9167
303932fd
DB		 9168 /* Note, bucket_map must have nsgs+1 entries. */
9169 for (i = 0; i <= nsgs; i++) {
9170 /* Compute size of a command with i SG entries */
e1f7de0c 9171 size = i + min_blocks;
303932fd
DB		 9172 b = num_buckets; /* Assume the biggest bucket */
9173 /* Find the bucket that is just big enough */
e1f7de0c 9174 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 9175 if (bucket[j] >= size) {
9176 b = j;
9177 break;
9178 }
9179 }
9180 /* for a command with i SG entries, use bucket b. */
9181 bucket_map[i] = b;
9182 }
9183}
9184
105a3dbc
RE		 9185/*
9186 * return -ENODEV on err, 0 on success (or no action)
9187 * allocates numerous items that must be freed later
9188 */
c706a795 9189static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 9190{
6c311b57
SC		 9191 int i;
9192 unsigned long register_value;
e1f7de0c
MG		 9193 unsigned long transMethod = CFGTBL_Trans_Performant |
9194 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 9195 CFGTBL_Trans_enable_directed_msix |
9196 (trans_support & (CFGTBL_Trans_io_accel1 |
9197 CFGTBL_Trans_io_accel2));
e1f7de0c 9198 struct access_method access = SA5_performant_access;
def342bd
SC		 9199
9200 /* This is a bit complicated. There are 8 registers on
9201 * the controller which we write to to tell it 8 different
9202 * sizes of commands which there may be. It's a way of
9203 * reducing the DMA done to fetch each command. Encoded into
9204 * each command's tag are 3 bits which communicate to the controller
9205 * which of the eight sizes that command fits within. The size of
9206 * each command depends on how many scatter gather entries there are.
9207 * Each SG entry requires 16 bytes. The eight registers are programmed
9208 * with the number of 16-byte blocks a command of that size requires.
9209 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 9210 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 9211 * blocks. Note, this only extends to the SG entries contained
9212 * within the command block, and does not extend to chained blocks
9213 * of SG elements. bft[] contains the eight values we write to
9214 * the registers. They are not evenly distributed, but have more
9215 * sizes for small commands, and fewer sizes for larger commands.
9216 */
d66ae08b 9217 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 9218#define MIN_IOACCEL2_BFT_ENTRY 5
9219#define HPSA_IOACCEL2_HEADER_SZ 4
9220 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
9221 13, 14, 15, 16, 17, 18, 19,
9222 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
9223 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
9224 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
9225 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
9226 16 * MIN_IOACCEL2_BFT_ENTRY);
9227 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 9228 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 9229 /* 5 = 1 s/g entry or 4k
9230 * 6 = 2 s/g entry or 8k
9231 * 8 = 4 s/g entry or 16k
9232 * 10 = 6 s/g entry or 24k
9233 */
303932fd 9234
b3a52e79
SC		 9235 /* If the controller supports either ioaccel method then
9236 * we can also use the RAID stack submit path that does not
9237 * perform the superfluous readl() after each command submission.
9238 */
9239 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
9240 access = SA5_performant_access_no_read;
9241
303932fd 9242 /* Controller spec: zero out this buffer. */
072b0518
SC		 9243 for (i = 0; i < h->nreply_queues; i++)
9244 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 9245
d66ae08b
SC		 9246 bft[7] = SG_ENTRIES_IN_CMD + 4;
9247 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 9248 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 9249 for (i = 0; i < 8; i++)
9250 writel(bft[i], &h->transtable->BlockFetch[i]);
9251
9252 /* size of controller ring buffer */
9253 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 9254 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 9255 writel(0, &h->transtable->RepQCtrAddrLow32);
9256 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9257
9258 for (i = 0; i < h->nreply_queues; i++) {
9259 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9260 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9261 &h->transtable->RepQAddr[i].lower);
9262 }
9263
b9af4937 9264 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9265 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9266 /*
9267 * enable outbound interrupt coalescing in accelerator mode;
9268 */
9269 if (trans_support & CFGTBL_Trans_io_accel1) {
9270 access = SA5_ioaccel_mode1_access;
9271 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9272 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 9273 } else {
9274 if (trans_support & CFGTBL_Trans_io_accel2) {
9275 access = SA5_ioaccel_mode2_access;
9276 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9277 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
9278 }
e1f7de0c 9279 }
303932fd 9280 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9281 if (hpsa_wait_for_mode_change_ack(h)) {
9282 dev_err(&h->pdev->dev,
9283 "performant mode problem - doorbell timeout\n");
9284 return -ENODEV;
9285 }
303932fd
DB		 9286 register_value = readl(&(h->cfgtable->TransportActive));
9287 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9288 dev_err(&h->pdev->dev,
9289 "performant mode problem - transport not active\n");
c706a795 9290 return -ENODEV;
303932fd 9291 }
960a30e7 9292 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9293 h->access = access;
9294 h->transMethod = transMethod;
9295
b9af4937
SC		 9296 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9297 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9298 return 0;
e1f7de0c 9299
b9af4937
SC		 9300 if (trans_support & CFGTBL_Trans_io_accel1) {
9301 /* Set up I/O accelerator mode */
9302 for (i = 0; i < h->nreply_queues; i++) {
9303 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9304 h->reply_queue[i].current_entry =
9305 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9306 }
9307 bft[7] = h->ioaccel_maxsg + 8;
9308 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9309 h->ioaccel1_blockFetchTable);
e1f7de0c 9310
b9af4937 9311 /* initialize all reply queue entries to unused */
072b0518
SC		 9312 for (i = 0; i < h->nreply_queues; i++)
9313 memset(h->reply_queue[i].head,
9314 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9315 h->reply_queue_size);
e1f7de0c 9316
b9af4937
SC		 9317 /* set all the constant fields in the accelerator command
9318 * frames once at init time to save CPU cycles later.
9319 */
9320 for (i = 0; i < h->nr_cmds; i++) {
9321 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9322
9323 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9324 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9325 (i * sizeof(struct ErrorInfo)));
9326 cp->err_info_len = sizeof(struct ErrorInfo);
9327 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9328 cp->host_context_flags =
9329 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9330 cp->timeout_sec = 0;
9331 cp->ReplyQueue = 0;
50a0decf 9332 cp->tag =
f2405db8 9333 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9334 cp->host_addr =
9335 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9336 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9337 }
9338 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9339 u64 cfg_offset, cfg_base_addr_index;
9340 u32 bft2_offset, cfg_base_addr;
9341 int rc;
9342
9343 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9344 &cfg_base_addr_index, &cfg_offset);
9345 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9346 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9347 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9348 4, h->ioaccel2_blockFetchTable);
9349 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9350 BUILD_BUG_ON(offsetof(struct CfgTable,
9351 io_accel_request_size_offset) != 0xb8);
9352 h->ioaccel2_bft2_regs =
9353 remap_pci_mem(pci_resource_start(h->pdev,
9354 cfg_base_addr_index) +
9355 cfg_offset + bft2_offset,
9356 ARRAY_SIZE(bft2) *
9357 sizeof(*h->ioaccel2_bft2_regs));
9358 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9359 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9360 }
b9af4937 9361 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9362 if (hpsa_wait_for_mode_change_ack(h)) {
9363 dev_err(&h->pdev->dev,
9364 "performant mode problem - enabling ioaccel mode\n");
9365 return -ENODEV;
9366 }
9367 return 0;
e1f7de0c
MG		 9368}
9369
1fb7c98a
RE		 9370/* Free ioaccel1 mode command blocks and block fetch table */
9371static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9372{
105a3dbc 9373 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9374 pci_free_consistent(h->pdev,
9375 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9376 h->ioaccel_cmd_pool,
9377 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9378 h->ioaccel_cmd_pool = NULL;
9379 h->ioaccel_cmd_pool_dhandle = 0;
9380 }
1fb7c98a 9381 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9382 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9383}
9384
d37ffbe4
RE		 9385/* Allocate ioaccel1 mode command blocks and block fetch table */
9386static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9387{
283b4a9b
SC		 9388 h->ioaccel_maxsg =
9389 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9390 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9391 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9392
e1f7de0c
MG		 9393 /* Command structures must be aligned on a 128-byte boundary
9394 * because the 7 lower bits of the address are used by the
9395 * hardware.
9396 */
e1f7de0c
MG		 9397 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9398 IOACCEL1_COMMANDLIST_ALIGNMENT);
9399 h->ioaccel_cmd_pool =
9400 pci_alloc_consistent(h->pdev,
9401 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9402 &(h->ioaccel_cmd_pool_dhandle));
9403
9404 h->ioaccel1_blockFetchTable =
283b4a9b 9405 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9406 sizeof(u32)), GFP_KERNEL);
9407
9408 if ((h->ioaccel_cmd_pool == NULL) ||
9409 (h->ioaccel1_blockFetchTable == NULL))
9410 goto clean_up;
9411
9412 memset(h->ioaccel_cmd_pool, 0,
9413 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9414 return 0;
9415
9416clean_up:
1fb7c98a 9417 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9418 return -ENOMEM;
6c311b57
SC		 9419}
9420
1fb7c98a
RE		 9421/* Free ioaccel2 mode command blocks and block fetch table */
9422static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9423{
d9a729f3
WS		 9424 hpsa_free_ioaccel2_sg_chain_blocks(h);
9425
105a3dbc 9426 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9427 pci_free_consistent(h->pdev,
9428 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9429 h->ioaccel2_cmd_pool,
9430 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9431 h->ioaccel2_cmd_pool = NULL;
9432 h->ioaccel2_cmd_pool_dhandle = 0;
9433 }
1fb7c98a 9434 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9435 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9436}
9437
d37ffbe4
RE		 9438/* Allocate ioaccel2 mode command blocks and block fetch table */
9439static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9440{
d9a729f3
WS		 9441 int rc;
9442
aca9012a
SC		 9443 /* Allocate ioaccel2 mode command blocks and block fetch table */
9444
9445 h->ioaccel_maxsg =
9446 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9447 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9448 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9449
aca9012a
SC		 9450 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9451 IOACCEL2_COMMANDLIST_ALIGNMENT);
9452 h->ioaccel2_cmd_pool =
9453 pci_alloc_consistent(h->pdev,
9454 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9455 &(h->ioaccel2_cmd_pool_dhandle));
9456
9457 h->ioaccel2_blockFetchTable =
9458 kmalloc(((h->ioaccel_maxsg + 1) *
9459 sizeof(u32)), GFP_KERNEL);
9460
9461 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9462 (h->ioaccel2_blockFetchTable == NULL)) {
9463 rc = -ENOMEM;
9464 goto clean_up;
9465 }
9466
9467 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9468 if (rc)
aca9012a
SC		 9469 goto clean_up;
9470
9471 memset(h->ioaccel2_cmd_pool, 0,
9472 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9473 return 0;
9474
9475clean_up:
1fb7c98a 9476 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9477 return rc;
aca9012a
SC		 9478}
9479
105a3dbc
RE		 9480/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9481static void hpsa_free_performant_mode(struct ctlr_info *h)
9482{
9483 kfree(h->blockFetchTable);
9484 h->blockFetchTable = NULL;
9485 hpsa_free_reply_queues(h);
9486 hpsa_free_ioaccel1_cmd_and_bft(h);
9487 hpsa_free_ioaccel2_cmd_and_bft(h);
9488}
9489
9490/* return -ENODEV on error, 0 on success (or no action)
9491 * allocates numerous items that must be freed later
9492 */
9493static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9494{
9495 u32 trans_support;
e1f7de0c
MG		 9496 unsigned long transMethod = CFGTBL_Trans_Performant |
9497 CFGTBL_Trans_use_short_tags;
105a3dbc 9498 int i, rc;
6c311b57 9499
02ec19c8 9500 if (hpsa_simple_mode)
105a3dbc 9501 return 0;
02ec19c8 9502
67c99a72 9503 trans_support = readl(&(h->cfgtable->TransportSupport));
9504 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9505 return 0;
67c99a72 9506
e1f7de0c
MG		 9507 /* Check for I/O accelerator mode support */
9508 if (trans_support & CFGTBL_Trans_io_accel1) {
9509 transMethod |= CFGTBL_Trans_io_accel1 |
9510 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9511 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9512 if (rc)
9513 return rc;
9514 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9515 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9516 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9517 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9518 if (rc)
9519 return rc;
e1f7de0c
MG		 9520 }
9521
eee0f03a 9522 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 9523 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9524 /* Performant mode ring buffer and supporting data structures */
072b0518 9525 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9526
254f796b 9527 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 9528 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
9529 h->reply_queue_size,
9530 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 9531 if (!h->reply_queue[i].head) {
9532 rc = -ENOMEM;
9533 goto clean1; /* rq, ioaccel */
9534 }
254f796b
MG		 9535 h->reply_queue[i].size = h->max_commands;
9536 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9537 h->reply_queue[i].current_entry = 0;
9538 }
9539
6c311b57 9540 /* Need a block fetch table for performant mode */
d66ae08b 9541 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9542 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9543 if (!h->blockFetchTable) {
9544 rc = -ENOMEM;
9545 goto clean1; /* rq, ioaccel */
9546 }
6c311b57 9547
105a3dbc
RE		 9548 rc = hpsa_enter_performant_mode(h, trans_support);
9549 if (rc)
9550 goto clean2; /* bft, rq, ioaccel */
9551 return 0;
303932fd 9552
105a3dbc 9553clean2: /* bft, rq, ioaccel */
303932fd 9554 kfree(h->blockFetchTable);
105a3dbc
RE		 9555 h->blockFetchTable = NULL;
9556clean1: /* rq, ioaccel */
9557 hpsa_free_reply_queues(h);
9558 hpsa_free_ioaccel1_cmd_and_bft(h);
9559 hpsa_free_ioaccel2_cmd_and_bft(h);
9560 return rc;
303932fd
DB		 9561}
9562
23100dd9 9563static int is_accelerated_cmd(struct CommandList *c)
76438d08 9564{
23100dd9
SC		 9565 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9566}
9567
9568static void hpsa_drain_accel_commands(struct ctlr_info *h)
9569{
9570 struct CommandList *c = NULL;
f2405db8 9571 int i, accel_cmds_out;
281a7fd0 9572 int refcount;
76438d08 9573
f2405db8 9574 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9575 accel_cmds_out = 0;
f2405db8 9576 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9577 c = h->cmd_pool + i;
281a7fd0
WS		 9578 refcount = atomic_inc_return(&c->refcount);
9579 if (refcount > 1) /* Command is allocated */
9580 accel_cmds_out += is_accelerated_cmd(c);
9581 cmd_free(h, c);
f2405db8 9582 }
23100dd9 9583 if (accel_cmds_out <= 0)
281a7fd0 9584 break;
76438d08
SC		 9585 msleep(100);
9586 } while (1);
9587}
9588
d04e62b9
KB		 9589static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9590 struct hpsa_sas_port *hpsa_sas_port)
9591{
9592 struct hpsa_sas_phy *hpsa_sas_phy;
9593 struct sas_phy *phy;
9594
9595 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9596 if (!hpsa_sas_phy)
9597 return NULL;
9598
9599 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9600 hpsa_sas_port->next_phy_index);
9601 if (!phy) {
9602 kfree(hpsa_sas_phy);
9603 return NULL;
9604 }
9605
9606 hpsa_sas_port->next_phy_index++;
9607 hpsa_sas_phy->phy = phy;
9608 hpsa_sas_phy->parent_port = hpsa_sas_port;
9609
9610 return hpsa_sas_phy;
9611}
9612
9613static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9614{
9615 struct sas_phy *phy = hpsa_sas_phy->phy;
9616
9617 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
9618 sas_phy_free(phy);
9619 if (hpsa_sas_phy->added_to_port)
9620 list_del(&hpsa_sas_phy->phy_list_entry);
9621 kfree(hpsa_sas_phy);
9622}
9623
9624static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9625{
9626 int rc;
9627 struct hpsa_sas_port *hpsa_sas_port;
9628 struct sas_phy *phy;
9629 struct sas_identify *identify;
9630
9631 hpsa_sas_port = hpsa_sas_phy->parent_port;
9632 phy = hpsa_sas_phy->phy;
9633
9634 identify = &phy->identify;
9635 memset(identify, 0, sizeof(*identify));
9636 identify->sas_address = hpsa_sas_port->sas_address;
9637 identify->device_type = SAS_END_DEVICE;
9638 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9639 identify->target_port_protocols = SAS_PROTOCOL_STP;
9640 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9641 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9642 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9643 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9644 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9645
9646 rc = sas_phy_add(hpsa_sas_phy->phy);
9647 if (rc)
9648 return rc;
9649
9650 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9651 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9652 &hpsa_sas_port->phy_list_head);
9653 hpsa_sas_phy->added_to_port = true;
9654
9655 return 0;
9656}
9657
9658static int
9659 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9660 struct sas_rphy *rphy)
9661{
9662 struct sas_identify *identify;
9663
9664 identify = &rphy->identify;
9665 identify->sas_address = hpsa_sas_port->sas_address;
9666 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9667 identify->target_port_protocols = SAS_PROTOCOL_STP;
9668
9669 return sas_rphy_add(rphy);
9670}
9671
9672static struct hpsa_sas_port
9673 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9674 u64 sas_address)
9675{
9676 int rc;
9677 struct hpsa_sas_port *hpsa_sas_port;
9678 struct sas_port *port;
9679
9680 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9681 if (!hpsa_sas_port)
9682 return NULL;
9683
9684 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9685 hpsa_sas_port->parent_node = hpsa_sas_node;
9686
9687 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9688 if (!port)
9689 goto free_hpsa_port;
9690
9691 rc = sas_port_add(port);
9692 if (rc)
9693 goto free_sas_port;
9694
9695 hpsa_sas_port->port = port;
9696 hpsa_sas_port->sas_address = sas_address;
9697 list_add_tail(&hpsa_sas_port->port_list_entry,
9698 &hpsa_sas_node->port_list_head);
9699
9700 return hpsa_sas_port;
9701
9702free_sas_port:
9703 sas_port_free(port);
9704free_hpsa_port:
9705 kfree(hpsa_sas_port);
9706
9707 return NULL;
9708}
9709
9710static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9711{
9712 struct hpsa_sas_phy *hpsa_sas_phy;
9713 struct hpsa_sas_phy *next;
9714
9715 list_for_each_entry_safe(hpsa_sas_phy, next,
9716 &hpsa_sas_port->phy_list_head, phy_list_entry)
9717 hpsa_free_sas_phy(hpsa_sas_phy);
9718
9719 sas_port_delete(hpsa_sas_port->port);
9720 list_del(&hpsa_sas_port->port_list_entry);
9721 kfree(hpsa_sas_port);
9722}
9723
9724static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9725{
9726 struct hpsa_sas_node *hpsa_sas_node;
9727
9728 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9729 if (hpsa_sas_node) {
9730 hpsa_sas_node->parent_dev = parent_dev;
9731 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9732 }
9733
9734 return hpsa_sas_node;
9735}
9736
9737static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9738{
9739 struct hpsa_sas_port *hpsa_sas_port;
9740 struct hpsa_sas_port *next;
9741
9742 if (!hpsa_sas_node)
9743 return;
9744
9745 list_for_each_entry_safe(hpsa_sas_port, next,
9746 &hpsa_sas_node->port_list_head, port_list_entry)
9747 hpsa_free_sas_port(hpsa_sas_port);
9748
9749 kfree(hpsa_sas_node);
9750}
9751
9752static struct hpsa_scsi_dev_t
9753 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9754 struct sas_rphy *rphy)
9755{
9756 int i;
9757 struct hpsa_scsi_dev_t *device;
9758
9759 for (i = 0; i < h->ndevices; i++) {
9760 device = h->dev[i];
9761 if (!device->sas_port)
9762 continue;
9763 if (device->sas_port->rphy == rphy)
9764 return device;
9765 }
9766
9767 return NULL;
9768}
9769
9770static int hpsa_add_sas_host(struct ctlr_info *h)
9771{
9772 int rc;
9773 struct device *parent_dev;
9774 struct hpsa_sas_node *hpsa_sas_node;
9775 struct hpsa_sas_port *hpsa_sas_port;
9776 struct hpsa_sas_phy *hpsa_sas_phy;
9777
9778 parent_dev = &h->scsi_host->shost_gendev;
9779
9780 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9781 if (!hpsa_sas_node)
9782 return -ENOMEM;
9783
9784 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9785 if (!hpsa_sas_port) {
9786 rc = -ENODEV;
9787 goto free_sas_node;
9788 }
9789
9790 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9791 if (!hpsa_sas_phy) {
9792 rc = -ENODEV;
9793 goto free_sas_port;
9794 }
9795
9796 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9797 if (rc)
9798 goto free_sas_phy;
9799
9800 h->sas_host = hpsa_sas_node;
9801
9802 return 0;
9803
9804free_sas_phy:
9805 hpsa_free_sas_phy(hpsa_sas_phy);
9806free_sas_port:
9807 hpsa_free_sas_port(hpsa_sas_port);
9808free_sas_node:
9809 hpsa_free_sas_node(hpsa_sas_node);
9810
9811 return rc;
9812}
9813
9814static void hpsa_delete_sas_host(struct ctlr_info *h)
9815{
9816 hpsa_free_sas_node(h->sas_host);
9817}
9818
9819static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9820 struct hpsa_scsi_dev_t *device)
9821{
9822 int rc;
9823 struct hpsa_sas_port *hpsa_sas_port;
9824 struct sas_rphy *rphy;
9825
9826 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9827 if (!hpsa_sas_port)
9828 return -ENOMEM;
9829
9830 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9831 if (!rphy) {
9832 rc = -ENODEV;
9833 goto free_sas_port;
9834 }
9835
9836 hpsa_sas_port->rphy = rphy;
9837 device->sas_port = hpsa_sas_port;
9838
9839 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9840 if (rc)
9841 goto free_sas_port;
9842
9843 return 0;
9844
9845free_sas_port:
9846 hpsa_free_sas_port(hpsa_sas_port);
9847 device->sas_port = NULL;
9848
9849 return rc;
9850}
9851
9852static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9853{
9854 if (device->sas_port) {
9855 hpsa_free_sas_port(device->sas_port);
9856 device->sas_port = NULL;
9857 }
9858}
9859
9860static int
9861hpsa_sas_get_linkerrors(struct sas_phy *phy)
9862{
9863 return 0;
9864}
9865
9866static int
9867hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9868{
aa105695 9869 *identifier = 0;
d04e62b9
KB		 9870 return 0;
9871}
9872
9873static int
9874hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9875{
9876 return -ENXIO;
9877}
9878
9879static int
9880hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9881{
9882 return 0;
9883}
9884
9885static int
9886hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9887{
9888 return 0;
9889}
9890
9891static int
9892hpsa_sas_phy_setup(struct sas_phy *phy)
9893{
9894 return 0;
9895}
9896
9897static void
9898hpsa_sas_phy_release(struct sas_phy *phy)
9899{
9900}
9901
9902static int
9903hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9904{
9905 return -EINVAL;
9906}
9907
9908/* SMP = Serial Management Protocol */
9909static int
9910hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
9911struct request *req)
9912{
9913 return -EINVAL;
9914}
9915
9916static struct sas_function_template hpsa_sas_transport_functions = {
9917 .get_linkerrors = hpsa_sas_get_linkerrors,
9918 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9919 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9920 .phy_reset = hpsa_sas_phy_reset,
9921 .phy_enable = hpsa_sas_phy_enable,
9922 .phy_setup = hpsa_sas_phy_setup,
9923 .phy_release = hpsa_sas_phy_release,
9924 .set_phy_speed = hpsa_sas_phy_speed,
9925 .smp_handler = hpsa_sas_smp_handler,
9926};
9927
edd16368
SC		 9928/*
9929 * This is it. Register the PCI driver information for the cards we control
9930 * the OS will call our registered routines when it finds one of our cards.
9931 */
9932static int __init hpsa_init(void)
9933{
d04e62b9
KB		 9934 int rc;
9935
9936 hpsa_sas_transport_template =
9937 sas_attach_transport(&hpsa_sas_transport_functions);
9938 if (!hpsa_sas_transport_template)
9939 return -ENODEV;
9940
9941 rc = pci_register_driver(&hpsa_pci_driver);
9942
9943 if (rc)
9944 sas_release_transport(hpsa_sas_transport_template);
9945
9946 return rc;
edd16368
SC		 9947}
9948
9949static void __exit hpsa_cleanup(void)
9950{
9951 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9952 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9953}
9954
e1f7de0c
MG		 9955static void __attribute__((unused)) verify_offsets(void)
9956{
dd0e19f3
ST		 9957#define VERIFY_OFFSET(member, offset) \
9958 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9959
9960 VERIFY_OFFSET(structure_size, 0);
9961 VERIFY_OFFSET(volume_blk_size, 4);
9962 VERIFY_OFFSET(volume_blk_cnt, 8);
9963 VERIFY_OFFSET(phys_blk_shift, 16);
9964 VERIFY_OFFSET(parity_rotation_shift, 17);
9965 VERIFY_OFFSET(strip_size, 18);
9966 VERIFY_OFFSET(disk_starting_blk, 20);
9967 VERIFY_OFFSET(disk_blk_cnt, 28);
9968 VERIFY_OFFSET(data_disks_per_row, 36);
9969 VERIFY_OFFSET(metadata_disks_per_row, 38);
9970 VERIFY_OFFSET(row_cnt, 40);
9971 VERIFY_OFFSET(layout_map_count, 42);
9972 VERIFY_OFFSET(flags, 44);
9973 VERIFY_OFFSET(dekindex, 46);
9974 /* VERIFY_OFFSET(reserved, 48 */
9975 VERIFY_OFFSET(data, 64);
9976
9977#undef VERIFY_OFFSET
9978
b66cc250
MM		 9979#define VERIFY_OFFSET(member, offset) \
9980 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9981
9982 VERIFY_OFFSET(IU_type, 0);
9983 VERIFY_OFFSET(direction, 1);
9984 VERIFY_OFFSET(reply_queue, 2);
9985 /* VERIFY_OFFSET(reserved1, 3); */
9986 VERIFY_OFFSET(scsi_nexus, 4);
9987 VERIFY_OFFSET(Tag, 8);
9988 VERIFY_OFFSET(cdb, 16);
9989 VERIFY_OFFSET(cciss_lun, 32);
9990 VERIFY_OFFSET(data_len, 40);
9991 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9992 VERIFY_OFFSET(sg_count, 45);
9993 /* VERIFY_OFFSET(reserved3 */
9994 VERIFY_OFFSET(err_ptr, 48);
9995 VERIFY_OFFSET(err_len, 56);
9996 /* VERIFY_OFFSET(reserved4 */
9997 VERIFY_OFFSET(sg, 64);
9998
9999#undef VERIFY_OFFSET
10000
e1f7de0c
MG		 10001#define VERIFY_OFFSET(member, offset) \
10002 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
10003
10004 VERIFY_OFFSET(dev_handle, 0x00);
10005 VERIFY_OFFSET(reserved1, 0x02);
10006 VERIFY_OFFSET(function, 0x03);
10007 VERIFY_OFFSET(reserved2, 0x04);
10008 VERIFY_OFFSET(err_info, 0x0C);
10009 VERIFY_OFFSET(reserved3, 0x10);
10010 VERIFY_OFFSET(err_info_len, 0x12);
10011 VERIFY_OFFSET(reserved4, 0x13);
10012 VERIFY_OFFSET(sgl_offset, 0x14);
10013 VERIFY_OFFSET(reserved5, 0x15);
10014 VERIFY_OFFSET(transfer_len, 0x1C);
10015 VERIFY_OFFSET(reserved6, 0x20);
10016 VERIFY_OFFSET(io_flags, 0x24);
10017 VERIFY_OFFSET(reserved7, 0x26);
10018 VERIFY_OFFSET(LUN, 0x34);
10019 VERIFY_OFFSET(control, 0x3C);
10020 VERIFY_OFFSET(CDB, 0x40);
10021 VERIFY_OFFSET(reserved8, 0x50);
10022 VERIFY_OFFSET(host_context_flags, 0x60);
10023 VERIFY_OFFSET(timeout_sec, 0x62);
10024 VERIFY_OFFSET(ReplyQueue, 0x64);
10025 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 10026 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 10027 VERIFY_OFFSET(host_addr, 0x70);
10028 VERIFY_OFFSET(CISS_LUN, 0x78);
10029 VERIFY_OFFSET(SG, 0x78 + 8);
10030#undef VERIFY_OFFSET
10031}
10032
edd16368
SC		 10033module_init(hpsa_init);
10034module_exit(hpsa_cleanup);
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