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[SCSI] hpsa: add task management for ioaccel mode 2
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
76438d08
SC		 223static void hpsa_drain_commands(struct ctlr_info *h);
224static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
227 u8 *scsi3addr);
edd16368 228
edd16368
SC		 229static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
230{
231 unsigned long *priv = shost_priv(sdev->host);
232 return (struct ctlr_info *) *priv;
233}
234
a23513e8
SC		 235static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
236{
237 unsigned long *priv = shost_priv(sh);
238 return (struct ctlr_info *) *priv;
239}
240
edd16368
SC		 241static int check_for_unit_attention(struct ctlr_info *h,
242 struct CommandList *c)
243{
244 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
245 return 0;
246
247 switch (c->err_info->SenseInfo[12]) {
248 case STATE_CHANGED:
f79cfec6 249 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 250 "detected, command retried\n", h->ctlr);
251 break;
252 case LUN_FAILED:
f79cfec6 253 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 254 "detected, action required\n", h->ctlr);
255 break;
256 case REPORT_LUNS_CHANGED:
f79cfec6 257 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 258 "changed, action required\n", h->ctlr);
edd16368 259 /*
4f4eb9f1
ST		 260 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
261 * target (array) devices.
edd16368
SC		 262 */
263 break;
264 case POWER_OR_RESET:
f79cfec6 265 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 266 "or device reset detected\n", h->ctlr);
267 break;
268 case UNIT_ATTENTION_CLEARED:
f79cfec6 269 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 270 "cleared by another initiator\n", h->ctlr);
271 break;
272 default:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 274 "unit attention detected\n", h->ctlr);
275 break;
276 }
277 return 1;
278}
279
852af20a
MB		 280static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
281{
282 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
283 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
284 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
285 return 0;
286 dev_warn(&h->pdev->dev, HPSA "device busy");
287 return 1;
288}
289
edd16368
SC		 290static ssize_t host_store_rescan(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 struct ctlr_info *h;
295 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 296 h = shost_to_hba(shost);
31468401 297 hpsa_scan_start(h->scsi_host);
edd16368
SC		 298 return count;
299}
300
d28ce020
SC		 301static ssize_t host_show_firmware_revision(struct device *dev,
302 struct device_attribute *attr, char *buf)
303{
304 struct ctlr_info *h;
305 struct Scsi_Host *shost = class_to_shost(dev);
306 unsigned char *fwrev;
307
308 h = shost_to_hba(shost);
309 if (!h->hba_inquiry_data)
310 return 0;
311 fwrev = &h->hba_inquiry_data[32];
312 return snprintf(buf, 20, "%c%c%c%c\n",
313 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
314}
315
94a13649
SC		 316static ssize_t host_show_commands_outstanding(struct device *dev,
317 struct device_attribute *attr, char *buf)
318{
319 struct Scsi_Host *shost = class_to_shost(dev);
320 struct ctlr_info *h = shost_to_hba(shost);
321
322 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
323}
324
745a7a25
SC		 325static ssize_t host_show_transport_mode(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330
331 h = shost_to_hba(shost);
332 return snprintf(buf, 20, "%s\n",
960a30e7 333 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 334 "performant" : "simple");
335}
336
46380786 337/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 338static u32 unresettable_controller[] = {
339 0x324a103C, /* Smart Array P712m */
340 0x324b103C, /* SmartArray P711m */
341 0x3223103C, /* Smart Array P800 */
342 0x3234103C, /* Smart Array P400 */
343 0x3235103C, /* Smart Array P400i */
344 0x3211103C, /* Smart Array E200i */
345 0x3212103C, /* Smart Array E200 */
346 0x3213103C, /* Smart Array E200i */
347 0x3214103C, /* Smart Array E200i */
348 0x3215103C, /* Smart Array E200i */
349 0x3237103C, /* Smart Array E500 */
350 0x323D103C, /* Smart Array P700m */
7af0abbc 351 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 352 0x409C0E11, /* Smart Array 6400 */
353 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 354 0x40700E11, /* Smart Array 5300 */
355 0x40820E11, /* Smart Array 532 */
356 0x40830E11, /* Smart Array 5312 */
357 0x409A0E11, /* Smart Array 641 */
358 0x409B0E11, /* Smart Array 642 */
359 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 360};
361
46380786
SC		 362/* List of controllers which cannot even be soft reset */
363static u32 soft_unresettable_controller[] = {
7af0abbc 364 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 365 0x40700E11, /* Smart Array 5300 */
366 0x40820E11, /* Smart Array 532 */
367 0x40830E11, /* Smart Array 5312 */
368 0x409A0E11, /* Smart Array 641 */
369 0x409B0E11, /* Smart Array 642 */
370 0x40910E11, /* Smart Array 6i */
46380786
SC		 371 /* Exclude 640x boards. These are two pci devices in one slot
372 * which share a battery backed cache module. One controls the
373 * cache, the other accesses the cache through the one that controls
374 * it. If we reset the one controlling the cache, the other will
375 * likely not be happy. Just forbid resetting this conjoined mess.
376 * The 640x isn't really supported by hpsa anyway.
377 */
378 0x409C0E11, /* Smart Array 6400 */
379 0x409D0E11, /* Smart Array 6400 EM */
380};
381
382static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 383{
384 int i;
385
386 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 387 if (unresettable_controller[i] == board_id)
388 return 0;
389 return 1;
390}
391
392static int ctlr_is_soft_resettable(u32 board_id)
393{
394 int i;
395
396 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
397 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 398 return 0;
399 return 1;
400}
401
46380786
SC		 402static int ctlr_is_resettable(u32 board_id)
403{
404 return ctlr_is_hard_resettable(board_id) ||
405 ctlr_is_soft_resettable(board_id);
406}
407
941b1cda
SC		 408static ssize_t host_show_resettable(struct device *dev,
409 struct device_attribute *attr, char *buf)
410{
411 struct ctlr_info *h;
412 struct Scsi_Host *shost = class_to_shost(dev);
413
414 h = shost_to_hba(shost);
46380786 415 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 416}
417
edd16368
SC		 418static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
419{
420 return (scsi3addr[3] & 0xC0) == 0x40;
421}
422
423static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 424 "1(ADM)", "UNKNOWN"
edd16368
SC		 425};
426#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
427
428static ssize_t raid_level_show(struct device *dev,
429 struct device_attribute *attr, char *buf)
430{
431 ssize_t l = 0;
82a72c0a 432 unsigned char rlevel;
edd16368
SC		 433 struct ctlr_info *h;
434 struct scsi_device *sdev;
435 struct hpsa_scsi_dev_t *hdev;
436 unsigned long flags;
437
438 sdev = to_scsi_device(dev);
439 h = sdev_to_hba(sdev);
440 spin_lock_irqsave(&h->lock, flags);
441 hdev = sdev->hostdata;
442 if (!hdev) {
443 spin_unlock_irqrestore(&h->lock, flags);
444 return -ENODEV;
445 }
446
447 /* Is this even a logical drive? */
448 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
449 spin_unlock_irqrestore(&h->lock, flags);
450 l = snprintf(buf, PAGE_SIZE, "N/A\n");
451 return l;
452 }
453
454 rlevel = hdev->raid_level;
455 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 456 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 457 rlevel = RAID_UNKNOWN;
458 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
459 return l;
460}
461
462static ssize_t lunid_show(struct device *dev,
463 struct device_attribute *attr, char *buf)
464{
465 struct ctlr_info *h;
466 struct scsi_device *sdev;
467 struct hpsa_scsi_dev_t *hdev;
468 unsigned long flags;
469 unsigned char lunid[8];
470
471 sdev = to_scsi_device(dev);
472 h = sdev_to_hba(sdev);
473 spin_lock_irqsave(&h->lock, flags);
474 hdev = sdev->hostdata;
475 if (!hdev) {
476 spin_unlock_irqrestore(&h->lock, flags);
477 return -ENODEV;
478 }
479 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
480 spin_unlock_irqrestore(&h->lock, flags);
481 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
482 lunid[0], lunid[1], lunid[2], lunid[3],
483 lunid[4], lunid[5], lunid[6], lunid[7]);
484}
485
486static ssize_t unique_id_show(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct scsi_device *sdev;
491 struct hpsa_scsi_dev_t *hdev;
492 unsigned long flags;
493 unsigned char sn[16];
494
495 sdev = to_scsi_device(dev);
496 h = sdev_to_hba(sdev);
497 spin_lock_irqsave(&h->lock, flags);
498 hdev = sdev->hostdata;
499 if (!hdev) {
500 spin_unlock_irqrestore(&h->lock, flags);
501 return -ENODEV;
502 }
503 memcpy(sn, hdev->device_id, sizeof(sn));
504 spin_unlock_irqrestore(&h->lock, flags);
505 return snprintf(buf, 16 * 2 + 2,
506 "%02X%02X%02X%02X%02X%02X%02X%02X"
507 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
508 sn[0], sn[1], sn[2], sn[3],
509 sn[4], sn[5], sn[6], sn[7],
510 sn[8], sn[9], sn[10], sn[11],
511 sn[12], sn[13], sn[14], sn[15]);
512}
513
c1988684
ST		 514static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
515 struct device_attribute *attr, char *buf)
516{
517 struct ctlr_info *h;
518 struct scsi_device *sdev;
519 struct hpsa_scsi_dev_t *hdev;
520 unsigned long flags;
521 int offload_enabled;
522
523 sdev = to_scsi_device(dev);
524 h = sdev_to_hba(sdev);
525 spin_lock_irqsave(&h->lock, flags);
526 hdev = sdev->hostdata;
527 if (!hdev) {
528 spin_unlock_irqrestore(&h->lock, flags);
529 return -ENODEV;
530 }
531 offload_enabled = hdev->offload_enabled;
532 spin_unlock_irqrestore(&h->lock, flags);
533 return snprintf(buf, 20, "%d\n", offload_enabled);
534}
535
3f5eac3a
SC		 536static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
537static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
538static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
539static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 540static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
541 host_show_hp_ssd_smart_path_enabled, NULL);
3f5eac3a
SC		 542static DEVICE_ATTR(firmware_revision, S_IRUGO,
543 host_show_firmware_revision, NULL);
544static DEVICE_ATTR(commands_outstanding, S_IRUGO,
545 host_show_commands_outstanding, NULL);
546static DEVICE_ATTR(transport_mode, S_IRUGO,
547 host_show_transport_mode, NULL);
941b1cda
SC		 548static DEVICE_ATTR(resettable, S_IRUGO,
549 host_show_resettable, NULL);
3f5eac3a
SC		 550
551static struct device_attribute *hpsa_sdev_attrs[] = {
552 &dev_attr_raid_level,
553 &dev_attr_lunid,
554 &dev_attr_unique_id,
c1988684 555 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 556 NULL,
557};
558
559static struct device_attribute *hpsa_shost_attrs[] = {
560 &dev_attr_rescan,
561 &dev_attr_firmware_revision,
562 &dev_attr_commands_outstanding,
563 &dev_attr_transport_mode,
941b1cda 564 &dev_attr_resettable,
3f5eac3a
SC		 565 NULL,
566};
567
568static struct scsi_host_template hpsa_driver_template = {
569 .module = THIS_MODULE,
f79cfec6
SC		 570 .name = HPSA,
571 .proc_name = HPSA,
3f5eac3a
SC		 572 .queuecommand = hpsa_scsi_queue_command,
573 .scan_start = hpsa_scan_start,
574 .scan_finished = hpsa_scan_finished,
575 .change_queue_depth = hpsa_change_queue_depth,
576 .this_id = -1,
577 .use_clustering = ENABLE_CLUSTERING,
75167d2c 578 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 579 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
580 .ioctl = hpsa_ioctl,
581 .slave_alloc = hpsa_slave_alloc,
582 .slave_destroy = hpsa_slave_destroy,
583#ifdef CONFIG_COMPAT
584 .compat_ioctl = hpsa_compat_ioctl,
585#endif
586 .sdev_attrs = hpsa_sdev_attrs,
587 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 588 .max_sectors = 8192,
54b2b50c 589 .no_write_same = 1,
3f5eac3a
SC		 590};
591
592
593/* Enqueuing and dequeuing functions for cmdlists. */
594static inline void addQ(struct list_head *list, struct CommandList *c)
595{
596 list_add_tail(&c->list, list);
597}
598
254f796b 599static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 600{
601 u32 a;
254f796b 602 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 603 unsigned long flags;
3f5eac3a 604
e1f7de0c
MG		 605 if (h->transMethod & CFGTBL_Trans_io_accel1)
606 return h->access.command_completed(h, q);
607
3f5eac3a 608 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 609 return h->access.command_completed(h, q);
3f5eac3a 610
254f796b
MG		 611 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
612 a = rq->head[rq->current_entry];
613 rq->current_entry++;
e16a33ad 614 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 615 h->commands_outstanding--;
e16a33ad 616 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 617 } else {
618 a = FIFO_EMPTY;
619 }
620 /* Check for wraparound */
254f796b
MG		 621 if (rq->current_entry == h->max_commands) {
622 rq->current_entry = 0;
623 rq->wraparound ^= 1;
3f5eac3a
SC		 624 }
625 return a;
626}
627
c349775e
ST		 628/*
629 * There are some special bits in the bus address of the
630 * command that we have to set for the controller to know
631 * how to process the command:
632 *
633 * Normal performant mode:
634 * bit 0: 1 means performant mode, 0 means simple mode.
635 * bits 1-3 = block fetch table entry
636 * bits 4-6 = command type (== 0)
637 *
638 * ioaccel1 mode:
639 * bit 0 = "performant mode" bit.
640 * bits 1-3 = block fetch table entry
641 * bits 4-6 = command type (== 110)
642 * (command type is needed because ioaccel1 mode
643 * commands are submitted through the same register as normal
644 * mode commands, so this is how the controller knows whether
645 * the command is normal mode or ioaccel1 mode.)
646 *
647 * ioaccel2 mode:
648 * bit 0 = "performant mode" bit.
649 * bits 1-4 = block fetch table entry (note extra bit)
650 * bits 4-6 = not needed, because ioaccel2 mode has
651 * a separate special register for submitting commands.
652 */
653
3f5eac3a
SC		 654/* set_performant_mode: Modify the tag for cciss performant
655 * set bit 0 for pull model, bits 3-1 for block fetch
656 * register number
657 */
658static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
659{
254f796b 660 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 661 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 662 if (likely(h->msix_vector > 0))
254f796b 663 c->Header.ReplyQueue =
804a5cb5 664 raw_smp_processor_id() % h->nreply_queues;
254f796b 665 }
3f5eac3a
SC		 666}
667
c349775e
ST		 668static void set_ioaccel1_performant_mode(struct ctlr_info *h,
669 struct CommandList *c)
670{
671 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
672
673 /* Tell the controller to post the reply to the queue for this
674 * processor. This seems to give the best I/O throughput.
675 */
676 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
677 /* Set the bits in the address sent down to include:
678 * - performant mode bit (bit 0)
679 * - pull count (bits 1-3)
680 * - command type (bits 4-6)
681 */
682 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
683 IOACCEL1_BUSADDR_CMDTYPE;
684}
685
686static void set_ioaccel2_performant_mode(struct ctlr_info *h,
687 struct CommandList *c)
688{
689 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
690
691 /* Tell the controller to post the reply to the queue for this
692 * processor. This seems to give the best I/O throughput.
693 */
694 cp->reply_queue = smp_processor_id() % h->nreply_queues;
695 /* Set the bits in the address sent down to include:
696 * - performant mode bit not used in ioaccel mode 2
697 * - pull count (bits 0-3)
698 * - command type isn't needed for ioaccel2
699 */
700 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
701}
702
e85c5974
SC		 703static int is_firmware_flash_cmd(u8 *cdb)
704{
705 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
706}
707
708/*
709 * During firmware flash, the heartbeat register may not update as frequently
710 * as it should. So we dial down lockup detection during firmware flash. and
711 * dial it back up when firmware flash completes.
712 */
713#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
714#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
715static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
716 struct CommandList *c)
717{
718 if (!is_firmware_flash_cmd(c->Request.CDB))
719 return;
720 atomic_inc(&h->firmware_flash_in_progress);
721 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
722}
723
724static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
725 struct CommandList *c)
726{
727 if (is_firmware_flash_cmd(c->Request.CDB) &&
728 atomic_dec_and_test(&h->firmware_flash_in_progress))
729 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
730}
731
3f5eac3a
SC		 732static void enqueue_cmd_and_start_io(struct ctlr_info *h,
733 struct CommandList *c)
734{
735 unsigned long flags;
736
c349775e
ST		 737 switch (c->cmd_type) {
738 case CMD_IOACCEL1:
739 set_ioaccel1_performant_mode(h, c);
740 break;
741 case CMD_IOACCEL2:
742 set_ioaccel2_performant_mode(h, c);
743 break;
744 default:
745 set_performant_mode(h, c);
746 }
e85c5974 747 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 748 spin_lock_irqsave(&h->lock, flags);
749 addQ(&h->reqQ, c);
750 h->Qdepth++;
3f5eac3a 751 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 752 start_io(h);
3f5eac3a
SC		 753}
754
755static inline void removeQ(struct CommandList *c)
756{
757 if (WARN_ON(list_empty(&c->list)))
758 return;
759 list_del_init(&c->list);
760}
761
762static inline int is_hba_lunid(unsigned char scsi3addr[])
763{
764 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
765}
766
767static inline int is_scsi_rev_5(struct ctlr_info *h)
768{
769 if (!h->hba_inquiry_data)
770 return 0;
771 if ((h->hba_inquiry_data[2] & 0x07) == 5)
772 return 1;
773 return 0;
774}
775
edd16368
SC		 776static int hpsa_find_target_lun(struct ctlr_info *h,
777 unsigned char scsi3addr[], int bus, int *target, int *lun)
778{
779 /* finds an unused bus, target, lun for a new physical device
780 * assumes h->devlock is held
781 */
782 int i, found = 0;
cfe5badc 783 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 784
263d9401 785 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 786
787 for (i = 0; i < h->ndevices; i++) {
788 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 789 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 790 }
791
263d9401
AM		 792 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
793 if (i < HPSA_MAX_DEVICES) {
794 /* *bus = 1; */
795 *target = i;
796 *lun = 0;
797 found = 1;
edd16368
SC		 798 }
799 return !found;
800}
801
802/* Add an entry into h->dev[] array. */
803static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
804 struct hpsa_scsi_dev_t *device,
805 struct hpsa_scsi_dev_t *added[], int *nadded)
806{
807 /* assumes h->devlock is held */
808 int n = h->ndevices;
809 int i;
810 unsigned char addr1[8], addr2[8];
811 struct hpsa_scsi_dev_t *sd;
812
cfe5badc 813 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 814 dev_err(&h->pdev->dev, "too many devices, some will be "
815 "inaccessible.\n");
816 return -1;
817 }
818
819 /* physical devices do not have lun or target assigned until now. */
820 if (device->lun != -1)
821 /* Logical device, lun is already assigned. */
822 goto lun_assigned;
823
824 /* If this device a non-zero lun of a multi-lun device
825 * byte 4 of the 8-byte LUN addr will contain the logical
826 * unit no, zero otherise.
827 */
828 if (device->scsi3addr[4] == 0) {
829 /* This is not a non-zero lun of a multi-lun device */
830 if (hpsa_find_target_lun(h, device->scsi3addr,
831 device->bus, &device->target, &device->lun) != 0)
832 return -1;
833 goto lun_assigned;
834 }
835
836 /* This is a non-zero lun of a multi-lun device.
837 * Search through our list and find the device which
838 * has the same 8 byte LUN address, excepting byte 4.
839 * Assign the same bus and target for this new LUN.
840 * Use the logical unit number from the firmware.
841 */
842 memcpy(addr1, device->scsi3addr, 8);
843 addr1[4] = 0;
844 for (i = 0; i < n; i++) {
845 sd = h->dev[i];
846 memcpy(addr2, sd->scsi3addr, 8);
847 addr2[4] = 0;
848 /* differ only in byte 4? */
849 if (memcmp(addr1, addr2, 8) == 0) {
850 device->bus = sd->bus;
851 device->target = sd->target;
852 device->lun = device->scsi3addr[4];
853 break;
854 }
855 }
856 if (device->lun == -1) {
857 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
858 " suspect firmware bug or unsupported hardware "
859 "configuration.\n");
860 return -1;
861 }
862
863lun_assigned:
864
865 h->dev[n] = device;
866 h->ndevices++;
867 added[*nadded] = device;
868 (*nadded)++;
869
870 /* initially, (before registering with scsi layer) we don't
871 * know our hostno and we don't want to print anything first
872 * time anyway (the scsi layer's inquiries will show that info)
873 */
874 /* if (hostno != -1) */
875 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
876 scsi_device_type(device->devtype), hostno,
877 device->bus, device->target, device->lun);
878 return 0;
879}
880
bd9244f7
ST		 881/* Update an entry in h->dev[] array. */
882static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
883 int entry, struct hpsa_scsi_dev_t *new_entry)
884{
885 /* assumes h->devlock is held */
886 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
887
888 /* Raid level changed. */
889 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 890
891 /* Raid offload parameters changed. */
892 h->dev[entry]->offload_config = new_entry->offload_config;
893 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
894
bd9244f7
ST		 895 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
896 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
897 new_entry->target, new_entry->lun);
898}
899
2a8ccf31
SC		 900/* Replace an entry from h->dev[] array. */
901static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
902 int entry, struct hpsa_scsi_dev_t *new_entry,
903 struct hpsa_scsi_dev_t *added[], int *nadded,
904 struct hpsa_scsi_dev_t *removed[], int *nremoved)
905{
906 /* assumes h->devlock is held */
cfe5badc 907 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 908 removed[*nremoved] = h->dev[entry];
909 (*nremoved)++;
01350d05
SC		 910
911 /*
912 * New physical devices won't have target/lun assigned yet
913 * so we need to preserve the values in the slot we are replacing.
914 */
915 if (new_entry->target == -1) {
916 new_entry->target = h->dev[entry]->target;
917 new_entry->lun = h->dev[entry]->lun;
918 }
919
2a8ccf31
SC		 920 h->dev[entry] = new_entry;
921 added[*nadded] = new_entry;
922 (*nadded)++;
923 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
924 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
925 new_entry->target, new_entry->lun);
926}
927
edd16368
SC		 928/* Remove an entry from h->dev[] array. */
929static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
930 struct hpsa_scsi_dev_t *removed[], int *nremoved)
931{
932 /* assumes h->devlock is held */
933 int i;
934 struct hpsa_scsi_dev_t *sd;
935
cfe5badc 936 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 937
938 sd = h->dev[entry];
939 removed[*nremoved] = h->dev[entry];
940 (*nremoved)++;
941
942 for (i = entry; i < h->ndevices-1; i++)
943 h->dev[i] = h->dev[i+1];
944 h->ndevices--;
945 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
946 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
947 sd->lun);
948}
949
950#define SCSI3ADDR_EQ(a, b) ( \
951 (a)[7] == (b)[7] && \
952 (a)[6] == (b)[6] && \
953 (a)[5] == (b)[5] && \
954 (a)[4] == (b)[4] && \
955 (a)[3] == (b)[3] && \
956 (a)[2] == (b)[2] && \
957 (a)[1] == (b)[1] && \
958 (a)[0] == (b)[0])
959
960static void fixup_botched_add(struct ctlr_info *h,
961 struct hpsa_scsi_dev_t *added)
962{
963 /* called when scsi_add_device fails in order to re-adjust
964 * h->dev[] to match the mid layer's view.
965 */
966 unsigned long flags;
967 int i, j;
968
969 spin_lock_irqsave(&h->lock, flags);
970 for (i = 0; i < h->ndevices; i++) {
971 if (h->dev[i] == added) {
972 for (j = i; j < h->ndevices-1; j++)
973 h->dev[j] = h->dev[j+1];
974 h->ndevices--;
975 break;
976 }
977 }
978 spin_unlock_irqrestore(&h->lock, flags);
979 kfree(added);
980}
981
982static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
983 struct hpsa_scsi_dev_t *dev2)
984{
edd16368
SC		 985 /* we compare everything except lun and target as these
986 * are not yet assigned. Compare parts likely
987 * to differ first
988 */
989 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
990 sizeof(dev1->scsi3addr)) != 0)
991 return 0;
992 if (memcmp(dev1->device_id, dev2->device_id,
993 sizeof(dev1->device_id)) != 0)
994 return 0;
995 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
996 return 0;
997 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
998 return 0;
edd16368
SC		 999 if (dev1->devtype != dev2->devtype)
1000 return 0;
edd16368
SC		 1001 if (dev1->bus != dev2->bus)
1002 return 0;
1003 return 1;
1004}
1005
bd9244f7
ST		 1006static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1007 struct hpsa_scsi_dev_t *dev2)
1008{
1009 /* Device attributes that can change, but don't mean
1010 * that the device is a different device, nor that the OS
1011 * needs to be told anything about the change.
1012 */
1013 if (dev1->raid_level != dev2->raid_level)
1014 return 1;
250fb125
SC		 1015 if (dev1->offload_config != dev2->offload_config)
1016 return 1;
1017 if (dev1->offload_enabled != dev2->offload_enabled)
1018 return 1;
bd9244f7
ST		 1019 return 0;
1020}
1021
edd16368
SC		 1022/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1023 * and return needle location in *index. If scsi3addr matches, but not
1024 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1025 * location in *index.
1026 * In the case of a minor device attribute change, such as RAID level, just
1027 * return DEVICE_UPDATED, along with the updated device's location in index.
1028 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1029 */
1030static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1031 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1032 int *index)
1033{
1034 int i;
1035#define DEVICE_NOT_FOUND 0
1036#define DEVICE_CHANGED 1
1037#define DEVICE_SAME 2
bd9244f7 1038#define DEVICE_UPDATED 3
edd16368 1039 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1040 if (haystack[i] == NULL) /* previously removed. */
1041 continue;
edd16368
SC		 1042 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1043 *index = i;
bd9244f7
ST		 1044 if (device_is_the_same(needle, haystack[i])) {
1045 if (device_updated(needle, haystack[i]))
1046 return DEVICE_UPDATED;
edd16368 1047 return DEVICE_SAME;
bd9244f7 1048 } else {
edd16368 1049 return DEVICE_CHANGED;
bd9244f7 1050 }
edd16368
SC		 1051 }
1052 }
1053 *index = -1;
1054 return DEVICE_NOT_FOUND;
1055}
1056
4967bd3e 1057static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1058 struct hpsa_scsi_dev_t *sd[], int nsds)
1059{
1060 /* sd contains scsi3 addresses and devtypes, and inquiry
1061 * data. This function takes what's in sd to be the current
1062 * reality and updates h->dev[] to reflect that reality.
1063 */
1064 int i, entry, device_change, changes = 0;
1065 struct hpsa_scsi_dev_t *csd;
1066 unsigned long flags;
1067 struct hpsa_scsi_dev_t **added, **removed;
1068 int nadded, nremoved;
1069 struct Scsi_Host *sh = NULL;
1070
cfe5badc
ST		 1071 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1072 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1073
1074 if (!added || !removed) {
1075 dev_warn(&h->pdev->dev, "out of memory in "
1076 "adjust_hpsa_scsi_table\n");
1077 goto free_and_out;
1078 }
1079
1080 spin_lock_irqsave(&h->devlock, flags);
1081
1082 /* find any devices in h->dev[] that are not in
1083 * sd[] and remove them from h->dev[], and for any
1084 * devices which have changed, remove the old device
1085 * info and add the new device info.
bd9244f7
ST		 1086 * If minor device attributes change, just update
1087 * the existing device structure.
edd16368
SC		 1088 */
1089 i = 0;
1090 nremoved = 0;
1091 nadded = 0;
1092 while (i < h->ndevices) {
1093 csd = h->dev[i];
1094 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1095 if (device_change == DEVICE_NOT_FOUND) {
1096 changes++;
1097 hpsa_scsi_remove_entry(h, hostno, i,
1098 removed, &nremoved);
1099 continue; /* remove ^^^, hence i not incremented */
1100 } else if (device_change == DEVICE_CHANGED) {
1101 changes++;
2a8ccf31
SC		 1102 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1103 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1104 /* Set it to NULL to prevent it from being freed
1105 * at the bottom of hpsa_update_scsi_devices()
1106 */
1107 sd[entry] = NULL;
bd9244f7
ST		 1108 } else if (device_change == DEVICE_UPDATED) {
1109 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1110 }
1111 i++;
1112 }
1113
1114 /* Now, make sure every device listed in sd[] is also
1115 * listed in h->dev[], adding them if they aren't found
1116 */
1117
1118 for (i = 0; i < nsds; i++) {
1119 if (!sd[i]) /* if already added above. */
1120 continue;
1121 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1122 h->ndevices, &entry);
1123 if (device_change == DEVICE_NOT_FOUND) {
1124 changes++;
1125 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1126 added, &nadded) != 0)
1127 break;
1128 sd[i] = NULL; /* prevent from being freed later. */
1129 } else if (device_change == DEVICE_CHANGED) {
1130 /* should never happen... */
1131 changes++;
1132 dev_warn(&h->pdev->dev,
1133 "device unexpectedly changed.\n");
1134 /* but if it does happen, we just ignore that device */
1135 }
1136 }
1137 spin_unlock_irqrestore(&h->devlock, flags);
1138
1139 /* Don't notify scsi mid layer of any changes the first time through
1140 * (or if there are no changes) scsi_scan_host will do it later the
1141 * first time through.
1142 */
1143 if (hostno == -1 || !changes)
1144 goto free_and_out;
1145
1146 sh = h->scsi_host;
1147 /* Notify scsi mid layer of any removed devices */
1148 for (i = 0; i < nremoved; i++) {
1149 struct scsi_device *sdev =
1150 scsi_device_lookup(sh, removed[i]->bus,
1151 removed[i]->target, removed[i]->lun);
1152 if (sdev != NULL) {
1153 scsi_remove_device(sdev);
1154 scsi_device_put(sdev);
1155 } else {
1156 /* We don't expect to get here.
1157 * future cmds to this device will get selection
1158 * timeout as if the device was gone.
1159 */
1160 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1161 " for removal.", hostno, removed[i]->bus,
1162 removed[i]->target, removed[i]->lun);
1163 }
1164 kfree(removed[i]);
1165 removed[i] = NULL;
1166 }
1167
1168 /* Notify scsi mid layer of any added devices */
1169 for (i = 0; i < nadded; i++) {
1170 if (scsi_add_device(sh, added[i]->bus,
1171 added[i]->target, added[i]->lun) == 0)
1172 continue;
1173 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1174 "device not added.\n", hostno, added[i]->bus,
1175 added[i]->target, added[i]->lun);
1176 /* now we have to remove it from h->dev,
1177 * since it didn't get added to scsi mid layer
1178 */
1179 fixup_botched_add(h, added[i]);
1180 }
1181
1182free_and_out:
1183 kfree(added);
1184 kfree(removed);
edd16368
SC		 1185}
1186
1187/*
9e03aa2f 1188 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1189 * Assume's h->devlock is held.
1190 */
1191static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1192 int bus, int target, int lun)
1193{
1194 int i;
1195 struct hpsa_scsi_dev_t *sd;
1196
1197 for (i = 0; i < h->ndevices; i++) {
1198 sd = h->dev[i];
1199 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1200 return sd;
1201 }
1202 return NULL;
1203}
1204
1205/* link sdev->hostdata to our per-device structure. */
1206static int hpsa_slave_alloc(struct scsi_device *sdev)
1207{
1208 struct hpsa_scsi_dev_t *sd;
1209 unsigned long flags;
1210 struct ctlr_info *h;
1211
1212 h = sdev_to_hba(sdev);
1213 spin_lock_irqsave(&h->devlock, flags);
1214 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1215 sdev_id(sdev), sdev->lun);
1216 if (sd != NULL)
1217 sdev->hostdata = sd;
1218 spin_unlock_irqrestore(&h->devlock, flags);
1219 return 0;
1220}
1221
1222static void hpsa_slave_destroy(struct scsi_device *sdev)
1223{
bcc44255 1224 /* nothing to do. */
edd16368
SC		 1225}
1226
33a2ffce
SC		 1227static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1228{
1229 int i;
1230
1231 if (!h->cmd_sg_list)
1232 return;
1233 for (i = 0; i < h->nr_cmds; i++) {
1234 kfree(h->cmd_sg_list[i]);
1235 h->cmd_sg_list[i] = NULL;
1236 }
1237 kfree(h->cmd_sg_list);
1238 h->cmd_sg_list = NULL;
1239}
1240
1241static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1242{
1243 int i;
1244
1245 if (h->chainsize <= 0)
1246 return 0;
1247
1248 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1249 GFP_KERNEL);
1250 if (!h->cmd_sg_list)
1251 return -ENOMEM;
1252 for (i = 0; i < h->nr_cmds; i++) {
1253 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1254 h->chainsize, GFP_KERNEL);
1255 if (!h->cmd_sg_list[i])
1256 goto clean;
1257 }
1258 return 0;
1259
1260clean:
1261 hpsa_free_sg_chain_blocks(h);
1262 return -ENOMEM;
1263}
1264
e2bea6df 1265static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1266 struct CommandList *c)
1267{
1268 struct SGDescriptor *chain_sg, *chain_block;
1269 u64 temp64;
1270
1271 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1272 chain_block = h->cmd_sg_list[c->cmdindex];
1273 chain_sg->Ext = HPSA_SG_CHAIN;
1274 chain_sg->Len = sizeof(*chain_sg) *
1275 (c->Header.SGTotal - h->max_cmd_sg_entries);
1276 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1277 PCI_DMA_TODEVICE);
e2bea6df
SC		 1278 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1279 /* prevent subsequent unmapping */
1280 chain_sg->Addr.lower = 0;
1281 chain_sg->Addr.upper = 0;
1282 return -1;
1283 }
33a2ffce
SC		 1284 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1285 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1286 return 0;
33a2ffce
SC		 1287}
1288
1289static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1290 struct CommandList *c)
1291{
1292 struct SGDescriptor *chain_sg;
1293 union u64bit temp64;
1294
1295 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1296 return;
1297
1298 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1299 temp64.val32.lower = chain_sg->Addr.lower;
1300 temp64.val32.upper = chain_sg->Addr.upper;
1301 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1302}
1303
c349775e
ST		 1304static void handle_ioaccel_mode2_error(struct ctlr_info *h,
1305 struct CommandList *c,
1306 struct scsi_cmnd *cmd,
1307 struct io_accel2_cmd *c2)
1308{
1309 int data_len;
1310
1311 switch (c2->error_data.serv_response) {
1312 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1313 switch (c2->error_data.status) {
1314 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1315 break;
1316 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1317 dev_warn(&h->pdev->dev,
1318 "%s: task complete with check condition.\n",
1319 "HP SSD Smart Path");
1320 if (c2->error_data.data_present !=
1321 IOACCEL2_SENSE_DATA_PRESENT)
1322 break;
1323 /* copy the sense data */
1324 data_len = c2->error_data.sense_data_len;
1325 if (data_len > SCSI_SENSE_BUFFERSIZE)
1326 data_len = SCSI_SENSE_BUFFERSIZE;
1327 if (data_len > sizeof(c2->error_data.sense_data_buff))
1328 data_len =
1329 sizeof(c2->error_data.sense_data_buff);
1330 memcpy(cmd->sense_buffer,
1331 c2->error_data.sense_data_buff, data_len);
1332 cmd->result |= SAM_STAT_CHECK_CONDITION;
1333 break;
1334 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1335 dev_warn(&h->pdev->dev,
1336 "%s: task complete with BUSY status.\n",
1337 "HP SSD Smart Path");
1338 break;
1339 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1340 dev_warn(&h->pdev->dev,
1341 "%s: task complete with reservation conflict.\n",
1342 "HP SSD Smart Path");
1343 break;
1344 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1345 /* Make scsi midlayer do unlimited retries */
1346 cmd->result = DID_IMM_RETRY << 16;
1347 break;
1348 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1349 dev_warn(&h->pdev->dev,
1350 "%s: task complete with aborted status.\n",
1351 "HP SSD Smart Path");
1352 break;
1353 default:
1354 dev_warn(&h->pdev->dev,
1355 "%s: task complete with unrecognized status: 0x%02x\n",
1356 "HP SSD Smart Path", c2->error_data.status);
1357 break;
1358 }
1359 break;
1360 case IOACCEL2_SERV_RESPONSE_FAILURE:
1361 /* don't expect to get here. */
1362 dev_warn(&h->pdev->dev,
1363 "unexpected delivery or target failure, status = 0x%02x\n",
1364 c2->error_data.status);
1365 break;
1366 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1367 break;
1368 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1369 break;
1370 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1371 dev_warn(&h->pdev->dev, "task management function rejected.\n");
1372 break;
1373 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1374 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1375 break;
1376 default:
1377 dev_warn(&h->pdev->dev,
1378 "%s: Unrecognized server response: 0x%02x\n",
1379 "HP SSD Smart Path", c2->error_data.serv_response);
1380 break;
1381 }
1382}
1383
1384static void process_ioaccel2_completion(struct ctlr_info *h,
1385 struct CommandList *c, struct scsi_cmnd *cmd,
1386 struct hpsa_scsi_dev_t *dev)
1387{
1388 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1389
1390 /* check for good status */
1391 if (likely(c2->error_data.serv_response == 0 &&
1392 c2->error_data.status == 0)) {
1393 cmd_free(h, c);
1394 cmd->scsi_done(cmd);
1395 return;
1396 }
1397
1398 /* Any RAID offload error results in retry which will use
1399 * the normal I/O path so the controller can handle whatever's
1400 * wrong.
1401 */
1402 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1403 c2->error_data.serv_response ==
1404 IOACCEL2_SERV_RESPONSE_FAILURE) {
1405 if (c2->error_data.status !=
1406 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1407 dev_warn(&h->pdev->dev,
1408 "%s: Error 0x%02x, Retrying on standard path.\n",
1409 "HP SSD Smart Path", c2->error_data.status);
1410 dev->offload_enabled = 0;
1411 cmd->result = DID_SOFT_ERROR << 16;
1412 cmd_free(h, c);
1413 cmd->scsi_done(cmd);
1414 return;
1415 }
1416 handle_ioaccel_mode2_error(h, c, cmd, c2);
1417 cmd_free(h, c);
1418 cmd->scsi_done(cmd);
1419}
1420
1fb011fb 1421static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1422{
1423 struct scsi_cmnd *cmd;
1424 struct ctlr_info *h;
1425 struct ErrorInfo *ei;
283b4a9b 1426 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1427
1428 unsigned char sense_key;
1429 unsigned char asc; /* additional sense code */
1430 unsigned char ascq; /* additional sense code qualifier */
db111e18 1431 unsigned long sense_data_size;
edd16368
SC		 1432
1433 ei = cp->err_info;
1434 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1435 h = cp->h;
283b4a9b 1436 dev = cmd->device->hostdata;
edd16368
SC		 1437
1438 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1439 if ((cp->cmd_type == CMD_SCSI) &&
1440 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1441 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1442
1443 cmd->result = (DID_OK << 16); /* host byte */
1444 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1445
1446 if (cp->cmd_type == CMD_IOACCEL2)
1447 return process_ioaccel2_completion(h, cp, cmd, dev);
1448
5512672f 1449 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1450
1451 /* copy the sense data whether we need to or not. */
db111e18
SC		 1452 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1453 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1454 else
1455 sense_data_size = sizeof(ei->SenseInfo);
1456 if (ei->SenseLen < sense_data_size)
1457 sense_data_size = ei->SenseLen;
1458
1459 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1460 scsi_set_resid(cmd, ei->ResidualCnt);
1461
1462 if (ei->CommandStatus == 0) {
edd16368 1463 cmd_free(h, cp);
2cc5bfaf 1464 cmd->scsi_done(cmd);
edd16368
SC		 1465 return;
1466 }
1467
e1f7de0c
MG		 1468 /* For I/O accelerator commands, copy over some fields to the normal
1469 * CISS header used below for error handling.
1470 */
1471 if (cp->cmd_type == CMD_IOACCEL1) {
1472 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1473 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1474 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1475 cp->Header.Tag.lower = c->Tag.lower;
1476 cp->Header.Tag.upper = c->Tag.upper;
1477 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1478 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1479
1480 /* Any RAID offload error results in retry which will use
1481 * the normal I/O path so the controller can handle whatever's
1482 * wrong.
1483 */
1484 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1485 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1486 dev->offload_enabled = 0;
1487 cmd->result = DID_SOFT_ERROR << 16;
1488 cmd_free(h, cp);
1489 cmd->scsi_done(cmd);
1490 return;
1491 }
e1f7de0c
MG		 1492 }
1493
edd16368
SC		 1494 /* an error has occurred */
1495 switch (ei->CommandStatus) {
1496
1497 case CMD_TARGET_STATUS:
1498 if (ei->ScsiStatus) {
1499 /* Get sense key */
1500 sense_key = 0xf & ei->SenseInfo[2];
1501 /* Get additional sense code */
1502 asc = ei->SenseInfo[12];
1503 /* Get addition sense code qualifier */
1504 ascq = ei->SenseInfo[13];
1505 }
1506
1507 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1508 if (check_for_unit_attention(h, cp))
edd16368 1509 break;
edd16368
SC		 1510 if (sense_key == ILLEGAL_REQUEST) {
1511 /*
1512 * SCSI REPORT_LUNS is commonly unsupported on
1513 * Smart Array. Suppress noisy complaint.
1514 */
1515 if (cp->Request.CDB[0] == REPORT_LUNS)
1516 break;
1517
1518 /* If ASC/ASCQ indicate Logical Unit
1519 * Not Supported condition,
1520 */
1521 if ((asc == 0x25) && (ascq == 0x0)) {
1522 dev_warn(&h->pdev->dev, "cp %p "
1523 "has check condition\n", cp);
1524 break;
1525 }
1526 }
1527
1528 if (sense_key == NOT_READY) {
1529 /* If Sense is Not Ready, Logical Unit
1530 * Not ready, Manual Intervention
1531 * required
1532 */
1533 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1534 dev_warn(&h->pdev->dev, "cp %p "
1535 "has check condition: unit "
1536 "not ready, manual "
1537 "intervention required\n", cp);
1538 break;
1539 }
1540 }
1d3b3609
MG		 1541 if (sense_key == ABORTED_COMMAND) {
1542 /* Aborted command is retryable */
1543 dev_warn(&h->pdev->dev, "cp %p "
1544 "has check condition: aborted command: "
1545 "ASC: 0x%x, ASCQ: 0x%x\n",
1546 cp, asc, ascq);
2e311fba 1547 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1548 break;
1549 }
edd16368 1550 /* Must be some other type of check condition */
21b8e4ef 1551 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1552 "unknown type: "
1553 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1554 "Returning result: 0x%x, "
1555 "cmd=[%02x %02x %02x %02x %02x "
807be732 1556 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1557 "%02x %02x %02x %02x %02x]\n",
1558 cp, sense_key, asc, ascq,
1559 cmd->result,
1560 cmd->cmnd[0], cmd->cmnd[1],
1561 cmd->cmnd[2], cmd->cmnd[3],
1562 cmd->cmnd[4], cmd->cmnd[5],
1563 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1564 cmd->cmnd[8], cmd->cmnd[9],
1565 cmd->cmnd[10], cmd->cmnd[11],
1566 cmd->cmnd[12], cmd->cmnd[13],
1567 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1568 break;
1569 }
1570
1571
1572 /* Problem was not a check condition
1573 * Pass it up to the upper layers...
1574 */
1575 if (ei->ScsiStatus) {
1576 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1577 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1578 "Returning result: 0x%x\n",
1579 cp, ei->ScsiStatus,
1580 sense_key, asc, ascq,
1581 cmd->result);
1582 } else { /* scsi status is zero??? How??? */
1583 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1584 "Returning no connection.\n", cp),
1585
1586 /* Ordinarily, this case should never happen,
1587 * but there is a bug in some released firmware
1588 * revisions that allows it to happen if, for
1589 * example, a 4100 backplane loses power and
1590 * the tape drive is in it. We assume that
1591 * it's a fatal error of some kind because we
1592 * can't show that it wasn't. We will make it
1593 * look like selection timeout since that is
1594 * the most common reason for this to occur,
1595 * and it's severe enough.
1596 */
1597
1598 cmd->result = DID_NO_CONNECT << 16;
1599 }
1600 break;
1601
1602 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1603 break;
1604 case CMD_DATA_OVERRUN:
1605 dev_warn(&h->pdev->dev, "cp %p has"
1606 " completed with data overrun "
1607 "reported\n", cp);
1608 break;
1609 case CMD_INVALID: {
1610 /* print_bytes(cp, sizeof(*cp), 1, 0);
1611 print_cmd(cp); */
1612 /* We get CMD_INVALID if you address a non-existent device
1613 * instead of a selection timeout (no response). You will
1614 * see this if you yank out a drive, then try to access it.
1615 * This is kind of a shame because it means that any other
1616 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1617 * missing target. */
1618 cmd->result = DID_NO_CONNECT << 16;
1619 }
1620 break;
1621 case CMD_PROTOCOL_ERR:
256d0eaa 1622 cmd->result = DID_ERROR << 16;
edd16368 1623 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1624 "protocol error\n", cp);
edd16368
SC		 1625 break;
1626 case CMD_HARDWARE_ERR:
1627 cmd->result = DID_ERROR << 16;
1628 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1629 break;
1630 case CMD_CONNECTION_LOST:
1631 cmd->result = DID_ERROR << 16;
1632 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1633 break;
1634 case CMD_ABORTED:
1635 cmd->result = DID_ABORT << 16;
1636 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1637 cp, ei->ScsiStatus);
1638 break;
1639 case CMD_ABORT_FAILED:
1640 cmd->result = DID_ERROR << 16;
1641 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1642 break;
1643 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1644 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1645 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1646 "abort\n", cp);
1647 break;
1648 case CMD_TIMEOUT:
1649 cmd->result = DID_TIME_OUT << 16;
1650 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1651 break;
1d5e2ed0
SC		 1652 case CMD_UNABORTABLE:
1653 cmd->result = DID_ERROR << 16;
1654 dev_warn(&h->pdev->dev, "Command unabortable\n");
1655 break;
283b4a9b
SC		 1656 case CMD_IOACCEL_DISABLED:
1657 /* This only handles the direct pass-through case since RAID
1658 * offload is handled above. Just attempt a retry.
1659 */
1660 cmd->result = DID_SOFT_ERROR << 16;
1661 dev_warn(&h->pdev->dev,
1662 "cp %p had HP SSD Smart Path error\n", cp);
1663 break;
edd16368
SC		 1664 default:
1665 cmd->result = DID_ERROR << 16;
1666 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1667 cp, ei->CommandStatus);
1668 }
edd16368 1669 cmd_free(h, cp);
2cc5bfaf 1670 cmd->scsi_done(cmd);
edd16368
SC		 1671}
1672
edd16368
SC		 1673static void hpsa_pci_unmap(struct pci_dev *pdev,
1674 struct CommandList *c, int sg_used, int data_direction)
1675{
1676 int i;
1677 union u64bit addr64;
1678
1679 for (i = 0; i < sg_used; i++) {
1680 addr64.val32.lower = c->SG[i].Addr.lower;
1681 addr64.val32.upper = c->SG[i].Addr.upper;
1682 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1683 data_direction);
1684 }
1685}
1686
a2dac136 1687static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1688 struct CommandList *cp,
1689 unsigned char *buf,
1690 size_t buflen,
1691 int data_direction)
1692{
01a02ffc 1693 u64 addr64;
edd16368
SC		 1694
1695 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1696 cp->Header.SGList = 0;
1697 cp->Header.SGTotal = 0;
a2dac136 1698 return 0;
edd16368
SC		 1699 }
1700
01a02ffc 1701 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1702 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1703 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1704 cp->Header.SGList = 0;
1705 cp->Header.SGTotal = 0;
a2dac136 1706 return -1;
eceaae18 1707 }
edd16368 1708 cp->SG[0].Addr.lower =
01a02ffc 1709 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1710 cp->SG[0].Addr.upper =
01a02ffc 1711 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1712 cp->SG[0].Len = buflen;
e1d9cbfa 1713 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1714 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1715 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1716 return 0;
edd16368
SC		 1717}
1718
1719static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1720 struct CommandList *c)
1721{
1722 DECLARE_COMPLETION_ONSTACK(wait);
1723
1724 c->waiting = &wait;
1725 enqueue_cmd_and_start_io(h, c);
1726 wait_for_completion(&wait);
1727}
1728
a0c12413
SC		 1729static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1730 struct CommandList *c)
1731{
1732 unsigned long flags;
1733
1734 /* If controller lockup detected, fake a hardware error. */
1735 spin_lock_irqsave(&h->lock, flags);
1736 if (unlikely(h->lockup_detected)) {
1737 spin_unlock_irqrestore(&h->lock, flags);
1738 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1739 } else {
1740 spin_unlock_irqrestore(&h->lock, flags);
1741 hpsa_scsi_do_simple_cmd_core(h, c);
1742 }
1743}
1744
9c2fc160 1745#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1746static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1747 struct CommandList *c, int data_direction)
1748{
9c2fc160 1749 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1750
1751 do {
7630abd0 1752 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1753 hpsa_scsi_do_simple_cmd_core(h, c);
1754 retry_count++;
9c2fc160
SC		 1755 if (retry_count > 3) {
1756 msleep(backoff_time);
1757 if (backoff_time < 1000)
1758 backoff_time *= 2;
1759 }
852af20a 1760 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1761 check_for_busy(h, c)) &&
1762 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1763 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1764}
1765
1766static void hpsa_scsi_interpret_error(struct CommandList *cp)
1767{
1768 struct ErrorInfo *ei;
1769 struct device *d = &cp->h->pdev->dev;
1770
1771 ei = cp->err_info;
1772 switch (ei->CommandStatus) {
1773 case CMD_TARGET_STATUS:
1774 dev_warn(d, "cmd %p has completed with errors\n", cp);
1775 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1776 ei->ScsiStatus);
1777 if (ei->ScsiStatus == 0)
1778 dev_warn(d, "SCSI status is abnormally zero. "
1779 "(probably indicates selection timeout "
1780 "reported incorrectly due to a known "
1781 "firmware bug, circa July, 2001.)\n");
1782 break;
1783 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1784 dev_info(d, "UNDERRUN\n");
1785 break;
1786 case CMD_DATA_OVERRUN:
1787 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1788 break;
1789 case CMD_INVALID: {
1790 /* controller unfortunately reports SCSI passthru's
1791 * to non-existent targets as invalid commands.
1792 */
1793 dev_warn(d, "cp %p is reported invalid (probably means "
1794 "target device no longer present)\n", cp);
1795 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1796 print_cmd(cp); */
1797 }
1798 break;
1799 case CMD_PROTOCOL_ERR:
1800 dev_warn(d, "cp %p has protocol error \n", cp);
1801 break;
1802 case CMD_HARDWARE_ERR:
1803 /* cmd->result = DID_ERROR << 16; */
1804 dev_warn(d, "cp %p had hardware error\n", cp);
1805 break;
1806 case CMD_CONNECTION_LOST:
1807 dev_warn(d, "cp %p had connection lost\n", cp);
1808 break;
1809 case CMD_ABORTED:
1810 dev_warn(d, "cp %p was aborted\n", cp);
1811 break;
1812 case CMD_ABORT_FAILED:
1813 dev_warn(d, "cp %p reports abort failed\n", cp);
1814 break;
1815 case CMD_UNSOLICITED_ABORT:
1816 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1817 break;
1818 case CMD_TIMEOUT:
1819 dev_warn(d, "cp %p timed out\n", cp);
1820 break;
1d5e2ed0
SC		 1821 case CMD_UNABORTABLE:
1822 dev_warn(d, "Command unabortable\n");
1823 break;
edd16368
SC		 1824 default:
1825 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1826 ei->CommandStatus);
1827 }
1828}
1829
1830static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1831 unsigned char page, unsigned char *buf,
1832 unsigned char bufsize)
1833{
1834 int rc = IO_OK;
1835 struct CommandList *c;
1836 struct ErrorInfo *ei;
1837
1838 c = cmd_special_alloc(h);
1839
1840 if (c == NULL) { /* trouble... */
1841 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1842 return -ENOMEM;
edd16368
SC		 1843 }
1844
a2dac136
SC		 1845 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1846 page, scsi3addr, TYPE_CMD)) {
1847 rc = -1;
1848 goto out;
1849 }
edd16368
SC		 1850 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1851 ei = c->err_info;
1852 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1853 hpsa_scsi_interpret_error(c);
1854 rc = -1;
1855 }
a2dac136 1856out:
edd16368
SC		 1857 cmd_special_free(h, c);
1858 return rc;
1859}
1860
bf711ac6
ST		 1861static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
1862 u8 reset_type)
edd16368
SC		 1863{
1864 int rc = IO_OK;
1865 struct CommandList *c;
1866 struct ErrorInfo *ei;
1867
1868 c = cmd_special_alloc(h);
1869
1870 if (c == NULL) { /* trouble... */
1871 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1872 return -ENOMEM;
edd16368
SC		 1873 }
1874
a2dac136 1875 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 1876 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
1877 scsi3addr, TYPE_MSG);
1878 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 1879 hpsa_scsi_do_simple_cmd_core(h, c);
1880 /* no unmap needed here because no data xfer. */
1881
1882 ei = c->err_info;
1883 if (ei->CommandStatus != 0) {
1884 hpsa_scsi_interpret_error(c);
1885 rc = -1;
1886 }
1887 cmd_special_free(h, c);
1888 return rc;
1889}
1890
1891static void hpsa_get_raid_level(struct ctlr_info *h,
1892 unsigned char *scsi3addr, unsigned char *raid_level)
1893{
1894 int rc;
1895 unsigned char *buf;
1896
1897 *raid_level = RAID_UNKNOWN;
1898 buf = kzalloc(64, GFP_KERNEL);
1899 if (!buf)
1900 return;
1901 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1902 if (rc == 0)
1903 *raid_level = buf[8];
1904 if (*raid_level > RAID_UNKNOWN)
1905 *raid_level = RAID_UNKNOWN;
1906 kfree(buf);
1907 return;
1908}
1909
283b4a9b
SC		 1910#define HPSA_MAP_DEBUG
1911#ifdef HPSA_MAP_DEBUG
1912static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1913 struct raid_map_data *map_buff)
1914{
1915 struct raid_map_disk_data *dd = &map_buff->data[0];
1916 int map, row, col;
1917 u16 map_cnt, row_cnt, disks_per_row;
1918
1919 if (rc != 0)
1920 return;
1921
1922 dev_info(&h->pdev->dev, "structure_size = %u\n",
1923 le32_to_cpu(map_buff->structure_size));
1924 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1925 le32_to_cpu(map_buff->volume_blk_size));
1926 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1927 le64_to_cpu(map_buff->volume_blk_cnt));
1928 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1929 map_buff->phys_blk_shift);
1930 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1931 map_buff->parity_rotation_shift);
1932 dev_info(&h->pdev->dev, "strip_size = %u\n",
1933 le16_to_cpu(map_buff->strip_size));
1934 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1935 le64_to_cpu(map_buff->disk_starting_blk));
1936 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1937 le64_to_cpu(map_buff->disk_blk_cnt));
1938 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1939 le16_to_cpu(map_buff->data_disks_per_row));
1940 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1941 le16_to_cpu(map_buff->metadata_disks_per_row));
1942 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1943 le16_to_cpu(map_buff->row_cnt));
1944 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1945 le16_to_cpu(map_buff->layout_map_count));
1946
1947 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1948 for (map = 0; map < map_cnt; map++) {
1949 dev_info(&h->pdev->dev, "Map%u:\n", map);
1950 row_cnt = le16_to_cpu(map_buff->row_cnt);
1951 for (row = 0; row < row_cnt; row++) {
1952 dev_info(&h->pdev->dev, " Row%u:\n", row);
1953 disks_per_row =
1954 le16_to_cpu(map_buff->data_disks_per_row);
1955 for (col = 0; col < disks_per_row; col++, dd++)
1956 dev_info(&h->pdev->dev,
1957 " D%02u: h=0x%04x xor=%u,%u\n",
1958 col, dd->ioaccel_handle,
1959 dd->xor_mult[0], dd->xor_mult[1]);
1960 disks_per_row =
1961 le16_to_cpu(map_buff->metadata_disks_per_row);
1962 for (col = 0; col < disks_per_row; col++, dd++)
1963 dev_info(&h->pdev->dev,
1964 " M%02u: h=0x%04x xor=%u,%u\n",
1965 col, dd->ioaccel_handle,
1966 dd->xor_mult[0], dd->xor_mult[1]);
1967 }
1968 }
1969}
1970#else
1971static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
1972 __attribute__((unused)) int rc,
1973 __attribute__((unused)) struct raid_map_data *map_buff)
1974{
1975}
1976#endif
1977
1978static int hpsa_get_raid_map(struct ctlr_info *h,
1979 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1980{
1981 int rc = 0;
1982 struct CommandList *c;
1983 struct ErrorInfo *ei;
1984
1985 c = cmd_special_alloc(h);
1986 if (c == NULL) {
1987 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1988 return -ENOMEM;
1989 }
1990 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
1991 sizeof(this_device->raid_map), 0,
1992 scsi3addr, TYPE_CMD)) {
1993 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
1994 cmd_special_free(h, c);
1995 return -ENOMEM;
1996 }
1997 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1998 ei = c->err_info;
1999 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2000 hpsa_scsi_interpret_error(c);
2001 cmd_special_free(h, c);
2002 return -1;
2003 }
2004 cmd_special_free(h, c);
2005
2006 /* @todo in the future, dynamically allocate RAID map memory */
2007 if (le32_to_cpu(this_device->raid_map.structure_size) >
2008 sizeof(this_device->raid_map)) {
2009 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2010 rc = -1;
2011 }
2012 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2013 return rc;
2014}
2015
2016static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2017 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2018{
2019 int rc;
2020 unsigned char *buf;
2021 u8 ioaccel_status;
2022
2023 this_device->offload_config = 0;
2024 this_device->offload_enabled = 0;
2025
2026 buf = kzalloc(64, GFP_KERNEL);
2027 if (!buf)
2028 return;
2029 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2030 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
2031 if (rc != 0)
2032 goto out;
2033
2034#define IOACCEL_STATUS_BYTE 4
2035#define OFFLOAD_CONFIGURED_BIT 0x01
2036#define OFFLOAD_ENABLED_BIT 0x02
2037 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2038 this_device->offload_config =
2039 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2040 if (this_device->offload_config) {
2041 this_device->offload_enabled =
2042 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2043 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2044 this_device->offload_enabled = 0;
2045 }
2046out:
2047 kfree(buf);
2048 return;
2049}
2050
edd16368
SC		 2051/* Get the device id from inquiry page 0x83 */
2052static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2053 unsigned char *device_id, int buflen)
2054{
2055 int rc;
2056 unsigned char *buf;
2057
2058 if (buflen > 16)
2059 buflen = 16;
2060 buf = kzalloc(64, GFP_KERNEL);
2061 if (!buf)
2062 return -1;
2063 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
2064 if (rc == 0)
2065 memcpy(device_id, &buf[8], buflen);
2066 kfree(buf);
2067 return rc != 0;
2068}
2069
2070static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2071 struct ReportLUNdata *buf, int bufsize,
2072 int extended_response)
2073{
2074 int rc = IO_OK;
2075 struct CommandList *c;
2076 unsigned char scsi3addr[8];
2077 struct ErrorInfo *ei;
2078
2079 c = cmd_special_alloc(h);
2080 if (c == NULL) { /* trouble... */
2081 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2082 return -1;
2083 }
e89c0ae7
SC		 2084 /* address the controller */
2085 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2086 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2087 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2088 rc = -1;
2089 goto out;
2090 }
edd16368
SC		 2091 if (extended_response)
2092 c->Request.CDB[1] = extended_response;
2093 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2094 ei = c->err_info;
2095 if (ei->CommandStatus != 0 &&
2096 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2097 hpsa_scsi_interpret_error(c);
2098 rc = -1;
283b4a9b
SC		 2099 } else {
2100 if (buf->extended_response_flag != extended_response) {
2101 dev_err(&h->pdev->dev,
2102 "report luns requested format %u, got %u\n",
2103 extended_response,
2104 buf->extended_response_flag);
2105 rc = -1;
2106 }
edd16368 2107 }
a2dac136 2108out:
edd16368
SC		 2109 cmd_special_free(h, c);
2110 return rc;
2111}
2112
2113static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2114 struct ReportLUNdata *buf,
2115 int bufsize, int extended_response)
2116{
2117 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2118}
2119
2120static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2121 struct ReportLUNdata *buf, int bufsize)
2122{
2123 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2124}
2125
2126static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2127 int bus, int target, int lun)
2128{
2129 device->bus = bus;
2130 device->target = target;
2131 device->lun = lun;
2132}
2133
2134static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2135 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2136 unsigned char *is_OBDR_device)
edd16368 2137{
0b0e1d6c
SC		 2138
2139#define OBDR_SIG_OFFSET 43
2140#define OBDR_TAPE_SIG "$DR-10"
2141#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2142#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2143
ea6d3bc3 2144 unsigned char *inq_buff;
0b0e1d6c 2145 unsigned char *obdr_sig;
edd16368 2146
ea6d3bc3 2147 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2148 if (!inq_buff)
2149 goto bail_out;
2150
edd16368
SC		 2151 /* Do an inquiry to the device to see what it is. */
2152 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2153 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2154 /* Inquiry failed (msg printed already) */
2155 dev_err(&h->pdev->dev,
2156 "hpsa_update_device_info: inquiry failed\n");
2157 goto bail_out;
2158 }
2159
edd16368
SC		 2160 this_device->devtype = (inq_buff[0] & 0x1f);
2161 memcpy(this_device->scsi3addr, scsi3addr, 8);
2162 memcpy(this_device->vendor, &inq_buff[8],
2163 sizeof(this_device->vendor));
2164 memcpy(this_device->model, &inq_buff[16],
2165 sizeof(this_device->model));
edd16368
SC		 2166 memset(this_device->device_id, 0,
2167 sizeof(this_device->device_id));
2168 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2169 sizeof(this_device->device_id));
2170
2171 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2172 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2173 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2174 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2175 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2176 } else {
edd16368 2177 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2178 this_device->offload_config = 0;
2179 this_device->offload_enabled = 0;
2180 }
edd16368 2181
0b0e1d6c
SC		 2182 if (is_OBDR_device) {
2183 /* See if this is a One-Button-Disaster-Recovery device
2184 * by looking for "$DR-10" at offset 43 in inquiry data.
2185 */
2186 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2187 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2188 strncmp(obdr_sig, OBDR_TAPE_SIG,
2189 OBDR_SIG_LEN) == 0);
2190 }
2191
edd16368
SC		 2192 kfree(inq_buff);
2193 return 0;
2194
2195bail_out:
2196 kfree(inq_buff);
2197 return 1;
2198}
2199
4f4eb9f1 2200static unsigned char *ext_target_model[] = {
edd16368
SC		 2201 "MSA2012",
2202 "MSA2024",
2203 "MSA2312",
2204 "MSA2324",
fda38518 2205 "P2000 G3 SAS",
e06c8e5c 2206 "MSA 2040 SAS",
edd16368
SC		 2207 NULL,
2208};
2209
4f4eb9f1 2210static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2211{
2212 int i;
2213
4f4eb9f1
ST		 2214 for (i = 0; ext_target_model[i]; i++)
2215 if (strncmp(device->model, ext_target_model[i],
2216 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2217 return 1;
2218 return 0;
2219}
2220
2221/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2222 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2223 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2224 * Logical drive target and lun are assigned at this time, but
2225 * physical device lun and target assignment are deferred (assigned
2226 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2227 */
2228static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2229 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2230{
1f310bde
SC		 2231 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2232
2233 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2234 /* physical device, target and lun filled in later */
edd16368 2235 if (is_hba_lunid(lunaddrbytes))
1f310bde 2236 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2237 else
1f310bde
SC		 2238 /* defer target, lun assignment for physical devices */
2239 hpsa_set_bus_target_lun(device, 2, -1, -1);
2240 return;
2241 }
2242 /* It's a logical device */
4f4eb9f1
ST		 2243 if (is_ext_target(h, device)) {
2244 /* external target way, put logicals on bus 1
1f310bde
SC		 2245 * and match target/lun numbers box
2246 * reports, other smart array, bus 0, target 0, match lunid
2247 */
2248 hpsa_set_bus_target_lun(device,
2249 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2250 return;
edd16368 2251 }
1f310bde 2252 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2253}
2254
2255/*
2256 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2257 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2258 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2259 * it for some reason. *tmpdevice is the target we're adding,
2260 * this_device is a pointer into the current element of currentsd[]
2261 * that we're building up in update_scsi_devices(), below.
2262 * lunzerobits is a bitmap that tracks which targets already have a
2263 * lun 0 assigned.
2264 * Returns 1 if an enclosure was added, 0 if not.
2265 */
4f4eb9f1 2266static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2267 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2268 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2269 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2270{
2271 unsigned char scsi3addr[8];
2272
1f310bde 2273 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2274 return 0; /* There is already a lun 0 on this target. */
2275
2276 if (!is_logical_dev_addr_mode(lunaddrbytes))
2277 return 0; /* It's the logical targets that may lack lun 0. */
2278
4f4eb9f1
ST		 2279 if (!is_ext_target(h, tmpdevice))
2280 return 0; /* Only external target devices have this problem. */
edd16368 2281
1f310bde 2282 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2283 return 0;
2284
c4f8a299 2285 memset(scsi3addr, 0, 8);
1f310bde 2286 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2287 if (is_hba_lunid(scsi3addr))
2288 return 0; /* Don't add the RAID controller here. */
2289
339b2b14
SC		 2290 if (is_scsi_rev_5(h))
2291 return 0; /* p1210m doesn't need to do this. */
2292
4f4eb9f1 2293 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2294 dev_warn(&h->pdev->dev, "Maximum number of external "
2295 "target devices exceeded. Check your hardware "
edd16368
SC		 2296 "configuration.");
2297 return 0;
2298 }
2299
0b0e1d6c 2300 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2301 return 0;
4f4eb9f1 2302 (*n_ext_target_devs)++;
1f310bde
SC		 2303 hpsa_set_bus_target_lun(this_device,
2304 tmpdevice->bus, tmpdevice->target, 0);
2305 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2306 return 1;
2307}
2308
54b6e9e9
ST		 2309/*
2310 * Get address of physical disk used for an ioaccel2 mode command:
2311 * 1. Extract ioaccel2 handle from the command.
2312 * 2. Find a matching ioaccel2 handle from list of physical disks.
2313 * 3. Return:
2314 * 1 and set scsi3addr to address of matching physical
2315 * 0 if no matching physical disk was found.
2316 */
2317static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2318 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2319{
2320 struct ReportExtendedLUNdata *physicals = NULL;
2321 int responsesize = 24; /* size of physical extended response */
2322 int extended = 2; /* flag forces reporting 'other dev info'. */
2323 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2324 u32 nphysicals = 0; /* number of reported physical devs */
2325 int found = 0; /* found match (1) or not (0) */
2326 u32 find; /* handle we need to match */
2327 int i;
2328 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2329 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2330 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2331 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2332 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2333
2334 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2335 return 0; /* no match */
2336
2337 /* point to the ioaccel2 device handle */
2338 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2339 if (c2a == NULL)
2340 return 0; /* no match */
2341
2342 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2343 if (scmd == NULL)
2344 return 0; /* no match */
2345
2346 d = scmd->device->hostdata;
2347 if (d == NULL)
2348 return 0; /* no match */
2349
2350 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2351 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2352 find = c2a->scsi_nexus;
2353
2354 /* Get the list of physical devices */
2355 physicals = kzalloc(reportsize, GFP_KERNEL);
2356 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2357 reportsize, extended)) {
2358 dev_err(&h->pdev->dev,
2359 "Can't lookup %s device handle: report physical LUNs failed.\n",
2360 "HP SSD Smart Path");
2361 kfree(physicals);
2362 return 0;
2363 }
2364 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2365 responsesize;
2366
2367
2368 /* find ioaccel2 handle in list of physicals: */
2369 for (i = 0; i < nphysicals; i++) {
2370 /* handle is in bytes 28-31 of each lun */
2371 if (memcmp(&((struct ReportExtendedLUNdata *)
2372 physicals)->LUN[i][20], &find, 4) != 0) {
2373 continue; /* didn't match */
2374 }
2375 found = 1;
2376 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2377 physicals)->LUN[i][0], 8);
2378 break; /* found it */
2379 }
2380
2381 kfree(physicals);
2382 if (found)
2383 return 1;
2384 else
2385 return 0;
2386
2387}
edd16368
SC		 2388/*
2389 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2390 * logdev. The number of luns in physdev and logdev are returned in
2391 * *nphysicals and *nlogicals, respectively.
2392 * Returns 0 on success, -1 otherwise.
2393 */
2394static int hpsa_gather_lun_info(struct ctlr_info *h,
2395 int reportlunsize,
283b4a9b 2396 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2397 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2398{
283b4a9b
SC		 2399 int physical_entry_size = 8;
2400
2401 *physical_mode = 0;
2402
2403 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2404 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2405 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2406 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2407 physical_entry_size = 24;
2408 }
a93aa1fe 2409 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2410 *physical_mode)) {
edd16368
SC		 2411 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2412 return -1;
2413 }
283b4a9b
SC		 2414 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2415 physical_entry_size;
edd16368
SC		 2416 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2417 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2418 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2419 *nphysicals - HPSA_MAX_PHYS_LUN);
2420 *nphysicals = HPSA_MAX_PHYS_LUN;
2421 }
2422 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2423 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2424 return -1;
2425 }
6df1e954 2426 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2427 /* Reject Logicals in excess of our max capability. */
2428 if (*nlogicals > HPSA_MAX_LUN) {
2429 dev_warn(&h->pdev->dev,
2430 "maximum logical LUNs (%d) exceeded. "
2431 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2432 *nlogicals - HPSA_MAX_LUN);
2433 *nlogicals = HPSA_MAX_LUN;
2434 }
2435 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2436 dev_warn(&h->pdev->dev,
2437 "maximum logical + physical LUNs (%d) exceeded. "
2438 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2439 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2440 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2441 }
2442 return 0;
2443}
2444
339b2b14 2445u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2446 int nphysicals, int nlogicals,
2447 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2448 struct ReportLUNdata *logdev_list)
2449{
2450 /* Helper function, figure out where the LUN ID info is coming from
2451 * given index i, lists of physical and logical devices, where in
2452 * the list the raid controller is supposed to appear (first or last)
2453 */
2454
2455 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2456 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2457
2458 if (i == raid_ctlr_position)
2459 return RAID_CTLR_LUNID;
2460
2461 if (i < logicals_start)
2462 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2463
2464 if (i < last_device)
2465 return &logdev_list->LUN[i - nphysicals -
2466 (raid_ctlr_position == 0)][0];
2467 BUG();
2468 return NULL;
2469}
2470
edd16368
SC		 2471static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2472{
2473 /* the idea here is we could get notified
2474 * that some devices have changed, so we do a report
2475 * physical luns and report logical luns cmd, and adjust
2476 * our list of devices accordingly.
2477 *
2478 * The scsi3addr's of devices won't change so long as the
2479 * adapter is not reset. That means we can rescan and
2480 * tell which devices we already know about, vs. new
2481 * devices, vs. disappearing devices.
2482 */
a93aa1fe 2483 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2484 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2485 u32 nphysicals = 0;
2486 u32 nlogicals = 0;
283b4a9b 2487 int physical_mode = 0;
01a02ffc 2488 u32 ndev_allocated = 0;
edd16368
SC		 2489 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2490 int ncurrent = 0;
283b4a9b 2491 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2492 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2493 int raid_ctlr_position;
aca4a520 2494 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2495
cfe5badc 2496 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2497 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2498 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2499 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2500
0b0e1d6c 2501 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2502 dev_err(&h->pdev->dev, "out of memory\n");
2503 goto out;
2504 }
2505 memset(lunzerobits, 0, sizeof(lunzerobits));
2506
a93aa1fe
MG		 2507 if (hpsa_gather_lun_info(h, reportlunsize,
2508 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2509 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2510 goto out;
2511
aca4a520
ST		 2512 /* We might see up to the maximum number of logical and physical disks
2513 * plus external target devices, and a device for the local RAID
2514 * controller.
edd16368 2515 */
aca4a520 2516 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2517
2518 /* Allocate the per device structures */
2519 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2520 if (i >= HPSA_MAX_DEVICES) {
2521 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2522 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2523 ndevs_to_allocate - HPSA_MAX_DEVICES);
2524 break;
2525 }
2526
edd16368
SC		 2527 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2528 if (!currentsd[i]) {
2529 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2530 __FILE__, __LINE__);
2531 goto out;
2532 }
2533 ndev_allocated++;
2534 }
2535
339b2b14
SC		 2536 if (unlikely(is_scsi_rev_5(h)))
2537 raid_ctlr_position = 0;
2538 else
2539 raid_ctlr_position = nphysicals + nlogicals;
2540
edd16368 2541 /* adjust our table of devices */
4f4eb9f1 2542 n_ext_target_devs = 0;
edd16368 2543 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2544 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2545
2546 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2547 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2548 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2549 /* skip masked physical devices. */
339b2b14
SC		 2550 if (lunaddrbytes[3] & 0xC0 &&
2551 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2552 continue;
2553
2554 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2555 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2556 &is_OBDR))
edd16368 2557 continue; /* skip it if we can't talk to it. */
1f310bde 2558 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2559 this_device = currentsd[ncurrent];
2560
2561 /*
4f4eb9f1 2562 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2563 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2564 * is nonetheless an enclosure device there. We have to
2565 * present that otherwise linux won't find anything if
2566 * there is no lun 0.
2567 */
4f4eb9f1 2568 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2569 lunaddrbytes, lunzerobits,
4f4eb9f1 2570 &n_ext_target_devs)) {
edd16368
SC		 2571 ncurrent++;
2572 this_device = currentsd[ncurrent];
2573 }
2574
2575 *this_device = *tmpdevice;
edd16368
SC		 2576
2577 switch (this_device->devtype) {
0b0e1d6c 2578 case TYPE_ROM:
edd16368
SC		 2579 /* We don't *really* support actual CD-ROM devices,
2580 * just "One Button Disaster Recovery" tape drive
2581 * which temporarily pretends to be a CD-ROM drive.
2582 * So we check that the device is really an OBDR tape
2583 * device by checking for "$DR-10" in bytes 43-48 of
2584 * the inquiry data.
2585 */
0b0e1d6c
SC		 2586 if (is_OBDR)
2587 ncurrent++;
edd16368
SC		 2588 break;
2589 case TYPE_DISK:
283b4a9b
SC		 2590 if (i >= nphysicals) {
2591 ncurrent++;
edd16368 2592 break;
283b4a9b
SC		 2593 }
2594 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2595 memcpy(&this_device->ioaccel_handle,
2596 &lunaddrbytes[20],
2597 sizeof(this_device->ioaccel_handle));
2598 ncurrent++;
2599 }
edd16368
SC		 2600 break;
2601 case TYPE_TAPE:
2602 case TYPE_MEDIUM_CHANGER:
2603 ncurrent++;
2604 break;
2605 case TYPE_RAID:
2606 /* Only present the Smartarray HBA as a RAID controller.
2607 * If it's a RAID controller other than the HBA itself
2608 * (an external RAID controller, MSA500 or similar)
2609 * don't present it.
2610 */
2611 if (!is_hba_lunid(lunaddrbytes))
2612 break;
2613 ncurrent++;
2614 break;
2615 default:
2616 break;
2617 }
cfe5badc 2618 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2619 break;
2620 }
2621 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2622out:
2623 kfree(tmpdevice);
2624 for (i = 0; i < ndev_allocated; i++)
2625 kfree(currentsd[i]);
2626 kfree(currentsd);
edd16368
SC		 2627 kfree(physdev_list);
2628 kfree(logdev_list);
edd16368
SC		 2629}
2630
2631/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2632 * dma mapping and fills in the scatter gather entries of the
2633 * hpsa command, cp.
2634 */
33a2ffce 2635static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2636 struct CommandList *cp,
2637 struct scsi_cmnd *cmd)
2638{
2639 unsigned int len;
2640 struct scatterlist *sg;
01a02ffc 2641 u64 addr64;
33a2ffce
SC		 2642 int use_sg, i, sg_index, chained;
2643 struct SGDescriptor *curr_sg;
edd16368 2644
33a2ffce 2645 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2646
2647 use_sg = scsi_dma_map(cmd);
2648 if (use_sg < 0)
2649 return use_sg;
2650
2651 if (!use_sg)
2652 goto sglist_finished;
2653
33a2ffce
SC		 2654 curr_sg = cp->SG;
2655 chained = 0;
2656 sg_index = 0;
edd16368 2657 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2658 if (i == h->max_cmd_sg_entries - 1 &&
2659 use_sg > h->max_cmd_sg_entries) {
2660 chained = 1;
2661 curr_sg = h->cmd_sg_list[cp->cmdindex];
2662 sg_index = 0;
2663 }
01a02ffc 2664 addr64 = (u64) sg_dma_address(sg);
edd16368 2665 len = sg_dma_len(sg);
33a2ffce
SC		 2666 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2667 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2668 curr_sg->Len = len;
e1d9cbfa 2669 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2670 curr_sg++;
2671 }
2672
2673 if (use_sg + chained > h->maxSG)
2674 h->maxSG = use_sg + chained;
2675
2676 if (chained) {
2677 cp->Header.SGList = h->max_cmd_sg_entries;
2678 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2679 if (hpsa_map_sg_chain_block(h, cp)) {
2680 scsi_dma_unmap(cmd);
2681 return -1;
2682 }
33a2ffce 2683 return 0;
edd16368
SC		 2684 }
2685
2686sglist_finished:
2687
01a02ffc
SC		 2688 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2689 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2690 return 0;
2691}
2692
283b4a9b
SC		 2693#define IO_ACCEL_INELIGIBLE (1)
2694static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2695{
2696 int is_write = 0;
2697 u32 block;
2698 u32 block_cnt;
2699
2700 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2701 switch (cdb[0]) {
2702 case WRITE_6:
2703 case WRITE_12:
2704 is_write = 1;
2705 case READ_6:
2706 case READ_12:
2707 if (*cdb_len == 6) {
2708 block = (((u32) cdb[2]) << 8) | cdb[3];
2709 block_cnt = cdb[4];
2710 } else {
2711 BUG_ON(*cdb_len != 12);
2712 block = (((u32) cdb[2]) << 24) |
2713 (((u32) cdb[3]) << 16) |
2714 (((u32) cdb[4]) << 8) |
2715 cdb[5];
2716 block_cnt =
2717 (((u32) cdb[6]) << 24) |
2718 (((u32) cdb[7]) << 16) |
2719 (((u32) cdb[8]) << 8) |
2720 cdb[9];
2721 }
2722 if (block_cnt > 0xffff)
2723 return IO_ACCEL_INELIGIBLE;
2724
2725 cdb[0] = is_write ? WRITE_10 : READ_10;
2726 cdb[1] = 0;
2727 cdb[2] = (u8) (block >> 24);
2728 cdb[3] = (u8) (block >> 16);
2729 cdb[4] = (u8) (block >> 8);
2730 cdb[5] = (u8) (block);
2731 cdb[6] = 0;
2732 cdb[7] = (u8) (block_cnt >> 8);
2733 cdb[8] = (u8) (block_cnt);
2734 cdb[9] = 0;
2735 *cdb_len = 10;
2736 break;
2737 }
2738 return 0;
2739}
2740
c349775e 2741static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2742 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2743 u8 *scsi3addr)
e1f7de0c
MG		 2744{
2745 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2746 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2747 unsigned int len;
2748 unsigned int total_len = 0;
2749 struct scatterlist *sg;
2750 u64 addr64;
2751 int use_sg, i;
2752 struct SGDescriptor *curr_sg;
2753 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2754
283b4a9b
SC		 2755 /* TODO: implement chaining support */
2756 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2757 return IO_ACCEL_INELIGIBLE;
2758
e1f7de0c
MG		 2759 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2760
283b4a9b
SC		 2761 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2762 return IO_ACCEL_INELIGIBLE;
2763
e1f7de0c
MG		 2764 c->cmd_type = CMD_IOACCEL1;
2765
2766 /* Adjust the DMA address to point to the accelerated command buffer */
2767 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2768 (c->cmdindex * sizeof(*cp));
2769 BUG_ON(c->busaddr & 0x0000007F);
2770
2771 use_sg = scsi_dma_map(cmd);
2772 if (use_sg < 0)
2773 return use_sg;
2774
2775 if (use_sg) {
2776 curr_sg = cp->SG;
2777 scsi_for_each_sg(cmd, sg, use_sg, i) {
2778 addr64 = (u64) sg_dma_address(sg);
2779 len = sg_dma_len(sg);
2780 total_len += len;
2781 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2782 curr_sg->Addr.upper =
2783 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2784 curr_sg->Len = len;
2785
2786 if (i == (scsi_sg_count(cmd) - 1))
2787 curr_sg->Ext = HPSA_SG_LAST;
2788 else
2789 curr_sg->Ext = 0; /* we are not chaining */
2790 curr_sg++;
2791 }
2792
2793 switch (cmd->sc_data_direction) {
2794 case DMA_TO_DEVICE:
2795 control |= IOACCEL1_CONTROL_DATA_OUT;
2796 break;
2797 case DMA_FROM_DEVICE:
2798 control |= IOACCEL1_CONTROL_DATA_IN;
2799 break;
2800 case DMA_NONE:
2801 control |= IOACCEL1_CONTROL_NODATAXFER;
2802 break;
2803 default:
2804 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2805 cmd->sc_data_direction);
2806 BUG();
2807 break;
2808 }
2809 } else {
2810 control |= IOACCEL1_CONTROL_NODATAXFER;
2811 }
2812
c349775e 2813 c->Header.SGList = use_sg;
e1f7de0c 2814 /* Fill out the command structure to submit */
283b4a9b 2815 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2816 cp->transfer_len = total_len;
2817 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2818 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2819 cp->control = control;
283b4a9b
SC		 2820 memcpy(cp->CDB, cdb, cdb_len);
2821 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2822 /* Tag was already set at init time. */
283b4a9b 2823 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2824 return 0;
2825}
edd16368 2826
283b4a9b
SC		 2827/*
2828 * Queue a command directly to a device behind the controller using the
2829 * I/O accelerator path.
2830 */
2831static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2832 struct CommandList *c)
2833{
2834 struct scsi_cmnd *cmd = c->scsi_cmd;
2835 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2836
2837 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2838 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2839}
2840
c349775e
ST		 2841static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
2842 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2843 u8 *scsi3addr)
2844{
2845 struct scsi_cmnd *cmd = c->scsi_cmd;
2846 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
2847 struct ioaccel2_sg_element *curr_sg;
2848 int use_sg, i;
2849 struct scatterlist *sg;
2850 u64 addr64;
2851 u32 len;
2852 u32 total_len = 0;
2853
2854 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2855 return IO_ACCEL_INELIGIBLE;
2856
2857 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2858 return IO_ACCEL_INELIGIBLE;
2859 c->cmd_type = CMD_IOACCEL2;
2860 /* Adjust the DMA address to point to the accelerated command buffer */
2861 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
2862 (c->cmdindex * sizeof(*cp));
2863 BUG_ON(c->busaddr & 0x0000007F);
2864
2865 memset(cp, 0, sizeof(*cp));
2866 cp->IU_type = IOACCEL2_IU_TYPE;
2867
2868 use_sg = scsi_dma_map(cmd);
2869 if (use_sg < 0)
2870 return use_sg;
2871
2872 if (use_sg) {
2873 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
2874 curr_sg = cp->sg;
2875 scsi_for_each_sg(cmd, sg, use_sg, i) {
2876 addr64 = (u64) sg_dma_address(sg);
2877 len = sg_dma_len(sg);
2878 total_len += len;
2879 curr_sg->address = cpu_to_le64(addr64);
2880 curr_sg->length = cpu_to_le32(len);
2881 curr_sg->reserved[0] = 0;
2882 curr_sg->reserved[1] = 0;
2883 curr_sg->reserved[2] = 0;
2884 curr_sg->chain_indicator = 0;
2885 curr_sg++;
2886 }
2887
2888 switch (cmd->sc_data_direction) {
2889 case DMA_TO_DEVICE:
2890 cp->direction = IOACCEL2_DIR_DATA_OUT;
2891 break;
2892 case DMA_FROM_DEVICE:
2893 cp->direction = IOACCEL2_DIR_DATA_IN;
2894 break;
2895 case DMA_NONE:
2896 cp->direction = IOACCEL2_DIR_NO_DATA;
2897 break;
2898 default:
2899 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2900 cmd->sc_data_direction);
2901 BUG();
2902 break;
2903 }
2904 } else {
2905 cp->direction = IOACCEL2_DIR_NO_DATA;
2906 }
2907 cp->scsi_nexus = ioaccel_handle;
2908 cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
2909 DIRECT_LOOKUP_BIT;
2910 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
2911 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
2912 cp->cmd_priority_task_attr = 0;
2913
2914 /* fill in sg elements */
2915 cp->sg_count = (u8) use_sg;
2916
2917 cp->data_len = cpu_to_le32(total_len);
2918 cp->err_ptr = cpu_to_le64(c->busaddr +
2919 offsetof(struct io_accel2_cmd, error_data));
2920 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
2921
2922 enqueue_cmd_and_start_io(h, c);
2923 return 0;
2924}
2925
2926/*
2927 * Queue a command to the correct I/O accelerator path.
2928 */
2929static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
2930 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2931 u8 *scsi3addr)
2932{
2933 if (h->transMethod & CFGTBL_Trans_io_accel1)
2934 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
2935 cdb, cdb_len, scsi3addr);
2936 else
2937 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
2938 cdb, cdb_len, scsi3addr);
2939}
2940
283b4a9b
SC		 2941/*
2942 * Attempt to perform offload RAID mapping for a logical volume I/O.
2943 */
2944static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
2945 struct CommandList *c)
2946{
2947 struct scsi_cmnd *cmd = c->scsi_cmd;
2948 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2949 struct raid_map_data *map = &dev->raid_map;
2950 struct raid_map_disk_data *dd = &map->data[0];
2951 int is_write = 0;
2952 u32 map_index;
2953 u64 first_block, last_block;
2954 u32 block_cnt;
2955 u32 blocks_per_row;
2956 u64 first_row, last_row;
2957 u32 first_row_offset, last_row_offset;
2958 u32 first_column, last_column;
2959 u32 map_row;
2960 u32 disk_handle;
2961 u64 disk_block;
2962 u32 disk_block_cnt;
2963 u8 cdb[16];
2964 u8 cdb_len;
2965#if BITS_PER_LONG == 32
2966 u64 tmpdiv;
2967#endif
2968
2969 BUG_ON(!(dev->offload_config && dev->offload_enabled));
2970
2971 /* check for valid opcode, get LBA and block count */
2972 switch (cmd->cmnd[0]) {
2973 case WRITE_6:
2974 is_write = 1;
2975 case READ_6:
2976 first_block =
2977 (((u64) cmd->cmnd[2]) << 8) |
2978 cmd->cmnd[3];
2979 block_cnt = cmd->cmnd[4];
2980 break;
2981 case WRITE_10:
2982 is_write = 1;
2983 case READ_10:
2984 first_block =
2985 (((u64) cmd->cmnd[2]) << 24) |
2986 (((u64) cmd->cmnd[3]) << 16) |
2987 (((u64) cmd->cmnd[4]) << 8) |
2988 cmd->cmnd[5];
2989 block_cnt =
2990 (((u32) cmd->cmnd[7]) << 8) |
2991 cmd->cmnd[8];
2992 break;
2993 case WRITE_12:
2994 is_write = 1;
2995 case READ_12:
2996 first_block =
2997 (((u64) cmd->cmnd[2]) << 24) |
2998 (((u64) cmd->cmnd[3]) << 16) |
2999 (((u64) cmd->cmnd[4]) << 8) |
3000 cmd->cmnd[5];
3001 block_cnt =
3002 (((u32) cmd->cmnd[6]) << 24) |
3003 (((u32) cmd->cmnd[7]) << 16) |
3004 (((u32) cmd->cmnd[8]) << 8) |
3005 cmd->cmnd[9];
3006 break;
3007 case WRITE_16:
3008 is_write = 1;
3009 case READ_16:
3010 first_block =
3011 (((u64) cmd->cmnd[2]) << 56) |
3012 (((u64) cmd->cmnd[3]) << 48) |
3013 (((u64) cmd->cmnd[4]) << 40) |
3014 (((u64) cmd->cmnd[5]) << 32) |
3015 (((u64) cmd->cmnd[6]) << 24) |
3016 (((u64) cmd->cmnd[7]) << 16) |
3017 (((u64) cmd->cmnd[8]) << 8) |
3018 cmd->cmnd[9];
3019 block_cnt =
3020 (((u32) cmd->cmnd[10]) << 24) |
3021 (((u32) cmd->cmnd[11]) << 16) |
3022 (((u32) cmd->cmnd[12]) << 8) |
3023 cmd->cmnd[13];
3024 break;
3025 default:
3026 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3027 }
3028 BUG_ON(block_cnt == 0);
3029 last_block = first_block + block_cnt - 1;
3030
3031 /* check for write to non-RAID-0 */
3032 if (is_write && dev->raid_level != 0)
3033 return IO_ACCEL_INELIGIBLE;
3034
3035 /* check for invalid block or wraparound */
3036 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3037 return IO_ACCEL_INELIGIBLE;
3038
3039 /* calculate stripe information for the request */
3040 blocks_per_row = map->data_disks_per_row * map->strip_size;
3041#if BITS_PER_LONG == 32
3042 tmpdiv = first_block;
3043 (void) do_div(tmpdiv, blocks_per_row);
3044 first_row = tmpdiv;
3045 tmpdiv = last_block;
3046 (void) do_div(tmpdiv, blocks_per_row);
3047 last_row = tmpdiv;
3048 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3049 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3050 tmpdiv = first_row_offset;
3051 (void) do_div(tmpdiv, map->strip_size);
3052 first_column = tmpdiv;
3053 tmpdiv = last_row_offset;
3054 (void) do_div(tmpdiv, map->strip_size);
3055 last_column = tmpdiv;
3056#else
3057 first_row = first_block / blocks_per_row;
3058 last_row = last_block / blocks_per_row;
3059 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3060 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3061 first_column = first_row_offset / map->strip_size;
3062 last_column = last_row_offset / map->strip_size;
3063#endif
3064
3065 /* if this isn't a single row/column then give to the controller */
3066 if ((first_row != last_row) || (first_column != last_column))
3067 return IO_ACCEL_INELIGIBLE;
3068
3069 /* proceeding with driver mapping */
3070 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3071 map->row_cnt;
3072 map_index = (map_row * (map->data_disks_per_row +
3073 map->metadata_disks_per_row)) + first_column;
3074 if (dev->raid_level == 2) {
3075 /* simple round-robin balancing of RAID 1+0 reads across
3076 * primary and mirror members. this is appropriate for SSD
3077 * but not optimal for HDD.
3078 */
3079 if (dev->offload_to_mirror)
3080 map_index += map->data_disks_per_row;
3081 dev->offload_to_mirror = !dev->offload_to_mirror;
3082 }
3083 disk_handle = dd[map_index].ioaccel_handle;
3084 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3085 (first_row_offset - (first_column * map->strip_size));
3086 disk_block_cnt = block_cnt;
3087
3088 /* handle differing logical/physical block sizes */
3089 if (map->phys_blk_shift) {
3090 disk_block <<= map->phys_blk_shift;
3091 disk_block_cnt <<= map->phys_blk_shift;
3092 }
3093 BUG_ON(disk_block_cnt > 0xffff);
3094
3095 /* build the new CDB for the physical disk I/O */
3096 if (disk_block > 0xffffffff) {
3097 cdb[0] = is_write ? WRITE_16 : READ_16;
3098 cdb[1] = 0;
3099 cdb[2] = (u8) (disk_block >> 56);
3100 cdb[3] = (u8) (disk_block >> 48);
3101 cdb[4] = (u8) (disk_block >> 40);
3102 cdb[5] = (u8) (disk_block >> 32);
3103 cdb[6] = (u8) (disk_block >> 24);
3104 cdb[7] = (u8) (disk_block >> 16);
3105 cdb[8] = (u8) (disk_block >> 8);
3106 cdb[9] = (u8) (disk_block);
3107 cdb[10] = (u8) (disk_block_cnt >> 24);
3108 cdb[11] = (u8) (disk_block_cnt >> 16);
3109 cdb[12] = (u8) (disk_block_cnt >> 8);
3110 cdb[13] = (u8) (disk_block_cnt);
3111 cdb[14] = 0;
3112 cdb[15] = 0;
3113 cdb_len = 16;
3114 } else {
3115 cdb[0] = is_write ? WRITE_10 : READ_10;
3116 cdb[1] = 0;
3117 cdb[2] = (u8) (disk_block >> 24);
3118 cdb[3] = (u8) (disk_block >> 16);
3119 cdb[4] = (u8) (disk_block >> 8);
3120 cdb[5] = (u8) (disk_block);
3121 cdb[6] = 0;
3122 cdb[7] = (u8) (disk_block_cnt >> 8);
3123 cdb[8] = (u8) (disk_block_cnt);
3124 cdb[9] = 0;
3125 cdb_len = 10;
3126 }
3127 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3128 dev->scsi3addr);
3129}
3130
f281233d 3131static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3132 void (*done)(struct scsi_cmnd *))
3133{
3134 struct ctlr_info *h;
3135 struct hpsa_scsi_dev_t *dev;
3136 unsigned char scsi3addr[8];
3137 struct CommandList *c;
3138 unsigned long flags;
283b4a9b 3139 int rc = 0;
edd16368
SC		 3140
3141 /* Get the ptr to our adapter structure out of cmd->host. */
3142 h = sdev_to_hba(cmd->device);
3143 dev = cmd->device->hostdata;
3144 if (!dev) {
3145 cmd->result = DID_NO_CONNECT << 16;
3146 done(cmd);
3147 return 0;
3148 }
3149 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3150
edd16368 3151 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3152 if (unlikely(h->lockup_detected)) {
3153 spin_unlock_irqrestore(&h->lock, flags);
3154 cmd->result = DID_ERROR << 16;
3155 done(cmd);
3156 return 0;
3157 }
edd16368 3158 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3159 c = cmd_alloc(h);
edd16368
SC		 3160 if (c == NULL) { /* trouble... */
3161 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3162 return SCSI_MLQUEUE_HOST_BUSY;
3163 }
3164
3165 /* Fill in the command list header */
3166
3167 cmd->scsi_done = done; /* save this for use by completion code */
3168
3169 /* save c in case we have to abort it */
3170 cmd->host_scribble = (unsigned char *) c;
3171
3172 c->cmd_type = CMD_SCSI;
3173 c->scsi_cmd = cmd;
e1f7de0c 3174
283b4a9b
SC		 3175 /* Call alternate submit routine for I/O accelerated commands.
3176 * Retries always go down the normal I/O path.
3177 */
3178 if (likely(cmd->retries == 0 &&
3179 cmd->request->cmd_type == REQ_TYPE_FS)) {
3180 if (dev->offload_enabled) {
3181 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3182 if (rc == 0)
3183 return 0; /* Sent on ioaccel path */
3184 if (rc < 0) { /* scsi_dma_map failed. */
3185 cmd_free(h, c);
3186 return SCSI_MLQUEUE_HOST_BUSY;
3187 }
3188 } else if (dev->ioaccel_handle) {
3189 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3190 if (rc == 0)
3191 return 0; /* Sent on direct map path */
3192 if (rc < 0) { /* scsi_dma_map failed. */
3193 cmd_free(h, c);
3194 return SCSI_MLQUEUE_HOST_BUSY;
3195 }
3196 }
3197 }
e1f7de0c 3198
edd16368
SC		 3199 c->Header.ReplyQueue = 0; /* unused in simple mode */
3200 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3201 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3202 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3203
3204 /* Fill in the request block... */
3205
3206 c->Request.Timeout = 0;
3207 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3208 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3209 c->Request.CDBLen = cmd->cmd_len;
3210 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3211 c->Request.Type.Type = TYPE_CMD;
3212 c->Request.Type.Attribute = ATTR_SIMPLE;
3213 switch (cmd->sc_data_direction) {
3214 case DMA_TO_DEVICE:
3215 c->Request.Type.Direction = XFER_WRITE;
3216 break;
3217 case DMA_FROM_DEVICE:
3218 c->Request.Type.Direction = XFER_READ;
3219 break;
3220 case DMA_NONE:
3221 c->Request.Type.Direction = XFER_NONE;
3222 break;
3223 case DMA_BIDIRECTIONAL:
3224 /* This can happen if a buggy application does a scsi passthru
3225 * and sets both inlen and outlen to non-zero. ( see
3226 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3227 */
3228
3229 c->Request.Type.Direction = XFER_RSVD;
3230 /* This is technically wrong, and hpsa controllers should
3231 * reject it with CMD_INVALID, which is the most correct
3232 * response, but non-fibre backends appear to let it
3233 * slide by, and give the same results as if this field
3234 * were set correctly. Either way is acceptable for
3235 * our purposes here.
3236 */
3237
3238 break;
3239
3240 default:
3241 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3242 cmd->sc_data_direction);
3243 BUG();
3244 break;
3245 }
3246
33a2ffce 3247 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3248 cmd_free(h, c);
3249 return SCSI_MLQUEUE_HOST_BUSY;
3250 }
3251 enqueue_cmd_and_start_io(h, c);
3252 /* the cmd'll come back via intr handler in complete_scsi_command() */
3253 return 0;
3254}
3255
f281233d
JG		 3256static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3257
5f389360
SC		 3258static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3259{
3260 unsigned long flags;
3261
3262 /*
3263 * Don't let rescans be initiated on a controller known
3264 * to be locked up. If the controller locks up *during*
3265 * a rescan, that thread is probably hosed, but at least
3266 * we can prevent new rescan threads from piling up on a
3267 * locked up controller.
3268 */
3269 spin_lock_irqsave(&h->lock, flags);
3270 if (unlikely(h->lockup_detected)) {
3271 spin_unlock_irqrestore(&h->lock, flags);
3272 spin_lock_irqsave(&h->scan_lock, flags);
3273 h->scan_finished = 1;
3274 wake_up_all(&h->scan_wait_queue);
3275 spin_unlock_irqrestore(&h->scan_lock, flags);
3276 return 1;
3277 }
3278 spin_unlock_irqrestore(&h->lock, flags);
3279 return 0;
3280}
3281
a08a8471
SC		 3282static void hpsa_scan_start(struct Scsi_Host *sh)
3283{
3284 struct ctlr_info *h = shost_to_hba(sh);
3285 unsigned long flags;
3286
5f389360
SC		 3287 if (do_not_scan_if_controller_locked_up(h))
3288 return;
3289
a08a8471
SC		 3290 /* wait until any scan already in progress is finished. */
3291 while (1) {
3292 spin_lock_irqsave(&h->scan_lock, flags);
3293 if (h->scan_finished)
3294 break;
3295 spin_unlock_irqrestore(&h->scan_lock, flags);
3296 wait_event(h->scan_wait_queue, h->scan_finished);
3297 /* Note: We don't need to worry about a race between this
3298 * thread and driver unload because the midlayer will
3299 * have incremented the reference count, so unload won't
3300 * happen if we're in here.
3301 */
3302 }
3303 h->scan_finished = 0; /* mark scan as in progress */
3304 spin_unlock_irqrestore(&h->scan_lock, flags);
3305
5f389360
SC		 3306 if (do_not_scan_if_controller_locked_up(h))
3307 return;
3308
a08a8471
SC		 3309 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3310
3311 spin_lock_irqsave(&h->scan_lock, flags);
3312 h->scan_finished = 1; /* mark scan as finished. */
3313 wake_up_all(&h->scan_wait_queue);
3314 spin_unlock_irqrestore(&h->scan_lock, flags);
3315}
3316
3317static int hpsa_scan_finished(struct Scsi_Host *sh,
3318 unsigned long elapsed_time)
3319{
3320 struct ctlr_info *h = shost_to_hba(sh);
3321 unsigned long flags;
3322 int finished;
3323
3324 spin_lock_irqsave(&h->scan_lock, flags);
3325 finished = h->scan_finished;
3326 spin_unlock_irqrestore(&h->scan_lock, flags);
3327 return finished;
3328}
3329
667e23d4
SC		 3330static int hpsa_change_queue_depth(struct scsi_device *sdev,
3331 int qdepth, int reason)
3332{
3333 struct ctlr_info *h = sdev_to_hba(sdev);
3334
3335 if (reason != SCSI_QDEPTH_DEFAULT)
3336 return -ENOTSUPP;
3337
3338 if (qdepth < 1)
3339 qdepth = 1;
3340 else
3341 if (qdepth > h->nr_cmds)
3342 qdepth = h->nr_cmds;
3343 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3344 return sdev->queue_depth;
3345}
3346
edd16368
SC		 3347static void hpsa_unregister_scsi(struct ctlr_info *h)
3348{
3349 /* we are being forcibly unloaded, and may not refuse. */
3350 scsi_remove_host(h->scsi_host);
3351 scsi_host_put(h->scsi_host);
3352 h->scsi_host = NULL;
3353}
3354
3355static int hpsa_register_scsi(struct ctlr_info *h)
3356{
b705690d
SC		 3357 struct Scsi_Host *sh;
3358 int error;
edd16368 3359
b705690d
SC		 3360 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3361 if (sh == NULL)
3362 goto fail;
3363
3364 sh->io_port = 0;
3365 sh->n_io_port = 0;
3366 sh->this_id = -1;
3367 sh->max_channel = 3;
3368 sh->max_cmd_len = MAX_COMMAND_SIZE;
3369 sh->max_lun = HPSA_MAX_LUN;
3370 sh->max_id = HPSA_MAX_LUN;
3371 sh->can_queue = h->nr_cmds;
3372 sh->cmd_per_lun = h->nr_cmds;
3373 sh->sg_tablesize = h->maxsgentries;
3374 h->scsi_host = sh;
3375 sh->hostdata[0] = (unsigned long) h;
3376 sh->irq = h->intr[h->intr_mode];
3377 sh->unique_id = sh->irq;
3378 error = scsi_add_host(sh, &h->pdev->dev);
3379 if (error)
3380 goto fail_host_put;
3381 scsi_scan_host(sh);
3382 return 0;
3383
3384 fail_host_put:
3385 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3386 " failed for controller %d\n", __func__, h->ctlr);
3387 scsi_host_put(sh);
3388 return error;
3389 fail:
3390 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3391 " failed for controller %d\n", __func__, h->ctlr);
3392 return -ENOMEM;
edd16368
SC		 3393}
3394
3395static int wait_for_device_to_become_ready(struct ctlr_info *h,
3396 unsigned char lunaddr[])
3397{
3398 int rc = 0;
3399 int count = 0;
3400 int waittime = 1; /* seconds */
3401 struct CommandList *c;
3402
3403 c = cmd_special_alloc(h);
3404 if (!c) {
3405 dev_warn(&h->pdev->dev, "out of memory in "
3406 "wait_for_device_to_become_ready.\n");
3407 return IO_ERROR;
3408 }
3409
3410 /* Send test unit ready until device ready, or give up. */
3411 while (count < HPSA_TUR_RETRY_LIMIT) {
3412
3413 /* Wait for a bit. do this first, because if we send
3414 * the TUR right away, the reset will just abort it.
3415 */
3416 msleep(1000 * waittime);
3417 count++;
3418
3419 /* Increase wait time with each try, up to a point. */
3420 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3421 waittime = waittime * 2;
3422
a2dac136
SC		 3423 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3424 (void) fill_cmd(c, TEST_UNIT_READY, h,
3425 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3426 hpsa_scsi_do_simple_cmd_core(h, c);
3427 /* no unmap needed here because no data xfer. */
3428
3429 if (c->err_info->CommandStatus == CMD_SUCCESS)
3430 break;
3431
3432 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3433 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3434 (c->err_info->SenseInfo[2] == NO_SENSE ||
3435 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3436 break;
3437
3438 dev_warn(&h->pdev->dev, "waiting %d secs "
3439 "for device to become ready.\n", waittime);
3440 rc = 1; /* device not ready. */
3441 }
3442
3443 if (rc)
3444 dev_warn(&h->pdev->dev, "giving up on device.\n");
3445 else
3446 dev_warn(&h->pdev->dev, "device is ready.\n");
3447
3448 cmd_special_free(h, c);
3449 return rc;
3450}
3451
3452/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3453 * complaining. Doing a host- or bus-reset can't do anything good here.
3454 */
3455static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3456{
3457 int rc;
3458 struct ctlr_info *h;
3459 struct hpsa_scsi_dev_t *dev;
3460
3461 /* find the controller to which the command to be aborted was sent */
3462 h = sdev_to_hba(scsicmd->device);
3463 if (h == NULL) /* paranoia */
3464 return FAILED;
edd16368
SC		 3465 dev = scsicmd->device->hostdata;
3466 if (!dev) {
3467 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3468 "device lookup failed.\n");
3469 return FAILED;
3470 }
d416b0c7
SC		 3471 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3472 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3473 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3474 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3475 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3476 return SUCCESS;
3477
3478 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3479 return FAILED;
3480}
3481
6cba3f19
SC		 3482static void swizzle_abort_tag(u8 *tag)
3483{
3484 u8 original_tag[8];
3485
3486 memcpy(original_tag, tag, 8);
3487 tag[0] = original_tag[3];
3488 tag[1] = original_tag[2];
3489 tag[2] = original_tag[1];
3490 tag[3] = original_tag[0];
3491 tag[4] = original_tag[7];
3492 tag[5] = original_tag[6];
3493 tag[6] = original_tag[5];
3494 tag[7] = original_tag[4];
3495}
3496
17eb87d2
ST		 3497static void hpsa_get_tag(struct ctlr_info *h,
3498 struct CommandList *c, u32 *taglower, u32 *tagupper)
3499{
3500 if (c->cmd_type == CMD_IOACCEL1) {
3501 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3502 &h->ioaccel_cmd_pool[c->cmdindex];
3503 *tagupper = cm1->Tag.upper;
3504 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 3505 return;
3506 }
3507 if (c->cmd_type == CMD_IOACCEL2) {
3508 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
3509 &h->ioaccel2_cmd_pool[c->cmdindex];
3510 *tagupper = cm2->Tag.upper;
3511 *taglower = cm2->Tag.lower;
3512 return;
17eb87d2 3513 }
54b6e9e9
ST		 3514 *tagupper = c->Header.Tag.upper;
3515 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 3516}
3517
54b6e9e9 3518
75167d2c 3519static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3520 struct CommandList *abort, int swizzle)
75167d2c
SC		 3521{
3522 int rc = IO_OK;
3523 struct CommandList *c;
3524 struct ErrorInfo *ei;
17eb87d2 3525 u32 tagupper, taglower;
75167d2c
SC		 3526
3527 c = cmd_special_alloc(h);
3528 if (c == NULL) { /* trouble... */
3529 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3530 return -ENOMEM;
3531 }
3532
a2dac136
SC		 3533 /* fill_cmd can't fail here, no buffer to map */
3534 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3535 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3536 if (swizzle)
3537 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3538 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3539 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3540 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3541 __func__, tagupper, taglower);
75167d2c
SC		 3542 /* no unmap needed here because no data xfer. */
3543
3544 ei = c->err_info;
3545 switch (ei->CommandStatus) {
3546 case CMD_SUCCESS:
3547 break;
3548 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3549 rc = -1;
3550 break;
3551 default:
3552 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3553 __func__, tagupper, taglower);
75167d2c
SC		 3554 hpsa_scsi_interpret_error(c);
3555 rc = -1;
3556 break;
3557 }
3558 cmd_special_free(h, c);
3559 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3560 abort->Header.Tag.upper, abort->Header.Tag.lower);
3561 return rc;
3562}
3563
3564/*
3565 * hpsa_find_cmd_in_queue
3566 *
3567 * Used to determine whether a command (find) is still present
3568 * in queue_head. Optionally excludes the last element of queue_head.
3569 *
3570 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3571 * not yet been submitted, and so can be aborted by the driver without
3572 * sending an abort to the hardware.
3573 *
3574 * Returns pointer to command if found in queue, NULL otherwise.
3575 */
3576static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3577 struct scsi_cmnd *find, struct list_head *queue_head)
3578{
3579 unsigned long flags;
3580 struct CommandList *c = NULL; /* ptr into cmpQ */
3581
3582 if (!find)
3583 return 0;
3584 spin_lock_irqsave(&h->lock, flags);
3585 list_for_each_entry(c, queue_head, list) {
3586 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3587 continue;
3588 if (c->scsi_cmd == find) {
3589 spin_unlock_irqrestore(&h->lock, flags);
3590 return c;
3591 }
3592 }
3593 spin_unlock_irqrestore(&h->lock, flags);
3594 return NULL;
3595}
3596
6cba3f19
SC		 3597static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3598 u8 *tag, struct list_head *queue_head)
3599{
3600 unsigned long flags;
3601 struct CommandList *c;
3602
3603 spin_lock_irqsave(&h->lock, flags);
3604 list_for_each_entry(c, queue_head, list) {
3605 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3606 continue;
3607 spin_unlock_irqrestore(&h->lock, flags);
3608 return c;
3609 }
3610 spin_unlock_irqrestore(&h->lock, flags);
3611 return NULL;
3612}
3613
54b6e9e9
ST		 3614/* ioaccel2 path firmware cannot handle abort task requests.
3615 * Change abort requests to physical target reset, and send to the
3616 * address of the physical disk used for the ioaccel 2 command.
3617 * Return 0 on success (IO_OK)
3618 * -1 on failure
3619 */
3620
3621static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
3622 unsigned char *scsi3addr, struct CommandList *abort)
3623{
3624 int rc = IO_OK;
3625 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
3626 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
3627 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
3628 unsigned char *psa = &phys_scsi3addr[0];
3629
3630 /* Get a pointer to the hpsa logical device. */
3631 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
3632 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
3633 if (dev == NULL) {
3634 dev_warn(&h->pdev->dev,
3635 "Cannot abort: no device pointer for command.\n");
3636 return -1; /* not abortable */
3637 }
3638
3639 if (!dev->offload_enabled) {
3640 dev_warn(&h->pdev->dev,
3641 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
3642 return -1; /* not abortable */
3643 }
3644
3645 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
3646 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
3647 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
3648 return -1; /* not abortable */
3649 }
3650
3651 /* send the reset */
3652 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
3653 if (rc != 0) {
3654 dev_warn(&h->pdev->dev,
3655 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3656 psa[0], psa[1], psa[2], psa[3],
3657 psa[4], psa[5], psa[6], psa[7]);
3658 return rc; /* failed to reset */
3659 }
3660
3661 /* wait for device to recover */
3662 if (wait_for_device_to_become_ready(h, psa) != 0) {
3663 dev_warn(&h->pdev->dev,
3664 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3665 psa[0], psa[1], psa[2], psa[3],
3666 psa[4], psa[5], psa[6], psa[7]);
3667 return -1; /* failed to recover */
3668 }
3669
3670 /* device recovered */
3671 dev_info(&h->pdev->dev,
3672 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3673 psa[0], psa[1], psa[2], psa[3],
3674 psa[4], psa[5], psa[6], psa[7]);
3675
3676 return rc; /* success */
3677}
3678
6cba3f19
SC		 3679/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3680 * tell which kind we're dealing with, so we send the abort both ways. There
3681 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3682 * way we construct our tags but we check anyway in case the assumptions which
3683 * make this true someday become false.
3684 */
3685static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3686 unsigned char *scsi3addr, struct CommandList *abort)
3687{
3688 u8 swizzled_tag[8];
3689 struct CommandList *c;
3690 int rc = 0, rc2 = 0;
3691
54b6e9e9
ST		 3692 /* ioccelerator mode 2 commands should be aborted via the
3693 * accelerated path, since RAID path is unaware of these commands,
3694 * but underlying firmware can't handle abort TMF.
3695 * Change abort to physical device reset.
3696 */
3697 if (abort->cmd_type == CMD_IOACCEL2)
3698 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
3699
6cba3f19
SC		 3700 /* we do not expect to find the swizzled tag in our queue, but
3701 * check anyway just to be sure the assumptions which make this
3702 * the case haven't become wrong.
3703 */
3704 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3705 swizzle_abort_tag(swizzled_tag);
3706 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3707 if (c != NULL) {
3708 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3709 return hpsa_send_abort(h, scsi3addr, abort, 0);
3710 }
3711 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3712
3713 /* if the command is still in our queue, we can't conclude that it was
3714 * aborted (it might have just completed normally) but in any case
3715 * we don't need to try to abort it another way.
3716 */
3717 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3718 if (c)
3719 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3720 return rc && rc2;
3721}
3722
75167d2c
SC		 3723/* Send an abort for the specified command.
3724 * If the device and controller support it,
3725 * send a task abort request.
3726 */
3727static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3728{
3729
3730 int i, rc;
3731 struct ctlr_info *h;
3732 struct hpsa_scsi_dev_t *dev;
3733 struct CommandList *abort; /* pointer to command to be aborted */
3734 struct CommandList *found;
3735 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3736 char msg[256]; /* For debug messaging. */
3737 int ml = 0;
17eb87d2 3738 u32 tagupper, taglower;
75167d2c
SC		 3739
3740 /* Find the controller of the command to be aborted */
3741 h = sdev_to_hba(sc->device);
3742 if (WARN(h == NULL,
3743 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3744 return FAILED;
3745
3746 /* Check that controller supports some kind of task abort */
3747 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3748 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3749 return FAILED;
3750
3751 memset(msg, 0, sizeof(msg));
3752 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3753 h->scsi_host->host_no, sc->device->channel,
3754 sc->device->id, sc->device->lun);
3755
3756 /* Find the device of the command to be aborted */
3757 dev = sc->device->hostdata;
3758 if (!dev) {
3759 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3760 msg);
3761 return FAILED;
3762 }
3763
3764 /* Get SCSI command to be aborted */
3765 abort = (struct CommandList *) sc->host_scribble;
3766 if (abort == NULL) {
3767 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3768 msg);
3769 return FAILED;
3770 }
17eb87d2
ST		 3771 hpsa_get_tag(h, abort, &taglower, &tagupper);
3772 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3773 as = (struct scsi_cmnd *) abort->scsi_cmd;
3774 if (as != NULL)
3775 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3776 as->cmnd[0], as->serial_number);
3777 dev_dbg(&h->pdev->dev, "%s\n", msg);
3778 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3779 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3780
3781 /* Search reqQ to See if command is queued but not submitted,
3782 * if so, complete the command with aborted status and remove
3783 * it from the reqQ.
3784 */
3785 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3786 if (found) {
3787 found->err_info->CommandStatus = CMD_ABORTED;
3788 finish_cmd(found);
3789 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3790 msg);
3791 return SUCCESS;
3792 }
3793
3794 /* not in reqQ, if also not in cmpQ, must have already completed */
3795 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3796 if (!found) {
d6ebd0f7 3797 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 3798 msg);
3799 return SUCCESS;
3800 }
3801
3802 /*
3803 * Command is in flight, or possibly already completed
3804 * by the firmware (but not to the scsi mid layer) but we can't
3805 * distinguish which. Send the abort down.
3806 */
6cba3f19 3807 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 3808 if (rc != 0) {
3809 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
3810 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
3811 h->scsi_host->host_no,
3812 dev->bus, dev->target, dev->lun);
3813 return FAILED;
3814 }
3815 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
3816
3817 /* If the abort(s) above completed and actually aborted the
3818 * command, then the command to be aborted should already be
3819 * completed. If not, wait around a bit more to see if they
3820 * manage to complete normally.
3821 */
3822#define ABORT_COMPLETE_WAIT_SECS 30
3823 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
3824 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3825 if (!found)
3826 return SUCCESS;
3827 msleep(100);
3828 }
3829 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
3830 msg, ABORT_COMPLETE_WAIT_SECS);
3831 return FAILED;
3832}
3833
3834
edd16368
SC		 3835/*
3836 * For operations that cannot sleep, a command block is allocated at init,
3837 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
3838 * which ones are free or in use. Lock must be held when calling this.
3839 * cmd_free() is the complement.
3840 */
3841static struct CommandList *cmd_alloc(struct ctlr_info *h)
3842{
3843 struct CommandList *c;
3844 int i;
3845 union u64bit temp64;
3846 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 3847 unsigned long flags;
edd16368 3848
e16a33ad 3849 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3850 do {
3851 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 3852 if (i == h->nr_cmds) {
3853 spin_unlock_irqrestore(&h->lock, flags);
edd16368 3854 return NULL;
e16a33ad 3855 }
edd16368
SC		 3856 } while (test_and_set_bit
3857 (i & (BITS_PER_LONG - 1),
3858 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 3859 spin_unlock_irqrestore(&h->lock, flags);
3860
edd16368
SC		 3861 c = h->cmd_pool + i;
3862 memset(c, 0, sizeof(*c));
3863 cmd_dma_handle = h->cmd_pool_dhandle
3864 + i * sizeof(*c);
3865 c->err_info = h->errinfo_pool + i;
3866 memset(c->err_info, 0, sizeof(*c->err_info));
3867 err_dma_handle = h->errinfo_pool_dhandle
3868 + i * sizeof(*c->err_info);
edd16368
SC		 3869
3870 c->cmdindex = i;
3871
9e0fc764 3872 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3873 c->busaddr = (u32) cmd_dma_handle;
3874 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3875 c->ErrDesc.Addr.lower = temp64.val32.lower;
3876 c->ErrDesc.Addr.upper = temp64.val32.upper;
3877 c->ErrDesc.Len = sizeof(*c->err_info);
3878
3879 c->h = h;
3880 return c;
3881}
3882
3883/* For operations that can wait for kmalloc to possibly sleep,
3884 * this routine can be called. Lock need not be held to call
3885 * cmd_special_alloc. cmd_special_free() is the complement.
3886 */
3887static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
3888{
3889 struct CommandList *c;
3890 union u64bit temp64;
3891 dma_addr_t cmd_dma_handle, err_dma_handle;
3892
3893 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
3894 if (c == NULL)
3895 return NULL;
3896 memset(c, 0, sizeof(*c));
3897
e1f7de0c 3898 c->cmd_type = CMD_SCSI;
edd16368
SC		 3899 c->cmdindex = -1;
3900
3901 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
3902 &err_dma_handle);
3903
3904 if (c->err_info == NULL) {
3905 pci_free_consistent(h->pdev,
3906 sizeof(*c), c, cmd_dma_handle);
3907 return NULL;
3908 }
3909 memset(c->err_info, 0, sizeof(*c->err_info));
3910
9e0fc764 3911 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3912 c->busaddr = (u32) cmd_dma_handle;
3913 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3914 c->ErrDesc.Addr.lower = temp64.val32.lower;
3915 c->ErrDesc.Addr.upper = temp64.val32.upper;
3916 c->ErrDesc.Len = sizeof(*c->err_info);
3917
3918 c->h = h;
3919 return c;
3920}
3921
3922static void cmd_free(struct ctlr_info *h, struct CommandList *c)
3923{
3924 int i;
e16a33ad 3925 unsigned long flags;
edd16368
SC		 3926
3927 i = c - h->cmd_pool;
e16a33ad 3928 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3929 clear_bit(i & (BITS_PER_LONG - 1),
3930 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 3931 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 3932}
3933
3934static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
3935{
3936 union u64bit temp64;
3937
3938 temp64.val32.lower = c->ErrDesc.Addr.lower;
3939 temp64.val32.upper = c->ErrDesc.Addr.upper;
3940 pci_free_consistent(h->pdev, sizeof(*c->err_info),
3941 c->err_info, (dma_addr_t) temp64.val);
3942 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 3943 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 3944}
3945
3946#ifdef CONFIG_COMPAT
3947
edd16368
SC		 3948static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
3949{
3950 IOCTL32_Command_struct __user *arg32 =
3951 (IOCTL32_Command_struct __user *) arg;
3952 IOCTL_Command_struct arg64;
3953 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
3954 int err;
3955 u32 cp;
3956
938abd84 3957 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3958 err = 0;
3959 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3960 sizeof(arg64.LUN_info));
3961 err |= copy_from_user(&arg64.Request, &arg32->Request,
3962 sizeof(arg64.Request));
3963 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3964 sizeof(arg64.error_info));
3965 err |= get_user(arg64.buf_size, &arg32->buf_size);
3966 err |= get_user(cp, &arg32->buf);
3967 arg64.buf = compat_ptr(cp);
3968 err |= copy_to_user(p, &arg64, sizeof(arg64));
3969
3970 if (err)
3971 return -EFAULT;
3972
e39eeaed 3973 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 3974 if (err)
3975 return err;
3976 err |= copy_in_user(&arg32->error_info, &p->error_info,
3977 sizeof(arg32->error_info));
3978 if (err)
3979 return -EFAULT;
3980 return err;
3981}
3982
3983static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
3984 int cmd, void *arg)
3985{
3986 BIG_IOCTL32_Command_struct __user *arg32 =
3987 (BIG_IOCTL32_Command_struct __user *) arg;
3988 BIG_IOCTL_Command_struct arg64;
3989 BIG_IOCTL_Command_struct __user *p =
3990 compat_alloc_user_space(sizeof(arg64));
3991 int err;
3992 u32 cp;
3993
938abd84 3994 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3995 err = 0;
3996 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3997 sizeof(arg64.LUN_info));
3998 err |= copy_from_user(&arg64.Request, &arg32->Request,
3999 sizeof(arg64.Request));
4000 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4001 sizeof(arg64.error_info));
4002 err |= get_user(arg64.buf_size, &arg32->buf_size);
4003 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4004 err |= get_user(cp, &arg32->buf);
4005 arg64.buf = compat_ptr(cp);
4006 err |= copy_to_user(p, &arg64, sizeof(arg64));
4007
4008 if (err)
4009 return -EFAULT;
4010
e39eeaed 4011 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4012 if (err)
4013 return err;
4014 err |= copy_in_user(&arg32->error_info, &p->error_info,
4015 sizeof(arg32->error_info));
4016 if (err)
4017 return -EFAULT;
4018 return err;
4019}
71fe75a7
SC		 4020
4021static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4022{
4023 switch (cmd) {
4024 case CCISS_GETPCIINFO:
4025 case CCISS_GETINTINFO:
4026 case CCISS_SETINTINFO:
4027 case CCISS_GETNODENAME:
4028 case CCISS_SETNODENAME:
4029 case CCISS_GETHEARTBEAT:
4030 case CCISS_GETBUSTYPES:
4031 case CCISS_GETFIRMVER:
4032 case CCISS_GETDRIVVER:
4033 case CCISS_REVALIDVOLS:
4034 case CCISS_DEREGDISK:
4035 case CCISS_REGNEWDISK:
4036 case CCISS_REGNEWD:
4037 case CCISS_RESCANDISK:
4038 case CCISS_GETLUNINFO:
4039 return hpsa_ioctl(dev, cmd, arg);
4040
4041 case CCISS_PASSTHRU32:
4042 return hpsa_ioctl32_passthru(dev, cmd, arg);
4043 case CCISS_BIG_PASSTHRU32:
4044 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4045
4046 default:
4047 return -ENOIOCTLCMD;
4048 }
4049}
edd16368
SC		 4050#endif
4051
4052static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4053{
4054 struct hpsa_pci_info pciinfo;
4055
4056 if (!argp)
4057 return -EINVAL;
4058 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4059 pciinfo.bus = h->pdev->bus->number;
4060 pciinfo.dev_fn = h->pdev->devfn;
4061 pciinfo.board_id = h->board_id;
4062 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4063 return -EFAULT;
4064 return 0;
4065}
4066
4067static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4068{
4069 DriverVer_type DriverVer;
4070 unsigned char vmaj, vmin, vsubmin;
4071 int rc;
4072
4073 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4074 &vmaj, &vmin, &vsubmin);
4075 if (rc != 3) {
4076 dev_info(&h->pdev->dev, "driver version string '%s' "
4077 "unrecognized.", HPSA_DRIVER_VERSION);
4078 vmaj = 0;
4079 vmin = 0;
4080 vsubmin = 0;
4081 }
4082 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4083 if (!argp)
4084 return -EINVAL;
4085 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4086 return -EFAULT;
4087 return 0;
4088}
4089
4090static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4091{
4092 IOCTL_Command_struct iocommand;
4093 struct CommandList *c;
4094 char *buff = NULL;
4095 union u64bit temp64;
c1f63c8f 4096 int rc = 0;
edd16368
SC		 4097
4098 if (!argp)
4099 return -EINVAL;
4100 if (!capable(CAP_SYS_RAWIO))
4101 return -EPERM;
4102 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4103 return -EFAULT;
4104 if ((iocommand.buf_size < 1) &&
4105 (iocommand.Request.Type.Direction != XFER_NONE)) {
4106 return -EINVAL;
4107 }
4108 if (iocommand.buf_size > 0) {
4109 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4110 if (buff == NULL)
4111 return -EFAULT;
b03a7771
SC		 4112 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4113 /* Copy the data into the buffer we created */
4114 if (copy_from_user(buff, iocommand.buf,
4115 iocommand.buf_size)) {
c1f63c8f
SC		 4116 rc = -EFAULT;
4117 goto out_kfree;
b03a7771
SC		 4118 }
4119 } else {
4120 memset(buff, 0, iocommand.buf_size);
edd16368 4121 }
b03a7771 4122 }
edd16368
SC		 4123 c = cmd_special_alloc(h);
4124 if (c == NULL) {
c1f63c8f
SC		 4125 rc = -ENOMEM;
4126 goto out_kfree;
edd16368
SC		 4127 }
4128 /* Fill in the command type */
4129 c->cmd_type = CMD_IOCTL_PEND;
4130 /* Fill in Command Header */
4131 c->Header.ReplyQueue = 0; /* unused in simple mode */
4132 if (iocommand.buf_size > 0) { /* buffer to fill */
4133 c->Header.SGList = 1;
4134 c->Header.SGTotal = 1;
4135 } else { /* no buffers to fill */
4136 c->Header.SGList = 0;
4137 c->Header.SGTotal = 0;
4138 }
4139 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4140 /* use the kernel address the cmd block for tag */
4141 c->Header.Tag.lower = c->busaddr;
4142
4143 /* Fill in Request block */
4144 memcpy(&c->Request, &iocommand.Request,
4145 sizeof(c->Request));
4146
4147 /* Fill in the scatter gather information */
4148 if (iocommand.buf_size > 0) {
4149 temp64.val = pci_map_single(h->pdev, buff,
4150 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4151 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4152 c->SG[0].Addr.lower = 0;
4153 c->SG[0].Addr.upper = 0;
4154 c->SG[0].Len = 0;
4155 rc = -ENOMEM;
4156 goto out;
4157 }
edd16368
SC		 4158 c->SG[0].Addr.lower = temp64.val32.lower;
4159 c->SG[0].Addr.upper = temp64.val32.upper;
4160 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4161 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4162 }
a0c12413 4163 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4164 if (iocommand.buf_size > 0)
4165 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4166 check_ioctl_unit_attention(h, c);
4167
4168 /* Copy the error information out */
4169 memcpy(&iocommand.error_info, c->err_info,
4170 sizeof(iocommand.error_info));
4171 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4172 rc = -EFAULT;
4173 goto out;
edd16368 4174 }
b03a7771
SC		 4175 if (iocommand.Request.Type.Direction == XFER_READ &&
4176 iocommand.buf_size > 0) {
edd16368
SC		 4177 /* Copy the data out of the buffer we created */
4178 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4179 rc = -EFAULT;
4180 goto out;
edd16368
SC		 4181 }
4182 }
c1f63c8f 4183out:
edd16368 4184 cmd_special_free(h, c);
c1f63c8f
SC		 4185out_kfree:
4186 kfree(buff);
4187 return rc;
edd16368
SC		 4188}
4189
4190static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4191{
4192 BIG_IOCTL_Command_struct *ioc;
4193 struct CommandList *c;
4194 unsigned char **buff = NULL;
4195 int *buff_size = NULL;
4196 union u64bit temp64;
4197 BYTE sg_used = 0;
4198 int status = 0;
4199 int i;
01a02ffc
SC		 4200 u32 left;
4201 u32 sz;
edd16368
SC		 4202 BYTE __user *data_ptr;
4203
4204 if (!argp)
4205 return -EINVAL;
4206 if (!capable(CAP_SYS_RAWIO))
4207 return -EPERM;
4208 ioc = (BIG_IOCTL_Command_struct *)
4209 kmalloc(sizeof(*ioc), GFP_KERNEL);
4210 if (!ioc) {
4211 status = -ENOMEM;
4212 goto cleanup1;
4213 }
4214 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4215 status = -EFAULT;
4216 goto cleanup1;
4217 }
4218 if ((ioc->buf_size < 1) &&
4219 (ioc->Request.Type.Direction != XFER_NONE)) {
4220 status = -EINVAL;
4221 goto cleanup1;
4222 }
4223 /* Check kmalloc limits using all SGs */
4224 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4225 status = -EINVAL;
4226 goto cleanup1;
4227 }
d66ae08b 4228 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4229 status = -EINVAL;
4230 goto cleanup1;
4231 }
d66ae08b 4232 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4233 if (!buff) {
4234 status = -ENOMEM;
4235 goto cleanup1;
4236 }
d66ae08b 4237 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4238 if (!buff_size) {
4239 status = -ENOMEM;
4240 goto cleanup1;
4241 }
4242 left = ioc->buf_size;
4243 data_ptr = ioc->buf;
4244 while (left) {
4245 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4246 buff_size[sg_used] = sz;
4247 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4248 if (buff[sg_used] == NULL) {
4249 status = -ENOMEM;
4250 goto cleanup1;
4251 }
4252 if (ioc->Request.Type.Direction == XFER_WRITE) {
4253 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4254 status = -ENOMEM;
4255 goto cleanup1;
4256 }
4257 } else
4258 memset(buff[sg_used], 0, sz);
4259 left -= sz;
4260 data_ptr += sz;
4261 sg_used++;
4262 }
4263 c = cmd_special_alloc(h);
4264 if (c == NULL) {
4265 status = -ENOMEM;
4266 goto cleanup1;
4267 }
4268 c->cmd_type = CMD_IOCTL_PEND;
4269 c->Header.ReplyQueue = 0;
b03a7771 4270 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4271 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4272 c->Header.Tag.lower = c->busaddr;
4273 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4274 if (ioc->buf_size > 0) {
4275 int i;
4276 for (i = 0; i < sg_used; i++) {
4277 temp64.val = pci_map_single(h->pdev, buff[i],
4278 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4279 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4280 c->SG[i].Addr.lower = 0;
4281 c->SG[i].Addr.upper = 0;
4282 c->SG[i].Len = 0;
4283 hpsa_pci_unmap(h->pdev, c, i,
4284 PCI_DMA_BIDIRECTIONAL);
4285 status = -ENOMEM;
e2d4a1f6 4286 goto cleanup0;
bcc48ffa 4287 }
edd16368
SC		 4288 c->SG[i].Addr.lower = temp64.val32.lower;
4289 c->SG[i].Addr.upper = temp64.val32.upper;
4290 c->SG[i].Len = buff_size[i];
e1d9cbfa 4291 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4292 }
4293 }
a0c12413 4294 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4295 if (sg_used)
4296 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4297 check_ioctl_unit_attention(h, c);
4298 /* Copy the error information out */
4299 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4300 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4301 status = -EFAULT;
e2d4a1f6 4302 goto cleanup0;
edd16368 4303 }
b03a7771 4304 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4305 /* Copy the data out of the buffer we created */
4306 BYTE __user *ptr = ioc->buf;
4307 for (i = 0; i < sg_used; i++) {
4308 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4309 status = -EFAULT;
e2d4a1f6 4310 goto cleanup0;
edd16368
SC		 4311 }
4312 ptr += buff_size[i];
4313 }
4314 }
edd16368 4315 status = 0;
e2d4a1f6
SC		 4316cleanup0:
4317 cmd_special_free(h, c);
edd16368
SC		 4318cleanup1:
4319 if (buff) {
4320 for (i = 0; i < sg_used; i++)
4321 kfree(buff[i]);
4322 kfree(buff);
4323 }
4324 kfree(buff_size);
4325 kfree(ioc);
4326 return status;
4327}
4328
4329static void check_ioctl_unit_attention(struct ctlr_info *h,
4330 struct CommandList *c)
4331{
4332 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4333 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4334 (void) check_for_unit_attention(h, c);
4335}
0390f0c0
SC		 4336
4337static int increment_passthru_count(struct ctlr_info *h)
4338{
4339 unsigned long flags;
4340
4341 spin_lock_irqsave(&h->passthru_count_lock, flags);
4342 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4343 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4344 return -1;
4345 }
4346 h->passthru_count++;
4347 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4348 return 0;
4349}
4350
4351static void decrement_passthru_count(struct ctlr_info *h)
4352{
4353 unsigned long flags;
4354
4355 spin_lock_irqsave(&h->passthru_count_lock, flags);
4356 if (h->passthru_count <= 0) {
4357 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4358 /* not expecting to get here. */
4359 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4360 return;
4361 }
4362 h->passthru_count--;
4363 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4364}
4365
edd16368
SC		 4366/*
4367 * ioctl
4368 */
4369static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4370{
4371 struct ctlr_info *h;
4372 void __user *argp = (void __user *)arg;
0390f0c0 4373 int rc;
edd16368
SC		 4374
4375 h = sdev_to_hba(dev);
4376
4377 switch (cmd) {
4378 case CCISS_DEREGDISK:
4379 case CCISS_REGNEWDISK:
4380 case CCISS_REGNEWD:
a08a8471 4381 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4382 return 0;
4383 case CCISS_GETPCIINFO:
4384 return hpsa_getpciinfo_ioctl(h, argp);
4385 case CCISS_GETDRIVVER:
4386 return hpsa_getdrivver_ioctl(h, argp);
4387 case CCISS_PASSTHRU:
0390f0c0
SC		 4388 if (increment_passthru_count(h))
4389 return -EAGAIN;
4390 rc = hpsa_passthru_ioctl(h, argp);
4391 decrement_passthru_count(h);
4392 return rc;
edd16368 4393 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4394 if (increment_passthru_count(h))
4395 return -EAGAIN;
4396 rc = hpsa_big_passthru_ioctl(h, argp);
4397 decrement_passthru_count(h);
4398 return rc;
edd16368
SC		 4399 default:
4400 return -ENOTTY;
4401 }
4402}
4403
6f039790
GKH		 4404static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4405 u8 reset_type)
64670ac8
SC		 4406{
4407 struct CommandList *c;
4408
4409 c = cmd_alloc(h);
4410 if (!c)
4411 return -ENOMEM;
a2dac136
SC		 4412 /* fill_cmd can't fail here, no data buffer to map */
4413 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4414 RAID_CTLR_LUNID, TYPE_MSG);
4415 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4416 c->waiting = NULL;
4417 enqueue_cmd_and_start_io(h, c);
4418 /* Don't wait for completion, the reset won't complete. Don't free
4419 * the command either. This is the last command we will send before
4420 * re-initializing everything, so it doesn't matter and won't leak.
4421 */
4422 return 0;
4423}
4424
a2dac136 4425static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 4426 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 4427 int cmd_type)
4428{
4429 int pci_dir = XFER_NONE;
75167d2c 4430 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4431
4432 c->cmd_type = CMD_IOCTL_PEND;
4433 c->Header.ReplyQueue = 0;
4434 if (buff != NULL && size > 0) {
4435 c->Header.SGList = 1;
4436 c->Header.SGTotal = 1;
4437 } else {
4438 c->Header.SGList = 0;
4439 c->Header.SGTotal = 0;
4440 }
4441 c->Header.Tag.lower = c->busaddr;
4442 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4443
4444 c->Request.Type.Type = cmd_type;
4445 if (cmd_type == TYPE_CMD) {
4446 switch (cmd) {
4447 case HPSA_INQUIRY:
4448 /* are we trying to read a vital product page */
4449 if (page_code != 0) {
4450 c->Request.CDB[1] = 0x01;
4451 c->Request.CDB[2] = page_code;
4452 }
4453 c->Request.CDBLen = 6;
4454 c->Request.Type.Attribute = ATTR_SIMPLE;
4455 c->Request.Type.Direction = XFER_READ;
4456 c->Request.Timeout = 0;
4457 c->Request.CDB[0] = HPSA_INQUIRY;
4458 c->Request.CDB[4] = size & 0xFF;
4459 break;
4460 case HPSA_REPORT_LOG:
4461 case HPSA_REPORT_PHYS:
4462 /* Talking to controller so It's a physical command
4463 mode = 00 target = 0. Nothing to write.
4464 */
4465 c->Request.CDBLen = 12;
4466 c->Request.Type.Attribute = ATTR_SIMPLE;
4467 c->Request.Type.Direction = XFER_READ;
4468 c->Request.Timeout = 0;
4469 c->Request.CDB[0] = cmd;
4470 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4471 c->Request.CDB[7] = (size >> 16) & 0xFF;
4472 c->Request.CDB[8] = (size >> 8) & 0xFF;
4473 c->Request.CDB[9] = size & 0xFF;
4474 break;
edd16368
SC		 4475 case HPSA_CACHE_FLUSH:
4476 c->Request.CDBLen = 12;
4477 c->Request.Type.Attribute = ATTR_SIMPLE;
4478 c->Request.Type.Direction = XFER_WRITE;
4479 c->Request.Timeout = 0;
4480 c->Request.CDB[0] = BMIC_WRITE;
4481 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4482 c->Request.CDB[7] = (size >> 8) & 0xFF;
4483 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4484 break;
4485 case TEST_UNIT_READY:
4486 c->Request.CDBLen = 6;
4487 c->Request.Type.Attribute = ATTR_SIMPLE;
4488 c->Request.Type.Direction = XFER_NONE;
4489 c->Request.Timeout = 0;
4490 break;
283b4a9b
SC		 4491 case HPSA_GET_RAID_MAP:
4492 c->Request.CDBLen = 12;
4493 c->Request.Type.Attribute = ATTR_SIMPLE;
4494 c->Request.Type.Direction = XFER_READ;
4495 c->Request.Timeout = 0;
4496 c->Request.CDB[0] = HPSA_CISS_READ;
4497 c->Request.CDB[1] = cmd;
4498 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4499 c->Request.CDB[7] = (size >> 16) & 0xFF;
4500 c->Request.CDB[8] = (size >> 8) & 0xFF;
4501 c->Request.CDB[9] = size & 0xFF;
4502 break;
edd16368
SC		 4503 default:
4504 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4505 BUG();
a2dac136 4506 return -1;
edd16368
SC		 4507 }
4508 } else if (cmd_type == TYPE_MSG) {
4509 switch (cmd) {
4510
4511 case HPSA_DEVICE_RESET_MSG:
4512 c->Request.CDBLen = 16;
4513 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4514 c->Request.Type.Attribute = ATTR_SIMPLE;
4515 c->Request.Type.Direction = XFER_NONE;
4516 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4517 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4518 c->Request.CDB[0] = cmd;
21e89afd 4519 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4520 /* If bytes 4-7 are zero, it means reset the */
4521 /* LunID device */
4522 c->Request.CDB[4] = 0x00;
4523 c->Request.CDB[5] = 0x00;
4524 c->Request.CDB[6] = 0x00;
4525 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4526 break;
4527 case HPSA_ABORT_MSG:
4528 a = buff; /* point to command to be aborted */
4529 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4530 a->Header.Tag.upper, a->Header.Tag.lower,
4531 c->Header.Tag.upper, c->Header.Tag.lower);
4532 c->Request.CDBLen = 16;
4533 c->Request.Type.Type = TYPE_MSG;
4534 c->Request.Type.Attribute = ATTR_SIMPLE;
4535 c->Request.Type.Direction = XFER_WRITE;
4536 c->Request.Timeout = 0; /* Don't time out */
4537 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4538 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4539 c->Request.CDB[2] = 0x00; /* reserved */
4540 c->Request.CDB[3] = 0x00; /* reserved */
4541 /* Tag to abort goes in CDB[4]-CDB[11] */
4542 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4543 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4544 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4545 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4546 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4547 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4548 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4549 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4550 c->Request.CDB[12] = 0x00; /* reserved */
4551 c->Request.CDB[13] = 0x00; /* reserved */
4552 c->Request.CDB[14] = 0x00; /* reserved */
4553 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4554 break;
edd16368
SC		 4555 default:
4556 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4557 cmd);
4558 BUG();
4559 }
4560 } else {
4561 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4562 BUG();
4563 }
4564
4565 switch (c->Request.Type.Direction) {
4566 case XFER_READ:
4567 pci_dir = PCI_DMA_FROMDEVICE;
4568 break;
4569 case XFER_WRITE:
4570 pci_dir = PCI_DMA_TODEVICE;
4571 break;
4572 case XFER_NONE:
4573 pci_dir = PCI_DMA_NONE;
4574 break;
4575 default:
4576 pci_dir = PCI_DMA_BIDIRECTIONAL;
4577 }
a2dac136
SC		 4578 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4579 return -1;
4580 return 0;
edd16368
SC		 4581}
4582
4583/*
4584 * Map (physical) PCI mem into (virtual) kernel space
4585 */
4586static void __iomem *remap_pci_mem(ulong base, ulong size)
4587{
4588 ulong page_base = ((ulong) base) & PAGE_MASK;
4589 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4590 void __iomem *page_remapped = ioremap_nocache(page_base,
4591 page_offs + size);
edd16368
SC		 4592
4593 return page_remapped ? (page_remapped + page_offs) : NULL;
4594}
4595
4596/* Takes cmds off the submission queue and sends them to the hardware,
4597 * then puts them on the queue of cmds waiting for completion.
4598 */
4599static void start_io(struct ctlr_info *h)
4600{
4601 struct CommandList *c;
e16a33ad 4602 unsigned long flags;
edd16368 4603
e16a33ad 4604 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4605 while (!list_empty(&h->reqQ)) {
4606 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4607 /* can't do anything if fifo is full */
4608 if ((h->access.fifo_full(h))) {
396883e2 4609 h->fifo_recently_full = 1;
edd16368
SC		 4610 dev_warn(&h->pdev->dev, "fifo full\n");
4611 break;
4612 }
396883e2 4613 h->fifo_recently_full = 0;
edd16368
SC		 4614
4615 /* Get the first entry from the Request Q */
4616 removeQ(c);
4617 h->Qdepth--;
4618
edd16368
SC		 4619 /* Put job onto the completed Q */
4620 addQ(&h->cmpQ, c);
e16a33ad
MG		 4621
4622 /* Must increment commands_outstanding before unlocking
4623 * and submitting to avoid race checking for fifo full
4624 * condition.
4625 */
4626 h->commands_outstanding++;
4627 if (h->commands_outstanding > h->max_outstanding)
4628 h->max_outstanding = h->commands_outstanding;
4629
4630 /* Tell the controller execute command */
4631 spin_unlock_irqrestore(&h->lock, flags);
4632 h->access.submit_command(h, c);
4633 spin_lock_irqsave(&h->lock, flags);
edd16368 4634 }
e16a33ad 4635 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4636}
4637
254f796b 4638static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4639{
254f796b 4640 return h->access.command_completed(h, q);
edd16368
SC		 4641}
4642
900c5440 4643static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4644{
4645 return h->access.intr_pending(h);
4646}
4647
4648static inline long interrupt_not_for_us(struct ctlr_info *h)
4649{
10f66018
SC		 4650 return (h->access.intr_pending(h) == 0) ||
4651 (h->interrupts_enabled == 0);
edd16368
SC		 4652}
4653
01a02ffc
SC		 4654static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4655 u32 raw_tag)
edd16368
SC		 4656{
4657 if (unlikely(tag_index >= h->nr_cmds)) {
4658 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4659 return 1;
4660 }
4661 return 0;
4662}
4663
5a3d16f5 4664static inline void finish_cmd(struct CommandList *c)
edd16368 4665{
e16a33ad 4666 unsigned long flags;
396883e2
SC		 4667 int io_may_be_stalled = 0;
4668 struct ctlr_info *h = c->h;
e16a33ad 4669
396883e2 4670 spin_lock_irqsave(&h->lock, flags);
edd16368 4671 removeQ(c);
396883e2
SC		 4672
4673 /*
4674 * Check for possibly stalled i/o.
4675 *
4676 * If a fifo_full condition is encountered, requests will back up
4677 * in h->reqQ. This queue is only emptied out by start_io which is
4678 * only called when a new i/o request comes in. If no i/o's are
4679 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4680 * start_io from here if we detect such a danger.
4681 *
4682 * Normally, we shouldn't hit this case, but pounding on the
4683 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4684 * commands_outstanding is low. We want to avoid calling
4685 * start_io from in here as much as possible, and esp. don't
4686 * want to get in a cycle where we call start_io every time
4687 * through here.
4688 */
4689 if (unlikely(h->fifo_recently_full) &&
4690 h->commands_outstanding < 5)
4691 io_may_be_stalled = 1;
4692
4693 spin_unlock_irqrestore(&h->lock, flags);
4694
e85c5974 4695 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 4696 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
4697 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 4698 complete_scsi_command(c);
edd16368
SC		 4699 else if (c->cmd_type == CMD_IOCTL_PEND)
4700 complete(c->waiting);
396883e2
SC		 4701 if (unlikely(io_may_be_stalled))
4702 start_io(h);
edd16368
SC		 4703}
4704
a104c99f
SC		 4705static inline u32 hpsa_tag_contains_index(u32 tag)
4706{
a104c99f
SC		 4707 return tag & DIRECT_LOOKUP_BIT;
4708}
4709
4710static inline u32 hpsa_tag_to_index(u32 tag)
4711{
a104c99f
SC		 4712 return tag >> DIRECT_LOOKUP_SHIFT;
4713}
4714
a9a3a273
SC		 4715
4716static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4717{
a9a3a273
SC		 4718#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4719#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4720 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4721 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4722 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4723}
4724
303932fd 4725/* process completion of an indexed ("direct lookup") command */
1d94f94d 4726static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4727 u32 raw_tag)
4728{
4729 u32 tag_index;
4730 struct CommandList *c;
4731
4732 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4733 if (!bad_tag(h, tag_index, raw_tag)) {
4734 c = h->cmd_pool + tag_index;
4735 finish_cmd(c);
4736 }
303932fd
DB		 4737}
4738
4739/* process completion of a non-indexed command */
1d94f94d 4740static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4741 u32 raw_tag)
4742{
4743 u32 tag;
4744 struct CommandList *c = NULL;
e16a33ad 4745 unsigned long flags;
303932fd 4746
a9a3a273 4747 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4748 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4749 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4750 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4751 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4752 finish_cmd(c);
1d94f94d 4753 return;
303932fd
DB		 4754 }
4755 }
e16a33ad 4756 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4757 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4758}
4759
64670ac8
SC		 4760/* Some controllers, like p400, will give us one interrupt
4761 * after a soft reset, even if we turned interrupts off.
4762 * Only need to check for this in the hpsa_xxx_discard_completions
4763 * functions.
4764 */
4765static int ignore_bogus_interrupt(struct ctlr_info *h)
4766{
4767 if (likely(!reset_devices))
4768 return 0;
4769
4770 if (likely(h->interrupts_enabled))
4771 return 0;
4772
4773 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4774 "(known firmware bug.) Ignoring.\n");
4775
4776 return 1;
4777}
4778
254f796b
MG		 4779/*
4780 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4781 * Relies on (h-q[x] == x) being true for x such that
4782 * 0 <= x < MAX_REPLY_QUEUES.
4783 */
4784static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4785{
254f796b
MG		 4786 return container_of((queue - *queue), struct ctlr_info, q[0]);
4787}
4788
4789static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4790{
4791 struct ctlr_info *h = queue_to_hba(queue);
4792 u8 q = *(u8 *) queue;
64670ac8
SC		 4793 u32 raw_tag;
4794
4795 if (ignore_bogus_interrupt(h))
4796 return IRQ_NONE;
4797
4798 if (interrupt_not_for_us(h))
4799 return IRQ_NONE;
a0c12413 4800 h->last_intr_timestamp = get_jiffies_64();
64670ac8 4801 while (interrupt_pending(h)) {
254f796b 4802 raw_tag = get_next_completion(h, q);
64670ac8 4803 while (raw_tag != FIFO_EMPTY)
254f796b 4804 raw_tag = next_command(h, q);
64670ac8 4805 }
64670ac8
SC		 4806 return IRQ_HANDLED;
4807}
4808
254f796b 4809static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 4810{
254f796b 4811 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 4812 u32 raw_tag;
254f796b 4813 u8 q = *(u8 *) queue;
64670ac8
SC		 4814
4815 if (ignore_bogus_interrupt(h))
4816 return IRQ_NONE;
4817
a0c12413 4818 h->last_intr_timestamp = get_jiffies_64();
254f796b 4819 raw_tag = get_next_completion(h, q);
64670ac8 4820 while (raw_tag != FIFO_EMPTY)
254f796b 4821 raw_tag = next_command(h, q);
64670ac8
SC		 4822 return IRQ_HANDLED;
4823}
4824
254f796b 4825static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 4826{
254f796b 4827 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 4828 u32 raw_tag;
254f796b 4829 u8 q = *(u8 *) queue;
edd16368
SC		 4830
4831 if (interrupt_not_for_us(h))
4832 return IRQ_NONE;
a0c12413 4833 h->last_intr_timestamp = get_jiffies_64();
10f66018 4834 while (interrupt_pending(h)) {
254f796b 4835 raw_tag = get_next_completion(h, q);
10f66018 4836 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4837 if (likely(hpsa_tag_contains_index(raw_tag)))
4838 process_indexed_cmd(h, raw_tag);
10f66018 4839 else
1d94f94d 4840 process_nonindexed_cmd(h, raw_tag);
254f796b 4841 raw_tag = next_command(h, q);
10f66018
SC		 4842 }
4843 }
10f66018
SC		 4844 return IRQ_HANDLED;
4845}
4846
254f796b 4847static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 4848{
254f796b 4849 struct ctlr_info *h = queue_to_hba(queue);
10f66018 4850 u32 raw_tag;
254f796b 4851 u8 q = *(u8 *) queue;
10f66018 4852
a0c12413 4853 h->last_intr_timestamp = get_jiffies_64();
254f796b 4854 raw_tag = get_next_completion(h, q);
303932fd 4855 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4856 if (likely(hpsa_tag_contains_index(raw_tag)))
4857 process_indexed_cmd(h, raw_tag);
303932fd 4858 else
1d94f94d 4859 process_nonindexed_cmd(h, raw_tag);
254f796b 4860 raw_tag = next_command(h, q);
edd16368 4861 }
edd16368
SC		 4862 return IRQ_HANDLED;
4863}
4864
a9a3a273
SC		 4865/* Send a message CDB to the firmware. Careful, this only works
4866 * in simple mode, not performant mode due to the tag lookup.
4867 * We only ever use this immediately after a controller reset.
4868 */
6f039790
GKH		 4869static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
4870 unsigned char type)
edd16368
SC		 4871{
4872 struct Command {
4873 struct CommandListHeader CommandHeader;
4874 struct RequestBlock Request;
4875 struct ErrDescriptor ErrorDescriptor;
4876 };
4877 struct Command *cmd;
4878 static const size_t cmd_sz = sizeof(*cmd) +
4879 sizeof(cmd->ErrorDescriptor);
4880 dma_addr_t paddr64;
4881 uint32_t paddr32, tag;
4882 void __iomem *vaddr;
4883 int i, err;
4884
4885 vaddr = pci_ioremap_bar(pdev, 0);
4886 if (vaddr == NULL)
4887 return -ENOMEM;
4888
4889 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4890 * CCISS commands, so they must be allocated from the lower 4GiB of
4891 * memory.
4892 */
4893 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4894 if (err) {
4895 iounmap(vaddr);
4896 return -ENOMEM;
4897 }
4898
4899 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4900 if (cmd == NULL) {
4901 iounmap(vaddr);
4902 return -ENOMEM;
4903 }
4904
4905 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4906 * although there's no guarantee, we assume that the address is at
4907 * least 4-byte aligned (most likely, it's page-aligned).
4908 */
4909 paddr32 = paddr64;
4910
4911 cmd->CommandHeader.ReplyQueue = 0;
4912 cmd->CommandHeader.SGList = 0;
4913 cmd->CommandHeader.SGTotal = 0;
4914 cmd->CommandHeader.Tag.lower = paddr32;
4915 cmd->CommandHeader.Tag.upper = 0;
4916 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4917
4918 cmd->Request.CDBLen = 16;
4919 cmd->Request.Type.Type = TYPE_MSG;
4920 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4921 cmd->Request.Type.Direction = XFER_NONE;
4922 cmd->Request.Timeout = 0; /* Don't time out */
4923 cmd->Request.CDB[0] = opcode;
4924 cmd->Request.CDB[1] = type;
4925 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
4926 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
4927 cmd->ErrorDescriptor.Addr.upper = 0;
4928 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
4929
4930 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4931
4932 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
4933 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 4934 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 4935 break;
4936 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
4937 }
4938
4939 iounmap(vaddr);
4940
4941 /* we leak the DMA buffer here ... no choice since the controller could
4942 * still complete the command.
4943 */
4944 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
4945 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
4946 opcode, type);
4947 return -ETIMEDOUT;
4948 }
4949
4950 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4951
4952 if (tag & HPSA_ERROR_BIT) {
4953 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4954 opcode, type);
4955 return -EIO;
4956 }
4957
4958 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4959 opcode, type);
4960 return 0;
4961}
4962
edd16368
SC		 4963#define hpsa_noop(p) hpsa_message(p, 3, 0)
4964
1df8552a 4965static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 4966 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 4967{
4968 u16 pmcsr;
4969 int pos;
4970
4971 if (use_doorbell) {
4972 /* For everything after the P600, the PCI power state method
4973 * of resetting the controller doesn't work, so we have this
4974 * other way using the doorbell register.
4975 */
4976 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 4977 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 4978
4979 /* PMC hardware guys tell us we need a 5 second delay after
4980 * doorbell reset and before any attempt to talk to the board
4981 * at all to ensure that this actually works and doesn't fall
4982 * over in some weird corner cases.
4983 */
4984 msleep(5000);
1df8552a
SC		 4985 } else { /* Try to do it the PCI power state way */
4986
4987 /* Quoting from the Open CISS Specification: "The Power
4988 * Management Control/Status Register (CSR) controls the power
4989 * state of the device. The normal operating state is D0,
4990 * CSR=00h. The software off state is D3, CSR=03h. To reset
4991 * the controller, place the interface device in D3 then to D0,
4992 * this causes a secondary PCI reset which will reset the
4993 * controller." */
4994
4995 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4996 if (pos == 0) {
4997 dev_err(&pdev->dev,
4998 "hpsa_reset_controller: "
4999 "PCI PM not supported\n");
5000 return -ENODEV;
5001 }
5002 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5003 /* enter the D3hot power management state */
5004 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5005 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5006 pmcsr |= PCI_D3hot;
5007 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5008
5009 msleep(500);
5010
5011 /* enter the D0 power management state */
5012 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5013 pmcsr |= PCI_D0;
5014 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5015
5016 /*
5017 * The P600 requires a small delay when changing states.
5018 * Otherwise we may think the board did not reset and we bail.
5019 * This for kdump only and is particular to the P600.
5020 */
5021 msleep(500);
1df8552a
SC		 5022 }
5023 return 0;
5024}
5025
6f039790 5026static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5027{
5028 memset(driver_version, 0, len);
f79cfec6 5029 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5030}
5031
6f039790 5032static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5033{
5034 char *driver_version;
5035 int i, size = sizeof(cfgtable->driver_version);
5036
5037 driver_version = kmalloc(size, GFP_KERNEL);
5038 if (!driver_version)
5039 return -ENOMEM;
5040
5041 init_driver_version(driver_version, size);
5042 for (i = 0; i < size; i++)
5043 writeb(driver_version[i], &cfgtable->driver_version[i]);
5044 kfree(driver_version);
5045 return 0;
5046}
5047
6f039790
GKH		 5048static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5049 unsigned char *driver_ver)
580ada3c
SC		 5050{
5051 int i;
5052
5053 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5054 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5055}
5056
6f039790 5057static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5058{
5059
5060 char *driver_ver, *old_driver_ver;
5061 int rc, size = sizeof(cfgtable->driver_version);
5062
5063 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5064 if (!old_driver_ver)
5065 return -ENOMEM;
5066 driver_ver = old_driver_ver + size;
5067
5068 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5069 * should have been changed, otherwise we know the reset failed.
5070 */
5071 init_driver_version(old_driver_ver, size);
5072 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5073 rc = !memcmp(driver_ver, old_driver_ver, size);
5074 kfree(old_driver_ver);
5075 return rc;
5076}
edd16368 5077/* This does a hard reset of the controller using PCI power management
1df8552a 5078 * states or the using the doorbell register.
edd16368 5079 */
6f039790 5080static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5081{
1df8552a
SC		 5082 u64 cfg_offset;
5083 u32 cfg_base_addr;
5084 u64 cfg_base_addr_index;
5085 void __iomem *vaddr;
5086 unsigned long paddr;
580ada3c 5087 u32 misc_fw_support;
270d05de 5088 int rc;
1df8552a 5089 struct CfgTable __iomem *cfgtable;
cf0b08d0 5090 u32 use_doorbell;
18867659 5091 u32 board_id;
270d05de 5092 u16 command_register;
edd16368 5093
1df8552a
SC		 5094 /* For controllers as old as the P600, this is very nearly
5095 * the same thing as
edd16368
SC		 5096 *
5097 * pci_save_state(pci_dev);
5098 * pci_set_power_state(pci_dev, PCI_D3hot);
5099 * pci_set_power_state(pci_dev, PCI_D0);
5100 * pci_restore_state(pci_dev);
5101 *
1df8552a
SC		 5102 * For controllers newer than the P600, the pci power state
5103 * method of resetting doesn't work so we have another way
5104 * using the doorbell register.
edd16368 5105 */
18867659 5106
25c1e56a 5107 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5108 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5109 dev_warn(&pdev->dev, "Not resetting device.\n");
5110 return -ENODEV;
5111 }
46380786
SC		 5112
5113 /* if controller is soft- but not hard resettable... */
5114 if (!ctlr_is_hard_resettable(board_id))
5115 return -ENOTSUPP; /* try soft reset later. */
18867659 5116
270d05de
SC		 5117 /* Save the PCI command register */
5118 pci_read_config_word(pdev, 4, &command_register);
5119 /* Turn the board off. This is so that later pci_restore_state()
5120 * won't turn the board on before the rest of config space is ready.
5121 */
5122 pci_disable_device(pdev);
5123 pci_save_state(pdev);
edd16368 5124
1df8552a
SC		 5125 /* find the first memory BAR, so we can find the cfg table */
5126 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5127 if (rc)
5128 return rc;
5129 vaddr = remap_pci_mem(paddr, 0x250);
5130 if (!vaddr)
5131 return -ENOMEM;
edd16368 5132
1df8552a
SC		 5133 /* find cfgtable in order to check if reset via doorbell is supported */
5134 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5135 &cfg_base_addr_index, &cfg_offset);
5136 if (rc)
5137 goto unmap_vaddr;
5138 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5139 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5140 if (!cfgtable) {
5141 rc = -ENOMEM;
5142 goto unmap_vaddr;
5143 }
580ada3c
SC		 5144 rc = write_driver_ver_to_cfgtable(cfgtable);
5145 if (rc)
5146 goto unmap_vaddr;
edd16368 5147
cf0b08d0
SC		 5148 /* If reset via doorbell register is supported, use that.
5149 * There are two such methods. Favor the newest method.
5150 */
1df8552a 5151 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5152 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5153 if (use_doorbell) {
5154 use_doorbell = DOORBELL_CTLR_RESET2;
5155 } else {
5156 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5157 if (use_doorbell) {
fba63097
MM		 5158 dev_warn(&pdev->dev, "Soft reset not supported. "
5159 "Firmware update is required.\n");
64670ac8 5160 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5161 goto unmap_cfgtable;
5162 }
5163 }
edd16368 5164
1df8552a
SC		 5165 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5166 if (rc)
5167 goto unmap_cfgtable;
edd16368 5168
270d05de
SC		 5169 pci_restore_state(pdev);
5170 rc = pci_enable_device(pdev);
5171 if (rc) {
5172 dev_warn(&pdev->dev, "failed to enable device.\n");
5173 goto unmap_cfgtable;
edd16368 5174 }
270d05de 5175 pci_write_config_word(pdev, 4, command_register);
edd16368 5176
1df8552a
SC		 5177 /* Some devices (notably the HP Smart Array 5i Controller)
5178 need a little pause here */
5179 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5180
fe5389c8
SC		 5181 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5182 if (rc) {
5183 dev_warn(&pdev->dev,
64670ac8
SC		 5184 "failed waiting for board to become ready "
5185 "after hard reset\n");
fe5389c8
SC		 5186 goto unmap_cfgtable;
5187 }
fe5389c8 5188
580ada3c
SC		 5189 rc = controller_reset_failed(vaddr);
5190 if (rc < 0)
5191 goto unmap_cfgtable;
5192 if (rc) {
64670ac8
SC		 5193 dev_warn(&pdev->dev, "Unable to successfully reset "
5194 "controller. Will try soft reset.\n");
5195 rc = -ENOTSUPP;
580ada3c 5196 } else {
64670ac8 5197 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5198 }
5199
5200unmap_cfgtable:
5201 iounmap(cfgtable);
5202
5203unmap_vaddr:
5204 iounmap(vaddr);
5205 return rc;
edd16368
SC		 5206}
5207
5208/*
5209 * We cannot read the structure directly, for portability we must use
5210 * the io functions.
5211 * This is for debug only.
5212 */
edd16368
SC		 5213static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5214{
58f8665c 5215#ifdef HPSA_DEBUG
edd16368
SC		 5216 int i;
5217 char temp_name[17];
5218
5219 dev_info(dev, "Controller Configuration information\n");
5220 dev_info(dev, "------------------------------------\n");
5221 for (i = 0; i < 4; i++)
5222 temp_name[i] = readb(&(tb->Signature[i]));
5223 temp_name[4] = '\0';
5224 dev_info(dev, " Signature = %s\n", temp_name);
5225 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5226 dev_info(dev, " Transport methods supported = 0x%x\n",
5227 readl(&(tb->TransportSupport)));
5228 dev_info(dev, " Transport methods active = 0x%x\n",
5229 readl(&(tb->TransportActive)));
5230 dev_info(dev, " Requested transport Method = 0x%x\n",
5231 readl(&(tb->HostWrite.TransportRequest)));
5232 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5233 readl(&(tb->HostWrite.CoalIntDelay)));
5234 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5235 readl(&(tb->HostWrite.CoalIntCount)));
5236 dev_info(dev, " Max outstanding commands = 0x%d\n",
5237 readl(&(tb->CmdsOutMax)));
5238 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5239 for (i = 0; i < 16; i++)
5240 temp_name[i] = readb(&(tb->ServerName[i]));
5241 temp_name[16] = '\0';
5242 dev_info(dev, " Server Name = %s\n", temp_name);
5243 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5244 readl(&(tb->HeartBeat)));
edd16368 5245#endif /* HPSA_DEBUG */
58f8665c 5246}
edd16368
SC		 5247
5248static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5249{
5250 int i, offset, mem_type, bar_type;
5251
5252 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5253 return 0;
5254 offset = 0;
5255 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5256 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5257 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5258 offset += 4;
5259 else {
5260 mem_type = pci_resource_flags(pdev, i) &
5261 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5262 switch (mem_type) {
5263 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5264 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5265 offset += 4; /* 32 bit */
5266 break;
5267 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5268 offset += 8;
5269 break;
5270 default: /* reserved in PCI 2.2 */
5271 dev_warn(&pdev->dev,
5272 "base address is invalid\n");
5273 return -1;
5274 break;
5275 }
5276 }
5277 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5278 return i + 1;
5279 }
5280 return -1;
5281}
5282
5283/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5284 * controllers that are capable. If not, we use IO-APIC mode.
5285 */
5286
6f039790 5287static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5288{
5289#ifdef CONFIG_PCI_MSI
254f796b
MG		 5290 int err, i;
5291 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5292
5293 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5294 hpsa_msix_entries[i].vector = 0;
5295 hpsa_msix_entries[i].entry = i;
5296 }
edd16368
SC		 5297
5298 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5299 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5300 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5301 goto default_int_mode;
55c06c71
SC		 5302 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5303 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5304 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5305 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5306 h->msix_vector);
edd16368 5307 if (err > 0) {
55c06c71 5308 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5309 "available\n", err);
eee0f03a
HR		 5310 h->msix_vector = err;
5311 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5312 h->msix_vector);
5313 }
5314 if (!err) {
5315 for (i = 0; i < h->msix_vector; i++)
5316 h->intr[i] = hpsa_msix_entries[i].vector;
5317 return;
edd16368 5318 } else {
55c06c71 5319 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5320 err);
eee0f03a 5321 h->msix_vector = 0;
edd16368
SC		 5322 goto default_int_mode;
5323 }
5324 }
55c06c71
SC		 5325 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5326 dev_info(&h->pdev->dev, "MSI\n");
5327 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5328 h->msi_vector = 1;
5329 else
55c06c71 5330 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5331 }
5332default_int_mode:
5333#endif /* CONFIG_PCI_MSI */
5334 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5335 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5336}
5337
6f039790 5338static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5339{
5340 int i;
5341 u32 subsystem_vendor_id, subsystem_device_id;
5342
5343 subsystem_vendor_id = pdev->subsystem_vendor;
5344 subsystem_device_id = pdev->subsystem_device;
5345 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5346 subsystem_vendor_id;
5347
5348 for (i = 0; i < ARRAY_SIZE(products); i++)
5349 if (*board_id == products[i].board_id)
5350 return i;
5351
6798cc0a
SC		 5352 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5353 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5354 !hpsa_allow_any) {
e5c880d1
SC		 5355 dev_warn(&pdev->dev, "unrecognized board ID: "
5356 "0x%08x, ignoring.\n", *board_id);
5357 return -ENODEV;
5358 }
5359 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5360}
5361
6f039790
GKH		 5362static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5363 unsigned long *memory_bar)
3a7774ce
SC		 5364{
5365 int i;
5366
5367 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5368 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5369 /* addressing mode bits already removed */
12d2cd47
SC		 5370 *memory_bar = pci_resource_start(pdev, i);
5371 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5372 *memory_bar);
5373 return 0;
5374 }
12d2cd47 5375 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5376 return -ENODEV;
5377}
5378
6f039790
GKH		 5379static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5380 int wait_for_ready)
2c4c8c8b 5381{
fe5389c8 5382 int i, iterations;
2c4c8c8b 5383 u32 scratchpad;
fe5389c8
SC		 5384 if (wait_for_ready)
5385 iterations = HPSA_BOARD_READY_ITERATIONS;
5386 else
5387 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5388
fe5389c8
SC		 5389 for (i = 0; i < iterations; i++) {
5390 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5391 if (wait_for_ready) {
5392 if (scratchpad == HPSA_FIRMWARE_READY)
5393 return 0;
5394 } else {
5395 if (scratchpad != HPSA_FIRMWARE_READY)
5396 return 0;
5397 }
2c4c8c8b
SC		 5398 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5399 }
fe5389c8 5400 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5401 return -ENODEV;
5402}
5403
6f039790
GKH		 5404static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5405 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5406 u64 *cfg_offset)
a51fd47f
SC		 5407{
5408 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5409 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5410 *cfg_base_addr &= (u32) 0x0000ffff;
5411 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5412 if (*cfg_base_addr_index == -1) {
5413 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5414 return -ENODEV;
5415 }
5416 return 0;
5417}
5418
6f039790 5419static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5420{
01a02ffc
SC		 5421 u64 cfg_offset;
5422 u32 cfg_base_addr;
5423 u64 cfg_base_addr_index;
303932fd 5424 u32 trans_offset;
a51fd47f 5425 int rc;
77c4495c 5426
a51fd47f
SC		 5427 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5428 &cfg_base_addr_index, &cfg_offset);
5429 if (rc)
5430 return rc;
77c4495c 5431 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5432 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5433 if (!h->cfgtable)
5434 return -ENOMEM;
580ada3c
SC		 5435 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5436 if (rc)
5437 return rc;
77c4495c 5438 /* Find performant mode table. */
a51fd47f 5439 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5440 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5441 cfg_base_addr_index)+cfg_offset+trans_offset,
5442 sizeof(*h->transtable));
5443 if (!h->transtable)
5444 return -ENOMEM;
5445 return 0;
5446}
5447
6f039790 5448static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5449{
5450 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5451
5452 /* Limit commands in memory limited kdump scenario. */
5453 if (reset_devices && h->max_commands > 32)
5454 h->max_commands = 32;
5455
cba3d38b
SC		 5456 if (h->max_commands < 16) {
5457 dev_warn(&h->pdev->dev, "Controller reports "
5458 "max supported commands of %d, an obvious lie. "
5459 "Using 16. Ensure that firmware is up to date.\n",
5460 h->max_commands);
5461 h->max_commands = 16;
5462 }
5463}
5464
b93d7536
SC		 5465/* Interrogate the hardware for some limits:
5466 * max commands, max SG elements without chaining, and with chaining,
5467 * SG chain block size, etc.
5468 */
6f039790 5469static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5470{
cba3d38b 5471 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5472 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5473 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5474 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5475 /*
5476 * Limit in-command s/g elements to 32 save dma'able memory.
5477 * Howvever spec says if 0, use 31
5478 */
5479 h->max_cmd_sg_entries = 31;
5480 if (h->maxsgentries > 512) {
5481 h->max_cmd_sg_entries = 32;
5482 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5483 h->maxsgentries--; /* save one for chain pointer */
5484 } else {
5485 h->maxsgentries = 31; /* default to traditional values */
5486 h->chainsize = 0;
5487 }
75167d2c
SC		 5488
5489 /* Find out what task management functions are supported and cache */
5490 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5491 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5492 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5493 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5494 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5495}
5496
76c46e49
SC		 5497static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5498{
0fc9fd40 5499 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5500 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5501 return false;
5502 }
5503 return true;
5504}
5505
97a5e98c 5506static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5507{
97a5e98c 5508 u32 driver_support;
f7c39101 5509
28e13446
SC		 5510#ifdef CONFIG_X86
5511 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5512 driver_support = readl(&(h->cfgtable->driver_support));
5513 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5514#endif
28e13446
SC		 5515 driver_support |= ENABLE_UNIT_ATTN;
5516 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5517}
5518
3d0eab67
SC		 5519/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5520 * in a prefetch beyond physical memory.
5521 */
5522static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5523{
5524 u32 dma_prefetch;
5525
5526 if (h->board_id != 0x3225103C)
5527 return;
5528 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5529 dma_prefetch |= 0x8000;
5530 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5531}
5532
76438d08
SC		 5533static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5534{
5535 int i;
5536 u32 doorbell_value;
5537 unsigned long flags;
5538 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5539 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5540 spin_lock_irqsave(&h->lock, flags);
5541 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5542 spin_unlock_irqrestore(&h->lock, flags);
5543 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5544 break;
5545 /* delay and try again */
5546 msleep(20);
5547 }
5548}
5549
6f039790 5550static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5551{
5552 int i;
6eaf46fd
SC		 5553 u32 doorbell_value;
5554 unsigned long flags;
eb6b2ae9
SC		 5555
5556 /* under certain very rare conditions, this can take awhile.
5557 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5558 * as we enter this code.)
5559 */
5560 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5561 spin_lock_irqsave(&h->lock, flags);
5562 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5563 spin_unlock_irqrestore(&h->lock, flags);
382be668 5564 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5565 break;
5566 /* delay and try again */
60d3f5b0 5567 usleep_range(10000, 20000);
eb6b2ae9 5568 }
3f4336f3
SC		 5569}
5570
6f039790 5571static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5572{
5573 u32 trans_support;
5574
5575 trans_support = readl(&(h->cfgtable->TransportSupport));
5576 if (!(trans_support & SIMPLE_MODE))
5577 return -ENOTSUPP;
5578
5579 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5580
3f4336f3
SC		 5581 /* Update the field, and then ring the doorbell */
5582 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 5583 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 5584 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5585 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5586 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5587 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5588 goto error;
960a30e7 5589 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5590 return 0;
283b4a9b
SC		 5591error:
5592 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5593 return -ENODEV;
eb6b2ae9
SC		 5594}
5595
6f039790 5596static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5597{
eb6b2ae9 5598 int prod_index, err;
edd16368 5599
e5c880d1
SC		 5600 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5601 if (prod_index < 0)
5602 return -ENODEV;
5603 h->product_name = products[prod_index].product_name;
5604 h->access = *(products[prod_index].access);
edd16368 5605
e5a44df8
MG		 5606 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5607 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5608
55c06c71 5609 err = pci_enable_device(h->pdev);
edd16368 5610 if (err) {
55c06c71 5611 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5612 return err;
5613 }
5614
5cb460a6
SC		 5615 /* Enable bus mastering (pci_disable_device may disable this) */
5616 pci_set_master(h->pdev);
5617
f79cfec6 5618 err = pci_request_regions(h->pdev, HPSA);
edd16368 5619 if (err) {
55c06c71
SC		 5620 dev_err(&h->pdev->dev,
5621 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5622 return err;
5623 }
6b3f4c52 5624 hpsa_interrupt_mode(h);
12d2cd47 5625 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5626 if (err)
edd16368 5627 goto err_out_free_res;
edd16368 5628 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5629 if (!h->vaddr) {
5630 err = -ENOMEM;
5631 goto err_out_free_res;
5632 }
fe5389c8 5633 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5634 if (err)
edd16368 5635 goto err_out_free_res;
77c4495c
SC		 5636 err = hpsa_find_cfgtables(h);
5637 if (err)
edd16368 5638 goto err_out_free_res;
b93d7536 5639 hpsa_find_board_params(h);
edd16368 5640
76c46e49 5641 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5642 err = -ENODEV;
5643 goto err_out_free_res;
5644 }
97a5e98c 5645 hpsa_set_driver_support_bits(h);
3d0eab67 5646 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5647 err = hpsa_enter_simple_mode(h);
5648 if (err)
edd16368 5649 goto err_out_free_res;
edd16368
SC		 5650 return 0;
5651
5652err_out_free_res:
204892e9
SC		 5653 if (h->transtable)
5654 iounmap(h->transtable);
5655 if (h->cfgtable)
5656 iounmap(h->cfgtable);
5657 if (h->vaddr)
5658 iounmap(h->vaddr);
f0bd0b68 5659 pci_disable_device(h->pdev);
55c06c71 5660 pci_release_regions(h->pdev);
edd16368
SC		 5661 return err;
5662}
5663
6f039790 5664static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5665{
5666 int rc;
5667
5668#define HBA_INQUIRY_BYTE_COUNT 64
5669 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5670 if (!h->hba_inquiry_data)
5671 return;
5672 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5673 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5674 if (rc != 0) {
5675 kfree(h->hba_inquiry_data);
5676 h->hba_inquiry_data = NULL;
5677 }
5678}
5679
6f039790 5680static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5681{
1df8552a 5682 int rc, i;
4c2a8c40
SC		 5683
5684 if (!reset_devices)
5685 return 0;
5686
1df8552a
SC		 5687 /* Reset the controller with a PCI power-cycle or via doorbell */
5688 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5689
1df8552a
SC		 5690 /* -ENOTSUPP here means we cannot reset the controller
5691 * but it's already (and still) up and running in
18867659
SC		 5692 * "performant mode". Or, it might be 640x, which can't reset
5693 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5694 */
5695 if (rc == -ENOTSUPP)
64670ac8 5696 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5697 if (rc)
5698 return -ENODEV;
4c2a8c40
SC		 5699
5700 /* Now try to get the controller to respond to a no-op */
2b870cb3 5701 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5702 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5703 if (hpsa_noop(pdev) == 0)
5704 break;
5705 else
5706 dev_warn(&pdev->dev, "no-op failed%s\n",
5707 (i < 11 ? "; re-trying" : ""));
5708 }
5709 return 0;
5710}
5711
6f039790 5712static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5713{
5714 h->cmd_pool_bits = kzalloc(
5715 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5716 sizeof(unsigned long), GFP_KERNEL);
5717 h->cmd_pool = pci_alloc_consistent(h->pdev,
5718 h->nr_cmds * sizeof(*h->cmd_pool),
5719 &(h->cmd_pool_dhandle));
5720 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5721 h->nr_cmds * sizeof(*h->errinfo_pool),
5722 &(h->errinfo_pool_dhandle));
5723 if ((h->cmd_pool_bits == NULL)
5724 || (h->cmd_pool == NULL)
5725 || (h->errinfo_pool == NULL)) {
5726 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5727 return -ENOMEM;
5728 }
5729 return 0;
5730}
5731
5732static void hpsa_free_cmd_pool(struct ctlr_info *h)
5733{
5734 kfree(h->cmd_pool_bits);
5735 if (h->cmd_pool)
5736 pci_free_consistent(h->pdev,
5737 h->nr_cmds * sizeof(struct CommandList),
5738 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 5739 if (h->ioaccel2_cmd_pool)
5740 pci_free_consistent(h->pdev,
5741 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
5742 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 5743 if (h->errinfo_pool)
5744 pci_free_consistent(h->pdev,
5745 h->nr_cmds * sizeof(struct ErrorInfo),
5746 h->errinfo_pool,
5747 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5748 if (h->ioaccel_cmd_pool)
5749 pci_free_consistent(h->pdev,
5750 h->nr_cmds * sizeof(struct io_accel1_cmd),
5751 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5752}
5753
0ae01a32
SC		 5754static int hpsa_request_irq(struct ctlr_info *h,
5755 irqreturn_t (*msixhandler)(int, void *),
5756 irqreturn_t (*intxhandler)(int, void *))
5757{
254f796b 5758 int rc, i;
0ae01a32 5759
254f796b
MG		 5760 /*
5761 * initialize h->q[x] = x so that interrupt handlers know which
5762 * queue to process.
5763 */
5764 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5765 h->q[i] = (u8) i;
5766
eee0f03a 5767 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5768 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5769 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5770 rc = request_irq(h->intr[i], msixhandler,
5771 0, h->devname,
5772 &h->q[i]);
5773 } else {
5774 /* Use single reply pool */
eee0f03a 5775 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5776 rc = request_irq(h->intr[h->intr_mode],
5777 msixhandler, 0, h->devname,
5778 &h->q[h->intr_mode]);
5779 } else {
5780 rc = request_irq(h->intr[h->intr_mode],
5781 intxhandler, IRQF_SHARED, h->devname,
5782 &h->q[h->intr_mode]);
5783 }
5784 }
0ae01a32
SC		 5785 if (rc) {
5786 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5787 h->intr[h->intr_mode], h->devname);
5788 return -ENODEV;
5789 }
5790 return 0;
5791}
5792
6f039790 5793static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5794{
5795 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
5796 HPSA_RESET_TYPE_CONTROLLER)) {
5797 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
5798 return -EIO;
5799 }
5800
5801 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
5802 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
5803 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
5804 return -1;
5805 }
5806
5807 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
5808 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
5809 dev_warn(&h->pdev->dev, "Board failed to become ready "
5810 "after soft reset.\n");
5811 return -1;
5812 }
5813
5814 return 0;
5815}
5816
254f796b
MG		 5817static void free_irqs(struct ctlr_info *h)
5818{
5819 int i;
5820
5821 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
5822 /* Single reply queue, only one irq to free */
5823 i = h->intr_mode;
5824 free_irq(h->intr[i], &h->q[i]);
5825 return;
5826 }
5827
eee0f03a 5828 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5829 free_irq(h->intr[i], &h->q[i]);
5830}
5831
0097f0f4 5832static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 5833{
254f796b 5834 free_irqs(h);
64670ac8 5835#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 5836 if (h->msix_vector) {
5837 if (h->pdev->msix_enabled)
5838 pci_disable_msix(h->pdev);
5839 } else if (h->msi_vector) {
5840 if (h->pdev->msi_enabled)
5841 pci_disable_msi(h->pdev);
5842 }
64670ac8 5843#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 5844}
5845
5846static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
5847{
5848 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 5849 hpsa_free_sg_chain_blocks(h);
5850 hpsa_free_cmd_pool(h);
e1f7de0c 5851 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 5852 kfree(h->blockFetchTable);
5853 pci_free_consistent(h->pdev, h->reply_pool_size,
5854 h->reply_pool, h->reply_pool_dhandle);
5855 if (h->vaddr)
5856 iounmap(h->vaddr);
5857 if (h->transtable)
5858 iounmap(h->transtable);
5859 if (h->cfgtable)
5860 iounmap(h->cfgtable);
5861 pci_release_regions(h->pdev);
5862 kfree(h);
5863}
5864
a0c12413
SC		 5865/* Called when controller lockup detected. */
5866static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
5867{
5868 struct CommandList *c = NULL;
5869
5870 assert_spin_locked(&h->lock);
5871 /* Mark all outstanding commands as failed and complete them. */
5872 while (!list_empty(list)) {
5873 c = list_entry(list->next, struct CommandList, list);
5874 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 5875 finish_cmd(c);
a0c12413
SC		 5876 }
5877}
5878
5879static void controller_lockup_detected(struct ctlr_info *h)
5880{
5881 unsigned long flags;
5882
a0c12413
SC		 5883 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5884 spin_lock_irqsave(&h->lock, flags);
5885 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
5886 spin_unlock_irqrestore(&h->lock, flags);
5887 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
5888 h->lockup_detected);
5889 pci_disable_device(h->pdev);
5890 spin_lock_irqsave(&h->lock, flags);
5891 fail_all_cmds_on_list(h, &h->cmpQ);
5892 fail_all_cmds_on_list(h, &h->reqQ);
5893 spin_unlock_irqrestore(&h->lock, flags);
5894}
5895
a0c12413
SC		 5896static void detect_controller_lockup(struct ctlr_info *h)
5897{
5898 u64 now;
5899 u32 heartbeat;
5900 unsigned long flags;
5901
a0c12413
SC		 5902 now = get_jiffies_64();
5903 /* If we've received an interrupt recently, we're ok. */
5904 if (time_after64(h->last_intr_timestamp +
e85c5974 5905 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5906 return;
5907
5908 /*
5909 * If we've already checked the heartbeat recently, we're ok.
5910 * This could happen if someone sends us a signal. We
5911 * otherwise don't care about signals in this thread.
5912 */
5913 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 5914 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5915 return;
5916
5917 /* If heartbeat has not changed since we last looked, we're not ok. */
5918 spin_lock_irqsave(&h->lock, flags);
5919 heartbeat = readl(&h->cfgtable->HeartBeat);
5920 spin_unlock_irqrestore(&h->lock, flags);
5921 if (h->last_heartbeat == heartbeat) {
5922 controller_lockup_detected(h);
5923 return;
5924 }
5925
5926 /* We're ok. */
5927 h->last_heartbeat = heartbeat;
5928 h->last_heartbeat_timestamp = now;
5929}
5930
76438d08
SC		 5931static int hpsa_kickoff_rescan(struct ctlr_info *h)
5932{
5933 int i;
5934 char *event_type;
5935
5936 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 5937 if ((h->transMethod & (CFGTBL_Trans_io_accel1
5938 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 5939 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
5940 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
5941
5942 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
5943 event_type = "state change";
5944 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
5945 event_type = "configuration change";
5946 /* Stop sending new RAID offload reqs via the IO accelerator */
5947 scsi_block_requests(h->scsi_host);
5948 for (i = 0; i < h->ndevices; i++)
5949 h->dev[i]->offload_enabled = 0;
5950 hpsa_drain_commands(h);
5951 /* Set 'accelerator path config change' bit */
5952 dev_warn(&h->pdev->dev,
5953 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
5954 h->events, event_type);
5955 writel(h->events, &(h->cfgtable->clear_event_notify));
5956 /* Set the "clear event notify field update" bit 6 */
5957 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
5958 /* Wait until ctlr clears 'clear event notify field', bit 6 */
5959 hpsa_wait_for_clear_event_notify_ack(h);
5960 scsi_unblock_requests(h->scsi_host);
5961 } else {
5962 /* Acknowledge controller notification events. */
5963 writel(h->events, &(h->cfgtable->clear_event_notify));
5964 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
5965 hpsa_wait_for_clear_event_notify_ack(h);
5966#if 0
5967 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5968 hpsa_wait_for_mode_change_ack(h);
5969#endif
5970 }
5971
5972 /* Something in the device list may have changed to trigger
5973 * the event, so do a rescan.
5974 */
5975 hpsa_scan_start(h->scsi_host);
5976 /* release reference taken on scsi host in check_controller_events */
5977 scsi_host_put(h->scsi_host);
5978 return 0;
5979}
5980
5981/* Check a register on the controller to see if there are configuration
5982 * changes (added/changed/removed logical drives, etc.) which mean that
5983 * we should rescan the controller for devices. If so, add the controller
5984 * to the list of controllers needing to be rescanned, and gets a
5985 * reference to the associated scsi_host.
5986 */
5987static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
5988{
5989 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
5990 return;
5991
5992 h->events = readl(&(h->cfgtable->event_notify));
5993 if (!h->events)
5994 return;
5995
5996 /*
5997 * Take a reference on scsi host for the duration of the scan
5998 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
5999 * as only a single thread accesses this list.
6000 */
6001 scsi_host_get(h->scsi_host);
6002 hpsa_kickoff_rescan(h);
6003}
6004
8a98db73 6005static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6006{
6007 unsigned long flags;
8a98db73
SC		 6008 struct ctlr_info *h = container_of(to_delayed_work(work),
6009 struct ctlr_info, monitor_ctlr_work);
6010 detect_controller_lockup(h);
6011 if (h->lockup_detected)
6012 return;
76438d08 6013 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6014 spin_lock_irqsave(&h->lock, flags);
6015 if (h->remove_in_progress) {
6016 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6017 return;
6018 }
8a98db73
SC		 6019 schedule_delayed_work(&h->monitor_ctlr_work,
6020 h->heartbeat_sample_interval);
6021 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6022}
6023
6f039790 6024static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6025{
4c2a8c40 6026 int dac, rc;
edd16368 6027 struct ctlr_info *h;
64670ac8
SC		 6028 int try_soft_reset = 0;
6029 unsigned long flags;
edd16368
SC		 6030
6031 if (number_of_controllers == 0)
6032 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6033
4c2a8c40 6034 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6035 if (rc) {
6036 if (rc != -ENOTSUPP)
6037 return rc;
6038 /* If the reset fails in a particular way (it has no way to do
6039 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6040 * a soft reset once we get the controller configured up to the
6041 * point that it can accept a command.
6042 */
6043 try_soft_reset = 1;
6044 rc = 0;
6045 }
6046
6047reinit_after_soft_reset:
edd16368 6048
303932fd
DB		 6049 /* Command structures must be aligned on a 32-byte boundary because
6050 * the 5 lower bits of the address are used by the hardware. and by
6051 * the driver. See comments in hpsa.h for more info.
6052 */
283b4a9b 6053#define COMMANDLIST_ALIGNMENT 128
303932fd 6054 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6055 h = kzalloc(sizeof(*h), GFP_KERNEL);
6056 if (!h)
ecd9aad4 6057 return -ENOMEM;
edd16368 6058
55c06c71 6059 h->pdev = pdev;
a9a3a273 6060 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6061 INIT_LIST_HEAD(&h->cmpQ);
6062 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6063 spin_lock_init(&h->lock);
6064 spin_lock_init(&h->scan_lock);
0390f0c0 6065 spin_lock_init(&h->passthru_count_lock);
55c06c71 6066 rc = hpsa_pci_init(h);
ecd9aad4 6067 if (rc != 0)
edd16368
SC		 6068 goto clean1;
6069
f79cfec6 6070 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6071 h->ctlr = number_of_controllers;
6072 number_of_controllers++;
edd16368
SC		 6073
6074 /* configure PCI DMA stuff */
ecd9aad4
SC		 6075 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6076 if (rc == 0) {
edd16368 6077 dac = 1;
ecd9aad4
SC		 6078 } else {
6079 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6080 if (rc == 0) {
6081 dac = 0;
6082 } else {
6083 dev_err(&pdev->dev, "no suitable DMA available\n");
6084 goto clean1;
6085 }
edd16368
SC		 6086 }
6087
6088 /* make sure the board interrupts are off */
6089 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6090
0ae01a32 6091 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6092 goto clean2;
303932fd
DB		 6093 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6094 h->devname, pdev->device,
a9a3a273 6095 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6096 if (hpsa_allocate_cmd_pool(h))
edd16368 6097 goto clean4;
33a2ffce
SC		 6098 if (hpsa_allocate_sg_chain_blocks(h))
6099 goto clean4;
a08a8471
SC		 6100 init_waitqueue_head(&h->scan_wait_queue);
6101 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6102
6103 pci_set_drvdata(pdev, h);
9a41338e
SC		 6104 h->ndevices = 0;
6105 h->scsi_host = NULL;
6106 spin_lock_init(&h->devlock);
64670ac8
SC		 6107 hpsa_put_ctlr_into_performant_mode(h);
6108
6109 /* At this point, the controller is ready to take commands.
6110 * Now, if reset_devices and the hard reset didn't work, try
6111 * the soft reset and see if that works.
6112 */
6113 if (try_soft_reset) {
6114
6115 /* This is kind of gross. We may or may not get a completion
6116 * from the soft reset command, and if we do, then the value
6117 * from the fifo may or may not be valid. So, we wait 10 secs
6118 * after the reset throwing away any completions we get during
6119 * that time. Unregister the interrupt handler and register
6120 * fake ones to scoop up any residual completions.
6121 */
6122 spin_lock_irqsave(&h->lock, flags);
6123 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6124 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6125 free_irqs(h);
64670ac8
SC		 6126 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6127 hpsa_intx_discard_completions);
6128 if (rc) {
6129 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6130 "soft reset.\n");
6131 goto clean4;
6132 }
6133
6134 rc = hpsa_kdump_soft_reset(h);
6135 if (rc)
6136 /* Neither hard nor soft reset worked, we're hosed. */
6137 goto clean4;
6138
6139 dev_info(&h->pdev->dev, "Board READY.\n");
6140 dev_info(&h->pdev->dev,
6141 "Waiting for stale completions to drain.\n");
6142 h->access.set_intr_mask(h, HPSA_INTR_ON);
6143 msleep(10000);
6144 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6145
6146 rc = controller_reset_failed(h->cfgtable);
6147 if (rc)
6148 dev_info(&h->pdev->dev,
6149 "Soft reset appears to have failed.\n");
6150
6151 /* since the controller's reset, we have to go back and re-init
6152 * everything. Easiest to just forget what we've done and do it
6153 * all over again.
6154 */
6155 hpsa_undo_allocations_after_kdump_soft_reset(h);
6156 try_soft_reset = 0;
6157 if (rc)
6158 /* don't go to clean4, we already unallocated */
6159 return -ENODEV;
6160
6161 goto reinit_after_soft_reset;
6162 }
edd16368
SC		 6163
6164 /* Turn the interrupts on so we can service requests */
6165 h->access.set_intr_mask(h, HPSA_INTR_ON);
6166
339b2b14 6167 hpsa_hba_inquiry(h);
edd16368 6168 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6169
6170 /* Monitor the controller for firmware lockups */
6171 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6172 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6173 schedule_delayed_work(&h->monitor_ctlr_work,
6174 h->heartbeat_sample_interval);
88bf6d62 6175 return 0;
edd16368
SC		 6176
6177clean4:
33a2ffce 6178 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6179 hpsa_free_cmd_pool(h);
254f796b 6180 free_irqs(h);
edd16368
SC		 6181clean2:
6182clean1:
edd16368 6183 kfree(h);
ecd9aad4 6184 return rc;
edd16368
SC		 6185}
6186
6187static void hpsa_flush_cache(struct ctlr_info *h)
6188{
6189 char *flush_buf;
6190 struct CommandList *c;
702890e3
SC		 6191 unsigned long flags;
6192
6193 /* Don't bother trying to flush the cache if locked up */
6194 spin_lock_irqsave(&h->lock, flags);
6195 if (unlikely(h->lockup_detected)) {
6196 spin_unlock_irqrestore(&h->lock, flags);
6197 return;
6198 }
6199 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6200
6201 flush_buf = kzalloc(4, GFP_KERNEL);
6202 if (!flush_buf)
6203 return;
6204
6205 c = cmd_special_alloc(h);
6206 if (!c) {
6207 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6208 goto out_of_memory;
6209 }
a2dac136
SC		 6210 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6211 RAID_CTLR_LUNID, TYPE_CMD)) {
6212 goto out;
6213 }
edd16368
SC		 6214 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6215 if (c->err_info->CommandStatus != 0)
a2dac136 6216out:
edd16368
SC		 6217 dev_warn(&h->pdev->dev,
6218 "error flushing cache on controller\n");
6219 cmd_special_free(h, c);
6220out_of_memory:
6221 kfree(flush_buf);
6222}
6223
6224static void hpsa_shutdown(struct pci_dev *pdev)
6225{
6226 struct ctlr_info *h;
6227
6228 h = pci_get_drvdata(pdev);
6229 /* Turn board interrupts off and send the flush cache command
6230 * sendcmd will turn off interrupt, and send the flush...
6231 * To write all data in the battery backed cache to disks
6232 */
6233 hpsa_flush_cache(h);
6234 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6235 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6236}
6237
6f039790 6238static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6239{
6240 int i;
6241
6242 for (i = 0; i < h->ndevices; i++)
6243 kfree(h->dev[i]);
6244}
6245
6f039790 6246static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6247{
6248 struct ctlr_info *h;
8a98db73 6249 unsigned long flags;
edd16368
SC		 6250
6251 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6252 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6253 return;
6254 }
6255 h = pci_get_drvdata(pdev);
8a98db73
SC		 6256
6257 /* Get rid of any controller monitoring work items */
6258 spin_lock_irqsave(&h->lock, flags);
6259 h->remove_in_progress = 1;
6260 cancel_delayed_work(&h->monitor_ctlr_work);
6261 spin_unlock_irqrestore(&h->lock, flags);
6262
edd16368
SC		 6263 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6264 hpsa_shutdown(pdev);
6265 iounmap(h->vaddr);
204892e9
SC		 6266 iounmap(h->transtable);
6267 iounmap(h->cfgtable);
55e14e76 6268 hpsa_free_device_info(h);
33a2ffce 6269 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6270 pci_free_consistent(h->pdev,
6271 h->nr_cmds * sizeof(struct CommandList),
6272 h->cmd_pool, h->cmd_pool_dhandle);
6273 pci_free_consistent(h->pdev,
6274 h->nr_cmds * sizeof(struct ErrorInfo),
6275 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6276 pci_free_consistent(h->pdev, h->reply_pool_size,
6277 h->reply_pool, h->reply_pool_dhandle);
edd16368 6278 kfree(h->cmd_pool_bits);
303932fd 6279 kfree(h->blockFetchTable);
e1f7de0c 6280 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6281 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6282 kfree(h->hba_inquiry_data);
f0bd0b68 6283 pci_disable_device(pdev);
edd16368 6284 pci_release_regions(pdev);
edd16368
SC		 6285 kfree(h);
6286}
6287
6288static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6289 __attribute__((unused)) pm_message_t state)
6290{
6291 return -ENOSYS;
6292}
6293
6294static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6295{
6296 return -ENOSYS;
6297}
6298
6299static struct pci_driver hpsa_pci_driver = {
f79cfec6 6300 .name = HPSA,
edd16368 6301 .probe = hpsa_init_one,
6f039790 6302 .remove = hpsa_remove_one,
edd16368
SC		 6303 .id_table = hpsa_pci_device_id, /* id_table */
6304 .shutdown = hpsa_shutdown,
6305 .suspend = hpsa_suspend,
6306 .resume = hpsa_resume,
6307};
6308
303932fd
DB		 6309/* Fill in bucket_map[], given nsgs (the max number of
6310 * scatter gather elements supported) and bucket[],
6311 * which is an array of 8 integers. The bucket[] array
6312 * contains 8 different DMA transfer sizes (in 16
6313 * byte increments) which the controller uses to fetch
6314 * commands. This function fills in bucket_map[], which
6315 * maps a given number of scatter gather elements to one of
6316 * the 8 DMA transfer sizes. The point of it is to allow the
6317 * controller to only do as much DMA as needed to fetch the
6318 * command, with the DMA transfer size encoded in the lower
6319 * bits of the command address.
6320 */
6321static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6322 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6323{
6324 int i, j, b, size;
6325
303932fd
DB		 6326 /* Note, bucket_map must have nsgs+1 entries. */
6327 for (i = 0; i <= nsgs; i++) {
6328 /* Compute size of a command with i SG entries */
e1f7de0c 6329 size = i + min_blocks;
303932fd
DB		 6330 b = num_buckets; /* Assume the biggest bucket */
6331 /* Find the bucket that is just big enough */
e1f7de0c 6332 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6333 if (bucket[j] >= size) {
6334 b = j;
6335 break;
6336 }
6337 }
6338 /* for a command with i SG entries, use bucket b. */
6339 bucket_map[i] = b;
6340 }
6341}
6342
e1f7de0c 6343static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6344{
6c311b57
SC		 6345 int i;
6346 unsigned long register_value;
e1f7de0c
MG		 6347 unsigned long transMethod = CFGTBL_Trans_Performant |
6348 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6349 CFGTBL_Trans_enable_directed_msix |
6350 (trans_support & (CFGTBL_Trans_io_accel1 |
6351 CFGTBL_Trans_io_accel2));
e1f7de0c 6352 struct access_method access = SA5_performant_access;
def342bd
SC		 6353
6354 /* This is a bit complicated. There are 8 registers on
6355 * the controller which we write to to tell it 8 different
6356 * sizes of commands which there may be. It's a way of
6357 * reducing the DMA done to fetch each command. Encoded into
6358 * each command's tag are 3 bits which communicate to the controller
6359 * which of the eight sizes that command fits within. The size of
6360 * each command depends on how many scatter gather entries there are.
6361 * Each SG entry requires 16 bytes. The eight registers are programmed
6362 * with the number of 16-byte blocks a command of that size requires.
6363 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6364 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6365 * blocks. Note, this only extends to the SG entries contained
6366 * within the command block, and does not extend to chained blocks
6367 * of SG elements. bft[] contains the eight values we write to
6368 * the registers. They are not evenly distributed, but have more
6369 * sizes for small commands, and fewer sizes for larger commands.
6370 */
d66ae08b 6371 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6372#define MIN_IOACCEL2_BFT_ENTRY 5
6373#define HPSA_IOACCEL2_HEADER_SZ 4
6374 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6375 13, 14, 15, 16, 17, 18, 19,
6376 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6377 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6378 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6379 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6380 16 * MIN_IOACCEL2_BFT_ENTRY);
6381 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6382 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6383 /* 5 = 1 s/g entry or 4k
6384 * 6 = 2 s/g entry or 8k
6385 * 8 = 4 s/g entry or 16k
6386 * 10 = 6 s/g entry or 24k
6387 */
303932fd 6388
303932fd
DB		 6389 /* Controller spec: zero out this buffer. */
6390 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6391
d66ae08b
SC		 6392 bft[7] = SG_ENTRIES_IN_CMD + 4;
6393 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6394 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6395 for (i = 0; i < 8; i++)
6396 writel(bft[i], &h->transtable->BlockFetch[i]);
6397
6398 /* size of controller ring buffer */
6399 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6400 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6401 writel(0, &h->transtable->RepQCtrAddrLow32);
6402 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6403
6404 for (i = 0; i < h->nreply_queues; i++) {
6405 writel(0, &h->transtable->RepQAddr[i].upper);
6406 writel(h->reply_pool_dhandle +
6407 (h->max_commands * sizeof(u64) * i),
6408 &h->transtable->RepQAddr[i].lower);
6409 }
6410
b9af4937 6411 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6412 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6413 /*
6414 * enable outbound interrupt coalescing in accelerator mode;
6415 */
6416 if (trans_support & CFGTBL_Trans_io_accel1) {
6417 access = SA5_ioaccel_mode1_access;
6418 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6419 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6420 } else {
6421 if (trans_support & CFGTBL_Trans_io_accel2) {
6422 access = SA5_ioaccel_mode2_access;
6423 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6424 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6425 }
e1f7de0c 6426 }
303932fd 6427 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6428 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6429 register_value = readl(&(h->cfgtable->TransportActive));
6430 if (!(register_value & CFGTBL_Trans_Performant)) {
6431 dev_warn(&h->pdev->dev, "unable to get board into"
6432 " performant mode\n");
6433 return;
6434 }
960a30e7 6435 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6436 h->access = access;
6437 h->transMethod = transMethod;
6438
b9af4937
SC		 6439 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6440 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6441 return;
6442
b9af4937
SC		 6443 if (trans_support & CFGTBL_Trans_io_accel1) {
6444 /* Set up I/O accelerator mode */
6445 for (i = 0; i < h->nreply_queues; i++) {
6446 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6447 h->reply_queue[i].current_entry =
6448 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6449 }
6450 bft[7] = h->ioaccel_maxsg + 8;
6451 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6452 h->ioaccel1_blockFetchTable);
e1f7de0c 6453
b9af4937
SC		 6454 /* initialize all reply queue entries to unused */
6455 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6456 h->reply_pool_size);
e1f7de0c 6457
b9af4937
SC		 6458 /* set all the constant fields in the accelerator command
6459 * frames once at init time to save CPU cycles later.
6460 */
6461 for (i = 0; i < h->nr_cmds; i++) {
6462 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6463
6464 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6465 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6466 (i * sizeof(struct ErrorInfo)));
6467 cp->err_info_len = sizeof(struct ErrorInfo);
6468 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6469 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6470 cp->timeout_sec = 0;
6471 cp->ReplyQueue = 0;
6472 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6473 DIRECT_LOOKUP_BIT;
6474 cp->Tag.upper = 0;
6475 cp->host_addr.lower =
6476 (u32) (h->ioaccel_cmd_pool_dhandle +
6477 (i * sizeof(struct io_accel1_cmd)));
6478 cp->host_addr.upper = 0;
6479 }
6480 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6481 u64 cfg_offset, cfg_base_addr_index;
6482 u32 bft2_offset, cfg_base_addr;
6483 int rc;
6484
6485 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6486 &cfg_base_addr_index, &cfg_offset);
6487 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6488 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6489 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6490 4, h->ioaccel2_blockFetchTable);
6491 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6492 BUILD_BUG_ON(offsetof(struct CfgTable,
6493 io_accel_request_size_offset) != 0xb8);
6494 h->ioaccel2_bft2_regs =
6495 remap_pci_mem(pci_resource_start(h->pdev,
6496 cfg_base_addr_index) +
6497 cfg_offset + bft2_offset,
6498 ARRAY_SIZE(bft2) *
6499 sizeof(*h->ioaccel2_bft2_regs));
6500 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6501 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6502 }
b9af4937
SC		 6503 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6504 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6505}
6506
6507static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6508{
283b4a9b
SC		 6509 h->ioaccel_maxsg =
6510 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6511 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6512 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6513
e1f7de0c
MG		 6514 /* Command structures must be aligned on a 128-byte boundary
6515 * because the 7 lower bits of the address are used by the
6516 * hardware.
6517 */
6518#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6519 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6520 IOACCEL1_COMMANDLIST_ALIGNMENT);
6521 h->ioaccel_cmd_pool =
6522 pci_alloc_consistent(h->pdev,
6523 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6524 &(h->ioaccel_cmd_pool_dhandle));
6525
6526 h->ioaccel1_blockFetchTable =
283b4a9b 6527 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6528 sizeof(u32)), GFP_KERNEL);
6529
6530 if ((h->ioaccel_cmd_pool == NULL) ||
6531 (h->ioaccel1_blockFetchTable == NULL))
6532 goto clean_up;
6533
6534 memset(h->ioaccel_cmd_pool, 0,
6535 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6536 return 0;
6537
6538clean_up:
6539 if (h->ioaccel_cmd_pool)
6540 pci_free_consistent(h->pdev,
6541 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6542 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6543 kfree(h->ioaccel1_blockFetchTable);
6544 return 1;
6c311b57
SC		 6545}
6546
aca9012a
SC		 6547static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6548{
6549 /* Allocate ioaccel2 mode command blocks and block fetch table */
6550
6551 h->ioaccel_maxsg =
6552 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6553 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6554 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6555
6556#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6557 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6558 IOACCEL2_COMMANDLIST_ALIGNMENT);
6559 h->ioaccel2_cmd_pool =
6560 pci_alloc_consistent(h->pdev,
6561 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6562 &(h->ioaccel2_cmd_pool_dhandle));
6563
6564 h->ioaccel2_blockFetchTable =
6565 kmalloc(((h->ioaccel_maxsg + 1) *
6566 sizeof(u32)), GFP_KERNEL);
6567
6568 if ((h->ioaccel2_cmd_pool == NULL) ||
6569 (h->ioaccel2_blockFetchTable == NULL))
6570 goto clean_up;
6571
6572 memset(h->ioaccel2_cmd_pool, 0,
6573 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
6574 return 0;
6575
6576clean_up:
6577 if (h->ioaccel2_cmd_pool)
6578 pci_free_consistent(h->pdev,
6579 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6580 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
6581 kfree(h->ioaccel2_blockFetchTable);
6582 return 1;
6583}
6584
6f039790 6585static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 6586{
6587 u32 trans_support;
e1f7de0c
MG		 6588 unsigned long transMethod = CFGTBL_Trans_Performant |
6589 CFGTBL_Trans_use_short_tags;
254f796b 6590 int i;
6c311b57 6591
02ec19c8
SC		 6592 if (hpsa_simple_mode)
6593 return;
6594
e1f7de0c
MG		 6595 /* Check for I/O accelerator mode support */
6596 if (trans_support & CFGTBL_Trans_io_accel1) {
6597 transMethod |= CFGTBL_Trans_io_accel1 |
6598 CFGTBL_Trans_enable_directed_msix;
6599 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
6600 goto clean_up;
aca9012a
SC		 6601 } else {
6602 if (trans_support & CFGTBL_Trans_io_accel2) {
6603 transMethod |= CFGTBL_Trans_io_accel2 |
6604 CFGTBL_Trans_enable_directed_msix;
6605 if (ioaccel2_alloc_cmds_and_bft(h))
6606 goto clean_up;
6607 }
e1f7de0c
MG		 6608 }
6609
6610 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 6611 trans_support = readl(&(h->cfgtable->TransportSupport));
6612 if (!(trans_support & PERFORMANT_MODE))
6613 return;
6614
eee0f03a 6615 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 6616 hpsa_get_max_perf_mode_cmds(h);
6c311b57 6617 /* Performant mode ring buffer and supporting data structures */
254f796b 6618 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 6619 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
6620 &(h->reply_pool_dhandle));
6621
254f796b
MG		 6622 for (i = 0; i < h->nreply_queues; i++) {
6623 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
6624 h->reply_queue[i].size = h->max_commands;
6625 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
6626 h->reply_queue[i].current_entry = 0;
6627 }
6628
6c311b57 6629 /* Need a block fetch table for performant mode */
d66ae08b 6630 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 6631 sizeof(u32)), GFP_KERNEL);
6632
6633 if ((h->reply_pool == NULL)
6634 || (h->blockFetchTable == NULL))
6635 goto clean_up;
6636
e1f7de0c 6637 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 6638 return;
6639
6640clean_up:
6641 if (h->reply_pool)
6642 pci_free_consistent(h->pdev, h->reply_pool_size,
6643 h->reply_pool, h->reply_pool_dhandle);
6644 kfree(h->blockFetchTable);
6645}
6646
76438d08
SC		 6647static void hpsa_drain_commands(struct ctlr_info *h)
6648{
6649 int cmds_out;
6650 unsigned long flags;
6651
6652 do { /* wait for all outstanding commands to drain out */
6653 spin_lock_irqsave(&h->lock, flags);
6654 cmds_out = h->commands_outstanding;
6655 spin_unlock_irqrestore(&h->lock, flags);
6656 if (cmds_out <= 0)
6657 break;
6658 msleep(100);
6659 } while (1);
6660}
6661
edd16368
SC		 6662/*
6663 * This is it. Register the PCI driver information for the cards we control
6664 * the OS will call our registered routines when it finds one of our cards.
6665 */
6666static int __init hpsa_init(void)
6667{
31468401 6668 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 6669}
6670
6671static void __exit hpsa_cleanup(void)
6672{
6673 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 6674}
6675
e1f7de0c
MG		 6676static void __attribute__((unused)) verify_offsets(void)
6677{
b66cc250
MM		 6678#define VERIFY_OFFSET(member, offset) \
6679 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
6680
6681 VERIFY_OFFSET(IU_type, 0);
6682 VERIFY_OFFSET(direction, 1);
6683 VERIFY_OFFSET(reply_queue, 2);
6684 /* VERIFY_OFFSET(reserved1, 3); */
6685 VERIFY_OFFSET(scsi_nexus, 4);
6686 VERIFY_OFFSET(Tag, 8);
6687 VERIFY_OFFSET(cdb, 16);
6688 VERIFY_OFFSET(cciss_lun, 32);
6689 VERIFY_OFFSET(data_len, 40);
6690 VERIFY_OFFSET(cmd_priority_task_attr, 44);
6691 VERIFY_OFFSET(sg_count, 45);
6692 /* VERIFY_OFFSET(reserved3 */
6693 VERIFY_OFFSET(err_ptr, 48);
6694 VERIFY_OFFSET(err_len, 56);
6695 /* VERIFY_OFFSET(reserved4 */
6696 VERIFY_OFFSET(sg, 64);
6697
6698#undef VERIFY_OFFSET
6699
e1f7de0c
MG		 6700#define VERIFY_OFFSET(member, offset) \
6701 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
6702
6703 VERIFY_OFFSET(dev_handle, 0x00);
6704 VERIFY_OFFSET(reserved1, 0x02);
6705 VERIFY_OFFSET(function, 0x03);
6706 VERIFY_OFFSET(reserved2, 0x04);
6707 VERIFY_OFFSET(err_info, 0x0C);
6708 VERIFY_OFFSET(reserved3, 0x10);
6709 VERIFY_OFFSET(err_info_len, 0x12);
6710 VERIFY_OFFSET(reserved4, 0x13);
6711 VERIFY_OFFSET(sgl_offset, 0x14);
6712 VERIFY_OFFSET(reserved5, 0x15);
6713 VERIFY_OFFSET(transfer_len, 0x1C);
6714 VERIFY_OFFSET(reserved6, 0x20);
6715 VERIFY_OFFSET(io_flags, 0x24);
6716 VERIFY_OFFSET(reserved7, 0x26);
6717 VERIFY_OFFSET(LUN, 0x34);
6718 VERIFY_OFFSET(control, 0x3C);
6719 VERIFY_OFFSET(CDB, 0x40);
6720 VERIFY_OFFSET(reserved8, 0x50);
6721 VERIFY_OFFSET(host_context_flags, 0x60);
6722 VERIFY_OFFSET(timeout_sec, 0x62);
6723 VERIFY_OFFSET(ReplyQueue, 0x64);
6724 VERIFY_OFFSET(reserved9, 0x65);
6725 VERIFY_OFFSET(Tag, 0x68);
6726 VERIFY_OFFSET(host_addr, 0x70);
6727 VERIFY_OFFSET(CISS_LUN, 0x78);
6728 VERIFY_OFFSET(SG, 0x78 + 8);
6729#undef VERIFY_OFFSET
6730}
6731
edd16368
SC		 6732module_init(hpsa_init);
6733module_exit(hpsa_cleanup);
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