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hpsa: Convert SCSI LLD ->queuecommand() for host_lock less operation
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
42a91641 51#include <linux/percpu-defs.h>
094963da 52#include <linux/percpu.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 58#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368
SC		 61
62/* How long to wait (in milliseconds) for board to go into simple mode */
63#define MAX_CONFIG_WAIT 30000
64#define MAX_IOCTL_CONFIG_WAIT 1000
65
66/*define how many times we will try a command because of bus resets */
67#define MAX_CMD_RETRIES 3
68
69/* Embedded module documentation macros - see modules.h */
70MODULE_AUTHOR("Hewlett-Packard Company");
71MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
72 HPSA_DRIVER_VERSION);
73MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
74MODULE_VERSION(HPSA_DRIVER_VERSION);
75MODULE_LICENSE("GPL");
76
77static int hpsa_allow_any;
78module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
79MODULE_PARM_DESC(hpsa_allow_any,
80 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 81static int hpsa_simple_mode;
82module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
83MODULE_PARM_DESC(hpsa_simple_mode,
84 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 85
86/* define the PCI info for the cards we can control */
87static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 128 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
129 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
130 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
131 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
132 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 133 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 134 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 135 {0,}
136};
137
138MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
139
140/* board_id = Subsystem Device ID & Vendor ID
141 * product = Marketing Name for the board
142 * access = Address of the struct of function pointers
143 */
144static struct board_type products[] = {
edd16368
SC		 145 {0x3241103C, "Smart Array P212", &SA5_access},
146 {0x3243103C, "Smart Array P410", &SA5_access},
147 {0x3245103C, "Smart Array P410i", &SA5_access},
148 {0x3247103C, "Smart Array P411", &SA5_access},
149 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 150 {0x324A103C, "Smart Array P712m", &SA5_access},
151 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 152 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 153 {0x3350103C, "Smart Array P222", &SA5_access},
154 {0x3351103C, "Smart Array P420", &SA5_access},
155 {0x3352103C, "Smart Array P421", &SA5_access},
156 {0x3353103C, "Smart Array P822", &SA5_access},
157 {0x3354103C, "Smart Array P420i", &SA5_access},
158 {0x3355103C, "Smart Array P220i", &SA5_access},
159 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 160 {0x1921103C, "Smart Array P830i", &SA5_access},
161 {0x1922103C, "Smart Array P430", &SA5_access},
162 {0x1923103C, "Smart Array P431", &SA5_access},
163 {0x1924103C, "Smart Array P830", &SA5_access},
164 {0x1926103C, "Smart Array P731m", &SA5_access},
165 {0x1928103C, "Smart Array P230i", &SA5_access},
166 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 167 {0x21BD103C, "Smart Array", &SA5_access},
168 {0x21BE103C, "Smart Array", &SA5_access},
169 {0x21BF103C, "Smart Array", &SA5_access},
170 {0x21C0103C, "Smart Array", &SA5_access},
171 {0x21C1103C, "Smart Array", &SA5_access},
172 {0x21C2103C, "Smart Array", &SA5_access},
173 {0x21C3103C, "Smart Array", &SA5_access},
174 {0x21C4103C, "Smart Array", &SA5_access},
175 {0x21C5103C, "Smart Array", &SA5_access},
3b7a45e5 176 {0x21C6103C, "Smart Array", &SA5_access},
97b9f53d
MM		 177 {0x21C7103C, "Smart Array", &SA5_access},
178 {0x21C8103C, "Smart Array", &SA5_access},
179 {0x21C9103C, "Smart Array", &SA5_access},
3b7a45e5
JH		 180 {0x21CA103C, "Smart Array", &SA5_access},
181 {0x21CB103C, "Smart Array", &SA5_access},
182 {0x21CC103C, "Smart Array", &SA5_access},
183 {0x21CD103C, "Smart Array", &SA5_access},
184 {0x21CE103C, "Smart Array", &SA5_access},
8e616a5e
SC		 185 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
186 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
187 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
188 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
189 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 190 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
191};
192
193static int number_of_controllers;
194
10f66018
SC		 195static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
196static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 197static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
0b57075d
SC		 198static void lock_and_start_io(struct ctlr_info *h);
199static void start_io(struct ctlr_info *h, unsigned long *flags);
edd16368
SC		 200
201#ifdef CONFIG_COMPAT
42a91641
DB		 202static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
203 void __user *arg);
edd16368
SC		 204#endif
205
206static void cmd_free(struct ctlr_info *h, struct CommandList *c);
207static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
208static struct CommandList *cmd_alloc(struct ctlr_info *h);
209static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 210static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 211 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 212 int cmd_type);
b7bb24eb 213#define VPD_PAGE (1 << 8)
edd16368 214
f281233d 215static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 216static void hpsa_scan_start(struct Scsi_Host *);
217static int hpsa_scan_finished(struct Scsi_Host *sh,
218 unsigned long elapsed_time);
667e23d4
SC		 219static int hpsa_change_queue_depth(struct scsi_device *sdev,
220 int qdepth, int reason);
edd16368
SC		 221
222static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 223static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 224static int hpsa_slave_alloc(struct scsi_device *sdev);
225static void hpsa_slave_destroy(struct scsi_device *sdev);
226
edd16368 227static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 228static int check_for_unit_attention(struct ctlr_info *h,
229 struct CommandList *c);
230static void check_ioctl_unit_attention(struct ctlr_info *h,
231 struct CommandList *c);
303932fd
DB		 232/* performant mode helper functions */
233static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 234 int nsgs, int min_blocks, int *bucket_map);
6f039790 235static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 236static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 237static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
238 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
239 u64 *cfg_offset);
240static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
241 unsigned long *memory_bar);
242static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
243static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
244 int wait_for_ready);
75167d2c 245static inline void finish_cmd(struct CommandList *c);
283b4a9b 246static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 247#define BOARD_NOT_READY 0
248#define BOARD_READY 1
23100dd9 249static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 250static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 251static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
252 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
253 u8 *scsi3addr);
edd16368 254
edd16368
SC		 255static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
256{
257 unsigned long *priv = shost_priv(sdev->host);
258 return (struct ctlr_info *) *priv;
259}
260
a23513e8
SC		 261static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
262{
263 unsigned long *priv = shost_priv(sh);
264 return (struct ctlr_info *) *priv;
265}
266
edd16368
SC		 267static int check_for_unit_attention(struct ctlr_info *h,
268 struct CommandList *c)
269{
270 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
271 return 0;
272
273 switch (c->err_info->SenseInfo[12]) {
274 case STATE_CHANGED:
f79cfec6 275 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 276 "detected, command retried\n", h->ctlr);
277 break;
278 case LUN_FAILED:
7f73695a
SC		 279 dev_warn(&h->pdev->dev,
280 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 281 break;
282 case REPORT_LUNS_CHANGED:
7f73695a
SC		 283 dev_warn(&h->pdev->dev,
284 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 285 /*
4f4eb9f1
ST		 286 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
287 * target (array) devices.
edd16368
SC		 288 */
289 break;
290 case POWER_OR_RESET:
f79cfec6 291 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 292 "or device reset detected\n", h->ctlr);
293 break;
294 case UNIT_ATTENTION_CLEARED:
f79cfec6 295 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 296 "cleared by another initiator\n", h->ctlr);
297 break;
298 default:
f79cfec6 299 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 300 "unit attention detected\n", h->ctlr);
301 break;
302 }
303 return 1;
304}
305
852af20a
MB		 306static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
307{
308 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
309 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
310 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
311 return 0;
312 dev_warn(&h->pdev->dev, HPSA "device busy");
313 return 1;
314}
315
da0697bd
ST		 316static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
317 struct device_attribute *attr,
318 const char *buf, size_t count)
319{
320 int status, len;
321 struct ctlr_info *h;
322 struct Scsi_Host *shost = class_to_shost(dev);
323 char tmpbuf[10];
324
325 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
326 return -EACCES;
327 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
328 strncpy(tmpbuf, buf, len);
329 tmpbuf[len] = '\0';
330 if (sscanf(tmpbuf, "%d", &status) != 1)
331 return -EINVAL;
332 h = shost_to_hba(shost);
333 h->acciopath_status = !!status;
334 dev_warn(&h->pdev->dev,
335 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
336 h->acciopath_status ? "enabled" : "disabled");
337 return count;
338}
339
2ba8bfc8
SC		 340static ssize_t host_store_raid_offload_debug(struct device *dev,
341 struct device_attribute *attr,
342 const char *buf, size_t count)
343{
344 int debug_level, len;
345 struct ctlr_info *h;
346 struct Scsi_Host *shost = class_to_shost(dev);
347 char tmpbuf[10];
348
349 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
350 return -EACCES;
351 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
352 strncpy(tmpbuf, buf, len);
353 tmpbuf[len] = '\0';
354 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
355 return -EINVAL;
356 if (debug_level < 0)
357 debug_level = 0;
358 h = shost_to_hba(shost);
359 h->raid_offload_debug = debug_level;
360 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
361 h->raid_offload_debug);
362 return count;
363}
364
edd16368
SC		 365static ssize_t host_store_rescan(struct device *dev,
366 struct device_attribute *attr,
367 const char *buf, size_t count)
368{
369 struct ctlr_info *h;
370 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 371 h = shost_to_hba(shost);
31468401 372 hpsa_scan_start(h->scsi_host);
edd16368
SC		 373 return count;
374}
375
d28ce020
SC		 376static ssize_t host_show_firmware_revision(struct device *dev,
377 struct device_attribute *attr, char *buf)
378{
379 struct ctlr_info *h;
380 struct Scsi_Host *shost = class_to_shost(dev);
381 unsigned char *fwrev;
382
383 h = shost_to_hba(shost);
384 if (!h->hba_inquiry_data)
385 return 0;
386 fwrev = &h->hba_inquiry_data[32];
387 return snprintf(buf, 20, "%c%c%c%c\n",
388 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
389}
390
94a13649
SC		 391static ssize_t host_show_commands_outstanding(struct device *dev,
392 struct device_attribute *attr, char *buf)
393{
394 struct Scsi_Host *shost = class_to_shost(dev);
395 struct ctlr_info *h = shost_to_hba(shost);
396
0cbf768e
SC		 397 return snprintf(buf, 20, "%d\n",
398 atomic_read(&h->commands_outstanding));
94a13649
SC		 399}
400
745a7a25
SC		 401static ssize_t host_show_transport_mode(struct device *dev,
402 struct device_attribute *attr, char *buf)
403{
404 struct ctlr_info *h;
405 struct Scsi_Host *shost = class_to_shost(dev);
406
407 h = shost_to_hba(shost);
408 return snprintf(buf, 20, "%s\n",
960a30e7 409 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 410 "performant" : "simple");
411}
412
da0697bd
ST		 413static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
414 struct device_attribute *attr, char *buf)
415{
416 struct ctlr_info *h;
417 struct Scsi_Host *shost = class_to_shost(dev);
418
419 h = shost_to_hba(shost);
420 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
421 (h->acciopath_status == 1) ? "enabled" : "disabled");
422}
423
46380786 424/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 425static u32 unresettable_controller[] = {
426 0x324a103C, /* Smart Array P712m */
427 0x324b103C, /* SmartArray P711m */
428 0x3223103C, /* Smart Array P800 */
429 0x3234103C, /* Smart Array P400 */
430 0x3235103C, /* Smart Array P400i */
431 0x3211103C, /* Smart Array E200i */
432 0x3212103C, /* Smart Array E200 */
433 0x3213103C, /* Smart Array E200i */
434 0x3214103C, /* Smart Array E200i */
435 0x3215103C, /* Smart Array E200i */
436 0x3237103C, /* Smart Array E500 */
437 0x323D103C, /* Smart Array P700m */
7af0abbc 438 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 439 0x409C0E11, /* Smart Array 6400 */
440 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 441 0x40700E11, /* Smart Array 5300 */
442 0x40820E11, /* Smart Array 532 */
443 0x40830E11, /* Smart Array 5312 */
444 0x409A0E11, /* Smart Array 641 */
445 0x409B0E11, /* Smart Array 642 */
446 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 447};
448
46380786
SC		 449/* List of controllers which cannot even be soft reset */
450static u32 soft_unresettable_controller[] = {
7af0abbc 451 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 452 0x40700E11, /* Smart Array 5300 */
453 0x40820E11, /* Smart Array 532 */
454 0x40830E11, /* Smart Array 5312 */
455 0x409A0E11, /* Smart Array 641 */
456 0x409B0E11, /* Smart Array 642 */
457 0x40910E11, /* Smart Array 6i */
46380786
SC		 458 /* Exclude 640x boards. These are two pci devices in one slot
459 * which share a battery backed cache module. One controls the
460 * cache, the other accesses the cache through the one that controls
461 * it. If we reset the one controlling the cache, the other will
462 * likely not be happy. Just forbid resetting this conjoined mess.
463 * The 640x isn't really supported by hpsa anyway.
464 */
465 0x409C0E11, /* Smart Array 6400 */
466 0x409D0E11, /* Smart Array 6400 EM */
467};
468
469static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 470{
471 int i;
472
473 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 474 if (unresettable_controller[i] == board_id)
475 return 0;
476 return 1;
477}
478
479static int ctlr_is_soft_resettable(u32 board_id)
480{
481 int i;
482
483 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
484 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 485 return 0;
486 return 1;
487}
488
46380786
SC		 489static int ctlr_is_resettable(u32 board_id)
490{
491 return ctlr_is_hard_resettable(board_id) ||
492 ctlr_is_soft_resettable(board_id);
493}
494
941b1cda
SC		 495static ssize_t host_show_resettable(struct device *dev,
496 struct device_attribute *attr, char *buf)
497{
498 struct ctlr_info *h;
499 struct Scsi_Host *shost = class_to_shost(dev);
500
501 h = shost_to_hba(shost);
46380786 502 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 503}
504
edd16368
SC		 505static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
506{
507 return (scsi3addr[3] & 0xC0) == 0x40;
508}
509
510static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 511 "1(ADM)", "UNKNOWN"
edd16368 512};
6b80b18f
ST		 513#define HPSA_RAID_0 0
514#define HPSA_RAID_4 1
515#define HPSA_RAID_1 2 /* also used for RAID 10 */
516#define HPSA_RAID_5 3 /* also used for RAID 50 */
517#define HPSA_RAID_51 4
518#define HPSA_RAID_6 5 /* also used for RAID 60 */
519#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 520#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
521
522static ssize_t raid_level_show(struct device *dev,
523 struct device_attribute *attr, char *buf)
524{
525 ssize_t l = 0;
82a72c0a 526 unsigned char rlevel;
edd16368
SC		 527 struct ctlr_info *h;
528 struct scsi_device *sdev;
529 struct hpsa_scsi_dev_t *hdev;
530 unsigned long flags;
531
532 sdev = to_scsi_device(dev);
533 h = sdev_to_hba(sdev);
534 spin_lock_irqsave(&h->lock, flags);
535 hdev = sdev->hostdata;
536 if (!hdev) {
537 spin_unlock_irqrestore(&h->lock, flags);
538 return -ENODEV;
539 }
540
541 /* Is this even a logical drive? */
542 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
543 spin_unlock_irqrestore(&h->lock, flags);
544 l = snprintf(buf, PAGE_SIZE, "N/A\n");
545 return l;
546 }
547
548 rlevel = hdev->raid_level;
549 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 550 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 551 rlevel = RAID_UNKNOWN;
552 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
553 return l;
554}
555
556static ssize_t lunid_show(struct device *dev,
557 struct device_attribute *attr, char *buf)
558{
559 struct ctlr_info *h;
560 struct scsi_device *sdev;
561 struct hpsa_scsi_dev_t *hdev;
562 unsigned long flags;
563 unsigned char lunid[8];
564
565 sdev = to_scsi_device(dev);
566 h = sdev_to_hba(sdev);
567 spin_lock_irqsave(&h->lock, flags);
568 hdev = sdev->hostdata;
569 if (!hdev) {
570 spin_unlock_irqrestore(&h->lock, flags);
571 return -ENODEV;
572 }
573 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
574 spin_unlock_irqrestore(&h->lock, flags);
575 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
576 lunid[0], lunid[1], lunid[2], lunid[3],
577 lunid[4], lunid[5], lunid[6], lunid[7]);
578}
579
580static ssize_t unique_id_show(struct device *dev,
581 struct device_attribute *attr, char *buf)
582{
583 struct ctlr_info *h;
584 struct scsi_device *sdev;
585 struct hpsa_scsi_dev_t *hdev;
586 unsigned long flags;
587 unsigned char sn[16];
588
589 sdev = to_scsi_device(dev);
590 h = sdev_to_hba(sdev);
591 spin_lock_irqsave(&h->lock, flags);
592 hdev = sdev->hostdata;
593 if (!hdev) {
594 spin_unlock_irqrestore(&h->lock, flags);
595 return -ENODEV;
596 }
597 memcpy(sn, hdev->device_id, sizeof(sn));
598 spin_unlock_irqrestore(&h->lock, flags);
599 return snprintf(buf, 16 * 2 + 2,
600 "%02X%02X%02X%02X%02X%02X%02X%02X"
601 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
602 sn[0], sn[1], sn[2], sn[3],
603 sn[4], sn[5], sn[6], sn[7],
604 sn[8], sn[9], sn[10], sn[11],
605 sn[12], sn[13], sn[14], sn[15]);
606}
607
c1988684
ST		 608static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
609 struct device_attribute *attr, char *buf)
610{
611 struct ctlr_info *h;
612 struct scsi_device *sdev;
613 struct hpsa_scsi_dev_t *hdev;
614 unsigned long flags;
615 int offload_enabled;
616
617 sdev = to_scsi_device(dev);
618 h = sdev_to_hba(sdev);
619 spin_lock_irqsave(&h->lock, flags);
620 hdev = sdev->hostdata;
621 if (!hdev) {
622 spin_unlock_irqrestore(&h->lock, flags);
623 return -ENODEV;
624 }
625 offload_enabled = hdev->offload_enabled;
626 spin_unlock_irqrestore(&h->lock, flags);
627 return snprintf(buf, 20, "%d\n", offload_enabled);
628}
629
3f5eac3a
SC		 630static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
631static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
632static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
633static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 634static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
635 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 636static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
637 host_show_hp_ssd_smart_path_status,
638 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 639static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
640 host_store_raid_offload_debug);
3f5eac3a
SC		 641static DEVICE_ATTR(firmware_revision, S_IRUGO,
642 host_show_firmware_revision, NULL);
643static DEVICE_ATTR(commands_outstanding, S_IRUGO,
644 host_show_commands_outstanding, NULL);
645static DEVICE_ATTR(transport_mode, S_IRUGO,
646 host_show_transport_mode, NULL);
941b1cda
SC		 647static DEVICE_ATTR(resettable, S_IRUGO,
648 host_show_resettable, NULL);
3f5eac3a
SC		 649
650static struct device_attribute *hpsa_sdev_attrs[] = {
651 &dev_attr_raid_level,
652 &dev_attr_lunid,
653 &dev_attr_unique_id,
c1988684 654 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 655 NULL,
656};
657
658static struct device_attribute *hpsa_shost_attrs[] = {
659 &dev_attr_rescan,
660 &dev_attr_firmware_revision,
661 &dev_attr_commands_outstanding,
662 &dev_attr_transport_mode,
941b1cda 663 &dev_attr_resettable,
da0697bd 664 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 665 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 666 NULL,
667};
668
669static struct scsi_host_template hpsa_driver_template = {
670 .module = THIS_MODULE,
f79cfec6
SC		 671 .name = HPSA,
672 .proc_name = HPSA,
3f5eac3a
SC		 673 .queuecommand = hpsa_scsi_queue_command,
674 .scan_start = hpsa_scan_start,
675 .scan_finished = hpsa_scan_finished,
676 .change_queue_depth = hpsa_change_queue_depth,
677 .this_id = -1,
678 .use_clustering = ENABLE_CLUSTERING,
75167d2c 679 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 680 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
681 .ioctl = hpsa_ioctl,
682 .slave_alloc = hpsa_slave_alloc,
683 .slave_destroy = hpsa_slave_destroy,
684#ifdef CONFIG_COMPAT
685 .compat_ioctl = hpsa_compat_ioctl,
686#endif
687 .sdev_attrs = hpsa_sdev_attrs,
688 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 689 .max_sectors = 8192,
54b2b50c 690 .no_write_same = 1,
3f5eac3a
SC		 691};
692
693
694/* Enqueuing and dequeuing functions for cmdlists. */
695static inline void addQ(struct list_head *list, struct CommandList *c)
696{
697 list_add_tail(&c->list, list);
698}
699
254f796b 700static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 701{
702 u32 a;
072b0518 703 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 704
e1f7de0c
MG		 705 if (h->transMethod & CFGTBL_Trans_io_accel1)
706 return h->access.command_completed(h, q);
707
3f5eac3a 708 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 709 return h->access.command_completed(h, q);
3f5eac3a 710
254f796b
MG		 711 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
712 a = rq->head[rq->current_entry];
713 rq->current_entry++;
0cbf768e 714 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 715 } else {
716 a = FIFO_EMPTY;
717 }
718 /* Check for wraparound */
254f796b
MG		 719 if (rq->current_entry == h->max_commands) {
720 rq->current_entry = 0;
721 rq->wraparound ^= 1;
3f5eac3a
SC		 722 }
723 return a;
724}
725
c349775e
ST		 726/*
727 * There are some special bits in the bus address of the
728 * command that we have to set for the controller to know
729 * how to process the command:
730 *
731 * Normal performant mode:
732 * bit 0: 1 means performant mode, 0 means simple mode.
733 * bits 1-3 = block fetch table entry
734 * bits 4-6 = command type (== 0)
735 *
736 * ioaccel1 mode:
737 * bit 0 = "performant mode" bit.
738 * bits 1-3 = block fetch table entry
739 * bits 4-6 = command type (== 110)
740 * (command type is needed because ioaccel1 mode
741 * commands are submitted through the same register as normal
742 * mode commands, so this is how the controller knows whether
743 * the command is normal mode or ioaccel1 mode.)
744 *
745 * ioaccel2 mode:
746 * bit 0 = "performant mode" bit.
747 * bits 1-4 = block fetch table entry (note extra bit)
748 * bits 4-6 = not needed, because ioaccel2 mode has
749 * a separate special register for submitting commands.
750 */
751
3f5eac3a
SC		 752/* set_performant_mode: Modify the tag for cciss performant
753 * set bit 0 for pull model, bits 3-1 for block fetch
754 * register number
755 */
756static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
757{
254f796b 758 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 759 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 760 if (likely(h->msix_vector > 0))
254f796b 761 c->Header.ReplyQueue =
804a5cb5 762 raw_smp_processor_id() % h->nreply_queues;
254f796b 763 }
3f5eac3a
SC		 764}
765
c349775e
ST		 766static void set_ioaccel1_performant_mode(struct ctlr_info *h,
767 struct CommandList *c)
768{
769 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
770
771 /* Tell the controller to post the reply to the queue for this
772 * processor. This seems to give the best I/O throughput.
773 */
774 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
775 /* Set the bits in the address sent down to include:
776 * - performant mode bit (bit 0)
777 * - pull count (bits 1-3)
778 * - command type (bits 4-6)
779 */
780 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
781 IOACCEL1_BUSADDR_CMDTYPE;
782}
783
784static void set_ioaccel2_performant_mode(struct ctlr_info *h,
785 struct CommandList *c)
786{
787 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
788
789 /* Tell the controller to post the reply to the queue for this
790 * processor. This seems to give the best I/O throughput.
791 */
792 cp->reply_queue = smp_processor_id() % h->nreply_queues;
793 /* Set the bits in the address sent down to include:
794 * - performant mode bit not used in ioaccel mode 2
795 * - pull count (bits 0-3)
796 * - command type isn't needed for ioaccel2
797 */
798 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
799}
800
e85c5974
SC		 801static int is_firmware_flash_cmd(u8 *cdb)
802{
803 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
804}
805
806/*
807 * During firmware flash, the heartbeat register may not update as frequently
808 * as it should. So we dial down lockup detection during firmware flash. and
809 * dial it back up when firmware flash completes.
810 */
811#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
812#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
813static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
814 struct CommandList *c)
815{
816 if (!is_firmware_flash_cmd(c->Request.CDB))
817 return;
818 atomic_inc(&h->firmware_flash_in_progress);
819 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
820}
821
822static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
823 struct CommandList *c)
824{
825 if (is_firmware_flash_cmd(c->Request.CDB) &&
826 atomic_dec_and_test(&h->firmware_flash_in_progress))
827 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
828}
829
3f5eac3a
SC		 830static void enqueue_cmd_and_start_io(struct ctlr_info *h,
831 struct CommandList *c)
832{
833 unsigned long flags;
834
c349775e
ST		 835 switch (c->cmd_type) {
836 case CMD_IOACCEL1:
837 set_ioaccel1_performant_mode(h, c);
838 break;
839 case CMD_IOACCEL2:
840 set_ioaccel2_performant_mode(h, c);
841 break;
842 default:
843 set_performant_mode(h, c);
844 }
e85c5974 845 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 846 spin_lock_irqsave(&h->lock, flags);
847 addQ(&h->reqQ, c);
848 h->Qdepth++;
0b57075d 849 start_io(h, &flags);
3f5eac3a
SC		 850 spin_unlock_irqrestore(&h->lock, flags);
851}
852
853static inline void removeQ(struct CommandList *c)
854{
855 if (WARN_ON(list_empty(&c->list)))
856 return;
857 list_del_init(&c->list);
858}
859
860static inline int is_hba_lunid(unsigned char scsi3addr[])
861{
862 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
863}
864
865static inline int is_scsi_rev_5(struct ctlr_info *h)
866{
867 if (!h->hba_inquiry_data)
868 return 0;
869 if ((h->hba_inquiry_data[2] & 0x07) == 5)
870 return 1;
871 return 0;
872}
873
edd16368
SC		 874static int hpsa_find_target_lun(struct ctlr_info *h,
875 unsigned char scsi3addr[], int bus, int *target, int *lun)
876{
877 /* finds an unused bus, target, lun for a new physical device
878 * assumes h->devlock is held
879 */
880 int i, found = 0;
cfe5badc 881 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 882
263d9401 883 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 884
885 for (i = 0; i < h->ndevices; i++) {
886 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 887 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 888 }
889
263d9401
AM		 890 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
891 if (i < HPSA_MAX_DEVICES) {
892 /* *bus = 1; */
893 *target = i;
894 *lun = 0;
895 found = 1;
edd16368
SC		 896 }
897 return !found;
898}
899
900/* Add an entry into h->dev[] array. */
901static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
902 struct hpsa_scsi_dev_t *device,
903 struct hpsa_scsi_dev_t *added[], int *nadded)
904{
905 /* assumes h->devlock is held */
906 int n = h->ndevices;
907 int i;
908 unsigned char addr1[8], addr2[8];
909 struct hpsa_scsi_dev_t *sd;
910
cfe5badc 911 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 912 dev_err(&h->pdev->dev, "too many devices, some will be "
913 "inaccessible.\n");
914 return -1;
915 }
916
917 /* physical devices do not have lun or target assigned until now. */
918 if (device->lun != -1)
919 /* Logical device, lun is already assigned. */
920 goto lun_assigned;
921
922 /* If this device a non-zero lun of a multi-lun device
923 * byte 4 of the 8-byte LUN addr will contain the logical
924 * unit no, zero otherise.
925 */
926 if (device->scsi3addr[4] == 0) {
927 /* This is not a non-zero lun of a multi-lun device */
928 if (hpsa_find_target_lun(h, device->scsi3addr,
929 device->bus, &device->target, &device->lun) != 0)
930 return -1;
931 goto lun_assigned;
932 }
933
934 /* This is a non-zero lun of a multi-lun device.
935 * Search through our list and find the device which
936 * has the same 8 byte LUN address, excepting byte 4.
937 * Assign the same bus and target for this new LUN.
938 * Use the logical unit number from the firmware.
939 */
940 memcpy(addr1, device->scsi3addr, 8);
941 addr1[4] = 0;
942 for (i = 0; i < n; i++) {
943 sd = h->dev[i];
944 memcpy(addr2, sd->scsi3addr, 8);
945 addr2[4] = 0;
946 /* differ only in byte 4? */
947 if (memcmp(addr1, addr2, 8) == 0) {
948 device->bus = sd->bus;
949 device->target = sd->target;
950 device->lun = device->scsi3addr[4];
951 break;
952 }
953 }
954 if (device->lun == -1) {
955 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
956 " suspect firmware bug or unsupported hardware "
957 "configuration.\n");
958 return -1;
959 }
960
961lun_assigned:
962
963 h->dev[n] = device;
964 h->ndevices++;
965 added[*nadded] = device;
966 (*nadded)++;
967
968 /* initially, (before registering with scsi layer) we don't
969 * know our hostno and we don't want to print anything first
970 * time anyway (the scsi layer's inquiries will show that info)
971 */
972 /* if (hostno != -1) */
973 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
974 scsi_device_type(device->devtype), hostno,
975 device->bus, device->target, device->lun);
976 return 0;
977}
978
bd9244f7
ST		 979/* Update an entry in h->dev[] array. */
980static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
981 int entry, struct hpsa_scsi_dev_t *new_entry)
982{
983 /* assumes h->devlock is held */
984 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
985
986 /* Raid level changed. */
987 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 988
989 /* Raid offload parameters changed. */
990 h->dev[entry]->offload_config = new_entry->offload_config;
991 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 992 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
993 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
994 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 995
bd9244f7
ST		 996 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
997 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
998 new_entry->target, new_entry->lun);
999}
1000
2a8ccf31
SC		 1001/* Replace an entry from h->dev[] array. */
1002static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1003 int entry, struct hpsa_scsi_dev_t *new_entry,
1004 struct hpsa_scsi_dev_t *added[], int *nadded,
1005 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1006{
1007 /* assumes h->devlock is held */
cfe5badc 1008 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1009 removed[*nremoved] = h->dev[entry];
1010 (*nremoved)++;
01350d05
SC		 1011
1012 /*
1013 * New physical devices won't have target/lun assigned yet
1014 * so we need to preserve the values in the slot we are replacing.
1015 */
1016 if (new_entry->target == -1) {
1017 new_entry->target = h->dev[entry]->target;
1018 new_entry->lun = h->dev[entry]->lun;
1019 }
1020
2a8ccf31
SC		 1021 h->dev[entry] = new_entry;
1022 added[*nadded] = new_entry;
1023 (*nadded)++;
1024 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1025 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1026 new_entry->target, new_entry->lun);
1027}
1028
edd16368
SC		 1029/* Remove an entry from h->dev[] array. */
1030static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1031 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1032{
1033 /* assumes h->devlock is held */
1034 int i;
1035 struct hpsa_scsi_dev_t *sd;
1036
cfe5badc 1037 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1038
1039 sd = h->dev[entry];
1040 removed[*nremoved] = h->dev[entry];
1041 (*nremoved)++;
1042
1043 for (i = entry; i < h->ndevices-1; i++)
1044 h->dev[i] = h->dev[i+1];
1045 h->ndevices--;
1046 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1047 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1048 sd->lun);
1049}
1050
1051#define SCSI3ADDR_EQ(a, b) ( \
1052 (a)[7] == (b)[7] && \
1053 (a)[6] == (b)[6] && \
1054 (a)[5] == (b)[5] && \
1055 (a)[4] == (b)[4] && \
1056 (a)[3] == (b)[3] && \
1057 (a)[2] == (b)[2] && \
1058 (a)[1] == (b)[1] && \
1059 (a)[0] == (b)[0])
1060
1061static void fixup_botched_add(struct ctlr_info *h,
1062 struct hpsa_scsi_dev_t *added)
1063{
1064 /* called when scsi_add_device fails in order to re-adjust
1065 * h->dev[] to match the mid layer's view.
1066 */
1067 unsigned long flags;
1068 int i, j;
1069
1070 spin_lock_irqsave(&h->lock, flags);
1071 for (i = 0; i < h->ndevices; i++) {
1072 if (h->dev[i] == added) {
1073 for (j = i; j < h->ndevices-1; j++)
1074 h->dev[j] = h->dev[j+1];
1075 h->ndevices--;
1076 break;
1077 }
1078 }
1079 spin_unlock_irqrestore(&h->lock, flags);
1080 kfree(added);
1081}
1082
1083static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1084 struct hpsa_scsi_dev_t *dev2)
1085{
edd16368
SC		 1086 /* we compare everything except lun and target as these
1087 * are not yet assigned. Compare parts likely
1088 * to differ first
1089 */
1090 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1091 sizeof(dev1->scsi3addr)) != 0)
1092 return 0;
1093 if (memcmp(dev1->device_id, dev2->device_id,
1094 sizeof(dev1->device_id)) != 0)
1095 return 0;
1096 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1097 return 0;
1098 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1099 return 0;
edd16368
SC		 1100 if (dev1->devtype != dev2->devtype)
1101 return 0;
edd16368
SC		 1102 if (dev1->bus != dev2->bus)
1103 return 0;
1104 return 1;
1105}
1106
bd9244f7
ST		 1107static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1108 struct hpsa_scsi_dev_t *dev2)
1109{
1110 /* Device attributes that can change, but don't mean
1111 * that the device is a different device, nor that the OS
1112 * needs to be told anything about the change.
1113 */
1114 if (dev1->raid_level != dev2->raid_level)
1115 return 1;
250fb125
SC		 1116 if (dev1->offload_config != dev2->offload_config)
1117 return 1;
1118 if (dev1->offload_enabled != dev2->offload_enabled)
1119 return 1;
bd9244f7
ST		 1120 return 0;
1121}
1122
edd16368
SC		 1123/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1124 * and return needle location in *index. If scsi3addr matches, but not
1125 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1126 * location in *index.
1127 * In the case of a minor device attribute change, such as RAID level, just
1128 * return DEVICE_UPDATED, along with the updated device's location in index.
1129 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1130 */
1131static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1132 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1133 int *index)
1134{
1135 int i;
1136#define DEVICE_NOT_FOUND 0
1137#define DEVICE_CHANGED 1
1138#define DEVICE_SAME 2
bd9244f7 1139#define DEVICE_UPDATED 3
edd16368 1140 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1141 if (haystack[i] == NULL) /* previously removed. */
1142 continue;
edd16368
SC		 1143 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1144 *index = i;
bd9244f7
ST		 1145 if (device_is_the_same(needle, haystack[i])) {
1146 if (device_updated(needle, haystack[i]))
1147 return DEVICE_UPDATED;
edd16368 1148 return DEVICE_SAME;
bd9244f7 1149 } else {
9846590e
SC		 1150 /* Keep offline devices offline */
1151 if (needle->volume_offline)
1152 return DEVICE_NOT_FOUND;
edd16368 1153 return DEVICE_CHANGED;
bd9244f7 1154 }
edd16368
SC		 1155 }
1156 }
1157 *index = -1;
1158 return DEVICE_NOT_FOUND;
1159}
1160
9846590e
SC		 1161static void hpsa_monitor_offline_device(struct ctlr_info *h,
1162 unsigned char scsi3addr[])
1163{
1164 struct offline_device_entry *device;
1165 unsigned long flags;
1166
1167 /* Check to see if device is already on the list */
1168 spin_lock_irqsave(&h->offline_device_lock, flags);
1169 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1170 if (memcmp(device->scsi3addr, scsi3addr,
1171 sizeof(device->scsi3addr)) == 0) {
1172 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1173 return;
1174 }
1175 }
1176 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1177
1178 /* Device is not on the list, add it. */
1179 device = kmalloc(sizeof(*device), GFP_KERNEL);
1180 if (!device) {
1181 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1182 return;
1183 }
1184 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1185 spin_lock_irqsave(&h->offline_device_lock, flags);
1186 list_add_tail(&device->offline_list, &h->offline_device_list);
1187 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1188}
1189
1190/* Print a message explaining various offline volume states */
1191static void hpsa_show_volume_status(struct ctlr_info *h,
1192 struct hpsa_scsi_dev_t *sd)
1193{
1194 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1195 dev_info(&h->pdev->dev,
1196 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1197 h->scsi_host->host_no,
1198 sd->bus, sd->target, sd->lun);
1199 switch (sd->volume_offline) {
1200 case HPSA_LV_OK:
1201 break;
1202 case HPSA_LV_UNDERGOING_ERASE:
1203 dev_info(&h->pdev->dev,
1204 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1205 h->scsi_host->host_no,
1206 sd->bus, sd->target, sd->lun);
1207 break;
1208 case HPSA_LV_UNDERGOING_RPI:
1209 dev_info(&h->pdev->dev,
1210 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1211 h->scsi_host->host_no,
1212 sd->bus, sd->target, sd->lun);
1213 break;
1214 case HPSA_LV_PENDING_RPI:
1215 dev_info(&h->pdev->dev,
1216 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1217 h->scsi_host->host_no,
1218 sd->bus, sd->target, sd->lun);
1219 break;
1220 case HPSA_LV_ENCRYPTED_NO_KEY:
1221 dev_info(&h->pdev->dev,
1222 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1223 h->scsi_host->host_no,
1224 sd->bus, sd->target, sd->lun);
1225 break;
1226 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1227 dev_info(&h->pdev->dev,
1228 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1229 h->scsi_host->host_no,
1230 sd->bus, sd->target, sd->lun);
1231 break;
1232 case HPSA_LV_UNDERGOING_ENCRYPTION:
1233 dev_info(&h->pdev->dev,
1234 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1235 h->scsi_host->host_no,
1236 sd->bus, sd->target, sd->lun);
1237 break;
1238 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1239 dev_info(&h->pdev->dev,
1240 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1241 h->scsi_host->host_no,
1242 sd->bus, sd->target, sd->lun);
1243 break;
1244 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1245 dev_info(&h->pdev->dev,
1246 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1247 h->scsi_host->host_no,
1248 sd->bus, sd->target, sd->lun);
1249 break;
1250 case HPSA_LV_PENDING_ENCRYPTION:
1251 dev_info(&h->pdev->dev,
1252 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1253 h->scsi_host->host_no,
1254 sd->bus, sd->target, sd->lun);
1255 break;
1256 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1257 dev_info(&h->pdev->dev,
1258 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1259 h->scsi_host->host_no,
1260 sd->bus, sd->target, sd->lun);
1261 break;
1262 }
1263}
1264
4967bd3e 1265static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1266 struct hpsa_scsi_dev_t *sd[], int nsds)
1267{
1268 /* sd contains scsi3 addresses and devtypes, and inquiry
1269 * data. This function takes what's in sd to be the current
1270 * reality and updates h->dev[] to reflect that reality.
1271 */
1272 int i, entry, device_change, changes = 0;
1273 struct hpsa_scsi_dev_t *csd;
1274 unsigned long flags;
1275 struct hpsa_scsi_dev_t **added, **removed;
1276 int nadded, nremoved;
1277 struct Scsi_Host *sh = NULL;
1278
cfe5badc
ST		 1279 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1280 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1281
1282 if (!added || !removed) {
1283 dev_warn(&h->pdev->dev, "out of memory in "
1284 "adjust_hpsa_scsi_table\n");
1285 goto free_and_out;
1286 }
1287
1288 spin_lock_irqsave(&h->devlock, flags);
1289
1290 /* find any devices in h->dev[] that are not in
1291 * sd[] and remove them from h->dev[], and for any
1292 * devices which have changed, remove the old device
1293 * info and add the new device info.
bd9244f7
ST		 1294 * If minor device attributes change, just update
1295 * the existing device structure.
edd16368
SC		 1296 */
1297 i = 0;
1298 nremoved = 0;
1299 nadded = 0;
1300 while (i < h->ndevices) {
1301 csd = h->dev[i];
1302 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1303 if (device_change == DEVICE_NOT_FOUND) {
1304 changes++;
1305 hpsa_scsi_remove_entry(h, hostno, i,
1306 removed, &nremoved);
1307 continue; /* remove ^^^, hence i not incremented */
1308 } else if (device_change == DEVICE_CHANGED) {
1309 changes++;
2a8ccf31
SC		 1310 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1311 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1312 /* Set it to NULL to prevent it from being freed
1313 * at the bottom of hpsa_update_scsi_devices()
1314 */
1315 sd[entry] = NULL;
bd9244f7
ST		 1316 } else if (device_change == DEVICE_UPDATED) {
1317 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1318 }
1319 i++;
1320 }
1321
1322 /* Now, make sure every device listed in sd[] is also
1323 * listed in h->dev[], adding them if they aren't found
1324 */
1325
1326 for (i = 0; i < nsds; i++) {
1327 if (!sd[i]) /* if already added above. */
1328 continue;
9846590e
SC		 1329
1330 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1331 * as the SCSI mid-layer does not handle such devices well.
1332 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1333 * at 160Hz, and prevents the system from coming up.
1334 */
1335 if (sd[i]->volume_offline) {
1336 hpsa_show_volume_status(h, sd[i]);
1337 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1338 h->scsi_host->host_no,
1339 sd[i]->bus, sd[i]->target, sd[i]->lun);
1340 continue;
1341 }
1342
edd16368
SC		 1343 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1344 h->ndevices, &entry);
1345 if (device_change == DEVICE_NOT_FOUND) {
1346 changes++;
1347 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1348 added, &nadded) != 0)
1349 break;
1350 sd[i] = NULL; /* prevent from being freed later. */
1351 } else if (device_change == DEVICE_CHANGED) {
1352 /* should never happen... */
1353 changes++;
1354 dev_warn(&h->pdev->dev,
1355 "device unexpectedly changed.\n");
1356 /* but if it does happen, we just ignore that device */
1357 }
1358 }
1359 spin_unlock_irqrestore(&h->devlock, flags);
1360
9846590e
SC		 1361 /* Monitor devices which are in one of several NOT READY states to be
1362 * brought online later. This must be done without holding h->devlock,
1363 * so don't touch h->dev[]
1364 */
1365 for (i = 0; i < nsds; i++) {
1366 if (!sd[i]) /* if already added above. */
1367 continue;
1368 if (sd[i]->volume_offline)
1369 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1370 }
1371
edd16368
SC		 1372 /* Don't notify scsi mid layer of any changes the first time through
1373 * (or if there are no changes) scsi_scan_host will do it later the
1374 * first time through.
1375 */
1376 if (hostno == -1 || !changes)
1377 goto free_and_out;
1378
1379 sh = h->scsi_host;
1380 /* Notify scsi mid layer of any removed devices */
1381 for (i = 0; i < nremoved; i++) {
1382 struct scsi_device *sdev =
1383 scsi_device_lookup(sh, removed[i]->bus,
1384 removed[i]->target, removed[i]->lun);
1385 if (sdev != NULL) {
1386 scsi_remove_device(sdev);
1387 scsi_device_put(sdev);
1388 } else {
1389 /* We don't expect to get here.
1390 * future cmds to this device will get selection
1391 * timeout as if the device was gone.
1392 */
1393 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1394 " for removal.", hostno, removed[i]->bus,
1395 removed[i]->target, removed[i]->lun);
1396 }
1397 kfree(removed[i]);
1398 removed[i] = NULL;
1399 }
1400
1401 /* Notify scsi mid layer of any added devices */
1402 for (i = 0; i < nadded; i++) {
1403 if (scsi_add_device(sh, added[i]->bus,
1404 added[i]->target, added[i]->lun) == 0)
1405 continue;
1406 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1407 "device not added.\n", hostno, added[i]->bus,
1408 added[i]->target, added[i]->lun);
1409 /* now we have to remove it from h->dev,
1410 * since it didn't get added to scsi mid layer
1411 */
1412 fixup_botched_add(h, added[i]);
1413 }
1414
1415free_and_out:
1416 kfree(added);
1417 kfree(removed);
edd16368
SC		 1418}
1419
1420/*
9e03aa2f 1421 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1422 * Assume's h->devlock is held.
1423 */
1424static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1425 int bus, int target, int lun)
1426{
1427 int i;
1428 struct hpsa_scsi_dev_t *sd;
1429
1430 for (i = 0; i < h->ndevices; i++) {
1431 sd = h->dev[i];
1432 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1433 return sd;
1434 }
1435 return NULL;
1436}
1437
1438/* link sdev->hostdata to our per-device structure. */
1439static int hpsa_slave_alloc(struct scsi_device *sdev)
1440{
1441 struct hpsa_scsi_dev_t *sd;
1442 unsigned long flags;
1443 struct ctlr_info *h;
1444
1445 h = sdev_to_hba(sdev);
1446 spin_lock_irqsave(&h->devlock, flags);
1447 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1448 sdev_id(sdev), sdev->lun);
1449 if (sd != NULL)
1450 sdev->hostdata = sd;
1451 spin_unlock_irqrestore(&h->devlock, flags);
1452 return 0;
1453}
1454
1455static void hpsa_slave_destroy(struct scsi_device *sdev)
1456{
bcc44255 1457 /* nothing to do. */
edd16368
SC		 1458}
1459
33a2ffce
SC		 1460static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1461{
1462 int i;
1463
1464 if (!h->cmd_sg_list)
1465 return;
1466 for (i = 0; i < h->nr_cmds; i++) {
1467 kfree(h->cmd_sg_list[i]);
1468 h->cmd_sg_list[i] = NULL;
1469 }
1470 kfree(h->cmd_sg_list);
1471 h->cmd_sg_list = NULL;
1472}
1473
1474static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1475{
1476 int i;
1477
1478 if (h->chainsize <= 0)
1479 return 0;
1480
1481 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1482 GFP_KERNEL);
1483 if (!h->cmd_sg_list)
1484 return -ENOMEM;
1485 for (i = 0; i < h->nr_cmds; i++) {
1486 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1487 h->chainsize, GFP_KERNEL);
1488 if (!h->cmd_sg_list[i])
1489 goto clean;
1490 }
1491 return 0;
1492
1493clean:
1494 hpsa_free_sg_chain_blocks(h);
1495 return -ENOMEM;
1496}
1497
e2bea6df 1498static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1499 struct CommandList *c)
1500{
1501 struct SGDescriptor *chain_sg, *chain_block;
1502 u64 temp64;
50a0decf 1503 u32 chain_len;
33a2ffce
SC		 1504
1505 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1506 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1507 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1508 chain_len = sizeof(*chain_sg) *
33a2ffce 1509 (c->Header.SGTotal - h->max_cmd_sg_entries);
50a0decf
SC		 1510 chain_sg->Len = cpu_to_le32(chain_len);
1511 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1512 PCI_DMA_TODEVICE);
e2bea6df
SC		 1513 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1514 /* prevent subsequent unmapping */
50a0decf 1515 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1516 return -1;
1517 }
50a0decf 1518 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1519 return 0;
33a2ffce
SC		 1520}
1521
1522static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1523 struct CommandList *c)
1524{
1525 struct SGDescriptor *chain_sg;
33a2ffce 1526
50a0decf 1527 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1528 return;
1529
1530 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1531 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1532 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1533}
1534
a09c1441
ST		 1535
1536/* Decode the various types of errors on ioaccel2 path.
1537 * Return 1 for any error that should generate a RAID path retry.
1538 * Return 0 for errors that don't require a RAID path retry.
1539 */
1540static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1541 struct CommandList *c,
1542 struct scsi_cmnd *cmd,
1543 struct io_accel2_cmd *c2)
1544{
1545 int data_len;
a09c1441 1546 int retry = 0;
c349775e
ST		 1547
1548 switch (c2->error_data.serv_response) {
1549 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1550 switch (c2->error_data.status) {
1551 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1552 break;
1553 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1554 dev_warn(&h->pdev->dev,
1555 "%s: task complete with check condition.\n",
1556 "HP SSD Smart Path");
ee6b1889 1557 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1558 if (c2->error_data.data_present !=
ee6b1889
SC		 1559 IOACCEL2_SENSE_DATA_PRESENT) {
1560 memset(cmd->sense_buffer, 0,
1561 SCSI_SENSE_BUFFERSIZE);
c349775e 1562 break;
ee6b1889 1563 }
c349775e
ST		 1564 /* copy the sense data */
1565 data_len = c2->error_data.sense_data_len;
1566 if (data_len > SCSI_SENSE_BUFFERSIZE)
1567 data_len = SCSI_SENSE_BUFFERSIZE;
1568 if (data_len > sizeof(c2->error_data.sense_data_buff))
1569 data_len =
1570 sizeof(c2->error_data.sense_data_buff);
1571 memcpy(cmd->sense_buffer,
1572 c2->error_data.sense_data_buff, data_len);
a09c1441 1573 retry = 1;
c349775e
ST		 1574 break;
1575 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1576 dev_warn(&h->pdev->dev,
1577 "%s: task complete with BUSY status.\n",
1578 "HP SSD Smart Path");
a09c1441 1579 retry = 1;
c349775e
ST		 1580 break;
1581 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1582 dev_warn(&h->pdev->dev,
1583 "%s: task complete with reservation conflict.\n",
1584 "HP SSD Smart Path");
a09c1441 1585 retry = 1;
c349775e
ST		 1586 break;
1587 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1588 /* Make scsi midlayer do unlimited retries */
1589 cmd->result = DID_IMM_RETRY << 16;
1590 break;
1591 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1592 dev_warn(&h->pdev->dev,
1593 "%s: task complete with aborted status.\n",
1594 "HP SSD Smart Path");
a09c1441 1595 retry = 1;
c349775e
ST		 1596 break;
1597 default:
1598 dev_warn(&h->pdev->dev,
1599 "%s: task complete with unrecognized status: 0x%02x\n",
1600 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1601 retry = 1;
c349775e
ST		 1602 break;
1603 }
1604 break;
1605 case IOACCEL2_SERV_RESPONSE_FAILURE:
1606 /* don't expect to get here. */
1607 dev_warn(&h->pdev->dev,
1608 "unexpected delivery or target failure, status = 0x%02x\n",
1609 c2->error_data.status);
a09c1441 1610 retry = 1;
c349775e
ST		 1611 break;
1612 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1613 break;
1614 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1615 break;
1616 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1617 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1618 retry = 1;
c349775e
ST		 1619 break;
1620 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1621 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1622 break;
1623 default:
1624 dev_warn(&h->pdev->dev,
1625 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1626 "HP SSD Smart Path",
1627 c2->error_data.serv_response);
1628 retry = 1;
c349775e
ST		 1629 break;
1630 }
a09c1441
ST		 1631
1632 return retry; /* retry on raid path? */
c349775e
ST		 1633}
1634
1635static void process_ioaccel2_completion(struct ctlr_info *h,
1636 struct CommandList *c, struct scsi_cmnd *cmd,
1637 struct hpsa_scsi_dev_t *dev)
1638{
1639 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1640 int raid_retry = 0;
c349775e
ST		 1641
1642 /* check for good status */
1643 if (likely(c2->error_data.serv_response == 0 &&
1644 c2->error_data.status == 0)) {
1645 cmd_free(h, c);
1646 cmd->scsi_done(cmd);
1647 return;
1648 }
1649
1650 /* Any RAID offload error results in retry which will use
1651 * the normal I/O path so the controller can handle whatever's
1652 * wrong.
1653 */
1654 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1655 c2->error_data.serv_response ==
1656 IOACCEL2_SERV_RESPONSE_FAILURE) {
c349775e 1657 dev->offload_enabled = 0;
e863d68e 1658 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1659 cmd->result = DID_SOFT_ERROR << 16;
1660 cmd_free(h, c);
1661 cmd->scsi_done(cmd);
1662 return;
1663 }
a09c1441
ST		 1664 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1665 /* If error found, disable Smart Path, schedule a rescan,
1666 * and force a retry on the standard path.
1667 */
1668 if (raid_retry) {
1669 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1670 "HP SSD Smart Path");
1671 dev->offload_enabled = 0; /* Disable Smart Path */
1672 h->drv_req_rescan = 1; /* schedule controller rescan */
1673 cmd->result = DID_SOFT_ERROR << 16;
1674 }
c349775e
ST		 1675 cmd_free(h, c);
1676 cmd->scsi_done(cmd);
1677}
1678
1fb011fb 1679static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1680{
1681 struct scsi_cmnd *cmd;
1682 struct ctlr_info *h;
1683 struct ErrorInfo *ei;
283b4a9b 1684 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1685
1686 unsigned char sense_key;
1687 unsigned char asc; /* additional sense code */
1688 unsigned char ascq; /* additional sense code qualifier */
db111e18 1689 unsigned long sense_data_size;
edd16368
SC		 1690
1691 ei = cp->err_info;
1692 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1693 h = cp->h;
283b4a9b 1694 dev = cmd->device->hostdata;
edd16368
SC		 1695
1696 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1697 if ((cp->cmd_type == CMD_SCSI) &&
1698 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1699 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1700
1701 cmd->result = (DID_OK << 16); /* host byte */
1702 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1703
1704 if (cp->cmd_type == CMD_IOACCEL2)
1705 return process_ioaccel2_completion(h, cp, cmd, dev);
1706
5512672f 1707 cmd->result |= ei->ScsiStatus;
edd16368 1708
6aa4c361
RE		 1709 scsi_set_resid(cmd, ei->ResidualCnt);
1710 if (ei->CommandStatus == 0) {
1711 cmd_free(h, cp);
1712 cmd->scsi_done(cmd);
1713 return;
1714 }
1715
1716 /* copy the sense data */
db111e18
SC		 1717 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1718 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1719 else
1720 sense_data_size = sizeof(ei->SenseInfo);
1721 if (ei->SenseLen < sense_data_size)
1722 sense_data_size = ei->SenseLen;
1723
1724 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368 1725
e1f7de0c
MG		 1726 /* For I/O accelerator commands, copy over some fields to the normal
1727 * CISS header used below for error handling.
1728 */
1729 if (cp->cmd_type == CMD_IOACCEL1) {
1730 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1731 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1732 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 1733 cp->Header.tag = c->tag;
e1f7de0c
MG		 1734 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1735 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1736
1737 /* Any RAID offload error results in retry which will use
1738 * the normal I/O path so the controller can handle whatever's
1739 * wrong.
1740 */
1741 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1742 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1743 dev->offload_enabled = 0;
1744 cmd->result = DID_SOFT_ERROR << 16;
1745 cmd_free(h, cp);
1746 cmd->scsi_done(cmd);
1747 return;
1748 }
e1f7de0c
MG		 1749 }
1750
edd16368
SC		 1751 /* an error has occurred */
1752 switch (ei->CommandStatus) {
1753
1754 case CMD_TARGET_STATUS:
1755 if (ei->ScsiStatus) {
1756 /* Get sense key */
1757 sense_key = 0xf & ei->SenseInfo[2];
1758 /* Get additional sense code */
1759 asc = ei->SenseInfo[12];
1760 /* Get addition sense code qualifier */
1761 ascq = ei->SenseInfo[13];
1762 }
edd16368 1763 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 1764 if (sense_key == ABORTED_COMMAND) {
2e311fba 1765 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1766 break;
1767 }
edd16368
SC		 1768 break;
1769 }
edd16368
SC		 1770 /* Problem was not a check condition
1771 * Pass it up to the upper layers...
1772 */
1773 if (ei->ScsiStatus) {
1774 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1775 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1776 "Returning result: 0x%x\n",
1777 cp, ei->ScsiStatus,
1778 sense_key, asc, ascq,
1779 cmd->result);
1780 } else { /* scsi status is zero??? How??? */
1781 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1782 "Returning no connection.\n", cp),
1783
1784 /* Ordinarily, this case should never happen,
1785 * but there is a bug in some released firmware
1786 * revisions that allows it to happen if, for
1787 * example, a 4100 backplane loses power and
1788 * the tape drive is in it. We assume that
1789 * it's a fatal error of some kind because we
1790 * can't show that it wasn't. We will make it
1791 * look like selection timeout since that is
1792 * the most common reason for this to occur,
1793 * and it's severe enough.
1794 */
1795
1796 cmd->result = DID_NO_CONNECT << 16;
1797 }
1798 break;
1799
1800 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1801 break;
1802 case CMD_DATA_OVERRUN:
1803 dev_warn(&h->pdev->dev, "cp %p has"
1804 " completed with data overrun "
1805 "reported\n", cp);
1806 break;
1807 case CMD_INVALID: {
1808 /* print_bytes(cp, sizeof(*cp), 1, 0);
1809 print_cmd(cp); */
1810 /* We get CMD_INVALID if you address a non-existent device
1811 * instead of a selection timeout (no response). You will
1812 * see this if you yank out a drive, then try to access it.
1813 * This is kind of a shame because it means that any other
1814 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1815 * missing target. */
1816 cmd->result = DID_NO_CONNECT << 16;
1817 }
1818 break;
1819 case CMD_PROTOCOL_ERR:
256d0eaa 1820 cmd->result = DID_ERROR << 16;
edd16368 1821 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1822 "protocol error\n", cp);
edd16368
SC		 1823 break;
1824 case CMD_HARDWARE_ERR:
1825 cmd->result = DID_ERROR << 16;
1826 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1827 break;
1828 case CMD_CONNECTION_LOST:
1829 cmd->result = DID_ERROR << 16;
1830 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1831 break;
1832 case CMD_ABORTED:
1833 cmd->result = DID_ABORT << 16;
1834 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1835 cp, ei->ScsiStatus);
1836 break;
1837 case CMD_ABORT_FAILED:
1838 cmd->result = DID_ERROR << 16;
1839 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1840 break;
1841 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1842 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1843 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1844 "abort\n", cp);
1845 break;
1846 case CMD_TIMEOUT:
1847 cmd->result = DID_TIME_OUT << 16;
1848 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1849 break;
1d5e2ed0
SC		 1850 case CMD_UNABORTABLE:
1851 cmd->result = DID_ERROR << 16;
1852 dev_warn(&h->pdev->dev, "Command unabortable\n");
1853 break;
283b4a9b
SC		 1854 case CMD_IOACCEL_DISABLED:
1855 /* This only handles the direct pass-through case since RAID
1856 * offload is handled above. Just attempt a retry.
1857 */
1858 cmd->result = DID_SOFT_ERROR << 16;
1859 dev_warn(&h->pdev->dev,
1860 "cp %p had HP SSD Smart Path error\n", cp);
1861 break;
edd16368
SC		 1862 default:
1863 cmd->result = DID_ERROR << 16;
1864 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1865 cp, ei->CommandStatus);
1866 }
edd16368 1867 cmd_free(h, cp);
2cc5bfaf 1868 cmd->scsi_done(cmd);
edd16368
SC		 1869}
1870
edd16368
SC		 1871static void hpsa_pci_unmap(struct pci_dev *pdev,
1872 struct CommandList *c, int sg_used, int data_direction)
1873{
1874 int i;
edd16368 1875
50a0decf
SC		 1876 for (i = 0; i < sg_used; i++)
1877 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
1878 le32_to_cpu(c->SG[i].Len),
1879 data_direction);
edd16368
SC		 1880}
1881
a2dac136 1882static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1883 struct CommandList *cp,
1884 unsigned char *buf,
1885 size_t buflen,
1886 int data_direction)
1887{
01a02ffc 1888 u64 addr64;
edd16368
SC		 1889
1890 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1891 cp->Header.SGList = 0;
50a0decf 1892 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1893 return 0;
edd16368
SC		 1894 }
1895
50a0decf 1896 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1897 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1898 /* Prevent subsequent unmap of something never mapped */
eceaae18 1899 cp->Header.SGList = 0;
50a0decf 1900 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 1901 return -1;
eceaae18 1902 }
50a0decf
SC		 1903 cp->SG[0].Addr = cpu_to_le64(addr64);
1904 cp->SG[0].Len = cpu_to_le32(buflen);
1905 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
1906 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
1907 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 1908 return 0;
edd16368
SC		 1909}
1910
1911static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1912 struct CommandList *c)
1913{
1914 DECLARE_COMPLETION_ONSTACK(wait);
1915
1916 c->waiting = &wait;
1917 enqueue_cmd_and_start_io(h, c);
1918 wait_for_completion(&wait);
1919}
1920
094963da
SC		 1921static u32 lockup_detected(struct ctlr_info *h)
1922{
1923 int cpu;
1924 u32 rc, *lockup_detected;
1925
1926 cpu = get_cpu();
1927 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
1928 rc = *lockup_detected;
1929 put_cpu();
1930 return rc;
1931}
1932
a0c12413
SC		 1933static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1934 struct CommandList *c)
1935{
a0c12413 1936 /* If controller lockup detected, fake a hardware error. */
094963da 1937 if (unlikely(lockup_detected(h)))
a0c12413 1938 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
094963da 1939 else
a0c12413 1940 hpsa_scsi_do_simple_cmd_core(h, c);
a0c12413
SC		 1941}
1942
9c2fc160 1943#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1944static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1945 struct CommandList *c, int data_direction)
1946{
9c2fc160 1947 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1948
1949 do {
7630abd0 1950 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1951 hpsa_scsi_do_simple_cmd_core(h, c);
1952 retry_count++;
9c2fc160
SC		 1953 if (retry_count > 3) {
1954 msleep(backoff_time);
1955 if (backoff_time < 1000)
1956 backoff_time *= 2;
1957 }
852af20a 1958 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1959 check_for_busy(h, c)) &&
1960 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1961 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1962}
1963
d1e8beac
SC		 1964static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
1965 struct CommandList *c)
edd16368 1966{
d1e8beac
SC		 1967 const u8 *cdb = c->Request.CDB;
1968 const u8 *lun = c->Header.LUN.LunAddrBytes;
1969
1970 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
1971 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1972 txt, lun[0], lun[1], lun[2], lun[3],
1973 lun[4], lun[5], lun[6], lun[7],
1974 cdb[0], cdb[1], cdb[2], cdb[3],
1975 cdb[4], cdb[5], cdb[6], cdb[7],
1976 cdb[8], cdb[9], cdb[10], cdb[11],
1977 cdb[12], cdb[13], cdb[14], cdb[15]);
1978}
1979
1980static void hpsa_scsi_interpret_error(struct ctlr_info *h,
1981 struct CommandList *cp)
1982{
1983 const struct ErrorInfo *ei = cp->err_info;
edd16368 1984 struct device *d = &cp->h->pdev->dev;
d1e8beac 1985 const u8 *sd = ei->SenseInfo;
edd16368 1986
edd16368
SC		 1987 switch (ei->CommandStatus) {
1988 case CMD_TARGET_STATUS:
d1e8beac
SC		 1989 hpsa_print_cmd(h, "SCSI status", cp);
1990 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
1991 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
1992 sd[2] & 0x0f, sd[12], sd[13]);
1993 else
1994 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 1995 if (ei->ScsiStatus == 0)
1996 dev_warn(d, "SCSI status is abnormally zero. "
1997 "(probably indicates selection timeout "
1998 "reported incorrectly due to a known "
1999 "firmware bug, circa July, 2001.)\n");
2000 break;
2001 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2002 break;
2003 case CMD_DATA_OVERRUN:
d1e8beac 2004 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2005 break;
2006 case CMD_INVALID: {
2007 /* controller unfortunately reports SCSI passthru's
2008 * to non-existent targets as invalid commands.
2009 */
d1e8beac
SC		 2010 hpsa_print_cmd(h, "invalid command", cp);
2011 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2012 }
2013 break;
2014 case CMD_PROTOCOL_ERR:
d1e8beac 2015 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2016 break;
2017 case CMD_HARDWARE_ERR:
d1e8beac 2018 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2019 break;
2020 case CMD_CONNECTION_LOST:
d1e8beac 2021 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2022 break;
2023 case CMD_ABORTED:
d1e8beac 2024 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2025 break;
2026 case CMD_ABORT_FAILED:
d1e8beac 2027 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2028 break;
2029 case CMD_UNSOLICITED_ABORT:
d1e8beac 2030 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2031 break;
2032 case CMD_TIMEOUT:
d1e8beac 2033 hpsa_print_cmd(h, "timed out", cp);
edd16368 2034 break;
1d5e2ed0 2035 case CMD_UNABORTABLE:
d1e8beac 2036 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2037 break;
edd16368 2038 default:
d1e8beac
SC		 2039 hpsa_print_cmd(h, "unknown status", cp);
2040 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2041 ei->CommandStatus);
2042 }
2043}
2044
2045static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2046 u16 page, unsigned char *buf,
edd16368
SC		 2047 unsigned char bufsize)
2048{
2049 int rc = IO_OK;
2050 struct CommandList *c;
2051 struct ErrorInfo *ei;
2052
2053 c = cmd_special_alloc(h);
2054
2055 if (c == NULL) { /* trouble... */
2056 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2057 return -ENOMEM;
edd16368
SC		 2058 }
2059
a2dac136
SC		 2060 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2061 page, scsi3addr, TYPE_CMD)) {
2062 rc = -1;
2063 goto out;
2064 }
edd16368
SC		 2065 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2066 ei = c->err_info;
2067 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2068 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2069 rc = -1;
2070 }
a2dac136 2071out:
edd16368
SC		 2072 cmd_special_free(h, c);
2073 return rc;
2074}
2075
316b221a
SC		 2076static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2077 unsigned char *scsi3addr, unsigned char page,
2078 struct bmic_controller_parameters *buf, size_t bufsize)
2079{
2080 int rc = IO_OK;
2081 struct CommandList *c;
2082 struct ErrorInfo *ei;
2083
2084 c = cmd_special_alloc(h);
2085
2086 if (c == NULL) { /* trouble... */
2087 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2088 return -ENOMEM;
2089 }
2090
2091 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2092 page, scsi3addr, TYPE_CMD)) {
2093 rc = -1;
2094 goto out;
2095 }
2096 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2097 ei = c->err_info;
2098 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2099 hpsa_scsi_interpret_error(h, c);
2100 rc = -1;
2101 }
2102out:
2103 cmd_special_free(h, c);
2104 return rc;
2105 }
2106
bf711ac6
ST		 2107static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2108 u8 reset_type)
edd16368
SC		 2109{
2110 int rc = IO_OK;
2111 struct CommandList *c;
2112 struct ErrorInfo *ei;
2113
2114 c = cmd_special_alloc(h);
2115
2116 if (c == NULL) { /* trouble... */
2117 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2118 return -ENOMEM;
edd16368
SC		 2119 }
2120
a2dac136 2121 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2122 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2123 scsi3addr, TYPE_MSG);
2124 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2125 hpsa_scsi_do_simple_cmd_core(h, c);
2126 /* no unmap needed here because no data xfer. */
2127
2128 ei = c->err_info;
2129 if (ei->CommandStatus != 0) {
d1e8beac 2130 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2131 rc = -1;
2132 }
2133 cmd_special_free(h, c);
2134 return rc;
2135}
2136
2137static void hpsa_get_raid_level(struct ctlr_info *h,
2138 unsigned char *scsi3addr, unsigned char *raid_level)
2139{
2140 int rc;
2141 unsigned char *buf;
2142
2143 *raid_level = RAID_UNKNOWN;
2144 buf = kzalloc(64, GFP_KERNEL);
2145 if (!buf)
2146 return;
b7bb24eb 2147 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2148 if (rc == 0)
2149 *raid_level = buf[8];
2150 if (*raid_level > RAID_UNKNOWN)
2151 *raid_level = RAID_UNKNOWN;
2152 kfree(buf);
2153 return;
2154}
2155
283b4a9b
SC		 2156#define HPSA_MAP_DEBUG
2157#ifdef HPSA_MAP_DEBUG
2158static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2159 struct raid_map_data *map_buff)
2160{
2161 struct raid_map_disk_data *dd = &map_buff->data[0];
2162 int map, row, col;
2163 u16 map_cnt, row_cnt, disks_per_row;
2164
2165 if (rc != 0)
2166 return;
2167
2ba8bfc8
SC		 2168 /* Show details only if debugging has been activated. */
2169 if (h->raid_offload_debug < 2)
2170 return;
2171
283b4a9b
SC		 2172 dev_info(&h->pdev->dev, "structure_size = %u\n",
2173 le32_to_cpu(map_buff->structure_size));
2174 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2175 le32_to_cpu(map_buff->volume_blk_size));
2176 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2177 le64_to_cpu(map_buff->volume_blk_cnt));
2178 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2179 map_buff->phys_blk_shift);
2180 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2181 map_buff->parity_rotation_shift);
2182 dev_info(&h->pdev->dev, "strip_size = %u\n",
2183 le16_to_cpu(map_buff->strip_size));
2184 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2185 le64_to_cpu(map_buff->disk_starting_blk));
2186 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2187 le64_to_cpu(map_buff->disk_blk_cnt));
2188 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2189 le16_to_cpu(map_buff->data_disks_per_row));
2190 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2191 le16_to_cpu(map_buff->metadata_disks_per_row));
2192 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2193 le16_to_cpu(map_buff->row_cnt));
2194 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2195 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2196 dev_info(&h->pdev->dev, "flags = %u\n",
2197 le16_to_cpu(map_buff->flags));
2198 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2199 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2200 else
2201 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2202 dev_info(&h->pdev->dev, "dekindex = %u\n",
2203 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2204
2205 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2206 for (map = 0; map < map_cnt; map++) {
2207 dev_info(&h->pdev->dev, "Map%u:\n", map);
2208 row_cnt = le16_to_cpu(map_buff->row_cnt);
2209 for (row = 0; row < row_cnt; row++) {
2210 dev_info(&h->pdev->dev, " Row%u:\n", row);
2211 disks_per_row =
2212 le16_to_cpu(map_buff->data_disks_per_row);
2213 for (col = 0; col < disks_per_row; col++, dd++)
2214 dev_info(&h->pdev->dev,
2215 " D%02u: h=0x%04x xor=%u,%u\n",
2216 col, dd->ioaccel_handle,
2217 dd->xor_mult[0], dd->xor_mult[1]);
2218 disks_per_row =
2219 le16_to_cpu(map_buff->metadata_disks_per_row);
2220 for (col = 0; col < disks_per_row; col++, dd++)
2221 dev_info(&h->pdev->dev,
2222 " M%02u: h=0x%04x xor=%u,%u\n",
2223 col, dd->ioaccel_handle,
2224 dd->xor_mult[0], dd->xor_mult[1]);
2225 }
2226 }
2227}
2228#else
2229static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2230 __attribute__((unused)) int rc,
2231 __attribute__((unused)) struct raid_map_data *map_buff)
2232{
2233}
2234#endif
2235
2236static int hpsa_get_raid_map(struct ctlr_info *h,
2237 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2238{
2239 int rc = 0;
2240 struct CommandList *c;
2241 struct ErrorInfo *ei;
2242
2243 c = cmd_special_alloc(h);
2244 if (c == NULL) {
2245 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2246 return -ENOMEM;
2247 }
2248 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2249 sizeof(this_device->raid_map), 0,
2250 scsi3addr, TYPE_CMD)) {
2251 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2252 cmd_special_free(h, c);
2253 return -ENOMEM;
2254 }
2255 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2256 ei = c->err_info;
2257 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2258 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2259 cmd_special_free(h, c);
2260 return -1;
2261 }
2262 cmd_special_free(h, c);
2263
2264 /* @todo in the future, dynamically allocate RAID map memory */
2265 if (le32_to_cpu(this_device->raid_map.structure_size) >
2266 sizeof(this_device->raid_map)) {
2267 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2268 rc = -1;
2269 }
2270 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2271 return rc;
2272}
2273
1b70150a
SC		 2274static int hpsa_vpd_page_supported(struct ctlr_info *h,
2275 unsigned char scsi3addr[], u8 page)
2276{
2277 int rc;
2278 int i;
2279 int pages;
2280 unsigned char *buf, bufsize;
2281
2282 buf = kzalloc(256, GFP_KERNEL);
2283 if (!buf)
2284 return 0;
2285
2286 /* Get the size of the page list first */
2287 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2288 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2289 buf, HPSA_VPD_HEADER_SZ);
2290 if (rc != 0)
2291 goto exit_unsupported;
2292 pages = buf[3];
2293 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2294 bufsize = pages + HPSA_VPD_HEADER_SZ;
2295 else
2296 bufsize = 255;
2297
2298 /* Get the whole VPD page list */
2299 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2300 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2301 buf, bufsize);
2302 if (rc != 0)
2303 goto exit_unsupported;
2304
2305 pages = buf[3];
2306 for (i = 1; i <= pages; i++)
2307 if (buf[3 + i] == page)
2308 goto exit_supported;
2309exit_unsupported:
2310 kfree(buf);
2311 return 0;
2312exit_supported:
2313 kfree(buf);
2314 return 1;
2315}
2316
283b4a9b
SC		 2317static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2318 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2319{
2320 int rc;
2321 unsigned char *buf;
2322 u8 ioaccel_status;
2323
2324 this_device->offload_config = 0;
2325 this_device->offload_enabled = 0;
2326
2327 buf = kzalloc(64, GFP_KERNEL);
2328 if (!buf)
2329 return;
1b70150a
SC		 2330 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2331 goto out;
283b4a9b 2332 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2333 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2334 if (rc != 0)
2335 goto out;
2336
2337#define IOACCEL_STATUS_BYTE 4
2338#define OFFLOAD_CONFIGURED_BIT 0x01
2339#define OFFLOAD_ENABLED_BIT 0x02
2340 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2341 this_device->offload_config =
2342 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2343 if (this_device->offload_config) {
2344 this_device->offload_enabled =
2345 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2346 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2347 this_device->offload_enabled = 0;
2348 }
2349out:
2350 kfree(buf);
2351 return;
2352}
2353
edd16368
SC		 2354/* Get the device id from inquiry page 0x83 */
2355static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2356 unsigned char *device_id, int buflen)
2357{
2358 int rc;
2359 unsigned char *buf;
2360
2361 if (buflen > 16)
2362 buflen = 16;
2363 buf = kzalloc(64, GFP_KERNEL);
2364 if (!buf)
a84d794d 2365 return -ENOMEM;
b7bb24eb 2366 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2367 if (rc == 0)
2368 memcpy(device_id, &buf[8], buflen);
2369 kfree(buf);
2370 return rc != 0;
2371}
2372
2373static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2374 struct ReportLUNdata *buf, int bufsize,
2375 int extended_response)
2376{
2377 int rc = IO_OK;
2378 struct CommandList *c;
2379 unsigned char scsi3addr[8];
2380 struct ErrorInfo *ei;
2381
2382 c = cmd_special_alloc(h);
2383 if (c == NULL) { /* trouble... */
2384 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2385 return -1;
2386 }
e89c0ae7
SC		 2387 /* address the controller */
2388 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2389 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2390 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2391 rc = -1;
2392 goto out;
2393 }
edd16368
SC		 2394 if (extended_response)
2395 c->Request.CDB[1] = extended_response;
2396 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2397 ei = c->err_info;
2398 if (ei->CommandStatus != 0 &&
2399 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2400 hpsa_scsi_interpret_error(h, c);
edd16368 2401 rc = -1;
283b4a9b
SC		 2402 } else {
2403 if (buf->extended_response_flag != extended_response) {
2404 dev_err(&h->pdev->dev,
2405 "report luns requested format %u, got %u\n",
2406 extended_response,
2407 buf->extended_response_flag);
2408 rc = -1;
2409 }
edd16368 2410 }
a2dac136 2411out:
edd16368
SC		 2412 cmd_special_free(h, c);
2413 return rc;
2414}
2415
2416static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2417 struct ReportLUNdata *buf,
2418 int bufsize, int extended_response)
2419{
2420 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2421}
2422
2423static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2424 struct ReportLUNdata *buf, int bufsize)
2425{
2426 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2427}
2428
2429static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2430 int bus, int target, int lun)
2431{
2432 device->bus = bus;
2433 device->target = target;
2434 device->lun = lun;
2435}
2436
9846590e
SC		 2437/* Use VPD inquiry to get details of volume status */
2438static int hpsa_get_volume_status(struct ctlr_info *h,
2439 unsigned char scsi3addr[])
2440{
2441 int rc;
2442 int status;
2443 int size;
2444 unsigned char *buf;
2445
2446 buf = kzalloc(64, GFP_KERNEL);
2447 if (!buf)
2448 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2449
2450 /* Does controller have VPD for logical volume status? */
24a4b078 2451 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2452 goto exit_failed;
9846590e
SC		 2453
2454 /* Get the size of the VPD return buffer */
2455 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2456 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2457 if (rc != 0)
9846590e 2458 goto exit_failed;
9846590e
SC		 2459 size = buf[3];
2460
2461 /* Now get the whole VPD buffer */
2462 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2463 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2464 if (rc != 0)
9846590e 2465 goto exit_failed;
9846590e
SC		 2466 status = buf[4]; /* status byte */
2467
2468 kfree(buf);
2469 return status;
2470exit_failed:
2471 kfree(buf);
2472 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2473}
2474
2475/* Determine offline status of a volume.
2476 * Return either:
2477 * 0 (not offline)
67955ba3 2478 * 0xff (offline for unknown reasons)
9846590e
SC		 2479 * # (integer code indicating one of several NOT READY states
2480 * describing why a volume is to be kept offline)
2481 */
67955ba3 2482static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2483 unsigned char scsi3addr[])
2484{
2485 struct CommandList *c;
2486 unsigned char *sense, sense_key, asc, ascq;
2487 int ldstat = 0;
2488 u16 cmd_status;
2489 u8 scsi_status;
2490#define ASC_LUN_NOT_READY 0x04
2491#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2492#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2493
2494 c = cmd_alloc(h);
2495 if (!c)
2496 return 0;
2497 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2498 hpsa_scsi_do_simple_cmd_core(h, c);
2499 sense = c->err_info->SenseInfo;
2500 sense_key = sense[2];
2501 asc = sense[12];
2502 ascq = sense[13];
2503 cmd_status = c->err_info->CommandStatus;
2504 scsi_status = c->err_info->ScsiStatus;
2505 cmd_free(h, c);
2506 /* Is the volume 'not ready'? */
2507 if (cmd_status != CMD_TARGET_STATUS ||
2508 scsi_status != SAM_STAT_CHECK_CONDITION ||
2509 sense_key != NOT_READY ||
2510 asc != ASC_LUN_NOT_READY) {
2511 return 0;
2512 }
2513
2514 /* Determine the reason for not ready state */
2515 ldstat = hpsa_get_volume_status(h, scsi3addr);
2516
2517 /* Keep volume offline in certain cases: */
2518 switch (ldstat) {
2519 case HPSA_LV_UNDERGOING_ERASE:
2520 case HPSA_LV_UNDERGOING_RPI:
2521 case HPSA_LV_PENDING_RPI:
2522 case HPSA_LV_ENCRYPTED_NO_KEY:
2523 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2524 case HPSA_LV_UNDERGOING_ENCRYPTION:
2525 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2526 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2527 return ldstat;
2528 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2529 /* If VPD status page isn't available,
2530 * use ASC/ASCQ to determine state
2531 */
2532 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2533 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2534 return ldstat;
2535 break;
2536 default:
2537 break;
2538 }
2539 return 0;
2540}
2541
edd16368 2542static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2543 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2544 unsigned char *is_OBDR_device)
edd16368 2545{
0b0e1d6c
SC		 2546
2547#define OBDR_SIG_OFFSET 43
2548#define OBDR_TAPE_SIG "$DR-10"
2549#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2550#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2551
ea6d3bc3 2552 unsigned char *inq_buff;
0b0e1d6c 2553 unsigned char *obdr_sig;
edd16368 2554
ea6d3bc3 2555 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2556 if (!inq_buff)
2557 goto bail_out;
2558
edd16368
SC		 2559 /* Do an inquiry to the device to see what it is. */
2560 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2561 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2562 /* Inquiry failed (msg printed already) */
2563 dev_err(&h->pdev->dev,
2564 "hpsa_update_device_info: inquiry failed\n");
2565 goto bail_out;
2566 }
2567
edd16368
SC		 2568 this_device->devtype = (inq_buff[0] & 0x1f);
2569 memcpy(this_device->scsi3addr, scsi3addr, 8);
2570 memcpy(this_device->vendor, &inq_buff[8],
2571 sizeof(this_device->vendor));
2572 memcpy(this_device->model, &inq_buff[16],
2573 sizeof(this_device->model));
edd16368
SC		 2574 memset(this_device->device_id, 0,
2575 sizeof(this_device->device_id));
2576 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2577 sizeof(this_device->device_id));
2578
2579 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2580 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 2581 int volume_offline;
2582
edd16368 2583 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2584 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2585 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 2586 volume_offline = hpsa_volume_offline(h, scsi3addr);
2587 if (volume_offline < 0 || volume_offline > 0xff)
2588 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
2589 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 2590 } else {
edd16368 2591 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2592 this_device->offload_config = 0;
2593 this_device->offload_enabled = 0;
9846590e 2594 this_device->volume_offline = 0;
283b4a9b 2595 }
edd16368 2596
0b0e1d6c
SC		 2597 if (is_OBDR_device) {
2598 /* See if this is a One-Button-Disaster-Recovery device
2599 * by looking for "$DR-10" at offset 43 in inquiry data.
2600 */
2601 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2602 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2603 strncmp(obdr_sig, OBDR_TAPE_SIG,
2604 OBDR_SIG_LEN) == 0);
2605 }
2606
edd16368
SC		 2607 kfree(inq_buff);
2608 return 0;
2609
2610bail_out:
2611 kfree(inq_buff);
2612 return 1;
2613}
2614
4f4eb9f1 2615static unsigned char *ext_target_model[] = {
edd16368
SC		 2616 "MSA2012",
2617 "MSA2024",
2618 "MSA2312",
2619 "MSA2324",
fda38518 2620 "P2000 G3 SAS",
e06c8e5c 2621 "MSA 2040 SAS",
edd16368
SC		 2622 NULL,
2623};
2624
4f4eb9f1 2625static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2626{
2627 int i;
2628
4f4eb9f1
ST		 2629 for (i = 0; ext_target_model[i]; i++)
2630 if (strncmp(device->model, ext_target_model[i],
2631 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2632 return 1;
2633 return 0;
2634}
2635
2636/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2637 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2638 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2639 * Logical drive target and lun are assigned at this time, but
2640 * physical device lun and target assignment are deferred (assigned
2641 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2642 */
2643static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2644 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2645{
1f310bde
SC		 2646 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2647
2648 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2649 /* physical device, target and lun filled in later */
edd16368 2650 if (is_hba_lunid(lunaddrbytes))
1f310bde 2651 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2652 else
1f310bde
SC		 2653 /* defer target, lun assignment for physical devices */
2654 hpsa_set_bus_target_lun(device, 2, -1, -1);
2655 return;
2656 }
2657 /* It's a logical device */
4f4eb9f1
ST		 2658 if (is_ext_target(h, device)) {
2659 /* external target way, put logicals on bus 1
1f310bde
SC		 2660 * and match target/lun numbers box
2661 * reports, other smart array, bus 0, target 0, match lunid
2662 */
2663 hpsa_set_bus_target_lun(device,
2664 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2665 return;
edd16368 2666 }
1f310bde 2667 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2668}
2669
2670/*
2671 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2672 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2673 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2674 * it for some reason. *tmpdevice is the target we're adding,
2675 * this_device is a pointer into the current element of currentsd[]
2676 * that we're building up in update_scsi_devices(), below.
2677 * lunzerobits is a bitmap that tracks which targets already have a
2678 * lun 0 assigned.
2679 * Returns 1 if an enclosure was added, 0 if not.
2680 */
4f4eb9f1 2681static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2682 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2683 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2684 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2685{
2686 unsigned char scsi3addr[8];
2687
1f310bde 2688 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2689 return 0; /* There is already a lun 0 on this target. */
2690
2691 if (!is_logical_dev_addr_mode(lunaddrbytes))
2692 return 0; /* It's the logical targets that may lack lun 0. */
2693
4f4eb9f1
ST		 2694 if (!is_ext_target(h, tmpdevice))
2695 return 0; /* Only external target devices have this problem. */
edd16368 2696
1f310bde 2697 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2698 return 0;
2699
c4f8a299 2700 memset(scsi3addr, 0, 8);
1f310bde 2701 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2702 if (is_hba_lunid(scsi3addr))
2703 return 0; /* Don't add the RAID controller here. */
2704
339b2b14
SC		 2705 if (is_scsi_rev_5(h))
2706 return 0; /* p1210m doesn't need to do this. */
2707
4f4eb9f1 2708 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2709 dev_warn(&h->pdev->dev, "Maximum number of external "
2710 "target devices exceeded. Check your hardware "
edd16368
SC		 2711 "configuration.");
2712 return 0;
2713 }
2714
0b0e1d6c 2715 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2716 return 0;
4f4eb9f1 2717 (*n_ext_target_devs)++;
1f310bde
SC		 2718 hpsa_set_bus_target_lun(this_device,
2719 tmpdevice->bus, tmpdevice->target, 0);
2720 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2721 return 1;
2722}
2723
54b6e9e9
ST		 2724/*
2725 * Get address of physical disk used for an ioaccel2 mode command:
2726 * 1. Extract ioaccel2 handle from the command.
2727 * 2. Find a matching ioaccel2 handle from list of physical disks.
2728 * 3. Return:
2729 * 1 and set scsi3addr to address of matching physical
2730 * 0 if no matching physical disk was found.
2731 */
2732static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2733 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2734{
2735 struct ReportExtendedLUNdata *physicals = NULL;
2736 int responsesize = 24; /* size of physical extended response */
2737 int extended = 2; /* flag forces reporting 'other dev info'. */
2738 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2739 u32 nphysicals = 0; /* number of reported physical devs */
2740 int found = 0; /* found match (1) or not (0) */
2741 u32 find; /* handle we need to match */
2742 int i;
2743 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2744 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2745 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2746 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2747 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2748
2749 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2750 return 0; /* no match */
2751
2752 /* point to the ioaccel2 device handle */
2753 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2754 if (c2a == NULL)
2755 return 0; /* no match */
2756
2757 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2758 if (scmd == NULL)
2759 return 0; /* no match */
2760
2761 d = scmd->device->hostdata;
2762 if (d == NULL)
2763 return 0; /* no match */
2764
50a0decf
SC		 2765 it_nexus = cpu_to_le32(d->ioaccel_handle);
2766 scsi_nexus = cpu_to_le32(c2a->scsi_nexus);
54b6e9e9
ST		 2767 find = c2a->scsi_nexus;
2768
2ba8bfc8
SC		 2769 if (h->raid_offload_debug > 0)
2770 dev_info(&h->pdev->dev,
2771 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2772 __func__, scsi_nexus,
2773 d->device_id[0], d->device_id[1], d->device_id[2],
2774 d->device_id[3], d->device_id[4], d->device_id[5],
2775 d->device_id[6], d->device_id[7], d->device_id[8],
2776 d->device_id[9], d->device_id[10], d->device_id[11],
2777 d->device_id[12], d->device_id[13], d->device_id[14],
2778 d->device_id[15]);
2779
54b6e9e9
ST		 2780 /* Get the list of physical devices */
2781 physicals = kzalloc(reportsize, GFP_KERNEL);
3b51a7a3
JH		 2782 if (physicals == NULL)
2783 return 0;
54b6e9e9
ST		 2784 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2785 reportsize, extended)) {
2786 dev_err(&h->pdev->dev,
2787 "Can't lookup %s device handle: report physical LUNs failed.\n",
2788 "HP SSD Smart Path");
2789 kfree(physicals);
2790 return 0;
2791 }
2792 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2793 responsesize;
2794
54b6e9e9
ST		 2795 /* find ioaccel2 handle in list of physicals: */
2796 for (i = 0; i < nphysicals; i++) {
d5b5d964
SC		 2797 struct ext_report_lun_entry *entry = &physicals->LUN[i];
2798
54b6e9e9 2799 /* handle is in bytes 28-31 of each lun */
d5b5d964 2800 if (entry->ioaccel_handle != find)
54b6e9e9 2801 continue; /* didn't match */
54b6e9e9 2802 found = 1;
d5b5d964 2803 memcpy(scsi3addr, entry->lunid, 8);
2ba8bfc8
SC		 2804 if (h->raid_offload_debug > 0)
2805 dev_info(&h->pdev->dev,
d5b5d964 2806 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n",
2ba8bfc8 2807 __func__, find,
d5b5d964 2808 entry->ioaccel_handle, scsi3addr);
54b6e9e9
ST		 2809 break; /* found it */
2810 }
2811
2812 kfree(physicals);
2813 if (found)
2814 return 1;
2815 else
2816 return 0;
2817
2818}
edd16368
SC		 2819/*
2820 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2821 * logdev. The number of luns in physdev and logdev are returned in
2822 * *nphysicals and *nlogicals, respectively.
2823 * Returns 0 on success, -1 otherwise.
2824 */
2825static int hpsa_gather_lun_info(struct ctlr_info *h,
92084715 2826 int reportphyslunsize, int reportloglunsize,
283b4a9b 2827 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2828 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2829{
283b4a9b
SC		 2830 int physical_entry_size = 8;
2831
2832 *physical_mode = 0;
2833
2834 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2835 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2836 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2837 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2838 physical_entry_size = 24;
2839 }
92084715 2840 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportphyslunsize,
283b4a9b 2841 *physical_mode)) {
edd16368
SC		 2842 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2843 return -1;
2844 }
283b4a9b
SC		 2845 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2846 physical_entry_size;
edd16368
SC		 2847 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2848 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2849 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2850 *nphysicals - HPSA_MAX_PHYS_LUN);
2851 *nphysicals = HPSA_MAX_PHYS_LUN;
2852 }
92084715 2853 if (hpsa_scsi_do_report_log_luns(h, logdev, reportloglunsize)) {
edd16368
SC		 2854 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2855 return -1;
2856 }
6df1e954 2857 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2858 /* Reject Logicals in excess of our max capability. */
2859 if (*nlogicals > HPSA_MAX_LUN) {
2860 dev_warn(&h->pdev->dev,
2861 "maximum logical LUNs (%d) exceeded. "
2862 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2863 *nlogicals - HPSA_MAX_LUN);
2864 *nlogicals = HPSA_MAX_LUN;
2865 }
2866 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2867 dev_warn(&h->pdev->dev,
2868 "maximum logical + physical LUNs (%d) exceeded. "
2869 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2870 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2871 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2872 }
2873 return 0;
2874}
2875
42a91641
DB		 2876static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
2877 int i, int nphysicals, int nlogicals,
a93aa1fe 2878 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2879 struct ReportLUNdata *logdev_list)
2880{
2881 /* Helper function, figure out where the LUN ID info is coming from
2882 * given index i, lists of physical and logical devices, where in
2883 * the list the raid controller is supposed to appear (first or last)
2884 */
2885
2886 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2887 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2888
2889 if (i == raid_ctlr_position)
2890 return RAID_CTLR_LUNID;
2891
2892 if (i < logicals_start)
d5b5d964
SC		 2893 return &physdev_list->LUN[i -
2894 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 2895
2896 if (i < last_device)
2897 return &logdev_list->LUN[i - nphysicals -
2898 (raid_ctlr_position == 0)][0];
2899 BUG();
2900 return NULL;
2901}
2902
316b221a
SC		 2903static int hpsa_hba_mode_enabled(struct ctlr_info *h)
2904{
2905 int rc;
6e8e8088 2906 int hba_mode_enabled;
316b221a
SC		 2907 struct bmic_controller_parameters *ctlr_params;
2908 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
2909 GFP_KERNEL);
2910
2911 if (!ctlr_params)
96444fbb 2912 return -ENOMEM;
316b221a
SC		 2913 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
2914 sizeof(struct bmic_controller_parameters));
96444fbb 2915 if (rc) {
316b221a 2916 kfree(ctlr_params);
96444fbb 2917 return rc;
316b221a 2918 }
6e8e8088
JH		 2919
2920 hba_mode_enabled =
2921 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
2922 kfree(ctlr_params);
2923 return hba_mode_enabled;
316b221a
SC		 2924}
2925
edd16368
SC		 2926static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2927{
2928 /* the idea here is we could get notified
2929 * that some devices have changed, so we do a report
2930 * physical luns and report logical luns cmd, and adjust
2931 * our list of devices accordingly.
2932 *
2933 * The scsi3addr's of devices won't change so long as the
2934 * adapter is not reset. That means we can rescan and
2935 * tell which devices we already know about, vs. new
2936 * devices, vs. disappearing devices.
2937 */
a93aa1fe 2938 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2939 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2940 u32 nphysicals = 0;
2941 u32 nlogicals = 0;
283b4a9b 2942 int physical_mode = 0;
01a02ffc 2943 u32 ndev_allocated = 0;
edd16368
SC		 2944 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2945 int ncurrent = 0;
4f4eb9f1 2946 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2947 int raid_ctlr_position;
2bbf5c7f 2948 int rescan_hba_mode;
aca4a520 2949 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2950
cfe5badc 2951 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 2952 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
2953 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368
SC		 2954 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2955
0b0e1d6c 2956 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2957 dev_err(&h->pdev->dev, "out of memory\n");
2958 goto out;
2959 }
2960 memset(lunzerobits, 0, sizeof(lunzerobits));
2961
316b221a 2962 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 2963 if (rescan_hba_mode < 0)
2964 goto out;
316b221a
SC		 2965
2966 if (!h->hba_mode_enabled && rescan_hba_mode)
2967 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
2968 else if (h->hba_mode_enabled && !rescan_hba_mode)
2969 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
2970
2971 h->hba_mode_enabled = rescan_hba_mode;
2972
92084715
SC		 2973 if (hpsa_gather_lun_info(h,
2974 sizeof(*physdev_list), sizeof(*logdev_list),
a93aa1fe 2975 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2976 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2977 goto out;
2978
aca4a520
ST		 2979 /* We might see up to the maximum number of logical and physical disks
2980 * plus external target devices, and a device for the local RAID
2981 * controller.
edd16368 2982 */
aca4a520 2983 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2984
2985 /* Allocate the per device structures */
2986 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2987 if (i >= HPSA_MAX_DEVICES) {
2988 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2989 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2990 ndevs_to_allocate - HPSA_MAX_DEVICES);
2991 break;
2992 }
2993
edd16368
SC		 2994 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2995 if (!currentsd[i]) {
2996 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2997 __FILE__, __LINE__);
2998 goto out;
2999 }
3000 ndev_allocated++;
3001 }
3002
8645291b 3003 if (is_scsi_rev_5(h))
339b2b14
SC		 3004 raid_ctlr_position = 0;
3005 else
3006 raid_ctlr_position = nphysicals + nlogicals;
3007
edd16368 3008 /* adjust our table of devices */
4f4eb9f1 3009 n_ext_target_devs = 0;
edd16368 3010 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3011 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3012
3013 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3014 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3015 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3016 /* skip masked physical devices. */
339b2b14
SC		 3017 if (lunaddrbytes[3] & 0xC0 &&
3018 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3019 continue;
3020
3021 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3022 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3023 &is_OBDR))
edd16368 3024 continue; /* skip it if we can't talk to it. */
1f310bde 3025 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3026 this_device = currentsd[ncurrent];
3027
3028 /*
4f4eb9f1 3029 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3030 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3031 * is nonetheless an enclosure device there. We have to
3032 * present that otherwise linux won't find anything if
3033 * there is no lun 0.
3034 */
4f4eb9f1 3035 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3036 lunaddrbytes, lunzerobits,
4f4eb9f1 3037 &n_ext_target_devs)) {
edd16368
SC		 3038 ncurrent++;
3039 this_device = currentsd[ncurrent];
3040 }
3041
3042 *this_device = *tmpdevice;
edd16368
SC		 3043
3044 switch (this_device->devtype) {
0b0e1d6c 3045 case TYPE_ROM:
edd16368
SC		 3046 /* We don't *really* support actual CD-ROM devices,
3047 * just "One Button Disaster Recovery" tape drive
3048 * which temporarily pretends to be a CD-ROM drive.
3049 * So we check that the device is really an OBDR tape
3050 * device by checking for "$DR-10" in bytes 43-48 of
3051 * the inquiry data.
3052 */
0b0e1d6c
SC		 3053 if (is_OBDR)
3054 ncurrent++;
edd16368
SC		 3055 break;
3056 case TYPE_DISK:
316b221a
SC		 3057 if (h->hba_mode_enabled) {
3058 /* never use raid mapper in HBA mode */
3059 this_device->offload_enabled = 0;
3060 ncurrent++;
3061 break;
3062 } else if (h->acciopath_status) {
3063 if (i >= nphysicals) {
3064 ncurrent++;
3065 break;
3066 }
3067 } else {
3068 if (i < nphysicals)
3069 break;
283b4a9b 3070 ncurrent++;
edd16368 3071 break;
283b4a9b
SC		 3072 }
3073 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3074 memcpy(&this_device->ioaccel_handle,
3075 &lunaddrbytes[20],
3076 sizeof(this_device->ioaccel_handle));
3077 ncurrent++;
3078 }
edd16368
SC		 3079 break;
3080 case TYPE_TAPE:
3081 case TYPE_MEDIUM_CHANGER:
3082 ncurrent++;
3083 break;
3084 case TYPE_RAID:
3085 /* Only present the Smartarray HBA as a RAID controller.
3086 * If it's a RAID controller other than the HBA itself
3087 * (an external RAID controller, MSA500 or similar)
3088 * don't present it.
3089 */
3090 if (!is_hba_lunid(lunaddrbytes))
3091 break;
3092 ncurrent++;
3093 break;
3094 default:
3095 break;
3096 }
cfe5badc 3097 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3098 break;
3099 }
3100 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3101out:
3102 kfree(tmpdevice);
3103 for (i = 0; i < ndev_allocated; i++)
3104 kfree(currentsd[i]);
3105 kfree(currentsd);
edd16368
SC		 3106 kfree(physdev_list);
3107 kfree(logdev_list);
edd16368
SC		 3108}
3109
3110/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3111 * dma mapping and fills in the scatter gather entries of the
3112 * hpsa command, cp.
3113 */
33a2ffce 3114static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3115 struct CommandList *cp,
3116 struct scsi_cmnd *cmd)
3117{
3118 unsigned int len;
3119 struct scatterlist *sg;
01a02ffc 3120 u64 addr64;
33a2ffce
SC		 3121 int use_sg, i, sg_index, chained;
3122 struct SGDescriptor *curr_sg;
edd16368 3123
33a2ffce 3124 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3125
3126 use_sg = scsi_dma_map(cmd);
3127 if (use_sg < 0)
3128 return use_sg;
3129
3130 if (!use_sg)
3131 goto sglist_finished;
3132
33a2ffce
SC		 3133 curr_sg = cp->SG;
3134 chained = 0;
3135 sg_index = 0;
edd16368 3136 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3137 if (i == h->max_cmd_sg_entries - 1 &&
3138 use_sg > h->max_cmd_sg_entries) {
3139 chained = 1;
3140 curr_sg = h->cmd_sg_list[cp->cmdindex];
3141 sg_index = 0;
3142 }
01a02ffc 3143 addr64 = (u64) sg_dma_address(sg);
edd16368 3144 len = sg_dma_len(sg);
50a0decf
SC		 3145 curr_sg->Addr = cpu_to_le64(addr64);
3146 curr_sg->Len = cpu_to_le32(len);
3147 curr_sg->Ext = cpu_to_le32(0);
33a2ffce
SC		 3148 curr_sg++;
3149 }
50a0decf 3150 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3151
3152 if (use_sg + chained > h->maxSG)
3153 h->maxSG = use_sg + chained;
3154
3155 if (chained) {
3156 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3157 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3158 if (hpsa_map_sg_chain_block(h, cp)) {
3159 scsi_dma_unmap(cmd);
3160 return -1;
3161 }
33a2ffce 3162 return 0;
edd16368
SC		 3163 }
3164
3165sglist_finished:
3166
01a02ffc 3167 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
50a0decf 3168 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in this cmd list */
edd16368
SC		 3169 return 0;
3170}
3171
283b4a9b
SC		 3172#define IO_ACCEL_INELIGIBLE (1)
3173static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3174{
3175 int is_write = 0;
3176 u32 block;
3177 u32 block_cnt;
3178
3179 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3180 switch (cdb[0]) {
3181 case WRITE_6:
3182 case WRITE_12:
3183 is_write = 1;
3184 case READ_6:
3185 case READ_12:
3186 if (*cdb_len == 6) {
3187 block = (((u32) cdb[2]) << 8) | cdb[3];
3188 block_cnt = cdb[4];
3189 } else {
3190 BUG_ON(*cdb_len != 12);
3191 block = (((u32) cdb[2]) << 24) |
3192 (((u32) cdb[3]) << 16) |
3193 (((u32) cdb[4]) << 8) |
3194 cdb[5];
3195 block_cnt =
3196 (((u32) cdb[6]) << 24) |
3197 (((u32) cdb[7]) << 16) |
3198 (((u32) cdb[8]) << 8) |
3199 cdb[9];
3200 }
3201 if (block_cnt > 0xffff)
3202 return IO_ACCEL_INELIGIBLE;
3203
3204 cdb[0] = is_write ? WRITE_10 : READ_10;
3205 cdb[1] = 0;
3206 cdb[2] = (u8) (block >> 24);
3207 cdb[3] = (u8) (block >> 16);
3208 cdb[4] = (u8) (block >> 8);
3209 cdb[5] = (u8) (block);
3210 cdb[6] = 0;
3211 cdb[7] = (u8) (block_cnt >> 8);
3212 cdb[8] = (u8) (block_cnt);
3213 cdb[9] = 0;
3214 *cdb_len = 10;
3215 break;
3216 }
3217 return 0;
3218}
3219
c349775e 3220static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3221 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3222 u8 *scsi3addr)
e1f7de0c
MG		 3223{
3224 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3225 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3226 unsigned int len;
3227 unsigned int total_len = 0;
3228 struct scatterlist *sg;
3229 u64 addr64;
3230 int use_sg, i;
3231 struct SGDescriptor *curr_sg;
3232 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3233
283b4a9b
SC		 3234 /* TODO: implement chaining support */
3235 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3236 return IO_ACCEL_INELIGIBLE;
3237
e1f7de0c
MG		 3238 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3239
283b4a9b
SC		 3240 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3241 return IO_ACCEL_INELIGIBLE;
3242
e1f7de0c
MG		 3243 c->cmd_type = CMD_IOACCEL1;
3244
3245 /* Adjust the DMA address to point to the accelerated command buffer */
3246 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3247 (c->cmdindex * sizeof(*cp));
3248 BUG_ON(c->busaddr & 0x0000007F);
3249
3250 use_sg = scsi_dma_map(cmd);
3251 if (use_sg < 0)
3252 return use_sg;
3253
3254 if (use_sg) {
3255 curr_sg = cp->SG;
3256 scsi_for_each_sg(cmd, sg, use_sg, i) {
3257 addr64 = (u64) sg_dma_address(sg);
3258 len = sg_dma_len(sg);
3259 total_len += len;
50a0decf
SC		 3260 curr_sg->Addr = cpu_to_le64(addr64);
3261 curr_sg->Len = cpu_to_le32(len);
3262 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3263 curr_sg++;
3264 }
50a0decf 3265 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3266
3267 switch (cmd->sc_data_direction) {
3268 case DMA_TO_DEVICE:
3269 control |= IOACCEL1_CONTROL_DATA_OUT;
3270 break;
3271 case DMA_FROM_DEVICE:
3272 control |= IOACCEL1_CONTROL_DATA_IN;
3273 break;
3274 case DMA_NONE:
3275 control |= IOACCEL1_CONTROL_NODATAXFER;
3276 break;
3277 default:
3278 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3279 cmd->sc_data_direction);
3280 BUG();
3281 break;
3282 }
3283 } else {
3284 control |= IOACCEL1_CONTROL_NODATAXFER;
3285 }
3286
c349775e 3287 c->Header.SGList = use_sg;
e1f7de0c 3288 /* Fill out the command structure to submit */
283b4a9b 3289 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3290 cp->transfer_len = total_len;
3291 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3292 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3293 cp->control = control;
283b4a9b
SC		 3294 memcpy(cp->CDB, cdb, cdb_len);
3295 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3296 /* Tag was already set at init time. */
283b4a9b 3297 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3298 return 0;
3299}
edd16368 3300
283b4a9b
SC		 3301/*
3302 * Queue a command directly to a device behind the controller using the
3303 * I/O accelerator path.
3304 */
3305static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3306 struct CommandList *c)
3307{
3308 struct scsi_cmnd *cmd = c->scsi_cmd;
3309 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3310
3311 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3312 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3313}
3314
dd0e19f3
ST		 3315/*
3316 * Set encryption parameters for the ioaccel2 request
3317 */
3318static void set_encrypt_ioaccel2(struct ctlr_info *h,
3319 struct CommandList *c, struct io_accel2_cmd *cp)
3320{
3321 struct scsi_cmnd *cmd = c->scsi_cmd;
3322 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3323 struct raid_map_data *map = &dev->raid_map;
3324 u64 first_block;
3325
3326 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3327
3328 /* Are we doing encryption on this device */
3329 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3330 return;
3331 /* Set the data encryption key index. */
3332 cp->dekindex = map->dekindex;
3333
3334 /* Set the encryption enable flag, encoded into direction field. */
3335 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3336
3337 /* Set encryption tweak values based on logical block address
3338 * If block size is 512, tweak value is LBA.
3339 * For other block sizes, tweak is (LBA * block size)/ 512)
3340 */
3341 switch (cmd->cmnd[0]) {
3342 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3343 case WRITE_6:
3344 case READ_6:
3345 if (map->volume_blk_size == 512) {
3346 cp->tweak_lower =
3347 (((u32) cmd->cmnd[2]) << 8) |
3348 cmd->cmnd[3];
3349 cp->tweak_upper = 0;
3350 } else {
3351 first_block =
3352 (((u64) cmd->cmnd[2]) << 8) |
3353 cmd->cmnd[3];
3354 first_block = (first_block * map->volume_blk_size)/512;
3355 cp->tweak_lower = (u32)first_block;
3356 cp->tweak_upper = (u32)(first_block >> 32);
3357 }
3358 break;
3359 case WRITE_10:
3360 case READ_10:
3361 if (map->volume_blk_size == 512) {
3362 cp->tweak_lower =
3363 (((u32) cmd->cmnd[2]) << 24) |
3364 (((u32) cmd->cmnd[3]) << 16) |
3365 (((u32) cmd->cmnd[4]) << 8) |
3366 cmd->cmnd[5];
3367 cp->tweak_upper = 0;
3368 } else {
3369 first_block =
3370 (((u64) cmd->cmnd[2]) << 24) |
3371 (((u64) cmd->cmnd[3]) << 16) |
3372 (((u64) cmd->cmnd[4]) << 8) |
3373 cmd->cmnd[5];
3374 first_block = (first_block * map->volume_blk_size)/512;
3375 cp->tweak_lower = (u32)first_block;
3376 cp->tweak_upper = (u32)(first_block >> 32);
3377 }
3378 break;
3379 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3380 case WRITE_12:
3381 case READ_12:
3382 if (map->volume_blk_size == 512) {
3383 cp->tweak_lower =
3384 (((u32) cmd->cmnd[2]) << 24) |
3385 (((u32) cmd->cmnd[3]) << 16) |
3386 (((u32) cmd->cmnd[4]) << 8) |
3387 cmd->cmnd[5];
3388 cp->tweak_upper = 0;
3389 } else {
3390 first_block =
3391 (((u64) cmd->cmnd[2]) << 24) |
3392 (((u64) cmd->cmnd[3]) << 16) |
3393 (((u64) cmd->cmnd[4]) << 8) |
3394 cmd->cmnd[5];
3395 first_block = (first_block * map->volume_blk_size)/512;
3396 cp->tweak_lower = (u32)first_block;
3397 cp->tweak_upper = (u32)(first_block >> 32);
3398 }
3399 break;
3400 case WRITE_16:
3401 case READ_16:
3402 if (map->volume_blk_size == 512) {
3403 cp->tweak_lower =
3404 (((u32) cmd->cmnd[6]) << 24) |
3405 (((u32) cmd->cmnd[7]) << 16) |
3406 (((u32) cmd->cmnd[8]) << 8) |
3407 cmd->cmnd[9];
3408 cp->tweak_upper =
3409 (((u32) cmd->cmnd[2]) << 24) |
3410 (((u32) cmd->cmnd[3]) << 16) |
3411 (((u32) cmd->cmnd[4]) << 8) |
3412 cmd->cmnd[5];
3413 } else {
3414 first_block =
3415 (((u64) cmd->cmnd[2]) << 56) |
3416 (((u64) cmd->cmnd[3]) << 48) |
3417 (((u64) cmd->cmnd[4]) << 40) |
3418 (((u64) cmd->cmnd[5]) << 32) |
3419 (((u64) cmd->cmnd[6]) << 24) |
3420 (((u64) cmd->cmnd[7]) << 16) |
3421 (((u64) cmd->cmnd[8]) << 8) |
3422 cmd->cmnd[9];
3423 first_block = (first_block * map->volume_blk_size)/512;
3424 cp->tweak_lower = (u32)first_block;
3425 cp->tweak_upper = (u32)(first_block >> 32);
3426 }
3427 break;
3428 default:
3429 dev_err(&h->pdev->dev,
3430 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3431 __func__);
3432 BUG();
3433 break;
3434 }
3435}
3436
c349775e
ST		 3437static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3438 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3439 u8 *scsi3addr)
3440{
3441 struct scsi_cmnd *cmd = c->scsi_cmd;
3442 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3443 struct ioaccel2_sg_element *curr_sg;
3444 int use_sg, i;
3445 struct scatterlist *sg;
3446 u64 addr64;
3447 u32 len;
3448 u32 total_len = 0;
3449
3450 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3451 return IO_ACCEL_INELIGIBLE;
3452
3453 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3454 return IO_ACCEL_INELIGIBLE;
3455 c->cmd_type = CMD_IOACCEL2;
3456 /* Adjust the DMA address to point to the accelerated command buffer */
3457 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3458 (c->cmdindex * sizeof(*cp));
3459 BUG_ON(c->busaddr & 0x0000007F);
3460
3461 memset(cp, 0, sizeof(*cp));
3462 cp->IU_type = IOACCEL2_IU_TYPE;
3463
3464 use_sg = scsi_dma_map(cmd);
3465 if (use_sg < 0)
3466 return use_sg;
3467
3468 if (use_sg) {
3469 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3470 curr_sg = cp->sg;
3471 scsi_for_each_sg(cmd, sg, use_sg, i) {
3472 addr64 = (u64) sg_dma_address(sg);
3473 len = sg_dma_len(sg);
3474 total_len += len;
3475 curr_sg->address = cpu_to_le64(addr64);
3476 curr_sg->length = cpu_to_le32(len);
3477 curr_sg->reserved[0] = 0;
3478 curr_sg->reserved[1] = 0;
3479 curr_sg->reserved[2] = 0;
3480 curr_sg->chain_indicator = 0;
3481 curr_sg++;
3482 }
3483
3484 switch (cmd->sc_data_direction) {
3485 case DMA_TO_DEVICE:
dd0e19f3
ST		 3486 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3487 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3488 break;
3489 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3490 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3491 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3492 break;
3493 case DMA_NONE:
dd0e19f3
ST		 3494 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3495 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3496 break;
3497 default:
3498 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3499 cmd->sc_data_direction);
3500 BUG();
3501 break;
3502 }
3503 } else {
dd0e19f3
ST		 3504 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3505 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3506 }
dd0e19f3
ST		 3507
3508 /* Set encryption parameters, if necessary */
3509 set_encrypt_ioaccel2(h, c, cp);
3510
c349775e 3511 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3512 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3513 DIRECT_LOOKUP_BIT;
3514 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e
ST		 3515
3516 /* fill in sg elements */
3517 cp->sg_count = (u8) use_sg;
3518
3519 cp->data_len = cpu_to_le32(total_len);
3520 cp->err_ptr = cpu_to_le64(c->busaddr +
3521 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3522 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e
ST		 3523
3524 enqueue_cmd_and_start_io(h, c);
3525 return 0;
3526}
3527
3528/*
3529 * Queue a command to the correct I/O accelerator path.
3530 */
3531static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3532 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3533 u8 *scsi3addr)
3534{
3535 if (h->transMethod & CFGTBL_Trans_io_accel1)
3536 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3537 cdb, cdb_len, scsi3addr);
3538 else
3539 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3540 cdb, cdb_len, scsi3addr);
3541}
3542
6b80b18f
ST		 3543static void raid_map_helper(struct raid_map_data *map,
3544 int offload_to_mirror, u32 *map_index, u32 *current_group)
3545{
3546 if (offload_to_mirror == 0) {
3547 /* use physical disk in the first mirrored group. */
3548 *map_index %= map->data_disks_per_row;
3549 return;
3550 }
3551 do {
3552 /* determine mirror group that *map_index indicates */
3553 *current_group = *map_index / map->data_disks_per_row;
3554 if (offload_to_mirror == *current_group)
3555 continue;
3556 if (*current_group < (map->layout_map_count - 1)) {
3557 /* select map index from next group */
3558 *map_index += map->data_disks_per_row;
3559 (*current_group)++;
3560 } else {
3561 /* select map index from first group */
3562 *map_index %= map->data_disks_per_row;
3563 *current_group = 0;
3564 }
3565 } while (offload_to_mirror != *current_group);
3566}
3567
283b4a9b
SC		 3568/*
3569 * Attempt to perform offload RAID mapping for a logical volume I/O.
3570 */
3571static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3572 struct CommandList *c)
3573{
3574 struct scsi_cmnd *cmd = c->scsi_cmd;
3575 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3576 struct raid_map_data *map = &dev->raid_map;
3577 struct raid_map_disk_data *dd = &map->data[0];
3578 int is_write = 0;
3579 u32 map_index;
3580 u64 first_block, last_block;
3581 u32 block_cnt;
3582 u32 blocks_per_row;
3583 u64 first_row, last_row;
3584 u32 first_row_offset, last_row_offset;
3585 u32 first_column, last_column;
6b80b18f
ST		 3586 u64 r0_first_row, r0_last_row;
3587 u32 r5or6_blocks_per_row;
3588 u64 r5or6_first_row, r5or6_last_row;
3589 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3590 u32 r5or6_first_column, r5or6_last_column;
3591 u32 total_disks_per_row;
3592 u32 stripesize;
3593 u32 first_group, last_group, current_group;
283b4a9b
SC		 3594 u32 map_row;
3595 u32 disk_handle;
3596 u64 disk_block;
3597 u32 disk_block_cnt;
3598 u8 cdb[16];
3599 u8 cdb_len;
3600#if BITS_PER_LONG == 32
3601 u64 tmpdiv;
3602#endif
6b80b18f 3603 int offload_to_mirror;
283b4a9b
SC		 3604
3605 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3606
3607 /* check for valid opcode, get LBA and block count */
3608 switch (cmd->cmnd[0]) {
3609 case WRITE_6:
3610 is_write = 1;
3611 case READ_6:
3612 first_block =
3613 (((u64) cmd->cmnd[2]) << 8) |
3614 cmd->cmnd[3];
3615 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 3616 if (block_cnt == 0)
3617 block_cnt = 256;
283b4a9b
SC		 3618 break;
3619 case WRITE_10:
3620 is_write = 1;
3621 case READ_10:
3622 first_block =
3623 (((u64) cmd->cmnd[2]) << 24) |
3624 (((u64) cmd->cmnd[3]) << 16) |
3625 (((u64) cmd->cmnd[4]) << 8) |
3626 cmd->cmnd[5];
3627 block_cnt =
3628 (((u32) cmd->cmnd[7]) << 8) |
3629 cmd->cmnd[8];
3630 break;
3631 case WRITE_12:
3632 is_write = 1;
3633 case READ_12:
3634 first_block =
3635 (((u64) cmd->cmnd[2]) << 24) |
3636 (((u64) cmd->cmnd[3]) << 16) |
3637 (((u64) cmd->cmnd[4]) << 8) |
3638 cmd->cmnd[5];
3639 block_cnt =
3640 (((u32) cmd->cmnd[6]) << 24) |
3641 (((u32) cmd->cmnd[7]) << 16) |
3642 (((u32) cmd->cmnd[8]) << 8) |
3643 cmd->cmnd[9];
3644 break;
3645 case WRITE_16:
3646 is_write = 1;
3647 case READ_16:
3648 first_block =
3649 (((u64) cmd->cmnd[2]) << 56) |
3650 (((u64) cmd->cmnd[3]) << 48) |
3651 (((u64) cmd->cmnd[4]) << 40) |
3652 (((u64) cmd->cmnd[5]) << 32) |
3653 (((u64) cmd->cmnd[6]) << 24) |
3654 (((u64) cmd->cmnd[7]) << 16) |
3655 (((u64) cmd->cmnd[8]) << 8) |
3656 cmd->cmnd[9];
3657 block_cnt =
3658 (((u32) cmd->cmnd[10]) << 24) |
3659 (((u32) cmd->cmnd[11]) << 16) |
3660 (((u32) cmd->cmnd[12]) << 8) |
3661 cmd->cmnd[13];
3662 break;
3663 default:
3664 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3665 }
283b4a9b
SC		 3666 last_block = first_block + block_cnt - 1;
3667
3668 /* check for write to non-RAID-0 */
3669 if (is_write && dev->raid_level != 0)
3670 return IO_ACCEL_INELIGIBLE;
3671
3672 /* check for invalid block or wraparound */
3673 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3674 return IO_ACCEL_INELIGIBLE;
3675
3676 /* calculate stripe information for the request */
3677 blocks_per_row = map->data_disks_per_row * map->strip_size;
3678#if BITS_PER_LONG == 32
3679 tmpdiv = first_block;
3680 (void) do_div(tmpdiv, blocks_per_row);
3681 first_row = tmpdiv;
3682 tmpdiv = last_block;
3683 (void) do_div(tmpdiv, blocks_per_row);
3684 last_row = tmpdiv;
3685 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3686 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3687 tmpdiv = first_row_offset;
3688 (void) do_div(tmpdiv, map->strip_size);
3689 first_column = tmpdiv;
3690 tmpdiv = last_row_offset;
3691 (void) do_div(tmpdiv, map->strip_size);
3692 last_column = tmpdiv;
3693#else
3694 first_row = first_block / blocks_per_row;
3695 last_row = last_block / blocks_per_row;
3696 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3697 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3698 first_column = first_row_offset / map->strip_size;
3699 last_column = last_row_offset / map->strip_size;
3700#endif
3701
3702 /* if this isn't a single row/column then give to the controller */
3703 if ((first_row != last_row) || (first_column != last_column))
3704 return IO_ACCEL_INELIGIBLE;
3705
3706 /* proceeding with driver mapping */
6b80b18f
ST		 3707 total_disks_per_row = map->data_disks_per_row +
3708 map->metadata_disks_per_row;
283b4a9b
SC		 3709 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3710 map->row_cnt;
6b80b18f
ST		 3711 map_index = (map_row * total_disks_per_row) + first_column;
3712
3713 switch (dev->raid_level) {
3714 case HPSA_RAID_0:
3715 break; /* nothing special to do */
3716 case HPSA_RAID_1:
3717 /* Handles load balance across RAID 1 members.
3718 * (2-drive R1 and R10 with even # of drives.)
3719 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3720 */
6b80b18f 3721 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3722 if (dev->offload_to_mirror)
3723 map_index += map->data_disks_per_row;
3724 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3725 break;
3726 case HPSA_RAID_ADM:
3727 /* Handles N-way mirrors (R1-ADM)
3728 * and R10 with # of drives divisible by 3.)
3729 */
3730 BUG_ON(map->layout_map_count != 3);
3731
3732 offload_to_mirror = dev->offload_to_mirror;
3733 raid_map_helper(map, offload_to_mirror,
3734 &map_index, &current_group);
3735 /* set mirror group to use next time */
3736 offload_to_mirror =
3737 (offload_to_mirror >= map->layout_map_count - 1)
3738 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 3739 dev->offload_to_mirror = offload_to_mirror;
3740 /* Avoid direct use of dev->offload_to_mirror within this
3741 * function since multiple threads might simultaneously
3742 * increment it beyond the range of dev->layout_map_count -1.
3743 */
3744 break;
3745 case HPSA_RAID_5:
3746 case HPSA_RAID_6:
3747 if (map->layout_map_count <= 1)
3748 break;
3749
3750 /* Verify first and last block are in same RAID group */
3751 r5or6_blocks_per_row =
3752 map->strip_size * map->data_disks_per_row;
3753 BUG_ON(r5or6_blocks_per_row == 0);
3754 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3755#if BITS_PER_LONG == 32
3756 tmpdiv = first_block;
3757 first_group = do_div(tmpdiv, stripesize);
3758 tmpdiv = first_group;
3759 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3760 first_group = tmpdiv;
3761 tmpdiv = last_block;
3762 last_group = do_div(tmpdiv, stripesize);
3763 tmpdiv = last_group;
3764 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3765 last_group = tmpdiv;
3766#else
3767 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3768 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 3769#endif
000ff7c2 3770 if (first_group != last_group)
6b80b18f
ST		 3771 return IO_ACCEL_INELIGIBLE;
3772
3773 /* Verify request is in a single row of RAID 5/6 */
3774#if BITS_PER_LONG == 32
3775 tmpdiv = first_block;
3776 (void) do_div(tmpdiv, stripesize);
3777 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3778 tmpdiv = last_block;
3779 (void) do_div(tmpdiv, stripesize);
3780 r5or6_last_row = r0_last_row = tmpdiv;
3781#else
3782 first_row = r5or6_first_row = r0_first_row =
3783 first_block / stripesize;
3784 r5or6_last_row = r0_last_row = last_block / stripesize;
3785#endif
3786 if (r5or6_first_row != r5or6_last_row)
3787 return IO_ACCEL_INELIGIBLE;
3788
3789
3790 /* Verify request is in a single column */
3791#if BITS_PER_LONG == 32
3792 tmpdiv = first_block;
3793 first_row_offset = do_div(tmpdiv, stripesize);
3794 tmpdiv = first_row_offset;
3795 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3796 r5or6_first_row_offset = first_row_offset;
3797 tmpdiv = last_block;
3798 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3799 tmpdiv = r5or6_last_row_offset;
3800 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3801 tmpdiv = r5or6_first_row_offset;
3802 (void) do_div(tmpdiv, map->strip_size);
3803 first_column = r5or6_first_column = tmpdiv;
3804 tmpdiv = r5or6_last_row_offset;
3805 (void) do_div(tmpdiv, map->strip_size);
3806 r5or6_last_column = tmpdiv;
3807#else
3808 first_row_offset = r5or6_first_row_offset =
3809 (u32)((first_block % stripesize) %
3810 r5or6_blocks_per_row);
3811
3812 r5or6_last_row_offset =
3813 (u32)((last_block % stripesize) %
3814 r5or6_blocks_per_row);
3815
3816 first_column = r5or6_first_column =
3817 r5or6_first_row_offset / map->strip_size;
3818 r5or6_last_column =
3819 r5or6_last_row_offset / map->strip_size;
3820#endif
3821 if (r5or6_first_column != r5or6_last_column)
3822 return IO_ACCEL_INELIGIBLE;
3823
3824 /* Request is eligible */
3825 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3826 map->row_cnt;
3827
3828 map_index = (first_group *
3829 (map->row_cnt * total_disks_per_row)) +
3830 (map_row * total_disks_per_row) + first_column;
3831 break;
3832 default:
3833 return IO_ACCEL_INELIGIBLE;
283b4a9b 3834 }
6b80b18f 3835
283b4a9b
SC		 3836 disk_handle = dd[map_index].ioaccel_handle;
3837 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3838 (first_row_offset - (first_column * map->strip_size));
3839 disk_block_cnt = block_cnt;
3840
3841 /* handle differing logical/physical block sizes */
3842 if (map->phys_blk_shift) {
3843 disk_block <<= map->phys_blk_shift;
3844 disk_block_cnt <<= map->phys_blk_shift;
3845 }
3846 BUG_ON(disk_block_cnt > 0xffff);
3847
3848 /* build the new CDB for the physical disk I/O */
3849 if (disk_block > 0xffffffff) {
3850 cdb[0] = is_write ? WRITE_16 : READ_16;
3851 cdb[1] = 0;
3852 cdb[2] = (u8) (disk_block >> 56);
3853 cdb[3] = (u8) (disk_block >> 48);
3854 cdb[4] = (u8) (disk_block >> 40);
3855 cdb[5] = (u8) (disk_block >> 32);
3856 cdb[6] = (u8) (disk_block >> 24);
3857 cdb[7] = (u8) (disk_block >> 16);
3858 cdb[8] = (u8) (disk_block >> 8);
3859 cdb[9] = (u8) (disk_block);
3860 cdb[10] = (u8) (disk_block_cnt >> 24);
3861 cdb[11] = (u8) (disk_block_cnt >> 16);
3862 cdb[12] = (u8) (disk_block_cnt >> 8);
3863 cdb[13] = (u8) (disk_block_cnt);
3864 cdb[14] = 0;
3865 cdb[15] = 0;
3866 cdb_len = 16;
3867 } else {
3868 cdb[0] = is_write ? WRITE_10 : READ_10;
3869 cdb[1] = 0;
3870 cdb[2] = (u8) (disk_block >> 24);
3871 cdb[3] = (u8) (disk_block >> 16);
3872 cdb[4] = (u8) (disk_block >> 8);
3873 cdb[5] = (u8) (disk_block);
3874 cdb[6] = 0;
3875 cdb[7] = (u8) (disk_block_cnt >> 8);
3876 cdb[8] = (u8) (disk_block_cnt);
3877 cdb[9] = 0;
3878 cdb_len = 10;
3879 }
3880 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3881 dev->scsi3addr);
3882}
3883
763aadbf
NB		 3884/*
3885 * Running in struct Scsi_Host->host_lock less mode using LLD internal
3886 * struct ctlr_info *h->lock w/ spin_lock_irqsave() protection.
3887 */
3888static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
edd16368
SC		 3889{
3890 struct ctlr_info *h;
3891 struct hpsa_scsi_dev_t *dev;
3892 unsigned char scsi3addr[8];
3893 struct CommandList *c;
283b4a9b 3894 int rc = 0;
edd16368
SC		 3895
3896 /* Get the ptr to our adapter structure out of cmd->host. */
3897 h = sdev_to_hba(cmd->device);
3898 dev = cmd->device->hostdata;
3899 if (!dev) {
3900 cmd->result = DID_NO_CONNECT << 16;
763aadbf 3901 cmd->scsi_done(cmd);
edd16368
SC		 3902 return 0;
3903 }
3904 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3905
094963da 3906 if (unlikely(lockup_detected(h))) {
a0c12413 3907 cmd->result = DID_ERROR << 16;
763aadbf 3908 cmd->scsi_done(cmd);
a0c12413
SC		 3909 return 0;
3910 }
e16a33ad 3911 c = cmd_alloc(h);
edd16368
SC		 3912 if (c == NULL) { /* trouble... */
3913 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3914 return SCSI_MLQUEUE_HOST_BUSY;
3915 }
3916
3917 /* Fill in the command list header */
edd16368
SC		 3918 /* save c in case we have to abort it */
3919 cmd->host_scribble = (unsigned char *) c;
3920
3921 c->cmd_type = CMD_SCSI;
3922 c->scsi_cmd = cmd;
e1f7de0c 3923
283b4a9b
SC		 3924 /* Call alternate submit routine for I/O accelerated commands.
3925 * Retries always go down the normal I/O path.
3926 */
3927 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3928 cmd->request->cmd_type == REQ_TYPE_FS &&
3929 h->acciopath_status)) {
283b4a9b
SC		 3930 if (dev->offload_enabled) {
3931 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3932 if (rc == 0)
3933 return 0; /* Sent on ioaccel path */
3934 if (rc < 0) { /* scsi_dma_map failed. */
3935 cmd_free(h, c);
3936 return SCSI_MLQUEUE_HOST_BUSY;
3937 }
3938 } else if (dev->ioaccel_handle) {
3939 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3940 if (rc == 0)
3941 return 0; /* Sent on direct map path */
3942 if (rc < 0) { /* scsi_dma_map failed. */
3943 cmd_free(h, c);
3944 return SCSI_MLQUEUE_HOST_BUSY;
3945 }
3946 }
3947 }
e1f7de0c 3948
edd16368
SC		 3949 c->Header.ReplyQueue = 0; /* unused in simple mode */
3950 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
50a0decf
SC		 3951 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT) |
3952 DIRECT_LOOKUP_BIT);
edd16368
SC		 3953
3954 /* Fill in the request block... */
3955
3956 c->Request.Timeout = 0;
3957 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3958 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3959 c->Request.CDBLen = cmd->cmd_len;
3960 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 3961 switch (cmd->sc_data_direction) {
3962 case DMA_TO_DEVICE:
a505b86f
SC		 3963 c->Request.type_attr_dir =
3964 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 3965 break;
3966 case DMA_FROM_DEVICE:
a505b86f
SC		 3967 c->Request.type_attr_dir =
3968 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 3969 break;
3970 case DMA_NONE:
a505b86f
SC		 3971 c->Request.type_attr_dir =
3972 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 3973 break;
3974 case DMA_BIDIRECTIONAL:
3975 /* This can happen if a buggy application does a scsi passthru
3976 * and sets both inlen and outlen to non-zero. ( see
3977 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3978 */
3979
a505b86f
SC		 3980 c->Request.type_attr_dir =
3981 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 3982 /* This is technically wrong, and hpsa controllers should
3983 * reject it with CMD_INVALID, which is the most correct
3984 * response, but non-fibre backends appear to let it
3985 * slide by, and give the same results as if this field
3986 * were set correctly. Either way is acceptable for
3987 * our purposes here.
3988 */
3989
3990 break;
3991
3992 default:
3993 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3994 cmd->sc_data_direction);
3995 BUG();
3996 break;
3997 }
3998
33a2ffce 3999 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4000 cmd_free(h, c);
4001 return SCSI_MLQUEUE_HOST_BUSY;
4002 }
4003 enqueue_cmd_and_start_io(h, c);
4004 /* the cmd'll come back via intr handler in complete_scsi_command() */
4005 return 0;
4006}
4007
5f389360
SC		 4008static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4009{
4010 unsigned long flags;
4011
4012 /*
4013 * Don't let rescans be initiated on a controller known
4014 * to be locked up. If the controller locks up *during*
4015 * a rescan, that thread is probably hosed, but at least
4016 * we can prevent new rescan threads from piling up on a
4017 * locked up controller.
4018 */
094963da 4019 if (unlikely(lockup_detected(h))) {
5f389360
SC		 4020 spin_lock_irqsave(&h->scan_lock, flags);
4021 h->scan_finished = 1;
4022 wake_up_all(&h->scan_wait_queue);
4023 spin_unlock_irqrestore(&h->scan_lock, flags);
4024 return 1;
4025 }
5f389360
SC		 4026 return 0;
4027}
4028
a08a8471
SC		 4029static void hpsa_scan_start(struct Scsi_Host *sh)
4030{
4031 struct ctlr_info *h = shost_to_hba(sh);
4032 unsigned long flags;
4033
5f389360
SC		 4034 if (do_not_scan_if_controller_locked_up(h))
4035 return;
4036
a08a8471
SC		 4037 /* wait until any scan already in progress is finished. */
4038 while (1) {
4039 spin_lock_irqsave(&h->scan_lock, flags);
4040 if (h->scan_finished)
4041 break;
4042 spin_unlock_irqrestore(&h->scan_lock, flags);
4043 wait_event(h->scan_wait_queue, h->scan_finished);
4044 /* Note: We don't need to worry about a race between this
4045 * thread and driver unload because the midlayer will
4046 * have incremented the reference count, so unload won't
4047 * happen if we're in here.
4048 */
4049 }
4050 h->scan_finished = 0; /* mark scan as in progress */
4051 spin_unlock_irqrestore(&h->scan_lock, flags);
4052
5f389360
SC		 4053 if (do_not_scan_if_controller_locked_up(h))
4054 return;
4055
a08a8471
SC		 4056 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4057
4058 spin_lock_irqsave(&h->scan_lock, flags);
4059 h->scan_finished = 1; /* mark scan as finished. */
4060 wake_up_all(&h->scan_wait_queue);
4061 spin_unlock_irqrestore(&h->scan_lock, flags);
4062}
4063
4064static int hpsa_scan_finished(struct Scsi_Host *sh,
4065 unsigned long elapsed_time)
4066{
4067 struct ctlr_info *h = shost_to_hba(sh);
4068 unsigned long flags;
4069 int finished;
4070
4071 spin_lock_irqsave(&h->scan_lock, flags);
4072 finished = h->scan_finished;
4073 spin_unlock_irqrestore(&h->scan_lock, flags);
4074 return finished;
4075}
4076
667e23d4
SC		 4077static int hpsa_change_queue_depth(struct scsi_device *sdev,
4078 int qdepth, int reason)
4079{
4080 struct ctlr_info *h = sdev_to_hba(sdev);
4081
4082 if (reason != SCSI_QDEPTH_DEFAULT)
4083 return -ENOTSUPP;
4084
4085 if (qdepth < 1)
4086 qdepth = 1;
4087 else
4088 if (qdepth > h->nr_cmds)
4089 qdepth = h->nr_cmds;
c8b09f6f 4090 scsi_adjust_queue_depth(sdev, qdepth);
667e23d4
SC		 4091 return sdev->queue_depth;
4092}
4093
edd16368
SC		 4094static void hpsa_unregister_scsi(struct ctlr_info *h)
4095{
4096 /* we are being forcibly unloaded, and may not refuse. */
4097 scsi_remove_host(h->scsi_host);
4098 scsi_host_put(h->scsi_host);
4099 h->scsi_host = NULL;
4100}
4101
4102static int hpsa_register_scsi(struct ctlr_info *h)
4103{
b705690d
SC		 4104 struct Scsi_Host *sh;
4105 int error;
edd16368 4106
b705690d
SC		 4107 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4108 if (sh == NULL)
4109 goto fail;
4110
4111 sh->io_port = 0;
4112 sh->n_io_port = 0;
4113 sh->this_id = -1;
4114 sh->max_channel = 3;
4115 sh->max_cmd_len = MAX_COMMAND_SIZE;
4116 sh->max_lun = HPSA_MAX_LUN;
4117 sh->max_id = HPSA_MAX_LUN;
4118 sh->can_queue = h->nr_cmds;
316b221a
SC		 4119 if (h->hba_mode_enabled)
4120 sh->cmd_per_lun = 7;
4121 else
4122 sh->cmd_per_lun = h->nr_cmds;
b705690d
SC		 4123 sh->sg_tablesize = h->maxsgentries;
4124 h->scsi_host = sh;
4125 sh->hostdata[0] = (unsigned long) h;
4126 sh->irq = h->intr[h->intr_mode];
4127 sh->unique_id = sh->irq;
4128 error = scsi_add_host(sh, &h->pdev->dev);
4129 if (error)
4130 goto fail_host_put;
4131 scsi_scan_host(sh);
4132 return 0;
4133
4134 fail_host_put:
4135 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4136 " failed for controller %d\n", __func__, h->ctlr);
4137 scsi_host_put(sh);
4138 return error;
4139 fail:
4140 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4141 " failed for controller %d\n", __func__, h->ctlr);
4142 return -ENOMEM;
edd16368
SC		 4143}
4144
4145static int wait_for_device_to_become_ready(struct ctlr_info *h,
4146 unsigned char lunaddr[])
4147{
8919358e 4148 int rc;
edd16368
SC		 4149 int count = 0;
4150 int waittime = 1; /* seconds */
4151 struct CommandList *c;
4152
4153 c = cmd_special_alloc(h);
4154 if (!c) {
4155 dev_warn(&h->pdev->dev, "out of memory in "
4156 "wait_for_device_to_become_ready.\n");
4157 return IO_ERROR;
4158 }
4159
4160 /* Send test unit ready until device ready, or give up. */
4161 while (count < HPSA_TUR_RETRY_LIMIT) {
4162
4163 /* Wait for a bit. do this first, because if we send
4164 * the TUR right away, the reset will just abort it.
4165 */
4166 msleep(1000 * waittime);
4167 count++;
8919358e 4168 rc = 0; /* Device ready. */
edd16368
SC		 4169
4170 /* Increase wait time with each try, up to a point. */
4171 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4172 waittime = waittime * 2;
4173
a2dac136
SC		 4174 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4175 (void) fill_cmd(c, TEST_UNIT_READY, h,
4176 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4177 hpsa_scsi_do_simple_cmd_core(h, c);
4178 /* no unmap needed here because no data xfer. */
4179
4180 if (c->err_info->CommandStatus == CMD_SUCCESS)
4181 break;
4182
4183 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4184 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4185 (c->err_info->SenseInfo[2] == NO_SENSE ||
4186 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4187 break;
4188
4189 dev_warn(&h->pdev->dev, "waiting %d secs "
4190 "for device to become ready.\n", waittime);
4191 rc = 1; /* device not ready. */
4192 }
4193
4194 if (rc)
4195 dev_warn(&h->pdev->dev, "giving up on device.\n");
4196 else
4197 dev_warn(&h->pdev->dev, "device is ready.\n");
4198
4199 cmd_special_free(h, c);
4200 return rc;
4201}
4202
4203/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4204 * complaining. Doing a host- or bus-reset can't do anything good here.
4205 */
4206static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4207{
4208 int rc;
4209 struct ctlr_info *h;
4210 struct hpsa_scsi_dev_t *dev;
4211
4212 /* find the controller to which the command to be aborted was sent */
4213 h = sdev_to_hba(scsicmd->device);
4214 if (h == NULL) /* paranoia */
4215 return FAILED;
edd16368
SC		 4216 dev = scsicmd->device->hostdata;
4217 if (!dev) {
4218 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4219 "device lookup failed.\n");
4220 return FAILED;
4221 }
d416b0c7
SC		 4222 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4223 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4224 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4225 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4226 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4227 return SUCCESS;
4228
4229 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4230 return FAILED;
4231}
4232
6cba3f19
SC		 4233static void swizzle_abort_tag(u8 *tag)
4234{
4235 u8 original_tag[8];
4236
4237 memcpy(original_tag, tag, 8);
4238 tag[0] = original_tag[3];
4239 tag[1] = original_tag[2];
4240 tag[2] = original_tag[1];
4241 tag[3] = original_tag[0];
4242 tag[4] = original_tag[7];
4243 tag[5] = original_tag[6];
4244 tag[6] = original_tag[5];
4245 tag[7] = original_tag[4];
4246}
4247
17eb87d2
ST		 4248static void hpsa_get_tag(struct ctlr_info *h,
4249 struct CommandList *c, u32 *taglower, u32 *tagupper)
4250{
4251 if (c->cmd_type == CMD_IOACCEL1) {
4252 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4253 &h->ioaccel_cmd_pool[c->cmdindex];
50a0decf
SC		 4254 *tagupper = (u32) (cm1->tag >> 32);
4255 *taglower = (u32) (cm1->tag & 0x0ffffffffULL);
54b6e9e9
ST		 4256 return;
4257 }
4258 if (c->cmd_type == CMD_IOACCEL2) {
4259 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4260 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4261 /* upper tag not used in ioaccel2 mode */
4262 memset(tagupper, 0, sizeof(*tagupper));
4263 *taglower = cm2->Tag;
54b6e9e9 4264 return;
17eb87d2 4265 }
50a0decf
SC		 4266 *tagupper = (u32) (c->Header.tag >> 32);
4267 *taglower = (u32) (c->Header.tag & 0x0ffffffffULL);
17eb87d2
ST		 4268}
4269
75167d2c 4270static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4271 struct CommandList *abort, int swizzle)
75167d2c
SC		 4272{
4273 int rc = IO_OK;
4274 struct CommandList *c;
4275 struct ErrorInfo *ei;
17eb87d2 4276 u32 tagupper, taglower;
75167d2c
SC		 4277
4278 c = cmd_special_alloc(h);
4279 if (c == NULL) { /* trouble... */
4280 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4281 return -ENOMEM;
4282 }
4283
a2dac136
SC		 4284 /* fill_cmd can't fail here, no buffer to map */
4285 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4286 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4287 if (swizzle)
4288 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4289 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4290 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4291 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4292 __func__, tagupper, taglower);
75167d2c
SC		 4293 /* no unmap needed here because no data xfer. */
4294
4295 ei = c->err_info;
4296 switch (ei->CommandStatus) {
4297 case CMD_SUCCESS:
4298 break;
4299 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4300 rc = -1;
4301 break;
4302 default:
4303 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4304 __func__, tagupper, taglower);
d1e8beac 4305 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4306 rc = -1;
4307 break;
4308 }
4309 cmd_special_free(h, c);
dd0e19f3
ST		 4310 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4311 __func__, tagupper, taglower);
75167d2c
SC		 4312 return rc;
4313}
4314
4315/*
4316 * hpsa_find_cmd_in_queue
4317 *
4318 * Used to determine whether a command (find) is still present
4319 * in queue_head. Optionally excludes the last element of queue_head.
4320 *
4321 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4322 * not yet been submitted, and so can be aborted by the driver without
4323 * sending an abort to the hardware.
4324 *
4325 * Returns pointer to command if found in queue, NULL otherwise.
4326 */
4327static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4328 struct scsi_cmnd *find, struct list_head *queue_head)
4329{
4330 unsigned long flags;
4331 struct CommandList *c = NULL; /* ptr into cmpQ */
4332
4333 if (!find)
42a91641 4334 return NULL;
75167d2c
SC		 4335 spin_lock_irqsave(&h->lock, flags);
4336 list_for_each_entry(c, queue_head, list) {
4337 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4338 continue;
4339 if (c->scsi_cmd == find) {
4340 spin_unlock_irqrestore(&h->lock, flags);
4341 return c;
4342 }
4343 }
4344 spin_unlock_irqrestore(&h->lock, flags);
4345 return NULL;
4346}
4347
6cba3f19
SC		 4348static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4349 u8 *tag, struct list_head *queue_head)
4350{
4351 unsigned long flags;
4352 struct CommandList *c;
4353
4354 spin_lock_irqsave(&h->lock, flags);
4355 list_for_each_entry(c, queue_head, list) {
50a0decf 4356 if (memcmp(&c->Header.tag, tag, 8) != 0)
6cba3f19
SC		 4357 continue;
4358 spin_unlock_irqrestore(&h->lock, flags);
4359 return c;
4360 }
4361 spin_unlock_irqrestore(&h->lock, flags);
4362 return NULL;
4363}
4364
54b6e9e9
ST		 4365/* ioaccel2 path firmware cannot handle abort task requests.
4366 * Change abort requests to physical target reset, and send to the
4367 * address of the physical disk used for the ioaccel 2 command.
4368 * Return 0 on success (IO_OK)
4369 * -1 on failure
4370 */
4371
4372static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4373 unsigned char *scsi3addr, struct CommandList *abort)
4374{
4375 int rc = IO_OK;
4376 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4377 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4378 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4379 unsigned char *psa = &phys_scsi3addr[0];
4380
4381 /* Get a pointer to the hpsa logical device. */
4382 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4383 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4384 if (dev == NULL) {
4385 dev_warn(&h->pdev->dev,
4386 "Cannot abort: no device pointer for command.\n");
4387 return -1; /* not abortable */
4388 }
4389
2ba8bfc8
SC		 4390 if (h->raid_offload_debug > 0)
4391 dev_info(&h->pdev->dev,
4392 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4393 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4394 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4395 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4396
54b6e9e9
ST		 4397 if (!dev->offload_enabled) {
4398 dev_warn(&h->pdev->dev,
4399 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4400 return -1; /* not abortable */
4401 }
4402
4403 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4404 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4405 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4406 return -1; /* not abortable */
4407 }
4408
4409 /* send the reset */
2ba8bfc8
SC		 4410 if (h->raid_offload_debug > 0)
4411 dev_info(&h->pdev->dev,
4412 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4413 psa[0], psa[1], psa[2], psa[3],
4414 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4415 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4416 if (rc != 0) {
4417 dev_warn(&h->pdev->dev,
4418 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4419 psa[0], psa[1], psa[2], psa[3],
4420 psa[4], psa[5], psa[6], psa[7]);
4421 return rc; /* failed to reset */
4422 }
4423
4424 /* wait for device to recover */
4425 if (wait_for_device_to_become_ready(h, psa) != 0) {
4426 dev_warn(&h->pdev->dev,
4427 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4428 psa[0], psa[1], psa[2], psa[3],
4429 psa[4], psa[5], psa[6], psa[7]);
4430 return -1; /* failed to recover */
4431 }
4432
4433 /* device recovered */
4434 dev_info(&h->pdev->dev,
4435 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4436 psa[0], psa[1], psa[2], psa[3],
4437 psa[4], psa[5], psa[6], psa[7]);
4438
4439 return rc; /* success */
4440}
4441
6cba3f19
SC		 4442/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4443 * tell which kind we're dealing with, so we send the abort both ways. There
4444 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4445 * way we construct our tags but we check anyway in case the assumptions which
4446 * make this true someday become false.
4447 */
4448static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4449 unsigned char *scsi3addr, struct CommandList *abort)
4450{
4451 u8 swizzled_tag[8];
4452 struct CommandList *c;
4453 int rc = 0, rc2 = 0;
4454
54b6e9e9
ST		 4455 /* ioccelerator mode 2 commands should be aborted via the
4456 * accelerated path, since RAID path is unaware of these commands,
4457 * but underlying firmware can't handle abort TMF.
4458 * Change abort to physical device reset.
4459 */
4460 if (abort->cmd_type == CMD_IOACCEL2)
4461 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4462
6cba3f19
SC		 4463 /* we do not expect to find the swizzled tag in our queue, but
4464 * check anyway just to be sure the assumptions which make this
4465 * the case haven't become wrong.
4466 */
4467 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4468 swizzle_abort_tag(swizzled_tag);
4469 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4470 if (c != NULL) {
4471 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4472 return hpsa_send_abort(h, scsi3addr, abort, 0);
4473 }
4474 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4475
4476 /* if the command is still in our queue, we can't conclude that it was
4477 * aborted (it might have just completed normally) but in any case
4478 * we don't need to try to abort it another way.
4479 */
4480 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4481 if (c)
4482 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4483 return rc && rc2;
4484}
4485
75167d2c
SC		 4486/* Send an abort for the specified command.
4487 * If the device and controller support it,
4488 * send a task abort request.
4489 */
4490static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4491{
4492
4493 int i, rc;
4494 struct ctlr_info *h;
4495 struct hpsa_scsi_dev_t *dev;
4496 struct CommandList *abort; /* pointer to command to be aborted */
4497 struct CommandList *found;
4498 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4499 char msg[256]; /* For debug messaging. */
4500 int ml = 0;
17eb87d2 4501 u32 tagupper, taglower;
75167d2c
SC		 4502
4503 /* Find the controller of the command to be aborted */
4504 h = sdev_to_hba(sc->device);
4505 if (WARN(h == NULL,
4506 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4507 return FAILED;
4508
4509 /* Check that controller supports some kind of task abort */
4510 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4511 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4512 return FAILED;
4513
4514 memset(msg, 0, sizeof(msg));
9cb78c16 4515 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ",
75167d2c
SC		 4516 h->scsi_host->host_no, sc->device->channel,
4517 sc->device->id, sc->device->lun);
4518
4519 /* Find the device of the command to be aborted */
4520 dev = sc->device->hostdata;
4521 if (!dev) {
4522 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4523 msg);
4524 return FAILED;
4525 }
4526
4527 /* Get SCSI command to be aborted */
4528 abort = (struct CommandList *) sc->host_scribble;
4529 if (abort == NULL) {
4530 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4531 msg);
4532 return FAILED;
4533 }
17eb87d2
ST		 4534 hpsa_get_tag(h, abort, &taglower, &tagupper);
4535 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4536 as = (struct scsi_cmnd *) abort->scsi_cmd;
4537 if (as != NULL)
4538 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4539 as->cmnd[0], as->serial_number);
4540 dev_dbg(&h->pdev->dev, "%s\n", msg);
4541 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4542 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4543
4544 /* Search reqQ to See if command is queued but not submitted,
4545 * if so, complete the command with aborted status and remove
4546 * it from the reqQ.
4547 */
4548 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4549 if (found) {
4550 found->err_info->CommandStatus = CMD_ABORTED;
4551 finish_cmd(found);
4552 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4553 msg);
4554 return SUCCESS;
4555 }
4556
4557 /* not in reqQ, if also not in cmpQ, must have already completed */
4558 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4559 if (!found) {
d6ebd0f7 4560 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4561 msg);
4562 return SUCCESS;
4563 }
4564
4565 /*
4566 * Command is in flight, or possibly already completed
4567 * by the firmware (but not to the scsi mid layer) but we can't
4568 * distinguish which. Send the abort down.
4569 */
6cba3f19 4570 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4571 if (rc != 0) {
4572 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4573 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4574 h->scsi_host->host_no,
4575 dev->bus, dev->target, dev->lun);
4576 return FAILED;
4577 }
4578 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4579
4580 /* If the abort(s) above completed and actually aborted the
4581 * command, then the command to be aborted should already be
4582 * completed. If not, wait around a bit more to see if they
4583 * manage to complete normally.
4584 */
4585#define ABORT_COMPLETE_WAIT_SECS 30
4586 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4587 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4588 if (!found)
4589 return SUCCESS;
4590 msleep(100);
4591 }
4592 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4593 msg, ABORT_COMPLETE_WAIT_SECS);
4594 return FAILED;
4595}
4596
4597
edd16368
SC		 4598/*
4599 * For operations that cannot sleep, a command block is allocated at init,
4600 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4601 * which ones are free or in use. Lock must be held when calling this.
4602 * cmd_free() is the complement.
4603 */
4604static struct CommandList *cmd_alloc(struct ctlr_info *h)
4605{
4606 struct CommandList *c;
4607 int i;
4608 union u64bit temp64;
4609 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4610 unsigned long flags;
edd16368 4611
e16a33ad 4612 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4613 do {
4614 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4615 if (i == h->nr_cmds) {
4616 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4617 return NULL;
e16a33ad 4618 }
edd16368
SC		 4619 } while (test_and_set_bit
4620 (i & (BITS_PER_LONG - 1),
4621 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4622 spin_unlock_irqrestore(&h->lock, flags);
4623
edd16368
SC		 4624 c = h->cmd_pool + i;
4625 memset(c, 0, sizeof(*c));
4626 cmd_dma_handle = h->cmd_pool_dhandle
4627 + i * sizeof(*c);
4628 c->err_info = h->errinfo_pool + i;
4629 memset(c->err_info, 0, sizeof(*c->err_info));
4630 err_dma_handle = h->errinfo_pool_dhandle
4631 + i * sizeof(*c->err_info);
edd16368
SC		 4632
4633 c->cmdindex = i;
4634
9e0fc764 4635 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4636 c->busaddr = (u32) cmd_dma_handle;
4637 temp64.val = (u64) err_dma_handle;
50a0decf
SC		 4638 c->ErrDesc.Addr = cpu_to_le64(err_dma_handle);
4639 c->ErrDesc.Len = cpu_to_le32(sizeof(*c->err_info));
edd16368
SC		 4640
4641 c->h = h;
4642 return c;
4643}
4644
4645/* For operations that can wait for kmalloc to possibly sleep,
4646 * this routine can be called. Lock need not be held to call
4647 * cmd_special_alloc. cmd_special_free() is the complement.
4648 */
4649static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4650{
4651 struct CommandList *c;
edd16368
SC		 4652 dma_addr_t cmd_dma_handle, err_dma_handle;
4653
7c845eb5 4654 c = pci_zalloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
edd16368
SC		 4655 if (c == NULL)
4656 return NULL;
edd16368 4657
e1f7de0c 4658 c->cmd_type = CMD_SCSI;
edd16368
SC		 4659 c->cmdindex = -1;
4660
7c845eb5
JP		 4661 c->err_info = pci_zalloc_consistent(h->pdev, sizeof(*c->err_info),
4662 &err_dma_handle);
edd16368
SC		 4663
4664 if (c->err_info == NULL) {
4665 pci_free_consistent(h->pdev,
4666 sizeof(*c), c, cmd_dma_handle);
4667 return NULL;
4668 }
edd16368 4669
9e0fc764 4670 INIT_LIST_HEAD(&c->list);
01a02ffc 4671 c->busaddr = (u32) cmd_dma_handle;
50a0decf
SC		 4672 c->ErrDesc.Addr = cpu_to_le64(err_dma_handle);
4673 c->ErrDesc.Len = cpu_to_le32(sizeof(*c->err_info));
edd16368
SC		 4674
4675 c->h = h;
4676 return c;
4677}
4678
4679static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4680{
4681 int i;
e16a33ad 4682 unsigned long flags;
edd16368
SC		 4683
4684 i = c - h->cmd_pool;
e16a33ad 4685 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4686 clear_bit(i & (BITS_PER_LONG - 1),
4687 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4688 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4689}
4690
4691static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4692{
edd16368 4693 pci_free_consistent(h->pdev, sizeof(*c->err_info),
50a0decf
SC		 4694 c->err_info,
4695 (dma_addr_t) le64_to_cpu(c->ErrDesc.Addr));
edd16368 4696 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4697 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4698}
4699
4700#ifdef CONFIG_COMPAT
4701
42a91641
DB		 4702static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
4703 void __user *arg)
edd16368
SC		 4704{
4705 IOCTL32_Command_struct __user *arg32 =
4706 (IOCTL32_Command_struct __user *) arg;
4707 IOCTL_Command_struct arg64;
4708 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4709 int err;
4710 u32 cp;
4711
938abd84 4712 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4713 err = 0;
4714 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4715 sizeof(arg64.LUN_info));
4716 err |= copy_from_user(&arg64.Request, &arg32->Request,
4717 sizeof(arg64.Request));
4718 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4719 sizeof(arg64.error_info));
4720 err |= get_user(arg64.buf_size, &arg32->buf_size);
4721 err |= get_user(cp, &arg32->buf);
4722 arg64.buf = compat_ptr(cp);
4723 err |= copy_to_user(p, &arg64, sizeof(arg64));
4724
4725 if (err)
4726 return -EFAULT;
4727
42a91641 4728 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 4729 if (err)
4730 return err;
4731 err |= copy_in_user(&arg32->error_info, &p->error_info,
4732 sizeof(arg32->error_info));
4733 if (err)
4734 return -EFAULT;
4735 return err;
4736}
4737
4738static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 4739 int cmd, void __user *arg)
edd16368
SC		 4740{
4741 BIG_IOCTL32_Command_struct __user *arg32 =
4742 (BIG_IOCTL32_Command_struct __user *) arg;
4743 BIG_IOCTL_Command_struct arg64;
4744 BIG_IOCTL_Command_struct __user *p =
4745 compat_alloc_user_space(sizeof(arg64));
4746 int err;
4747 u32 cp;
4748
938abd84 4749 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4750 err = 0;
4751 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4752 sizeof(arg64.LUN_info));
4753 err |= copy_from_user(&arg64.Request, &arg32->Request,
4754 sizeof(arg64.Request));
4755 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4756 sizeof(arg64.error_info));
4757 err |= get_user(arg64.buf_size, &arg32->buf_size);
4758 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4759 err |= get_user(cp, &arg32->buf);
4760 arg64.buf = compat_ptr(cp);
4761 err |= copy_to_user(p, &arg64, sizeof(arg64));
4762
4763 if (err)
4764 return -EFAULT;
4765
42a91641 4766 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 4767 if (err)
4768 return err;
4769 err |= copy_in_user(&arg32->error_info, &p->error_info,
4770 sizeof(arg32->error_info));
4771 if (err)
4772 return -EFAULT;
4773 return err;
4774}
71fe75a7 4775
42a91641 4776static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 4777{
4778 switch (cmd) {
4779 case CCISS_GETPCIINFO:
4780 case CCISS_GETINTINFO:
4781 case CCISS_SETINTINFO:
4782 case CCISS_GETNODENAME:
4783 case CCISS_SETNODENAME:
4784 case CCISS_GETHEARTBEAT:
4785 case CCISS_GETBUSTYPES:
4786 case CCISS_GETFIRMVER:
4787 case CCISS_GETDRIVVER:
4788 case CCISS_REVALIDVOLS:
4789 case CCISS_DEREGDISK:
4790 case CCISS_REGNEWDISK:
4791 case CCISS_REGNEWD:
4792 case CCISS_RESCANDISK:
4793 case CCISS_GETLUNINFO:
4794 return hpsa_ioctl(dev, cmd, arg);
4795
4796 case CCISS_PASSTHRU32:
4797 return hpsa_ioctl32_passthru(dev, cmd, arg);
4798 case CCISS_BIG_PASSTHRU32:
4799 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4800
4801 default:
4802 return -ENOIOCTLCMD;
4803 }
4804}
edd16368
SC		 4805#endif
4806
4807static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4808{
4809 struct hpsa_pci_info pciinfo;
4810
4811 if (!argp)
4812 return -EINVAL;
4813 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4814 pciinfo.bus = h->pdev->bus->number;
4815 pciinfo.dev_fn = h->pdev->devfn;
4816 pciinfo.board_id = h->board_id;
4817 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4818 return -EFAULT;
4819 return 0;
4820}
4821
4822static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4823{
4824 DriverVer_type DriverVer;
4825 unsigned char vmaj, vmin, vsubmin;
4826 int rc;
4827
4828 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4829 &vmaj, &vmin, &vsubmin);
4830 if (rc != 3) {
4831 dev_info(&h->pdev->dev, "driver version string '%s' "
4832 "unrecognized.", HPSA_DRIVER_VERSION);
4833 vmaj = 0;
4834 vmin = 0;
4835 vsubmin = 0;
4836 }
4837 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4838 if (!argp)
4839 return -EINVAL;
4840 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4841 return -EFAULT;
4842 return 0;
4843}
4844
4845static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4846{
4847 IOCTL_Command_struct iocommand;
4848 struct CommandList *c;
4849 char *buff = NULL;
50a0decf 4850 u64 temp64;
c1f63c8f 4851 int rc = 0;
edd16368
SC		 4852
4853 if (!argp)
4854 return -EINVAL;
4855 if (!capable(CAP_SYS_RAWIO))
4856 return -EPERM;
4857 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4858 return -EFAULT;
4859 if ((iocommand.buf_size < 1) &&
4860 (iocommand.Request.Type.Direction != XFER_NONE)) {
4861 return -EINVAL;
4862 }
4863 if (iocommand.buf_size > 0) {
4864 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4865 if (buff == NULL)
4866 return -EFAULT;
9233fb10 4867 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 4868 /* Copy the data into the buffer we created */
4869 if (copy_from_user(buff, iocommand.buf,
4870 iocommand.buf_size)) {
c1f63c8f
SC		 4871 rc = -EFAULT;
4872 goto out_kfree;
b03a7771
SC		 4873 }
4874 } else {
4875 memset(buff, 0, iocommand.buf_size);
edd16368 4876 }
b03a7771 4877 }
edd16368
SC		 4878 c = cmd_special_alloc(h);
4879 if (c == NULL) {
c1f63c8f
SC		 4880 rc = -ENOMEM;
4881 goto out_kfree;
edd16368
SC		 4882 }
4883 /* Fill in the command type */
4884 c->cmd_type = CMD_IOCTL_PEND;
4885 /* Fill in Command Header */
4886 c->Header.ReplyQueue = 0; /* unused in simple mode */
4887 if (iocommand.buf_size > 0) { /* buffer to fill */
4888 c->Header.SGList = 1;
50a0decf 4889 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 4890 } else { /* no buffers to fill */
4891 c->Header.SGList = 0;
50a0decf 4892 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 4893 }
4894 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4895 /* use the kernel address the cmd block for tag */
50a0decf 4896 c->Header.tag = c->busaddr;
edd16368
SC		 4897
4898 /* Fill in Request block */
4899 memcpy(&c->Request, &iocommand.Request,
4900 sizeof(c->Request));
4901
4902 /* Fill in the scatter gather information */
4903 if (iocommand.buf_size > 0) {
50a0decf 4904 temp64 = pci_map_single(h->pdev, buff,
edd16368 4905 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 4906 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
4907 c->SG[0].Addr = cpu_to_le64(0);
4908 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 4909 rc = -ENOMEM;
4910 goto out;
4911 }
50a0decf
SC		 4912 c->SG[0].Addr = cpu_to_le64(temp64);
4913 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
4914 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 4915 }
a0c12413 4916 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4917 if (iocommand.buf_size > 0)
4918 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4919 check_ioctl_unit_attention(h, c);
4920
4921 /* Copy the error information out */
4922 memcpy(&iocommand.error_info, c->err_info,
4923 sizeof(iocommand.error_info));
4924 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4925 rc = -EFAULT;
4926 goto out;
edd16368 4927 }
9233fb10 4928 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 4929 iocommand.buf_size > 0) {
edd16368
SC		 4930 /* Copy the data out of the buffer we created */
4931 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4932 rc = -EFAULT;
4933 goto out;
edd16368
SC		 4934 }
4935 }
c1f63c8f 4936out:
edd16368 4937 cmd_special_free(h, c);
c1f63c8f
SC		 4938out_kfree:
4939 kfree(buff);
4940 return rc;
edd16368
SC		 4941}
4942
4943static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4944{
4945 BIG_IOCTL_Command_struct *ioc;
4946 struct CommandList *c;
4947 unsigned char **buff = NULL;
4948 int *buff_size = NULL;
50a0decf 4949 u64 temp64;
edd16368
SC		 4950 BYTE sg_used = 0;
4951 int status = 0;
4952 int i;
01a02ffc
SC		 4953 u32 left;
4954 u32 sz;
edd16368
SC		 4955 BYTE __user *data_ptr;
4956
4957 if (!argp)
4958 return -EINVAL;
4959 if (!capable(CAP_SYS_RAWIO))
4960 return -EPERM;
4961 ioc = (BIG_IOCTL_Command_struct *)
4962 kmalloc(sizeof(*ioc), GFP_KERNEL);
4963 if (!ioc) {
4964 status = -ENOMEM;
4965 goto cleanup1;
4966 }
4967 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4968 status = -EFAULT;
4969 goto cleanup1;
4970 }
4971 if ((ioc->buf_size < 1) &&
4972 (ioc->Request.Type.Direction != XFER_NONE)) {
4973 status = -EINVAL;
4974 goto cleanup1;
4975 }
4976 /* Check kmalloc limits using all SGs */
4977 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4978 status = -EINVAL;
4979 goto cleanup1;
4980 }
d66ae08b 4981 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4982 status = -EINVAL;
4983 goto cleanup1;
4984 }
d66ae08b 4985 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4986 if (!buff) {
4987 status = -ENOMEM;
4988 goto cleanup1;
4989 }
d66ae08b 4990 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4991 if (!buff_size) {
4992 status = -ENOMEM;
4993 goto cleanup1;
4994 }
4995 left = ioc->buf_size;
4996 data_ptr = ioc->buf;
4997 while (left) {
4998 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4999 buff_size[sg_used] = sz;
5000 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5001 if (buff[sg_used] == NULL) {
5002 status = -ENOMEM;
5003 goto cleanup1;
5004 }
9233fb10 5005 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5006 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5007 status = -EFAULT;
edd16368
SC		 5008 goto cleanup1;
5009 }
5010 } else
5011 memset(buff[sg_used], 0, sz);
5012 left -= sz;
5013 data_ptr += sz;
5014 sg_used++;
5015 }
5016 c = cmd_special_alloc(h);
5017 if (c == NULL) {
5018 status = -ENOMEM;
5019 goto cleanup1;
5020 }
5021 c->cmd_type = CMD_IOCTL_PEND;
5022 c->Header.ReplyQueue = 0;
50a0decf
SC		 5023 c->Header.SGList = (u8) sg_used;
5024 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5025 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
50a0decf 5026 c->Header.tag = c->busaddr;
edd16368
SC		 5027 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5028 if (ioc->buf_size > 0) {
5029 int i;
5030 for (i = 0; i < sg_used; i++) {
50a0decf 5031 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5032 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5033 if (dma_mapping_error(&h->pdev->dev,
5034 (dma_addr_t) temp64)) {
5035 c->SG[i].Addr = cpu_to_le64(0);
5036 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5037 hpsa_pci_unmap(h->pdev, c, i,
5038 PCI_DMA_BIDIRECTIONAL);
5039 status = -ENOMEM;
e2d4a1f6 5040 goto cleanup0;
bcc48ffa 5041 }
50a0decf
SC		 5042 c->SG[i].Addr = cpu_to_le64(temp64);
5043 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5044 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5045 }
50a0decf 5046 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5047 }
a0c12413 5048 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5049 if (sg_used)
5050 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5051 check_ioctl_unit_attention(h, c);
5052 /* Copy the error information out */
5053 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5054 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5055 status = -EFAULT;
e2d4a1f6 5056 goto cleanup0;
edd16368 5057 }
9233fb10 5058 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
edd16368
SC		 5059 /* Copy the data out of the buffer we created */
5060 BYTE __user *ptr = ioc->buf;
5061 for (i = 0; i < sg_used; i++) {
5062 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5063 status = -EFAULT;
e2d4a1f6 5064 goto cleanup0;
edd16368
SC		 5065 }
5066 ptr += buff_size[i];
5067 }
5068 }
edd16368 5069 status = 0;
e2d4a1f6
SC		 5070cleanup0:
5071 cmd_special_free(h, c);
edd16368
SC		 5072cleanup1:
5073 if (buff) {
5074 for (i = 0; i < sg_used; i++)
5075 kfree(buff[i]);
5076 kfree(buff);
5077 }
5078 kfree(buff_size);
5079 kfree(ioc);
5080 return status;
5081}
5082
5083static void check_ioctl_unit_attention(struct ctlr_info *h,
5084 struct CommandList *c)
5085{
5086 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5087 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5088 (void) check_for_unit_attention(h, c);
5089}
0390f0c0
SC		 5090
5091static int increment_passthru_count(struct ctlr_info *h)
5092{
5093 unsigned long flags;
5094
5095 spin_lock_irqsave(&h->passthru_count_lock, flags);
5096 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5097 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5098 return -1;
5099 }
5100 h->passthru_count++;
5101 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5102 return 0;
5103}
5104
5105static void decrement_passthru_count(struct ctlr_info *h)
5106{
5107 unsigned long flags;
5108
5109 spin_lock_irqsave(&h->passthru_count_lock, flags);
5110 if (h->passthru_count <= 0) {
5111 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5112 /* not expecting to get here. */
5113 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5114 return;
5115 }
5116 h->passthru_count--;
5117 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5118}
5119
edd16368
SC		 5120/*
5121 * ioctl
5122 */
42a91641 5123static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5124{
5125 struct ctlr_info *h;
5126 void __user *argp = (void __user *)arg;
0390f0c0 5127 int rc;
edd16368
SC		 5128
5129 h = sdev_to_hba(dev);
5130
5131 switch (cmd) {
5132 case CCISS_DEREGDISK:
5133 case CCISS_REGNEWDISK:
5134 case CCISS_REGNEWD:
a08a8471 5135 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5136 return 0;
5137 case CCISS_GETPCIINFO:
5138 return hpsa_getpciinfo_ioctl(h, argp);
5139 case CCISS_GETDRIVVER:
5140 return hpsa_getdrivver_ioctl(h, argp);
5141 case CCISS_PASSTHRU:
0390f0c0
SC		 5142 if (increment_passthru_count(h))
5143 return -EAGAIN;
5144 rc = hpsa_passthru_ioctl(h, argp);
5145 decrement_passthru_count(h);
5146 return rc;
edd16368 5147 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5148 if (increment_passthru_count(h))
5149 return -EAGAIN;
5150 rc = hpsa_big_passthru_ioctl(h, argp);
5151 decrement_passthru_count(h);
5152 return rc;
edd16368
SC		 5153 default:
5154 return -ENOTTY;
5155 }
5156}
5157
6f039790
GKH		 5158static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5159 u8 reset_type)
64670ac8
SC		 5160{
5161 struct CommandList *c;
5162
5163 c = cmd_alloc(h);
5164 if (!c)
5165 return -ENOMEM;
a2dac136
SC		 5166 /* fill_cmd can't fail here, no data buffer to map */
5167 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5168 RAID_CTLR_LUNID, TYPE_MSG);
5169 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5170 c->waiting = NULL;
5171 enqueue_cmd_and_start_io(h, c);
5172 /* Don't wait for completion, the reset won't complete. Don't free
5173 * the command either. This is the last command we will send before
5174 * re-initializing everything, so it doesn't matter and won't leak.
5175 */
5176 return 0;
5177}
5178
a2dac136 5179static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5180 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5181 int cmd_type)
5182{
5183 int pci_dir = XFER_NONE;
75167d2c 5184 struct CommandList *a; /* for commands to be aborted */
50a0decf 5185 u32 tupper, tlower;
edd16368
SC		 5186
5187 c->cmd_type = CMD_IOCTL_PEND;
5188 c->Header.ReplyQueue = 0;
5189 if (buff != NULL && size > 0) {
5190 c->Header.SGList = 1;
50a0decf 5191 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5192 } else {
5193 c->Header.SGList = 0;
50a0decf 5194 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5195 }
50a0decf 5196 c->Header.tag = c->busaddr;
edd16368
SC		 5197 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5198
edd16368
SC		 5199 if (cmd_type == TYPE_CMD) {
5200 switch (cmd) {
5201 case HPSA_INQUIRY:
5202 /* are we trying to read a vital product page */
b7bb24eb 5203 if (page_code & VPD_PAGE) {
edd16368 5204 c->Request.CDB[1] = 0x01;
b7bb24eb 5205 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5206 }
5207 c->Request.CDBLen = 6;
a505b86f
SC		 5208 c->Request.type_attr_dir =
5209 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5210 c->Request.Timeout = 0;
5211 c->Request.CDB[0] = HPSA_INQUIRY;
5212 c->Request.CDB[4] = size & 0xFF;
5213 break;
5214 case HPSA_REPORT_LOG:
5215 case HPSA_REPORT_PHYS:
5216 /* Talking to controller so It's a physical command
5217 mode = 00 target = 0. Nothing to write.
5218 */
5219 c->Request.CDBLen = 12;
a505b86f
SC		 5220 c->Request.type_attr_dir =
5221 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5222 c->Request.Timeout = 0;
5223 c->Request.CDB[0] = cmd;
5224 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5225 c->Request.CDB[7] = (size >> 16) & 0xFF;
5226 c->Request.CDB[8] = (size >> 8) & 0xFF;
5227 c->Request.CDB[9] = size & 0xFF;
5228 break;
edd16368
SC		 5229 case HPSA_CACHE_FLUSH:
5230 c->Request.CDBLen = 12;
a505b86f
SC		 5231 c->Request.type_attr_dir =
5232 TYPE_ATTR_DIR(cmd_type,
5233 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5234 c->Request.Timeout = 0;
5235 c->Request.CDB[0] = BMIC_WRITE;
5236 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5237 c->Request.CDB[7] = (size >> 8) & 0xFF;
5238 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5239 break;
5240 case TEST_UNIT_READY:
5241 c->Request.CDBLen = 6;
a505b86f
SC		 5242 c->Request.type_attr_dir =
5243 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5244 c->Request.Timeout = 0;
5245 break;
283b4a9b
SC		 5246 case HPSA_GET_RAID_MAP:
5247 c->Request.CDBLen = 12;
a505b86f
SC		 5248 c->Request.type_attr_dir =
5249 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5250 c->Request.Timeout = 0;
5251 c->Request.CDB[0] = HPSA_CISS_READ;
5252 c->Request.CDB[1] = cmd;
5253 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5254 c->Request.CDB[7] = (size >> 16) & 0xFF;
5255 c->Request.CDB[8] = (size >> 8) & 0xFF;
5256 c->Request.CDB[9] = size & 0xFF;
5257 break;
316b221a
SC		 5258 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5259 c->Request.CDBLen = 10;
a505b86f
SC		 5260 c->Request.type_attr_dir =
5261 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5262 c->Request.Timeout = 0;
5263 c->Request.CDB[0] = BMIC_READ;
5264 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5265 c->Request.CDB[7] = (size >> 16) & 0xFF;
5266 c->Request.CDB[8] = (size >> 8) & 0xFF;
5267 break;
edd16368
SC		 5268 default:
5269 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5270 BUG();
a2dac136 5271 return -1;
edd16368
SC		 5272 }
5273 } else if (cmd_type == TYPE_MSG) {
5274 switch (cmd) {
5275
5276 case HPSA_DEVICE_RESET_MSG:
5277 c->Request.CDBLen = 16;
a505b86f
SC		 5278 c->Request.type_attr_dir =
5279 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5280 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5281 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5282 c->Request.CDB[0] = cmd;
21e89afd 5283 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5284 /* If bytes 4-7 are zero, it means reset the */
5285 /* LunID device */
5286 c->Request.CDB[4] = 0x00;
5287 c->Request.CDB[5] = 0x00;
5288 c->Request.CDB[6] = 0x00;
5289 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5290 break;
5291 case HPSA_ABORT_MSG:
5292 a = buff; /* point to command to be aborted */
50a0decf
SC		 5293 dev_dbg(&h->pdev->dev, "Abort Tag:0x%016llx using request Tag:0x%016llx",
5294 a->Header.tag, c->Header.tag);
5295 tlower = (u32) (a->Header.tag >> 32);
5296 tupper = (u32) (a->Header.tag & 0x0ffffffffULL);
75167d2c 5297 c->Request.CDBLen = 16;
a505b86f
SC		 5298 c->Request.type_attr_dir =
5299 TYPE_ATTR_DIR(cmd_type,
5300 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5301 c->Request.Timeout = 0; /* Don't time out */
5302 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5303 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5304 c->Request.CDB[2] = 0x00; /* reserved */
5305 c->Request.CDB[3] = 0x00; /* reserved */
5306 /* Tag to abort goes in CDB[4]-CDB[11] */
50a0decf
SC		 5307 c->Request.CDB[4] = tlower & 0xFF;
5308 c->Request.CDB[5] = (tlower >> 8) & 0xFF;
5309 c->Request.CDB[6] = (tlower >> 16) & 0xFF;
5310 c->Request.CDB[7] = (tlower >> 24) & 0xFF;
5311 c->Request.CDB[8] = tupper & 0xFF;
5312 c->Request.CDB[9] = (tupper >> 8) & 0xFF;
5313 c->Request.CDB[10] = (tupper >> 16) & 0xFF;
5314 c->Request.CDB[11] = (tupper >> 24) & 0xFF;
75167d2c
SC		 5315 c->Request.CDB[12] = 0x00; /* reserved */
5316 c->Request.CDB[13] = 0x00; /* reserved */
5317 c->Request.CDB[14] = 0x00; /* reserved */
5318 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5319 break;
edd16368
SC		 5320 default:
5321 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5322 cmd);
5323 BUG();
5324 }
5325 } else {
5326 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5327 BUG();
5328 }
5329
a505b86f 5330 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5331 case XFER_READ:
5332 pci_dir = PCI_DMA_FROMDEVICE;
5333 break;
5334 case XFER_WRITE:
5335 pci_dir = PCI_DMA_TODEVICE;
5336 break;
5337 case XFER_NONE:
5338 pci_dir = PCI_DMA_NONE;
5339 break;
5340 default:
5341 pci_dir = PCI_DMA_BIDIRECTIONAL;
5342 }
a2dac136
SC		 5343 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5344 return -1;
5345 return 0;
edd16368
SC		 5346}
5347
5348/*
5349 * Map (physical) PCI mem into (virtual) kernel space
5350 */
5351static void __iomem *remap_pci_mem(ulong base, ulong size)
5352{
5353 ulong page_base = ((ulong) base) & PAGE_MASK;
5354 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5355 void __iomem *page_remapped = ioremap_nocache(page_base,
5356 page_offs + size);
edd16368
SC		 5357
5358 return page_remapped ? (page_remapped + page_offs) : NULL;
5359}
5360
5361/* Takes cmds off the submission queue and sends them to the hardware,
5362 * then puts them on the queue of cmds waiting for completion.
0b57075d 5363 * Assumes h->lock is held
edd16368 5364 */
0b57075d 5365static void start_io(struct ctlr_info *h, unsigned long *flags)
edd16368
SC		 5366{
5367 struct CommandList *c;
5368
9e0fc764
SC		 5369 while (!list_empty(&h->reqQ)) {
5370 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5371 /* can't do anything if fifo is full */
5372 if ((h->access.fifo_full(h))) {
396883e2 5373 h->fifo_recently_full = 1;
edd16368
SC		 5374 dev_warn(&h->pdev->dev, "fifo full\n");
5375 break;
5376 }
396883e2 5377 h->fifo_recently_full = 0;
edd16368
SC		 5378
5379 /* Get the first entry from the Request Q */
5380 removeQ(c);
5381 h->Qdepth--;
5382
edd16368
SC		 5383 /* Put job onto the completed Q */
5384 addQ(&h->cmpQ, c);
0cbf768e 5385 atomic_inc(&h->commands_outstanding);
0b57075d 5386 spin_unlock_irqrestore(&h->lock, *flags);
0cbf768e 5387 /* Tell the controller execute command */
e16a33ad 5388 h->access.submit_command(h, c);
0b57075d 5389 spin_lock_irqsave(&h->lock, *flags);
edd16368 5390 }
0b57075d
SC		 5391}
5392
5393static void lock_and_start_io(struct ctlr_info *h)
5394{
5395 unsigned long flags;
5396
5397 spin_lock_irqsave(&h->lock, flags);
5398 start_io(h, &flags);
e16a33ad 5399 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5400}
5401
254f796b 5402static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5403{
254f796b 5404 return h->access.command_completed(h, q);
edd16368
SC		 5405}
5406
900c5440 5407static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5408{
5409 return h->access.intr_pending(h);
5410}
5411
5412static inline long interrupt_not_for_us(struct ctlr_info *h)
5413{
10f66018
SC		 5414 return (h->access.intr_pending(h) == 0) ||
5415 (h->interrupts_enabled == 0);
edd16368
SC		 5416}
5417
01a02ffc
SC		 5418static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5419 u32 raw_tag)
edd16368
SC		 5420{
5421 if (unlikely(tag_index >= h->nr_cmds)) {
5422 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5423 return 1;
5424 }
5425 return 0;
5426}
5427
5a3d16f5 5428static inline void finish_cmd(struct CommandList *c)
edd16368 5429{
e16a33ad 5430 unsigned long flags;
396883e2
SC		 5431 int io_may_be_stalled = 0;
5432 struct ctlr_info *h = c->h;
0cbf768e 5433 int count;
e16a33ad 5434
396883e2 5435 spin_lock_irqsave(&h->lock, flags);
edd16368 5436 removeQ(c);
396883e2
SC		 5437
5438 /*
5439 * Check for possibly stalled i/o.
5440 *
5441 * If a fifo_full condition is encountered, requests will back up
5442 * in h->reqQ. This queue is only emptied out by start_io which is
5443 * only called when a new i/o request comes in. If no i/o's are
5444 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5445 * start_io from here if we detect such a danger.
5446 *
5447 * Normally, we shouldn't hit this case, but pounding on the
5448 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5449 * commands_outstanding is low. We want to avoid calling
5450 * start_io from in here as much as possible, and esp. don't
5451 * want to get in a cycle where we call start_io every time
5452 * through here.
5453 */
0cbf768e 5454 count = atomic_read(&h->commands_outstanding);
396883e2 5455 spin_unlock_irqrestore(&h->lock, flags);
0cbf768e
SC		 5456 if (unlikely(h->fifo_recently_full) && count < 5)
5457 io_may_be_stalled = 1;
396883e2 5458
e85c5974 5459 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5460 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5461 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5462 complete_scsi_command(c);
edd16368
SC		 5463 else if (c->cmd_type == CMD_IOCTL_PEND)
5464 complete(c->waiting);
396883e2 5465 if (unlikely(io_may_be_stalled))
0b57075d 5466 lock_and_start_io(h);
edd16368
SC		 5467}
5468
a104c99f
SC		 5469static inline u32 hpsa_tag_contains_index(u32 tag)
5470{
a104c99f
SC		 5471 return tag & DIRECT_LOOKUP_BIT;
5472}
5473
5474static inline u32 hpsa_tag_to_index(u32 tag)
5475{
a104c99f
SC		 5476 return tag >> DIRECT_LOOKUP_SHIFT;
5477}
5478
a9a3a273
SC		 5479
5480static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5481{
a9a3a273
SC		 5482#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5483#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5484 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5485 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5486 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5487}
5488
303932fd 5489/* process completion of an indexed ("direct lookup") command */
1d94f94d 5490static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5491 u32 raw_tag)
5492{
5493 u32 tag_index;
5494 struct CommandList *c;
5495
5496 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5497 if (!bad_tag(h, tag_index, raw_tag)) {
5498 c = h->cmd_pool + tag_index;
5499 finish_cmd(c);
5500 }
303932fd
DB		 5501}
5502
5503/* process completion of a non-indexed command */
1d94f94d 5504static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5505 u32 raw_tag)
5506{
5507 u32 tag;
5508 struct CommandList *c = NULL;
e16a33ad 5509 unsigned long flags;
303932fd 5510
a9a3a273 5511 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5512 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5513 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5514 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5515 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5516 finish_cmd(c);
1d94f94d 5517 return;
303932fd
DB		 5518 }
5519 }
e16a33ad 5520 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5521 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5522}
5523
64670ac8
SC		 5524/* Some controllers, like p400, will give us one interrupt
5525 * after a soft reset, even if we turned interrupts off.
5526 * Only need to check for this in the hpsa_xxx_discard_completions
5527 * functions.
5528 */
5529static int ignore_bogus_interrupt(struct ctlr_info *h)
5530{
5531 if (likely(!reset_devices))
5532 return 0;
5533
5534 if (likely(h->interrupts_enabled))
5535 return 0;
5536
5537 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5538 "(known firmware bug.) Ignoring.\n");
5539
5540 return 1;
5541}
5542
254f796b
MG		 5543/*
5544 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5545 * Relies on (h-q[x] == x) being true for x such that
5546 * 0 <= x < MAX_REPLY_QUEUES.
5547 */
5548static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5549{
254f796b
MG		 5550 return container_of((queue - *queue), struct ctlr_info, q[0]);
5551}
5552
5553static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5554{
5555 struct ctlr_info *h = queue_to_hba(queue);
5556 u8 q = *(u8 *) queue;
64670ac8
SC		 5557 u32 raw_tag;
5558
5559 if (ignore_bogus_interrupt(h))
5560 return IRQ_NONE;
5561
5562 if (interrupt_not_for_us(h))
5563 return IRQ_NONE;
a0c12413 5564 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5565 while (interrupt_pending(h)) {
254f796b 5566 raw_tag = get_next_completion(h, q);
64670ac8 5567 while (raw_tag != FIFO_EMPTY)
254f796b 5568 raw_tag = next_command(h, q);
64670ac8 5569 }
64670ac8
SC		 5570 return IRQ_HANDLED;
5571}
5572
254f796b 5573static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5574{
254f796b 5575 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5576 u32 raw_tag;
254f796b 5577 u8 q = *(u8 *) queue;
64670ac8
SC		 5578
5579 if (ignore_bogus_interrupt(h))
5580 return IRQ_NONE;
5581
a0c12413 5582 h->last_intr_timestamp = get_jiffies_64();
254f796b 5583 raw_tag = get_next_completion(h, q);
64670ac8 5584 while (raw_tag != FIFO_EMPTY)
254f796b 5585 raw_tag = next_command(h, q);
64670ac8
SC		 5586 return IRQ_HANDLED;
5587}
5588
254f796b 5589static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5590{
254f796b 5591 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5592 u32 raw_tag;
254f796b 5593 u8 q = *(u8 *) queue;
edd16368
SC		 5594
5595 if (interrupt_not_for_us(h))
5596 return IRQ_NONE;
a0c12413 5597 h->last_intr_timestamp = get_jiffies_64();
10f66018 5598 while (interrupt_pending(h)) {
254f796b 5599 raw_tag = get_next_completion(h, q);
10f66018 5600 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5601 if (likely(hpsa_tag_contains_index(raw_tag)))
5602 process_indexed_cmd(h, raw_tag);
10f66018 5603 else
1d94f94d 5604 process_nonindexed_cmd(h, raw_tag);
254f796b 5605 raw_tag = next_command(h, q);
10f66018
SC		 5606 }
5607 }
10f66018
SC		 5608 return IRQ_HANDLED;
5609}
5610
254f796b 5611static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5612{
254f796b 5613 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5614 u32 raw_tag;
254f796b 5615 u8 q = *(u8 *) queue;
10f66018 5616
a0c12413 5617 h->last_intr_timestamp = get_jiffies_64();
254f796b 5618 raw_tag = get_next_completion(h, q);
303932fd 5619 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5620 if (likely(hpsa_tag_contains_index(raw_tag)))
5621 process_indexed_cmd(h, raw_tag);
303932fd 5622 else
1d94f94d 5623 process_nonindexed_cmd(h, raw_tag);
254f796b 5624 raw_tag = next_command(h, q);
edd16368 5625 }
edd16368
SC		 5626 return IRQ_HANDLED;
5627}
5628
a9a3a273
SC		 5629/* Send a message CDB to the firmware. Careful, this only works
5630 * in simple mode, not performant mode due to the tag lookup.
5631 * We only ever use this immediately after a controller reset.
5632 */
6f039790
GKH		 5633static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5634 unsigned char type)
edd16368
SC		 5635{
5636 struct Command {
5637 struct CommandListHeader CommandHeader;
5638 struct RequestBlock Request;
5639 struct ErrDescriptor ErrorDescriptor;
5640 };
5641 struct Command *cmd;
5642 static const size_t cmd_sz = sizeof(*cmd) +
5643 sizeof(cmd->ErrorDescriptor);
5644 dma_addr_t paddr64;
5645 uint32_t paddr32, tag;
5646 void __iomem *vaddr;
5647 int i, err;
5648
5649 vaddr = pci_ioremap_bar(pdev, 0);
5650 if (vaddr == NULL)
5651 return -ENOMEM;
5652
5653 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5654 * CCISS commands, so they must be allocated from the lower 4GiB of
5655 * memory.
5656 */
5657 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5658 if (err) {
5659 iounmap(vaddr);
5660 return -ENOMEM;
5661 }
5662
5663 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5664 if (cmd == NULL) {
5665 iounmap(vaddr);
5666 return -ENOMEM;
5667 }
5668
5669 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5670 * although there's no guarantee, we assume that the address is at
5671 * least 4-byte aligned (most likely, it's page-aligned).
5672 */
5673 paddr32 = paddr64;
5674
5675 cmd->CommandHeader.ReplyQueue = 0;
5676 cmd->CommandHeader.SGList = 0;
50a0decf
SC		 5677 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
5678 cmd->CommandHeader.tag = paddr32;
edd16368
SC		 5679 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5680
5681 cmd->Request.CDBLen = 16;
a505b86f
SC		 5682 cmd->Request.type_attr_dir =
5683 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 5684 cmd->Request.Timeout = 0; /* Don't time out */
5685 cmd->Request.CDB[0] = opcode;
5686 cmd->Request.CDB[1] = type;
5687 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf
SC		 5688 cmd->ErrorDescriptor.Addr =
5689 cpu_to_le64((paddr32 + sizeof(*cmd)));
5690 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368
SC		 5691
5692 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5693
5694 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5695 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5696 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5697 break;
5698 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5699 }
5700
5701 iounmap(vaddr);
5702
5703 /* we leak the DMA buffer here ... no choice since the controller could
5704 * still complete the command.
5705 */
5706 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5707 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5708 opcode, type);
5709 return -ETIMEDOUT;
5710 }
5711
5712 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5713
5714 if (tag & HPSA_ERROR_BIT) {
5715 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5716 opcode, type);
5717 return -EIO;
5718 }
5719
5720 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5721 opcode, type);
5722 return 0;
5723}
5724
edd16368
SC		 5725#define hpsa_noop(p) hpsa_message(p, 3, 0)
5726
1df8552a 5727static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 5728 void __iomem *vaddr, u32 use_doorbell)
1df8552a
SC		 5729{
5730 u16 pmcsr;
5731 int pos;
5732
5733 if (use_doorbell) {
5734 /* For everything after the P600, the PCI power state method
5735 * of resetting the controller doesn't work, so we have this
5736 * other way using the doorbell register.
5737 */
5738 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5739 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 5740
00701a96 5741 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 5742 * doorbell reset and before any attempt to talk to the board
5743 * at all to ensure that this actually works and doesn't fall
5744 * over in some weird corner cases.
5745 */
00701a96 5746 msleep(10000);
1df8552a
SC		 5747 } else { /* Try to do it the PCI power state way */
5748
5749 /* Quoting from the Open CISS Specification: "The Power
5750 * Management Control/Status Register (CSR) controls the power
5751 * state of the device. The normal operating state is D0,
5752 * CSR=00h. The software off state is D3, CSR=03h. To reset
5753 * the controller, place the interface device in D3 then to D0,
5754 * this causes a secondary PCI reset which will reset the
5755 * controller." */
5756
5757 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5758 if (pos == 0) {
5759 dev_err(&pdev->dev,
5760 "hpsa_reset_controller: "
5761 "PCI PM not supported\n");
5762 return -ENODEV;
5763 }
5764 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5765 /* enter the D3hot power management state */
5766 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5767 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5768 pmcsr |= PCI_D3hot;
5769 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5770
5771 msleep(500);
5772
5773 /* enter the D0 power management state */
5774 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5775 pmcsr |= PCI_D0;
5776 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5777
5778 /*
5779 * The P600 requires a small delay when changing states.
5780 * Otherwise we may think the board did not reset and we bail.
5781 * This for kdump only and is particular to the P600.
5782 */
5783 msleep(500);
1df8552a
SC		 5784 }
5785 return 0;
5786}
5787
6f039790 5788static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5789{
5790 memset(driver_version, 0, len);
f79cfec6 5791 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5792}
5793
6f039790 5794static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5795{
5796 char *driver_version;
5797 int i, size = sizeof(cfgtable->driver_version);
5798
5799 driver_version = kmalloc(size, GFP_KERNEL);
5800 if (!driver_version)
5801 return -ENOMEM;
5802
5803 init_driver_version(driver_version, size);
5804 for (i = 0; i < size; i++)
5805 writeb(driver_version[i], &cfgtable->driver_version[i]);
5806 kfree(driver_version);
5807 return 0;
5808}
5809
6f039790
GKH		 5810static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5811 unsigned char *driver_ver)
580ada3c
SC		 5812{
5813 int i;
5814
5815 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5816 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5817}
5818
6f039790 5819static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5820{
5821
5822 char *driver_ver, *old_driver_ver;
5823 int rc, size = sizeof(cfgtable->driver_version);
5824
5825 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5826 if (!old_driver_ver)
5827 return -ENOMEM;
5828 driver_ver = old_driver_ver + size;
5829
5830 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5831 * should have been changed, otherwise we know the reset failed.
5832 */
5833 init_driver_version(old_driver_ver, size);
5834 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5835 rc = !memcmp(driver_ver, old_driver_ver, size);
5836 kfree(old_driver_ver);
5837 return rc;
5838}
edd16368 5839/* This does a hard reset of the controller using PCI power management
1df8552a 5840 * states or the using the doorbell register.
edd16368 5841 */
6f039790 5842static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5843{
1df8552a
SC		 5844 u64 cfg_offset;
5845 u32 cfg_base_addr;
5846 u64 cfg_base_addr_index;
5847 void __iomem *vaddr;
5848 unsigned long paddr;
580ada3c 5849 u32 misc_fw_support;
270d05de 5850 int rc;
1df8552a 5851 struct CfgTable __iomem *cfgtable;
cf0b08d0 5852 u32 use_doorbell;
18867659 5853 u32 board_id;
270d05de 5854 u16 command_register;
edd16368 5855
1df8552a
SC		 5856 /* For controllers as old as the P600, this is very nearly
5857 * the same thing as
edd16368
SC		 5858 *
5859 * pci_save_state(pci_dev);
5860 * pci_set_power_state(pci_dev, PCI_D3hot);
5861 * pci_set_power_state(pci_dev, PCI_D0);
5862 * pci_restore_state(pci_dev);
5863 *
1df8552a
SC		 5864 * For controllers newer than the P600, the pci power state
5865 * method of resetting doesn't work so we have another way
5866 * using the doorbell register.
edd16368 5867 */
18867659 5868
25c1e56a 5869 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5870 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5871 dev_warn(&pdev->dev, "Not resetting device.\n");
5872 return -ENODEV;
5873 }
46380786
SC		 5874
5875 /* if controller is soft- but not hard resettable... */
5876 if (!ctlr_is_hard_resettable(board_id))
5877 return -ENOTSUPP; /* try soft reset later. */
18867659 5878
270d05de
SC		 5879 /* Save the PCI command register */
5880 pci_read_config_word(pdev, 4, &command_register);
270d05de 5881 pci_save_state(pdev);
edd16368 5882
1df8552a
SC		 5883 /* find the first memory BAR, so we can find the cfg table */
5884 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5885 if (rc)
5886 return rc;
5887 vaddr = remap_pci_mem(paddr, 0x250);
5888 if (!vaddr)
5889 return -ENOMEM;
edd16368 5890
1df8552a
SC		 5891 /* find cfgtable in order to check if reset via doorbell is supported */
5892 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5893 &cfg_base_addr_index, &cfg_offset);
5894 if (rc)
5895 goto unmap_vaddr;
5896 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5897 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5898 if (!cfgtable) {
5899 rc = -ENOMEM;
5900 goto unmap_vaddr;
5901 }
580ada3c
SC		 5902 rc = write_driver_ver_to_cfgtable(cfgtable);
5903 if (rc)
5904 goto unmap_vaddr;
edd16368 5905
cf0b08d0
SC		 5906 /* If reset via doorbell register is supported, use that.
5907 * There are two such methods. Favor the newest method.
5908 */
1df8552a 5909 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5910 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5911 if (use_doorbell) {
5912 use_doorbell = DOORBELL_CTLR_RESET2;
5913 } else {
5914 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5915 if (use_doorbell) {
fba63097
MM		 5916 dev_warn(&pdev->dev, "Soft reset not supported. "
5917 "Firmware update is required.\n");
64670ac8 5918 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5919 goto unmap_cfgtable;
5920 }
5921 }
edd16368 5922
1df8552a
SC		 5923 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5924 if (rc)
5925 goto unmap_cfgtable;
edd16368 5926
270d05de 5927 pci_restore_state(pdev);
270d05de 5928 pci_write_config_word(pdev, 4, command_register);
edd16368 5929
1df8552a
SC		 5930 /* Some devices (notably the HP Smart Array 5i Controller)
5931 need a little pause here */
5932 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5933
fe5389c8
SC		 5934 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5935 if (rc) {
5936 dev_warn(&pdev->dev,
64670ac8
SC		 5937 "failed waiting for board to become ready "
5938 "after hard reset\n");
fe5389c8
SC		 5939 goto unmap_cfgtable;
5940 }
fe5389c8 5941
580ada3c
SC		 5942 rc = controller_reset_failed(vaddr);
5943 if (rc < 0)
5944 goto unmap_cfgtable;
5945 if (rc) {
64670ac8
SC		 5946 dev_warn(&pdev->dev, "Unable to successfully reset "
5947 "controller. Will try soft reset.\n");
5948 rc = -ENOTSUPP;
580ada3c 5949 } else {
64670ac8 5950 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5951 }
5952
5953unmap_cfgtable:
5954 iounmap(cfgtable);
5955
5956unmap_vaddr:
5957 iounmap(vaddr);
5958 return rc;
edd16368
SC		 5959}
5960
5961/*
5962 * We cannot read the structure directly, for portability we must use
5963 * the io functions.
5964 * This is for debug only.
5965 */
42a91641 5966static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 5967{
58f8665c 5968#ifdef HPSA_DEBUG
edd16368
SC		 5969 int i;
5970 char temp_name[17];
5971
5972 dev_info(dev, "Controller Configuration information\n");
5973 dev_info(dev, "------------------------------------\n");
5974 for (i = 0; i < 4; i++)
5975 temp_name[i] = readb(&(tb->Signature[i]));
5976 temp_name[4] = '\0';
5977 dev_info(dev, " Signature = %s\n", temp_name);
5978 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5979 dev_info(dev, " Transport methods supported = 0x%x\n",
5980 readl(&(tb->TransportSupport)));
5981 dev_info(dev, " Transport methods active = 0x%x\n",
5982 readl(&(tb->TransportActive)));
5983 dev_info(dev, " Requested transport Method = 0x%x\n",
5984 readl(&(tb->HostWrite.TransportRequest)));
5985 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5986 readl(&(tb->HostWrite.CoalIntDelay)));
5987 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5988 readl(&(tb->HostWrite.CoalIntCount)));
5989 dev_info(dev, " Max outstanding commands = 0x%d\n",
5990 readl(&(tb->CmdsOutMax)));
5991 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5992 for (i = 0; i < 16; i++)
5993 temp_name[i] = readb(&(tb->ServerName[i]));
5994 temp_name[16] = '\0';
5995 dev_info(dev, " Server Name = %s\n", temp_name);
5996 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5997 readl(&(tb->HeartBeat)));
edd16368 5998#endif /* HPSA_DEBUG */
58f8665c 5999}
edd16368
SC		 6000
6001static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6002{
6003 int i, offset, mem_type, bar_type;
6004
6005 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6006 return 0;
6007 offset = 0;
6008 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6009 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6010 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6011 offset += 4;
6012 else {
6013 mem_type = pci_resource_flags(pdev, i) &
6014 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6015 switch (mem_type) {
6016 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6017 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6018 offset += 4; /* 32 bit */
6019 break;
6020 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6021 offset += 8;
6022 break;
6023 default: /* reserved in PCI 2.2 */
6024 dev_warn(&pdev->dev,
6025 "base address is invalid\n");
6026 return -1;
6027 break;
6028 }
6029 }
6030 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6031 return i + 1;
6032 }
6033 return -1;
6034}
6035
6036/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6037 * controllers that are capable. If not, we use IO-APIC mode.
6038 */
6039
6f039790 6040static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6041{
6042#ifdef CONFIG_PCI_MSI
254f796b
MG		 6043 int err, i;
6044 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6045
6046 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6047 hpsa_msix_entries[i].vector = 0;
6048 hpsa_msix_entries[i].entry = i;
6049 }
edd16368
SC		 6050
6051 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6052 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6053 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6054 goto default_int_mode;
55c06c71
SC		 6055 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6056 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6057 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6058 if (h->msix_vector > num_online_cpus())
6059 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6060 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6061 1, h->msix_vector);
6062 if (err < 0) {
6063 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6064 h->msix_vector = 0;
6065 goto single_msi_mode;
6066 } else if (err < h->msix_vector) {
55c06c71 6067 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6068 "available\n", err);
edd16368 6069 }
18fce3c4
AG		 6070 h->msix_vector = err;
6071 for (i = 0; i < h->msix_vector; i++)
6072 h->intr[i] = hpsa_msix_entries[i].vector;
6073 return;
edd16368 6074 }
18fce3c4 6075single_msi_mode:
55c06c71
SC		 6076 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6077 dev_info(&h->pdev->dev, "MSI\n");
6078 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6079 h->msi_vector = 1;
6080 else
55c06c71 6081 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6082 }
6083default_int_mode:
6084#endif /* CONFIG_PCI_MSI */
6085 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6086 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6087}
6088
6f039790 6089static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6090{
6091 int i;
6092 u32 subsystem_vendor_id, subsystem_device_id;
6093
6094 subsystem_vendor_id = pdev->subsystem_vendor;
6095 subsystem_device_id = pdev->subsystem_device;
6096 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6097 subsystem_vendor_id;
6098
6099 for (i = 0; i < ARRAY_SIZE(products); i++)
6100 if (*board_id == products[i].board_id)
6101 return i;
6102
6798cc0a
SC		 6103 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6104 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6105 !hpsa_allow_any) {
e5c880d1
SC		 6106 dev_warn(&pdev->dev, "unrecognized board ID: "
6107 "0x%08x, ignoring.\n", *board_id);
6108 return -ENODEV;
6109 }
6110 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6111}
6112
6f039790
GKH		 6113static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6114 unsigned long *memory_bar)
3a7774ce
SC		 6115{
6116 int i;
6117
6118 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6119 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6120 /* addressing mode bits already removed */
12d2cd47
SC		 6121 *memory_bar = pci_resource_start(pdev, i);
6122 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6123 *memory_bar);
6124 return 0;
6125 }
12d2cd47 6126 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6127 return -ENODEV;
6128}
6129
6f039790
GKH		 6130static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6131 int wait_for_ready)
2c4c8c8b 6132{
fe5389c8 6133 int i, iterations;
2c4c8c8b 6134 u32 scratchpad;
fe5389c8
SC		 6135 if (wait_for_ready)
6136 iterations = HPSA_BOARD_READY_ITERATIONS;
6137 else
6138 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6139
fe5389c8
SC		 6140 for (i = 0; i < iterations; i++) {
6141 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6142 if (wait_for_ready) {
6143 if (scratchpad == HPSA_FIRMWARE_READY)
6144 return 0;
6145 } else {
6146 if (scratchpad != HPSA_FIRMWARE_READY)
6147 return 0;
6148 }
2c4c8c8b
SC		 6149 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6150 }
fe5389c8 6151 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6152 return -ENODEV;
6153}
6154
6f039790
GKH		 6155static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6156 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6157 u64 *cfg_offset)
a51fd47f
SC		 6158{
6159 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6160 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6161 *cfg_base_addr &= (u32) 0x0000ffff;
6162 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6163 if (*cfg_base_addr_index == -1) {
6164 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6165 return -ENODEV;
6166 }
6167 return 0;
6168}
6169
6f039790 6170static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6171{
01a02ffc
SC		 6172 u64 cfg_offset;
6173 u32 cfg_base_addr;
6174 u64 cfg_base_addr_index;
303932fd 6175 u32 trans_offset;
a51fd47f 6176 int rc;
77c4495c 6177
a51fd47f
SC		 6178 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6179 &cfg_base_addr_index, &cfg_offset);
6180 if (rc)
6181 return rc;
77c4495c 6182 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6183 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6184 if (!h->cfgtable)
6185 return -ENOMEM;
580ada3c
SC		 6186 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6187 if (rc)
6188 return rc;
77c4495c 6189 /* Find performant mode table. */
a51fd47f 6190 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6191 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6192 cfg_base_addr_index)+cfg_offset+trans_offset,
6193 sizeof(*h->transtable));
6194 if (!h->transtable)
6195 return -ENOMEM;
6196 return 0;
6197}
6198
6f039790 6199static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6200{
6201 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6202
6203 /* Limit commands in memory limited kdump scenario. */
6204 if (reset_devices && h->max_commands > 32)
6205 h->max_commands = 32;
6206
cba3d38b
SC		 6207 if (h->max_commands < 16) {
6208 dev_warn(&h->pdev->dev, "Controller reports "
6209 "max supported commands of %d, an obvious lie. "
6210 "Using 16. Ensure that firmware is up to date.\n",
6211 h->max_commands);
6212 h->max_commands = 16;
6213 }
6214}
6215
b93d7536
SC		 6216/* Interrogate the hardware for some limits:
6217 * max commands, max SG elements without chaining, and with chaining,
6218 * SG chain block size, etc.
6219 */
6f039790 6220static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6221{
cba3d38b 6222 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6223 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6224 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6225 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6226 /*
6227 * Limit in-command s/g elements to 32 save dma'able memory.
6228 * Howvever spec says if 0, use 31
6229 */
6230 h->max_cmd_sg_entries = 31;
6231 if (h->maxsgentries > 512) {
6232 h->max_cmd_sg_entries = 32;
1a63ea6f 6233 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6234 h->maxsgentries--; /* save one for chain pointer */
6235 } else {
b93d7536 6236 h->chainsize = 0;
1a63ea6f 6237 h->maxsgentries = 31; /* default to traditional values */
b93d7536 6238 }
75167d2c
SC		 6239
6240 /* Find out what task management functions are supported and cache */
6241 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6242 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6243 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6244 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6245 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6246}
6247
76c46e49
SC		 6248static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6249{
0fc9fd40 6250 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6251 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6252 return false;
6253 }
6254 return true;
6255}
6256
97a5e98c 6257static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6258{
97a5e98c 6259 u32 driver_support;
f7c39101 6260
97a5e98c 6261 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6262 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6263#ifdef CONFIG_X86
97a5e98c 6264 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6265#endif
28e13446
SC		 6266 driver_support |= ENABLE_UNIT_ATTN;
6267 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6268}
6269
3d0eab67
SC		 6270/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6271 * in a prefetch beyond physical memory.
6272 */
6273static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6274{
6275 u32 dma_prefetch;
6276
6277 if (h->board_id != 0x3225103C)
6278 return;
6279 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6280 dma_prefetch |= 0x8000;
6281 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6282}
6283
76438d08
SC		 6284static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6285{
6286 int i;
6287 u32 doorbell_value;
6288 unsigned long flags;
6289 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6290 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6291 spin_lock_irqsave(&h->lock, flags);
6292 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6293 spin_unlock_irqrestore(&h->lock, flags);
6294 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6295 break;
6296 /* delay and try again */
6297 msleep(20);
6298 }
6299}
6300
6f039790 6301static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6302{
6303 int i;
6eaf46fd
SC		 6304 u32 doorbell_value;
6305 unsigned long flags;
eb6b2ae9
SC		 6306
6307 /* under certain very rare conditions, this can take awhile.
6308 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6309 * as we enter this code.)
6310 */
6311 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6312 spin_lock_irqsave(&h->lock, flags);
6313 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6314 spin_unlock_irqrestore(&h->lock, flags);
382be668 6315 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6316 break;
6317 /* delay and try again */
60d3f5b0 6318 usleep_range(10000, 20000);
eb6b2ae9 6319 }
3f4336f3
SC		 6320}
6321
6f039790 6322static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6323{
6324 u32 trans_support;
6325
6326 trans_support = readl(&(h->cfgtable->TransportSupport));
6327 if (!(trans_support & SIMPLE_MODE))
6328 return -ENOTSUPP;
6329
6330 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6331
3f4336f3
SC		 6332 /* Update the field, and then ring the doorbell */
6333 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6334 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6335 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6336 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6337 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6338 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6339 goto error;
960a30e7 6340 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6341 return 0;
283b4a9b
SC		 6342error:
6343 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6344 return -ENODEV;
eb6b2ae9
SC		 6345}
6346
6f039790 6347static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6348{
eb6b2ae9 6349 int prod_index, err;
edd16368 6350
e5c880d1
SC		 6351 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6352 if (prod_index < 0)
6353 return -ENODEV;
6354 h->product_name = products[prod_index].product_name;
6355 h->access = *(products[prod_index].access);
edd16368 6356
e5a44df8
MG		 6357 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6358 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6359
55c06c71 6360 err = pci_enable_device(h->pdev);
edd16368 6361 if (err) {
55c06c71 6362 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6363 return err;
6364 }
6365
5cb460a6
SC		 6366 /* Enable bus mastering (pci_disable_device may disable this) */
6367 pci_set_master(h->pdev);
6368
f79cfec6 6369 err = pci_request_regions(h->pdev, HPSA);
edd16368 6370 if (err) {
55c06c71
SC		 6371 dev_err(&h->pdev->dev,
6372 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6373 return err;
6374 }
6b3f4c52 6375 hpsa_interrupt_mode(h);
12d2cd47 6376 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6377 if (err)
edd16368 6378 goto err_out_free_res;
edd16368 6379 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6380 if (!h->vaddr) {
6381 err = -ENOMEM;
6382 goto err_out_free_res;
6383 }
fe5389c8 6384 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6385 if (err)
edd16368 6386 goto err_out_free_res;
77c4495c
SC		 6387 err = hpsa_find_cfgtables(h);
6388 if (err)
edd16368 6389 goto err_out_free_res;
b93d7536 6390 hpsa_find_board_params(h);
edd16368 6391
76c46e49 6392 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6393 err = -ENODEV;
6394 goto err_out_free_res;
6395 }
97a5e98c 6396 hpsa_set_driver_support_bits(h);
3d0eab67 6397 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6398 err = hpsa_enter_simple_mode(h);
6399 if (err)
edd16368 6400 goto err_out_free_res;
edd16368
SC		 6401 return 0;
6402
6403err_out_free_res:
204892e9
SC		 6404 if (h->transtable)
6405 iounmap(h->transtable);
6406 if (h->cfgtable)
6407 iounmap(h->cfgtable);
6408 if (h->vaddr)
6409 iounmap(h->vaddr);
f0bd0b68 6410 pci_disable_device(h->pdev);
55c06c71 6411 pci_release_regions(h->pdev);
edd16368
SC		 6412 return err;
6413}
6414
6f039790 6415static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6416{
6417 int rc;
6418
6419#define HBA_INQUIRY_BYTE_COUNT 64
6420 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6421 if (!h->hba_inquiry_data)
6422 return;
6423 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6424 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6425 if (rc != 0) {
6426 kfree(h->hba_inquiry_data);
6427 h->hba_inquiry_data = NULL;
6428 }
6429}
6430
6f039790 6431static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6432{
1df8552a 6433 int rc, i;
4c2a8c40
SC		 6434
6435 if (!reset_devices)
6436 return 0;
6437
132aa220
TH		 6438 /* kdump kernel is loading, we don't know in which state is
6439 * the pci interface. The dev->enable_cnt is equal zero
6440 * so we call enable+disable, wait a while and switch it on.
6441 */
6442 rc = pci_enable_device(pdev);
6443 if (rc) {
6444 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6445 return -ENODEV;
6446 }
6447 pci_disable_device(pdev);
6448 msleep(260); /* a randomly chosen number */
6449 rc = pci_enable_device(pdev);
6450 if (rc) {
6451 dev_warn(&pdev->dev, "failed to enable device.\n");
6452 return -ENODEV;
6453 }
859c75ab 6454 pci_set_master(pdev);
1df8552a
SC		 6455 /* Reset the controller with a PCI power-cycle or via doorbell */
6456 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6457
1df8552a
SC		 6458 /* -ENOTSUPP here means we cannot reset the controller
6459 * but it's already (and still) up and running in
18867659
SC		 6460 * "performant mode". Or, it might be 640x, which can't reset
6461 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6462 */
132aa220
TH		 6463 if (rc) {
6464 if (rc != -ENOTSUPP) /* just try to do the kdump anyhow. */
6465 rc = -ENODEV;
6466 goto out_disable;
6467 }
4c2a8c40
SC		 6468
6469 /* Now try to get the controller to respond to a no-op */
2b870cb3 6470 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6471 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6472 if (hpsa_noop(pdev) == 0)
6473 break;
6474 else
6475 dev_warn(&pdev->dev, "no-op failed%s\n",
6476 (i < 11 ? "; re-trying" : ""));
6477 }
132aa220
TH		 6478
6479out_disable:
6480
6481 pci_disable_device(pdev);
6482 return rc;
4c2a8c40
SC		 6483}
6484
6f039790 6485static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6486{
6487 h->cmd_pool_bits = kzalloc(
6488 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6489 sizeof(unsigned long), GFP_KERNEL);
6490 h->cmd_pool = pci_alloc_consistent(h->pdev,
6491 h->nr_cmds * sizeof(*h->cmd_pool),
6492 &(h->cmd_pool_dhandle));
6493 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6494 h->nr_cmds * sizeof(*h->errinfo_pool),
6495 &(h->errinfo_pool_dhandle));
6496 if ((h->cmd_pool_bits == NULL)
6497 || (h->cmd_pool == NULL)
6498 || (h->errinfo_pool == NULL)) {
6499 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6500 return -ENOMEM;
6501 }
6502 return 0;
6503}
6504
6505static void hpsa_free_cmd_pool(struct ctlr_info *h)
6506{
6507 kfree(h->cmd_pool_bits);
6508 if (h->cmd_pool)
6509 pci_free_consistent(h->pdev,
6510 h->nr_cmds * sizeof(struct CommandList),
6511 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6512 if (h->ioaccel2_cmd_pool)
6513 pci_free_consistent(h->pdev,
6514 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6515 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6516 if (h->errinfo_pool)
6517 pci_free_consistent(h->pdev,
6518 h->nr_cmds * sizeof(struct ErrorInfo),
6519 h->errinfo_pool,
6520 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6521 if (h->ioaccel_cmd_pool)
6522 pci_free_consistent(h->pdev,
6523 h->nr_cmds * sizeof(struct io_accel1_cmd),
6524 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6525}
6526
41b3cf08
SC		 6527static void hpsa_irq_affinity_hints(struct ctlr_info *h)
6528{
6529 int i, cpu, rc;
6530
6531 cpu = cpumask_first(cpu_online_mask);
6532 for (i = 0; i < h->msix_vector; i++) {
6533 rc = irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
6534 cpu = cpumask_next(cpu, cpu_online_mask);
6535 }
6536}
6537
0ae01a32
SC		 6538static int hpsa_request_irq(struct ctlr_info *h,
6539 irqreturn_t (*msixhandler)(int, void *),
6540 irqreturn_t (*intxhandler)(int, void *))
6541{
254f796b 6542 int rc, i;
0ae01a32 6543
254f796b
MG		 6544 /*
6545 * initialize h->q[x] = x so that interrupt handlers know which
6546 * queue to process.
6547 */
6548 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6549 h->q[i] = (u8) i;
6550
eee0f03a 6551 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6552 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6553 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6554 rc = request_irq(h->intr[i], msixhandler,
6555 0, h->devname,
6556 &h->q[i]);
41b3cf08 6557 hpsa_irq_affinity_hints(h);
254f796b
MG		 6558 } else {
6559 /* Use single reply pool */
eee0f03a 6560 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6561 rc = request_irq(h->intr[h->intr_mode],
6562 msixhandler, 0, h->devname,
6563 &h->q[h->intr_mode]);
6564 } else {
6565 rc = request_irq(h->intr[h->intr_mode],
6566 intxhandler, IRQF_SHARED, h->devname,
6567 &h->q[h->intr_mode]);
6568 }
6569 }
0ae01a32
SC		 6570 if (rc) {
6571 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6572 h->intr[h->intr_mode], h->devname);
6573 return -ENODEV;
6574 }
6575 return 0;
6576}
6577
6f039790 6578static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6579{
6580 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6581 HPSA_RESET_TYPE_CONTROLLER)) {
6582 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6583 return -EIO;
6584 }
6585
6586 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6587 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6588 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6589 return -1;
6590 }
6591
6592 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6593 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6594 dev_warn(&h->pdev->dev, "Board failed to become ready "
6595 "after soft reset.\n");
6596 return -1;
6597 }
6598
6599 return 0;
6600}
6601
254f796b
MG		 6602static void free_irqs(struct ctlr_info *h)
6603{
6604 int i;
6605
6606 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6607 /* Single reply queue, only one irq to free */
6608 i = h->intr_mode;
41b3cf08 6609 irq_set_affinity_hint(h->intr[i], NULL);
254f796b
MG		 6610 free_irq(h->intr[i], &h->q[i]);
6611 return;
6612 }
6613
41b3cf08
SC		 6614 for (i = 0; i < h->msix_vector; i++) {
6615 irq_set_affinity_hint(h->intr[i], NULL);
254f796b 6616 free_irq(h->intr[i], &h->q[i]);
41b3cf08 6617 }
254f796b
MG		 6618}
6619
0097f0f4 6620static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6621{
254f796b 6622 free_irqs(h);
64670ac8 6623#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6624 if (h->msix_vector) {
6625 if (h->pdev->msix_enabled)
6626 pci_disable_msix(h->pdev);
6627 } else if (h->msi_vector) {
6628 if (h->pdev->msi_enabled)
6629 pci_disable_msi(h->pdev);
6630 }
64670ac8 6631#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6632}
6633
072b0518
SC		 6634static void hpsa_free_reply_queues(struct ctlr_info *h)
6635{
6636 int i;
6637
6638 for (i = 0; i < h->nreply_queues; i++) {
6639 if (!h->reply_queue[i].head)
6640 continue;
6641 pci_free_consistent(h->pdev, h->reply_queue_size,
6642 h->reply_queue[i].head, h->reply_queue[i].busaddr);
6643 h->reply_queue[i].head = NULL;
6644 h->reply_queue[i].busaddr = 0;
6645 }
6646}
6647
0097f0f4
SC		 6648static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6649{
6650 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6651 hpsa_free_sg_chain_blocks(h);
6652 hpsa_free_cmd_pool(h);
e1f7de0c 6653 kfree(h->ioaccel1_blockFetchTable);
64670ac8 6654 kfree(h->blockFetchTable);
072b0518 6655 hpsa_free_reply_queues(h);
64670ac8
SC		 6656 if (h->vaddr)
6657 iounmap(h->vaddr);
6658 if (h->transtable)
6659 iounmap(h->transtable);
6660 if (h->cfgtable)
6661 iounmap(h->cfgtable);
132aa220 6662 pci_disable_device(h->pdev);
64670ac8
SC		 6663 pci_release_regions(h->pdev);
6664 kfree(h);
6665}
6666
a0c12413
SC		 6667/* Called when controller lockup detected. */
6668static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6669{
6670 struct CommandList *c = NULL;
6671
6672 assert_spin_locked(&h->lock);
6673 /* Mark all outstanding commands as failed and complete them. */
6674 while (!list_empty(list)) {
6675 c = list_entry(list->next, struct CommandList, list);
6676 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6677 finish_cmd(c);
a0c12413
SC		 6678 }
6679}
6680
094963da
SC		 6681static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
6682{
6683 int i, cpu;
6684
6685 cpu = cpumask_first(cpu_online_mask);
6686 for (i = 0; i < num_online_cpus(); i++) {
6687 u32 *lockup_detected;
6688 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
6689 *lockup_detected = value;
6690 cpu = cpumask_next(cpu, cpu_online_mask);
6691 }
6692 wmb(); /* be sure the per-cpu variables are out to memory */
6693}
6694
a0c12413
SC		 6695static void controller_lockup_detected(struct ctlr_info *h)
6696{
6697 unsigned long flags;
094963da 6698 u32 lockup_detected;
a0c12413 6699
a0c12413
SC		 6700 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6701 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 6702 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6703 if (!lockup_detected) {
6704 /* no heartbeat, but controller gave us a zero. */
6705 dev_warn(&h->pdev->dev,
6706 "lockup detected but scratchpad register is zero\n");
6707 lockup_detected = 0xffffffff;
6708 }
6709 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413
SC		 6710 spin_unlock_irqrestore(&h->lock, flags);
6711 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
094963da 6712 lockup_detected);
a0c12413
SC		 6713 pci_disable_device(h->pdev);
6714 spin_lock_irqsave(&h->lock, flags);
6715 fail_all_cmds_on_list(h, &h->cmpQ);
6716 fail_all_cmds_on_list(h, &h->reqQ);
6717 spin_unlock_irqrestore(&h->lock, flags);
6718}
6719
a0c12413
SC		 6720static void detect_controller_lockup(struct ctlr_info *h)
6721{
6722 u64 now;
6723 u32 heartbeat;
6724 unsigned long flags;
6725
a0c12413
SC		 6726 now = get_jiffies_64();
6727 /* If we've received an interrupt recently, we're ok. */
6728 if (time_after64(h->last_intr_timestamp +
e85c5974 6729 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6730 return;
6731
6732 /*
6733 * If we've already checked the heartbeat recently, we're ok.
6734 * This could happen if someone sends us a signal. We
6735 * otherwise don't care about signals in this thread.
6736 */
6737 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6738 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6739 return;
6740
6741 /* If heartbeat has not changed since we last looked, we're not ok. */
6742 spin_lock_irqsave(&h->lock, flags);
6743 heartbeat = readl(&h->cfgtable->HeartBeat);
6744 spin_unlock_irqrestore(&h->lock, flags);
6745 if (h->last_heartbeat == heartbeat) {
6746 controller_lockup_detected(h);
6747 return;
6748 }
6749
6750 /* We're ok. */
6751 h->last_heartbeat = heartbeat;
6752 h->last_heartbeat_timestamp = now;
6753}
6754
9846590e 6755static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6756{
6757 int i;
6758 char *event_type;
6759
e863d68e
ST		 6760 /* Clear the driver-requested rescan flag */
6761 h->drv_req_rescan = 0;
6762
76438d08 6763 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6764 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6765 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6766 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6767 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6768
6769 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6770 event_type = "state change";
6771 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6772 event_type = "configuration change";
6773 /* Stop sending new RAID offload reqs via the IO accelerator */
6774 scsi_block_requests(h->scsi_host);
6775 for (i = 0; i < h->ndevices; i++)
6776 h->dev[i]->offload_enabled = 0;
23100dd9 6777 hpsa_drain_accel_commands(h);
76438d08
SC		 6778 /* Set 'accelerator path config change' bit */
6779 dev_warn(&h->pdev->dev,
6780 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6781 h->events, event_type);
6782 writel(h->events, &(h->cfgtable->clear_event_notify));
6783 /* Set the "clear event notify field update" bit 6 */
6784 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6785 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6786 hpsa_wait_for_clear_event_notify_ack(h);
6787 scsi_unblock_requests(h->scsi_host);
6788 } else {
6789 /* Acknowledge controller notification events. */
6790 writel(h->events, &(h->cfgtable->clear_event_notify));
6791 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6792 hpsa_wait_for_clear_event_notify_ack(h);
6793#if 0
6794 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6795 hpsa_wait_for_mode_change_ack(h);
6796#endif
6797 }
9846590e 6798 return;
76438d08
SC		 6799}
6800
6801/* Check a register on the controller to see if there are configuration
6802 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6803 * we should rescan the controller for devices.
6804 * Also check flag for driver-initiated rescan.
76438d08 6805 */
9846590e 6806static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6807{
9846590e
SC		 6808 if (h->drv_req_rescan)
6809 return 1;
6810
76438d08 6811 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6812 return 0;
76438d08
SC		 6813
6814 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6815 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6816}
76438d08 6817
9846590e
SC		 6818/*
6819 * Check if any of the offline devices have become ready
6820 */
6821static int hpsa_offline_devices_ready(struct ctlr_info *h)
6822{
6823 unsigned long flags;
6824 struct offline_device_entry *d;
6825 struct list_head *this, *tmp;
6826
6827 spin_lock_irqsave(&h->offline_device_lock, flags);
6828 list_for_each_safe(this, tmp, &h->offline_device_list) {
6829 d = list_entry(this, struct offline_device_entry,
6830 offline_list);
6831 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 6832 if (!hpsa_volume_offline(h, d->scsi3addr)) {
6833 spin_lock_irqsave(&h->offline_device_lock, flags);
6834 list_del(&d->offline_list);
6835 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 6836 return 1;
d1fea47c 6837 }
9846590e
SC		 6838 spin_lock_irqsave(&h->offline_device_lock, flags);
6839 }
6840 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6841 return 0;
76438d08
SC		 6842}
6843
9846590e 6844
8a98db73 6845static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6846{
6847 unsigned long flags;
8a98db73
SC		 6848 struct ctlr_info *h = container_of(to_delayed_work(work),
6849 struct ctlr_info, monitor_ctlr_work);
6850 detect_controller_lockup(h);
094963da 6851 if (lockup_detected(h))
8a98db73 6852 return;
9846590e
SC		 6853
6854 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6855 scsi_host_get(h->scsi_host);
6856 h->drv_req_rescan = 0;
6857 hpsa_ack_ctlr_events(h);
6858 hpsa_scan_start(h->scsi_host);
6859 scsi_host_put(h->scsi_host);
6860 }
6861
8a98db73
SC		 6862 spin_lock_irqsave(&h->lock, flags);
6863 if (h->remove_in_progress) {
6864 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6865 return;
6866 }
8a98db73
SC		 6867 schedule_delayed_work(&h->monitor_ctlr_work,
6868 h->heartbeat_sample_interval);
6869 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6870}
6871
6f039790 6872static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6873{
4c2a8c40 6874 int dac, rc;
edd16368 6875 struct ctlr_info *h;
64670ac8
SC		 6876 int try_soft_reset = 0;
6877 unsigned long flags;
edd16368
SC		 6878
6879 if (number_of_controllers == 0)
6880 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6881
4c2a8c40 6882 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6883 if (rc) {
6884 if (rc != -ENOTSUPP)
6885 return rc;
6886 /* If the reset fails in a particular way (it has no way to do
6887 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6888 * a soft reset once we get the controller configured up to the
6889 * point that it can accept a command.
6890 */
6891 try_soft_reset = 1;
6892 rc = 0;
6893 }
6894
6895reinit_after_soft_reset:
edd16368 6896
303932fd
DB		 6897 /* Command structures must be aligned on a 32-byte boundary because
6898 * the 5 lower bits of the address are used by the hardware. and by
6899 * the driver. See comments in hpsa.h for more info.
6900 */
303932fd 6901 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6902 h = kzalloc(sizeof(*h), GFP_KERNEL);
6903 if (!h)
ecd9aad4 6904 return -ENOMEM;
edd16368 6905
55c06c71 6906 h->pdev = pdev;
a9a3a273 6907 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6908 INIT_LIST_HEAD(&h->cmpQ);
6909 INIT_LIST_HEAD(&h->reqQ);
9846590e 6910 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6911 spin_lock_init(&h->lock);
9846590e 6912 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6913 spin_lock_init(&h->scan_lock);
0390f0c0 6914 spin_lock_init(&h->passthru_count_lock);
094963da
SC		 6915
6916 /* Allocate and clear per-cpu variable lockup_detected */
6917 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 6918 if (!h->lockup_detected) {
6919 rc = -ENOMEM;
094963da 6920 goto clean1;
2a5ac326 6921 }
094963da
SC		 6922 set_lockup_detected_for_all_cpus(h, 0);
6923
55c06c71 6924 rc = hpsa_pci_init(h);
ecd9aad4 6925 if (rc != 0)
edd16368
SC		 6926 goto clean1;
6927
f79cfec6 6928 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6929 h->ctlr = number_of_controllers;
6930 number_of_controllers++;
edd16368
SC		 6931
6932 /* configure PCI DMA stuff */
ecd9aad4
SC		 6933 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6934 if (rc == 0) {
edd16368 6935 dac = 1;
ecd9aad4
SC		 6936 } else {
6937 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6938 if (rc == 0) {
6939 dac = 0;
6940 } else {
6941 dev_err(&pdev->dev, "no suitable DMA available\n");
6942 goto clean1;
6943 }
edd16368
SC		 6944 }
6945
6946 /* make sure the board interrupts are off */
6947 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6948
0ae01a32 6949 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6950 goto clean2;
303932fd
DB		 6951 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6952 h->devname, pdev->device,
a9a3a273 6953 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6954 if (hpsa_allocate_cmd_pool(h))
edd16368 6955 goto clean4;
33a2ffce
SC		 6956 if (hpsa_allocate_sg_chain_blocks(h))
6957 goto clean4;
a08a8471
SC		 6958 init_waitqueue_head(&h->scan_wait_queue);
6959 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6960
6961 pci_set_drvdata(pdev, h);
9a41338e 6962 h->ndevices = 0;
316b221a 6963 h->hba_mode_enabled = 0;
9a41338e
SC		 6964 h->scsi_host = NULL;
6965 spin_lock_init(&h->devlock);
64670ac8
SC		 6966 hpsa_put_ctlr_into_performant_mode(h);
6967
6968 /* At this point, the controller is ready to take commands.
6969 * Now, if reset_devices and the hard reset didn't work, try
6970 * the soft reset and see if that works.
6971 */
6972 if (try_soft_reset) {
6973
6974 /* This is kind of gross. We may or may not get a completion
6975 * from the soft reset command, and if we do, then the value
6976 * from the fifo may or may not be valid. So, we wait 10 secs
6977 * after the reset throwing away any completions we get during
6978 * that time. Unregister the interrupt handler and register
6979 * fake ones to scoop up any residual completions.
6980 */
6981 spin_lock_irqsave(&h->lock, flags);
6982 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6983 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6984 free_irqs(h);
64670ac8
SC		 6985 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6986 hpsa_intx_discard_completions);
6987 if (rc) {
6988 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6989 "soft reset.\n");
6990 goto clean4;
6991 }
6992
6993 rc = hpsa_kdump_soft_reset(h);
6994 if (rc)
6995 /* Neither hard nor soft reset worked, we're hosed. */
6996 goto clean4;
6997
6998 dev_info(&h->pdev->dev, "Board READY.\n");
6999 dev_info(&h->pdev->dev,
7000 "Waiting for stale completions to drain.\n");
7001 h->access.set_intr_mask(h, HPSA_INTR_ON);
7002 msleep(10000);
7003 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7004
7005 rc = controller_reset_failed(h->cfgtable);
7006 if (rc)
7007 dev_info(&h->pdev->dev,
7008 "Soft reset appears to have failed.\n");
7009
7010 /* since the controller's reset, we have to go back and re-init
7011 * everything. Easiest to just forget what we've done and do it
7012 * all over again.
7013 */
7014 hpsa_undo_allocations_after_kdump_soft_reset(h);
7015 try_soft_reset = 0;
7016 if (rc)
7017 /* don't go to clean4, we already unallocated */
7018 return -ENODEV;
7019
7020 goto reinit_after_soft_reset;
7021 }
edd16368 7022
316b221a
SC		 7023 /* Enable Accelerated IO path at driver layer */
7024 h->acciopath_status = 1;
da0697bd 7025
e863d68e
ST		 7026 h->drv_req_rescan = 0;
7027
edd16368
SC		 7028 /* Turn the interrupts on so we can service requests */
7029 h->access.set_intr_mask(h, HPSA_INTR_ON);
7030
339b2b14 7031 hpsa_hba_inquiry(h);
edd16368 7032 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 7033
7034 /* Monitor the controller for firmware lockups */
7035 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7036 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7037 schedule_delayed_work(&h->monitor_ctlr_work,
7038 h->heartbeat_sample_interval);
88bf6d62 7039 return 0;
edd16368
SC		 7040
7041clean4:
33a2ffce 7042 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7043 hpsa_free_cmd_pool(h);
254f796b 7044 free_irqs(h);
edd16368
SC		 7045clean2:
7046clean1:
094963da
SC		 7047 if (h->lockup_detected)
7048 free_percpu(h->lockup_detected);
edd16368 7049 kfree(h);
ecd9aad4 7050 return rc;
edd16368
SC		 7051}
7052
7053static void hpsa_flush_cache(struct ctlr_info *h)
7054{
7055 char *flush_buf;
7056 struct CommandList *c;
702890e3
SC		 7057
7058 /* Don't bother trying to flush the cache if locked up */
094963da 7059 if (unlikely(lockup_detected(h)))
702890e3 7060 return;
edd16368
SC		 7061 flush_buf = kzalloc(4, GFP_KERNEL);
7062 if (!flush_buf)
7063 return;
7064
7065 c = cmd_special_alloc(h);
7066 if (!c) {
7067 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
7068 goto out_of_memory;
7069 }
a2dac136
SC		 7070 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7071 RAID_CTLR_LUNID, TYPE_CMD)) {
7072 goto out;
7073 }
edd16368
SC		 7074 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7075 if (c->err_info->CommandStatus != 0)
a2dac136 7076out:
edd16368
SC		 7077 dev_warn(&h->pdev->dev,
7078 "error flushing cache on controller\n");
7079 cmd_special_free(h, c);
7080out_of_memory:
7081 kfree(flush_buf);
7082}
7083
7084static void hpsa_shutdown(struct pci_dev *pdev)
7085{
7086 struct ctlr_info *h;
7087
7088 h = pci_get_drvdata(pdev);
7089 /* Turn board interrupts off and send the flush cache command
7090 * sendcmd will turn off interrupt, and send the flush...
7091 * To write all data in the battery backed cache to disks
7092 */
7093 hpsa_flush_cache(h);
7094 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7095 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7096}
7097
6f039790 7098static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7099{
7100 int i;
7101
7102 for (i = 0; i < h->ndevices; i++)
7103 kfree(h->dev[i]);
7104}
7105
6f039790 7106static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7107{
7108 struct ctlr_info *h;
8a98db73 7109 unsigned long flags;
edd16368
SC		 7110
7111 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7112 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7113 return;
7114 }
7115 h = pci_get_drvdata(pdev);
8a98db73
SC		 7116
7117 /* Get rid of any controller monitoring work items */
7118 spin_lock_irqsave(&h->lock, flags);
7119 h->remove_in_progress = 1;
7120 cancel_delayed_work(&h->monitor_ctlr_work);
7121 spin_unlock_irqrestore(&h->lock, flags);
7122
edd16368
SC		 7123 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7124 hpsa_shutdown(pdev);
7125 iounmap(h->vaddr);
204892e9
SC		 7126 iounmap(h->transtable);
7127 iounmap(h->cfgtable);
55e14e76 7128 hpsa_free_device_info(h);
33a2ffce 7129 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7130 pci_free_consistent(h->pdev,
7131 h->nr_cmds * sizeof(struct CommandList),
7132 h->cmd_pool, h->cmd_pool_dhandle);
7133 pci_free_consistent(h->pdev,
7134 h->nr_cmds * sizeof(struct ErrorInfo),
7135 h->errinfo_pool, h->errinfo_pool_dhandle);
072b0518 7136 hpsa_free_reply_queues(h);
edd16368 7137 kfree(h->cmd_pool_bits);
303932fd 7138 kfree(h->blockFetchTable);
e1f7de0c 7139 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7140 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7141 kfree(h->hba_inquiry_data);
f0bd0b68 7142 pci_disable_device(pdev);
edd16368 7143 pci_release_regions(pdev);
094963da 7144 free_percpu(h->lockup_detected);
edd16368
SC		 7145 kfree(h);
7146}
7147
7148static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7149 __attribute__((unused)) pm_message_t state)
7150{
7151 return -ENOSYS;
7152}
7153
7154static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7155{
7156 return -ENOSYS;
7157}
7158
7159static struct pci_driver hpsa_pci_driver = {
f79cfec6 7160 .name = HPSA,
edd16368 7161 .probe = hpsa_init_one,
6f039790 7162 .remove = hpsa_remove_one,
edd16368
SC		 7163 .id_table = hpsa_pci_device_id, /* id_table */
7164 .shutdown = hpsa_shutdown,
7165 .suspend = hpsa_suspend,
7166 .resume = hpsa_resume,
7167};
7168
303932fd
DB		 7169/* Fill in bucket_map[], given nsgs (the max number of
7170 * scatter gather elements supported) and bucket[],
7171 * which is an array of 8 integers. The bucket[] array
7172 * contains 8 different DMA transfer sizes (in 16
7173 * byte increments) which the controller uses to fetch
7174 * commands. This function fills in bucket_map[], which
7175 * maps a given number of scatter gather elements to one of
7176 * the 8 DMA transfer sizes. The point of it is to allow the
7177 * controller to only do as much DMA as needed to fetch the
7178 * command, with the DMA transfer size encoded in the lower
7179 * bits of the command address.
7180 */
7181static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7182 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7183{
7184 int i, j, b, size;
7185
303932fd
DB		 7186 /* Note, bucket_map must have nsgs+1 entries. */
7187 for (i = 0; i <= nsgs; i++) {
7188 /* Compute size of a command with i SG entries */
e1f7de0c 7189 size = i + min_blocks;
303932fd
DB		 7190 b = num_buckets; /* Assume the biggest bucket */
7191 /* Find the bucket that is just big enough */
e1f7de0c 7192 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7193 if (bucket[j] >= size) {
7194 b = j;
7195 break;
7196 }
7197 }
7198 /* for a command with i SG entries, use bucket b. */
7199 bucket_map[i] = b;
7200 }
7201}
7202
e1f7de0c 7203static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7204{
6c311b57
SC		 7205 int i;
7206 unsigned long register_value;
e1f7de0c
MG		 7207 unsigned long transMethod = CFGTBL_Trans_Performant |
7208 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7209 CFGTBL_Trans_enable_directed_msix |
7210 (trans_support & (CFGTBL_Trans_io_accel1 |
7211 CFGTBL_Trans_io_accel2));
e1f7de0c 7212 struct access_method access = SA5_performant_access;
def342bd
SC		 7213
7214 /* This is a bit complicated. There are 8 registers on
7215 * the controller which we write to to tell it 8 different
7216 * sizes of commands which there may be. It's a way of
7217 * reducing the DMA done to fetch each command. Encoded into
7218 * each command's tag are 3 bits which communicate to the controller
7219 * which of the eight sizes that command fits within. The size of
7220 * each command depends on how many scatter gather entries there are.
7221 * Each SG entry requires 16 bytes. The eight registers are programmed
7222 * with the number of 16-byte blocks a command of that size requires.
7223 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7224 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7225 * blocks. Note, this only extends to the SG entries contained
7226 * within the command block, and does not extend to chained blocks
7227 * of SG elements. bft[] contains the eight values we write to
7228 * the registers. They are not evenly distributed, but have more
7229 * sizes for small commands, and fewer sizes for larger commands.
7230 */
d66ae08b 7231 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7232#define MIN_IOACCEL2_BFT_ENTRY 5
7233#define HPSA_IOACCEL2_HEADER_SZ 4
7234 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7235 13, 14, 15, 16, 17, 18, 19,
7236 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7237 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7238 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7239 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7240 16 * MIN_IOACCEL2_BFT_ENTRY);
7241 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7242 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7243 /* 5 = 1 s/g entry or 4k
7244 * 6 = 2 s/g entry or 8k
7245 * 8 = 4 s/g entry or 16k
7246 * 10 = 6 s/g entry or 24k
7247 */
303932fd 7248
b3a52e79
SC		 7249 /* If the controller supports either ioaccel method then
7250 * we can also use the RAID stack submit path that does not
7251 * perform the superfluous readl() after each command submission.
7252 */
7253 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7254 access = SA5_performant_access_no_read;
7255
303932fd 7256 /* Controller spec: zero out this buffer. */
072b0518
SC		 7257 for (i = 0; i < h->nreply_queues; i++)
7258 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7259
d66ae08b
SC		 7260 bft[7] = SG_ENTRIES_IN_CMD + 4;
7261 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7262 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7263 for (i = 0; i < 8; i++)
7264 writel(bft[i], &h->transtable->BlockFetch[i]);
7265
7266 /* size of controller ring buffer */
7267 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7268 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7269 writel(0, &h->transtable->RepQCtrAddrLow32);
7270 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7271
7272 for (i = 0; i < h->nreply_queues; i++) {
7273 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7274 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7275 &h->transtable->RepQAddr[i].lower);
7276 }
7277
b9af4937 7278 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7279 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7280 /*
7281 * enable outbound interrupt coalescing in accelerator mode;
7282 */
7283 if (trans_support & CFGTBL_Trans_io_accel1) {
7284 access = SA5_ioaccel_mode1_access;
7285 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7286 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7287 } else {
7288 if (trans_support & CFGTBL_Trans_io_accel2) {
7289 access = SA5_ioaccel_mode2_access;
7290 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7291 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7292 }
e1f7de0c 7293 }
303932fd 7294 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7295 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7296 register_value = readl(&(h->cfgtable->TransportActive));
7297 if (!(register_value & CFGTBL_Trans_Performant)) {
7298 dev_warn(&h->pdev->dev, "unable to get board into"
7299 " performant mode\n");
7300 return;
7301 }
960a30e7 7302 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7303 h->access = access;
7304 h->transMethod = transMethod;
7305
b9af4937
SC		 7306 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7307 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7308 return;
7309
b9af4937
SC		 7310 if (trans_support & CFGTBL_Trans_io_accel1) {
7311 /* Set up I/O accelerator mode */
7312 for (i = 0; i < h->nreply_queues; i++) {
7313 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7314 h->reply_queue[i].current_entry =
7315 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7316 }
7317 bft[7] = h->ioaccel_maxsg + 8;
7318 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7319 h->ioaccel1_blockFetchTable);
e1f7de0c 7320
b9af4937 7321 /* initialize all reply queue entries to unused */
072b0518
SC		 7322 for (i = 0; i < h->nreply_queues; i++)
7323 memset(h->reply_queue[i].head,
7324 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7325 h->reply_queue_size);
e1f7de0c 7326
b9af4937
SC		 7327 /* set all the constant fields in the accelerator command
7328 * frames once at init time to save CPU cycles later.
7329 */
7330 for (i = 0; i < h->nr_cmds; i++) {
7331 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7332
7333 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7334 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7335 (i * sizeof(struct ErrorInfo)));
7336 cp->err_info_len = sizeof(struct ErrorInfo);
7337 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7338 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7339 cp->timeout_sec = 0;
7340 cp->ReplyQueue = 0;
50a0decf
SC		 7341 cp->tag =
7342 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT) |
7343 DIRECT_LOOKUP_BIT);
7344 cp->host_addr =
7345 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7346 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7347 }
7348 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7349 u64 cfg_offset, cfg_base_addr_index;
7350 u32 bft2_offset, cfg_base_addr;
7351 int rc;
7352
7353 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7354 &cfg_base_addr_index, &cfg_offset);
7355 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7356 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7357 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7358 4, h->ioaccel2_blockFetchTable);
7359 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7360 BUILD_BUG_ON(offsetof(struct CfgTable,
7361 io_accel_request_size_offset) != 0xb8);
7362 h->ioaccel2_bft2_regs =
7363 remap_pci_mem(pci_resource_start(h->pdev,
7364 cfg_base_addr_index) +
7365 cfg_offset + bft2_offset,
7366 ARRAY_SIZE(bft2) *
7367 sizeof(*h->ioaccel2_bft2_regs));
7368 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7369 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7370 }
b9af4937
SC		 7371 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7372 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7373}
7374
7375static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7376{
283b4a9b
SC		 7377 h->ioaccel_maxsg =
7378 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7379 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7380 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7381
e1f7de0c
MG		 7382 /* Command structures must be aligned on a 128-byte boundary
7383 * because the 7 lower bits of the address are used by the
7384 * hardware.
7385 */
e1f7de0c
MG		 7386 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7387 IOACCEL1_COMMANDLIST_ALIGNMENT);
7388 h->ioaccel_cmd_pool =
7389 pci_alloc_consistent(h->pdev,
7390 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7391 &(h->ioaccel_cmd_pool_dhandle));
7392
7393 h->ioaccel1_blockFetchTable =
283b4a9b 7394 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7395 sizeof(u32)), GFP_KERNEL);
7396
7397 if ((h->ioaccel_cmd_pool == NULL) ||
7398 (h->ioaccel1_blockFetchTable == NULL))
7399 goto clean_up;
7400
7401 memset(h->ioaccel_cmd_pool, 0,
7402 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7403 return 0;
7404
7405clean_up:
7406 if (h->ioaccel_cmd_pool)
7407 pci_free_consistent(h->pdev,
7408 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7409 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7410 kfree(h->ioaccel1_blockFetchTable);
7411 return 1;
6c311b57
SC		 7412}
7413
aca9012a
SC		 7414static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7415{
7416 /* Allocate ioaccel2 mode command blocks and block fetch table */
7417
7418 h->ioaccel_maxsg =
7419 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7420 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7421 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7422
aca9012a
SC		 7423 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7424 IOACCEL2_COMMANDLIST_ALIGNMENT);
7425 h->ioaccel2_cmd_pool =
7426 pci_alloc_consistent(h->pdev,
7427 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7428 &(h->ioaccel2_cmd_pool_dhandle));
7429
7430 h->ioaccel2_blockFetchTable =
7431 kmalloc(((h->ioaccel_maxsg + 1) *
7432 sizeof(u32)), GFP_KERNEL);
7433
7434 if ((h->ioaccel2_cmd_pool == NULL) ||
7435 (h->ioaccel2_blockFetchTable == NULL))
7436 goto clean_up;
7437
7438 memset(h->ioaccel2_cmd_pool, 0,
7439 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7440 return 0;
7441
7442clean_up:
7443 if (h->ioaccel2_cmd_pool)
7444 pci_free_consistent(h->pdev,
7445 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7446 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7447 kfree(h->ioaccel2_blockFetchTable);
7448 return 1;
7449}
7450
6f039790 7451static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7452{
7453 u32 trans_support;
e1f7de0c
MG		 7454 unsigned long transMethod = CFGTBL_Trans_Performant |
7455 CFGTBL_Trans_use_short_tags;
254f796b 7456 int i;
6c311b57 7457
02ec19c8
SC		 7458 if (hpsa_simple_mode)
7459 return;
7460
67c99a72 7461 trans_support = readl(&(h->cfgtable->TransportSupport));
7462 if (!(trans_support & PERFORMANT_MODE))
7463 return;
7464
e1f7de0c
MG		 7465 /* Check for I/O accelerator mode support */
7466 if (trans_support & CFGTBL_Trans_io_accel1) {
7467 transMethod |= CFGTBL_Trans_io_accel1 |
7468 CFGTBL_Trans_enable_directed_msix;
7469 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7470 goto clean_up;
aca9012a
SC		 7471 } else {
7472 if (trans_support & CFGTBL_Trans_io_accel2) {
7473 transMethod |= CFGTBL_Trans_io_accel2 |
7474 CFGTBL_Trans_enable_directed_msix;
7475 if (ioaccel2_alloc_cmds_and_bft(h))
7476 goto clean_up;
7477 }
e1f7de0c
MG		 7478 }
7479
eee0f03a 7480 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7481 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7482 /* Performant mode ring buffer and supporting data structures */
072b0518 7483 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 7484
254f796b 7485 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 7486 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
7487 h->reply_queue_size,
7488 &(h->reply_queue[i].busaddr));
7489 if (!h->reply_queue[i].head)
7490 goto clean_up;
254f796b
MG		 7491 h->reply_queue[i].size = h->max_commands;
7492 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7493 h->reply_queue[i].current_entry = 0;
7494 }
7495
6c311b57 7496 /* Need a block fetch table for performant mode */
d66ae08b 7497 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 7498 sizeof(u32)), GFP_KERNEL);
072b0518 7499 if (!h->blockFetchTable)
6c311b57
SC		 7500 goto clean_up;
7501
e1f7de0c 7502 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7503 return;
7504
7505clean_up:
072b0518 7506 hpsa_free_reply_queues(h);
303932fd
DB		 7507 kfree(h->blockFetchTable);
7508}
7509
23100dd9 7510static int is_accelerated_cmd(struct CommandList *c)
76438d08 7511{
23100dd9
SC		 7512 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7513}
7514
7515static void hpsa_drain_accel_commands(struct ctlr_info *h)
7516{
7517 struct CommandList *c = NULL;
76438d08 7518 unsigned long flags;
23100dd9 7519 int accel_cmds_out;
76438d08
SC		 7520
7521 do { /* wait for all outstanding commands to drain out */
23100dd9 7522 accel_cmds_out = 0;
76438d08 7523 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7524 list_for_each_entry(c, &h->cmpQ, list)
7525 accel_cmds_out += is_accelerated_cmd(c);
7526 list_for_each_entry(c, &h->reqQ, list)
7527 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7528 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7529 if (accel_cmds_out <= 0)
76438d08
SC		 7530 break;
7531 msleep(100);
7532 } while (1);
7533}
7534
edd16368
SC		 7535/*
7536 * This is it. Register the PCI driver information for the cards we control
7537 * the OS will call our registered routines when it finds one of our cards.
7538 */
7539static int __init hpsa_init(void)
7540{
31468401 7541 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7542}
7543
7544static void __exit hpsa_cleanup(void)
7545{
7546 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7547}
7548
e1f7de0c
MG		 7549static void __attribute__((unused)) verify_offsets(void)
7550{
dd0e19f3
ST		 7551#define VERIFY_OFFSET(member, offset) \
7552 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7553
7554 VERIFY_OFFSET(structure_size, 0);
7555 VERIFY_OFFSET(volume_blk_size, 4);
7556 VERIFY_OFFSET(volume_blk_cnt, 8);
7557 VERIFY_OFFSET(phys_blk_shift, 16);
7558 VERIFY_OFFSET(parity_rotation_shift, 17);
7559 VERIFY_OFFSET(strip_size, 18);
7560 VERIFY_OFFSET(disk_starting_blk, 20);
7561 VERIFY_OFFSET(disk_blk_cnt, 28);
7562 VERIFY_OFFSET(data_disks_per_row, 36);
7563 VERIFY_OFFSET(metadata_disks_per_row, 38);
7564 VERIFY_OFFSET(row_cnt, 40);
7565 VERIFY_OFFSET(layout_map_count, 42);
7566 VERIFY_OFFSET(flags, 44);
7567 VERIFY_OFFSET(dekindex, 46);
7568 /* VERIFY_OFFSET(reserved, 48 */
7569 VERIFY_OFFSET(data, 64);
7570
7571#undef VERIFY_OFFSET
7572
b66cc250
MM		 7573#define VERIFY_OFFSET(member, offset) \
7574 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7575
7576 VERIFY_OFFSET(IU_type, 0);
7577 VERIFY_OFFSET(direction, 1);
7578 VERIFY_OFFSET(reply_queue, 2);
7579 /* VERIFY_OFFSET(reserved1, 3); */
7580 VERIFY_OFFSET(scsi_nexus, 4);
7581 VERIFY_OFFSET(Tag, 8);
7582 VERIFY_OFFSET(cdb, 16);
7583 VERIFY_OFFSET(cciss_lun, 32);
7584 VERIFY_OFFSET(data_len, 40);
7585 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7586 VERIFY_OFFSET(sg_count, 45);
7587 /* VERIFY_OFFSET(reserved3 */
7588 VERIFY_OFFSET(err_ptr, 48);
7589 VERIFY_OFFSET(err_len, 56);
7590 /* VERIFY_OFFSET(reserved4 */
7591 VERIFY_OFFSET(sg, 64);
7592
7593#undef VERIFY_OFFSET
7594
e1f7de0c
MG		 7595#define VERIFY_OFFSET(member, offset) \
7596 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7597
7598 VERIFY_OFFSET(dev_handle, 0x00);
7599 VERIFY_OFFSET(reserved1, 0x02);
7600 VERIFY_OFFSET(function, 0x03);
7601 VERIFY_OFFSET(reserved2, 0x04);
7602 VERIFY_OFFSET(err_info, 0x0C);
7603 VERIFY_OFFSET(reserved3, 0x10);
7604 VERIFY_OFFSET(err_info_len, 0x12);
7605 VERIFY_OFFSET(reserved4, 0x13);
7606 VERIFY_OFFSET(sgl_offset, 0x14);
7607 VERIFY_OFFSET(reserved5, 0x15);
7608 VERIFY_OFFSET(transfer_len, 0x1C);
7609 VERIFY_OFFSET(reserved6, 0x20);
7610 VERIFY_OFFSET(io_flags, 0x24);
7611 VERIFY_OFFSET(reserved7, 0x26);
7612 VERIFY_OFFSET(LUN, 0x34);
7613 VERIFY_OFFSET(control, 0x3C);
7614 VERIFY_OFFSET(CDB, 0x40);
7615 VERIFY_OFFSET(reserved8, 0x50);
7616 VERIFY_OFFSET(host_context_flags, 0x60);
7617 VERIFY_OFFSET(timeout_sec, 0x62);
7618 VERIFY_OFFSET(ReplyQueue, 0x64);
7619 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 7620 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 7621 VERIFY_OFFSET(host_addr, 0x70);
7622 VERIFY_OFFSET(CISS_LUN, 0x78);
7623 VERIFY_OFFSET(SG, 0x78 + 8);
7624#undef VERIFY_OFFSET
7625}
7626
edd16368
SC		 7627module_init(hpsa_init);
7628module_exit(hpsa_cleanup);
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