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hpsa: correct decode sense data
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
73153fe5 47#include <scsi/scsi_dbg.h>
edd16368
SC		 48#include <linux/cciss_ioctl.h>
49#include <linux/string.h>
50#include <linux/bitmap.h>
60063497 51#include <linux/atomic.h>
a0c12413 52#include <linux/jiffies.h>
42a91641 53#include <linux/percpu-defs.h>
094963da 54#include <linux/percpu.h>
2b08b3e9 55#include <asm/unaligned.h>
283b4a9b 56#include <asm/div64.h>
edd16368
SC		 57#include "hpsa_cmd.h"
58#include "hpsa.h"
59
60/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 61#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 62#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 63#define HPSA "hpsa"
edd16368 64
007e7aa9
RE		 65/* How long to wait for CISS doorbell communication */
66#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
67#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
68#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
69#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 70#define MAX_IOCTL_CONFIG_WAIT 1000
71
72/*define how many times we will try a command because of bus resets */
73#define MAX_CMD_RETRIES 3
74
75/* Embedded module documentation macros - see modules.h */
76MODULE_AUTHOR("Hewlett-Packard Company");
77MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
78 HPSA_DRIVER_VERSION);
79MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
80MODULE_VERSION(HPSA_DRIVER_VERSION);
81MODULE_LICENSE("GPL");
82
83static int hpsa_allow_any;
84module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
85MODULE_PARM_DESC(hpsa_allow_any,
86 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 87static int hpsa_simple_mode;
88module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
89MODULE_PARM_DESC(hpsa_simple_mode,
90 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 91
92/* define the PCI info for the cards we can control */
93static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
8e616a5e
SC		 135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
139 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 140 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 141 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 142 {0,}
143};
144
145MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
146
147/* board_id = Subsystem Device ID & Vendor ID
148 * product = Marketing Name for the board
149 * access = Address of the struct of function pointers
150 */
151static struct board_type products[] = {
edd16368
SC		 152 {0x3241103C, "Smart Array P212", &SA5_access},
153 {0x3243103C, "Smart Array P410", &SA5_access},
154 {0x3245103C, "Smart Array P410i", &SA5_access},
155 {0x3247103C, "Smart Array P411", &SA5_access},
156 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 157 {0x324A103C, "Smart Array P712m", &SA5_access},
158 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 159 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 160 {0x3350103C, "Smart Array P222", &SA5_access},
161 {0x3351103C, "Smart Array P420", &SA5_access},
162 {0x3352103C, "Smart Array P421", &SA5_access},
163 {0x3353103C, "Smart Array P822", &SA5_access},
164 {0x3354103C, "Smart Array P420i", &SA5_access},
165 {0x3355103C, "Smart Array P220i", &SA5_access},
166 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 167 {0x1921103C, "Smart Array P830i", &SA5_access},
168 {0x1922103C, "Smart Array P430", &SA5_access},
169 {0x1923103C, "Smart Array P431", &SA5_access},
170 {0x1924103C, "Smart Array P830", &SA5_access},
171 {0x1926103C, "Smart Array P731m", &SA5_access},
172 {0x1928103C, "Smart Array P230i", &SA5_access},
173 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 174 {0x21BD103C, "Smart Array P244br", &SA5_access},
175 {0x21BE103C, "Smart Array P741m", &SA5_access},
176 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
177 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 178 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 179 {0x21C2103C, "Smart Array P440", &SA5_access},
180 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 181 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 182 {0x21C5103C, "Smart Array P841", &SA5_access},
183 {0x21C6103C, "Smart HBA H244br", &SA5_access},
184 {0x21C7103C, "Smart HBA H240", &SA5_access},
185 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 186 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 187 {0x21CA103C, "Smart Array P246br", &SA5_access},
188 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 189 {0x21CC103C, "Smart Array", &SA5_access},
190 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 191 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 192 {0x05809005, "SmartHBA-SA", &SA5_access},
8e616a5e
SC		 193 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
194 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
195 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
196 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
197 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 198 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
199};
200
a58e7e53
WS		 201#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
202static const struct scsi_cmnd hpsa_cmd_busy;
203#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
204static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 205static int number_of_controllers;
206
10f66018
SC		 207static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
208static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 209static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 210
211#ifdef CONFIG_COMPAT
42a91641
DB		 212static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
213 void __user *arg);
edd16368
SC		 214#endif
215
216static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 217static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 218static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
219static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
220 struct scsi_cmnd *scmd);
a2dac136 221static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 222 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 223 int cmd_type);
2c143342 224static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 225#define VPD_PAGE (1 << 8)
edd16368 226
f281233d 227static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 228static void hpsa_scan_start(struct Scsi_Host *);
229static int hpsa_scan_finished(struct Scsi_Host *sh,
230 unsigned long elapsed_time);
7c0a0229 231static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 232
233static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 234static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 235static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 236static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 237static void hpsa_slave_destroy(struct scsi_device *sdev);
238
edd16368 239static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 240static int check_for_unit_attention(struct ctlr_info *h,
241 struct CommandList *c);
242static void check_ioctl_unit_attention(struct ctlr_info *h,
243 struct CommandList *c);
303932fd
DB		 244/* performant mode helper functions */
245static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 246 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 247static void hpsa_free_performant_mode(struct ctlr_info *h);
248static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 249static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 250static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
251 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
252 u64 *cfg_offset);
253static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
254 unsigned long *memory_bar);
255static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
256static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
257 int wait_for_ready);
75167d2c 258static inline void finish_cmd(struct CommandList *c);
c706a795 259static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 260#define BOARD_NOT_READY 0
261#define BOARD_READY 1
23100dd9 262static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 263static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 264static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
265 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 266 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 267static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 268static u32 lockup_detected(struct ctlr_info *h);
269static int detect_controller_lockup(struct ctlr_info *h);
edd16368 270
edd16368
SC		 271static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
272{
273 unsigned long *priv = shost_priv(sdev->host);
274 return (struct ctlr_info *) *priv;
275}
276
a23513e8
SC		 277static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
278{
279 unsigned long *priv = shost_priv(sh);
280 return (struct ctlr_info *) *priv;
281}
282
a58e7e53
WS		 283static inline bool hpsa_is_cmd_idle(struct CommandList *c)
284{
285 return c->scsi_cmd == SCSI_CMD_IDLE;
286}
287
d604f533
WS		 288static inline bool hpsa_is_pending_event(struct CommandList *c)
289{
290 return c->abort_pending || c->reset_pending;
291}
292
9437ac43
SC		 293/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
294static void decode_sense_data(const u8 *sense_data, int sense_data_len,
295 u8 *sense_key, u8 *asc, u8 *ascq)
296{
297 struct scsi_sense_hdr sshdr;
298 bool rc;
299
300 *sense_key = -1;
301 *asc = -1;
302 *ascq = -1;
303
304 if (sense_data_len < 1)
305 return;
306
307 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
308 if (rc) {
309 *sense_key = sshdr.sense_key;
310 *asc = sshdr.asc;
311 *ascq = sshdr.ascq;
312 }
313}
314
edd16368
SC		 315static int check_for_unit_attention(struct ctlr_info *h,
316 struct CommandList *c)
317{
9437ac43
SC		 318 u8 sense_key, asc, ascq;
319 int sense_len;
320
321 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
322 sense_len = sizeof(c->err_info->SenseInfo);
323 else
324 sense_len = c->err_info->SenseLen;
325
326 decode_sense_data(c->err_info->SenseInfo, sense_len,
327 &sense_key, &asc, &ascq);
81c27557 328 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 329 return 0;
330
9437ac43 331 switch (asc) {
edd16368 332 case STATE_CHANGED:
9437ac43 333 dev_warn(&h->pdev->dev,
2946e82b
RE		 334 "%s: a state change detected, command retried\n",
335 h->devname);
edd16368
SC		 336 break;
337 case LUN_FAILED:
7f73695a 338 dev_warn(&h->pdev->dev,
2946e82b 339 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 340 break;
341 case REPORT_LUNS_CHANGED:
7f73695a 342 dev_warn(&h->pdev->dev,
2946e82b 343 "%s: report LUN data changed\n", h->devname);
edd16368 344 /*
4f4eb9f1
ST		 345 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
346 * target (array) devices.
edd16368
SC		 347 */
348 break;
349 case POWER_OR_RESET:
2946e82b
RE		 350 dev_warn(&h->pdev->dev,
351 "%s: a power on or device reset detected\n",
352 h->devname);
edd16368
SC		 353 break;
354 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 355 dev_warn(&h->pdev->dev,
356 "%s: unit attention cleared by another initiator\n",
357 h->devname);
edd16368
SC		 358 break;
359 default:
2946e82b
RE		 360 dev_warn(&h->pdev->dev,
361 "%s: unknown unit attention detected\n",
362 h->devname);
edd16368
SC		 363 break;
364 }
365 return 1;
366}
367
852af20a
MB		 368static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
369{
370 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
371 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
372 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
373 return 0;
374 dev_warn(&h->pdev->dev, HPSA "device busy");
375 return 1;
376}
377
e985c58f
SC		 378static u32 lockup_detected(struct ctlr_info *h);
379static ssize_t host_show_lockup_detected(struct device *dev,
380 struct device_attribute *attr, char *buf)
381{
382 int ld;
383 struct ctlr_info *h;
384 struct Scsi_Host *shost = class_to_shost(dev);
385
386 h = shost_to_hba(shost);
387 ld = lockup_detected(h);
388
389 return sprintf(buf, "ld=%d\n", ld);
390}
391
da0697bd
ST		 392static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
393 struct device_attribute *attr,
394 const char *buf, size_t count)
395{
396 int status, len;
397 struct ctlr_info *h;
398 struct Scsi_Host *shost = class_to_shost(dev);
399 char tmpbuf[10];
400
401 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
402 return -EACCES;
403 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
404 strncpy(tmpbuf, buf, len);
405 tmpbuf[len] = '\0';
406 if (sscanf(tmpbuf, "%d", &status) != 1)
407 return -EINVAL;
408 h = shost_to_hba(shost);
409 h->acciopath_status = !!status;
410 dev_warn(&h->pdev->dev,
411 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
412 h->acciopath_status ? "enabled" : "disabled");
413 return count;
414}
415
2ba8bfc8
SC		 416static ssize_t host_store_raid_offload_debug(struct device *dev,
417 struct device_attribute *attr,
418 const char *buf, size_t count)
419{
420 int debug_level, len;
421 struct ctlr_info *h;
422 struct Scsi_Host *shost = class_to_shost(dev);
423 char tmpbuf[10];
424
425 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
426 return -EACCES;
427 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
428 strncpy(tmpbuf, buf, len);
429 tmpbuf[len] = '\0';
430 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
431 return -EINVAL;
432 if (debug_level < 0)
433 debug_level = 0;
434 h = shost_to_hba(shost);
435 h->raid_offload_debug = debug_level;
436 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
437 h->raid_offload_debug);
438 return count;
439}
440
edd16368
SC		 441static ssize_t host_store_rescan(struct device *dev,
442 struct device_attribute *attr,
443 const char *buf, size_t count)
444{
445 struct ctlr_info *h;
446 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 447 h = shost_to_hba(shost);
31468401 448 hpsa_scan_start(h->scsi_host);
edd16368
SC		 449 return count;
450}
451
d28ce020
SC		 452static ssize_t host_show_firmware_revision(struct device *dev,
453 struct device_attribute *attr, char *buf)
454{
455 struct ctlr_info *h;
456 struct Scsi_Host *shost = class_to_shost(dev);
457 unsigned char *fwrev;
458
459 h = shost_to_hba(shost);
460 if (!h->hba_inquiry_data)
461 return 0;
462 fwrev = &h->hba_inquiry_data[32];
463 return snprintf(buf, 20, "%c%c%c%c\n",
464 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
465}
466
94a13649
SC		 467static ssize_t host_show_commands_outstanding(struct device *dev,
468 struct device_attribute *attr, char *buf)
469{
470 struct Scsi_Host *shost = class_to_shost(dev);
471 struct ctlr_info *h = shost_to_hba(shost);
472
0cbf768e
SC		 473 return snprintf(buf, 20, "%d\n",
474 atomic_read(&h->commands_outstanding));
94a13649
SC		 475}
476
745a7a25
SC		 477static ssize_t host_show_transport_mode(struct device *dev,
478 struct device_attribute *attr, char *buf)
479{
480 struct ctlr_info *h;
481 struct Scsi_Host *shost = class_to_shost(dev);
482
483 h = shost_to_hba(shost);
484 return snprintf(buf, 20, "%s\n",
960a30e7 485 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 486 "performant" : "simple");
487}
488
da0697bd
ST		 489static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
490 struct device_attribute *attr, char *buf)
491{
492 struct ctlr_info *h;
493 struct Scsi_Host *shost = class_to_shost(dev);
494
495 h = shost_to_hba(shost);
496 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
497 (h->acciopath_status == 1) ? "enabled" : "disabled");
498}
499
46380786 500/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 501static u32 unresettable_controller[] = {
502 0x324a103C, /* Smart Array P712m */
9b5c48c2 503 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 504 0x3223103C, /* Smart Array P800 */
505 0x3234103C, /* Smart Array P400 */
506 0x3235103C, /* Smart Array P400i */
507 0x3211103C, /* Smart Array E200i */
508 0x3212103C, /* Smart Array E200 */
509 0x3213103C, /* Smart Array E200i */
510 0x3214103C, /* Smart Array E200i */
511 0x3215103C, /* Smart Array E200i */
512 0x3237103C, /* Smart Array E500 */
513 0x323D103C, /* Smart Array P700m */
7af0abbc 514 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 515 0x409C0E11, /* Smart Array 6400 */
516 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 517 0x40700E11, /* Smart Array 5300 */
518 0x40820E11, /* Smart Array 532 */
519 0x40830E11, /* Smart Array 5312 */
520 0x409A0E11, /* Smart Array 641 */
521 0x409B0E11, /* Smart Array 642 */
522 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 523};
524
46380786
SC		 525/* List of controllers which cannot even be soft reset */
526static u32 soft_unresettable_controller[] = {
7af0abbc 527 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 528 0x40700E11, /* Smart Array 5300 */
529 0x40820E11, /* Smart Array 532 */
530 0x40830E11, /* Smart Array 5312 */
531 0x409A0E11, /* Smart Array 641 */
532 0x409B0E11, /* Smart Array 642 */
533 0x40910E11, /* Smart Array 6i */
46380786
SC		 534 /* Exclude 640x boards. These are two pci devices in one slot
535 * which share a battery backed cache module. One controls the
536 * cache, the other accesses the cache through the one that controls
537 * it. If we reset the one controlling the cache, the other will
538 * likely not be happy. Just forbid resetting this conjoined mess.
539 * The 640x isn't really supported by hpsa anyway.
540 */
541 0x409C0E11, /* Smart Array 6400 */
542 0x409D0E11, /* Smart Array 6400 EM */
543};
544
9b5c48c2
SC		 545static u32 needs_abort_tags_swizzled[] = {
546 0x323D103C, /* Smart Array P700m */
547 0x324a103C, /* Smart Array P712m */
548 0x324b103C, /* SmartArray P711m */
549};
550
551static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 552{
553 int i;
554
9b5c48c2
SC		 555 for (i = 0; i < nelems; i++)
556 if (a[i] == board_id)
557 return 1;
558 return 0;
46380786
SC		 559}
560
9b5c48c2 561static int ctlr_is_hard_resettable(u32 board_id)
46380786 562{
9b5c48c2
SC		 563 return !board_id_in_array(unresettable_controller,
564 ARRAY_SIZE(unresettable_controller), board_id);
565}
46380786 566
9b5c48c2
SC		 567static int ctlr_is_soft_resettable(u32 board_id)
568{
569 return !board_id_in_array(soft_unresettable_controller,
570 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 571}
572
46380786
SC		 573static int ctlr_is_resettable(u32 board_id)
574{
575 return ctlr_is_hard_resettable(board_id) ||
576 ctlr_is_soft_resettable(board_id);
577}
578
9b5c48c2
SC		 579static int ctlr_needs_abort_tags_swizzled(u32 board_id)
580{
581 return board_id_in_array(needs_abort_tags_swizzled,
582 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
583}
584
941b1cda
SC		 585static ssize_t host_show_resettable(struct device *dev,
586 struct device_attribute *attr, char *buf)
587{
588 struct ctlr_info *h;
589 struct Scsi_Host *shost = class_to_shost(dev);
590
591 h = shost_to_hba(shost);
46380786 592 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 593}
594
edd16368
SC		 595static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
596{
597 return (scsi3addr[3] & 0xC0) == 0x40;
598}
599
f2ef0ce7
RE		 600static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
601 "1(+0)ADM", "UNKNOWN"
edd16368 602};
6b80b18f
ST		 603#define HPSA_RAID_0 0
604#define HPSA_RAID_4 1
605#define HPSA_RAID_1 2 /* also used for RAID 10 */
606#define HPSA_RAID_5 3 /* also used for RAID 50 */
607#define HPSA_RAID_51 4
608#define HPSA_RAID_6 5 /* also used for RAID 60 */
609#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 610#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
611
612static ssize_t raid_level_show(struct device *dev,
613 struct device_attribute *attr, char *buf)
614{
615 ssize_t l = 0;
82a72c0a 616 unsigned char rlevel;
edd16368
SC		 617 struct ctlr_info *h;
618 struct scsi_device *sdev;
619 struct hpsa_scsi_dev_t *hdev;
620 unsigned long flags;
621
622 sdev = to_scsi_device(dev);
623 h = sdev_to_hba(sdev);
624 spin_lock_irqsave(&h->lock, flags);
625 hdev = sdev->hostdata;
626 if (!hdev) {
627 spin_unlock_irqrestore(&h->lock, flags);
628 return -ENODEV;
629 }
630
631 /* Is this even a logical drive? */
632 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
633 spin_unlock_irqrestore(&h->lock, flags);
634 l = snprintf(buf, PAGE_SIZE, "N/A\n");
635 return l;
636 }
637
638 rlevel = hdev->raid_level;
639 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 640 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 641 rlevel = RAID_UNKNOWN;
642 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
643 return l;
644}
645
646static ssize_t lunid_show(struct device *dev,
647 struct device_attribute *attr, char *buf)
648{
649 struct ctlr_info *h;
650 struct scsi_device *sdev;
651 struct hpsa_scsi_dev_t *hdev;
652 unsigned long flags;
653 unsigned char lunid[8];
654
655 sdev = to_scsi_device(dev);
656 h = sdev_to_hba(sdev);
657 spin_lock_irqsave(&h->lock, flags);
658 hdev = sdev->hostdata;
659 if (!hdev) {
660 spin_unlock_irqrestore(&h->lock, flags);
661 return -ENODEV;
662 }
663 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
664 spin_unlock_irqrestore(&h->lock, flags);
665 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
666 lunid[0], lunid[1], lunid[2], lunid[3],
667 lunid[4], lunid[5], lunid[6], lunid[7]);
668}
669
670static ssize_t unique_id_show(struct device *dev,
671 struct device_attribute *attr, char *buf)
672{
673 struct ctlr_info *h;
674 struct scsi_device *sdev;
675 struct hpsa_scsi_dev_t *hdev;
676 unsigned long flags;
677 unsigned char sn[16];
678
679 sdev = to_scsi_device(dev);
680 h = sdev_to_hba(sdev);
681 spin_lock_irqsave(&h->lock, flags);
682 hdev = sdev->hostdata;
683 if (!hdev) {
684 spin_unlock_irqrestore(&h->lock, flags);
685 return -ENODEV;
686 }
687 memcpy(sn, hdev->device_id, sizeof(sn));
688 spin_unlock_irqrestore(&h->lock, flags);
689 return snprintf(buf, 16 * 2 + 2,
690 "%02X%02X%02X%02X%02X%02X%02X%02X"
691 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
692 sn[0], sn[1], sn[2], sn[3],
693 sn[4], sn[5], sn[6], sn[7],
694 sn[8], sn[9], sn[10], sn[11],
695 sn[12], sn[13], sn[14], sn[15]);
696}
697
c1988684
ST		 698static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
699 struct device_attribute *attr, char *buf)
700{
701 struct ctlr_info *h;
702 struct scsi_device *sdev;
703 struct hpsa_scsi_dev_t *hdev;
704 unsigned long flags;
705 int offload_enabled;
706
707 sdev = to_scsi_device(dev);
708 h = sdev_to_hba(sdev);
709 spin_lock_irqsave(&h->lock, flags);
710 hdev = sdev->hostdata;
711 if (!hdev) {
712 spin_unlock_irqrestore(&h->lock, flags);
713 return -ENODEV;
714 }
715 offload_enabled = hdev->offload_enabled;
716 spin_unlock_irqrestore(&h->lock, flags);
717 return snprintf(buf, 20, "%d\n", offload_enabled);
718}
719
3f5eac3a
SC		 720static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
721static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
722static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
723static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 724static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
725 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 726static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
727 host_show_hp_ssd_smart_path_status,
728 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 729static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
730 host_store_raid_offload_debug);
3f5eac3a
SC		 731static DEVICE_ATTR(firmware_revision, S_IRUGO,
732 host_show_firmware_revision, NULL);
733static DEVICE_ATTR(commands_outstanding, S_IRUGO,
734 host_show_commands_outstanding, NULL);
735static DEVICE_ATTR(transport_mode, S_IRUGO,
736 host_show_transport_mode, NULL);
941b1cda
SC		 737static DEVICE_ATTR(resettable, S_IRUGO,
738 host_show_resettable, NULL);
e985c58f
SC		 739static DEVICE_ATTR(lockup_detected, S_IRUGO,
740 host_show_lockup_detected, NULL);
3f5eac3a
SC		 741
742static struct device_attribute *hpsa_sdev_attrs[] = {
743 &dev_attr_raid_level,
744 &dev_attr_lunid,
745 &dev_attr_unique_id,
c1988684 746 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 747 &dev_attr_lockup_detected,
3f5eac3a
SC		 748 NULL,
749};
750
751static struct device_attribute *hpsa_shost_attrs[] = {
752 &dev_attr_rescan,
753 &dev_attr_firmware_revision,
754 &dev_attr_commands_outstanding,
755 &dev_attr_transport_mode,
941b1cda 756 &dev_attr_resettable,
da0697bd 757 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 758 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 759 NULL,
760};
761
41ce4c35
SC		 762#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
763 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
764
3f5eac3a
SC		 765static struct scsi_host_template hpsa_driver_template = {
766 .module = THIS_MODULE,
f79cfec6
SC		 767 .name = HPSA,
768 .proc_name = HPSA,
3f5eac3a
SC		 769 .queuecommand = hpsa_scsi_queue_command,
770 .scan_start = hpsa_scan_start,
771 .scan_finished = hpsa_scan_finished,
7c0a0229 772 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 773 .this_id = -1,
774 .use_clustering = ENABLE_CLUSTERING,
75167d2c 775 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 776 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
777 .ioctl = hpsa_ioctl,
778 .slave_alloc = hpsa_slave_alloc,
41ce4c35 779 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 780 .slave_destroy = hpsa_slave_destroy,
781#ifdef CONFIG_COMPAT
782 .compat_ioctl = hpsa_compat_ioctl,
783#endif
784 .sdev_attrs = hpsa_sdev_attrs,
785 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 786 .max_sectors = 8192,
54b2b50c 787 .no_write_same = 1,
3f5eac3a
SC		 788};
789
254f796b 790static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 791{
792 u32 a;
072b0518 793 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 794
e1f7de0c
MG		 795 if (h->transMethod & CFGTBL_Trans_io_accel1)
796 return h->access.command_completed(h, q);
797
3f5eac3a 798 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 799 return h->access.command_completed(h, q);
3f5eac3a 800
254f796b
MG		 801 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
802 a = rq->head[rq->current_entry];
803 rq->current_entry++;
0cbf768e 804 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 805 } else {
806 a = FIFO_EMPTY;
807 }
808 /* Check for wraparound */
254f796b
MG		 809 if (rq->current_entry == h->max_commands) {
810 rq->current_entry = 0;
811 rq->wraparound ^= 1;
3f5eac3a
SC		 812 }
813 return a;
814}
815
c349775e
ST		 816/*
817 * There are some special bits in the bus address of the
818 * command that we have to set for the controller to know
819 * how to process the command:
820 *
821 * Normal performant mode:
822 * bit 0: 1 means performant mode, 0 means simple mode.
823 * bits 1-3 = block fetch table entry
824 * bits 4-6 = command type (== 0)
825 *
826 * ioaccel1 mode:
827 * bit 0 = "performant mode" bit.
828 * bits 1-3 = block fetch table entry
829 * bits 4-6 = command type (== 110)
830 * (command type is needed because ioaccel1 mode
831 * commands are submitted through the same register as normal
832 * mode commands, so this is how the controller knows whether
833 * the command is normal mode or ioaccel1 mode.)
834 *
835 * ioaccel2 mode:
836 * bit 0 = "performant mode" bit.
837 * bits 1-4 = block fetch table entry (note extra bit)
838 * bits 4-6 = not needed, because ioaccel2 mode has
839 * a separate special register for submitting commands.
840 */
841
25163bd5
WS		 842/*
843 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 844 * set bit 0 for pull model, bits 3-1 for block fetch
845 * register number
846 */
25163bd5
WS		 847#define DEFAULT_REPLY_QUEUE (-1)
848static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
849 int reply_queue)
3f5eac3a 850{
254f796b 851 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 852 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 853 if (unlikely(!h->msix_vector))
854 return;
855 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 856 c->Header.ReplyQueue =
804a5cb5 857 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 858 else
859 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 860 }
3f5eac3a
SC		 861}
862
c349775e 863static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 864 struct CommandList *c,
865 int reply_queue)
c349775e
ST		 866{
867 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
868
25163bd5
WS		 869 /*
870 * Tell the controller to post the reply to the queue for this
c349775e
ST		 871 * processor. This seems to give the best I/O throughput.
872 */
25163bd5
WS		 873 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
874 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
875 else
876 cp->ReplyQueue = reply_queue % h->nreply_queues;
877 /*
878 * Set the bits in the address sent down to include:
c349775e
ST		 879 * - performant mode bit (bit 0)
880 * - pull count (bits 1-3)
881 * - command type (bits 4-6)
882 */
883 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
884 IOACCEL1_BUSADDR_CMDTYPE;
885}
886
8be986cc
SC		 887static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
888 struct CommandList *c,
889 int reply_queue)
890{
891 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
892 &h->ioaccel2_cmd_pool[c->cmdindex];
893
894 /* Tell the controller to post the reply to the queue for this
895 * processor. This seems to give the best I/O throughput.
896 */
897 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
898 cp->reply_queue = smp_processor_id() % h->nreply_queues;
899 else
900 cp->reply_queue = reply_queue % h->nreply_queues;
901 /* Set the bits in the address sent down to include:
902 * - performant mode bit not used in ioaccel mode 2
903 * - pull count (bits 0-3)
904 * - command type isn't needed for ioaccel2
905 */
906 c->busaddr |= h->ioaccel2_blockFetchTable[0];
907}
908
c349775e 909static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 910 struct CommandList *c,
911 int reply_queue)
c349775e
ST		 912{
913 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
914
25163bd5
WS		 915 /*
916 * Tell the controller to post the reply to the queue for this
c349775e
ST		 917 * processor. This seems to give the best I/O throughput.
918 */
25163bd5
WS		 919 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
920 cp->reply_queue = smp_processor_id() % h->nreply_queues;
921 else
922 cp->reply_queue = reply_queue % h->nreply_queues;
923 /*
924 * Set the bits in the address sent down to include:
c349775e
ST		 925 * - performant mode bit not used in ioaccel mode 2
926 * - pull count (bits 0-3)
927 * - command type isn't needed for ioaccel2
928 */
929 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
930}
931
e85c5974
SC		 932static int is_firmware_flash_cmd(u8 *cdb)
933{
934 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
935}
936
937/*
938 * During firmware flash, the heartbeat register may not update as frequently
939 * as it should. So we dial down lockup detection during firmware flash. and
940 * dial it back up when firmware flash completes.
941 */
942#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
943#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
944static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
945 struct CommandList *c)
946{
947 if (!is_firmware_flash_cmd(c->Request.CDB))
948 return;
949 atomic_inc(&h->firmware_flash_in_progress);
950 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
951}
952
953static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
954 struct CommandList *c)
955{
956 if (is_firmware_flash_cmd(c->Request.CDB) &&
957 atomic_dec_and_test(&h->firmware_flash_in_progress))
958 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
959}
960
25163bd5
WS		 961static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
962 struct CommandList *c, int reply_queue)
3f5eac3a 963{
c05e8866
SC		 964 dial_down_lockup_detection_during_fw_flash(h, c);
965 atomic_inc(&h->commands_outstanding);
c349775e
ST		 966 switch (c->cmd_type) {
967 case CMD_IOACCEL1:
25163bd5 968 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 969 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 970 break;
971 case CMD_IOACCEL2:
25163bd5 972 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 973 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 974 break;
8be986cc
SC		 975 case IOACCEL2_TMF:
976 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
977 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
978 break;
c349775e 979 default:
25163bd5 980 set_performant_mode(h, c, reply_queue);
c05e8866 981 h->access.submit_command(h, c);
c349775e 982 }
3f5eac3a
SC		 983}
984
a58e7e53 985static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 986{
d604f533 987 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 988 return finish_cmd(c);
989
25163bd5
WS		 990 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
991}
992
3f5eac3a
SC		 993static inline int is_hba_lunid(unsigned char scsi3addr[])
994{
995 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
996}
997
998static inline int is_scsi_rev_5(struct ctlr_info *h)
999{
1000 if (!h->hba_inquiry_data)
1001 return 0;
1002 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1003 return 1;
1004 return 0;
1005}
1006
edd16368
SC		 1007static int hpsa_find_target_lun(struct ctlr_info *h,
1008 unsigned char scsi3addr[], int bus, int *target, int *lun)
1009{
1010 /* finds an unused bus, target, lun for a new physical device
1011 * assumes h->devlock is held
1012 */
1013 int i, found = 0;
cfe5badc 1014 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1015
263d9401 1016 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1017
1018 for (i = 0; i < h->ndevices; i++) {
1019 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1020 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1021 }
1022
263d9401
AM		 1023 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1024 if (i < HPSA_MAX_DEVICES) {
1025 /* *bus = 1; */
1026 *target = i;
1027 *lun = 0;
1028 found = 1;
edd16368
SC		 1029 }
1030 return !found;
1031}
1032
0d96ef5f
WS		 1033static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1034 struct hpsa_scsi_dev_t *dev, char *description)
1035{
1036 dev_printk(level, &h->pdev->dev,
1037 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1038 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1039 description,
1040 scsi_device_type(dev->devtype),
1041 dev->vendor,
1042 dev->model,
1043 dev->raid_level > RAID_UNKNOWN ?
1044 "RAID-?" : raid_label[dev->raid_level],
1045 dev->offload_config ? '+' : '-',
1046 dev->offload_enabled ? '+' : '-',
1047 dev->expose_state);
1048}
1049
edd16368
SC		 1050/* Add an entry into h->dev[] array. */
1051static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1052 struct hpsa_scsi_dev_t *device,
1053 struct hpsa_scsi_dev_t *added[], int *nadded)
1054{
1055 /* assumes h->devlock is held */
1056 int n = h->ndevices;
1057 int i;
1058 unsigned char addr1[8], addr2[8];
1059 struct hpsa_scsi_dev_t *sd;
1060
cfe5badc 1061 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1062 dev_err(&h->pdev->dev, "too many devices, some will be "
1063 "inaccessible.\n");
1064 return -1;
1065 }
1066
1067 /* physical devices do not have lun or target assigned until now. */
1068 if (device->lun != -1)
1069 /* Logical device, lun is already assigned. */
1070 goto lun_assigned;
1071
1072 /* If this device a non-zero lun of a multi-lun device
1073 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1074 * unit no, zero otherwise.
edd16368
SC		 1075 */
1076 if (device->scsi3addr[4] == 0) {
1077 /* This is not a non-zero lun of a multi-lun device */
1078 if (hpsa_find_target_lun(h, device->scsi3addr,
1079 device->bus, &device->target, &device->lun) != 0)
1080 return -1;
1081 goto lun_assigned;
1082 }
1083
1084 /* This is a non-zero lun of a multi-lun device.
1085 * Search through our list and find the device which
1086 * has the same 8 byte LUN address, excepting byte 4.
1087 * Assign the same bus and target for this new LUN.
1088 * Use the logical unit number from the firmware.
1089 */
1090 memcpy(addr1, device->scsi3addr, 8);
1091 addr1[4] = 0;
1092 for (i = 0; i < n; i++) {
1093 sd = h->dev[i];
1094 memcpy(addr2, sd->scsi3addr, 8);
1095 addr2[4] = 0;
1096 /* differ only in byte 4? */
1097 if (memcmp(addr1, addr2, 8) == 0) {
1098 device->bus = sd->bus;
1099 device->target = sd->target;
1100 device->lun = device->scsi3addr[4];
1101 break;
1102 }
1103 }
1104 if (device->lun == -1) {
1105 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1106 " suspect firmware bug or unsupported hardware "
1107 "configuration.\n");
1108 return -1;
1109 }
1110
1111lun_assigned:
1112
1113 h->dev[n] = device;
1114 h->ndevices++;
1115 added[*nadded] = device;
1116 (*nadded)++;
0d96ef5f
WS		 1117 hpsa_show_dev_msg(KERN_INFO, h, device,
1118 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1119 device->offload_to_be_enabled = device->offload_enabled;
1120 device->offload_enabled = 0;
edd16368
SC		 1121 return 0;
1122}
1123
bd9244f7
ST		 1124/* Update an entry in h->dev[] array. */
1125static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1126 int entry, struct hpsa_scsi_dev_t *new_entry)
1127{
a473d86c 1128 int offload_enabled;
bd9244f7
ST		 1129 /* assumes h->devlock is held */
1130 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1131
1132 /* Raid level changed. */
1133 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1134
03383736
DB		 1135 /* Raid offload parameters changed. Careful about the ordering. */
1136 if (new_entry->offload_config && new_entry->offload_enabled) {
1137 /*
1138 * if drive is newly offload_enabled, we want to copy the
1139 * raid map data first. If previously offload_enabled and
1140 * offload_config were set, raid map data had better be
1141 * the same as it was before. if raid map data is changed
1142 * then it had better be the case that
1143 * h->dev[entry]->offload_enabled is currently 0.
1144 */
1145 h->dev[entry]->raid_map = new_entry->raid_map;
1146 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1147 }
a3144e0b
JH		 1148 if (new_entry->hba_ioaccel_enabled) {
1149 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1150 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1151 }
1152 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1153 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1154 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1155 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1156
41ce4c35
SC		 1157 /*
1158 * We can turn off ioaccel offload now, but need to delay turning
1159 * it on until we can update h->dev[entry]->phys_disk[], but we
1160 * can't do that until all the devices are updated.
1161 */
1162 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1163 if (!new_entry->offload_enabled)
1164 h->dev[entry]->offload_enabled = 0;
1165
a473d86c
RE		 1166 offload_enabled = h->dev[entry]->offload_enabled;
1167 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1168 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1169 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1170}
1171
2a8ccf31
SC		 1172/* Replace an entry from h->dev[] array. */
1173static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1174 int entry, struct hpsa_scsi_dev_t *new_entry,
1175 struct hpsa_scsi_dev_t *added[], int *nadded,
1176 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1177{
1178 /* assumes h->devlock is held */
cfe5badc 1179 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1180 removed[*nremoved] = h->dev[entry];
1181 (*nremoved)++;
01350d05
SC		 1182
1183 /*
1184 * New physical devices won't have target/lun assigned yet
1185 * so we need to preserve the values in the slot we are replacing.
1186 */
1187 if (new_entry->target == -1) {
1188 new_entry->target = h->dev[entry]->target;
1189 new_entry->lun = h->dev[entry]->lun;
1190 }
1191
2a8ccf31
SC		 1192 h->dev[entry] = new_entry;
1193 added[*nadded] = new_entry;
1194 (*nadded)++;
0d96ef5f 1195 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1196 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1197 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1198}
1199
edd16368
SC		 1200/* Remove an entry from h->dev[] array. */
1201static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1202 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1203{
1204 /* assumes h->devlock is held */
1205 int i;
1206 struct hpsa_scsi_dev_t *sd;
1207
cfe5badc 1208 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1209
1210 sd = h->dev[entry];
1211 removed[*nremoved] = h->dev[entry];
1212 (*nremoved)++;
1213
1214 for (i = entry; i < h->ndevices-1; i++)
1215 h->dev[i] = h->dev[i+1];
1216 h->ndevices--;
0d96ef5f 1217 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1218}
1219
1220#define SCSI3ADDR_EQ(a, b) ( \
1221 (a)[7] == (b)[7] && \
1222 (a)[6] == (b)[6] && \
1223 (a)[5] == (b)[5] && \
1224 (a)[4] == (b)[4] && \
1225 (a)[3] == (b)[3] && \
1226 (a)[2] == (b)[2] && \
1227 (a)[1] == (b)[1] && \
1228 (a)[0] == (b)[0])
1229
1230static void fixup_botched_add(struct ctlr_info *h,
1231 struct hpsa_scsi_dev_t *added)
1232{
1233 /* called when scsi_add_device fails in order to re-adjust
1234 * h->dev[] to match the mid layer's view.
1235 */
1236 unsigned long flags;
1237 int i, j;
1238
1239 spin_lock_irqsave(&h->lock, flags);
1240 for (i = 0; i < h->ndevices; i++) {
1241 if (h->dev[i] == added) {
1242 for (j = i; j < h->ndevices-1; j++)
1243 h->dev[j] = h->dev[j+1];
1244 h->ndevices--;
1245 break;
1246 }
1247 }
1248 spin_unlock_irqrestore(&h->lock, flags);
1249 kfree(added);
1250}
1251
1252static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1253 struct hpsa_scsi_dev_t *dev2)
1254{
edd16368
SC		 1255 /* we compare everything except lun and target as these
1256 * are not yet assigned. Compare parts likely
1257 * to differ first
1258 */
1259 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1260 sizeof(dev1->scsi3addr)) != 0)
1261 return 0;
1262 if (memcmp(dev1->device_id, dev2->device_id,
1263 sizeof(dev1->device_id)) != 0)
1264 return 0;
1265 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1266 return 0;
1267 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1268 return 0;
edd16368
SC		 1269 if (dev1->devtype != dev2->devtype)
1270 return 0;
edd16368
SC		 1271 if (dev1->bus != dev2->bus)
1272 return 0;
1273 return 1;
1274}
1275
bd9244f7
ST		 1276static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1277 struct hpsa_scsi_dev_t *dev2)
1278{
1279 /* Device attributes that can change, but don't mean
1280 * that the device is a different device, nor that the OS
1281 * needs to be told anything about the change.
1282 */
1283 if (dev1->raid_level != dev2->raid_level)
1284 return 1;
250fb125
SC		 1285 if (dev1->offload_config != dev2->offload_config)
1286 return 1;
1287 if (dev1->offload_enabled != dev2->offload_enabled)
1288 return 1;
03383736
DB		 1289 if (dev1->queue_depth != dev2->queue_depth)
1290 return 1;
bd9244f7
ST		 1291 return 0;
1292}
1293
edd16368
SC		 1294/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1295 * and return needle location in *index. If scsi3addr matches, but not
1296 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1297 * location in *index.
1298 * In the case of a minor device attribute change, such as RAID level, just
1299 * return DEVICE_UPDATED, along with the updated device's location in index.
1300 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1301 */
1302static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1303 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1304 int *index)
1305{
1306 int i;
1307#define DEVICE_NOT_FOUND 0
1308#define DEVICE_CHANGED 1
1309#define DEVICE_SAME 2
bd9244f7 1310#define DEVICE_UPDATED 3
edd16368 1311 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1312 if (haystack[i] == NULL) /* previously removed. */
1313 continue;
edd16368
SC		 1314 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1315 *index = i;
bd9244f7
ST		 1316 if (device_is_the_same(needle, haystack[i])) {
1317 if (device_updated(needle, haystack[i]))
1318 return DEVICE_UPDATED;
edd16368 1319 return DEVICE_SAME;
bd9244f7 1320 } else {
9846590e
SC		 1321 /* Keep offline devices offline */
1322 if (needle->volume_offline)
1323 return DEVICE_NOT_FOUND;
edd16368 1324 return DEVICE_CHANGED;
bd9244f7 1325 }
edd16368
SC		 1326 }
1327 }
1328 *index = -1;
1329 return DEVICE_NOT_FOUND;
1330}
1331
9846590e
SC		 1332static void hpsa_monitor_offline_device(struct ctlr_info *h,
1333 unsigned char scsi3addr[])
1334{
1335 struct offline_device_entry *device;
1336 unsigned long flags;
1337
1338 /* Check to see if device is already on the list */
1339 spin_lock_irqsave(&h->offline_device_lock, flags);
1340 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1341 if (memcmp(device->scsi3addr, scsi3addr,
1342 sizeof(device->scsi3addr)) == 0) {
1343 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1344 return;
1345 }
1346 }
1347 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1348
1349 /* Device is not on the list, add it. */
1350 device = kmalloc(sizeof(*device), GFP_KERNEL);
1351 if (!device) {
1352 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1353 return;
1354 }
1355 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1356 spin_lock_irqsave(&h->offline_device_lock, flags);
1357 list_add_tail(&device->offline_list, &h->offline_device_list);
1358 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1359}
1360
1361/* Print a message explaining various offline volume states */
1362static void hpsa_show_volume_status(struct ctlr_info *h,
1363 struct hpsa_scsi_dev_t *sd)
1364{
1365 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1366 dev_info(&h->pdev->dev,
1367 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1368 h->scsi_host->host_no,
1369 sd->bus, sd->target, sd->lun);
1370 switch (sd->volume_offline) {
1371 case HPSA_LV_OK:
1372 break;
1373 case HPSA_LV_UNDERGOING_ERASE:
1374 dev_info(&h->pdev->dev,
1375 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1376 h->scsi_host->host_no,
1377 sd->bus, sd->target, sd->lun);
1378 break;
1379 case HPSA_LV_UNDERGOING_RPI:
1380 dev_info(&h->pdev->dev,
1381 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1382 h->scsi_host->host_no,
1383 sd->bus, sd->target, sd->lun);
1384 break;
1385 case HPSA_LV_PENDING_RPI:
1386 dev_info(&h->pdev->dev,
1387 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1388 h->scsi_host->host_no,
1389 sd->bus, sd->target, sd->lun);
1390 break;
1391 case HPSA_LV_ENCRYPTED_NO_KEY:
1392 dev_info(&h->pdev->dev,
1393 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1394 h->scsi_host->host_no,
1395 sd->bus, sd->target, sd->lun);
1396 break;
1397 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1398 dev_info(&h->pdev->dev,
1399 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1400 h->scsi_host->host_no,
1401 sd->bus, sd->target, sd->lun);
1402 break;
1403 case HPSA_LV_UNDERGOING_ENCRYPTION:
1404 dev_info(&h->pdev->dev,
1405 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1406 h->scsi_host->host_no,
1407 sd->bus, sd->target, sd->lun);
1408 break;
1409 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1410 dev_info(&h->pdev->dev,
1411 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1412 h->scsi_host->host_no,
1413 sd->bus, sd->target, sd->lun);
1414 break;
1415 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1416 dev_info(&h->pdev->dev,
1417 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1418 h->scsi_host->host_no,
1419 sd->bus, sd->target, sd->lun);
1420 break;
1421 case HPSA_LV_PENDING_ENCRYPTION:
1422 dev_info(&h->pdev->dev,
1423 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1424 h->scsi_host->host_no,
1425 sd->bus, sd->target, sd->lun);
1426 break;
1427 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1428 dev_info(&h->pdev->dev,
1429 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1430 h->scsi_host->host_no,
1431 sd->bus, sd->target, sd->lun);
1432 break;
1433 }
1434}
1435
03383736
DB		 1436/*
1437 * Figure the list of physical drive pointers for a logical drive with
1438 * raid offload configured.
1439 */
1440static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1441 struct hpsa_scsi_dev_t *dev[], int ndevices,
1442 struct hpsa_scsi_dev_t *logical_drive)
1443{
1444 struct raid_map_data *map = &logical_drive->raid_map;
1445 struct raid_map_disk_data *dd = &map->data[0];
1446 int i, j;
1447 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1448 le16_to_cpu(map->metadata_disks_per_row);
1449 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1450 le16_to_cpu(map->layout_map_count) *
1451 total_disks_per_row;
1452 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1453 total_disks_per_row;
1454 int qdepth;
1455
1456 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1457 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1458
d604f533
WS		 1459 logical_drive->nphysical_disks = nraid_map_entries;
1460
03383736
DB		 1461 qdepth = 0;
1462 for (i = 0; i < nraid_map_entries; i++) {
1463 logical_drive->phys_disk[i] = NULL;
1464 if (!logical_drive->offload_config)
1465 continue;
1466 for (j = 0; j < ndevices; j++) {
1467 if (dev[j]->devtype != TYPE_DISK)
1468 continue;
1469 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1470 continue;
1471 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1472 continue;
1473
1474 logical_drive->phys_disk[i] = dev[j];
1475 if (i < nphys_disk)
1476 qdepth = min(h->nr_cmds, qdepth +
1477 logical_drive->phys_disk[i]->queue_depth);
1478 break;
1479 }
1480
1481 /*
1482 * This can happen if a physical drive is removed and
1483 * the logical drive is degraded. In that case, the RAID
1484 * map data will refer to a physical disk which isn't actually
1485 * present. And in that case offload_enabled should already
1486 * be 0, but we'll turn it off here just in case
1487 */
1488 if (!logical_drive->phys_disk[i]) {
1489 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1490 logical_drive->offload_to_be_enabled = 0;
1491 logical_drive->queue_depth = 8;
03383736
DB		 1492 }
1493 }
1494 if (nraid_map_entries)
1495 /*
1496 * This is correct for reads, too high for full stripe writes,
1497 * way too high for partial stripe writes
1498 */
1499 logical_drive->queue_depth = qdepth;
1500 else
1501 logical_drive->queue_depth = h->nr_cmds;
1502}
1503
1504static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1505 struct hpsa_scsi_dev_t *dev[], int ndevices)
1506{
1507 int i;
1508
1509 for (i = 0; i < ndevices; i++) {
1510 if (dev[i]->devtype != TYPE_DISK)
1511 continue;
1512 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1513 continue;
41ce4c35
SC		 1514
1515 /*
1516 * If offload is currently enabled, the RAID map and
1517 * phys_disk[] assignment *better* not be changing
1518 * and since it isn't changing, we do not need to
1519 * update it.
1520 */
1521 if (dev[i]->offload_enabled)
1522 continue;
1523
03383736
DB		 1524 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1525 }
1526}
1527
4967bd3e 1528static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1529 struct hpsa_scsi_dev_t *sd[], int nsds)
1530{
1531 /* sd contains scsi3 addresses and devtypes, and inquiry
1532 * data. This function takes what's in sd to be the current
1533 * reality and updates h->dev[] to reflect that reality.
1534 */
1535 int i, entry, device_change, changes = 0;
1536 struct hpsa_scsi_dev_t *csd;
1537 unsigned long flags;
1538 struct hpsa_scsi_dev_t **added, **removed;
1539 int nadded, nremoved;
1540 struct Scsi_Host *sh = NULL;
1541
cfe5badc
ST		 1542 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1543 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1544
1545 if (!added || !removed) {
1546 dev_warn(&h->pdev->dev, "out of memory in "
1547 "adjust_hpsa_scsi_table\n");
1548 goto free_and_out;
1549 }
1550
1551 spin_lock_irqsave(&h->devlock, flags);
1552
1553 /* find any devices in h->dev[] that are not in
1554 * sd[] and remove them from h->dev[], and for any
1555 * devices which have changed, remove the old device
1556 * info and add the new device info.
bd9244f7
ST		 1557 * If minor device attributes change, just update
1558 * the existing device structure.
edd16368
SC		 1559 */
1560 i = 0;
1561 nremoved = 0;
1562 nadded = 0;
1563 while (i < h->ndevices) {
1564 csd = h->dev[i];
1565 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1566 if (device_change == DEVICE_NOT_FOUND) {
1567 changes++;
1568 hpsa_scsi_remove_entry(h, hostno, i,
1569 removed, &nremoved);
1570 continue; /* remove ^^^, hence i not incremented */
1571 } else if (device_change == DEVICE_CHANGED) {
1572 changes++;
2a8ccf31
SC		 1573 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1574 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1575 /* Set it to NULL to prevent it from being freed
1576 * at the bottom of hpsa_update_scsi_devices()
1577 */
1578 sd[entry] = NULL;
bd9244f7
ST		 1579 } else if (device_change == DEVICE_UPDATED) {
1580 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1581 }
1582 i++;
1583 }
1584
1585 /* Now, make sure every device listed in sd[] is also
1586 * listed in h->dev[], adding them if they aren't found
1587 */
1588
1589 for (i = 0; i < nsds; i++) {
1590 if (!sd[i]) /* if already added above. */
1591 continue;
9846590e
SC		 1592
1593 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1594 * as the SCSI mid-layer does not handle such devices well.
1595 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1596 * at 160Hz, and prevents the system from coming up.
1597 */
1598 if (sd[i]->volume_offline) {
1599 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1600 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1601 continue;
1602 }
1603
edd16368
SC		 1604 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1605 h->ndevices, &entry);
1606 if (device_change == DEVICE_NOT_FOUND) {
1607 changes++;
1608 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1609 added, &nadded) != 0)
1610 break;
1611 sd[i] = NULL; /* prevent from being freed later. */
1612 } else if (device_change == DEVICE_CHANGED) {
1613 /* should never happen... */
1614 changes++;
1615 dev_warn(&h->pdev->dev,
1616 "device unexpectedly changed.\n");
1617 /* but if it does happen, we just ignore that device */
1618 }
1619 }
41ce4c35
SC		 1620 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1621
1622 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1623 * any logical drives that need it enabled.
1624 */
1625 for (i = 0; i < h->ndevices; i++)
1626 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1627
edd16368
SC		 1628 spin_unlock_irqrestore(&h->devlock, flags);
1629
9846590e
SC		 1630 /* Monitor devices which are in one of several NOT READY states to be
1631 * brought online later. This must be done without holding h->devlock,
1632 * so don't touch h->dev[]
1633 */
1634 for (i = 0; i < nsds; i++) {
1635 if (!sd[i]) /* if already added above. */
1636 continue;
1637 if (sd[i]->volume_offline)
1638 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1639 }
1640
edd16368
SC		 1641 /* Don't notify scsi mid layer of any changes the first time through
1642 * (or if there are no changes) scsi_scan_host will do it later the
1643 * first time through.
1644 */
1645 if (hostno == -1 || !changes)
1646 goto free_and_out;
1647
1648 sh = h->scsi_host;
1649 /* Notify scsi mid layer of any removed devices */
1650 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1651 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1652 struct scsi_device *sdev =
1653 scsi_device_lookup(sh, removed[i]->bus,
1654 removed[i]->target, removed[i]->lun);
1655 if (sdev != NULL) {
1656 scsi_remove_device(sdev);
1657 scsi_device_put(sdev);
1658 } else {
1659 /*
1660 * We don't expect to get here.
1661 * future cmds to this device will get selection
1662 * timeout as if the device was gone.
1663 */
0d96ef5f
WS		 1664 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1665 "didn't find device for removal.");
41ce4c35 1666 }
edd16368
SC		 1667 }
1668 kfree(removed[i]);
1669 removed[i] = NULL;
1670 }
1671
1672 /* Notify scsi mid layer of any added devices */
1673 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1674 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1675 continue;
edd16368
SC		 1676 if (scsi_add_device(sh, added[i]->bus,
1677 added[i]->target, added[i]->lun) == 0)
1678 continue;
0d96ef5f
WS		 1679 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1680 "addition failed, device not added.");
edd16368
SC		 1681 /* now we have to remove it from h->dev,
1682 * since it didn't get added to scsi mid layer
1683 */
1684 fixup_botched_add(h, added[i]);
105a3dbc 1685 added[i] = NULL;
edd16368
SC		 1686 }
1687
1688free_and_out:
1689 kfree(added);
1690 kfree(removed);
edd16368
SC		 1691}
1692
1693/*
9e03aa2f 1694 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1695 * Assume's h->devlock is held.
1696 */
1697static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1698 int bus, int target, int lun)
1699{
1700 int i;
1701 struct hpsa_scsi_dev_t *sd;
1702
1703 for (i = 0; i < h->ndevices; i++) {
1704 sd = h->dev[i];
1705 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1706 return sd;
1707 }
1708 return NULL;
1709}
1710
edd16368
SC		 1711static int hpsa_slave_alloc(struct scsi_device *sdev)
1712{
1713 struct hpsa_scsi_dev_t *sd;
1714 unsigned long flags;
1715 struct ctlr_info *h;
1716
1717 h = sdev_to_hba(sdev);
1718 spin_lock_irqsave(&h->devlock, flags);
1719 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1720 sdev_id(sdev), sdev->lun);
41ce4c35 1721 if (likely(sd)) {
03383736 1722 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1723 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1724 } else
1725 sdev->hostdata = NULL;
edd16368
SC		 1726 spin_unlock_irqrestore(&h->devlock, flags);
1727 return 0;
1728}
1729
41ce4c35
SC		 1730/* configure scsi device based on internal per-device structure */
1731static int hpsa_slave_configure(struct scsi_device *sdev)
1732{
1733 struct hpsa_scsi_dev_t *sd;
1734 int queue_depth;
1735
1736 sd = sdev->hostdata;
1737 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1738
1739 if (sd)
1740 queue_depth = sd->queue_depth != 0 ?
1741 sd->queue_depth : sdev->host->can_queue;
1742 else
1743 queue_depth = sdev->host->can_queue;
1744
1745 scsi_change_queue_depth(sdev, queue_depth);
1746
1747 return 0;
1748}
1749
edd16368
SC		 1750static void hpsa_slave_destroy(struct scsi_device *sdev)
1751{
bcc44255 1752 /* nothing to do. */
edd16368
SC		 1753}
1754
d9a729f3
WS		 1755static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1756{
1757 int i;
1758
1759 if (!h->ioaccel2_cmd_sg_list)
1760 return;
1761 for (i = 0; i < h->nr_cmds; i++) {
1762 kfree(h->ioaccel2_cmd_sg_list[i]);
1763 h->ioaccel2_cmd_sg_list[i] = NULL;
1764 }
1765 kfree(h->ioaccel2_cmd_sg_list);
1766 h->ioaccel2_cmd_sg_list = NULL;
1767}
1768
1769static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1770{
1771 int i;
1772
1773 if (h->chainsize <= 0)
1774 return 0;
1775
1776 h->ioaccel2_cmd_sg_list =
1777 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1778 GFP_KERNEL);
1779 if (!h->ioaccel2_cmd_sg_list)
1780 return -ENOMEM;
1781 for (i = 0; i < h->nr_cmds; i++) {
1782 h->ioaccel2_cmd_sg_list[i] =
1783 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1784 h->maxsgentries, GFP_KERNEL);
1785 if (!h->ioaccel2_cmd_sg_list[i])
1786 goto clean;
1787 }
1788 return 0;
1789
1790clean:
1791 hpsa_free_ioaccel2_sg_chain_blocks(h);
1792 return -ENOMEM;
1793}
1794
33a2ffce
SC		 1795static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1796{
1797 int i;
1798
1799 if (!h->cmd_sg_list)
1800 return;
1801 for (i = 0; i < h->nr_cmds; i++) {
1802 kfree(h->cmd_sg_list[i]);
1803 h->cmd_sg_list[i] = NULL;
1804 }
1805 kfree(h->cmd_sg_list);
1806 h->cmd_sg_list = NULL;
1807}
1808
105a3dbc 1809static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1810{
1811 int i;
1812
1813 if (h->chainsize <= 0)
1814 return 0;
1815
1816 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1817 GFP_KERNEL);
3d4e6af8
RE		 1818 if (!h->cmd_sg_list) {
1819 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1820 return -ENOMEM;
3d4e6af8 1821 }
33a2ffce
SC		 1822 for (i = 0; i < h->nr_cmds; i++) {
1823 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1824 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1825 if (!h->cmd_sg_list[i]) {
1826 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1827 goto clean;
3d4e6af8 1828 }
33a2ffce
SC		 1829 }
1830 return 0;
1831
1832clean:
1833 hpsa_free_sg_chain_blocks(h);
1834 return -ENOMEM;
1835}
1836
d9a729f3
WS		 1837static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1838 struct io_accel2_cmd *cp, struct CommandList *c)
1839{
1840 struct ioaccel2_sg_element *chain_block;
1841 u64 temp64;
1842 u32 chain_size;
1843
1844 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1845 chain_size = le32_to_cpu(cp->data_len);
1846 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1847 PCI_DMA_TODEVICE);
1848 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1849 /* prevent subsequent unmapping */
1850 cp->sg->address = 0;
1851 return -1;
1852 }
1853 cp->sg->address = cpu_to_le64(temp64);
1854 return 0;
1855}
1856
1857static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1858 struct io_accel2_cmd *cp)
1859{
1860 struct ioaccel2_sg_element *chain_sg;
1861 u64 temp64;
1862 u32 chain_size;
1863
1864 chain_sg = cp->sg;
1865 temp64 = le64_to_cpu(chain_sg->address);
1866 chain_size = le32_to_cpu(cp->data_len);
1867 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1868}
1869
e2bea6df 1870static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1871 struct CommandList *c)
1872{
1873 struct SGDescriptor *chain_sg, *chain_block;
1874 u64 temp64;
50a0decf 1875 u32 chain_len;
33a2ffce
SC		 1876
1877 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1878 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1879 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1880 chain_len = sizeof(*chain_sg) *
2b08b3e9 1881 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1882 chain_sg->Len = cpu_to_le32(chain_len);
1883 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1884 PCI_DMA_TODEVICE);
e2bea6df
SC		 1885 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1886 /* prevent subsequent unmapping */
50a0decf 1887 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1888 return -1;
1889 }
50a0decf 1890 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1891 return 0;
33a2ffce
SC		 1892}
1893
1894static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1895 struct CommandList *c)
1896{
1897 struct SGDescriptor *chain_sg;
33a2ffce 1898
50a0decf 1899 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1900 return;
1901
1902 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1903 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1904 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1905}
1906
a09c1441
ST		 1907
1908/* Decode the various types of errors on ioaccel2 path.
1909 * Return 1 for any error that should generate a RAID path retry.
1910 * Return 0 for errors that don't require a RAID path retry.
1911 */
1912static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1913 struct CommandList *c,
1914 struct scsi_cmnd *cmd,
1915 struct io_accel2_cmd *c2)
1916{
1917 int data_len;
a09c1441 1918 int retry = 0;
c40820d5 1919 u32 ioaccel2_resid = 0;
c349775e
ST		 1920
1921 switch (c2->error_data.serv_response) {
1922 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1923 switch (c2->error_data.status) {
1924 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1925 break;
1926 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 1927 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1928 if (c2->error_data.data_present !=
ee6b1889
SC		 1929 IOACCEL2_SENSE_DATA_PRESENT) {
1930 memset(cmd->sense_buffer, 0,
1931 SCSI_SENSE_BUFFERSIZE);
c349775e 1932 break;
ee6b1889 1933 }
c349775e
ST		 1934 /* copy the sense data */
1935 data_len = c2->error_data.sense_data_len;
1936 if (data_len > SCSI_SENSE_BUFFERSIZE)
1937 data_len = SCSI_SENSE_BUFFERSIZE;
1938 if (data_len > sizeof(c2->error_data.sense_data_buff))
1939 data_len =
1940 sizeof(c2->error_data.sense_data_buff);
1941 memcpy(cmd->sense_buffer,
1942 c2->error_data.sense_data_buff, data_len);
a09c1441 1943 retry = 1;
c349775e
ST		 1944 break;
1945 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 1946 retry = 1;
c349775e
ST		 1947 break;
1948 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 1949 retry = 1;
c349775e
ST		 1950 break;
1951 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1952 retry = 1;
c349775e
ST		 1953 break;
1954 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 1955 retry = 1;
c349775e
ST		 1956 break;
1957 default:
a09c1441 1958 retry = 1;
c349775e
ST		 1959 break;
1960 }
1961 break;
1962 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 1963 switch (c2->error_data.status) {
1964 case IOACCEL2_STATUS_SR_IO_ERROR:
1965 case IOACCEL2_STATUS_SR_IO_ABORTED:
1966 case IOACCEL2_STATUS_SR_OVERRUN:
1967 retry = 1;
1968 break;
1969 case IOACCEL2_STATUS_SR_UNDERRUN:
1970 cmd->result = (DID_OK << 16); /* host byte */
1971 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
1972 ioaccel2_resid = get_unaligned_le32(
1973 &c2->error_data.resid_cnt[0]);
1974 scsi_set_resid(cmd, ioaccel2_resid);
1975 break;
1976 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
1977 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
1978 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
1979 /* We will get an event from ctlr to trigger rescan */
1980 retry = 1;
1981 break;
1982 default:
1983 retry = 1;
c40820d5 1984 }
c349775e
ST		 1985 break;
1986 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1987 break;
1988 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1989 break;
1990 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 1991 retry = 1;
c349775e
ST		 1992 break;
1993 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 1994 break;
1995 default:
a09c1441 1996 retry = 1;
c349775e
ST		 1997 break;
1998 }
a09c1441
ST		 1999
2000 return retry; /* retry on raid path? */
c349775e
ST		 2001}
2002
a58e7e53
WS		 2003static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2004 struct CommandList *c)
2005{
d604f533
WS		 2006 bool do_wake = false;
2007
a58e7e53
WS		 2008 /*
2009 * Prevent the following race in the abort handler:
2010 *
2011 * 1. LLD is requested to abort a SCSI command
2012 * 2. The SCSI command completes
2013 * 3. The struct CommandList associated with step 2 is made available
2014 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2015 * 5. Abort handler follows scsi_cmnd->host_scribble and
2016 * finds struct CommandList and tries to aborts it
2017 * Now we have aborted the wrong command.
2018 *
d604f533
WS		 2019 * Reset c->scsi_cmd here so that the abort or reset handler will know
2020 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2021 * waiting for this command, and, if so, wake it.
2022 */
2023 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2024 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2025 if (c->abort_pending) {
d604f533 2026 do_wake = true;
a58e7e53 2027 c->abort_pending = false;
a58e7e53 2028 }
d604f533
WS		 2029 if (c->reset_pending) {
2030 unsigned long flags;
2031 struct hpsa_scsi_dev_t *dev;
2032
2033 /*
2034 * There appears to be a reset pending; lock the lock and
2035 * reconfirm. If so, then decrement the count of outstanding
2036 * commands and wake the reset command if this is the last one.
2037 */
2038 spin_lock_irqsave(&h->lock, flags);
2039 dev = c->reset_pending; /* Re-fetch under the lock. */
2040 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2041 do_wake = true;
2042 c->reset_pending = NULL;
2043 spin_unlock_irqrestore(&h->lock, flags);
2044 }
2045
2046 if (do_wake)
2047 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2048}
2049
73153fe5
WS		 2050static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2051 struct CommandList *c)
2052{
2053 hpsa_cmd_resolve_events(h, c);
2054 cmd_tagged_free(h, c);
2055}
2056
8a0ff92c
WS		 2057static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2058 struct CommandList *c, struct scsi_cmnd *cmd)
2059{
73153fe5 2060 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2061 cmd->scsi_done(cmd);
2062}
2063
2064static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2065{
2066 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2067 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2068}
2069
a58e7e53
WS		 2070static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2071{
2072 cmd->result = DID_ABORT << 16;
2073}
2074
2075static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2076 struct scsi_cmnd *cmd)
2077{
2078 hpsa_set_scsi_cmd_aborted(cmd);
2079 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2080 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2081 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2082}
2083
c349775e
ST		 2084static void process_ioaccel2_completion(struct ctlr_info *h,
2085 struct CommandList *c, struct scsi_cmnd *cmd,
2086 struct hpsa_scsi_dev_t *dev)
2087{
2088 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2089
2090 /* check for good status */
2091 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2092 c2->error_data.status == 0))
2093 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2094
8a0ff92c
WS		 2095 /*
2096 * Any RAID offload error results in retry which will use
c349775e
ST		 2097 * the normal I/O path so the controller can handle whatever's
2098 * wrong.
2099 */
2100 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2101 c2->error_data.serv_response ==
2102 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2103 if (c2->error_data.status ==
2104 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2105 dev->offload_enabled = 0;
8a0ff92c
WS		 2106
2107 return hpsa_retry_cmd(h, c);
a09c1441 2108 }
080ef1cc
DB		 2109
2110 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2111 return hpsa_retry_cmd(h, c);
080ef1cc 2112
8a0ff92c 2113 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2114}
2115
9437ac43
SC		 2116/* Returns 0 on success, < 0 otherwise. */
2117static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2118 struct CommandList *cp)
2119{
2120 u8 tmf_status = cp->err_info->ScsiStatus;
2121
2122 switch (tmf_status) {
2123 case CISS_TMF_COMPLETE:
2124 /*
2125 * CISS_TMF_COMPLETE never happens, instead,
2126 * ei->CommandStatus == 0 for this case.
2127 */
2128 case CISS_TMF_SUCCESS:
2129 return 0;
2130 case CISS_TMF_INVALID_FRAME:
2131 case CISS_TMF_NOT_SUPPORTED:
2132 case CISS_TMF_FAILED:
2133 case CISS_TMF_WRONG_LUN:
2134 case CISS_TMF_OVERLAPPED_TAG:
2135 break;
2136 default:
2137 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2138 tmf_status);
2139 break;
2140 }
2141 return -tmf_status;
2142}
2143
1fb011fb 2144static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2145{
2146 struct scsi_cmnd *cmd;
2147 struct ctlr_info *h;
2148 struct ErrorInfo *ei;
283b4a9b 2149 struct hpsa_scsi_dev_t *dev;
d9a729f3 2150 struct io_accel2_cmd *c2;
edd16368 2151
9437ac43
SC		 2152 u8 sense_key;
2153 u8 asc; /* additional sense code */
2154 u8 ascq; /* additional sense code qualifier */
db111e18 2155 unsigned long sense_data_size;
edd16368
SC		 2156
2157 ei = cp->err_info;
7fa3030c 2158 cmd = cp->scsi_cmd;
edd16368 2159 h = cp->h;
283b4a9b 2160 dev = cmd->device->hostdata;
d9a729f3 2161 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2162
2163 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2164 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2165 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2166 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2167
d9a729f3
WS		 2168 if ((cp->cmd_type == CMD_IOACCEL2) &&
2169 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2170 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2171
edd16368
SC		 2172 cmd->result = (DID_OK << 16); /* host byte */
2173 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2174
03383736
DB		 2175 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2176 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2177
25163bd5
WS		 2178 /*
2179 * We check for lockup status here as it may be set for
2180 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2181 * fail_all_oustanding_cmds()
2182 */
2183 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2184 /* DID_NO_CONNECT will prevent a retry */
2185 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2186 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2187 }
2188
d604f533
WS		 2189 if ((unlikely(hpsa_is_pending_event(cp)))) {
2190 if (cp->reset_pending)
2191 return hpsa_cmd_resolve_and_free(h, cp);
2192 if (cp->abort_pending)
2193 return hpsa_cmd_abort_and_free(h, cp, cmd);
2194 }
2195
c349775e
ST		 2196 if (cp->cmd_type == CMD_IOACCEL2)
2197 return process_ioaccel2_completion(h, cp, cmd, dev);
2198
6aa4c361 2199 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2200 if (ei->CommandStatus == 0)
2201 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2202
e1f7de0c
MG		 2203 /* For I/O accelerator commands, copy over some fields to the normal
2204 * CISS header used below for error handling.
2205 */
2206 if (cp->cmd_type == CMD_IOACCEL1) {
2207 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2208 cp->Header.SGList = scsi_sg_count(cmd);
2209 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2210 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2211 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2212 cp->Header.tag = c->tag;
e1f7de0c
MG		 2213 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2214 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2215
2216 /* Any RAID offload error results in retry which will use
2217 * the normal I/O path so the controller can handle whatever's
2218 * wrong.
2219 */
2220 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2221 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2222 dev->offload_enabled = 0;
d604f533 2223 return hpsa_retry_cmd(h, cp);
283b4a9b 2224 }
e1f7de0c
MG		 2225 }
2226
edd16368
SC		 2227 /* an error has occurred */
2228 switch (ei->CommandStatus) {
2229
2230 case CMD_TARGET_STATUS:
9437ac43
SC		 2231 cmd->result |= ei->ScsiStatus;
2232 /* copy the sense data */
2233 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2234 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2235 else
2236 sense_data_size = sizeof(ei->SenseInfo);
2237 if (ei->SenseLen < sense_data_size)
2238 sense_data_size = ei->SenseLen;
2239 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2240 if (ei->ScsiStatus)
2241 decode_sense_data(ei->SenseInfo, sense_data_size,
2242 &sense_key, &asc, &ascq);
edd16368 2243 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2244 if (sense_key == ABORTED_COMMAND) {
2e311fba 2245 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2246 break;
2247 }
edd16368
SC		 2248 break;
2249 }
edd16368
SC		 2250 /* Problem was not a check condition
2251 * Pass it up to the upper layers...
2252 */
2253 if (ei->ScsiStatus) {
2254 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2255 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2256 "Returning result: 0x%x\n",
2257 cp, ei->ScsiStatus,
2258 sense_key, asc, ascq,
2259 cmd->result);
2260 } else { /* scsi status is zero??? How??? */
2261 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2262 "Returning no connection.\n", cp),
2263
2264 /* Ordinarily, this case should never happen,
2265 * but there is a bug in some released firmware
2266 * revisions that allows it to happen if, for
2267 * example, a 4100 backplane loses power and
2268 * the tape drive is in it. We assume that
2269 * it's a fatal error of some kind because we
2270 * can't show that it wasn't. We will make it
2271 * look like selection timeout since that is
2272 * the most common reason for this to occur,
2273 * and it's severe enough.
2274 */
2275
2276 cmd->result = DID_NO_CONNECT << 16;
2277 }
2278 break;
2279
2280 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2281 break;
2282 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2283 dev_warn(&h->pdev->dev,
2284 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2285 break;
2286 case CMD_INVALID: {
2287 /* print_bytes(cp, sizeof(*cp), 1, 0);
2288 print_cmd(cp); */
2289 /* We get CMD_INVALID if you address a non-existent device
2290 * instead of a selection timeout (no response). You will
2291 * see this if you yank out a drive, then try to access it.
2292 * This is kind of a shame because it means that any other
2293 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2294 * missing target. */
2295 cmd->result = DID_NO_CONNECT << 16;
2296 }
2297 break;
2298 case CMD_PROTOCOL_ERR:
256d0eaa 2299 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2300 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2301 cp->Request.CDB);
edd16368
SC		 2302 break;
2303 case CMD_HARDWARE_ERR:
2304 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2305 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2306 cp->Request.CDB);
edd16368
SC		 2307 break;
2308 case CMD_CONNECTION_LOST:
2309 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2310 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2311 cp->Request.CDB);
edd16368
SC		 2312 break;
2313 case CMD_ABORTED:
a58e7e53
WS		 2314 /* Return now to avoid calling scsi_done(). */
2315 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2316 case CMD_ABORT_FAILED:
2317 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2318 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2319 cp->Request.CDB);
edd16368
SC		 2320 break;
2321 case CMD_UNSOLICITED_ABORT:
f6e76055 2322 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2323 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2324 cp->Request.CDB);
edd16368
SC		 2325 break;
2326 case CMD_TIMEOUT:
2327 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2328 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2329 cp->Request.CDB);
edd16368 2330 break;
1d5e2ed0
SC		 2331 case CMD_UNABORTABLE:
2332 cmd->result = DID_ERROR << 16;
2333 dev_warn(&h->pdev->dev, "Command unabortable\n");
2334 break;
9437ac43
SC		 2335 case CMD_TMF_STATUS:
2336 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2337 cmd->result = DID_ERROR << 16;
2338 break;
283b4a9b
SC		 2339 case CMD_IOACCEL_DISABLED:
2340 /* This only handles the direct pass-through case since RAID
2341 * offload is handled above. Just attempt a retry.
2342 */
2343 cmd->result = DID_SOFT_ERROR << 16;
2344 dev_warn(&h->pdev->dev,
2345 "cp %p had HP SSD Smart Path error\n", cp);
2346 break;
edd16368
SC		 2347 default:
2348 cmd->result = DID_ERROR << 16;
2349 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2350 cp, ei->CommandStatus);
2351 }
8a0ff92c
WS		 2352
2353 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2354}
2355
edd16368
SC		 2356static void hpsa_pci_unmap(struct pci_dev *pdev,
2357 struct CommandList *c, int sg_used, int data_direction)
2358{
2359 int i;
edd16368 2360
50a0decf
SC		 2361 for (i = 0; i < sg_used; i++)
2362 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2363 le32_to_cpu(c->SG[i].Len),
2364 data_direction);
edd16368
SC		 2365}
2366
a2dac136 2367static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2368 struct CommandList *cp,
2369 unsigned char *buf,
2370 size_t buflen,
2371 int data_direction)
2372{
01a02ffc 2373 u64 addr64;
edd16368
SC		 2374
2375 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2376 cp->Header.SGList = 0;
50a0decf 2377 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2378 return 0;
edd16368
SC		 2379 }
2380
50a0decf 2381 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2382 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2383 /* Prevent subsequent unmap of something never mapped */
eceaae18 2384 cp->Header.SGList = 0;
50a0decf 2385 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2386 return -1;
eceaae18 2387 }
50a0decf
SC		 2388 cp->SG[0].Addr = cpu_to_le64(addr64);
2389 cp->SG[0].Len = cpu_to_le32(buflen);
2390 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2391 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2392 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2393 return 0;
edd16368
SC		 2394}
2395
25163bd5
WS		 2396#define NO_TIMEOUT ((unsigned long) -1)
2397#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2398static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2399 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2400{
2401 DECLARE_COMPLETION_ONSTACK(wait);
2402
2403 c->waiting = &wait;
25163bd5
WS		 2404 __enqueue_cmd_and_start_io(h, c, reply_queue);
2405 if (timeout_msecs == NO_TIMEOUT) {
2406 /* TODO: get rid of this no-timeout thing */
2407 wait_for_completion_io(&wait);
2408 return IO_OK;
2409 }
2410 if (!wait_for_completion_io_timeout(&wait,
2411 msecs_to_jiffies(timeout_msecs))) {
2412 dev_warn(&h->pdev->dev, "Command timed out.\n");
2413 return -ETIMEDOUT;
2414 }
2415 return IO_OK;
2416}
2417
2418static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2419 int reply_queue, unsigned long timeout_msecs)
2420{
2421 if (unlikely(lockup_detected(h))) {
2422 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2423 return IO_OK;
2424 }
2425 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2426}
2427
094963da
SC		 2428static u32 lockup_detected(struct ctlr_info *h)
2429{
2430 int cpu;
2431 u32 rc, *lockup_detected;
2432
2433 cpu = get_cpu();
2434 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2435 rc = *lockup_detected;
2436 put_cpu();
2437 return rc;
2438}
2439
9c2fc160 2440#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2441static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2442 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2443{
9c2fc160 2444 int backoff_time = 10, retry_count = 0;
25163bd5 2445 int rc;
edd16368
SC		 2446
2447 do {
7630abd0 2448 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2449 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2450 timeout_msecs);
2451 if (rc)
2452 break;
edd16368 2453 retry_count++;
9c2fc160
SC		 2454 if (retry_count > 3) {
2455 msleep(backoff_time);
2456 if (backoff_time < 1000)
2457 backoff_time *= 2;
2458 }
852af20a 2459 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2460 check_for_busy(h, c)) &&
2461 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2462 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2463 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2464 rc = -EIO;
2465 return rc;
edd16368
SC		 2466}
2467
d1e8beac
SC		 2468static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2469 struct CommandList *c)
edd16368 2470{
d1e8beac
SC		 2471 const u8 *cdb = c->Request.CDB;
2472 const u8 *lun = c->Header.LUN.LunAddrBytes;
2473
2474 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2475 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2476 txt, lun[0], lun[1], lun[2], lun[3],
2477 lun[4], lun[5], lun[6], lun[7],
2478 cdb[0], cdb[1], cdb[2], cdb[3],
2479 cdb[4], cdb[5], cdb[6], cdb[7],
2480 cdb[8], cdb[9], cdb[10], cdb[11],
2481 cdb[12], cdb[13], cdb[14], cdb[15]);
2482}
2483
2484static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2485 struct CommandList *cp)
2486{
2487 const struct ErrorInfo *ei = cp->err_info;
edd16368 2488 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2489 u8 sense_key, asc, ascq;
2490 int sense_len;
edd16368 2491
edd16368
SC		 2492 switch (ei->CommandStatus) {
2493 case CMD_TARGET_STATUS:
9437ac43
SC		 2494 if (ei->SenseLen > sizeof(ei->SenseInfo))
2495 sense_len = sizeof(ei->SenseInfo);
2496 else
2497 sense_len = ei->SenseLen;
2498 decode_sense_data(ei->SenseInfo, sense_len,
2499 &sense_key, &asc, &ascq);
d1e8beac
SC		 2500 hpsa_print_cmd(h, "SCSI status", cp);
2501 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2502 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2503 sense_key, asc, ascq);
d1e8beac 2504 else
9437ac43 2505 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2506 if (ei->ScsiStatus == 0)
2507 dev_warn(d, "SCSI status is abnormally zero. "
2508 "(probably indicates selection timeout "
2509 "reported incorrectly due to a known "
2510 "firmware bug, circa July, 2001.)\n");
2511 break;
2512 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2513 break;
2514 case CMD_DATA_OVERRUN:
d1e8beac 2515 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2516 break;
2517 case CMD_INVALID: {
2518 /* controller unfortunately reports SCSI passthru's
2519 * to non-existent targets as invalid commands.
2520 */
d1e8beac
SC		 2521 hpsa_print_cmd(h, "invalid command", cp);
2522 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2523 }
2524 break;
2525 case CMD_PROTOCOL_ERR:
d1e8beac 2526 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2527 break;
2528 case CMD_HARDWARE_ERR:
d1e8beac 2529 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2530 break;
2531 case CMD_CONNECTION_LOST:
d1e8beac 2532 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2533 break;
2534 case CMD_ABORTED:
d1e8beac 2535 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2536 break;
2537 case CMD_ABORT_FAILED:
d1e8beac 2538 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2539 break;
2540 case CMD_UNSOLICITED_ABORT:
d1e8beac 2541 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2542 break;
2543 case CMD_TIMEOUT:
d1e8beac 2544 hpsa_print_cmd(h, "timed out", cp);
edd16368 2545 break;
1d5e2ed0 2546 case CMD_UNABORTABLE:
d1e8beac 2547 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2548 break;
25163bd5
WS		 2549 case CMD_CTLR_LOCKUP:
2550 hpsa_print_cmd(h, "controller lockup detected", cp);
2551 break;
edd16368 2552 default:
d1e8beac
SC		 2553 hpsa_print_cmd(h, "unknown status", cp);
2554 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2555 ei->CommandStatus);
2556 }
2557}
2558
2559static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2560 u16 page, unsigned char *buf,
edd16368
SC		 2561 unsigned char bufsize)
2562{
2563 int rc = IO_OK;
2564 struct CommandList *c;
2565 struct ErrorInfo *ei;
2566
45fcb86e 2567 c = cmd_alloc(h);
edd16368 2568
a2dac136
SC		 2569 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2570 page, scsi3addr, TYPE_CMD)) {
2571 rc = -1;
2572 goto out;
2573 }
25163bd5
WS		 2574 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2575 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2576 if (rc)
2577 goto out;
edd16368
SC		 2578 ei = c->err_info;
2579 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2580 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2581 rc = -1;
2582 }
a2dac136 2583out:
45fcb86e 2584 cmd_free(h, c);
edd16368
SC		 2585 return rc;
2586}
2587
316b221a
SC		 2588static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2589 unsigned char *scsi3addr, unsigned char page,
2590 struct bmic_controller_parameters *buf, size_t bufsize)
2591{
2592 int rc = IO_OK;
2593 struct CommandList *c;
2594 struct ErrorInfo *ei;
2595
45fcb86e 2596 c = cmd_alloc(h);
316b221a
SC		 2597 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2598 page, scsi3addr, TYPE_CMD)) {
2599 rc = -1;
2600 goto out;
2601 }
25163bd5
WS		 2602 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2603 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2604 if (rc)
2605 goto out;
316b221a
SC		 2606 ei = c->err_info;
2607 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2608 hpsa_scsi_interpret_error(h, c);
2609 rc = -1;
2610 }
2611out:
45fcb86e 2612 cmd_free(h, c);
316b221a 2613 return rc;
bf43caf3 2614}
316b221a 2615
bf711ac6 2616static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2617 u8 reset_type, int reply_queue)
edd16368
SC		 2618{
2619 int rc = IO_OK;
2620 struct CommandList *c;
2621 struct ErrorInfo *ei;
2622
45fcb86e 2623 c = cmd_alloc(h);
edd16368 2624
edd16368 2625
a2dac136 2626 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2627 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2628 scsi3addr, TYPE_MSG);
2629 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2630 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2631 if (rc) {
2632 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2633 goto out;
2634 }
edd16368
SC		 2635 /* no unmap needed here because no data xfer. */
2636
2637 ei = c->err_info;
2638 if (ei->CommandStatus != 0) {
d1e8beac 2639 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2640 rc = -1;
2641 }
25163bd5 2642out:
45fcb86e 2643 cmd_free(h, c);
edd16368
SC		 2644 return rc;
2645}
2646
d604f533
WS		 2647static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2648 struct hpsa_scsi_dev_t *dev,
2649 unsigned char *scsi3addr)
2650{
2651 int i;
2652 bool match = false;
2653 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2654 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2655
2656 if (hpsa_is_cmd_idle(c))
2657 return false;
2658
2659 switch (c->cmd_type) {
2660 case CMD_SCSI:
2661 case CMD_IOCTL_PEND:
2662 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2663 sizeof(c->Header.LUN.LunAddrBytes));
2664 break;
2665
2666 case CMD_IOACCEL1:
2667 case CMD_IOACCEL2:
2668 if (c->phys_disk == dev) {
2669 /* HBA mode match */
2670 match = true;
2671 } else {
2672 /* Possible RAID mode -- check each phys dev. */
2673 /* FIXME: Do we need to take out a lock here? If
2674 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2675 * instead. */
2676 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2677 /* FIXME: an alternate test might be
2678 *
2679 * match = dev->phys_disk[i]->ioaccel_handle
2680 * == c2->scsi_nexus; */
2681 match = dev->phys_disk[i] == c->phys_disk;
2682 }
2683 }
2684 break;
2685
2686 case IOACCEL2_TMF:
2687 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2688 match = dev->phys_disk[i]->ioaccel_handle ==
2689 le32_to_cpu(ac->it_nexus);
2690 }
2691 break;
2692
2693 case 0: /* The command is in the middle of being initialized. */
2694 match = false;
2695 break;
2696
2697 default:
2698 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2699 c->cmd_type);
2700 BUG();
2701 }
2702
2703 return match;
2704}
2705
2706static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2707 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2708{
2709 int i;
2710 int rc = 0;
2711
2712 /* We can really only handle one reset at a time */
2713 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2714 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2715 return -EINTR;
2716 }
2717
2718 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2719
2720 for (i = 0; i < h->nr_cmds; i++) {
2721 struct CommandList *c = h->cmd_pool + i;
2722 int refcount = atomic_inc_return(&c->refcount);
2723
2724 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2725 unsigned long flags;
2726
2727 /*
2728 * Mark the target command as having a reset pending,
2729 * then lock a lock so that the command cannot complete
2730 * while we're considering it. If the command is not
2731 * idle then count it; otherwise revoke the event.
2732 */
2733 c->reset_pending = dev;
2734 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2735 if (!hpsa_is_cmd_idle(c))
2736 atomic_inc(&dev->reset_cmds_out);
2737 else
2738 c->reset_pending = NULL;
2739 spin_unlock_irqrestore(&h->lock, flags);
2740 }
2741
2742 cmd_free(h, c);
2743 }
2744
2745 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2746 if (!rc)
2747 wait_event(h->event_sync_wait_queue,
2748 atomic_read(&dev->reset_cmds_out) == 0 ||
2749 lockup_detected(h));
2750
2751 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2752 dev_warn(&h->pdev->dev,
2753 "Controller lockup detected during reset wait\n");
2754 rc = -ENODEV;
2755 }
d604f533
WS		 2756
2757 if (unlikely(rc))
2758 atomic_set(&dev->reset_cmds_out, 0);
2759
2760 mutex_unlock(&h->reset_mutex);
2761 return rc;
2762}
2763
edd16368
SC		 2764static void hpsa_get_raid_level(struct ctlr_info *h,
2765 unsigned char *scsi3addr, unsigned char *raid_level)
2766{
2767 int rc;
2768 unsigned char *buf;
2769
2770 *raid_level = RAID_UNKNOWN;
2771 buf = kzalloc(64, GFP_KERNEL);
2772 if (!buf)
2773 return;
b7bb24eb 2774 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2775 if (rc == 0)
2776 *raid_level = buf[8];
2777 if (*raid_level > RAID_UNKNOWN)
2778 *raid_level = RAID_UNKNOWN;
2779 kfree(buf);
2780 return;
2781}
2782
283b4a9b
SC		 2783#define HPSA_MAP_DEBUG
2784#ifdef HPSA_MAP_DEBUG
2785static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2786 struct raid_map_data *map_buff)
2787{
2788 struct raid_map_disk_data *dd = &map_buff->data[0];
2789 int map, row, col;
2790 u16 map_cnt, row_cnt, disks_per_row;
2791
2792 if (rc != 0)
2793 return;
2794
2ba8bfc8
SC		 2795 /* Show details only if debugging has been activated. */
2796 if (h->raid_offload_debug < 2)
2797 return;
2798
283b4a9b
SC		 2799 dev_info(&h->pdev->dev, "structure_size = %u\n",
2800 le32_to_cpu(map_buff->structure_size));
2801 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2802 le32_to_cpu(map_buff->volume_blk_size));
2803 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2804 le64_to_cpu(map_buff->volume_blk_cnt));
2805 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2806 map_buff->phys_blk_shift);
2807 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2808 map_buff->parity_rotation_shift);
2809 dev_info(&h->pdev->dev, "strip_size = %u\n",
2810 le16_to_cpu(map_buff->strip_size));
2811 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2812 le64_to_cpu(map_buff->disk_starting_blk));
2813 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2814 le64_to_cpu(map_buff->disk_blk_cnt));
2815 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2816 le16_to_cpu(map_buff->data_disks_per_row));
2817 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2818 le16_to_cpu(map_buff->metadata_disks_per_row));
2819 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2820 le16_to_cpu(map_buff->row_cnt));
2821 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2822 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2823 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2824 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2825 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2826 le16_to_cpu(map_buff->flags) &
2827 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2828 dev_info(&h->pdev->dev, "dekindex = %u\n",
2829 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2830 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2831 for (map = 0; map < map_cnt; map++) {
2832 dev_info(&h->pdev->dev, "Map%u:\n", map);
2833 row_cnt = le16_to_cpu(map_buff->row_cnt);
2834 for (row = 0; row < row_cnt; row++) {
2835 dev_info(&h->pdev->dev, " Row%u:\n", row);
2836 disks_per_row =
2837 le16_to_cpu(map_buff->data_disks_per_row);
2838 for (col = 0; col < disks_per_row; col++, dd++)
2839 dev_info(&h->pdev->dev,
2840 " D%02u: h=0x%04x xor=%u,%u\n",
2841 col, dd->ioaccel_handle,
2842 dd->xor_mult[0], dd->xor_mult[1]);
2843 disks_per_row =
2844 le16_to_cpu(map_buff->metadata_disks_per_row);
2845 for (col = 0; col < disks_per_row; col++, dd++)
2846 dev_info(&h->pdev->dev,
2847 " M%02u: h=0x%04x xor=%u,%u\n",
2848 col, dd->ioaccel_handle,
2849 dd->xor_mult[0], dd->xor_mult[1]);
2850 }
2851 }
2852}
2853#else
2854static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2855 __attribute__((unused)) int rc,
2856 __attribute__((unused)) struct raid_map_data *map_buff)
2857{
2858}
2859#endif
2860
2861static int hpsa_get_raid_map(struct ctlr_info *h,
2862 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2863{
2864 int rc = 0;
2865 struct CommandList *c;
2866 struct ErrorInfo *ei;
2867
45fcb86e 2868 c = cmd_alloc(h);
bf43caf3 2869
283b4a9b
SC		 2870 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2871 sizeof(this_device->raid_map), 0,
2872 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2873 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2874 cmd_free(h, c);
2875 return -1;
283b4a9b 2876 }
25163bd5
WS		 2877 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2878 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2879 if (rc)
2880 goto out;
283b4a9b
SC		 2881 ei = c->err_info;
2882 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2883 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2884 rc = -1;
2885 goto out;
283b4a9b 2886 }
45fcb86e 2887 cmd_free(h, c);
283b4a9b
SC		 2888
2889 /* @todo in the future, dynamically allocate RAID map memory */
2890 if (le32_to_cpu(this_device->raid_map.structure_size) >
2891 sizeof(this_device->raid_map)) {
2892 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2893 rc = -1;
2894 }
2895 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2896 return rc;
25163bd5
WS		 2897out:
2898 cmd_free(h, c);
2899 return rc;
283b4a9b
SC		 2900}
2901
03383736
DB		 2902static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2903 unsigned char scsi3addr[], u16 bmic_device_index,
2904 struct bmic_identify_physical_device *buf, size_t bufsize)
2905{
2906 int rc = IO_OK;
2907 struct CommandList *c;
2908 struct ErrorInfo *ei;
2909
2910 c = cmd_alloc(h);
2911 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2912 0, RAID_CTLR_LUNID, TYPE_CMD);
2913 if (rc)
2914 goto out;
2915
2916 c->Request.CDB[2] = bmic_device_index & 0xff;
2917 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2918
25163bd5
WS		 2919 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2920 NO_TIMEOUT);
03383736
DB		 2921 ei = c->err_info;
2922 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2923 hpsa_scsi_interpret_error(h, c);
2924 rc = -1;
2925 }
2926out:
2927 cmd_free(h, c);
2928 return rc;
2929}
2930
1b70150a
SC		 2931static int hpsa_vpd_page_supported(struct ctlr_info *h,
2932 unsigned char scsi3addr[], u8 page)
2933{
2934 int rc;
2935 int i;
2936 int pages;
2937 unsigned char *buf, bufsize;
2938
2939 buf = kzalloc(256, GFP_KERNEL);
2940 if (!buf)
2941 return 0;
2942
2943 /* Get the size of the page list first */
2944 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2945 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2946 buf, HPSA_VPD_HEADER_SZ);
2947 if (rc != 0)
2948 goto exit_unsupported;
2949 pages = buf[3];
2950 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2951 bufsize = pages + HPSA_VPD_HEADER_SZ;
2952 else
2953 bufsize = 255;
2954
2955 /* Get the whole VPD page list */
2956 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2957 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2958 buf, bufsize);
2959 if (rc != 0)
2960 goto exit_unsupported;
2961
2962 pages = buf[3];
2963 for (i = 1; i <= pages; i++)
2964 if (buf[3 + i] == page)
2965 goto exit_supported;
2966exit_unsupported:
2967 kfree(buf);
2968 return 0;
2969exit_supported:
2970 kfree(buf);
2971 return 1;
2972}
2973
283b4a9b
SC		 2974static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2975 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2976{
2977 int rc;
2978 unsigned char *buf;
2979 u8 ioaccel_status;
2980
2981 this_device->offload_config = 0;
2982 this_device->offload_enabled = 0;
41ce4c35 2983 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2984
2985 buf = kzalloc(64, GFP_KERNEL);
2986 if (!buf)
2987 return;
1b70150a
SC		 2988 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2989 goto out;
283b4a9b 2990 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2991 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2992 if (rc != 0)
2993 goto out;
2994
2995#define IOACCEL_STATUS_BYTE 4
2996#define OFFLOAD_CONFIGURED_BIT 0x01
2997#define OFFLOAD_ENABLED_BIT 0x02
2998 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2999 this_device->offload_config =
3000 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3001 if (this_device->offload_config) {
3002 this_device->offload_enabled =
3003 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3004 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3005 this_device->offload_enabled = 0;
3006 }
41ce4c35 3007 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3008out:
3009 kfree(buf);
3010 return;
3011}
3012
edd16368
SC		 3013/* Get the device id from inquiry page 0x83 */
3014static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3015 unsigned char *device_id, int buflen)
3016{
3017 int rc;
3018 unsigned char *buf;
3019
3020 if (buflen > 16)
3021 buflen = 16;
3022 buf = kzalloc(64, GFP_KERNEL);
3023 if (!buf)
a84d794d 3024 return -ENOMEM;
b7bb24eb 3025 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3026 if (rc == 0)
3027 memcpy(device_id, &buf[8], buflen);
3028 kfree(buf);
3029 return rc != 0;
3030}
3031
3032static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3033 void *buf, int bufsize,
edd16368
SC		 3034 int extended_response)
3035{
3036 int rc = IO_OK;
3037 struct CommandList *c;
3038 unsigned char scsi3addr[8];
3039 struct ErrorInfo *ei;
3040
45fcb86e 3041 c = cmd_alloc(h);
bf43caf3 3042
e89c0ae7
SC		 3043 /* address the controller */
3044 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3045 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3046 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3047 rc = -1;
3048 goto out;
3049 }
edd16368
SC		 3050 if (extended_response)
3051 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3052 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3053 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3054 if (rc)
3055 goto out;
edd16368
SC		 3056 ei = c->err_info;
3057 if (ei->CommandStatus != 0 &&
3058 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3059 hpsa_scsi_interpret_error(h, c);
edd16368 3060 rc = -1;
283b4a9b 3061 } else {
03383736
DB		 3062 struct ReportLUNdata *rld = buf;
3063
3064 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3065 dev_err(&h->pdev->dev,
3066 "report luns requested format %u, got %u\n",
3067 extended_response,
03383736 3068 rld->extended_response_flag);
283b4a9b
SC		 3069 rc = -1;
3070 }
edd16368 3071 }
a2dac136 3072out:
45fcb86e 3073 cmd_free(h, c);
edd16368
SC		 3074 return rc;
3075}
3076
3077static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3078 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3079{
03383736
DB		 3080 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3081 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3082}
3083
3084static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3085 struct ReportLUNdata *buf, int bufsize)
3086{
3087 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3088}
3089
3090static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3091 int bus, int target, int lun)
3092{
3093 device->bus = bus;
3094 device->target = target;
3095 device->lun = lun;
3096}
3097
9846590e
SC		 3098/* Use VPD inquiry to get details of volume status */
3099static int hpsa_get_volume_status(struct ctlr_info *h,
3100 unsigned char scsi3addr[])
3101{
3102 int rc;
3103 int status;
3104 int size;
3105 unsigned char *buf;
3106
3107 buf = kzalloc(64, GFP_KERNEL);
3108 if (!buf)
3109 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3110
3111 /* Does controller have VPD for logical volume status? */
24a4b078 3112 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3113 goto exit_failed;
9846590e
SC		 3114
3115 /* Get the size of the VPD return buffer */
3116 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3117 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3118 if (rc != 0)
9846590e 3119 goto exit_failed;
9846590e
SC		 3120 size = buf[3];
3121
3122 /* Now get the whole VPD buffer */
3123 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3124 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3125 if (rc != 0)
9846590e 3126 goto exit_failed;
9846590e
SC		 3127 status = buf[4]; /* status byte */
3128
3129 kfree(buf);
3130 return status;
3131exit_failed:
3132 kfree(buf);
3133 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3134}
3135
3136/* Determine offline status of a volume.
3137 * Return either:
3138 * 0 (not offline)
67955ba3 3139 * 0xff (offline for unknown reasons)
9846590e
SC		 3140 * # (integer code indicating one of several NOT READY states
3141 * describing why a volume is to be kept offline)
3142 */
67955ba3 3143static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3144 unsigned char scsi3addr[])
3145{
3146 struct CommandList *c;
9437ac43
SC		 3147 unsigned char *sense;
3148 u8 sense_key, asc, ascq;
3149 int sense_len;
25163bd5 3150 int rc, ldstat = 0;
9846590e
SC		 3151 u16 cmd_status;
3152 u8 scsi_status;
3153#define ASC_LUN_NOT_READY 0x04
3154#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3155#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3156
3157 c = cmd_alloc(h);
bf43caf3 3158
9846590e 3159 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3160 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3161 if (rc) {
3162 cmd_free(h, c);
3163 return 0;
3164 }
9846590e 3165 sense = c->err_info->SenseInfo;
9437ac43
SC		 3166 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3167 sense_len = sizeof(c->err_info->SenseInfo);
3168 else
3169 sense_len = c->err_info->SenseLen;
3170 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3171 cmd_status = c->err_info->CommandStatus;
3172 scsi_status = c->err_info->ScsiStatus;
3173 cmd_free(h, c);
3174 /* Is the volume 'not ready'? */
3175 if (cmd_status != CMD_TARGET_STATUS ||
3176 scsi_status != SAM_STAT_CHECK_CONDITION ||
3177 sense_key != NOT_READY ||
3178 asc != ASC_LUN_NOT_READY) {
3179 return 0;
3180 }
3181
3182 /* Determine the reason for not ready state */
3183 ldstat = hpsa_get_volume_status(h, scsi3addr);
3184
3185 /* Keep volume offline in certain cases: */
3186 switch (ldstat) {
3187 case HPSA_LV_UNDERGOING_ERASE:
3188 case HPSA_LV_UNDERGOING_RPI:
3189 case HPSA_LV_PENDING_RPI:
3190 case HPSA_LV_ENCRYPTED_NO_KEY:
3191 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3192 case HPSA_LV_UNDERGOING_ENCRYPTION:
3193 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3194 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3195 return ldstat;
3196 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3197 /* If VPD status page isn't available,
3198 * use ASC/ASCQ to determine state
3199 */
3200 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3201 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3202 return ldstat;
3203 break;
3204 default:
3205 break;
3206 }
3207 return 0;
3208}
3209
9b5c48c2
SC		 3210/*
3211 * Find out if a logical device supports aborts by simply trying one.
3212 * Smart Array may claim not to support aborts on logical drives, but
3213 * if a MSA2000 * is connected, the drives on that will be presented
3214 * by the Smart Array as logical drives, and aborts may be sent to
3215 * those devices successfully. So the simplest way to find out is
3216 * to simply try an abort and see how the device responds.
3217 */
3218static int hpsa_device_supports_aborts(struct ctlr_info *h,
3219 unsigned char *scsi3addr)
3220{
3221 struct CommandList *c;
3222 struct ErrorInfo *ei;
3223 int rc = 0;
3224
3225 u64 tag = (u64) -1; /* bogus tag */
3226
3227 /* Assume that physical devices support aborts */
3228 if (!is_logical_dev_addr_mode(scsi3addr))
3229 return 1;
3230
3231 c = cmd_alloc(h);
bf43caf3 3232
9b5c48c2
SC		 3233 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3234 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3235 /* no unmap needed here because no data xfer. */
3236 ei = c->err_info;
3237 switch (ei->CommandStatus) {
3238 case CMD_INVALID:
3239 rc = 0;
3240 break;
3241 case CMD_UNABORTABLE:
3242 case CMD_ABORT_FAILED:
3243 rc = 1;
3244 break;
9437ac43
SC		 3245 case CMD_TMF_STATUS:
3246 rc = hpsa_evaluate_tmf_status(h, c);
3247 break;
9b5c48c2
SC		 3248 default:
3249 rc = 0;
3250 break;
3251 }
3252 cmd_free(h, c);
3253 return rc;
3254}
3255
edd16368 3256static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3257 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3258 unsigned char *is_OBDR_device)
edd16368 3259{
0b0e1d6c
SC		 3260
3261#define OBDR_SIG_OFFSET 43
3262#define OBDR_TAPE_SIG "$DR-10"
3263#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3264#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3265
ea6d3bc3 3266 unsigned char *inq_buff;
0b0e1d6c 3267 unsigned char *obdr_sig;
edd16368 3268
ea6d3bc3 3269 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3270 if (!inq_buff)
3271 goto bail_out;
3272
edd16368
SC		 3273 /* Do an inquiry to the device to see what it is. */
3274 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3275 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3276 /* Inquiry failed (msg printed already) */
3277 dev_err(&h->pdev->dev,
3278 "hpsa_update_device_info: inquiry failed\n");
3279 goto bail_out;
3280 }
3281
edd16368
SC		 3282 this_device->devtype = (inq_buff[0] & 0x1f);
3283 memcpy(this_device->scsi3addr, scsi3addr, 8);
3284 memcpy(this_device->vendor, &inq_buff[8],
3285 sizeof(this_device->vendor));
3286 memcpy(this_device->model, &inq_buff[16],
3287 sizeof(this_device->model));
edd16368
SC		 3288 memset(this_device->device_id, 0,
3289 sizeof(this_device->device_id));
3290 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3291 sizeof(this_device->device_id));
3292
3293 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3294 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3295 int volume_offline;
3296
edd16368 3297 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3298 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3299 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3300 volume_offline = hpsa_volume_offline(h, scsi3addr);
3301 if (volume_offline < 0 || volume_offline > 0xff)
3302 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3303 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3304 } else {
edd16368 3305 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3306 this_device->offload_config = 0;
3307 this_device->offload_enabled = 0;
41ce4c35 3308 this_device->offload_to_be_enabled = 0;
a3144e0b 3309 this_device->hba_ioaccel_enabled = 0;
9846590e 3310 this_device->volume_offline = 0;
03383736 3311 this_device->queue_depth = h->nr_cmds;
283b4a9b 3312 }
edd16368 3313
0b0e1d6c
SC		 3314 if (is_OBDR_device) {
3315 /* See if this is a One-Button-Disaster-Recovery device
3316 * by looking for "$DR-10" at offset 43 in inquiry data.
3317 */
3318 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3319 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3320 strncmp(obdr_sig, OBDR_TAPE_SIG,
3321 OBDR_SIG_LEN) == 0);
3322 }
edd16368
SC		 3323 kfree(inq_buff);
3324 return 0;
3325
3326bail_out:
3327 kfree(inq_buff);
3328 return 1;
3329}
3330
9b5c48c2
SC		 3331static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3332 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3333{
3334 unsigned long flags;
3335 int rc, entry;
3336 /*
3337 * See if this device supports aborts. If we already know
3338 * the device, we already know if it supports aborts, otherwise
3339 * we have to find out if it supports aborts by trying one.
3340 */
3341 spin_lock_irqsave(&h->devlock, flags);
3342 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3343 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3344 entry >= 0 && entry < h->ndevices) {
3345 dev->supports_aborts = h->dev[entry]->supports_aborts;
3346 spin_unlock_irqrestore(&h->devlock, flags);
3347 } else {
3348 spin_unlock_irqrestore(&h->devlock, flags);
3349 dev->supports_aborts =
3350 hpsa_device_supports_aborts(h, scsi3addr);
3351 if (dev->supports_aborts < 0)
3352 dev->supports_aborts = 0;
3353 }
3354}
3355
4f4eb9f1 3356static unsigned char *ext_target_model[] = {
edd16368
SC		 3357 "MSA2012",
3358 "MSA2024",
3359 "MSA2312",
3360 "MSA2324",
fda38518 3361 "P2000 G3 SAS",
e06c8e5c 3362 "MSA 2040 SAS",
edd16368
SC		 3363 NULL,
3364};
3365
4f4eb9f1 3366static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3367{
3368 int i;
3369
4f4eb9f1
ST		 3370 for (i = 0; ext_target_model[i]; i++)
3371 if (strncmp(device->model, ext_target_model[i],
3372 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3373 return 1;
3374 return 0;
3375}
3376
3377/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3378 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3379 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3380 * Logical drive target and lun are assigned at this time, but
3381 * physical device lun and target assignment are deferred (assigned
3382 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3383 */
3384static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3385 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3386{
1f310bde
SC		 3387 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3388
3389 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3390 /* physical device, target and lun filled in later */
edd16368 3391 if (is_hba_lunid(lunaddrbytes))
1f310bde 3392 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3393 else
1f310bde
SC		 3394 /* defer target, lun assignment for physical devices */
3395 hpsa_set_bus_target_lun(device, 2, -1, -1);
3396 return;
3397 }
3398 /* It's a logical device */
4f4eb9f1
ST		 3399 if (is_ext_target(h, device)) {
3400 /* external target way, put logicals on bus 1
1f310bde
SC		 3401 * and match target/lun numbers box
3402 * reports, other smart array, bus 0, target 0, match lunid
3403 */
3404 hpsa_set_bus_target_lun(device,
3405 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3406 return;
edd16368 3407 }
1f310bde 3408 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3409}
3410
3411/*
3412 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3413 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3414 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3415 * it for some reason. *tmpdevice is the target we're adding,
3416 * this_device is a pointer into the current element of currentsd[]
3417 * that we're building up in update_scsi_devices(), below.
3418 * lunzerobits is a bitmap that tracks which targets already have a
3419 * lun 0 assigned.
3420 * Returns 1 if an enclosure was added, 0 if not.
3421 */
4f4eb9f1 3422static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3423 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3424 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3425 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3426{
3427 unsigned char scsi3addr[8];
3428
1f310bde 3429 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3430 return 0; /* There is already a lun 0 on this target. */
3431
3432 if (!is_logical_dev_addr_mode(lunaddrbytes))
3433 return 0; /* It's the logical targets that may lack lun 0. */
3434
4f4eb9f1
ST		 3435 if (!is_ext_target(h, tmpdevice))
3436 return 0; /* Only external target devices have this problem. */
edd16368 3437
1f310bde 3438 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3439 return 0;
3440
c4f8a299 3441 memset(scsi3addr, 0, 8);
1f310bde 3442 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3443 if (is_hba_lunid(scsi3addr))
3444 return 0; /* Don't add the RAID controller here. */
3445
339b2b14
SC		 3446 if (is_scsi_rev_5(h))
3447 return 0; /* p1210m doesn't need to do this. */
3448
4f4eb9f1 3449 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3450 dev_warn(&h->pdev->dev, "Maximum number of external "
3451 "target devices exceeded. Check your hardware "
edd16368
SC		 3452 "configuration.");
3453 return 0;
3454 }
3455
0b0e1d6c 3456 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3457 return 0;
4f4eb9f1 3458 (*n_ext_target_devs)++;
1f310bde
SC		 3459 hpsa_set_bus_target_lun(this_device,
3460 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3461 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3462 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3463 return 1;
3464}
3465
54b6e9e9
ST		 3466/*
3467 * Get address of physical disk used for an ioaccel2 mode command:
3468 * 1. Extract ioaccel2 handle from the command.
3469 * 2. Find a matching ioaccel2 handle from list of physical disks.
3470 * 3. Return:
3471 * 1 and set scsi3addr to address of matching physical
3472 * 0 if no matching physical disk was found.
3473 */
3474static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3475 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3476{
41ce4c35
SC		 3477 struct io_accel2_cmd *c2 =
3478 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3479 unsigned long flags;
54b6e9e9 3480 int i;
54b6e9e9 3481
41ce4c35
SC		 3482 spin_lock_irqsave(&h->devlock, flags);
3483 for (i = 0; i < h->ndevices; i++)
3484 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3485 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3486 sizeof(h->dev[i]->scsi3addr));
3487 spin_unlock_irqrestore(&h->devlock, flags);
3488 return 1;
3489 }
3490 spin_unlock_irqrestore(&h->devlock, flags);
3491 return 0;
54b6e9e9 3492}
41ce4c35 3493
edd16368
SC		 3494/*
3495 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3496 * logdev. The number of luns in physdev and logdev are returned in
3497 * *nphysicals and *nlogicals, respectively.
3498 * Returns 0 on success, -1 otherwise.
3499 */
3500static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3501 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3502 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3503{
03383736 3504 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3505 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3506 return -1;
3507 }
03383736 3508 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3509 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3510 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3511 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3512 *nphysicals = HPSA_MAX_PHYS_LUN;
3513 }
03383736 3514 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3515 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3516 return -1;
3517 }
6df1e954 3518 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3519 /* Reject Logicals in excess of our max capability. */
3520 if (*nlogicals > HPSA_MAX_LUN) {
3521 dev_warn(&h->pdev->dev,
3522 "maximum logical LUNs (%d) exceeded. "
3523 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3524 *nlogicals - HPSA_MAX_LUN);
3525 *nlogicals = HPSA_MAX_LUN;
3526 }
3527 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3528 dev_warn(&h->pdev->dev,
3529 "maximum logical + physical LUNs (%d) exceeded. "
3530 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3531 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3532 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3533 }
3534 return 0;
3535}
3536
42a91641
DB		 3537static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3538 int i, int nphysicals, int nlogicals,
a93aa1fe 3539 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3540 struct ReportLUNdata *logdev_list)
3541{
3542 /* Helper function, figure out where the LUN ID info is coming from
3543 * given index i, lists of physical and logical devices, where in
3544 * the list the raid controller is supposed to appear (first or last)
3545 */
3546
3547 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3548 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3549
3550 if (i == raid_ctlr_position)
3551 return RAID_CTLR_LUNID;
3552
3553 if (i < logicals_start)
d5b5d964
SC		 3554 return &physdev_list->LUN[i -
3555 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3556
3557 if (i < last_device)
3558 return &logdev_list->LUN[i - nphysicals -
3559 (raid_ctlr_position == 0)][0];
3560 BUG();
3561 return NULL;
3562}
3563
316b221a
SC		 3564static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3565{
3566 int rc;
6e8e8088 3567 int hba_mode_enabled;
316b221a
SC		 3568 struct bmic_controller_parameters *ctlr_params;
3569 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3570 GFP_KERNEL);
3571
3572 if (!ctlr_params)
96444fbb 3573 return -ENOMEM;
316b221a
SC		 3574 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3575 sizeof(struct bmic_controller_parameters));
96444fbb 3576 if (rc) {
316b221a 3577 kfree(ctlr_params);
96444fbb 3578 return rc;
316b221a 3579 }
6e8e8088
JH		 3580
3581 hba_mode_enabled =
3582 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3583 kfree(ctlr_params);
3584 return hba_mode_enabled;
316b221a
SC		 3585}
3586
03383736
DB		 3587/* get physical drive ioaccel handle and queue depth */
3588static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3589 struct hpsa_scsi_dev_t *dev,
3590 u8 *lunaddrbytes,
3591 struct bmic_identify_physical_device *id_phys)
3592{
3593 int rc;
3594 struct ext_report_lun_entry *rle =
3595 (struct ext_report_lun_entry *) lunaddrbytes;
3596
3597 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3598 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3599 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3600 memset(id_phys, 0, sizeof(*id_phys));
3601 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3602 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3603 sizeof(*id_phys));
3604 if (!rc)
3605 /* Reserve space for FW operations */
3606#define DRIVE_CMDS_RESERVED_FOR_FW 2
3607#define DRIVE_QUEUE_DEPTH 7
3608 dev->queue_depth =
3609 le16_to_cpu(id_phys->current_queue_depth_limit) -
3610 DRIVE_CMDS_RESERVED_FOR_FW;
3611 else
3612 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3613 atomic_set(&dev->ioaccel_cmds_out, 0);
d604f533 3614 atomic_set(&dev->reset_cmds_out, 0);
03383736
DB		 3615}
3616
edd16368
SC		 3617static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3618{
3619 /* the idea here is we could get notified
3620 * that some devices have changed, so we do a report
3621 * physical luns and report logical luns cmd, and adjust
3622 * our list of devices accordingly.
3623 *
3624 * The scsi3addr's of devices won't change so long as the
3625 * adapter is not reset. That means we can rescan and
3626 * tell which devices we already know about, vs. new
3627 * devices, vs. disappearing devices.
3628 */
a93aa1fe 3629 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3630 struct ReportLUNdata *logdev_list = NULL;
03383736 3631 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3632 u32 nphysicals = 0;
3633 u32 nlogicals = 0;
3634 u32 ndev_allocated = 0;
edd16368
SC		 3635 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3636 int ncurrent = 0;
4f4eb9f1 3637 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3638 int raid_ctlr_position;
2bbf5c7f 3639 int rescan_hba_mode;
aca4a520 3640 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3641
cfe5badc 3642 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3643 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3644 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3645 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3646 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3647
03383736
DB		 3648 if (!currentsd || !physdev_list || !logdev_list ||
3649 !tmpdevice || !id_phys) {
edd16368
SC		 3650 dev_err(&h->pdev->dev, "out of memory\n");
3651 goto out;
3652 }
3653 memset(lunzerobits, 0, sizeof(lunzerobits));
3654
316b221a 3655 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3656 if (rescan_hba_mode < 0)
3657 goto out;
316b221a
SC		 3658
3659 if (!h->hba_mode_enabled && rescan_hba_mode)
3660 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3661 else if (h->hba_mode_enabled && !rescan_hba_mode)
3662 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3663
3664 h->hba_mode_enabled = rescan_hba_mode;
3665
03383736
DB		 3666 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3667 logdev_list, &nlogicals))
edd16368
SC		 3668 goto out;
3669
aca4a520
ST		 3670 /* We might see up to the maximum number of logical and physical disks
3671 * plus external target devices, and a device for the local RAID
3672 * controller.
edd16368 3673 */
aca4a520 3674 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3675
3676 /* Allocate the per device structures */
3677 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3678 if (i >= HPSA_MAX_DEVICES) {
3679 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3680 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3681 ndevs_to_allocate - HPSA_MAX_DEVICES);
3682 break;
3683 }
3684
edd16368
SC		 3685 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3686 if (!currentsd[i]) {
3687 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3688 __FILE__, __LINE__);
3689 goto out;
3690 }
3691 ndev_allocated++;
3692 }
3693
8645291b 3694 if (is_scsi_rev_5(h))
339b2b14
SC		 3695 raid_ctlr_position = 0;
3696 else
3697 raid_ctlr_position = nphysicals + nlogicals;
3698
edd16368 3699 /* adjust our table of devices */
4f4eb9f1 3700 n_ext_target_devs = 0;
edd16368 3701 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3702 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3703
3704 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3705 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3706 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3707
3708 /* skip masked non-disk devices */
3709 if (MASKED_DEVICE(lunaddrbytes))
3710 if (i < nphysicals + (raid_ctlr_position == 0) &&
3711 NON_DISK_PHYS_DEV(lunaddrbytes))
3712 continue;
edd16368
SC		 3713
3714 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3715 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3716 &is_OBDR))
edd16368 3717 continue; /* skip it if we can't talk to it. */
1f310bde 3718 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3719 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3720 this_device = currentsd[ncurrent];
3721
3722 /*
4f4eb9f1 3723 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3724 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3725 * is nonetheless an enclosure device there. We have to
3726 * present that otherwise linux won't find anything if
3727 * there is no lun 0.
3728 */
4f4eb9f1 3729 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3730 lunaddrbytes, lunzerobits,
4f4eb9f1 3731 &n_ext_target_devs)) {
edd16368
SC		 3732 ncurrent++;
3733 this_device = currentsd[ncurrent];
3734 }
3735
3736 *this_device = *tmpdevice;
edd16368 3737
41ce4c35
SC		 3738 /* do not expose masked devices */
3739 if (MASKED_DEVICE(lunaddrbytes) &&
3740 i < nphysicals + (raid_ctlr_position == 0)) {
3741 if (h->hba_mode_enabled)
3742 dev_warn(&h->pdev->dev,
3743 "Masked physical device detected\n");
3744 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3745 } else {
3746 this_device->expose_state =
3747 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3748 }
3749
edd16368 3750 switch (this_device->devtype) {
0b0e1d6c 3751 case TYPE_ROM:
edd16368
SC		 3752 /* We don't *really* support actual CD-ROM devices,
3753 * just "One Button Disaster Recovery" tape drive
3754 * which temporarily pretends to be a CD-ROM drive.
3755 * So we check that the device is really an OBDR tape
3756 * device by checking for "$DR-10" in bytes 43-48 of
3757 * the inquiry data.
3758 */
0b0e1d6c
SC		 3759 if (is_OBDR)
3760 ncurrent++;
edd16368
SC		 3761 break;
3762 case TYPE_DISK:
ecf418d1 3763 if (i >= nphysicals) {
316b221a
SC		 3764 ncurrent++;
3765 break;
283b4a9b 3766 }
ecf418d1
JH		 3767
3768 if (h->hba_mode_enabled)
3769 /* never use raid mapper in HBA mode */
3770 this_device->offload_enabled = 0;
3771 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3772 h->transMethod & CFGTBL_Trans_io_accel2))
3773 break;
3774
3775 hpsa_get_ioaccel_drive_info(h, this_device,
3776 lunaddrbytes, id_phys);
3777 atomic_set(&this_device->ioaccel_cmds_out, 0);
3778 ncurrent++;
edd16368
SC		 3779 break;
3780 case TYPE_TAPE:
3781 case TYPE_MEDIUM_CHANGER:
3782 ncurrent++;
3783 break;
41ce4c35
SC		 3784 case TYPE_ENCLOSURE:
3785 if (h->hba_mode_enabled)
3786 ncurrent++;
3787 break;
edd16368
SC		 3788 case TYPE_RAID:
3789 /* Only present the Smartarray HBA as a RAID controller.
3790 * If it's a RAID controller other than the HBA itself
3791 * (an external RAID controller, MSA500 or similar)
3792 * don't present it.
3793 */
3794 if (!is_hba_lunid(lunaddrbytes))
3795 break;
3796 ncurrent++;
3797 break;
3798 default:
3799 break;
3800 }
cfe5badc 3801 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3802 break;
3803 }
3804 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3805out:
3806 kfree(tmpdevice);
3807 for (i = 0; i < ndev_allocated; i++)
3808 kfree(currentsd[i]);
3809 kfree(currentsd);
edd16368
SC		 3810 kfree(physdev_list);
3811 kfree(logdev_list);
03383736 3812 kfree(id_phys);
edd16368
SC		 3813}
3814
ec5cbf04
WS		 3815static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3816 struct scatterlist *sg)
3817{
3818 u64 addr64 = (u64) sg_dma_address(sg);
3819 unsigned int len = sg_dma_len(sg);
3820
3821 desc->Addr = cpu_to_le64(addr64);
3822 desc->Len = cpu_to_le32(len);
3823 desc->Ext = 0;
3824}
3825
c7ee65b3
WS		 3826/*
3827 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3828 * dma mapping and fills in the scatter gather entries of the
3829 * hpsa command, cp.
3830 */
33a2ffce 3831static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3832 struct CommandList *cp,
3833 struct scsi_cmnd *cmd)
3834{
edd16368 3835 struct scatterlist *sg;
b3a7ba7c 3836 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3837 struct SGDescriptor *curr_sg;
edd16368 3838
33a2ffce 3839 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3840
3841 use_sg = scsi_dma_map(cmd);
3842 if (use_sg < 0)
3843 return use_sg;
3844
3845 if (!use_sg)
3846 goto sglist_finished;
3847
b3a7ba7c
WS		 3848 /*
3849 * If the number of entries is greater than the max for a single list,
3850 * then we have a chained list; we will set up all but one entry in the
3851 * first list (the last entry is saved for link information);
3852 * otherwise, we don't have a chained list and we'll set up at each of
3853 * the entries in the one list.
3854 */
33a2ffce 3855 curr_sg = cp->SG;
b3a7ba7c
WS		 3856 chained = use_sg > h->max_cmd_sg_entries;
3857 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3858 last_sg = scsi_sg_count(cmd) - 1;
3859 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3860 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3861 curr_sg++;
3862 }
ec5cbf04 3863
b3a7ba7c
WS		 3864 if (chained) {
3865 /*
3866 * Continue with the chained list. Set curr_sg to the chained
3867 * list. Modify the limit to the total count less the entries
3868 * we've already set up. Resume the scan at the list entry
3869 * where the previous loop left off.
3870 */
3871 curr_sg = h->cmd_sg_list[cp->cmdindex];
3872 sg_limit = use_sg - sg_limit;
3873 for_each_sg(sg, sg, sg_limit, i) {
3874 hpsa_set_sg_descriptor(curr_sg, sg);
3875 curr_sg++;
3876 }
3877 }
3878
ec5cbf04 3879 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3880 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3881
3882 if (use_sg + chained > h->maxSG)
3883 h->maxSG = use_sg + chained;
3884
3885 if (chained) {
3886 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3887 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3888 if (hpsa_map_sg_chain_block(h, cp)) {
3889 scsi_dma_unmap(cmd);
3890 return -1;
3891 }
33a2ffce 3892 return 0;
edd16368
SC		 3893 }
3894
3895sglist_finished:
3896
01a02ffc 3897 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3898 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3899 return 0;
3900}
3901
283b4a9b
SC		 3902#define IO_ACCEL_INELIGIBLE (1)
3903static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3904{
3905 int is_write = 0;
3906 u32 block;
3907 u32 block_cnt;
3908
3909 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3910 switch (cdb[0]) {
3911 case WRITE_6:
3912 case WRITE_12:
3913 is_write = 1;
3914 case READ_6:
3915 case READ_12:
3916 if (*cdb_len == 6) {
3917 block = (((u32) cdb[2]) << 8) | cdb[3];
3918 block_cnt = cdb[4];
3919 } else {
3920 BUG_ON(*cdb_len != 12);
3921 block = (((u32) cdb[2]) << 24) |
3922 (((u32) cdb[3]) << 16) |
3923 (((u32) cdb[4]) << 8) |
3924 cdb[5];
3925 block_cnt =
3926 (((u32) cdb[6]) << 24) |
3927 (((u32) cdb[7]) << 16) |
3928 (((u32) cdb[8]) << 8) |
3929 cdb[9];
3930 }
3931 if (block_cnt > 0xffff)
3932 return IO_ACCEL_INELIGIBLE;
3933
3934 cdb[0] = is_write ? WRITE_10 : READ_10;
3935 cdb[1] = 0;
3936 cdb[2] = (u8) (block >> 24);
3937 cdb[3] = (u8) (block >> 16);
3938 cdb[4] = (u8) (block >> 8);
3939 cdb[5] = (u8) (block);
3940 cdb[6] = 0;
3941 cdb[7] = (u8) (block_cnt >> 8);
3942 cdb[8] = (u8) (block_cnt);
3943 cdb[9] = 0;
3944 *cdb_len = 10;
3945 break;
3946 }
3947 return 0;
3948}
3949
c349775e 3950static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3951 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3952 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3953{
3954 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3955 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3956 unsigned int len;
3957 unsigned int total_len = 0;
3958 struct scatterlist *sg;
3959 u64 addr64;
3960 int use_sg, i;
3961 struct SGDescriptor *curr_sg;
3962 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3963
283b4a9b 3964 /* TODO: implement chaining support */
03383736
DB		 3965 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3966 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3967 return IO_ACCEL_INELIGIBLE;
03383736 3968 }
283b4a9b 3969
e1f7de0c
MG		 3970 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3971
03383736
DB		 3972 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3973 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3974 return IO_ACCEL_INELIGIBLE;
03383736 3975 }
283b4a9b 3976
e1f7de0c
MG		 3977 c->cmd_type = CMD_IOACCEL1;
3978
3979 /* Adjust the DMA address to point to the accelerated command buffer */
3980 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3981 (c->cmdindex * sizeof(*cp));
3982 BUG_ON(c->busaddr & 0x0000007F);
3983
3984 use_sg = scsi_dma_map(cmd);
03383736
DB		 3985 if (use_sg < 0) {
3986 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3987 return use_sg;
03383736 3988 }
e1f7de0c
MG		 3989
3990 if (use_sg) {
3991 curr_sg = cp->SG;
3992 scsi_for_each_sg(cmd, sg, use_sg, i) {
3993 addr64 = (u64) sg_dma_address(sg);
3994 len = sg_dma_len(sg);
3995 total_len += len;
50a0decf
SC		 3996 curr_sg->Addr = cpu_to_le64(addr64);
3997 curr_sg->Len = cpu_to_le32(len);
3998 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3999 curr_sg++;
4000 }
50a0decf 4001 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4002
4003 switch (cmd->sc_data_direction) {
4004 case DMA_TO_DEVICE:
4005 control |= IOACCEL1_CONTROL_DATA_OUT;
4006 break;
4007 case DMA_FROM_DEVICE:
4008 control |= IOACCEL1_CONTROL_DATA_IN;
4009 break;
4010 case DMA_NONE:
4011 control |= IOACCEL1_CONTROL_NODATAXFER;
4012 break;
4013 default:
4014 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4015 cmd->sc_data_direction);
4016 BUG();
4017 break;
4018 }
4019 } else {
4020 control |= IOACCEL1_CONTROL_NODATAXFER;
4021 }
4022
c349775e 4023 c->Header.SGList = use_sg;
e1f7de0c 4024 /* Fill out the command structure to submit */
2b08b3e9
DB		 4025 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4026 cp->transfer_len = cpu_to_le32(total_len);
4027 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4028 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4029 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4030 memcpy(cp->CDB, cdb, cdb_len);
4031 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4032 /* Tag was already set at init time. */
283b4a9b 4033 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4034 return 0;
4035}
edd16368 4036
283b4a9b
SC		 4037/*
4038 * Queue a command directly to a device behind the controller using the
4039 * I/O accelerator path.
4040 */
4041static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4042 struct CommandList *c)
4043{
4044 struct scsi_cmnd *cmd = c->scsi_cmd;
4045 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4046
03383736
DB		 4047 c->phys_disk = dev;
4048
283b4a9b 4049 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4050 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4051}
4052
dd0e19f3
ST		 4053/*
4054 * Set encryption parameters for the ioaccel2 request
4055 */
4056static void set_encrypt_ioaccel2(struct ctlr_info *h,
4057 struct CommandList *c, struct io_accel2_cmd *cp)
4058{
4059 struct scsi_cmnd *cmd = c->scsi_cmd;
4060 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4061 struct raid_map_data *map = &dev->raid_map;
4062 u64 first_block;
4063
dd0e19f3 4064 /* Are we doing encryption on this device */
2b08b3e9 4065 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4066 return;
4067 /* Set the data encryption key index. */
4068 cp->dekindex = map->dekindex;
4069
4070 /* Set the encryption enable flag, encoded into direction field. */
4071 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4072
4073 /* Set encryption tweak values based on logical block address
4074 * If block size is 512, tweak value is LBA.
4075 * For other block sizes, tweak is (LBA * block size)/ 512)
4076 */
4077 switch (cmd->cmnd[0]) {
4078 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4079 case WRITE_6:
4080 case READ_6:
2b08b3e9 4081 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4082 break;
4083 case WRITE_10:
4084 case READ_10:
dd0e19f3
ST		 4085 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4086 case WRITE_12:
4087 case READ_12:
2b08b3e9 4088 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4089 break;
4090 case WRITE_16:
4091 case READ_16:
2b08b3e9 4092 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4093 break;
4094 default:
4095 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4096 "ERROR: %s: size (0x%x) not supported for encryption\n",
4097 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4098 BUG();
4099 break;
4100 }
2b08b3e9
DB		 4101
4102 if (le32_to_cpu(map->volume_blk_size) != 512)
4103 first_block = first_block *
4104 le32_to_cpu(map->volume_blk_size)/512;
4105
4106 cp->tweak_lower = cpu_to_le32(first_block);
4107 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4108}
4109
c349775e
ST		 4110static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4111 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4112 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4113{
4114 struct scsi_cmnd *cmd = c->scsi_cmd;
4115 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4116 struct ioaccel2_sg_element *curr_sg;
4117 int use_sg, i;
4118 struct scatterlist *sg;
4119 u64 addr64;
4120 u32 len;
4121 u32 total_len = 0;
4122
d9a729f3 4123 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4124
03383736
DB		 4125 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4126 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4127 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4128 }
4129
c349775e
ST		 4130 c->cmd_type = CMD_IOACCEL2;
4131 /* Adjust the DMA address to point to the accelerated command buffer */
4132 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4133 (c->cmdindex * sizeof(*cp));
4134 BUG_ON(c->busaddr & 0x0000007F);
4135
4136 memset(cp, 0, sizeof(*cp));
4137 cp->IU_type = IOACCEL2_IU_TYPE;
4138
4139 use_sg = scsi_dma_map(cmd);
03383736
DB		 4140 if (use_sg < 0) {
4141 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4142 return use_sg;
03383736 4143 }
c349775e
ST		 4144
4145 if (use_sg) {
c349775e 4146 curr_sg = cp->sg;
d9a729f3
WS		 4147 if (use_sg > h->ioaccel_maxsg) {
4148 addr64 = le64_to_cpu(
4149 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4150 curr_sg->address = cpu_to_le64(addr64);
4151 curr_sg->length = 0;
4152 curr_sg->reserved[0] = 0;
4153 curr_sg->reserved[1] = 0;
4154 curr_sg->reserved[2] = 0;
4155 curr_sg->chain_indicator = 0x80;
4156
4157 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4158 }
c349775e
ST		 4159 scsi_for_each_sg(cmd, sg, use_sg, i) {
4160 addr64 = (u64) sg_dma_address(sg);
4161 len = sg_dma_len(sg);
4162 total_len += len;
4163 curr_sg->address = cpu_to_le64(addr64);
4164 curr_sg->length = cpu_to_le32(len);
4165 curr_sg->reserved[0] = 0;
4166 curr_sg->reserved[1] = 0;
4167 curr_sg->reserved[2] = 0;
4168 curr_sg->chain_indicator = 0;
4169 curr_sg++;
4170 }
4171
4172 switch (cmd->sc_data_direction) {
4173 case DMA_TO_DEVICE:
dd0e19f3
ST		 4174 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4175 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4176 break;
4177 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4178 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4179 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4180 break;
4181 case DMA_NONE:
dd0e19f3
ST		 4182 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4183 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4184 break;
4185 default:
4186 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4187 cmd->sc_data_direction);
4188 BUG();
4189 break;
4190 }
4191 } else {
dd0e19f3
ST		 4192 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4193 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4194 }
dd0e19f3
ST		 4195
4196 /* Set encryption parameters, if necessary */
4197 set_encrypt_ioaccel2(h, c, cp);
4198
2b08b3e9 4199 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4200 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4201 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4202
c349775e
ST		 4203 cp->data_len = cpu_to_le32(total_len);
4204 cp->err_ptr = cpu_to_le64(c->busaddr +
4205 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4206 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4207
d9a729f3
WS		 4208 /* fill in sg elements */
4209 if (use_sg > h->ioaccel_maxsg) {
4210 cp->sg_count = 1;
4211 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4212 atomic_dec(&phys_disk->ioaccel_cmds_out);
4213 scsi_dma_unmap(cmd);
4214 return -1;
4215 }
4216 } else
4217 cp->sg_count = (u8) use_sg;
4218
c349775e
ST		 4219 enqueue_cmd_and_start_io(h, c);
4220 return 0;
4221}
4222
4223/*
4224 * Queue a command to the correct I/O accelerator path.
4225 */
4226static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4227 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4228 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4229{
03383736
DB		 4230 /* Try to honor the device's queue depth */
4231 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4232 phys_disk->queue_depth) {
4233 atomic_dec(&phys_disk->ioaccel_cmds_out);
4234 return IO_ACCEL_INELIGIBLE;
4235 }
c349775e
ST		 4236 if (h->transMethod & CFGTBL_Trans_io_accel1)
4237 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4238 cdb, cdb_len, scsi3addr,
4239 phys_disk);
c349775e
ST		 4240 else
4241 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4242 cdb, cdb_len, scsi3addr,
4243 phys_disk);
c349775e
ST		 4244}
4245
6b80b18f
ST		 4246static void raid_map_helper(struct raid_map_data *map,
4247 int offload_to_mirror, u32 *map_index, u32 *current_group)
4248{
4249 if (offload_to_mirror == 0) {
4250 /* use physical disk in the first mirrored group. */
2b08b3e9 4251 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4252 return;
4253 }
4254 do {
4255 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4256 *current_group = *map_index /
4257 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4258 if (offload_to_mirror == *current_group)
4259 continue;
2b08b3e9 4260 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4261 /* select map index from next group */
2b08b3e9 4262 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4263 (*current_group)++;
4264 } else {
4265 /* select map index from first group */
2b08b3e9 4266 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4267 *current_group = 0;
4268 }
4269 } while (offload_to_mirror != *current_group);
4270}
4271
283b4a9b
SC		 4272/*
4273 * Attempt to perform offload RAID mapping for a logical volume I/O.
4274 */
4275static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4276 struct CommandList *c)
4277{
4278 struct scsi_cmnd *cmd = c->scsi_cmd;
4279 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4280 struct raid_map_data *map = &dev->raid_map;
4281 struct raid_map_disk_data *dd = &map->data[0];
4282 int is_write = 0;
4283 u32 map_index;
4284 u64 first_block, last_block;
4285 u32 block_cnt;
4286 u32 blocks_per_row;
4287 u64 first_row, last_row;
4288 u32 first_row_offset, last_row_offset;
4289 u32 first_column, last_column;
6b80b18f
ST		 4290 u64 r0_first_row, r0_last_row;
4291 u32 r5or6_blocks_per_row;
4292 u64 r5or6_first_row, r5or6_last_row;
4293 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4294 u32 r5or6_first_column, r5or6_last_column;
4295 u32 total_disks_per_row;
4296 u32 stripesize;
4297 u32 first_group, last_group, current_group;
283b4a9b
SC		 4298 u32 map_row;
4299 u32 disk_handle;
4300 u64 disk_block;
4301 u32 disk_block_cnt;
4302 u8 cdb[16];
4303 u8 cdb_len;
2b08b3e9 4304 u16 strip_size;
283b4a9b
SC		 4305#if BITS_PER_LONG == 32
4306 u64 tmpdiv;
4307#endif
6b80b18f 4308 int offload_to_mirror;
283b4a9b 4309
283b4a9b
SC		 4310 /* check for valid opcode, get LBA and block count */
4311 switch (cmd->cmnd[0]) {
4312 case WRITE_6:
4313 is_write = 1;
4314 case READ_6:
4315 first_block =
4316 (((u64) cmd->cmnd[2]) << 8) |
4317 cmd->cmnd[3];
4318 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4319 if (block_cnt == 0)
4320 block_cnt = 256;
283b4a9b
SC		 4321 break;
4322 case WRITE_10:
4323 is_write = 1;
4324 case READ_10:
4325 first_block =
4326 (((u64) cmd->cmnd[2]) << 24) |
4327 (((u64) cmd->cmnd[3]) << 16) |
4328 (((u64) cmd->cmnd[4]) << 8) |
4329 cmd->cmnd[5];
4330 block_cnt =
4331 (((u32) cmd->cmnd[7]) << 8) |
4332 cmd->cmnd[8];
4333 break;
4334 case WRITE_12:
4335 is_write = 1;
4336 case READ_12:
4337 first_block =
4338 (((u64) cmd->cmnd[2]) << 24) |
4339 (((u64) cmd->cmnd[3]) << 16) |
4340 (((u64) cmd->cmnd[4]) << 8) |
4341 cmd->cmnd[5];
4342 block_cnt =
4343 (((u32) cmd->cmnd[6]) << 24) |
4344 (((u32) cmd->cmnd[7]) << 16) |
4345 (((u32) cmd->cmnd[8]) << 8) |
4346 cmd->cmnd[9];
4347 break;
4348 case WRITE_16:
4349 is_write = 1;
4350 case READ_16:
4351 first_block =
4352 (((u64) cmd->cmnd[2]) << 56) |
4353 (((u64) cmd->cmnd[3]) << 48) |
4354 (((u64) cmd->cmnd[4]) << 40) |
4355 (((u64) cmd->cmnd[5]) << 32) |
4356 (((u64) cmd->cmnd[6]) << 24) |
4357 (((u64) cmd->cmnd[7]) << 16) |
4358 (((u64) cmd->cmnd[8]) << 8) |
4359 cmd->cmnd[9];
4360 block_cnt =
4361 (((u32) cmd->cmnd[10]) << 24) |
4362 (((u32) cmd->cmnd[11]) << 16) |
4363 (((u32) cmd->cmnd[12]) << 8) |
4364 cmd->cmnd[13];
4365 break;
4366 default:
4367 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4368 }
283b4a9b
SC		 4369 last_block = first_block + block_cnt - 1;
4370
4371 /* check for write to non-RAID-0 */
4372 if (is_write && dev->raid_level != 0)
4373 return IO_ACCEL_INELIGIBLE;
4374
4375 /* check for invalid block or wraparound */
2b08b3e9
DB		 4376 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4377 last_block < first_block)
283b4a9b
SC		 4378 return IO_ACCEL_INELIGIBLE;
4379
4380 /* calculate stripe information for the request */
2b08b3e9
DB		 4381 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4382 le16_to_cpu(map->strip_size);
4383 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4384#if BITS_PER_LONG == 32
4385 tmpdiv = first_block;
4386 (void) do_div(tmpdiv, blocks_per_row);
4387 first_row = tmpdiv;
4388 tmpdiv = last_block;
4389 (void) do_div(tmpdiv, blocks_per_row);
4390 last_row = tmpdiv;
4391 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4392 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4393 tmpdiv = first_row_offset;
2b08b3e9 4394 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4395 first_column = tmpdiv;
4396 tmpdiv = last_row_offset;
2b08b3e9 4397 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4398 last_column = tmpdiv;
4399#else
4400 first_row = first_block / blocks_per_row;
4401 last_row = last_block / blocks_per_row;
4402 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4403 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4404 first_column = first_row_offset / strip_size;
4405 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4406#endif
4407
4408 /* if this isn't a single row/column then give to the controller */
4409 if ((first_row != last_row) || (first_column != last_column))
4410 return IO_ACCEL_INELIGIBLE;
4411
4412 /* proceeding with driver mapping */
2b08b3e9
DB		 4413 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4414 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4415 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4416 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4417 map_index = (map_row * total_disks_per_row) + first_column;
4418
4419 switch (dev->raid_level) {
4420 case HPSA_RAID_0:
4421 break; /* nothing special to do */
4422 case HPSA_RAID_1:
4423 /* Handles load balance across RAID 1 members.
4424 * (2-drive R1 and R10 with even # of drives.)
4425 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4426 */
2b08b3e9 4427 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4428 if (dev->offload_to_mirror)
2b08b3e9 4429 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4430 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4431 break;
4432 case HPSA_RAID_ADM:
4433 /* Handles N-way mirrors (R1-ADM)
4434 * and R10 with # of drives divisible by 3.)
4435 */
2b08b3e9 4436 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4437
4438 offload_to_mirror = dev->offload_to_mirror;
4439 raid_map_helper(map, offload_to_mirror,
4440 &map_index, &current_group);
4441 /* set mirror group to use next time */
4442 offload_to_mirror =
2b08b3e9
DB		 4443 (offload_to_mirror >=
4444 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4445 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4446 dev->offload_to_mirror = offload_to_mirror;
4447 /* Avoid direct use of dev->offload_to_mirror within this
4448 * function since multiple threads might simultaneously
4449 * increment it beyond the range of dev->layout_map_count -1.
4450 */
4451 break;
4452 case HPSA_RAID_5:
4453 case HPSA_RAID_6:
2b08b3e9 4454 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4455 break;
4456
4457 /* Verify first and last block are in same RAID group */
4458 r5or6_blocks_per_row =
2b08b3e9
DB		 4459 le16_to_cpu(map->strip_size) *
4460 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4461 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4462 stripesize = r5or6_blocks_per_row *
4463 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4464#if BITS_PER_LONG == 32
4465 tmpdiv = first_block;
4466 first_group = do_div(tmpdiv, stripesize);
4467 tmpdiv = first_group;
4468 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4469 first_group = tmpdiv;
4470 tmpdiv = last_block;
4471 last_group = do_div(tmpdiv, stripesize);
4472 tmpdiv = last_group;
4473 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4474 last_group = tmpdiv;
4475#else
4476 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4477 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4478#endif
000ff7c2 4479 if (first_group != last_group)
6b80b18f
ST		 4480 return IO_ACCEL_INELIGIBLE;
4481
4482 /* Verify request is in a single row of RAID 5/6 */
4483#if BITS_PER_LONG == 32
4484 tmpdiv = first_block;
4485 (void) do_div(tmpdiv, stripesize);
4486 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4487 tmpdiv = last_block;
4488 (void) do_div(tmpdiv, stripesize);
4489 r5or6_last_row = r0_last_row = tmpdiv;
4490#else
4491 first_row = r5or6_first_row = r0_first_row =
4492 first_block / stripesize;
4493 r5or6_last_row = r0_last_row = last_block / stripesize;
4494#endif
4495 if (r5or6_first_row != r5or6_last_row)
4496 return IO_ACCEL_INELIGIBLE;
4497
4498
4499 /* Verify request is in a single column */
4500#if BITS_PER_LONG == 32
4501 tmpdiv = first_block;
4502 first_row_offset = do_div(tmpdiv, stripesize);
4503 tmpdiv = first_row_offset;
4504 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4505 r5or6_first_row_offset = first_row_offset;
4506 tmpdiv = last_block;
4507 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4508 tmpdiv = r5or6_last_row_offset;
4509 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4510 tmpdiv = r5or6_first_row_offset;
4511 (void) do_div(tmpdiv, map->strip_size);
4512 first_column = r5or6_first_column = tmpdiv;
4513 tmpdiv = r5or6_last_row_offset;
4514 (void) do_div(tmpdiv, map->strip_size);
4515 r5or6_last_column = tmpdiv;
4516#else
4517 first_row_offset = r5or6_first_row_offset =
4518 (u32)((first_block % stripesize) %
4519 r5or6_blocks_per_row);
4520
4521 r5or6_last_row_offset =
4522 (u32)((last_block % stripesize) %
4523 r5or6_blocks_per_row);
4524
4525 first_column = r5or6_first_column =
2b08b3e9 4526 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4527 r5or6_last_column =
2b08b3e9 4528 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4529#endif
4530 if (r5or6_first_column != r5or6_last_column)
4531 return IO_ACCEL_INELIGIBLE;
4532
4533 /* Request is eligible */
4534 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4535 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4536
4537 map_index = (first_group *
2b08b3e9 4538 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4539 (map_row * total_disks_per_row) + first_column;
4540 break;
4541 default:
4542 return IO_ACCEL_INELIGIBLE;
283b4a9b 4543 }
6b80b18f 4544
07543e0c
SC		 4545 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4546 return IO_ACCEL_INELIGIBLE;
4547
03383736
DB		 4548 c->phys_disk = dev->phys_disk[map_index];
4549
283b4a9b 4550 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4551 disk_block = le64_to_cpu(map->disk_starting_blk) +
4552 first_row * le16_to_cpu(map->strip_size) +
4553 (first_row_offset - first_column *
4554 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4555 disk_block_cnt = block_cnt;
4556
4557 /* handle differing logical/physical block sizes */
4558 if (map->phys_blk_shift) {
4559 disk_block <<= map->phys_blk_shift;
4560 disk_block_cnt <<= map->phys_blk_shift;
4561 }
4562 BUG_ON(disk_block_cnt > 0xffff);
4563
4564 /* build the new CDB for the physical disk I/O */
4565 if (disk_block > 0xffffffff) {
4566 cdb[0] = is_write ? WRITE_16 : READ_16;
4567 cdb[1] = 0;
4568 cdb[2] = (u8) (disk_block >> 56);
4569 cdb[3] = (u8) (disk_block >> 48);
4570 cdb[4] = (u8) (disk_block >> 40);
4571 cdb[5] = (u8) (disk_block >> 32);
4572 cdb[6] = (u8) (disk_block >> 24);
4573 cdb[7] = (u8) (disk_block >> 16);
4574 cdb[8] = (u8) (disk_block >> 8);
4575 cdb[9] = (u8) (disk_block);
4576 cdb[10] = (u8) (disk_block_cnt >> 24);
4577 cdb[11] = (u8) (disk_block_cnt >> 16);
4578 cdb[12] = (u8) (disk_block_cnt >> 8);
4579 cdb[13] = (u8) (disk_block_cnt);
4580 cdb[14] = 0;
4581 cdb[15] = 0;
4582 cdb_len = 16;
4583 } else {
4584 cdb[0] = is_write ? WRITE_10 : READ_10;
4585 cdb[1] = 0;
4586 cdb[2] = (u8) (disk_block >> 24);
4587 cdb[3] = (u8) (disk_block >> 16);
4588 cdb[4] = (u8) (disk_block >> 8);
4589 cdb[5] = (u8) (disk_block);
4590 cdb[6] = 0;
4591 cdb[7] = (u8) (disk_block_cnt >> 8);
4592 cdb[8] = (u8) (disk_block_cnt);
4593 cdb[9] = 0;
4594 cdb_len = 10;
4595 }
4596 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4597 dev->scsi3addr,
4598 dev->phys_disk[map_index]);
283b4a9b
SC		 4599}
4600
25163bd5
WS		 4601/*
4602 * Submit commands down the "normal" RAID stack path
4603 * All callers to hpsa_ciss_submit must check lockup_detected
4604 * beforehand, before (opt.) and after calling cmd_alloc
4605 */
574f05d3
SC		 4606static int hpsa_ciss_submit(struct ctlr_info *h,
4607 struct CommandList *c, struct scsi_cmnd *cmd,
4608 unsigned char scsi3addr[])
edd16368 4609{
edd16368 4610 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4611 c->cmd_type = CMD_SCSI;
4612 c->scsi_cmd = cmd;
4613 c->Header.ReplyQueue = 0; /* unused in simple mode */
4614 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4615 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4616
4617 /* Fill in the request block... */
4618
4619 c->Request.Timeout = 0;
edd16368
SC		 4620 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4621 c->Request.CDBLen = cmd->cmd_len;
4622 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4623 switch (cmd->sc_data_direction) {
4624 case DMA_TO_DEVICE:
a505b86f
SC		 4625 c->Request.type_attr_dir =
4626 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4627 break;
4628 case DMA_FROM_DEVICE:
a505b86f
SC		 4629 c->Request.type_attr_dir =
4630 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4631 break;
4632 case DMA_NONE:
a505b86f
SC		 4633 c->Request.type_attr_dir =
4634 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4635 break;
4636 case DMA_BIDIRECTIONAL:
4637 /* This can happen if a buggy application does a scsi passthru
4638 * and sets both inlen and outlen to non-zero. ( see
4639 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4640 */
4641
a505b86f
SC		 4642 c->Request.type_attr_dir =
4643 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4644 /* This is technically wrong, and hpsa controllers should
4645 * reject it with CMD_INVALID, which is the most correct
4646 * response, but non-fibre backends appear to let it
4647 * slide by, and give the same results as if this field
4648 * were set correctly. Either way is acceptable for
4649 * our purposes here.
4650 */
4651
4652 break;
4653
4654 default:
4655 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4656 cmd->sc_data_direction);
4657 BUG();
4658 break;
4659 }
4660
33a2ffce 4661 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4662 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4663 return SCSI_MLQUEUE_HOST_BUSY;
4664 }
4665 enqueue_cmd_and_start_io(h, c);
4666 /* the cmd'll come back via intr handler in complete_scsi_command() */
4667 return 0;
4668}
4669
360c73bd
SC		 4670static void hpsa_cmd_init(struct ctlr_info *h, int index,
4671 struct CommandList *c)
4672{
4673 dma_addr_t cmd_dma_handle, err_dma_handle;
4674
4675 /* Zero out all of commandlist except the last field, refcount */
4676 memset(c, 0, offsetof(struct CommandList, refcount));
4677 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4678 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4679 c->err_info = h->errinfo_pool + index;
4680 memset(c->err_info, 0, sizeof(*c->err_info));
4681 err_dma_handle = h->errinfo_pool_dhandle
4682 + index * sizeof(*c->err_info);
4683 c->cmdindex = index;
4684 c->busaddr = (u32) cmd_dma_handle;
4685 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4686 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4687 c->h = h;
a58e7e53 4688 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4689}
4690
4691static void hpsa_preinitialize_commands(struct ctlr_info *h)
4692{
4693 int i;
4694
4695 for (i = 0; i < h->nr_cmds; i++) {
4696 struct CommandList *c = h->cmd_pool + i;
4697
4698 hpsa_cmd_init(h, i, c);
4699 atomic_set(&c->refcount, 0);
4700 }
4701}
4702
4703static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4704 struct CommandList *c)
4705{
4706 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4707
73153fe5
WS		 4708 BUG_ON(c->cmdindex != index);
4709
360c73bd
SC		 4710 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4711 memset(c->err_info, 0, sizeof(*c->err_info));
4712 c->busaddr = (u32) cmd_dma_handle;
4713}
4714
592a0ad5
WS		 4715static int hpsa_ioaccel_submit(struct ctlr_info *h,
4716 struct CommandList *c, struct scsi_cmnd *cmd,
4717 unsigned char *scsi3addr)
4718{
4719 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4720 int rc = IO_ACCEL_INELIGIBLE;
4721
4722 cmd->host_scribble = (unsigned char *) c;
4723
4724 if (dev->offload_enabled) {
4725 hpsa_cmd_init(h, c->cmdindex, c);
4726 c->cmd_type = CMD_SCSI;
4727 c->scsi_cmd = cmd;
4728 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4729 if (rc < 0) /* scsi_dma_map failed. */
4730 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4731 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4732 hpsa_cmd_init(h, c->cmdindex, c);
4733 c->cmd_type = CMD_SCSI;
4734 c->scsi_cmd = cmd;
4735 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4736 if (rc < 0) /* scsi_dma_map failed. */
4737 rc = SCSI_MLQUEUE_HOST_BUSY;
4738 }
4739 return rc;
4740}
4741
080ef1cc
DB		 4742static void hpsa_command_resubmit_worker(struct work_struct *work)
4743{
4744 struct scsi_cmnd *cmd;
4745 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4746 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4747
4748 cmd = c->scsi_cmd;
4749 dev = cmd->device->hostdata;
4750 if (!dev) {
4751 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4752 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4753 }
d604f533
WS		 4754 if (c->reset_pending)
4755 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4756 if (c->abort_pending)
4757 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4758 if (c->cmd_type == CMD_IOACCEL2) {
4759 struct ctlr_info *h = c->h;
4760 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4761 int rc;
4762
4763 if (c2->error_data.serv_response ==
4764 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4765 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4766 if (rc == 0)
4767 return;
4768 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4769 /*
4770 * If we get here, it means dma mapping failed.
4771 * Try again via scsi mid layer, which will
4772 * then get SCSI_MLQUEUE_HOST_BUSY.
4773 */
4774 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4775 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4776 }
4777 /* else, fall thru and resubmit down CISS path */
4778 }
4779 }
360c73bd 4780 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4781 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4782 /*
4783 * If we get here, it means dma mapping failed. Try
4784 * again via scsi mid layer, which will then get
4785 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4786 *
4787 * hpsa_ciss_submit will have already freed c
4788 * if it encountered a dma mapping failure.
080ef1cc
DB		 4789 */
4790 cmd->result = DID_IMM_RETRY << 16;
4791 cmd->scsi_done(cmd);
4792 }
4793}
4794
574f05d3
SC		 4795/* Running in struct Scsi_Host->host_lock less mode */
4796static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4797{
4798 struct ctlr_info *h;
4799 struct hpsa_scsi_dev_t *dev;
4800 unsigned char scsi3addr[8];
4801 struct CommandList *c;
4802 int rc = 0;
4803
4804 /* Get the ptr to our adapter structure out of cmd->host. */
4805 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4806
4807 BUG_ON(cmd->request->tag < 0);
4808
574f05d3
SC		 4809 dev = cmd->device->hostdata;
4810 if (!dev) {
4811 cmd->result = DID_NO_CONNECT << 16;
4812 cmd->scsi_done(cmd);
4813 return 0;
4814 }
574f05d3 4815
73153fe5 4816 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4817
407863cb 4818 if (unlikely(lockup_detected(h))) {
25163bd5 4819 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4820 cmd->scsi_done(cmd);
4821 return 0;
4822 }
73153fe5 4823 c = cmd_tagged_alloc(h, cmd);
574f05d3 4824
407863cb
SC		 4825 /*
4826 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4827 * Retries always go down the normal I/O path.
4828 */
4829 if (likely(cmd->retries == 0 &&
4830 cmd->request->cmd_type == REQ_TYPE_FS &&
4831 h->acciopath_status)) {
592a0ad5
WS		 4832 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4833 if (rc == 0)
4834 return 0;
4835 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4836 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4837 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4838 }
4839 }
4840 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4841}
4842
8ebc9248 4843static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4844{
4845 unsigned long flags;
4846
8ebc9248
WS		 4847 spin_lock_irqsave(&h->scan_lock, flags);
4848 h->scan_finished = 1;
4849 wake_up_all(&h->scan_wait_queue);
4850 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4851}
4852
a08a8471
SC		 4853static void hpsa_scan_start(struct Scsi_Host *sh)
4854{
4855 struct ctlr_info *h = shost_to_hba(sh);
4856 unsigned long flags;
4857
8ebc9248
WS		 4858 /*
4859 * Don't let rescans be initiated on a controller known to be locked
4860 * up. If the controller locks up *during* a rescan, that thread is
4861 * probably hosed, but at least we can prevent new rescan threads from
4862 * piling up on a locked up controller.
4863 */
4864 if (unlikely(lockup_detected(h)))
4865 return hpsa_scan_complete(h);
5f389360 4866
a08a8471
SC		 4867 /* wait until any scan already in progress is finished. */
4868 while (1) {
4869 spin_lock_irqsave(&h->scan_lock, flags);
4870 if (h->scan_finished)
4871 break;
4872 spin_unlock_irqrestore(&h->scan_lock, flags);
4873 wait_event(h->scan_wait_queue, h->scan_finished);
4874 /* Note: We don't need to worry about a race between this
4875 * thread and driver unload because the midlayer will
4876 * have incremented the reference count, so unload won't
4877 * happen if we're in here.
4878 */
4879 }
4880 h->scan_finished = 0; /* mark scan as in progress */
4881 spin_unlock_irqrestore(&h->scan_lock, flags);
4882
8ebc9248
WS		 4883 if (unlikely(lockup_detected(h)))
4884 return hpsa_scan_complete(h);
5f389360 4885
a08a8471
SC		 4886 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4887
8ebc9248 4888 hpsa_scan_complete(h);
a08a8471
SC		 4889}
4890
7c0a0229
DB		 4891static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4892{
03383736
DB		 4893 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4894
4895 if (!logical_drive)
4896 return -ENODEV;
7c0a0229
DB		 4897
4898 if (qdepth < 1)
4899 qdepth = 1;
03383736
DB		 4900 else if (qdepth > logical_drive->queue_depth)
4901 qdepth = logical_drive->queue_depth;
4902
4903 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4904}
4905
a08a8471
SC		 4906static int hpsa_scan_finished(struct Scsi_Host *sh,
4907 unsigned long elapsed_time)
4908{
4909 struct ctlr_info *h = shost_to_hba(sh);
4910 unsigned long flags;
4911 int finished;
4912
4913 spin_lock_irqsave(&h->scan_lock, flags);
4914 finished = h->scan_finished;
4915 spin_unlock_irqrestore(&h->scan_lock, flags);
4916 return finished;
4917}
4918
2946e82b 4919static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 4920{
b705690d
SC		 4921 struct Scsi_Host *sh;
4922 int error;
edd16368 4923
b705690d 4924 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 4925 if (sh == NULL) {
4926 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4927 return -ENOMEM;
4928 }
b705690d
SC		 4929
4930 sh->io_port = 0;
4931 sh->n_io_port = 0;
4932 sh->this_id = -1;
4933 sh->max_channel = 3;
4934 sh->max_cmd_len = MAX_COMMAND_SIZE;
4935 sh->max_lun = HPSA_MAX_LUN;
4936 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4937 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4938 sh->cmd_per_lun = sh->can_queue;
b705690d 4939 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 4940 sh->hostdata[0] = (unsigned long) h;
4941 sh->irq = h->intr[h->intr_mode];
4942 sh->unique_id = sh->irq;
73153fe5
WS		 4943 error = scsi_init_shared_tag_map(sh, sh->can_queue);
4944 if (error) {
4945 dev_err(&h->pdev->dev,
4946 "%s: scsi_init_shared_tag_map failed for controller %d\n",
4947 __func__, h->ctlr);
2946e82b
RE		 4948 scsi_host_put(sh);
4949 return error;
73153fe5 4950 }
2946e82b 4951 h->scsi_host = sh;
b705690d 4952 return 0;
2946e82b 4953}
b705690d 4954
2946e82b
RE		 4955static int hpsa_scsi_add_host(struct ctlr_info *h)
4956{
4957 int rv;
4958
4959 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
4960 if (rv) {
4961 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
4962 return rv;
4963 }
4964 scsi_scan_host(h->scsi_host);
4965 return 0;
edd16368
SC		 4966}
4967
73153fe5
WS		 4968/*
4969 * The block layer has already gone to the trouble of picking out a unique,
4970 * small-integer tag for this request. We use an offset from that value as
4971 * an index to select our command block. (The offset allows us to reserve the
4972 * low-numbered entries for our own uses.)
4973 */
4974static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
4975{
4976 int idx = scmd->request->tag;
4977
4978 if (idx < 0)
4979 return idx;
4980
4981 /* Offset to leave space for internal cmds. */
4982 return idx += HPSA_NRESERVED_CMDS;
4983}
4984
b69324ff
WS		 4985/*
4986 * Send a TEST_UNIT_READY command to the specified LUN using the specified
4987 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
4988 */
4989static int hpsa_send_test_unit_ready(struct ctlr_info *h,
4990 struct CommandList *c, unsigned char lunaddr[],
4991 int reply_queue)
4992{
4993 int rc;
4994
4995 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4996 (void) fill_cmd(c, TEST_UNIT_READY, h,
4997 NULL, 0, 0, lunaddr, TYPE_CMD);
4998 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
4999 if (rc)
5000 return rc;
5001 /* no unmap needed here because no data xfer. */
5002
5003 /* Check if the unit is already ready. */
5004 if (c->err_info->CommandStatus == CMD_SUCCESS)
5005 return 0;
5006
5007 /*
5008 * The first command sent after reset will receive "unit attention" to
5009 * indicate that the LUN has been reset...this is actually what we're
5010 * looking for (but, success is good too).
5011 */
5012 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5013 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5014 (c->err_info->SenseInfo[2] == NO_SENSE ||
5015 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5016 return 0;
5017
5018 return 1;
5019}
5020
5021/*
5022 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5023 * returns zero when the unit is ready, and non-zero when giving up.
5024 */
5025static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5026 struct CommandList *c,
5027 unsigned char lunaddr[], int reply_queue)
edd16368 5028{
8919358e 5029 int rc;
edd16368
SC		 5030 int count = 0;
5031 int waittime = 1; /* seconds */
edd16368
SC		 5032
5033 /* Send test unit ready until device ready, or give up. */
b69324ff 5034 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5035
b69324ff
WS		 5036 /*
5037 * Wait for a bit. do this first, because if we send
edd16368
SC		 5038 * the TUR right away, the reset will just abort it.
5039 */
5040 msleep(1000 * waittime);
b69324ff
WS		 5041
5042 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5043 if (!rc)
5044 break;
edd16368
SC		 5045
5046 /* Increase wait time with each try, up to a point. */
5047 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5048 waittime *= 2;
edd16368 5049
b69324ff
WS		 5050 dev_warn(&h->pdev->dev,
5051 "waiting %d secs for device to become ready.\n",
5052 waittime);
5053 }
edd16368 5054
b69324ff
WS		 5055 return rc;
5056}
edd16368 5057
b69324ff
WS		 5058static int wait_for_device_to_become_ready(struct ctlr_info *h,
5059 unsigned char lunaddr[],
5060 int reply_queue)
5061{
5062 int first_queue;
5063 int last_queue;
5064 int rq;
5065 int rc = 0;
5066 struct CommandList *c;
5067
5068 c = cmd_alloc(h);
5069
5070 /*
5071 * If no specific reply queue was requested, then send the TUR
5072 * repeatedly, requesting a reply on each reply queue; otherwise execute
5073 * the loop exactly once using only the specified queue.
5074 */
5075 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5076 first_queue = 0;
5077 last_queue = h->nreply_queues - 1;
5078 } else {
5079 first_queue = reply_queue;
5080 last_queue = reply_queue;
5081 }
5082
5083 for (rq = first_queue; rq <= last_queue; rq++) {
5084 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5085 if (rc)
edd16368 5086 break;
edd16368
SC		 5087 }
5088
5089 if (rc)
5090 dev_warn(&h->pdev->dev, "giving up on device.\n");
5091 else
5092 dev_warn(&h->pdev->dev, "device is ready.\n");
5093
45fcb86e 5094 cmd_free(h, c);
edd16368
SC		 5095 return rc;
5096}
5097
5098/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5099 * complaining. Doing a host- or bus-reset can't do anything good here.
5100 */
5101static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5102{
5103 int rc;
5104 struct ctlr_info *h;
5105 struct hpsa_scsi_dev_t *dev;
2dc127bb 5106 char msg[48];
edd16368
SC		 5107
5108 /* find the controller to which the command to be aborted was sent */
5109 h = sdev_to_hba(scsicmd->device);
5110 if (h == NULL) /* paranoia */
5111 return FAILED;
e345893b
DB		 5112
5113 if (lockup_detected(h))
5114 return FAILED;
5115
edd16368
SC		 5116 dev = scsicmd->device->hostdata;
5117 if (!dev) {
d604f533 5118 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5119 return FAILED;
5120 }
25163bd5
WS		 5121
5122 /* if controller locked up, we can guarantee command won't complete */
5123 if (lockup_detected(h)) {
2dc127bb
DC		 5124 snprintf(msg, sizeof(msg),
5125 "cmd %d RESET FAILED, lockup detected",
5126 hpsa_get_cmd_index(scsicmd));
73153fe5 5127 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5128 return FAILED;
5129 }
5130
5131 /* this reset request might be the result of a lockup; check */
5132 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5133 snprintf(msg, sizeof(msg),
5134 "cmd %d RESET FAILED, new lockup detected",
5135 hpsa_get_cmd_index(scsicmd));
73153fe5 5136 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5137 return FAILED;
5138 }
5139
d604f533
WS		 5140 /* Do not attempt on controller */
5141 if (is_hba_lunid(dev->scsi3addr))
5142 return SUCCESS;
5143
25163bd5
WS		 5144 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5145
edd16368 5146 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5147 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5148 DEFAULT_REPLY_QUEUE);
2dc127bb
DC		 5149 snprintf(msg, sizeof(msg), "reset %s",
5150 rc == 0 ? "completed successfully" : "failed");
d604f533
WS		 5151 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5152 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5153}
5154
6cba3f19
SC		 5155static void swizzle_abort_tag(u8 *tag)
5156{
5157 u8 original_tag[8];
5158
5159 memcpy(original_tag, tag, 8);
5160 tag[0] = original_tag[3];
5161 tag[1] = original_tag[2];
5162 tag[2] = original_tag[1];
5163 tag[3] = original_tag[0];
5164 tag[4] = original_tag[7];
5165 tag[5] = original_tag[6];
5166 tag[6] = original_tag[5];
5167 tag[7] = original_tag[4];
5168}
5169
17eb87d2 5170static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5171 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5172{
2b08b3e9 5173 u64 tag;
17eb87d2
ST		 5174 if (c->cmd_type == CMD_IOACCEL1) {
5175 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5176 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5177 tag = le64_to_cpu(cm1->tag);
5178 *tagupper = cpu_to_le32(tag >> 32);
5179 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5180 return;
5181 }
5182 if (c->cmd_type == CMD_IOACCEL2) {
5183 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5184 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5185 /* upper tag not used in ioaccel2 mode */
5186 memset(tagupper, 0, sizeof(*tagupper));
5187 *taglower = cm2->Tag;
54b6e9e9 5188 return;
17eb87d2 5189 }
2b08b3e9
DB		 5190 tag = le64_to_cpu(c->Header.tag);
5191 *tagupper = cpu_to_le32(tag >> 32);
5192 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5193}
5194
75167d2c 5195static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5196 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5197{
5198 int rc = IO_OK;
5199 struct CommandList *c;
5200 struct ErrorInfo *ei;
2b08b3e9 5201 __le32 tagupper, taglower;
75167d2c 5202
45fcb86e 5203 c = cmd_alloc(h);
75167d2c 5204
a2dac136 5205 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5206 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5207 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5208 if (h->needs_abort_tags_swizzled)
6cba3f19 5209 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5210 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5211 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5212 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5213 __func__, tagupper, taglower);
75167d2c
SC		 5214 /* no unmap needed here because no data xfer. */
5215
5216 ei = c->err_info;
5217 switch (ei->CommandStatus) {
5218 case CMD_SUCCESS:
5219 break;
9437ac43
SC		 5220 case CMD_TMF_STATUS:
5221 rc = hpsa_evaluate_tmf_status(h, c);
5222 break;
75167d2c
SC		 5223 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5224 rc = -1;
5225 break;
5226 default:
5227 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5228 __func__, tagupper, taglower);
d1e8beac 5229 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5230 rc = -1;
5231 break;
5232 }
45fcb86e 5233 cmd_free(h, c);
dd0e19f3
ST		 5234 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5235 __func__, tagupper, taglower);
75167d2c
SC		 5236 return rc;
5237}
5238
8be986cc
SC		 5239static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5240 struct CommandList *command_to_abort, int reply_queue)
5241{
5242 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5243 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5244 struct io_accel2_cmd *c2a =
5245 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5246 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5247 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5248
5249 /*
5250 * We're overlaying struct hpsa_tmf_struct on top of something which
5251 * was allocated as a struct io_accel2_cmd, so we better be sure it
5252 * actually fits, and doesn't overrun the error info space.
5253 */
5254 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5255 sizeof(struct io_accel2_cmd));
5256 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5257 offsetof(struct hpsa_tmf_struct, error_len) +
5258 sizeof(ac->error_len));
5259
5260 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5261 c->scsi_cmd = SCSI_CMD_BUSY;
5262
8be986cc
SC		 5263 /* Adjust the DMA address to point to the accelerated command buffer */
5264 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5265 (c->cmdindex * sizeof(struct io_accel2_cmd));
5266 BUG_ON(c->busaddr & 0x0000007F);
5267
5268 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5269 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5270 ac->reply_queue = reply_queue;
5271 ac->tmf = IOACCEL2_TMF_ABORT;
5272 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5273 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5274 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5275 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5276 ac->error_ptr = cpu_to_le64(c->busaddr +
5277 offsetof(struct io_accel2_cmd, error_data));
5278 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5279}
5280
54b6e9e9
ST		 5281/* ioaccel2 path firmware cannot handle abort task requests.
5282 * Change abort requests to physical target reset, and send to the
5283 * address of the physical disk used for the ioaccel 2 command.
5284 * Return 0 on success (IO_OK)
5285 * -1 on failure
5286 */
5287
5288static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5289 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5290{
5291 int rc = IO_OK;
5292 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5293 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5294 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5295 unsigned char *psa = &phys_scsi3addr[0];
5296
5297 /* Get a pointer to the hpsa logical device. */
7fa3030c 5298 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5299 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5300 if (dev == NULL) {
5301 dev_warn(&h->pdev->dev,
5302 "Cannot abort: no device pointer for command.\n");
5303 return -1; /* not abortable */
5304 }
5305
2ba8bfc8
SC		 5306 if (h->raid_offload_debug > 0)
5307 dev_info(&h->pdev->dev,
0d96ef5f 5308 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5309 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5310 "Reset as abort",
2ba8bfc8
SC		 5311 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5312 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5313
54b6e9e9
ST		 5314 if (!dev->offload_enabled) {
5315 dev_warn(&h->pdev->dev,
5316 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5317 return -1; /* not abortable */
5318 }
5319
5320 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5321 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5322 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5323 return -1; /* not abortable */
5324 }
5325
5326 /* send the reset */
2ba8bfc8
SC		 5327 if (h->raid_offload_debug > 0)
5328 dev_info(&h->pdev->dev,
5329 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5330 psa[0], psa[1], psa[2], psa[3],
5331 psa[4], psa[5], psa[6], psa[7]);
d604f533 5332 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5333 if (rc != 0) {
5334 dev_warn(&h->pdev->dev,
5335 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5336 psa[0], psa[1], psa[2], psa[3],
5337 psa[4], psa[5], psa[6], psa[7]);
5338 return rc; /* failed to reset */
5339 }
5340
5341 /* wait for device to recover */
b69324ff 5342 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5343 dev_warn(&h->pdev->dev,
5344 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5345 psa[0], psa[1], psa[2], psa[3],
5346 psa[4], psa[5], psa[6], psa[7]);
5347 return -1; /* failed to recover */
5348 }
5349
5350 /* device recovered */
5351 dev_info(&h->pdev->dev,
5352 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5353 psa[0], psa[1], psa[2], psa[3],
5354 psa[4], psa[5], psa[6], psa[7]);
5355
5356 return rc; /* success */
5357}
5358
8be986cc
SC		 5359static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5360 struct CommandList *abort, int reply_queue)
5361{
5362 int rc = IO_OK;
5363 struct CommandList *c;
5364 __le32 taglower, tagupper;
5365 struct hpsa_scsi_dev_t *dev;
5366 struct io_accel2_cmd *c2;
5367
5368 dev = abort->scsi_cmd->device->hostdata;
5369 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5370 return -1;
5371
5372 c = cmd_alloc(h);
5373 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5374 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5375 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5376 hpsa_get_tag(h, abort, &taglower, &tagupper);
5377 dev_dbg(&h->pdev->dev,
5378 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5379 __func__, tagupper, taglower);
5380 /* no unmap needed here because no data xfer. */
5381
5382 dev_dbg(&h->pdev->dev,
5383 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5384 __func__, tagupper, taglower, c2->error_data.serv_response);
5385 switch (c2->error_data.serv_response) {
5386 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5387 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5388 rc = 0;
5389 break;
5390 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5391 case IOACCEL2_SERV_RESPONSE_FAILURE:
5392 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5393 rc = -1;
5394 break;
5395 default:
5396 dev_warn(&h->pdev->dev,
5397 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5398 __func__, tagupper, taglower,
5399 c2->error_data.serv_response);
5400 rc = -1;
5401 }
5402 cmd_free(h, c);
5403 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5404 tagupper, taglower);
5405 return rc;
5406}
5407
6cba3f19 5408static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5409 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5410{
8be986cc
SC		 5411 /*
5412 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5413 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5414 * but not all underlying firmware can handle abort TMF.
5415 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5416 */
8be986cc
SC		 5417 if (abort->cmd_type == CMD_IOACCEL2) {
5418 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5419 return hpsa_send_abort_ioaccel2(h, abort,
5420 reply_queue);
5421 else
5422 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5423 abort, reply_queue);
8be986cc 5424 }
9b5c48c2 5425 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5426}
54b6e9e9 5427
25163bd5
WS		 5428/* Find out which reply queue a command was meant to return on */
5429static int hpsa_extract_reply_queue(struct ctlr_info *h,
5430 struct CommandList *c)
5431{
5432 if (c->cmd_type == CMD_IOACCEL2)
5433 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5434 return c->Header.ReplyQueue;
6cba3f19
SC		 5435}
5436
9b5c48c2
SC		 5437/*
5438 * Limit concurrency of abort commands to prevent
5439 * over-subscription of commands
5440 */
5441static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5442{
5443#define ABORT_CMD_WAIT_MSECS 5000
5444 return !wait_event_timeout(h->abort_cmd_wait_queue,
5445 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5446 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5447}
5448
75167d2c
SC		 5449/* Send an abort for the specified command.
5450 * If the device and controller support it,
5451 * send a task abort request.
5452 */
5453static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5454{
5455
a58e7e53 5456 int rc;
75167d2c
SC		 5457 struct ctlr_info *h;
5458 struct hpsa_scsi_dev_t *dev;
5459 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5460 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5461 char msg[256]; /* For debug messaging. */
5462 int ml = 0;
2b08b3e9 5463 __le32 tagupper, taglower;
25163bd5
WS		 5464 int refcount, reply_queue;
5465
5466 if (sc == NULL)
5467 return FAILED;
75167d2c 5468
9b5c48c2
SC		 5469 if (sc->device == NULL)
5470 return FAILED;
5471
75167d2c
SC		 5472 /* Find the controller of the command to be aborted */
5473 h = sdev_to_hba(sc->device);
9b5c48c2 5474 if (h == NULL)
75167d2c
SC		 5475 return FAILED;
5476
25163bd5
WS		 5477 /* Find the device of the command to be aborted */
5478 dev = sc->device->hostdata;
5479 if (!dev) {
5480 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5481 msg);
e345893b 5482 return FAILED;
25163bd5
WS		 5483 }
5484
5485 /* If controller locked up, we can guarantee command won't complete */
5486 if (lockup_detected(h)) {
5487 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5488 "ABORT FAILED, lockup detected");
5489 return FAILED;
5490 }
5491
5492 /* This is a good time to check if controller lockup has occurred */
5493 if (detect_controller_lockup(h)) {
5494 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5495 "ABORT FAILED, new lockup detected");
5496 return FAILED;
5497 }
e345893b 5498
75167d2c
SC		 5499 /* Check that controller supports some kind of task abort */
5500 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5501 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5502 return FAILED;
5503
5504 memset(msg, 0, sizeof(msg));
4b761557 5505 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5506 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5507 sc->device->id, sc->device->lun,
4b761557 5508 "Aborting command", sc);
75167d2c 5509
75167d2c
SC		 5510 /* Get SCSI command to be aborted */
5511 abort = (struct CommandList *) sc->host_scribble;
5512 if (abort == NULL) {
281a7fd0
WS		 5513 /* This can happen if the command already completed. */
5514 return SUCCESS;
5515 }
5516 refcount = atomic_inc_return(&abort->refcount);
5517 if (refcount == 1) { /* Command is done already. */
5518 cmd_free(h, abort);
5519 return SUCCESS;
75167d2c 5520 }
9b5c48c2
SC		 5521
5522 /* Don't bother trying the abort if we know it won't work. */
5523 if (abort->cmd_type != CMD_IOACCEL2 &&
5524 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5525 cmd_free(h, abort);
5526 return FAILED;
5527 }
5528
a58e7e53
WS		 5529 /*
5530 * Check that we're aborting the right command.
5531 * It's possible the CommandList already completed and got re-used.
5532 */
5533 if (abort->scsi_cmd != sc) {
5534 cmd_free(h, abort);
5535 return SUCCESS;
5536 }
5537
5538 abort->abort_pending = true;
17eb87d2 5539 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5540 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5541 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5542 as = abort->scsi_cmd;
75167d2c 5543 if (as != NULL)
4b761557
RE		 5544 ml += sprintf(msg+ml,
5545 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5546 as->cmd_len, as->cmnd[0], as->cmnd[1],
5547 as->serial_number);
5548 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5549 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5550
75167d2c
SC		 5551 /*
5552 * Command is in flight, or possibly already completed
5553 * by the firmware (but not to the scsi mid layer) but we can't
5554 * distinguish which. Send the abort down.
5555 */
9b5c48c2
SC		 5556 if (wait_for_available_abort_cmd(h)) {
5557 dev_warn(&h->pdev->dev,
4b761557
RE		 5558 "%s FAILED, timeout waiting for an abort command to become available.\n",
5559 msg);
9b5c48c2
SC		 5560 cmd_free(h, abort);
5561 return FAILED;
5562 }
25163bd5 5563 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5564 atomic_inc(&h->abort_cmds_available);
5565 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5566 if (rc != 0) {
4b761557 5567 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5568 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5569 "FAILED to abort command");
281a7fd0 5570 cmd_free(h, abort);
75167d2c
SC		 5571 return FAILED;
5572 }
4b761557 5573 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5574 wait_event(h->event_sync_wait_queue,
a58e7e53 5575 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5576 cmd_free(h, abort);
a58e7e53 5577 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5578}
5579
73153fe5
WS		 5580/*
5581 * For operations with an associated SCSI command, a command block is allocated
5582 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5583 * block request tag as an index into a table of entries. cmd_tagged_free() is
5584 * the complement, although cmd_free() may be called instead.
5585 */
5586static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5587 struct scsi_cmnd *scmd)
5588{
5589 int idx = hpsa_get_cmd_index(scmd);
5590 struct CommandList *c = h->cmd_pool + idx;
5591
5592 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5593 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5594 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5595 /* The index value comes from the block layer, so if it's out of
5596 * bounds, it's probably not our bug.
5597 */
5598 BUG();
5599 }
5600
5601 atomic_inc(&c->refcount);
5602 if (unlikely(!hpsa_is_cmd_idle(c))) {
5603 /*
5604 * We expect that the SCSI layer will hand us a unique tag
5605 * value. Thus, there should never be a collision here between
5606 * two requests...because if the selected command isn't idle
5607 * then someone is going to be very disappointed.
5608 */
5609 dev_err(&h->pdev->dev,
5610 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5611 idx);
5612 if (c->scsi_cmd != NULL)
5613 scsi_print_command(c->scsi_cmd);
5614 scsi_print_command(scmd);
5615 }
5616
5617 hpsa_cmd_partial_init(h, idx, c);
5618 return c;
5619}
5620
5621static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5622{
5623 /*
5624 * Release our reference to the block. We don't need to do anything
5625 * else to free it, because it is accessed by index. (There's no point
5626 * in checking the result of the decrement, since we cannot guarantee
5627 * that there isn't a concurrent abort which is also accessing it.)
5628 */
5629 (void)atomic_dec(&c->refcount);
5630}
5631
edd16368
SC		 5632/*
5633 * For operations that cannot sleep, a command block is allocated at init,
5634 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5635 * which ones are free or in use. Lock must be held when calling this.
5636 * cmd_free() is the complement.
bf43caf3
RE		 5637 * This function never gives up and returns NULL. If it hangs,
5638 * another thread must call cmd_free() to free some tags.
edd16368 5639 */
281a7fd0 5640
edd16368
SC		 5641static struct CommandList *cmd_alloc(struct ctlr_info *h)
5642{
5643 struct CommandList *c;
360c73bd 5644 int refcount, i;
73153fe5 5645 int offset = 0;
4c413128 5646
33811026
RE		 5647 /*
5648 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5649 * multiple threads could get in here, and one thread could
5650 * be scanning through the list of bits looking for a free
5651 * one, but the free ones are always behind him, and other
5652 * threads sneak in behind him and eat them before he can
5653 * get to them, so that while there is always a free one, a
5654 * very unlucky thread might be starved anyway, never able to
5655 * beat the other threads. In reality, this happens so
5656 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5657 *
5658 * Note that we start allocating commands before the SCSI host structure
5659 * is initialized. Since the search starts at bit zero, this
5660 * all works, since we have at least one command structure available;
5661 * however, it means that the structures with the low indexes have to be
5662 * reserved for driver-initiated requests, while requests from the block
5663 * layer will use the higher indexes.
4c413128 5664 */
edd16368 5665
281a7fd0 5666 for (;;) {
73153fe5
WS		 5667 i = find_next_zero_bit(h->cmd_pool_bits,
5668 HPSA_NRESERVED_CMDS,
5669 offset);
5670 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5671 offset = 0;
5672 continue;
5673 }
5674 c = h->cmd_pool + i;
5675 refcount = atomic_inc_return(&c->refcount);
5676 if (unlikely(refcount > 1)) {
5677 cmd_free(h, c); /* already in use */
73153fe5 5678 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5679 continue;
5680 }
5681 set_bit(i & (BITS_PER_LONG - 1),
5682 h->cmd_pool_bits + (i / BITS_PER_LONG));
5683 break; /* it's ours now. */
5684 }
360c73bd 5685 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5686 return c;
5687}
5688
73153fe5
WS		 5689/*
5690 * This is the complementary operation to cmd_alloc(). Note, however, in some
5691 * corner cases it may also be used to free blocks allocated by
5692 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5693 * the clear-bit is harmless.
5694 */
edd16368
SC		 5695static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5696{
281a7fd0
WS		 5697 if (atomic_dec_and_test(&c->refcount)) {
5698 int i;
edd16368 5699
281a7fd0
WS		 5700 i = c - h->cmd_pool;
5701 clear_bit(i & (BITS_PER_LONG - 1),
5702 h->cmd_pool_bits + (i / BITS_PER_LONG));
5703 }
edd16368
SC		 5704}
5705
edd16368
SC		 5706#ifdef CONFIG_COMPAT
5707
42a91641
DB		 5708static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5709 void __user *arg)
edd16368
SC		 5710{
5711 IOCTL32_Command_struct __user *arg32 =
5712 (IOCTL32_Command_struct __user *) arg;
5713 IOCTL_Command_struct arg64;
5714 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5715 int err;
5716 u32 cp;
5717
938abd84 5718 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5719 err = 0;
5720 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5721 sizeof(arg64.LUN_info));
5722 err |= copy_from_user(&arg64.Request, &arg32->Request,
5723 sizeof(arg64.Request));
5724 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5725 sizeof(arg64.error_info));
5726 err |= get_user(arg64.buf_size, &arg32->buf_size);
5727 err |= get_user(cp, &arg32->buf);
5728 arg64.buf = compat_ptr(cp);
5729 err |= copy_to_user(p, &arg64, sizeof(arg64));
5730
5731 if (err)
5732 return -EFAULT;
5733
42a91641 5734 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5735 if (err)
5736 return err;
5737 err |= copy_in_user(&arg32->error_info, &p->error_info,
5738 sizeof(arg32->error_info));
5739 if (err)
5740 return -EFAULT;
5741 return err;
5742}
5743
5744static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5745 int cmd, void __user *arg)
edd16368
SC		 5746{
5747 BIG_IOCTL32_Command_struct __user *arg32 =
5748 (BIG_IOCTL32_Command_struct __user *) arg;
5749 BIG_IOCTL_Command_struct arg64;
5750 BIG_IOCTL_Command_struct __user *p =
5751 compat_alloc_user_space(sizeof(arg64));
5752 int err;
5753 u32 cp;
5754
938abd84 5755 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5756 err = 0;
5757 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5758 sizeof(arg64.LUN_info));
5759 err |= copy_from_user(&arg64.Request, &arg32->Request,
5760 sizeof(arg64.Request));
5761 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5762 sizeof(arg64.error_info));
5763 err |= get_user(arg64.buf_size, &arg32->buf_size);
5764 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5765 err |= get_user(cp, &arg32->buf);
5766 arg64.buf = compat_ptr(cp);
5767 err |= copy_to_user(p, &arg64, sizeof(arg64));
5768
5769 if (err)
5770 return -EFAULT;
5771
42a91641 5772 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5773 if (err)
5774 return err;
5775 err |= copy_in_user(&arg32->error_info, &p->error_info,
5776 sizeof(arg32->error_info));
5777 if (err)
5778 return -EFAULT;
5779 return err;
5780}
71fe75a7 5781
42a91641 5782static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5783{
5784 switch (cmd) {
5785 case CCISS_GETPCIINFO:
5786 case CCISS_GETINTINFO:
5787 case CCISS_SETINTINFO:
5788 case CCISS_GETNODENAME:
5789 case CCISS_SETNODENAME:
5790 case CCISS_GETHEARTBEAT:
5791 case CCISS_GETBUSTYPES:
5792 case CCISS_GETFIRMVER:
5793 case CCISS_GETDRIVVER:
5794 case CCISS_REVALIDVOLS:
5795 case CCISS_DEREGDISK:
5796 case CCISS_REGNEWDISK:
5797 case CCISS_REGNEWD:
5798 case CCISS_RESCANDISK:
5799 case CCISS_GETLUNINFO:
5800 return hpsa_ioctl(dev, cmd, arg);
5801
5802 case CCISS_PASSTHRU32:
5803 return hpsa_ioctl32_passthru(dev, cmd, arg);
5804 case CCISS_BIG_PASSTHRU32:
5805 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5806
5807 default:
5808 return -ENOIOCTLCMD;
5809 }
5810}
edd16368
SC		 5811#endif
5812
5813static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5814{
5815 struct hpsa_pci_info pciinfo;
5816
5817 if (!argp)
5818 return -EINVAL;
5819 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5820 pciinfo.bus = h->pdev->bus->number;
5821 pciinfo.dev_fn = h->pdev->devfn;
5822 pciinfo.board_id = h->board_id;
5823 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5824 return -EFAULT;
5825 return 0;
5826}
5827
5828static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5829{
5830 DriverVer_type DriverVer;
5831 unsigned char vmaj, vmin, vsubmin;
5832 int rc;
5833
5834 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5835 &vmaj, &vmin, &vsubmin);
5836 if (rc != 3) {
5837 dev_info(&h->pdev->dev, "driver version string '%s' "
5838 "unrecognized.", HPSA_DRIVER_VERSION);
5839 vmaj = 0;
5840 vmin = 0;
5841 vsubmin = 0;
5842 }
5843 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5844 if (!argp)
5845 return -EINVAL;
5846 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5847 return -EFAULT;
5848 return 0;
5849}
5850
5851static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5852{
5853 IOCTL_Command_struct iocommand;
5854 struct CommandList *c;
5855 char *buff = NULL;
50a0decf 5856 u64 temp64;
c1f63c8f 5857 int rc = 0;
edd16368
SC		 5858
5859 if (!argp)
5860 return -EINVAL;
5861 if (!capable(CAP_SYS_RAWIO))
5862 return -EPERM;
5863 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5864 return -EFAULT;
5865 if ((iocommand.buf_size < 1) &&
5866 (iocommand.Request.Type.Direction != XFER_NONE)) {
5867 return -EINVAL;
5868 }
5869 if (iocommand.buf_size > 0) {
5870 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5871 if (buff == NULL)
2dd02d74 5872 return -ENOMEM;
9233fb10 5873 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5874 /* Copy the data into the buffer we created */
5875 if (copy_from_user(buff, iocommand.buf,
5876 iocommand.buf_size)) {
c1f63c8f
SC		 5877 rc = -EFAULT;
5878 goto out_kfree;
b03a7771
SC		 5879 }
5880 } else {
5881 memset(buff, 0, iocommand.buf_size);
edd16368 5882 }
b03a7771 5883 }
45fcb86e 5884 c = cmd_alloc(h);
bf43caf3 5885
edd16368
SC		 5886 /* Fill in the command type */
5887 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5888 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5889 /* Fill in Command Header */
5890 c->Header.ReplyQueue = 0; /* unused in simple mode */
5891 if (iocommand.buf_size > 0) { /* buffer to fill */
5892 c->Header.SGList = 1;
50a0decf 5893 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5894 } else { /* no buffers to fill */
5895 c->Header.SGList = 0;
50a0decf 5896 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5897 }
5898 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5899
5900 /* Fill in Request block */
5901 memcpy(&c->Request, &iocommand.Request,
5902 sizeof(c->Request));
5903
5904 /* Fill in the scatter gather information */
5905 if (iocommand.buf_size > 0) {
50a0decf 5906 temp64 = pci_map_single(h->pdev, buff,
edd16368 5907 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5908 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5909 c->SG[0].Addr = cpu_to_le64(0);
5910 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5911 rc = -ENOMEM;
5912 goto out;
5913 }
50a0decf
SC		 5914 c->SG[0].Addr = cpu_to_le64(temp64);
5915 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5916 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5917 }
25163bd5 5918 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5919 if (iocommand.buf_size > 0)
5920 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5921 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5922 if (rc) {
5923 rc = -EIO;
5924 goto out;
5925 }
edd16368
SC		 5926
5927 /* Copy the error information out */
5928 memcpy(&iocommand.error_info, c->err_info,
5929 sizeof(iocommand.error_info));
5930 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5931 rc = -EFAULT;
5932 goto out;
edd16368 5933 }
9233fb10 5934 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5935 iocommand.buf_size > 0) {
edd16368
SC		 5936 /* Copy the data out of the buffer we created */
5937 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5938 rc = -EFAULT;
5939 goto out;
edd16368
SC		 5940 }
5941 }
c1f63c8f 5942out:
45fcb86e 5943 cmd_free(h, c);
c1f63c8f
SC		 5944out_kfree:
5945 kfree(buff);
5946 return rc;
edd16368
SC		 5947}
5948
5949static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5950{
5951 BIG_IOCTL_Command_struct *ioc;
5952 struct CommandList *c;
5953 unsigned char **buff = NULL;
5954 int *buff_size = NULL;
50a0decf 5955 u64 temp64;
edd16368
SC		 5956 BYTE sg_used = 0;
5957 int status = 0;
01a02ffc
SC		 5958 u32 left;
5959 u32 sz;
edd16368
SC		 5960 BYTE __user *data_ptr;
5961
5962 if (!argp)
5963 return -EINVAL;
5964 if (!capable(CAP_SYS_RAWIO))
5965 return -EPERM;
5966 ioc = (BIG_IOCTL_Command_struct *)
5967 kmalloc(sizeof(*ioc), GFP_KERNEL);
5968 if (!ioc) {
5969 status = -ENOMEM;
5970 goto cleanup1;
5971 }
5972 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5973 status = -EFAULT;
5974 goto cleanup1;
5975 }
5976 if ((ioc->buf_size < 1) &&
5977 (ioc->Request.Type.Direction != XFER_NONE)) {
5978 status = -EINVAL;
5979 goto cleanup1;
5980 }
5981 /* Check kmalloc limits using all SGs */
5982 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5983 status = -EINVAL;
5984 goto cleanup1;
5985 }
d66ae08b 5986 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5987 status = -EINVAL;
5988 goto cleanup1;
5989 }
d66ae08b 5990 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5991 if (!buff) {
5992 status = -ENOMEM;
5993 goto cleanup1;
5994 }
d66ae08b 5995 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5996 if (!buff_size) {
5997 status = -ENOMEM;
5998 goto cleanup1;
5999 }
6000 left = ioc->buf_size;
6001 data_ptr = ioc->buf;
6002 while (left) {
6003 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6004 buff_size[sg_used] = sz;
6005 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6006 if (buff[sg_used] == NULL) {
6007 status = -ENOMEM;
6008 goto cleanup1;
6009 }
9233fb10 6010 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6011 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6012 status = -EFAULT;
edd16368
SC		 6013 goto cleanup1;
6014 }
6015 } else
6016 memset(buff[sg_used], 0, sz);
6017 left -= sz;
6018 data_ptr += sz;
6019 sg_used++;
6020 }
45fcb86e 6021 c = cmd_alloc(h);
bf43caf3 6022
edd16368 6023 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6024 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6025 c->Header.ReplyQueue = 0;
50a0decf
SC		 6026 c->Header.SGList = (u8) sg_used;
6027 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6028 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6029 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6030 if (ioc->buf_size > 0) {
6031 int i;
6032 for (i = 0; i < sg_used; i++) {
50a0decf 6033 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6034 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6035 if (dma_mapping_error(&h->pdev->dev,
6036 (dma_addr_t) temp64)) {
6037 c->SG[i].Addr = cpu_to_le64(0);
6038 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6039 hpsa_pci_unmap(h->pdev, c, i,
6040 PCI_DMA_BIDIRECTIONAL);
6041 status = -ENOMEM;
e2d4a1f6 6042 goto cleanup0;
bcc48ffa 6043 }
50a0decf
SC		 6044 c->SG[i].Addr = cpu_to_le64(temp64);
6045 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6046 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6047 }
50a0decf 6048 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6049 }
25163bd5 6050 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6051 if (sg_used)
6052 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6053 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6054 if (status) {
6055 status = -EIO;
6056 goto cleanup0;
6057 }
6058
edd16368
SC		 6059 /* Copy the error information out */
6060 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6061 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6062 status = -EFAULT;
e2d4a1f6 6063 goto cleanup0;
edd16368 6064 }
9233fb10 6065 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6066 int i;
6067
edd16368
SC		 6068 /* Copy the data out of the buffer we created */
6069 BYTE __user *ptr = ioc->buf;
6070 for (i = 0; i < sg_used; i++) {
6071 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6072 status = -EFAULT;
e2d4a1f6 6073 goto cleanup0;
edd16368
SC		 6074 }
6075 ptr += buff_size[i];
6076 }
6077 }
edd16368 6078 status = 0;
e2d4a1f6 6079cleanup0:
45fcb86e 6080 cmd_free(h, c);
edd16368
SC		 6081cleanup1:
6082 if (buff) {
2b08b3e9
DB		 6083 int i;
6084
edd16368
SC		 6085 for (i = 0; i < sg_used; i++)
6086 kfree(buff[i]);
6087 kfree(buff);
6088 }
6089 kfree(buff_size);
6090 kfree(ioc);
6091 return status;
6092}
6093
6094static void check_ioctl_unit_attention(struct ctlr_info *h,
6095 struct CommandList *c)
6096{
6097 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6098 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6099 (void) check_for_unit_attention(h, c);
6100}
0390f0c0 6101
edd16368
SC		 6102/*
6103 * ioctl
6104 */
42a91641 6105static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6106{
6107 struct ctlr_info *h;
6108 void __user *argp = (void __user *)arg;
0390f0c0 6109 int rc;
edd16368
SC		 6110
6111 h = sdev_to_hba(dev);
6112
6113 switch (cmd) {
6114 case CCISS_DEREGDISK:
6115 case CCISS_REGNEWDISK:
6116 case CCISS_REGNEWD:
a08a8471 6117 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6118 return 0;
6119 case CCISS_GETPCIINFO:
6120 return hpsa_getpciinfo_ioctl(h, argp);
6121 case CCISS_GETDRIVVER:
6122 return hpsa_getdrivver_ioctl(h, argp);
6123 case CCISS_PASSTHRU:
34f0c627 6124 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6125 return -EAGAIN;
6126 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6127 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6128 return rc;
edd16368 6129 case CCISS_BIG_PASSTHRU:
34f0c627 6130 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6131 return -EAGAIN;
6132 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6133 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6134 return rc;
edd16368
SC		 6135 default:
6136 return -ENOTTY;
6137 }
6138}
6139
bf43caf3 6140static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6141 u8 reset_type)
64670ac8
SC		 6142{
6143 struct CommandList *c;
6144
6145 c = cmd_alloc(h);
bf43caf3 6146
a2dac136
SC		 6147 /* fill_cmd can't fail here, no data buffer to map */
6148 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6149 RAID_CTLR_LUNID, TYPE_MSG);
6150 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6151 c->waiting = NULL;
6152 enqueue_cmd_and_start_io(h, c);
6153 /* Don't wait for completion, the reset won't complete. Don't free
6154 * the command either. This is the last command we will send before
6155 * re-initializing everything, so it doesn't matter and won't leak.
6156 */
bf43caf3 6157 return;
64670ac8
SC		 6158}
6159
a2dac136 6160static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6161 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6162 int cmd_type)
6163{
6164 int pci_dir = XFER_NONE;
9b5c48c2 6165 u64 tag; /* for commands to be aborted */
edd16368
SC		 6166
6167 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6168 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6169 c->Header.ReplyQueue = 0;
6170 if (buff != NULL && size > 0) {
6171 c->Header.SGList = 1;
50a0decf 6172 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6173 } else {
6174 c->Header.SGList = 0;
50a0decf 6175 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6176 }
edd16368
SC		 6177 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6178
edd16368
SC		 6179 if (cmd_type == TYPE_CMD) {
6180 switch (cmd) {
6181 case HPSA_INQUIRY:
6182 /* are we trying to read a vital product page */
b7bb24eb 6183 if (page_code & VPD_PAGE) {
edd16368 6184 c->Request.CDB[1] = 0x01;
b7bb24eb 6185 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6186 }
6187 c->Request.CDBLen = 6;
a505b86f
SC		 6188 c->Request.type_attr_dir =
6189 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6190 c->Request.Timeout = 0;
6191 c->Request.CDB[0] = HPSA_INQUIRY;
6192 c->Request.CDB[4] = size & 0xFF;
6193 break;
6194 case HPSA_REPORT_LOG:
6195 case HPSA_REPORT_PHYS:
6196 /* Talking to controller so It's a physical command
6197 mode = 00 target = 0. Nothing to write.
6198 */
6199 c->Request.CDBLen = 12;
a505b86f
SC		 6200 c->Request.type_attr_dir =
6201 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6202 c->Request.Timeout = 0;
6203 c->Request.CDB[0] = cmd;
6204 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6205 c->Request.CDB[7] = (size >> 16) & 0xFF;
6206 c->Request.CDB[8] = (size >> 8) & 0xFF;
6207 c->Request.CDB[9] = size & 0xFF;
6208 break;
edd16368
SC		 6209 case HPSA_CACHE_FLUSH:
6210 c->Request.CDBLen = 12;
a505b86f
SC		 6211 c->Request.type_attr_dir =
6212 TYPE_ATTR_DIR(cmd_type,
6213 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6214 c->Request.Timeout = 0;
6215 c->Request.CDB[0] = BMIC_WRITE;
6216 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6217 c->Request.CDB[7] = (size >> 8) & 0xFF;
6218 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6219 break;
6220 case TEST_UNIT_READY:
6221 c->Request.CDBLen = 6;
a505b86f
SC		 6222 c->Request.type_attr_dir =
6223 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6224 c->Request.Timeout = 0;
6225 break;
283b4a9b
SC		 6226 case HPSA_GET_RAID_MAP:
6227 c->Request.CDBLen = 12;
a505b86f
SC		 6228 c->Request.type_attr_dir =
6229 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6230 c->Request.Timeout = 0;
6231 c->Request.CDB[0] = HPSA_CISS_READ;
6232 c->Request.CDB[1] = cmd;
6233 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6234 c->Request.CDB[7] = (size >> 16) & 0xFF;
6235 c->Request.CDB[8] = (size >> 8) & 0xFF;
6236 c->Request.CDB[9] = size & 0xFF;
6237 break;
316b221a
SC		 6238 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6239 c->Request.CDBLen = 10;
a505b86f
SC		 6240 c->Request.type_attr_dir =
6241 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6242 c->Request.Timeout = 0;
6243 c->Request.CDB[0] = BMIC_READ;
6244 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6245 c->Request.CDB[7] = (size >> 16) & 0xFF;
6246 c->Request.CDB[8] = (size >> 8) & 0xFF;
6247 break;
03383736
DB		 6248 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6249 c->Request.CDBLen = 10;
6250 c->Request.type_attr_dir =
6251 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6252 c->Request.Timeout = 0;
6253 c->Request.CDB[0] = BMIC_READ;
6254 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6255 c->Request.CDB[7] = (size >> 16) & 0xFF;
6256 c->Request.CDB[8] = (size >> 8) & 0XFF;
6257 break;
edd16368
SC		 6258 default:
6259 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6260 BUG();
a2dac136 6261 return -1;
edd16368
SC		 6262 }
6263 } else if (cmd_type == TYPE_MSG) {
6264 switch (cmd) {
6265
6266 case HPSA_DEVICE_RESET_MSG:
6267 c->Request.CDBLen = 16;
a505b86f
SC		 6268 c->Request.type_attr_dir =
6269 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6270 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6271 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6272 c->Request.CDB[0] = cmd;
21e89afd 6273 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6274 /* If bytes 4-7 are zero, it means reset the */
6275 /* LunID device */
6276 c->Request.CDB[4] = 0x00;
6277 c->Request.CDB[5] = 0x00;
6278 c->Request.CDB[6] = 0x00;
6279 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6280 break;
6281 case HPSA_ABORT_MSG:
9b5c48c2 6282 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6283 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6284 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6285 tag, c->Header.tag);
75167d2c 6286 c->Request.CDBLen = 16;
a505b86f
SC		 6287 c->Request.type_attr_dir =
6288 TYPE_ATTR_DIR(cmd_type,
6289 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6290 c->Request.Timeout = 0; /* Don't time out */
6291 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6292 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6293 c->Request.CDB[2] = 0x00; /* reserved */
6294 c->Request.CDB[3] = 0x00; /* reserved */
6295 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6296 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6297 c->Request.CDB[12] = 0x00; /* reserved */
6298 c->Request.CDB[13] = 0x00; /* reserved */
6299 c->Request.CDB[14] = 0x00; /* reserved */
6300 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6301 break;
edd16368
SC		 6302 default:
6303 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6304 cmd);
6305 BUG();
6306 }
6307 } else {
6308 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6309 BUG();
6310 }
6311
a505b86f 6312 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6313 case XFER_READ:
6314 pci_dir = PCI_DMA_FROMDEVICE;
6315 break;
6316 case XFER_WRITE:
6317 pci_dir = PCI_DMA_TODEVICE;
6318 break;
6319 case XFER_NONE:
6320 pci_dir = PCI_DMA_NONE;
6321 break;
6322 default:
6323 pci_dir = PCI_DMA_BIDIRECTIONAL;
6324 }
a2dac136
SC		 6325 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6326 return -1;
6327 return 0;
edd16368
SC		 6328}
6329
6330/*
6331 * Map (physical) PCI mem into (virtual) kernel space
6332 */
6333static void __iomem *remap_pci_mem(ulong base, ulong size)
6334{
6335 ulong page_base = ((ulong) base) & PAGE_MASK;
6336 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6337 void __iomem *page_remapped = ioremap_nocache(page_base,
6338 page_offs + size);
edd16368
SC		 6339
6340 return page_remapped ? (page_remapped + page_offs) : NULL;
6341}
6342
254f796b 6343static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6344{
254f796b 6345 return h->access.command_completed(h, q);
edd16368
SC		 6346}
6347
900c5440 6348static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6349{
6350 return h->access.intr_pending(h);
6351}
6352
6353static inline long interrupt_not_for_us(struct ctlr_info *h)
6354{
10f66018
SC		 6355 return (h->access.intr_pending(h) == 0) ||
6356 (h->interrupts_enabled == 0);
edd16368
SC		 6357}
6358
01a02ffc
SC		 6359static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6360 u32 raw_tag)
edd16368
SC		 6361{
6362 if (unlikely(tag_index >= h->nr_cmds)) {
6363 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6364 return 1;
6365 }
6366 return 0;
6367}
6368
5a3d16f5 6369static inline void finish_cmd(struct CommandList *c)
edd16368 6370{
e85c5974 6371 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6372 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6373 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6374 complete_scsi_command(c);
8be986cc 6375 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6376 complete(c->waiting);
a104c99f
SC		 6377}
6378
a9a3a273
SC		 6379
6380static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 6381{
a9a3a273
SC		 6382#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
6383#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 6384 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 6385 return tag & ~HPSA_SIMPLE_ERROR_BITS;
6386 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 6387}
6388
303932fd 6389/* process completion of an indexed ("direct lookup") command */
1d94f94d 6390static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6391 u32 raw_tag)
6392{
6393 u32 tag_index;
6394 struct CommandList *c;
6395
f2405db8 6396 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6397 if (!bad_tag(h, tag_index, raw_tag)) {
6398 c = h->cmd_pool + tag_index;
6399 finish_cmd(c);
6400 }
303932fd
DB		 6401}
6402
64670ac8
SC		 6403/* Some controllers, like p400, will give us one interrupt
6404 * after a soft reset, even if we turned interrupts off.
6405 * Only need to check for this in the hpsa_xxx_discard_completions
6406 * functions.
6407 */
6408static int ignore_bogus_interrupt(struct ctlr_info *h)
6409{
6410 if (likely(!reset_devices))
6411 return 0;
6412
6413 if (likely(h->interrupts_enabled))
6414 return 0;
6415
6416 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6417 "(known firmware bug.) Ignoring.\n");
6418
6419 return 1;
6420}
6421
254f796b
MG		 6422/*
6423 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6424 * Relies on (h-q[x] == x) being true for x such that
6425 * 0 <= x < MAX_REPLY_QUEUES.
6426 */
6427static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6428{
254f796b
MG		 6429 return container_of((queue - *queue), struct ctlr_info, q[0]);
6430}
6431
6432static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6433{
6434 struct ctlr_info *h = queue_to_hba(queue);
6435 u8 q = *(u8 *) queue;
64670ac8
SC		 6436 u32 raw_tag;
6437
6438 if (ignore_bogus_interrupt(h))
6439 return IRQ_NONE;
6440
6441 if (interrupt_not_for_us(h))
6442 return IRQ_NONE;
a0c12413 6443 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6444 while (interrupt_pending(h)) {
254f796b 6445 raw_tag = get_next_completion(h, q);
64670ac8 6446 while (raw_tag != FIFO_EMPTY)
254f796b 6447 raw_tag = next_command(h, q);
64670ac8 6448 }
64670ac8
SC		 6449 return IRQ_HANDLED;
6450}
6451
254f796b 6452static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6453{
254f796b 6454 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6455 u32 raw_tag;
254f796b 6456 u8 q = *(u8 *) queue;
64670ac8
SC		 6457
6458 if (ignore_bogus_interrupt(h))
6459 return IRQ_NONE;
6460
a0c12413 6461 h->last_intr_timestamp = get_jiffies_64();
254f796b 6462 raw_tag = get_next_completion(h, q);
64670ac8 6463 while (raw_tag != FIFO_EMPTY)
254f796b 6464 raw_tag = next_command(h, q);
64670ac8
SC		 6465 return IRQ_HANDLED;
6466}
6467
254f796b 6468static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6469{
254f796b 6470 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6471 u32 raw_tag;
254f796b 6472 u8 q = *(u8 *) queue;
edd16368
SC		 6473
6474 if (interrupt_not_for_us(h))
6475 return IRQ_NONE;
a0c12413 6476 h->last_intr_timestamp = get_jiffies_64();
10f66018 6477 while (interrupt_pending(h)) {
254f796b 6478 raw_tag = get_next_completion(h, q);
10f66018 6479 while (raw_tag != FIFO_EMPTY) {
f2405db8 6480 process_indexed_cmd(h, raw_tag);
254f796b 6481 raw_tag = next_command(h, q);
10f66018
SC		 6482 }
6483 }
10f66018
SC		 6484 return IRQ_HANDLED;
6485}
6486
254f796b 6487static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6488{
254f796b 6489 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6490 u32 raw_tag;
254f796b 6491 u8 q = *(u8 *) queue;
10f66018 6492
a0c12413 6493 h->last_intr_timestamp = get_jiffies_64();
254f796b 6494 raw_tag = get_next_completion(h, q);
303932fd 6495 while (raw_tag != FIFO_EMPTY) {
f2405db8 6496 process_indexed_cmd(h, raw_tag);
254f796b 6497 raw_tag = next_command(h, q);
edd16368 6498 }
edd16368
SC		 6499 return IRQ_HANDLED;
6500}
6501
a9a3a273
SC		 6502/* Send a message CDB to the firmware. Careful, this only works
6503 * in simple mode, not performant mode due to the tag lookup.
6504 * We only ever use this immediately after a controller reset.
6505 */
6f039790
GKH		 6506static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6507 unsigned char type)
edd16368
SC		 6508{
6509 struct Command {
6510 struct CommandListHeader CommandHeader;
6511 struct RequestBlock Request;
6512 struct ErrDescriptor ErrorDescriptor;
6513 };
6514 struct Command *cmd;
6515 static const size_t cmd_sz = sizeof(*cmd) +
6516 sizeof(cmd->ErrorDescriptor);
6517 dma_addr_t paddr64;
2b08b3e9
DB		 6518 __le32 paddr32;
6519 u32 tag;
edd16368
SC		 6520 void __iomem *vaddr;
6521 int i, err;
6522
6523 vaddr = pci_ioremap_bar(pdev, 0);
6524 if (vaddr == NULL)
6525 return -ENOMEM;
6526
6527 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6528 * CCISS commands, so they must be allocated from the lower 4GiB of
6529 * memory.
6530 */
6531 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6532 if (err) {
6533 iounmap(vaddr);
1eaec8f3 6534 return err;
edd16368
SC		 6535 }
6536
6537 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6538 if (cmd == NULL) {
6539 iounmap(vaddr);
6540 return -ENOMEM;
6541 }
6542
6543 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6544 * although there's no guarantee, we assume that the address is at
6545 * least 4-byte aligned (most likely, it's page-aligned).
6546 */
2b08b3e9 6547 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6548
6549 cmd->CommandHeader.ReplyQueue = 0;
6550 cmd->CommandHeader.SGList = 0;
50a0decf 6551 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6552 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6553 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6554
6555 cmd->Request.CDBLen = 16;
a505b86f
SC		 6556 cmd->Request.type_attr_dir =
6557 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6558 cmd->Request.Timeout = 0; /* Don't time out */
6559 cmd->Request.CDB[0] = opcode;
6560 cmd->Request.CDB[1] = type;
6561 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6562 cmd->ErrorDescriptor.Addr =
2b08b3e9 6563 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6564 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6565
2b08b3e9 6566 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6567
6568 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6569 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6570 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6571 break;
6572 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6573 }
6574
6575 iounmap(vaddr);
6576
6577 /* we leak the DMA buffer here ... no choice since the controller could
6578 * still complete the command.
6579 */
6580 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6581 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6582 opcode, type);
6583 return -ETIMEDOUT;
6584 }
6585
6586 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6587
6588 if (tag & HPSA_ERROR_BIT) {
6589 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6590 opcode, type);
6591 return -EIO;
6592 }
6593
6594 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6595 opcode, type);
6596 return 0;
6597}
6598
edd16368
SC		 6599#define hpsa_noop(p) hpsa_message(p, 3, 0)
6600
1df8552a 6601static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6602 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6603{
1df8552a
SC		 6604
6605 if (use_doorbell) {
6606 /* For everything after the P600, the PCI power state method
6607 * of resetting the controller doesn't work, so we have this
6608 * other way using the doorbell register.
6609 */
6610 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6611 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6612
00701a96 6613 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6614 * doorbell reset and before any attempt to talk to the board
6615 * at all to ensure that this actually works and doesn't fall
6616 * over in some weird corner cases.
6617 */
00701a96 6618 msleep(10000);
1df8552a
SC		 6619 } else { /* Try to do it the PCI power state way */
6620
6621 /* Quoting from the Open CISS Specification: "The Power
6622 * Management Control/Status Register (CSR) controls the power
6623 * state of the device. The normal operating state is D0,
6624 * CSR=00h. The software off state is D3, CSR=03h. To reset
6625 * the controller, place the interface device in D3 then to D0,
6626 * this causes a secondary PCI reset which will reset the
6627 * controller." */
2662cab8
DB		 6628
6629 int rc = 0;
6630
1df8552a 6631 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6632
1df8552a 6633 /* enter the D3hot power management state */
2662cab8
DB		 6634 rc = pci_set_power_state(pdev, PCI_D3hot);
6635 if (rc)
6636 return rc;
1df8552a
SC		 6637
6638 msleep(500);
6639
6640 /* enter the D0 power management state */
2662cab8
DB		 6641 rc = pci_set_power_state(pdev, PCI_D0);
6642 if (rc)
6643 return rc;
c4853efe
MM		 6644
6645 /*
6646 * The P600 requires a small delay when changing states.
6647 * Otherwise we may think the board did not reset and we bail.
6648 * This for kdump only and is particular to the P600.
6649 */
6650 msleep(500);
1df8552a
SC		 6651 }
6652 return 0;
6653}
6654
6f039790 6655static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6656{
6657 memset(driver_version, 0, len);
f79cfec6 6658 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6659}
6660
6f039790 6661static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6662{
6663 char *driver_version;
6664 int i, size = sizeof(cfgtable->driver_version);
6665
6666 driver_version = kmalloc(size, GFP_KERNEL);
6667 if (!driver_version)
6668 return -ENOMEM;
6669
6670 init_driver_version(driver_version, size);
6671 for (i = 0; i < size; i++)
6672 writeb(driver_version[i], &cfgtable->driver_version[i]);
6673 kfree(driver_version);
6674 return 0;
6675}
6676
6f039790
GKH		 6677static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6678 unsigned char *driver_ver)
580ada3c
SC		 6679{
6680 int i;
6681
6682 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6683 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6684}
6685
6f039790 6686static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6687{
6688
6689 char *driver_ver, *old_driver_ver;
6690 int rc, size = sizeof(cfgtable->driver_version);
6691
6692 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6693 if (!old_driver_ver)
6694 return -ENOMEM;
6695 driver_ver = old_driver_ver + size;
6696
6697 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6698 * should have been changed, otherwise we know the reset failed.
6699 */
6700 init_driver_version(old_driver_ver, size);
6701 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6702 rc = !memcmp(driver_ver, old_driver_ver, size);
6703 kfree(old_driver_ver);
6704 return rc;
6705}
edd16368 6706/* This does a hard reset of the controller using PCI power management
1df8552a 6707 * states or the using the doorbell register.
edd16368 6708 */
6b6c1cd7 6709static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6710{
1df8552a
SC		 6711 u64 cfg_offset;
6712 u32 cfg_base_addr;
6713 u64 cfg_base_addr_index;
6714 void __iomem *vaddr;
6715 unsigned long paddr;
580ada3c 6716 u32 misc_fw_support;
270d05de 6717 int rc;
1df8552a 6718 struct CfgTable __iomem *cfgtable;
cf0b08d0 6719 u32 use_doorbell;
270d05de 6720 u16 command_register;
edd16368 6721
1df8552a
SC		 6722 /* For controllers as old as the P600, this is very nearly
6723 * the same thing as
edd16368
SC		 6724 *
6725 * pci_save_state(pci_dev);
6726 * pci_set_power_state(pci_dev, PCI_D3hot);
6727 * pci_set_power_state(pci_dev, PCI_D0);
6728 * pci_restore_state(pci_dev);
6729 *
1df8552a
SC		 6730 * For controllers newer than the P600, the pci power state
6731 * method of resetting doesn't work so we have another way
6732 * using the doorbell register.
edd16368 6733 */
18867659 6734
60f923b9
RE		 6735 if (!ctlr_is_resettable(board_id)) {
6736 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6737 return -ENODEV;
6738 }
46380786
SC		 6739
6740 /* if controller is soft- but not hard resettable... */
6741 if (!ctlr_is_hard_resettable(board_id))
6742 return -ENOTSUPP; /* try soft reset later. */
18867659 6743
270d05de
SC		 6744 /* Save the PCI command register */
6745 pci_read_config_word(pdev, 4, &command_register);
270d05de 6746 pci_save_state(pdev);
edd16368 6747
1df8552a
SC		 6748 /* find the first memory BAR, so we can find the cfg table */
6749 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6750 if (rc)
6751 return rc;
6752 vaddr = remap_pci_mem(paddr, 0x250);
6753 if (!vaddr)
6754 return -ENOMEM;
edd16368 6755
1df8552a
SC		 6756 /* find cfgtable in order to check if reset via doorbell is supported */
6757 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6758 &cfg_base_addr_index, &cfg_offset);
6759 if (rc)
6760 goto unmap_vaddr;
6761 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6762 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6763 if (!cfgtable) {
6764 rc = -ENOMEM;
6765 goto unmap_vaddr;
6766 }
580ada3c
SC		 6767 rc = write_driver_ver_to_cfgtable(cfgtable);
6768 if (rc)
03741d95 6769 goto unmap_cfgtable;
edd16368 6770
cf0b08d0
SC		 6771 /* If reset via doorbell register is supported, use that.
6772 * There are two such methods. Favor the newest method.
6773 */
1df8552a 6774 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6775 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6776 if (use_doorbell) {
6777 use_doorbell = DOORBELL_CTLR_RESET2;
6778 } else {
6779 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6780 if (use_doorbell) {
050f7147
SC		 6781 dev_warn(&pdev->dev,
6782 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6783 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6784 goto unmap_cfgtable;
6785 }
6786 }
edd16368 6787
1df8552a
SC		 6788 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6789 if (rc)
6790 goto unmap_cfgtable;
edd16368 6791
270d05de 6792 pci_restore_state(pdev);
270d05de 6793 pci_write_config_word(pdev, 4, command_register);
edd16368 6794
1df8552a
SC		 6795 /* Some devices (notably the HP Smart Array 5i Controller)
6796 need a little pause here */
6797 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6798
fe5389c8
SC		 6799 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6800 if (rc) {
6801 dev_warn(&pdev->dev,
050f7147 6802 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6803 goto unmap_cfgtable;
6804 }
fe5389c8 6805
580ada3c
SC		 6806 rc = controller_reset_failed(vaddr);
6807 if (rc < 0)
6808 goto unmap_cfgtable;
6809 if (rc) {
64670ac8
SC		 6810 dev_warn(&pdev->dev, "Unable to successfully reset "
6811 "controller. Will try soft reset.\n");
6812 rc = -ENOTSUPP;
580ada3c 6813 } else {
64670ac8 6814 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6815 }
6816
6817unmap_cfgtable:
6818 iounmap(cfgtable);
6819
6820unmap_vaddr:
6821 iounmap(vaddr);
6822 return rc;
edd16368
SC		 6823}
6824
6825/*
6826 * We cannot read the structure directly, for portability we must use
6827 * the io functions.
6828 * This is for debug only.
6829 */
42a91641 6830static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6831{
58f8665c 6832#ifdef HPSA_DEBUG
edd16368
SC		 6833 int i;
6834 char temp_name[17];
6835
6836 dev_info(dev, "Controller Configuration information\n");
6837 dev_info(dev, "------------------------------------\n");
6838 for (i = 0; i < 4; i++)
6839 temp_name[i] = readb(&(tb->Signature[i]));
6840 temp_name[4] = '\0';
6841 dev_info(dev, " Signature = %s\n", temp_name);
6842 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6843 dev_info(dev, " Transport methods supported = 0x%x\n",
6844 readl(&(tb->TransportSupport)));
6845 dev_info(dev, " Transport methods active = 0x%x\n",
6846 readl(&(tb->TransportActive)));
6847 dev_info(dev, " Requested transport Method = 0x%x\n",
6848 readl(&(tb->HostWrite.TransportRequest)));
6849 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6850 readl(&(tb->HostWrite.CoalIntDelay)));
6851 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6852 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6853 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6854 readl(&(tb->CmdsOutMax)));
6855 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6856 for (i = 0; i < 16; i++)
6857 temp_name[i] = readb(&(tb->ServerName[i]));
6858 temp_name[16] = '\0';
6859 dev_info(dev, " Server Name = %s\n", temp_name);
6860 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6861 readl(&(tb->HeartBeat)));
edd16368 6862#endif /* HPSA_DEBUG */
58f8665c 6863}
edd16368
SC		 6864
6865static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6866{
6867 int i, offset, mem_type, bar_type;
6868
6869 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6870 return 0;
6871 offset = 0;
6872 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6873 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6874 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6875 offset += 4;
6876 else {
6877 mem_type = pci_resource_flags(pdev, i) &
6878 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6879 switch (mem_type) {
6880 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6881 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6882 offset += 4; /* 32 bit */
6883 break;
6884 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6885 offset += 8;
6886 break;
6887 default: /* reserved in PCI 2.2 */
6888 dev_warn(&pdev->dev,
6889 "base address is invalid\n");
6890 return -1;
6891 break;
6892 }
6893 }
6894 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6895 return i + 1;
6896 }
6897 return -1;
6898}
6899
cc64c817
RE		 6900static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6901{
6902 if (h->msix_vector) {
6903 if (h->pdev->msix_enabled)
6904 pci_disable_msix(h->pdev);
105a3dbc 6905 h->msix_vector = 0;
cc64c817
RE		 6906 } else if (h->msi_vector) {
6907 if (h->pdev->msi_enabled)
6908 pci_disable_msi(h->pdev);
105a3dbc 6909 h->msi_vector = 0;
cc64c817
RE		 6910 }
6911}
6912
edd16368 6913/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6914 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6915 */
6f039790 6916static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6917{
6918#ifdef CONFIG_PCI_MSI
254f796b
MG		 6919 int err, i;
6920 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6921
6922 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6923 hpsa_msix_entries[i].vector = 0;
6924 hpsa_msix_entries[i].entry = i;
6925 }
edd16368
SC		 6926
6927 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6928 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6929 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6930 goto default_int_mode;
55c06c71 6931 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6932 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6933 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6934 if (h->msix_vector > num_online_cpus())
6935 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6936 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6937 1, h->msix_vector);
6938 if (err < 0) {
6939 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6940 h->msix_vector = 0;
6941 goto single_msi_mode;
6942 } else if (err < h->msix_vector) {
55c06c71 6943 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6944 "available\n", err);
edd16368 6945 }
18fce3c4
AG		 6946 h->msix_vector = err;
6947 for (i = 0; i < h->msix_vector; i++)
6948 h->intr[i] = hpsa_msix_entries[i].vector;
6949 return;
edd16368 6950 }
18fce3c4 6951single_msi_mode:
55c06c71 6952 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6953 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6954 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6955 h->msi_vector = 1;
6956 else
55c06c71 6957 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6958 }
6959default_int_mode:
6960#endif /* CONFIG_PCI_MSI */
6961 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6962 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6963}
6964
6f039790 6965static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6966{
6967 int i;
6968 u32 subsystem_vendor_id, subsystem_device_id;
6969
6970 subsystem_vendor_id = pdev->subsystem_vendor;
6971 subsystem_device_id = pdev->subsystem_device;
6972 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6973 subsystem_vendor_id;
6974
6975 for (i = 0; i < ARRAY_SIZE(products); i++)
6976 if (*board_id == products[i].board_id)
6977 return i;
6978
6798cc0a
SC		 6979 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6980 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6981 !hpsa_allow_any) {
e5c880d1
SC		 6982 dev_warn(&pdev->dev, "unrecognized board ID: "
6983 "0x%08x, ignoring.\n", *board_id);
6984 return -ENODEV;
6985 }
6986 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6987}
6988
6f039790
GKH		 6989static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6990 unsigned long *memory_bar)
3a7774ce
SC		 6991{
6992 int i;
6993
6994 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6995 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6996 /* addressing mode bits already removed */
12d2cd47
SC		 6997 *memory_bar = pci_resource_start(pdev, i);
6998 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6999 *memory_bar);
7000 return 0;
7001 }
12d2cd47 7002 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7003 return -ENODEV;
7004}
7005
6f039790
GKH		 7006static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7007 int wait_for_ready)
2c4c8c8b 7008{
fe5389c8 7009 int i, iterations;
2c4c8c8b 7010 u32 scratchpad;
fe5389c8
SC		 7011 if (wait_for_ready)
7012 iterations = HPSA_BOARD_READY_ITERATIONS;
7013 else
7014 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7015
fe5389c8
SC		 7016 for (i = 0; i < iterations; i++) {
7017 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7018 if (wait_for_ready) {
7019 if (scratchpad == HPSA_FIRMWARE_READY)
7020 return 0;
7021 } else {
7022 if (scratchpad != HPSA_FIRMWARE_READY)
7023 return 0;
7024 }
2c4c8c8b
SC		 7025 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7026 }
fe5389c8 7027 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7028 return -ENODEV;
7029}
7030
6f039790
GKH		 7031static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7032 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7033 u64 *cfg_offset)
a51fd47f
SC		 7034{
7035 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7036 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7037 *cfg_base_addr &= (u32) 0x0000ffff;
7038 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7039 if (*cfg_base_addr_index == -1) {
7040 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7041 return -ENODEV;
7042 }
7043 return 0;
7044}
7045
195f2c65
RE		 7046static void hpsa_free_cfgtables(struct ctlr_info *h)
7047{
105a3dbc 7048 if (h->transtable) {
195f2c65 7049 iounmap(h->transtable);
105a3dbc
RE		 7050 h->transtable = NULL;
7051 }
7052 if (h->cfgtable) {
195f2c65 7053 iounmap(h->cfgtable);
105a3dbc
RE		 7054 h->cfgtable = NULL;
7055 }
195f2c65
RE		 7056}
7057
7058/* Find and map CISS config table and transfer table
7059+ * several items must be unmapped (freed) later
7060+ * */
6f039790 7061static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7062{
01a02ffc
SC		 7063 u64 cfg_offset;
7064 u32 cfg_base_addr;
7065 u64 cfg_base_addr_index;
303932fd 7066 u32 trans_offset;
a51fd47f 7067 int rc;
77c4495c 7068
a51fd47f
SC		 7069 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7070 &cfg_base_addr_index, &cfg_offset);
7071 if (rc)
7072 return rc;
77c4495c 7073 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7074 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7075 if (!h->cfgtable) {
7076 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7077 return -ENOMEM;
cd3c81c4 7078 }
580ada3c
SC		 7079 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7080 if (rc)
7081 return rc;
77c4495c 7082 /* Find performant mode table. */
a51fd47f 7083 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7084 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7085 cfg_base_addr_index)+cfg_offset+trans_offset,
7086 sizeof(*h->transtable));
195f2c65
RE		 7087 if (!h->transtable) {
7088 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7089 hpsa_free_cfgtables(h);
77c4495c 7090 return -ENOMEM;
195f2c65 7091 }
77c4495c
SC		 7092 return 0;
7093}
7094
6f039790 7095static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7096{
41ce4c35
SC		 7097#define MIN_MAX_COMMANDS 16
7098 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7099
7100 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7101
7102 /* Limit commands in memory limited kdump scenario. */
7103 if (reset_devices && h->max_commands > 32)
7104 h->max_commands = 32;
7105
41ce4c35
SC		 7106 if (h->max_commands < MIN_MAX_COMMANDS) {
7107 dev_warn(&h->pdev->dev,
7108 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7109 h->max_commands,
7110 MIN_MAX_COMMANDS);
7111 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7112 }
7113}
7114
c7ee65b3
WS		 7115/* If the controller reports that the total max sg entries is greater than 512,
7116 * then we know that chained SG blocks work. (Original smart arrays did not
7117 * support chained SG blocks and would return zero for max sg entries.)
7118 */
7119static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7120{
7121 return h->maxsgentries > 512;
7122}
7123
b93d7536
SC		 7124/* Interrogate the hardware for some limits:
7125 * max commands, max SG elements without chaining, and with chaining,
7126 * SG chain block size, etc.
7127 */
6f039790 7128static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7129{
cba3d38b 7130 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7131 h->nr_cmds = h->max_commands;
b93d7536 7132 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7133 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7134 if (hpsa_supports_chained_sg_blocks(h)) {
7135 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7136 h->max_cmd_sg_entries = 32;
1a63ea6f 7137 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7138 h->maxsgentries--; /* save one for chain pointer */
7139 } else {
c7ee65b3
WS		 7140 /*
7141 * Original smart arrays supported at most 31 s/g entries
7142 * embedded inline in the command (trying to use more
7143 * would lock up the controller)
7144 */
7145 h->max_cmd_sg_entries = 31;
1a63ea6f 7146 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7147 h->chainsize = 0;
b93d7536 7148 }
75167d2c
SC		 7149
7150 /* Find out what task management functions are supported and cache */
7151 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7152 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7153 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7154 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7155 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7156 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7157 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7158}
7159
76c46e49
SC		 7160static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7161{
0fc9fd40 7162 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7163 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7164 return false;
7165 }
7166 return true;
7167}
7168
97a5e98c 7169static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7170{
97a5e98c 7171 u32 driver_support;
f7c39101 7172
97a5e98c 7173 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7174 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7175#ifdef CONFIG_X86
97a5e98c 7176 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7177#endif
28e13446
SC		 7178 driver_support |= ENABLE_UNIT_ATTN;
7179 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7180}
7181
3d0eab67
SC		 7182/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7183 * in a prefetch beyond physical memory.
7184 */
7185static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7186{
7187 u32 dma_prefetch;
7188
7189 if (h->board_id != 0x3225103C)
7190 return;
7191 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7192 dma_prefetch |= 0x8000;
7193 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7194}
7195
c706a795 7196static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7197{
7198 int i;
7199 u32 doorbell_value;
7200 unsigned long flags;
7201 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7202 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7203 spin_lock_irqsave(&h->lock, flags);
7204 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7205 spin_unlock_irqrestore(&h->lock, flags);
7206 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7207 goto done;
76438d08 7208 /* delay and try again */
007e7aa9 7209 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7210 }
c706a795
RE		 7211 return -ENODEV;
7212done:
7213 return 0;
76438d08
SC		 7214}
7215
c706a795 7216static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7217{
7218 int i;
6eaf46fd
SC		 7219 u32 doorbell_value;
7220 unsigned long flags;
eb6b2ae9
SC		 7221
7222 /* under certain very rare conditions, this can take awhile.
7223 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7224 * as we enter this code.)
7225 */
007e7aa9 7226 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7227 if (h->remove_in_progress)
7228 goto done;
6eaf46fd
SC		 7229 spin_lock_irqsave(&h->lock, flags);
7230 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7231 spin_unlock_irqrestore(&h->lock, flags);
382be668 7232 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7233 goto done;
eb6b2ae9 7234 /* delay and try again */
007e7aa9 7235 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7236 }
c706a795
RE		 7237 return -ENODEV;
7238done:
7239 return 0;
3f4336f3
SC		 7240}
7241
c706a795 7242/* return -ENODEV or other reason on error, 0 on success */
6f039790 7243static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7244{
7245 u32 trans_support;
7246
7247 trans_support = readl(&(h->cfgtable->TransportSupport));
7248 if (!(trans_support & SIMPLE_MODE))
7249 return -ENOTSUPP;
7250
7251 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7252
3f4336f3
SC		 7253 /* Update the field, and then ring the doorbell */
7254 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7255 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7256 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7257 if (hpsa_wait_for_mode_change_ack(h))
7258 goto error;
eb6b2ae9 7259 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7260 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7261 goto error;
960a30e7 7262 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7263 return 0;
283b4a9b 7264error:
050f7147 7265 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7266 return -ENODEV;
eb6b2ae9
SC		 7267}
7268
195f2c65
RE		 7269/* free items allocated or mapped by hpsa_pci_init */
7270static void hpsa_free_pci_init(struct ctlr_info *h)
7271{
7272 hpsa_free_cfgtables(h); /* pci_init 4 */
7273 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7274 h->vaddr = NULL;
195f2c65 7275 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7276 /*
7277 * call pci_disable_device before pci_release_regions per
7278 * Documentation/PCI/pci.txt
7279 */
195f2c65 7280 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7281 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7282}
7283
7284/* several items must be freed later */
6f039790 7285static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7286{
eb6b2ae9 7287 int prod_index, err;
edd16368 7288
e5c880d1
SC		 7289 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7290 if (prod_index < 0)
60f923b9 7291 return prod_index;
e5c880d1
SC		 7292 h->product_name = products[prod_index].product_name;
7293 h->access = *(products[prod_index].access);
edd16368 7294
9b5c48c2
SC		 7295 h->needs_abort_tags_swizzled =
7296 ctlr_needs_abort_tags_swizzled(h->board_id);
7297
e5a44df8
MG		 7298 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7299 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7300
55c06c71 7301 err = pci_enable_device(h->pdev);
edd16368 7302 if (err) {
195f2c65 7303 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7304 pci_disable_device(h->pdev);
edd16368
SC		 7305 return err;
7306 }
7307
f79cfec6 7308 err = pci_request_regions(h->pdev, HPSA);
edd16368 7309 if (err) {
55c06c71 7310 dev_err(&h->pdev->dev,
195f2c65 7311 "failed to obtain PCI resources\n");
943a7021
RE		 7312 pci_disable_device(h->pdev);
7313 return err;
edd16368 7314 }
4fa604e1
RE		 7315
7316 pci_set_master(h->pdev);
7317
6b3f4c52 7318 hpsa_interrupt_mode(h);
12d2cd47 7319 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7320 if (err)
195f2c65 7321 goto clean2; /* intmode+region, pci */
edd16368 7322 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7323 if (!h->vaddr) {
195f2c65 7324 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7325 err = -ENOMEM;
195f2c65 7326 goto clean2; /* intmode+region, pci */
204892e9 7327 }
fe5389c8 7328 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7329 if (err)
195f2c65 7330 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7331 err = hpsa_find_cfgtables(h);
7332 if (err)
195f2c65 7333 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7334 hpsa_find_board_params(h);
edd16368 7335
76c46e49 7336 if (!hpsa_CISS_signature_present(h)) {
edd16368 7337 err = -ENODEV;
195f2c65 7338 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7339 }
97a5e98c 7340 hpsa_set_driver_support_bits(h);
3d0eab67 7341 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7342 err = hpsa_enter_simple_mode(h);
7343 if (err)
195f2c65 7344 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7345 return 0;
7346
195f2c65
RE		 7347clean4: /* cfgtables, vaddr, intmode+region, pci */
7348 hpsa_free_cfgtables(h);
7349clean3: /* vaddr, intmode+region, pci */
7350 iounmap(h->vaddr);
105a3dbc 7351 h->vaddr = NULL;
195f2c65
RE		 7352clean2: /* intmode+region, pci */
7353 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7354 /*
7355 * call pci_disable_device before pci_release_regions per
7356 * Documentation/PCI/pci.txt
7357 */
195f2c65 7358 pci_disable_device(h->pdev);
943a7021 7359 pci_release_regions(h->pdev);
edd16368
SC		 7360 return err;
7361}
7362
6f039790 7363static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7364{
7365 int rc;
7366
7367#define HBA_INQUIRY_BYTE_COUNT 64
7368 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7369 if (!h->hba_inquiry_data)
7370 return;
7371 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7372 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7373 if (rc != 0) {
7374 kfree(h->hba_inquiry_data);
7375 h->hba_inquiry_data = NULL;
7376 }
7377}
7378
6b6c1cd7 7379static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7380{
1df8552a 7381 int rc, i;
3b747298 7382 void __iomem *vaddr;
4c2a8c40
SC		 7383
7384 if (!reset_devices)
7385 return 0;
7386
132aa220
TH		 7387 /* kdump kernel is loading, we don't know in which state is
7388 * the pci interface. The dev->enable_cnt is equal zero
7389 * so we call enable+disable, wait a while and switch it on.
7390 */
7391 rc = pci_enable_device(pdev);
7392 if (rc) {
7393 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7394 return -ENODEV;
7395 }
7396 pci_disable_device(pdev);
7397 msleep(260); /* a randomly chosen number */
7398 rc = pci_enable_device(pdev);
7399 if (rc) {
7400 dev_warn(&pdev->dev, "failed to enable device.\n");
7401 return -ENODEV;
7402 }
4fa604e1 7403
859c75ab 7404 pci_set_master(pdev);
4fa604e1 7405
3b747298
TH		 7406 vaddr = pci_ioremap_bar(pdev, 0);
7407 if (vaddr == NULL) {
7408 rc = -ENOMEM;
7409 goto out_disable;
7410 }
7411 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7412 iounmap(vaddr);
7413
1df8552a 7414 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7415 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7416
1df8552a
SC		 7417 /* -ENOTSUPP here means we cannot reset the controller
7418 * but it's already (and still) up and running in
18867659
SC		 7419 * "performant mode". Or, it might be 640x, which can't reset
7420 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7421 */
adf1b3a3 7422 if (rc)
132aa220 7423 goto out_disable;
4c2a8c40
SC		 7424
7425 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7426 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7427 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7428 if (hpsa_noop(pdev) == 0)
7429 break;
7430 else
7431 dev_warn(&pdev->dev, "no-op failed%s\n",
7432 (i < 11 ? "; re-trying" : ""));
7433 }
132aa220
TH		 7434
7435out_disable:
7436
7437 pci_disable_device(pdev);
7438 return rc;
4c2a8c40
SC		 7439}
7440
1fb7c98a
RE		 7441static void hpsa_free_cmd_pool(struct ctlr_info *h)
7442{
7443 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7444 h->cmd_pool_bits = NULL;
7445 if (h->cmd_pool) {
1fb7c98a
RE		 7446 pci_free_consistent(h->pdev,
7447 h->nr_cmds * sizeof(struct CommandList),
7448 h->cmd_pool,
7449 h->cmd_pool_dhandle);
105a3dbc
RE		 7450 h->cmd_pool = NULL;
7451 h->cmd_pool_dhandle = 0;
7452 }
7453 if (h->errinfo_pool) {
1fb7c98a
RE		 7454 pci_free_consistent(h->pdev,
7455 h->nr_cmds * sizeof(struct ErrorInfo),
7456 h->errinfo_pool,
7457 h->errinfo_pool_dhandle);
105a3dbc
RE		 7458 h->errinfo_pool = NULL;
7459 h->errinfo_pool_dhandle = 0;
7460 }
1fb7c98a
RE		 7461}
7462
d37ffbe4 7463static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7464{
7465 h->cmd_pool_bits = kzalloc(
7466 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7467 sizeof(unsigned long), GFP_KERNEL);
7468 h->cmd_pool = pci_alloc_consistent(h->pdev,
7469 h->nr_cmds * sizeof(*h->cmd_pool),
7470 &(h->cmd_pool_dhandle));
7471 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7472 h->nr_cmds * sizeof(*h->errinfo_pool),
7473 &(h->errinfo_pool_dhandle));
7474 if ((h->cmd_pool_bits == NULL)
7475 || (h->cmd_pool == NULL)
7476 || (h->errinfo_pool == NULL)) {
7477 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7478 goto clean_up;
2e9d1b36 7479 }
360c73bd 7480 hpsa_preinitialize_commands(h);
2e9d1b36 7481 return 0;
2c143342
RE		 7482clean_up:
7483 hpsa_free_cmd_pool(h);
7484 return -ENOMEM;
2e9d1b36
SC		 7485}
7486
41b3cf08
SC		 7487static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7488{
ec429952 7489 int i, cpu;
41b3cf08
SC		 7490
7491 cpu = cpumask_first(cpu_online_mask);
7492 for (i = 0; i < h->msix_vector; i++) {
ec429952 7493 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7494 cpu = cpumask_next(cpu, cpu_online_mask);
7495 }
7496}
7497
ec501a18
RE		 7498/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7499static void hpsa_free_irqs(struct ctlr_info *h)
7500{
7501 int i;
7502
7503 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7504 /* Single reply queue, only one irq to free */
7505 i = h->intr_mode;
7506 irq_set_affinity_hint(h->intr[i], NULL);
7507 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7508 h->q[i] = 0;
ec501a18
RE		 7509 return;
7510 }
7511
7512 for (i = 0; i < h->msix_vector; i++) {
7513 irq_set_affinity_hint(h->intr[i], NULL);
7514 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7515 h->q[i] = 0;
ec501a18 7516 }
a4e17fc1
RE		 7517 for (; i < MAX_REPLY_QUEUES; i++)
7518 h->q[i] = 0;
ec501a18
RE		 7519}
7520
9ee61794
RE		 7521/* returns 0 on success; cleans up and returns -Enn on error */
7522static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7523 irqreturn_t (*msixhandler)(int, void *),
7524 irqreturn_t (*intxhandler)(int, void *))
7525{
254f796b 7526 int rc, i;
0ae01a32 7527
254f796b
MG		 7528 /*
7529 * initialize h->q[x] = x so that interrupt handlers know which
7530 * queue to process.
7531 */
7532 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7533 h->q[i] = (u8) i;
7534
eee0f03a 7535 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7536 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7537 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7538 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7539 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7540 0, h->intrname[i],
254f796b 7541 &h->q[i]);
a4e17fc1
RE		 7542 if (rc) {
7543 int j;
7544
7545 dev_err(&h->pdev->dev,
7546 "failed to get irq %d for %s\n",
7547 h->intr[i], h->devname);
7548 for (j = 0; j < i; j++) {
7549 free_irq(h->intr[j], &h->q[j]);
7550 h->q[j] = 0;
7551 }
7552 for (; j < MAX_REPLY_QUEUES; j++)
7553 h->q[j] = 0;
7554 return rc;
7555 }
7556 }
41b3cf08 7557 hpsa_irq_affinity_hints(h);
254f796b
MG		 7558 } else {
7559 /* Use single reply pool */
eee0f03a 7560 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7561 if (h->msix_vector)
7562 sprintf(h->intrname[h->intr_mode],
7563 "%s-msix", h->devname);
7564 else
7565 sprintf(h->intrname[h->intr_mode],
7566 "%s-msi", h->devname);
254f796b 7567 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7568 msixhandler, 0,
7569 h->intrname[h->intr_mode],
254f796b
MG		 7570 &h->q[h->intr_mode]);
7571 } else {
8b47004a
RE		 7572 sprintf(h->intrname[h->intr_mode],
7573 "%s-intx", h->devname);
254f796b 7574 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7575 intxhandler, IRQF_SHARED,
7576 h->intrname[h->intr_mode],
254f796b
MG		 7577 &h->q[h->intr_mode]);
7578 }
105a3dbc 7579 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7580 }
0ae01a32 7581 if (rc) {
195f2c65 7582 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7583 h->intr[h->intr_mode], h->devname);
195f2c65 7584 hpsa_free_irqs(h);
0ae01a32
SC		 7585 return -ENODEV;
7586 }
7587 return 0;
7588}
7589
6f039790 7590static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7591{
39c53f55 7592 int rc;
bf43caf3 7593 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7594
7595 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7596 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7597 if (rc) {
64670ac8 7598 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7599 return rc;
64670ac8
SC		 7600 }
7601
7602 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7603 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7604 if (rc) {
64670ac8
SC		 7605 dev_warn(&h->pdev->dev, "Board failed to become ready "
7606 "after soft reset.\n");
39c53f55 7607 return rc;
64670ac8
SC		 7608 }
7609
7610 return 0;
7611}
7612
072b0518
SC		 7613static void hpsa_free_reply_queues(struct ctlr_info *h)
7614{
7615 int i;
7616
7617 for (i = 0; i < h->nreply_queues; i++) {
7618 if (!h->reply_queue[i].head)
7619 continue;
1fb7c98a
RE		 7620 pci_free_consistent(h->pdev,
7621 h->reply_queue_size,
7622 h->reply_queue[i].head,
7623 h->reply_queue[i].busaddr);
072b0518
SC		 7624 h->reply_queue[i].head = NULL;
7625 h->reply_queue[i].busaddr = 0;
7626 }
105a3dbc 7627 h->reply_queue_size = 0;
072b0518
SC		 7628}
7629
0097f0f4
SC		 7630static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7631{
105a3dbc
RE		 7632 hpsa_free_performant_mode(h); /* init_one 7 */
7633 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7634 hpsa_free_cmd_pool(h); /* init_one 5 */
7635 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7636 scsi_host_put(h->scsi_host); /* init_one 3 */
7637 h->scsi_host = NULL; /* init_one 3 */
7638 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7639 free_percpu(h->lockup_detected); /* init_one 2 */
7640 h->lockup_detected = NULL; /* init_one 2 */
7641 if (h->resubmit_wq) {
7642 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7643 h->resubmit_wq = NULL;
7644 }
7645 if (h->rescan_ctlr_wq) {
7646 destroy_workqueue(h->rescan_ctlr_wq);
7647 h->rescan_ctlr_wq = NULL;
7648 }
105a3dbc 7649 kfree(h); /* init_one 1 */
64670ac8
SC		 7650}
7651
a0c12413 7652/* Called when controller lockup detected. */
f2405db8 7653static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7654{
281a7fd0
WS		 7655 int i, refcount;
7656 struct CommandList *c;
25163bd5 7657 int failcount = 0;
a0c12413 7658
080ef1cc 7659 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7660 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7661 c = h->cmd_pool + i;
281a7fd0
WS		 7662 refcount = atomic_inc_return(&c->refcount);
7663 if (refcount > 1) {
25163bd5 7664 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7665 finish_cmd(c);
433b5f4d 7666 atomic_dec(&h->commands_outstanding);
25163bd5 7667 failcount++;
281a7fd0
WS		 7668 }
7669 cmd_free(h, c);
a0c12413 7670 }
25163bd5
WS		 7671 dev_warn(&h->pdev->dev,
7672 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7673}
7674
094963da
SC		 7675static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7676{
c8ed0010 7677 int cpu;
094963da 7678
c8ed0010 7679 for_each_online_cpu(cpu) {
094963da
SC		 7680 u32 *lockup_detected;
7681 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7682 *lockup_detected = value;
094963da
SC		 7683 }
7684 wmb(); /* be sure the per-cpu variables are out to memory */
7685}
7686
a0c12413
SC		 7687static void controller_lockup_detected(struct ctlr_info *h)
7688{
7689 unsigned long flags;
094963da 7690 u32 lockup_detected;
a0c12413 7691
a0c12413
SC		 7692 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7693 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7694 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7695 if (!lockup_detected) {
7696 /* no heartbeat, but controller gave us a zero. */
7697 dev_warn(&h->pdev->dev,
25163bd5
WS		 7698 "lockup detected after %d but scratchpad register is zero\n",
7699 h->heartbeat_sample_interval / HZ);
094963da
SC		 7700 lockup_detected = 0xffffffff;
7701 }
7702 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7703 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7704 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7705 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7706 pci_disable_device(h->pdev);
f2405db8 7707 fail_all_outstanding_cmds(h);
a0c12413
SC		 7708}
7709
25163bd5 7710static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7711{
7712 u64 now;
7713 u32 heartbeat;
7714 unsigned long flags;
7715
a0c12413
SC		 7716 now = get_jiffies_64();
7717 /* If we've received an interrupt recently, we're ok. */
7718 if (time_after64(h->last_intr_timestamp +
e85c5974 7719 (h->heartbeat_sample_interval), now))
25163bd5 7720 return false;
a0c12413
SC		 7721
7722 /*
7723 * If we've already checked the heartbeat recently, we're ok.
7724 * This could happen if someone sends us a signal. We
7725 * otherwise don't care about signals in this thread.
7726 */
7727 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7728 (h->heartbeat_sample_interval), now))
25163bd5 7729 return false;
a0c12413
SC		 7730
7731 /* If heartbeat has not changed since we last looked, we're not ok. */
7732 spin_lock_irqsave(&h->lock, flags);
7733 heartbeat = readl(&h->cfgtable->HeartBeat);
7734 spin_unlock_irqrestore(&h->lock, flags);
7735 if (h->last_heartbeat == heartbeat) {
7736 controller_lockup_detected(h);
25163bd5 7737 return true;
a0c12413
SC		 7738 }
7739
7740 /* We're ok. */
7741 h->last_heartbeat = heartbeat;
7742 h->last_heartbeat_timestamp = now;
25163bd5 7743 return false;
a0c12413
SC		 7744}
7745
9846590e 7746static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7747{
7748 int i;
7749 char *event_type;
7750
e4aa3e6a
SC		 7751 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7752 return;
7753
76438d08 7754 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7755 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7756 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7757 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7758 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7759
7760 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7761 event_type = "state change";
7762 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7763 event_type = "configuration change";
7764 /* Stop sending new RAID offload reqs via the IO accelerator */
7765 scsi_block_requests(h->scsi_host);
7766 for (i = 0; i < h->ndevices; i++)
7767 h->dev[i]->offload_enabled = 0;
23100dd9 7768 hpsa_drain_accel_commands(h);
76438d08
SC		 7769 /* Set 'accelerator path config change' bit */
7770 dev_warn(&h->pdev->dev,
7771 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7772 h->events, event_type);
7773 writel(h->events, &(h->cfgtable->clear_event_notify));
7774 /* Set the "clear event notify field update" bit 6 */
7775 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7776 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7777 hpsa_wait_for_clear_event_notify_ack(h);
7778 scsi_unblock_requests(h->scsi_host);
7779 } else {
7780 /* Acknowledge controller notification events. */
7781 writel(h->events, &(h->cfgtable->clear_event_notify));
7782 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7783 hpsa_wait_for_clear_event_notify_ack(h);
7784#if 0
7785 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7786 hpsa_wait_for_mode_change_ack(h);
7787#endif
7788 }
9846590e 7789 return;
76438d08
SC		 7790}
7791
7792/* Check a register on the controller to see if there are configuration
7793 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7794 * we should rescan the controller for devices.
7795 * Also check flag for driver-initiated rescan.
76438d08 7796 */
9846590e 7797static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7798{
7799 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7800 return 0;
76438d08
SC		 7801
7802 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7803 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7804}
76438d08 7805
9846590e
SC		 7806/*
7807 * Check if any of the offline devices have become ready
7808 */
7809static int hpsa_offline_devices_ready(struct ctlr_info *h)
7810{
7811 unsigned long flags;
7812 struct offline_device_entry *d;
7813 struct list_head *this, *tmp;
7814
7815 spin_lock_irqsave(&h->offline_device_lock, flags);
7816 list_for_each_safe(this, tmp, &h->offline_device_list) {
7817 d = list_entry(this, struct offline_device_entry,
7818 offline_list);
7819 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7820 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7821 spin_lock_irqsave(&h->offline_device_lock, flags);
7822 list_del(&d->offline_list);
7823 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7824 return 1;
d1fea47c 7825 }
9846590e
SC		 7826 spin_lock_irqsave(&h->offline_device_lock, flags);
7827 }
7828 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7829 return 0;
76438d08
SC		 7830}
7831
6636e7f4 7832static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7833{
7834 unsigned long flags;
8a98db73 7835 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7836 struct ctlr_info, rescan_ctlr_work);
7837
7838
7839 if (h->remove_in_progress)
8a98db73 7840 return;
9846590e
SC		 7841
7842 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7843 scsi_host_get(h->scsi_host);
9846590e
SC		 7844 hpsa_ack_ctlr_events(h);
7845 hpsa_scan_start(h->scsi_host);
7846 scsi_host_put(h->scsi_host);
7847 }
8a98db73 7848 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7849 if (!h->remove_in_progress)
7850 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7851 h->heartbeat_sample_interval);
7852 spin_unlock_irqrestore(&h->lock, flags);
7853}
7854
7855static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7856{
7857 unsigned long flags;
7858 struct ctlr_info *h = container_of(to_delayed_work(work),
7859 struct ctlr_info, monitor_ctlr_work);
7860
7861 detect_controller_lockup(h);
7862 if (lockup_detected(h))
a0c12413 7863 return;
6636e7f4
DB		 7864
7865 spin_lock_irqsave(&h->lock, flags);
7866 if (!h->remove_in_progress)
7867 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7868 h->heartbeat_sample_interval);
7869 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7870}
7871
6636e7f4
DB		 7872static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7873 char *name)
7874{
7875 struct workqueue_struct *wq = NULL;
6636e7f4 7876
397ea9cb 7877 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7878 if (!wq)
7879 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7880
7881 return wq;
7882}
7883
6f039790 7884static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7885{
4c2a8c40 7886 int dac, rc;
edd16368 7887 struct ctlr_info *h;
64670ac8
SC		 7888 int try_soft_reset = 0;
7889 unsigned long flags;
6b6c1cd7 7890 u32 board_id;
edd16368
SC		 7891
7892 if (number_of_controllers == 0)
7893 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7894
6b6c1cd7
TH		 7895 rc = hpsa_lookup_board_id(pdev, &board_id);
7896 if (rc < 0) {
7897 dev_warn(&pdev->dev, "Board ID not found\n");
7898 return rc;
7899 }
7900
7901 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7902 if (rc) {
7903 if (rc != -ENOTSUPP)
7904 return rc;
7905 /* If the reset fails in a particular way (it has no way to do
7906 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7907 * a soft reset once we get the controller configured up to the
7908 * point that it can accept a command.
7909 */
7910 try_soft_reset = 1;
7911 rc = 0;
7912 }
7913
7914reinit_after_soft_reset:
edd16368 7915
303932fd
DB		 7916 /* Command structures must be aligned on a 32-byte boundary because
7917 * the 5 lower bits of the address are used by the hardware. and by
7918 * the driver. See comments in hpsa.h for more info.
7919 */
303932fd 7920 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 7921 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 7922 if (!h) {
7923 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 7924 return -ENOMEM;
105a3dbc 7925 }
edd16368 7926
55c06c71 7927 h->pdev = pdev;
105a3dbc 7928
a9a3a273 7929 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7930 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7931 spin_lock_init(&h->lock);
9846590e 7932 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7933 spin_lock_init(&h->scan_lock);
34f0c627 7934 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7935 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 7936
7937 /* Allocate and clear per-cpu variable lockup_detected */
7938 h->lockup_detected = alloc_percpu(u32);
2a5ac326 7939 if (!h->lockup_detected) {
105a3dbc 7940 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 7941 rc = -ENOMEM;
2efa5929 7942 goto clean1; /* aer/h */
2a5ac326 7943 }
094963da
SC		 7944 set_lockup_detected_for_all_cpus(h, 0);
7945
55c06c71 7946 rc = hpsa_pci_init(h);
105a3dbc 7947 if (rc)
2946e82b
RE		 7948 goto clean2; /* lu, aer/h */
7949
7950 /* relies on h-> settings made by hpsa_pci_init, including
7951 * interrupt_mode h->intr */
7952 rc = hpsa_scsi_host_alloc(h);
7953 if (rc)
7954 goto clean2_5; /* pci, lu, aer/h */
edd16368 7955
2946e82b 7956 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 7957 h->ctlr = number_of_controllers;
7958 number_of_controllers++;
edd16368
SC		 7959
7960 /* configure PCI DMA stuff */
ecd9aad4
SC		 7961 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7962 if (rc == 0) {
edd16368 7963 dac = 1;
ecd9aad4
SC		 7964 } else {
7965 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7966 if (rc == 0) {
7967 dac = 0;
7968 } else {
7969 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 7970 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 7971 }
edd16368
SC		 7972 }
7973
7974 /* make sure the board interrupts are off */
7975 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7976
105a3dbc
RE		 7977 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
7978 if (rc)
2946e82b 7979 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 7980 rc = hpsa_alloc_cmd_pool(h);
8947fd10 7981 if (rc)
2946e82b 7982 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 7983 rc = hpsa_alloc_sg_chain_blocks(h);
7984 if (rc)
2946e82b 7985 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 7986 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7987 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 7988 init_waitqueue_head(&h->event_sync_wait_queue);
7989 mutex_init(&h->reset_mutex);
a08a8471 7990 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7991
7992 pci_set_drvdata(pdev, h);
9a41338e 7993 h->ndevices = 0;
316b221a 7994 h->hba_mode_enabled = 0;
2946e82b 7995
9a41338e 7996 spin_lock_init(&h->devlock);
105a3dbc
RE		 7997 rc = hpsa_put_ctlr_into_performant_mode(h);
7998 if (rc)
2946e82b
RE		 7999 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8000
8001 /* hook into SCSI subsystem */
8002 rc = hpsa_scsi_add_host(h);
8003 if (rc)
8004 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8005
8006 /* create the resubmit workqueue */
8007 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8008 if (!h->rescan_ctlr_wq) {
8009 rc = -ENOMEM;
8010 goto clean7;
8011 }
8012
8013 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8014 if (!h->resubmit_wq) {
8015 rc = -ENOMEM;
8016 goto clean7; /* aer/h */
8017 }
64670ac8 8018
105a3dbc
RE		 8019 /*
8020 * At this point, the controller is ready to take commands.
64670ac8
SC		 8021 * Now, if reset_devices and the hard reset didn't work, try
8022 * the soft reset and see if that works.
8023 */
8024 if (try_soft_reset) {
8025
8026 /* This is kind of gross. We may or may not get a completion
8027 * from the soft reset command, and if we do, then the value
8028 * from the fifo may or may not be valid. So, we wait 10 secs
8029 * after the reset throwing away any completions we get during
8030 * that time. Unregister the interrupt handler and register
8031 * fake ones to scoop up any residual completions.
8032 */
8033 spin_lock_irqsave(&h->lock, flags);
8034 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8035 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8036 hpsa_free_irqs(h);
9ee61794 8037 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8038 hpsa_intx_discard_completions);
8039 if (rc) {
9ee61794
RE		 8040 dev_warn(&h->pdev->dev,
8041 "Failed to request_irq after soft reset.\n");
d498757c 8042 /*
b2ef480c
RE		 8043 * cannot goto clean7 or free_irqs will be called
8044 * again. Instead, do its work
8045 */
8046 hpsa_free_performant_mode(h); /* clean7 */
8047 hpsa_free_sg_chain_blocks(h); /* clean6 */
8048 hpsa_free_cmd_pool(h); /* clean5 */
8049 /*
8050 * skip hpsa_free_irqs(h) clean4 since that
8051 * was just called before request_irqs failed
d498757c
RE		 8052 */
8053 goto clean3;
64670ac8
SC		 8054 }
8055
8056 rc = hpsa_kdump_soft_reset(h);
8057 if (rc)
8058 /* Neither hard nor soft reset worked, we're hosed. */
2946e82b 8059 goto clean9;
64670ac8
SC		 8060
8061 dev_info(&h->pdev->dev, "Board READY.\n");
8062 dev_info(&h->pdev->dev,
8063 "Waiting for stale completions to drain.\n");
8064 h->access.set_intr_mask(h, HPSA_INTR_ON);
8065 msleep(10000);
8066 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8067
8068 rc = controller_reset_failed(h->cfgtable);
8069 if (rc)
8070 dev_info(&h->pdev->dev,
8071 "Soft reset appears to have failed.\n");
8072
8073 /* since the controller's reset, we have to go back and re-init
8074 * everything. Easiest to just forget what we've done and do it
8075 * all over again.
8076 */
8077 hpsa_undo_allocations_after_kdump_soft_reset(h);
8078 try_soft_reset = 0;
8079 if (rc)
b2ef480c 8080 /* don't goto clean, we already unallocated */
64670ac8
SC		 8081 return -ENODEV;
8082
8083 goto reinit_after_soft_reset;
8084 }
edd16368 8085
105a3dbc
RE		 8086 /* Enable Accelerated IO path at driver layer */
8087 h->acciopath_status = 1;
da0697bd 8088
e863d68e 8089
edd16368
SC		 8090 /* Turn the interrupts on so we can service requests */
8091 h->access.set_intr_mask(h, HPSA_INTR_ON);
8092
339b2b14 8093 hpsa_hba_inquiry(h);
8a98db73
SC		 8094
8095 /* Monitor the controller for firmware lockups */
8096 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8097 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8098 schedule_delayed_work(&h->monitor_ctlr_work,
8099 h->heartbeat_sample_interval);
6636e7f4
DB		 8100 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8101 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8102 h->heartbeat_sample_interval);
88bf6d62 8103 return 0;
edd16368 8104
2946e82b 8105clean9: /* wq, sh, perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc 8106 kfree(h->hba_inquiry_data);
2946e82b 8107clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8108 hpsa_free_performant_mode(h);
8109 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8110clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8111 hpsa_free_sg_chain_blocks(h);
2946e82b 8112clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8113 hpsa_free_cmd_pool(h);
2946e82b 8114clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8115 hpsa_free_irqs(h);
2946e82b
RE		 8116clean3: /* shost, pci, lu, aer/h */
8117 scsi_host_put(h->scsi_host);
8118 h->scsi_host = NULL;
8119clean2_5: /* pci, lu, aer/h */
195f2c65 8120 hpsa_free_pci_init(h);
2946e82b 8121clean2: /* lu, aer/h */
105a3dbc
RE		 8122 if (h->lockup_detected) {
8123 free_percpu(h->lockup_detected);
8124 h->lockup_detected = NULL;
8125 }
8126clean1: /* wq/aer/h */
8127 if (h->resubmit_wq) {
080ef1cc 8128 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8129 h->resubmit_wq = NULL;
8130 }
8131 if (h->rescan_ctlr_wq) {
6636e7f4 8132 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8133 h->rescan_ctlr_wq = NULL;
8134 }
edd16368 8135 kfree(h);
ecd9aad4 8136 return rc;
edd16368
SC		 8137}
8138
8139static void hpsa_flush_cache(struct ctlr_info *h)
8140{
8141 char *flush_buf;
8142 struct CommandList *c;
25163bd5 8143 int rc;
702890e3 8144
094963da 8145 if (unlikely(lockup_detected(h)))
702890e3 8146 return;
edd16368
SC		 8147 flush_buf = kzalloc(4, GFP_KERNEL);
8148 if (!flush_buf)
8149 return;
8150
45fcb86e 8151 c = cmd_alloc(h);
bf43caf3 8152
a2dac136
SC		 8153 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8154 RAID_CTLR_LUNID, TYPE_CMD)) {
8155 goto out;
8156 }
25163bd5
WS		 8157 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8158 PCI_DMA_TODEVICE, NO_TIMEOUT);
8159 if (rc)
8160 goto out;
edd16368 8161 if (c->err_info->CommandStatus != 0)
a2dac136 8162out:
edd16368
SC		 8163 dev_warn(&h->pdev->dev,
8164 "error flushing cache on controller\n");
45fcb86e 8165 cmd_free(h, c);
edd16368
SC		 8166 kfree(flush_buf);
8167}
8168
8169static void hpsa_shutdown(struct pci_dev *pdev)
8170{
8171 struct ctlr_info *h;
8172
8173 h = pci_get_drvdata(pdev);
8174 /* Turn board interrupts off and send the flush cache command
8175 * sendcmd will turn off interrupt, and send the flush...
8176 * To write all data in the battery backed cache to disks
8177 */
8178 hpsa_flush_cache(h);
8179 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8180 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8181 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8182}
8183
6f039790 8184static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8185{
8186 int i;
8187
105a3dbc 8188 for (i = 0; i < h->ndevices; i++) {
55e14e76 8189 kfree(h->dev[i]);
105a3dbc
RE		 8190 h->dev[i] = NULL;
8191 }
55e14e76
SC		 8192}
8193
6f039790 8194static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8195{
8196 struct ctlr_info *h;
8a98db73 8197 unsigned long flags;
edd16368
SC		 8198
8199 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8200 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8201 return;
8202 }
8203 h = pci_get_drvdata(pdev);
8a98db73
SC		 8204
8205 /* Get rid of any controller monitoring work items */
8206 spin_lock_irqsave(&h->lock, flags);
8207 h->remove_in_progress = 1;
8a98db73 8208 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8209 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8210 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8211 destroy_workqueue(h->rescan_ctlr_wq);
8212 destroy_workqueue(h->resubmit_wq);
cc64c817 8213
105a3dbc 8214 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8215 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8216 hpsa_shutdown(pdev);
cc64c817 8217
105a3dbc
RE		 8218 hpsa_free_device_info(h); /* scan */
8219
2946e82b
RE		 8220 kfree(h->hba_inquiry_data); /* init_one 10 */
8221 h->hba_inquiry_data = NULL; /* init_one 10 */
8222 if (h->scsi_host)
8223 scsi_remove_host(h->scsi_host); /* init_one 8 */
8224 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8225 hpsa_free_performant_mode(h); /* init_one 7 */
8226 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8227 hpsa_free_cmd_pool(h); /* init_one 5 */
8228
8229 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8230
2946e82b
RE		 8231 scsi_host_put(h->scsi_host); /* init_one 3 */
8232 h->scsi_host = NULL; /* init_one 3 */
8233
195f2c65 8234 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8235 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8236
105a3dbc
RE		 8237 free_percpu(h->lockup_detected); /* init_one 2 */
8238 h->lockup_detected = NULL; /* init_one 2 */
8239 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8240 kfree(h); /* init_one 1 */
edd16368
SC		 8241}
8242
8243static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8244 __attribute__((unused)) pm_message_t state)
8245{
8246 return -ENOSYS;
8247}
8248
8249static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8250{
8251 return -ENOSYS;
8252}
8253
8254static struct pci_driver hpsa_pci_driver = {
f79cfec6 8255 .name = HPSA,
edd16368 8256 .probe = hpsa_init_one,
6f039790 8257 .remove = hpsa_remove_one,
edd16368
SC		 8258 .id_table = hpsa_pci_device_id, /* id_table */
8259 .shutdown = hpsa_shutdown,
8260 .suspend = hpsa_suspend,
8261 .resume = hpsa_resume,
8262};
8263
303932fd
DB		 8264/* Fill in bucket_map[], given nsgs (the max number of
8265 * scatter gather elements supported) and bucket[],
8266 * which is an array of 8 integers. The bucket[] array
8267 * contains 8 different DMA transfer sizes (in 16
8268 * byte increments) which the controller uses to fetch
8269 * commands. This function fills in bucket_map[], which
8270 * maps a given number of scatter gather elements to one of
8271 * the 8 DMA transfer sizes. The point of it is to allow the
8272 * controller to only do as much DMA as needed to fetch the
8273 * command, with the DMA transfer size encoded in the lower
8274 * bits of the command address.
8275 */
8276static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8277 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8278{
8279 int i, j, b, size;
8280
303932fd
DB		 8281 /* Note, bucket_map must have nsgs+1 entries. */
8282 for (i = 0; i <= nsgs; i++) {
8283 /* Compute size of a command with i SG entries */
e1f7de0c 8284 size = i + min_blocks;
303932fd
DB		 8285 b = num_buckets; /* Assume the biggest bucket */
8286 /* Find the bucket that is just big enough */
e1f7de0c 8287 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8288 if (bucket[j] >= size) {
8289 b = j;
8290 break;
8291 }
8292 }
8293 /* for a command with i SG entries, use bucket b. */
8294 bucket_map[i] = b;
8295 }
8296}
8297
105a3dbc
RE		 8298/*
8299 * return -ENODEV on err, 0 on success (or no action)
8300 * allocates numerous items that must be freed later
8301 */
c706a795 8302static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8303{
6c311b57
SC		 8304 int i;
8305 unsigned long register_value;
e1f7de0c
MG		 8306 unsigned long transMethod = CFGTBL_Trans_Performant |
8307 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8308 CFGTBL_Trans_enable_directed_msix |
8309 (trans_support & (CFGTBL_Trans_io_accel1 |
8310 CFGTBL_Trans_io_accel2));
e1f7de0c 8311 struct access_method access = SA5_performant_access;
def342bd
SC		 8312
8313 /* This is a bit complicated. There are 8 registers on
8314 * the controller which we write to to tell it 8 different
8315 * sizes of commands which there may be. It's a way of
8316 * reducing the DMA done to fetch each command. Encoded into
8317 * each command's tag are 3 bits which communicate to the controller
8318 * which of the eight sizes that command fits within. The size of
8319 * each command depends on how many scatter gather entries there are.
8320 * Each SG entry requires 16 bytes. The eight registers are programmed
8321 * with the number of 16-byte blocks a command of that size requires.
8322 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8323 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8324 * blocks. Note, this only extends to the SG entries contained
8325 * within the command block, and does not extend to chained blocks
8326 * of SG elements. bft[] contains the eight values we write to
8327 * the registers. They are not evenly distributed, but have more
8328 * sizes for small commands, and fewer sizes for larger commands.
8329 */
d66ae08b 8330 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8331#define MIN_IOACCEL2_BFT_ENTRY 5
8332#define HPSA_IOACCEL2_HEADER_SZ 4
8333 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8334 13, 14, 15, 16, 17, 18, 19,
8335 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8336 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8337 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8338 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8339 16 * MIN_IOACCEL2_BFT_ENTRY);
8340 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8341 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8342 /* 5 = 1 s/g entry or 4k
8343 * 6 = 2 s/g entry or 8k
8344 * 8 = 4 s/g entry or 16k
8345 * 10 = 6 s/g entry or 24k
8346 */
303932fd 8347
b3a52e79
SC		 8348 /* If the controller supports either ioaccel method then
8349 * we can also use the RAID stack submit path that does not
8350 * perform the superfluous readl() after each command submission.
8351 */
8352 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8353 access = SA5_performant_access_no_read;
8354
303932fd 8355 /* Controller spec: zero out this buffer. */
072b0518
SC		 8356 for (i = 0; i < h->nreply_queues; i++)
8357 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8358
d66ae08b
SC		 8359 bft[7] = SG_ENTRIES_IN_CMD + 4;
8360 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8361 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8362 for (i = 0; i < 8; i++)
8363 writel(bft[i], &h->transtable->BlockFetch[i]);
8364
8365 /* size of controller ring buffer */
8366 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8367 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8368 writel(0, &h->transtable->RepQCtrAddrLow32);
8369 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8370
8371 for (i = 0; i < h->nreply_queues; i++) {
8372 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8373 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8374 &h->transtable->RepQAddr[i].lower);
8375 }
8376
b9af4937 8377 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8378 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8379 /*
8380 * enable outbound interrupt coalescing in accelerator mode;
8381 */
8382 if (trans_support & CFGTBL_Trans_io_accel1) {
8383 access = SA5_ioaccel_mode1_access;
8384 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8385 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8386 } else {
8387 if (trans_support & CFGTBL_Trans_io_accel2) {
8388 access = SA5_ioaccel_mode2_access;
8389 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8390 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8391 }
e1f7de0c 8392 }
303932fd 8393 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8394 if (hpsa_wait_for_mode_change_ack(h)) {
8395 dev_err(&h->pdev->dev,
8396 "performant mode problem - doorbell timeout\n");
8397 return -ENODEV;
8398 }
303932fd
DB		 8399 register_value = readl(&(h->cfgtable->TransportActive));
8400 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8401 dev_err(&h->pdev->dev,
8402 "performant mode problem - transport not active\n");
c706a795 8403 return -ENODEV;
303932fd 8404 }
960a30e7 8405 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8406 h->access = access;
8407 h->transMethod = transMethod;
8408
b9af4937
SC		 8409 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8410 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8411 return 0;
e1f7de0c 8412
b9af4937
SC		 8413 if (trans_support & CFGTBL_Trans_io_accel1) {
8414 /* Set up I/O accelerator mode */
8415 for (i = 0; i < h->nreply_queues; i++) {
8416 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8417 h->reply_queue[i].current_entry =
8418 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8419 }
8420 bft[7] = h->ioaccel_maxsg + 8;
8421 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8422 h->ioaccel1_blockFetchTable);
e1f7de0c 8423
b9af4937 8424 /* initialize all reply queue entries to unused */
072b0518
SC		 8425 for (i = 0; i < h->nreply_queues; i++)
8426 memset(h->reply_queue[i].head,
8427 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8428 h->reply_queue_size);
e1f7de0c 8429
b9af4937
SC		 8430 /* set all the constant fields in the accelerator command
8431 * frames once at init time to save CPU cycles later.
8432 */
8433 for (i = 0; i < h->nr_cmds; i++) {
8434 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8435
8436 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8437 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8438 (i * sizeof(struct ErrorInfo)));
8439 cp->err_info_len = sizeof(struct ErrorInfo);
8440 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8441 cp->host_context_flags =
8442 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8443 cp->timeout_sec = 0;
8444 cp->ReplyQueue = 0;
50a0decf 8445 cp->tag =
f2405db8 8446 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8447 cp->host_addr =
8448 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8449 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8450 }
8451 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8452 u64 cfg_offset, cfg_base_addr_index;
8453 u32 bft2_offset, cfg_base_addr;
8454 int rc;
8455
8456 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8457 &cfg_base_addr_index, &cfg_offset);
8458 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8459 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8460 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8461 4, h->ioaccel2_blockFetchTable);
8462 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8463 BUILD_BUG_ON(offsetof(struct CfgTable,
8464 io_accel_request_size_offset) != 0xb8);
8465 h->ioaccel2_bft2_regs =
8466 remap_pci_mem(pci_resource_start(h->pdev,
8467 cfg_base_addr_index) +
8468 cfg_offset + bft2_offset,
8469 ARRAY_SIZE(bft2) *
8470 sizeof(*h->ioaccel2_bft2_regs));
8471 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8472 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8473 }
b9af4937 8474 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8475 if (hpsa_wait_for_mode_change_ack(h)) {
8476 dev_err(&h->pdev->dev,
8477 "performant mode problem - enabling ioaccel mode\n");
8478 return -ENODEV;
8479 }
8480 return 0;
e1f7de0c
MG		 8481}
8482
1fb7c98a
RE		 8483/* Free ioaccel1 mode command blocks and block fetch table */
8484static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8485{
105a3dbc 8486 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8487 pci_free_consistent(h->pdev,
8488 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8489 h->ioaccel_cmd_pool,
8490 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8491 h->ioaccel_cmd_pool = NULL;
8492 h->ioaccel_cmd_pool_dhandle = 0;
8493 }
1fb7c98a 8494 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8495 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8496}
8497
d37ffbe4
RE		 8498/* Allocate ioaccel1 mode command blocks and block fetch table */
8499static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8500{
283b4a9b
SC		 8501 h->ioaccel_maxsg =
8502 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8503 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8504 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8505
e1f7de0c
MG		 8506 /* Command structures must be aligned on a 128-byte boundary
8507 * because the 7 lower bits of the address are used by the
8508 * hardware.
8509 */
e1f7de0c
MG		 8510 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8511 IOACCEL1_COMMANDLIST_ALIGNMENT);
8512 h->ioaccel_cmd_pool =
8513 pci_alloc_consistent(h->pdev,
8514 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8515 &(h->ioaccel_cmd_pool_dhandle));
8516
8517 h->ioaccel1_blockFetchTable =
283b4a9b 8518 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8519 sizeof(u32)), GFP_KERNEL);
8520
8521 if ((h->ioaccel_cmd_pool == NULL) ||
8522 (h->ioaccel1_blockFetchTable == NULL))
8523 goto clean_up;
8524
8525 memset(h->ioaccel_cmd_pool, 0,
8526 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8527 return 0;
8528
8529clean_up:
1fb7c98a 8530 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8531 return -ENOMEM;
6c311b57
SC		 8532}
8533
1fb7c98a
RE		 8534/* Free ioaccel2 mode command blocks and block fetch table */
8535static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8536{
d9a729f3
WS		 8537 hpsa_free_ioaccel2_sg_chain_blocks(h);
8538
105a3dbc 8539 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8540 pci_free_consistent(h->pdev,
8541 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8542 h->ioaccel2_cmd_pool,
8543 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8544 h->ioaccel2_cmd_pool = NULL;
8545 h->ioaccel2_cmd_pool_dhandle = 0;
8546 }
1fb7c98a 8547 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8548 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8549}
8550
d37ffbe4
RE		 8551/* Allocate ioaccel2 mode command blocks and block fetch table */
8552static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8553{
d9a729f3
WS		 8554 int rc;
8555
aca9012a
SC		 8556 /* Allocate ioaccel2 mode command blocks and block fetch table */
8557
8558 h->ioaccel_maxsg =
8559 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8560 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8561 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8562
aca9012a
SC		 8563 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8564 IOACCEL2_COMMANDLIST_ALIGNMENT);
8565 h->ioaccel2_cmd_pool =
8566 pci_alloc_consistent(h->pdev,
8567 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8568 &(h->ioaccel2_cmd_pool_dhandle));
8569
8570 h->ioaccel2_blockFetchTable =
8571 kmalloc(((h->ioaccel_maxsg + 1) *
8572 sizeof(u32)), GFP_KERNEL);
8573
8574 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8575 (h->ioaccel2_blockFetchTable == NULL)) {
8576 rc = -ENOMEM;
8577 goto clean_up;
8578 }
8579
8580 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8581 if (rc)
aca9012a
SC		 8582 goto clean_up;
8583
8584 memset(h->ioaccel2_cmd_pool, 0,
8585 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8586 return 0;
8587
8588clean_up:
1fb7c98a 8589 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8590 return rc;
aca9012a
SC		 8591}
8592
105a3dbc
RE		 8593/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8594static void hpsa_free_performant_mode(struct ctlr_info *h)
8595{
8596 kfree(h->blockFetchTable);
8597 h->blockFetchTable = NULL;
8598 hpsa_free_reply_queues(h);
8599 hpsa_free_ioaccel1_cmd_and_bft(h);
8600 hpsa_free_ioaccel2_cmd_and_bft(h);
8601}
8602
8603/* return -ENODEV on error, 0 on success (or no action)
8604 * allocates numerous items that must be freed later
8605 */
8606static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8607{
8608 u32 trans_support;
e1f7de0c
MG		 8609 unsigned long transMethod = CFGTBL_Trans_Performant |
8610 CFGTBL_Trans_use_short_tags;
105a3dbc 8611 int i, rc;
6c311b57 8612
02ec19c8 8613 if (hpsa_simple_mode)
105a3dbc 8614 return 0;
02ec19c8 8615
67c99a72 8616 trans_support = readl(&(h->cfgtable->TransportSupport));
8617 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8618 return 0;
67c99a72 8619
e1f7de0c
MG		 8620 /* Check for I/O accelerator mode support */
8621 if (trans_support & CFGTBL_Trans_io_accel1) {
8622 transMethod |= CFGTBL_Trans_io_accel1 |
8623 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8624 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8625 if (rc)
8626 return rc;
8627 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8628 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8629 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8630 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8631 if (rc)
8632 return rc;
e1f7de0c
MG		 8633 }
8634
eee0f03a 8635 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8636 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8637 /* Performant mode ring buffer and supporting data structures */
072b0518 8638 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8639
254f796b 8640 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8641 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8642 h->reply_queue_size,
8643 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8644 if (!h->reply_queue[i].head) {
8645 rc = -ENOMEM;
8646 goto clean1; /* rq, ioaccel */
8647 }
254f796b
MG		 8648 h->reply_queue[i].size = h->max_commands;
8649 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8650 h->reply_queue[i].current_entry = 0;
8651 }
8652
6c311b57 8653 /* Need a block fetch table for performant mode */
d66ae08b 8654 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8655 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8656 if (!h->blockFetchTable) {
8657 rc = -ENOMEM;
8658 goto clean1; /* rq, ioaccel */
8659 }
6c311b57 8660
105a3dbc
RE		 8661 rc = hpsa_enter_performant_mode(h, trans_support);
8662 if (rc)
8663 goto clean2; /* bft, rq, ioaccel */
8664 return 0;
303932fd 8665
105a3dbc 8666clean2: /* bft, rq, ioaccel */
303932fd 8667 kfree(h->blockFetchTable);
105a3dbc
RE		 8668 h->blockFetchTable = NULL;
8669clean1: /* rq, ioaccel */
8670 hpsa_free_reply_queues(h);
8671 hpsa_free_ioaccel1_cmd_and_bft(h);
8672 hpsa_free_ioaccel2_cmd_and_bft(h);
8673 return rc;
303932fd
DB		 8674}
8675
23100dd9 8676static int is_accelerated_cmd(struct CommandList *c)
76438d08 8677{
23100dd9
SC		 8678 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8679}
8680
8681static void hpsa_drain_accel_commands(struct ctlr_info *h)
8682{
8683 struct CommandList *c = NULL;
f2405db8 8684 int i, accel_cmds_out;
281a7fd0 8685 int refcount;
76438d08 8686
f2405db8 8687 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8688 accel_cmds_out = 0;
f2405db8 8689 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8690 c = h->cmd_pool + i;
281a7fd0
WS		 8691 refcount = atomic_inc_return(&c->refcount);
8692 if (refcount > 1) /* Command is allocated */
8693 accel_cmds_out += is_accelerated_cmd(c);
8694 cmd_free(h, c);
f2405db8 8695 }
23100dd9 8696 if (accel_cmds_out <= 0)
281a7fd0 8697 break;
76438d08
SC		 8698 msleep(100);
8699 } while (1);
8700}
8701
edd16368
SC		 8702/*
8703 * This is it. Register the PCI driver information for the cards we control
8704 * the OS will call our registered routines when it finds one of our cards.
8705 */
8706static int __init hpsa_init(void)
8707{
31468401 8708 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8709}
8710
8711static void __exit hpsa_cleanup(void)
8712{
8713 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8714}
8715
e1f7de0c
MG		 8716static void __attribute__((unused)) verify_offsets(void)
8717{
dd0e19f3
ST		 8718#define VERIFY_OFFSET(member, offset) \
8719 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8720
8721 VERIFY_OFFSET(structure_size, 0);
8722 VERIFY_OFFSET(volume_blk_size, 4);
8723 VERIFY_OFFSET(volume_blk_cnt, 8);
8724 VERIFY_OFFSET(phys_blk_shift, 16);
8725 VERIFY_OFFSET(parity_rotation_shift, 17);
8726 VERIFY_OFFSET(strip_size, 18);
8727 VERIFY_OFFSET(disk_starting_blk, 20);
8728 VERIFY_OFFSET(disk_blk_cnt, 28);
8729 VERIFY_OFFSET(data_disks_per_row, 36);
8730 VERIFY_OFFSET(metadata_disks_per_row, 38);
8731 VERIFY_OFFSET(row_cnt, 40);
8732 VERIFY_OFFSET(layout_map_count, 42);
8733 VERIFY_OFFSET(flags, 44);
8734 VERIFY_OFFSET(dekindex, 46);
8735 /* VERIFY_OFFSET(reserved, 48 */
8736 VERIFY_OFFSET(data, 64);
8737
8738#undef VERIFY_OFFSET
8739
b66cc250
MM		 8740#define VERIFY_OFFSET(member, offset) \
8741 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8742
8743 VERIFY_OFFSET(IU_type, 0);
8744 VERIFY_OFFSET(direction, 1);
8745 VERIFY_OFFSET(reply_queue, 2);
8746 /* VERIFY_OFFSET(reserved1, 3); */
8747 VERIFY_OFFSET(scsi_nexus, 4);
8748 VERIFY_OFFSET(Tag, 8);
8749 VERIFY_OFFSET(cdb, 16);
8750 VERIFY_OFFSET(cciss_lun, 32);
8751 VERIFY_OFFSET(data_len, 40);
8752 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8753 VERIFY_OFFSET(sg_count, 45);
8754 /* VERIFY_OFFSET(reserved3 */
8755 VERIFY_OFFSET(err_ptr, 48);
8756 VERIFY_OFFSET(err_len, 56);
8757 /* VERIFY_OFFSET(reserved4 */
8758 VERIFY_OFFSET(sg, 64);
8759
8760#undef VERIFY_OFFSET
8761
e1f7de0c
MG		 8762#define VERIFY_OFFSET(member, offset) \
8763 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8764
8765 VERIFY_OFFSET(dev_handle, 0x00);
8766 VERIFY_OFFSET(reserved1, 0x02);
8767 VERIFY_OFFSET(function, 0x03);
8768 VERIFY_OFFSET(reserved2, 0x04);
8769 VERIFY_OFFSET(err_info, 0x0C);
8770 VERIFY_OFFSET(reserved3, 0x10);
8771 VERIFY_OFFSET(err_info_len, 0x12);
8772 VERIFY_OFFSET(reserved4, 0x13);
8773 VERIFY_OFFSET(sgl_offset, 0x14);
8774 VERIFY_OFFSET(reserved5, 0x15);
8775 VERIFY_OFFSET(transfer_len, 0x1C);
8776 VERIFY_OFFSET(reserved6, 0x20);
8777 VERIFY_OFFSET(io_flags, 0x24);
8778 VERIFY_OFFSET(reserved7, 0x26);
8779 VERIFY_OFFSET(LUN, 0x34);
8780 VERIFY_OFFSET(control, 0x3C);
8781 VERIFY_OFFSET(CDB, 0x40);
8782 VERIFY_OFFSET(reserved8, 0x50);
8783 VERIFY_OFFSET(host_context_flags, 0x60);
8784 VERIFY_OFFSET(timeout_sec, 0x62);
8785 VERIFY_OFFSET(ReplyQueue, 0x64);
8786 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8787 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8788 VERIFY_OFFSET(host_addr, 0x70);
8789 VERIFY_OFFSET(CISS_LUN, 0x78);
8790 VERIFY_OFFSET(SG, 0x78 + 8);
8791#undef VERIFY_OFFSET
8792}
8793
edd16368
SC		 8794module_init(hpsa_init);
8795module_exit(hpsa_cleanup);
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