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[SCSI] hpsa: bring format-in-progress drives online when ready
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
283b4a9b 51#include <asm/div64.h>
edd16368
SC		 52#include "hpsa_cmd.h"
53#include "hpsa.h"
54
55/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 56#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 57#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 58#define HPSA "hpsa"
edd16368
SC		 59
60/* How long to wait (in milliseconds) for board to go into simple mode */
61#define MAX_CONFIG_WAIT 30000
62#define MAX_IOCTL_CONFIG_WAIT 1000
63
64/*define how many times we will try a command because of bus resets */
65#define MAX_CMD_RETRIES 3
66
67/* Embedded module documentation macros - see modules.h */
68MODULE_AUTHOR("Hewlett-Packard Company");
69MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
70 HPSA_DRIVER_VERSION);
71MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
72MODULE_VERSION(HPSA_DRIVER_VERSION);
73MODULE_LICENSE("GPL");
74
75static int hpsa_allow_any;
76module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(hpsa_allow_any,
78 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 79static int hpsa_simple_mode;
80module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(hpsa_simple_mode,
82 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 83
84/* define the PCI info for the cards we can control */
85static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 86 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
8e616a5e
SC		 121 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
122 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
123 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
124 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
125 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 126 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 127 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 128 {0,}
129};
130
131MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
132
133/* board_id = Subsystem Device ID & Vendor ID
134 * product = Marketing Name for the board
135 * access = Address of the struct of function pointers
136 */
137static struct board_type products[] = {
edd16368
SC		 138 {0x3241103C, "Smart Array P212", &SA5_access},
139 {0x3243103C, "Smart Array P410", &SA5_access},
140 {0x3245103C, "Smart Array P410i", &SA5_access},
141 {0x3247103C, "Smart Array P411", &SA5_access},
142 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 143 {0x324A103C, "Smart Array P712m", &SA5_access},
144 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 145 {0x3350103C, "Smart Array P222", &SA5_access},
146 {0x3351103C, "Smart Array P420", &SA5_access},
147 {0x3352103C, "Smart Array P421", &SA5_access},
148 {0x3353103C, "Smart Array P822", &SA5_access},
149 {0x3354103C, "Smart Array P420i", &SA5_access},
150 {0x3355103C, "Smart Array P220i", &SA5_access},
151 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 152 {0x1921103C, "Smart Array P830i", &SA5_access},
153 {0x1922103C, "Smart Array P430", &SA5_access},
154 {0x1923103C, "Smart Array P431", &SA5_access},
155 {0x1924103C, "Smart Array P830", &SA5_access},
156 {0x1926103C, "Smart Array P731m", &SA5_access},
157 {0x1928103C, "Smart Array P230i", &SA5_access},
158 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 159 {0x21BD103C, "Smart Array", &SA5_access},
160 {0x21BE103C, "Smart Array", &SA5_access},
161 {0x21BF103C, "Smart Array", &SA5_access},
162 {0x21C0103C, "Smart Array", &SA5_access},
163 {0x21C1103C, "Smart Array", &SA5_access},
164 {0x21C2103C, "Smart Array", &SA5_access},
165 {0x21C3103C, "Smart Array", &SA5_access},
166 {0x21C4103C, "Smart Array", &SA5_access},
167 {0x21C5103C, "Smart Array", &SA5_access},
168 {0x21C7103C, "Smart Array", &SA5_access},
169 {0x21C8103C, "Smart Array", &SA5_access},
170 {0x21C9103C, "Smart Array", &SA5_access},
8e616a5e
SC		 171 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
172 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
173 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
174 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
175 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 176 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
177};
178
179static int number_of_controllers;
180
10f66018
SC		 181static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
182static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 183static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
184static void start_io(struct ctlr_info *h);
185
186#ifdef CONFIG_COMPAT
187static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
188#endif
189
190static void cmd_free(struct ctlr_info *h, struct CommandList *c);
191static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
192static struct CommandList *cmd_alloc(struct ctlr_info *h);
193static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 194static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 195 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 196 int cmd_type);
b7bb24eb 197#define VPD_PAGE (1 << 8)
edd16368 198
f281233d 199static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 200static void hpsa_scan_start(struct Scsi_Host *);
201static int hpsa_scan_finished(struct Scsi_Host *sh,
202 unsigned long elapsed_time);
667e23d4
SC		 203static int hpsa_change_queue_depth(struct scsi_device *sdev,
204 int qdepth, int reason);
edd16368
SC		 205
206static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 207static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 208static int hpsa_slave_alloc(struct scsi_device *sdev);
209static void hpsa_slave_destroy(struct scsi_device *sdev);
210
edd16368 211static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 212static int check_for_unit_attention(struct ctlr_info *h,
213 struct CommandList *c);
214static void check_ioctl_unit_attention(struct ctlr_info *h,
215 struct CommandList *c);
303932fd
DB		 216/* performant mode helper functions */
217static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 218 int nsgs, int min_blocks, int *bucket_map);
6f039790 219static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 220static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 221static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
222 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
223 u64 *cfg_offset);
224static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
225 unsigned long *memory_bar);
226static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
227static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
228 int wait_for_ready);
75167d2c 229static inline void finish_cmd(struct CommandList *c);
283b4a9b 230static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 231#define BOARD_NOT_READY 0
232#define BOARD_READY 1
23100dd9 233static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 234static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 235static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
236 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
237 u8 *scsi3addr);
edd16368 238
edd16368
SC		 239static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
240{
241 unsigned long *priv = shost_priv(sdev->host);
242 return (struct ctlr_info *) *priv;
243}
244
a23513e8
SC		 245static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
246{
247 unsigned long *priv = shost_priv(sh);
248 return (struct ctlr_info *) *priv;
249}
250
edd16368
SC		 251static int check_for_unit_attention(struct ctlr_info *h,
252 struct CommandList *c)
253{
254 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
255 return 0;
256
257 switch (c->err_info->SenseInfo[12]) {
258 case STATE_CHANGED:
f79cfec6 259 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 260 "detected, command retried\n", h->ctlr);
261 break;
262 case LUN_FAILED:
f79cfec6 263 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 264 "detected, action required\n", h->ctlr);
265 break;
266 case REPORT_LUNS_CHANGED:
f79cfec6 267 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 268 "changed, action required\n", h->ctlr);
edd16368 269 /*
4f4eb9f1
ST		 270 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
271 * target (array) devices.
edd16368
SC		 272 */
273 break;
274 case POWER_OR_RESET:
f79cfec6 275 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 276 "or device reset detected\n", h->ctlr);
277 break;
278 case UNIT_ATTENTION_CLEARED:
f79cfec6 279 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 280 "cleared by another initiator\n", h->ctlr);
281 break;
282 default:
f79cfec6 283 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 284 "unit attention detected\n", h->ctlr);
285 break;
286 }
287 return 1;
288}
289
852af20a
MB		 290static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
291{
292 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
293 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
294 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
295 return 0;
296 dev_warn(&h->pdev->dev, HPSA "device busy");
297 return 1;
298}
299
da0697bd
ST		 300static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
301 struct device_attribute *attr,
302 const char *buf, size_t count)
303{
304 int status, len;
305 struct ctlr_info *h;
306 struct Scsi_Host *shost = class_to_shost(dev);
307 char tmpbuf[10];
308
309 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
310 return -EACCES;
311 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
312 strncpy(tmpbuf, buf, len);
313 tmpbuf[len] = '\0';
314 if (sscanf(tmpbuf, "%d", &status) != 1)
315 return -EINVAL;
316 h = shost_to_hba(shost);
317 h->acciopath_status = !!status;
318 dev_warn(&h->pdev->dev,
319 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
320 h->acciopath_status ? "enabled" : "disabled");
321 return count;
322}
323
2ba8bfc8
SC		 324static ssize_t host_store_raid_offload_debug(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t count)
327{
328 int debug_level, len;
329 struct ctlr_info *h;
330 struct Scsi_Host *shost = class_to_shost(dev);
331 char tmpbuf[10];
332
333 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
334 return -EACCES;
335 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
336 strncpy(tmpbuf, buf, len);
337 tmpbuf[len] = '\0';
338 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
339 return -EINVAL;
340 if (debug_level < 0)
341 debug_level = 0;
342 h = shost_to_hba(shost);
343 h->raid_offload_debug = debug_level;
344 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
345 h->raid_offload_debug);
346 return count;
347}
348
edd16368
SC		 349static ssize_t host_store_rescan(struct device *dev,
350 struct device_attribute *attr,
351 const char *buf, size_t count)
352{
353 struct ctlr_info *h;
354 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 355 h = shost_to_hba(shost);
31468401 356 hpsa_scan_start(h->scsi_host);
edd16368
SC		 357 return count;
358}
359
d28ce020
SC		 360static ssize_t host_show_firmware_revision(struct device *dev,
361 struct device_attribute *attr, char *buf)
362{
363 struct ctlr_info *h;
364 struct Scsi_Host *shost = class_to_shost(dev);
365 unsigned char *fwrev;
366
367 h = shost_to_hba(shost);
368 if (!h->hba_inquiry_data)
369 return 0;
370 fwrev = &h->hba_inquiry_data[32];
371 return snprintf(buf, 20, "%c%c%c%c\n",
372 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
373}
374
94a13649
SC		 375static ssize_t host_show_commands_outstanding(struct device *dev,
376 struct device_attribute *attr, char *buf)
377{
378 struct Scsi_Host *shost = class_to_shost(dev);
379 struct ctlr_info *h = shost_to_hba(shost);
380
381 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
382}
383
745a7a25
SC		 384static ssize_t host_show_transport_mode(struct device *dev,
385 struct device_attribute *attr, char *buf)
386{
387 struct ctlr_info *h;
388 struct Scsi_Host *shost = class_to_shost(dev);
389
390 h = shost_to_hba(shost);
391 return snprintf(buf, 20, "%s\n",
960a30e7 392 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 393 "performant" : "simple");
394}
395
da0697bd
ST		 396static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
397 struct device_attribute *attr, char *buf)
398{
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401
402 h = shost_to_hba(shost);
403 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
404 (h->acciopath_status == 1) ? "enabled" : "disabled");
405}
406
46380786 407/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 408static u32 unresettable_controller[] = {
409 0x324a103C, /* Smart Array P712m */
410 0x324b103C, /* SmartArray P711m */
411 0x3223103C, /* Smart Array P800 */
412 0x3234103C, /* Smart Array P400 */
413 0x3235103C, /* Smart Array P400i */
414 0x3211103C, /* Smart Array E200i */
415 0x3212103C, /* Smart Array E200 */
416 0x3213103C, /* Smart Array E200i */
417 0x3214103C, /* Smart Array E200i */
418 0x3215103C, /* Smart Array E200i */
419 0x3237103C, /* Smart Array E500 */
420 0x323D103C, /* Smart Array P700m */
7af0abbc 421 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 422 0x409C0E11, /* Smart Array 6400 */
423 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 424 0x40700E11, /* Smart Array 5300 */
425 0x40820E11, /* Smart Array 532 */
426 0x40830E11, /* Smart Array 5312 */
427 0x409A0E11, /* Smart Array 641 */
428 0x409B0E11, /* Smart Array 642 */
429 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 430};
431
46380786
SC		 432/* List of controllers which cannot even be soft reset */
433static u32 soft_unresettable_controller[] = {
7af0abbc 434 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 435 0x40700E11, /* Smart Array 5300 */
436 0x40820E11, /* Smart Array 532 */
437 0x40830E11, /* Smart Array 5312 */
438 0x409A0E11, /* Smart Array 641 */
439 0x409B0E11, /* Smart Array 642 */
440 0x40910E11, /* Smart Array 6i */
46380786
SC		 441 /* Exclude 640x boards. These are two pci devices in one slot
442 * which share a battery backed cache module. One controls the
443 * cache, the other accesses the cache through the one that controls
444 * it. If we reset the one controlling the cache, the other will
445 * likely not be happy. Just forbid resetting this conjoined mess.
446 * The 640x isn't really supported by hpsa anyway.
447 */
448 0x409C0E11, /* Smart Array 6400 */
449 0x409D0E11, /* Smart Array 6400 EM */
450};
451
452static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 453{
454 int i;
455
456 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 457 if (unresettable_controller[i] == board_id)
458 return 0;
459 return 1;
460}
461
462static int ctlr_is_soft_resettable(u32 board_id)
463{
464 int i;
465
466 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
467 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 468 return 0;
469 return 1;
470}
471
46380786
SC		 472static int ctlr_is_resettable(u32 board_id)
473{
474 return ctlr_is_hard_resettable(board_id) ||
475 ctlr_is_soft_resettable(board_id);
476}
477
941b1cda
SC		 478static ssize_t host_show_resettable(struct device *dev,
479 struct device_attribute *attr, char *buf)
480{
481 struct ctlr_info *h;
482 struct Scsi_Host *shost = class_to_shost(dev);
483
484 h = shost_to_hba(shost);
46380786 485 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 486}
487
edd16368
SC		 488static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
489{
490 return (scsi3addr[3] & 0xC0) == 0x40;
491}
492
493static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 494 "1(ADM)", "UNKNOWN"
edd16368 495};
6b80b18f
ST		 496#define HPSA_RAID_0 0
497#define HPSA_RAID_4 1
498#define HPSA_RAID_1 2 /* also used for RAID 10 */
499#define HPSA_RAID_5 3 /* also used for RAID 50 */
500#define HPSA_RAID_51 4
501#define HPSA_RAID_6 5 /* also used for RAID 60 */
502#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 503#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
504
505static ssize_t raid_level_show(struct device *dev,
506 struct device_attribute *attr, char *buf)
507{
508 ssize_t l = 0;
82a72c0a 509 unsigned char rlevel;
edd16368
SC		 510 struct ctlr_info *h;
511 struct scsi_device *sdev;
512 struct hpsa_scsi_dev_t *hdev;
513 unsigned long flags;
514
515 sdev = to_scsi_device(dev);
516 h = sdev_to_hba(sdev);
517 spin_lock_irqsave(&h->lock, flags);
518 hdev = sdev->hostdata;
519 if (!hdev) {
520 spin_unlock_irqrestore(&h->lock, flags);
521 return -ENODEV;
522 }
523
524 /* Is this even a logical drive? */
525 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
526 spin_unlock_irqrestore(&h->lock, flags);
527 l = snprintf(buf, PAGE_SIZE, "N/A\n");
528 return l;
529 }
530
531 rlevel = hdev->raid_level;
532 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 533 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 534 rlevel = RAID_UNKNOWN;
535 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
536 return l;
537}
538
539static ssize_t lunid_show(struct device *dev,
540 struct device_attribute *attr, char *buf)
541{
542 struct ctlr_info *h;
543 struct scsi_device *sdev;
544 struct hpsa_scsi_dev_t *hdev;
545 unsigned long flags;
546 unsigned char lunid[8];
547
548 sdev = to_scsi_device(dev);
549 h = sdev_to_hba(sdev);
550 spin_lock_irqsave(&h->lock, flags);
551 hdev = sdev->hostdata;
552 if (!hdev) {
553 spin_unlock_irqrestore(&h->lock, flags);
554 return -ENODEV;
555 }
556 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
557 spin_unlock_irqrestore(&h->lock, flags);
558 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
559 lunid[0], lunid[1], lunid[2], lunid[3],
560 lunid[4], lunid[5], lunid[6], lunid[7]);
561}
562
563static ssize_t unique_id_show(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct scsi_device *sdev;
568 struct hpsa_scsi_dev_t *hdev;
569 unsigned long flags;
570 unsigned char sn[16];
571
572 sdev = to_scsi_device(dev);
573 h = sdev_to_hba(sdev);
574 spin_lock_irqsave(&h->lock, flags);
575 hdev = sdev->hostdata;
576 if (!hdev) {
577 spin_unlock_irqrestore(&h->lock, flags);
578 return -ENODEV;
579 }
580 memcpy(sn, hdev->device_id, sizeof(sn));
581 spin_unlock_irqrestore(&h->lock, flags);
582 return snprintf(buf, 16 * 2 + 2,
583 "%02X%02X%02X%02X%02X%02X%02X%02X"
584 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
585 sn[0], sn[1], sn[2], sn[3],
586 sn[4], sn[5], sn[6], sn[7],
587 sn[8], sn[9], sn[10], sn[11],
588 sn[12], sn[13], sn[14], sn[15]);
589}
590
c1988684
ST		 591static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
592 struct device_attribute *attr, char *buf)
593{
594 struct ctlr_info *h;
595 struct scsi_device *sdev;
596 struct hpsa_scsi_dev_t *hdev;
597 unsigned long flags;
598 int offload_enabled;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608 offload_enabled = hdev->offload_enabled;
609 spin_unlock_irqrestore(&h->lock, flags);
610 return snprintf(buf, 20, "%d\n", offload_enabled);
611}
612
3f5eac3a
SC		 613static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
614static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
615static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
616static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 617static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
618 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 619static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
620 host_show_hp_ssd_smart_path_status,
621 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 622static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
623 host_store_raid_offload_debug);
3f5eac3a
SC		 624static DEVICE_ATTR(firmware_revision, S_IRUGO,
625 host_show_firmware_revision, NULL);
626static DEVICE_ATTR(commands_outstanding, S_IRUGO,
627 host_show_commands_outstanding, NULL);
628static DEVICE_ATTR(transport_mode, S_IRUGO,
629 host_show_transport_mode, NULL);
941b1cda
SC		 630static DEVICE_ATTR(resettable, S_IRUGO,
631 host_show_resettable, NULL);
3f5eac3a
SC		 632
633static struct device_attribute *hpsa_sdev_attrs[] = {
634 &dev_attr_raid_level,
635 &dev_attr_lunid,
636 &dev_attr_unique_id,
c1988684 637 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 638 NULL,
639};
640
641static struct device_attribute *hpsa_shost_attrs[] = {
642 &dev_attr_rescan,
643 &dev_attr_firmware_revision,
644 &dev_attr_commands_outstanding,
645 &dev_attr_transport_mode,
941b1cda 646 &dev_attr_resettable,
da0697bd 647 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 648 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 649 NULL,
650};
651
652static struct scsi_host_template hpsa_driver_template = {
653 .module = THIS_MODULE,
f79cfec6
SC		 654 .name = HPSA,
655 .proc_name = HPSA,
3f5eac3a
SC		 656 .queuecommand = hpsa_scsi_queue_command,
657 .scan_start = hpsa_scan_start,
658 .scan_finished = hpsa_scan_finished,
659 .change_queue_depth = hpsa_change_queue_depth,
660 .this_id = -1,
661 .use_clustering = ENABLE_CLUSTERING,
75167d2c 662 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 663 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
664 .ioctl = hpsa_ioctl,
665 .slave_alloc = hpsa_slave_alloc,
666 .slave_destroy = hpsa_slave_destroy,
667#ifdef CONFIG_COMPAT
668 .compat_ioctl = hpsa_compat_ioctl,
669#endif
670 .sdev_attrs = hpsa_sdev_attrs,
671 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 672 .max_sectors = 8192,
54b2b50c 673 .no_write_same = 1,
3f5eac3a
SC		 674};
675
676
677/* Enqueuing and dequeuing functions for cmdlists. */
678static inline void addQ(struct list_head *list, struct CommandList *c)
679{
680 list_add_tail(&c->list, list);
681}
682
254f796b 683static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 684{
685 u32 a;
254f796b 686 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 687 unsigned long flags;
3f5eac3a 688
e1f7de0c
MG		 689 if (h->transMethod & CFGTBL_Trans_io_accel1)
690 return h->access.command_completed(h, q);
691
3f5eac3a 692 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 693 return h->access.command_completed(h, q);
3f5eac3a 694
254f796b
MG		 695 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
696 a = rq->head[rq->current_entry];
697 rq->current_entry++;
e16a33ad 698 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 699 h->commands_outstanding--;
e16a33ad 700 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 701 } else {
702 a = FIFO_EMPTY;
703 }
704 /* Check for wraparound */
254f796b
MG		 705 if (rq->current_entry == h->max_commands) {
706 rq->current_entry = 0;
707 rq->wraparound ^= 1;
3f5eac3a
SC		 708 }
709 return a;
710}
711
c349775e
ST		 712/*
713 * There are some special bits in the bus address of the
714 * command that we have to set for the controller to know
715 * how to process the command:
716 *
717 * Normal performant mode:
718 * bit 0: 1 means performant mode, 0 means simple mode.
719 * bits 1-3 = block fetch table entry
720 * bits 4-6 = command type (== 0)
721 *
722 * ioaccel1 mode:
723 * bit 0 = "performant mode" bit.
724 * bits 1-3 = block fetch table entry
725 * bits 4-6 = command type (== 110)
726 * (command type is needed because ioaccel1 mode
727 * commands are submitted through the same register as normal
728 * mode commands, so this is how the controller knows whether
729 * the command is normal mode or ioaccel1 mode.)
730 *
731 * ioaccel2 mode:
732 * bit 0 = "performant mode" bit.
733 * bits 1-4 = block fetch table entry (note extra bit)
734 * bits 4-6 = not needed, because ioaccel2 mode has
735 * a separate special register for submitting commands.
736 */
737
3f5eac3a
SC		 738/* set_performant_mode: Modify the tag for cciss performant
739 * set bit 0 for pull model, bits 3-1 for block fetch
740 * register number
741 */
742static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
743{
254f796b 744 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 745 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 746 if (likely(h->msix_vector > 0))
254f796b 747 c->Header.ReplyQueue =
804a5cb5 748 raw_smp_processor_id() % h->nreply_queues;
254f796b 749 }
3f5eac3a
SC		 750}
751
c349775e
ST		 752static void set_ioaccel1_performant_mode(struct ctlr_info *h,
753 struct CommandList *c)
754{
755 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
756
757 /* Tell the controller to post the reply to the queue for this
758 * processor. This seems to give the best I/O throughput.
759 */
760 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
761 /* Set the bits in the address sent down to include:
762 * - performant mode bit (bit 0)
763 * - pull count (bits 1-3)
764 * - command type (bits 4-6)
765 */
766 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
767 IOACCEL1_BUSADDR_CMDTYPE;
768}
769
770static void set_ioaccel2_performant_mode(struct ctlr_info *h,
771 struct CommandList *c)
772{
773 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
774
775 /* Tell the controller to post the reply to the queue for this
776 * processor. This seems to give the best I/O throughput.
777 */
778 cp->reply_queue = smp_processor_id() % h->nreply_queues;
779 /* Set the bits in the address sent down to include:
780 * - performant mode bit not used in ioaccel mode 2
781 * - pull count (bits 0-3)
782 * - command type isn't needed for ioaccel2
783 */
784 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
785}
786
e85c5974
SC		 787static int is_firmware_flash_cmd(u8 *cdb)
788{
789 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
790}
791
792/*
793 * During firmware flash, the heartbeat register may not update as frequently
794 * as it should. So we dial down lockup detection during firmware flash. and
795 * dial it back up when firmware flash completes.
796 */
797#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
798#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
799static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
800 struct CommandList *c)
801{
802 if (!is_firmware_flash_cmd(c->Request.CDB))
803 return;
804 atomic_inc(&h->firmware_flash_in_progress);
805 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
806}
807
808static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
809 struct CommandList *c)
810{
811 if (is_firmware_flash_cmd(c->Request.CDB) &&
812 atomic_dec_and_test(&h->firmware_flash_in_progress))
813 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
814}
815
3f5eac3a
SC		 816static void enqueue_cmd_and_start_io(struct ctlr_info *h,
817 struct CommandList *c)
818{
819 unsigned long flags;
820
c349775e
ST		 821 switch (c->cmd_type) {
822 case CMD_IOACCEL1:
823 set_ioaccel1_performant_mode(h, c);
824 break;
825 case CMD_IOACCEL2:
826 set_ioaccel2_performant_mode(h, c);
827 break;
828 default:
829 set_performant_mode(h, c);
830 }
e85c5974 831 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 832 spin_lock_irqsave(&h->lock, flags);
833 addQ(&h->reqQ, c);
834 h->Qdepth++;
3f5eac3a 835 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 836 start_io(h);
3f5eac3a
SC		 837}
838
839static inline void removeQ(struct CommandList *c)
840{
841 if (WARN_ON(list_empty(&c->list)))
842 return;
843 list_del_init(&c->list);
844}
845
846static inline int is_hba_lunid(unsigned char scsi3addr[])
847{
848 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
849}
850
851static inline int is_scsi_rev_5(struct ctlr_info *h)
852{
853 if (!h->hba_inquiry_data)
854 return 0;
855 if ((h->hba_inquiry_data[2] & 0x07) == 5)
856 return 1;
857 return 0;
858}
859
edd16368
SC		 860static int hpsa_find_target_lun(struct ctlr_info *h,
861 unsigned char scsi3addr[], int bus, int *target, int *lun)
862{
863 /* finds an unused bus, target, lun for a new physical device
864 * assumes h->devlock is held
865 */
866 int i, found = 0;
cfe5badc 867 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 868
263d9401 869 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 870
871 for (i = 0; i < h->ndevices; i++) {
872 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 873 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 874 }
875
263d9401
AM		 876 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
877 if (i < HPSA_MAX_DEVICES) {
878 /* *bus = 1; */
879 *target = i;
880 *lun = 0;
881 found = 1;
edd16368
SC		 882 }
883 return !found;
884}
885
886/* Add an entry into h->dev[] array. */
887static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
888 struct hpsa_scsi_dev_t *device,
889 struct hpsa_scsi_dev_t *added[], int *nadded)
890{
891 /* assumes h->devlock is held */
892 int n = h->ndevices;
893 int i;
894 unsigned char addr1[8], addr2[8];
895 struct hpsa_scsi_dev_t *sd;
896
cfe5badc 897 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 898 dev_err(&h->pdev->dev, "too many devices, some will be "
899 "inaccessible.\n");
900 return -1;
901 }
902
903 /* physical devices do not have lun or target assigned until now. */
904 if (device->lun != -1)
905 /* Logical device, lun is already assigned. */
906 goto lun_assigned;
907
908 /* If this device a non-zero lun of a multi-lun device
909 * byte 4 of the 8-byte LUN addr will contain the logical
910 * unit no, zero otherise.
911 */
912 if (device->scsi3addr[4] == 0) {
913 /* This is not a non-zero lun of a multi-lun device */
914 if (hpsa_find_target_lun(h, device->scsi3addr,
915 device->bus, &device->target, &device->lun) != 0)
916 return -1;
917 goto lun_assigned;
918 }
919
920 /* This is a non-zero lun of a multi-lun device.
921 * Search through our list and find the device which
922 * has the same 8 byte LUN address, excepting byte 4.
923 * Assign the same bus and target for this new LUN.
924 * Use the logical unit number from the firmware.
925 */
926 memcpy(addr1, device->scsi3addr, 8);
927 addr1[4] = 0;
928 for (i = 0; i < n; i++) {
929 sd = h->dev[i];
930 memcpy(addr2, sd->scsi3addr, 8);
931 addr2[4] = 0;
932 /* differ only in byte 4? */
933 if (memcmp(addr1, addr2, 8) == 0) {
934 device->bus = sd->bus;
935 device->target = sd->target;
936 device->lun = device->scsi3addr[4];
937 break;
938 }
939 }
940 if (device->lun == -1) {
941 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
942 " suspect firmware bug or unsupported hardware "
943 "configuration.\n");
944 return -1;
945 }
946
947lun_assigned:
948
949 h->dev[n] = device;
950 h->ndevices++;
951 added[*nadded] = device;
952 (*nadded)++;
953
954 /* initially, (before registering with scsi layer) we don't
955 * know our hostno and we don't want to print anything first
956 * time anyway (the scsi layer's inquiries will show that info)
957 */
958 /* if (hostno != -1) */
959 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
960 scsi_device_type(device->devtype), hostno,
961 device->bus, device->target, device->lun);
962 return 0;
963}
964
bd9244f7
ST		 965/* Update an entry in h->dev[] array. */
966static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
967 int entry, struct hpsa_scsi_dev_t *new_entry)
968{
969 /* assumes h->devlock is held */
970 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
971
972 /* Raid level changed. */
973 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 974
975 /* Raid offload parameters changed. */
976 h->dev[entry]->offload_config = new_entry->offload_config;
977 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 978 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
979 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
980 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 981
bd9244f7
ST		 982 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
983 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
984 new_entry->target, new_entry->lun);
985}
986
2a8ccf31
SC		 987/* Replace an entry from h->dev[] array. */
988static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
989 int entry, struct hpsa_scsi_dev_t *new_entry,
990 struct hpsa_scsi_dev_t *added[], int *nadded,
991 struct hpsa_scsi_dev_t *removed[], int *nremoved)
992{
993 /* assumes h->devlock is held */
cfe5badc 994 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 995 removed[*nremoved] = h->dev[entry];
996 (*nremoved)++;
01350d05
SC		 997
998 /*
999 * New physical devices won't have target/lun assigned yet
1000 * so we need to preserve the values in the slot we are replacing.
1001 */
1002 if (new_entry->target == -1) {
1003 new_entry->target = h->dev[entry]->target;
1004 new_entry->lun = h->dev[entry]->lun;
1005 }
1006
2a8ccf31
SC		 1007 h->dev[entry] = new_entry;
1008 added[*nadded] = new_entry;
1009 (*nadded)++;
1010 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1011 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1012 new_entry->target, new_entry->lun);
1013}
1014
edd16368
SC		 1015/* Remove an entry from h->dev[] array. */
1016static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1017 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1018{
1019 /* assumes h->devlock is held */
1020 int i;
1021 struct hpsa_scsi_dev_t *sd;
1022
cfe5badc 1023 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1024
1025 sd = h->dev[entry];
1026 removed[*nremoved] = h->dev[entry];
1027 (*nremoved)++;
1028
1029 for (i = entry; i < h->ndevices-1; i++)
1030 h->dev[i] = h->dev[i+1];
1031 h->ndevices--;
1032 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1033 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1034 sd->lun);
1035}
1036
1037#define SCSI3ADDR_EQ(a, b) ( \
1038 (a)[7] == (b)[7] && \
1039 (a)[6] == (b)[6] && \
1040 (a)[5] == (b)[5] && \
1041 (a)[4] == (b)[4] && \
1042 (a)[3] == (b)[3] && \
1043 (a)[2] == (b)[2] && \
1044 (a)[1] == (b)[1] && \
1045 (a)[0] == (b)[0])
1046
1047static void fixup_botched_add(struct ctlr_info *h,
1048 struct hpsa_scsi_dev_t *added)
1049{
1050 /* called when scsi_add_device fails in order to re-adjust
1051 * h->dev[] to match the mid layer's view.
1052 */
1053 unsigned long flags;
1054 int i, j;
1055
1056 spin_lock_irqsave(&h->lock, flags);
1057 for (i = 0; i < h->ndevices; i++) {
1058 if (h->dev[i] == added) {
1059 for (j = i; j < h->ndevices-1; j++)
1060 h->dev[j] = h->dev[j+1];
1061 h->ndevices--;
1062 break;
1063 }
1064 }
1065 spin_unlock_irqrestore(&h->lock, flags);
1066 kfree(added);
1067}
1068
1069static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1070 struct hpsa_scsi_dev_t *dev2)
1071{
edd16368
SC		 1072 /* we compare everything except lun and target as these
1073 * are not yet assigned. Compare parts likely
1074 * to differ first
1075 */
1076 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1077 sizeof(dev1->scsi3addr)) != 0)
1078 return 0;
1079 if (memcmp(dev1->device_id, dev2->device_id,
1080 sizeof(dev1->device_id)) != 0)
1081 return 0;
1082 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1083 return 0;
1084 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1085 return 0;
edd16368
SC		 1086 if (dev1->devtype != dev2->devtype)
1087 return 0;
edd16368
SC		 1088 if (dev1->bus != dev2->bus)
1089 return 0;
1090 return 1;
1091}
1092
bd9244f7
ST		 1093static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1094 struct hpsa_scsi_dev_t *dev2)
1095{
1096 /* Device attributes that can change, but don't mean
1097 * that the device is a different device, nor that the OS
1098 * needs to be told anything about the change.
1099 */
1100 if (dev1->raid_level != dev2->raid_level)
1101 return 1;
250fb125
SC		 1102 if (dev1->offload_config != dev2->offload_config)
1103 return 1;
1104 if (dev1->offload_enabled != dev2->offload_enabled)
1105 return 1;
bd9244f7
ST		 1106 return 0;
1107}
1108
edd16368
SC		 1109/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1110 * and return needle location in *index. If scsi3addr matches, but not
1111 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1112 * location in *index.
1113 * In the case of a minor device attribute change, such as RAID level, just
1114 * return DEVICE_UPDATED, along with the updated device's location in index.
1115 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1116 */
1117static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1118 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1119 int *index)
1120{
1121 int i;
1122#define DEVICE_NOT_FOUND 0
1123#define DEVICE_CHANGED 1
1124#define DEVICE_SAME 2
bd9244f7 1125#define DEVICE_UPDATED 3
edd16368 1126 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1127 if (haystack[i] == NULL) /* previously removed. */
1128 continue;
edd16368
SC		 1129 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1130 *index = i;
bd9244f7
ST		 1131 if (device_is_the_same(needle, haystack[i])) {
1132 if (device_updated(needle, haystack[i]))
1133 return DEVICE_UPDATED;
edd16368 1134 return DEVICE_SAME;
bd9244f7 1135 } else {
9846590e
SC		 1136 /* Keep offline devices offline */
1137 if (needle->volume_offline)
1138 return DEVICE_NOT_FOUND;
edd16368 1139 return DEVICE_CHANGED;
bd9244f7 1140 }
edd16368
SC		 1141 }
1142 }
1143 *index = -1;
1144 return DEVICE_NOT_FOUND;
1145}
1146
9846590e
SC		 1147static void hpsa_monitor_offline_device(struct ctlr_info *h,
1148 unsigned char scsi3addr[])
1149{
1150 struct offline_device_entry *device;
1151 unsigned long flags;
1152
1153 /* Check to see if device is already on the list */
1154 spin_lock_irqsave(&h->offline_device_lock, flags);
1155 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1156 if (memcmp(device->scsi3addr, scsi3addr,
1157 sizeof(device->scsi3addr)) == 0) {
1158 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1159 return;
1160 }
1161 }
1162 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1163
1164 /* Device is not on the list, add it. */
1165 device = kmalloc(sizeof(*device), GFP_KERNEL);
1166 if (!device) {
1167 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1168 return;
1169 }
1170 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1171 spin_lock_irqsave(&h->offline_device_lock, flags);
1172 list_add_tail(&device->offline_list, &h->offline_device_list);
1173 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1174}
1175
1176/* Print a message explaining various offline volume states */
1177static void hpsa_show_volume_status(struct ctlr_info *h,
1178 struct hpsa_scsi_dev_t *sd)
1179{
1180 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1181 dev_info(&h->pdev->dev,
1182 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1183 h->scsi_host->host_no,
1184 sd->bus, sd->target, sd->lun);
1185 switch (sd->volume_offline) {
1186 case HPSA_LV_OK:
1187 break;
1188 case HPSA_LV_UNDERGOING_ERASE:
1189 dev_info(&h->pdev->dev,
1190 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1191 h->scsi_host->host_no,
1192 sd->bus, sd->target, sd->lun);
1193 break;
1194 case HPSA_LV_UNDERGOING_RPI:
1195 dev_info(&h->pdev->dev,
1196 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1197 h->scsi_host->host_no,
1198 sd->bus, sd->target, sd->lun);
1199 break;
1200 case HPSA_LV_PENDING_RPI:
1201 dev_info(&h->pdev->dev,
1202 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1203 h->scsi_host->host_no,
1204 sd->bus, sd->target, sd->lun);
1205 break;
1206 case HPSA_LV_ENCRYPTED_NO_KEY:
1207 dev_info(&h->pdev->dev,
1208 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1209 h->scsi_host->host_no,
1210 sd->bus, sd->target, sd->lun);
1211 break;
1212 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1213 dev_info(&h->pdev->dev,
1214 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1215 h->scsi_host->host_no,
1216 sd->bus, sd->target, sd->lun);
1217 break;
1218 case HPSA_LV_UNDERGOING_ENCRYPTION:
1219 dev_info(&h->pdev->dev,
1220 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1221 h->scsi_host->host_no,
1222 sd->bus, sd->target, sd->lun);
1223 break;
1224 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1225 dev_info(&h->pdev->dev,
1226 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1227 h->scsi_host->host_no,
1228 sd->bus, sd->target, sd->lun);
1229 break;
1230 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1231 dev_info(&h->pdev->dev,
1232 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1233 h->scsi_host->host_no,
1234 sd->bus, sd->target, sd->lun);
1235 break;
1236 case HPSA_LV_PENDING_ENCRYPTION:
1237 dev_info(&h->pdev->dev,
1238 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1239 h->scsi_host->host_no,
1240 sd->bus, sd->target, sd->lun);
1241 break;
1242 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1243 dev_info(&h->pdev->dev,
1244 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1245 h->scsi_host->host_no,
1246 sd->bus, sd->target, sd->lun);
1247 break;
1248 }
1249}
1250
4967bd3e 1251static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1252 struct hpsa_scsi_dev_t *sd[], int nsds)
1253{
1254 /* sd contains scsi3 addresses and devtypes, and inquiry
1255 * data. This function takes what's in sd to be the current
1256 * reality and updates h->dev[] to reflect that reality.
1257 */
1258 int i, entry, device_change, changes = 0;
1259 struct hpsa_scsi_dev_t *csd;
1260 unsigned long flags;
1261 struct hpsa_scsi_dev_t **added, **removed;
1262 int nadded, nremoved;
1263 struct Scsi_Host *sh = NULL;
1264
cfe5badc
ST		 1265 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1266 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1267
1268 if (!added || !removed) {
1269 dev_warn(&h->pdev->dev, "out of memory in "
1270 "adjust_hpsa_scsi_table\n");
1271 goto free_and_out;
1272 }
1273
1274 spin_lock_irqsave(&h->devlock, flags);
1275
1276 /* find any devices in h->dev[] that are not in
1277 * sd[] and remove them from h->dev[], and for any
1278 * devices which have changed, remove the old device
1279 * info and add the new device info.
bd9244f7
ST		 1280 * If minor device attributes change, just update
1281 * the existing device structure.
edd16368
SC		 1282 */
1283 i = 0;
1284 nremoved = 0;
1285 nadded = 0;
1286 while (i < h->ndevices) {
1287 csd = h->dev[i];
1288 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1289 if (device_change == DEVICE_NOT_FOUND) {
1290 changes++;
1291 hpsa_scsi_remove_entry(h, hostno, i,
1292 removed, &nremoved);
1293 continue; /* remove ^^^, hence i not incremented */
1294 } else if (device_change == DEVICE_CHANGED) {
1295 changes++;
2a8ccf31
SC		 1296 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1297 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1298 /* Set it to NULL to prevent it from being freed
1299 * at the bottom of hpsa_update_scsi_devices()
1300 */
1301 sd[entry] = NULL;
bd9244f7
ST		 1302 } else if (device_change == DEVICE_UPDATED) {
1303 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1304 }
1305 i++;
1306 }
1307
1308 /* Now, make sure every device listed in sd[] is also
1309 * listed in h->dev[], adding them if they aren't found
1310 */
1311
1312 for (i = 0; i < nsds; i++) {
1313 if (!sd[i]) /* if already added above. */
1314 continue;
9846590e
SC		 1315
1316 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1317 * as the SCSI mid-layer does not handle such devices well.
1318 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1319 * at 160Hz, and prevents the system from coming up.
1320 */
1321 if (sd[i]->volume_offline) {
1322 hpsa_show_volume_status(h, sd[i]);
1323 dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n",
1324 h->scsi_host->host_no,
1325 sd[i]->bus, sd[i]->target, sd[i]->lun);
1326 continue;
1327 }
1328
edd16368
SC		 1329 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1330 h->ndevices, &entry);
1331 if (device_change == DEVICE_NOT_FOUND) {
1332 changes++;
1333 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1334 added, &nadded) != 0)
1335 break;
1336 sd[i] = NULL; /* prevent from being freed later. */
1337 } else if (device_change == DEVICE_CHANGED) {
1338 /* should never happen... */
1339 changes++;
1340 dev_warn(&h->pdev->dev,
1341 "device unexpectedly changed.\n");
1342 /* but if it does happen, we just ignore that device */
1343 }
1344 }
1345 spin_unlock_irqrestore(&h->devlock, flags);
1346
9846590e
SC		 1347 /* Monitor devices which are in one of several NOT READY states to be
1348 * brought online later. This must be done without holding h->devlock,
1349 * so don't touch h->dev[]
1350 */
1351 for (i = 0; i < nsds; i++) {
1352 if (!sd[i]) /* if already added above. */
1353 continue;
1354 if (sd[i]->volume_offline)
1355 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1356 }
1357
edd16368
SC		 1358 /* Don't notify scsi mid layer of any changes the first time through
1359 * (or if there are no changes) scsi_scan_host will do it later the
1360 * first time through.
1361 */
1362 if (hostno == -1 || !changes)
1363 goto free_and_out;
1364
1365 sh = h->scsi_host;
1366 /* Notify scsi mid layer of any removed devices */
1367 for (i = 0; i < nremoved; i++) {
1368 struct scsi_device *sdev =
1369 scsi_device_lookup(sh, removed[i]->bus,
1370 removed[i]->target, removed[i]->lun);
1371 if (sdev != NULL) {
1372 scsi_remove_device(sdev);
1373 scsi_device_put(sdev);
1374 } else {
1375 /* We don't expect to get here.
1376 * future cmds to this device will get selection
1377 * timeout as if the device was gone.
1378 */
1379 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1380 " for removal.", hostno, removed[i]->bus,
1381 removed[i]->target, removed[i]->lun);
1382 }
1383 kfree(removed[i]);
1384 removed[i] = NULL;
1385 }
1386
1387 /* Notify scsi mid layer of any added devices */
1388 for (i = 0; i < nadded; i++) {
1389 if (scsi_add_device(sh, added[i]->bus,
1390 added[i]->target, added[i]->lun) == 0)
1391 continue;
1392 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1393 "device not added.\n", hostno, added[i]->bus,
1394 added[i]->target, added[i]->lun);
1395 /* now we have to remove it from h->dev,
1396 * since it didn't get added to scsi mid layer
1397 */
1398 fixup_botched_add(h, added[i]);
1399 }
1400
1401free_and_out:
1402 kfree(added);
1403 kfree(removed);
edd16368
SC		 1404}
1405
1406/*
9e03aa2f 1407 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1408 * Assume's h->devlock is held.
1409 */
1410static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1411 int bus, int target, int lun)
1412{
1413 int i;
1414 struct hpsa_scsi_dev_t *sd;
1415
1416 for (i = 0; i < h->ndevices; i++) {
1417 sd = h->dev[i];
1418 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1419 return sd;
1420 }
1421 return NULL;
1422}
1423
1424/* link sdev->hostdata to our per-device structure. */
1425static int hpsa_slave_alloc(struct scsi_device *sdev)
1426{
1427 struct hpsa_scsi_dev_t *sd;
1428 unsigned long flags;
1429 struct ctlr_info *h;
1430
1431 h = sdev_to_hba(sdev);
1432 spin_lock_irqsave(&h->devlock, flags);
1433 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1434 sdev_id(sdev), sdev->lun);
1435 if (sd != NULL)
1436 sdev->hostdata = sd;
1437 spin_unlock_irqrestore(&h->devlock, flags);
1438 return 0;
1439}
1440
1441static void hpsa_slave_destroy(struct scsi_device *sdev)
1442{
bcc44255 1443 /* nothing to do. */
edd16368
SC		 1444}
1445
33a2ffce
SC		 1446static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1447{
1448 int i;
1449
1450 if (!h->cmd_sg_list)
1451 return;
1452 for (i = 0; i < h->nr_cmds; i++) {
1453 kfree(h->cmd_sg_list[i]);
1454 h->cmd_sg_list[i] = NULL;
1455 }
1456 kfree(h->cmd_sg_list);
1457 h->cmd_sg_list = NULL;
1458}
1459
1460static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1461{
1462 int i;
1463
1464 if (h->chainsize <= 0)
1465 return 0;
1466
1467 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1468 GFP_KERNEL);
1469 if (!h->cmd_sg_list)
1470 return -ENOMEM;
1471 for (i = 0; i < h->nr_cmds; i++) {
1472 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1473 h->chainsize, GFP_KERNEL);
1474 if (!h->cmd_sg_list[i])
1475 goto clean;
1476 }
1477 return 0;
1478
1479clean:
1480 hpsa_free_sg_chain_blocks(h);
1481 return -ENOMEM;
1482}
1483
e2bea6df 1484static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1485 struct CommandList *c)
1486{
1487 struct SGDescriptor *chain_sg, *chain_block;
1488 u64 temp64;
1489
1490 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1491 chain_block = h->cmd_sg_list[c->cmdindex];
1492 chain_sg->Ext = HPSA_SG_CHAIN;
1493 chain_sg->Len = sizeof(*chain_sg) *
1494 (c->Header.SGTotal - h->max_cmd_sg_entries);
1495 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1496 PCI_DMA_TODEVICE);
e2bea6df
SC		 1497 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1498 /* prevent subsequent unmapping */
1499 chain_sg->Addr.lower = 0;
1500 chain_sg->Addr.upper = 0;
1501 return -1;
1502 }
33a2ffce
SC		 1503 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1504 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1505 return 0;
33a2ffce
SC		 1506}
1507
1508static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1509 struct CommandList *c)
1510{
1511 struct SGDescriptor *chain_sg;
1512 union u64bit temp64;
1513
1514 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1515 return;
1516
1517 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1518 temp64.val32.lower = chain_sg->Addr.lower;
1519 temp64.val32.upper = chain_sg->Addr.upper;
1520 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1521}
1522
a09c1441
ST		 1523
1524/* Decode the various types of errors on ioaccel2 path.
1525 * Return 1 for any error that should generate a RAID path retry.
1526 * Return 0 for errors that don't require a RAID path retry.
1527 */
1528static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1529 struct CommandList *c,
1530 struct scsi_cmnd *cmd,
1531 struct io_accel2_cmd *c2)
1532{
1533 int data_len;
a09c1441 1534 int retry = 0;
c349775e
ST		 1535
1536 switch (c2->error_data.serv_response) {
1537 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1538 switch (c2->error_data.status) {
1539 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1540 break;
1541 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1542 dev_warn(&h->pdev->dev,
1543 "%s: task complete with check condition.\n",
1544 "HP SSD Smart Path");
1545 if (c2->error_data.data_present !=
1546 IOACCEL2_SENSE_DATA_PRESENT)
1547 break;
1548 /* copy the sense data */
1549 data_len = c2->error_data.sense_data_len;
1550 if (data_len > SCSI_SENSE_BUFFERSIZE)
1551 data_len = SCSI_SENSE_BUFFERSIZE;
1552 if (data_len > sizeof(c2->error_data.sense_data_buff))
1553 data_len =
1554 sizeof(c2->error_data.sense_data_buff);
1555 memcpy(cmd->sense_buffer,
1556 c2->error_data.sense_data_buff, data_len);
1557 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1558 retry = 1;
c349775e
ST		 1559 break;
1560 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1561 dev_warn(&h->pdev->dev,
1562 "%s: task complete with BUSY status.\n",
1563 "HP SSD Smart Path");
a09c1441 1564 retry = 1;
c349775e
ST		 1565 break;
1566 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1567 dev_warn(&h->pdev->dev,
1568 "%s: task complete with reservation conflict.\n",
1569 "HP SSD Smart Path");
a09c1441 1570 retry = 1;
c349775e
ST		 1571 break;
1572 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1573 /* Make scsi midlayer do unlimited retries */
1574 cmd->result = DID_IMM_RETRY << 16;
1575 break;
1576 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1577 dev_warn(&h->pdev->dev,
1578 "%s: task complete with aborted status.\n",
1579 "HP SSD Smart Path");
a09c1441 1580 retry = 1;
c349775e
ST		 1581 break;
1582 default:
1583 dev_warn(&h->pdev->dev,
1584 "%s: task complete with unrecognized status: 0x%02x\n",
1585 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1586 retry = 1;
c349775e
ST		 1587 break;
1588 }
1589 break;
1590 case IOACCEL2_SERV_RESPONSE_FAILURE:
1591 /* don't expect to get here. */
1592 dev_warn(&h->pdev->dev,
1593 "unexpected delivery or target failure, status = 0x%02x\n",
1594 c2->error_data.status);
a09c1441 1595 retry = 1;
c349775e
ST		 1596 break;
1597 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1598 break;
1599 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1600 break;
1601 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1602 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1603 retry = 1;
c349775e
ST		 1604 break;
1605 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1606 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1607 break;
1608 default:
1609 dev_warn(&h->pdev->dev,
1610 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1611 "HP SSD Smart Path",
1612 c2->error_data.serv_response);
1613 retry = 1;
c349775e
ST		 1614 break;
1615 }
a09c1441
ST		 1616
1617 return retry; /* retry on raid path? */
c349775e
ST		 1618}
1619
1620static void process_ioaccel2_completion(struct ctlr_info *h,
1621 struct CommandList *c, struct scsi_cmnd *cmd,
1622 struct hpsa_scsi_dev_t *dev)
1623{
1624 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1625 int raid_retry = 0;
c349775e
ST		 1626
1627 /* check for good status */
1628 if (likely(c2->error_data.serv_response == 0 &&
1629 c2->error_data.status == 0)) {
1630 cmd_free(h, c);
1631 cmd->scsi_done(cmd);
1632 return;
1633 }
1634
1635 /* Any RAID offload error results in retry which will use
1636 * the normal I/O path so the controller can handle whatever's
1637 * wrong.
1638 */
1639 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1640 c2->error_data.serv_response ==
1641 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1642 if (c2->error_data.status ==
1643 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1644 dev_warn(&h->pdev->dev,
1645 "%s: Path is unavailable, retrying on standard path.\n",
1646 "HP SSD Smart Path");
1647 else
c349775e 1648 dev_warn(&h->pdev->dev,
a09c1441 1649 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1650 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1651
c349775e 1652 dev->offload_enabled = 0;
e863d68e 1653 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1654 cmd->result = DID_SOFT_ERROR << 16;
1655 cmd_free(h, c);
1656 cmd->scsi_done(cmd);
1657 return;
1658 }
a09c1441
ST		 1659 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1660 /* If error found, disable Smart Path, schedule a rescan,
1661 * and force a retry on the standard path.
1662 */
1663 if (raid_retry) {
1664 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1665 "HP SSD Smart Path");
1666 dev->offload_enabled = 0; /* Disable Smart Path */
1667 h->drv_req_rescan = 1; /* schedule controller rescan */
1668 cmd->result = DID_SOFT_ERROR << 16;
1669 }
c349775e
ST		 1670 cmd_free(h, c);
1671 cmd->scsi_done(cmd);
1672}
1673
1fb011fb 1674static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1675{
1676 struct scsi_cmnd *cmd;
1677 struct ctlr_info *h;
1678 struct ErrorInfo *ei;
283b4a9b 1679 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1680
1681 unsigned char sense_key;
1682 unsigned char asc; /* additional sense code */
1683 unsigned char ascq; /* additional sense code qualifier */
db111e18 1684 unsigned long sense_data_size;
edd16368
SC		 1685
1686 ei = cp->err_info;
1687 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1688 h = cp->h;
283b4a9b 1689 dev = cmd->device->hostdata;
edd16368
SC		 1690
1691 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1692 if ((cp->cmd_type == CMD_SCSI) &&
1693 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1694 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1695
1696 cmd->result = (DID_OK << 16); /* host byte */
1697 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1698
1699 if (cp->cmd_type == CMD_IOACCEL2)
1700 return process_ioaccel2_completion(h, cp, cmd, dev);
1701
5512672f 1702 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1703
1704 /* copy the sense data whether we need to or not. */
db111e18
SC		 1705 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1706 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1707 else
1708 sense_data_size = sizeof(ei->SenseInfo);
1709 if (ei->SenseLen < sense_data_size)
1710 sense_data_size = ei->SenseLen;
1711
1712 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1713 scsi_set_resid(cmd, ei->ResidualCnt);
1714
1715 if (ei->CommandStatus == 0) {
edd16368 1716 cmd_free(h, cp);
2cc5bfaf 1717 cmd->scsi_done(cmd);
edd16368
SC		 1718 return;
1719 }
1720
e1f7de0c
MG		 1721 /* For I/O accelerator commands, copy over some fields to the normal
1722 * CISS header used below for error handling.
1723 */
1724 if (cp->cmd_type == CMD_IOACCEL1) {
1725 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1726 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1727 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1728 cp->Header.Tag.lower = c->Tag.lower;
1729 cp->Header.Tag.upper = c->Tag.upper;
1730 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1731 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1732
1733 /* Any RAID offload error results in retry which will use
1734 * the normal I/O path so the controller can handle whatever's
1735 * wrong.
1736 */
1737 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1738 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1739 dev->offload_enabled = 0;
1740 cmd->result = DID_SOFT_ERROR << 16;
1741 cmd_free(h, cp);
1742 cmd->scsi_done(cmd);
1743 return;
1744 }
e1f7de0c
MG		 1745 }
1746
edd16368
SC		 1747 /* an error has occurred */
1748 switch (ei->CommandStatus) {
1749
1750 case CMD_TARGET_STATUS:
1751 if (ei->ScsiStatus) {
1752 /* Get sense key */
1753 sense_key = 0xf & ei->SenseInfo[2];
1754 /* Get additional sense code */
1755 asc = ei->SenseInfo[12];
1756 /* Get addition sense code qualifier */
1757 ascq = ei->SenseInfo[13];
1758 }
1759
1760 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1761 if (check_for_unit_attention(h, cp))
edd16368 1762 break;
edd16368
SC		 1763 if (sense_key == ILLEGAL_REQUEST) {
1764 /*
1765 * SCSI REPORT_LUNS is commonly unsupported on
1766 * Smart Array. Suppress noisy complaint.
1767 */
1768 if (cp->Request.CDB[0] == REPORT_LUNS)
1769 break;
1770
1771 /* If ASC/ASCQ indicate Logical Unit
1772 * Not Supported condition,
1773 */
1774 if ((asc == 0x25) && (ascq == 0x0)) {
1775 dev_warn(&h->pdev->dev, "cp %p "
1776 "has check condition\n", cp);
1777 break;
1778 }
1779 }
1780
1781 if (sense_key == NOT_READY) {
1782 /* If Sense is Not Ready, Logical Unit
1783 * Not ready, Manual Intervention
1784 * required
1785 */
1786 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1787 dev_warn(&h->pdev->dev, "cp %p "
1788 "has check condition: unit "
1789 "not ready, manual "
1790 "intervention required\n", cp);
1791 break;
1792 }
1793 }
1d3b3609
MG		 1794 if (sense_key == ABORTED_COMMAND) {
1795 /* Aborted command is retryable */
1796 dev_warn(&h->pdev->dev, "cp %p "
1797 "has check condition: aborted command: "
1798 "ASC: 0x%x, ASCQ: 0x%x\n",
1799 cp, asc, ascq);
2e311fba 1800 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1801 break;
1802 }
edd16368 1803 /* Must be some other type of check condition */
21b8e4ef 1804 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1805 "unknown type: "
1806 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1807 "Returning result: 0x%x, "
1808 "cmd=[%02x %02x %02x %02x %02x "
807be732 1809 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1810 "%02x %02x %02x %02x %02x]\n",
1811 cp, sense_key, asc, ascq,
1812 cmd->result,
1813 cmd->cmnd[0], cmd->cmnd[1],
1814 cmd->cmnd[2], cmd->cmnd[3],
1815 cmd->cmnd[4], cmd->cmnd[5],
1816 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1817 cmd->cmnd[8], cmd->cmnd[9],
1818 cmd->cmnd[10], cmd->cmnd[11],
1819 cmd->cmnd[12], cmd->cmnd[13],
1820 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1821 break;
1822 }
1823
1824
1825 /* Problem was not a check condition
1826 * Pass it up to the upper layers...
1827 */
1828 if (ei->ScsiStatus) {
1829 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1830 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1831 "Returning result: 0x%x\n",
1832 cp, ei->ScsiStatus,
1833 sense_key, asc, ascq,
1834 cmd->result);
1835 } else { /* scsi status is zero??? How??? */
1836 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1837 "Returning no connection.\n", cp),
1838
1839 /* Ordinarily, this case should never happen,
1840 * but there is a bug in some released firmware
1841 * revisions that allows it to happen if, for
1842 * example, a 4100 backplane loses power and
1843 * the tape drive is in it. We assume that
1844 * it's a fatal error of some kind because we
1845 * can't show that it wasn't. We will make it
1846 * look like selection timeout since that is
1847 * the most common reason for this to occur,
1848 * and it's severe enough.
1849 */
1850
1851 cmd->result = DID_NO_CONNECT << 16;
1852 }
1853 break;
1854
1855 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1856 break;
1857 case CMD_DATA_OVERRUN:
1858 dev_warn(&h->pdev->dev, "cp %p has"
1859 " completed with data overrun "
1860 "reported\n", cp);
1861 break;
1862 case CMD_INVALID: {
1863 /* print_bytes(cp, sizeof(*cp), 1, 0);
1864 print_cmd(cp); */
1865 /* We get CMD_INVALID if you address a non-existent device
1866 * instead of a selection timeout (no response). You will
1867 * see this if you yank out a drive, then try to access it.
1868 * This is kind of a shame because it means that any other
1869 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1870 * missing target. */
1871 cmd->result = DID_NO_CONNECT << 16;
1872 }
1873 break;
1874 case CMD_PROTOCOL_ERR:
256d0eaa 1875 cmd->result = DID_ERROR << 16;
edd16368 1876 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1877 "protocol error\n", cp);
edd16368
SC		 1878 break;
1879 case CMD_HARDWARE_ERR:
1880 cmd->result = DID_ERROR << 16;
1881 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1882 break;
1883 case CMD_CONNECTION_LOST:
1884 cmd->result = DID_ERROR << 16;
1885 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1886 break;
1887 case CMD_ABORTED:
1888 cmd->result = DID_ABORT << 16;
1889 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1890 cp, ei->ScsiStatus);
1891 break;
1892 case CMD_ABORT_FAILED:
1893 cmd->result = DID_ERROR << 16;
1894 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1895 break;
1896 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1897 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1898 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1899 "abort\n", cp);
1900 break;
1901 case CMD_TIMEOUT:
1902 cmd->result = DID_TIME_OUT << 16;
1903 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1904 break;
1d5e2ed0
SC		 1905 case CMD_UNABORTABLE:
1906 cmd->result = DID_ERROR << 16;
1907 dev_warn(&h->pdev->dev, "Command unabortable\n");
1908 break;
283b4a9b
SC		 1909 case CMD_IOACCEL_DISABLED:
1910 /* This only handles the direct pass-through case since RAID
1911 * offload is handled above. Just attempt a retry.
1912 */
1913 cmd->result = DID_SOFT_ERROR << 16;
1914 dev_warn(&h->pdev->dev,
1915 "cp %p had HP SSD Smart Path error\n", cp);
1916 break;
edd16368
SC		 1917 default:
1918 cmd->result = DID_ERROR << 16;
1919 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1920 cp, ei->CommandStatus);
1921 }
edd16368 1922 cmd_free(h, cp);
2cc5bfaf 1923 cmd->scsi_done(cmd);
edd16368
SC		 1924}
1925
edd16368
SC		 1926static void hpsa_pci_unmap(struct pci_dev *pdev,
1927 struct CommandList *c, int sg_used, int data_direction)
1928{
1929 int i;
1930 union u64bit addr64;
1931
1932 for (i = 0; i < sg_used; i++) {
1933 addr64.val32.lower = c->SG[i].Addr.lower;
1934 addr64.val32.upper = c->SG[i].Addr.upper;
1935 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1936 data_direction);
1937 }
1938}
1939
a2dac136 1940static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1941 struct CommandList *cp,
1942 unsigned char *buf,
1943 size_t buflen,
1944 int data_direction)
1945{
01a02ffc 1946 u64 addr64;
edd16368
SC		 1947
1948 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1949 cp->Header.SGList = 0;
1950 cp->Header.SGTotal = 0;
a2dac136 1951 return 0;
edd16368
SC		 1952 }
1953
01a02ffc 1954 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1955 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1956 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1957 cp->Header.SGList = 0;
1958 cp->Header.SGTotal = 0;
a2dac136 1959 return -1;
eceaae18 1960 }
edd16368 1961 cp->SG[0].Addr.lower =
01a02ffc 1962 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1963 cp->SG[0].Addr.upper =
01a02ffc 1964 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1965 cp->SG[0].Len = buflen;
e1d9cbfa 1966 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1967 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1968 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1969 return 0;
edd16368
SC		 1970}
1971
1972static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1973 struct CommandList *c)
1974{
1975 DECLARE_COMPLETION_ONSTACK(wait);
1976
1977 c->waiting = &wait;
1978 enqueue_cmd_and_start_io(h, c);
1979 wait_for_completion(&wait);
1980}
1981
a0c12413
SC		 1982static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1983 struct CommandList *c)
1984{
1985 unsigned long flags;
1986
1987 /* If controller lockup detected, fake a hardware error. */
1988 spin_lock_irqsave(&h->lock, flags);
1989 if (unlikely(h->lockup_detected)) {
1990 spin_unlock_irqrestore(&h->lock, flags);
1991 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1992 } else {
1993 spin_unlock_irqrestore(&h->lock, flags);
1994 hpsa_scsi_do_simple_cmd_core(h, c);
1995 }
1996}
1997
9c2fc160 1998#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1999static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2000 struct CommandList *c, int data_direction)
2001{
9c2fc160 2002 int backoff_time = 10, retry_count = 0;
edd16368
SC		 2003
2004 do {
7630abd0 2005 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 2006 hpsa_scsi_do_simple_cmd_core(h, c);
2007 retry_count++;
9c2fc160
SC		 2008 if (retry_count > 3) {
2009 msleep(backoff_time);
2010 if (backoff_time < 1000)
2011 backoff_time *= 2;
2012 }
852af20a 2013 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2014 check_for_busy(h, c)) &&
2015 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 2016 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
2017}
2018
d1e8beac
SC		 2019static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2020 struct CommandList *c)
edd16368 2021{
d1e8beac
SC		 2022 const u8 *cdb = c->Request.CDB;
2023 const u8 *lun = c->Header.LUN.LunAddrBytes;
2024
2025 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2026 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2027 txt, lun[0], lun[1], lun[2], lun[3],
2028 lun[4], lun[5], lun[6], lun[7],
2029 cdb[0], cdb[1], cdb[2], cdb[3],
2030 cdb[4], cdb[5], cdb[6], cdb[7],
2031 cdb[8], cdb[9], cdb[10], cdb[11],
2032 cdb[12], cdb[13], cdb[14], cdb[15]);
2033}
2034
2035static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2036 struct CommandList *cp)
2037{
2038 const struct ErrorInfo *ei = cp->err_info;
edd16368 2039 struct device *d = &cp->h->pdev->dev;
d1e8beac 2040 const u8 *sd = ei->SenseInfo;
edd16368 2041
edd16368
SC		 2042 switch (ei->CommandStatus) {
2043 case CMD_TARGET_STATUS:
d1e8beac
SC		 2044 hpsa_print_cmd(h, "SCSI status", cp);
2045 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
2046 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
2047 sd[2] & 0x0f, sd[12], sd[13]);
2048 else
2049 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 2050 if (ei->ScsiStatus == 0)
2051 dev_warn(d, "SCSI status is abnormally zero. "
2052 "(probably indicates selection timeout "
2053 "reported incorrectly due to a known "
2054 "firmware bug, circa July, 2001.)\n");
2055 break;
2056 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2057 break;
2058 case CMD_DATA_OVERRUN:
d1e8beac 2059 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2060 break;
2061 case CMD_INVALID: {
2062 /* controller unfortunately reports SCSI passthru's
2063 * to non-existent targets as invalid commands.
2064 */
d1e8beac
SC		 2065 hpsa_print_cmd(h, "invalid command", cp);
2066 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2067 }
2068 break;
2069 case CMD_PROTOCOL_ERR:
d1e8beac 2070 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2071 break;
2072 case CMD_HARDWARE_ERR:
d1e8beac 2073 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2074 break;
2075 case CMD_CONNECTION_LOST:
d1e8beac 2076 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2077 break;
2078 case CMD_ABORTED:
d1e8beac 2079 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2080 break;
2081 case CMD_ABORT_FAILED:
d1e8beac 2082 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2083 break;
2084 case CMD_UNSOLICITED_ABORT:
d1e8beac 2085 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2086 break;
2087 case CMD_TIMEOUT:
d1e8beac 2088 hpsa_print_cmd(h, "timed out", cp);
edd16368 2089 break;
1d5e2ed0 2090 case CMD_UNABORTABLE:
d1e8beac 2091 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2092 break;
edd16368 2093 default:
d1e8beac
SC		 2094 hpsa_print_cmd(h, "unknown status", cp);
2095 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2096 ei->CommandStatus);
2097 }
2098}
2099
2100static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2101 u16 page, unsigned char *buf,
edd16368
SC		 2102 unsigned char bufsize)
2103{
2104 int rc = IO_OK;
2105 struct CommandList *c;
2106 struct ErrorInfo *ei;
2107
2108 c = cmd_special_alloc(h);
2109
2110 if (c == NULL) { /* trouble... */
2111 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 2112 return -ENOMEM;
edd16368
SC		 2113 }
2114
a2dac136
SC		 2115 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2116 page, scsi3addr, TYPE_CMD)) {
2117 rc = -1;
2118 goto out;
2119 }
edd16368
SC		 2120 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2121 ei = c->err_info;
2122 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2123 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2124 rc = -1;
2125 }
a2dac136 2126out:
edd16368
SC		 2127 cmd_special_free(h, c);
2128 return rc;
2129}
2130
bf711ac6
ST		 2131static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2132 u8 reset_type)
edd16368
SC		 2133{
2134 int rc = IO_OK;
2135 struct CommandList *c;
2136 struct ErrorInfo *ei;
2137
2138 c = cmd_special_alloc(h);
2139
2140 if (c == NULL) { /* trouble... */
2141 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2142 return -ENOMEM;
edd16368
SC		 2143 }
2144
a2dac136 2145 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2146 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2147 scsi3addr, TYPE_MSG);
2148 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2149 hpsa_scsi_do_simple_cmd_core(h, c);
2150 /* no unmap needed here because no data xfer. */
2151
2152 ei = c->err_info;
2153 if (ei->CommandStatus != 0) {
d1e8beac 2154 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2155 rc = -1;
2156 }
2157 cmd_special_free(h, c);
2158 return rc;
2159}
2160
2161static void hpsa_get_raid_level(struct ctlr_info *h,
2162 unsigned char *scsi3addr, unsigned char *raid_level)
2163{
2164 int rc;
2165 unsigned char *buf;
2166
2167 *raid_level = RAID_UNKNOWN;
2168 buf = kzalloc(64, GFP_KERNEL);
2169 if (!buf)
2170 return;
b7bb24eb 2171 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2172 if (rc == 0)
2173 *raid_level = buf[8];
2174 if (*raid_level > RAID_UNKNOWN)
2175 *raid_level = RAID_UNKNOWN;
2176 kfree(buf);
2177 return;
2178}
2179
283b4a9b
SC		 2180#define HPSA_MAP_DEBUG
2181#ifdef HPSA_MAP_DEBUG
2182static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2183 struct raid_map_data *map_buff)
2184{
2185 struct raid_map_disk_data *dd = &map_buff->data[0];
2186 int map, row, col;
2187 u16 map_cnt, row_cnt, disks_per_row;
2188
2189 if (rc != 0)
2190 return;
2191
2ba8bfc8
SC		 2192 /* Show details only if debugging has been activated. */
2193 if (h->raid_offload_debug < 2)
2194 return;
2195
283b4a9b
SC		 2196 dev_info(&h->pdev->dev, "structure_size = %u\n",
2197 le32_to_cpu(map_buff->structure_size));
2198 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2199 le32_to_cpu(map_buff->volume_blk_size));
2200 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2201 le64_to_cpu(map_buff->volume_blk_cnt));
2202 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2203 map_buff->phys_blk_shift);
2204 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2205 map_buff->parity_rotation_shift);
2206 dev_info(&h->pdev->dev, "strip_size = %u\n",
2207 le16_to_cpu(map_buff->strip_size));
2208 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2209 le64_to_cpu(map_buff->disk_starting_blk));
2210 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2211 le64_to_cpu(map_buff->disk_blk_cnt));
2212 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2213 le16_to_cpu(map_buff->data_disks_per_row));
2214 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2215 le16_to_cpu(map_buff->metadata_disks_per_row));
2216 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2217 le16_to_cpu(map_buff->row_cnt));
2218 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2219 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2220 dev_info(&h->pdev->dev, "flags = %u\n",
2221 le16_to_cpu(map_buff->flags));
2222 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2223 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2224 else
2225 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2226 dev_info(&h->pdev->dev, "dekindex = %u\n",
2227 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2228
2229 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2230 for (map = 0; map < map_cnt; map++) {
2231 dev_info(&h->pdev->dev, "Map%u:\n", map);
2232 row_cnt = le16_to_cpu(map_buff->row_cnt);
2233 for (row = 0; row < row_cnt; row++) {
2234 dev_info(&h->pdev->dev, " Row%u:\n", row);
2235 disks_per_row =
2236 le16_to_cpu(map_buff->data_disks_per_row);
2237 for (col = 0; col < disks_per_row; col++, dd++)
2238 dev_info(&h->pdev->dev,
2239 " D%02u: h=0x%04x xor=%u,%u\n",
2240 col, dd->ioaccel_handle,
2241 dd->xor_mult[0], dd->xor_mult[1]);
2242 disks_per_row =
2243 le16_to_cpu(map_buff->metadata_disks_per_row);
2244 for (col = 0; col < disks_per_row; col++, dd++)
2245 dev_info(&h->pdev->dev,
2246 " M%02u: h=0x%04x xor=%u,%u\n",
2247 col, dd->ioaccel_handle,
2248 dd->xor_mult[0], dd->xor_mult[1]);
2249 }
2250 }
2251}
2252#else
2253static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2254 __attribute__((unused)) int rc,
2255 __attribute__((unused)) struct raid_map_data *map_buff)
2256{
2257}
2258#endif
2259
2260static int hpsa_get_raid_map(struct ctlr_info *h,
2261 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2262{
2263 int rc = 0;
2264 struct CommandList *c;
2265 struct ErrorInfo *ei;
2266
2267 c = cmd_special_alloc(h);
2268 if (c == NULL) {
2269 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2270 return -ENOMEM;
2271 }
2272 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2273 sizeof(this_device->raid_map), 0,
2274 scsi3addr, TYPE_CMD)) {
2275 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2276 cmd_special_free(h, c);
2277 return -ENOMEM;
2278 }
2279 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2280 ei = c->err_info;
2281 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2282 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2283 cmd_special_free(h, c);
2284 return -1;
2285 }
2286 cmd_special_free(h, c);
2287
2288 /* @todo in the future, dynamically allocate RAID map memory */
2289 if (le32_to_cpu(this_device->raid_map.structure_size) >
2290 sizeof(this_device->raid_map)) {
2291 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2292 rc = -1;
2293 }
2294 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2295 return rc;
2296}
2297
1b70150a
SC		 2298static int hpsa_vpd_page_supported(struct ctlr_info *h,
2299 unsigned char scsi3addr[], u8 page)
2300{
2301 int rc;
2302 int i;
2303 int pages;
2304 unsigned char *buf, bufsize;
2305
2306 buf = kzalloc(256, GFP_KERNEL);
2307 if (!buf)
2308 return 0;
2309
2310 /* Get the size of the page list first */
2311 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2312 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2313 buf, HPSA_VPD_HEADER_SZ);
2314 if (rc != 0)
2315 goto exit_unsupported;
2316 pages = buf[3];
2317 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2318 bufsize = pages + HPSA_VPD_HEADER_SZ;
2319 else
2320 bufsize = 255;
2321
2322 /* Get the whole VPD page list */
2323 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2324 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2325 buf, bufsize);
2326 if (rc != 0)
2327 goto exit_unsupported;
2328
2329 pages = buf[3];
2330 for (i = 1; i <= pages; i++)
2331 if (buf[3 + i] == page)
2332 goto exit_supported;
2333exit_unsupported:
2334 kfree(buf);
2335 return 0;
2336exit_supported:
2337 kfree(buf);
2338 return 1;
2339}
2340
283b4a9b
SC		 2341static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2342 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2343{
2344 int rc;
2345 unsigned char *buf;
2346 u8 ioaccel_status;
2347
2348 this_device->offload_config = 0;
2349 this_device->offload_enabled = 0;
2350
2351 buf = kzalloc(64, GFP_KERNEL);
2352 if (!buf)
2353 return;
1b70150a
SC		 2354 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2355 goto out;
283b4a9b 2356 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2357 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2358 if (rc != 0)
2359 goto out;
2360
2361#define IOACCEL_STATUS_BYTE 4
2362#define OFFLOAD_CONFIGURED_BIT 0x01
2363#define OFFLOAD_ENABLED_BIT 0x02
2364 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2365 this_device->offload_config =
2366 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2367 if (this_device->offload_config) {
2368 this_device->offload_enabled =
2369 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2370 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2371 this_device->offload_enabled = 0;
2372 }
2373out:
2374 kfree(buf);
2375 return;
2376}
2377
edd16368
SC		 2378/* Get the device id from inquiry page 0x83 */
2379static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2380 unsigned char *device_id, int buflen)
2381{
2382 int rc;
2383 unsigned char *buf;
2384
2385 if (buflen > 16)
2386 buflen = 16;
2387 buf = kzalloc(64, GFP_KERNEL);
2388 if (!buf)
2389 return -1;
b7bb24eb 2390 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2391 if (rc == 0)
2392 memcpy(device_id, &buf[8], buflen);
2393 kfree(buf);
2394 return rc != 0;
2395}
2396
2397static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2398 struct ReportLUNdata *buf, int bufsize,
2399 int extended_response)
2400{
2401 int rc = IO_OK;
2402 struct CommandList *c;
2403 unsigned char scsi3addr[8];
2404 struct ErrorInfo *ei;
2405
2406 c = cmd_special_alloc(h);
2407 if (c == NULL) { /* trouble... */
2408 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2409 return -1;
2410 }
e89c0ae7
SC		 2411 /* address the controller */
2412 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2413 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2414 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2415 rc = -1;
2416 goto out;
2417 }
edd16368
SC		 2418 if (extended_response)
2419 c->Request.CDB[1] = extended_response;
2420 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2421 ei = c->err_info;
2422 if (ei->CommandStatus != 0 &&
2423 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2424 hpsa_scsi_interpret_error(h, c);
edd16368 2425 rc = -1;
283b4a9b
SC		 2426 } else {
2427 if (buf->extended_response_flag != extended_response) {
2428 dev_err(&h->pdev->dev,
2429 "report luns requested format %u, got %u\n",
2430 extended_response,
2431 buf->extended_response_flag);
2432 rc = -1;
2433 }
edd16368 2434 }
a2dac136 2435out:
edd16368
SC		 2436 cmd_special_free(h, c);
2437 return rc;
2438}
2439
2440static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2441 struct ReportLUNdata *buf,
2442 int bufsize, int extended_response)
2443{
2444 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2445}
2446
2447static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2448 struct ReportLUNdata *buf, int bufsize)
2449{
2450 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2451}
2452
2453static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2454 int bus, int target, int lun)
2455{
2456 device->bus = bus;
2457 device->target = target;
2458 device->lun = lun;
2459}
2460
9846590e
SC		 2461/* Use VPD inquiry to get details of volume status */
2462static int hpsa_get_volume_status(struct ctlr_info *h,
2463 unsigned char scsi3addr[])
2464{
2465 int rc;
2466 int status;
2467 int size;
2468 unsigned char *buf;
2469
2470 buf = kzalloc(64, GFP_KERNEL);
2471 if (!buf)
2472 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2473
2474 /* Does controller have VPD for logical volume status? */
2475 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) {
2476 dev_warn(&h->pdev->dev, "Logical volume status VPD page is unsupported.\n");
2477 goto exit_failed;
2478 }
2479
2480 /* Get the size of the VPD return buffer */
2481 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2482 buf, HPSA_VPD_HEADER_SZ);
2483 if (rc != 0) {
2484 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2485 goto exit_failed;
2486 }
2487 size = buf[3];
2488
2489 /* Now get the whole VPD buffer */
2490 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2491 buf, size + HPSA_VPD_HEADER_SZ);
2492 if (rc != 0) {
2493 dev_warn(&h->pdev->dev, "Logical volume status VPD inquiry failed.\n");
2494 goto exit_failed;
2495 }
2496 status = buf[4]; /* status byte */
2497
2498 kfree(buf);
2499 return status;
2500exit_failed:
2501 kfree(buf);
2502 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2503}
2504
2505/* Determine offline status of a volume.
2506 * Return either:
2507 * 0 (not offline)
2508 * -1 (offline for unknown reasons)
2509 * # (integer code indicating one of several NOT READY states
2510 * describing why a volume is to be kept offline)
2511 */
2512static unsigned char hpsa_volume_offline(struct ctlr_info *h,
2513 unsigned char scsi3addr[])
2514{
2515 struct CommandList *c;
2516 unsigned char *sense, sense_key, asc, ascq;
2517 int ldstat = 0;
2518 u16 cmd_status;
2519 u8 scsi_status;
2520#define ASC_LUN_NOT_READY 0x04
2521#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2522#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2523
2524 c = cmd_alloc(h);
2525 if (!c)
2526 return 0;
2527 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
2528 hpsa_scsi_do_simple_cmd_core(h, c);
2529 sense = c->err_info->SenseInfo;
2530 sense_key = sense[2];
2531 asc = sense[12];
2532 ascq = sense[13];
2533 cmd_status = c->err_info->CommandStatus;
2534 scsi_status = c->err_info->ScsiStatus;
2535 cmd_free(h, c);
2536 /* Is the volume 'not ready'? */
2537 if (cmd_status != CMD_TARGET_STATUS ||
2538 scsi_status != SAM_STAT_CHECK_CONDITION ||
2539 sense_key != NOT_READY ||
2540 asc != ASC_LUN_NOT_READY) {
2541 return 0;
2542 }
2543
2544 /* Determine the reason for not ready state */
2545 ldstat = hpsa_get_volume_status(h, scsi3addr);
2546
2547 /* Keep volume offline in certain cases: */
2548 switch (ldstat) {
2549 case HPSA_LV_UNDERGOING_ERASE:
2550 case HPSA_LV_UNDERGOING_RPI:
2551 case HPSA_LV_PENDING_RPI:
2552 case HPSA_LV_ENCRYPTED_NO_KEY:
2553 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2554 case HPSA_LV_UNDERGOING_ENCRYPTION:
2555 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2556 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2557 return ldstat;
2558 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2559 /* If VPD status page isn't available,
2560 * use ASC/ASCQ to determine state
2561 */
2562 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2563 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2564 return ldstat;
2565 break;
2566 default:
2567 break;
2568 }
2569 return 0;
2570}
2571
edd16368 2572static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2573 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2574 unsigned char *is_OBDR_device)
edd16368 2575{
0b0e1d6c
SC		 2576
2577#define OBDR_SIG_OFFSET 43
2578#define OBDR_TAPE_SIG "$DR-10"
2579#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2580#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2581
ea6d3bc3 2582 unsigned char *inq_buff;
0b0e1d6c 2583 unsigned char *obdr_sig;
edd16368 2584
ea6d3bc3 2585 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2586 if (!inq_buff)
2587 goto bail_out;
2588
edd16368
SC		 2589 /* Do an inquiry to the device to see what it is. */
2590 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2591 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2592 /* Inquiry failed (msg printed already) */
2593 dev_err(&h->pdev->dev,
2594 "hpsa_update_device_info: inquiry failed\n");
2595 goto bail_out;
2596 }
2597
edd16368
SC		 2598 this_device->devtype = (inq_buff[0] & 0x1f);
2599 memcpy(this_device->scsi3addr, scsi3addr, 8);
2600 memcpy(this_device->vendor, &inq_buff[8],
2601 sizeof(this_device->vendor));
2602 memcpy(this_device->model, &inq_buff[16],
2603 sizeof(this_device->model));
edd16368
SC		 2604 memset(this_device->device_id, 0,
2605 sizeof(this_device->device_id));
2606 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2607 sizeof(this_device->device_id));
2608
2609 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2610 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2611 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2612 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2613 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
9846590e
SC		 2614 this_device->volume_offline =
2615 hpsa_volume_offline(h, scsi3addr);
283b4a9b 2616 } else {
edd16368 2617 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2618 this_device->offload_config = 0;
2619 this_device->offload_enabled = 0;
9846590e 2620 this_device->volume_offline = 0;
283b4a9b 2621 }
edd16368 2622
0b0e1d6c
SC		 2623 if (is_OBDR_device) {
2624 /* See if this is a One-Button-Disaster-Recovery device
2625 * by looking for "$DR-10" at offset 43 in inquiry data.
2626 */
2627 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2628 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2629 strncmp(obdr_sig, OBDR_TAPE_SIG,
2630 OBDR_SIG_LEN) == 0);
2631 }
2632
edd16368
SC		 2633 kfree(inq_buff);
2634 return 0;
2635
2636bail_out:
2637 kfree(inq_buff);
2638 return 1;
2639}
2640
4f4eb9f1 2641static unsigned char *ext_target_model[] = {
edd16368
SC		 2642 "MSA2012",
2643 "MSA2024",
2644 "MSA2312",
2645 "MSA2324",
fda38518 2646 "P2000 G3 SAS",
e06c8e5c 2647 "MSA 2040 SAS",
edd16368
SC		 2648 NULL,
2649};
2650
4f4eb9f1 2651static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2652{
2653 int i;
2654
4f4eb9f1
ST		 2655 for (i = 0; ext_target_model[i]; i++)
2656 if (strncmp(device->model, ext_target_model[i],
2657 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2658 return 1;
2659 return 0;
2660}
2661
2662/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2663 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2664 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2665 * Logical drive target and lun are assigned at this time, but
2666 * physical device lun and target assignment are deferred (assigned
2667 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2668 */
2669static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2670 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2671{
1f310bde
SC		 2672 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2673
2674 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2675 /* physical device, target and lun filled in later */
edd16368 2676 if (is_hba_lunid(lunaddrbytes))
1f310bde 2677 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2678 else
1f310bde
SC		 2679 /* defer target, lun assignment for physical devices */
2680 hpsa_set_bus_target_lun(device, 2, -1, -1);
2681 return;
2682 }
2683 /* It's a logical device */
4f4eb9f1
ST		 2684 if (is_ext_target(h, device)) {
2685 /* external target way, put logicals on bus 1
1f310bde
SC		 2686 * and match target/lun numbers box
2687 * reports, other smart array, bus 0, target 0, match lunid
2688 */
2689 hpsa_set_bus_target_lun(device,
2690 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2691 return;
edd16368 2692 }
1f310bde 2693 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2694}
2695
2696/*
2697 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2698 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2699 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2700 * it for some reason. *tmpdevice is the target we're adding,
2701 * this_device is a pointer into the current element of currentsd[]
2702 * that we're building up in update_scsi_devices(), below.
2703 * lunzerobits is a bitmap that tracks which targets already have a
2704 * lun 0 assigned.
2705 * Returns 1 if an enclosure was added, 0 if not.
2706 */
4f4eb9f1 2707static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2708 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2709 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2710 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2711{
2712 unsigned char scsi3addr[8];
2713
1f310bde 2714 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2715 return 0; /* There is already a lun 0 on this target. */
2716
2717 if (!is_logical_dev_addr_mode(lunaddrbytes))
2718 return 0; /* It's the logical targets that may lack lun 0. */
2719
4f4eb9f1
ST		 2720 if (!is_ext_target(h, tmpdevice))
2721 return 0; /* Only external target devices have this problem. */
edd16368 2722
1f310bde 2723 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2724 return 0;
2725
c4f8a299 2726 memset(scsi3addr, 0, 8);
1f310bde 2727 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2728 if (is_hba_lunid(scsi3addr))
2729 return 0; /* Don't add the RAID controller here. */
2730
339b2b14
SC		 2731 if (is_scsi_rev_5(h))
2732 return 0; /* p1210m doesn't need to do this. */
2733
4f4eb9f1 2734 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2735 dev_warn(&h->pdev->dev, "Maximum number of external "
2736 "target devices exceeded. Check your hardware "
edd16368
SC		 2737 "configuration.");
2738 return 0;
2739 }
2740
0b0e1d6c 2741 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2742 return 0;
4f4eb9f1 2743 (*n_ext_target_devs)++;
1f310bde
SC		 2744 hpsa_set_bus_target_lun(this_device,
2745 tmpdevice->bus, tmpdevice->target, 0);
2746 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2747 return 1;
2748}
2749
54b6e9e9
ST		 2750/*
2751 * Get address of physical disk used for an ioaccel2 mode command:
2752 * 1. Extract ioaccel2 handle from the command.
2753 * 2. Find a matching ioaccel2 handle from list of physical disks.
2754 * 3. Return:
2755 * 1 and set scsi3addr to address of matching physical
2756 * 0 if no matching physical disk was found.
2757 */
2758static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2759 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2760{
2761 struct ReportExtendedLUNdata *physicals = NULL;
2762 int responsesize = 24; /* size of physical extended response */
2763 int extended = 2; /* flag forces reporting 'other dev info'. */
2764 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2765 u32 nphysicals = 0; /* number of reported physical devs */
2766 int found = 0; /* found match (1) or not (0) */
2767 u32 find; /* handle we need to match */
2768 int i;
2769 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2770 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2771 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2772 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2773 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2774
2775 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2776 return 0; /* no match */
2777
2778 /* point to the ioaccel2 device handle */
2779 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2780 if (c2a == NULL)
2781 return 0; /* no match */
2782
2783 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2784 if (scmd == NULL)
2785 return 0; /* no match */
2786
2787 d = scmd->device->hostdata;
2788 if (d == NULL)
2789 return 0; /* no match */
2790
2791 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2792 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2793 find = c2a->scsi_nexus;
2794
2ba8bfc8
SC		 2795 if (h->raid_offload_debug > 0)
2796 dev_info(&h->pdev->dev,
2797 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2798 __func__, scsi_nexus,
2799 d->device_id[0], d->device_id[1], d->device_id[2],
2800 d->device_id[3], d->device_id[4], d->device_id[5],
2801 d->device_id[6], d->device_id[7], d->device_id[8],
2802 d->device_id[9], d->device_id[10], d->device_id[11],
2803 d->device_id[12], d->device_id[13], d->device_id[14],
2804 d->device_id[15]);
2805
54b6e9e9
ST		 2806 /* Get the list of physical devices */
2807 physicals = kzalloc(reportsize, GFP_KERNEL);
2808 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2809 reportsize, extended)) {
2810 dev_err(&h->pdev->dev,
2811 "Can't lookup %s device handle: report physical LUNs failed.\n",
2812 "HP SSD Smart Path");
2813 kfree(physicals);
2814 return 0;
2815 }
2816 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2817 responsesize;
2818
2819
2820 /* find ioaccel2 handle in list of physicals: */
2821 for (i = 0; i < nphysicals; i++) {
2822 /* handle is in bytes 28-31 of each lun */
2823 if (memcmp(&((struct ReportExtendedLUNdata *)
2824 physicals)->LUN[i][20], &find, 4) != 0) {
2825 continue; /* didn't match */
2826 }
2827 found = 1;
2828 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2829 physicals)->LUN[i][0], 8);
2ba8bfc8
SC		 2830 if (h->raid_offload_debug > 0)
2831 dev_info(&h->pdev->dev,
2832 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2833 __func__, find,
2834 ((struct ReportExtendedLUNdata *)
2835 physicals)->LUN[i][20],
2836 scsi3addr[0], scsi3addr[1], scsi3addr[2],
2837 scsi3addr[3], scsi3addr[4], scsi3addr[5],
2838 scsi3addr[6], scsi3addr[7]);
54b6e9e9
ST		 2839 break; /* found it */
2840 }
2841
2842 kfree(physicals);
2843 if (found)
2844 return 1;
2845 else
2846 return 0;
2847
2848}
edd16368
SC		 2849/*
2850 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2851 * logdev. The number of luns in physdev and logdev are returned in
2852 * *nphysicals and *nlogicals, respectively.
2853 * Returns 0 on success, -1 otherwise.
2854 */
2855static int hpsa_gather_lun_info(struct ctlr_info *h,
2856 int reportlunsize,
283b4a9b 2857 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2858 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2859{
283b4a9b
SC		 2860 int physical_entry_size = 8;
2861
2862 *physical_mode = 0;
2863
2864 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2865 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2866 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2867 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2868 physical_entry_size = 24;
2869 }
a93aa1fe 2870 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2871 *physical_mode)) {
edd16368
SC		 2872 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2873 return -1;
2874 }
283b4a9b
SC		 2875 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2876 physical_entry_size;
edd16368
SC		 2877 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2878 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2879 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2880 *nphysicals - HPSA_MAX_PHYS_LUN);
2881 *nphysicals = HPSA_MAX_PHYS_LUN;
2882 }
2883 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2884 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2885 return -1;
2886 }
6df1e954 2887 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2888 /* Reject Logicals in excess of our max capability. */
2889 if (*nlogicals > HPSA_MAX_LUN) {
2890 dev_warn(&h->pdev->dev,
2891 "maximum logical LUNs (%d) exceeded. "
2892 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2893 *nlogicals - HPSA_MAX_LUN);
2894 *nlogicals = HPSA_MAX_LUN;
2895 }
2896 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2897 dev_warn(&h->pdev->dev,
2898 "maximum logical + physical LUNs (%d) exceeded. "
2899 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2900 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2901 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2902 }
2903 return 0;
2904}
2905
339b2b14 2906u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2907 int nphysicals, int nlogicals,
2908 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2909 struct ReportLUNdata *logdev_list)
2910{
2911 /* Helper function, figure out where the LUN ID info is coming from
2912 * given index i, lists of physical and logical devices, where in
2913 * the list the raid controller is supposed to appear (first or last)
2914 */
2915
2916 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2917 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2918
2919 if (i == raid_ctlr_position)
2920 return RAID_CTLR_LUNID;
2921
2922 if (i < logicals_start)
2923 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2924
2925 if (i < last_device)
2926 return &logdev_list->LUN[i - nphysicals -
2927 (raid_ctlr_position == 0)][0];
2928 BUG();
2929 return NULL;
2930}
2931
edd16368
SC		 2932static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2933{
2934 /* the idea here is we could get notified
2935 * that some devices have changed, so we do a report
2936 * physical luns and report logical luns cmd, and adjust
2937 * our list of devices accordingly.
2938 *
2939 * The scsi3addr's of devices won't change so long as the
2940 * adapter is not reset. That means we can rescan and
2941 * tell which devices we already know about, vs. new
2942 * devices, vs. disappearing devices.
2943 */
a93aa1fe 2944 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2945 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2946 u32 nphysicals = 0;
2947 u32 nlogicals = 0;
283b4a9b 2948 int physical_mode = 0;
01a02ffc 2949 u32 ndev_allocated = 0;
edd16368
SC		 2950 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2951 int ncurrent = 0;
283b4a9b 2952 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2953 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2954 int raid_ctlr_position;
aca4a520 2955 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2956
cfe5badc 2957 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2958 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2959 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2960 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2961
0b0e1d6c 2962 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2963 dev_err(&h->pdev->dev, "out of memory\n");
2964 goto out;
2965 }
2966 memset(lunzerobits, 0, sizeof(lunzerobits));
2967
a93aa1fe
MG		 2968 if (hpsa_gather_lun_info(h, reportlunsize,
2969 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2970 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2971 goto out;
2972
aca4a520
ST		 2973 /* We might see up to the maximum number of logical and physical disks
2974 * plus external target devices, and a device for the local RAID
2975 * controller.
edd16368 2976 */
aca4a520 2977 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2978
2979 /* Allocate the per device structures */
2980 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2981 if (i >= HPSA_MAX_DEVICES) {
2982 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2983 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2984 ndevs_to_allocate - HPSA_MAX_DEVICES);
2985 break;
2986 }
2987
edd16368
SC		 2988 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2989 if (!currentsd[i]) {
2990 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2991 __FILE__, __LINE__);
2992 goto out;
2993 }
2994 ndev_allocated++;
2995 }
2996
339b2b14
SC		 2997 if (unlikely(is_scsi_rev_5(h)))
2998 raid_ctlr_position = 0;
2999 else
3000 raid_ctlr_position = nphysicals + nlogicals;
3001
edd16368 3002 /* adjust our table of devices */
4f4eb9f1 3003 n_ext_target_devs = 0;
edd16368 3004 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3005 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3006
3007 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3008 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3009 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 3010 /* skip masked physical devices. */
339b2b14
SC		 3011 if (lunaddrbytes[3] & 0xC0 &&
3012 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 3013 continue;
3014
3015 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3016 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3017 &is_OBDR))
edd16368 3018 continue; /* skip it if we can't talk to it. */
1f310bde 3019 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 3020 this_device = currentsd[ncurrent];
3021
3022 /*
4f4eb9f1 3023 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3024 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3025 * is nonetheless an enclosure device there. We have to
3026 * present that otherwise linux won't find anything if
3027 * there is no lun 0.
3028 */
4f4eb9f1 3029 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3030 lunaddrbytes, lunzerobits,
4f4eb9f1 3031 &n_ext_target_devs)) {
edd16368
SC		 3032 ncurrent++;
3033 this_device = currentsd[ncurrent];
3034 }
3035
3036 *this_device = *tmpdevice;
edd16368
SC		 3037
3038 switch (this_device->devtype) {
0b0e1d6c 3039 case TYPE_ROM:
edd16368
SC		 3040 /* We don't *really* support actual CD-ROM devices,
3041 * just "One Button Disaster Recovery" tape drive
3042 * which temporarily pretends to be a CD-ROM drive.
3043 * So we check that the device is really an OBDR tape
3044 * device by checking for "$DR-10" in bytes 43-48 of
3045 * the inquiry data.
3046 */
0b0e1d6c
SC		 3047 if (is_OBDR)
3048 ncurrent++;
edd16368
SC		 3049 break;
3050 case TYPE_DISK:
283b4a9b
SC		 3051 if (i >= nphysicals) {
3052 ncurrent++;
edd16368 3053 break;
283b4a9b
SC		 3054 }
3055 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
3056 memcpy(&this_device->ioaccel_handle,
3057 &lunaddrbytes[20],
3058 sizeof(this_device->ioaccel_handle));
3059 ncurrent++;
3060 }
edd16368
SC		 3061 break;
3062 case TYPE_TAPE:
3063 case TYPE_MEDIUM_CHANGER:
3064 ncurrent++;
3065 break;
3066 case TYPE_RAID:
3067 /* Only present the Smartarray HBA as a RAID controller.
3068 * If it's a RAID controller other than the HBA itself
3069 * (an external RAID controller, MSA500 or similar)
3070 * don't present it.
3071 */
3072 if (!is_hba_lunid(lunaddrbytes))
3073 break;
3074 ncurrent++;
3075 break;
3076 default:
3077 break;
3078 }
cfe5badc 3079 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3080 break;
3081 }
3082 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3083out:
3084 kfree(tmpdevice);
3085 for (i = 0; i < ndev_allocated; i++)
3086 kfree(currentsd[i]);
3087 kfree(currentsd);
edd16368
SC		 3088 kfree(physdev_list);
3089 kfree(logdev_list);
edd16368
SC		 3090}
3091
3092/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
3093 * dma mapping and fills in the scatter gather entries of the
3094 * hpsa command, cp.
3095 */
33a2ffce 3096static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3097 struct CommandList *cp,
3098 struct scsi_cmnd *cmd)
3099{
3100 unsigned int len;
3101 struct scatterlist *sg;
01a02ffc 3102 u64 addr64;
33a2ffce
SC		 3103 int use_sg, i, sg_index, chained;
3104 struct SGDescriptor *curr_sg;
edd16368 3105
33a2ffce 3106 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3107
3108 use_sg = scsi_dma_map(cmd);
3109 if (use_sg < 0)
3110 return use_sg;
3111
3112 if (!use_sg)
3113 goto sglist_finished;
3114
33a2ffce
SC		 3115 curr_sg = cp->SG;
3116 chained = 0;
3117 sg_index = 0;
edd16368 3118 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3119 if (i == h->max_cmd_sg_entries - 1 &&
3120 use_sg > h->max_cmd_sg_entries) {
3121 chained = 1;
3122 curr_sg = h->cmd_sg_list[cp->cmdindex];
3123 sg_index = 0;
3124 }
01a02ffc 3125 addr64 = (u64) sg_dma_address(sg);
edd16368 3126 len = sg_dma_len(sg);
33a2ffce
SC		 3127 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3128 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3129 curr_sg->Len = len;
e1d9cbfa 3130 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 3131 curr_sg++;
3132 }
3133
3134 if (use_sg + chained > h->maxSG)
3135 h->maxSG = use_sg + chained;
3136
3137 if (chained) {
3138 cp->Header.SGList = h->max_cmd_sg_entries;
3139 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 3140 if (hpsa_map_sg_chain_block(h, cp)) {
3141 scsi_dma_unmap(cmd);
3142 return -1;
3143 }
33a2ffce 3144 return 0;
edd16368
SC		 3145 }
3146
3147sglist_finished:
3148
01a02ffc
SC		 3149 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
3150 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 3151 return 0;
3152}
3153
283b4a9b
SC		 3154#define IO_ACCEL_INELIGIBLE (1)
3155static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3156{
3157 int is_write = 0;
3158 u32 block;
3159 u32 block_cnt;
3160
3161 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3162 switch (cdb[0]) {
3163 case WRITE_6:
3164 case WRITE_12:
3165 is_write = 1;
3166 case READ_6:
3167 case READ_12:
3168 if (*cdb_len == 6) {
3169 block = (((u32) cdb[2]) << 8) | cdb[3];
3170 block_cnt = cdb[4];
3171 } else {
3172 BUG_ON(*cdb_len != 12);
3173 block = (((u32) cdb[2]) << 24) |
3174 (((u32) cdb[3]) << 16) |
3175 (((u32) cdb[4]) << 8) |
3176 cdb[5];
3177 block_cnt =
3178 (((u32) cdb[6]) << 24) |
3179 (((u32) cdb[7]) << 16) |
3180 (((u32) cdb[8]) << 8) |
3181 cdb[9];
3182 }
3183 if (block_cnt > 0xffff)
3184 return IO_ACCEL_INELIGIBLE;
3185
3186 cdb[0] = is_write ? WRITE_10 : READ_10;
3187 cdb[1] = 0;
3188 cdb[2] = (u8) (block >> 24);
3189 cdb[3] = (u8) (block >> 16);
3190 cdb[4] = (u8) (block >> 8);
3191 cdb[5] = (u8) (block);
3192 cdb[6] = 0;
3193 cdb[7] = (u8) (block_cnt >> 8);
3194 cdb[8] = (u8) (block_cnt);
3195 cdb[9] = 0;
3196 *cdb_len = 10;
3197 break;
3198 }
3199 return 0;
3200}
3201
c349775e 3202static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 3203 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3204 u8 *scsi3addr)
e1f7de0c
MG		 3205{
3206 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3207 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3208 unsigned int len;
3209 unsigned int total_len = 0;
3210 struct scatterlist *sg;
3211 u64 addr64;
3212 int use_sg, i;
3213 struct SGDescriptor *curr_sg;
3214 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3215
283b4a9b
SC		 3216 /* TODO: implement chaining support */
3217 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3218 return IO_ACCEL_INELIGIBLE;
3219
e1f7de0c
MG		 3220 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3221
283b4a9b
SC		 3222 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3223 return IO_ACCEL_INELIGIBLE;
3224
e1f7de0c
MG		 3225 c->cmd_type = CMD_IOACCEL1;
3226
3227 /* Adjust the DMA address to point to the accelerated command buffer */
3228 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3229 (c->cmdindex * sizeof(*cp));
3230 BUG_ON(c->busaddr & 0x0000007F);
3231
3232 use_sg = scsi_dma_map(cmd);
3233 if (use_sg < 0)
3234 return use_sg;
3235
3236 if (use_sg) {
3237 curr_sg = cp->SG;
3238 scsi_for_each_sg(cmd, sg, use_sg, i) {
3239 addr64 = (u64) sg_dma_address(sg);
3240 len = sg_dma_len(sg);
3241 total_len += len;
3242 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
3243 curr_sg->Addr.upper =
3244 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
3245 curr_sg->Len = len;
3246
3247 if (i == (scsi_sg_count(cmd) - 1))
3248 curr_sg->Ext = HPSA_SG_LAST;
3249 else
3250 curr_sg->Ext = 0; /* we are not chaining */
3251 curr_sg++;
3252 }
3253
3254 switch (cmd->sc_data_direction) {
3255 case DMA_TO_DEVICE:
3256 control |= IOACCEL1_CONTROL_DATA_OUT;
3257 break;
3258 case DMA_FROM_DEVICE:
3259 control |= IOACCEL1_CONTROL_DATA_IN;
3260 break;
3261 case DMA_NONE:
3262 control |= IOACCEL1_CONTROL_NODATAXFER;
3263 break;
3264 default:
3265 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3266 cmd->sc_data_direction);
3267 BUG();
3268 break;
3269 }
3270 } else {
3271 control |= IOACCEL1_CONTROL_NODATAXFER;
3272 }
3273
c349775e 3274 c->Header.SGList = use_sg;
e1f7de0c 3275 /* Fill out the command structure to submit */
283b4a9b 3276 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3277 cp->transfer_len = total_len;
3278 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3279 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3280 cp->control = control;
283b4a9b
SC		 3281 memcpy(cp->CDB, cdb, cdb_len);
3282 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3283 /* Tag was already set at init time. */
283b4a9b 3284 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3285 return 0;
3286}
edd16368 3287
283b4a9b
SC		 3288/*
3289 * Queue a command directly to a device behind the controller using the
3290 * I/O accelerator path.
3291 */
3292static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3293 struct CommandList *c)
3294{
3295 struct scsi_cmnd *cmd = c->scsi_cmd;
3296 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3297
3298 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3299 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3300}
3301
dd0e19f3
ST		 3302/*
3303 * Set encryption parameters for the ioaccel2 request
3304 */
3305static void set_encrypt_ioaccel2(struct ctlr_info *h,
3306 struct CommandList *c, struct io_accel2_cmd *cp)
3307{
3308 struct scsi_cmnd *cmd = c->scsi_cmd;
3309 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3310 struct raid_map_data *map = &dev->raid_map;
3311 u64 first_block;
3312
3313 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3314
3315 /* Are we doing encryption on this device */
3316 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3317 return;
3318 /* Set the data encryption key index. */
3319 cp->dekindex = map->dekindex;
3320
3321 /* Set the encryption enable flag, encoded into direction field. */
3322 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3323
3324 /* Set encryption tweak values based on logical block address
3325 * If block size is 512, tweak value is LBA.
3326 * For other block sizes, tweak is (LBA * block size)/ 512)
3327 */
3328 switch (cmd->cmnd[0]) {
3329 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3330 case WRITE_6:
3331 case READ_6:
3332 if (map->volume_blk_size == 512) {
3333 cp->tweak_lower =
3334 (((u32) cmd->cmnd[2]) << 8) |
3335 cmd->cmnd[3];
3336 cp->tweak_upper = 0;
3337 } else {
3338 first_block =
3339 (((u64) cmd->cmnd[2]) << 8) |
3340 cmd->cmnd[3];
3341 first_block = (first_block * map->volume_blk_size)/512;
3342 cp->tweak_lower = (u32)first_block;
3343 cp->tweak_upper = (u32)(first_block >> 32);
3344 }
3345 break;
3346 case WRITE_10:
3347 case READ_10:
3348 if (map->volume_blk_size == 512) {
3349 cp->tweak_lower =
3350 (((u32) cmd->cmnd[2]) << 24) |
3351 (((u32) cmd->cmnd[3]) << 16) |
3352 (((u32) cmd->cmnd[4]) << 8) |
3353 cmd->cmnd[5];
3354 cp->tweak_upper = 0;
3355 } else {
3356 first_block =
3357 (((u64) cmd->cmnd[2]) << 24) |
3358 (((u64) cmd->cmnd[3]) << 16) |
3359 (((u64) cmd->cmnd[4]) << 8) |
3360 cmd->cmnd[5];
3361 first_block = (first_block * map->volume_blk_size)/512;
3362 cp->tweak_lower = (u32)first_block;
3363 cp->tweak_upper = (u32)(first_block >> 32);
3364 }
3365 break;
3366 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3367 case WRITE_12:
3368 case READ_12:
3369 if (map->volume_blk_size == 512) {
3370 cp->tweak_lower =
3371 (((u32) cmd->cmnd[2]) << 24) |
3372 (((u32) cmd->cmnd[3]) << 16) |
3373 (((u32) cmd->cmnd[4]) << 8) |
3374 cmd->cmnd[5];
3375 cp->tweak_upper = 0;
3376 } else {
3377 first_block =
3378 (((u64) cmd->cmnd[2]) << 24) |
3379 (((u64) cmd->cmnd[3]) << 16) |
3380 (((u64) cmd->cmnd[4]) << 8) |
3381 cmd->cmnd[5];
3382 first_block = (first_block * map->volume_blk_size)/512;
3383 cp->tweak_lower = (u32)first_block;
3384 cp->tweak_upper = (u32)(first_block >> 32);
3385 }
3386 break;
3387 case WRITE_16:
3388 case READ_16:
3389 if (map->volume_blk_size == 512) {
3390 cp->tweak_lower =
3391 (((u32) cmd->cmnd[6]) << 24) |
3392 (((u32) cmd->cmnd[7]) << 16) |
3393 (((u32) cmd->cmnd[8]) << 8) |
3394 cmd->cmnd[9];
3395 cp->tweak_upper =
3396 (((u32) cmd->cmnd[2]) << 24) |
3397 (((u32) cmd->cmnd[3]) << 16) |
3398 (((u32) cmd->cmnd[4]) << 8) |
3399 cmd->cmnd[5];
3400 } else {
3401 first_block =
3402 (((u64) cmd->cmnd[2]) << 56) |
3403 (((u64) cmd->cmnd[3]) << 48) |
3404 (((u64) cmd->cmnd[4]) << 40) |
3405 (((u64) cmd->cmnd[5]) << 32) |
3406 (((u64) cmd->cmnd[6]) << 24) |
3407 (((u64) cmd->cmnd[7]) << 16) |
3408 (((u64) cmd->cmnd[8]) << 8) |
3409 cmd->cmnd[9];
3410 first_block = (first_block * map->volume_blk_size)/512;
3411 cp->tweak_lower = (u32)first_block;
3412 cp->tweak_upper = (u32)(first_block >> 32);
3413 }
3414 break;
3415 default:
3416 dev_err(&h->pdev->dev,
3417 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3418 __func__);
3419 BUG();
3420 break;
3421 }
3422}
3423
c349775e
ST		 3424static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3425 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3426 u8 *scsi3addr)
3427{
3428 struct scsi_cmnd *cmd = c->scsi_cmd;
3429 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3430 struct ioaccel2_sg_element *curr_sg;
3431 int use_sg, i;
3432 struct scatterlist *sg;
3433 u64 addr64;
3434 u32 len;
3435 u32 total_len = 0;
3436
3437 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3438 return IO_ACCEL_INELIGIBLE;
3439
3440 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3441 return IO_ACCEL_INELIGIBLE;
3442 c->cmd_type = CMD_IOACCEL2;
3443 /* Adjust the DMA address to point to the accelerated command buffer */
3444 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3445 (c->cmdindex * sizeof(*cp));
3446 BUG_ON(c->busaddr & 0x0000007F);
3447
3448 memset(cp, 0, sizeof(*cp));
3449 cp->IU_type = IOACCEL2_IU_TYPE;
3450
3451 use_sg = scsi_dma_map(cmd);
3452 if (use_sg < 0)
3453 return use_sg;
3454
3455 if (use_sg) {
3456 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3457 curr_sg = cp->sg;
3458 scsi_for_each_sg(cmd, sg, use_sg, i) {
3459 addr64 = (u64) sg_dma_address(sg);
3460 len = sg_dma_len(sg);
3461 total_len += len;
3462 curr_sg->address = cpu_to_le64(addr64);
3463 curr_sg->length = cpu_to_le32(len);
3464 curr_sg->reserved[0] = 0;
3465 curr_sg->reserved[1] = 0;
3466 curr_sg->reserved[2] = 0;
3467 curr_sg->chain_indicator = 0;
3468 curr_sg++;
3469 }
3470
3471 switch (cmd->sc_data_direction) {
3472 case DMA_TO_DEVICE:
dd0e19f3
ST		 3473 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3474 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3475 break;
3476 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3477 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3478 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3479 break;
3480 case DMA_NONE:
dd0e19f3
ST		 3481 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3482 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3483 break;
3484 default:
3485 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3486 cmd->sc_data_direction);
3487 BUG();
3488 break;
3489 }
3490 } else {
dd0e19f3
ST		 3491 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3492 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3493 }
dd0e19f3
ST		 3494
3495 /* Set encryption parameters, if necessary */
3496 set_encrypt_ioaccel2(h, c, cp);
3497
c349775e 3498 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3499 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3500 DIRECT_LOOKUP_BIT;
3501 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
3502 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
3503 cp->cmd_priority_task_attr = 0;
3504
3505 /* fill in sg elements */
3506 cp->sg_count = (u8) use_sg;
3507
3508 cp->data_len = cpu_to_le32(total_len);
3509 cp->err_ptr = cpu_to_le64(c->busaddr +
3510 offsetof(struct io_accel2_cmd, error_data));
3511 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3512
3513 enqueue_cmd_and_start_io(h, c);
3514 return 0;
3515}
3516
3517/*
3518 * Queue a command to the correct I/O accelerator path.
3519 */
3520static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3521 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3522 u8 *scsi3addr)
3523{
3524 if (h->transMethod & CFGTBL_Trans_io_accel1)
3525 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3526 cdb, cdb_len, scsi3addr);
3527 else
3528 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3529 cdb, cdb_len, scsi3addr);
3530}
3531
6b80b18f
ST		 3532static void raid_map_helper(struct raid_map_data *map,
3533 int offload_to_mirror, u32 *map_index, u32 *current_group)
3534{
3535 if (offload_to_mirror == 0) {
3536 /* use physical disk in the first mirrored group. */
3537 *map_index %= map->data_disks_per_row;
3538 return;
3539 }
3540 do {
3541 /* determine mirror group that *map_index indicates */
3542 *current_group = *map_index / map->data_disks_per_row;
3543 if (offload_to_mirror == *current_group)
3544 continue;
3545 if (*current_group < (map->layout_map_count - 1)) {
3546 /* select map index from next group */
3547 *map_index += map->data_disks_per_row;
3548 (*current_group)++;
3549 } else {
3550 /* select map index from first group */
3551 *map_index %= map->data_disks_per_row;
3552 *current_group = 0;
3553 }
3554 } while (offload_to_mirror != *current_group);
3555}
3556
283b4a9b
SC		 3557/*
3558 * Attempt to perform offload RAID mapping for a logical volume I/O.
3559 */
3560static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3561 struct CommandList *c)
3562{
3563 struct scsi_cmnd *cmd = c->scsi_cmd;
3564 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3565 struct raid_map_data *map = &dev->raid_map;
3566 struct raid_map_disk_data *dd = &map->data[0];
3567 int is_write = 0;
3568 u32 map_index;
3569 u64 first_block, last_block;
3570 u32 block_cnt;
3571 u32 blocks_per_row;
3572 u64 first_row, last_row;
3573 u32 first_row_offset, last_row_offset;
3574 u32 first_column, last_column;
6b80b18f
ST		 3575 u64 r0_first_row, r0_last_row;
3576 u32 r5or6_blocks_per_row;
3577 u64 r5or6_first_row, r5or6_last_row;
3578 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3579 u32 r5or6_first_column, r5or6_last_column;
3580 u32 total_disks_per_row;
3581 u32 stripesize;
3582 u32 first_group, last_group, current_group;
283b4a9b
SC		 3583 u32 map_row;
3584 u32 disk_handle;
3585 u64 disk_block;
3586 u32 disk_block_cnt;
3587 u8 cdb[16];
3588 u8 cdb_len;
3589#if BITS_PER_LONG == 32
3590 u64 tmpdiv;
3591#endif
6b80b18f 3592 int offload_to_mirror;
283b4a9b
SC		 3593
3594 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3595
3596 /* check for valid opcode, get LBA and block count */
3597 switch (cmd->cmnd[0]) {
3598 case WRITE_6:
3599 is_write = 1;
3600 case READ_6:
3601 first_block =
3602 (((u64) cmd->cmnd[2]) << 8) |
3603 cmd->cmnd[3];
3604 block_cnt = cmd->cmnd[4];
3605 break;
3606 case WRITE_10:
3607 is_write = 1;
3608 case READ_10:
3609 first_block =
3610 (((u64) cmd->cmnd[2]) << 24) |
3611 (((u64) cmd->cmnd[3]) << 16) |
3612 (((u64) cmd->cmnd[4]) << 8) |
3613 cmd->cmnd[5];
3614 block_cnt =
3615 (((u32) cmd->cmnd[7]) << 8) |
3616 cmd->cmnd[8];
3617 break;
3618 case WRITE_12:
3619 is_write = 1;
3620 case READ_12:
3621 first_block =
3622 (((u64) cmd->cmnd[2]) << 24) |
3623 (((u64) cmd->cmnd[3]) << 16) |
3624 (((u64) cmd->cmnd[4]) << 8) |
3625 cmd->cmnd[5];
3626 block_cnt =
3627 (((u32) cmd->cmnd[6]) << 24) |
3628 (((u32) cmd->cmnd[7]) << 16) |
3629 (((u32) cmd->cmnd[8]) << 8) |
3630 cmd->cmnd[9];
3631 break;
3632 case WRITE_16:
3633 is_write = 1;
3634 case READ_16:
3635 first_block =
3636 (((u64) cmd->cmnd[2]) << 56) |
3637 (((u64) cmd->cmnd[3]) << 48) |
3638 (((u64) cmd->cmnd[4]) << 40) |
3639 (((u64) cmd->cmnd[5]) << 32) |
3640 (((u64) cmd->cmnd[6]) << 24) |
3641 (((u64) cmd->cmnd[7]) << 16) |
3642 (((u64) cmd->cmnd[8]) << 8) |
3643 cmd->cmnd[9];
3644 block_cnt =
3645 (((u32) cmd->cmnd[10]) << 24) |
3646 (((u32) cmd->cmnd[11]) << 16) |
3647 (((u32) cmd->cmnd[12]) << 8) |
3648 cmd->cmnd[13];
3649 break;
3650 default:
3651 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3652 }
3653 BUG_ON(block_cnt == 0);
3654 last_block = first_block + block_cnt - 1;
3655
3656 /* check for write to non-RAID-0 */
3657 if (is_write && dev->raid_level != 0)
3658 return IO_ACCEL_INELIGIBLE;
3659
3660 /* check for invalid block or wraparound */
3661 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3662 return IO_ACCEL_INELIGIBLE;
3663
3664 /* calculate stripe information for the request */
3665 blocks_per_row = map->data_disks_per_row * map->strip_size;
3666#if BITS_PER_LONG == 32
3667 tmpdiv = first_block;
3668 (void) do_div(tmpdiv, blocks_per_row);
3669 first_row = tmpdiv;
3670 tmpdiv = last_block;
3671 (void) do_div(tmpdiv, blocks_per_row);
3672 last_row = tmpdiv;
3673 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3674 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3675 tmpdiv = first_row_offset;
3676 (void) do_div(tmpdiv, map->strip_size);
3677 first_column = tmpdiv;
3678 tmpdiv = last_row_offset;
3679 (void) do_div(tmpdiv, map->strip_size);
3680 last_column = tmpdiv;
3681#else
3682 first_row = first_block / blocks_per_row;
3683 last_row = last_block / blocks_per_row;
3684 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3685 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3686 first_column = first_row_offset / map->strip_size;
3687 last_column = last_row_offset / map->strip_size;
3688#endif
3689
3690 /* if this isn't a single row/column then give to the controller */
3691 if ((first_row != last_row) || (first_column != last_column))
3692 return IO_ACCEL_INELIGIBLE;
3693
3694 /* proceeding with driver mapping */
6b80b18f
ST		 3695 total_disks_per_row = map->data_disks_per_row +
3696 map->metadata_disks_per_row;
283b4a9b
SC		 3697 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3698 map->row_cnt;
6b80b18f
ST		 3699 map_index = (map_row * total_disks_per_row) + first_column;
3700
3701 switch (dev->raid_level) {
3702 case HPSA_RAID_0:
3703 break; /* nothing special to do */
3704 case HPSA_RAID_1:
3705 /* Handles load balance across RAID 1 members.
3706 * (2-drive R1 and R10 with even # of drives.)
3707 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3708 */
6b80b18f 3709 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3710 if (dev->offload_to_mirror)
3711 map_index += map->data_disks_per_row;
3712 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3713 break;
3714 case HPSA_RAID_ADM:
3715 /* Handles N-way mirrors (R1-ADM)
3716 * and R10 with # of drives divisible by 3.)
3717 */
3718 BUG_ON(map->layout_map_count != 3);
3719
3720 offload_to_mirror = dev->offload_to_mirror;
3721 raid_map_helper(map, offload_to_mirror,
3722 &map_index, &current_group);
3723 /* set mirror group to use next time */
3724 offload_to_mirror =
3725 (offload_to_mirror >= map->layout_map_count - 1)
3726 ? 0 : offload_to_mirror + 1;
3727 /* FIXME: remove after debug/dev */
3728 BUG_ON(offload_to_mirror >= map->layout_map_count);
3729 dev_warn(&h->pdev->dev,
3730 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3731 map_index, offload_to_mirror);
3732 dev->offload_to_mirror = offload_to_mirror;
3733 /* Avoid direct use of dev->offload_to_mirror within this
3734 * function since multiple threads might simultaneously
3735 * increment it beyond the range of dev->layout_map_count -1.
3736 */
3737 break;
3738 case HPSA_RAID_5:
3739 case HPSA_RAID_6:
3740 if (map->layout_map_count <= 1)
3741 break;
3742
3743 /* Verify first and last block are in same RAID group */
3744 r5or6_blocks_per_row =
3745 map->strip_size * map->data_disks_per_row;
3746 BUG_ON(r5or6_blocks_per_row == 0);
3747 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3748#if BITS_PER_LONG == 32
3749 tmpdiv = first_block;
3750 first_group = do_div(tmpdiv, stripesize);
3751 tmpdiv = first_group;
3752 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3753 first_group = tmpdiv;
3754 tmpdiv = last_block;
3755 last_group = do_div(tmpdiv, stripesize);
3756 tmpdiv = last_group;
3757 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3758 last_group = tmpdiv;
3759#else
3760 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3761 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3762 if (first_group != last_group)
3763#endif
3764 return IO_ACCEL_INELIGIBLE;
3765
3766 /* Verify request is in a single row of RAID 5/6 */
3767#if BITS_PER_LONG == 32
3768 tmpdiv = first_block;
3769 (void) do_div(tmpdiv, stripesize);
3770 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3771 tmpdiv = last_block;
3772 (void) do_div(tmpdiv, stripesize);
3773 r5or6_last_row = r0_last_row = tmpdiv;
3774#else
3775 first_row = r5or6_first_row = r0_first_row =
3776 first_block / stripesize;
3777 r5or6_last_row = r0_last_row = last_block / stripesize;
3778#endif
3779 if (r5or6_first_row != r5or6_last_row)
3780 return IO_ACCEL_INELIGIBLE;
3781
3782
3783 /* Verify request is in a single column */
3784#if BITS_PER_LONG == 32
3785 tmpdiv = first_block;
3786 first_row_offset = do_div(tmpdiv, stripesize);
3787 tmpdiv = first_row_offset;
3788 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3789 r5or6_first_row_offset = first_row_offset;
3790 tmpdiv = last_block;
3791 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3792 tmpdiv = r5or6_last_row_offset;
3793 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3794 tmpdiv = r5or6_first_row_offset;
3795 (void) do_div(tmpdiv, map->strip_size);
3796 first_column = r5or6_first_column = tmpdiv;
3797 tmpdiv = r5or6_last_row_offset;
3798 (void) do_div(tmpdiv, map->strip_size);
3799 r5or6_last_column = tmpdiv;
3800#else
3801 first_row_offset = r5or6_first_row_offset =
3802 (u32)((first_block % stripesize) %
3803 r5or6_blocks_per_row);
3804
3805 r5or6_last_row_offset =
3806 (u32)((last_block % stripesize) %
3807 r5or6_blocks_per_row);
3808
3809 first_column = r5or6_first_column =
3810 r5or6_first_row_offset / map->strip_size;
3811 r5or6_last_column =
3812 r5or6_last_row_offset / map->strip_size;
3813#endif
3814 if (r5or6_first_column != r5or6_last_column)
3815 return IO_ACCEL_INELIGIBLE;
3816
3817 /* Request is eligible */
3818 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3819 map->row_cnt;
3820
3821 map_index = (first_group *
3822 (map->row_cnt * total_disks_per_row)) +
3823 (map_row * total_disks_per_row) + first_column;
3824 break;
3825 default:
3826 return IO_ACCEL_INELIGIBLE;
283b4a9b 3827 }
6b80b18f 3828
283b4a9b
SC		 3829 disk_handle = dd[map_index].ioaccel_handle;
3830 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3831 (first_row_offset - (first_column * map->strip_size));
3832 disk_block_cnt = block_cnt;
3833
3834 /* handle differing logical/physical block sizes */
3835 if (map->phys_blk_shift) {
3836 disk_block <<= map->phys_blk_shift;
3837 disk_block_cnt <<= map->phys_blk_shift;
3838 }
3839 BUG_ON(disk_block_cnt > 0xffff);
3840
3841 /* build the new CDB for the physical disk I/O */
3842 if (disk_block > 0xffffffff) {
3843 cdb[0] = is_write ? WRITE_16 : READ_16;
3844 cdb[1] = 0;
3845 cdb[2] = (u8) (disk_block >> 56);
3846 cdb[3] = (u8) (disk_block >> 48);
3847 cdb[4] = (u8) (disk_block >> 40);
3848 cdb[5] = (u8) (disk_block >> 32);
3849 cdb[6] = (u8) (disk_block >> 24);
3850 cdb[7] = (u8) (disk_block >> 16);
3851 cdb[8] = (u8) (disk_block >> 8);
3852 cdb[9] = (u8) (disk_block);
3853 cdb[10] = (u8) (disk_block_cnt >> 24);
3854 cdb[11] = (u8) (disk_block_cnt >> 16);
3855 cdb[12] = (u8) (disk_block_cnt >> 8);
3856 cdb[13] = (u8) (disk_block_cnt);
3857 cdb[14] = 0;
3858 cdb[15] = 0;
3859 cdb_len = 16;
3860 } else {
3861 cdb[0] = is_write ? WRITE_10 : READ_10;
3862 cdb[1] = 0;
3863 cdb[2] = (u8) (disk_block >> 24);
3864 cdb[3] = (u8) (disk_block >> 16);
3865 cdb[4] = (u8) (disk_block >> 8);
3866 cdb[5] = (u8) (disk_block);
3867 cdb[6] = 0;
3868 cdb[7] = (u8) (disk_block_cnt >> 8);
3869 cdb[8] = (u8) (disk_block_cnt);
3870 cdb[9] = 0;
3871 cdb_len = 10;
3872 }
3873 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3874 dev->scsi3addr);
3875}
3876
f281233d 3877static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3878 void (*done)(struct scsi_cmnd *))
3879{
3880 struct ctlr_info *h;
3881 struct hpsa_scsi_dev_t *dev;
3882 unsigned char scsi3addr[8];
3883 struct CommandList *c;
3884 unsigned long flags;
283b4a9b 3885 int rc = 0;
edd16368
SC		 3886
3887 /* Get the ptr to our adapter structure out of cmd->host. */
3888 h = sdev_to_hba(cmd->device);
3889 dev = cmd->device->hostdata;
3890 if (!dev) {
3891 cmd->result = DID_NO_CONNECT << 16;
3892 done(cmd);
3893 return 0;
3894 }
3895 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3896
edd16368 3897 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3898 if (unlikely(h->lockup_detected)) {
3899 spin_unlock_irqrestore(&h->lock, flags);
3900 cmd->result = DID_ERROR << 16;
3901 done(cmd);
3902 return 0;
3903 }
edd16368 3904 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3905 c = cmd_alloc(h);
edd16368
SC		 3906 if (c == NULL) { /* trouble... */
3907 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3908 return SCSI_MLQUEUE_HOST_BUSY;
3909 }
3910
3911 /* Fill in the command list header */
3912
3913 cmd->scsi_done = done; /* save this for use by completion code */
3914
3915 /* save c in case we have to abort it */
3916 cmd->host_scribble = (unsigned char *) c;
3917
3918 c->cmd_type = CMD_SCSI;
3919 c->scsi_cmd = cmd;
e1f7de0c 3920
283b4a9b
SC		 3921 /* Call alternate submit routine for I/O accelerated commands.
3922 * Retries always go down the normal I/O path.
3923 */
3924 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3925 cmd->request->cmd_type == REQ_TYPE_FS &&
3926 h->acciopath_status)) {
283b4a9b
SC		 3927 if (dev->offload_enabled) {
3928 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3929 if (rc == 0)
3930 return 0; /* Sent on ioaccel path */
3931 if (rc < 0) { /* scsi_dma_map failed. */
3932 cmd_free(h, c);
3933 return SCSI_MLQUEUE_HOST_BUSY;
3934 }
3935 } else if (dev->ioaccel_handle) {
3936 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3937 if (rc == 0)
3938 return 0; /* Sent on direct map path */
3939 if (rc < 0) { /* scsi_dma_map failed. */
3940 cmd_free(h, c);
3941 return SCSI_MLQUEUE_HOST_BUSY;
3942 }
3943 }
3944 }
e1f7de0c 3945
edd16368
SC		 3946 c->Header.ReplyQueue = 0; /* unused in simple mode */
3947 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3948 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3949 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3950
3951 /* Fill in the request block... */
3952
3953 c->Request.Timeout = 0;
3954 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3955 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3956 c->Request.CDBLen = cmd->cmd_len;
3957 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3958 c->Request.Type.Type = TYPE_CMD;
3959 c->Request.Type.Attribute = ATTR_SIMPLE;
3960 switch (cmd->sc_data_direction) {
3961 case DMA_TO_DEVICE:
3962 c->Request.Type.Direction = XFER_WRITE;
3963 break;
3964 case DMA_FROM_DEVICE:
3965 c->Request.Type.Direction = XFER_READ;
3966 break;
3967 case DMA_NONE:
3968 c->Request.Type.Direction = XFER_NONE;
3969 break;
3970 case DMA_BIDIRECTIONAL:
3971 /* This can happen if a buggy application does a scsi passthru
3972 * and sets both inlen and outlen to non-zero. ( see
3973 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3974 */
3975
3976 c->Request.Type.Direction = XFER_RSVD;
3977 /* This is technically wrong, and hpsa controllers should
3978 * reject it with CMD_INVALID, which is the most correct
3979 * response, but non-fibre backends appear to let it
3980 * slide by, and give the same results as if this field
3981 * were set correctly. Either way is acceptable for
3982 * our purposes here.
3983 */
3984
3985 break;
3986
3987 default:
3988 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3989 cmd->sc_data_direction);
3990 BUG();
3991 break;
3992 }
3993
33a2ffce 3994 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3995 cmd_free(h, c);
3996 return SCSI_MLQUEUE_HOST_BUSY;
3997 }
3998 enqueue_cmd_and_start_io(h, c);
3999 /* the cmd'll come back via intr handler in complete_scsi_command() */
4000 return 0;
4001}
4002
f281233d
JG		 4003static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
4004
5f389360
SC		 4005static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
4006{
4007 unsigned long flags;
4008
4009 /*
4010 * Don't let rescans be initiated on a controller known
4011 * to be locked up. If the controller locks up *during*
4012 * a rescan, that thread is probably hosed, but at least
4013 * we can prevent new rescan threads from piling up on a
4014 * locked up controller.
4015 */
4016 spin_lock_irqsave(&h->lock, flags);
4017 if (unlikely(h->lockup_detected)) {
4018 spin_unlock_irqrestore(&h->lock, flags);
4019 spin_lock_irqsave(&h->scan_lock, flags);
4020 h->scan_finished = 1;
4021 wake_up_all(&h->scan_wait_queue);
4022 spin_unlock_irqrestore(&h->scan_lock, flags);
4023 return 1;
4024 }
4025 spin_unlock_irqrestore(&h->lock, flags);
4026 return 0;
4027}
4028
a08a8471
SC		 4029static void hpsa_scan_start(struct Scsi_Host *sh)
4030{
4031 struct ctlr_info *h = shost_to_hba(sh);
4032 unsigned long flags;
4033
5f389360
SC		 4034 if (do_not_scan_if_controller_locked_up(h))
4035 return;
4036
a08a8471
SC		 4037 /* wait until any scan already in progress is finished. */
4038 while (1) {
4039 spin_lock_irqsave(&h->scan_lock, flags);
4040 if (h->scan_finished)
4041 break;
4042 spin_unlock_irqrestore(&h->scan_lock, flags);
4043 wait_event(h->scan_wait_queue, h->scan_finished);
4044 /* Note: We don't need to worry about a race between this
4045 * thread and driver unload because the midlayer will
4046 * have incremented the reference count, so unload won't
4047 * happen if we're in here.
4048 */
4049 }
4050 h->scan_finished = 0; /* mark scan as in progress */
4051 spin_unlock_irqrestore(&h->scan_lock, flags);
4052
5f389360
SC		 4053 if (do_not_scan_if_controller_locked_up(h))
4054 return;
4055
a08a8471
SC		 4056 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4057
4058 spin_lock_irqsave(&h->scan_lock, flags);
4059 h->scan_finished = 1; /* mark scan as finished. */
4060 wake_up_all(&h->scan_wait_queue);
4061 spin_unlock_irqrestore(&h->scan_lock, flags);
4062}
4063
4064static int hpsa_scan_finished(struct Scsi_Host *sh,
4065 unsigned long elapsed_time)
4066{
4067 struct ctlr_info *h = shost_to_hba(sh);
4068 unsigned long flags;
4069 int finished;
4070
4071 spin_lock_irqsave(&h->scan_lock, flags);
4072 finished = h->scan_finished;
4073 spin_unlock_irqrestore(&h->scan_lock, flags);
4074 return finished;
4075}
4076
667e23d4
SC		 4077static int hpsa_change_queue_depth(struct scsi_device *sdev,
4078 int qdepth, int reason)
4079{
4080 struct ctlr_info *h = sdev_to_hba(sdev);
4081
4082 if (reason != SCSI_QDEPTH_DEFAULT)
4083 return -ENOTSUPP;
4084
4085 if (qdepth < 1)
4086 qdepth = 1;
4087 else
4088 if (qdepth > h->nr_cmds)
4089 qdepth = h->nr_cmds;
4090 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4091 return sdev->queue_depth;
4092}
4093
edd16368
SC		 4094static void hpsa_unregister_scsi(struct ctlr_info *h)
4095{
4096 /* we are being forcibly unloaded, and may not refuse. */
4097 scsi_remove_host(h->scsi_host);
4098 scsi_host_put(h->scsi_host);
4099 h->scsi_host = NULL;
4100}
4101
4102static int hpsa_register_scsi(struct ctlr_info *h)
4103{
b705690d
SC		 4104 struct Scsi_Host *sh;
4105 int error;
edd16368 4106
b705690d
SC		 4107 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4108 if (sh == NULL)
4109 goto fail;
4110
4111 sh->io_port = 0;
4112 sh->n_io_port = 0;
4113 sh->this_id = -1;
4114 sh->max_channel = 3;
4115 sh->max_cmd_len = MAX_COMMAND_SIZE;
4116 sh->max_lun = HPSA_MAX_LUN;
4117 sh->max_id = HPSA_MAX_LUN;
4118 sh->can_queue = h->nr_cmds;
4119 sh->cmd_per_lun = h->nr_cmds;
4120 sh->sg_tablesize = h->maxsgentries;
4121 h->scsi_host = sh;
4122 sh->hostdata[0] = (unsigned long) h;
4123 sh->irq = h->intr[h->intr_mode];
4124 sh->unique_id = sh->irq;
4125 error = scsi_add_host(sh, &h->pdev->dev);
4126 if (error)
4127 goto fail_host_put;
4128 scsi_scan_host(sh);
4129 return 0;
4130
4131 fail_host_put:
4132 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4133 " failed for controller %d\n", __func__, h->ctlr);
4134 scsi_host_put(sh);
4135 return error;
4136 fail:
4137 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4138 " failed for controller %d\n", __func__, h->ctlr);
4139 return -ENOMEM;
edd16368
SC		 4140}
4141
4142static int wait_for_device_to_become_ready(struct ctlr_info *h,
4143 unsigned char lunaddr[])
4144{
4145 int rc = 0;
4146 int count = 0;
4147 int waittime = 1; /* seconds */
4148 struct CommandList *c;
4149
4150 c = cmd_special_alloc(h);
4151 if (!c) {
4152 dev_warn(&h->pdev->dev, "out of memory in "
4153 "wait_for_device_to_become_ready.\n");
4154 return IO_ERROR;
4155 }
4156
4157 /* Send test unit ready until device ready, or give up. */
4158 while (count < HPSA_TUR_RETRY_LIMIT) {
4159
4160 /* Wait for a bit. do this first, because if we send
4161 * the TUR right away, the reset will just abort it.
4162 */
4163 msleep(1000 * waittime);
4164 count++;
4165
4166 /* Increase wait time with each try, up to a point. */
4167 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4168 waittime = waittime * 2;
4169
a2dac136
SC		 4170 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4171 (void) fill_cmd(c, TEST_UNIT_READY, h,
4172 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 4173 hpsa_scsi_do_simple_cmd_core(h, c);
4174 /* no unmap needed here because no data xfer. */
4175
4176 if (c->err_info->CommandStatus == CMD_SUCCESS)
4177 break;
4178
4179 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4180 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4181 (c->err_info->SenseInfo[2] == NO_SENSE ||
4182 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4183 break;
4184
4185 dev_warn(&h->pdev->dev, "waiting %d secs "
4186 "for device to become ready.\n", waittime);
4187 rc = 1; /* device not ready. */
4188 }
4189
4190 if (rc)
4191 dev_warn(&h->pdev->dev, "giving up on device.\n");
4192 else
4193 dev_warn(&h->pdev->dev, "device is ready.\n");
4194
4195 cmd_special_free(h, c);
4196 return rc;
4197}
4198
4199/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4200 * complaining. Doing a host- or bus-reset can't do anything good here.
4201 */
4202static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4203{
4204 int rc;
4205 struct ctlr_info *h;
4206 struct hpsa_scsi_dev_t *dev;
4207
4208 /* find the controller to which the command to be aborted was sent */
4209 h = sdev_to_hba(scsicmd->device);
4210 if (h == NULL) /* paranoia */
4211 return FAILED;
edd16368
SC		 4212 dev = scsicmd->device->hostdata;
4213 if (!dev) {
4214 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4215 "device lookup failed.\n");
4216 return FAILED;
4217 }
d416b0c7
SC		 4218 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
4219 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 4220 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 4221 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 4222 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4223 return SUCCESS;
4224
4225 dev_warn(&h->pdev->dev, "resetting device failed.\n");
4226 return FAILED;
4227}
4228
6cba3f19
SC		 4229static void swizzle_abort_tag(u8 *tag)
4230{
4231 u8 original_tag[8];
4232
4233 memcpy(original_tag, tag, 8);
4234 tag[0] = original_tag[3];
4235 tag[1] = original_tag[2];
4236 tag[2] = original_tag[1];
4237 tag[3] = original_tag[0];
4238 tag[4] = original_tag[7];
4239 tag[5] = original_tag[6];
4240 tag[6] = original_tag[5];
4241 tag[7] = original_tag[4];
4242}
4243
17eb87d2
ST		 4244static void hpsa_get_tag(struct ctlr_info *h,
4245 struct CommandList *c, u32 *taglower, u32 *tagupper)
4246{
4247 if (c->cmd_type == CMD_IOACCEL1) {
4248 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4249 &h->ioaccel_cmd_pool[c->cmdindex];
4250 *tagupper = cm1->Tag.upper;
4251 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4252 return;
4253 }
4254 if (c->cmd_type == CMD_IOACCEL2) {
4255 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4256 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4257 /* upper tag not used in ioaccel2 mode */
4258 memset(tagupper, 0, sizeof(*tagupper));
4259 *taglower = cm2->Tag;
54b6e9e9 4260 return;
17eb87d2 4261 }
54b6e9e9
ST		 4262 *tagupper = c->Header.Tag.upper;
4263 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4264}
4265
54b6e9e9 4266
75167d2c 4267static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4268 struct CommandList *abort, int swizzle)
75167d2c
SC		 4269{
4270 int rc = IO_OK;
4271 struct CommandList *c;
4272 struct ErrorInfo *ei;
17eb87d2 4273 u32 tagupper, taglower;
75167d2c
SC		 4274
4275 c = cmd_special_alloc(h);
4276 if (c == NULL) { /* trouble... */
4277 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4278 return -ENOMEM;
4279 }
4280
a2dac136
SC		 4281 /* fill_cmd can't fail here, no buffer to map */
4282 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4283 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4284 if (swizzle)
4285 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4286 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4287 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4288 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4289 __func__, tagupper, taglower);
75167d2c
SC		 4290 /* no unmap needed here because no data xfer. */
4291
4292 ei = c->err_info;
4293 switch (ei->CommandStatus) {
4294 case CMD_SUCCESS:
4295 break;
4296 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4297 rc = -1;
4298 break;
4299 default:
4300 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4301 __func__, tagupper, taglower);
d1e8beac 4302 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4303 rc = -1;
4304 break;
4305 }
4306 cmd_special_free(h, c);
dd0e19f3
ST		 4307 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4308 __func__, tagupper, taglower);
75167d2c
SC		 4309 return rc;
4310}
4311
4312/*
4313 * hpsa_find_cmd_in_queue
4314 *
4315 * Used to determine whether a command (find) is still present
4316 * in queue_head. Optionally excludes the last element of queue_head.
4317 *
4318 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4319 * not yet been submitted, and so can be aborted by the driver without
4320 * sending an abort to the hardware.
4321 *
4322 * Returns pointer to command if found in queue, NULL otherwise.
4323 */
4324static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4325 struct scsi_cmnd *find, struct list_head *queue_head)
4326{
4327 unsigned long flags;
4328 struct CommandList *c = NULL; /* ptr into cmpQ */
4329
4330 if (!find)
4331 return 0;
4332 spin_lock_irqsave(&h->lock, flags);
4333 list_for_each_entry(c, queue_head, list) {
4334 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4335 continue;
4336 if (c->scsi_cmd == find) {
4337 spin_unlock_irqrestore(&h->lock, flags);
4338 return c;
4339 }
4340 }
4341 spin_unlock_irqrestore(&h->lock, flags);
4342 return NULL;
4343}
4344
6cba3f19
SC		 4345static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4346 u8 *tag, struct list_head *queue_head)
4347{
4348 unsigned long flags;
4349 struct CommandList *c;
4350
4351 spin_lock_irqsave(&h->lock, flags);
4352 list_for_each_entry(c, queue_head, list) {
4353 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4354 continue;
4355 spin_unlock_irqrestore(&h->lock, flags);
4356 return c;
4357 }
4358 spin_unlock_irqrestore(&h->lock, flags);
4359 return NULL;
4360}
4361
54b6e9e9
ST		 4362/* ioaccel2 path firmware cannot handle abort task requests.
4363 * Change abort requests to physical target reset, and send to the
4364 * address of the physical disk used for the ioaccel 2 command.
4365 * Return 0 on success (IO_OK)
4366 * -1 on failure
4367 */
4368
4369static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4370 unsigned char *scsi3addr, struct CommandList *abort)
4371{
4372 int rc = IO_OK;
4373 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4374 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4375 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4376 unsigned char *psa = &phys_scsi3addr[0];
4377
4378 /* Get a pointer to the hpsa logical device. */
4379 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4380 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4381 if (dev == NULL) {
4382 dev_warn(&h->pdev->dev,
4383 "Cannot abort: no device pointer for command.\n");
4384 return -1; /* not abortable */
4385 }
4386
2ba8bfc8
SC		 4387 if (h->raid_offload_debug > 0)
4388 dev_info(&h->pdev->dev,
4389 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4390 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4391 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4392 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4393
54b6e9e9
ST		 4394 if (!dev->offload_enabled) {
4395 dev_warn(&h->pdev->dev,
4396 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4397 return -1; /* not abortable */
4398 }
4399
4400 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4401 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4402 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4403 return -1; /* not abortable */
4404 }
4405
4406 /* send the reset */
2ba8bfc8
SC		 4407 if (h->raid_offload_debug > 0)
4408 dev_info(&h->pdev->dev,
4409 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4410 psa[0], psa[1], psa[2], psa[3],
4411 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4412 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4413 if (rc != 0) {
4414 dev_warn(&h->pdev->dev,
4415 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4416 psa[0], psa[1], psa[2], psa[3],
4417 psa[4], psa[5], psa[6], psa[7]);
4418 return rc; /* failed to reset */
4419 }
4420
4421 /* wait for device to recover */
4422 if (wait_for_device_to_become_ready(h, psa) != 0) {
4423 dev_warn(&h->pdev->dev,
4424 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4425 psa[0], psa[1], psa[2], psa[3],
4426 psa[4], psa[5], psa[6], psa[7]);
4427 return -1; /* failed to recover */
4428 }
4429
4430 /* device recovered */
4431 dev_info(&h->pdev->dev,
4432 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4433 psa[0], psa[1], psa[2], psa[3],
4434 psa[4], psa[5], psa[6], psa[7]);
4435
4436 return rc; /* success */
4437}
4438
6cba3f19
SC		 4439/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4440 * tell which kind we're dealing with, so we send the abort both ways. There
4441 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4442 * way we construct our tags but we check anyway in case the assumptions which
4443 * make this true someday become false.
4444 */
4445static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4446 unsigned char *scsi3addr, struct CommandList *abort)
4447{
4448 u8 swizzled_tag[8];
4449 struct CommandList *c;
4450 int rc = 0, rc2 = 0;
4451
54b6e9e9
ST		 4452 /* ioccelerator mode 2 commands should be aborted via the
4453 * accelerated path, since RAID path is unaware of these commands,
4454 * but underlying firmware can't handle abort TMF.
4455 * Change abort to physical device reset.
4456 */
4457 if (abort->cmd_type == CMD_IOACCEL2)
4458 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4459
6cba3f19
SC		 4460 /* we do not expect to find the swizzled tag in our queue, but
4461 * check anyway just to be sure the assumptions which make this
4462 * the case haven't become wrong.
4463 */
4464 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4465 swizzle_abort_tag(swizzled_tag);
4466 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4467 if (c != NULL) {
4468 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4469 return hpsa_send_abort(h, scsi3addr, abort, 0);
4470 }
4471 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4472
4473 /* if the command is still in our queue, we can't conclude that it was
4474 * aborted (it might have just completed normally) but in any case
4475 * we don't need to try to abort it another way.
4476 */
4477 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4478 if (c)
4479 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4480 return rc && rc2;
4481}
4482
75167d2c
SC		 4483/* Send an abort for the specified command.
4484 * If the device and controller support it,
4485 * send a task abort request.
4486 */
4487static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4488{
4489
4490 int i, rc;
4491 struct ctlr_info *h;
4492 struct hpsa_scsi_dev_t *dev;
4493 struct CommandList *abort; /* pointer to command to be aborted */
4494 struct CommandList *found;
4495 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4496 char msg[256]; /* For debug messaging. */
4497 int ml = 0;
17eb87d2 4498 u32 tagupper, taglower;
75167d2c
SC		 4499
4500 /* Find the controller of the command to be aborted */
4501 h = sdev_to_hba(sc->device);
4502 if (WARN(h == NULL,
4503 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4504 return FAILED;
4505
4506 /* Check that controller supports some kind of task abort */
4507 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4508 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4509 return FAILED;
4510
4511 memset(msg, 0, sizeof(msg));
4512 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4513 h->scsi_host->host_no, sc->device->channel,
4514 sc->device->id, sc->device->lun);
4515
4516 /* Find the device of the command to be aborted */
4517 dev = sc->device->hostdata;
4518 if (!dev) {
4519 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4520 msg);
4521 return FAILED;
4522 }
4523
4524 /* Get SCSI command to be aborted */
4525 abort = (struct CommandList *) sc->host_scribble;
4526 if (abort == NULL) {
4527 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4528 msg);
4529 return FAILED;
4530 }
17eb87d2
ST		 4531 hpsa_get_tag(h, abort, &taglower, &tagupper);
4532 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4533 as = (struct scsi_cmnd *) abort->scsi_cmd;
4534 if (as != NULL)
4535 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4536 as->cmnd[0], as->serial_number);
4537 dev_dbg(&h->pdev->dev, "%s\n", msg);
4538 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4539 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4540
4541 /* Search reqQ to See if command is queued but not submitted,
4542 * if so, complete the command with aborted status and remove
4543 * it from the reqQ.
4544 */
4545 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4546 if (found) {
4547 found->err_info->CommandStatus = CMD_ABORTED;
4548 finish_cmd(found);
4549 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4550 msg);
4551 return SUCCESS;
4552 }
4553
4554 /* not in reqQ, if also not in cmpQ, must have already completed */
4555 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4556 if (!found) {
d6ebd0f7 4557 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4558 msg);
4559 return SUCCESS;
4560 }
4561
4562 /*
4563 * Command is in flight, or possibly already completed
4564 * by the firmware (but not to the scsi mid layer) but we can't
4565 * distinguish which. Send the abort down.
4566 */
6cba3f19 4567 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4568 if (rc != 0) {
4569 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4570 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4571 h->scsi_host->host_no,
4572 dev->bus, dev->target, dev->lun);
4573 return FAILED;
4574 }
4575 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4576
4577 /* If the abort(s) above completed and actually aborted the
4578 * command, then the command to be aborted should already be
4579 * completed. If not, wait around a bit more to see if they
4580 * manage to complete normally.
4581 */
4582#define ABORT_COMPLETE_WAIT_SECS 30
4583 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4584 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4585 if (!found)
4586 return SUCCESS;
4587 msleep(100);
4588 }
4589 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4590 msg, ABORT_COMPLETE_WAIT_SECS);
4591 return FAILED;
4592}
4593
4594
edd16368
SC		 4595/*
4596 * For operations that cannot sleep, a command block is allocated at init,
4597 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4598 * which ones are free or in use. Lock must be held when calling this.
4599 * cmd_free() is the complement.
4600 */
4601static struct CommandList *cmd_alloc(struct ctlr_info *h)
4602{
4603 struct CommandList *c;
4604 int i;
4605 union u64bit temp64;
4606 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4607 unsigned long flags;
edd16368 4608
e16a33ad 4609 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4610 do {
4611 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4612 if (i == h->nr_cmds) {
4613 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4614 return NULL;
e16a33ad 4615 }
edd16368
SC		 4616 } while (test_and_set_bit
4617 (i & (BITS_PER_LONG - 1),
4618 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4619 spin_unlock_irqrestore(&h->lock, flags);
4620
edd16368
SC		 4621 c = h->cmd_pool + i;
4622 memset(c, 0, sizeof(*c));
4623 cmd_dma_handle = h->cmd_pool_dhandle
4624 + i * sizeof(*c);
4625 c->err_info = h->errinfo_pool + i;
4626 memset(c->err_info, 0, sizeof(*c->err_info));
4627 err_dma_handle = h->errinfo_pool_dhandle
4628 + i * sizeof(*c->err_info);
edd16368
SC		 4629
4630 c->cmdindex = i;
4631
9e0fc764 4632 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4633 c->busaddr = (u32) cmd_dma_handle;
4634 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4635 c->ErrDesc.Addr.lower = temp64.val32.lower;
4636 c->ErrDesc.Addr.upper = temp64.val32.upper;
4637 c->ErrDesc.Len = sizeof(*c->err_info);
4638
4639 c->h = h;
4640 return c;
4641}
4642
4643/* For operations that can wait for kmalloc to possibly sleep,
4644 * this routine can be called. Lock need not be held to call
4645 * cmd_special_alloc. cmd_special_free() is the complement.
4646 */
4647static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4648{
4649 struct CommandList *c;
4650 union u64bit temp64;
4651 dma_addr_t cmd_dma_handle, err_dma_handle;
4652
4653 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4654 if (c == NULL)
4655 return NULL;
4656 memset(c, 0, sizeof(*c));
4657
e1f7de0c 4658 c->cmd_type = CMD_SCSI;
edd16368
SC		 4659 c->cmdindex = -1;
4660
4661 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4662 &err_dma_handle);
4663
4664 if (c->err_info == NULL) {
4665 pci_free_consistent(h->pdev,
4666 sizeof(*c), c, cmd_dma_handle);
4667 return NULL;
4668 }
4669 memset(c->err_info, 0, sizeof(*c->err_info));
4670
9e0fc764 4671 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4672 c->busaddr = (u32) cmd_dma_handle;
4673 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4674 c->ErrDesc.Addr.lower = temp64.val32.lower;
4675 c->ErrDesc.Addr.upper = temp64.val32.upper;
4676 c->ErrDesc.Len = sizeof(*c->err_info);
4677
4678 c->h = h;
4679 return c;
4680}
4681
4682static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4683{
4684 int i;
e16a33ad 4685 unsigned long flags;
edd16368
SC		 4686
4687 i = c - h->cmd_pool;
e16a33ad 4688 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4689 clear_bit(i & (BITS_PER_LONG - 1),
4690 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4691 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4692}
4693
4694static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4695{
4696 union u64bit temp64;
4697
4698 temp64.val32.lower = c->ErrDesc.Addr.lower;
4699 temp64.val32.upper = c->ErrDesc.Addr.upper;
4700 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4701 c->err_info, (dma_addr_t) temp64.val);
4702 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4703 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4704}
4705
4706#ifdef CONFIG_COMPAT
4707
edd16368
SC		 4708static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4709{
4710 IOCTL32_Command_struct __user *arg32 =
4711 (IOCTL32_Command_struct __user *) arg;
4712 IOCTL_Command_struct arg64;
4713 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4714 int err;
4715 u32 cp;
4716
938abd84 4717 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4718 err = 0;
4719 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4720 sizeof(arg64.LUN_info));
4721 err |= copy_from_user(&arg64.Request, &arg32->Request,
4722 sizeof(arg64.Request));
4723 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4724 sizeof(arg64.error_info));
4725 err |= get_user(arg64.buf_size, &arg32->buf_size);
4726 err |= get_user(cp, &arg32->buf);
4727 arg64.buf = compat_ptr(cp);
4728 err |= copy_to_user(p, &arg64, sizeof(arg64));
4729
4730 if (err)
4731 return -EFAULT;
4732
e39eeaed 4733 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4734 if (err)
4735 return err;
4736 err |= copy_in_user(&arg32->error_info, &p->error_info,
4737 sizeof(arg32->error_info));
4738 if (err)
4739 return -EFAULT;
4740 return err;
4741}
4742
4743static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4744 int cmd, void *arg)
4745{
4746 BIG_IOCTL32_Command_struct __user *arg32 =
4747 (BIG_IOCTL32_Command_struct __user *) arg;
4748 BIG_IOCTL_Command_struct arg64;
4749 BIG_IOCTL_Command_struct __user *p =
4750 compat_alloc_user_space(sizeof(arg64));
4751 int err;
4752 u32 cp;
4753
938abd84 4754 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4755 err = 0;
4756 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4757 sizeof(arg64.LUN_info));
4758 err |= copy_from_user(&arg64.Request, &arg32->Request,
4759 sizeof(arg64.Request));
4760 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4761 sizeof(arg64.error_info));
4762 err |= get_user(arg64.buf_size, &arg32->buf_size);
4763 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4764 err |= get_user(cp, &arg32->buf);
4765 arg64.buf = compat_ptr(cp);
4766 err |= copy_to_user(p, &arg64, sizeof(arg64));
4767
4768 if (err)
4769 return -EFAULT;
4770
e39eeaed 4771 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4772 if (err)
4773 return err;
4774 err |= copy_in_user(&arg32->error_info, &p->error_info,
4775 sizeof(arg32->error_info));
4776 if (err)
4777 return -EFAULT;
4778 return err;
4779}
71fe75a7
SC		 4780
4781static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4782{
4783 switch (cmd) {
4784 case CCISS_GETPCIINFO:
4785 case CCISS_GETINTINFO:
4786 case CCISS_SETINTINFO:
4787 case CCISS_GETNODENAME:
4788 case CCISS_SETNODENAME:
4789 case CCISS_GETHEARTBEAT:
4790 case CCISS_GETBUSTYPES:
4791 case CCISS_GETFIRMVER:
4792 case CCISS_GETDRIVVER:
4793 case CCISS_REVALIDVOLS:
4794 case CCISS_DEREGDISK:
4795 case CCISS_REGNEWDISK:
4796 case CCISS_REGNEWD:
4797 case CCISS_RESCANDISK:
4798 case CCISS_GETLUNINFO:
4799 return hpsa_ioctl(dev, cmd, arg);
4800
4801 case CCISS_PASSTHRU32:
4802 return hpsa_ioctl32_passthru(dev, cmd, arg);
4803 case CCISS_BIG_PASSTHRU32:
4804 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4805
4806 default:
4807 return -ENOIOCTLCMD;
4808 }
4809}
edd16368
SC		 4810#endif
4811
4812static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4813{
4814 struct hpsa_pci_info pciinfo;
4815
4816 if (!argp)
4817 return -EINVAL;
4818 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4819 pciinfo.bus = h->pdev->bus->number;
4820 pciinfo.dev_fn = h->pdev->devfn;
4821 pciinfo.board_id = h->board_id;
4822 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4823 return -EFAULT;
4824 return 0;
4825}
4826
4827static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4828{
4829 DriverVer_type DriverVer;
4830 unsigned char vmaj, vmin, vsubmin;
4831 int rc;
4832
4833 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4834 &vmaj, &vmin, &vsubmin);
4835 if (rc != 3) {
4836 dev_info(&h->pdev->dev, "driver version string '%s' "
4837 "unrecognized.", HPSA_DRIVER_VERSION);
4838 vmaj = 0;
4839 vmin = 0;
4840 vsubmin = 0;
4841 }
4842 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4843 if (!argp)
4844 return -EINVAL;
4845 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4846 return -EFAULT;
4847 return 0;
4848}
4849
4850static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4851{
4852 IOCTL_Command_struct iocommand;
4853 struct CommandList *c;
4854 char *buff = NULL;
4855 union u64bit temp64;
c1f63c8f 4856 int rc = 0;
edd16368
SC		 4857
4858 if (!argp)
4859 return -EINVAL;
4860 if (!capable(CAP_SYS_RAWIO))
4861 return -EPERM;
4862 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4863 return -EFAULT;
4864 if ((iocommand.buf_size < 1) &&
4865 (iocommand.Request.Type.Direction != XFER_NONE)) {
4866 return -EINVAL;
4867 }
4868 if (iocommand.buf_size > 0) {
4869 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4870 if (buff == NULL)
4871 return -EFAULT;
b03a7771
SC		 4872 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4873 /* Copy the data into the buffer we created */
4874 if (copy_from_user(buff, iocommand.buf,
4875 iocommand.buf_size)) {
c1f63c8f
SC		 4876 rc = -EFAULT;
4877 goto out_kfree;
b03a7771
SC		 4878 }
4879 } else {
4880 memset(buff, 0, iocommand.buf_size);
edd16368 4881 }
b03a7771 4882 }
edd16368
SC		 4883 c = cmd_special_alloc(h);
4884 if (c == NULL) {
c1f63c8f
SC		 4885 rc = -ENOMEM;
4886 goto out_kfree;
edd16368
SC		 4887 }
4888 /* Fill in the command type */
4889 c->cmd_type = CMD_IOCTL_PEND;
4890 /* Fill in Command Header */
4891 c->Header.ReplyQueue = 0; /* unused in simple mode */
4892 if (iocommand.buf_size > 0) { /* buffer to fill */
4893 c->Header.SGList = 1;
4894 c->Header.SGTotal = 1;
4895 } else { /* no buffers to fill */
4896 c->Header.SGList = 0;
4897 c->Header.SGTotal = 0;
4898 }
4899 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4900 /* use the kernel address the cmd block for tag */
4901 c->Header.Tag.lower = c->busaddr;
4902
4903 /* Fill in Request block */
4904 memcpy(&c->Request, &iocommand.Request,
4905 sizeof(c->Request));
4906
4907 /* Fill in the scatter gather information */
4908 if (iocommand.buf_size > 0) {
4909 temp64.val = pci_map_single(h->pdev, buff,
4910 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4911 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4912 c->SG[0].Addr.lower = 0;
4913 c->SG[0].Addr.upper = 0;
4914 c->SG[0].Len = 0;
4915 rc = -ENOMEM;
4916 goto out;
4917 }
edd16368
SC		 4918 c->SG[0].Addr.lower = temp64.val32.lower;
4919 c->SG[0].Addr.upper = temp64.val32.upper;
4920 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4921 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4922 }
a0c12413 4923 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4924 if (iocommand.buf_size > 0)
4925 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4926 check_ioctl_unit_attention(h, c);
4927
4928 /* Copy the error information out */
4929 memcpy(&iocommand.error_info, c->err_info,
4930 sizeof(iocommand.error_info));
4931 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4932 rc = -EFAULT;
4933 goto out;
edd16368 4934 }
b03a7771
SC		 4935 if (iocommand.Request.Type.Direction == XFER_READ &&
4936 iocommand.buf_size > 0) {
edd16368
SC		 4937 /* Copy the data out of the buffer we created */
4938 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4939 rc = -EFAULT;
4940 goto out;
edd16368
SC		 4941 }
4942 }
c1f63c8f 4943out:
edd16368 4944 cmd_special_free(h, c);
c1f63c8f
SC		 4945out_kfree:
4946 kfree(buff);
4947 return rc;
edd16368
SC		 4948}
4949
4950static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4951{
4952 BIG_IOCTL_Command_struct *ioc;
4953 struct CommandList *c;
4954 unsigned char **buff = NULL;
4955 int *buff_size = NULL;
4956 union u64bit temp64;
4957 BYTE sg_used = 0;
4958 int status = 0;
4959 int i;
01a02ffc
SC		 4960 u32 left;
4961 u32 sz;
edd16368
SC		 4962 BYTE __user *data_ptr;
4963
4964 if (!argp)
4965 return -EINVAL;
4966 if (!capable(CAP_SYS_RAWIO))
4967 return -EPERM;
4968 ioc = (BIG_IOCTL_Command_struct *)
4969 kmalloc(sizeof(*ioc), GFP_KERNEL);
4970 if (!ioc) {
4971 status = -ENOMEM;
4972 goto cleanup1;
4973 }
4974 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4975 status = -EFAULT;
4976 goto cleanup1;
4977 }
4978 if ((ioc->buf_size < 1) &&
4979 (ioc->Request.Type.Direction != XFER_NONE)) {
4980 status = -EINVAL;
4981 goto cleanup1;
4982 }
4983 /* Check kmalloc limits using all SGs */
4984 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4985 status = -EINVAL;
4986 goto cleanup1;
4987 }
d66ae08b 4988 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4989 status = -EINVAL;
4990 goto cleanup1;
4991 }
d66ae08b 4992 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4993 if (!buff) {
4994 status = -ENOMEM;
4995 goto cleanup1;
4996 }
d66ae08b 4997 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4998 if (!buff_size) {
4999 status = -ENOMEM;
5000 goto cleanup1;
5001 }
5002 left = ioc->buf_size;
5003 data_ptr = ioc->buf;
5004 while (left) {
5005 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5006 buff_size[sg_used] = sz;
5007 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5008 if (buff[sg_used] == NULL) {
5009 status = -ENOMEM;
5010 goto cleanup1;
5011 }
5012 if (ioc->Request.Type.Direction == XFER_WRITE) {
5013 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
5014 status = -ENOMEM;
5015 goto cleanup1;
5016 }
5017 } else
5018 memset(buff[sg_used], 0, sz);
5019 left -= sz;
5020 data_ptr += sz;
5021 sg_used++;
5022 }
5023 c = cmd_special_alloc(h);
5024 if (c == NULL) {
5025 status = -ENOMEM;
5026 goto cleanup1;
5027 }
5028 c->cmd_type = CMD_IOCTL_PEND;
5029 c->Header.ReplyQueue = 0;
b03a7771 5030 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 5031 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
5032 c->Header.Tag.lower = c->busaddr;
5033 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5034 if (ioc->buf_size > 0) {
5035 int i;
5036 for (i = 0; i < sg_used; i++) {
5037 temp64.val = pci_map_single(h->pdev, buff[i],
5038 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 5039 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
5040 c->SG[i].Addr.lower = 0;
5041 c->SG[i].Addr.upper = 0;
5042 c->SG[i].Len = 0;
5043 hpsa_pci_unmap(h->pdev, c, i,
5044 PCI_DMA_BIDIRECTIONAL);
5045 status = -ENOMEM;
e2d4a1f6 5046 goto cleanup0;
bcc48ffa 5047 }
edd16368
SC		 5048 c->SG[i].Addr.lower = temp64.val32.lower;
5049 c->SG[i].Addr.upper = temp64.val32.upper;
5050 c->SG[i].Len = buff_size[i];
e1d9cbfa 5051 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 5052 }
5053 }
a0c12413 5054 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 5055 if (sg_used)
5056 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 5057 check_ioctl_unit_attention(h, c);
5058 /* Copy the error information out */
5059 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5060 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5061 status = -EFAULT;
e2d4a1f6 5062 goto cleanup0;
edd16368 5063 }
b03a7771 5064 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 5065 /* Copy the data out of the buffer we created */
5066 BYTE __user *ptr = ioc->buf;
5067 for (i = 0; i < sg_used; i++) {
5068 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5069 status = -EFAULT;
e2d4a1f6 5070 goto cleanup0;
edd16368
SC		 5071 }
5072 ptr += buff_size[i];
5073 }
5074 }
edd16368 5075 status = 0;
e2d4a1f6
SC		 5076cleanup0:
5077 cmd_special_free(h, c);
edd16368
SC		 5078cleanup1:
5079 if (buff) {
5080 for (i = 0; i < sg_used; i++)
5081 kfree(buff[i]);
5082 kfree(buff);
5083 }
5084 kfree(buff_size);
5085 kfree(ioc);
5086 return status;
5087}
5088
5089static void check_ioctl_unit_attention(struct ctlr_info *h,
5090 struct CommandList *c)
5091{
5092 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5093 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5094 (void) check_for_unit_attention(h, c);
5095}
0390f0c0
SC		 5096
5097static int increment_passthru_count(struct ctlr_info *h)
5098{
5099 unsigned long flags;
5100
5101 spin_lock_irqsave(&h->passthru_count_lock, flags);
5102 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
5103 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5104 return -1;
5105 }
5106 h->passthru_count++;
5107 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5108 return 0;
5109}
5110
5111static void decrement_passthru_count(struct ctlr_info *h)
5112{
5113 unsigned long flags;
5114
5115 spin_lock_irqsave(&h->passthru_count_lock, flags);
5116 if (h->passthru_count <= 0) {
5117 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5118 /* not expecting to get here. */
5119 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
5120 return;
5121 }
5122 h->passthru_count--;
5123 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
5124}
5125
edd16368
SC		 5126/*
5127 * ioctl
5128 */
5129static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
5130{
5131 struct ctlr_info *h;
5132 void __user *argp = (void __user *)arg;
0390f0c0 5133 int rc;
edd16368
SC		 5134
5135 h = sdev_to_hba(dev);
5136
5137 switch (cmd) {
5138 case CCISS_DEREGDISK:
5139 case CCISS_REGNEWDISK:
5140 case CCISS_REGNEWD:
a08a8471 5141 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5142 return 0;
5143 case CCISS_GETPCIINFO:
5144 return hpsa_getpciinfo_ioctl(h, argp);
5145 case CCISS_GETDRIVVER:
5146 return hpsa_getdrivver_ioctl(h, argp);
5147 case CCISS_PASSTHRU:
0390f0c0
SC		 5148 if (increment_passthru_count(h))
5149 return -EAGAIN;
5150 rc = hpsa_passthru_ioctl(h, argp);
5151 decrement_passthru_count(h);
5152 return rc;
edd16368 5153 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 5154 if (increment_passthru_count(h))
5155 return -EAGAIN;
5156 rc = hpsa_big_passthru_ioctl(h, argp);
5157 decrement_passthru_count(h);
5158 return rc;
edd16368
SC		 5159 default:
5160 return -ENOTTY;
5161 }
5162}
5163
6f039790
GKH		 5164static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5165 u8 reset_type)
64670ac8
SC		 5166{
5167 struct CommandList *c;
5168
5169 c = cmd_alloc(h);
5170 if (!c)
5171 return -ENOMEM;
a2dac136
SC		 5172 /* fill_cmd can't fail here, no data buffer to map */
5173 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5174 RAID_CTLR_LUNID, TYPE_MSG);
5175 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5176 c->waiting = NULL;
5177 enqueue_cmd_and_start_io(h, c);
5178 /* Don't wait for completion, the reset won't complete. Don't free
5179 * the command either. This is the last command we will send before
5180 * re-initializing everything, so it doesn't matter and won't leak.
5181 */
5182 return 0;
5183}
5184
a2dac136 5185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5186 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5187 int cmd_type)
5188{
5189 int pci_dir = XFER_NONE;
75167d2c 5190 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 5191
5192 c->cmd_type = CMD_IOCTL_PEND;
5193 c->Header.ReplyQueue = 0;
5194 if (buff != NULL && size > 0) {
5195 c->Header.SGList = 1;
5196 c->Header.SGTotal = 1;
5197 } else {
5198 c->Header.SGList = 0;
5199 c->Header.SGTotal = 0;
5200 }
5201 c->Header.Tag.lower = c->busaddr;
5202 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5203
5204 c->Request.Type.Type = cmd_type;
5205 if (cmd_type == TYPE_CMD) {
5206 switch (cmd) {
5207 case HPSA_INQUIRY:
5208 /* are we trying to read a vital product page */
b7bb24eb 5209 if (page_code & VPD_PAGE) {
edd16368 5210 c->Request.CDB[1] = 0x01;
b7bb24eb 5211 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5212 }
5213 c->Request.CDBLen = 6;
5214 c->Request.Type.Attribute = ATTR_SIMPLE;
5215 c->Request.Type.Direction = XFER_READ;
5216 c->Request.Timeout = 0;
5217 c->Request.CDB[0] = HPSA_INQUIRY;
5218 c->Request.CDB[4] = size & 0xFF;
5219 break;
5220 case HPSA_REPORT_LOG:
5221 case HPSA_REPORT_PHYS:
5222 /* Talking to controller so It's a physical command
5223 mode = 00 target = 0. Nothing to write.
5224 */
5225 c->Request.CDBLen = 12;
5226 c->Request.Type.Attribute = ATTR_SIMPLE;
5227 c->Request.Type.Direction = XFER_READ;
5228 c->Request.Timeout = 0;
5229 c->Request.CDB[0] = cmd;
5230 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5231 c->Request.CDB[7] = (size >> 16) & 0xFF;
5232 c->Request.CDB[8] = (size >> 8) & 0xFF;
5233 c->Request.CDB[9] = size & 0xFF;
5234 break;
edd16368
SC		 5235 case HPSA_CACHE_FLUSH:
5236 c->Request.CDBLen = 12;
5237 c->Request.Type.Attribute = ATTR_SIMPLE;
5238 c->Request.Type.Direction = XFER_WRITE;
5239 c->Request.Timeout = 0;
5240 c->Request.CDB[0] = BMIC_WRITE;
5241 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5242 c->Request.CDB[7] = (size >> 8) & 0xFF;
5243 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5244 break;
5245 case TEST_UNIT_READY:
5246 c->Request.CDBLen = 6;
5247 c->Request.Type.Attribute = ATTR_SIMPLE;
5248 c->Request.Type.Direction = XFER_NONE;
5249 c->Request.Timeout = 0;
5250 break;
283b4a9b
SC		 5251 case HPSA_GET_RAID_MAP:
5252 c->Request.CDBLen = 12;
5253 c->Request.Type.Attribute = ATTR_SIMPLE;
5254 c->Request.Type.Direction = XFER_READ;
5255 c->Request.Timeout = 0;
5256 c->Request.CDB[0] = HPSA_CISS_READ;
5257 c->Request.CDB[1] = cmd;
5258 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5259 c->Request.CDB[7] = (size >> 16) & 0xFF;
5260 c->Request.CDB[8] = (size >> 8) & 0xFF;
5261 c->Request.CDB[9] = size & 0xFF;
5262 break;
edd16368
SC		 5263 default:
5264 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5265 BUG();
a2dac136 5266 return -1;
edd16368
SC		 5267 }
5268 } else if (cmd_type == TYPE_MSG) {
5269 switch (cmd) {
5270
5271 case HPSA_DEVICE_RESET_MSG:
5272 c->Request.CDBLen = 16;
5273 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5274 c->Request.Type.Attribute = ATTR_SIMPLE;
5275 c->Request.Type.Direction = XFER_NONE;
5276 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5277 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5278 c->Request.CDB[0] = cmd;
21e89afd 5279 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5280 /* If bytes 4-7 are zero, it means reset the */
5281 /* LunID device */
5282 c->Request.CDB[4] = 0x00;
5283 c->Request.CDB[5] = 0x00;
5284 c->Request.CDB[6] = 0x00;
5285 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5286 break;
5287 case HPSA_ABORT_MSG:
5288 a = buff; /* point to command to be aborted */
5289 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5290 a->Header.Tag.upper, a->Header.Tag.lower,
5291 c->Header.Tag.upper, c->Header.Tag.lower);
5292 c->Request.CDBLen = 16;
5293 c->Request.Type.Type = TYPE_MSG;
5294 c->Request.Type.Attribute = ATTR_SIMPLE;
5295 c->Request.Type.Direction = XFER_WRITE;
5296 c->Request.Timeout = 0; /* Don't time out */
5297 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5298 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5299 c->Request.CDB[2] = 0x00; /* reserved */
5300 c->Request.CDB[3] = 0x00; /* reserved */
5301 /* Tag to abort goes in CDB[4]-CDB[11] */
5302 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5303 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5304 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5305 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5306 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5307 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5308 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5309 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5310 c->Request.CDB[12] = 0x00; /* reserved */
5311 c->Request.CDB[13] = 0x00; /* reserved */
5312 c->Request.CDB[14] = 0x00; /* reserved */
5313 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5314 break;
edd16368
SC		 5315 default:
5316 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5317 cmd);
5318 BUG();
5319 }
5320 } else {
5321 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5322 BUG();
5323 }
5324
5325 switch (c->Request.Type.Direction) {
5326 case XFER_READ:
5327 pci_dir = PCI_DMA_FROMDEVICE;
5328 break;
5329 case XFER_WRITE:
5330 pci_dir = PCI_DMA_TODEVICE;
5331 break;
5332 case XFER_NONE:
5333 pci_dir = PCI_DMA_NONE;
5334 break;
5335 default:
5336 pci_dir = PCI_DMA_BIDIRECTIONAL;
5337 }
a2dac136
SC		 5338 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5339 return -1;
5340 return 0;
edd16368
SC		 5341}
5342
5343/*
5344 * Map (physical) PCI mem into (virtual) kernel space
5345 */
5346static void __iomem *remap_pci_mem(ulong base, ulong size)
5347{
5348 ulong page_base = ((ulong) base) & PAGE_MASK;
5349 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5350 void __iomem *page_remapped = ioremap_nocache(page_base,
5351 page_offs + size);
edd16368
SC		 5352
5353 return page_remapped ? (page_remapped + page_offs) : NULL;
5354}
5355
5356/* Takes cmds off the submission queue and sends them to the hardware,
5357 * then puts them on the queue of cmds waiting for completion.
5358 */
5359static void start_io(struct ctlr_info *h)
5360{
5361 struct CommandList *c;
e16a33ad 5362 unsigned long flags;
edd16368 5363
e16a33ad 5364 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 5365 while (!list_empty(&h->reqQ)) {
5366 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5367 /* can't do anything if fifo is full */
5368 if ((h->access.fifo_full(h))) {
396883e2 5369 h->fifo_recently_full = 1;
edd16368
SC		 5370 dev_warn(&h->pdev->dev, "fifo full\n");
5371 break;
5372 }
396883e2 5373 h->fifo_recently_full = 0;
edd16368
SC		 5374
5375 /* Get the first entry from the Request Q */
5376 removeQ(c);
5377 h->Qdepth--;
5378
edd16368
SC		 5379 /* Put job onto the completed Q */
5380 addQ(&h->cmpQ, c);
e16a33ad
MG		 5381
5382 /* Must increment commands_outstanding before unlocking
5383 * and submitting to avoid race checking for fifo full
5384 * condition.
5385 */
5386 h->commands_outstanding++;
5387 if (h->commands_outstanding > h->max_outstanding)
5388 h->max_outstanding = h->commands_outstanding;
5389
5390 /* Tell the controller execute command */
5391 spin_unlock_irqrestore(&h->lock, flags);
5392 h->access.submit_command(h, c);
5393 spin_lock_irqsave(&h->lock, flags);
edd16368 5394 }
e16a33ad 5395 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5396}
5397
254f796b 5398static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5399{
254f796b 5400 return h->access.command_completed(h, q);
edd16368
SC		 5401}
5402
900c5440 5403static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5404{
5405 return h->access.intr_pending(h);
5406}
5407
5408static inline long interrupt_not_for_us(struct ctlr_info *h)
5409{
10f66018
SC		 5410 return (h->access.intr_pending(h) == 0) ||
5411 (h->interrupts_enabled == 0);
edd16368
SC		 5412}
5413
01a02ffc
SC		 5414static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5415 u32 raw_tag)
edd16368
SC		 5416{
5417 if (unlikely(tag_index >= h->nr_cmds)) {
5418 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5419 return 1;
5420 }
5421 return 0;
5422}
5423
5a3d16f5 5424static inline void finish_cmd(struct CommandList *c)
edd16368 5425{
e16a33ad 5426 unsigned long flags;
396883e2
SC		 5427 int io_may_be_stalled = 0;
5428 struct ctlr_info *h = c->h;
e16a33ad 5429
396883e2 5430 spin_lock_irqsave(&h->lock, flags);
edd16368 5431 removeQ(c);
396883e2
SC		 5432
5433 /*
5434 * Check for possibly stalled i/o.
5435 *
5436 * If a fifo_full condition is encountered, requests will back up
5437 * in h->reqQ. This queue is only emptied out by start_io which is
5438 * only called when a new i/o request comes in. If no i/o's are
5439 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5440 * start_io from here if we detect such a danger.
5441 *
5442 * Normally, we shouldn't hit this case, but pounding on the
5443 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5444 * commands_outstanding is low. We want to avoid calling
5445 * start_io from in here as much as possible, and esp. don't
5446 * want to get in a cycle where we call start_io every time
5447 * through here.
5448 */
5449 if (unlikely(h->fifo_recently_full) &&
5450 h->commands_outstanding < 5)
5451 io_may_be_stalled = 1;
5452
5453 spin_unlock_irqrestore(&h->lock, flags);
5454
e85c5974 5455 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5456 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5457 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5458 complete_scsi_command(c);
edd16368
SC		 5459 else if (c->cmd_type == CMD_IOCTL_PEND)
5460 complete(c->waiting);
396883e2
SC		 5461 if (unlikely(io_may_be_stalled))
5462 start_io(h);
edd16368
SC		 5463}
5464
a104c99f
SC		 5465static inline u32 hpsa_tag_contains_index(u32 tag)
5466{
a104c99f
SC		 5467 return tag & DIRECT_LOOKUP_BIT;
5468}
5469
5470static inline u32 hpsa_tag_to_index(u32 tag)
5471{
a104c99f
SC		 5472 return tag >> DIRECT_LOOKUP_SHIFT;
5473}
5474
a9a3a273
SC		 5475
5476static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5477{
a9a3a273
SC		 5478#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5479#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5480 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5481 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5482 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5483}
5484
303932fd 5485/* process completion of an indexed ("direct lookup") command */
1d94f94d 5486static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5487 u32 raw_tag)
5488{
5489 u32 tag_index;
5490 struct CommandList *c;
5491
5492 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5493 if (!bad_tag(h, tag_index, raw_tag)) {
5494 c = h->cmd_pool + tag_index;
5495 finish_cmd(c);
5496 }
303932fd
DB		 5497}
5498
5499/* process completion of a non-indexed command */
1d94f94d 5500static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5501 u32 raw_tag)
5502{
5503 u32 tag;
5504 struct CommandList *c = NULL;
e16a33ad 5505 unsigned long flags;
303932fd 5506
a9a3a273 5507 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5508 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5509 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5510 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5511 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5512 finish_cmd(c);
1d94f94d 5513 return;
303932fd
DB		 5514 }
5515 }
e16a33ad 5516 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5517 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5518}
5519
64670ac8
SC		 5520/* Some controllers, like p400, will give us one interrupt
5521 * after a soft reset, even if we turned interrupts off.
5522 * Only need to check for this in the hpsa_xxx_discard_completions
5523 * functions.
5524 */
5525static int ignore_bogus_interrupt(struct ctlr_info *h)
5526{
5527 if (likely(!reset_devices))
5528 return 0;
5529
5530 if (likely(h->interrupts_enabled))
5531 return 0;
5532
5533 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5534 "(known firmware bug.) Ignoring.\n");
5535
5536 return 1;
5537}
5538
254f796b
MG		 5539/*
5540 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5541 * Relies on (h-q[x] == x) being true for x such that
5542 * 0 <= x < MAX_REPLY_QUEUES.
5543 */
5544static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5545{
254f796b
MG		 5546 return container_of((queue - *queue), struct ctlr_info, q[0]);
5547}
5548
5549static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5550{
5551 struct ctlr_info *h = queue_to_hba(queue);
5552 u8 q = *(u8 *) queue;
64670ac8
SC		 5553 u32 raw_tag;
5554
5555 if (ignore_bogus_interrupt(h))
5556 return IRQ_NONE;
5557
5558 if (interrupt_not_for_us(h))
5559 return IRQ_NONE;
a0c12413 5560 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5561 while (interrupt_pending(h)) {
254f796b 5562 raw_tag = get_next_completion(h, q);
64670ac8 5563 while (raw_tag != FIFO_EMPTY)
254f796b 5564 raw_tag = next_command(h, q);
64670ac8 5565 }
64670ac8
SC		 5566 return IRQ_HANDLED;
5567}
5568
254f796b 5569static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5570{
254f796b 5571 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5572 u32 raw_tag;
254f796b 5573 u8 q = *(u8 *) queue;
64670ac8
SC		 5574
5575 if (ignore_bogus_interrupt(h))
5576 return IRQ_NONE;
5577
a0c12413 5578 h->last_intr_timestamp = get_jiffies_64();
254f796b 5579 raw_tag = get_next_completion(h, q);
64670ac8 5580 while (raw_tag != FIFO_EMPTY)
254f796b 5581 raw_tag = next_command(h, q);
64670ac8
SC		 5582 return IRQ_HANDLED;
5583}
5584
254f796b 5585static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5586{
254f796b 5587 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5588 u32 raw_tag;
254f796b 5589 u8 q = *(u8 *) queue;
edd16368
SC		 5590
5591 if (interrupt_not_for_us(h))
5592 return IRQ_NONE;
a0c12413 5593 h->last_intr_timestamp = get_jiffies_64();
10f66018 5594 while (interrupt_pending(h)) {
254f796b 5595 raw_tag = get_next_completion(h, q);
10f66018 5596 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5597 if (likely(hpsa_tag_contains_index(raw_tag)))
5598 process_indexed_cmd(h, raw_tag);
10f66018 5599 else
1d94f94d 5600 process_nonindexed_cmd(h, raw_tag);
254f796b 5601 raw_tag = next_command(h, q);
10f66018
SC		 5602 }
5603 }
10f66018
SC		 5604 return IRQ_HANDLED;
5605}
5606
254f796b 5607static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5608{
254f796b 5609 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5610 u32 raw_tag;
254f796b 5611 u8 q = *(u8 *) queue;
10f66018 5612
a0c12413 5613 h->last_intr_timestamp = get_jiffies_64();
254f796b 5614 raw_tag = get_next_completion(h, q);
303932fd 5615 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5616 if (likely(hpsa_tag_contains_index(raw_tag)))
5617 process_indexed_cmd(h, raw_tag);
303932fd 5618 else
1d94f94d 5619 process_nonindexed_cmd(h, raw_tag);
254f796b 5620 raw_tag = next_command(h, q);
edd16368 5621 }
edd16368
SC		 5622 return IRQ_HANDLED;
5623}
5624
a9a3a273
SC		 5625/* Send a message CDB to the firmware. Careful, this only works
5626 * in simple mode, not performant mode due to the tag lookup.
5627 * We only ever use this immediately after a controller reset.
5628 */
6f039790
GKH		 5629static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5630 unsigned char type)
edd16368
SC		 5631{
5632 struct Command {
5633 struct CommandListHeader CommandHeader;
5634 struct RequestBlock Request;
5635 struct ErrDescriptor ErrorDescriptor;
5636 };
5637 struct Command *cmd;
5638 static const size_t cmd_sz = sizeof(*cmd) +
5639 sizeof(cmd->ErrorDescriptor);
5640 dma_addr_t paddr64;
5641 uint32_t paddr32, tag;
5642 void __iomem *vaddr;
5643 int i, err;
5644
5645 vaddr = pci_ioremap_bar(pdev, 0);
5646 if (vaddr == NULL)
5647 return -ENOMEM;
5648
5649 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5650 * CCISS commands, so they must be allocated from the lower 4GiB of
5651 * memory.
5652 */
5653 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5654 if (err) {
5655 iounmap(vaddr);
5656 return -ENOMEM;
5657 }
5658
5659 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5660 if (cmd == NULL) {
5661 iounmap(vaddr);
5662 return -ENOMEM;
5663 }
5664
5665 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5666 * although there's no guarantee, we assume that the address is at
5667 * least 4-byte aligned (most likely, it's page-aligned).
5668 */
5669 paddr32 = paddr64;
5670
5671 cmd->CommandHeader.ReplyQueue = 0;
5672 cmd->CommandHeader.SGList = 0;
5673 cmd->CommandHeader.SGTotal = 0;
5674 cmd->CommandHeader.Tag.lower = paddr32;
5675 cmd->CommandHeader.Tag.upper = 0;
5676 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5677
5678 cmd->Request.CDBLen = 16;
5679 cmd->Request.Type.Type = TYPE_MSG;
5680 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5681 cmd->Request.Type.Direction = XFER_NONE;
5682 cmd->Request.Timeout = 0; /* Don't time out */
5683 cmd->Request.CDB[0] = opcode;
5684 cmd->Request.CDB[1] = type;
5685 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5686 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5687 cmd->ErrorDescriptor.Addr.upper = 0;
5688 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5689
5690 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5691
5692 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5693 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5694 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5695 break;
5696 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5697 }
5698
5699 iounmap(vaddr);
5700
5701 /* we leak the DMA buffer here ... no choice since the controller could
5702 * still complete the command.
5703 */
5704 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5705 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5706 opcode, type);
5707 return -ETIMEDOUT;
5708 }
5709
5710 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5711
5712 if (tag & HPSA_ERROR_BIT) {
5713 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5714 opcode, type);
5715 return -EIO;
5716 }
5717
5718 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5719 opcode, type);
5720 return 0;
5721}
5722
edd16368
SC		 5723#define hpsa_noop(p) hpsa_message(p, 3, 0)
5724
1df8552a 5725static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5726 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5727{
5728 u16 pmcsr;
5729 int pos;
5730
5731 if (use_doorbell) {
5732 /* For everything after the P600, the PCI power state method
5733 * of resetting the controller doesn't work, so we have this
5734 * other way using the doorbell register.
5735 */
5736 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5737 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5738
5739 /* PMC hardware guys tell us we need a 5 second delay after
5740 * doorbell reset and before any attempt to talk to the board
5741 * at all to ensure that this actually works and doesn't fall
5742 * over in some weird corner cases.
5743 */
5744 msleep(5000);
1df8552a
SC		 5745 } else { /* Try to do it the PCI power state way */
5746
5747 /* Quoting from the Open CISS Specification: "The Power
5748 * Management Control/Status Register (CSR) controls the power
5749 * state of the device. The normal operating state is D0,
5750 * CSR=00h. The software off state is D3, CSR=03h. To reset
5751 * the controller, place the interface device in D3 then to D0,
5752 * this causes a secondary PCI reset which will reset the
5753 * controller." */
5754
5755 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5756 if (pos == 0) {
5757 dev_err(&pdev->dev,
5758 "hpsa_reset_controller: "
5759 "PCI PM not supported\n");
5760 return -ENODEV;
5761 }
5762 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5763 /* enter the D3hot power management state */
5764 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5765 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5766 pmcsr |= PCI_D3hot;
5767 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5768
5769 msleep(500);
5770
5771 /* enter the D0 power management state */
5772 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5773 pmcsr |= PCI_D0;
5774 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5775
5776 /*
5777 * The P600 requires a small delay when changing states.
5778 * Otherwise we may think the board did not reset and we bail.
5779 * This for kdump only and is particular to the P600.
5780 */
5781 msleep(500);
1df8552a
SC		 5782 }
5783 return 0;
5784}
5785
6f039790 5786static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5787{
5788 memset(driver_version, 0, len);
f79cfec6 5789 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5790}
5791
6f039790 5792static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5793{
5794 char *driver_version;
5795 int i, size = sizeof(cfgtable->driver_version);
5796
5797 driver_version = kmalloc(size, GFP_KERNEL);
5798 if (!driver_version)
5799 return -ENOMEM;
5800
5801 init_driver_version(driver_version, size);
5802 for (i = 0; i < size; i++)
5803 writeb(driver_version[i], &cfgtable->driver_version[i]);
5804 kfree(driver_version);
5805 return 0;
5806}
5807
6f039790
GKH		 5808static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5809 unsigned char *driver_ver)
580ada3c
SC		 5810{
5811 int i;
5812
5813 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5814 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5815}
5816
6f039790 5817static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5818{
5819
5820 char *driver_ver, *old_driver_ver;
5821 int rc, size = sizeof(cfgtable->driver_version);
5822
5823 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5824 if (!old_driver_ver)
5825 return -ENOMEM;
5826 driver_ver = old_driver_ver + size;
5827
5828 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5829 * should have been changed, otherwise we know the reset failed.
5830 */
5831 init_driver_version(old_driver_ver, size);
5832 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5833 rc = !memcmp(driver_ver, old_driver_ver, size);
5834 kfree(old_driver_ver);
5835 return rc;
5836}
edd16368 5837/* This does a hard reset of the controller using PCI power management
1df8552a 5838 * states or the using the doorbell register.
edd16368 5839 */
6f039790 5840static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5841{
1df8552a
SC		 5842 u64 cfg_offset;
5843 u32 cfg_base_addr;
5844 u64 cfg_base_addr_index;
5845 void __iomem *vaddr;
5846 unsigned long paddr;
580ada3c 5847 u32 misc_fw_support;
270d05de 5848 int rc;
1df8552a 5849 struct CfgTable __iomem *cfgtable;
cf0b08d0 5850 u32 use_doorbell;
18867659 5851 u32 board_id;
270d05de 5852 u16 command_register;
edd16368 5853
1df8552a
SC		 5854 /* For controllers as old as the P600, this is very nearly
5855 * the same thing as
edd16368
SC		 5856 *
5857 * pci_save_state(pci_dev);
5858 * pci_set_power_state(pci_dev, PCI_D3hot);
5859 * pci_set_power_state(pci_dev, PCI_D0);
5860 * pci_restore_state(pci_dev);
5861 *
1df8552a
SC		 5862 * For controllers newer than the P600, the pci power state
5863 * method of resetting doesn't work so we have another way
5864 * using the doorbell register.
edd16368 5865 */
18867659 5866
25c1e56a 5867 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5868 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5869 dev_warn(&pdev->dev, "Not resetting device.\n");
5870 return -ENODEV;
5871 }
46380786
SC		 5872
5873 /* if controller is soft- but not hard resettable... */
5874 if (!ctlr_is_hard_resettable(board_id))
5875 return -ENOTSUPP; /* try soft reset later. */
18867659 5876
270d05de
SC		 5877 /* Save the PCI command register */
5878 pci_read_config_word(pdev, 4, &command_register);
5879 /* Turn the board off. This is so that later pci_restore_state()
5880 * won't turn the board on before the rest of config space is ready.
5881 */
5882 pci_disable_device(pdev);
5883 pci_save_state(pdev);
edd16368 5884
1df8552a
SC		 5885 /* find the first memory BAR, so we can find the cfg table */
5886 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5887 if (rc)
5888 return rc;
5889 vaddr = remap_pci_mem(paddr, 0x250);
5890 if (!vaddr)
5891 return -ENOMEM;
edd16368 5892
1df8552a
SC		 5893 /* find cfgtable in order to check if reset via doorbell is supported */
5894 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5895 &cfg_base_addr_index, &cfg_offset);
5896 if (rc)
5897 goto unmap_vaddr;
5898 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5899 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5900 if (!cfgtable) {
5901 rc = -ENOMEM;
5902 goto unmap_vaddr;
5903 }
580ada3c
SC		 5904 rc = write_driver_ver_to_cfgtable(cfgtable);
5905 if (rc)
5906 goto unmap_vaddr;
edd16368 5907
cf0b08d0
SC		 5908 /* If reset via doorbell register is supported, use that.
5909 * There are two such methods. Favor the newest method.
5910 */
1df8552a 5911 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5912 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5913 if (use_doorbell) {
5914 use_doorbell = DOORBELL_CTLR_RESET2;
5915 } else {
5916 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5917 if (use_doorbell) {
fba63097
MM		 5918 dev_warn(&pdev->dev, "Soft reset not supported. "
5919 "Firmware update is required.\n");
64670ac8 5920 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5921 goto unmap_cfgtable;
5922 }
5923 }
edd16368 5924
1df8552a
SC		 5925 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5926 if (rc)
5927 goto unmap_cfgtable;
edd16368 5928
270d05de
SC		 5929 pci_restore_state(pdev);
5930 rc = pci_enable_device(pdev);
5931 if (rc) {
5932 dev_warn(&pdev->dev, "failed to enable device.\n");
5933 goto unmap_cfgtable;
edd16368 5934 }
270d05de 5935 pci_write_config_word(pdev, 4, command_register);
edd16368 5936
1df8552a
SC		 5937 /* Some devices (notably the HP Smart Array 5i Controller)
5938 need a little pause here */
5939 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5940
fe5389c8
SC		 5941 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5942 if (rc) {
5943 dev_warn(&pdev->dev,
64670ac8
SC		 5944 "failed waiting for board to become ready "
5945 "after hard reset\n");
fe5389c8
SC		 5946 goto unmap_cfgtable;
5947 }
fe5389c8 5948
580ada3c
SC		 5949 rc = controller_reset_failed(vaddr);
5950 if (rc < 0)
5951 goto unmap_cfgtable;
5952 if (rc) {
64670ac8
SC		 5953 dev_warn(&pdev->dev, "Unable to successfully reset "
5954 "controller. Will try soft reset.\n");
5955 rc = -ENOTSUPP;
580ada3c 5956 } else {
64670ac8 5957 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5958 }
5959
5960unmap_cfgtable:
5961 iounmap(cfgtable);
5962
5963unmap_vaddr:
5964 iounmap(vaddr);
5965 return rc;
edd16368
SC		 5966}
5967
5968/*
5969 * We cannot read the structure directly, for portability we must use
5970 * the io functions.
5971 * This is for debug only.
5972 */
edd16368
SC		 5973static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5974{
58f8665c 5975#ifdef HPSA_DEBUG
edd16368
SC		 5976 int i;
5977 char temp_name[17];
5978
5979 dev_info(dev, "Controller Configuration information\n");
5980 dev_info(dev, "------------------------------------\n");
5981 for (i = 0; i < 4; i++)
5982 temp_name[i] = readb(&(tb->Signature[i]));
5983 temp_name[4] = '\0';
5984 dev_info(dev, " Signature = %s\n", temp_name);
5985 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5986 dev_info(dev, " Transport methods supported = 0x%x\n",
5987 readl(&(tb->TransportSupport)));
5988 dev_info(dev, " Transport methods active = 0x%x\n",
5989 readl(&(tb->TransportActive)));
5990 dev_info(dev, " Requested transport Method = 0x%x\n",
5991 readl(&(tb->HostWrite.TransportRequest)));
5992 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5993 readl(&(tb->HostWrite.CoalIntDelay)));
5994 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5995 readl(&(tb->HostWrite.CoalIntCount)));
5996 dev_info(dev, " Max outstanding commands = 0x%d\n",
5997 readl(&(tb->CmdsOutMax)));
5998 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5999 for (i = 0; i < 16; i++)
6000 temp_name[i] = readb(&(tb->ServerName[i]));
6001 temp_name[16] = '\0';
6002 dev_info(dev, " Server Name = %s\n", temp_name);
6003 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6004 readl(&(tb->HeartBeat)));
edd16368 6005#endif /* HPSA_DEBUG */
58f8665c 6006}
edd16368
SC		 6007
6008static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6009{
6010 int i, offset, mem_type, bar_type;
6011
6012 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6013 return 0;
6014 offset = 0;
6015 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6016 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6017 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6018 offset += 4;
6019 else {
6020 mem_type = pci_resource_flags(pdev, i) &
6021 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6022 switch (mem_type) {
6023 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6024 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6025 offset += 4; /* 32 bit */
6026 break;
6027 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6028 offset += 8;
6029 break;
6030 default: /* reserved in PCI 2.2 */
6031 dev_warn(&pdev->dev,
6032 "base address is invalid\n");
6033 return -1;
6034 break;
6035 }
6036 }
6037 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6038 return i + 1;
6039 }
6040 return -1;
6041}
6042
6043/* If MSI/MSI-X is supported by the kernel we will try to enable it on
6044 * controllers that are capable. If not, we use IO-APIC mode.
6045 */
6046
6f039790 6047static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6048{
6049#ifdef CONFIG_PCI_MSI
254f796b
MG		 6050 int err, i;
6051 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6052
6053 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6054 hpsa_msix_entries[i].vector = 0;
6055 hpsa_msix_entries[i].entry = i;
6056 }
edd16368
SC		 6057
6058 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6059 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6060 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6061 goto default_int_mode;
55c06c71
SC		 6062 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
6063 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 6064 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 6065 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 6066 h->msix_vector);
edd16368 6067 if (err > 0) {
55c06c71 6068 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6069 "available\n", err);
eee0f03a
HR		 6070 h->msix_vector = err;
6071 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
6072 h->msix_vector);
6073 }
6074 if (!err) {
6075 for (i = 0; i < h->msix_vector; i++)
6076 h->intr[i] = hpsa_msix_entries[i].vector;
6077 return;
edd16368 6078 } else {
55c06c71 6079 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 6080 err);
eee0f03a 6081 h->msix_vector = 0;
edd16368
SC		 6082 goto default_int_mode;
6083 }
6084 }
55c06c71
SC		 6085 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
6086 dev_info(&h->pdev->dev, "MSI\n");
6087 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6088 h->msi_vector = 1;
6089 else
55c06c71 6090 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6091 }
6092default_int_mode:
6093#endif /* CONFIG_PCI_MSI */
6094 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6095 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6096}
6097
6f039790 6098static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6099{
6100 int i;
6101 u32 subsystem_vendor_id, subsystem_device_id;
6102
6103 subsystem_vendor_id = pdev->subsystem_vendor;
6104 subsystem_device_id = pdev->subsystem_device;
6105 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6106 subsystem_vendor_id;
6107
6108 for (i = 0; i < ARRAY_SIZE(products); i++)
6109 if (*board_id == products[i].board_id)
6110 return i;
6111
6798cc0a
SC		 6112 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6113 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6114 !hpsa_allow_any) {
e5c880d1
SC		 6115 dev_warn(&pdev->dev, "unrecognized board ID: "
6116 "0x%08x, ignoring.\n", *board_id);
6117 return -ENODEV;
6118 }
6119 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6120}
6121
6f039790
GKH		 6122static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6123 unsigned long *memory_bar)
3a7774ce
SC		 6124{
6125 int i;
6126
6127 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6128 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6129 /* addressing mode bits already removed */
12d2cd47
SC		 6130 *memory_bar = pci_resource_start(pdev, i);
6131 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6132 *memory_bar);
6133 return 0;
6134 }
12d2cd47 6135 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6136 return -ENODEV;
6137}
6138
6f039790
GKH		 6139static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6140 int wait_for_ready)
2c4c8c8b 6141{
fe5389c8 6142 int i, iterations;
2c4c8c8b 6143 u32 scratchpad;
fe5389c8
SC		 6144 if (wait_for_ready)
6145 iterations = HPSA_BOARD_READY_ITERATIONS;
6146 else
6147 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6148
fe5389c8
SC		 6149 for (i = 0; i < iterations; i++) {
6150 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6151 if (wait_for_ready) {
6152 if (scratchpad == HPSA_FIRMWARE_READY)
6153 return 0;
6154 } else {
6155 if (scratchpad != HPSA_FIRMWARE_READY)
6156 return 0;
6157 }
2c4c8c8b
SC		 6158 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6159 }
fe5389c8 6160 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6161 return -ENODEV;
6162}
6163
6f039790
GKH		 6164static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6165 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6166 u64 *cfg_offset)
a51fd47f
SC		 6167{
6168 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6169 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6170 *cfg_base_addr &= (u32) 0x0000ffff;
6171 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6172 if (*cfg_base_addr_index == -1) {
6173 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6174 return -ENODEV;
6175 }
6176 return 0;
6177}
6178
6f039790 6179static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6180{
01a02ffc
SC		 6181 u64 cfg_offset;
6182 u32 cfg_base_addr;
6183 u64 cfg_base_addr_index;
303932fd 6184 u32 trans_offset;
a51fd47f 6185 int rc;
77c4495c 6186
a51fd47f
SC		 6187 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6188 &cfg_base_addr_index, &cfg_offset);
6189 if (rc)
6190 return rc;
77c4495c 6191 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6192 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 6193 if (!h->cfgtable)
6194 return -ENOMEM;
580ada3c
SC		 6195 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6196 if (rc)
6197 return rc;
77c4495c 6198 /* Find performant mode table. */
a51fd47f 6199 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6200 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6201 cfg_base_addr_index)+cfg_offset+trans_offset,
6202 sizeof(*h->transtable));
6203 if (!h->transtable)
6204 return -ENOMEM;
6205 return 0;
6206}
6207
6f039790 6208static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 6209{
6210 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 6211
6212 /* Limit commands in memory limited kdump scenario. */
6213 if (reset_devices && h->max_commands > 32)
6214 h->max_commands = 32;
6215
cba3d38b
SC		 6216 if (h->max_commands < 16) {
6217 dev_warn(&h->pdev->dev, "Controller reports "
6218 "max supported commands of %d, an obvious lie. "
6219 "Using 16. Ensure that firmware is up to date.\n",
6220 h->max_commands);
6221 h->max_commands = 16;
6222 }
6223}
6224
b93d7536
SC		 6225/* Interrogate the hardware for some limits:
6226 * max commands, max SG elements without chaining, and with chaining,
6227 * SG chain block size, etc.
6228 */
6f039790 6229static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6230{
cba3d38b 6231 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 6232 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
6233 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6234 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 6235 /*
6236 * Limit in-command s/g elements to 32 save dma'able memory.
6237 * Howvever spec says if 0, use 31
6238 */
6239 h->max_cmd_sg_entries = 31;
6240 if (h->maxsgentries > 512) {
6241 h->max_cmd_sg_entries = 32;
6242 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
6243 h->maxsgentries--; /* save one for chain pointer */
6244 } else {
6245 h->maxsgentries = 31; /* default to traditional values */
6246 h->chainsize = 0;
6247 }
75167d2c
SC		 6248
6249 /* Find out what task management functions are supported and cache */
6250 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6251 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6252 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6253 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6254 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6255}
6256
76c46e49
SC		 6257static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6258{
0fc9fd40 6259 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6260 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6261 return false;
6262 }
6263 return true;
6264}
6265
97a5e98c 6266static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6267{
97a5e98c 6268 u32 driver_support;
f7c39101 6269
28e13446
SC		 6270#ifdef CONFIG_X86
6271 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6272 driver_support = readl(&(h->cfgtable->driver_support));
6273 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6274#endif
28e13446
SC		 6275 driver_support |= ENABLE_UNIT_ATTN;
6276 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6277}
6278
3d0eab67
SC		 6279/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6280 * in a prefetch beyond physical memory.
6281 */
6282static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6283{
6284 u32 dma_prefetch;
6285
6286 if (h->board_id != 0x3225103C)
6287 return;
6288 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6289 dma_prefetch |= 0x8000;
6290 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6291}
6292
76438d08
SC		 6293static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6294{
6295 int i;
6296 u32 doorbell_value;
6297 unsigned long flags;
6298 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6299 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6300 spin_lock_irqsave(&h->lock, flags);
6301 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6302 spin_unlock_irqrestore(&h->lock, flags);
6303 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6304 break;
6305 /* delay and try again */
6306 msleep(20);
6307 }
6308}
6309
6f039790 6310static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6311{
6312 int i;
6eaf46fd
SC		 6313 u32 doorbell_value;
6314 unsigned long flags;
eb6b2ae9
SC		 6315
6316 /* under certain very rare conditions, this can take awhile.
6317 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6318 * as we enter this code.)
6319 */
6320 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6321 spin_lock_irqsave(&h->lock, flags);
6322 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6323 spin_unlock_irqrestore(&h->lock, flags);
382be668 6324 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6325 break;
6326 /* delay and try again */
60d3f5b0 6327 usleep_range(10000, 20000);
eb6b2ae9 6328 }
3f4336f3
SC		 6329}
6330
6f039790 6331static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6332{
6333 u32 trans_support;
6334
6335 trans_support = readl(&(h->cfgtable->TransportSupport));
6336 if (!(trans_support & SIMPLE_MODE))
6337 return -ENOTSUPP;
6338
6339 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6340
3f4336f3
SC		 6341 /* Update the field, and then ring the doorbell */
6342 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6343 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6344 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6345 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6346 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6347 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6348 goto error;
960a30e7 6349 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6350 return 0;
283b4a9b
SC		 6351error:
6352 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6353 return -ENODEV;
eb6b2ae9
SC		 6354}
6355
6f039790 6356static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6357{
eb6b2ae9 6358 int prod_index, err;
edd16368 6359
e5c880d1
SC		 6360 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6361 if (prod_index < 0)
6362 return -ENODEV;
6363 h->product_name = products[prod_index].product_name;
6364 h->access = *(products[prod_index].access);
edd16368 6365
e5a44df8
MG		 6366 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6367 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6368
55c06c71 6369 err = pci_enable_device(h->pdev);
edd16368 6370 if (err) {
55c06c71 6371 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6372 return err;
6373 }
6374
5cb460a6
SC		 6375 /* Enable bus mastering (pci_disable_device may disable this) */
6376 pci_set_master(h->pdev);
6377
f79cfec6 6378 err = pci_request_regions(h->pdev, HPSA);
edd16368 6379 if (err) {
55c06c71
SC		 6380 dev_err(&h->pdev->dev,
6381 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6382 return err;
6383 }
6b3f4c52 6384 hpsa_interrupt_mode(h);
12d2cd47 6385 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6386 if (err)
edd16368 6387 goto err_out_free_res;
edd16368 6388 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6389 if (!h->vaddr) {
6390 err = -ENOMEM;
6391 goto err_out_free_res;
6392 }
fe5389c8 6393 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6394 if (err)
edd16368 6395 goto err_out_free_res;
77c4495c
SC		 6396 err = hpsa_find_cfgtables(h);
6397 if (err)
edd16368 6398 goto err_out_free_res;
b93d7536 6399 hpsa_find_board_params(h);
edd16368 6400
76c46e49 6401 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6402 err = -ENODEV;
6403 goto err_out_free_res;
6404 }
97a5e98c 6405 hpsa_set_driver_support_bits(h);
3d0eab67 6406 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6407 err = hpsa_enter_simple_mode(h);
6408 if (err)
edd16368 6409 goto err_out_free_res;
edd16368
SC		 6410 return 0;
6411
6412err_out_free_res:
204892e9
SC		 6413 if (h->transtable)
6414 iounmap(h->transtable);
6415 if (h->cfgtable)
6416 iounmap(h->cfgtable);
6417 if (h->vaddr)
6418 iounmap(h->vaddr);
f0bd0b68 6419 pci_disable_device(h->pdev);
55c06c71 6420 pci_release_regions(h->pdev);
edd16368
SC		 6421 return err;
6422}
6423
6f039790 6424static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6425{
6426 int rc;
6427
6428#define HBA_INQUIRY_BYTE_COUNT 64
6429 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6430 if (!h->hba_inquiry_data)
6431 return;
6432 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6433 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6434 if (rc != 0) {
6435 kfree(h->hba_inquiry_data);
6436 h->hba_inquiry_data = NULL;
6437 }
6438}
6439
6f039790 6440static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6441{
1df8552a 6442 int rc, i;
4c2a8c40
SC		 6443
6444 if (!reset_devices)
6445 return 0;
6446
1df8552a
SC		 6447 /* Reset the controller with a PCI power-cycle or via doorbell */
6448 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6449
1df8552a
SC		 6450 /* -ENOTSUPP here means we cannot reset the controller
6451 * but it's already (and still) up and running in
18867659
SC		 6452 * "performant mode". Or, it might be 640x, which can't reset
6453 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6454 */
6455 if (rc == -ENOTSUPP)
64670ac8 6456 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6457 if (rc)
6458 return -ENODEV;
4c2a8c40
SC		 6459
6460 /* Now try to get the controller to respond to a no-op */
2b870cb3 6461 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6462 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6463 if (hpsa_noop(pdev) == 0)
6464 break;
6465 else
6466 dev_warn(&pdev->dev, "no-op failed%s\n",
6467 (i < 11 ? "; re-trying" : ""));
6468 }
6469 return 0;
6470}
6471
6f039790 6472static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6473{
6474 h->cmd_pool_bits = kzalloc(
6475 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6476 sizeof(unsigned long), GFP_KERNEL);
6477 h->cmd_pool = pci_alloc_consistent(h->pdev,
6478 h->nr_cmds * sizeof(*h->cmd_pool),
6479 &(h->cmd_pool_dhandle));
6480 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6481 h->nr_cmds * sizeof(*h->errinfo_pool),
6482 &(h->errinfo_pool_dhandle));
6483 if ((h->cmd_pool_bits == NULL)
6484 || (h->cmd_pool == NULL)
6485 || (h->errinfo_pool == NULL)) {
6486 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6487 return -ENOMEM;
6488 }
6489 return 0;
6490}
6491
6492static void hpsa_free_cmd_pool(struct ctlr_info *h)
6493{
6494 kfree(h->cmd_pool_bits);
6495 if (h->cmd_pool)
6496 pci_free_consistent(h->pdev,
6497 h->nr_cmds * sizeof(struct CommandList),
6498 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6499 if (h->ioaccel2_cmd_pool)
6500 pci_free_consistent(h->pdev,
6501 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6502 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6503 if (h->errinfo_pool)
6504 pci_free_consistent(h->pdev,
6505 h->nr_cmds * sizeof(struct ErrorInfo),
6506 h->errinfo_pool,
6507 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6508 if (h->ioaccel_cmd_pool)
6509 pci_free_consistent(h->pdev,
6510 h->nr_cmds * sizeof(struct io_accel1_cmd),
6511 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6512}
6513
0ae01a32
SC		 6514static int hpsa_request_irq(struct ctlr_info *h,
6515 irqreturn_t (*msixhandler)(int, void *),
6516 irqreturn_t (*intxhandler)(int, void *))
6517{
254f796b 6518 int rc, i;
0ae01a32 6519
254f796b
MG		 6520 /*
6521 * initialize h->q[x] = x so that interrupt handlers know which
6522 * queue to process.
6523 */
6524 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6525 h->q[i] = (u8) i;
6526
eee0f03a 6527 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6528 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6529 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6530 rc = request_irq(h->intr[i], msixhandler,
6531 0, h->devname,
6532 &h->q[i]);
6533 } else {
6534 /* Use single reply pool */
eee0f03a 6535 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6536 rc = request_irq(h->intr[h->intr_mode],
6537 msixhandler, 0, h->devname,
6538 &h->q[h->intr_mode]);
6539 } else {
6540 rc = request_irq(h->intr[h->intr_mode],
6541 intxhandler, IRQF_SHARED, h->devname,
6542 &h->q[h->intr_mode]);
6543 }
6544 }
0ae01a32
SC		 6545 if (rc) {
6546 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6547 h->intr[h->intr_mode], h->devname);
6548 return -ENODEV;
6549 }
6550 return 0;
6551}
6552
6f039790 6553static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6554{
6555 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6556 HPSA_RESET_TYPE_CONTROLLER)) {
6557 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6558 return -EIO;
6559 }
6560
6561 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6562 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6563 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6564 return -1;
6565 }
6566
6567 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6568 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6569 dev_warn(&h->pdev->dev, "Board failed to become ready "
6570 "after soft reset.\n");
6571 return -1;
6572 }
6573
6574 return 0;
6575}
6576
254f796b
MG		 6577static void free_irqs(struct ctlr_info *h)
6578{
6579 int i;
6580
6581 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6582 /* Single reply queue, only one irq to free */
6583 i = h->intr_mode;
6584 free_irq(h->intr[i], &h->q[i]);
6585 return;
6586 }
6587
eee0f03a 6588 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6589 free_irq(h->intr[i], &h->q[i]);
6590}
6591
0097f0f4 6592static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6593{
254f796b 6594 free_irqs(h);
64670ac8 6595#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6596 if (h->msix_vector) {
6597 if (h->pdev->msix_enabled)
6598 pci_disable_msix(h->pdev);
6599 } else if (h->msi_vector) {
6600 if (h->pdev->msi_enabled)
6601 pci_disable_msi(h->pdev);
6602 }
64670ac8 6603#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6604}
6605
6606static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6607{
6608 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6609 hpsa_free_sg_chain_blocks(h);
6610 hpsa_free_cmd_pool(h);
e1f7de0c 6611 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6612 kfree(h->blockFetchTable);
6613 pci_free_consistent(h->pdev, h->reply_pool_size,
6614 h->reply_pool, h->reply_pool_dhandle);
6615 if (h->vaddr)
6616 iounmap(h->vaddr);
6617 if (h->transtable)
6618 iounmap(h->transtable);
6619 if (h->cfgtable)
6620 iounmap(h->cfgtable);
6621 pci_release_regions(h->pdev);
6622 kfree(h);
6623}
6624
a0c12413
SC		 6625/* Called when controller lockup detected. */
6626static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6627{
6628 struct CommandList *c = NULL;
6629
6630 assert_spin_locked(&h->lock);
6631 /* Mark all outstanding commands as failed and complete them. */
6632 while (!list_empty(list)) {
6633 c = list_entry(list->next, struct CommandList, list);
6634 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6635 finish_cmd(c);
a0c12413
SC		 6636 }
6637}
6638
6639static void controller_lockup_detected(struct ctlr_info *h)
6640{
6641 unsigned long flags;
6642
a0c12413
SC		 6643 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6644 spin_lock_irqsave(&h->lock, flags);
6645 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6646 spin_unlock_irqrestore(&h->lock, flags);
6647 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6648 h->lockup_detected);
6649 pci_disable_device(h->pdev);
6650 spin_lock_irqsave(&h->lock, flags);
6651 fail_all_cmds_on_list(h, &h->cmpQ);
6652 fail_all_cmds_on_list(h, &h->reqQ);
6653 spin_unlock_irqrestore(&h->lock, flags);
6654}
6655
a0c12413
SC		 6656static void detect_controller_lockup(struct ctlr_info *h)
6657{
6658 u64 now;
6659 u32 heartbeat;
6660 unsigned long flags;
6661
a0c12413
SC		 6662 now = get_jiffies_64();
6663 /* If we've received an interrupt recently, we're ok. */
6664 if (time_after64(h->last_intr_timestamp +
e85c5974 6665 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6666 return;
6667
6668 /*
6669 * If we've already checked the heartbeat recently, we're ok.
6670 * This could happen if someone sends us a signal. We
6671 * otherwise don't care about signals in this thread.
6672 */
6673 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6674 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6675 return;
6676
6677 /* If heartbeat has not changed since we last looked, we're not ok. */
6678 spin_lock_irqsave(&h->lock, flags);
6679 heartbeat = readl(&h->cfgtable->HeartBeat);
6680 spin_unlock_irqrestore(&h->lock, flags);
6681 if (h->last_heartbeat == heartbeat) {
6682 controller_lockup_detected(h);
6683 return;
6684 }
6685
6686 /* We're ok. */
6687 h->last_heartbeat = heartbeat;
6688 h->last_heartbeat_timestamp = now;
6689}
6690
9846590e 6691static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 6692{
6693 int i;
6694 char *event_type;
6695
e863d68e
ST		 6696 /* Clear the driver-requested rescan flag */
6697 h->drv_req_rescan = 0;
6698
76438d08 6699 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6700 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6701 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6702 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6703 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6704
6705 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6706 event_type = "state change";
6707 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6708 event_type = "configuration change";
6709 /* Stop sending new RAID offload reqs via the IO accelerator */
6710 scsi_block_requests(h->scsi_host);
6711 for (i = 0; i < h->ndevices; i++)
6712 h->dev[i]->offload_enabled = 0;
23100dd9 6713 hpsa_drain_accel_commands(h);
76438d08
SC		 6714 /* Set 'accelerator path config change' bit */
6715 dev_warn(&h->pdev->dev,
6716 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6717 h->events, event_type);
6718 writel(h->events, &(h->cfgtable->clear_event_notify));
6719 /* Set the "clear event notify field update" bit 6 */
6720 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6721 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6722 hpsa_wait_for_clear_event_notify_ack(h);
6723 scsi_unblock_requests(h->scsi_host);
6724 } else {
6725 /* Acknowledge controller notification events. */
6726 writel(h->events, &(h->cfgtable->clear_event_notify));
6727 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6728 hpsa_wait_for_clear_event_notify_ack(h);
6729#if 0
6730 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6731 hpsa_wait_for_mode_change_ack(h);
6732#endif
6733 }
9846590e 6734 return;
76438d08
SC		 6735}
6736
6737/* Check a register on the controller to see if there are configuration
6738 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6739 * we should rescan the controller for devices.
6740 * Also check flag for driver-initiated rescan.
76438d08 6741 */
9846590e 6742static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 6743{
9846590e
SC		 6744 if (h->drv_req_rescan)
6745 return 1;
6746
76438d08 6747 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 6748 return 0;
76438d08
SC		 6749
6750 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 6751 return h->events & RESCAN_REQUIRED_EVENT_BITS;
6752}
76438d08 6753
9846590e
SC		 6754/*
6755 * Check if any of the offline devices have become ready
6756 */
6757static int hpsa_offline_devices_ready(struct ctlr_info *h)
6758{
6759 unsigned long flags;
6760 struct offline_device_entry *d;
6761 struct list_head *this, *tmp;
6762
6763 spin_lock_irqsave(&h->offline_device_lock, flags);
6764 list_for_each_safe(this, tmp, &h->offline_device_list) {
6765 d = list_entry(this, struct offline_device_entry,
6766 offline_list);
6767 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6768 if (!hpsa_volume_offline(h, d->scsi3addr))
6769 return 1;
6770 spin_lock_irqsave(&h->offline_device_lock, flags);
6771 }
6772 spin_unlock_irqrestore(&h->offline_device_lock, flags);
6773 return 0;
76438d08
SC		 6774}
6775
9846590e 6776
8a98db73 6777static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6778{
6779 unsigned long flags;
8a98db73
SC		 6780 struct ctlr_info *h = container_of(to_delayed_work(work),
6781 struct ctlr_info, monitor_ctlr_work);
6782 detect_controller_lockup(h);
6783 if (h->lockup_detected)
6784 return;
9846590e
SC		 6785
6786 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
6787 scsi_host_get(h->scsi_host);
6788 h->drv_req_rescan = 0;
6789 hpsa_ack_ctlr_events(h);
6790 hpsa_scan_start(h->scsi_host);
6791 scsi_host_put(h->scsi_host);
6792 }
6793
8a98db73
SC		 6794 spin_lock_irqsave(&h->lock, flags);
6795 if (h->remove_in_progress) {
6796 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6797 return;
6798 }
8a98db73
SC		 6799 schedule_delayed_work(&h->monitor_ctlr_work,
6800 h->heartbeat_sample_interval);
6801 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6802}
6803
6f039790 6804static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6805{
4c2a8c40 6806 int dac, rc;
edd16368 6807 struct ctlr_info *h;
64670ac8
SC		 6808 int try_soft_reset = 0;
6809 unsigned long flags;
edd16368
SC		 6810
6811 if (number_of_controllers == 0)
6812 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6813
4c2a8c40 6814 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6815 if (rc) {
6816 if (rc != -ENOTSUPP)
6817 return rc;
6818 /* If the reset fails in a particular way (it has no way to do
6819 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6820 * a soft reset once we get the controller configured up to the
6821 * point that it can accept a command.
6822 */
6823 try_soft_reset = 1;
6824 rc = 0;
6825 }
6826
6827reinit_after_soft_reset:
edd16368 6828
303932fd
DB		 6829 /* Command structures must be aligned on a 32-byte boundary because
6830 * the 5 lower bits of the address are used by the hardware. and by
6831 * the driver. See comments in hpsa.h for more info.
6832 */
283b4a9b 6833#define COMMANDLIST_ALIGNMENT 128
303932fd 6834 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6835 h = kzalloc(sizeof(*h), GFP_KERNEL);
6836 if (!h)
ecd9aad4 6837 return -ENOMEM;
edd16368 6838
55c06c71 6839 h->pdev = pdev;
a9a3a273 6840 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6841 INIT_LIST_HEAD(&h->cmpQ);
6842 INIT_LIST_HEAD(&h->reqQ);
9846590e 6843 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 6844 spin_lock_init(&h->lock);
9846590e 6845 spin_lock_init(&h->offline_device_lock);
6eaf46fd 6846 spin_lock_init(&h->scan_lock);
0390f0c0 6847 spin_lock_init(&h->passthru_count_lock);
55c06c71 6848 rc = hpsa_pci_init(h);
ecd9aad4 6849 if (rc != 0)
edd16368
SC		 6850 goto clean1;
6851
f79cfec6 6852 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6853 h->ctlr = number_of_controllers;
6854 number_of_controllers++;
edd16368
SC		 6855
6856 /* configure PCI DMA stuff */
ecd9aad4
SC		 6857 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6858 if (rc == 0) {
edd16368 6859 dac = 1;
ecd9aad4
SC		 6860 } else {
6861 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6862 if (rc == 0) {
6863 dac = 0;
6864 } else {
6865 dev_err(&pdev->dev, "no suitable DMA available\n");
6866 goto clean1;
6867 }
edd16368
SC		 6868 }
6869
6870 /* make sure the board interrupts are off */
6871 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6872
0ae01a32 6873 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6874 goto clean2;
303932fd
DB		 6875 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6876 h->devname, pdev->device,
a9a3a273 6877 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6878 if (hpsa_allocate_cmd_pool(h))
edd16368 6879 goto clean4;
33a2ffce
SC		 6880 if (hpsa_allocate_sg_chain_blocks(h))
6881 goto clean4;
a08a8471
SC		 6882 init_waitqueue_head(&h->scan_wait_queue);
6883 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6884
6885 pci_set_drvdata(pdev, h);
9a41338e
SC		 6886 h->ndevices = 0;
6887 h->scsi_host = NULL;
6888 spin_lock_init(&h->devlock);
64670ac8
SC		 6889 hpsa_put_ctlr_into_performant_mode(h);
6890
6891 /* At this point, the controller is ready to take commands.
6892 * Now, if reset_devices and the hard reset didn't work, try
6893 * the soft reset and see if that works.
6894 */
6895 if (try_soft_reset) {
6896
6897 /* This is kind of gross. We may or may not get a completion
6898 * from the soft reset command, and if we do, then the value
6899 * from the fifo may or may not be valid. So, we wait 10 secs
6900 * after the reset throwing away any completions we get during
6901 * that time. Unregister the interrupt handler and register
6902 * fake ones to scoop up any residual completions.
6903 */
6904 spin_lock_irqsave(&h->lock, flags);
6905 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6906 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6907 free_irqs(h);
64670ac8
SC		 6908 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6909 hpsa_intx_discard_completions);
6910 if (rc) {
6911 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6912 "soft reset.\n");
6913 goto clean4;
6914 }
6915
6916 rc = hpsa_kdump_soft_reset(h);
6917 if (rc)
6918 /* Neither hard nor soft reset worked, we're hosed. */
6919 goto clean4;
6920
6921 dev_info(&h->pdev->dev, "Board READY.\n");
6922 dev_info(&h->pdev->dev,
6923 "Waiting for stale completions to drain.\n");
6924 h->access.set_intr_mask(h, HPSA_INTR_ON);
6925 msleep(10000);
6926 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6927
6928 rc = controller_reset_failed(h->cfgtable);
6929 if (rc)
6930 dev_info(&h->pdev->dev,
6931 "Soft reset appears to have failed.\n");
6932
6933 /* since the controller's reset, we have to go back and re-init
6934 * everything. Easiest to just forget what we've done and do it
6935 * all over again.
6936 */
6937 hpsa_undo_allocations_after_kdump_soft_reset(h);
6938 try_soft_reset = 0;
6939 if (rc)
6940 /* don't go to clean4, we already unallocated */
6941 return -ENODEV;
6942
6943 goto reinit_after_soft_reset;
6944 }
edd16368 6945
da0697bd
ST		 6946 /* Enable Accelerated IO path at driver layer */
6947 h->acciopath_status = 1;
6948
e863d68e
ST		 6949 h->drv_req_rescan = 0;
6950
edd16368
SC		 6951 /* Turn the interrupts on so we can service requests */
6952 h->access.set_intr_mask(h, HPSA_INTR_ON);
6953
339b2b14 6954 hpsa_hba_inquiry(h);
edd16368 6955 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6956
6957 /* Monitor the controller for firmware lockups */
6958 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6959 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6960 schedule_delayed_work(&h->monitor_ctlr_work,
6961 h->heartbeat_sample_interval);
88bf6d62 6962 return 0;
edd16368
SC		 6963
6964clean4:
33a2ffce 6965 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6966 hpsa_free_cmd_pool(h);
254f796b 6967 free_irqs(h);
edd16368
SC		 6968clean2:
6969clean1:
edd16368 6970 kfree(h);
ecd9aad4 6971 return rc;
edd16368
SC		 6972}
6973
6974static void hpsa_flush_cache(struct ctlr_info *h)
6975{
6976 char *flush_buf;
6977 struct CommandList *c;
702890e3
SC		 6978 unsigned long flags;
6979
6980 /* Don't bother trying to flush the cache if locked up */
6981 spin_lock_irqsave(&h->lock, flags);
6982 if (unlikely(h->lockup_detected)) {
6983 spin_unlock_irqrestore(&h->lock, flags);
6984 return;
6985 }
6986 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6987
6988 flush_buf = kzalloc(4, GFP_KERNEL);
6989 if (!flush_buf)
6990 return;
6991
6992 c = cmd_special_alloc(h);
6993 if (!c) {
6994 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6995 goto out_of_memory;
6996 }
a2dac136
SC		 6997 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6998 RAID_CTLR_LUNID, TYPE_CMD)) {
6999 goto out;
7000 }
edd16368
SC		 7001 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
7002 if (c->err_info->CommandStatus != 0)
a2dac136 7003out:
edd16368
SC		 7004 dev_warn(&h->pdev->dev,
7005 "error flushing cache on controller\n");
7006 cmd_special_free(h, c);
7007out_of_memory:
7008 kfree(flush_buf);
7009}
7010
7011static void hpsa_shutdown(struct pci_dev *pdev)
7012{
7013 struct ctlr_info *h;
7014
7015 h = pci_get_drvdata(pdev);
7016 /* Turn board interrupts off and send the flush cache command
7017 * sendcmd will turn off interrupt, and send the flush...
7018 * To write all data in the battery backed cache to disks
7019 */
7020 hpsa_flush_cache(h);
7021 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 7022 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 7023}
7024
6f039790 7025static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7026{
7027 int i;
7028
7029 for (i = 0; i < h->ndevices; i++)
7030 kfree(h->dev[i]);
7031}
7032
6f039790 7033static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7034{
7035 struct ctlr_info *h;
8a98db73 7036 unsigned long flags;
edd16368
SC		 7037
7038 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7039 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7040 return;
7041 }
7042 h = pci_get_drvdata(pdev);
8a98db73
SC		 7043
7044 /* Get rid of any controller monitoring work items */
7045 spin_lock_irqsave(&h->lock, flags);
7046 h->remove_in_progress = 1;
7047 cancel_delayed_work(&h->monitor_ctlr_work);
7048 spin_unlock_irqrestore(&h->lock, flags);
7049
edd16368
SC		 7050 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
7051 hpsa_shutdown(pdev);
7052 iounmap(h->vaddr);
204892e9
SC		 7053 iounmap(h->transtable);
7054 iounmap(h->cfgtable);
55e14e76 7055 hpsa_free_device_info(h);
33a2ffce 7056 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 7057 pci_free_consistent(h->pdev,
7058 h->nr_cmds * sizeof(struct CommandList),
7059 h->cmd_pool, h->cmd_pool_dhandle);
7060 pci_free_consistent(h->pdev,
7061 h->nr_cmds * sizeof(struct ErrorInfo),
7062 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 7063 pci_free_consistent(h->pdev, h->reply_pool_size,
7064 h->reply_pool, h->reply_pool_dhandle);
edd16368 7065 kfree(h->cmd_pool_bits);
303932fd 7066 kfree(h->blockFetchTable);
e1f7de0c 7067 kfree(h->ioaccel1_blockFetchTable);
aca9012a 7068 kfree(h->ioaccel2_blockFetchTable);
339b2b14 7069 kfree(h->hba_inquiry_data);
f0bd0b68 7070 pci_disable_device(pdev);
edd16368 7071 pci_release_regions(pdev);
edd16368
SC		 7072 kfree(h);
7073}
7074
7075static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7076 __attribute__((unused)) pm_message_t state)
7077{
7078 return -ENOSYS;
7079}
7080
7081static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7082{
7083 return -ENOSYS;
7084}
7085
7086static struct pci_driver hpsa_pci_driver = {
f79cfec6 7087 .name = HPSA,
edd16368 7088 .probe = hpsa_init_one,
6f039790 7089 .remove = hpsa_remove_one,
edd16368
SC		 7090 .id_table = hpsa_pci_device_id, /* id_table */
7091 .shutdown = hpsa_shutdown,
7092 .suspend = hpsa_suspend,
7093 .resume = hpsa_resume,
7094};
7095
303932fd
DB		 7096/* Fill in bucket_map[], given nsgs (the max number of
7097 * scatter gather elements supported) and bucket[],
7098 * which is an array of 8 integers. The bucket[] array
7099 * contains 8 different DMA transfer sizes (in 16
7100 * byte increments) which the controller uses to fetch
7101 * commands. This function fills in bucket_map[], which
7102 * maps a given number of scatter gather elements to one of
7103 * the 8 DMA transfer sizes. The point of it is to allow the
7104 * controller to only do as much DMA as needed to fetch the
7105 * command, with the DMA transfer size encoded in the lower
7106 * bits of the command address.
7107 */
7108static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 7109 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 7110{
7111 int i, j, b, size;
7112
303932fd
DB		 7113 /* Note, bucket_map must have nsgs+1 entries. */
7114 for (i = 0; i <= nsgs; i++) {
7115 /* Compute size of a command with i SG entries */
e1f7de0c 7116 size = i + min_blocks;
303932fd
DB		 7117 b = num_buckets; /* Assume the biggest bucket */
7118 /* Find the bucket that is just big enough */
e1f7de0c 7119 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7120 if (bucket[j] >= size) {
7121 b = j;
7122 break;
7123 }
7124 }
7125 /* for a command with i SG entries, use bucket b. */
7126 bucket_map[i] = b;
7127 }
7128}
7129
e1f7de0c 7130static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7131{
6c311b57
SC		 7132 int i;
7133 unsigned long register_value;
e1f7de0c
MG		 7134 unsigned long transMethod = CFGTBL_Trans_Performant |
7135 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7136 CFGTBL_Trans_enable_directed_msix |
7137 (trans_support & (CFGTBL_Trans_io_accel1 |
7138 CFGTBL_Trans_io_accel2));
e1f7de0c 7139 struct access_method access = SA5_performant_access;
def342bd
SC		 7140
7141 /* This is a bit complicated. There are 8 registers on
7142 * the controller which we write to to tell it 8 different
7143 * sizes of commands which there may be. It's a way of
7144 * reducing the DMA done to fetch each command. Encoded into
7145 * each command's tag are 3 bits which communicate to the controller
7146 * which of the eight sizes that command fits within. The size of
7147 * each command depends on how many scatter gather entries there are.
7148 * Each SG entry requires 16 bytes. The eight registers are programmed
7149 * with the number of 16-byte blocks a command of that size requires.
7150 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7151 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7152 * blocks. Note, this only extends to the SG entries contained
7153 * within the command block, and does not extend to chained blocks
7154 * of SG elements. bft[] contains the eight values we write to
7155 * the registers. They are not evenly distributed, but have more
7156 * sizes for small commands, and fewer sizes for larger commands.
7157 */
d66ae08b 7158 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7159#define MIN_IOACCEL2_BFT_ENTRY 5
7160#define HPSA_IOACCEL2_HEADER_SZ 4
7161 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7162 13, 14, 15, 16, 17, 18, 19,
7163 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7164 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7165 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7166 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7167 16 * MIN_IOACCEL2_BFT_ENTRY);
7168 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7169 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7170 /* 5 = 1 s/g entry or 4k
7171 * 6 = 2 s/g entry or 8k
7172 * 8 = 4 s/g entry or 16k
7173 * 10 = 6 s/g entry or 24k
7174 */
303932fd 7175
303932fd
DB		 7176 /* Controller spec: zero out this buffer. */
7177 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 7178
d66ae08b
SC		 7179 bft[7] = SG_ENTRIES_IN_CMD + 4;
7180 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7181 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7182 for (i = 0; i < 8; i++)
7183 writel(bft[i], &h->transtable->BlockFetch[i]);
7184
7185 /* size of controller ring buffer */
7186 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7187 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7188 writel(0, &h->transtable->RepQCtrAddrLow32);
7189 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7190
7191 for (i = 0; i < h->nreply_queues; i++) {
7192 writel(0, &h->transtable->RepQAddr[i].upper);
7193 writel(h->reply_pool_dhandle +
7194 (h->max_commands * sizeof(u64) * i),
7195 &h->transtable->RepQAddr[i].lower);
7196 }
7197
b9af4937 7198 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7199 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7200 /*
7201 * enable outbound interrupt coalescing in accelerator mode;
7202 */
7203 if (trans_support & CFGTBL_Trans_io_accel1) {
7204 access = SA5_ioaccel_mode1_access;
7205 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7206 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7207 } else {
7208 if (trans_support & CFGTBL_Trans_io_accel2) {
7209 access = SA5_ioaccel_mode2_access;
7210 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7211 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7212 }
e1f7de0c 7213 }
303932fd 7214 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 7215 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 7216 register_value = readl(&(h->cfgtable->TransportActive));
7217 if (!(register_value & CFGTBL_Trans_Performant)) {
7218 dev_warn(&h->pdev->dev, "unable to get board into"
7219 " performant mode\n");
7220 return;
7221 }
960a30e7 7222 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7223 h->access = access;
7224 h->transMethod = transMethod;
7225
b9af4937
SC		 7226 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7227 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 7228 return;
7229
b9af4937
SC		 7230 if (trans_support & CFGTBL_Trans_io_accel1) {
7231 /* Set up I/O accelerator mode */
7232 for (i = 0; i < h->nreply_queues; i++) {
7233 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7234 h->reply_queue[i].current_entry =
7235 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7236 }
7237 bft[7] = h->ioaccel_maxsg + 8;
7238 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7239 h->ioaccel1_blockFetchTable);
e1f7de0c 7240
b9af4937
SC		 7241 /* initialize all reply queue entries to unused */
7242 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
7243 h->reply_pool_size);
e1f7de0c 7244
b9af4937
SC		 7245 /* set all the constant fields in the accelerator command
7246 * frames once at init time to save CPU cycles later.
7247 */
7248 for (i = 0; i < h->nr_cmds; i++) {
7249 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7250
7251 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7252 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7253 (i * sizeof(struct ErrorInfo)));
7254 cp->err_info_len = sizeof(struct ErrorInfo);
7255 cp->sgl_offset = IOACCEL1_SGLOFFSET;
7256 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
7257 cp->timeout_sec = 0;
7258 cp->ReplyQueue = 0;
7259 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
7260 DIRECT_LOOKUP_BIT;
7261 cp->Tag.upper = 0;
7262 cp->host_addr.lower =
7263 (u32) (h->ioaccel_cmd_pool_dhandle +
7264 (i * sizeof(struct io_accel1_cmd)));
7265 cp->host_addr.upper = 0;
7266 }
7267 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7268 u64 cfg_offset, cfg_base_addr_index;
7269 u32 bft2_offset, cfg_base_addr;
7270 int rc;
7271
7272 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7273 &cfg_base_addr_index, &cfg_offset);
7274 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7275 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7276 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7277 4, h->ioaccel2_blockFetchTable);
7278 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7279 BUILD_BUG_ON(offsetof(struct CfgTable,
7280 io_accel_request_size_offset) != 0xb8);
7281 h->ioaccel2_bft2_regs =
7282 remap_pci_mem(pci_resource_start(h->pdev,
7283 cfg_base_addr_index) +
7284 cfg_offset + bft2_offset,
7285 ARRAY_SIZE(bft2) *
7286 sizeof(*h->ioaccel2_bft2_regs));
7287 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7288 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7289 }
b9af4937
SC		 7290 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7291 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7292}
7293
7294static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7295{
283b4a9b
SC		 7296 h->ioaccel_maxsg =
7297 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7298 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7299 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7300
e1f7de0c
MG		 7301 /* Command structures must be aligned on a 128-byte boundary
7302 * because the 7 lower bits of the address are used by the
7303 * hardware.
7304 */
7305#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
7306 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7307 IOACCEL1_COMMANDLIST_ALIGNMENT);
7308 h->ioaccel_cmd_pool =
7309 pci_alloc_consistent(h->pdev,
7310 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7311 &(h->ioaccel_cmd_pool_dhandle));
7312
7313 h->ioaccel1_blockFetchTable =
283b4a9b 7314 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7315 sizeof(u32)), GFP_KERNEL);
7316
7317 if ((h->ioaccel_cmd_pool == NULL) ||
7318 (h->ioaccel1_blockFetchTable == NULL))
7319 goto clean_up;
7320
7321 memset(h->ioaccel_cmd_pool, 0,
7322 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7323 return 0;
7324
7325clean_up:
7326 if (h->ioaccel_cmd_pool)
7327 pci_free_consistent(h->pdev,
7328 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7329 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7330 kfree(h->ioaccel1_blockFetchTable);
7331 return 1;
6c311b57
SC		 7332}
7333
aca9012a
SC		 7334static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7335{
7336 /* Allocate ioaccel2 mode command blocks and block fetch table */
7337
7338 h->ioaccel_maxsg =
7339 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7340 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7341 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7342
7343#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
7344 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7345 IOACCEL2_COMMANDLIST_ALIGNMENT);
7346 h->ioaccel2_cmd_pool =
7347 pci_alloc_consistent(h->pdev,
7348 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7349 &(h->ioaccel2_cmd_pool_dhandle));
7350
7351 h->ioaccel2_blockFetchTable =
7352 kmalloc(((h->ioaccel_maxsg + 1) *
7353 sizeof(u32)), GFP_KERNEL);
7354
7355 if ((h->ioaccel2_cmd_pool == NULL) ||
7356 (h->ioaccel2_blockFetchTable == NULL))
7357 goto clean_up;
7358
7359 memset(h->ioaccel2_cmd_pool, 0,
7360 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7361 return 0;
7362
7363clean_up:
7364 if (h->ioaccel2_cmd_pool)
7365 pci_free_consistent(h->pdev,
7366 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7367 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7368 kfree(h->ioaccel2_blockFetchTable);
7369 return 1;
7370}
7371
6f039790 7372static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7373{
7374 u32 trans_support;
e1f7de0c
MG		 7375 unsigned long transMethod = CFGTBL_Trans_Performant |
7376 CFGTBL_Trans_use_short_tags;
254f796b 7377 int i;
6c311b57 7378
02ec19c8
SC		 7379 if (hpsa_simple_mode)
7380 return;
7381
e1f7de0c
MG		 7382 /* Check for I/O accelerator mode support */
7383 if (trans_support & CFGTBL_Trans_io_accel1) {
7384 transMethod |= CFGTBL_Trans_io_accel1 |
7385 CFGTBL_Trans_enable_directed_msix;
7386 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7387 goto clean_up;
aca9012a
SC		 7388 } else {
7389 if (trans_support & CFGTBL_Trans_io_accel2) {
7390 transMethod |= CFGTBL_Trans_io_accel2 |
7391 CFGTBL_Trans_enable_directed_msix;
7392 if (ioaccel2_alloc_cmds_and_bft(h))
7393 goto clean_up;
7394 }
e1f7de0c
MG		 7395 }
7396
7397 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 7398 trans_support = readl(&(h->cfgtable->TransportSupport));
7399 if (!(trans_support & PERFORMANT_MODE))
7400 return;
7401
eee0f03a 7402 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7403 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7404 /* Performant mode ring buffer and supporting data structures */
254f796b 7405 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 7406 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
7407 &(h->reply_pool_dhandle));
7408
254f796b
MG		 7409 for (i = 0; i < h->nreply_queues; i++) {
7410 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
7411 h->reply_queue[i].size = h->max_commands;
7412 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7413 h->reply_queue[i].current_entry = 0;
7414 }
7415
6c311b57 7416 /* Need a block fetch table for performant mode */
d66ae08b 7417 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 7418 sizeof(u32)), GFP_KERNEL);
7419
7420 if ((h->reply_pool == NULL)
7421 || (h->blockFetchTable == NULL))
7422 goto clean_up;
7423
e1f7de0c 7424 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7425 return;
7426
7427clean_up:
7428 if (h->reply_pool)
7429 pci_free_consistent(h->pdev, h->reply_pool_size,
7430 h->reply_pool, h->reply_pool_dhandle);
7431 kfree(h->blockFetchTable);
7432}
7433
23100dd9 7434static int is_accelerated_cmd(struct CommandList *c)
76438d08 7435{
23100dd9
SC		 7436 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7437}
7438
7439static void hpsa_drain_accel_commands(struct ctlr_info *h)
7440{
7441 struct CommandList *c = NULL;
76438d08 7442 unsigned long flags;
23100dd9 7443 int accel_cmds_out;
76438d08
SC		 7444
7445 do { /* wait for all outstanding commands to drain out */
23100dd9 7446 accel_cmds_out = 0;
76438d08 7447 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7448 list_for_each_entry(c, &h->cmpQ, list)
7449 accel_cmds_out += is_accelerated_cmd(c);
7450 list_for_each_entry(c, &h->reqQ, list)
7451 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7452 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7453 if (accel_cmds_out <= 0)
76438d08
SC		 7454 break;
7455 msleep(100);
7456 } while (1);
7457}
7458
edd16368
SC		 7459/*
7460 * This is it. Register the PCI driver information for the cards we control
7461 * the OS will call our registered routines when it finds one of our cards.
7462 */
7463static int __init hpsa_init(void)
7464{
31468401 7465 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7466}
7467
7468static void __exit hpsa_cleanup(void)
7469{
7470 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7471}
7472
e1f7de0c
MG		 7473static void __attribute__((unused)) verify_offsets(void)
7474{
dd0e19f3
ST		 7475#define VERIFY_OFFSET(member, offset) \
7476 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7477
7478 VERIFY_OFFSET(structure_size, 0);
7479 VERIFY_OFFSET(volume_blk_size, 4);
7480 VERIFY_OFFSET(volume_blk_cnt, 8);
7481 VERIFY_OFFSET(phys_blk_shift, 16);
7482 VERIFY_OFFSET(parity_rotation_shift, 17);
7483 VERIFY_OFFSET(strip_size, 18);
7484 VERIFY_OFFSET(disk_starting_blk, 20);
7485 VERIFY_OFFSET(disk_blk_cnt, 28);
7486 VERIFY_OFFSET(data_disks_per_row, 36);
7487 VERIFY_OFFSET(metadata_disks_per_row, 38);
7488 VERIFY_OFFSET(row_cnt, 40);
7489 VERIFY_OFFSET(layout_map_count, 42);
7490 VERIFY_OFFSET(flags, 44);
7491 VERIFY_OFFSET(dekindex, 46);
7492 /* VERIFY_OFFSET(reserved, 48 */
7493 VERIFY_OFFSET(data, 64);
7494
7495#undef VERIFY_OFFSET
7496
b66cc250
MM		 7497#define VERIFY_OFFSET(member, offset) \
7498 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7499
7500 VERIFY_OFFSET(IU_type, 0);
7501 VERIFY_OFFSET(direction, 1);
7502 VERIFY_OFFSET(reply_queue, 2);
7503 /* VERIFY_OFFSET(reserved1, 3); */
7504 VERIFY_OFFSET(scsi_nexus, 4);
7505 VERIFY_OFFSET(Tag, 8);
7506 VERIFY_OFFSET(cdb, 16);
7507 VERIFY_OFFSET(cciss_lun, 32);
7508 VERIFY_OFFSET(data_len, 40);
7509 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7510 VERIFY_OFFSET(sg_count, 45);
7511 /* VERIFY_OFFSET(reserved3 */
7512 VERIFY_OFFSET(err_ptr, 48);
7513 VERIFY_OFFSET(err_len, 56);
7514 /* VERIFY_OFFSET(reserved4 */
7515 VERIFY_OFFSET(sg, 64);
7516
7517#undef VERIFY_OFFSET
7518
e1f7de0c
MG		 7519#define VERIFY_OFFSET(member, offset) \
7520 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7521
7522 VERIFY_OFFSET(dev_handle, 0x00);
7523 VERIFY_OFFSET(reserved1, 0x02);
7524 VERIFY_OFFSET(function, 0x03);
7525 VERIFY_OFFSET(reserved2, 0x04);
7526 VERIFY_OFFSET(err_info, 0x0C);
7527 VERIFY_OFFSET(reserved3, 0x10);
7528 VERIFY_OFFSET(err_info_len, 0x12);
7529 VERIFY_OFFSET(reserved4, 0x13);
7530 VERIFY_OFFSET(sgl_offset, 0x14);
7531 VERIFY_OFFSET(reserved5, 0x15);
7532 VERIFY_OFFSET(transfer_len, 0x1C);
7533 VERIFY_OFFSET(reserved6, 0x20);
7534 VERIFY_OFFSET(io_flags, 0x24);
7535 VERIFY_OFFSET(reserved7, 0x26);
7536 VERIFY_OFFSET(LUN, 0x34);
7537 VERIFY_OFFSET(control, 0x3C);
7538 VERIFY_OFFSET(CDB, 0x40);
7539 VERIFY_OFFSET(reserved8, 0x50);
7540 VERIFY_OFFSET(host_context_flags, 0x60);
7541 VERIFY_OFFSET(timeout_sec, 0x62);
7542 VERIFY_OFFSET(ReplyQueue, 0x64);
7543 VERIFY_OFFSET(reserved9, 0x65);
7544 VERIFY_OFFSET(Tag, 0x68);
7545 VERIFY_OFFSET(host_addr, 0x70);
7546 VERIFY_OFFSET(CISS_LUN, 0x78);
7547 VERIFY_OFFSET(SG, 0x78 + 8);
7548#undef VERIFY_OFFSET
7549}
7550
edd16368
SC		 7551module_init(hpsa_init);
7552module_exit(hpsa_cleanup);
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