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hpsa: disable report lun data caching
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
b48d9804 233#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 234
f281233d 235static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 236static void hpsa_scan_start(struct Scsi_Host *);
237static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
7c0a0229 239static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 240
241static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 242static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 243static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 244static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 245static void hpsa_slave_destroy(struct scsi_device *sdev);
246
8aa60681 247static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 248static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
303932fd
DB		 252/* performant mode helper functions */
253static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 254 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 255static void hpsa_free_performant_mode(struct ctlr_info *h);
256static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 257static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 258static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
75167d2c 266static inline void finish_cmd(struct CommandList *c);
c706a795 267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 268#define BOARD_NOT_READY 0
269#define BOARD_READY 1
23100dd9 270static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 271static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 272static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 275static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 276static u32 lockup_detected(struct ctlr_info *h);
277static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 278static void hpsa_disable_rld_caching(struct ctlr_info *h);
34592254 279static int hpsa_luns_changed(struct ctlr_info *h);
edd16368 280
edd16368
SC		 281static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
282{
283 unsigned long *priv = shost_priv(sdev->host);
284 return (struct ctlr_info *) *priv;
285}
286
a23513e8
SC		 287static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
288{
289 unsigned long *priv = shost_priv(sh);
290 return (struct ctlr_info *) *priv;
291}
292
a58e7e53
WS		 293static inline bool hpsa_is_cmd_idle(struct CommandList *c)
294{
295 return c->scsi_cmd == SCSI_CMD_IDLE;
296}
297
d604f533
WS		 298static inline bool hpsa_is_pending_event(struct CommandList *c)
299{
300 return c->abort_pending || c->reset_pending;
301}
302
9437ac43
SC		 303/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
304static void decode_sense_data(const u8 *sense_data, int sense_data_len,
305 u8 *sense_key, u8 *asc, u8 *ascq)
306{
307 struct scsi_sense_hdr sshdr;
308 bool rc;
309
310 *sense_key = -1;
311 *asc = -1;
312 *ascq = -1;
313
314 if (sense_data_len < 1)
315 return;
316
317 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
318 if (rc) {
319 *sense_key = sshdr.sense_key;
320 *asc = sshdr.asc;
321 *ascq = sshdr.ascq;
322 }
323}
324
edd16368
SC		 325static int check_for_unit_attention(struct ctlr_info *h,
326 struct CommandList *c)
327{
9437ac43
SC		 328 u8 sense_key, asc, ascq;
329 int sense_len;
330
331 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
332 sense_len = sizeof(c->err_info->SenseInfo);
333 else
334 sense_len = c->err_info->SenseLen;
335
336 decode_sense_data(c->err_info->SenseInfo, sense_len,
337 &sense_key, &asc, &ascq);
81c27557 338 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 339 return 0;
340
9437ac43 341 switch (asc) {
edd16368 342 case STATE_CHANGED:
9437ac43 343 dev_warn(&h->pdev->dev,
2946e82b
RE		 344 "%s: a state change detected, command retried\n",
345 h->devname);
edd16368
SC		 346 break;
347 case LUN_FAILED:
7f73695a 348 dev_warn(&h->pdev->dev,
2946e82b 349 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 350 break;
351 case REPORT_LUNS_CHANGED:
7f73695a 352 dev_warn(&h->pdev->dev,
2946e82b 353 "%s: report LUN data changed\n", h->devname);
edd16368 354 /*
4f4eb9f1
ST		 355 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
356 * target (array) devices.
edd16368
SC		 357 */
358 break;
359 case POWER_OR_RESET:
2946e82b
RE		 360 dev_warn(&h->pdev->dev,
361 "%s: a power on or device reset detected\n",
362 h->devname);
edd16368
SC		 363 break;
364 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 365 dev_warn(&h->pdev->dev,
366 "%s: unit attention cleared by another initiator\n",
367 h->devname);
edd16368
SC		 368 break;
369 default:
2946e82b
RE		 370 dev_warn(&h->pdev->dev,
371 "%s: unknown unit attention detected\n",
372 h->devname);
edd16368
SC		 373 break;
374 }
375 return 1;
376}
377
852af20a
MB		 378static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
379{
380 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
381 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
382 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
383 return 0;
384 dev_warn(&h->pdev->dev, HPSA "device busy");
385 return 1;
386}
387
e985c58f
SC		 388static u32 lockup_detected(struct ctlr_info *h);
389static ssize_t host_show_lockup_detected(struct device *dev,
390 struct device_attribute *attr, char *buf)
391{
392 int ld;
393 struct ctlr_info *h;
394 struct Scsi_Host *shost = class_to_shost(dev);
395
396 h = shost_to_hba(shost);
397 ld = lockup_detected(h);
398
399 return sprintf(buf, "ld=%d\n", ld);
400}
401
da0697bd
ST		 402static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
403 struct device_attribute *attr,
404 const char *buf, size_t count)
405{
406 int status, len;
407 struct ctlr_info *h;
408 struct Scsi_Host *shost = class_to_shost(dev);
409 char tmpbuf[10];
410
411 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
412 return -EACCES;
413 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
414 strncpy(tmpbuf, buf, len);
415 tmpbuf[len] = '\0';
416 if (sscanf(tmpbuf, "%d", &status) != 1)
417 return -EINVAL;
418 h = shost_to_hba(shost);
419 h->acciopath_status = !!status;
420 dev_warn(&h->pdev->dev,
421 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
422 h->acciopath_status ? "enabled" : "disabled");
423 return count;
424}
425
2ba8bfc8
SC		 426static ssize_t host_store_raid_offload_debug(struct device *dev,
427 struct device_attribute *attr,
428 const char *buf, size_t count)
429{
430 int debug_level, len;
431 struct ctlr_info *h;
432 struct Scsi_Host *shost = class_to_shost(dev);
433 char tmpbuf[10];
434
435 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
436 return -EACCES;
437 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
438 strncpy(tmpbuf, buf, len);
439 tmpbuf[len] = '\0';
440 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
441 return -EINVAL;
442 if (debug_level < 0)
443 debug_level = 0;
444 h = shost_to_hba(shost);
445 h->raid_offload_debug = debug_level;
446 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
447 h->raid_offload_debug);
448 return count;
449}
450
edd16368
SC		 451static ssize_t host_store_rescan(struct device *dev,
452 struct device_attribute *attr,
453 const char *buf, size_t count)
454{
455 struct ctlr_info *h;
456 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 457 h = shost_to_hba(shost);
31468401 458 hpsa_scan_start(h->scsi_host);
edd16368
SC		 459 return count;
460}
461
d28ce020
SC		 462static ssize_t host_show_firmware_revision(struct device *dev,
463 struct device_attribute *attr, char *buf)
464{
465 struct ctlr_info *h;
466 struct Scsi_Host *shost = class_to_shost(dev);
467 unsigned char *fwrev;
468
469 h = shost_to_hba(shost);
470 if (!h->hba_inquiry_data)
471 return 0;
472 fwrev = &h->hba_inquiry_data[32];
473 return snprintf(buf, 20, "%c%c%c%c\n",
474 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
475}
476
94a13649
SC		 477static ssize_t host_show_commands_outstanding(struct device *dev,
478 struct device_attribute *attr, char *buf)
479{
480 struct Scsi_Host *shost = class_to_shost(dev);
481 struct ctlr_info *h = shost_to_hba(shost);
482
0cbf768e
SC		 483 return snprintf(buf, 20, "%d\n",
484 atomic_read(&h->commands_outstanding));
94a13649
SC		 485}
486
745a7a25
SC		 487static ssize_t host_show_transport_mode(struct device *dev,
488 struct device_attribute *attr, char *buf)
489{
490 struct ctlr_info *h;
491 struct Scsi_Host *shost = class_to_shost(dev);
492
493 h = shost_to_hba(shost);
494 return snprintf(buf, 20, "%s\n",
960a30e7 495 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 496 "performant" : "simple");
497}
498
da0697bd
ST		 499static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
500 struct device_attribute *attr, char *buf)
501{
502 struct ctlr_info *h;
503 struct Scsi_Host *shost = class_to_shost(dev);
504
505 h = shost_to_hba(shost);
506 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
507 (h->acciopath_status == 1) ? "enabled" : "disabled");
508}
509
46380786 510/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 511static u32 unresettable_controller[] = {
512 0x324a103C, /* Smart Array P712m */
9b5c48c2 513 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 514 0x3223103C, /* Smart Array P800 */
515 0x3234103C, /* Smart Array P400 */
516 0x3235103C, /* Smart Array P400i */
517 0x3211103C, /* Smart Array E200i */
518 0x3212103C, /* Smart Array E200 */
519 0x3213103C, /* Smart Array E200i */
520 0x3214103C, /* Smart Array E200i */
521 0x3215103C, /* Smart Array E200i */
522 0x3237103C, /* Smart Array E500 */
523 0x323D103C, /* Smart Array P700m */
7af0abbc 524 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 525 0x409C0E11, /* Smart Array 6400 */
526 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 527 0x40700E11, /* Smart Array 5300 */
528 0x40820E11, /* Smart Array 532 */
529 0x40830E11, /* Smart Array 5312 */
530 0x409A0E11, /* Smart Array 641 */
531 0x409B0E11, /* Smart Array 642 */
532 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 533};
534
46380786
SC		 535/* List of controllers which cannot even be soft reset */
536static u32 soft_unresettable_controller[] = {
7af0abbc 537 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 538 0x40700E11, /* Smart Array 5300 */
539 0x40820E11, /* Smart Array 532 */
540 0x40830E11, /* Smart Array 5312 */
541 0x409A0E11, /* Smart Array 641 */
542 0x409B0E11, /* Smart Array 642 */
543 0x40910E11, /* Smart Array 6i */
46380786
SC		 544 /* Exclude 640x boards. These are two pci devices in one slot
545 * which share a battery backed cache module. One controls the
546 * cache, the other accesses the cache through the one that controls
547 * it. If we reset the one controlling the cache, the other will
548 * likely not be happy. Just forbid resetting this conjoined mess.
549 * The 640x isn't really supported by hpsa anyway.
550 */
551 0x409C0E11, /* Smart Array 6400 */
552 0x409D0E11, /* Smart Array 6400 EM */
553};
554
9b5c48c2
SC		 555static u32 needs_abort_tags_swizzled[] = {
556 0x323D103C, /* Smart Array P700m */
557 0x324a103C, /* Smart Array P712m */
558 0x324b103C, /* SmartArray P711m */
559};
560
561static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 562{
563 int i;
564
9b5c48c2
SC		 565 for (i = 0; i < nelems; i++)
566 if (a[i] == board_id)
567 return 1;
568 return 0;
46380786
SC		 569}
570
9b5c48c2 571static int ctlr_is_hard_resettable(u32 board_id)
46380786 572{
9b5c48c2
SC		 573 return !board_id_in_array(unresettable_controller,
574 ARRAY_SIZE(unresettable_controller), board_id);
575}
46380786 576
9b5c48c2
SC		 577static int ctlr_is_soft_resettable(u32 board_id)
578{
579 return !board_id_in_array(soft_unresettable_controller,
580 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 581}
582
46380786
SC		 583static int ctlr_is_resettable(u32 board_id)
584{
585 return ctlr_is_hard_resettable(board_id) ||
586 ctlr_is_soft_resettable(board_id);
587}
588
9b5c48c2
SC		 589static int ctlr_needs_abort_tags_swizzled(u32 board_id)
590{
591 return board_id_in_array(needs_abort_tags_swizzled,
592 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
593}
594
941b1cda
SC		 595static ssize_t host_show_resettable(struct device *dev,
596 struct device_attribute *attr, char *buf)
597{
598 struct ctlr_info *h;
599 struct Scsi_Host *shost = class_to_shost(dev);
600
601 h = shost_to_hba(shost);
46380786 602 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 603}
604
edd16368
SC		 605static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
606{
607 return (scsi3addr[3] & 0xC0) == 0x40;
608}
609
f2ef0ce7
RE		 610static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
611 "1(+0)ADM", "UNKNOWN"
edd16368 612};
6b80b18f
ST		 613#define HPSA_RAID_0 0
614#define HPSA_RAID_4 1
615#define HPSA_RAID_1 2 /* also used for RAID 10 */
616#define HPSA_RAID_5 3 /* also used for RAID 50 */
617#define HPSA_RAID_51 4
618#define HPSA_RAID_6 5 /* also used for RAID 60 */
619#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 620#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
621
f3f01730
KB		 622static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
623{
624 return !device->physical_device;
625}
626
edd16368
SC		 627static ssize_t raid_level_show(struct device *dev,
628 struct device_attribute *attr, char *buf)
629{
630 ssize_t l = 0;
82a72c0a 631 unsigned char rlevel;
edd16368
SC		 632 struct ctlr_info *h;
633 struct scsi_device *sdev;
634 struct hpsa_scsi_dev_t *hdev;
635 unsigned long flags;
636
637 sdev = to_scsi_device(dev);
638 h = sdev_to_hba(sdev);
639 spin_lock_irqsave(&h->lock, flags);
640 hdev = sdev->hostdata;
641 if (!hdev) {
642 spin_unlock_irqrestore(&h->lock, flags);
643 return -ENODEV;
644 }
645
646 /* Is this even a logical drive? */
f3f01730 647 if (!is_logical_device(hdev)) {
edd16368
SC		 648 spin_unlock_irqrestore(&h->lock, flags);
649 l = snprintf(buf, PAGE_SIZE, "N/A\n");
650 return l;
651 }
652
653 rlevel = hdev->raid_level;
654 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 655 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 656 rlevel = RAID_UNKNOWN;
657 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
658 return l;
659}
660
661static ssize_t lunid_show(struct device *dev,
662 struct device_attribute *attr, char *buf)
663{
664 struct ctlr_info *h;
665 struct scsi_device *sdev;
666 struct hpsa_scsi_dev_t *hdev;
667 unsigned long flags;
668 unsigned char lunid[8];
669
670 sdev = to_scsi_device(dev);
671 h = sdev_to_hba(sdev);
672 spin_lock_irqsave(&h->lock, flags);
673 hdev = sdev->hostdata;
674 if (!hdev) {
675 spin_unlock_irqrestore(&h->lock, flags);
676 return -ENODEV;
677 }
678 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
679 spin_unlock_irqrestore(&h->lock, flags);
680 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
681 lunid[0], lunid[1], lunid[2], lunid[3],
682 lunid[4], lunid[5], lunid[6], lunid[7]);
683}
684
685static ssize_t unique_id_show(struct device *dev,
686 struct device_attribute *attr, char *buf)
687{
688 struct ctlr_info *h;
689 struct scsi_device *sdev;
690 struct hpsa_scsi_dev_t *hdev;
691 unsigned long flags;
692 unsigned char sn[16];
693
694 sdev = to_scsi_device(dev);
695 h = sdev_to_hba(sdev);
696 spin_lock_irqsave(&h->lock, flags);
697 hdev = sdev->hostdata;
698 if (!hdev) {
699 spin_unlock_irqrestore(&h->lock, flags);
700 return -ENODEV;
701 }
702 memcpy(sn, hdev->device_id, sizeof(sn));
703 spin_unlock_irqrestore(&h->lock, flags);
704 return snprintf(buf, 16 * 2 + 2,
705 "%02X%02X%02X%02X%02X%02X%02X%02X"
706 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
707 sn[0], sn[1], sn[2], sn[3],
708 sn[4], sn[5], sn[6], sn[7],
709 sn[8], sn[9], sn[10], sn[11],
710 sn[12], sn[13], sn[14], sn[15]);
711}
712
c1988684
ST		 713static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
714 struct device_attribute *attr, char *buf)
715{
716 struct ctlr_info *h;
717 struct scsi_device *sdev;
718 struct hpsa_scsi_dev_t *hdev;
719 unsigned long flags;
720 int offload_enabled;
721
722 sdev = to_scsi_device(dev);
723 h = sdev_to_hba(sdev);
724 spin_lock_irqsave(&h->lock, flags);
725 hdev = sdev->hostdata;
726 if (!hdev) {
727 spin_unlock_irqrestore(&h->lock, flags);
728 return -ENODEV;
729 }
730 offload_enabled = hdev->offload_enabled;
731 spin_unlock_irqrestore(&h->lock, flags);
732 return snprintf(buf, 20, "%d\n", offload_enabled);
733}
734
8270b862
JH		 735#define MAX_PATHS 8
736#define PATH_STRING_LEN 50
737
738static ssize_t path_info_show(struct device *dev,
739 struct device_attribute *attr, char *buf)
740{
741 struct ctlr_info *h;
742 struct scsi_device *sdev;
743 struct hpsa_scsi_dev_t *hdev;
744 unsigned long flags;
745 int i;
746 int output_len = 0;
747 u8 box;
748 u8 bay;
749 u8 path_map_index = 0;
750 char *active;
751 unsigned char phys_connector[2];
752 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
753
754 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
755 sdev = to_scsi_device(dev);
756 h = sdev_to_hba(sdev);
757 spin_lock_irqsave(&h->devlock, flags);
758 hdev = sdev->hostdata;
759 if (!hdev) {
760 spin_unlock_irqrestore(&h->devlock, flags);
761 return -ENODEV;
762 }
763
764 bay = hdev->bay;
765 for (i = 0; i < MAX_PATHS; i++) {
766 path_map_index = 1<<i;
767 if (i == hdev->active_path_index)
768 active = "Active";
769 else if (hdev->path_map & path_map_index)
770 active = "Inactive";
771 else
772 continue;
773
774 output_len = snprintf(path[i],
775 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
776 h->scsi_host->host_no,
777 hdev->bus, hdev->target, hdev->lun,
778 scsi_device_type(hdev->devtype));
779
66749d0d 780 if (hdev->external ||
f3f01730
KB		 781 hdev->devtype == TYPE_RAID ||
782 is_logical_device(hdev)) {
8270b862
JH		 783 output_len += snprintf(path[i] + output_len,
784 PATH_STRING_LEN, "%s\n",
785 active);
786 continue;
787 }
788
789 box = hdev->box[i];
790 memcpy(&phys_connector, &hdev->phys_connector[i],
791 sizeof(phys_connector));
792 if (phys_connector[0] < '0')
793 phys_connector[0] = '0';
794 if (phys_connector[1] < '0')
795 phys_connector[1] = '0';
796 if (hdev->phys_connector[i] > 0)
797 output_len += snprintf(path[i] + output_len,
798 PATH_STRING_LEN,
799 "PORT: %.2s ",
800 phys_connector);
2a168208 801 if (hdev->devtype == TYPE_DISK && hdev->expose_device) {
8270b862
JH		 802 if (box == 0 || box == 0xFF) {
803 output_len += snprintf(path[i] + output_len,
804 PATH_STRING_LEN,
805 "BAY: %hhu %s\n",
806 bay, active);
807 } else {
808 output_len += snprintf(path[i] + output_len,
809 PATH_STRING_LEN,
810 "BOX: %hhu BAY: %hhu %s\n",
811 box, bay, active);
812 }
813 } else if (box != 0 && box != 0xFF) {
814 output_len += snprintf(path[i] + output_len,
815 PATH_STRING_LEN, "BOX: %hhu %s\n",
816 box, active);
817 } else
818 output_len += snprintf(path[i] + output_len,
819 PATH_STRING_LEN, "%s\n", active);
820 }
821
822 spin_unlock_irqrestore(&h->devlock, flags);
823 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
824 path[0], path[1], path[2], path[3],
825 path[4], path[5], path[6], path[7]);
826}
827
3f5eac3a
SC		 828static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
829static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
830static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
831static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 832static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
833 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 834static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 835static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
836 host_show_hp_ssd_smart_path_status,
837 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 838static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
839 host_store_raid_offload_debug);
3f5eac3a
SC		 840static DEVICE_ATTR(firmware_revision, S_IRUGO,
841 host_show_firmware_revision, NULL);
842static DEVICE_ATTR(commands_outstanding, S_IRUGO,
843 host_show_commands_outstanding, NULL);
844static DEVICE_ATTR(transport_mode, S_IRUGO,
845 host_show_transport_mode, NULL);
941b1cda
SC		 846static DEVICE_ATTR(resettable, S_IRUGO,
847 host_show_resettable, NULL);
e985c58f
SC		 848static DEVICE_ATTR(lockup_detected, S_IRUGO,
849 host_show_lockup_detected, NULL);
3f5eac3a
SC		 850
851static struct device_attribute *hpsa_sdev_attrs[] = {
852 &dev_attr_raid_level,
853 &dev_attr_lunid,
854 &dev_attr_unique_id,
c1988684 855 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 856 &dev_attr_path_info,
e985c58f 857 &dev_attr_lockup_detected,
3f5eac3a
SC		 858 NULL,
859};
860
861static struct device_attribute *hpsa_shost_attrs[] = {
862 &dev_attr_rescan,
863 &dev_attr_firmware_revision,
864 &dev_attr_commands_outstanding,
865 &dev_attr_transport_mode,
941b1cda 866 &dev_attr_resettable,
da0697bd 867 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 868 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 869 NULL,
870};
871
41ce4c35
SC		 872#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
873 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
874
3f5eac3a
SC		 875static struct scsi_host_template hpsa_driver_template = {
876 .module = THIS_MODULE,
f79cfec6
SC		 877 .name = HPSA,
878 .proc_name = HPSA,
3f5eac3a
SC		 879 .queuecommand = hpsa_scsi_queue_command,
880 .scan_start = hpsa_scan_start,
881 .scan_finished = hpsa_scan_finished,
7c0a0229 882 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 883 .this_id = -1,
884 .use_clustering = ENABLE_CLUSTERING,
75167d2c 885 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 886 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
887 .ioctl = hpsa_ioctl,
888 .slave_alloc = hpsa_slave_alloc,
41ce4c35 889 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 890 .slave_destroy = hpsa_slave_destroy,
891#ifdef CONFIG_COMPAT
892 .compat_ioctl = hpsa_compat_ioctl,
893#endif
894 .sdev_attrs = hpsa_sdev_attrs,
895 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 896 .max_sectors = 8192,
54b2b50c 897 .no_write_same = 1,
3f5eac3a
SC		 898};
899
254f796b 900static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 901{
902 u32 a;
072b0518 903 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 904
e1f7de0c
MG		 905 if (h->transMethod & CFGTBL_Trans_io_accel1)
906 return h->access.command_completed(h, q);
907
3f5eac3a 908 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 909 return h->access.command_completed(h, q);
3f5eac3a 910
254f796b
MG		 911 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
912 a = rq->head[rq->current_entry];
913 rq->current_entry++;
0cbf768e 914 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 915 } else {
916 a = FIFO_EMPTY;
917 }
918 /* Check for wraparound */
254f796b
MG		 919 if (rq->current_entry == h->max_commands) {
920 rq->current_entry = 0;
921 rq->wraparound ^= 1;
3f5eac3a
SC		 922 }
923 return a;
924}
925
c349775e
ST		 926/*
927 * There are some special bits in the bus address of the
928 * command that we have to set for the controller to know
929 * how to process the command:
930 *
931 * Normal performant mode:
932 * bit 0: 1 means performant mode, 0 means simple mode.
933 * bits 1-3 = block fetch table entry
934 * bits 4-6 = command type (== 0)
935 *
936 * ioaccel1 mode:
937 * bit 0 = "performant mode" bit.
938 * bits 1-3 = block fetch table entry
939 * bits 4-6 = command type (== 110)
940 * (command type is needed because ioaccel1 mode
941 * commands are submitted through the same register as normal
942 * mode commands, so this is how the controller knows whether
943 * the command is normal mode or ioaccel1 mode.)
944 *
945 * ioaccel2 mode:
946 * bit 0 = "performant mode" bit.
947 * bits 1-4 = block fetch table entry (note extra bit)
948 * bits 4-6 = not needed, because ioaccel2 mode has
949 * a separate special register for submitting commands.
950 */
951
25163bd5
WS		 952/*
953 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 954 * set bit 0 for pull model, bits 3-1 for block fetch
955 * register number
956 */
25163bd5
WS		 957#define DEFAULT_REPLY_QUEUE (-1)
958static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
959 int reply_queue)
3f5eac3a 960{
254f796b 961 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 962 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 963 if (unlikely(!h->msix_vector))
964 return;
965 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 966 c->Header.ReplyQueue =
804a5cb5 967 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 968 else
969 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 970 }
3f5eac3a
SC		 971}
972
c349775e 973static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 974 struct CommandList *c,
975 int reply_queue)
c349775e
ST		 976{
977 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
978
25163bd5
WS		 979 /*
980 * Tell the controller to post the reply to the queue for this
c349775e
ST		 981 * processor. This seems to give the best I/O throughput.
982 */
25163bd5
WS		 983 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
984 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
985 else
986 cp->ReplyQueue = reply_queue % h->nreply_queues;
987 /*
988 * Set the bits in the address sent down to include:
c349775e
ST		 989 * - performant mode bit (bit 0)
990 * - pull count (bits 1-3)
991 * - command type (bits 4-6)
992 */
993 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
994 IOACCEL1_BUSADDR_CMDTYPE;
995}
996
8be986cc
SC		 997static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
998 struct CommandList *c,
999 int reply_queue)
1000{
1001 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1002 &h->ioaccel2_cmd_pool[c->cmdindex];
1003
1004 /* Tell the controller to post the reply to the queue for this
1005 * processor. This seems to give the best I/O throughput.
1006 */
1007 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1008 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1009 else
1010 cp->reply_queue = reply_queue % h->nreply_queues;
1011 /* Set the bits in the address sent down to include:
1012 * - performant mode bit not used in ioaccel mode 2
1013 * - pull count (bits 0-3)
1014 * - command type isn't needed for ioaccel2
1015 */
1016 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1017}
1018
c349775e 1019static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1020 struct CommandList *c,
1021 int reply_queue)
c349775e
ST		 1022{
1023 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1024
25163bd5
WS		 1025 /*
1026 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1027 * processor. This seems to give the best I/O throughput.
1028 */
25163bd5
WS		 1029 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1030 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1031 else
1032 cp->reply_queue = reply_queue % h->nreply_queues;
1033 /*
1034 * Set the bits in the address sent down to include:
c349775e
ST		 1035 * - performant mode bit not used in ioaccel mode 2
1036 * - pull count (bits 0-3)
1037 * - command type isn't needed for ioaccel2
1038 */
1039 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1040}
1041
e85c5974
SC		 1042static int is_firmware_flash_cmd(u8 *cdb)
1043{
1044 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1045}
1046
1047/*
1048 * During firmware flash, the heartbeat register may not update as frequently
1049 * as it should. So we dial down lockup detection during firmware flash. and
1050 * dial it back up when firmware flash completes.
1051 */
1052#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1053#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1054static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1055 struct CommandList *c)
1056{
1057 if (!is_firmware_flash_cmd(c->Request.CDB))
1058 return;
1059 atomic_inc(&h->firmware_flash_in_progress);
1060 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1061}
1062
1063static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1064 struct CommandList *c)
1065{
1066 if (is_firmware_flash_cmd(c->Request.CDB) &&
1067 atomic_dec_and_test(&h->firmware_flash_in_progress))
1068 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1069}
1070
25163bd5
WS		 1071static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1072 struct CommandList *c, int reply_queue)
3f5eac3a 1073{
c05e8866
SC		 1074 dial_down_lockup_detection_during_fw_flash(h, c);
1075 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1076 switch (c->cmd_type) {
1077 case CMD_IOACCEL1:
25163bd5 1078 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1079 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1080 break;
1081 case CMD_IOACCEL2:
25163bd5 1082 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1083 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1084 break;
8be986cc
SC		 1085 case IOACCEL2_TMF:
1086 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1087 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1088 break;
c349775e 1089 default:
25163bd5 1090 set_performant_mode(h, c, reply_queue);
c05e8866 1091 h->access.submit_command(h, c);
c349775e 1092 }
3f5eac3a
SC		 1093}
1094
a58e7e53 1095static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1096{
d604f533 1097 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1098 return finish_cmd(c);
1099
25163bd5
WS		 1100 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1101}
1102
3f5eac3a
SC		 1103static inline int is_hba_lunid(unsigned char scsi3addr[])
1104{
1105 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1106}
1107
1108static inline int is_scsi_rev_5(struct ctlr_info *h)
1109{
1110 if (!h->hba_inquiry_data)
1111 return 0;
1112 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1113 return 1;
1114 return 0;
1115}
1116
edd16368
SC		 1117static int hpsa_find_target_lun(struct ctlr_info *h,
1118 unsigned char scsi3addr[], int bus, int *target, int *lun)
1119{
1120 /* finds an unused bus, target, lun for a new physical device
1121 * assumes h->devlock is held
1122 */
1123 int i, found = 0;
cfe5badc 1124 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1125
263d9401 1126 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1127
1128 for (i = 0; i < h->ndevices; i++) {
1129 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1130 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1131 }
1132
263d9401
AM		 1133 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1134 if (i < HPSA_MAX_DEVICES) {
1135 /* *bus = 1; */
1136 *target = i;
1137 *lun = 0;
1138 found = 1;
edd16368
SC		 1139 }
1140 return !found;
1141}
1142
1d33d85d 1143static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1144 struct hpsa_scsi_dev_t *dev, char *description)
1145{
9975ec9d
DB		 1146 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1147 return;
1148
0d96ef5f
WS		 1149 dev_printk(level, &h->pdev->dev,
1150 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1151 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1152 description,
1153 scsi_device_type(dev->devtype),
1154 dev->vendor,
1155 dev->model,
1156 dev->raid_level > RAID_UNKNOWN ?
1157 "RAID-?" : raid_label[dev->raid_level],
1158 dev->offload_config ? '+' : '-',
1159 dev->offload_enabled ? '+' : '-',
2a168208 1160 dev->expose_device);
0d96ef5f
WS		 1161}
1162
edd16368 1163/* Add an entry into h->dev[] array. */
8aa60681 1164static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1165 struct hpsa_scsi_dev_t *device,
1166 struct hpsa_scsi_dev_t *added[], int *nadded)
1167{
1168 /* assumes h->devlock is held */
1169 int n = h->ndevices;
1170 int i;
1171 unsigned char addr1[8], addr2[8];
1172 struct hpsa_scsi_dev_t *sd;
1173
cfe5badc 1174 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1175 dev_err(&h->pdev->dev, "too many devices, some will be "
1176 "inaccessible.\n");
1177 return -1;
1178 }
1179
1180 /* physical devices do not have lun or target assigned until now. */
1181 if (device->lun != -1)
1182 /* Logical device, lun is already assigned. */
1183 goto lun_assigned;
1184
1185 /* If this device a non-zero lun of a multi-lun device
1186 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1187 * unit no, zero otherwise.
edd16368
SC		 1188 */
1189 if (device->scsi3addr[4] == 0) {
1190 /* This is not a non-zero lun of a multi-lun device */
1191 if (hpsa_find_target_lun(h, device->scsi3addr,
1192 device->bus, &device->target, &device->lun) != 0)
1193 return -1;
1194 goto lun_assigned;
1195 }
1196
1197 /* This is a non-zero lun of a multi-lun device.
1198 * Search through our list and find the device which
9a4178b7 1199 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1200 * Assign the same bus and target for this new LUN.
1201 * Use the logical unit number from the firmware.
1202 */
1203 memcpy(addr1, device->scsi3addr, 8);
1204 addr1[4] = 0;
9a4178b7 1205 addr1[5] = 0;
edd16368
SC		 1206 for (i = 0; i < n; i++) {
1207 sd = h->dev[i];
1208 memcpy(addr2, sd->scsi3addr, 8);
1209 addr2[4] = 0;
9a4178b7 1210 addr2[5] = 0;
1211 /* differ only in byte 4 and 5? */
edd16368
SC		 1212 if (memcmp(addr1, addr2, 8) == 0) {
1213 device->bus = sd->bus;
1214 device->target = sd->target;
1215 device->lun = device->scsi3addr[4];
1216 break;
1217 }
1218 }
1219 if (device->lun == -1) {
1220 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1221 " suspect firmware bug or unsupported hardware "
1222 "configuration.\n");
1223 return -1;
1224 }
1225
1226lun_assigned:
1227
1228 h->dev[n] = device;
1229 h->ndevices++;
1230 added[*nadded] = device;
1231 (*nadded)++;
0d96ef5f 1232 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1233 device->expose_device ? "added" : "masked");
a473d86c
RE		 1234 device->offload_to_be_enabled = device->offload_enabled;
1235 device->offload_enabled = 0;
edd16368
SC		 1236 return 0;
1237}
1238
bd9244f7 1239/* Update an entry in h->dev[] array. */
8aa60681 1240static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1241 int entry, struct hpsa_scsi_dev_t *new_entry)
1242{
a473d86c 1243 int offload_enabled;
bd9244f7
ST		 1244 /* assumes h->devlock is held */
1245 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1246
1247 /* Raid level changed. */
1248 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1249
03383736
DB		 1250 /* Raid offload parameters changed. Careful about the ordering. */
1251 if (new_entry->offload_config && new_entry->offload_enabled) {
1252 /*
1253 * if drive is newly offload_enabled, we want to copy the
1254 * raid map data first. If previously offload_enabled and
1255 * offload_config were set, raid map data had better be
1256 * the same as it was before. if raid map data is changed
1257 * then it had better be the case that
1258 * h->dev[entry]->offload_enabled is currently 0.
1259 */
1260 h->dev[entry]->raid_map = new_entry->raid_map;
1261 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1262 }
a3144e0b
JH		 1263 if (new_entry->hba_ioaccel_enabled) {
1264 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1265 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1266 }
1267 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1268 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1269 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1270 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1271
41ce4c35
SC		 1272 /*
1273 * We can turn off ioaccel offload now, but need to delay turning
1274 * it on until we can update h->dev[entry]->phys_disk[], but we
1275 * can't do that until all the devices are updated.
1276 */
1277 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1278 if (!new_entry->offload_enabled)
1279 h->dev[entry]->offload_enabled = 0;
1280
a473d86c
RE		 1281 offload_enabled = h->dev[entry]->offload_enabled;
1282 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1283 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1284 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1285}
1286
2a8ccf31 1287/* Replace an entry from h->dev[] array. */
8aa60681 1288static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1289 int entry, struct hpsa_scsi_dev_t *new_entry,
1290 struct hpsa_scsi_dev_t *added[], int *nadded,
1291 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1292{
1293 /* assumes h->devlock is held */
cfe5badc 1294 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1295 removed[*nremoved] = h->dev[entry];
1296 (*nremoved)++;
01350d05
SC		 1297
1298 /*
1299 * New physical devices won't have target/lun assigned yet
1300 * so we need to preserve the values in the slot we are replacing.
1301 */
1302 if (new_entry->target == -1) {
1303 new_entry->target = h->dev[entry]->target;
1304 new_entry->lun = h->dev[entry]->lun;
1305 }
1306
2a8ccf31
SC		 1307 h->dev[entry] = new_entry;
1308 added[*nadded] = new_entry;
1309 (*nadded)++;
0d96ef5f 1310 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1311 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1312 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1313}
1314
edd16368 1315/* Remove an entry from h->dev[] array. */
8aa60681 1316static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1317 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1318{
1319 /* assumes h->devlock is held */
1320 int i;
1321 struct hpsa_scsi_dev_t *sd;
1322
cfe5badc 1323 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1324
1325 sd = h->dev[entry];
1326 removed[*nremoved] = h->dev[entry];
1327 (*nremoved)++;
1328
1329 for (i = entry; i < h->ndevices-1; i++)
1330 h->dev[i] = h->dev[i+1];
1331 h->ndevices--;
0d96ef5f 1332 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1333}
1334
1335#define SCSI3ADDR_EQ(a, b) ( \
1336 (a)[7] == (b)[7] && \
1337 (a)[6] == (b)[6] && \
1338 (a)[5] == (b)[5] && \
1339 (a)[4] == (b)[4] && \
1340 (a)[3] == (b)[3] && \
1341 (a)[2] == (b)[2] && \
1342 (a)[1] == (b)[1] && \
1343 (a)[0] == (b)[0])
1344
1345static void fixup_botched_add(struct ctlr_info *h,
1346 struct hpsa_scsi_dev_t *added)
1347{
1348 /* called when scsi_add_device fails in order to re-adjust
1349 * h->dev[] to match the mid layer's view.
1350 */
1351 unsigned long flags;
1352 int i, j;
1353
1354 spin_lock_irqsave(&h->lock, flags);
1355 for (i = 0; i < h->ndevices; i++) {
1356 if (h->dev[i] == added) {
1357 for (j = i; j < h->ndevices-1; j++)
1358 h->dev[j] = h->dev[j+1];
1359 h->ndevices--;
1360 break;
1361 }
1362 }
1363 spin_unlock_irqrestore(&h->lock, flags);
1364 kfree(added);
1365}
1366
1367static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1368 struct hpsa_scsi_dev_t *dev2)
1369{
edd16368
SC		 1370 /* we compare everything except lun and target as these
1371 * are not yet assigned. Compare parts likely
1372 * to differ first
1373 */
1374 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1375 sizeof(dev1->scsi3addr)) != 0)
1376 return 0;
1377 if (memcmp(dev1->device_id, dev2->device_id,
1378 sizeof(dev1->device_id)) != 0)
1379 return 0;
1380 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1381 return 0;
1382 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1383 return 0;
edd16368
SC		 1384 if (dev1->devtype != dev2->devtype)
1385 return 0;
edd16368
SC		 1386 if (dev1->bus != dev2->bus)
1387 return 0;
1388 return 1;
1389}
1390
bd9244f7
ST		 1391static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1392 struct hpsa_scsi_dev_t *dev2)
1393{
1394 /* Device attributes that can change, but don't mean
1395 * that the device is a different device, nor that the OS
1396 * needs to be told anything about the change.
1397 */
1398 if (dev1->raid_level != dev2->raid_level)
1399 return 1;
250fb125
SC		 1400 if (dev1->offload_config != dev2->offload_config)
1401 return 1;
1402 if (dev1->offload_enabled != dev2->offload_enabled)
1403 return 1;
93849508
DB		 1404 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1405 if (dev1->queue_depth != dev2->queue_depth)
1406 return 1;
bd9244f7
ST		 1407 return 0;
1408}
1409
edd16368
SC		 1410/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1411 * and return needle location in *index. If scsi3addr matches, but not
1412 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1413 * location in *index.
1414 * In the case of a minor device attribute change, such as RAID level, just
1415 * return DEVICE_UPDATED, along with the updated device's location in index.
1416 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1417 */
1418static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1419 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1420 int *index)
1421{
1422 int i;
1423#define DEVICE_NOT_FOUND 0
1424#define DEVICE_CHANGED 1
1425#define DEVICE_SAME 2
bd9244f7 1426#define DEVICE_UPDATED 3
1d33d85d
DB		 1427 if (needle == NULL)
1428 return DEVICE_NOT_FOUND;
1429
edd16368 1430 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1431 if (haystack[i] == NULL) /* previously removed. */
1432 continue;
edd16368
SC		 1433 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1434 *index = i;
bd9244f7
ST		 1435 if (device_is_the_same(needle, haystack[i])) {
1436 if (device_updated(needle, haystack[i]))
1437 return DEVICE_UPDATED;
edd16368 1438 return DEVICE_SAME;
bd9244f7 1439 } else {
9846590e
SC		 1440 /* Keep offline devices offline */
1441 if (needle->volume_offline)
1442 return DEVICE_NOT_FOUND;
edd16368 1443 return DEVICE_CHANGED;
bd9244f7 1444 }
edd16368
SC		 1445 }
1446 }
1447 *index = -1;
1448 return DEVICE_NOT_FOUND;
1449}
1450
9846590e
SC		 1451static void hpsa_monitor_offline_device(struct ctlr_info *h,
1452 unsigned char scsi3addr[])
1453{
1454 struct offline_device_entry *device;
1455 unsigned long flags;
1456
1457 /* Check to see if device is already on the list */
1458 spin_lock_irqsave(&h->offline_device_lock, flags);
1459 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1460 if (memcmp(device->scsi3addr, scsi3addr,
1461 sizeof(device->scsi3addr)) == 0) {
1462 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1463 return;
1464 }
1465 }
1466 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1467
1468 /* Device is not on the list, add it. */
1469 device = kmalloc(sizeof(*device), GFP_KERNEL);
1470 if (!device) {
1471 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1472 return;
1473 }
1474 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1475 spin_lock_irqsave(&h->offline_device_lock, flags);
1476 list_add_tail(&device->offline_list, &h->offline_device_list);
1477 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1478}
1479
1480/* Print a message explaining various offline volume states */
1481static void hpsa_show_volume_status(struct ctlr_info *h,
1482 struct hpsa_scsi_dev_t *sd)
1483{
1484 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1485 dev_info(&h->pdev->dev,
1486 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1487 h->scsi_host->host_no,
1488 sd->bus, sd->target, sd->lun);
1489 switch (sd->volume_offline) {
1490 case HPSA_LV_OK:
1491 break;
1492 case HPSA_LV_UNDERGOING_ERASE:
1493 dev_info(&h->pdev->dev,
1494 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1495 h->scsi_host->host_no,
1496 sd->bus, sd->target, sd->lun);
1497 break;
5ca01204
SB		 1498 case HPSA_LV_NOT_AVAILABLE:
1499 dev_info(&h->pdev->dev,
1500 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1501 h->scsi_host->host_no,
1502 sd->bus, sd->target, sd->lun);
1503 break;
9846590e
SC		 1504 case HPSA_LV_UNDERGOING_RPI:
1505 dev_info(&h->pdev->dev,
5ca01204 1506 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1507 h->scsi_host->host_no,
1508 sd->bus, sd->target, sd->lun);
1509 break;
1510 case HPSA_LV_PENDING_RPI:
1511 dev_info(&h->pdev->dev,
5ca01204
SB		 1512 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1513 h->scsi_host->host_no,
1514 sd->bus, sd->target, sd->lun);
9846590e
SC		 1515 break;
1516 case HPSA_LV_ENCRYPTED_NO_KEY:
1517 dev_info(&h->pdev->dev,
1518 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1519 h->scsi_host->host_no,
1520 sd->bus, sd->target, sd->lun);
1521 break;
1522 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1523 dev_info(&h->pdev->dev,
1524 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1525 h->scsi_host->host_no,
1526 sd->bus, sd->target, sd->lun);
1527 break;
1528 case HPSA_LV_UNDERGOING_ENCRYPTION:
1529 dev_info(&h->pdev->dev,
1530 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1531 h->scsi_host->host_no,
1532 sd->bus, sd->target, sd->lun);
1533 break;
1534 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1535 dev_info(&h->pdev->dev,
1536 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1537 h->scsi_host->host_no,
1538 sd->bus, sd->target, sd->lun);
1539 break;
1540 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1541 dev_info(&h->pdev->dev,
1542 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1543 h->scsi_host->host_no,
1544 sd->bus, sd->target, sd->lun);
1545 break;
1546 case HPSA_LV_PENDING_ENCRYPTION:
1547 dev_info(&h->pdev->dev,
1548 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1549 h->scsi_host->host_no,
1550 sd->bus, sd->target, sd->lun);
1551 break;
1552 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1553 dev_info(&h->pdev->dev,
1554 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1555 h->scsi_host->host_no,
1556 sd->bus, sd->target, sd->lun);
1557 break;
1558 }
1559}
1560
03383736
DB		 1561/*
1562 * Figure the list of physical drive pointers for a logical drive with
1563 * raid offload configured.
1564 */
1565static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1566 struct hpsa_scsi_dev_t *dev[], int ndevices,
1567 struct hpsa_scsi_dev_t *logical_drive)
1568{
1569 struct raid_map_data *map = &logical_drive->raid_map;
1570 struct raid_map_disk_data *dd = &map->data[0];
1571 int i, j;
1572 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1573 le16_to_cpu(map->metadata_disks_per_row);
1574 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1575 le16_to_cpu(map->layout_map_count) *
1576 total_disks_per_row;
1577 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1578 total_disks_per_row;
1579 int qdepth;
1580
1581 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1582 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1583
d604f533
WS		 1584 logical_drive->nphysical_disks = nraid_map_entries;
1585
03383736
DB		 1586 qdepth = 0;
1587 for (i = 0; i < nraid_map_entries; i++) {
1588 logical_drive->phys_disk[i] = NULL;
1589 if (!logical_drive->offload_config)
1590 continue;
1591 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1592 if (dev[j] == NULL)
1593 continue;
03383736
DB		 1594 if (dev[j]->devtype != TYPE_DISK)
1595 continue;
f3f01730 1596 if (is_logical_device(dev[j]))
03383736
DB		 1597 continue;
1598 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1599 continue;
1600
1601 logical_drive->phys_disk[i] = dev[j];
1602 if (i < nphys_disk)
1603 qdepth = min(h->nr_cmds, qdepth +
1604 logical_drive->phys_disk[i]->queue_depth);
1605 break;
1606 }
1607
1608 /*
1609 * This can happen if a physical drive is removed and
1610 * the logical drive is degraded. In that case, the RAID
1611 * map data will refer to a physical disk which isn't actually
1612 * present. And in that case offload_enabled should already
1613 * be 0, but we'll turn it off here just in case
1614 */
1615 if (!logical_drive->phys_disk[i]) {
1616 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1617 logical_drive->offload_to_be_enabled = 0;
1618 logical_drive->queue_depth = 8;
03383736
DB		 1619 }
1620 }
1621 if (nraid_map_entries)
1622 /*
1623 * This is correct for reads, too high for full stripe writes,
1624 * way too high for partial stripe writes
1625 */
1626 logical_drive->queue_depth = qdepth;
1627 else
1628 logical_drive->queue_depth = h->nr_cmds;
1629}
1630
1631static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1632 struct hpsa_scsi_dev_t *dev[], int ndevices)
1633{
1634 int i;
1635
1636 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1637 if (dev[i] == NULL)
1638 continue;
03383736
DB		 1639 if (dev[i]->devtype != TYPE_DISK)
1640 continue;
f3f01730 1641 if (!is_logical_device(dev[i]))
03383736 1642 continue;
41ce4c35
SC		 1643
1644 /*
1645 * If offload is currently enabled, the RAID map and
1646 * phys_disk[] assignment *better* not be changing
1647 * and since it isn't changing, we do not need to
1648 * update it.
1649 */
1650 if (dev[i]->offload_enabled)
1651 continue;
1652
03383736
DB		 1653 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1654 }
1655}
1656
096ccff4
KB		 1657static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1658{
1659 int rc = 0;
1660
1661 if (!h->scsi_host)
1662 return 1;
1663
1664 rc = scsi_add_device(h->scsi_host, device->bus,
1665 device->target, device->lun);
1666 return rc;
1667}
1668
1669static void hpsa_remove_device(struct ctlr_info *h,
1670 struct hpsa_scsi_dev_t *device)
1671{
1672 struct scsi_device *sdev = NULL;
1673
1674 if (!h->scsi_host)
1675 return;
1676
1677 sdev = scsi_device_lookup(h->scsi_host, device->bus,
1678 device->target, device->lun);
1679
1680 if (sdev) {
1681 scsi_remove_device(sdev);
1682 scsi_device_put(sdev);
1683 } else {
1684 /*
1685 * We don't expect to get here. Future commands
1686 * to this device will get a selection timeout as
1687 * if the device were gone.
1688 */
1689 hpsa_show_dev_msg(KERN_WARNING, h, device,
1690 "didn't find device for removal.");
1691 }
1692}
1693
8aa60681 1694static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1695 struct hpsa_scsi_dev_t *sd[], int nsds)
1696{
1697 /* sd contains scsi3 addresses and devtypes, and inquiry
1698 * data. This function takes what's in sd to be the current
1699 * reality and updates h->dev[] to reflect that reality.
1700 */
1701 int i, entry, device_change, changes = 0;
1702 struct hpsa_scsi_dev_t *csd;
1703 unsigned long flags;
1704 struct hpsa_scsi_dev_t **added, **removed;
1705 int nadded, nremoved;
edd16368 1706
da03ded0
DB		 1707 /*
1708 * A reset can cause a device status to change
1709 * re-schedule the scan to see what happened.
1710 */
1711 if (h->reset_in_progress) {
1712 h->drv_req_rescan = 1;
1713 return;
1714 }
1715
cfe5badc
ST		 1716 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1717 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1718
1719 if (!added || !removed) {
1720 dev_warn(&h->pdev->dev, "out of memory in "
1721 "adjust_hpsa_scsi_table\n");
1722 goto free_and_out;
1723 }
1724
1725 spin_lock_irqsave(&h->devlock, flags);
1726
1727 /* find any devices in h->dev[] that are not in
1728 * sd[] and remove them from h->dev[], and for any
1729 * devices which have changed, remove the old device
1730 * info and add the new device info.
bd9244f7
ST		 1731 * If minor device attributes change, just update
1732 * the existing device structure.
edd16368
SC		 1733 */
1734 i = 0;
1735 nremoved = 0;
1736 nadded = 0;
1737 while (i < h->ndevices) {
1738 csd = h->dev[i];
1739 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1740 if (device_change == DEVICE_NOT_FOUND) {
1741 changes++;
8aa60681 1742 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1743 continue; /* remove ^^^, hence i not incremented */
1744 } else if (device_change == DEVICE_CHANGED) {
1745 changes++;
8aa60681 1746 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1747 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1748 /* Set it to NULL to prevent it from being freed
1749 * at the bottom of hpsa_update_scsi_devices()
1750 */
1751 sd[entry] = NULL;
bd9244f7 1752 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1753 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1754 }
1755 i++;
1756 }
1757
1758 /* Now, make sure every device listed in sd[] is also
1759 * listed in h->dev[], adding them if they aren't found
1760 */
1761
1762 for (i = 0; i < nsds; i++) {
1763 if (!sd[i]) /* if already added above. */
1764 continue;
9846590e
SC		 1765
1766 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1767 * as the SCSI mid-layer does not handle such devices well.
1768 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1769 * at 160Hz, and prevents the system from coming up.
1770 */
1771 if (sd[i]->volume_offline) {
1772 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1773 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1774 continue;
1775 }
1776
edd16368
SC		 1777 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1778 h->ndevices, &entry);
1779 if (device_change == DEVICE_NOT_FOUND) {
1780 changes++;
8aa60681 1781 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1782 break;
1783 sd[i] = NULL; /* prevent from being freed later. */
1784 } else if (device_change == DEVICE_CHANGED) {
1785 /* should never happen... */
1786 changes++;
1787 dev_warn(&h->pdev->dev,
1788 "device unexpectedly changed.\n");
1789 /* but if it does happen, we just ignore that device */
1790 }
1791 }
41ce4c35
SC		 1792 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1793
1794 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1795 * any logical drives that need it enabled.
1796 */
1d33d85d
DB		 1797 for (i = 0; i < h->ndevices; i++) {
1798 if (h->dev[i] == NULL)
1799 continue;
41ce4c35 1800 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1801 }
41ce4c35 1802
edd16368
SC		 1803 spin_unlock_irqrestore(&h->devlock, flags);
1804
9846590e
SC		 1805 /* Monitor devices which are in one of several NOT READY states to be
1806 * brought online later. This must be done without holding h->devlock,
1807 * so don't touch h->dev[]
1808 */
1809 for (i = 0; i < nsds; i++) {
1810 if (!sd[i]) /* if already added above. */
1811 continue;
1812 if (sd[i]->volume_offline)
1813 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1814 }
1815
edd16368
SC		 1816 /* Don't notify scsi mid layer of any changes the first time through
1817 * (or if there are no changes) scsi_scan_host will do it later the
1818 * first time through.
1819 */
8aa60681 1820 if (!changes)
edd16368
SC		 1821 goto free_and_out;
1822
edd16368
SC		 1823 /* Notify scsi mid layer of any removed devices */
1824 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1825 if (removed[i] == NULL)
1826 continue;
096ccff4
KB		 1827 if (removed[i]->expose_device)
1828 hpsa_remove_device(h, removed[i]);
edd16368
SC		 1829 kfree(removed[i]);
1830 removed[i] = NULL;
1831 }
1832
1833 /* Notify scsi mid layer of any added devices */
1834 for (i = 0; i < nadded; i++) {
096ccff4
KB		 1835 int rc = 0;
1836
1d33d85d
DB		 1837 if (added[i] == NULL)
1838 continue;
2a168208 1839 if (!(added[i]->expose_device))
41ce4c35 1840 continue;
096ccff4
KB		 1841 rc = hpsa_add_device(h, added[i]);
1842 if (!rc)
edd16368 1843 continue;
096ccff4
KB		 1844 dev_warn(&h->pdev->dev,
1845 "addition failed %d, device not added.", rc);
edd16368
SC		 1846 /* now we have to remove it from h->dev,
1847 * since it didn't get added to scsi mid layer
1848 */
1849 fixup_botched_add(h, added[i]);
853633e8 1850 h->drv_req_rescan = 1;
edd16368
SC		 1851 }
1852
1853free_and_out:
1854 kfree(added);
1855 kfree(removed);
edd16368
SC		 1856}
1857
1858/*
9e03aa2f 1859 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1860 * Assume's h->devlock is held.
1861 */
1862static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1863 int bus, int target, int lun)
1864{
1865 int i;
1866 struct hpsa_scsi_dev_t *sd;
1867
1868 for (i = 0; i < h->ndevices; i++) {
1869 sd = h->dev[i];
1870 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1871 return sd;
1872 }
1873 return NULL;
1874}
1875
edd16368
SC		 1876static int hpsa_slave_alloc(struct scsi_device *sdev)
1877{
1878 struct hpsa_scsi_dev_t *sd;
1879 unsigned long flags;
1880 struct ctlr_info *h;
1881
1882 h = sdev_to_hba(sdev);
1883 spin_lock_irqsave(&h->devlock, flags);
1884 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1885 sdev_id(sdev), sdev->lun);
41ce4c35 1886 if (likely(sd)) {
03383736 1887 atomic_set(&sd->ioaccel_cmds_out, 0);
2a168208 1888 sdev->hostdata = sd->expose_device ? sd : NULL;
41ce4c35
SC		 1889 } else
1890 sdev->hostdata = NULL;
edd16368
SC		 1891 spin_unlock_irqrestore(&h->devlock, flags);
1892 return 0;
1893}
1894
41ce4c35
SC		 1895/* configure scsi device based on internal per-device structure */
1896static int hpsa_slave_configure(struct scsi_device *sdev)
1897{
1898 struct hpsa_scsi_dev_t *sd;
1899 int queue_depth;
1900
1901 sd = sdev->hostdata;
2a168208 1902 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 1903
1904 if (sd)
1905 queue_depth = sd->queue_depth != 0 ?
1906 sd->queue_depth : sdev->host->can_queue;
1907 else
1908 queue_depth = sdev->host->can_queue;
1909
1910 scsi_change_queue_depth(sdev, queue_depth);
1911
1912 return 0;
1913}
1914
edd16368
SC		 1915static void hpsa_slave_destroy(struct scsi_device *sdev)
1916{
bcc44255 1917 /* nothing to do. */
edd16368
SC		 1918}
1919
d9a729f3
WS		 1920static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1921{
1922 int i;
1923
1924 if (!h->ioaccel2_cmd_sg_list)
1925 return;
1926 for (i = 0; i < h->nr_cmds; i++) {
1927 kfree(h->ioaccel2_cmd_sg_list[i]);
1928 h->ioaccel2_cmd_sg_list[i] = NULL;
1929 }
1930 kfree(h->ioaccel2_cmd_sg_list);
1931 h->ioaccel2_cmd_sg_list = NULL;
1932}
1933
1934static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1935{
1936 int i;
1937
1938 if (h->chainsize <= 0)
1939 return 0;
1940
1941 h->ioaccel2_cmd_sg_list =
1942 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1943 GFP_KERNEL);
1944 if (!h->ioaccel2_cmd_sg_list)
1945 return -ENOMEM;
1946 for (i = 0; i < h->nr_cmds; i++) {
1947 h->ioaccel2_cmd_sg_list[i] =
1948 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1949 h->maxsgentries, GFP_KERNEL);
1950 if (!h->ioaccel2_cmd_sg_list[i])
1951 goto clean;
1952 }
1953 return 0;
1954
1955clean:
1956 hpsa_free_ioaccel2_sg_chain_blocks(h);
1957 return -ENOMEM;
1958}
1959
33a2ffce
SC		 1960static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1961{
1962 int i;
1963
1964 if (!h->cmd_sg_list)
1965 return;
1966 for (i = 0; i < h->nr_cmds; i++) {
1967 kfree(h->cmd_sg_list[i]);
1968 h->cmd_sg_list[i] = NULL;
1969 }
1970 kfree(h->cmd_sg_list);
1971 h->cmd_sg_list = NULL;
1972}
1973
105a3dbc 1974static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1975{
1976 int i;
1977
1978 if (h->chainsize <= 0)
1979 return 0;
1980
1981 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1982 GFP_KERNEL);
3d4e6af8
RE		 1983 if (!h->cmd_sg_list) {
1984 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1985 return -ENOMEM;
3d4e6af8 1986 }
33a2ffce
SC		 1987 for (i = 0; i < h->nr_cmds; i++) {
1988 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1989 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1990 if (!h->cmd_sg_list[i]) {
1991 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1992 goto clean;
3d4e6af8 1993 }
33a2ffce
SC		 1994 }
1995 return 0;
1996
1997clean:
1998 hpsa_free_sg_chain_blocks(h);
1999 return -ENOMEM;
2000}
2001
d9a729f3
WS		 2002static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2003 struct io_accel2_cmd *cp, struct CommandList *c)
2004{
2005 struct ioaccel2_sg_element *chain_block;
2006 u64 temp64;
2007 u32 chain_size;
2008
2009 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2010 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2011 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
2012 PCI_DMA_TODEVICE);
2013 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2014 /* prevent subsequent unmapping */
2015 cp->sg->address = 0;
2016 return -1;
2017 }
2018 cp->sg->address = cpu_to_le64(temp64);
2019 return 0;
2020}
2021
2022static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2023 struct io_accel2_cmd *cp)
2024{
2025 struct ioaccel2_sg_element *chain_sg;
2026 u64 temp64;
2027 u32 chain_size;
2028
2029 chain_sg = cp->sg;
2030 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2031 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2032 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2033}
2034
e2bea6df 2035static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2036 struct CommandList *c)
2037{
2038 struct SGDescriptor *chain_sg, *chain_block;
2039 u64 temp64;
50a0decf 2040 u32 chain_len;
33a2ffce
SC		 2041
2042 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2043 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2044 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2045 chain_len = sizeof(*chain_sg) *
2b08b3e9 2046 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2047 chain_sg->Len = cpu_to_le32(chain_len);
2048 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2049 PCI_DMA_TODEVICE);
e2bea6df
SC		 2050 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2051 /* prevent subsequent unmapping */
50a0decf 2052 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2053 return -1;
2054 }
50a0decf 2055 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2056 return 0;
33a2ffce
SC		 2057}
2058
2059static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2060 struct CommandList *c)
2061{
2062 struct SGDescriptor *chain_sg;
33a2ffce 2063
50a0decf 2064 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2065 return;
2066
2067 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2068 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2069 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2070}
2071
a09c1441
ST		 2072
2073/* Decode the various types of errors on ioaccel2 path.
2074 * Return 1 for any error that should generate a RAID path retry.
2075 * Return 0 for errors that don't require a RAID path retry.
2076 */
2077static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2078 struct CommandList *c,
2079 struct scsi_cmnd *cmd,
2080 struct io_accel2_cmd *c2)
2081{
2082 int data_len;
a09c1441 2083 int retry = 0;
c40820d5 2084 u32 ioaccel2_resid = 0;
c349775e
ST		 2085
2086 switch (c2->error_data.serv_response) {
2087 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2088 switch (c2->error_data.status) {
2089 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2090 break;
2091 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2092 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2093 if (c2->error_data.data_present !=
ee6b1889
SC		 2094 IOACCEL2_SENSE_DATA_PRESENT) {
2095 memset(cmd->sense_buffer, 0,
2096 SCSI_SENSE_BUFFERSIZE);
c349775e 2097 break;
ee6b1889 2098 }
c349775e
ST		 2099 /* copy the sense data */
2100 data_len = c2->error_data.sense_data_len;
2101 if (data_len > SCSI_SENSE_BUFFERSIZE)
2102 data_len = SCSI_SENSE_BUFFERSIZE;
2103 if (data_len > sizeof(c2->error_data.sense_data_buff))
2104 data_len =
2105 sizeof(c2->error_data.sense_data_buff);
2106 memcpy(cmd->sense_buffer,
2107 c2->error_data.sense_data_buff, data_len);
a09c1441 2108 retry = 1;
c349775e
ST		 2109 break;
2110 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2111 retry = 1;
c349775e
ST		 2112 break;
2113 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2114 retry = 1;
c349775e
ST		 2115 break;
2116 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2117 retry = 1;
c349775e
ST		 2118 break;
2119 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2120 retry = 1;
c349775e
ST		 2121 break;
2122 default:
a09c1441 2123 retry = 1;
c349775e
ST		 2124 break;
2125 }
2126 break;
2127 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2128 switch (c2->error_data.status) {
2129 case IOACCEL2_STATUS_SR_IO_ERROR:
2130 case IOACCEL2_STATUS_SR_IO_ABORTED:
2131 case IOACCEL2_STATUS_SR_OVERRUN:
2132 retry = 1;
2133 break;
2134 case IOACCEL2_STATUS_SR_UNDERRUN:
2135 cmd->result = (DID_OK << 16); /* host byte */
2136 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2137 ioaccel2_resid = get_unaligned_le32(
2138 &c2->error_data.resid_cnt[0]);
2139 scsi_set_resid(cmd, ioaccel2_resid);
2140 break;
2141 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2142 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2143 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2144 /* We will get an event from ctlr to trigger rescan */
2145 retry = 1;
2146 break;
2147 default:
2148 retry = 1;
c40820d5 2149 }
c349775e
ST		 2150 break;
2151 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2152 break;
2153 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2154 break;
2155 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2156 retry = 1;
c349775e
ST		 2157 break;
2158 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2159 break;
2160 default:
a09c1441 2161 retry = 1;
c349775e
ST		 2162 break;
2163 }
a09c1441
ST		 2164
2165 return retry; /* retry on raid path? */
c349775e
ST		 2166}
2167
a58e7e53
WS		 2168static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2169 struct CommandList *c)
2170{
d604f533
WS		 2171 bool do_wake = false;
2172
a58e7e53
WS		 2173 /*
2174 * Prevent the following race in the abort handler:
2175 *
2176 * 1. LLD is requested to abort a SCSI command
2177 * 2. The SCSI command completes
2178 * 3. The struct CommandList associated with step 2 is made available
2179 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2180 * 5. Abort handler follows scsi_cmnd->host_scribble and
2181 * finds struct CommandList and tries to aborts it
2182 * Now we have aborted the wrong command.
2183 *
d604f533
WS		 2184 * Reset c->scsi_cmd here so that the abort or reset handler will know
2185 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2186 * waiting for this command, and, if so, wake it.
2187 */
2188 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2189 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2190 if (c->abort_pending) {
d604f533 2191 do_wake = true;
a58e7e53 2192 c->abort_pending = false;
a58e7e53 2193 }
d604f533
WS		 2194 if (c->reset_pending) {
2195 unsigned long flags;
2196 struct hpsa_scsi_dev_t *dev;
2197
2198 /*
2199 * There appears to be a reset pending; lock the lock and
2200 * reconfirm. If so, then decrement the count of outstanding
2201 * commands and wake the reset command if this is the last one.
2202 */
2203 spin_lock_irqsave(&h->lock, flags);
2204 dev = c->reset_pending; /* Re-fetch under the lock. */
2205 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2206 do_wake = true;
2207 c->reset_pending = NULL;
2208 spin_unlock_irqrestore(&h->lock, flags);
2209 }
2210
2211 if (do_wake)
2212 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2213}
2214
73153fe5
WS		 2215static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2216 struct CommandList *c)
2217{
2218 hpsa_cmd_resolve_events(h, c);
2219 cmd_tagged_free(h, c);
2220}
2221
8a0ff92c
WS		 2222static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2223 struct CommandList *c, struct scsi_cmnd *cmd)
2224{
73153fe5 2225 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2226 cmd->scsi_done(cmd);
2227}
2228
2229static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2230{
2231 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2232 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2233}
2234
a58e7e53
WS		 2235static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2236{
2237 cmd->result = DID_ABORT << 16;
2238}
2239
2240static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2241 struct scsi_cmnd *cmd)
2242{
2243 hpsa_set_scsi_cmd_aborted(cmd);
2244 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2245 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2246 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2247}
2248
c349775e
ST		 2249static void process_ioaccel2_completion(struct ctlr_info *h,
2250 struct CommandList *c, struct scsi_cmnd *cmd,
2251 struct hpsa_scsi_dev_t *dev)
2252{
2253 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2254
2255 /* check for good status */
2256 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2257 c2->error_data.status == 0))
2258 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2259
8a0ff92c
WS		 2260 /*
2261 * Any RAID offload error results in retry which will use
c349775e
ST		 2262 * the normal I/O path so the controller can handle whatever's
2263 * wrong.
2264 */
f3f01730 2265 if (is_logical_device(dev) &&
c349775e
ST		 2266 c2->error_data.serv_response ==
2267 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2268 if (c2->error_data.status ==
2269 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2270 dev->offload_enabled = 0;
8a0ff92c
WS		 2271
2272 return hpsa_retry_cmd(h, c);
a09c1441 2273 }
080ef1cc
DB		 2274
2275 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2276 return hpsa_retry_cmd(h, c);
080ef1cc 2277
8a0ff92c 2278 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2279}
2280
9437ac43
SC		 2281/* Returns 0 on success, < 0 otherwise. */
2282static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2283 struct CommandList *cp)
2284{
2285 u8 tmf_status = cp->err_info->ScsiStatus;
2286
2287 switch (tmf_status) {
2288 case CISS_TMF_COMPLETE:
2289 /*
2290 * CISS_TMF_COMPLETE never happens, instead,
2291 * ei->CommandStatus == 0 for this case.
2292 */
2293 case CISS_TMF_SUCCESS:
2294 return 0;
2295 case CISS_TMF_INVALID_FRAME:
2296 case CISS_TMF_NOT_SUPPORTED:
2297 case CISS_TMF_FAILED:
2298 case CISS_TMF_WRONG_LUN:
2299 case CISS_TMF_OVERLAPPED_TAG:
2300 break;
2301 default:
2302 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2303 tmf_status);
2304 break;
2305 }
2306 return -tmf_status;
2307}
2308
1fb011fb 2309static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2310{
2311 struct scsi_cmnd *cmd;
2312 struct ctlr_info *h;
2313 struct ErrorInfo *ei;
283b4a9b 2314 struct hpsa_scsi_dev_t *dev;
d9a729f3 2315 struct io_accel2_cmd *c2;
edd16368 2316
9437ac43
SC		 2317 u8 sense_key;
2318 u8 asc; /* additional sense code */
2319 u8 ascq; /* additional sense code qualifier */
db111e18 2320 unsigned long sense_data_size;
edd16368
SC		 2321
2322 ei = cp->err_info;
7fa3030c 2323 cmd = cp->scsi_cmd;
edd16368 2324 h = cp->h;
283b4a9b 2325 dev = cmd->device->hostdata;
d9a729f3 2326 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2327
2328 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2329 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2330 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2331 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2332
d9a729f3
WS		 2333 if ((cp->cmd_type == CMD_IOACCEL2) &&
2334 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2335 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2336
edd16368
SC		 2337 cmd->result = (DID_OK << 16); /* host byte */
2338 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2339
03383736
DB		 2340 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2341 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2342
25163bd5
WS		 2343 /*
2344 * We check for lockup status here as it may be set for
2345 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2346 * fail_all_oustanding_cmds()
2347 */
2348 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2349 /* DID_NO_CONNECT will prevent a retry */
2350 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2351 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2352 }
2353
d604f533
WS		 2354 if ((unlikely(hpsa_is_pending_event(cp)))) {
2355 if (cp->reset_pending)
2356 return hpsa_cmd_resolve_and_free(h, cp);
2357 if (cp->abort_pending)
2358 return hpsa_cmd_abort_and_free(h, cp, cmd);
2359 }
2360
c349775e
ST		 2361 if (cp->cmd_type == CMD_IOACCEL2)
2362 return process_ioaccel2_completion(h, cp, cmd, dev);
2363
6aa4c361 2364 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2365 if (ei->CommandStatus == 0)
2366 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2367
e1f7de0c
MG		 2368 /* For I/O accelerator commands, copy over some fields to the normal
2369 * CISS header used below for error handling.
2370 */
2371 if (cp->cmd_type == CMD_IOACCEL1) {
2372 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2373 cp->Header.SGList = scsi_sg_count(cmd);
2374 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2375 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2376 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2377 cp->Header.tag = c->tag;
e1f7de0c
MG		 2378 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2379 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2380
2381 /* Any RAID offload error results in retry which will use
2382 * the normal I/O path so the controller can handle whatever's
2383 * wrong.
2384 */
f3f01730 2385 if (is_logical_device(dev)) {
283b4a9b
SC		 2386 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2387 dev->offload_enabled = 0;
d604f533 2388 return hpsa_retry_cmd(h, cp);
283b4a9b 2389 }
e1f7de0c
MG		 2390 }
2391
edd16368
SC		 2392 /* an error has occurred */
2393 switch (ei->CommandStatus) {
2394
2395 case CMD_TARGET_STATUS:
9437ac43
SC		 2396 cmd->result |= ei->ScsiStatus;
2397 /* copy the sense data */
2398 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2399 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2400 else
2401 sense_data_size = sizeof(ei->SenseInfo);
2402 if (ei->SenseLen < sense_data_size)
2403 sense_data_size = ei->SenseLen;
2404 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2405 if (ei->ScsiStatus)
2406 decode_sense_data(ei->SenseInfo, sense_data_size,
2407 &sense_key, &asc, &ascq);
edd16368 2408 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2409 if (sense_key == ABORTED_COMMAND) {
2e311fba 2410 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2411 break;
2412 }
edd16368
SC		 2413 break;
2414 }
edd16368
SC		 2415 /* Problem was not a check condition
2416 * Pass it up to the upper layers...
2417 */
2418 if (ei->ScsiStatus) {
2419 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2420 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2421 "Returning result: 0x%x\n",
2422 cp, ei->ScsiStatus,
2423 sense_key, asc, ascq,
2424 cmd->result);
2425 } else { /* scsi status is zero??? How??? */
2426 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2427 "Returning no connection.\n", cp),
2428
2429 /* Ordinarily, this case should never happen,
2430 * but there is a bug in some released firmware
2431 * revisions that allows it to happen if, for
2432 * example, a 4100 backplane loses power and
2433 * the tape drive is in it. We assume that
2434 * it's a fatal error of some kind because we
2435 * can't show that it wasn't. We will make it
2436 * look like selection timeout since that is
2437 * the most common reason for this to occur,
2438 * and it's severe enough.
2439 */
2440
2441 cmd->result = DID_NO_CONNECT << 16;
2442 }
2443 break;
2444
2445 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2446 break;
2447 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2448 dev_warn(&h->pdev->dev,
2449 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2450 break;
2451 case CMD_INVALID: {
2452 /* print_bytes(cp, sizeof(*cp), 1, 0);
2453 print_cmd(cp); */
2454 /* We get CMD_INVALID if you address a non-existent device
2455 * instead of a selection timeout (no response). You will
2456 * see this if you yank out a drive, then try to access it.
2457 * This is kind of a shame because it means that any other
2458 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2459 * missing target. */
2460 cmd->result = DID_NO_CONNECT << 16;
2461 }
2462 break;
2463 case CMD_PROTOCOL_ERR:
256d0eaa 2464 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2465 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2466 cp->Request.CDB);
edd16368
SC		 2467 break;
2468 case CMD_HARDWARE_ERR:
2469 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2470 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2471 cp->Request.CDB);
edd16368
SC		 2472 break;
2473 case CMD_CONNECTION_LOST:
2474 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2475 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2476 cp->Request.CDB);
edd16368
SC		 2477 break;
2478 case CMD_ABORTED:
a58e7e53
WS		 2479 /* Return now to avoid calling scsi_done(). */
2480 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2481 case CMD_ABORT_FAILED:
2482 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2483 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2484 cp->Request.CDB);
edd16368
SC		 2485 break;
2486 case CMD_UNSOLICITED_ABORT:
f6e76055 2487 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2488 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2489 cp->Request.CDB);
edd16368
SC		 2490 break;
2491 case CMD_TIMEOUT:
2492 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2493 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2494 cp->Request.CDB);
edd16368 2495 break;
1d5e2ed0
SC		 2496 case CMD_UNABORTABLE:
2497 cmd->result = DID_ERROR << 16;
2498 dev_warn(&h->pdev->dev, "Command unabortable\n");
2499 break;
9437ac43
SC		 2500 case CMD_TMF_STATUS:
2501 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2502 cmd->result = DID_ERROR << 16;
2503 break;
283b4a9b
SC		 2504 case CMD_IOACCEL_DISABLED:
2505 /* This only handles the direct pass-through case since RAID
2506 * offload is handled above. Just attempt a retry.
2507 */
2508 cmd->result = DID_SOFT_ERROR << 16;
2509 dev_warn(&h->pdev->dev,
2510 "cp %p had HP SSD Smart Path error\n", cp);
2511 break;
edd16368
SC		 2512 default:
2513 cmd->result = DID_ERROR << 16;
2514 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2515 cp, ei->CommandStatus);
2516 }
8a0ff92c
WS		 2517
2518 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2519}
2520
edd16368
SC		 2521static void hpsa_pci_unmap(struct pci_dev *pdev,
2522 struct CommandList *c, int sg_used, int data_direction)
2523{
2524 int i;
edd16368 2525
50a0decf
SC		 2526 for (i = 0; i < sg_used; i++)
2527 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2528 le32_to_cpu(c->SG[i].Len),
2529 data_direction);
edd16368
SC		 2530}
2531
a2dac136 2532static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2533 struct CommandList *cp,
2534 unsigned char *buf,
2535 size_t buflen,
2536 int data_direction)
2537{
01a02ffc 2538 u64 addr64;
edd16368
SC		 2539
2540 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2541 cp->Header.SGList = 0;
50a0decf 2542 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2543 return 0;
edd16368
SC		 2544 }
2545
50a0decf 2546 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2547 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2548 /* Prevent subsequent unmap of something never mapped */
eceaae18 2549 cp->Header.SGList = 0;
50a0decf 2550 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2551 return -1;
eceaae18 2552 }
50a0decf
SC		 2553 cp->SG[0].Addr = cpu_to_le64(addr64);
2554 cp->SG[0].Len = cpu_to_le32(buflen);
2555 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2556 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2557 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2558 return 0;
edd16368
SC		 2559}
2560
25163bd5
WS		 2561#define NO_TIMEOUT ((unsigned long) -1)
2562#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2563static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2564 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2565{
2566 DECLARE_COMPLETION_ONSTACK(wait);
2567
2568 c->waiting = &wait;
25163bd5
WS		 2569 __enqueue_cmd_and_start_io(h, c, reply_queue);
2570 if (timeout_msecs == NO_TIMEOUT) {
2571 /* TODO: get rid of this no-timeout thing */
2572 wait_for_completion_io(&wait);
2573 return IO_OK;
2574 }
2575 if (!wait_for_completion_io_timeout(&wait,
2576 msecs_to_jiffies(timeout_msecs))) {
2577 dev_warn(&h->pdev->dev, "Command timed out.\n");
2578 return -ETIMEDOUT;
2579 }
2580 return IO_OK;
2581}
2582
2583static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2584 int reply_queue, unsigned long timeout_msecs)
2585{
2586 if (unlikely(lockup_detected(h))) {
2587 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2588 return IO_OK;
2589 }
2590 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2591}
2592
094963da
SC		 2593static u32 lockup_detected(struct ctlr_info *h)
2594{
2595 int cpu;
2596 u32 rc, *lockup_detected;
2597
2598 cpu = get_cpu();
2599 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2600 rc = *lockup_detected;
2601 put_cpu();
2602 return rc;
2603}
2604
9c2fc160 2605#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2606static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2607 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2608{
9c2fc160 2609 int backoff_time = 10, retry_count = 0;
25163bd5 2610 int rc;
edd16368
SC		 2611
2612 do {
7630abd0 2613 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2614 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2615 timeout_msecs);
2616 if (rc)
2617 break;
edd16368 2618 retry_count++;
9c2fc160
SC		 2619 if (retry_count > 3) {
2620 msleep(backoff_time);
2621 if (backoff_time < 1000)
2622 backoff_time *= 2;
2623 }
852af20a 2624 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2625 check_for_busy(h, c)) &&
2626 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2627 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2628 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2629 rc = -EIO;
2630 return rc;
edd16368
SC		 2631}
2632
d1e8beac
SC		 2633static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2634 struct CommandList *c)
edd16368 2635{
d1e8beac
SC		 2636 const u8 *cdb = c->Request.CDB;
2637 const u8 *lun = c->Header.LUN.LunAddrBytes;
2638
2639 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2640 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2641 txt, lun[0], lun[1], lun[2], lun[3],
2642 lun[4], lun[5], lun[6], lun[7],
2643 cdb[0], cdb[1], cdb[2], cdb[3],
2644 cdb[4], cdb[5], cdb[6], cdb[7],
2645 cdb[8], cdb[9], cdb[10], cdb[11],
2646 cdb[12], cdb[13], cdb[14], cdb[15]);
2647}
2648
2649static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2650 struct CommandList *cp)
2651{
2652 const struct ErrorInfo *ei = cp->err_info;
edd16368 2653 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2654 u8 sense_key, asc, ascq;
2655 int sense_len;
edd16368 2656
edd16368
SC		 2657 switch (ei->CommandStatus) {
2658 case CMD_TARGET_STATUS:
9437ac43
SC		 2659 if (ei->SenseLen > sizeof(ei->SenseInfo))
2660 sense_len = sizeof(ei->SenseInfo);
2661 else
2662 sense_len = ei->SenseLen;
2663 decode_sense_data(ei->SenseInfo, sense_len,
2664 &sense_key, &asc, &ascq);
d1e8beac
SC		 2665 hpsa_print_cmd(h, "SCSI status", cp);
2666 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2667 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2668 sense_key, asc, ascq);
d1e8beac 2669 else
9437ac43 2670 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2671 if (ei->ScsiStatus == 0)
2672 dev_warn(d, "SCSI status is abnormally zero. "
2673 "(probably indicates selection timeout "
2674 "reported incorrectly due to a known "
2675 "firmware bug, circa July, 2001.)\n");
2676 break;
2677 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2678 break;
2679 case CMD_DATA_OVERRUN:
d1e8beac 2680 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2681 break;
2682 case CMD_INVALID: {
2683 /* controller unfortunately reports SCSI passthru's
2684 * to non-existent targets as invalid commands.
2685 */
d1e8beac
SC		 2686 hpsa_print_cmd(h, "invalid command", cp);
2687 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2688 }
2689 break;
2690 case CMD_PROTOCOL_ERR:
d1e8beac 2691 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2692 break;
2693 case CMD_HARDWARE_ERR:
d1e8beac 2694 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2695 break;
2696 case CMD_CONNECTION_LOST:
d1e8beac 2697 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2698 break;
2699 case CMD_ABORTED:
d1e8beac 2700 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2701 break;
2702 case CMD_ABORT_FAILED:
d1e8beac 2703 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2704 break;
2705 case CMD_UNSOLICITED_ABORT:
d1e8beac 2706 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2707 break;
2708 case CMD_TIMEOUT:
d1e8beac 2709 hpsa_print_cmd(h, "timed out", cp);
edd16368 2710 break;
1d5e2ed0 2711 case CMD_UNABORTABLE:
d1e8beac 2712 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2713 break;
25163bd5
WS		 2714 case CMD_CTLR_LOCKUP:
2715 hpsa_print_cmd(h, "controller lockup detected", cp);
2716 break;
edd16368 2717 default:
d1e8beac
SC		 2718 hpsa_print_cmd(h, "unknown status", cp);
2719 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2720 ei->CommandStatus);
2721 }
2722}
2723
2724static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2725 u16 page, unsigned char *buf,
edd16368
SC		 2726 unsigned char bufsize)
2727{
2728 int rc = IO_OK;
2729 struct CommandList *c;
2730 struct ErrorInfo *ei;
2731
45fcb86e 2732 c = cmd_alloc(h);
edd16368 2733
a2dac136
SC		 2734 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2735 page, scsi3addr, TYPE_CMD)) {
2736 rc = -1;
2737 goto out;
2738 }
25163bd5
WS		 2739 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2740 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2741 if (rc)
2742 goto out;
edd16368
SC		 2743 ei = c->err_info;
2744 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2745 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2746 rc = -1;
2747 }
a2dac136 2748out:
45fcb86e 2749 cmd_free(h, c);
edd16368
SC		 2750 return rc;
2751}
2752
bf711ac6 2753static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2754 u8 reset_type, int reply_queue)
edd16368
SC		 2755{
2756 int rc = IO_OK;
2757 struct CommandList *c;
2758 struct ErrorInfo *ei;
2759
45fcb86e 2760 c = cmd_alloc(h);
edd16368 2761
edd16368 2762
a2dac136 2763 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2764 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2765 scsi3addr, TYPE_MSG);
25163bd5
WS		 2766 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2767 if (rc) {
2768 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2769 goto out;
2770 }
edd16368
SC		 2771 /* no unmap needed here because no data xfer. */
2772
2773 ei = c->err_info;
2774 if (ei->CommandStatus != 0) {
d1e8beac 2775 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2776 rc = -1;
2777 }
25163bd5 2778out:
45fcb86e 2779 cmd_free(h, c);
edd16368
SC		 2780 return rc;
2781}
2782
d604f533
WS		 2783static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2784 struct hpsa_scsi_dev_t *dev,
2785 unsigned char *scsi3addr)
2786{
2787 int i;
2788 bool match = false;
2789 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2790 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2791
2792 if (hpsa_is_cmd_idle(c))
2793 return false;
2794
2795 switch (c->cmd_type) {
2796 case CMD_SCSI:
2797 case CMD_IOCTL_PEND:
2798 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2799 sizeof(c->Header.LUN.LunAddrBytes));
2800 break;
2801
2802 case CMD_IOACCEL1:
2803 case CMD_IOACCEL2:
2804 if (c->phys_disk == dev) {
2805 /* HBA mode match */
2806 match = true;
2807 } else {
2808 /* Possible RAID mode -- check each phys dev. */
2809 /* FIXME: Do we need to take out a lock here? If
2810 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2811 * instead. */
2812 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2813 /* FIXME: an alternate test might be
2814 *
2815 * match = dev->phys_disk[i]->ioaccel_handle
2816 * == c2->scsi_nexus; */
2817 match = dev->phys_disk[i] == c->phys_disk;
2818 }
2819 }
2820 break;
2821
2822 case IOACCEL2_TMF:
2823 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2824 match = dev->phys_disk[i]->ioaccel_handle ==
2825 le32_to_cpu(ac->it_nexus);
2826 }
2827 break;
2828
2829 case 0: /* The command is in the middle of being initialized. */
2830 match = false;
2831 break;
2832
2833 default:
2834 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2835 c->cmd_type);
2836 BUG();
2837 }
2838
2839 return match;
2840}
2841
2842static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2843 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2844{
2845 int i;
2846 int rc = 0;
2847
2848 /* We can really only handle one reset at a time */
2849 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2850 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2851 return -EINTR;
2852 }
2853
2854 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2855
2856 for (i = 0; i < h->nr_cmds; i++) {
2857 struct CommandList *c = h->cmd_pool + i;
2858 int refcount = atomic_inc_return(&c->refcount);
2859
2860 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2861 unsigned long flags;
2862
2863 /*
2864 * Mark the target command as having a reset pending,
2865 * then lock a lock so that the command cannot complete
2866 * while we're considering it. If the command is not
2867 * idle then count it; otherwise revoke the event.
2868 */
2869 c->reset_pending = dev;
2870 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2871 if (!hpsa_is_cmd_idle(c))
2872 atomic_inc(&dev->reset_cmds_out);
2873 else
2874 c->reset_pending = NULL;
2875 spin_unlock_irqrestore(&h->lock, flags);
2876 }
2877
2878 cmd_free(h, c);
2879 }
2880
2881 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2882 if (!rc)
2883 wait_event(h->event_sync_wait_queue,
2884 atomic_read(&dev->reset_cmds_out) == 0 ||
2885 lockup_detected(h));
2886
2887 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2888 dev_warn(&h->pdev->dev,
2889 "Controller lockup detected during reset wait\n");
2890 rc = -ENODEV;
2891 }
d604f533
WS		 2892
2893 if (unlikely(rc))
2894 atomic_set(&dev->reset_cmds_out, 0);
2895
2896 mutex_unlock(&h->reset_mutex);
2897 return rc;
2898}
2899
edd16368
SC		 2900static void hpsa_get_raid_level(struct ctlr_info *h,
2901 unsigned char *scsi3addr, unsigned char *raid_level)
2902{
2903 int rc;
2904 unsigned char *buf;
2905
2906 *raid_level = RAID_UNKNOWN;
2907 buf = kzalloc(64, GFP_KERNEL);
2908 if (!buf)
2909 return;
b7bb24eb 2910 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2911 if (rc == 0)
2912 *raid_level = buf[8];
2913 if (*raid_level > RAID_UNKNOWN)
2914 *raid_level = RAID_UNKNOWN;
2915 kfree(buf);
2916 return;
2917}
2918
283b4a9b
SC		 2919#define HPSA_MAP_DEBUG
2920#ifdef HPSA_MAP_DEBUG
2921static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2922 struct raid_map_data *map_buff)
2923{
2924 struct raid_map_disk_data *dd = &map_buff->data[0];
2925 int map, row, col;
2926 u16 map_cnt, row_cnt, disks_per_row;
2927
2928 if (rc != 0)
2929 return;
2930
2ba8bfc8
SC		 2931 /* Show details only if debugging has been activated. */
2932 if (h->raid_offload_debug < 2)
2933 return;
2934
283b4a9b
SC		 2935 dev_info(&h->pdev->dev, "structure_size = %u\n",
2936 le32_to_cpu(map_buff->structure_size));
2937 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2938 le32_to_cpu(map_buff->volume_blk_size));
2939 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2940 le64_to_cpu(map_buff->volume_blk_cnt));
2941 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2942 map_buff->phys_blk_shift);
2943 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2944 map_buff->parity_rotation_shift);
2945 dev_info(&h->pdev->dev, "strip_size = %u\n",
2946 le16_to_cpu(map_buff->strip_size));
2947 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2948 le64_to_cpu(map_buff->disk_starting_blk));
2949 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2950 le64_to_cpu(map_buff->disk_blk_cnt));
2951 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2952 le16_to_cpu(map_buff->data_disks_per_row));
2953 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2954 le16_to_cpu(map_buff->metadata_disks_per_row));
2955 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2956 le16_to_cpu(map_buff->row_cnt));
2957 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2958 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2959 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2960 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2961 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2962 le16_to_cpu(map_buff->flags) &
2963 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2964 dev_info(&h->pdev->dev, "dekindex = %u\n",
2965 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2966 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2967 for (map = 0; map < map_cnt; map++) {
2968 dev_info(&h->pdev->dev, "Map%u:\n", map);
2969 row_cnt = le16_to_cpu(map_buff->row_cnt);
2970 for (row = 0; row < row_cnt; row++) {
2971 dev_info(&h->pdev->dev, " Row%u:\n", row);
2972 disks_per_row =
2973 le16_to_cpu(map_buff->data_disks_per_row);
2974 for (col = 0; col < disks_per_row; col++, dd++)
2975 dev_info(&h->pdev->dev,
2976 " D%02u: h=0x%04x xor=%u,%u\n",
2977 col, dd->ioaccel_handle,
2978 dd->xor_mult[0], dd->xor_mult[1]);
2979 disks_per_row =
2980 le16_to_cpu(map_buff->metadata_disks_per_row);
2981 for (col = 0; col < disks_per_row; col++, dd++)
2982 dev_info(&h->pdev->dev,
2983 " M%02u: h=0x%04x xor=%u,%u\n",
2984 col, dd->ioaccel_handle,
2985 dd->xor_mult[0], dd->xor_mult[1]);
2986 }
2987 }
2988}
2989#else
2990static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2991 __attribute__((unused)) int rc,
2992 __attribute__((unused)) struct raid_map_data *map_buff)
2993{
2994}
2995#endif
2996
2997static int hpsa_get_raid_map(struct ctlr_info *h,
2998 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2999{
3000 int rc = 0;
3001 struct CommandList *c;
3002 struct ErrorInfo *ei;
3003
45fcb86e 3004 c = cmd_alloc(h);
bf43caf3 3005
283b4a9b
SC		 3006 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3007 sizeof(this_device->raid_map), 0,
3008 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3009 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3010 cmd_free(h, c);
3011 return -1;
283b4a9b 3012 }
25163bd5
WS		 3013 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3014 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3015 if (rc)
3016 goto out;
283b4a9b
SC		 3017 ei = c->err_info;
3018 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3019 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3020 rc = -1;
3021 goto out;
283b4a9b 3022 }
45fcb86e 3023 cmd_free(h, c);
283b4a9b
SC		 3024
3025 /* @todo in the future, dynamically allocate RAID map memory */
3026 if (le32_to_cpu(this_device->raid_map.structure_size) >
3027 sizeof(this_device->raid_map)) {
3028 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3029 rc = -1;
3030 }
3031 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3032 return rc;
25163bd5
WS		 3033out:
3034 cmd_free(h, c);
3035 return rc;
283b4a9b
SC		 3036}
3037
66749d0d
ST		 3038static int hpsa_bmic_id_controller(struct ctlr_info *h,
3039 struct bmic_identify_controller *buf, size_t bufsize)
3040{
3041 int rc = IO_OK;
3042 struct CommandList *c;
3043 struct ErrorInfo *ei;
3044
3045 c = cmd_alloc(h);
3046
3047 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3048 0, RAID_CTLR_LUNID, TYPE_CMD);
3049 if (rc)
3050 goto out;
3051
3052 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3053 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3054 if (rc)
3055 goto out;
3056 ei = c->err_info;
3057 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3058 hpsa_scsi_interpret_error(h, c);
3059 rc = -1;
3060 }
3061out:
3062 cmd_free(h, c);
3063 return rc;
3064}
3065
3066
03383736
DB		 3067static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3068 unsigned char scsi3addr[], u16 bmic_device_index,
3069 struct bmic_identify_physical_device *buf, size_t bufsize)
3070{
3071 int rc = IO_OK;
3072 struct CommandList *c;
3073 struct ErrorInfo *ei;
3074
3075 c = cmd_alloc(h);
3076 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3077 0, RAID_CTLR_LUNID, TYPE_CMD);
3078 if (rc)
3079 goto out;
3080
3081 c->Request.CDB[2] = bmic_device_index & 0xff;
3082 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3083
25163bd5
WS		 3084 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3085 NO_TIMEOUT);
03383736
DB		 3086 ei = c->err_info;
3087 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3088 hpsa_scsi_interpret_error(h, c);
3089 rc = -1;
3090 }
3091out:
3092 cmd_free(h, c);
3093 return rc;
3094}
3095
1b70150a
SC		 3096static int hpsa_vpd_page_supported(struct ctlr_info *h,
3097 unsigned char scsi3addr[], u8 page)
3098{
3099 int rc;
3100 int i;
3101 int pages;
3102 unsigned char *buf, bufsize;
3103
3104 buf = kzalloc(256, GFP_KERNEL);
3105 if (!buf)
3106 return 0;
3107
3108 /* Get the size of the page list first */
3109 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3110 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3111 buf, HPSA_VPD_HEADER_SZ);
3112 if (rc != 0)
3113 goto exit_unsupported;
3114 pages = buf[3];
3115 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3116 bufsize = pages + HPSA_VPD_HEADER_SZ;
3117 else
3118 bufsize = 255;
3119
3120 /* Get the whole VPD page list */
3121 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3122 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3123 buf, bufsize);
3124 if (rc != 0)
3125 goto exit_unsupported;
3126
3127 pages = buf[3];
3128 for (i = 1; i <= pages; i++)
3129 if (buf[3 + i] == page)
3130 goto exit_supported;
3131exit_unsupported:
3132 kfree(buf);
3133 return 0;
3134exit_supported:
3135 kfree(buf);
3136 return 1;
3137}
3138
283b4a9b
SC		 3139static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3140 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3141{
3142 int rc;
3143 unsigned char *buf;
3144 u8 ioaccel_status;
3145
3146 this_device->offload_config = 0;
3147 this_device->offload_enabled = 0;
41ce4c35 3148 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3149
3150 buf = kzalloc(64, GFP_KERNEL);
3151 if (!buf)
3152 return;
1b70150a
SC		 3153 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3154 goto out;
283b4a9b 3155 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3156 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3157 if (rc != 0)
3158 goto out;
3159
3160#define IOACCEL_STATUS_BYTE 4
3161#define OFFLOAD_CONFIGURED_BIT 0x01
3162#define OFFLOAD_ENABLED_BIT 0x02
3163 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3164 this_device->offload_config =
3165 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3166 if (this_device->offload_config) {
3167 this_device->offload_enabled =
3168 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3169 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3170 this_device->offload_enabled = 0;
3171 }
41ce4c35 3172 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3173out:
3174 kfree(buf);
3175 return;
3176}
3177
edd16368
SC		 3178/* Get the device id from inquiry page 0x83 */
3179static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3180 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3181{
3182 int rc;
3183 unsigned char *buf;
3184
3185 if (buflen > 16)
3186 buflen = 16;
3187 buf = kzalloc(64, GFP_KERNEL);
3188 if (!buf)
a84d794d 3189 return -ENOMEM;
b7bb24eb 3190 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368 3191 if (rc == 0)
75d23d89
DB		 3192 memcpy(device_id, &buf[index], buflen);
3193
edd16368 3194 kfree(buf);
75d23d89 3195
edd16368
SC		 3196 return rc != 0;
3197}
3198
3199static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3200 void *buf, int bufsize,
edd16368
SC		 3201 int extended_response)
3202{
3203 int rc = IO_OK;
3204 struct CommandList *c;
3205 unsigned char scsi3addr[8];
3206 struct ErrorInfo *ei;
3207
45fcb86e 3208 c = cmd_alloc(h);
bf43caf3 3209
e89c0ae7
SC		 3210 /* address the controller */
3211 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3212 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3213 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3214 rc = -1;
3215 goto out;
3216 }
edd16368
SC		 3217 if (extended_response)
3218 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3219 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3220 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3221 if (rc)
3222 goto out;
edd16368
SC		 3223 ei = c->err_info;
3224 if (ei->CommandStatus != 0 &&
3225 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3226 hpsa_scsi_interpret_error(h, c);
edd16368 3227 rc = -1;
283b4a9b 3228 } else {
03383736
DB		 3229 struct ReportLUNdata *rld = buf;
3230
3231 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3232 dev_err(&h->pdev->dev,
3233 "report luns requested format %u, got %u\n",
3234 extended_response,
03383736 3235 rld->extended_response_flag);
283b4a9b
SC		 3236 rc = -1;
3237 }
edd16368 3238 }
a2dac136 3239out:
45fcb86e 3240 cmd_free(h, c);
edd16368
SC		 3241 return rc;
3242}
3243
3244static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3245 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3246{
03383736
DB		 3247 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3248 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3249}
3250
3251static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3252 struct ReportLUNdata *buf, int bufsize)
3253{
3254 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3255}
3256
3257static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3258 int bus, int target, int lun)
3259{
3260 device->bus = bus;
3261 device->target = target;
3262 device->lun = lun;
3263}
3264
9846590e
SC		 3265/* Use VPD inquiry to get details of volume status */
3266static int hpsa_get_volume_status(struct ctlr_info *h,
3267 unsigned char scsi3addr[])
3268{
3269 int rc;
3270 int status;
3271 int size;
3272 unsigned char *buf;
3273
3274 buf = kzalloc(64, GFP_KERNEL);
3275 if (!buf)
3276 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3277
3278 /* Does controller have VPD for logical volume status? */
24a4b078 3279 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3280 goto exit_failed;
9846590e
SC		 3281
3282 /* Get the size of the VPD return buffer */
3283 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3284 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3285 if (rc != 0)
9846590e 3286 goto exit_failed;
9846590e
SC		 3287 size = buf[3];
3288
3289 /* Now get the whole VPD buffer */
3290 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3291 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3292 if (rc != 0)
9846590e 3293 goto exit_failed;
9846590e
SC		 3294 status = buf[4]; /* status byte */
3295
3296 kfree(buf);
3297 return status;
3298exit_failed:
3299 kfree(buf);
3300 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3301}
3302
3303/* Determine offline status of a volume.
3304 * Return either:
3305 * 0 (not offline)
67955ba3 3306 * 0xff (offline for unknown reasons)
9846590e
SC		 3307 * # (integer code indicating one of several NOT READY states
3308 * describing why a volume is to be kept offline)
3309 */
67955ba3 3310static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3311 unsigned char scsi3addr[])
3312{
3313 struct CommandList *c;
9437ac43
SC		 3314 unsigned char *sense;
3315 u8 sense_key, asc, ascq;
3316 int sense_len;
25163bd5 3317 int rc, ldstat = 0;
9846590e
SC		 3318 u16 cmd_status;
3319 u8 scsi_status;
3320#define ASC_LUN_NOT_READY 0x04
3321#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3322#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3323
3324 c = cmd_alloc(h);
bf43caf3 3325
9846590e 3326 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3327 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3328 if (rc) {
3329 cmd_free(h, c);
3330 return 0;
3331 }
9846590e 3332 sense = c->err_info->SenseInfo;
9437ac43
SC		 3333 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3334 sense_len = sizeof(c->err_info->SenseInfo);
3335 else
3336 sense_len = c->err_info->SenseLen;
3337 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3338 cmd_status = c->err_info->CommandStatus;
3339 scsi_status = c->err_info->ScsiStatus;
3340 cmd_free(h, c);
3341 /* Is the volume 'not ready'? */
3342 if (cmd_status != CMD_TARGET_STATUS ||
3343 scsi_status != SAM_STAT_CHECK_CONDITION ||
3344 sense_key != NOT_READY ||
3345 asc != ASC_LUN_NOT_READY) {
3346 return 0;
3347 }
3348
3349 /* Determine the reason for not ready state */
3350 ldstat = hpsa_get_volume_status(h, scsi3addr);
3351
3352 /* Keep volume offline in certain cases: */
3353 switch (ldstat) {
3354 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3355 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3356 case HPSA_LV_UNDERGOING_RPI:
3357 case HPSA_LV_PENDING_RPI:
3358 case HPSA_LV_ENCRYPTED_NO_KEY:
3359 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3360 case HPSA_LV_UNDERGOING_ENCRYPTION:
3361 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3362 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3363 return ldstat;
3364 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3365 /* If VPD status page isn't available,
3366 * use ASC/ASCQ to determine state
3367 */
3368 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3369 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3370 return ldstat;
3371 break;
3372 default:
3373 break;
3374 }
3375 return 0;
3376}
3377
9b5c48c2
SC		 3378/*
3379 * Find out if a logical device supports aborts by simply trying one.
3380 * Smart Array may claim not to support aborts on logical drives, but
3381 * if a MSA2000 * is connected, the drives on that will be presented
3382 * by the Smart Array as logical drives, and aborts may be sent to
3383 * those devices successfully. So the simplest way to find out is
3384 * to simply try an abort and see how the device responds.
3385 */
3386static int hpsa_device_supports_aborts(struct ctlr_info *h,
3387 unsigned char *scsi3addr)
3388{
3389 struct CommandList *c;
3390 struct ErrorInfo *ei;
3391 int rc = 0;
3392
3393 u64 tag = (u64) -1; /* bogus tag */
3394
3395 /* Assume that physical devices support aborts */
3396 if (!is_logical_dev_addr_mode(scsi3addr))
3397 return 1;
3398
3399 c = cmd_alloc(h);
bf43caf3 3400
9b5c48c2
SC		 3401 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3402 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3403 /* no unmap needed here because no data xfer. */
3404 ei = c->err_info;
3405 switch (ei->CommandStatus) {
3406 case CMD_INVALID:
3407 rc = 0;
3408 break;
3409 case CMD_UNABORTABLE:
3410 case CMD_ABORT_FAILED:
3411 rc = 1;
3412 break;
9437ac43
SC		 3413 case CMD_TMF_STATUS:
3414 rc = hpsa_evaluate_tmf_status(h, c);
3415 break;
9b5c48c2
SC		 3416 default:
3417 rc = 0;
3418 break;
3419 }
3420 cmd_free(h, c);
3421 return rc;
3422}
3423
75d23d89
DB		 3424static void sanitize_inquiry_string(unsigned char *s, int len)
3425{
3426 bool terminated = false;
3427
3428 for (; len > 0; (--len, ++s)) {
3429 if (*s == 0)
3430 terminated = true;
3431 if (terminated || *s < 0x20 || *s > 0x7e)
3432 *s = ' ';
3433 }
3434}
3435
edd16368 3436static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3437 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3438 unsigned char *is_OBDR_device)
edd16368 3439{
0b0e1d6c
SC		 3440
3441#define OBDR_SIG_OFFSET 43
3442#define OBDR_TAPE_SIG "$DR-10"
3443#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3444#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3445
ea6d3bc3 3446 unsigned char *inq_buff;
0b0e1d6c 3447 unsigned char *obdr_sig;
683fc444 3448 int rc = 0;
edd16368 3449
ea6d3bc3 3450 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3451 if (!inq_buff) {
3452 rc = -ENOMEM;
edd16368 3453 goto bail_out;
683fc444 3454 }
edd16368 3455
edd16368
SC		 3456 /* Do an inquiry to the device to see what it is. */
3457 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3458 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3459 /* Inquiry failed (msg printed already) */
3460 dev_err(&h->pdev->dev,
3461 "hpsa_update_device_info: inquiry failed\n");
683fc444 3462 rc = -EIO;
edd16368
SC		 3463 goto bail_out;
3464 }
3465
75d23d89
DB		 3466 sanitize_inquiry_string(&inq_buff[8], 8);
3467 sanitize_inquiry_string(&inq_buff[16], 16);
3468
edd16368
SC		 3469 this_device->devtype = (inq_buff[0] & 0x1f);
3470 memcpy(this_device->scsi3addr, scsi3addr, 8);
3471 memcpy(this_device->vendor, &inq_buff[8],
3472 sizeof(this_device->vendor));
3473 memcpy(this_device->model, &inq_buff[16],
3474 sizeof(this_device->model));
edd16368
SC		 3475 memset(this_device->device_id, 0,
3476 sizeof(this_device->device_id));
75d23d89 3477 hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
edd16368
SC		 3478 sizeof(this_device->device_id));
3479
3480 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3481 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3482 int volume_offline;
3483
edd16368 3484 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3485 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3486 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3487 volume_offline = hpsa_volume_offline(h, scsi3addr);
3488 if (volume_offline < 0 || volume_offline > 0xff)
3489 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3490 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3491 } else {
edd16368 3492 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3493 this_device->offload_config = 0;
3494 this_device->offload_enabled = 0;
41ce4c35 3495 this_device->offload_to_be_enabled = 0;
a3144e0b 3496 this_device->hba_ioaccel_enabled = 0;
9846590e 3497 this_device->volume_offline = 0;
03383736 3498 this_device->queue_depth = h->nr_cmds;
283b4a9b 3499 }
edd16368 3500
0b0e1d6c
SC		 3501 if (is_OBDR_device) {
3502 /* See if this is a One-Button-Disaster-Recovery device
3503 * by looking for "$DR-10" at offset 43 in inquiry data.
3504 */
3505 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3506 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3507 strncmp(obdr_sig, OBDR_TAPE_SIG,
3508 OBDR_SIG_LEN) == 0);
3509 }
edd16368
SC		 3510 kfree(inq_buff);
3511 return 0;
3512
3513bail_out:
3514 kfree(inq_buff);
683fc444 3515 return rc;
edd16368
SC		 3516}
3517
9b5c48c2
SC		 3518static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3519 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3520{
3521 unsigned long flags;
3522 int rc, entry;
3523 /*
3524 * See if this device supports aborts. If we already know
3525 * the device, we already know if it supports aborts, otherwise
3526 * we have to find out if it supports aborts by trying one.
3527 */
3528 spin_lock_irqsave(&h->devlock, flags);
3529 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3530 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3531 entry >= 0 && entry < h->ndevices) {
3532 dev->supports_aborts = h->dev[entry]->supports_aborts;
3533 spin_unlock_irqrestore(&h->devlock, flags);
3534 } else {
3535 spin_unlock_irqrestore(&h->devlock, flags);
3536 dev->supports_aborts =
3537 hpsa_device_supports_aborts(h, scsi3addr);
3538 if (dev->supports_aborts < 0)
3539 dev->supports_aborts = 0;
3540 }
3541}
3542
c795505a
KB		 3543/*
3544 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 3545 * Logical drive target and lun are assigned at this time, but
3546 * physical device lun and target assignment are deferred (assigned
3547 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 3548*/
edd16368 3549static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3550 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3551{
c795505a 3552 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 3553
3554 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3555 /* physical device, target and lun filled in later */
edd16368 3556 if (is_hba_lunid(lunaddrbytes))
c795505a
KB		 3557 hpsa_set_bus_target_lun(device,
3558 HPSA_HBA_BUS, 0, lunid & 0x3fff);
edd16368 3559 else
1f310bde 3560 /* defer target, lun assignment for physical devices */
c795505a
KB		 3561 hpsa_set_bus_target_lun(device,
3562 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 3563 return;
3564 }
3565 /* It's a logical device */
66749d0d 3566 if (device->external) {
1f310bde 3567 hpsa_set_bus_target_lun(device,
c795505a
KB		 3568 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
3569 lunid & 0x00ff);
1f310bde 3570 return;
edd16368 3571 }
c795505a
KB		 3572 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
3573 0, lunid & 0x3fff);
edd16368
SC		 3574}
3575
edd16368 3576
54b6e9e9
ST		 3577/*
3578 * Get address of physical disk used for an ioaccel2 mode command:
3579 * 1. Extract ioaccel2 handle from the command.
3580 * 2. Find a matching ioaccel2 handle from list of physical disks.
3581 * 3. Return:
3582 * 1 and set scsi3addr to address of matching physical
3583 * 0 if no matching physical disk was found.
3584 */
3585static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3586 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3587{
41ce4c35
SC		 3588 struct io_accel2_cmd *c2 =
3589 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3590 unsigned long flags;
54b6e9e9 3591 int i;
54b6e9e9 3592
41ce4c35
SC		 3593 spin_lock_irqsave(&h->devlock, flags);
3594 for (i = 0; i < h->ndevices; i++)
3595 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3596 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3597 sizeof(h->dev[i]->scsi3addr));
3598 spin_unlock_irqrestore(&h->devlock, flags);
3599 return 1;
3600 }
3601 spin_unlock_irqrestore(&h->devlock, flags);
3602 return 0;
54b6e9e9 3603}
41ce4c35 3604
66749d0d
ST		 3605static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
3606 int i, int nphysicals, int nlocal_logicals)
3607{
3608 /* In report logicals, local logicals are listed first,
3609 * then any externals.
3610 */
3611 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3612
3613 if (i == raid_ctlr_position)
3614 return 0;
3615
3616 if (i < logicals_start)
3617 return 0;
3618
3619 /* i is in logicals range, but still within local logicals */
3620 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
3621 return 0;
3622
3623 return 1; /* it's an external lun */
3624}
3625
edd16368
SC		 3626/*
3627 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3628 * logdev. The number of luns in physdev and logdev are returned in
3629 * *nphysicals and *nlogicals, respectively.
3630 * Returns 0 on success, -1 otherwise.
3631 */
3632static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3633 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3634 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3635{
03383736 3636 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3637 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3638 return -1;
3639 }
03383736 3640 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3641 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3642 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3643 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3644 *nphysicals = HPSA_MAX_PHYS_LUN;
3645 }
03383736 3646 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3647 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3648 return -1;
3649 }
6df1e954 3650 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3651 /* Reject Logicals in excess of our max capability. */
3652 if (*nlogicals > HPSA_MAX_LUN) {
3653 dev_warn(&h->pdev->dev,
3654 "maximum logical LUNs (%d) exceeded. "
3655 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3656 *nlogicals - HPSA_MAX_LUN);
3657 *nlogicals = HPSA_MAX_LUN;
3658 }
3659 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3660 dev_warn(&h->pdev->dev,
3661 "maximum logical + physical LUNs (%d) exceeded. "
3662 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3663 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3664 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3665 }
3666 return 0;
3667}
3668
42a91641
DB		 3669static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3670 int i, int nphysicals, int nlogicals,
a93aa1fe 3671 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3672 struct ReportLUNdata *logdev_list)
3673{
3674 /* Helper function, figure out where the LUN ID info is coming from
3675 * given index i, lists of physical and logical devices, where in
3676 * the list the raid controller is supposed to appear (first or last)
3677 */
3678
3679 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3680 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3681
3682 if (i == raid_ctlr_position)
3683 return RAID_CTLR_LUNID;
3684
3685 if (i < logicals_start)
d5b5d964
SC		 3686 return &physdev_list->LUN[i -
3687 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3688
3689 if (i < last_device)
3690 return &logdev_list->LUN[i - nphysicals -
3691 (raid_ctlr_position == 0)][0];
3692 BUG();
3693 return NULL;
3694}
3695
03383736
DB		 3696/* get physical drive ioaccel handle and queue depth */
3697static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3698 struct hpsa_scsi_dev_t *dev,
f2039b03 3699 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 3700 struct bmic_identify_physical_device *id_phys)
3701{
3702 int rc;
f2039b03 3703 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 3704
3705 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 3706 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 3707 dev->hba_ioaccel_enabled = 1;
03383736 3708 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 3709 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3710 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 3711 sizeof(*id_phys));
3712 if (!rc)
3713 /* Reserve space for FW operations */
3714#define DRIVE_CMDS_RESERVED_FOR_FW 2
3715#define DRIVE_QUEUE_DEPTH 7
3716 dev->queue_depth =
3717 le16_to_cpu(id_phys->current_queue_depth_limit) -
3718 DRIVE_CMDS_RESERVED_FOR_FW;
3719 else
3720 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3721}
3722
8270b862 3723static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 3724 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 3725 struct bmic_identify_physical_device *id_phys)
3726{
f2039b03
DB		 3727 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3728
3729 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 3730 this_device->hba_ioaccel_enabled = 1;
3731
3732 memcpy(&this_device->active_path_index,
3733 &id_phys->active_path_number,
3734 sizeof(this_device->active_path_index));
3735 memcpy(&this_device->path_map,
3736 &id_phys->redundant_path_present_map,
3737 sizeof(this_device->path_map));
3738 memcpy(&this_device->box,
3739 &id_phys->alternate_paths_phys_box_on_port,
3740 sizeof(this_device->box));
3741 memcpy(&this_device->phys_connector,
3742 &id_phys->alternate_paths_phys_connector,
3743 sizeof(this_device->phys_connector));
3744 memcpy(&this_device->bay,
3745 &id_phys->phys_bay_in_box,
3746 sizeof(this_device->bay));
3747}
3748
66749d0d
ST		 3749/* get number of local logical disks. */
3750static int hpsa_set_local_logical_count(struct ctlr_info *h,
3751 struct bmic_identify_controller *id_ctlr,
3752 u32 *nlocals)
3753{
3754 int rc;
3755
3756 if (!id_ctlr) {
3757 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
3758 __func__);
3759 return -ENOMEM;
3760 }
3761 memset(id_ctlr, 0, sizeof(*id_ctlr));
3762 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
3763 if (!rc)
3764 if (id_ctlr->configured_logical_drive_count < 256)
3765 *nlocals = id_ctlr->configured_logical_drive_count;
3766 else
3767 *nlocals = le16_to_cpu(
3768 id_ctlr->extended_logical_unit_count);
3769 else
3770 *nlocals = -1;
3771 return rc;
3772}
3773
3774
8aa60681 3775static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 3776{
3777 /* the idea here is we could get notified
3778 * that some devices have changed, so we do a report
3779 * physical luns and report logical luns cmd, and adjust
3780 * our list of devices accordingly.
3781 *
3782 * The scsi3addr's of devices won't change so long as the
3783 * adapter is not reset. That means we can rescan and
3784 * tell which devices we already know about, vs. new
3785 * devices, vs. disappearing devices.
3786 */
a93aa1fe 3787 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3788 struct ReportLUNdata *logdev_list = NULL;
03383736 3789 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 3790 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 3791 u32 nphysicals = 0;
3792 u32 nlogicals = 0;
66749d0d 3793 u32 nlocal_logicals = 0;
01a02ffc 3794 u32 ndev_allocated = 0;
edd16368
SC		 3795 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3796 int ncurrent = 0;
4f4eb9f1 3797 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3798 int raid_ctlr_position;
04fa2f44 3799 bool physical_device;
aca4a520 3800 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3801
cfe5badc 3802 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3803 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3804 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3805 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3806 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 3807 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 3808
03383736 3809 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 3810 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 3811 dev_err(&h->pdev->dev, "out of memory\n");
3812 goto out;
3813 }
3814 memset(lunzerobits, 0, sizeof(lunzerobits));
3815
853633e8
DB		 3816 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
3817
03383736 3818 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 3819 logdev_list, &nlogicals)) {
3820 h->drv_req_rescan = 1;
edd16368 3821 goto out;
853633e8 3822 }
edd16368 3823
66749d0d
ST		 3824 /* Set number of local logicals (non PTRAID) */
3825 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
3826 dev_warn(&h->pdev->dev,
3827 "%s: Can't determine number of local logical devices.\n",
3828 __func__);
3829 }
3830
aca4a520
ST		 3831 /* We might see up to the maximum number of logical and physical disks
3832 * plus external target devices, and a device for the local RAID
3833 * controller.
edd16368 3834 */
aca4a520 3835 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3836
3837 /* Allocate the per device structures */
3838 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3839 if (i >= HPSA_MAX_DEVICES) {
3840 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3841 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3842 ndevs_to_allocate - HPSA_MAX_DEVICES);
3843 break;
3844 }
3845
edd16368
SC		 3846 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3847 if (!currentsd[i]) {
3848 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3849 __FILE__, __LINE__);
853633e8 3850 h->drv_req_rescan = 1;
edd16368
SC		 3851 goto out;
3852 }
3853 ndev_allocated++;
3854 }
3855
8645291b 3856 if (is_scsi_rev_5(h))
339b2b14
SC		 3857 raid_ctlr_position = 0;
3858 else
3859 raid_ctlr_position = nphysicals + nlogicals;
3860
edd16368 3861 /* adjust our table of devices */
4f4eb9f1 3862 n_ext_target_devs = 0;
edd16368 3863 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3864 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 3865 int rc = 0;
f2039b03 3866 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 3867
04fa2f44
KB		 3868 physical_device = i < nphysicals + (raid_ctlr_position == 0);
3869
edd16368 3870 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3871 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3872 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3873
3874 /* skip masked non-disk devices */
04fa2f44
KB		 3875 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
3876 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
3877 continue;
edd16368
SC		 3878
3879 /* Get device type, vendor, model, device id */
683fc444
DB		 3880 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3881 &is_OBDR);
3882 if (rc == -ENOMEM) {
3883 dev_warn(&h->pdev->dev,
3884 "Out of memory, rescan deferred.\n");
853633e8 3885 h->drv_req_rescan = 1;
683fc444 3886 goto out;
853633e8 3887 }
683fc444
DB		 3888 if (rc) {
3889 dev_warn(&h->pdev->dev,
3890 "Inquiry failed, skipping device.\n");
3891 continue;
3892 }
3893
66749d0d
ST		 3894 /* Determine if this is a lun from an external target array */
3895 tmpdevice->external =
3896 figure_external_status(h, raid_ctlr_position, i,
3897 nphysicals, nlocal_logicals);
3898
1f310bde 3899 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3900 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3901 this_device = currentsd[ncurrent];
3902
34592254
ST		 3903 /* Turn on discovery_polling if there are ext target devices.
3904 * Event-based change notification is unreliable for those.
3905 */
3906 if (!h->discovery_polling) {
3907 if (tmpdevice->external) {
3908 h->discovery_polling = 1;
3909 dev_info(&h->pdev->dev,
3910 "External target, activate discovery polling.\n");
3911 }
3912 }
3913
3914
edd16368 3915 *this_device = *tmpdevice;
04fa2f44 3916 this_device->physical_device = physical_device;
edd16368 3917
04fa2f44
KB		 3918 /*
3919 * Expose all devices except for physical devices that
3920 * are masked.
3921 */
3922 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 3923 this_device->expose_device = 0;
3924 else
3925 this_device->expose_device = 1;
41ce4c35 3926
edd16368 3927 switch (this_device->devtype) {
0b0e1d6c 3928 case TYPE_ROM:
edd16368
SC		 3929 /* We don't *really* support actual CD-ROM devices,
3930 * just "One Button Disaster Recovery" tape drive
3931 * which temporarily pretends to be a CD-ROM drive.
3932 * So we check that the device is really an OBDR tape
3933 * device by checking for "$DR-10" in bytes 43-48 of
3934 * the inquiry data.
3935 */
0b0e1d6c
SC		 3936 if (is_OBDR)
3937 ncurrent++;
edd16368
SC		 3938 break;
3939 case TYPE_DISK:
04fa2f44 3940 if (this_device->physical_device) {
b9092b79
KB		 3941 /* The disk is in HBA mode. */
3942 /* Never use RAID mapper in HBA mode. */
ecf418d1 3943 this_device->offload_enabled = 0;
b9092b79 3944 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 3945 physdev_list, phys_dev_index, id_phys);
3946 hpsa_get_path_info(this_device,
3947 physdev_list, phys_dev_index, id_phys);
b9092b79 3948 }
ecf418d1 3949 ncurrent++;
edd16368
SC		 3950 break;
3951 case TYPE_TAPE:
3952 case TYPE_MEDIUM_CHANGER:
41ce4c35 3953 case TYPE_ENCLOSURE:
b9092b79 3954 ncurrent++;
41ce4c35 3955 break;
edd16368
SC		 3956 case TYPE_RAID:
3957 /* Only present the Smartarray HBA as a RAID controller.
3958 * If it's a RAID controller other than the HBA itself
3959 * (an external RAID controller, MSA500 or similar)
3960 * don't present it.
3961 */
3962 if (!is_hba_lunid(lunaddrbytes))
3963 break;
3964 ncurrent++;
3965 break;
3966 default:
3967 break;
3968 }
cfe5badc 3969 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3970 break;
3971 }
8aa60681 3972 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 3973out:
3974 kfree(tmpdevice);
3975 for (i = 0; i < ndev_allocated; i++)
3976 kfree(currentsd[i]);
3977 kfree(currentsd);
edd16368
SC		 3978 kfree(physdev_list);
3979 kfree(logdev_list);
66749d0d 3980 kfree(id_ctlr);
03383736 3981 kfree(id_phys);
edd16368
SC		 3982}
3983
ec5cbf04
WS		 3984static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3985 struct scatterlist *sg)
3986{
3987 u64 addr64 = (u64) sg_dma_address(sg);
3988 unsigned int len = sg_dma_len(sg);
3989
3990 desc->Addr = cpu_to_le64(addr64);
3991 desc->Len = cpu_to_le32(len);
3992 desc->Ext = 0;
3993}
3994
c7ee65b3
WS		 3995/*
3996 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3997 * dma mapping and fills in the scatter gather entries of the
3998 * hpsa command, cp.
3999 */
33a2ffce 4000static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4001 struct CommandList *cp,
4002 struct scsi_cmnd *cmd)
4003{
edd16368 4004 struct scatterlist *sg;
b3a7ba7c 4005 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4006 struct SGDescriptor *curr_sg;
edd16368 4007
33a2ffce 4008 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4009
4010 use_sg = scsi_dma_map(cmd);
4011 if (use_sg < 0)
4012 return use_sg;
4013
4014 if (!use_sg)
4015 goto sglist_finished;
4016
b3a7ba7c
WS		 4017 /*
4018 * If the number of entries is greater than the max for a single list,
4019 * then we have a chained list; we will set up all but one entry in the
4020 * first list (the last entry is saved for link information);
4021 * otherwise, we don't have a chained list and we'll set up at each of
4022 * the entries in the one list.
4023 */
33a2ffce 4024 curr_sg = cp->SG;
b3a7ba7c
WS		 4025 chained = use_sg > h->max_cmd_sg_entries;
4026 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4027 last_sg = scsi_sg_count(cmd) - 1;
4028 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4029 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4030 curr_sg++;
4031 }
ec5cbf04 4032
b3a7ba7c
WS		 4033 if (chained) {
4034 /*
4035 * Continue with the chained list. Set curr_sg to the chained
4036 * list. Modify the limit to the total count less the entries
4037 * we've already set up. Resume the scan at the list entry
4038 * where the previous loop left off.
4039 */
4040 curr_sg = h->cmd_sg_list[cp->cmdindex];
4041 sg_limit = use_sg - sg_limit;
4042 for_each_sg(sg, sg, sg_limit, i) {
4043 hpsa_set_sg_descriptor(curr_sg, sg);
4044 curr_sg++;
4045 }
4046 }
4047
ec5cbf04 4048 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4049 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4050
4051 if (use_sg + chained > h->maxSG)
4052 h->maxSG = use_sg + chained;
4053
4054 if (chained) {
4055 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4056 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4057 if (hpsa_map_sg_chain_block(h, cp)) {
4058 scsi_dma_unmap(cmd);
4059 return -1;
4060 }
33a2ffce 4061 return 0;
edd16368
SC		 4062 }
4063
4064sglist_finished:
4065
01a02ffc 4066 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4067 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4068 return 0;
4069}
4070
283b4a9b
SC		 4071#define IO_ACCEL_INELIGIBLE (1)
4072static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4073{
4074 int is_write = 0;
4075 u32 block;
4076 u32 block_cnt;
4077
4078 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4079 switch (cdb[0]) {
4080 case WRITE_6:
4081 case WRITE_12:
4082 is_write = 1;
4083 case READ_6:
4084 case READ_12:
4085 if (*cdb_len == 6) {
c8a6c9a6 4086 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4087 block_cnt = cdb[4];
c8a6c9a6
DB		 4088 if (block_cnt == 0)
4089 block_cnt = 256;
283b4a9b
SC		 4090 } else {
4091 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4092 block = get_unaligned_be32(&cdb[2]);
4093 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4094 }
4095 if (block_cnt > 0xffff)
4096 return IO_ACCEL_INELIGIBLE;
4097
4098 cdb[0] = is_write ? WRITE_10 : READ_10;
4099 cdb[1] = 0;
4100 cdb[2] = (u8) (block >> 24);
4101 cdb[3] = (u8) (block >> 16);
4102 cdb[4] = (u8) (block >> 8);
4103 cdb[5] = (u8) (block);
4104 cdb[6] = 0;
4105 cdb[7] = (u8) (block_cnt >> 8);
4106 cdb[8] = (u8) (block_cnt);
4107 cdb[9] = 0;
4108 *cdb_len = 10;
4109 break;
4110 }
4111 return 0;
4112}
4113
c349775e 4114static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4115 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4116 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4117{
4118 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4119 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4120 unsigned int len;
4121 unsigned int total_len = 0;
4122 struct scatterlist *sg;
4123 u64 addr64;
4124 int use_sg, i;
4125 struct SGDescriptor *curr_sg;
4126 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4127
283b4a9b 4128 /* TODO: implement chaining support */
03383736
DB		 4129 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4130 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4131 return IO_ACCEL_INELIGIBLE;
03383736 4132 }
283b4a9b 4133
e1f7de0c
MG		 4134 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4135
03383736
DB		 4136 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4137 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4138 return IO_ACCEL_INELIGIBLE;
03383736 4139 }
283b4a9b 4140
e1f7de0c
MG		 4141 c->cmd_type = CMD_IOACCEL1;
4142
4143 /* Adjust the DMA address to point to the accelerated command buffer */
4144 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4145 (c->cmdindex * sizeof(*cp));
4146 BUG_ON(c->busaddr & 0x0000007F);
4147
4148 use_sg = scsi_dma_map(cmd);
03383736
DB		 4149 if (use_sg < 0) {
4150 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4151 return use_sg;
03383736 4152 }
e1f7de0c
MG		 4153
4154 if (use_sg) {
4155 curr_sg = cp->SG;
4156 scsi_for_each_sg(cmd, sg, use_sg, i) {
4157 addr64 = (u64) sg_dma_address(sg);
4158 len = sg_dma_len(sg);
4159 total_len += len;
50a0decf
SC		 4160 curr_sg->Addr = cpu_to_le64(addr64);
4161 curr_sg->Len = cpu_to_le32(len);
4162 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4163 curr_sg++;
4164 }
50a0decf 4165 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4166
4167 switch (cmd->sc_data_direction) {
4168 case DMA_TO_DEVICE:
4169 control |= IOACCEL1_CONTROL_DATA_OUT;
4170 break;
4171 case DMA_FROM_DEVICE:
4172 control |= IOACCEL1_CONTROL_DATA_IN;
4173 break;
4174 case DMA_NONE:
4175 control |= IOACCEL1_CONTROL_NODATAXFER;
4176 break;
4177 default:
4178 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4179 cmd->sc_data_direction);
4180 BUG();
4181 break;
4182 }
4183 } else {
4184 control |= IOACCEL1_CONTROL_NODATAXFER;
4185 }
4186
c349775e 4187 c->Header.SGList = use_sg;
e1f7de0c 4188 /* Fill out the command structure to submit */
2b08b3e9
DB		 4189 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4190 cp->transfer_len = cpu_to_le32(total_len);
4191 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4192 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4193 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4194 memcpy(cp->CDB, cdb, cdb_len);
4195 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4196 /* Tag was already set at init time. */
283b4a9b 4197 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4198 return 0;
4199}
edd16368 4200
283b4a9b
SC		 4201/*
4202 * Queue a command directly to a device behind the controller using the
4203 * I/O accelerator path.
4204 */
4205static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4206 struct CommandList *c)
4207{
4208 struct scsi_cmnd *cmd = c->scsi_cmd;
4209 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4210
03383736
DB		 4211 c->phys_disk = dev;
4212
283b4a9b 4213 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4214 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4215}
4216
dd0e19f3
ST		 4217/*
4218 * Set encryption parameters for the ioaccel2 request
4219 */
4220static void set_encrypt_ioaccel2(struct ctlr_info *h,
4221 struct CommandList *c, struct io_accel2_cmd *cp)
4222{
4223 struct scsi_cmnd *cmd = c->scsi_cmd;
4224 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4225 struct raid_map_data *map = &dev->raid_map;
4226 u64 first_block;
4227
dd0e19f3 4228 /* Are we doing encryption on this device */
2b08b3e9 4229 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4230 return;
4231 /* Set the data encryption key index. */
4232 cp->dekindex = map->dekindex;
4233
4234 /* Set the encryption enable flag, encoded into direction field. */
4235 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4236
4237 /* Set encryption tweak values based on logical block address
4238 * If block size is 512, tweak value is LBA.
4239 * For other block sizes, tweak is (LBA * block size)/ 512)
4240 */
4241 switch (cmd->cmnd[0]) {
4242 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4243 case WRITE_6:
4244 case READ_6:
2b08b3e9 4245 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4246 break;
4247 case WRITE_10:
4248 case READ_10:
dd0e19f3
ST		 4249 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4250 case WRITE_12:
4251 case READ_12:
2b08b3e9 4252 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4253 break;
4254 case WRITE_16:
4255 case READ_16:
2b08b3e9 4256 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4257 break;
4258 default:
4259 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4260 "ERROR: %s: size (0x%x) not supported for encryption\n",
4261 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4262 BUG();
4263 break;
4264 }
2b08b3e9
DB		 4265
4266 if (le32_to_cpu(map->volume_blk_size) != 512)
4267 first_block = first_block *
4268 le32_to_cpu(map->volume_blk_size)/512;
4269
4270 cp->tweak_lower = cpu_to_le32(first_block);
4271 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4272}
4273
c349775e
ST		 4274static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4275 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4276 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4277{
4278 struct scsi_cmnd *cmd = c->scsi_cmd;
4279 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4280 struct ioaccel2_sg_element *curr_sg;
4281 int use_sg, i;
4282 struct scatterlist *sg;
4283 u64 addr64;
4284 u32 len;
4285 u32 total_len = 0;
4286
d9a729f3 4287 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4288
03383736
DB		 4289 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4290 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4291 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4292 }
4293
c349775e
ST		 4294 c->cmd_type = CMD_IOACCEL2;
4295 /* Adjust the DMA address to point to the accelerated command buffer */
4296 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4297 (c->cmdindex * sizeof(*cp));
4298 BUG_ON(c->busaddr & 0x0000007F);
4299
4300 memset(cp, 0, sizeof(*cp));
4301 cp->IU_type = IOACCEL2_IU_TYPE;
4302
4303 use_sg = scsi_dma_map(cmd);
03383736
DB		 4304 if (use_sg < 0) {
4305 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4306 return use_sg;
03383736 4307 }
c349775e
ST		 4308
4309 if (use_sg) {
c349775e 4310 curr_sg = cp->sg;
d9a729f3
WS		 4311 if (use_sg > h->ioaccel_maxsg) {
4312 addr64 = le64_to_cpu(
4313 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4314 curr_sg->address = cpu_to_le64(addr64);
4315 curr_sg->length = 0;
4316 curr_sg->reserved[0] = 0;
4317 curr_sg->reserved[1] = 0;
4318 curr_sg->reserved[2] = 0;
4319 curr_sg->chain_indicator = 0x80;
4320
4321 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4322 }
c349775e
ST		 4323 scsi_for_each_sg(cmd, sg, use_sg, i) {
4324 addr64 = (u64) sg_dma_address(sg);
4325 len = sg_dma_len(sg);
4326 total_len += len;
4327 curr_sg->address = cpu_to_le64(addr64);
4328 curr_sg->length = cpu_to_le32(len);
4329 curr_sg->reserved[0] = 0;
4330 curr_sg->reserved[1] = 0;
4331 curr_sg->reserved[2] = 0;
4332 curr_sg->chain_indicator = 0;
4333 curr_sg++;
4334 }
4335
4336 switch (cmd->sc_data_direction) {
4337 case DMA_TO_DEVICE:
dd0e19f3
ST		 4338 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4339 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4340 break;
4341 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4342 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4343 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4344 break;
4345 case DMA_NONE:
dd0e19f3
ST		 4346 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4347 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4348 break;
4349 default:
4350 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4351 cmd->sc_data_direction);
4352 BUG();
4353 break;
4354 }
4355 } else {
dd0e19f3
ST		 4356 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4357 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4358 }
dd0e19f3
ST		 4359
4360 /* Set encryption parameters, if necessary */
4361 set_encrypt_ioaccel2(h, c, cp);
4362
2b08b3e9 4363 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4364 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4365 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4366
c349775e
ST		 4367 cp->data_len = cpu_to_le32(total_len);
4368 cp->err_ptr = cpu_to_le64(c->busaddr +
4369 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4370 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4371
d9a729f3
WS		 4372 /* fill in sg elements */
4373 if (use_sg > h->ioaccel_maxsg) {
4374 cp->sg_count = 1;
a736e9b6 4375 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4376 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4377 atomic_dec(&phys_disk->ioaccel_cmds_out);
4378 scsi_dma_unmap(cmd);
4379 return -1;
4380 }
4381 } else
4382 cp->sg_count = (u8) use_sg;
4383
c349775e
ST		 4384 enqueue_cmd_and_start_io(h, c);
4385 return 0;
4386}
4387
4388/*
4389 * Queue a command to the correct I/O accelerator path.
4390 */
4391static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4392 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4393 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4394{
03383736
DB		 4395 /* Try to honor the device's queue depth */
4396 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4397 phys_disk->queue_depth) {
4398 atomic_dec(&phys_disk->ioaccel_cmds_out);
4399 return IO_ACCEL_INELIGIBLE;
4400 }
c349775e
ST		 4401 if (h->transMethod & CFGTBL_Trans_io_accel1)
4402 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4403 cdb, cdb_len, scsi3addr,
4404 phys_disk);
c349775e
ST		 4405 else
4406 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4407 cdb, cdb_len, scsi3addr,
4408 phys_disk);
c349775e
ST		 4409}
4410
6b80b18f
ST		 4411static void raid_map_helper(struct raid_map_data *map,
4412 int offload_to_mirror, u32 *map_index, u32 *current_group)
4413{
4414 if (offload_to_mirror == 0) {
4415 /* use physical disk in the first mirrored group. */
2b08b3e9 4416 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4417 return;
4418 }
4419 do {
4420 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4421 *current_group = *map_index /
4422 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4423 if (offload_to_mirror == *current_group)
4424 continue;
2b08b3e9 4425 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4426 /* select map index from next group */
2b08b3e9 4427 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4428 (*current_group)++;
4429 } else {
4430 /* select map index from first group */
2b08b3e9 4431 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4432 *current_group = 0;
4433 }
4434 } while (offload_to_mirror != *current_group);
4435}
4436
283b4a9b
SC		 4437/*
4438 * Attempt to perform offload RAID mapping for a logical volume I/O.
4439 */
4440static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4441 struct CommandList *c)
4442{
4443 struct scsi_cmnd *cmd = c->scsi_cmd;
4444 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4445 struct raid_map_data *map = &dev->raid_map;
4446 struct raid_map_disk_data *dd = &map->data[0];
4447 int is_write = 0;
4448 u32 map_index;
4449 u64 first_block, last_block;
4450 u32 block_cnt;
4451 u32 blocks_per_row;
4452 u64 first_row, last_row;
4453 u32 first_row_offset, last_row_offset;
4454 u32 first_column, last_column;
6b80b18f
ST		 4455 u64 r0_first_row, r0_last_row;
4456 u32 r5or6_blocks_per_row;
4457 u64 r5or6_first_row, r5or6_last_row;
4458 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4459 u32 r5or6_first_column, r5or6_last_column;
4460 u32 total_disks_per_row;
4461 u32 stripesize;
4462 u32 first_group, last_group, current_group;
283b4a9b
SC		 4463 u32 map_row;
4464 u32 disk_handle;
4465 u64 disk_block;
4466 u32 disk_block_cnt;
4467 u8 cdb[16];
4468 u8 cdb_len;
2b08b3e9 4469 u16 strip_size;
283b4a9b
SC		 4470#if BITS_PER_LONG == 32
4471 u64 tmpdiv;
4472#endif
6b80b18f 4473 int offload_to_mirror;
283b4a9b 4474
283b4a9b
SC		 4475 /* check for valid opcode, get LBA and block count */
4476 switch (cmd->cmnd[0]) {
4477 case WRITE_6:
4478 is_write = 1;
4479 case READ_6:
c8a6c9a6 4480 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4481 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4482 if (block_cnt == 0)
4483 block_cnt = 256;
283b4a9b
SC		 4484 break;
4485 case WRITE_10:
4486 is_write = 1;
4487 case READ_10:
4488 first_block =
4489 (((u64) cmd->cmnd[2]) << 24) |
4490 (((u64) cmd->cmnd[3]) << 16) |
4491 (((u64) cmd->cmnd[4]) << 8) |
4492 cmd->cmnd[5];
4493 block_cnt =
4494 (((u32) cmd->cmnd[7]) << 8) |
4495 cmd->cmnd[8];
4496 break;
4497 case WRITE_12:
4498 is_write = 1;
4499 case READ_12:
4500 first_block =
4501 (((u64) cmd->cmnd[2]) << 24) |
4502 (((u64) cmd->cmnd[3]) << 16) |
4503 (((u64) cmd->cmnd[4]) << 8) |
4504 cmd->cmnd[5];
4505 block_cnt =
4506 (((u32) cmd->cmnd[6]) << 24) |
4507 (((u32) cmd->cmnd[7]) << 16) |
4508 (((u32) cmd->cmnd[8]) << 8) |
4509 cmd->cmnd[9];
4510 break;
4511 case WRITE_16:
4512 is_write = 1;
4513 case READ_16:
4514 first_block =
4515 (((u64) cmd->cmnd[2]) << 56) |
4516 (((u64) cmd->cmnd[3]) << 48) |
4517 (((u64) cmd->cmnd[4]) << 40) |
4518 (((u64) cmd->cmnd[5]) << 32) |
4519 (((u64) cmd->cmnd[6]) << 24) |
4520 (((u64) cmd->cmnd[7]) << 16) |
4521 (((u64) cmd->cmnd[8]) << 8) |
4522 cmd->cmnd[9];
4523 block_cnt =
4524 (((u32) cmd->cmnd[10]) << 24) |
4525 (((u32) cmd->cmnd[11]) << 16) |
4526 (((u32) cmd->cmnd[12]) << 8) |
4527 cmd->cmnd[13];
4528 break;
4529 default:
4530 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4531 }
283b4a9b
SC		 4532 last_block = first_block + block_cnt - 1;
4533
4534 /* check for write to non-RAID-0 */
4535 if (is_write && dev->raid_level != 0)
4536 return IO_ACCEL_INELIGIBLE;
4537
4538 /* check for invalid block or wraparound */
2b08b3e9
DB		 4539 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4540 last_block < first_block)
283b4a9b
SC		 4541 return IO_ACCEL_INELIGIBLE;
4542
4543 /* calculate stripe information for the request */
2b08b3e9
DB		 4544 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4545 le16_to_cpu(map->strip_size);
4546 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4547#if BITS_PER_LONG == 32
4548 tmpdiv = first_block;
4549 (void) do_div(tmpdiv, blocks_per_row);
4550 first_row = tmpdiv;
4551 tmpdiv = last_block;
4552 (void) do_div(tmpdiv, blocks_per_row);
4553 last_row = tmpdiv;
4554 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4555 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4556 tmpdiv = first_row_offset;
2b08b3e9 4557 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4558 first_column = tmpdiv;
4559 tmpdiv = last_row_offset;
2b08b3e9 4560 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4561 last_column = tmpdiv;
4562#else
4563 first_row = first_block / blocks_per_row;
4564 last_row = last_block / blocks_per_row;
4565 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4566 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4567 first_column = first_row_offset / strip_size;
4568 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4569#endif
4570
4571 /* if this isn't a single row/column then give to the controller */
4572 if ((first_row != last_row) || (first_column != last_column))
4573 return IO_ACCEL_INELIGIBLE;
4574
4575 /* proceeding with driver mapping */
2b08b3e9
DB		 4576 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4577 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4578 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4579 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4580 map_index = (map_row * total_disks_per_row) + first_column;
4581
4582 switch (dev->raid_level) {
4583 case HPSA_RAID_0:
4584 break; /* nothing special to do */
4585 case HPSA_RAID_1:
4586 /* Handles load balance across RAID 1 members.
4587 * (2-drive R1 and R10 with even # of drives.)
4588 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4589 */
2b08b3e9 4590 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4591 if (dev->offload_to_mirror)
2b08b3e9 4592 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4593 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4594 break;
4595 case HPSA_RAID_ADM:
4596 /* Handles N-way mirrors (R1-ADM)
4597 * and R10 with # of drives divisible by 3.)
4598 */
2b08b3e9 4599 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4600
4601 offload_to_mirror = dev->offload_to_mirror;
4602 raid_map_helper(map, offload_to_mirror,
4603 &map_index, &current_group);
4604 /* set mirror group to use next time */
4605 offload_to_mirror =
2b08b3e9
DB		 4606 (offload_to_mirror >=
4607 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4608 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4609 dev->offload_to_mirror = offload_to_mirror;
4610 /* Avoid direct use of dev->offload_to_mirror within this
4611 * function since multiple threads might simultaneously
4612 * increment it beyond the range of dev->layout_map_count -1.
4613 */
4614 break;
4615 case HPSA_RAID_5:
4616 case HPSA_RAID_6:
2b08b3e9 4617 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4618 break;
4619
4620 /* Verify first and last block are in same RAID group */
4621 r5or6_blocks_per_row =
2b08b3e9
DB		 4622 le16_to_cpu(map->strip_size) *
4623 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4624 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4625 stripesize = r5or6_blocks_per_row *
4626 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4627#if BITS_PER_LONG == 32
4628 tmpdiv = first_block;
4629 first_group = do_div(tmpdiv, stripesize);
4630 tmpdiv = first_group;
4631 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4632 first_group = tmpdiv;
4633 tmpdiv = last_block;
4634 last_group = do_div(tmpdiv, stripesize);
4635 tmpdiv = last_group;
4636 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4637 last_group = tmpdiv;
4638#else
4639 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4640 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4641#endif
000ff7c2 4642 if (first_group != last_group)
6b80b18f
ST		 4643 return IO_ACCEL_INELIGIBLE;
4644
4645 /* Verify request is in a single row of RAID 5/6 */
4646#if BITS_PER_LONG == 32
4647 tmpdiv = first_block;
4648 (void) do_div(tmpdiv, stripesize);
4649 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4650 tmpdiv = last_block;
4651 (void) do_div(tmpdiv, stripesize);
4652 r5or6_last_row = r0_last_row = tmpdiv;
4653#else
4654 first_row = r5or6_first_row = r0_first_row =
4655 first_block / stripesize;
4656 r5or6_last_row = r0_last_row = last_block / stripesize;
4657#endif
4658 if (r5or6_first_row != r5or6_last_row)
4659 return IO_ACCEL_INELIGIBLE;
4660
4661
4662 /* Verify request is in a single column */
4663#if BITS_PER_LONG == 32
4664 tmpdiv = first_block;
4665 first_row_offset = do_div(tmpdiv, stripesize);
4666 tmpdiv = first_row_offset;
4667 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4668 r5or6_first_row_offset = first_row_offset;
4669 tmpdiv = last_block;
4670 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4671 tmpdiv = r5or6_last_row_offset;
4672 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4673 tmpdiv = r5or6_first_row_offset;
4674 (void) do_div(tmpdiv, map->strip_size);
4675 first_column = r5or6_first_column = tmpdiv;
4676 tmpdiv = r5or6_last_row_offset;
4677 (void) do_div(tmpdiv, map->strip_size);
4678 r5or6_last_column = tmpdiv;
4679#else
4680 first_row_offset = r5or6_first_row_offset =
4681 (u32)((first_block % stripesize) %
4682 r5or6_blocks_per_row);
4683
4684 r5or6_last_row_offset =
4685 (u32)((last_block % stripesize) %
4686 r5or6_blocks_per_row);
4687
4688 first_column = r5or6_first_column =
2b08b3e9 4689 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4690 r5or6_last_column =
2b08b3e9 4691 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4692#endif
4693 if (r5or6_first_column != r5or6_last_column)
4694 return IO_ACCEL_INELIGIBLE;
4695
4696 /* Request is eligible */
4697 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4698 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4699
4700 map_index = (first_group *
2b08b3e9 4701 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4702 (map_row * total_disks_per_row) + first_column;
4703 break;
4704 default:
4705 return IO_ACCEL_INELIGIBLE;
283b4a9b 4706 }
6b80b18f 4707
07543e0c
SC		 4708 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4709 return IO_ACCEL_INELIGIBLE;
4710
03383736
DB		 4711 c->phys_disk = dev->phys_disk[map_index];
4712
283b4a9b 4713 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4714 disk_block = le64_to_cpu(map->disk_starting_blk) +
4715 first_row * le16_to_cpu(map->strip_size) +
4716 (first_row_offset - first_column *
4717 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4718 disk_block_cnt = block_cnt;
4719
4720 /* handle differing logical/physical block sizes */
4721 if (map->phys_blk_shift) {
4722 disk_block <<= map->phys_blk_shift;
4723 disk_block_cnt <<= map->phys_blk_shift;
4724 }
4725 BUG_ON(disk_block_cnt > 0xffff);
4726
4727 /* build the new CDB for the physical disk I/O */
4728 if (disk_block > 0xffffffff) {
4729 cdb[0] = is_write ? WRITE_16 : READ_16;
4730 cdb[1] = 0;
4731 cdb[2] = (u8) (disk_block >> 56);
4732 cdb[3] = (u8) (disk_block >> 48);
4733 cdb[4] = (u8) (disk_block >> 40);
4734 cdb[5] = (u8) (disk_block >> 32);
4735 cdb[6] = (u8) (disk_block >> 24);
4736 cdb[7] = (u8) (disk_block >> 16);
4737 cdb[8] = (u8) (disk_block >> 8);
4738 cdb[9] = (u8) (disk_block);
4739 cdb[10] = (u8) (disk_block_cnt >> 24);
4740 cdb[11] = (u8) (disk_block_cnt >> 16);
4741 cdb[12] = (u8) (disk_block_cnt >> 8);
4742 cdb[13] = (u8) (disk_block_cnt);
4743 cdb[14] = 0;
4744 cdb[15] = 0;
4745 cdb_len = 16;
4746 } else {
4747 cdb[0] = is_write ? WRITE_10 : READ_10;
4748 cdb[1] = 0;
4749 cdb[2] = (u8) (disk_block >> 24);
4750 cdb[3] = (u8) (disk_block >> 16);
4751 cdb[4] = (u8) (disk_block >> 8);
4752 cdb[5] = (u8) (disk_block);
4753 cdb[6] = 0;
4754 cdb[7] = (u8) (disk_block_cnt >> 8);
4755 cdb[8] = (u8) (disk_block_cnt);
4756 cdb[9] = 0;
4757 cdb_len = 10;
4758 }
4759 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4760 dev->scsi3addr,
4761 dev->phys_disk[map_index]);
283b4a9b
SC		 4762}
4763
25163bd5
WS		 4764/*
4765 * Submit commands down the "normal" RAID stack path
4766 * All callers to hpsa_ciss_submit must check lockup_detected
4767 * beforehand, before (opt.) and after calling cmd_alloc
4768 */
574f05d3
SC		 4769static int hpsa_ciss_submit(struct ctlr_info *h,
4770 struct CommandList *c, struct scsi_cmnd *cmd,
4771 unsigned char scsi3addr[])
edd16368 4772{
edd16368 4773 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4774 c->cmd_type = CMD_SCSI;
4775 c->scsi_cmd = cmd;
4776 c->Header.ReplyQueue = 0; /* unused in simple mode */
4777 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4778 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4779
4780 /* Fill in the request block... */
4781
4782 c->Request.Timeout = 0;
edd16368
SC		 4783 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4784 c->Request.CDBLen = cmd->cmd_len;
4785 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4786 switch (cmd->sc_data_direction) {
4787 case DMA_TO_DEVICE:
a505b86f
SC		 4788 c->Request.type_attr_dir =
4789 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4790 break;
4791 case DMA_FROM_DEVICE:
a505b86f
SC		 4792 c->Request.type_attr_dir =
4793 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4794 break;
4795 case DMA_NONE:
a505b86f
SC		 4796 c->Request.type_attr_dir =
4797 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4798 break;
4799 case DMA_BIDIRECTIONAL:
4800 /* This can happen if a buggy application does a scsi passthru
4801 * and sets both inlen and outlen to non-zero. ( see
4802 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4803 */
4804
a505b86f
SC		 4805 c->Request.type_attr_dir =
4806 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4807 /* This is technically wrong, and hpsa controllers should
4808 * reject it with CMD_INVALID, which is the most correct
4809 * response, but non-fibre backends appear to let it
4810 * slide by, and give the same results as if this field
4811 * were set correctly. Either way is acceptable for
4812 * our purposes here.
4813 */
4814
4815 break;
4816
4817 default:
4818 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4819 cmd->sc_data_direction);
4820 BUG();
4821 break;
4822 }
4823
33a2ffce 4824 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4825 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4826 return SCSI_MLQUEUE_HOST_BUSY;
4827 }
4828 enqueue_cmd_and_start_io(h, c);
4829 /* the cmd'll come back via intr handler in complete_scsi_command() */
4830 return 0;
4831}
4832
360c73bd
SC		 4833static void hpsa_cmd_init(struct ctlr_info *h, int index,
4834 struct CommandList *c)
4835{
4836 dma_addr_t cmd_dma_handle, err_dma_handle;
4837
4838 /* Zero out all of commandlist except the last field, refcount */
4839 memset(c, 0, offsetof(struct CommandList, refcount));
4840 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4841 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4842 c->err_info = h->errinfo_pool + index;
4843 memset(c->err_info, 0, sizeof(*c->err_info));
4844 err_dma_handle = h->errinfo_pool_dhandle
4845 + index * sizeof(*c->err_info);
4846 c->cmdindex = index;
4847 c->busaddr = (u32) cmd_dma_handle;
4848 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4849 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4850 c->h = h;
a58e7e53 4851 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4852}
4853
4854static void hpsa_preinitialize_commands(struct ctlr_info *h)
4855{
4856 int i;
4857
4858 for (i = 0; i < h->nr_cmds; i++) {
4859 struct CommandList *c = h->cmd_pool + i;
4860
4861 hpsa_cmd_init(h, i, c);
4862 atomic_set(&c->refcount, 0);
4863 }
4864}
4865
4866static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4867 struct CommandList *c)
4868{
4869 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4870
73153fe5
WS		 4871 BUG_ON(c->cmdindex != index);
4872
360c73bd
SC		 4873 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4874 memset(c->err_info, 0, sizeof(*c->err_info));
4875 c->busaddr = (u32) cmd_dma_handle;
4876}
4877
592a0ad5
WS		 4878static int hpsa_ioaccel_submit(struct ctlr_info *h,
4879 struct CommandList *c, struct scsi_cmnd *cmd,
4880 unsigned char *scsi3addr)
4881{
4882 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4883 int rc = IO_ACCEL_INELIGIBLE;
4884
4885 cmd->host_scribble = (unsigned char *) c;
4886
4887 if (dev->offload_enabled) {
4888 hpsa_cmd_init(h, c->cmdindex, c);
4889 c->cmd_type = CMD_SCSI;
4890 c->scsi_cmd = cmd;
4891 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4892 if (rc < 0) /* scsi_dma_map failed. */
4893 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4894 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4895 hpsa_cmd_init(h, c->cmdindex, c);
4896 c->cmd_type = CMD_SCSI;
4897 c->scsi_cmd = cmd;
4898 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4899 if (rc < 0) /* scsi_dma_map failed. */
4900 rc = SCSI_MLQUEUE_HOST_BUSY;
4901 }
4902 return rc;
4903}
4904
080ef1cc
DB		 4905static void hpsa_command_resubmit_worker(struct work_struct *work)
4906{
4907 struct scsi_cmnd *cmd;
4908 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4909 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4910
4911 cmd = c->scsi_cmd;
4912 dev = cmd->device->hostdata;
4913 if (!dev) {
4914 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4915 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4916 }
d604f533
WS		 4917 if (c->reset_pending)
4918 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4919 if (c->abort_pending)
4920 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4921 if (c->cmd_type == CMD_IOACCEL2) {
4922 struct ctlr_info *h = c->h;
4923 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4924 int rc;
4925
4926 if (c2->error_data.serv_response ==
4927 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4928 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4929 if (rc == 0)
4930 return;
4931 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4932 /*
4933 * If we get here, it means dma mapping failed.
4934 * Try again via scsi mid layer, which will
4935 * then get SCSI_MLQUEUE_HOST_BUSY.
4936 */
4937 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4938 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4939 }
4940 /* else, fall thru and resubmit down CISS path */
4941 }
4942 }
360c73bd 4943 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4944 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4945 /*
4946 * If we get here, it means dma mapping failed. Try
4947 * again via scsi mid layer, which will then get
4948 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4949 *
4950 * hpsa_ciss_submit will have already freed c
4951 * if it encountered a dma mapping failure.
080ef1cc
DB		 4952 */
4953 cmd->result = DID_IMM_RETRY << 16;
4954 cmd->scsi_done(cmd);
4955 }
4956}
4957
574f05d3
SC		 4958/* Running in struct Scsi_Host->host_lock less mode */
4959static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4960{
4961 struct ctlr_info *h;
4962 struct hpsa_scsi_dev_t *dev;
4963 unsigned char scsi3addr[8];
4964 struct CommandList *c;
4965 int rc = 0;
4966
4967 /* Get the ptr to our adapter structure out of cmd->host. */
4968 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4969
4970 BUG_ON(cmd->request->tag < 0);
4971
574f05d3
SC		 4972 dev = cmd->device->hostdata;
4973 if (!dev) {
4974 cmd->result = DID_NO_CONNECT << 16;
4975 cmd->scsi_done(cmd);
4976 return 0;
4977 }
574f05d3 4978
73153fe5 4979 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4980
407863cb 4981 if (unlikely(lockup_detected(h))) {
25163bd5 4982 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4983 cmd->scsi_done(cmd);
4984 return 0;
4985 }
73153fe5 4986 c = cmd_tagged_alloc(h, cmd);
574f05d3 4987
407863cb
SC		 4988 /*
4989 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4990 * Retries always go down the normal I/O path.
4991 */
4992 if (likely(cmd->retries == 0 &&
4993 cmd->request->cmd_type == REQ_TYPE_FS &&
4994 h->acciopath_status)) {
592a0ad5
WS		 4995 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4996 if (rc == 0)
4997 return 0;
4998 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4999 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5000 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5001 }
5002 }
5003 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5004}
5005
8ebc9248 5006static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5007{
5008 unsigned long flags;
5009
8ebc9248
WS		 5010 spin_lock_irqsave(&h->scan_lock, flags);
5011 h->scan_finished = 1;
5012 wake_up_all(&h->scan_wait_queue);
5013 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5014}
5015
a08a8471
SC		 5016static void hpsa_scan_start(struct Scsi_Host *sh)
5017{
5018 struct ctlr_info *h = shost_to_hba(sh);
5019 unsigned long flags;
5020
8ebc9248
WS		 5021 /*
5022 * Don't let rescans be initiated on a controller known to be locked
5023 * up. If the controller locks up *during* a rescan, that thread is
5024 * probably hosed, but at least we can prevent new rescan threads from
5025 * piling up on a locked up controller.
5026 */
5027 if (unlikely(lockup_detected(h)))
5028 return hpsa_scan_complete(h);
5f389360 5029
a08a8471
SC		 5030 /* wait until any scan already in progress is finished. */
5031 while (1) {
5032 spin_lock_irqsave(&h->scan_lock, flags);
5033 if (h->scan_finished)
5034 break;
5035 spin_unlock_irqrestore(&h->scan_lock, flags);
5036 wait_event(h->scan_wait_queue, h->scan_finished);
5037 /* Note: We don't need to worry about a race between this
5038 * thread and driver unload because the midlayer will
5039 * have incremented the reference count, so unload won't
5040 * happen if we're in here.
5041 */
5042 }
5043 h->scan_finished = 0; /* mark scan as in progress */
5044 spin_unlock_irqrestore(&h->scan_lock, flags);
5045
8ebc9248
WS		 5046 if (unlikely(lockup_detected(h)))
5047 return hpsa_scan_complete(h);
5f389360 5048
8aa60681 5049 hpsa_update_scsi_devices(h);
a08a8471 5050
8ebc9248 5051 hpsa_scan_complete(h);
a08a8471
SC		 5052}
5053
7c0a0229
DB		 5054static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5055{
03383736
DB		 5056 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5057
5058 if (!logical_drive)
5059 return -ENODEV;
7c0a0229
DB		 5060
5061 if (qdepth < 1)
5062 qdepth = 1;
03383736
DB		 5063 else if (qdepth > logical_drive->queue_depth)
5064 qdepth = logical_drive->queue_depth;
5065
5066 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5067}
5068
a08a8471
SC		 5069static int hpsa_scan_finished(struct Scsi_Host *sh,
5070 unsigned long elapsed_time)
5071{
5072 struct ctlr_info *h = shost_to_hba(sh);
5073 unsigned long flags;
5074 int finished;
5075
5076 spin_lock_irqsave(&h->scan_lock, flags);
5077 finished = h->scan_finished;
5078 spin_unlock_irqrestore(&h->scan_lock, flags);
5079 return finished;
5080}
5081
2946e82b 5082static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5083{
b705690d
SC		 5084 struct Scsi_Host *sh;
5085 int error;
edd16368 5086
b705690d 5087 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5088 if (sh == NULL) {
5089 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5090 return -ENOMEM;
5091 }
b705690d
SC		 5092
5093 sh->io_port = 0;
5094 sh->n_io_port = 0;
5095 sh->this_id = -1;
5096 sh->max_channel = 3;
5097 sh->max_cmd_len = MAX_COMMAND_SIZE;
5098 sh->max_lun = HPSA_MAX_LUN;
5099 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5100 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5101 sh->cmd_per_lun = sh->can_queue;
b705690d 5102 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5103 sh->hostdata[0] = (unsigned long) h;
5104 sh->irq = h->intr[h->intr_mode];
5105 sh->unique_id = sh->irq;
73153fe5
WS		 5106 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5107 if (error) {
5108 dev_err(&h->pdev->dev,
5109 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5110 __func__, h->ctlr);
2946e82b
RE		 5111 scsi_host_put(sh);
5112 return error;
73153fe5 5113 }
2946e82b 5114 h->scsi_host = sh;
b705690d 5115 return 0;
2946e82b 5116}
b705690d 5117
2946e82b
RE		 5118static int hpsa_scsi_add_host(struct ctlr_info *h)
5119{
5120 int rv;
5121
5122 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5123 if (rv) {
5124 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5125 return rv;
5126 }
5127 scsi_scan_host(h->scsi_host);
5128 return 0;
edd16368
SC		 5129}
5130
73153fe5
WS		 5131/*
5132 * The block layer has already gone to the trouble of picking out a unique,
5133 * small-integer tag for this request. We use an offset from that value as
5134 * an index to select our command block. (The offset allows us to reserve the
5135 * low-numbered entries for our own uses.)
5136 */
5137static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5138{
5139 int idx = scmd->request->tag;
5140
5141 if (idx < 0)
5142 return idx;
5143
5144 /* Offset to leave space for internal cmds. */
5145 return idx += HPSA_NRESERVED_CMDS;
5146}
5147
b69324ff
WS		 5148/*
5149 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5150 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5151 */
5152static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5153 struct CommandList *c, unsigned char lunaddr[],
5154 int reply_queue)
5155{
5156 int rc;
5157
5158 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5159 (void) fill_cmd(c, TEST_UNIT_READY, h,
5160 NULL, 0, 0, lunaddr, TYPE_CMD);
5161 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5162 if (rc)
5163 return rc;
5164 /* no unmap needed here because no data xfer. */
5165
5166 /* Check if the unit is already ready. */
5167 if (c->err_info->CommandStatus == CMD_SUCCESS)
5168 return 0;
5169
5170 /*
5171 * The first command sent after reset will receive "unit attention" to
5172 * indicate that the LUN has been reset...this is actually what we're
5173 * looking for (but, success is good too).
5174 */
5175 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5176 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5177 (c->err_info->SenseInfo[2] == NO_SENSE ||
5178 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5179 return 0;
5180
5181 return 1;
5182}
5183
5184/*
5185 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5186 * returns zero when the unit is ready, and non-zero when giving up.
5187 */
5188static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5189 struct CommandList *c,
5190 unsigned char lunaddr[], int reply_queue)
edd16368 5191{
8919358e 5192 int rc;
edd16368
SC		 5193 int count = 0;
5194 int waittime = 1; /* seconds */
edd16368
SC		 5195
5196 /* Send test unit ready until device ready, or give up. */
b69324ff 5197 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5198
b69324ff
WS		 5199 /*
5200 * Wait for a bit. do this first, because if we send
edd16368
SC		 5201 * the TUR right away, the reset will just abort it.
5202 */
5203 msleep(1000 * waittime);
b69324ff
WS		 5204
5205 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5206 if (!rc)
5207 break;
edd16368
SC		 5208
5209 /* Increase wait time with each try, up to a point. */
5210 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5211 waittime *= 2;
edd16368 5212
b69324ff
WS		 5213 dev_warn(&h->pdev->dev,
5214 "waiting %d secs for device to become ready.\n",
5215 waittime);
5216 }
edd16368 5217
b69324ff
WS		 5218 return rc;
5219}
edd16368 5220
b69324ff
WS		 5221static int wait_for_device_to_become_ready(struct ctlr_info *h,
5222 unsigned char lunaddr[],
5223 int reply_queue)
5224{
5225 int first_queue;
5226 int last_queue;
5227 int rq;
5228 int rc = 0;
5229 struct CommandList *c;
5230
5231 c = cmd_alloc(h);
5232
5233 /*
5234 * If no specific reply queue was requested, then send the TUR
5235 * repeatedly, requesting a reply on each reply queue; otherwise execute
5236 * the loop exactly once using only the specified queue.
5237 */
5238 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5239 first_queue = 0;
5240 last_queue = h->nreply_queues - 1;
5241 } else {
5242 first_queue = reply_queue;
5243 last_queue = reply_queue;
5244 }
5245
5246 for (rq = first_queue; rq <= last_queue; rq++) {
5247 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5248 if (rc)
edd16368 5249 break;
edd16368
SC		 5250 }
5251
5252 if (rc)
5253 dev_warn(&h->pdev->dev, "giving up on device.\n");
5254 else
5255 dev_warn(&h->pdev->dev, "device is ready.\n");
5256
45fcb86e 5257 cmd_free(h, c);
edd16368
SC		 5258 return rc;
5259}
5260
5261/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5262 * complaining. Doing a host- or bus-reset can't do anything good here.
5263 */
5264static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5265{
5266 int rc;
5267 struct ctlr_info *h;
5268 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5269 u8 reset_type;
2dc127bb 5270 char msg[48];
edd16368
SC		 5271
5272 /* find the controller to which the command to be aborted was sent */
5273 h = sdev_to_hba(scsicmd->device);
5274 if (h == NULL) /* paranoia */
5275 return FAILED;
e345893b
DB		 5276
5277 if (lockup_detected(h))
5278 return FAILED;
5279
edd16368
SC		 5280 dev = scsicmd->device->hostdata;
5281 if (!dev) {
d604f533 5282 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5283 return FAILED;
5284 }
25163bd5
WS		 5285
5286 /* if controller locked up, we can guarantee command won't complete */
5287 if (lockup_detected(h)) {
2dc127bb
DC		 5288 snprintf(msg, sizeof(msg),
5289 "cmd %d RESET FAILED, lockup detected",
5290 hpsa_get_cmd_index(scsicmd));
73153fe5 5291 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5292 return FAILED;
5293 }
5294
5295 /* this reset request might be the result of a lockup; check */
5296 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5297 snprintf(msg, sizeof(msg),
5298 "cmd %d RESET FAILED, new lockup detected",
5299 hpsa_get_cmd_index(scsicmd));
73153fe5 5300 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5301 return FAILED;
5302 }
5303
d604f533
WS		 5304 /* Do not attempt on controller */
5305 if (is_hba_lunid(dev->scsi3addr))
5306 return SUCCESS;
5307
0b9b7b6e
ST		 5308 if (is_logical_dev_addr_mode(dev->scsi3addr))
5309 reset_type = HPSA_DEVICE_RESET_MSG;
5310 else
5311 reset_type = HPSA_PHYS_TARGET_RESET;
5312
5313 sprintf(msg, "resetting %s",
5314 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5315 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5316
da03ded0
DB		 5317 h->reset_in_progress = 1;
5318
edd16368 5319 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5320 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5321 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5322 sprintf(msg, "reset %s %s",
5323 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5324 rc == 0 ? "completed successfully" : "failed");
d604f533 5325 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5326 h->reset_in_progress = 0;
d604f533 5327 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5328}
5329
6cba3f19
SC		 5330static void swizzle_abort_tag(u8 *tag)
5331{
5332 u8 original_tag[8];
5333
5334 memcpy(original_tag, tag, 8);
5335 tag[0] = original_tag[3];
5336 tag[1] = original_tag[2];
5337 tag[2] = original_tag[1];
5338 tag[3] = original_tag[0];
5339 tag[4] = original_tag[7];
5340 tag[5] = original_tag[6];
5341 tag[6] = original_tag[5];
5342 tag[7] = original_tag[4];
5343}
5344
17eb87d2 5345static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5346 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5347{
2b08b3e9 5348 u64 tag;
17eb87d2
ST		 5349 if (c->cmd_type == CMD_IOACCEL1) {
5350 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5351 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5352 tag = le64_to_cpu(cm1->tag);
5353 *tagupper = cpu_to_le32(tag >> 32);
5354 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5355 return;
5356 }
5357 if (c->cmd_type == CMD_IOACCEL2) {
5358 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5359 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5360 /* upper tag not used in ioaccel2 mode */
5361 memset(tagupper, 0, sizeof(*tagupper));
5362 *taglower = cm2->Tag;
54b6e9e9 5363 return;
17eb87d2 5364 }
2b08b3e9
DB		 5365 tag = le64_to_cpu(c->Header.tag);
5366 *tagupper = cpu_to_le32(tag >> 32);
5367 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5368}
5369
75167d2c 5370static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5371 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5372{
5373 int rc = IO_OK;
5374 struct CommandList *c;
5375 struct ErrorInfo *ei;
2b08b3e9 5376 __le32 tagupper, taglower;
75167d2c 5377
45fcb86e 5378 c = cmd_alloc(h);
75167d2c 5379
a2dac136 5380 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5381 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5382 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5383 if (h->needs_abort_tags_swizzled)
6cba3f19 5384 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5385 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5386 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5387 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5388 __func__, tagupper, taglower);
75167d2c
SC		 5389 /* no unmap needed here because no data xfer. */
5390
5391 ei = c->err_info;
5392 switch (ei->CommandStatus) {
5393 case CMD_SUCCESS:
5394 break;
9437ac43
SC		 5395 case CMD_TMF_STATUS:
5396 rc = hpsa_evaluate_tmf_status(h, c);
5397 break;
75167d2c
SC		 5398 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5399 rc = -1;
5400 break;
5401 default:
5402 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5403 __func__, tagupper, taglower);
d1e8beac 5404 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5405 rc = -1;
5406 break;
5407 }
45fcb86e 5408 cmd_free(h, c);
dd0e19f3
ST		 5409 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5410 __func__, tagupper, taglower);
75167d2c
SC		 5411 return rc;
5412}
5413
8be986cc
SC		 5414static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5415 struct CommandList *command_to_abort, int reply_queue)
5416{
5417 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5418 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5419 struct io_accel2_cmd *c2a =
5420 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5421 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5422 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5423
5424 /*
5425 * We're overlaying struct hpsa_tmf_struct on top of something which
5426 * was allocated as a struct io_accel2_cmd, so we better be sure it
5427 * actually fits, and doesn't overrun the error info space.
5428 */
5429 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5430 sizeof(struct io_accel2_cmd));
5431 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5432 offsetof(struct hpsa_tmf_struct, error_len) +
5433 sizeof(ac->error_len));
5434
5435 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5436 c->scsi_cmd = SCSI_CMD_BUSY;
5437
8be986cc
SC		 5438 /* Adjust the DMA address to point to the accelerated command buffer */
5439 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5440 (c->cmdindex * sizeof(struct io_accel2_cmd));
5441 BUG_ON(c->busaddr & 0x0000007F);
5442
5443 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5444 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5445 ac->reply_queue = reply_queue;
5446 ac->tmf = IOACCEL2_TMF_ABORT;
5447 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5448 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5449 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5450 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5451 ac->error_ptr = cpu_to_le64(c->busaddr +
5452 offsetof(struct io_accel2_cmd, error_data));
5453 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5454}
5455
54b6e9e9
ST		 5456/* ioaccel2 path firmware cannot handle abort task requests.
5457 * Change abort requests to physical target reset, and send to the
5458 * address of the physical disk used for the ioaccel 2 command.
5459 * Return 0 on success (IO_OK)
5460 * -1 on failure
5461 */
5462
5463static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5464 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5465{
5466 int rc = IO_OK;
5467 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5468 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5469 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5470 unsigned char *psa = &phys_scsi3addr[0];
5471
5472 /* Get a pointer to the hpsa logical device. */
7fa3030c 5473 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5474 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5475 if (dev == NULL) {
5476 dev_warn(&h->pdev->dev,
5477 "Cannot abort: no device pointer for command.\n");
5478 return -1; /* not abortable */
5479 }
5480
2ba8bfc8
SC		 5481 if (h->raid_offload_debug > 0)
5482 dev_info(&h->pdev->dev,
0d96ef5f 5483 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5484 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5485 "Reset as abort",
2ba8bfc8
SC		 5486 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5487 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5488
54b6e9e9
ST		 5489 if (!dev->offload_enabled) {
5490 dev_warn(&h->pdev->dev,
5491 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5492 return -1; /* not abortable */
5493 }
5494
5495 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5496 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5497 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5498 return -1; /* not abortable */
5499 }
5500
5501 /* send the reset */
2ba8bfc8
SC		 5502 if (h->raid_offload_debug > 0)
5503 dev_info(&h->pdev->dev,
5504 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5505 psa[0], psa[1], psa[2], psa[3],
5506 psa[4], psa[5], psa[6], psa[7]);
d604f533 5507 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5508 if (rc != 0) {
5509 dev_warn(&h->pdev->dev,
5510 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5511 psa[0], psa[1], psa[2], psa[3],
5512 psa[4], psa[5], psa[6], psa[7]);
5513 return rc; /* failed to reset */
5514 }
5515
5516 /* wait for device to recover */
b69324ff 5517 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5518 dev_warn(&h->pdev->dev,
5519 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5520 psa[0], psa[1], psa[2], psa[3],
5521 psa[4], psa[5], psa[6], psa[7]);
5522 return -1; /* failed to recover */
5523 }
5524
5525 /* device recovered */
5526 dev_info(&h->pdev->dev,
5527 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5528 psa[0], psa[1], psa[2], psa[3],
5529 psa[4], psa[5], psa[6], psa[7]);
5530
5531 return rc; /* success */
5532}
5533
8be986cc
SC		 5534static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5535 struct CommandList *abort, int reply_queue)
5536{
5537 int rc = IO_OK;
5538 struct CommandList *c;
5539 __le32 taglower, tagupper;
5540 struct hpsa_scsi_dev_t *dev;
5541 struct io_accel2_cmd *c2;
5542
5543 dev = abort->scsi_cmd->device->hostdata;
5544 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5545 return -1;
5546
5547 c = cmd_alloc(h);
5548 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5549 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5550 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5551 hpsa_get_tag(h, abort, &taglower, &tagupper);
5552 dev_dbg(&h->pdev->dev,
5553 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5554 __func__, tagupper, taglower);
5555 /* no unmap needed here because no data xfer. */
5556
5557 dev_dbg(&h->pdev->dev,
5558 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5559 __func__, tagupper, taglower, c2->error_data.serv_response);
5560 switch (c2->error_data.serv_response) {
5561 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5562 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5563 rc = 0;
5564 break;
5565 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5566 case IOACCEL2_SERV_RESPONSE_FAILURE:
5567 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5568 rc = -1;
5569 break;
5570 default:
5571 dev_warn(&h->pdev->dev,
5572 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5573 __func__, tagupper, taglower,
5574 c2->error_data.serv_response);
5575 rc = -1;
5576 }
5577 cmd_free(h, c);
5578 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5579 tagupper, taglower);
5580 return rc;
5581}
5582
6cba3f19 5583static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5584 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5585{
8be986cc
SC		 5586 /*
5587 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5588 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5589 * but not all underlying firmware can handle abort TMF.
5590 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5591 */
8be986cc
SC		 5592 if (abort->cmd_type == CMD_IOACCEL2) {
5593 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5594 return hpsa_send_abort_ioaccel2(h, abort,
5595 reply_queue);
5596 else
5597 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5598 abort, reply_queue);
8be986cc 5599 }
9b5c48c2 5600 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5601}
54b6e9e9 5602
25163bd5
WS		 5603/* Find out which reply queue a command was meant to return on */
5604static int hpsa_extract_reply_queue(struct ctlr_info *h,
5605 struct CommandList *c)
5606{
5607 if (c->cmd_type == CMD_IOACCEL2)
5608 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5609 return c->Header.ReplyQueue;
6cba3f19
SC		 5610}
5611
9b5c48c2
SC		 5612/*
5613 * Limit concurrency of abort commands to prevent
5614 * over-subscription of commands
5615 */
5616static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5617{
5618#define ABORT_CMD_WAIT_MSECS 5000
5619 return !wait_event_timeout(h->abort_cmd_wait_queue,
5620 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5621 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5622}
5623
75167d2c
SC		 5624/* Send an abort for the specified command.
5625 * If the device and controller support it,
5626 * send a task abort request.
5627 */
5628static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5629{
5630
a58e7e53 5631 int rc;
75167d2c
SC		 5632 struct ctlr_info *h;
5633 struct hpsa_scsi_dev_t *dev;
5634 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5635 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5636 char msg[256]; /* For debug messaging. */
5637 int ml = 0;
2b08b3e9 5638 __le32 tagupper, taglower;
25163bd5
WS		 5639 int refcount, reply_queue;
5640
5641 if (sc == NULL)
5642 return FAILED;
75167d2c 5643
9b5c48c2
SC		 5644 if (sc->device == NULL)
5645 return FAILED;
5646
75167d2c
SC		 5647 /* Find the controller of the command to be aborted */
5648 h = sdev_to_hba(sc->device);
9b5c48c2 5649 if (h == NULL)
75167d2c
SC		 5650 return FAILED;
5651
25163bd5
WS		 5652 /* Find the device of the command to be aborted */
5653 dev = sc->device->hostdata;
5654 if (!dev) {
5655 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5656 msg);
e345893b 5657 return FAILED;
25163bd5
WS		 5658 }
5659
5660 /* If controller locked up, we can guarantee command won't complete */
5661 if (lockup_detected(h)) {
5662 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5663 "ABORT FAILED, lockup detected");
5664 return FAILED;
5665 }
5666
5667 /* This is a good time to check if controller lockup has occurred */
5668 if (detect_controller_lockup(h)) {
5669 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5670 "ABORT FAILED, new lockup detected");
5671 return FAILED;
5672 }
e345893b 5673
75167d2c
SC		 5674 /* Check that controller supports some kind of task abort */
5675 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5676 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5677 return FAILED;
5678
5679 memset(msg, 0, sizeof(msg));
4b761557 5680 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5681 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5682 sc->device->id, sc->device->lun,
4b761557 5683 "Aborting command", sc);
75167d2c 5684
75167d2c
SC		 5685 /* Get SCSI command to be aborted */
5686 abort = (struct CommandList *) sc->host_scribble;
5687 if (abort == NULL) {
281a7fd0
WS		 5688 /* This can happen if the command already completed. */
5689 return SUCCESS;
5690 }
5691 refcount = atomic_inc_return(&abort->refcount);
5692 if (refcount == 1) { /* Command is done already. */
5693 cmd_free(h, abort);
5694 return SUCCESS;
75167d2c 5695 }
9b5c48c2
SC		 5696
5697 /* Don't bother trying the abort if we know it won't work. */
5698 if (abort->cmd_type != CMD_IOACCEL2 &&
5699 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5700 cmd_free(h, abort);
5701 return FAILED;
5702 }
5703
a58e7e53
WS		 5704 /*
5705 * Check that we're aborting the right command.
5706 * It's possible the CommandList already completed and got re-used.
5707 */
5708 if (abort->scsi_cmd != sc) {
5709 cmd_free(h, abort);
5710 return SUCCESS;
5711 }
5712
5713 abort->abort_pending = true;
17eb87d2 5714 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5715 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5716 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5717 as = abort->scsi_cmd;
75167d2c 5718 if (as != NULL)
4b761557
RE		 5719 ml += sprintf(msg+ml,
5720 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5721 as->cmd_len, as->cmnd[0], as->cmnd[1],
5722 as->serial_number);
5723 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5724 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5725
75167d2c
SC		 5726 /*
5727 * Command is in flight, or possibly already completed
5728 * by the firmware (but not to the scsi mid layer) but we can't
5729 * distinguish which. Send the abort down.
5730 */
9b5c48c2
SC		 5731 if (wait_for_available_abort_cmd(h)) {
5732 dev_warn(&h->pdev->dev,
4b761557
RE		 5733 "%s FAILED, timeout waiting for an abort command to become available.\n",
5734 msg);
9b5c48c2
SC		 5735 cmd_free(h, abort);
5736 return FAILED;
5737 }
25163bd5 5738 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5739 atomic_inc(&h->abort_cmds_available);
5740 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5741 if (rc != 0) {
4b761557 5742 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5743 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5744 "FAILED to abort command");
281a7fd0 5745 cmd_free(h, abort);
75167d2c
SC		 5746 return FAILED;
5747 }
4b761557 5748 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5749 wait_event(h->event_sync_wait_queue,
a58e7e53 5750 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5751 cmd_free(h, abort);
a58e7e53 5752 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5753}
5754
73153fe5
WS		 5755/*
5756 * For operations with an associated SCSI command, a command block is allocated
5757 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5758 * block request tag as an index into a table of entries. cmd_tagged_free() is
5759 * the complement, although cmd_free() may be called instead.
5760 */
5761static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5762 struct scsi_cmnd *scmd)
5763{
5764 int idx = hpsa_get_cmd_index(scmd);
5765 struct CommandList *c = h->cmd_pool + idx;
5766
5767 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5768 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5769 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5770 /* The index value comes from the block layer, so if it's out of
5771 * bounds, it's probably not our bug.
5772 */
5773 BUG();
5774 }
5775
5776 atomic_inc(&c->refcount);
5777 if (unlikely(!hpsa_is_cmd_idle(c))) {
5778 /*
5779 * We expect that the SCSI layer will hand us a unique tag
5780 * value. Thus, there should never be a collision here between
5781 * two requests...because if the selected command isn't idle
5782 * then someone is going to be very disappointed.
5783 */
5784 dev_err(&h->pdev->dev,
5785 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5786 idx);
5787 if (c->scsi_cmd != NULL)
5788 scsi_print_command(c->scsi_cmd);
5789 scsi_print_command(scmd);
5790 }
5791
5792 hpsa_cmd_partial_init(h, idx, c);
5793 return c;
5794}
5795
5796static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5797{
5798 /*
5799 * Release our reference to the block. We don't need to do anything
5800 * else to free it, because it is accessed by index. (There's no point
5801 * in checking the result of the decrement, since we cannot guarantee
5802 * that there isn't a concurrent abort which is also accessing it.)
5803 */
5804 (void)atomic_dec(&c->refcount);
5805}
5806
edd16368
SC		 5807/*
5808 * For operations that cannot sleep, a command block is allocated at init,
5809 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5810 * which ones are free or in use. Lock must be held when calling this.
5811 * cmd_free() is the complement.
bf43caf3
RE		 5812 * This function never gives up and returns NULL. If it hangs,
5813 * another thread must call cmd_free() to free some tags.
edd16368 5814 */
281a7fd0 5815
edd16368
SC		 5816static struct CommandList *cmd_alloc(struct ctlr_info *h)
5817{
5818 struct CommandList *c;
360c73bd 5819 int refcount, i;
73153fe5 5820 int offset = 0;
4c413128 5821
33811026
RE		 5822 /*
5823 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5824 * multiple threads could get in here, and one thread could
5825 * be scanning through the list of bits looking for a free
5826 * one, but the free ones are always behind him, and other
5827 * threads sneak in behind him and eat them before he can
5828 * get to them, so that while there is always a free one, a
5829 * very unlucky thread might be starved anyway, never able to
5830 * beat the other threads. In reality, this happens so
5831 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5832 *
5833 * Note that we start allocating commands before the SCSI host structure
5834 * is initialized. Since the search starts at bit zero, this
5835 * all works, since we have at least one command structure available;
5836 * however, it means that the structures with the low indexes have to be
5837 * reserved for driver-initiated requests, while requests from the block
5838 * layer will use the higher indexes.
4c413128 5839 */
edd16368 5840
281a7fd0 5841 for (;;) {
73153fe5
WS		 5842 i = find_next_zero_bit(h->cmd_pool_bits,
5843 HPSA_NRESERVED_CMDS,
5844 offset);
5845 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5846 offset = 0;
5847 continue;
5848 }
5849 c = h->cmd_pool + i;
5850 refcount = atomic_inc_return(&c->refcount);
5851 if (unlikely(refcount > 1)) {
5852 cmd_free(h, c); /* already in use */
73153fe5 5853 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5854 continue;
5855 }
5856 set_bit(i & (BITS_PER_LONG - 1),
5857 h->cmd_pool_bits + (i / BITS_PER_LONG));
5858 break; /* it's ours now. */
5859 }
360c73bd 5860 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5861 return c;
5862}
5863
73153fe5
WS		 5864/*
5865 * This is the complementary operation to cmd_alloc(). Note, however, in some
5866 * corner cases it may also be used to free blocks allocated by
5867 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5868 * the clear-bit is harmless.
5869 */
edd16368
SC		 5870static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5871{
281a7fd0
WS		 5872 if (atomic_dec_and_test(&c->refcount)) {
5873 int i;
edd16368 5874
281a7fd0
WS		 5875 i = c - h->cmd_pool;
5876 clear_bit(i & (BITS_PER_LONG - 1),
5877 h->cmd_pool_bits + (i / BITS_PER_LONG));
5878 }
edd16368
SC		 5879}
5880
edd16368
SC		 5881#ifdef CONFIG_COMPAT
5882
42a91641
DB		 5883static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5884 void __user *arg)
edd16368
SC		 5885{
5886 IOCTL32_Command_struct __user *arg32 =
5887 (IOCTL32_Command_struct __user *) arg;
5888 IOCTL_Command_struct arg64;
5889 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5890 int err;
5891 u32 cp;
5892
938abd84 5893 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5894 err = 0;
5895 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5896 sizeof(arg64.LUN_info));
5897 err |= copy_from_user(&arg64.Request, &arg32->Request,
5898 sizeof(arg64.Request));
5899 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5900 sizeof(arg64.error_info));
5901 err |= get_user(arg64.buf_size, &arg32->buf_size);
5902 err |= get_user(cp, &arg32->buf);
5903 arg64.buf = compat_ptr(cp);
5904 err |= copy_to_user(p, &arg64, sizeof(arg64));
5905
5906 if (err)
5907 return -EFAULT;
5908
42a91641 5909 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5910 if (err)
5911 return err;
5912 err |= copy_in_user(&arg32->error_info, &p->error_info,
5913 sizeof(arg32->error_info));
5914 if (err)
5915 return -EFAULT;
5916 return err;
5917}
5918
5919static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5920 int cmd, void __user *arg)
edd16368
SC		 5921{
5922 BIG_IOCTL32_Command_struct __user *arg32 =
5923 (BIG_IOCTL32_Command_struct __user *) arg;
5924 BIG_IOCTL_Command_struct arg64;
5925 BIG_IOCTL_Command_struct __user *p =
5926 compat_alloc_user_space(sizeof(arg64));
5927 int err;
5928 u32 cp;
5929
938abd84 5930 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5931 err = 0;
5932 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5933 sizeof(arg64.LUN_info));
5934 err |= copy_from_user(&arg64.Request, &arg32->Request,
5935 sizeof(arg64.Request));
5936 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5937 sizeof(arg64.error_info));
5938 err |= get_user(arg64.buf_size, &arg32->buf_size);
5939 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5940 err |= get_user(cp, &arg32->buf);
5941 arg64.buf = compat_ptr(cp);
5942 err |= copy_to_user(p, &arg64, sizeof(arg64));
5943
5944 if (err)
5945 return -EFAULT;
5946
42a91641 5947 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5948 if (err)
5949 return err;
5950 err |= copy_in_user(&arg32->error_info, &p->error_info,
5951 sizeof(arg32->error_info));
5952 if (err)
5953 return -EFAULT;
5954 return err;
5955}
71fe75a7 5956
42a91641 5957static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5958{
5959 switch (cmd) {
5960 case CCISS_GETPCIINFO:
5961 case CCISS_GETINTINFO:
5962 case CCISS_SETINTINFO:
5963 case CCISS_GETNODENAME:
5964 case CCISS_SETNODENAME:
5965 case CCISS_GETHEARTBEAT:
5966 case CCISS_GETBUSTYPES:
5967 case CCISS_GETFIRMVER:
5968 case CCISS_GETDRIVVER:
5969 case CCISS_REVALIDVOLS:
5970 case CCISS_DEREGDISK:
5971 case CCISS_REGNEWDISK:
5972 case CCISS_REGNEWD:
5973 case CCISS_RESCANDISK:
5974 case CCISS_GETLUNINFO:
5975 return hpsa_ioctl(dev, cmd, arg);
5976
5977 case CCISS_PASSTHRU32:
5978 return hpsa_ioctl32_passthru(dev, cmd, arg);
5979 case CCISS_BIG_PASSTHRU32:
5980 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5981
5982 default:
5983 return -ENOIOCTLCMD;
5984 }
5985}
edd16368
SC		 5986#endif
5987
5988static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5989{
5990 struct hpsa_pci_info pciinfo;
5991
5992 if (!argp)
5993 return -EINVAL;
5994 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5995 pciinfo.bus = h->pdev->bus->number;
5996 pciinfo.dev_fn = h->pdev->devfn;
5997 pciinfo.board_id = h->board_id;
5998 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5999 return -EFAULT;
6000 return 0;
6001}
6002
6003static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6004{
6005 DriverVer_type DriverVer;
6006 unsigned char vmaj, vmin, vsubmin;
6007 int rc;
6008
6009 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6010 &vmaj, &vmin, &vsubmin);
6011 if (rc != 3) {
6012 dev_info(&h->pdev->dev, "driver version string '%s' "
6013 "unrecognized.", HPSA_DRIVER_VERSION);
6014 vmaj = 0;
6015 vmin = 0;
6016 vsubmin = 0;
6017 }
6018 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6019 if (!argp)
6020 return -EINVAL;
6021 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6022 return -EFAULT;
6023 return 0;
6024}
6025
6026static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6027{
6028 IOCTL_Command_struct iocommand;
6029 struct CommandList *c;
6030 char *buff = NULL;
50a0decf 6031 u64 temp64;
c1f63c8f 6032 int rc = 0;
edd16368
SC		 6033
6034 if (!argp)
6035 return -EINVAL;
6036 if (!capable(CAP_SYS_RAWIO))
6037 return -EPERM;
6038 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6039 return -EFAULT;
6040 if ((iocommand.buf_size < 1) &&
6041 (iocommand.Request.Type.Direction != XFER_NONE)) {
6042 return -EINVAL;
6043 }
6044 if (iocommand.buf_size > 0) {
6045 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6046 if (buff == NULL)
2dd02d74 6047 return -ENOMEM;
9233fb10 6048 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6049 /* Copy the data into the buffer we created */
6050 if (copy_from_user(buff, iocommand.buf,
6051 iocommand.buf_size)) {
c1f63c8f
SC		 6052 rc = -EFAULT;
6053 goto out_kfree;
b03a7771
SC		 6054 }
6055 } else {
6056 memset(buff, 0, iocommand.buf_size);
edd16368 6057 }
b03a7771 6058 }
45fcb86e 6059 c = cmd_alloc(h);
bf43caf3 6060
edd16368
SC		 6061 /* Fill in the command type */
6062 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6063 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6064 /* Fill in Command Header */
6065 c->Header.ReplyQueue = 0; /* unused in simple mode */
6066 if (iocommand.buf_size > 0) { /* buffer to fill */
6067 c->Header.SGList = 1;
50a0decf 6068 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6069 } else { /* no buffers to fill */
6070 c->Header.SGList = 0;
50a0decf 6071 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6072 }
6073 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6074
6075 /* Fill in Request block */
6076 memcpy(&c->Request, &iocommand.Request,
6077 sizeof(c->Request));
6078
6079 /* Fill in the scatter gather information */
6080 if (iocommand.buf_size > 0) {
50a0decf 6081 temp64 = pci_map_single(h->pdev, buff,
edd16368 6082 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6083 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6084 c->SG[0].Addr = cpu_to_le64(0);
6085 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6086 rc = -ENOMEM;
6087 goto out;
6088 }
50a0decf
SC		 6089 c->SG[0].Addr = cpu_to_le64(temp64);
6090 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6091 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6092 }
25163bd5 6093 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 6094 if (iocommand.buf_size > 0)
6095 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6096 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6097 if (rc) {
6098 rc = -EIO;
6099 goto out;
6100 }
edd16368
SC		 6101
6102 /* Copy the error information out */
6103 memcpy(&iocommand.error_info, c->err_info,
6104 sizeof(iocommand.error_info));
6105 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6106 rc = -EFAULT;
6107 goto out;
edd16368 6108 }
9233fb10 6109 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6110 iocommand.buf_size > 0) {
edd16368
SC		 6111 /* Copy the data out of the buffer we created */
6112 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6113 rc = -EFAULT;
6114 goto out;
edd16368
SC		 6115 }
6116 }
c1f63c8f 6117out:
45fcb86e 6118 cmd_free(h, c);
c1f63c8f
SC		 6119out_kfree:
6120 kfree(buff);
6121 return rc;
edd16368
SC		 6122}
6123
6124static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6125{
6126 BIG_IOCTL_Command_struct *ioc;
6127 struct CommandList *c;
6128 unsigned char **buff = NULL;
6129 int *buff_size = NULL;
50a0decf 6130 u64 temp64;
edd16368
SC		 6131 BYTE sg_used = 0;
6132 int status = 0;
01a02ffc
SC		 6133 u32 left;
6134 u32 sz;
edd16368
SC		 6135 BYTE __user *data_ptr;
6136
6137 if (!argp)
6138 return -EINVAL;
6139 if (!capable(CAP_SYS_RAWIO))
6140 return -EPERM;
6141 ioc = (BIG_IOCTL_Command_struct *)
6142 kmalloc(sizeof(*ioc), GFP_KERNEL);
6143 if (!ioc) {
6144 status = -ENOMEM;
6145 goto cleanup1;
6146 }
6147 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6148 status = -EFAULT;
6149 goto cleanup1;
6150 }
6151 if ((ioc->buf_size < 1) &&
6152 (ioc->Request.Type.Direction != XFER_NONE)) {
6153 status = -EINVAL;
6154 goto cleanup1;
6155 }
6156 /* Check kmalloc limits using all SGs */
6157 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6158 status = -EINVAL;
6159 goto cleanup1;
6160 }
d66ae08b 6161 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6162 status = -EINVAL;
6163 goto cleanup1;
6164 }
d66ae08b 6165 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6166 if (!buff) {
6167 status = -ENOMEM;
6168 goto cleanup1;
6169 }
d66ae08b 6170 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6171 if (!buff_size) {
6172 status = -ENOMEM;
6173 goto cleanup1;
6174 }
6175 left = ioc->buf_size;
6176 data_ptr = ioc->buf;
6177 while (left) {
6178 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6179 buff_size[sg_used] = sz;
6180 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6181 if (buff[sg_used] == NULL) {
6182 status = -ENOMEM;
6183 goto cleanup1;
6184 }
9233fb10 6185 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6186 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6187 status = -EFAULT;
edd16368
SC		 6188 goto cleanup1;
6189 }
6190 } else
6191 memset(buff[sg_used], 0, sz);
6192 left -= sz;
6193 data_ptr += sz;
6194 sg_used++;
6195 }
45fcb86e 6196 c = cmd_alloc(h);
bf43caf3 6197
edd16368 6198 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6199 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6200 c->Header.ReplyQueue = 0;
50a0decf
SC		 6201 c->Header.SGList = (u8) sg_used;
6202 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6203 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6204 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6205 if (ioc->buf_size > 0) {
6206 int i;
6207 for (i = 0; i < sg_used; i++) {
50a0decf 6208 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6209 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6210 if (dma_mapping_error(&h->pdev->dev,
6211 (dma_addr_t) temp64)) {
6212 c->SG[i].Addr = cpu_to_le64(0);
6213 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6214 hpsa_pci_unmap(h->pdev, c, i,
6215 PCI_DMA_BIDIRECTIONAL);
6216 status = -ENOMEM;
e2d4a1f6 6217 goto cleanup0;
bcc48ffa 6218 }
50a0decf
SC		 6219 c->SG[i].Addr = cpu_to_le64(temp64);
6220 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6221 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6222 }
50a0decf 6223 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6224 }
25163bd5 6225 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6226 if (sg_used)
6227 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6228 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6229 if (status) {
6230 status = -EIO;
6231 goto cleanup0;
6232 }
6233
edd16368
SC		 6234 /* Copy the error information out */
6235 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6236 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6237 status = -EFAULT;
e2d4a1f6 6238 goto cleanup0;
edd16368 6239 }
9233fb10 6240 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6241 int i;
6242
edd16368
SC		 6243 /* Copy the data out of the buffer we created */
6244 BYTE __user *ptr = ioc->buf;
6245 for (i = 0; i < sg_used; i++) {
6246 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6247 status = -EFAULT;
e2d4a1f6 6248 goto cleanup0;
edd16368
SC		 6249 }
6250 ptr += buff_size[i];
6251 }
6252 }
edd16368 6253 status = 0;
e2d4a1f6 6254cleanup0:
45fcb86e 6255 cmd_free(h, c);
edd16368
SC		 6256cleanup1:
6257 if (buff) {
2b08b3e9
DB		 6258 int i;
6259
edd16368
SC		 6260 for (i = 0; i < sg_used; i++)
6261 kfree(buff[i]);
6262 kfree(buff);
6263 }
6264 kfree(buff_size);
6265 kfree(ioc);
6266 return status;
6267}
6268
6269static void check_ioctl_unit_attention(struct ctlr_info *h,
6270 struct CommandList *c)
6271{
6272 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6273 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6274 (void) check_for_unit_attention(h, c);
6275}
0390f0c0 6276
edd16368
SC		 6277/*
6278 * ioctl
6279 */
42a91641 6280static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6281{
6282 struct ctlr_info *h;
6283 void __user *argp = (void __user *)arg;
0390f0c0 6284 int rc;
edd16368
SC		 6285
6286 h = sdev_to_hba(dev);
6287
6288 switch (cmd) {
6289 case CCISS_DEREGDISK:
6290 case CCISS_REGNEWDISK:
6291 case CCISS_REGNEWD:
a08a8471 6292 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6293 return 0;
6294 case CCISS_GETPCIINFO:
6295 return hpsa_getpciinfo_ioctl(h, argp);
6296 case CCISS_GETDRIVVER:
6297 return hpsa_getdrivver_ioctl(h, argp);
6298 case CCISS_PASSTHRU:
34f0c627 6299 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6300 return -EAGAIN;
6301 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6302 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6303 return rc;
edd16368 6304 case CCISS_BIG_PASSTHRU:
34f0c627 6305 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6306 return -EAGAIN;
6307 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6308 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6309 return rc;
edd16368
SC		 6310 default:
6311 return -ENOTTY;
6312 }
6313}
6314
bf43caf3 6315static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6316 u8 reset_type)
64670ac8
SC		 6317{
6318 struct CommandList *c;
6319
6320 c = cmd_alloc(h);
bf43caf3 6321
a2dac136
SC		 6322 /* fill_cmd can't fail here, no data buffer to map */
6323 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6324 RAID_CTLR_LUNID, TYPE_MSG);
6325 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6326 c->waiting = NULL;
6327 enqueue_cmd_and_start_io(h, c);
6328 /* Don't wait for completion, the reset won't complete. Don't free
6329 * the command either. This is the last command we will send before
6330 * re-initializing everything, so it doesn't matter and won't leak.
6331 */
bf43caf3 6332 return;
64670ac8
SC		 6333}
6334
a2dac136 6335static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6336 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6337 int cmd_type)
6338{
6339 int pci_dir = XFER_NONE;
9b5c48c2 6340 u64 tag; /* for commands to be aborted */
edd16368
SC		 6341
6342 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6343 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6344 c->Header.ReplyQueue = 0;
6345 if (buff != NULL && size > 0) {
6346 c->Header.SGList = 1;
50a0decf 6347 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6348 } else {
6349 c->Header.SGList = 0;
50a0decf 6350 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6351 }
edd16368
SC		 6352 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6353
edd16368
SC		 6354 if (cmd_type == TYPE_CMD) {
6355 switch (cmd) {
6356 case HPSA_INQUIRY:
6357 /* are we trying to read a vital product page */
b7bb24eb 6358 if (page_code & VPD_PAGE) {
edd16368 6359 c->Request.CDB[1] = 0x01;
b7bb24eb 6360 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6361 }
6362 c->Request.CDBLen = 6;
a505b86f
SC		 6363 c->Request.type_attr_dir =
6364 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6365 c->Request.Timeout = 0;
6366 c->Request.CDB[0] = HPSA_INQUIRY;
6367 c->Request.CDB[4] = size & 0xFF;
6368 break;
6369 case HPSA_REPORT_LOG:
6370 case HPSA_REPORT_PHYS:
6371 /* Talking to controller so It's a physical command
6372 mode = 00 target = 0. Nothing to write.
6373 */
6374 c->Request.CDBLen = 12;
a505b86f
SC		 6375 c->Request.type_attr_dir =
6376 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6377 c->Request.Timeout = 0;
6378 c->Request.CDB[0] = cmd;
6379 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6380 c->Request.CDB[7] = (size >> 16) & 0xFF;
6381 c->Request.CDB[8] = (size >> 8) & 0xFF;
6382 c->Request.CDB[9] = size & 0xFF;
6383 break;
c2adae44
ST		 6384 case BMIC_SENSE_DIAG_OPTIONS:
6385 c->Request.CDBLen = 16;
6386 c->Request.type_attr_dir =
6387 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6388 c->Request.Timeout = 0;
6389 /* Spec says this should be BMIC_WRITE */
6390 c->Request.CDB[0] = BMIC_READ;
6391 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6392 break;
6393 case BMIC_SET_DIAG_OPTIONS:
6394 c->Request.CDBLen = 16;
6395 c->Request.type_attr_dir =
6396 TYPE_ATTR_DIR(cmd_type,
6397 ATTR_SIMPLE, XFER_WRITE);
6398 c->Request.Timeout = 0;
6399 c->Request.CDB[0] = BMIC_WRITE;
6400 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6401 break;
edd16368
SC		 6402 case HPSA_CACHE_FLUSH:
6403 c->Request.CDBLen = 12;
a505b86f
SC		 6404 c->Request.type_attr_dir =
6405 TYPE_ATTR_DIR(cmd_type,
6406 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6407 c->Request.Timeout = 0;
6408 c->Request.CDB[0] = BMIC_WRITE;
6409 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6410 c->Request.CDB[7] = (size >> 8) & 0xFF;
6411 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6412 break;
6413 case TEST_UNIT_READY:
6414 c->Request.CDBLen = 6;
a505b86f
SC		 6415 c->Request.type_attr_dir =
6416 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6417 c->Request.Timeout = 0;
6418 break;
283b4a9b
SC		 6419 case HPSA_GET_RAID_MAP:
6420 c->Request.CDBLen = 12;
a505b86f
SC		 6421 c->Request.type_attr_dir =
6422 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6423 c->Request.Timeout = 0;
6424 c->Request.CDB[0] = HPSA_CISS_READ;
6425 c->Request.CDB[1] = cmd;
6426 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6427 c->Request.CDB[7] = (size >> 16) & 0xFF;
6428 c->Request.CDB[8] = (size >> 8) & 0xFF;
6429 c->Request.CDB[9] = size & 0xFF;
6430 break;
316b221a
SC		 6431 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6432 c->Request.CDBLen = 10;
a505b86f
SC		 6433 c->Request.type_attr_dir =
6434 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6435 c->Request.Timeout = 0;
6436 c->Request.CDB[0] = BMIC_READ;
6437 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6438 c->Request.CDB[7] = (size >> 16) & 0xFF;
6439 c->Request.CDB[8] = (size >> 8) & 0xFF;
6440 break;
03383736
DB		 6441 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6442 c->Request.CDBLen = 10;
6443 c->Request.type_attr_dir =
6444 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6445 c->Request.Timeout = 0;
6446 c->Request.CDB[0] = BMIC_READ;
6447 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6448 c->Request.CDB[7] = (size >> 16) & 0xFF;
6449 c->Request.CDB[8] = (size >> 8) & 0XFF;
6450 break;
66749d0d
ST		 6451 case BMIC_IDENTIFY_CONTROLLER:
6452 c->Request.CDBLen = 10;
6453 c->Request.type_attr_dir =
6454 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6455 c->Request.Timeout = 0;
6456 c->Request.CDB[0] = BMIC_READ;
6457 c->Request.CDB[1] = 0;
6458 c->Request.CDB[2] = 0;
6459 c->Request.CDB[3] = 0;
6460 c->Request.CDB[4] = 0;
6461 c->Request.CDB[5] = 0;
6462 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6463 c->Request.CDB[7] = (size >> 16) & 0xFF;
6464 c->Request.CDB[8] = (size >> 8) & 0XFF;
6465 c->Request.CDB[9] = 0;
6466 break;
6467
edd16368
SC		 6468 default:
6469 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6470 BUG();
a2dac136 6471 return -1;
edd16368
SC		 6472 }
6473 } else if (cmd_type == TYPE_MSG) {
6474 switch (cmd) {
6475
0b9b7b6e
ST		 6476 case HPSA_PHYS_TARGET_RESET:
6477 c->Request.CDBLen = 16;
6478 c->Request.type_attr_dir =
6479 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6480 c->Request.Timeout = 0; /* Don't time out */
6481 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6482 c->Request.CDB[0] = HPSA_RESET;
6483 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6484 /* Physical target reset needs no control bytes 4-7*/
6485 c->Request.CDB[4] = 0x00;
6486 c->Request.CDB[5] = 0x00;
6487 c->Request.CDB[6] = 0x00;
6488 c->Request.CDB[7] = 0x00;
6489 break;
edd16368
SC		 6490 case HPSA_DEVICE_RESET_MSG:
6491 c->Request.CDBLen = 16;
a505b86f
SC		 6492 c->Request.type_attr_dir =
6493 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6494 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6495 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6496 c->Request.CDB[0] = cmd;
21e89afd 6497 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6498 /* If bytes 4-7 are zero, it means reset the */
6499 /* LunID device */
6500 c->Request.CDB[4] = 0x00;
6501 c->Request.CDB[5] = 0x00;
6502 c->Request.CDB[6] = 0x00;
6503 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6504 break;
6505 case HPSA_ABORT_MSG:
9b5c48c2 6506 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6507 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6508 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6509 tag, c->Header.tag);
75167d2c 6510 c->Request.CDBLen = 16;
a505b86f
SC		 6511 c->Request.type_attr_dir =
6512 TYPE_ATTR_DIR(cmd_type,
6513 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6514 c->Request.Timeout = 0; /* Don't time out */
6515 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6516 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6517 c->Request.CDB[2] = 0x00; /* reserved */
6518 c->Request.CDB[3] = 0x00; /* reserved */
6519 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6520 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6521 c->Request.CDB[12] = 0x00; /* reserved */
6522 c->Request.CDB[13] = 0x00; /* reserved */
6523 c->Request.CDB[14] = 0x00; /* reserved */
6524 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6525 break;
edd16368
SC		 6526 default:
6527 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6528 cmd);
6529 BUG();
6530 }
6531 } else {
6532 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6533 BUG();
6534 }
6535
a505b86f 6536 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6537 case XFER_READ:
6538 pci_dir = PCI_DMA_FROMDEVICE;
6539 break;
6540 case XFER_WRITE:
6541 pci_dir = PCI_DMA_TODEVICE;
6542 break;
6543 case XFER_NONE:
6544 pci_dir = PCI_DMA_NONE;
6545 break;
6546 default:
6547 pci_dir = PCI_DMA_BIDIRECTIONAL;
6548 }
a2dac136
SC		 6549 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6550 return -1;
6551 return 0;
edd16368
SC		 6552}
6553
6554/*
6555 * Map (physical) PCI mem into (virtual) kernel space
6556 */
6557static void __iomem *remap_pci_mem(ulong base, ulong size)
6558{
6559 ulong page_base = ((ulong) base) & PAGE_MASK;
6560 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6561 void __iomem *page_remapped = ioremap_nocache(page_base,
6562 page_offs + size);
edd16368
SC		 6563
6564 return page_remapped ? (page_remapped + page_offs) : NULL;
6565}
6566
254f796b 6567static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6568{
254f796b 6569 return h->access.command_completed(h, q);
edd16368
SC		 6570}
6571
900c5440 6572static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6573{
6574 return h->access.intr_pending(h);
6575}
6576
6577static inline long interrupt_not_for_us(struct ctlr_info *h)
6578{
10f66018
SC		 6579 return (h->access.intr_pending(h) == 0) ||
6580 (h->interrupts_enabled == 0);
edd16368
SC		 6581}
6582
01a02ffc
SC		 6583static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6584 u32 raw_tag)
edd16368
SC		 6585{
6586 if (unlikely(tag_index >= h->nr_cmds)) {
6587 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6588 return 1;
6589 }
6590 return 0;
6591}
6592
5a3d16f5 6593static inline void finish_cmd(struct CommandList *c)
edd16368 6594{
e85c5974 6595 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6596 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6597 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6598 complete_scsi_command(c);
8be986cc 6599 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6600 complete(c->waiting);
a104c99f
SC		 6601}
6602
303932fd 6603/* process completion of an indexed ("direct lookup") command */
1d94f94d 6604static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6605 u32 raw_tag)
6606{
6607 u32 tag_index;
6608 struct CommandList *c;
6609
f2405db8 6610 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6611 if (!bad_tag(h, tag_index, raw_tag)) {
6612 c = h->cmd_pool + tag_index;
6613 finish_cmd(c);
6614 }
303932fd
DB		 6615}
6616
64670ac8
SC		 6617/* Some controllers, like p400, will give us one interrupt
6618 * after a soft reset, even if we turned interrupts off.
6619 * Only need to check for this in the hpsa_xxx_discard_completions
6620 * functions.
6621 */
6622static int ignore_bogus_interrupt(struct ctlr_info *h)
6623{
6624 if (likely(!reset_devices))
6625 return 0;
6626
6627 if (likely(h->interrupts_enabled))
6628 return 0;
6629
6630 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6631 "(known firmware bug.) Ignoring.\n");
6632
6633 return 1;
6634}
6635
254f796b
MG		 6636/*
6637 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6638 * Relies on (h-q[x] == x) being true for x such that
6639 * 0 <= x < MAX_REPLY_QUEUES.
6640 */
6641static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6642{
254f796b
MG		 6643 return container_of((queue - *queue), struct ctlr_info, q[0]);
6644}
6645
6646static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6647{
6648 struct ctlr_info *h = queue_to_hba(queue);
6649 u8 q = *(u8 *) queue;
64670ac8
SC		 6650 u32 raw_tag;
6651
6652 if (ignore_bogus_interrupt(h))
6653 return IRQ_NONE;
6654
6655 if (interrupt_not_for_us(h))
6656 return IRQ_NONE;
a0c12413 6657 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6658 while (interrupt_pending(h)) {
254f796b 6659 raw_tag = get_next_completion(h, q);
64670ac8 6660 while (raw_tag != FIFO_EMPTY)
254f796b 6661 raw_tag = next_command(h, q);
64670ac8 6662 }
64670ac8
SC		 6663 return IRQ_HANDLED;
6664}
6665
254f796b 6666static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6667{
254f796b 6668 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6669 u32 raw_tag;
254f796b 6670 u8 q = *(u8 *) queue;
64670ac8
SC		 6671
6672 if (ignore_bogus_interrupt(h))
6673 return IRQ_NONE;
6674
a0c12413 6675 h->last_intr_timestamp = get_jiffies_64();
254f796b 6676 raw_tag = get_next_completion(h, q);
64670ac8 6677 while (raw_tag != FIFO_EMPTY)
254f796b 6678 raw_tag = next_command(h, q);
64670ac8
SC		 6679 return IRQ_HANDLED;
6680}
6681
254f796b 6682static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6683{
254f796b 6684 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6685 u32 raw_tag;
254f796b 6686 u8 q = *(u8 *) queue;
edd16368
SC		 6687
6688 if (interrupt_not_for_us(h))
6689 return IRQ_NONE;
a0c12413 6690 h->last_intr_timestamp = get_jiffies_64();
10f66018 6691 while (interrupt_pending(h)) {
254f796b 6692 raw_tag = get_next_completion(h, q);
10f66018 6693 while (raw_tag != FIFO_EMPTY) {
f2405db8 6694 process_indexed_cmd(h, raw_tag);
254f796b 6695 raw_tag = next_command(h, q);
10f66018
SC		 6696 }
6697 }
10f66018
SC		 6698 return IRQ_HANDLED;
6699}
6700
254f796b 6701static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6702{
254f796b 6703 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6704 u32 raw_tag;
254f796b 6705 u8 q = *(u8 *) queue;
10f66018 6706
a0c12413 6707 h->last_intr_timestamp = get_jiffies_64();
254f796b 6708 raw_tag = get_next_completion(h, q);
303932fd 6709 while (raw_tag != FIFO_EMPTY) {
f2405db8 6710 process_indexed_cmd(h, raw_tag);
254f796b 6711 raw_tag = next_command(h, q);
edd16368 6712 }
edd16368
SC		 6713 return IRQ_HANDLED;
6714}
6715
a9a3a273
SC		 6716/* Send a message CDB to the firmware. Careful, this only works
6717 * in simple mode, not performant mode due to the tag lookup.
6718 * We only ever use this immediately after a controller reset.
6719 */
6f039790
GKH		 6720static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6721 unsigned char type)
edd16368
SC		 6722{
6723 struct Command {
6724 struct CommandListHeader CommandHeader;
6725 struct RequestBlock Request;
6726 struct ErrDescriptor ErrorDescriptor;
6727 };
6728 struct Command *cmd;
6729 static const size_t cmd_sz = sizeof(*cmd) +
6730 sizeof(cmd->ErrorDescriptor);
6731 dma_addr_t paddr64;
2b08b3e9
DB		 6732 __le32 paddr32;
6733 u32 tag;
edd16368
SC		 6734 void __iomem *vaddr;
6735 int i, err;
6736
6737 vaddr = pci_ioremap_bar(pdev, 0);
6738 if (vaddr == NULL)
6739 return -ENOMEM;
6740
6741 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6742 * CCISS commands, so they must be allocated from the lower 4GiB of
6743 * memory.
6744 */
6745 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6746 if (err) {
6747 iounmap(vaddr);
1eaec8f3 6748 return err;
edd16368
SC		 6749 }
6750
6751 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6752 if (cmd == NULL) {
6753 iounmap(vaddr);
6754 return -ENOMEM;
6755 }
6756
6757 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6758 * although there's no guarantee, we assume that the address is at
6759 * least 4-byte aligned (most likely, it's page-aligned).
6760 */
2b08b3e9 6761 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6762
6763 cmd->CommandHeader.ReplyQueue = 0;
6764 cmd->CommandHeader.SGList = 0;
50a0decf 6765 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6766 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6767 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6768
6769 cmd->Request.CDBLen = 16;
a505b86f
SC		 6770 cmd->Request.type_attr_dir =
6771 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6772 cmd->Request.Timeout = 0; /* Don't time out */
6773 cmd->Request.CDB[0] = opcode;
6774 cmd->Request.CDB[1] = type;
6775 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6776 cmd->ErrorDescriptor.Addr =
2b08b3e9 6777 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6778 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6779
2b08b3e9 6780 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6781
6782 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6783 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6784 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6785 break;
6786 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6787 }
6788
6789 iounmap(vaddr);
6790
6791 /* we leak the DMA buffer here ... no choice since the controller could
6792 * still complete the command.
6793 */
6794 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6795 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6796 opcode, type);
6797 return -ETIMEDOUT;
6798 }
6799
6800 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6801
6802 if (tag & HPSA_ERROR_BIT) {
6803 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6804 opcode, type);
6805 return -EIO;
6806 }
6807
6808 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6809 opcode, type);
6810 return 0;
6811}
6812
edd16368
SC		 6813#define hpsa_noop(p) hpsa_message(p, 3, 0)
6814
1df8552a 6815static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6816 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6817{
1df8552a
SC		 6818
6819 if (use_doorbell) {
6820 /* For everything after the P600, the PCI power state method
6821 * of resetting the controller doesn't work, so we have this
6822 * other way using the doorbell register.
6823 */
6824 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6825 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6826
00701a96 6827 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6828 * doorbell reset and before any attempt to talk to the board
6829 * at all to ensure that this actually works and doesn't fall
6830 * over in some weird corner cases.
6831 */
00701a96 6832 msleep(10000);
1df8552a
SC		 6833 } else { /* Try to do it the PCI power state way */
6834
6835 /* Quoting from the Open CISS Specification: "The Power
6836 * Management Control/Status Register (CSR) controls the power
6837 * state of the device. The normal operating state is D0,
6838 * CSR=00h. The software off state is D3, CSR=03h. To reset
6839 * the controller, place the interface device in D3 then to D0,
6840 * this causes a secondary PCI reset which will reset the
6841 * controller." */
2662cab8
DB		 6842
6843 int rc = 0;
6844
1df8552a 6845 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6846
1df8552a 6847 /* enter the D3hot power management state */
2662cab8
DB		 6848 rc = pci_set_power_state(pdev, PCI_D3hot);
6849 if (rc)
6850 return rc;
1df8552a
SC		 6851
6852 msleep(500);
6853
6854 /* enter the D0 power management state */
2662cab8
DB		 6855 rc = pci_set_power_state(pdev, PCI_D0);
6856 if (rc)
6857 return rc;
c4853efe
MM		 6858
6859 /*
6860 * The P600 requires a small delay when changing states.
6861 * Otherwise we may think the board did not reset and we bail.
6862 * This for kdump only and is particular to the P600.
6863 */
6864 msleep(500);
1df8552a
SC		 6865 }
6866 return 0;
6867}
6868
6f039790 6869static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6870{
6871 memset(driver_version, 0, len);
f79cfec6 6872 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6873}
6874
6f039790 6875static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6876{
6877 char *driver_version;
6878 int i, size = sizeof(cfgtable->driver_version);
6879
6880 driver_version = kmalloc(size, GFP_KERNEL);
6881 if (!driver_version)
6882 return -ENOMEM;
6883
6884 init_driver_version(driver_version, size);
6885 for (i = 0; i < size; i++)
6886 writeb(driver_version[i], &cfgtable->driver_version[i]);
6887 kfree(driver_version);
6888 return 0;
6889}
6890
6f039790
GKH		 6891static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6892 unsigned char *driver_ver)
580ada3c
SC		 6893{
6894 int i;
6895
6896 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6897 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6898}
6899
6f039790 6900static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6901{
6902
6903 char *driver_ver, *old_driver_ver;
6904 int rc, size = sizeof(cfgtable->driver_version);
6905
6906 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6907 if (!old_driver_ver)
6908 return -ENOMEM;
6909 driver_ver = old_driver_ver + size;
6910
6911 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6912 * should have been changed, otherwise we know the reset failed.
6913 */
6914 init_driver_version(old_driver_ver, size);
6915 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6916 rc = !memcmp(driver_ver, old_driver_ver, size);
6917 kfree(old_driver_ver);
6918 return rc;
6919}
edd16368 6920/* This does a hard reset of the controller using PCI power management
1df8552a 6921 * states or the using the doorbell register.
edd16368 6922 */
6b6c1cd7 6923static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6924{
1df8552a
SC		 6925 u64 cfg_offset;
6926 u32 cfg_base_addr;
6927 u64 cfg_base_addr_index;
6928 void __iomem *vaddr;
6929 unsigned long paddr;
580ada3c 6930 u32 misc_fw_support;
270d05de 6931 int rc;
1df8552a 6932 struct CfgTable __iomem *cfgtable;
cf0b08d0 6933 u32 use_doorbell;
270d05de 6934 u16 command_register;
edd16368 6935
1df8552a
SC		 6936 /* For controllers as old as the P600, this is very nearly
6937 * the same thing as
edd16368
SC		 6938 *
6939 * pci_save_state(pci_dev);
6940 * pci_set_power_state(pci_dev, PCI_D3hot);
6941 * pci_set_power_state(pci_dev, PCI_D0);
6942 * pci_restore_state(pci_dev);
6943 *
1df8552a
SC		 6944 * For controllers newer than the P600, the pci power state
6945 * method of resetting doesn't work so we have another way
6946 * using the doorbell register.
edd16368 6947 */
18867659 6948
60f923b9
RE		 6949 if (!ctlr_is_resettable(board_id)) {
6950 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6951 return -ENODEV;
6952 }
46380786
SC		 6953
6954 /* if controller is soft- but not hard resettable... */
6955 if (!ctlr_is_hard_resettable(board_id))
6956 return -ENOTSUPP; /* try soft reset later. */
18867659 6957
270d05de
SC		 6958 /* Save the PCI command register */
6959 pci_read_config_word(pdev, 4, &command_register);
270d05de 6960 pci_save_state(pdev);
edd16368 6961
1df8552a
SC		 6962 /* find the first memory BAR, so we can find the cfg table */
6963 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6964 if (rc)
6965 return rc;
6966 vaddr = remap_pci_mem(paddr, 0x250);
6967 if (!vaddr)
6968 return -ENOMEM;
edd16368 6969
1df8552a
SC		 6970 /* find cfgtable in order to check if reset via doorbell is supported */
6971 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6972 &cfg_base_addr_index, &cfg_offset);
6973 if (rc)
6974 goto unmap_vaddr;
6975 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6976 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6977 if (!cfgtable) {
6978 rc = -ENOMEM;
6979 goto unmap_vaddr;
6980 }
580ada3c
SC		 6981 rc = write_driver_ver_to_cfgtable(cfgtable);
6982 if (rc)
03741d95 6983 goto unmap_cfgtable;
edd16368 6984
cf0b08d0
SC		 6985 /* If reset via doorbell register is supported, use that.
6986 * There are two such methods. Favor the newest method.
6987 */
1df8552a 6988 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6989 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6990 if (use_doorbell) {
6991 use_doorbell = DOORBELL_CTLR_RESET2;
6992 } else {
6993 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6994 if (use_doorbell) {
050f7147
SC		 6995 dev_warn(&pdev->dev,
6996 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6997 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6998 goto unmap_cfgtable;
6999 }
7000 }
edd16368 7001
1df8552a
SC		 7002 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7003 if (rc)
7004 goto unmap_cfgtable;
edd16368 7005
270d05de 7006 pci_restore_state(pdev);
270d05de 7007 pci_write_config_word(pdev, 4, command_register);
edd16368 7008
1df8552a
SC		 7009 /* Some devices (notably the HP Smart Array 5i Controller)
7010 need a little pause here */
7011 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7012
fe5389c8
SC		 7013 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7014 if (rc) {
7015 dev_warn(&pdev->dev,
050f7147 7016 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7017 goto unmap_cfgtable;
7018 }
fe5389c8 7019
580ada3c
SC		 7020 rc = controller_reset_failed(vaddr);
7021 if (rc < 0)
7022 goto unmap_cfgtable;
7023 if (rc) {
64670ac8
SC		 7024 dev_warn(&pdev->dev, "Unable to successfully reset "
7025 "controller. Will try soft reset.\n");
7026 rc = -ENOTSUPP;
580ada3c 7027 } else {
64670ac8 7028 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7029 }
7030
7031unmap_cfgtable:
7032 iounmap(cfgtable);
7033
7034unmap_vaddr:
7035 iounmap(vaddr);
7036 return rc;
edd16368
SC		 7037}
7038
7039/*
7040 * We cannot read the structure directly, for portability we must use
7041 * the io functions.
7042 * This is for debug only.
7043 */
42a91641 7044static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7045{
58f8665c 7046#ifdef HPSA_DEBUG
edd16368
SC		 7047 int i;
7048 char temp_name[17];
7049
7050 dev_info(dev, "Controller Configuration information\n");
7051 dev_info(dev, "------------------------------------\n");
7052 for (i = 0; i < 4; i++)
7053 temp_name[i] = readb(&(tb->Signature[i]));
7054 temp_name[4] = '\0';
7055 dev_info(dev, " Signature = %s\n", temp_name);
7056 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7057 dev_info(dev, " Transport methods supported = 0x%x\n",
7058 readl(&(tb->TransportSupport)));
7059 dev_info(dev, " Transport methods active = 0x%x\n",
7060 readl(&(tb->TransportActive)));
7061 dev_info(dev, " Requested transport Method = 0x%x\n",
7062 readl(&(tb->HostWrite.TransportRequest)));
7063 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7064 readl(&(tb->HostWrite.CoalIntDelay)));
7065 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7066 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7067 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7068 readl(&(tb->CmdsOutMax)));
7069 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7070 for (i = 0; i < 16; i++)
7071 temp_name[i] = readb(&(tb->ServerName[i]));
7072 temp_name[16] = '\0';
7073 dev_info(dev, " Server Name = %s\n", temp_name);
7074 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7075 readl(&(tb->HeartBeat)));
edd16368 7076#endif /* HPSA_DEBUG */
58f8665c 7077}
edd16368
SC		 7078
7079static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7080{
7081 int i, offset, mem_type, bar_type;
7082
7083 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7084 return 0;
7085 offset = 0;
7086 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7087 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7088 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7089 offset += 4;
7090 else {
7091 mem_type = pci_resource_flags(pdev, i) &
7092 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7093 switch (mem_type) {
7094 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7095 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7096 offset += 4; /* 32 bit */
7097 break;
7098 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7099 offset += 8;
7100 break;
7101 default: /* reserved in PCI 2.2 */
7102 dev_warn(&pdev->dev,
7103 "base address is invalid\n");
7104 return -1;
7105 break;
7106 }
7107 }
7108 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7109 return i + 1;
7110 }
7111 return -1;
7112}
7113
cc64c817
RE		 7114static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7115{
7116 if (h->msix_vector) {
7117 if (h->pdev->msix_enabled)
7118 pci_disable_msix(h->pdev);
105a3dbc 7119 h->msix_vector = 0;
cc64c817
RE		 7120 } else if (h->msi_vector) {
7121 if (h->pdev->msi_enabled)
7122 pci_disable_msi(h->pdev);
105a3dbc 7123 h->msi_vector = 0;
cc64c817
RE		 7124 }
7125}
7126
edd16368 7127/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7128 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7129 */
6f039790 7130static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7131{
7132#ifdef CONFIG_PCI_MSI
254f796b
MG		 7133 int err, i;
7134 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7135
7136 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7137 hpsa_msix_entries[i].vector = 0;
7138 hpsa_msix_entries[i].entry = i;
7139 }
edd16368
SC		 7140
7141 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7142 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7143 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7144 goto default_int_mode;
55c06c71 7145 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7146 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7147 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7148 if (h->msix_vector > num_online_cpus())
7149 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7150 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7151 1, h->msix_vector);
7152 if (err < 0) {
7153 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7154 h->msix_vector = 0;
7155 goto single_msi_mode;
7156 } else if (err < h->msix_vector) {
55c06c71 7157 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7158 "available\n", err);
edd16368 7159 }
18fce3c4
AG		 7160 h->msix_vector = err;
7161 for (i = 0; i < h->msix_vector; i++)
7162 h->intr[i] = hpsa_msix_entries[i].vector;
7163 return;
edd16368 7164 }
18fce3c4 7165single_msi_mode:
55c06c71 7166 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7167 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7168 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7169 h->msi_vector = 1;
7170 else
55c06c71 7171 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7172 }
7173default_int_mode:
7174#endif /* CONFIG_PCI_MSI */
7175 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7176 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7177}
7178
6f039790 7179static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7180{
7181 int i;
7182 u32 subsystem_vendor_id, subsystem_device_id;
7183
7184 subsystem_vendor_id = pdev->subsystem_vendor;
7185 subsystem_device_id = pdev->subsystem_device;
7186 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7187 subsystem_vendor_id;
7188
7189 for (i = 0; i < ARRAY_SIZE(products); i++)
7190 if (*board_id == products[i].board_id)
7191 return i;
7192
6798cc0a
SC		 7193 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7194 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7195 !hpsa_allow_any) {
e5c880d1
SC		 7196 dev_warn(&pdev->dev, "unrecognized board ID: "
7197 "0x%08x, ignoring.\n", *board_id);
7198 return -ENODEV;
7199 }
7200 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7201}
7202
6f039790
GKH		 7203static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7204 unsigned long *memory_bar)
3a7774ce
SC		 7205{
7206 int i;
7207
7208 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7209 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7210 /* addressing mode bits already removed */
12d2cd47
SC		 7211 *memory_bar = pci_resource_start(pdev, i);
7212 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7213 *memory_bar);
7214 return 0;
7215 }
12d2cd47 7216 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7217 return -ENODEV;
7218}
7219
6f039790
GKH		 7220static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7221 int wait_for_ready)
2c4c8c8b 7222{
fe5389c8 7223 int i, iterations;
2c4c8c8b 7224 u32 scratchpad;
fe5389c8
SC		 7225 if (wait_for_ready)
7226 iterations = HPSA_BOARD_READY_ITERATIONS;
7227 else
7228 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7229
fe5389c8
SC		 7230 for (i = 0; i < iterations; i++) {
7231 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7232 if (wait_for_ready) {
7233 if (scratchpad == HPSA_FIRMWARE_READY)
7234 return 0;
7235 } else {
7236 if (scratchpad != HPSA_FIRMWARE_READY)
7237 return 0;
7238 }
2c4c8c8b
SC		 7239 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7240 }
fe5389c8 7241 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7242 return -ENODEV;
7243}
7244
6f039790
GKH		 7245static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7246 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7247 u64 *cfg_offset)
a51fd47f
SC		 7248{
7249 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7250 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7251 *cfg_base_addr &= (u32) 0x0000ffff;
7252 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7253 if (*cfg_base_addr_index == -1) {
7254 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7255 return -ENODEV;
7256 }
7257 return 0;
7258}
7259
195f2c65
RE		 7260static void hpsa_free_cfgtables(struct ctlr_info *h)
7261{
105a3dbc 7262 if (h->transtable) {
195f2c65 7263 iounmap(h->transtable);
105a3dbc
RE		 7264 h->transtable = NULL;
7265 }
7266 if (h->cfgtable) {
195f2c65 7267 iounmap(h->cfgtable);
105a3dbc
RE		 7268 h->cfgtable = NULL;
7269 }
195f2c65
RE		 7270}
7271
7272/* Find and map CISS config table and transfer table
7273+ * several items must be unmapped (freed) later
7274+ * */
6f039790 7275static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7276{
01a02ffc
SC		 7277 u64 cfg_offset;
7278 u32 cfg_base_addr;
7279 u64 cfg_base_addr_index;
303932fd 7280 u32 trans_offset;
a51fd47f 7281 int rc;
77c4495c 7282
a51fd47f
SC		 7283 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7284 &cfg_base_addr_index, &cfg_offset);
7285 if (rc)
7286 return rc;
77c4495c 7287 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7288 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7289 if (!h->cfgtable) {
7290 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7291 return -ENOMEM;
cd3c81c4 7292 }
580ada3c
SC		 7293 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7294 if (rc)
7295 return rc;
77c4495c 7296 /* Find performant mode table. */
a51fd47f 7297 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7298 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7299 cfg_base_addr_index)+cfg_offset+trans_offset,
7300 sizeof(*h->transtable));
195f2c65
RE		 7301 if (!h->transtable) {
7302 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7303 hpsa_free_cfgtables(h);
77c4495c 7304 return -ENOMEM;
195f2c65 7305 }
77c4495c
SC		 7306 return 0;
7307}
7308
6f039790 7309static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7310{
41ce4c35
SC		 7311#define MIN_MAX_COMMANDS 16
7312 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7313
7314 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7315
7316 /* Limit commands in memory limited kdump scenario. */
7317 if (reset_devices && h->max_commands > 32)
7318 h->max_commands = 32;
7319
41ce4c35
SC		 7320 if (h->max_commands < MIN_MAX_COMMANDS) {
7321 dev_warn(&h->pdev->dev,
7322 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7323 h->max_commands,
7324 MIN_MAX_COMMANDS);
7325 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7326 }
7327}
7328
c7ee65b3
WS		 7329/* If the controller reports that the total max sg entries is greater than 512,
7330 * then we know that chained SG blocks work. (Original smart arrays did not
7331 * support chained SG blocks and would return zero for max sg entries.)
7332 */
7333static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7334{
7335 return h->maxsgentries > 512;
7336}
7337
b93d7536
SC		 7338/* Interrogate the hardware for some limits:
7339 * max commands, max SG elements without chaining, and with chaining,
7340 * SG chain block size, etc.
7341 */
6f039790 7342static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7343{
cba3d38b 7344 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7345 h->nr_cmds = h->max_commands;
b93d7536 7346 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7347 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7348 if (hpsa_supports_chained_sg_blocks(h)) {
7349 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7350 h->max_cmd_sg_entries = 32;
1a63ea6f 7351 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7352 h->maxsgentries--; /* save one for chain pointer */
7353 } else {
c7ee65b3
WS		 7354 /*
7355 * Original smart arrays supported at most 31 s/g entries
7356 * embedded inline in the command (trying to use more
7357 * would lock up the controller)
7358 */
7359 h->max_cmd_sg_entries = 31;
1a63ea6f 7360 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7361 h->chainsize = 0;
b93d7536 7362 }
75167d2c
SC		 7363
7364 /* Find out what task management functions are supported and cache */
7365 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7366 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7367 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7368 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7369 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7370 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7371 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7372}
7373
76c46e49
SC		 7374static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7375{
0fc9fd40 7376 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7377 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7378 return false;
7379 }
7380 return true;
7381}
7382
97a5e98c 7383static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7384{
97a5e98c 7385 u32 driver_support;
f7c39101 7386
97a5e98c 7387 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7388 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7389#ifdef CONFIG_X86
97a5e98c 7390 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7391#endif
28e13446
SC		 7392 driver_support |= ENABLE_UNIT_ATTN;
7393 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7394}
7395
3d0eab67
SC		 7396/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7397 * in a prefetch beyond physical memory.
7398 */
7399static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7400{
7401 u32 dma_prefetch;
7402
7403 if (h->board_id != 0x3225103C)
7404 return;
7405 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7406 dma_prefetch |= 0x8000;
7407 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7408}
7409
c706a795 7410static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7411{
7412 int i;
7413 u32 doorbell_value;
7414 unsigned long flags;
7415 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7416 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7417 spin_lock_irqsave(&h->lock, flags);
7418 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7419 spin_unlock_irqrestore(&h->lock, flags);
7420 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7421 goto done;
76438d08 7422 /* delay and try again */
007e7aa9 7423 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7424 }
c706a795
RE		 7425 return -ENODEV;
7426done:
7427 return 0;
76438d08
SC		 7428}
7429
c706a795 7430static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7431{
7432 int i;
6eaf46fd
SC		 7433 u32 doorbell_value;
7434 unsigned long flags;
eb6b2ae9
SC		 7435
7436 /* under certain very rare conditions, this can take awhile.
7437 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7438 * as we enter this code.)
7439 */
007e7aa9 7440 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7441 if (h->remove_in_progress)
7442 goto done;
6eaf46fd
SC		 7443 spin_lock_irqsave(&h->lock, flags);
7444 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7445 spin_unlock_irqrestore(&h->lock, flags);
382be668 7446 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7447 goto done;
eb6b2ae9 7448 /* delay and try again */
007e7aa9 7449 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7450 }
c706a795
RE		 7451 return -ENODEV;
7452done:
7453 return 0;
3f4336f3
SC		 7454}
7455
c706a795 7456/* return -ENODEV or other reason on error, 0 on success */
6f039790 7457static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7458{
7459 u32 trans_support;
7460
7461 trans_support = readl(&(h->cfgtable->TransportSupport));
7462 if (!(trans_support & SIMPLE_MODE))
7463 return -ENOTSUPP;
7464
7465 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7466
3f4336f3
SC		 7467 /* Update the field, and then ring the doorbell */
7468 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7469 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7470 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7471 if (hpsa_wait_for_mode_change_ack(h))
7472 goto error;
eb6b2ae9 7473 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7474 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7475 goto error;
960a30e7 7476 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7477 return 0;
283b4a9b 7478error:
050f7147 7479 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7480 return -ENODEV;
eb6b2ae9
SC		 7481}
7482
195f2c65
RE		 7483/* free items allocated or mapped by hpsa_pci_init */
7484static void hpsa_free_pci_init(struct ctlr_info *h)
7485{
7486 hpsa_free_cfgtables(h); /* pci_init 4 */
7487 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7488 h->vaddr = NULL;
195f2c65 7489 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7490 /*
7491 * call pci_disable_device before pci_release_regions per
7492 * Documentation/PCI/pci.txt
7493 */
195f2c65 7494 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7495 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7496}
7497
7498/* several items must be freed later */
6f039790 7499static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7500{
eb6b2ae9 7501 int prod_index, err;
edd16368 7502
e5c880d1
SC		 7503 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7504 if (prod_index < 0)
60f923b9 7505 return prod_index;
e5c880d1
SC		 7506 h->product_name = products[prod_index].product_name;
7507 h->access = *(products[prod_index].access);
edd16368 7508
9b5c48c2
SC		 7509 h->needs_abort_tags_swizzled =
7510 ctlr_needs_abort_tags_swizzled(h->board_id);
7511
e5a44df8
MG		 7512 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7513 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7514
55c06c71 7515 err = pci_enable_device(h->pdev);
edd16368 7516 if (err) {
195f2c65 7517 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7518 pci_disable_device(h->pdev);
edd16368
SC		 7519 return err;
7520 }
7521
f79cfec6 7522 err = pci_request_regions(h->pdev, HPSA);
edd16368 7523 if (err) {
55c06c71 7524 dev_err(&h->pdev->dev,
195f2c65 7525 "failed to obtain PCI resources\n");
943a7021
RE		 7526 pci_disable_device(h->pdev);
7527 return err;
edd16368 7528 }
4fa604e1
RE		 7529
7530 pci_set_master(h->pdev);
7531
6b3f4c52 7532 hpsa_interrupt_mode(h);
12d2cd47 7533 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7534 if (err)
195f2c65 7535 goto clean2; /* intmode+region, pci */
edd16368 7536 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7537 if (!h->vaddr) {
195f2c65 7538 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7539 err = -ENOMEM;
195f2c65 7540 goto clean2; /* intmode+region, pci */
204892e9 7541 }
fe5389c8 7542 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7543 if (err)
195f2c65 7544 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7545 err = hpsa_find_cfgtables(h);
7546 if (err)
195f2c65 7547 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7548 hpsa_find_board_params(h);
edd16368 7549
76c46e49 7550 if (!hpsa_CISS_signature_present(h)) {
edd16368 7551 err = -ENODEV;
195f2c65 7552 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7553 }
97a5e98c 7554 hpsa_set_driver_support_bits(h);
3d0eab67 7555 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7556 err = hpsa_enter_simple_mode(h);
7557 if (err)
195f2c65 7558 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7559 return 0;
7560
195f2c65
RE		 7561clean4: /* cfgtables, vaddr, intmode+region, pci */
7562 hpsa_free_cfgtables(h);
7563clean3: /* vaddr, intmode+region, pci */
7564 iounmap(h->vaddr);
105a3dbc 7565 h->vaddr = NULL;
195f2c65
RE		 7566clean2: /* intmode+region, pci */
7567 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7568 /*
7569 * call pci_disable_device before pci_release_regions per
7570 * Documentation/PCI/pci.txt
7571 */
195f2c65 7572 pci_disable_device(h->pdev);
943a7021 7573 pci_release_regions(h->pdev);
edd16368
SC		 7574 return err;
7575}
7576
6f039790 7577static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7578{
7579 int rc;
7580
7581#define HBA_INQUIRY_BYTE_COUNT 64
7582 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7583 if (!h->hba_inquiry_data)
7584 return;
7585 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7586 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7587 if (rc != 0) {
7588 kfree(h->hba_inquiry_data);
7589 h->hba_inquiry_data = NULL;
7590 }
7591}
7592
6b6c1cd7 7593static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7594{
1df8552a 7595 int rc, i;
3b747298 7596 void __iomem *vaddr;
4c2a8c40
SC		 7597
7598 if (!reset_devices)
7599 return 0;
7600
132aa220
TH		 7601 /* kdump kernel is loading, we don't know in which state is
7602 * the pci interface. The dev->enable_cnt is equal zero
7603 * so we call enable+disable, wait a while and switch it on.
7604 */
7605 rc = pci_enable_device(pdev);
7606 if (rc) {
7607 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7608 return -ENODEV;
7609 }
7610 pci_disable_device(pdev);
7611 msleep(260); /* a randomly chosen number */
7612 rc = pci_enable_device(pdev);
7613 if (rc) {
7614 dev_warn(&pdev->dev, "failed to enable device.\n");
7615 return -ENODEV;
7616 }
4fa604e1 7617
859c75ab 7618 pci_set_master(pdev);
4fa604e1 7619
3b747298
TH		 7620 vaddr = pci_ioremap_bar(pdev, 0);
7621 if (vaddr == NULL) {
7622 rc = -ENOMEM;
7623 goto out_disable;
7624 }
7625 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7626 iounmap(vaddr);
7627
1df8552a 7628 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7629 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7630
1df8552a
SC		 7631 /* -ENOTSUPP here means we cannot reset the controller
7632 * but it's already (and still) up and running in
18867659
SC		 7633 * "performant mode". Or, it might be 640x, which can't reset
7634 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7635 */
adf1b3a3 7636 if (rc)
132aa220 7637 goto out_disable;
4c2a8c40
SC		 7638
7639 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7640 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7641 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7642 if (hpsa_noop(pdev) == 0)
7643 break;
7644 else
7645 dev_warn(&pdev->dev, "no-op failed%s\n",
7646 (i < 11 ? "; re-trying" : ""));
7647 }
132aa220
TH		 7648
7649out_disable:
7650
7651 pci_disable_device(pdev);
7652 return rc;
4c2a8c40
SC		 7653}
7654
1fb7c98a
RE		 7655static void hpsa_free_cmd_pool(struct ctlr_info *h)
7656{
7657 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7658 h->cmd_pool_bits = NULL;
7659 if (h->cmd_pool) {
1fb7c98a
RE		 7660 pci_free_consistent(h->pdev,
7661 h->nr_cmds * sizeof(struct CommandList),
7662 h->cmd_pool,
7663 h->cmd_pool_dhandle);
105a3dbc
RE		 7664 h->cmd_pool = NULL;
7665 h->cmd_pool_dhandle = 0;
7666 }
7667 if (h->errinfo_pool) {
1fb7c98a
RE		 7668 pci_free_consistent(h->pdev,
7669 h->nr_cmds * sizeof(struct ErrorInfo),
7670 h->errinfo_pool,
7671 h->errinfo_pool_dhandle);
105a3dbc
RE		 7672 h->errinfo_pool = NULL;
7673 h->errinfo_pool_dhandle = 0;
7674 }
1fb7c98a
RE		 7675}
7676
d37ffbe4 7677static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7678{
7679 h->cmd_pool_bits = kzalloc(
7680 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7681 sizeof(unsigned long), GFP_KERNEL);
7682 h->cmd_pool = pci_alloc_consistent(h->pdev,
7683 h->nr_cmds * sizeof(*h->cmd_pool),
7684 &(h->cmd_pool_dhandle));
7685 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7686 h->nr_cmds * sizeof(*h->errinfo_pool),
7687 &(h->errinfo_pool_dhandle));
7688 if ((h->cmd_pool_bits == NULL)
7689 || (h->cmd_pool == NULL)
7690 || (h->errinfo_pool == NULL)) {
7691 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7692 goto clean_up;
2e9d1b36 7693 }
360c73bd 7694 hpsa_preinitialize_commands(h);
2e9d1b36 7695 return 0;
2c143342
RE		 7696clean_up:
7697 hpsa_free_cmd_pool(h);
7698 return -ENOMEM;
2e9d1b36
SC		 7699}
7700
41b3cf08
SC		 7701static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7702{
ec429952 7703 int i, cpu;
41b3cf08
SC		 7704
7705 cpu = cpumask_first(cpu_online_mask);
7706 for (i = 0; i < h->msix_vector; i++) {
ec429952 7707 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7708 cpu = cpumask_next(cpu, cpu_online_mask);
7709 }
7710}
7711
ec501a18
RE		 7712/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7713static void hpsa_free_irqs(struct ctlr_info *h)
7714{
7715 int i;
7716
7717 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7718 /* Single reply queue, only one irq to free */
7719 i = h->intr_mode;
7720 irq_set_affinity_hint(h->intr[i], NULL);
7721 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7722 h->q[i] = 0;
ec501a18
RE		 7723 return;
7724 }
7725
7726 for (i = 0; i < h->msix_vector; i++) {
7727 irq_set_affinity_hint(h->intr[i], NULL);
7728 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7729 h->q[i] = 0;
ec501a18 7730 }
a4e17fc1
RE		 7731 for (; i < MAX_REPLY_QUEUES; i++)
7732 h->q[i] = 0;
ec501a18
RE		 7733}
7734
9ee61794
RE		 7735/* returns 0 on success; cleans up and returns -Enn on error */
7736static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7737 irqreturn_t (*msixhandler)(int, void *),
7738 irqreturn_t (*intxhandler)(int, void *))
7739{
254f796b 7740 int rc, i;
0ae01a32 7741
254f796b
MG		 7742 /*
7743 * initialize h->q[x] = x so that interrupt handlers know which
7744 * queue to process.
7745 */
7746 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7747 h->q[i] = (u8) i;
7748
eee0f03a 7749 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7750 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7751 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7752 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7753 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7754 0, h->intrname[i],
254f796b 7755 &h->q[i]);
a4e17fc1
RE		 7756 if (rc) {
7757 int j;
7758
7759 dev_err(&h->pdev->dev,
7760 "failed to get irq %d for %s\n",
7761 h->intr[i], h->devname);
7762 for (j = 0; j < i; j++) {
7763 free_irq(h->intr[j], &h->q[j]);
7764 h->q[j] = 0;
7765 }
7766 for (; j < MAX_REPLY_QUEUES; j++)
7767 h->q[j] = 0;
7768 return rc;
7769 }
7770 }
41b3cf08 7771 hpsa_irq_affinity_hints(h);
254f796b
MG		 7772 } else {
7773 /* Use single reply pool */
eee0f03a 7774 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7775 if (h->msix_vector)
7776 sprintf(h->intrname[h->intr_mode],
7777 "%s-msix", h->devname);
7778 else
7779 sprintf(h->intrname[h->intr_mode],
7780 "%s-msi", h->devname);
254f796b 7781 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7782 msixhandler, 0,
7783 h->intrname[h->intr_mode],
254f796b
MG		 7784 &h->q[h->intr_mode]);
7785 } else {
8b47004a
RE		 7786 sprintf(h->intrname[h->intr_mode],
7787 "%s-intx", h->devname);
254f796b 7788 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7789 intxhandler, IRQF_SHARED,
7790 h->intrname[h->intr_mode],
254f796b
MG		 7791 &h->q[h->intr_mode]);
7792 }
105a3dbc 7793 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7794 }
0ae01a32 7795 if (rc) {
195f2c65 7796 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7797 h->intr[h->intr_mode], h->devname);
195f2c65 7798 hpsa_free_irqs(h);
0ae01a32
SC		 7799 return -ENODEV;
7800 }
7801 return 0;
7802}
7803
6f039790 7804static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7805{
39c53f55 7806 int rc;
bf43caf3 7807 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7808
7809 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7810 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7811 if (rc) {
64670ac8 7812 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7813 return rc;
64670ac8
SC		 7814 }
7815
7816 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7817 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7818 if (rc) {
64670ac8
SC		 7819 dev_warn(&h->pdev->dev, "Board failed to become ready "
7820 "after soft reset.\n");
39c53f55 7821 return rc;
64670ac8
SC		 7822 }
7823
7824 return 0;
7825}
7826
072b0518
SC		 7827static void hpsa_free_reply_queues(struct ctlr_info *h)
7828{
7829 int i;
7830
7831 for (i = 0; i < h->nreply_queues; i++) {
7832 if (!h->reply_queue[i].head)
7833 continue;
1fb7c98a
RE		 7834 pci_free_consistent(h->pdev,
7835 h->reply_queue_size,
7836 h->reply_queue[i].head,
7837 h->reply_queue[i].busaddr);
072b0518
SC		 7838 h->reply_queue[i].head = NULL;
7839 h->reply_queue[i].busaddr = 0;
7840 }
105a3dbc 7841 h->reply_queue_size = 0;
072b0518
SC		 7842}
7843
0097f0f4
SC		 7844static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7845{
105a3dbc
RE		 7846 hpsa_free_performant_mode(h); /* init_one 7 */
7847 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7848 hpsa_free_cmd_pool(h); /* init_one 5 */
7849 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7850 scsi_host_put(h->scsi_host); /* init_one 3 */
7851 h->scsi_host = NULL; /* init_one 3 */
7852 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7853 free_percpu(h->lockup_detected); /* init_one 2 */
7854 h->lockup_detected = NULL; /* init_one 2 */
7855 if (h->resubmit_wq) {
7856 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7857 h->resubmit_wq = NULL;
7858 }
7859 if (h->rescan_ctlr_wq) {
7860 destroy_workqueue(h->rescan_ctlr_wq);
7861 h->rescan_ctlr_wq = NULL;
7862 }
105a3dbc 7863 kfree(h); /* init_one 1 */
64670ac8
SC		 7864}
7865
a0c12413 7866/* Called when controller lockup detected. */
f2405db8 7867static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7868{
281a7fd0
WS		 7869 int i, refcount;
7870 struct CommandList *c;
25163bd5 7871 int failcount = 0;
a0c12413 7872
080ef1cc 7873 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7874 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7875 c = h->cmd_pool + i;
281a7fd0
WS		 7876 refcount = atomic_inc_return(&c->refcount);
7877 if (refcount > 1) {
25163bd5 7878 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7879 finish_cmd(c);
433b5f4d 7880 atomic_dec(&h->commands_outstanding);
25163bd5 7881 failcount++;
281a7fd0
WS		 7882 }
7883 cmd_free(h, c);
a0c12413 7884 }
25163bd5
WS		 7885 dev_warn(&h->pdev->dev,
7886 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7887}
7888
094963da
SC		 7889static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7890{
c8ed0010 7891 int cpu;
094963da 7892
c8ed0010 7893 for_each_online_cpu(cpu) {
094963da
SC		 7894 u32 *lockup_detected;
7895 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7896 *lockup_detected = value;
094963da
SC		 7897 }
7898 wmb(); /* be sure the per-cpu variables are out to memory */
7899}
7900
a0c12413
SC		 7901static void controller_lockup_detected(struct ctlr_info *h)
7902{
7903 unsigned long flags;
094963da 7904 u32 lockup_detected;
a0c12413 7905
a0c12413
SC		 7906 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7907 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7908 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7909 if (!lockup_detected) {
7910 /* no heartbeat, but controller gave us a zero. */
7911 dev_warn(&h->pdev->dev,
25163bd5
WS		 7912 "lockup detected after %d but scratchpad register is zero\n",
7913 h->heartbeat_sample_interval / HZ);
094963da
SC		 7914 lockup_detected = 0xffffffff;
7915 }
7916 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7917 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7918 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7919 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7920 pci_disable_device(h->pdev);
f2405db8 7921 fail_all_outstanding_cmds(h);
a0c12413
SC		 7922}
7923
25163bd5 7924static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7925{
7926 u64 now;
7927 u32 heartbeat;
7928 unsigned long flags;
7929
a0c12413
SC		 7930 now = get_jiffies_64();
7931 /* If we've received an interrupt recently, we're ok. */
7932 if (time_after64(h->last_intr_timestamp +
e85c5974 7933 (h->heartbeat_sample_interval), now))
25163bd5 7934 return false;
a0c12413
SC		 7935
7936 /*
7937 * If we've already checked the heartbeat recently, we're ok.
7938 * This could happen if someone sends us a signal. We
7939 * otherwise don't care about signals in this thread.
7940 */
7941 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7942 (h->heartbeat_sample_interval), now))
25163bd5 7943 return false;
a0c12413
SC		 7944
7945 /* If heartbeat has not changed since we last looked, we're not ok. */
7946 spin_lock_irqsave(&h->lock, flags);
7947 heartbeat = readl(&h->cfgtable->HeartBeat);
7948 spin_unlock_irqrestore(&h->lock, flags);
7949 if (h->last_heartbeat == heartbeat) {
7950 controller_lockup_detected(h);
25163bd5 7951 return true;
a0c12413
SC		 7952 }
7953
7954 /* We're ok. */
7955 h->last_heartbeat = heartbeat;
7956 h->last_heartbeat_timestamp = now;
25163bd5 7957 return false;
a0c12413
SC		 7958}
7959
9846590e 7960static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7961{
7962 int i;
7963 char *event_type;
7964
e4aa3e6a
SC		 7965 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7966 return;
7967
76438d08 7968 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7969 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7970 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7971 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7972 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7973
7974 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7975 event_type = "state change";
7976 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7977 event_type = "configuration change";
7978 /* Stop sending new RAID offload reqs via the IO accelerator */
7979 scsi_block_requests(h->scsi_host);
7980 for (i = 0; i < h->ndevices; i++)
7981 h->dev[i]->offload_enabled = 0;
23100dd9 7982 hpsa_drain_accel_commands(h);
76438d08
SC		 7983 /* Set 'accelerator path config change' bit */
7984 dev_warn(&h->pdev->dev,
7985 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7986 h->events, event_type);
7987 writel(h->events, &(h->cfgtable->clear_event_notify));
7988 /* Set the "clear event notify field update" bit 6 */
7989 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7990 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7991 hpsa_wait_for_clear_event_notify_ack(h);
7992 scsi_unblock_requests(h->scsi_host);
7993 } else {
7994 /* Acknowledge controller notification events. */
7995 writel(h->events, &(h->cfgtable->clear_event_notify));
7996 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7997 hpsa_wait_for_clear_event_notify_ack(h);
7998#if 0
7999 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
8000 hpsa_wait_for_mode_change_ack(h);
8001#endif
8002 }
9846590e 8003 return;
76438d08
SC		 8004}
8005
8006/* Check a register on the controller to see if there are configuration
8007 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8008 * we should rescan the controller for devices.
8009 * Also check flag for driver-initiated rescan.
76438d08 8010 */
9846590e 8011static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8012{
853633e8
DB		 8013 if (h->drv_req_rescan) {
8014 h->drv_req_rescan = 0;
8015 return 1;
8016 }
8017
76438d08 8018 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8019 return 0;
76438d08
SC		 8020
8021 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8022 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8023}
76438d08 8024
9846590e
SC		 8025/*
8026 * Check if any of the offline devices have become ready
8027 */
8028static int hpsa_offline_devices_ready(struct ctlr_info *h)
8029{
8030 unsigned long flags;
8031 struct offline_device_entry *d;
8032 struct list_head *this, *tmp;
8033
8034 spin_lock_irqsave(&h->offline_device_lock, flags);
8035 list_for_each_safe(this, tmp, &h->offline_device_list) {
8036 d = list_entry(this, struct offline_device_entry,
8037 offline_list);
8038 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8039 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8040 spin_lock_irqsave(&h->offline_device_lock, flags);
8041 list_del(&d->offline_list);
8042 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8043 return 1;
d1fea47c 8044 }
9846590e
SC		 8045 spin_lock_irqsave(&h->offline_device_lock, flags);
8046 }
8047 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8048 return 0;
76438d08
SC		 8049}
8050
34592254
ST		 8051static int hpsa_luns_changed(struct ctlr_info *h)
8052{
8053 int rc = 1; /* assume there are changes */
8054 struct ReportLUNdata *logdev = NULL;
8055
8056 /* if we can't find out if lun data has changed,
8057 * assume that it has.
8058 */
8059
8060 if (!h->lastlogicals)
8061 goto out;
8062
8063 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
8064 if (!logdev) {
8065 dev_warn(&h->pdev->dev,
8066 "Out of memory, can't track lun changes.\n");
8067 goto out;
8068 }
8069 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8070 dev_warn(&h->pdev->dev,
8071 "report luns failed, can't track lun changes.\n");
8072 goto out;
8073 }
8074 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8075 dev_info(&h->pdev->dev,
8076 "Lun changes detected.\n");
8077 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8078 goto out;
8079 } else
8080 rc = 0; /* no changes detected. */
8081out:
8082 kfree(logdev);
8083 return rc;
8084}
8085
6636e7f4 8086static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 8087{
8088 unsigned long flags;
8a98db73 8089 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 8090 struct ctlr_info, rescan_ctlr_work);
8091
8092
8093 if (h->remove_in_progress)
8a98db73 8094 return;
9846590e
SC		 8095
8096 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
8097 scsi_host_get(h->scsi_host);
9846590e
SC		 8098 hpsa_ack_ctlr_events(h);
8099 hpsa_scan_start(h->scsi_host);
8100 scsi_host_put(h->scsi_host);
34592254 8101 } else if (h->discovery_polling) {
c2adae44 8102 hpsa_disable_rld_caching(h);
34592254
ST		 8103 if (hpsa_luns_changed(h)) {
8104 struct Scsi_Host *sh = NULL;
8105
8106 dev_info(&h->pdev->dev,
8107 "driver discovery polling rescan.\n");
8108 sh = scsi_host_get(h->scsi_host);
8109 if (sh != NULL) {
8110 hpsa_scan_start(sh);
8111 scsi_host_put(sh);
8112 }
8113 }
9846590e 8114 }
8a98db73 8115 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8116 if (!h->remove_in_progress)
8117 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8118 h->heartbeat_sample_interval);
8119 spin_unlock_irqrestore(&h->lock, flags);
8120}
8121
8122static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8123{
8124 unsigned long flags;
8125 struct ctlr_info *h = container_of(to_delayed_work(work),
8126 struct ctlr_info, monitor_ctlr_work);
8127
8128 detect_controller_lockup(h);
8129 if (lockup_detected(h))
a0c12413 8130 return;
6636e7f4
DB		 8131
8132 spin_lock_irqsave(&h->lock, flags);
8133 if (!h->remove_in_progress)
8134 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8135 h->heartbeat_sample_interval);
8136 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8137}
8138
6636e7f4
DB		 8139static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8140 char *name)
8141{
8142 struct workqueue_struct *wq = NULL;
6636e7f4 8143
397ea9cb 8144 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8145 if (!wq)
8146 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8147
8148 return wq;
8149}
8150
6f039790 8151static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8152{
4c2a8c40 8153 int dac, rc;
edd16368 8154 struct ctlr_info *h;
64670ac8
SC		 8155 int try_soft_reset = 0;
8156 unsigned long flags;
6b6c1cd7 8157 u32 board_id;
edd16368
SC		 8158
8159 if (number_of_controllers == 0)
8160 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8161
6b6c1cd7
TH		 8162 rc = hpsa_lookup_board_id(pdev, &board_id);
8163 if (rc < 0) {
8164 dev_warn(&pdev->dev, "Board ID not found\n");
8165 return rc;
8166 }
8167
8168 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8169 if (rc) {
8170 if (rc != -ENOTSUPP)
8171 return rc;
8172 /* If the reset fails in a particular way (it has no way to do
8173 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8174 * a soft reset once we get the controller configured up to the
8175 * point that it can accept a command.
8176 */
8177 try_soft_reset = 1;
8178 rc = 0;
8179 }
8180
8181reinit_after_soft_reset:
edd16368 8182
303932fd
DB		 8183 /* Command structures must be aligned on a 32-byte boundary because
8184 * the 5 lower bits of the address are used by the hardware. and by
8185 * the driver. See comments in hpsa.h for more info.
8186 */
303932fd 8187 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8188 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8189 if (!h) {
8190 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8191 return -ENOMEM;
105a3dbc 8192 }
edd16368 8193
55c06c71 8194 h->pdev = pdev;
105a3dbc 8195
a9a3a273 8196 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8197 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8198 spin_lock_init(&h->lock);
9846590e 8199 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8200 spin_lock_init(&h->scan_lock);
34f0c627 8201 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8202 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8203
8204 /* Allocate and clear per-cpu variable lockup_detected */
8205 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8206 if (!h->lockup_detected) {
105a3dbc 8207 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8208 rc = -ENOMEM;
2efa5929 8209 goto clean1; /* aer/h */
2a5ac326 8210 }
094963da
SC		 8211 set_lockup_detected_for_all_cpus(h, 0);
8212
55c06c71 8213 rc = hpsa_pci_init(h);
105a3dbc 8214 if (rc)
2946e82b
RE		 8215 goto clean2; /* lu, aer/h */
8216
8217 /* relies on h-> settings made by hpsa_pci_init, including
8218 * interrupt_mode h->intr */
8219 rc = hpsa_scsi_host_alloc(h);
8220 if (rc)
8221 goto clean2_5; /* pci, lu, aer/h */
edd16368 8222
2946e82b 8223 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8224 h->ctlr = number_of_controllers;
8225 number_of_controllers++;
edd16368
SC		 8226
8227 /* configure PCI DMA stuff */
ecd9aad4
SC		 8228 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8229 if (rc == 0) {
edd16368 8230 dac = 1;
ecd9aad4
SC		 8231 } else {
8232 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8233 if (rc == 0) {
8234 dac = 0;
8235 } else {
8236 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8237 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8238 }
edd16368
SC		 8239 }
8240
8241 /* make sure the board interrupts are off */
8242 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8243
105a3dbc
RE		 8244 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8245 if (rc)
2946e82b 8246 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8247 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8248 if (rc)
2946e82b 8249 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8250 rc = hpsa_alloc_sg_chain_blocks(h);
8251 if (rc)
2946e82b 8252 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8253 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8254 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8255 init_waitqueue_head(&h->event_sync_wait_queue);
8256 mutex_init(&h->reset_mutex);
a08a8471 8257 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8258
8259 pci_set_drvdata(pdev, h);
9a41338e 8260 h->ndevices = 0;
2946e82b 8261
9a41338e 8262 spin_lock_init(&h->devlock);
105a3dbc
RE		 8263 rc = hpsa_put_ctlr_into_performant_mode(h);
8264 if (rc)
2946e82b
RE		 8265 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8266
8267 /* hook into SCSI subsystem */
8268 rc = hpsa_scsi_add_host(h);
8269 if (rc)
8270 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8271
8272 /* create the resubmit workqueue */
8273 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8274 if (!h->rescan_ctlr_wq) {
8275 rc = -ENOMEM;
8276 goto clean7;
8277 }
8278
8279 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8280 if (!h->resubmit_wq) {
8281 rc = -ENOMEM;
8282 goto clean7; /* aer/h */
8283 }
64670ac8 8284
105a3dbc
RE		 8285 /*
8286 * At this point, the controller is ready to take commands.
64670ac8
SC		 8287 * Now, if reset_devices and the hard reset didn't work, try
8288 * the soft reset and see if that works.
8289 */
8290 if (try_soft_reset) {
8291
8292 /* This is kind of gross. We may or may not get a completion
8293 * from the soft reset command, and if we do, then the value
8294 * from the fifo may or may not be valid. So, we wait 10 secs
8295 * after the reset throwing away any completions we get during
8296 * that time. Unregister the interrupt handler and register
8297 * fake ones to scoop up any residual completions.
8298 */
8299 spin_lock_irqsave(&h->lock, flags);
8300 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8301 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8302 hpsa_free_irqs(h);
9ee61794 8303 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8304 hpsa_intx_discard_completions);
8305 if (rc) {
9ee61794
RE		 8306 dev_warn(&h->pdev->dev,
8307 "Failed to request_irq after soft reset.\n");
d498757c 8308 /*
b2ef480c
RE		 8309 * cannot goto clean7 or free_irqs will be called
8310 * again. Instead, do its work
8311 */
8312 hpsa_free_performant_mode(h); /* clean7 */
8313 hpsa_free_sg_chain_blocks(h); /* clean6 */
8314 hpsa_free_cmd_pool(h); /* clean5 */
8315 /*
8316 * skip hpsa_free_irqs(h) clean4 since that
8317 * was just called before request_irqs failed
d498757c
RE		 8318 */
8319 goto clean3;
64670ac8
SC		 8320 }
8321
8322 rc = hpsa_kdump_soft_reset(h);
8323 if (rc)
8324 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8325 goto clean7;
64670ac8
SC		 8326
8327 dev_info(&h->pdev->dev, "Board READY.\n");
8328 dev_info(&h->pdev->dev,
8329 "Waiting for stale completions to drain.\n");
8330 h->access.set_intr_mask(h, HPSA_INTR_ON);
8331 msleep(10000);
8332 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8333
8334 rc = controller_reset_failed(h->cfgtable);
8335 if (rc)
8336 dev_info(&h->pdev->dev,
8337 "Soft reset appears to have failed.\n");
8338
8339 /* since the controller's reset, we have to go back and re-init
8340 * everything. Easiest to just forget what we've done and do it
8341 * all over again.
8342 */
8343 hpsa_undo_allocations_after_kdump_soft_reset(h);
8344 try_soft_reset = 0;
8345 if (rc)
b2ef480c 8346 /* don't goto clean, we already unallocated */
64670ac8
SC		 8347 return -ENODEV;
8348
8349 goto reinit_after_soft_reset;
8350 }
edd16368 8351
105a3dbc
RE		 8352 /* Enable Accelerated IO path at driver layer */
8353 h->acciopath_status = 1;
34592254
ST		 8354 /* Disable discovery polling.*/
8355 h->discovery_polling = 0;
da0697bd 8356
e863d68e 8357
edd16368
SC		 8358 /* Turn the interrupts on so we can service requests */
8359 h->access.set_intr_mask(h, HPSA_INTR_ON);
8360
339b2b14 8361 hpsa_hba_inquiry(h);
8a98db73 8362
34592254
ST		 8363 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8364 if (!h->lastlogicals)
8365 dev_info(&h->pdev->dev,
8366 "Can't track change to report lun data\n");
8367
8a98db73
SC		 8368 /* Monitor the controller for firmware lockups */
8369 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8370 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8371 schedule_delayed_work(&h->monitor_ctlr_work,
8372 h->heartbeat_sample_interval);
6636e7f4
DB		 8373 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8374 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8375 h->heartbeat_sample_interval);
88bf6d62 8376 return 0;
edd16368 8377
2946e82b 8378clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8379 hpsa_free_performant_mode(h);
8380 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8381clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8382 hpsa_free_sg_chain_blocks(h);
2946e82b 8383clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8384 hpsa_free_cmd_pool(h);
2946e82b 8385clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8386 hpsa_free_irqs(h);
2946e82b
RE		 8387clean3: /* shost, pci, lu, aer/h */
8388 scsi_host_put(h->scsi_host);
8389 h->scsi_host = NULL;
8390clean2_5: /* pci, lu, aer/h */
195f2c65 8391 hpsa_free_pci_init(h);
2946e82b 8392clean2: /* lu, aer/h */
105a3dbc
RE		 8393 if (h->lockup_detected) {
8394 free_percpu(h->lockup_detected);
8395 h->lockup_detected = NULL;
8396 }
8397clean1: /* wq/aer/h */
8398 if (h->resubmit_wq) {
080ef1cc 8399 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8400 h->resubmit_wq = NULL;
8401 }
8402 if (h->rescan_ctlr_wq) {
6636e7f4 8403 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8404 h->rescan_ctlr_wq = NULL;
8405 }
edd16368 8406 kfree(h);
ecd9aad4 8407 return rc;
edd16368
SC		 8408}
8409
8410static void hpsa_flush_cache(struct ctlr_info *h)
8411{
8412 char *flush_buf;
8413 struct CommandList *c;
25163bd5 8414 int rc;
702890e3 8415
094963da 8416 if (unlikely(lockup_detected(h)))
702890e3 8417 return;
edd16368
SC		 8418 flush_buf = kzalloc(4, GFP_KERNEL);
8419 if (!flush_buf)
8420 return;
8421
45fcb86e 8422 c = cmd_alloc(h);
bf43caf3 8423
a2dac136
SC		 8424 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8425 RAID_CTLR_LUNID, TYPE_CMD)) {
8426 goto out;
8427 }
25163bd5
WS		 8428 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8429 PCI_DMA_TODEVICE, NO_TIMEOUT);
8430 if (rc)
8431 goto out;
edd16368 8432 if (c->err_info->CommandStatus != 0)
a2dac136 8433out:
edd16368
SC		 8434 dev_warn(&h->pdev->dev,
8435 "error flushing cache on controller\n");
45fcb86e 8436 cmd_free(h, c);
edd16368
SC		 8437 kfree(flush_buf);
8438}
8439
c2adae44
ST		 8440/* Make controller gather fresh report lun data each time we
8441 * send down a report luns request
8442 */
8443static void hpsa_disable_rld_caching(struct ctlr_info *h)
8444{
8445 u32 *options;
8446 struct CommandList *c;
8447 int rc;
8448
8449 /* Don't bother trying to set diag options if locked up */
8450 if (unlikely(h->lockup_detected))
8451 return;
8452
8453 options = kzalloc(sizeof(*options), GFP_KERNEL);
8454 if (!options) {
8455 dev_err(&h->pdev->dev,
8456 "Error: failed to disable rld caching, during alloc.\n");
8457 return;
8458 }
8459
8460 c = cmd_alloc(h);
8461
8462 /* first, get the current diag options settings */
8463 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8464 RAID_CTLR_LUNID, TYPE_CMD))
8465 goto errout;
8466
8467 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8468 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
8469 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8470 goto errout;
8471
8472 /* Now, set the bit for disabling the RLD caching */
8473 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8474
8475 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8476 RAID_CTLR_LUNID, TYPE_CMD))
8477 goto errout;
8478
8479 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8480 PCI_DMA_TODEVICE, NO_TIMEOUT);
8481 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8482 goto errout;
8483
8484 /* Now verify that it got set: */
8485 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8486 RAID_CTLR_LUNID, TYPE_CMD))
8487 goto errout;
8488
8489 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8490 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
8491 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8492 goto errout;
8493
8494 if (*options && HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
8495 goto out;
8496
8497errout:
8498 dev_err(&h->pdev->dev,
8499 "Error: failed to disable report lun data caching.\n");
8500out:
8501 cmd_free(h, c);
8502 kfree(options);
8503}
8504
edd16368
SC		 8505static void hpsa_shutdown(struct pci_dev *pdev)
8506{
8507 struct ctlr_info *h;
8508
8509 h = pci_get_drvdata(pdev);
8510 /* Turn board interrupts off and send the flush cache command
8511 * sendcmd will turn off interrupt, and send the flush...
8512 * To write all data in the battery backed cache to disks
8513 */
8514 hpsa_flush_cache(h);
8515 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8516 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8517 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8518}
8519
6f039790 8520static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8521{
8522 int i;
8523
105a3dbc 8524 for (i = 0; i < h->ndevices; i++) {
55e14e76 8525 kfree(h->dev[i]);
105a3dbc
RE		 8526 h->dev[i] = NULL;
8527 }
55e14e76
SC		 8528}
8529
6f039790 8530static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8531{
8532 struct ctlr_info *h;
8a98db73 8533 unsigned long flags;
edd16368
SC		 8534
8535 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8536 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8537 return;
8538 }
8539 h = pci_get_drvdata(pdev);
8a98db73
SC		 8540
8541 /* Get rid of any controller monitoring work items */
8542 spin_lock_irqsave(&h->lock, flags);
8543 h->remove_in_progress = 1;
8a98db73 8544 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8545 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8546 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8547 destroy_workqueue(h->rescan_ctlr_wq);
8548 destroy_workqueue(h->resubmit_wq);
cc64c817 8549
2d041306
DB		 8550 /*
8551 * Call before disabling interrupts.
8552 * scsi_remove_host can trigger I/O operations especially
8553 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8554 * operations which cannot complete and will hang the system.
8555 */
8556 if (h->scsi_host)
8557 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8558 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8559 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8560 hpsa_shutdown(pdev);
cc64c817 8561
105a3dbc
RE		 8562 hpsa_free_device_info(h); /* scan */
8563
2946e82b
RE		 8564 kfree(h->hba_inquiry_data); /* init_one 10 */
8565 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8566 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8567 hpsa_free_performant_mode(h); /* init_one 7 */
8568 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8569 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8570 kfree(h->lastlogicals);
105a3dbc
RE		 8571
8572 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8573
2946e82b
RE		 8574 scsi_host_put(h->scsi_host); /* init_one 3 */
8575 h->scsi_host = NULL; /* init_one 3 */
8576
195f2c65 8577 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8578 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8579
105a3dbc
RE		 8580 free_percpu(h->lockup_detected); /* init_one 2 */
8581 h->lockup_detected = NULL; /* init_one 2 */
8582 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8583 kfree(h); /* init_one 1 */
edd16368
SC		 8584}
8585
8586static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8587 __attribute__((unused)) pm_message_t state)
8588{
8589 return -ENOSYS;
8590}
8591
8592static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8593{
8594 return -ENOSYS;
8595}
8596
8597static struct pci_driver hpsa_pci_driver = {
f79cfec6 8598 .name = HPSA,
edd16368 8599 .probe = hpsa_init_one,
6f039790 8600 .remove = hpsa_remove_one,
edd16368
SC		 8601 .id_table = hpsa_pci_device_id, /* id_table */
8602 .shutdown = hpsa_shutdown,
8603 .suspend = hpsa_suspend,
8604 .resume = hpsa_resume,
8605};
8606
303932fd
DB		 8607/* Fill in bucket_map[], given nsgs (the max number of
8608 * scatter gather elements supported) and bucket[],
8609 * which is an array of 8 integers. The bucket[] array
8610 * contains 8 different DMA transfer sizes (in 16
8611 * byte increments) which the controller uses to fetch
8612 * commands. This function fills in bucket_map[], which
8613 * maps a given number of scatter gather elements to one of
8614 * the 8 DMA transfer sizes. The point of it is to allow the
8615 * controller to only do as much DMA as needed to fetch the
8616 * command, with the DMA transfer size encoded in the lower
8617 * bits of the command address.
8618 */
8619static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8620 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8621{
8622 int i, j, b, size;
8623
303932fd
DB		 8624 /* Note, bucket_map must have nsgs+1 entries. */
8625 for (i = 0; i <= nsgs; i++) {
8626 /* Compute size of a command with i SG entries */
e1f7de0c 8627 size = i + min_blocks;
303932fd
DB		 8628 b = num_buckets; /* Assume the biggest bucket */
8629 /* Find the bucket that is just big enough */
e1f7de0c 8630 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8631 if (bucket[j] >= size) {
8632 b = j;
8633 break;
8634 }
8635 }
8636 /* for a command with i SG entries, use bucket b. */
8637 bucket_map[i] = b;
8638 }
8639}
8640
105a3dbc
RE		 8641/*
8642 * return -ENODEV on err, 0 on success (or no action)
8643 * allocates numerous items that must be freed later
8644 */
c706a795 8645static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8646{
6c311b57
SC		 8647 int i;
8648 unsigned long register_value;
e1f7de0c
MG		 8649 unsigned long transMethod = CFGTBL_Trans_Performant |
8650 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8651 CFGTBL_Trans_enable_directed_msix |
8652 (trans_support & (CFGTBL_Trans_io_accel1 |
8653 CFGTBL_Trans_io_accel2));
e1f7de0c 8654 struct access_method access = SA5_performant_access;
def342bd
SC		 8655
8656 /* This is a bit complicated. There are 8 registers on
8657 * the controller which we write to to tell it 8 different
8658 * sizes of commands which there may be. It's a way of
8659 * reducing the DMA done to fetch each command. Encoded into
8660 * each command's tag are 3 bits which communicate to the controller
8661 * which of the eight sizes that command fits within. The size of
8662 * each command depends on how many scatter gather entries there are.
8663 * Each SG entry requires 16 bytes. The eight registers are programmed
8664 * with the number of 16-byte blocks a command of that size requires.
8665 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8666 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8667 * blocks. Note, this only extends to the SG entries contained
8668 * within the command block, and does not extend to chained blocks
8669 * of SG elements. bft[] contains the eight values we write to
8670 * the registers. They are not evenly distributed, but have more
8671 * sizes for small commands, and fewer sizes for larger commands.
8672 */
d66ae08b 8673 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8674#define MIN_IOACCEL2_BFT_ENTRY 5
8675#define HPSA_IOACCEL2_HEADER_SZ 4
8676 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8677 13, 14, 15, 16, 17, 18, 19,
8678 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8679 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8680 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8681 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8682 16 * MIN_IOACCEL2_BFT_ENTRY);
8683 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8684 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8685 /* 5 = 1 s/g entry or 4k
8686 * 6 = 2 s/g entry or 8k
8687 * 8 = 4 s/g entry or 16k
8688 * 10 = 6 s/g entry or 24k
8689 */
303932fd 8690
b3a52e79
SC		 8691 /* If the controller supports either ioaccel method then
8692 * we can also use the RAID stack submit path that does not
8693 * perform the superfluous readl() after each command submission.
8694 */
8695 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8696 access = SA5_performant_access_no_read;
8697
303932fd 8698 /* Controller spec: zero out this buffer. */
072b0518
SC		 8699 for (i = 0; i < h->nreply_queues; i++)
8700 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8701
d66ae08b
SC		 8702 bft[7] = SG_ENTRIES_IN_CMD + 4;
8703 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8704 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8705 for (i = 0; i < 8; i++)
8706 writel(bft[i], &h->transtable->BlockFetch[i]);
8707
8708 /* size of controller ring buffer */
8709 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8710 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8711 writel(0, &h->transtable->RepQCtrAddrLow32);
8712 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8713
8714 for (i = 0; i < h->nreply_queues; i++) {
8715 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8716 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8717 &h->transtable->RepQAddr[i].lower);
8718 }
8719
b9af4937 8720 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8721 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8722 /*
8723 * enable outbound interrupt coalescing in accelerator mode;
8724 */
8725 if (trans_support & CFGTBL_Trans_io_accel1) {
8726 access = SA5_ioaccel_mode1_access;
8727 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8728 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8729 } else {
8730 if (trans_support & CFGTBL_Trans_io_accel2) {
8731 access = SA5_ioaccel_mode2_access;
8732 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8733 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8734 }
e1f7de0c 8735 }
303932fd 8736 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8737 if (hpsa_wait_for_mode_change_ack(h)) {
8738 dev_err(&h->pdev->dev,
8739 "performant mode problem - doorbell timeout\n");
8740 return -ENODEV;
8741 }
303932fd
DB		 8742 register_value = readl(&(h->cfgtable->TransportActive));
8743 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8744 dev_err(&h->pdev->dev,
8745 "performant mode problem - transport not active\n");
c706a795 8746 return -ENODEV;
303932fd 8747 }
960a30e7 8748 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8749 h->access = access;
8750 h->transMethod = transMethod;
8751
b9af4937
SC		 8752 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8753 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8754 return 0;
e1f7de0c 8755
b9af4937
SC		 8756 if (trans_support & CFGTBL_Trans_io_accel1) {
8757 /* Set up I/O accelerator mode */
8758 for (i = 0; i < h->nreply_queues; i++) {
8759 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8760 h->reply_queue[i].current_entry =
8761 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8762 }
8763 bft[7] = h->ioaccel_maxsg + 8;
8764 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8765 h->ioaccel1_blockFetchTable);
e1f7de0c 8766
b9af4937 8767 /* initialize all reply queue entries to unused */
072b0518
SC		 8768 for (i = 0; i < h->nreply_queues; i++)
8769 memset(h->reply_queue[i].head,
8770 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8771 h->reply_queue_size);
e1f7de0c 8772
b9af4937
SC		 8773 /* set all the constant fields in the accelerator command
8774 * frames once at init time to save CPU cycles later.
8775 */
8776 for (i = 0; i < h->nr_cmds; i++) {
8777 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8778
8779 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8780 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8781 (i * sizeof(struct ErrorInfo)));
8782 cp->err_info_len = sizeof(struct ErrorInfo);
8783 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8784 cp->host_context_flags =
8785 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8786 cp->timeout_sec = 0;
8787 cp->ReplyQueue = 0;
50a0decf 8788 cp->tag =
f2405db8 8789 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8790 cp->host_addr =
8791 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8792 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8793 }
8794 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8795 u64 cfg_offset, cfg_base_addr_index;
8796 u32 bft2_offset, cfg_base_addr;
8797 int rc;
8798
8799 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8800 &cfg_base_addr_index, &cfg_offset);
8801 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8802 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8803 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8804 4, h->ioaccel2_blockFetchTable);
8805 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8806 BUILD_BUG_ON(offsetof(struct CfgTable,
8807 io_accel_request_size_offset) != 0xb8);
8808 h->ioaccel2_bft2_regs =
8809 remap_pci_mem(pci_resource_start(h->pdev,
8810 cfg_base_addr_index) +
8811 cfg_offset + bft2_offset,
8812 ARRAY_SIZE(bft2) *
8813 sizeof(*h->ioaccel2_bft2_regs));
8814 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8815 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8816 }
b9af4937 8817 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8818 if (hpsa_wait_for_mode_change_ack(h)) {
8819 dev_err(&h->pdev->dev,
8820 "performant mode problem - enabling ioaccel mode\n");
8821 return -ENODEV;
8822 }
8823 return 0;
e1f7de0c
MG		 8824}
8825
1fb7c98a
RE		 8826/* Free ioaccel1 mode command blocks and block fetch table */
8827static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8828{
105a3dbc 8829 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8830 pci_free_consistent(h->pdev,
8831 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8832 h->ioaccel_cmd_pool,
8833 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8834 h->ioaccel_cmd_pool = NULL;
8835 h->ioaccel_cmd_pool_dhandle = 0;
8836 }
1fb7c98a 8837 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8838 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8839}
8840
d37ffbe4
RE		 8841/* Allocate ioaccel1 mode command blocks and block fetch table */
8842static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8843{
283b4a9b
SC		 8844 h->ioaccel_maxsg =
8845 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8846 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8847 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8848
e1f7de0c
MG		 8849 /* Command structures must be aligned on a 128-byte boundary
8850 * because the 7 lower bits of the address are used by the
8851 * hardware.
8852 */
e1f7de0c
MG		 8853 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8854 IOACCEL1_COMMANDLIST_ALIGNMENT);
8855 h->ioaccel_cmd_pool =
8856 pci_alloc_consistent(h->pdev,
8857 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8858 &(h->ioaccel_cmd_pool_dhandle));
8859
8860 h->ioaccel1_blockFetchTable =
283b4a9b 8861 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8862 sizeof(u32)), GFP_KERNEL);
8863
8864 if ((h->ioaccel_cmd_pool == NULL) ||
8865 (h->ioaccel1_blockFetchTable == NULL))
8866 goto clean_up;
8867
8868 memset(h->ioaccel_cmd_pool, 0,
8869 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8870 return 0;
8871
8872clean_up:
1fb7c98a 8873 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8874 return -ENOMEM;
6c311b57
SC		 8875}
8876
1fb7c98a
RE		 8877/* Free ioaccel2 mode command blocks and block fetch table */
8878static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8879{
d9a729f3
WS		 8880 hpsa_free_ioaccel2_sg_chain_blocks(h);
8881
105a3dbc 8882 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8883 pci_free_consistent(h->pdev,
8884 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8885 h->ioaccel2_cmd_pool,
8886 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8887 h->ioaccel2_cmd_pool = NULL;
8888 h->ioaccel2_cmd_pool_dhandle = 0;
8889 }
1fb7c98a 8890 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8891 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8892}
8893
d37ffbe4
RE		 8894/* Allocate ioaccel2 mode command blocks and block fetch table */
8895static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8896{
d9a729f3
WS		 8897 int rc;
8898
aca9012a
SC		 8899 /* Allocate ioaccel2 mode command blocks and block fetch table */
8900
8901 h->ioaccel_maxsg =
8902 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8903 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8904 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8905
aca9012a
SC		 8906 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8907 IOACCEL2_COMMANDLIST_ALIGNMENT);
8908 h->ioaccel2_cmd_pool =
8909 pci_alloc_consistent(h->pdev,
8910 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8911 &(h->ioaccel2_cmd_pool_dhandle));
8912
8913 h->ioaccel2_blockFetchTable =
8914 kmalloc(((h->ioaccel_maxsg + 1) *
8915 sizeof(u32)), GFP_KERNEL);
8916
8917 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8918 (h->ioaccel2_blockFetchTable == NULL)) {
8919 rc = -ENOMEM;
8920 goto clean_up;
8921 }
8922
8923 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8924 if (rc)
aca9012a
SC		 8925 goto clean_up;
8926
8927 memset(h->ioaccel2_cmd_pool, 0,
8928 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8929 return 0;
8930
8931clean_up:
1fb7c98a 8932 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8933 return rc;
aca9012a
SC		 8934}
8935
105a3dbc
RE		 8936/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8937static void hpsa_free_performant_mode(struct ctlr_info *h)
8938{
8939 kfree(h->blockFetchTable);
8940 h->blockFetchTable = NULL;
8941 hpsa_free_reply_queues(h);
8942 hpsa_free_ioaccel1_cmd_and_bft(h);
8943 hpsa_free_ioaccel2_cmd_and_bft(h);
8944}
8945
8946/* return -ENODEV on error, 0 on success (or no action)
8947 * allocates numerous items that must be freed later
8948 */
8949static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8950{
8951 u32 trans_support;
e1f7de0c
MG		 8952 unsigned long transMethod = CFGTBL_Trans_Performant |
8953 CFGTBL_Trans_use_short_tags;
105a3dbc 8954 int i, rc;
6c311b57 8955
02ec19c8 8956 if (hpsa_simple_mode)
105a3dbc 8957 return 0;
02ec19c8 8958
67c99a72 8959 trans_support = readl(&(h->cfgtable->TransportSupport));
8960 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8961 return 0;
67c99a72 8962
e1f7de0c
MG		 8963 /* Check for I/O accelerator mode support */
8964 if (trans_support & CFGTBL_Trans_io_accel1) {
8965 transMethod |= CFGTBL_Trans_io_accel1 |
8966 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8967 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8968 if (rc)
8969 return rc;
8970 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8971 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8972 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8973 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8974 if (rc)
8975 return rc;
e1f7de0c
MG		 8976 }
8977
eee0f03a 8978 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8979 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8980 /* Performant mode ring buffer and supporting data structures */
072b0518 8981 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8982
254f796b 8983 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8984 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8985 h->reply_queue_size,
8986 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8987 if (!h->reply_queue[i].head) {
8988 rc = -ENOMEM;
8989 goto clean1; /* rq, ioaccel */
8990 }
254f796b
MG		 8991 h->reply_queue[i].size = h->max_commands;
8992 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8993 h->reply_queue[i].current_entry = 0;
8994 }
8995
6c311b57 8996 /* Need a block fetch table for performant mode */
d66ae08b 8997 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8998 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8999 if (!h->blockFetchTable) {
9000 rc = -ENOMEM;
9001 goto clean1; /* rq, ioaccel */
9002 }
6c311b57 9003
105a3dbc
RE		 9004 rc = hpsa_enter_performant_mode(h, trans_support);
9005 if (rc)
9006 goto clean2; /* bft, rq, ioaccel */
9007 return 0;
303932fd 9008
105a3dbc 9009clean2: /* bft, rq, ioaccel */
303932fd 9010 kfree(h->blockFetchTable);
105a3dbc
RE		 9011 h->blockFetchTable = NULL;
9012clean1: /* rq, ioaccel */
9013 hpsa_free_reply_queues(h);
9014 hpsa_free_ioaccel1_cmd_and_bft(h);
9015 hpsa_free_ioaccel2_cmd_and_bft(h);
9016 return rc;
303932fd
DB		 9017}
9018
23100dd9 9019static int is_accelerated_cmd(struct CommandList *c)
76438d08 9020{
23100dd9
SC		 9021 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9022}
9023
9024static void hpsa_drain_accel_commands(struct ctlr_info *h)
9025{
9026 struct CommandList *c = NULL;
f2405db8 9027 int i, accel_cmds_out;
281a7fd0 9028 int refcount;
76438d08 9029
f2405db8 9030 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9031 accel_cmds_out = 0;
f2405db8 9032 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9033 c = h->cmd_pool + i;
281a7fd0
WS		 9034 refcount = atomic_inc_return(&c->refcount);
9035 if (refcount > 1) /* Command is allocated */
9036 accel_cmds_out += is_accelerated_cmd(c);
9037 cmd_free(h, c);
f2405db8 9038 }
23100dd9 9039 if (accel_cmds_out <= 0)
281a7fd0 9040 break;
76438d08
SC		 9041 msleep(100);
9042 } while (1);
9043}
9044
edd16368
SC		 9045/*
9046 * This is it. Register the PCI driver information for the cards we control
9047 * the OS will call our registered routines when it finds one of our cards.
9048 */
9049static int __init hpsa_init(void)
9050{
31468401 9051 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 9052}
9053
9054static void __exit hpsa_cleanup(void)
9055{
9056 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 9057}
9058
e1f7de0c
MG		 9059static void __attribute__((unused)) verify_offsets(void)
9060{
dd0e19f3
ST		 9061#define VERIFY_OFFSET(member, offset) \
9062 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9063
9064 VERIFY_OFFSET(structure_size, 0);
9065 VERIFY_OFFSET(volume_blk_size, 4);
9066 VERIFY_OFFSET(volume_blk_cnt, 8);
9067 VERIFY_OFFSET(phys_blk_shift, 16);
9068 VERIFY_OFFSET(parity_rotation_shift, 17);
9069 VERIFY_OFFSET(strip_size, 18);
9070 VERIFY_OFFSET(disk_starting_blk, 20);
9071 VERIFY_OFFSET(disk_blk_cnt, 28);
9072 VERIFY_OFFSET(data_disks_per_row, 36);
9073 VERIFY_OFFSET(metadata_disks_per_row, 38);
9074 VERIFY_OFFSET(row_cnt, 40);
9075 VERIFY_OFFSET(layout_map_count, 42);
9076 VERIFY_OFFSET(flags, 44);
9077 VERIFY_OFFSET(dekindex, 46);
9078 /* VERIFY_OFFSET(reserved, 48 */
9079 VERIFY_OFFSET(data, 64);
9080
9081#undef VERIFY_OFFSET
9082
b66cc250
MM		 9083#define VERIFY_OFFSET(member, offset) \
9084 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9085
9086 VERIFY_OFFSET(IU_type, 0);
9087 VERIFY_OFFSET(direction, 1);
9088 VERIFY_OFFSET(reply_queue, 2);
9089 /* VERIFY_OFFSET(reserved1, 3); */
9090 VERIFY_OFFSET(scsi_nexus, 4);
9091 VERIFY_OFFSET(Tag, 8);
9092 VERIFY_OFFSET(cdb, 16);
9093 VERIFY_OFFSET(cciss_lun, 32);
9094 VERIFY_OFFSET(data_len, 40);
9095 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9096 VERIFY_OFFSET(sg_count, 45);
9097 /* VERIFY_OFFSET(reserved3 */
9098 VERIFY_OFFSET(err_ptr, 48);
9099 VERIFY_OFFSET(err_len, 56);
9100 /* VERIFY_OFFSET(reserved4 */
9101 VERIFY_OFFSET(sg, 64);
9102
9103#undef VERIFY_OFFSET
9104
e1f7de0c
MG		 9105#define VERIFY_OFFSET(member, offset) \
9106 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9107
9108 VERIFY_OFFSET(dev_handle, 0x00);
9109 VERIFY_OFFSET(reserved1, 0x02);
9110 VERIFY_OFFSET(function, 0x03);
9111 VERIFY_OFFSET(reserved2, 0x04);
9112 VERIFY_OFFSET(err_info, 0x0C);
9113 VERIFY_OFFSET(reserved3, 0x10);
9114 VERIFY_OFFSET(err_info_len, 0x12);
9115 VERIFY_OFFSET(reserved4, 0x13);
9116 VERIFY_OFFSET(sgl_offset, 0x14);
9117 VERIFY_OFFSET(reserved5, 0x15);
9118 VERIFY_OFFSET(transfer_len, 0x1C);
9119 VERIFY_OFFSET(reserved6, 0x20);
9120 VERIFY_OFFSET(io_flags, 0x24);
9121 VERIFY_OFFSET(reserved7, 0x26);
9122 VERIFY_OFFSET(LUN, 0x34);
9123 VERIFY_OFFSET(control, 0x3C);
9124 VERIFY_OFFSET(CDB, 0x40);
9125 VERIFY_OFFSET(reserved8, 0x50);
9126 VERIFY_OFFSET(host_context_flags, 0x60);
9127 VERIFY_OFFSET(timeout_sec, 0x62);
9128 VERIFY_OFFSET(ReplyQueue, 0x64);
9129 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9130 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9131 VERIFY_OFFSET(host_addr, 0x70);
9132 VERIFY_OFFSET(CISS_LUN, 0x78);
9133 VERIFY_OFFSET(SG, 0x78 + 8);
9134#undef VERIFY_OFFSET
9135}
9136
edd16368
SC		 9137module_init(hpsa_init);
9138module_exit(hpsa_cleanup);
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