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[SCSI] hpsa: get ioaccel mode 2 i/o working
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
76438d08
SC		 223static void hpsa_drain_commands(struct ctlr_info *h);
224static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
227 u8 *scsi3addr);
edd16368 228
edd16368
SC		 229static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
230{
231 unsigned long *priv = shost_priv(sdev->host);
232 return (struct ctlr_info *) *priv;
233}
234
a23513e8
SC		 235static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
236{
237 unsigned long *priv = shost_priv(sh);
238 return (struct ctlr_info *) *priv;
239}
240
edd16368
SC		 241static int check_for_unit_attention(struct ctlr_info *h,
242 struct CommandList *c)
243{
244 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
245 return 0;
246
247 switch (c->err_info->SenseInfo[12]) {
248 case STATE_CHANGED:
f79cfec6 249 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 250 "detected, command retried\n", h->ctlr);
251 break;
252 case LUN_FAILED:
f79cfec6 253 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 254 "detected, action required\n", h->ctlr);
255 break;
256 case REPORT_LUNS_CHANGED:
f79cfec6 257 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 258 "changed, action required\n", h->ctlr);
edd16368 259 /*
4f4eb9f1
ST		 260 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
261 * target (array) devices.
edd16368
SC		 262 */
263 break;
264 case POWER_OR_RESET:
f79cfec6 265 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 266 "or device reset detected\n", h->ctlr);
267 break;
268 case UNIT_ATTENTION_CLEARED:
f79cfec6 269 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 270 "cleared by another initiator\n", h->ctlr);
271 break;
272 default:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 274 "unit attention detected\n", h->ctlr);
275 break;
276 }
277 return 1;
278}
279
852af20a
MB		 280static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
281{
282 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
283 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
284 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
285 return 0;
286 dev_warn(&h->pdev->dev, HPSA "device busy");
287 return 1;
288}
289
edd16368
SC		 290static ssize_t host_store_rescan(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 struct ctlr_info *h;
295 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 296 h = shost_to_hba(shost);
31468401 297 hpsa_scan_start(h->scsi_host);
edd16368
SC		 298 return count;
299}
300
d28ce020
SC		 301static ssize_t host_show_firmware_revision(struct device *dev,
302 struct device_attribute *attr, char *buf)
303{
304 struct ctlr_info *h;
305 struct Scsi_Host *shost = class_to_shost(dev);
306 unsigned char *fwrev;
307
308 h = shost_to_hba(shost);
309 if (!h->hba_inquiry_data)
310 return 0;
311 fwrev = &h->hba_inquiry_data[32];
312 return snprintf(buf, 20, "%c%c%c%c\n",
313 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
314}
315
94a13649
SC		 316static ssize_t host_show_commands_outstanding(struct device *dev,
317 struct device_attribute *attr, char *buf)
318{
319 struct Scsi_Host *shost = class_to_shost(dev);
320 struct ctlr_info *h = shost_to_hba(shost);
321
322 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
323}
324
745a7a25
SC		 325static ssize_t host_show_transport_mode(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330
331 h = shost_to_hba(shost);
332 return snprintf(buf, 20, "%s\n",
960a30e7 333 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 334 "performant" : "simple");
335}
336
46380786 337/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 338static u32 unresettable_controller[] = {
339 0x324a103C, /* Smart Array P712m */
340 0x324b103C, /* SmartArray P711m */
341 0x3223103C, /* Smart Array P800 */
342 0x3234103C, /* Smart Array P400 */
343 0x3235103C, /* Smart Array P400i */
344 0x3211103C, /* Smart Array E200i */
345 0x3212103C, /* Smart Array E200 */
346 0x3213103C, /* Smart Array E200i */
347 0x3214103C, /* Smart Array E200i */
348 0x3215103C, /* Smart Array E200i */
349 0x3237103C, /* Smart Array E500 */
350 0x323D103C, /* Smart Array P700m */
7af0abbc 351 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 352 0x409C0E11, /* Smart Array 6400 */
353 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 354 0x40700E11, /* Smart Array 5300 */
355 0x40820E11, /* Smart Array 532 */
356 0x40830E11, /* Smart Array 5312 */
357 0x409A0E11, /* Smart Array 641 */
358 0x409B0E11, /* Smart Array 642 */
359 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 360};
361
46380786
SC		 362/* List of controllers which cannot even be soft reset */
363static u32 soft_unresettable_controller[] = {
7af0abbc 364 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 365 0x40700E11, /* Smart Array 5300 */
366 0x40820E11, /* Smart Array 532 */
367 0x40830E11, /* Smart Array 5312 */
368 0x409A0E11, /* Smart Array 641 */
369 0x409B0E11, /* Smart Array 642 */
370 0x40910E11, /* Smart Array 6i */
46380786
SC		 371 /* Exclude 640x boards. These are two pci devices in one slot
372 * which share a battery backed cache module. One controls the
373 * cache, the other accesses the cache through the one that controls
374 * it. If we reset the one controlling the cache, the other will
375 * likely not be happy. Just forbid resetting this conjoined mess.
376 * The 640x isn't really supported by hpsa anyway.
377 */
378 0x409C0E11, /* Smart Array 6400 */
379 0x409D0E11, /* Smart Array 6400 EM */
380};
381
382static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 383{
384 int i;
385
386 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 387 if (unresettable_controller[i] == board_id)
388 return 0;
389 return 1;
390}
391
392static int ctlr_is_soft_resettable(u32 board_id)
393{
394 int i;
395
396 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
397 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 398 return 0;
399 return 1;
400}
401
46380786
SC		 402static int ctlr_is_resettable(u32 board_id)
403{
404 return ctlr_is_hard_resettable(board_id) ||
405 ctlr_is_soft_resettable(board_id);
406}
407
941b1cda
SC		 408static ssize_t host_show_resettable(struct device *dev,
409 struct device_attribute *attr, char *buf)
410{
411 struct ctlr_info *h;
412 struct Scsi_Host *shost = class_to_shost(dev);
413
414 h = shost_to_hba(shost);
46380786 415 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 416}
417
edd16368
SC		 418static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
419{
420 return (scsi3addr[3] & 0xC0) == 0x40;
421}
422
423static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 424 "1(ADM)", "UNKNOWN"
edd16368
SC		 425};
426#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
427
428static ssize_t raid_level_show(struct device *dev,
429 struct device_attribute *attr, char *buf)
430{
431 ssize_t l = 0;
82a72c0a 432 unsigned char rlevel;
edd16368
SC		 433 struct ctlr_info *h;
434 struct scsi_device *sdev;
435 struct hpsa_scsi_dev_t *hdev;
436 unsigned long flags;
437
438 sdev = to_scsi_device(dev);
439 h = sdev_to_hba(sdev);
440 spin_lock_irqsave(&h->lock, flags);
441 hdev = sdev->hostdata;
442 if (!hdev) {
443 spin_unlock_irqrestore(&h->lock, flags);
444 return -ENODEV;
445 }
446
447 /* Is this even a logical drive? */
448 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
449 spin_unlock_irqrestore(&h->lock, flags);
450 l = snprintf(buf, PAGE_SIZE, "N/A\n");
451 return l;
452 }
453
454 rlevel = hdev->raid_level;
455 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 456 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 457 rlevel = RAID_UNKNOWN;
458 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
459 return l;
460}
461
462static ssize_t lunid_show(struct device *dev,
463 struct device_attribute *attr, char *buf)
464{
465 struct ctlr_info *h;
466 struct scsi_device *sdev;
467 struct hpsa_scsi_dev_t *hdev;
468 unsigned long flags;
469 unsigned char lunid[8];
470
471 sdev = to_scsi_device(dev);
472 h = sdev_to_hba(sdev);
473 spin_lock_irqsave(&h->lock, flags);
474 hdev = sdev->hostdata;
475 if (!hdev) {
476 spin_unlock_irqrestore(&h->lock, flags);
477 return -ENODEV;
478 }
479 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
480 spin_unlock_irqrestore(&h->lock, flags);
481 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
482 lunid[0], lunid[1], lunid[2], lunid[3],
483 lunid[4], lunid[5], lunid[6], lunid[7]);
484}
485
486static ssize_t unique_id_show(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct scsi_device *sdev;
491 struct hpsa_scsi_dev_t *hdev;
492 unsigned long flags;
493 unsigned char sn[16];
494
495 sdev = to_scsi_device(dev);
496 h = sdev_to_hba(sdev);
497 spin_lock_irqsave(&h->lock, flags);
498 hdev = sdev->hostdata;
499 if (!hdev) {
500 spin_unlock_irqrestore(&h->lock, flags);
501 return -ENODEV;
502 }
503 memcpy(sn, hdev->device_id, sizeof(sn));
504 spin_unlock_irqrestore(&h->lock, flags);
505 return snprintf(buf, 16 * 2 + 2,
506 "%02X%02X%02X%02X%02X%02X%02X%02X"
507 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
508 sn[0], sn[1], sn[2], sn[3],
509 sn[4], sn[5], sn[6], sn[7],
510 sn[8], sn[9], sn[10], sn[11],
511 sn[12], sn[13], sn[14], sn[15]);
512}
513
c1988684
ST		 514static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
515 struct device_attribute *attr, char *buf)
516{
517 struct ctlr_info *h;
518 struct scsi_device *sdev;
519 struct hpsa_scsi_dev_t *hdev;
520 unsigned long flags;
521 int offload_enabled;
522
523 sdev = to_scsi_device(dev);
524 h = sdev_to_hba(sdev);
525 spin_lock_irqsave(&h->lock, flags);
526 hdev = sdev->hostdata;
527 if (!hdev) {
528 spin_unlock_irqrestore(&h->lock, flags);
529 return -ENODEV;
530 }
531 offload_enabled = hdev->offload_enabled;
532 spin_unlock_irqrestore(&h->lock, flags);
533 return snprintf(buf, 20, "%d\n", offload_enabled);
534}
535
3f5eac3a
SC		 536static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
537static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
538static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
539static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 540static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
541 host_show_hp_ssd_smart_path_enabled, NULL);
3f5eac3a
SC		 542static DEVICE_ATTR(firmware_revision, S_IRUGO,
543 host_show_firmware_revision, NULL);
544static DEVICE_ATTR(commands_outstanding, S_IRUGO,
545 host_show_commands_outstanding, NULL);
546static DEVICE_ATTR(transport_mode, S_IRUGO,
547 host_show_transport_mode, NULL);
941b1cda
SC		 548static DEVICE_ATTR(resettable, S_IRUGO,
549 host_show_resettable, NULL);
3f5eac3a
SC		 550
551static struct device_attribute *hpsa_sdev_attrs[] = {
552 &dev_attr_raid_level,
553 &dev_attr_lunid,
554 &dev_attr_unique_id,
c1988684 555 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 556 NULL,
557};
558
559static struct device_attribute *hpsa_shost_attrs[] = {
560 &dev_attr_rescan,
561 &dev_attr_firmware_revision,
562 &dev_attr_commands_outstanding,
563 &dev_attr_transport_mode,
941b1cda 564 &dev_attr_resettable,
3f5eac3a
SC		 565 NULL,
566};
567
568static struct scsi_host_template hpsa_driver_template = {
569 .module = THIS_MODULE,
f79cfec6
SC		 570 .name = HPSA,
571 .proc_name = HPSA,
3f5eac3a
SC		 572 .queuecommand = hpsa_scsi_queue_command,
573 .scan_start = hpsa_scan_start,
574 .scan_finished = hpsa_scan_finished,
575 .change_queue_depth = hpsa_change_queue_depth,
576 .this_id = -1,
577 .use_clustering = ENABLE_CLUSTERING,
75167d2c 578 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 579 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
580 .ioctl = hpsa_ioctl,
581 .slave_alloc = hpsa_slave_alloc,
582 .slave_destroy = hpsa_slave_destroy,
583#ifdef CONFIG_COMPAT
584 .compat_ioctl = hpsa_compat_ioctl,
585#endif
586 .sdev_attrs = hpsa_sdev_attrs,
587 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 588 .max_sectors = 8192,
54b2b50c 589 .no_write_same = 1,
3f5eac3a
SC		 590};
591
592
593/* Enqueuing and dequeuing functions for cmdlists. */
594static inline void addQ(struct list_head *list, struct CommandList *c)
595{
596 list_add_tail(&c->list, list);
597}
598
254f796b 599static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 600{
601 u32 a;
254f796b 602 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 603 unsigned long flags;
3f5eac3a 604
e1f7de0c
MG		 605 if (h->transMethod & CFGTBL_Trans_io_accel1)
606 return h->access.command_completed(h, q);
607
3f5eac3a 608 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 609 return h->access.command_completed(h, q);
3f5eac3a 610
254f796b
MG		 611 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
612 a = rq->head[rq->current_entry];
613 rq->current_entry++;
e16a33ad 614 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 615 h->commands_outstanding--;
e16a33ad 616 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 617 } else {
618 a = FIFO_EMPTY;
619 }
620 /* Check for wraparound */
254f796b
MG		 621 if (rq->current_entry == h->max_commands) {
622 rq->current_entry = 0;
623 rq->wraparound ^= 1;
3f5eac3a
SC		 624 }
625 return a;
626}
627
c349775e
ST		 628/*
629 * There are some special bits in the bus address of the
630 * command that we have to set for the controller to know
631 * how to process the command:
632 *
633 * Normal performant mode:
634 * bit 0: 1 means performant mode, 0 means simple mode.
635 * bits 1-3 = block fetch table entry
636 * bits 4-6 = command type (== 0)
637 *
638 * ioaccel1 mode:
639 * bit 0 = "performant mode" bit.
640 * bits 1-3 = block fetch table entry
641 * bits 4-6 = command type (== 110)
642 * (command type is needed because ioaccel1 mode
643 * commands are submitted through the same register as normal
644 * mode commands, so this is how the controller knows whether
645 * the command is normal mode or ioaccel1 mode.)
646 *
647 * ioaccel2 mode:
648 * bit 0 = "performant mode" bit.
649 * bits 1-4 = block fetch table entry (note extra bit)
650 * bits 4-6 = not needed, because ioaccel2 mode has
651 * a separate special register for submitting commands.
652 */
653
3f5eac3a
SC		 654/* set_performant_mode: Modify the tag for cciss performant
655 * set bit 0 for pull model, bits 3-1 for block fetch
656 * register number
657 */
658static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
659{
254f796b 660 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 661 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 662 if (likely(h->msix_vector > 0))
254f796b 663 c->Header.ReplyQueue =
804a5cb5 664 raw_smp_processor_id() % h->nreply_queues;
254f796b 665 }
3f5eac3a
SC		 666}
667
c349775e
ST		 668static void set_ioaccel1_performant_mode(struct ctlr_info *h,
669 struct CommandList *c)
670{
671 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
672
673 /* Tell the controller to post the reply to the queue for this
674 * processor. This seems to give the best I/O throughput.
675 */
676 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
677 /* Set the bits in the address sent down to include:
678 * - performant mode bit (bit 0)
679 * - pull count (bits 1-3)
680 * - command type (bits 4-6)
681 */
682 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
683 IOACCEL1_BUSADDR_CMDTYPE;
684}
685
686static void set_ioaccel2_performant_mode(struct ctlr_info *h,
687 struct CommandList *c)
688{
689 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
690
691 /* Tell the controller to post the reply to the queue for this
692 * processor. This seems to give the best I/O throughput.
693 */
694 cp->reply_queue = smp_processor_id() % h->nreply_queues;
695 /* Set the bits in the address sent down to include:
696 * - performant mode bit not used in ioaccel mode 2
697 * - pull count (bits 0-3)
698 * - command type isn't needed for ioaccel2
699 */
700 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
701}
702
e85c5974
SC		 703static int is_firmware_flash_cmd(u8 *cdb)
704{
705 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
706}
707
708/*
709 * During firmware flash, the heartbeat register may not update as frequently
710 * as it should. So we dial down lockup detection during firmware flash. and
711 * dial it back up when firmware flash completes.
712 */
713#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
714#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
715static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
716 struct CommandList *c)
717{
718 if (!is_firmware_flash_cmd(c->Request.CDB))
719 return;
720 atomic_inc(&h->firmware_flash_in_progress);
721 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
722}
723
724static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
725 struct CommandList *c)
726{
727 if (is_firmware_flash_cmd(c->Request.CDB) &&
728 atomic_dec_and_test(&h->firmware_flash_in_progress))
729 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
730}
731
3f5eac3a
SC		 732static void enqueue_cmd_and_start_io(struct ctlr_info *h,
733 struct CommandList *c)
734{
735 unsigned long flags;
736
c349775e
ST		 737 switch (c->cmd_type) {
738 case CMD_IOACCEL1:
739 set_ioaccel1_performant_mode(h, c);
740 break;
741 case CMD_IOACCEL2:
742 set_ioaccel2_performant_mode(h, c);
743 break;
744 default:
745 set_performant_mode(h, c);
746 }
e85c5974 747 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 748 spin_lock_irqsave(&h->lock, flags);
749 addQ(&h->reqQ, c);
750 h->Qdepth++;
3f5eac3a 751 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 752 start_io(h);
3f5eac3a
SC		 753}
754
755static inline void removeQ(struct CommandList *c)
756{
757 if (WARN_ON(list_empty(&c->list)))
758 return;
759 list_del_init(&c->list);
760}
761
762static inline int is_hba_lunid(unsigned char scsi3addr[])
763{
764 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
765}
766
767static inline int is_scsi_rev_5(struct ctlr_info *h)
768{
769 if (!h->hba_inquiry_data)
770 return 0;
771 if ((h->hba_inquiry_data[2] & 0x07) == 5)
772 return 1;
773 return 0;
774}
775
edd16368
SC		 776static int hpsa_find_target_lun(struct ctlr_info *h,
777 unsigned char scsi3addr[], int bus, int *target, int *lun)
778{
779 /* finds an unused bus, target, lun for a new physical device
780 * assumes h->devlock is held
781 */
782 int i, found = 0;
cfe5badc 783 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 784
263d9401 785 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 786
787 for (i = 0; i < h->ndevices; i++) {
788 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 789 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 790 }
791
263d9401
AM		 792 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
793 if (i < HPSA_MAX_DEVICES) {
794 /* *bus = 1; */
795 *target = i;
796 *lun = 0;
797 found = 1;
edd16368
SC		 798 }
799 return !found;
800}
801
802/* Add an entry into h->dev[] array. */
803static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
804 struct hpsa_scsi_dev_t *device,
805 struct hpsa_scsi_dev_t *added[], int *nadded)
806{
807 /* assumes h->devlock is held */
808 int n = h->ndevices;
809 int i;
810 unsigned char addr1[8], addr2[8];
811 struct hpsa_scsi_dev_t *sd;
812
cfe5badc 813 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 814 dev_err(&h->pdev->dev, "too many devices, some will be "
815 "inaccessible.\n");
816 return -1;
817 }
818
819 /* physical devices do not have lun or target assigned until now. */
820 if (device->lun != -1)
821 /* Logical device, lun is already assigned. */
822 goto lun_assigned;
823
824 /* If this device a non-zero lun of a multi-lun device
825 * byte 4 of the 8-byte LUN addr will contain the logical
826 * unit no, zero otherise.
827 */
828 if (device->scsi3addr[4] == 0) {
829 /* This is not a non-zero lun of a multi-lun device */
830 if (hpsa_find_target_lun(h, device->scsi3addr,
831 device->bus, &device->target, &device->lun) != 0)
832 return -1;
833 goto lun_assigned;
834 }
835
836 /* This is a non-zero lun of a multi-lun device.
837 * Search through our list and find the device which
838 * has the same 8 byte LUN address, excepting byte 4.
839 * Assign the same bus and target for this new LUN.
840 * Use the logical unit number from the firmware.
841 */
842 memcpy(addr1, device->scsi3addr, 8);
843 addr1[4] = 0;
844 for (i = 0; i < n; i++) {
845 sd = h->dev[i];
846 memcpy(addr2, sd->scsi3addr, 8);
847 addr2[4] = 0;
848 /* differ only in byte 4? */
849 if (memcmp(addr1, addr2, 8) == 0) {
850 device->bus = sd->bus;
851 device->target = sd->target;
852 device->lun = device->scsi3addr[4];
853 break;
854 }
855 }
856 if (device->lun == -1) {
857 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
858 " suspect firmware bug or unsupported hardware "
859 "configuration.\n");
860 return -1;
861 }
862
863lun_assigned:
864
865 h->dev[n] = device;
866 h->ndevices++;
867 added[*nadded] = device;
868 (*nadded)++;
869
870 /* initially, (before registering with scsi layer) we don't
871 * know our hostno and we don't want to print anything first
872 * time anyway (the scsi layer's inquiries will show that info)
873 */
874 /* if (hostno != -1) */
875 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
876 scsi_device_type(device->devtype), hostno,
877 device->bus, device->target, device->lun);
878 return 0;
879}
880
bd9244f7
ST		 881/* Update an entry in h->dev[] array. */
882static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
883 int entry, struct hpsa_scsi_dev_t *new_entry)
884{
885 /* assumes h->devlock is held */
886 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
887
888 /* Raid level changed. */
889 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 890
891 /* Raid offload parameters changed. */
892 h->dev[entry]->offload_config = new_entry->offload_config;
893 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
894
bd9244f7
ST		 895 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
896 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
897 new_entry->target, new_entry->lun);
898}
899
2a8ccf31
SC		 900/* Replace an entry from h->dev[] array. */
901static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
902 int entry, struct hpsa_scsi_dev_t *new_entry,
903 struct hpsa_scsi_dev_t *added[], int *nadded,
904 struct hpsa_scsi_dev_t *removed[], int *nremoved)
905{
906 /* assumes h->devlock is held */
cfe5badc 907 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 908 removed[*nremoved] = h->dev[entry];
909 (*nremoved)++;
01350d05
SC		 910
911 /*
912 * New physical devices won't have target/lun assigned yet
913 * so we need to preserve the values in the slot we are replacing.
914 */
915 if (new_entry->target == -1) {
916 new_entry->target = h->dev[entry]->target;
917 new_entry->lun = h->dev[entry]->lun;
918 }
919
2a8ccf31
SC		 920 h->dev[entry] = new_entry;
921 added[*nadded] = new_entry;
922 (*nadded)++;
923 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
924 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
925 new_entry->target, new_entry->lun);
926}
927
edd16368
SC		 928/* Remove an entry from h->dev[] array. */
929static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
930 struct hpsa_scsi_dev_t *removed[], int *nremoved)
931{
932 /* assumes h->devlock is held */
933 int i;
934 struct hpsa_scsi_dev_t *sd;
935
cfe5badc 936 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 937
938 sd = h->dev[entry];
939 removed[*nremoved] = h->dev[entry];
940 (*nremoved)++;
941
942 for (i = entry; i < h->ndevices-1; i++)
943 h->dev[i] = h->dev[i+1];
944 h->ndevices--;
945 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
946 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
947 sd->lun);
948}
949
950#define SCSI3ADDR_EQ(a, b) ( \
951 (a)[7] == (b)[7] && \
952 (a)[6] == (b)[6] && \
953 (a)[5] == (b)[5] && \
954 (a)[4] == (b)[4] && \
955 (a)[3] == (b)[3] && \
956 (a)[2] == (b)[2] && \
957 (a)[1] == (b)[1] && \
958 (a)[0] == (b)[0])
959
960static void fixup_botched_add(struct ctlr_info *h,
961 struct hpsa_scsi_dev_t *added)
962{
963 /* called when scsi_add_device fails in order to re-adjust
964 * h->dev[] to match the mid layer's view.
965 */
966 unsigned long flags;
967 int i, j;
968
969 spin_lock_irqsave(&h->lock, flags);
970 for (i = 0; i < h->ndevices; i++) {
971 if (h->dev[i] == added) {
972 for (j = i; j < h->ndevices-1; j++)
973 h->dev[j] = h->dev[j+1];
974 h->ndevices--;
975 break;
976 }
977 }
978 spin_unlock_irqrestore(&h->lock, flags);
979 kfree(added);
980}
981
982static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
983 struct hpsa_scsi_dev_t *dev2)
984{
edd16368
SC		 985 /* we compare everything except lun and target as these
986 * are not yet assigned. Compare parts likely
987 * to differ first
988 */
989 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
990 sizeof(dev1->scsi3addr)) != 0)
991 return 0;
992 if (memcmp(dev1->device_id, dev2->device_id,
993 sizeof(dev1->device_id)) != 0)
994 return 0;
995 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
996 return 0;
997 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
998 return 0;
edd16368
SC		 999 if (dev1->devtype != dev2->devtype)
1000 return 0;
edd16368
SC		 1001 if (dev1->bus != dev2->bus)
1002 return 0;
1003 return 1;
1004}
1005
bd9244f7
ST		 1006static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1007 struct hpsa_scsi_dev_t *dev2)
1008{
1009 /* Device attributes that can change, but don't mean
1010 * that the device is a different device, nor that the OS
1011 * needs to be told anything about the change.
1012 */
1013 if (dev1->raid_level != dev2->raid_level)
1014 return 1;
250fb125
SC		 1015 if (dev1->offload_config != dev2->offload_config)
1016 return 1;
1017 if (dev1->offload_enabled != dev2->offload_enabled)
1018 return 1;
bd9244f7
ST		 1019 return 0;
1020}
1021
edd16368
SC		 1022/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1023 * and return needle location in *index. If scsi3addr matches, but not
1024 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1025 * location in *index.
1026 * In the case of a minor device attribute change, such as RAID level, just
1027 * return DEVICE_UPDATED, along with the updated device's location in index.
1028 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1029 */
1030static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1031 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1032 int *index)
1033{
1034 int i;
1035#define DEVICE_NOT_FOUND 0
1036#define DEVICE_CHANGED 1
1037#define DEVICE_SAME 2
bd9244f7 1038#define DEVICE_UPDATED 3
edd16368 1039 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1040 if (haystack[i] == NULL) /* previously removed. */
1041 continue;
edd16368
SC		 1042 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1043 *index = i;
bd9244f7
ST		 1044 if (device_is_the_same(needle, haystack[i])) {
1045 if (device_updated(needle, haystack[i]))
1046 return DEVICE_UPDATED;
edd16368 1047 return DEVICE_SAME;
bd9244f7 1048 } else {
edd16368 1049 return DEVICE_CHANGED;
bd9244f7 1050 }
edd16368
SC		 1051 }
1052 }
1053 *index = -1;
1054 return DEVICE_NOT_FOUND;
1055}
1056
4967bd3e 1057static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1058 struct hpsa_scsi_dev_t *sd[], int nsds)
1059{
1060 /* sd contains scsi3 addresses and devtypes, and inquiry
1061 * data. This function takes what's in sd to be the current
1062 * reality and updates h->dev[] to reflect that reality.
1063 */
1064 int i, entry, device_change, changes = 0;
1065 struct hpsa_scsi_dev_t *csd;
1066 unsigned long flags;
1067 struct hpsa_scsi_dev_t **added, **removed;
1068 int nadded, nremoved;
1069 struct Scsi_Host *sh = NULL;
1070
cfe5badc
ST		 1071 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1072 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1073
1074 if (!added || !removed) {
1075 dev_warn(&h->pdev->dev, "out of memory in "
1076 "adjust_hpsa_scsi_table\n");
1077 goto free_and_out;
1078 }
1079
1080 spin_lock_irqsave(&h->devlock, flags);
1081
1082 /* find any devices in h->dev[] that are not in
1083 * sd[] and remove them from h->dev[], and for any
1084 * devices which have changed, remove the old device
1085 * info and add the new device info.
bd9244f7
ST		 1086 * If minor device attributes change, just update
1087 * the existing device structure.
edd16368
SC		 1088 */
1089 i = 0;
1090 nremoved = 0;
1091 nadded = 0;
1092 while (i < h->ndevices) {
1093 csd = h->dev[i];
1094 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1095 if (device_change == DEVICE_NOT_FOUND) {
1096 changes++;
1097 hpsa_scsi_remove_entry(h, hostno, i,
1098 removed, &nremoved);
1099 continue; /* remove ^^^, hence i not incremented */
1100 } else if (device_change == DEVICE_CHANGED) {
1101 changes++;
2a8ccf31
SC		 1102 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1103 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1104 /* Set it to NULL to prevent it from being freed
1105 * at the bottom of hpsa_update_scsi_devices()
1106 */
1107 sd[entry] = NULL;
bd9244f7
ST		 1108 } else if (device_change == DEVICE_UPDATED) {
1109 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1110 }
1111 i++;
1112 }
1113
1114 /* Now, make sure every device listed in sd[] is also
1115 * listed in h->dev[], adding them if they aren't found
1116 */
1117
1118 for (i = 0; i < nsds; i++) {
1119 if (!sd[i]) /* if already added above. */
1120 continue;
1121 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1122 h->ndevices, &entry);
1123 if (device_change == DEVICE_NOT_FOUND) {
1124 changes++;
1125 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1126 added, &nadded) != 0)
1127 break;
1128 sd[i] = NULL; /* prevent from being freed later. */
1129 } else if (device_change == DEVICE_CHANGED) {
1130 /* should never happen... */
1131 changes++;
1132 dev_warn(&h->pdev->dev,
1133 "device unexpectedly changed.\n");
1134 /* but if it does happen, we just ignore that device */
1135 }
1136 }
1137 spin_unlock_irqrestore(&h->devlock, flags);
1138
1139 /* Don't notify scsi mid layer of any changes the first time through
1140 * (or if there are no changes) scsi_scan_host will do it later the
1141 * first time through.
1142 */
1143 if (hostno == -1 || !changes)
1144 goto free_and_out;
1145
1146 sh = h->scsi_host;
1147 /* Notify scsi mid layer of any removed devices */
1148 for (i = 0; i < nremoved; i++) {
1149 struct scsi_device *sdev =
1150 scsi_device_lookup(sh, removed[i]->bus,
1151 removed[i]->target, removed[i]->lun);
1152 if (sdev != NULL) {
1153 scsi_remove_device(sdev);
1154 scsi_device_put(sdev);
1155 } else {
1156 /* We don't expect to get here.
1157 * future cmds to this device will get selection
1158 * timeout as if the device was gone.
1159 */
1160 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1161 " for removal.", hostno, removed[i]->bus,
1162 removed[i]->target, removed[i]->lun);
1163 }
1164 kfree(removed[i]);
1165 removed[i] = NULL;
1166 }
1167
1168 /* Notify scsi mid layer of any added devices */
1169 for (i = 0; i < nadded; i++) {
1170 if (scsi_add_device(sh, added[i]->bus,
1171 added[i]->target, added[i]->lun) == 0)
1172 continue;
1173 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1174 "device not added.\n", hostno, added[i]->bus,
1175 added[i]->target, added[i]->lun);
1176 /* now we have to remove it from h->dev,
1177 * since it didn't get added to scsi mid layer
1178 */
1179 fixup_botched_add(h, added[i]);
1180 }
1181
1182free_and_out:
1183 kfree(added);
1184 kfree(removed);
edd16368
SC		 1185}
1186
1187/*
9e03aa2f 1188 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1189 * Assume's h->devlock is held.
1190 */
1191static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1192 int bus, int target, int lun)
1193{
1194 int i;
1195 struct hpsa_scsi_dev_t *sd;
1196
1197 for (i = 0; i < h->ndevices; i++) {
1198 sd = h->dev[i];
1199 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1200 return sd;
1201 }
1202 return NULL;
1203}
1204
1205/* link sdev->hostdata to our per-device structure. */
1206static int hpsa_slave_alloc(struct scsi_device *sdev)
1207{
1208 struct hpsa_scsi_dev_t *sd;
1209 unsigned long flags;
1210 struct ctlr_info *h;
1211
1212 h = sdev_to_hba(sdev);
1213 spin_lock_irqsave(&h->devlock, flags);
1214 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1215 sdev_id(sdev), sdev->lun);
1216 if (sd != NULL)
1217 sdev->hostdata = sd;
1218 spin_unlock_irqrestore(&h->devlock, flags);
1219 return 0;
1220}
1221
1222static void hpsa_slave_destroy(struct scsi_device *sdev)
1223{
bcc44255 1224 /* nothing to do. */
edd16368
SC		 1225}
1226
33a2ffce
SC		 1227static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1228{
1229 int i;
1230
1231 if (!h->cmd_sg_list)
1232 return;
1233 for (i = 0; i < h->nr_cmds; i++) {
1234 kfree(h->cmd_sg_list[i]);
1235 h->cmd_sg_list[i] = NULL;
1236 }
1237 kfree(h->cmd_sg_list);
1238 h->cmd_sg_list = NULL;
1239}
1240
1241static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1242{
1243 int i;
1244
1245 if (h->chainsize <= 0)
1246 return 0;
1247
1248 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1249 GFP_KERNEL);
1250 if (!h->cmd_sg_list)
1251 return -ENOMEM;
1252 for (i = 0; i < h->nr_cmds; i++) {
1253 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1254 h->chainsize, GFP_KERNEL);
1255 if (!h->cmd_sg_list[i])
1256 goto clean;
1257 }
1258 return 0;
1259
1260clean:
1261 hpsa_free_sg_chain_blocks(h);
1262 return -ENOMEM;
1263}
1264
e2bea6df 1265static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1266 struct CommandList *c)
1267{
1268 struct SGDescriptor *chain_sg, *chain_block;
1269 u64 temp64;
1270
1271 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1272 chain_block = h->cmd_sg_list[c->cmdindex];
1273 chain_sg->Ext = HPSA_SG_CHAIN;
1274 chain_sg->Len = sizeof(*chain_sg) *
1275 (c->Header.SGTotal - h->max_cmd_sg_entries);
1276 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1277 PCI_DMA_TODEVICE);
e2bea6df
SC		 1278 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1279 /* prevent subsequent unmapping */
1280 chain_sg->Addr.lower = 0;
1281 chain_sg->Addr.upper = 0;
1282 return -1;
1283 }
33a2ffce
SC		 1284 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1285 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1286 return 0;
33a2ffce
SC		 1287}
1288
1289static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1290 struct CommandList *c)
1291{
1292 struct SGDescriptor *chain_sg;
1293 union u64bit temp64;
1294
1295 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1296 return;
1297
1298 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1299 temp64.val32.lower = chain_sg->Addr.lower;
1300 temp64.val32.upper = chain_sg->Addr.upper;
1301 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1302}
1303
c349775e
ST		 1304static void handle_ioaccel_mode2_error(struct ctlr_info *h,
1305 struct CommandList *c,
1306 struct scsi_cmnd *cmd,
1307 struct io_accel2_cmd *c2)
1308{
1309 int data_len;
1310
1311 switch (c2->error_data.serv_response) {
1312 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1313 switch (c2->error_data.status) {
1314 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1315 break;
1316 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1317 dev_warn(&h->pdev->dev,
1318 "%s: task complete with check condition.\n",
1319 "HP SSD Smart Path");
1320 if (c2->error_data.data_present !=
1321 IOACCEL2_SENSE_DATA_PRESENT)
1322 break;
1323 /* copy the sense data */
1324 data_len = c2->error_data.sense_data_len;
1325 if (data_len > SCSI_SENSE_BUFFERSIZE)
1326 data_len = SCSI_SENSE_BUFFERSIZE;
1327 if (data_len > sizeof(c2->error_data.sense_data_buff))
1328 data_len =
1329 sizeof(c2->error_data.sense_data_buff);
1330 memcpy(cmd->sense_buffer,
1331 c2->error_data.sense_data_buff, data_len);
1332 cmd->result |= SAM_STAT_CHECK_CONDITION;
1333 break;
1334 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1335 dev_warn(&h->pdev->dev,
1336 "%s: task complete with BUSY status.\n",
1337 "HP SSD Smart Path");
1338 break;
1339 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1340 dev_warn(&h->pdev->dev,
1341 "%s: task complete with reservation conflict.\n",
1342 "HP SSD Smart Path");
1343 break;
1344 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1345 /* Make scsi midlayer do unlimited retries */
1346 cmd->result = DID_IMM_RETRY << 16;
1347 break;
1348 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1349 dev_warn(&h->pdev->dev,
1350 "%s: task complete with aborted status.\n",
1351 "HP SSD Smart Path");
1352 break;
1353 default:
1354 dev_warn(&h->pdev->dev,
1355 "%s: task complete with unrecognized status: 0x%02x\n",
1356 "HP SSD Smart Path", c2->error_data.status);
1357 break;
1358 }
1359 break;
1360 case IOACCEL2_SERV_RESPONSE_FAILURE:
1361 /* don't expect to get here. */
1362 dev_warn(&h->pdev->dev,
1363 "unexpected delivery or target failure, status = 0x%02x\n",
1364 c2->error_data.status);
1365 break;
1366 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1367 break;
1368 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1369 break;
1370 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1371 dev_warn(&h->pdev->dev, "task management function rejected.\n");
1372 break;
1373 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1374 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1375 break;
1376 default:
1377 dev_warn(&h->pdev->dev,
1378 "%s: Unrecognized server response: 0x%02x\n",
1379 "HP SSD Smart Path", c2->error_data.serv_response);
1380 break;
1381 }
1382}
1383
1384static void process_ioaccel2_completion(struct ctlr_info *h,
1385 struct CommandList *c, struct scsi_cmnd *cmd,
1386 struct hpsa_scsi_dev_t *dev)
1387{
1388 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1389
1390 /* check for good status */
1391 if (likely(c2->error_data.serv_response == 0 &&
1392 c2->error_data.status == 0)) {
1393 cmd_free(h, c);
1394 cmd->scsi_done(cmd);
1395 return;
1396 }
1397
1398 /* Any RAID offload error results in retry which will use
1399 * the normal I/O path so the controller can handle whatever's
1400 * wrong.
1401 */
1402 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1403 c2->error_data.serv_response ==
1404 IOACCEL2_SERV_RESPONSE_FAILURE) {
1405 if (c2->error_data.status !=
1406 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1407 dev_warn(&h->pdev->dev,
1408 "%s: Error 0x%02x, Retrying on standard path.\n",
1409 "HP SSD Smart Path", c2->error_data.status);
1410 dev->offload_enabled = 0;
1411 cmd->result = DID_SOFT_ERROR << 16;
1412 cmd_free(h, c);
1413 cmd->scsi_done(cmd);
1414 return;
1415 }
1416 handle_ioaccel_mode2_error(h, c, cmd, c2);
1417 cmd_free(h, c);
1418 cmd->scsi_done(cmd);
1419}
1420
1fb011fb 1421static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1422{
1423 struct scsi_cmnd *cmd;
1424 struct ctlr_info *h;
1425 struct ErrorInfo *ei;
283b4a9b 1426 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1427
1428 unsigned char sense_key;
1429 unsigned char asc; /* additional sense code */
1430 unsigned char ascq; /* additional sense code qualifier */
db111e18 1431 unsigned long sense_data_size;
edd16368
SC		 1432
1433 ei = cp->err_info;
1434 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1435 h = cp->h;
283b4a9b 1436 dev = cmd->device->hostdata;
edd16368
SC		 1437
1438 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1439 if ((cp->cmd_type == CMD_SCSI) &&
1440 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1441 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1442
1443 cmd->result = (DID_OK << 16); /* host byte */
1444 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1445
1446 if (cp->cmd_type == CMD_IOACCEL2)
1447 return process_ioaccel2_completion(h, cp, cmd, dev);
1448
5512672f 1449 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1450
1451 /* copy the sense data whether we need to or not. */
db111e18
SC		 1452 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1453 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1454 else
1455 sense_data_size = sizeof(ei->SenseInfo);
1456 if (ei->SenseLen < sense_data_size)
1457 sense_data_size = ei->SenseLen;
1458
1459 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1460 scsi_set_resid(cmd, ei->ResidualCnt);
1461
1462 if (ei->CommandStatus == 0) {
edd16368 1463 cmd_free(h, cp);
2cc5bfaf 1464 cmd->scsi_done(cmd);
edd16368
SC		 1465 return;
1466 }
1467
e1f7de0c
MG		 1468 /* For I/O accelerator commands, copy over some fields to the normal
1469 * CISS header used below for error handling.
1470 */
1471 if (cp->cmd_type == CMD_IOACCEL1) {
1472 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1473 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1474 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1475 cp->Header.Tag.lower = c->Tag.lower;
1476 cp->Header.Tag.upper = c->Tag.upper;
1477 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1478 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1479
1480 /* Any RAID offload error results in retry which will use
1481 * the normal I/O path so the controller can handle whatever's
1482 * wrong.
1483 */
1484 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1485 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1486 dev->offload_enabled = 0;
1487 cmd->result = DID_SOFT_ERROR << 16;
1488 cmd_free(h, cp);
1489 cmd->scsi_done(cmd);
1490 return;
1491 }
e1f7de0c
MG		 1492 }
1493
edd16368
SC		 1494 /* an error has occurred */
1495 switch (ei->CommandStatus) {
1496
1497 case CMD_TARGET_STATUS:
1498 if (ei->ScsiStatus) {
1499 /* Get sense key */
1500 sense_key = 0xf & ei->SenseInfo[2];
1501 /* Get additional sense code */
1502 asc = ei->SenseInfo[12];
1503 /* Get addition sense code qualifier */
1504 ascq = ei->SenseInfo[13];
1505 }
1506
1507 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1508 if (check_for_unit_attention(h, cp))
edd16368 1509 break;
edd16368
SC		 1510 if (sense_key == ILLEGAL_REQUEST) {
1511 /*
1512 * SCSI REPORT_LUNS is commonly unsupported on
1513 * Smart Array. Suppress noisy complaint.
1514 */
1515 if (cp->Request.CDB[0] == REPORT_LUNS)
1516 break;
1517
1518 /* If ASC/ASCQ indicate Logical Unit
1519 * Not Supported condition,
1520 */
1521 if ((asc == 0x25) && (ascq == 0x0)) {
1522 dev_warn(&h->pdev->dev, "cp %p "
1523 "has check condition\n", cp);
1524 break;
1525 }
1526 }
1527
1528 if (sense_key == NOT_READY) {
1529 /* If Sense is Not Ready, Logical Unit
1530 * Not ready, Manual Intervention
1531 * required
1532 */
1533 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1534 dev_warn(&h->pdev->dev, "cp %p "
1535 "has check condition: unit "
1536 "not ready, manual "
1537 "intervention required\n", cp);
1538 break;
1539 }
1540 }
1d3b3609
MG		 1541 if (sense_key == ABORTED_COMMAND) {
1542 /* Aborted command is retryable */
1543 dev_warn(&h->pdev->dev, "cp %p "
1544 "has check condition: aborted command: "
1545 "ASC: 0x%x, ASCQ: 0x%x\n",
1546 cp, asc, ascq);
2e311fba 1547 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1548 break;
1549 }
edd16368 1550 /* Must be some other type of check condition */
21b8e4ef 1551 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1552 "unknown type: "
1553 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1554 "Returning result: 0x%x, "
1555 "cmd=[%02x %02x %02x %02x %02x "
807be732 1556 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1557 "%02x %02x %02x %02x %02x]\n",
1558 cp, sense_key, asc, ascq,
1559 cmd->result,
1560 cmd->cmnd[0], cmd->cmnd[1],
1561 cmd->cmnd[2], cmd->cmnd[3],
1562 cmd->cmnd[4], cmd->cmnd[5],
1563 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1564 cmd->cmnd[8], cmd->cmnd[9],
1565 cmd->cmnd[10], cmd->cmnd[11],
1566 cmd->cmnd[12], cmd->cmnd[13],
1567 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1568 break;
1569 }
1570
1571
1572 /* Problem was not a check condition
1573 * Pass it up to the upper layers...
1574 */
1575 if (ei->ScsiStatus) {
1576 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1577 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1578 "Returning result: 0x%x\n",
1579 cp, ei->ScsiStatus,
1580 sense_key, asc, ascq,
1581 cmd->result);
1582 } else { /* scsi status is zero??? How??? */
1583 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1584 "Returning no connection.\n", cp),
1585
1586 /* Ordinarily, this case should never happen,
1587 * but there is a bug in some released firmware
1588 * revisions that allows it to happen if, for
1589 * example, a 4100 backplane loses power and
1590 * the tape drive is in it. We assume that
1591 * it's a fatal error of some kind because we
1592 * can't show that it wasn't. We will make it
1593 * look like selection timeout since that is
1594 * the most common reason for this to occur,
1595 * and it's severe enough.
1596 */
1597
1598 cmd->result = DID_NO_CONNECT << 16;
1599 }
1600 break;
1601
1602 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1603 break;
1604 case CMD_DATA_OVERRUN:
1605 dev_warn(&h->pdev->dev, "cp %p has"
1606 " completed with data overrun "
1607 "reported\n", cp);
1608 break;
1609 case CMD_INVALID: {
1610 /* print_bytes(cp, sizeof(*cp), 1, 0);
1611 print_cmd(cp); */
1612 /* We get CMD_INVALID if you address a non-existent device
1613 * instead of a selection timeout (no response). You will
1614 * see this if you yank out a drive, then try to access it.
1615 * This is kind of a shame because it means that any other
1616 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1617 * missing target. */
1618 cmd->result = DID_NO_CONNECT << 16;
1619 }
1620 break;
1621 case CMD_PROTOCOL_ERR:
256d0eaa 1622 cmd->result = DID_ERROR << 16;
edd16368 1623 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1624 "protocol error\n", cp);
edd16368
SC		 1625 break;
1626 case CMD_HARDWARE_ERR:
1627 cmd->result = DID_ERROR << 16;
1628 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1629 break;
1630 case CMD_CONNECTION_LOST:
1631 cmd->result = DID_ERROR << 16;
1632 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1633 break;
1634 case CMD_ABORTED:
1635 cmd->result = DID_ABORT << 16;
1636 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1637 cp, ei->ScsiStatus);
1638 break;
1639 case CMD_ABORT_FAILED:
1640 cmd->result = DID_ERROR << 16;
1641 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1642 break;
1643 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1644 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1645 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1646 "abort\n", cp);
1647 break;
1648 case CMD_TIMEOUT:
1649 cmd->result = DID_TIME_OUT << 16;
1650 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1651 break;
1d5e2ed0
SC		 1652 case CMD_UNABORTABLE:
1653 cmd->result = DID_ERROR << 16;
1654 dev_warn(&h->pdev->dev, "Command unabortable\n");
1655 break;
283b4a9b
SC		 1656 case CMD_IOACCEL_DISABLED:
1657 /* This only handles the direct pass-through case since RAID
1658 * offload is handled above. Just attempt a retry.
1659 */
1660 cmd->result = DID_SOFT_ERROR << 16;
1661 dev_warn(&h->pdev->dev,
1662 "cp %p had HP SSD Smart Path error\n", cp);
1663 break;
edd16368
SC		 1664 default:
1665 cmd->result = DID_ERROR << 16;
1666 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1667 cp, ei->CommandStatus);
1668 }
edd16368 1669 cmd_free(h, cp);
2cc5bfaf 1670 cmd->scsi_done(cmd);
edd16368
SC		 1671}
1672
edd16368
SC		 1673static void hpsa_pci_unmap(struct pci_dev *pdev,
1674 struct CommandList *c, int sg_used, int data_direction)
1675{
1676 int i;
1677 union u64bit addr64;
1678
1679 for (i = 0; i < sg_used; i++) {
1680 addr64.val32.lower = c->SG[i].Addr.lower;
1681 addr64.val32.upper = c->SG[i].Addr.upper;
1682 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1683 data_direction);
1684 }
1685}
1686
a2dac136 1687static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1688 struct CommandList *cp,
1689 unsigned char *buf,
1690 size_t buflen,
1691 int data_direction)
1692{
01a02ffc 1693 u64 addr64;
edd16368
SC		 1694
1695 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1696 cp->Header.SGList = 0;
1697 cp->Header.SGTotal = 0;
a2dac136 1698 return 0;
edd16368
SC		 1699 }
1700
01a02ffc 1701 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1702 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1703 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1704 cp->Header.SGList = 0;
1705 cp->Header.SGTotal = 0;
a2dac136 1706 return -1;
eceaae18 1707 }
edd16368 1708 cp->SG[0].Addr.lower =
01a02ffc 1709 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1710 cp->SG[0].Addr.upper =
01a02ffc 1711 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1712 cp->SG[0].Len = buflen;
e1d9cbfa 1713 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1714 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1715 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1716 return 0;
edd16368
SC		 1717}
1718
1719static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1720 struct CommandList *c)
1721{
1722 DECLARE_COMPLETION_ONSTACK(wait);
1723
1724 c->waiting = &wait;
1725 enqueue_cmd_and_start_io(h, c);
1726 wait_for_completion(&wait);
1727}
1728
a0c12413
SC		 1729static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1730 struct CommandList *c)
1731{
1732 unsigned long flags;
1733
1734 /* If controller lockup detected, fake a hardware error. */
1735 spin_lock_irqsave(&h->lock, flags);
1736 if (unlikely(h->lockup_detected)) {
1737 spin_unlock_irqrestore(&h->lock, flags);
1738 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1739 } else {
1740 spin_unlock_irqrestore(&h->lock, flags);
1741 hpsa_scsi_do_simple_cmd_core(h, c);
1742 }
1743}
1744
9c2fc160 1745#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1746static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1747 struct CommandList *c, int data_direction)
1748{
9c2fc160 1749 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1750
1751 do {
7630abd0 1752 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1753 hpsa_scsi_do_simple_cmd_core(h, c);
1754 retry_count++;
9c2fc160
SC		 1755 if (retry_count > 3) {
1756 msleep(backoff_time);
1757 if (backoff_time < 1000)
1758 backoff_time *= 2;
1759 }
852af20a 1760 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1761 check_for_busy(h, c)) &&
1762 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1763 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1764}
1765
1766static void hpsa_scsi_interpret_error(struct CommandList *cp)
1767{
1768 struct ErrorInfo *ei;
1769 struct device *d = &cp->h->pdev->dev;
1770
1771 ei = cp->err_info;
1772 switch (ei->CommandStatus) {
1773 case CMD_TARGET_STATUS:
1774 dev_warn(d, "cmd %p has completed with errors\n", cp);
1775 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1776 ei->ScsiStatus);
1777 if (ei->ScsiStatus == 0)
1778 dev_warn(d, "SCSI status is abnormally zero. "
1779 "(probably indicates selection timeout "
1780 "reported incorrectly due to a known "
1781 "firmware bug, circa July, 2001.)\n");
1782 break;
1783 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1784 dev_info(d, "UNDERRUN\n");
1785 break;
1786 case CMD_DATA_OVERRUN:
1787 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1788 break;
1789 case CMD_INVALID: {
1790 /* controller unfortunately reports SCSI passthru's
1791 * to non-existent targets as invalid commands.
1792 */
1793 dev_warn(d, "cp %p is reported invalid (probably means "
1794 "target device no longer present)\n", cp);
1795 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1796 print_cmd(cp); */
1797 }
1798 break;
1799 case CMD_PROTOCOL_ERR:
1800 dev_warn(d, "cp %p has protocol error \n", cp);
1801 break;
1802 case CMD_HARDWARE_ERR:
1803 /* cmd->result = DID_ERROR << 16; */
1804 dev_warn(d, "cp %p had hardware error\n", cp);
1805 break;
1806 case CMD_CONNECTION_LOST:
1807 dev_warn(d, "cp %p had connection lost\n", cp);
1808 break;
1809 case CMD_ABORTED:
1810 dev_warn(d, "cp %p was aborted\n", cp);
1811 break;
1812 case CMD_ABORT_FAILED:
1813 dev_warn(d, "cp %p reports abort failed\n", cp);
1814 break;
1815 case CMD_UNSOLICITED_ABORT:
1816 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1817 break;
1818 case CMD_TIMEOUT:
1819 dev_warn(d, "cp %p timed out\n", cp);
1820 break;
1d5e2ed0
SC		 1821 case CMD_UNABORTABLE:
1822 dev_warn(d, "Command unabortable\n");
1823 break;
edd16368
SC		 1824 default:
1825 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1826 ei->CommandStatus);
1827 }
1828}
1829
1830static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1831 unsigned char page, unsigned char *buf,
1832 unsigned char bufsize)
1833{
1834 int rc = IO_OK;
1835 struct CommandList *c;
1836 struct ErrorInfo *ei;
1837
1838 c = cmd_special_alloc(h);
1839
1840 if (c == NULL) { /* trouble... */
1841 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1842 return -ENOMEM;
edd16368
SC		 1843 }
1844
a2dac136
SC		 1845 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1846 page, scsi3addr, TYPE_CMD)) {
1847 rc = -1;
1848 goto out;
1849 }
edd16368
SC		 1850 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1851 ei = c->err_info;
1852 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1853 hpsa_scsi_interpret_error(c);
1854 rc = -1;
1855 }
a2dac136 1856out:
edd16368
SC		 1857 cmd_special_free(h, c);
1858 return rc;
1859}
1860
1861static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr)
1862{
1863 int rc = IO_OK;
1864 struct CommandList *c;
1865 struct ErrorInfo *ei;
1866
1867 c = cmd_special_alloc(h);
1868
1869 if (c == NULL) { /* trouble... */
1870 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1871 return -ENOMEM;
edd16368
SC		 1872 }
1873
a2dac136
SC		 1874 /* fill_cmd can't fail here, no data buffer to map. */
1875 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h,
1876 NULL, 0, 0, scsi3addr, TYPE_MSG);
edd16368
SC		 1877 hpsa_scsi_do_simple_cmd_core(h, c);
1878 /* no unmap needed here because no data xfer. */
1879
1880 ei = c->err_info;
1881 if (ei->CommandStatus != 0) {
1882 hpsa_scsi_interpret_error(c);
1883 rc = -1;
1884 }
1885 cmd_special_free(h, c);
1886 return rc;
1887}
1888
1889static void hpsa_get_raid_level(struct ctlr_info *h,
1890 unsigned char *scsi3addr, unsigned char *raid_level)
1891{
1892 int rc;
1893 unsigned char *buf;
1894
1895 *raid_level = RAID_UNKNOWN;
1896 buf = kzalloc(64, GFP_KERNEL);
1897 if (!buf)
1898 return;
1899 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1900 if (rc == 0)
1901 *raid_level = buf[8];
1902 if (*raid_level > RAID_UNKNOWN)
1903 *raid_level = RAID_UNKNOWN;
1904 kfree(buf);
1905 return;
1906}
1907
283b4a9b
SC		 1908#define HPSA_MAP_DEBUG
1909#ifdef HPSA_MAP_DEBUG
1910static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1911 struct raid_map_data *map_buff)
1912{
1913 struct raid_map_disk_data *dd = &map_buff->data[0];
1914 int map, row, col;
1915 u16 map_cnt, row_cnt, disks_per_row;
1916
1917 if (rc != 0)
1918 return;
1919
1920 dev_info(&h->pdev->dev, "structure_size = %u\n",
1921 le32_to_cpu(map_buff->structure_size));
1922 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1923 le32_to_cpu(map_buff->volume_blk_size));
1924 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1925 le64_to_cpu(map_buff->volume_blk_cnt));
1926 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1927 map_buff->phys_blk_shift);
1928 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1929 map_buff->parity_rotation_shift);
1930 dev_info(&h->pdev->dev, "strip_size = %u\n",
1931 le16_to_cpu(map_buff->strip_size));
1932 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1933 le64_to_cpu(map_buff->disk_starting_blk));
1934 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1935 le64_to_cpu(map_buff->disk_blk_cnt));
1936 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1937 le16_to_cpu(map_buff->data_disks_per_row));
1938 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1939 le16_to_cpu(map_buff->metadata_disks_per_row));
1940 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1941 le16_to_cpu(map_buff->row_cnt));
1942 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1943 le16_to_cpu(map_buff->layout_map_count));
1944
1945 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1946 for (map = 0; map < map_cnt; map++) {
1947 dev_info(&h->pdev->dev, "Map%u:\n", map);
1948 row_cnt = le16_to_cpu(map_buff->row_cnt);
1949 for (row = 0; row < row_cnt; row++) {
1950 dev_info(&h->pdev->dev, " Row%u:\n", row);
1951 disks_per_row =
1952 le16_to_cpu(map_buff->data_disks_per_row);
1953 for (col = 0; col < disks_per_row; col++, dd++)
1954 dev_info(&h->pdev->dev,
1955 " D%02u: h=0x%04x xor=%u,%u\n",
1956 col, dd->ioaccel_handle,
1957 dd->xor_mult[0], dd->xor_mult[1]);
1958 disks_per_row =
1959 le16_to_cpu(map_buff->metadata_disks_per_row);
1960 for (col = 0; col < disks_per_row; col++, dd++)
1961 dev_info(&h->pdev->dev,
1962 " M%02u: h=0x%04x xor=%u,%u\n",
1963 col, dd->ioaccel_handle,
1964 dd->xor_mult[0], dd->xor_mult[1]);
1965 }
1966 }
1967}
1968#else
1969static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
1970 __attribute__((unused)) int rc,
1971 __attribute__((unused)) struct raid_map_data *map_buff)
1972{
1973}
1974#endif
1975
1976static int hpsa_get_raid_map(struct ctlr_info *h,
1977 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1978{
1979 int rc = 0;
1980 struct CommandList *c;
1981 struct ErrorInfo *ei;
1982
1983 c = cmd_special_alloc(h);
1984 if (c == NULL) {
1985 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1986 return -ENOMEM;
1987 }
1988 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
1989 sizeof(this_device->raid_map), 0,
1990 scsi3addr, TYPE_CMD)) {
1991 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
1992 cmd_special_free(h, c);
1993 return -ENOMEM;
1994 }
1995 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1996 ei = c->err_info;
1997 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1998 hpsa_scsi_interpret_error(c);
1999 cmd_special_free(h, c);
2000 return -1;
2001 }
2002 cmd_special_free(h, c);
2003
2004 /* @todo in the future, dynamically allocate RAID map memory */
2005 if (le32_to_cpu(this_device->raid_map.structure_size) >
2006 sizeof(this_device->raid_map)) {
2007 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2008 rc = -1;
2009 }
2010 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2011 return rc;
2012}
2013
2014static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2015 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2016{
2017 int rc;
2018 unsigned char *buf;
2019 u8 ioaccel_status;
2020
2021 this_device->offload_config = 0;
2022 this_device->offload_enabled = 0;
2023
2024 buf = kzalloc(64, GFP_KERNEL);
2025 if (!buf)
2026 return;
2027 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2028 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
2029 if (rc != 0)
2030 goto out;
2031
2032#define IOACCEL_STATUS_BYTE 4
2033#define OFFLOAD_CONFIGURED_BIT 0x01
2034#define OFFLOAD_ENABLED_BIT 0x02
2035 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2036 this_device->offload_config =
2037 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2038 if (this_device->offload_config) {
2039 this_device->offload_enabled =
2040 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2041 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2042 this_device->offload_enabled = 0;
2043 }
2044out:
2045 kfree(buf);
2046 return;
2047}
2048
edd16368
SC		 2049/* Get the device id from inquiry page 0x83 */
2050static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2051 unsigned char *device_id, int buflen)
2052{
2053 int rc;
2054 unsigned char *buf;
2055
2056 if (buflen > 16)
2057 buflen = 16;
2058 buf = kzalloc(64, GFP_KERNEL);
2059 if (!buf)
2060 return -1;
2061 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
2062 if (rc == 0)
2063 memcpy(device_id, &buf[8], buflen);
2064 kfree(buf);
2065 return rc != 0;
2066}
2067
2068static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2069 struct ReportLUNdata *buf, int bufsize,
2070 int extended_response)
2071{
2072 int rc = IO_OK;
2073 struct CommandList *c;
2074 unsigned char scsi3addr[8];
2075 struct ErrorInfo *ei;
2076
2077 c = cmd_special_alloc(h);
2078 if (c == NULL) { /* trouble... */
2079 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2080 return -1;
2081 }
e89c0ae7
SC		 2082 /* address the controller */
2083 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2084 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2085 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2086 rc = -1;
2087 goto out;
2088 }
edd16368
SC		 2089 if (extended_response)
2090 c->Request.CDB[1] = extended_response;
2091 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2092 ei = c->err_info;
2093 if (ei->CommandStatus != 0 &&
2094 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2095 hpsa_scsi_interpret_error(c);
2096 rc = -1;
283b4a9b
SC		 2097 } else {
2098 if (buf->extended_response_flag != extended_response) {
2099 dev_err(&h->pdev->dev,
2100 "report luns requested format %u, got %u\n",
2101 extended_response,
2102 buf->extended_response_flag);
2103 rc = -1;
2104 }
edd16368 2105 }
a2dac136 2106out:
edd16368
SC		 2107 cmd_special_free(h, c);
2108 return rc;
2109}
2110
2111static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2112 struct ReportLUNdata *buf,
2113 int bufsize, int extended_response)
2114{
2115 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2116}
2117
2118static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2119 struct ReportLUNdata *buf, int bufsize)
2120{
2121 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2122}
2123
2124static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2125 int bus, int target, int lun)
2126{
2127 device->bus = bus;
2128 device->target = target;
2129 device->lun = lun;
2130}
2131
2132static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2133 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2134 unsigned char *is_OBDR_device)
edd16368 2135{
0b0e1d6c
SC		 2136
2137#define OBDR_SIG_OFFSET 43
2138#define OBDR_TAPE_SIG "$DR-10"
2139#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2140#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2141
ea6d3bc3 2142 unsigned char *inq_buff;
0b0e1d6c 2143 unsigned char *obdr_sig;
edd16368 2144
ea6d3bc3 2145 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2146 if (!inq_buff)
2147 goto bail_out;
2148
edd16368
SC		 2149 /* Do an inquiry to the device to see what it is. */
2150 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2151 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2152 /* Inquiry failed (msg printed already) */
2153 dev_err(&h->pdev->dev,
2154 "hpsa_update_device_info: inquiry failed\n");
2155 goto bail_out;
2156 }
2157
edd16368
SC		 2158 this_device->devtype = (inq_buff[0] & 0x1f);
2159 memcpy(this_device->scsi3addr, scsi3addr, 8);
2160 memcpy(this_device->vendor, &inq_buff[8],
2161 sizeof(this_device->vendor));
2162 memcpy(this_device->model, &inq_buff[16],
2163 sizeof(this_device->model));
edd16368
SC		 2164 memset(this_device->device_id, 0,
2165 sizeof(this_device->device_id));
2166 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2167 sizeof(this_device->device_id));
2168
2169 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2170 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2171 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2172 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2173 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2174 } else {
edd16368 2175 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2176 this_device->offload_config = 0;
2177 this_device->offload_enabled = 0;
2178 }
edd16368 2179
0b0e1d6c
SC		 2180 if (is_OBDR_device) {
2181 /* See if this is a One-Button-Disaster-Recovery device
2182 * by looking for "$DR-10" at offset 43 in inquiry data.
2183 */
2184 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2185 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2186 strncmp(obdr_sig, OBDR_TAPE_SIG,
2187 OBDR_SIG_LEN) == 0);
2188 }
2189
edd16368
SC		 2190 kfree(inq_buff);
2191 return 0;
2192
2193bail_out:
2194 kfree(inq_buff);
2195 return 1;
2196}
2197
4f4eb9f1 2198static unsigned char *ext_target_model[] = {
edd16368
SC		 2199 "MSA2012",
2200 "MSA2024",
2201 "MSA2312",
2202 "MSA2324",
fda38518 2203 "P2000 G3 SAS",
e06c8e5c 2204 "MSA 2040 SAS",
edd16368
SC		 2205 NULL,
2206};
2207
4f4eb9f1 2208static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2209{
2210 int i;
2211
4f4eb9f1
ST		 2212 for (i = 0; ext_target_model[i]; i++)
2213 if (strncmp(device->model, ext_target_model[i],
2214 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2215 return 1;
2216 return 0;
2217}
2218
2219/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2220 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2221 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2222 * Logical drive target and lun are assigned at this time, but
2223 * physical device lun and target assignment are deferred (assigned
2224 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2225 */
2226static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2227 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2228{
1f310bde
SC		 2229 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2230
2231 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2232 /* physical device, target and lun filled in later */
edd16368 2233 if (is_hba_lunid(lunaddrbytes))
1f310bde 2234 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2235 else
1f310bde
SC		 2236 /* defer target, lun assignment for physical devices */
2237 hpsa_set_bus_target_lun(device, 2, -1, -1);
2238 return;
2239 }
2240 /* It's a logical device */
4f4eb9f1
ST		 2241 if (is_ext_target(h, device)) {
2242 /* external target way, put logicals on bus 1
1f310bde
SC		 2243 * and match target/lun numbers box
2244 * reports, other smart array, bus 0, target 0, match lunid
2245 */
2246 hpsa_set_bus_target_lun(device,
2247 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2248 return;
edd16368 2249 }
1f310bde 2250 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2251}
2252
2253/*
2254 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2255 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2256 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2257 * it for some reason. *tmpdevice is the target we're adding,
2258 * this_device is a pointer into the current element of currentsd[]
2259 * that we're building up in update_scsi_devices(), below.
2260 * lunzerobits is a bitmap that tracks which targets already have a
2261 * lun 0 assigned.
2262 * Returns 1 if an enclosure was added, 0 if not.
2263 */
4f4eb9f1 2264static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2265 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2266 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2267 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2268{
2269 unsigned char scsi3addr[8];
2270
1f310bde 2271 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2272 return 0; /* There is already a lun 0 on this target. */
2273
2274 if (!is_logical_dev_addr_mode(lunaddrbytes))
2275 return 0; /* It's the logical targets that may lack lun 0. */
2276
4f4eb9f1
ST		 2277 if (!is_ext_target(h, tmpdevice))
2278 return 0; /* Only external target devices have this problem. */
edd16368 2279
1f310bde 2280 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2281 return 0;
2282
c4f8a299 2283 memset(scsi3addr, 0, 8);
1f310bde 2284 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2285 if (is_hba_lunid(scsi3addr))
2286 return 0; /* Don't add the RAID controller here. */
2287
339b2b14
SC		 2288 if (is_scsi_rev_5(h))
2289 return 0; /* p1210m doesn't need to do this. */
2290
4f4eb9f1 2291 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2292 dev_warn(&h->pdev->dev, "Maximum number of external "
2293 "target devices exceeded. Check your hardware "
edd16368
SC		 2294 "configuration.");
2295 return 0;
2296 }
2297
0b0e1d6c 2298 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2299 return 0;
4f4eb9f1 2300 (*n_ext_target_devs)++;
1f310bde
SC		 2301 hpsa_set_bus_target_lun(this_device,
2302 tmpdevice->bus, tmpdevice->target, 0);
2303 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2304 return 1;
2305}
2306
2307/*
2308 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2309 * logdev. The number of luns in physdev and logdev are returned in
2310 * *nphysicals and *nlogicals, respectively.
2311 * Returns 0 on success, -1 otherwise.
2312 */
2313static int hpsa_gather_lun_info(struct ctlr_info *h,
2314 int reportlunsize,
283b4a9b 2315 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2316 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2317{
283b4a9b
SC		 2318 int physical_entry_size = 8;
2319
2320 *physical_mode = 0;
2321
2322 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2323 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2324 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2325 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2326 physical_entry_size = 24;
2327 }
a93aa1fe 2328 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2329 *physical_mode)) {
edd16368
SC		 2330 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2331 return -1;
2332 }
283b4a9b
SC		 2333 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2334 physical_entry_size;
edd16368
SC		 2335 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2336 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2337 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2338 *nphysicals - HPSA_MAX_PHYS_LUN);
2339 *nphysicals = HPSA_MAX_PHYS_LUN;
2340 }
2341 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2342 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2343 return -1;
2344 }
6df1e954 2345 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2346 /* Reject Logicals in excess of our max capability. */
2347 if (*nlogicals > HPSA_MAX_LUN) {
2348 dev_warn(&h->pdev->dev,
2349 "maximum logical LUNs (%d) exceeded. "
2350 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2351 *nlogicals - HPSA_MAX_LUN);
2352 *nlogicals = HPSA_MAX_LUN;
2353 }
2354 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2355 dev_warn(&h->pdev->dev,
2356 "maximum logical + physical LUNs (%d) exceeded. "
2357 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2358 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2359 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2360 }
2361 return 0;
2362}
2363
339b2b14 2364u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2365 int nphysicals, int nlogicals,
2366 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2367 struct ReportLUNdata *logdev_list)
2368{
2369 /* Helper function, figure out where the LUN ID info is coming from
2370 * given index i, lists of physical and logical devices, where in
2371 * the list the raid controller is supposed to appear (first or last)
2372 */
2373
2374 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2375 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2376
2377 if (i == raid_ctlr_position)
2378 return RAID_CTLR_LUNID;
2379
2380 if (i < logicals_start)
2381 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2382
2383 if (i < last_device)
2384 return &logdev_list->LUN[i - nphysicals -
2385 (raid_ctlr_position == 0)][0];
2386 BUG();
2387 return NULL;
2388}
2389
edd16368
SC		 2390static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2391{
2392 /* the idea here is we could get notified
2393 * that some devices have changed, so we do a report
2394 * physical luns and report logical luns cmd, and adjust
2395 * our list of devices accordingly.
2396 *
2397 * The scsi3addr's of devices won't change so long as the
2398 * adapter is not reset. That means we can rescan and
2399 * tell which devices we already know about, vs. new
2400 * devices, vs. disappearing devices.
2401 */
a93aa1fe 2402 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2403 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2404 u32 nphysicals = 0;
2405 u32 nlogicals = 0;
283b4a9b 2406 int physical_mode = 0;
01a02ffc 2407 u32 ndev_allocated = 0;
edd16368
SC		 2408 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2409 int ncurrent = 0;
283b4a9b 2410 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2411 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2412 int raid_ctlr_position;
aca4a520 2413 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2414
cfe5badc 2415 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2416 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2417 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2418 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2419
0b0e1d6c 2420 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2421 dev_err(&h->pdev->dev, "out of memory\n");
2422 goto out;
2423 }
2424 memset(lunzerobits, 0, sizeof(lunzerobits));
2425
a93aa1fe
MG		 2426 if (hpsa_gather_lun_info(h, reportlunsize,
2427 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2428 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2429 goto out;
2430
aca4a520
ST		 2431 /* We might see up to the maximum number of logical and physical disks
2432 * plus external target devices, and a device for the local RAID
2433 * controller.
edd16368 2434 */
aca4a520 2435 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2436
2437 /* Allocate the per device structures */
2438 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2439 if (i >= HPSA_MAX_DEVICES) {
2440 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2441 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2442 ndevs_to_allocate - HPSA_MAX_DEVICES);
2443 break;
2444 }
2445
edd16368
SC		 2446 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2447 if (!currentsd[i]) {
2448 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2449 __FILE__, __LINE__);
2450 goto out;
2451 }
2452 ndev_allocated++;
2453 }
2454
339b2b14
SC		 2455 if (unlikely(is_scsi_rev_5(h)))
2456 raid_ctlr_position = 0;
2457 else
2458 raid_ctlr_position = nphysicals + nlogicals;
2459
edd16368 2460 /* adjust our table of devices */
4f4eb9f1 2461 n_ext_target_devs = 0;
edd16368 2462 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2463 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2464
2465 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2466 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2467 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2468 /* skip masked physical devices. */
339b2b14
SC		 2469 if (lunaddrbytes[3] & 0xC0 &&
2470 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2471 continue;
2472
2473 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2474 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2475 &is_OBDR))
edd16368 2476 continue; /* skip it if we can't talk to it. */
1f310bde 2477 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2478 this_device = currentsd[ncurrent];
2479
2480 /*
4f4eb9f1 2481 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2482 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2483 * is nonetheless an enclosure device there. We have to
2484 * present that otherwise linux won't find anything if
2485 * there is no lun 0.
2486 */
4f4eb9f1 2487 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2488 lunaddrbytes, lunzerobits,
4f4eb9f1 2489 &n_ext_target_devs)) {
edd16368
SC		 2490 ncurrent++;
2491 this_device = currentsd[ncurrent];
2492 }
2493
2494 *this_device = *tmpdevice;
edd16368
SC		 2495
2496 switch (this_device->devtype) {
0b0e1d6c 2497 case TYPE_ROM:
edd16368
SC		 2498 /* We don't *really* support actual CD-ROM devices,
2499 * just "One Button Disaster Recovery" tape drive
2500 * which temporarily pretends to be a CD-ROM drive.
2501 * So we check that the device is really an OBDR tape
2502 * device by checking for "$DR-10" in bytes 43-48 of
2503 * the inquiry data.
2504 */
0b0e1d6c
SC		 2505 if (is_OBDR)
2506 ncurrent++;
edd16368
SC		 2507 break;
2508 case TYPE_DISK:
283b4a9b
SC		 2509 if (i >= nphysicals) {
2510 ncurrent++;
edd16368 2511 break;
283b4a9b
SC		 2512 }
2513 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2514 memcpy(&this_device->ioaccel_handle,
2515 &lunaddrbytes[20],
2516 sizeof(this_device->ioaccel_handle));
2517 ncurrent++;
2518 }
edd16368
SC		 2519 break;
2520 case TYPE_TAPE:
2521 case TYPE_MEDIUM_CHANGER:
2522 ncurrent++;
2523 break;
2524 case TYPE_RAID:
2525 /* Only present the Smartarray HBA as a RAID controller.
2526 * If it's a RAID controller other than the HBA itself
2527 * (an external RAID controller, MSA500 or similar)
2528 * don't present it.
2529 */
2530 if (!is_hba_lunid(lunaddrbytes))
2531 break;
2532 ncurrent++;
2533 break;
2534 default:
2535 break;
2536 }
cfe5badc 2537 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2538 break;
2539 }
2540 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2541out:
2542 kfree(tmpdevice);
2543 for (i = 0; i < ndev_allocated; i++)
2544 kfree(currentsd[i]);
2545 kfree(currentsd);
edd16368
SC		 2546 kfree(physdev_list);
2547 kfree(logdev_list);
edd16368
SC		 2548}
2549
2550/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2551 * dma mapping and fills in the scatter gather entries of the
2552 * hpsa command, cp.
2553 */
33a2ffce 2554static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2555 struct CommandList *cp,
2556 struct scsi_cmnd *cmd)
2557{
2558 unsigned int len;
2559 struct scatterlist *sg;
01a02ffc 2560 u64 addr64;
33a2ffce
SC		 2561 int use_sg, i, sg_index, chained;
2562 struct SGDescriptor *curr_sg;
edd16368 2563
33a2ffce 2564 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2565
2566 use_sg = scsi_dma_map(cmd);
2567 if (use_sg < 0)
2568 return use_sg;
2569
2570 if (!use_sg)
2571 goto sglist_finished;
2572
33a2ffce
SC		 2573 curr_sg = cp->SG;
2574 chained = 0;
2575 sg_index = 0;
edd16368 2576 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2577 if (i == h->max_cmd_sg_entries - 1 &&
2578 use_sg > h->max_cmd_sg_entries) {
2579 chained = 1;
2580 curr_sg = h->cmd_sg_list[cp->cmdindex];
2581 sg_index = 0;
2582 }
01a02ffc 2583 addr64 = (u64) sg_dma_address(sg);
edd16368 2584 len = sg_dma_len(sg);
33a2ffce
SC		 2585 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2586 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2587 curr_sg->Len = len;
e1d9cbfa 2588 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2589 curr_sg++;
2590 }
2591
2592 if (use_sg + chained > h->maxSG)
2593 h->maxSG = use_sg + chained;
2594
2595 if (chained) {
2596 cp->Header.SGList = h->max_cmd_sg_entries;
2597 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2598 if (hpsa_map_sg_chain_block(h, cp)) {
2599 scsi_dma_unmap(cmd);
2600 return -1;
2601 }
33a2ffce 2602 return 0;
edd16368
SC		 2603 }
2604
2605sglist_finished:
2606
01a02ffc
SC		 2607 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2608 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2609 return 0;
2610}
2611
283b4a9b
SC		 2612#define IO_ACCEL_INELIGIBLE (1)
2613static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2614{
2615 int is_write = 0;
2616 u32 block;
2617 u32 block_cnt;
2618
2619 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2620 switch (cdb[0]) {
2621 case WRITE_6:
2622 case WRITE_12:
2623 is_write = 1;
2624 case READ_6:
2625 case READ_12:
2626 if (*cdb_len == 6) {
2627 block = (((u32) cdb[2]) << 8) | cdb[3];
2628 block_cnt = cdb[4];
2629 } else {
2630 BUG_ON(*cdb_len != 12);
2631 block = (((u32) cdb[2]) << 24) |
2632 (((u32) cdb[3]) << 16) |
2633 (((u32) cdb[4]) << 8) |
2634 cdb[5];
2635 block_cnt =
2636 (((u32) cdb[6]) << 24) |
2637 (((u32) cdb[7]) << 16) |
2638 (((u32) cdb[8]) << 8) |
2639 cdb[9];
2640 }
2641 if (block_cnt > 0xffff)
2642 return IO_ACCEL_INELIGIBLE;
2643
2644 cdb[0] = is_write ? WRITE_10 : READ_10;
2645 cdb[1] = 0;
2646 cdb[2] = (u8) (block >> 24);
2647 cdb[3] = (u8) (block >> 16);
2648 cdb[4] = (u8) (block >> 8);
2649 cdb[5] = (u8) (block);
2650 cdb[6] = 0;
2651 cdb[7] = (u8) (block_cnt >> 8);
2652 cdb[8] = (u8) (block_cnt);
2653 cdb[9] = 0;
2654 *cdb_len = 10;
2655 break;
2656 }
2657 return 0;
2658}
2659
c349775e 2660static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2661 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2662 u8 *scsi3addr)
e1f7de0c
MG		 2663{
2664 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2665 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2666 unsigned int len;
2667 unsigned int total_len = 0;
2668 struct scatterlist *sg;
2669 u64 addr64;
2670 int use_sg, i;
2671 struct SGDescriptor *curr_sg;
2672 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2673
283b4a9b
SC		 2674 /* TODO: implement chaining support */
2675 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2676 return IO_ACCEL_INELIGIBLE;
2677
e1f7de0c
MG		 2678 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2679
283b4a9b
SC		 2680 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2681 return IO_ACCEL_INELIGIBLE;
2682
e1f7de0c
MG		 2683 c->cmd_type = CMD_IOACCEL1;
2684
2685 /* Adjust the DMA address to point to the accelerated command buffer */
2686 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2687 (c->cmdindex * sizeof(*cp));
2688 BUG_ON(c->busaddr & 0x0000007F);
2689
2690 use_sg = scsi_dma_map(cmd);
2691 if (use_sg < 0)
2692 return use_sg;
2693
2694 if (use_sg) {
2695 curr_sg = cp->SG;
2696 scsi_for_each_sg(cmd, sg, use_sg, i) {
2697 addr64 = (u64) sg_dma_address(sg);
2698 len = sg_dma_len(sg);
2699 total_len += len;
2700 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2701 curr_sg->Addr.upper =
2702 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2703 curr_sg->Len = len;
2704
2705 if (i == (scsi_sg_count(cmd) - 1))
2706 curr_sg->Ext = HPSA_SG_LAST;
2707 else
2708 curr_sg->Ext = 0; /* we are not chaining */
2709 curr_sg++;
2710 }
2711
2712 switch (cmd->sc_data_direction) {
2713 case DMA_TO_DEVICE:
2714 control |= IOACCEL1_CONTROL_DATA_OUT;
2715 break;
2716 case DMA_FROM_DEVICE:
2717 control |= IOACCEL1_CONTROL_DATA_IN;
2718 break;
2719 case DMA_NONE:
2720 control |= IOACCEL1_CONTROL_NODATAXFER;
2721 break;
2722 default:
2723 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2724 cmd->sc_data_direction);
2725 BUG();
2726 break;
2727 }
2728 } else {
2729 control |= IOACCEL1_CONTROL_NODATAXFER;
2730 }
2731
c349775e 2732 c->Header.SGList = use_sg;
e1f7de0c 2733 /* Fill out the command structure to submit */
283b4a9b 2734 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2735 cp->transfer_len = total_len;
2736 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2737 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2738 cp->control = control;
283b4a9b
SC		 2739 memcpy(cp->CDB, cdb, cdb_len);
2740 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2741 /* Tag was already set at init time. */
283b4a9b 2742 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2743 return 0;
2744}
edd16368 2745
283b4a9b
SC		 2746/*
2747 * Queue a command directly to a device behind the controller using the
2748 * I/O accelerator path.
2749 */
2750static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2751 struct CommandList *c)
2752{
2753 struct scsi_cmnd *cmd = c->scsi_cmd;
2754 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2755
2756 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2757 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2758}
2759
c349775e
ST		 2760static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
2761 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2762 u8 *scsi3addr)
2763{
2764 struct scsi_cmnd *cmd = c->scsi_cmd;
2765 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
2766 struct ioaccel2_sg_element *curr_sg;
2767 int use_sg, i;
2768 struct scatterlist *sg;
2769 u64 addr64;
2770 u32 len;
2771 u32 total_len = 0;
2772
2773 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2774 return IO_ACCEL_INELIGIBLE;
2775
2776 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2777 return IO_ACCEL_INELIGIBLE;
2778 c->cmd_type = CMD_IOACCEL2;
2779 /* Adjust the DMA address to point to the accelerated command buffer */
2780 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
2781 (c->cmdindex * sizeof(*cp));
2782 BUG_ON(c->busaddr & 0x0000007F);
2783
2784 memset(cp, 0, sizeof(*cp));
2785 cp->IU_type = IOACCEL2_IU_TYPE;
2786
2787 use_sg = scsi_dma_map(cmd);
2788 if (use_sg < 0)
2789 return use_sg;
2790
2791 if (use_sg) {
2792 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
2793 curr_sg = cp->sg;
2794 scsi_for_each_sg(cmd, sg, use_sg, i) {
2795 addr64 = (u64) sg_dma_address(sg);
2796 len = sg_dma_len(sg);
2797 total_len += len;
2798 curr_sg->address = cpu_to_le64(addr64);
2799 curr_sg->length = cpu_to_le32(len);
2800 curr_sg->reserved[0] = 0;
2801 curr_sg->reserved[1] = 0;
2802 curr_sg->reserved[2] = 0;
2803 curr_sg->chain_indicator = 0;
2804 curr_sg++;
2805 }
2806
2807 switch (cmd->sc_data_direction) {
2808 case DMA_TO_DEVICE:
2809 cp->direction = IOACCEL2_DIR_DATA_OUT;
2810 break;
2811 case DMA_FROM_DEVICE:
2812 cp->direction = IOACCEL2_DIR_DATA_IN;
2813 break;
2814 case DMA_NONE:
2815 cp->direction = IOACCEL2_DIR_NO_DATA;
2816 break;
2817 default:
2818 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2819 cmd->sc_data_direction);
2820 BUG();
2821 break;
2822 }
2823 } else {
2824 cp->direction = IOACCEL2_DIR_NO_DATA;
2825 }
2826 cp->scsi_nexus = ioaccel_handle;
2827 cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
2828 DIRECT_LOOKUP_BIT;
2829 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
2830 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
2831 cp->cmd_priority_task_attr = 0;
2832
2833 /* fill in sg elements */
2834 cp->sg_count = (u8) use_sg;
2835
2836 cp->data_len = cpu_to_le32(total_len);
2837 cp->err_ptr = cpu_to_le64(c->busaddr +
2838 offsetof(struct io_accel2_cmd, error_data));
2839 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
2840
2841 enqueue_cmd_and_start_io(h, c);
2842 return 0;
2843}
2844
2845/*
2846 * Queue a command to the correct I/O accelerator path.
2847 */
2848static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
2849 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2850 u8 *scsi3addr)
2851{
2852 if (h->transMethod & CFGTBL_Trans_io_accel1)
2853 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
2854 cdb, cdb_len, scsi3addr);
2855 else
2856 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
2857 cdb, cdb_len, scsi3addr);
2858}
2859
283b4a9b
SC		 2860/*
2861 * Attempt to perform offload RAID mapping for a logical volume I/O.
2862 */
2863static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
2864 struct CommandList *c)
2865{
2866 struct scsi_cmnd *cmd = c->scsi_cmd;
2867 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2868 struct raid_map_data *map = &dev->raid_map;
2869 struct raid_map_disk_data *dd = &map->data[0];
2870 int is_write = 0;
2871 u32 map_index;
2872 u64 first_block, last_block;
2873 u32 block_cnt;
2874 u32 blocks_per_row;
2875 u64 first_row, last_row;
2876 u32 first_row_offset, last_row_offset;
2877 u32 first_column, last_column;
2878 u32 map_row;
2879 u32 disk_handle;
2880 u64 disk_block;
2881 u32 disk_block_cnt;
2882 u8 cdb[16];
2883 u8 cdb_len;
2884#if BITS_PER_LONG == 32
2885 u64 tmpdiv;
2886#endif
2887
2888 BUG_ON(!(dev->offload_config && dev->offload_enabled));
2889
2890 /* check for valid opcode, get LBA and block count */
2891 switch (cmd->cmnd[0]) {
2892 case WRITE_6:
2893 is_write = 1;
2894 case READ_6:
2895 first_block =
2896 (((u64) cmd->cmnd[2]) << 8) |
2897 cmd->cmnd[3];
2898 block_cnt = cmd->cmnd[4];
2899 break;
2900 case WRITE_10:
2901 is_write = 1;
2902 case READ_10:
2903 first_block =
2904 (((u64) cmd->cmnd[2]) << 24) |
2905 (((u64) cmd->cmnd[3]) << 16) |
2906 (((u64) cmd->cmnd[4]) << 8) |
2907 cmd->cmnd[5];
2908 block_cnt =
2909 (((u32) cmd->cmnd[7]) << 8) |
2910 cmd->cmnd[8];
2911 break;
2912 case WRITE_12:
2913 is_write = 1;
2914 case READ_12:
2915 first_block =
2916 (((u64) cmd->cmnd[2]) << 24) |
2917 (((u64) cmd->cmnd[3]) << 16) |
2918 (((u64) cmd->cmnd[4]) << 8) |
2919 cmd->cmnd[5];
2920 block_cnt =
2921 (((u32) cmd->cmnd[6]) << 24) |
2922 (((u32) cmd->cmnd[7]) << 16) |
2923 (((u32) cmd->cmnd[8]) << 8) |
2924 cmd->cmnd[9];
2925 break;
2926 case WRITE_16:
2927 is_write = 1;
2928 case READ_16:
2929 first_block =
2930 (((u64) cmd->cmnd[2]) << 56) |
2931 (((u64) cmd->cmnd[3]) << 48) |
2932 (((u64) cmd->cmnd[4]) << 40) |
2933 (((u64) cmd->cmnd[5]) << 32) |
2934 (((u64) cmd->cmnd[6]) << 24) |
2935 (((u64) cmd->cmnd[7]) << 16) |
2936 (((u64) cmd->cmnd[8]) << 8) |
2937 cmd->cmnd[9];
2938 block_cnt =
2939 (((u32) cmd->cmnd[10]) << 24) |
2940 (((u32) cmd->cmnd[11]) << 16) |
2941 (((u32) cmd->cmnd[12]) << 8) |
2942 cmd->cmnd[13];
2943 break;
2944 default:
2945 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
2946 }
2947 BUG_ON(block_cnt == 0);
2948 last_block = first_block + block_cnt - 1;
2949
2950 /* check for write to non-RAID-0 */
2951 if (is_write && dev->raid_level != 0)
2952 return IO_ACCEL_INELIGIBLE;
2953
2954 /* check for invalid block or wraparound */
2955 if (last_block >= map->volume_blk_cnt || last_block < first_block)
2956 return IO_ACCEL_INELIGIBLE;
2957
2958 /* calculate stripe information for the request */
2959 blocks_per_row = map->data_disks_per_row * map->strip_size;
2960#if BITS_PER_LONG == 32
2961 tmpdiv = first_block;
2962 (void) do_div(tmpdiv, blocks_per_row);
2963 first_row = tmpdiv;
2964 tmpdiv = last_block;
2965 (void) do_div(tmpdiv, blocks_per_row);
2966 last_row = tmpdiv;
2967 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2968 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2969 tmpdiv = first_row_offset;
2970 (void) do_div(tmpdiv, map->strip_size);
2971 first_column = tmpdiv;
2972 tmpdiv = last_row_offset;
2973 (void) do_div(tmpdiv, map->strip_size);
2974 last_column = tmpdiv;
2975#else
2976 first_row = first_block / blocks_per_row;
2977 last_row = last_block / blocks_per_row;
2978 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
2979 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2980 first_column = first_row_offset / map->strip_size;
2981 last_column = last_row_offset / map->strip_size;
2982#endif
2983
2984 /* if this isn't a single row/column then give to the controller */
2985 if ((first_row != last_row) || (first_column != last_column))
2986 return IO_ACCEL_INELIGIBLE;
2987
2988 /* proceeding with driver mapping */
2989 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2990 map->row_cnt;
2991 map_index = (map_row * (map->data_disks_per_row +
2992 map->metadata_disks_per_row)) + first_column;
2993 if (dev->raid_level == 2) {
2994 /* simple round-robin balancing of RAID 1+0 reads across
2995 * primary and mirror members. this is appropriate for SSD
2996 * but not optimal for HDD.
2997 */
2998 if (dev->offload_to_mirror)
2999 map_index += map->data_disks_per_row;
3000 dev->offload_to_mirror = !dev->offload_to_mirror;
3001 }
3002 disk_handle = dd[map_index].ioaccel_handle;
3003 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3004 (first_row_offset - (first_column * map->strip_size));
3005 disk_block_cnt = block_cnt;
3006
3007 /* handle differing logical/physical block sizes */
3008 if (map->phys_blk_shift) {
3009 disk_block <<= map->phys_blk_shift;
3010 disk_block_cnt <<= map->phys_blk_shift;
3011 }
3012 BUG_ON(disk_block_cnt > 0xffff);
3013
3014 /* build the new CDB for the physical disk I/O */
3015 if (disk_block > 0xffffffff) {
3016 cdb[0] = is_write ? WRITE_16 : READ_16;
3017 cdb[1] = 0;
3018 cdb[2] = (u8) (disk_block >> 56);
3019 cdb[3] = (u8) (disk_block >> 48);
3020 cdb[4] = (u8) (disk_block >> 40);
3021 cdb[5] = (u8) (disk_block >> 32);
3022 cdb[6] = (u8) (disk_block >> 24);
3023 cdb[7] = (u8) (disk_block >> 16);
3024 cdb[8] = (u8) (disk_block >> 8);
3025 cdb[9] = (u8) (disk_block);
3026 cdb[10] = (u8) (disk_block_cnt >> 24);
3027 cdb[11] = (u8) (disk_block_cnt >> 16);
3028 cdb[12] = (u8) (disk_block_cnt >> 8);
3029 cdb[13] = (u8) (disk_block_cnt);
3030 cdb[14] = 0;
3031 cdb[15] = 0;
3032 cdb_len = 16;
3033 } else {
3034 cdb[0] = is_write ? WRITE_10 : READ_10;
3035 cdb[1] = 0;
3036 cdb[2] = (u8) (disk_block >> 24);
3037 cdb[3] = (u8) (disk_block >> 16);
3038 cdb[4] = (u8) (disk_block >> 8);
3039 cdb[5] = (u8) (disk_block);
3040 cdb[6] = 0;
3041 cdb[7] = (u8) (disk_block_cnt >> 8);
3042 cdb[8] = (u8) (disk_block_cnt);
3043 cdb[9] = 0;
3044 cdb_len = 10;
3045 }
3046 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3047 dev->scsi3addr);
3048}
3049
f281233d 3050static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3051 void (*done)(struct scsi_cmnd *))
3052{
3053 struct ctlr_info *h;
3054 struct hpsa_scsi_dev_t *dev;
3055 unsigned char scsi3addr[8];
3056 struct CommandList *c;
3057 unsigned long flags;
283b4a9b 3058 int rc = 0;
edd16368
SC		 3059
3060 /* Get the ptr to our adapter structure out of cmd->host. */
3061 h = sdev_to_hba(cmd->device);
3062 dev = cmd->device->hostdata;
3063 if (!dev) {
3064 cmd->result = DID_NO_CONNECT << 16;
3065 done(cmd);
3066 return 0;
3067 }
3068 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3069
edd16368 3070 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3071 if (unlikely(h->lockup_detected)) {
3072 spin_unlock_irqrestore(&h->lock, flags);
3073 cmd->result = DID_ERROR << 16;
3074 done(cmd);
3075 return 0;
3076 }
edd16368 3077 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3078 c = cmd_alloc(h);
edd16368
SC		 3079 if (c == NULL) { /* trouble... */
3080 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3081 return SCSI_MLQUEUE_HOST_BUSY;
3082 }
3083
3084 /* Fill in the command list header */
3085
3086 cmd->scsi_done = done; /* save this for use by completion code */
3087
3088 /* save c in case we have to abort it */
3089 cmd->host_scribble = (unsigned char *) c;
3090
3091 c->cmd_type = CMD_SCSI;
3092 c->scsi_cmd = cmd;
e1f7de0c 3093
283b4a9b
SC		 3094 /* Call alternate submit routine for I/O accelerated commands.
3095 * Retries always go down the normal I/O path.
3096 */
3097 if (likely(cmd->retries == 0 &&
3098 cmd->request->cmd_type == REQ_TYPE_FS)) {
3099 if (dev->offload_enabled) {
3100 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3101 if (rc == 0)
3102 return 0; /* Sent on ioaccel path */
3103 if (rc < 0) { /* scsi_dma_map failed. */
3104 cmd_free(h, c);
3105 return SCSI_MLQUEUE_HOST_BUSY;
3106 }
3107 } else if (dev->ioaccel_handle) {
3108 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3109 if (rc == 0)
3110 return 0; /* Sent on direct map path */
3111 if (rc < 0) { /* scsi_dma_map failed. */
3112 cmd_free(h, c);
3113 return SCSI_MLQUEUE_HOST_BUSY;
3114 }
3115 }
3116 }
e1f7de0c 3117
edd16368
SC		 3118 c->Header.ReplyQueue = 0; /* unused in simple mode */
3119 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3120 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3121 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3122
3123 /* Fill in the request block... */
3124
3125 c->Request.Timeout = 0;
3126 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3127 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3128 c->Request.CDBLen = cmd->cmd_len;
3129 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3130 c->Request.Type.Type = TYPE_CMD;
3131 c->Request.Type.Attribute = ATTR_SIMPLE;
3132 switch (cmd->sc_data_direction) {
3133 case DMA_TO_DEVICE:
3134 c->Request.Type.Direction = XFER_WRITE;
3135 break;
3136 case DMA_FROM_DEVICE:
3137 c->Request.Type.Direction = XFER_READ;
3138 break;
3139 case DMA_NONE:
3140 c->Request.Type.Direction = XFER_NONE;
3141 break;
3142 case DMA_BIDIRECTIONAL:
3143 /* This can happen if a buggy application does a scsi passthru
3144 * and sets both inlen and outlen to non-zero. ( see
3145 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3146 */
3147
3148 c->Request.Type.Direction = XFER_RSVD;
3149 /* This is technically wrong, and hpsa controllers should
3150 * reject it with CMD_INVALID, which is the most correct
3151 * response, but non-fibre backends appear to let it
3152 * slide by, and give the same results as if this field
3153 * were set correctly. Either way is acceptable for
3154 * our purposes here.
3155 */
3156
3157 break;
3158
3159 default:
3160 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3161 cmd->sc_data_direction);
3162 BUG();
3163 break;
3164 }
3165
33a2ffce 3166 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3167 cmd_free(h, c);
3168 return SCSI_MLQUEUE_HOST_BUSY;
3169 }
3170 enqueue_cmd_and_start_io(h, c);
3171 /* the cmd'll come back via intr handler in complete_scsi_command() */
3172 return 0;
3173}
3174
f281233d
JG		 3175static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3176
5f389360
SC		 3177static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3178{
3179 unsigned long flags;
3180
3181 /*
3182 * Don't let rescans be initiated on a controller known
3183 * to be locked up. If the controller locks up *during*
3184 * a rescan, that thread is probably hosed, but at least
3185 * we can prevent new rescan threads from piling up on a
3186 * locked up controller.
3187 */
3188 spin_lock_irqsave(&h->lock, flags);
3189 if (unlikely(h->lockup_detected)) {
3190 spin_unlock_irqrestore(&h->lock, flags);
3191 spin_lock_irqsave(&h->scan_lock, flags);
3192 h->scan_finished = 1;
3193 wake_up_all(&h->scan_wait_queue);
3194 spin_unlock_irqrestore(&h->scan_lock, flags);
3195 return 1;
3196 }
3197 spin_unlock_irqrestore(&h->lock, flags);
3198 return 0;
3199}
3200
a08a8471
SC		 3201static void hpsa_scan_start(struct Scsi_Host *sh)
3202{
3203 struct ctlr_info *h = shost_to_hba(sh);
3204 unsigned long flags;
3205
5f389360
SC		 3206 if (do_not_scan_if_controller_locked_up(h))
3207 return;
3208
a08a8471
SC		 3209 /* wait until any scan already in progress is finished. */
3210 while (1) {
3211 spin_lock_irqsave(&h->scan_lock, flags);
3212 if (h->scan_finished)
3213 break;
3214 spin_unlock_irqrestore(&h->scan_lock, flags);
3215 wait_event(h->scan_wait_queue, h->scan_finished);
3216 /* Note: We don't need to worry about a race between this
3217 * thread and driver unload because the midlayer will
3218 * have incremented the reference count, so unload won't
3219 * happen if we're in here.
3220 */
3221 }
3222 h->scan_finished = 0; /* mark scan as in progress */
3223 spin_unlock_irqrestore(&h->scan_lock, flags);
3224
5f389360
SC		 3225 if (do_not_scan_if_controller_locked_up(h))
3226 return;
3227
a08a8471
SC		 3228 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3229
3230 spin_lock_irqsave(&h->scan_lock, flags);
3231 h->scan_finished = 1; /* mark scan as finished. */
3232 wake_up_all(&h->scan_wait_queue);
3233 spin_unlock_irqrestore(&h->scan_lock, flags);
3234}
3235
3236static int hpsa_scan_finished(struct Scsi_Host *sh,
3237 unsigned long elapsed_time)
3238{
3239 struct ctlr_info *h = shost_to_hba(sh);
3240 unsigned long flags;
3241 int finished;
3242
3243 spin_lock_irqsave(&h->scan_lock, flags);
3244 finished = h->scan_finished;
3245 spin_unlock_irqrestore(&h->scan_lock, flags);
3246 return finished;
3247}
3248
667e23d4
SC		 3249static int hpsa_change_queue_depth(struct scsi_device *sdev,
3250 int qdepth, int reason)
3251{
3252 struct ctlr_info *h = sdev_to_hba(sdev);
3253
3254 if (reason != SCSI_QDEPTH_DEFAULT)
3255 return -ENOTSUPP;
3256
3257 if (qdepth < 1)
3258 qdepth = 1;
3259 else
3260 if (qdepth > h->nr_cmds)
3261 qdepth = h->nr_cmds;
3262 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3263 return sdev->queue_depth;
3264}
3265
edd16368
SC		 3266static void hpsa_unregister_scsi(struct ctlr_info *h)
3267{
3268 /* we are being forcibly unloaded, and may not refuse. */
3269 scsi_remove_host(h->scsi_host);
3270 scsi_host_put(h->scsi_host);
3271 h->scsi_host = NULL;
3272}
3273
3274static int hpsa_register_scsi(struct ctlr_info *h)
3275{
b705690d
SC		 3276 struct Scsi_Host *sh;
3277 int error;
edd16368 3278
b705690d
SC		 3279 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3280 if (sh == NULL)
3281 goto fail;
3282
3283 sh->io_port = 0;
3284 sh->n_io_port = 0;
3285 sh->this_id = -1;
3286 sh->max_channel = 3;
3287 sh->max_cmd_len = MAX_COMMAND_SIZE;
3288 sh->max_lun = HPSA_MAX_LUN;
3289 sh->max_id = HPSA_MAX_LUN;
3290 sh->can_queue = h->nr_cmds;
3291 sh->cmd_per_lun = h->nr_cmds;
3292 sh->sg_tablesize = h->maxsgentries;
3293 h->scsi_host = sh;
3294 sh->hostdata[0] = (unsigned long) h;
3295 sh->irq = h->intr[h->intr_mode];
3296 sh->unique_id = sh->irq;
3297 error = scsi_add_host(sh, &h->pdev->dev);
3298 if (error)
3299 goto fail_host_put;
3300 scsi_scan_host(sh);
3301 return 0;
3302
3303 fail_host_put:
3304 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3305 " failed for controller %d\n", __func__, h->ctlr);
3306 scsi_host_put(sh);
3307 return error;
3308 fail:
3309 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3310 " failed for controller %d\n", __func__, h->ctlr);
3311 return -ENOMEM;
edd16368
SC		 3312}
3313
3314static int wait_for_device_to_become_ready(struct ctlr_info *h,
3315 unsigned char lunaddr[])
3316{
3317 int rc = 0;
3318 int count = 0;
3319 int waittime = 1; /* seconds */
3320 struct CommandList *c;
3321
3322 c = cmd_special_alloc(h);
3323 if (!c) {
3324 dev_warn(&h->pdev->dev, "out of memory in "
3325 "wait_for_device_to_become_ready.\n");
3326 return IO_ERROR;
3327 }
3328
3329 /* Send test unit ready until device ready, or give up. */
3330 while (count < HPSA_TUR_RETRY_LIMIT) {
3331
3332 /* Wait for a bit. do this first, because if we send
3333 * the TUR right away, the reset will just abort it.
3334 */
3335 msleep(1000 * waittime);
3336 count++;
3337
3338 /* Increase wait time with each try, up to a point. */
3339 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3340 waittime = waittime * 2;
3341
a2dac136
SC		 3342 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3343 (void) fill_cmd(c, TEST_UNIT_READY, h,
3344 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3345 hpsa_scsi_do_simple_cmd_core(h, c);
3346 /* no unmap needed here because no data xfer. */
3347
3348 if (c->err_info->CommandStatus == CMD_SUCCESS)
3349 break;
3350
3351 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3352 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3353 (c->err_info->SenseInfo[2] == NO_SENSE ||
3354 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3355 break;
3356
3357 dev_warn(&h->pdev->dev, "waiting %d secs "
3358 "for device to become ready.\n", waittime);
3359 rc = 1; /* device not ready. */
3360 }
3361
3362 if (rc)
3363 dev_warn(&h->pdev->dev, "giving up on device.\n");
3364 else
3365 dev_warn(&h->pdev->dev, "device is ready.\n");
3366
3367 cmd_special_free(h, c);
3368 return rc;
3369}
3370
3371/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3372 * complaining. Doing a host- or bus-reset can't do anything good here.
3373 */
3374static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3375{
3376 int rc;
3377 struct ctlr_info *h;
3378 struct hpsa_scsi_dev_t *dev;
3379
3380 /* find the controller to which the command to be aborted was sent */
3381 h = sdev_to_hba(scsicmd->device);
3382 if (h == NULL) /* paranoia */
3383 return FAILED;
edd16368
SC		 3384 dev = scsicmd->device->hostdata;
3385 if (!dev) {
3386 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3387 "device lookup failed.\n");
3388 return FAILED;
3389 }
d416b0c7
SC		 3390 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3391 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 3392 /* send a reset to the SCSI LUN which the command was sent to */
3393 rc = hpsa_send_reset(h, dev->scsi3addr);
3394 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3395 return SUCCESS;
3396
3397 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3398 return FAILED;
3399}
3400
6cba3f19
SC		 3401static void swizzle_abort_tag(u8 *tag)
3402{
3403 u8 original_tag[8];
3404
3405 memcpy(original_tag, tag, 8);
3406 tag[0] = original_tag[3];
3407 tag[1] = original_tag[2];
3408 tag[2] = original_tag[1];
3409 tag[3] = original_tag[0];
3410 tag[4] = original_tag[7];
3411 tag[5] = original_tag[6];
3412 tag[6] = original_tag[5];
3413 tag[7] = original_tag[4];
3414}
3415
17eb87d2
ST		 3416static void hpsa_get_tag(struct ctlr_info *h,
3417 struct CommandList *c, u32 *taglower, u32 *tagupper)
3418{
3419 if (c->cmd_type == CMD_IOACCEL1) {
3420 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3421 &h->ioaccel_cmd_pool[c->cmdindex];
3422 *tagupper = cm1->Tag.upper;
3423 *taglower = cm1->Tag.lower;
3424 } else {
3425 *tagupper = c->Header.Tag.upper;
3426 *taglower = c->Header.Tag.lower;
3427 }
3428}
3429
75167d2c 3430static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3431 struct CommandList *abort, int swizzle)
75167d2c
SC		 3432{
3433 int rc = IO_OK;
3434 struct CommandList *c;
3435 struct ErrorInfo *ei;
17eb87d2 3436 u32 tagupper, taglower;
75167d2c
SC		 3437
3438 c = cmd_special_alloc(h);
3439 if (c == NULL) { /* trouble... */
3440 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3441 return -ENOMEM;
3442 }
3443
a2dac136
SC		 3444 /* fill_cmd can't fail here, no buffer to map */
3445 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3446 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3447 if (swizzle)
3448 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3449 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3450 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3451 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3452 __func__, tagupper, taglower);
75167d2c
SC		 3453 /* no unmap needed here because no data xfer. */
3454
3455 ei = c->err_info;
3456 switch (ei->CommandStatus) {
3457 case CMD_SUCCESS:
3458 break;
3459 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3460 rc = -1;
3461 break;
3462 default:
3463 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3464 __func__, tagupper, taglower);
75167d2c
SC		 3465 hpsa_scsi_interpret_error(c);
3466 rc = -1;
3467 break;
3468 }
3469 cmd_special_free(h, c);
3470 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3471 abort->Header.Tag.upper, abort->Header.Tag.lower);
3472 return rc;
3473}
3474
3475/*
3476 * hpsa_find_cmd_in_queue
3477 *
3478 * Used to determine whether a command (find) is still present
3479 * in queue_head. Optionally excludes the last element of queue_head.
3480 *
3481 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3482 * not yet been submitted, and so can be aborted by the driver without
3483 * sending an abort to the hardware.
3484 *
3485 * Returns pointer to command if found in queue, NULL otherwise.
3486 */
3487static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3488 struct scsi_cmnd *find, struct list_head *queue_head)
3489{
3490 unsigned long flags;
3491 struct CommandList *c = NULL; /* ptr into cmpQ */
3492
3493 if (!find)
3494 return 0;
3495 spin_lock_irqsave(&h->lock, flags);
3496 list_for_each_entry(c, queue_head, list) {
3497 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3498 continue;
3499 if (c->scsi_cmd == find) {
3500 spin_unlock_irqrestore(&h->lock, flags);
3501 return c;
3502 }
3503 }
3504 spin_unlock_irqrestore(&h->lock, flags);
3505 return NULL;
3506}
3507
6cba3f19
SC		 3508static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3509 u8 *tag, struct list_head *queue_head)
3510{
3511 unsigned long flags;
3512 struct CommandList *c;
3513
3514 spin_lock_irqsave(&h->lock, flags);
3515 list_for_each_entry(c, queue_head, list) {
3516 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3517 continue;
3518 spin_unlock_irqrestore(&h->lock, flags);
3519 return c;
3520 }
3521 spin_unlock_irqrestore(&h->lock, flags);
3522 return NULL;
3523}
3524
3525/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3526 * tell which kind we're dealing with, so we send the abort both ways. There
3527 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3528 * way we construct our tags but we check anyway in case the assumptions which
3529 * make this true someday become false.
3530 */
3531static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3532 unsigned char *scsi3addr, struct CommandList *abort)
3533{
3534 u8 swizzled_tag[8];
3535 struct CommandList *c;
3536 int rc = 0, rc2 = 0;
3537
3538 /* we do not expect to find the swizzled tag in our queue, but
3539 * check anyway just to be sure the assumptions which make this
3540 * the case haven't become wrong.
3541 */
3542 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3543 swizzle_abort_tag(swizzled_tag);
3544 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3545 if (c != NULL) {
3546 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3547 return hpsa_send_abort(h, scsi3addr, abort, 0);
3548 }
3549 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3550
3551 /* if the command is still in our queue, we can't conclude that it was
3552 * aborted (it might have just completed normally) but in any case
3553 * we don't need to try to abort it another way.
3554 */
3555 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3556 if (c)
3557 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3558 return rc && rc2;
3559}
3560
75167d2c
SC		 3561/* Send an abort for the specified command.
3562 * If the device and controller support it,
3563 * send a task abort request.
3564 */
3565static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3566{
3567
3568 int i, rc;
3569 struct ctlr_info *h;
3570 struct hpsa_scsi_dev_t *dev;
3571 struct CommandList *abort; /* pointer to command to be aborted */
3572 struct CommandList *found;
3573 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3574 char msg[256]; /* For debug messaging. */
3575 int ml = 0;
17eb87d2 3576 u32 tagupper, taglower;
75167d2c
SC		 3577
3578 /* Find the controller of the command to be aborted */
3579 h = sdev_to_hba(sc->device);
3580 if (WARN(h == NULL,
3581 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3582 return FAILED;
3583
3584 /* Check that controller supports some kind of task abort */
3585 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3586 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3587 return FAILED;
3588
3589 memset(msg, 0, sizeof(msg));
3590 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3591 h->scsi_host->host_no, sc->device->channel,
3592 sc->device->id, sc->device->lun);
3593
3594 /* Find the device of the command to be aborted */
3595 dev = sc->device->hostdata;
3596 if (!dev) {
3597 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3598 msg);
3599 return FAILED;
3600 }
3601
3602 /* Get SCSI command to be aborted */
3603 abort = (struct CommandList *) sc->host_scribble;
3604 if (abort == NULL) {
3605 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3606 msg);
3607 return FAILED;
3608 }
17eb87d2
ST		 3609 hpsa_get_tag(h, abort, &taglower, &tagupper);
3610 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3611 as = (struct scsi_cmnd *) abort->scsi_cmd;
3612 if (as != NULL)
3613 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3614 as->cmnd[0], as->serial_number);
3615 dev_dbg(&h->pdev->dev, "%s\n", msg);
3616 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3617 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3618
3619 /* Search reqQ to See if command is queued but not submitted,
3620 * if so, complete the command with aborted status and remove
3621 * it from the reqQ.
3622 */
3623 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3624 if (found) {
3625 found->err_info->CommandStatus = CMD_ABORTED;
3626 finish_cmd(found);
3627 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3628 msg);
3629 return SUCCESS;
3630 }
3631
3632 /* not in reqQ, if also not in cmpQ, must have already completed */
3633 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3634 if (!found) {
d6ebd0f7 3635 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 3636 msg);
3637 return SUCCESS;
3638 }
3639
3640 /*
3641 * Command is in flight, or possibly already completed
3642 * by the firmware (but not to the scsi mid layer) but we can't
3643 * distinguish which. Send the abort down.
3644 */
6cba3f19 3645 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 3646 if (rc != 0) {
3647 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
3648 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
3649 h->scsi_host->host_no,
3650 dev->bus, dev->target, dev->lun);
3651 return FAILED;
3652 }
3653 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
3654
3655 /* If the abort(s) above completed and actually aborted the
3656 * command, then the command to be aborted should already be
3657 * completed. If not, wait around a bit more to see if they
3658 * manage to complete normally.
3659 */
3660#define ABORT_COMPLETE_WAIT_SECS 30
3661 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
3662 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3663 if (!found)
3664 return SUCCESS;
3665 msleep(100);
3666 }
3667 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
3668 msg, ABORT_COMPLETE_WAIT_SECS);
3669 return FAILED;
3670}
3671
3672
edd16368
SC		 3673/*
3674 * For operations that cannot sleep, a command block is allocated at init,
3675 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
3676 * which ones are free or in use. Lock must be held when calling this.
3677 * cmd_free() is the complement.
3678 */
3679static struct CommandList *cmd_alloc(struct ctlr_info *h)
3680{
3681 struct CommandList *c;
3682 int i;
3683 union u64bit temp64;
3684 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 3685 unsigned long flags;
edd16368 3686
e16a33ad 3687 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3688 do {
3689 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 3690 if (i == h->nr_cmds) {
3691 spin_unlock_irqrestore(&h->lock, flags);
edd16368 3692 return NULL;
e16a33ad 3693 }
edd16368
SC		 3694 } while (test_and_set_bit
3695 (i & (BITS_PER_LONG - 1),
3696 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 3697 spin_unlock_irqrestore(&h->lock, flags);
3698
edd16368
SC		 3699 c = h->cmd_pool + i;
3700 memset(c, 0, sizeof(*c));
3701 cmd_dma_handle = h->cmd_pool_dhandle
3702 + i * sizeof(*c);
3703 c->err_info = h->errinfo_pool + i;
3704 memset(c->err_info, 0, sizeof(*c->err_info));
3705 err_dma_handle = h->errinfo_pool_dhandle
3706 + i * sizeof(*c->err_info);
edd16368
SC		 3707
3708 c->cmdindex = i;
3709
9e0fc764 3710 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3711 c->busaddr = (u32) cmd_dma_handle;
3712 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3713 c->ErrDesc.Addr.lower = temp64.val32.lower;
3714 c->ErrDesc.Addr.upper = temp64.val32.upper;
3715 c->ErrDesc.Len = sizeof(*c->err_info);
3716
3717 c->h = h;
3718 return c;
3719}
3720
3721/* For operations that can wait for kmalloc to possibly sleep,
3722 * this routine can be called. Lock need not be held to call
3723 * cmd_special_alloc. cmd_special_free() is the complement.
3724 */
3725static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
3726{
3727 struct CommandList *c;
3728 union u64bit temp64;
3729 dma_addr_t cmd_dma_handle, err_dma_handle;
3730
3731 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
3732 if (c == NULL)
3733 return NULL;
3734 memset(c, 0, sizeof(*c));
3735
e1f7de0c 3736 c->cmd_type = CMD_SCSI;
edd16368
SC		 3737 c->cmdindex = -1;
3738
3739 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
3740 &err_dma_handle);
3741
3742 if (c->err_info == NULL) {
3743 pci_free_consistent(h->pdev,
3744 sizeof(*c), c, cmd_dma_handle);
3745 return NULL;
3746 }
3747 memset(c->err_info, 0, sizeof(*c->err_info));
3748
9e0fc764 3749 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 3750 c->busaddr = (u32) cmd_dma_handle;
3751 temp64.val = (u64) err_dma_handle;
edd16368
SC		 3752 c->ErrDesc.Addr.lower = temp64.val32.lower;
3753 c->ErrDesc.Addr.upper = temp64.val32.upper;
3754 c->ErrDesc.Len = sizeof(*c->err_info);
3755
3756 c->h = h;
3757 return c;
3758}
3759
3760static void cmd_free(struct ctlr_info *h, struct CommandList *c)
3761{
3762 int i;
e16a33ad 3763 unsigned long flags;
edd16368
SC		 3764
3765 i = c - h->cmd_pool;
e16a33ad 3766 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 3767 clear_bit(i & (BITS_PER_LONG - 1),
3768 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 3769 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 3770}
3771
3772static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
3773{
3774 union u64bit temp64;
3775
3776 temp64.val32.lower = c->ErrDesc.Addr.lower;
3777 temp64.val32.upper = c->ErrDesc.Addr.upper;
3778 pci_free_consistent(h->pdev, sizeof(*c->err_info),
3779 c->err_info, (dma_addr_t) temp64.val);
3780 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 3781 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 3782}
3783
3784#ifdef CONFIG_COMPAT
3785
edd16368
SC		 3786static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
3787{
3788 IOCTL32_Command_struct __user *arg32 =
3789 (IOCTL32_Command_struct __user *) arg;
3790 IOCTL_Command_struct arg64;
3791 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
3792 int err;
3793 u32 cp;
3794
938abd84 3795 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3796 err = 0;
3797 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3798 sizeof(arg64.LUN_info));
3799 err |= copy_from_user(&arg64.Request, &arg32->Request,
3800 sizeof(arg64.Request));
3801 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3802 sizeof(arg64.error_info));
3803 err |= get_user(arg64.buf_size, &arg32->buf_size);
3804 err |= get_user(cp, &arg32->buf);
3805 arg64.buf = compat_ptr(cp);
3806 err |= copy_to_user(p, &arg64, sizeof(arg64));
3807
3808 if (err)
3809 return -EFAULT;
3810
e39eeaed 3811 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 3812 if (err)
3813 return err;
3814 err |= copy_in_user(&arg32->error_info, &p->error_info,
3815 sizeof(arg32->error_info));
3816 if (err)
3817 return -EFAULT;
3818 return err;
3819}
3820
3821static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
3822 int cmd, void *arg)
3823{
3824 BIG_IOCTL32_Command_struct __user *arg32 =
3825 (BIG_IOCTL32_Command_struct __user *) arg;
3826 BIG_IOCTL_Command_struct arg64;
3827 BIG_IOCTL_Command_struct __user *p =
3828 compat_alloc_user_space(sizeof(arg64));
3829 int err;
3830 u32 cp;
3831
938abd84 3832 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 3833 err = 0;
3834 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
3835 sizeof(arg64.LUN_info));
3836 err |= copy_from_user(&arg64.Request, &arg32->Request,
3837 sizeof(arg64.Request));
3838 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
3839 sizeof(arg64.error_info));
3840 err |= get_user(arg64.buf_size, &arg32->buf_size);
3841 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
3842 err |= get_user(cp, &arg32->buf);
3843 arg64.buf = compat_ptr(cp);
3844 err |= copy_to_user(p, &arg64, sizeof(arg64));
3845
3846 if (err)
3847 return -EFAULT;
3848
e39eeaed 3849 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 3850 if (err)
3851 return err;
3852 err |= copy_in_user(&arg32->error_info, &p->error_info,
3853 sizeof(arg32->error_info));
3854 if (err)
3855 return -EFAULT;
3856 return err;
3857}
71fe75a7
SC		 3858
3859static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
3860{
3861 switch (cmd) {
3862 case CCISS_GETPCIINFO:
3863 case CCISS_GETINTINFO:
3864 case CCISS_SETINTINFO:
3865 case CCISS_GETNODENAME:
3866 case CCISS_SETNODENAME:
3867 case CCISS_GETHEARTBEAT:
3868 case CCISS_GETBUSTYPES:
3869 case CCISS_GETFIRMVER:
3870 case CCISS_GETDRIVVER:
3871 case CCISS_REVALIDVOLS:
3872 case CCISS_DEREGDISK:
3873 case CCISS_REGNEWDISK:
3874 case CCISS_REGNEWD:
3875 case CCISS_RESCANDISK:
3876 case CCISS_GETLUNINFO:
3877 return hpsa_ioctl(dev, cmd, arg);
3878
3879 case CCISS_PASSTHRU32:
3880 return hpsa_ioctl32_passthru(dev, cmd, arg);
3881 case CCISS_BIG_PASSTHRU32:
3882 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
3883
3884 default:
3885 return -ENOIOCTLCMD;
3886 }
3887}
edd16368
SC		 3888#endif
3889
3890static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
3891{
3892 struct hpsa_pci_info pciinfo;
3893
3894 if (!argp)
3895 return -EINVAL;
3896 pciinfo.domain = pci_domain_nr(h->pdev->bus);
3897 pciinfo.bus = h->pdev->bus->number;
3898 pciinfo.dev_fn = h->pdev->devfn;
3899 pciinfo.board_id = h->board_id;
3900 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
3901 return -EFAULT;
3902 return 0;
3903}
3904
3905static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
3906{
3907 DriverVer_type DriverVer;
3908 unsigned char vmaj, vmin, vsubmin;
3909 int rc;
3910
3911 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
3912 &vmaj, &vmin, &vsubmin);
3913 if (rc != 3) {
3914 dev_info(&h->pdev->dev, "driver version string '%s' "
3915 "unrecognized.", HPSA_DRIVER_VERSION);
3916 vmaj = 0;
3917 vmin = 0;
3918 vsubmin = 0;
3919 }
3920 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
3921 if (!argp)
3922 return -EINVAL;
3923 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
3924 return -EFAULT;
3925 return 0;
3926}
3927
3928static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
3929{
3930 IOCTL_Command_struct iocommand;
3931 struct CommandList *c;
3932 char *buff = NULL;
3933 union u64bit temp64;
c1f63c8f 3934 int rc = 0;
edd16368
SC		 3935
3936 if (!argp)
3937 return -EINVAL;
3938 if (!capable(CAP_SYS_RAWIO))
3939 return -EPERM;
3940 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
3941 return -EFAULT;
3942 if ((iocommand.buf_size < 1) &&
3943 (iocommand.Request.Type.Direction != XFER_NONE)) {
3944 return -EINVAL;
3945 }
3946 if (iocommand.buf_size > 0) {
3947 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
3948 if (buff == NULL)
3949 return -EFAULT;
b03a7771
SC		 3950 if (iocommand.Request.Type.Direction == XFER_WRITE) {
3951 /* Copy the data into the buffer we created */
3952 if (copy_from_user(buff, iocommand.buf,
3953 iocommand.buf_size)) {
c1f63c8f
SC		 3954 rc = -EFAULT;
3955 goto out_kfree;
b03a7771
SC		 3956 }
3957 } else {
3958 memset(buff, 0, iocommand.buf_size);
edd16368 3959 }
b03a7771 3960 }
edd16368
SC		 3961 c = cmd_special_alloc(h);
3962 if (c == NULL) {
c1f63c8f
SC		 3963 rc = -ENOMEM;
3964 goto out_kfree;
edd16368
SC		 3965 }
3966 /* Fill in the command type */
3967 c->cmd_type = CMD_IOCTL_PEND;
3968 /* Fill in Command Header */
3969 c->Header.ReplyQueue = 0; /* unused in simple mode */
3970 if (iocommand.buf_size > 0) { /* buffer to fill */
3971 c->Header.SGList = 1;
3972 c->Header.SGTotal = 1;
3973 } else { /* no buffers to fill */
3974 c->Header.SGList = 0;
3975 c->Header.SGTotal = 0;
3976 }
3977 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
3978 /* use the kernel address the cmd block for tag */
3979 c->Header.Tag.lower = c->busaddr;
3980
3981 /* Fill in Request block */
3982 memcpy(&c->Request, &iocommand.Request,
3983 sizeof(c->Request));
3984
3985 /* Fill in the scatter gather information */
3986 if (iocommand.buf_size > 0) {
3987 temp64.val = pci_map_single(h->pdev, buff,
3988 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 3989 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
3990 c->SG[0].Addr.lower = 0;
3991 c->SG[0].Addr.upper = 0;
3992 c->SG[0].Len = 0;
3993 rc = -ENOMEM;
3994 goto out;
3995 }
edd16368
SC		 3996 c->SG[0].Addr.lower = temp64.val32.lower;
3997 c->SG[0].Addr.upper = temp64.val32.upper;
3998 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 3999 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4000 }
a0c12413 4001 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4002 if (iocommand.buf_size > 0)
4003 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4004 check_ioctl_unit_attention(h, c);
4005
4006 /* Copy the error information out */
4007 memcpy(&iocommand.error_info, c->err_info,
4008 sizeof(iocommand.error_info));
4009 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4010 rc = -EFAULT;
4011 goto out;
edd16368 4012 }
b03a7771
SC		 4013 if (iocommand.Request.Type.Direction == XFER_READ &&
4014 iocommand.buf_size > 0) {
edd16368
SC		 4015 /* Copy the data out of the buffer we created */
4016 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4017 rc = -EFAULT;
4018 goto out;
edd16368
SC		 4019 }
4020 }
c1f63c8f 4021out:
edd16368 4022 cmd_special_free(h, c);
c1f63c8f
SC		 4023out_kfree:
4024 kfree(buff);
4025 return rc;
edd16368
SC		 4026}
4027
4028static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4029{
4030 BIG_IOCTL_Command_struct *ioc;
4031 struct CommandList *c;
4032 unsigned char **buff = NULL;
4033 int *buff_size = NULL;
4034 union u64bit temp64;
4035 BYTE sg_used = 0;
4036 int status = 0;
4037 int i;
01a02ffc
SC		 4038 u32 left;
4039 u32 sz;
edd16368
SC		 4040 BYTE __user *data_ptr;
4041
4042 if (!argp)
4043 return -EINVAL;
4044 if (!capable(CAP_SYS_RAWIO))
4045 return -EPERM;
4046 ioc = (BIG_IOCTL_Command_struct *)
4047 kmalloc(sizeof(*ioc), GFP_KERNEL);
4048 if (!ioc) {
4049 status = -ENOMEM;
4050 goto cleanup1;
4051 }
4052 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4053 status = -EFAULT;
4054 goto cleanup1;
4055 }
4056 if ((ioc->buf_size < 1) &&
4057 (ioc->Request.Type.Direction != XFER_NONE)) {
4058 status = -EINVAL;
4059 goto cleanup1;
4060 }
4061 /* Check kmalloc limits using all SGs */
4062 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4063 status = -EINVAL;
4064 goto cleanup1;
4065 }
d66ae08b 4066 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4067 status = -EINVAL;
4068 goto cleanup1;
4069 }
d66ae08b 4070 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4071 if (!buff) {
4072 status = -ENOMEM;
4073 goto cleanup1;
4074 }
d66ae08b 4075 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4076 if (!buff_size) {
4077 status = -ENOMEM;
4078 goto cleanup1;
4079 }
4080 left = ioc->buf_size;
4081 data_ptr = ioc->buf;
4082 while (left) {
4083 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4084 buff_size[sg_used] = sz;
4085 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4086 if (buff[sg_used] == NULL) {
4087 status = -ENOMEM;
4088 goto cleanup1;
4089 }
4090 if (ioc->Request.Type.Direction == XFER_WRITE) {
4091 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4092 status = -ENOMEM;
4093 goto cleanup1;
4094 }
4095 } else
4096 memset(buff[sg_used], 0, sz);
4097 left -= sz;
4098 data_ptr += sz;
4099 sg_used++;
4100 }
4101 c = cmd_special_alloc(h);
4102 if (c == NULL) {
4103 status = -ENOMEM;
4104 goto cleanup1;
4105 }
4106 c->cmd_type = CMD_IOCTL_PEND;
4107 c->Header.ReplyQueue = 0;
b03a7771 4108 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4109 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4110 c->Header.Tag.lower = c->busaddr;
4111 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4112 if (ioc->buf_size > 0) {
4113 int i;
4114 for (i = 0; i < sg_used; i++) {
4115 temp64.val = pci_map_single(h->pdev, buff[i],
4116 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4117 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4118 c->SG[i].Addr.lower = 0;
4119 c->SG[i].Addr.upper = 0;
4120 c->SG[i].Len = 0;
4121 hpsa_pci_unmap(h->pdev, c, i,
4122 PCI_DMA_BIDIRECTIONAL);
4123 status = -ENOMEM;
e2d4a1f6 4124 goto cleanup0;
bcc48ffa 4125 }
edd16368
SC		 4126 c->SG[i].Addr.lower = temp64.val32.lower;
4127 c->SG[i].Addr.upper = temp64.val32.upper;
4128 c->SG[i].Len = buff_size[i];
e1d9cbfa 4129 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4130 }
4131 }
a0c12413 4132 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4133 if (sg_used)
4134 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4135 check_ioctl_unit_attention(h, c);
4136 /* Copy the error information out */
4137 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4138 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4139 status = -EFAULT;
e2d4a1f6 4140 goto cleanup0;
edd16368 4141 }
b03a7771 4142 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4143 /* Copy the data out of the buffer we created */
4144 BYTE __user *ptr = ioc->buf;
4145 for (i = 0; i < sg_used; i++) {
4146 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4147 status = -EFAULT;
e2d4a1f6 4148 goto cleanup0;
edd16368
SC		 4149 }
4150 ptr += buff_size[i];
4151 }
4152 }
edd16368 4153 status = 0;
e2d4a1f6
SC		 4154cleanup0:
4155 cmd_special_free(h, c);
edd16368
SC		 4156cleanup1:
4157 if (buff) {
4158 for (i = 0; i < sg_used; i++)
4159 kfree(buff[i]);
4160 kfree(buff);
4161 }
4162 kfree(buff_size);
4163 kfree(ioc);
4164 return status;
4165}
4166
4167static void check_ioctl_unit_attention(struct ctlr_info *h,
4168 struct CommandList *c)
4169{
4170 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4171 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4172 (void) check_for_unit_attention(h, c);
4173}
0390f0c0
SC		 4174
4175static int increment_passthru_count(struct ctlr_info *h)
4176{
4177 unsigned long flags;
4178
4179 spin_lock_irqsave(&h->passthru_count_lock, flags);
4180 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4181 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4182 return -1;
4183 }
4184 h->passthru_count++;
4185 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4186 return 0;
4187}
4188
4189static void decrement_passthru_count(struct ctlr_info *h)
4190{
4191 unsigned long flags;
4192
4193 spin_lock_irqsave(&h->passthru_count_lock, flags);
4194 if (h->passthru_count <= 0) {
4195 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4196 /* not expecting to get here. */
4197 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4198 return;
4199 }
4200 h->passthru_count--;
4201 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4202}
4203
edd16368
SC		 4204/*
4205 * ioctl
4206 */
4207static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4208{
4209 struct ctlr_info *h;
4210 void __user *argp = (void __user *)arg;
0390f0c0 4211 int rc;
edd16368
SC		 4212
4213 h = sdev_to_hba(dev);
4214
4215 switch (cmd) {
4216 case CCISS_DEREGDISK:
4217 case CCISS_REGNEWDISK:
4218 case CCISS_REGNEWD:
a08a8471 4219 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4220 return 0;
4221 case CCISS_GETPCIINFO:
4222 return hpsa_getpciinfo_ioctl(h, argp);
4223 case CCISS_GETDRIVVER:
4224 return hpsa_getdrivver_ioctl(h, argp);
4225 case CCISS_PASSTHRU:
0390f0c0
SC		 4226 if (increment_passthru_count(h))
4227 return -EAGAIN;
4228 rc = hpsa_passthru_ioctl(h, argp);
4229 decrement_passthru_count(h);
4230 return rc;
edd16368 4231 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4232 if (increment_passthru_count(h))
4233 return -EAGAIN;
4234 rc = hpsa_big_passthru_ioctl(h, argp);
4235 decrement_passthru_count(h);
4236 return rc;
edd16368
SC		 4237 default:
4238 return -ENOTTY;
4239 }
4240}
4241
6f039790
GKH		 4242static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4243 u8 reset_type)
64670ac8
SC		 4244{
4245 struct CommandList *c;
4246
4247 c = cmd_alloc(h);
4248 if (!c)
4249 return -ENOMEM;
a2dac136
SC		 4250 /* fill_cmd can't fail here, no data buffer to map */
4251 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4252 RAID_CTLR_LUNID, TYPE_MSG);
4253 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4254 c->waiting = NULL;
4255 enqueue_cmd_and_start_io(h, c);
4256 /* Don't wait for completion, the reset won't complete. Don't free
4257 * the command either. This is the last command we will send before
4258 * re-initializing everything, so it doesn't matter and won't leak.
4259 */
4260 return 0;
4261}
4262
a2dac136 4263static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 4264 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 4265 int cmd_type)
4266{
4267 int pci_dir = XFER_NONE;
75167d2c 4268 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4269
4270 c->cmd_type = CMD_IOCTL_PEND;
4271 c->Header.ReplyQueue = 0;
4272 if (buff != NULL && size > 0) {
4273 c->Header.SGList = 1;
4274 c->Header.SGTotal = 1;
4275 } else {
4276 c->Header.SGList = 0;
4277 c->Header.SGTotal = 0;
4278 }
4279 c->Header.Tag.lower = c->busaddr;
4280 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4281
4282 c->Request.Type.Type = cmd_type;
4283 if (cmd_type == TYPE_CMD) {
4284 switch (cmd) {
4285 case HPSA_INQUIRY:
4286 /* are we trying to read a vital product page */
4287 if (page_code != 0) {
4288 c->Request.CDB[1] = 0x01;
4289 c->Request.CDB[2] = page_code;
4290 }
4291 c->Request.CDBLen = 6;
4292 c->Request.Type.Attribute = ATTR_SIMPLE;
4293 c->Request.Type.Direction = XFER_READ;
4294 c->Request.Timeout = 0;
4295 c->Request.CDB[0] = HPSA_INQUIRY;
4296 c->Request.CDB[4] = size & 0xFF;
4297 break;
4298 case HPSA_REPORT_LOG:
4299 case HPSA_REPORT_PHYS:
4300 /* Talking to controller so It's a physical command
4301 mode = 00 target = 0. Nothing to write.
4302 */
4303 c->Request.CDBLen = 12;
4304 c->Request.Type.Attribute = ATTR_SIMPLE;
4305 c->Request.Type.Direction = XFER_READ;
4306 c->Request.Timeout = 0;
4307 c->Request.CDB[0] = cmd;
4308 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4309 c->Request.CDB[7] = (size >> 16) & 0xFF;
4310 c->Request.CDB[8] = (size >> 8) & 0xFF;
4311 c->Request.CDB[9] = size & 0xFF;
4312 break;
edd16368
SC		 4313 case HPSA_CACHE_FLUSH:
4314 c->Request.CDBLen = 12;
4315 c->Request.Type.Attribute = ATTR_SIMPLE;
4316 c->Request.Type.Direction = XFER_WRITE;
4317 c->Request.Timeout = 0;
4318 c->Request.CDB[0] = BMIC_WRITE;
4319 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4320 c->Request.CDB[7] = (size >> 8) & 0xFF;
4321 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4322 break;
4323 case TEST_UNIT_READY:
4324 c->Request.CDBLen = 6;
4325 c->Request.Type.Attribute = ATTR_SIMPLE;
4326 c->Request.Type.Direction = XFER_NONE;
4327 c->Request.Timeout = 0;
4328 break;
283b4a9b
SC		 4329 case HPSA_GET_RAID_MAP:
4330 c->Request.CDBLen = 12;
4331 c->Request.Type.Attribute = ATTR_SIMPLE;
4332 c->Request.Type.Direction = XFER_READ;
4333 c->Request.Timeout = 0;
4334 c->Request.CDB[0] = HPSA_CISS_READ;
4335 c->Request.CDB[1] = cmd;
4336 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4337 c->Request.CDB[7] = (size >> 16) & 0xFF;
4338 c->Request.CDB[8] = (size >> 8) & 0xFF;
4339 c->Request.CDB[9] = size & 0xFF;
4340 break;
edd16368
SC		 4341 default:
4342 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4343 BUG();
a2dac136 4344 return -1;
edd16368
SC		 4345 }
4346 } else if (cmd_type == TYPE_MSG) {
4347 switch (cmd) {
4348
4349 case HPSA_DEVICE_RESET_MSG:
4350 c->Request.CDBLen = 16;
4351 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4352 c->Request.Type.Attribute = ATTR_SIMPLE;
4353 c->Request.Type.Direction = XFER_NONE;
4354 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4355 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4356 c->Request.CDB[0] = cmd;
21e89afd 4357 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4358 /* If bytes 4-7 are zero, it means reset the */
4359 /* LunID device */
4360 c->Request.CDB[4] = 0x00;
4361 c->Request.CDB[5] = 0x00;
4362 c->Request.CDB[6] = 0x00;
4363 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4364 break;
4365 case HPSA_ABORT_MSG:
4366 a = buff; /* point to command to be aborted */
4367 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4368 a->Header.Tag.upper, a->Header.Tag.lower,
4369 c->Header.Tag.upper, c->Header.Tag.lower);
4370 c->Request.CDBLen = 16;
4371 c->Request.Type.Type = TYPE_MSG;
4372 c->Request.Type.Attribute = ATTR_SIMPLE;
4373 c->Request.Type.Direction = XFER_WRITE;
4374 c->Request.Timeout = 0; /* Don't time out */
4375 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4376 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4377 c->Request.CDB[2] = 0x00; /* reserved */
4378 c->Request.CDB[3] = 0x00; /* reserved */
4379 /* Tag to abort goes in CDB[4]-CDB[11] */
4380 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4381 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4382 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4383 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4384 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4385 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4386 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4387 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4388 c->Request.CDB[12] = 0x00; /* reserved */
4389 c->Request.CDB[13] = 0x00; /* reserved */
4390 c->Request.CDB[14] = 0x00; /* reserved */
4391 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4392 break;
edd16368
SC		 4393 default:
4394 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4395 cmd);
4396 BUG();
4397 }
4398 } else {
4399 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4400 BUG();
4401 }
4402
4403 switch (c->Request.Type.Direction) {
4404 case XFER_READ:
4405 pci_dir = PCI_DMA_FROMDEVICE;
4406 break;
4407 case XFER_WRITE:
4408 pci_dir = PCI_DMA_TODEVICE;
4409 break;
4410 case XFER_NONE:
4411 pci_dir = PCI_DMA_NONE;
4412 break;
4413 default:
4414 pci_dir = PCI_DMA_BIDIRECTIONAL;
4415 }
a2dac136
SC		 4416 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4417 return -1;
4418 return 0;
edd16368
SC		 4419}
4420
4421/*
4422 * Map (physical) PCI mem into (virtual) kernel space
4423 */
4424static void __iomem *remap_pci_mem(ulong base, ulong size)
4425{
4426 ulong page_base = ((ulong) base) & PAGE_MASK;
4427 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4428 void __iomem *page_remapped = ioremap_nocache(page_base,
4429 page_offs + size);
edd16368
SC		 4430
4431 return page_remapped ? (page_remapped + page_offs) : NULL;
4432}
4433
4434/* Takes cmds off the submission queue and sends them to the hardware,
4435 * then puts them on the queue of cmds waiting for completion.
4436 */
4437static void start_io(struct ctlr_info *h)
4438{
4439 struct CommandList *c;
e16a33ad 4440 unsigned long flags;
edd16368 4441
e16a33ad 4442 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4443 while (!list_empty(&h->reqQ)) {
4444 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4445 /* can't do anything if fifo is full */
4446 if ((h->access.fifo_full(h))) {
396883e2 4447 h->fifo_recently_full = 1;
edd16368
SC		 4448 dev_warn(&h->pdev->dev, "fifo full\n");
4449 break;
4450 }
396883e2 4451 h->fifo_recently_full = 0;
edd16368
SC		 4452
4453 /* Get the first entry from the Request Q */
4454 removeQ(c);
4455 h->Qdepth--;
4456
edd16368
SC		 4457 /* Put job onto the completed Q */
4458 addQ(&h->cmpQ, c);
e16a33ad
MG		 4459
4460 /* Must increment commands_outstanding before unlocking
4461 * and submitting to avoid race checking for fifo full
4462 * condition.
4463 */
4464 h->commands_outstanding++;
4465 if (h->commands_outstanding > h->max_outstanding)
4466 h->max_outstanding = h->commands_outstanding;
4467
4468 /* Tell the controller execute command */
4469 spin_unlock_irqrestore(&h->lock, flags);
4470 h->access.submit_command(h, c);
4471 spin_lock_irqsave(&h->lock, flags);
edd16368 4472 }
e16a33ad 4473 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4474}
4475
254f796b 4476static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4477{
254f796b 4478 return h->access.command_completed(h, q);
edd16368
SC		 4479}
4480
900c5440 4481static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4482{
4483 return h->access.intr_pending(h);
4484}
4485
4486static inline long interrupt_not_for_us(struct ctlr_info *h)
4487{
10f66018
SC		 4488 return (h->access.intr_pending(h) == 0) ||
4489 (h->interrupts_enabled == 0);
edd16368
SC		 4490}
4491
01a02ffc
SC		 4492static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4493 u32 raw_tag)
edd16368
SC		 4494{
4495 if (unlikely(tag_index >= h->nr_cmds)) {
4496 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4497 return 1;
4498 }
4499 return 0;
4500}
4501
5a3d16f5 4502static inline void finish_cmd(struct CommandList *c)
edd16368 4503{
e16a33ad 4504 unsigned long flags;
396883e2
SC		 4505 int io_may_be_stalled = 0;
4506 struct ctlr_info *h = c->h;
e16a33ad 4507
396883e2 4508 spin_lock_irqsave(&h->lock, flags);
edd16368 4509 removeQ(c);
396883e2
SC		 4510
4511 /*
4512 * Check for possibly stalled i/o.
4513 *
4514 * If a fifo_full condition is encountered, requests will back up
4515 * in h->reqQ. This queue is only emptied out by start_io which is
4516 * only called when a new i/o request comes in. If no i/o's are
4517 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4518 * start_io from here if we detect such a danger.
4519 *
4520 * Normally, we shouldn't hit this case, but pounding on the
4521 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4522 * commands_outstanding is low. We want to avoid calling
4523 * start_io from in here as much as possible, and esp. don't
4524 * want to get in a cycle where we call start_io every time
4525 * through here.
4526 */
4527 if (unlikely(h->fifo_recently_full) &&
4528 h->commands_outstanding < 5)
4529 io_may_be_stalled = 1;
4530
4531 spin_unlock_irqrestore(&h->lock, flags);
4532
e85c5974 4533 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 4534 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
4535 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 4536 complete_scsi_command(c);
edd16368
SC		 4537 else if (c->cmd_type == CMD_IOCTL_PEND)
4538 complete(c->waiting);
396883e2
SC		 4539 if (unlikely(io_may_be_stalled))
4540 start_io(h);
edd16368
SC		 4541}
4542
a104c99f
SC		 4543static inline u32 hpsa_tag_contains_index(u32 tag)
4544{
a104c99f
SC		 4545 return tag & DIRECT_LOOKUP_BIT;
4546}
4547
4548static inline u32 hpsa_tag_to_index(u32 tag)
4549{
a104c99f
SC		 4550 return tag >> DIRECT_LOOKUP_SHIFT;
4551}
4552
a9a3a273
SC		 4553
4554static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4555{
a9a3a273
SC		 4556#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4557#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4558 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4559 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4560 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4561}
4562
303932fd 4563/* process completion of an indexed ("direct lookup") command */
1d94f94d 4564static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4565 u32 raw_tag)
4566{
4567 u32 tag_index;
4568 struct CommandList *c;
4569
4570 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4571 if (!bad_tag(h, tag_index, raw_tag)) {
4572 c = h->cmd_pool + tag_index;
4573 finish_cmd(c);
4574 }
303932fd
DB		 4575}
4576
4577/* process completion of a non-indexed command */
1d94f94d 4578static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4579 u32 raw_tag)
4580{
4581 u32 tag;
4582 struct CommandList *c = NULL;
e16a33ad 4583 unsigned long flags;
303932fd 4584
a9a3a273 4585 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4586 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4587 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4588 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4589 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4590 finish_cmd(c);
1d94f94d 4591 return;
303932fd
DB		 4592 }
4593 }
e16a33ad 4594 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4595 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4596}
4597
64670ac8
SC		 4598/* Some controllers, like p400, will give us one interrupt
4599 * after a soft reset, even if we turned interrupts off.
4600 * Only need to check for this in the hpsa_xxx_discard_completions
4601 * functions.
4602 */
4603static int ignore_bogus_interrupt(struct ctlr_info *h)
4604{
4605 if (likely(!reset_devices))
4606 return 0;
4607
4608 if (likely(h->interrupts_enabled))
4609 return 0;
4610
4611 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4612 "(known firmware bug.) Ignoring.\n");
4613
4614 return 1;
4615}
4616
254f796b
MG		 4617/*
4618 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4619 * Relies on (h-q[x] == x) being true for x such that
4620 * 0 <= x < MAX_REPLY_QUEUES.
4621 */
4622static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4623{
254f796b
MG		 4624 return container_of((queue - *queue), struct ctlr_info, q[0]);
4625}
4626
4627static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4628{
4629 struct ctlr_info *h = queue_to_hba(queue);
4630 u8 q = *(u8 *) queue;
64670ac8
SC		 4631 u32 raw_tag;
4632
4633 if (ignore_bogus_interrupt(h))
4634 return IRQ_NONE;
4635
4636 if (interrupt_not_for_us(h))
4637 return IRQ_NONE;
a0c12413 4638 h->last_intr_timestamp = get_jiffies_64();
64670ac8 4639 while (interrupt_pending(h)) {
254f796b 4640 raw_tag = get_next_completion(h, q);
64670ac8 4641 while (raw_tag != FIFO_EMPTY)
254f796b 4642 raw_tag = next_command(h, q);
64670ac8 4643 }
64670ac8
SC		 4644 return IRQ_HANDLED;
4645}
4646
254f796b 4647static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 4648{
254f796b 4649 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 4650 u32 raw_tag;
254f796b 4651 u8 q = *(u8 *) queue;
64670ac8
SC		 4652
4653 if (ignore_bogus_interrupt(h))
4654 return IRQ_NONE;
4655
a0c12413 4656 h->last_intr_timestamp = get_jiffies_64();
254f796b 4657 raw_tag = get_next_completion(h, q);
64670ac8 4658 while (raw_tag != FIFO_EMPTY)
254f796b 4659 raw_tag = next_command(h, q);
64670ac8
SC		 4660 return IRQ_HANDLED;
4661}
4662
254f796b 4663static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 4664{
254f796b 4665 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 4666 u32 raw_tag;
254f796b 4667 u8 q = *(u8 *) queue;
edd16368
SC		 4668
4669 if (interrupt_not_for_us(h))
4670 return IRQ_NONE;
a0c12413 4671 h->last_intr_timestamp = get_jiffies_64();
10f66018 4672 while (interrupt_pending(h)) {
254f796b 4673 raw_tag = get_next_completion(h, q);
10f66018 4674 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4675 if (likely(hpsa_tag_contains_index(raw_tag)))
4676 process_indexed_cmd(h, raw_tag);
10f66018 4677 else
1d94f94d 4678 process_nonindexed_cmd(h, raw_tag);
254f796b 4679 raw_tag = next_command(h, q);
10f66018
SC		 4680 }
4681 }
10f66018
SC		 4682 return IRQ_HANDLED;
4683}
4684
254f796b 4685static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 4686{
254f796b 4687 struct ctlr_info *h = queue_to_hba(queue);
10f66018 4688 u32 raw_tag;
254f796b 4689 u8 q = *(u8 *) queue;
10f66018 4690
a0c12413 4691 h->last_intr_timestamp = get_jiffies_64();
254f796b 4692 raw_tag = get_next_completion(h, q);
303932fd 4693 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 4694 if (likely(hpsa_tag_contains_index(raw_tag)))
4695 process_indexed_cmd(h, raw_tag);
303932fd 4696 else
1d94f94d 4697 process_nonindexed_cmd(h, raw_tag);
254f796b 4698 raw_tag = next_command(h, q);
edd16368 4699 }
edd16368
SC		 4700 return IRQ_HANDLED;
4701}
4702
a9a3a273
SC		 4703/* Send a message CDB to the firmware. Careful, this only works
4704 * in simple mode, not performant mode due to the tag lookup.
4705 * We only ever use this immediately after a controller reset.
4706 */
6f039790
GKH		 4707static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
4708 unsigned char type)
edd16368
SC		 4709{
4710 struct Command {
4711 struct CommandListHeader CommandHeader;
4712 struct RequestBlock Request;
4713 struct ErrDescriptor ErrorDescriptor;
4714 };
4715 struct Command *cmd;
4716 static const size_t cmd_sz = sizeof(*cmd) +
4717 sizeof(cmd->ErrorDescriptor);
4718 dma_addr_t paddr64;
4719 uint32_t paddr32, tag;
4720 void __iomem *vaddr;
4721 int i, err;
4722
4723 vaddr = pci_ioremap_bar(pdev, 0);
4724 if (vaddr == NULL)
4725 return -ENOMEM;
4726
4727 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
4728 * CCISS commands, so they must be allocated from the lower 4GiB of
4729 * memory.
4730 */
4731 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
4732 if (err) {
4733 iounmap(vaddr);
4734 return -ENOMEM;
4735 }
4736
4737 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
4738 if (cmd == NULL) {
4739 iounmap(vaddr);
4740 return -ENOMEM;
4741 }
4742
4743 /* This must fit, because of the 32-bit consistent DMA mask. Also,
4744 * although there's no guarantee, we assume that the address is at
4745 * least 4-byte aligned (most likely, it's page-aligned).
4746 */
4747 paddr32 = paddr64;
4748
4749 cmd->CommandHeader.ReplyQueue = 0;
4750 cmd->CommandHeader.SGList = 0;
4751 cmd->CommandHeader.SGTotal = 0;
4752 cmd->CommandHeader.Tag.lower = paddr32;
4753 cmd->CommandHeader.Tag.upper = 0;
4754 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
4755
4756 cmd->Request.CDBLen = 16;
4757 cmd->Request.Type.Type = TYPE_MSG;
4758 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
4759 cmd->Request.Type.Direction = XFER_NONE;
4760 cmd->Request.Timeout = 0; /* Don't time out */
4761 cmd->Request.CDB[0] = opcode;
4762 cmd->Request.CDB[1] = type;
4763 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
4764 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
4765 cmd->ErrorDescriptor.Addr.upper = 0;
4766 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
4767
4768 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
4769
4770 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
4771 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 4772 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 4773 break;
4774 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
4775 }
4776
4777 iounmap(vaddr);
4778
4779 /* we leak the DMA buffer here ... no choice since the controller could
4780 * still complete the command.
4781 */
4782 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
4783 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
4784 opcode, type);
4785 return -ETIMEDOUT;
4786 }
4787
4788 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
4789
4790 if (tag & HPSA_ERROR_BIT) {
4791 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
4792 opcode, type);
4793 return -EIO;
4794 }
4795
4796 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
4797 opcode, type);
4798 return 0;
4799}
4800
edd16368
SC		 4801#define hpsa_noop(p) hpsa_message(p, 3, 0)
4802
1df8552a 4803static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 4804 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 4805{
4806 u16 pmcsr;
4807 int pos;
4808
4809 if (use_doorbell) {
4810 /* For everything after the P600, the PCI power state method
4811 * of resetting the controller doesn't work, so we have this
4812 * other way using the doorbell register.
4813 */
4814 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 4815 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 4816
4817 /* PMC hardware guys tell us we need a 5 second delay after
4818 * doorbell reset and before any attempt to talk to the board
4819 * at all to ensure that this actually works and doesn't fall
4820 * over in some weird corner cases.
4821 */
4822 msleep(5000);
1df8552a
SC		 4823 } else { /* Try to do it the PCI power state way */
4824
4825 /* Quoting from the Open CISS Specification: "The Power
4826 * Management Control/Status Register (CSR) controls the power
4827 * state of the device. The normal operating state is D0,
4828 * CSR=00h. The software off state is D3, CSR=03h. To reset
4829 * the controller, place the interface device in D3 then to D0,
4830 * this causes a secondary PCI reset which will reset the
4831 * controller." */
4832
4833 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
4834 if (pos == 0) {
4835 dev_err(&pdev->dev,
4836 "hpsa_reset_controller: "
4837 "PCI PM not supported\n");
4838 return -ENODEV;
4839 }
4840 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
4841 /* enter the D3hot power management state */
4842 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
4843 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4844 pmcsr |= PCI_D3hot;
4845 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
4846
4847 msleep(500);
4848
4849 /* enter the D0 power management state */
4850 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
4851 pmcsr |= PCI_D0;
4852 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 4853
4854 /*
4855 * The P600 requires a small delay when changing states.
4856 * Otherwise we may think the board did not reset and we bail.
4857 * This for kdump only and is particular to the P600.
4858 */
4859 msleep(500);
1df8552a
SC		 4860 }
4861 return 0;
4862}
4863
6f039790 4864static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 4865{
4866 memset(driver_version, 0, len);
f79cfec6 4867 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 4868}
4869
6f039790 4870static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4871{
4872 char *driver_version;
4873 int i, size = sizeof(cfgtable->driver_version);
4874
4875 driver_version = kmalloc(size, GFP_KERNEL);
4876 if (!driver_version)
4877 return -ENOMEM;
4878
4879 init_driver_version(driver_version, size);
4880 for (i = 0; i < size; i++)
4881 writeb(driver_version[i], &cfgtable->driver_version[i]);
4882 kfree(driver_version);
4883 return 0;
4884}
4885
6f039790
GKH		 4886static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
4887 unsigned char *driver_ver)
580ada3c
SC		 4888{
4889 int i;
4890
4891 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
4892 driver_ver[i] = readb(&cfgtable->driver_version[i]);
4893}
4894
6f039790 4895static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 4896{
4897
4898 char *driver_ver, *old_driver_ver;
4899 int rc, size = sizeof(cfgtable->driver_version);
4900
4901 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
4902 if (!old_driver_ver)
4903 return -ENOMEM;
4904 driver_ver = old_driver_ver + size;
4905
4906 /* After a reset, the 32 bytes of "driver version" in the cfgtable
4907 * should have been changed, otherwise we know the reset failed.
4908 */
4909 init_driver_version(old_driver_ver, size);
4910 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
4911 rc = !memcmp(driver_ver, old_driver_ver, size);
4912 kfree(old_driver_ver);
4913 return rc;
4914}
edd16368 4915/* This does a hard reset of the controller using PCI power management
1df8552a 4916 * states or the using the doorbell register.
edd16368 4917 */
6f039790 4918static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 4919{
1df8552a
SC		 4920 u64 cfg_offset;
4921 u32 cfg_base_addr;
4922 u64 cfg_base_addr_index;
4923 void __iomem *vaddr;
4924 unsigned long paddr;
580ada3c 4925 u32 misc_fw_support;
270d05de 4926 int rc;
1df8552a 4927 struct CfgTable __iomem *cfgtable;
cf0b08d0 4928 u32 use_doorbell;
18867659 4929 u32 board_id;
270d05de 4930 u16 command_register;
edd16368 4931
1df8552a
SC		 4932 /* For controllers as old as the P600, this is very nearly
4933 * the same thing as
edd16368
SC		 4934 *
4935 * pci_save_state(pci_dev);
4936 * pci_set_power_state(pci_dev, PCI_D3hot);
4937 * pci_set_power_state(pci_dev, PCI_D0);
4938 * pci_restore_state(pci_dev);
4939 *
1df8552a
SC		 4940 * For controllers newer than the P600, the pci power state
4941 * method of resetting doesn't work so we have another way
4942 * using the doorbell register.
edd16368 4943 */
18867659 4944
25c1e56a 4945 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 4946 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 4947 dev_warn(&pdev->dev, "Not resetting device.\n");
4948 return -ENODEV;
4949 }
46380786
SC		 4950
4951 /* if controller is soft- but not hard resettable... */
4952 if (!ctlr_is_hard_resettable(board_id))
4953 return -ENOTSUPP; /* try soft reset later. */
18867659 4954
270d05de
SC		 4955 /* Save the PCI command register */
4956 pci_read_config_word(pdev, 4, &command_register);
4957 /* Turn the board off. This is so that later pci_restore_state()
4958 * won't turn the board on before the rest of config space is ready.
4959 */
4960 pci_disable_device(pdev);
4961 pci_save_state(pdev);
edd16368 4962
1df8552a
SC		 4963 /* find the first memory BAR, so we can find the cfg table */
4964 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
4965 if (rc)
4966 return rc;
4967 vaddr = remap_pci_mem(paddr, 0x250);
4968 if (!vaddr)
4969 return -ENOMEM;
edd16368 4970
1df8552a
SC		 4971 /* find cfgtable in order to check if reset via doorbell is supported */
4972 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
4973 &cfg_base_addr_index, &cfg_offset);
4974 if (rc)
4975 goto unmap_vaddr;
4976 cfgtable = remap_pci_mem(pci_resource_start(pdev,
4977 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
4978 if (!cfgtable) {
4979 rc = -ENOMEM;
4980 goto unmap_vaddr;
4981 }
580ada3c
SC		 4982 rc = write_driver_ver_to_cfgtable(cfgtable);
4983 if (rc)
4984 goto unmap_vaddr;
edd16368 4985
cf0b08d0
SC		 4986 /* If reset via doorbell register is supported, use that.
4987 * There are two such methods. Favor the newest method.
4988 */
1df8552a 4989 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 4990 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
4991 if (use_doorbell) {
4992 use_doorbell = DOORBELL_CTLR_RESET2;
4993 } else {
4994 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
4995 if (use_doorbell) {
fba63097
MM		 4996 dev_warn(&pdev->dev, "Soft reset not supported. "
4997 "Firmware update is required.\n");
64670ac8 4998 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 4999 goto unmap_cfgtable;
5000 }
5001 }
edd16368 5002
1df8552a
SC		 5003 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5004 if (rc)
5005 goto unmap_cfgtable;
edd16368 5006
270d05de
SC		 5007 pci_restore_state(pdev);
5008 rc = pci_enable_device(pdev);
5009 if (rc) {
5010 dev_warn(&pdev->dev, "failed to enable device.\n");
5011 goto unmap_cfgtable;
edd16368 5012 }
270d05de 5013 pci_write_config_word(pdev, 4, command_register);
edd16368 5014
1df8552a
SC		 5015 /* Some devices (notably the HP Smart Array 5i Controller)
5016 need a little pause here */
5017 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5018
fe5389c8
SC		 5019 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5020 if (rc) {
5021 dev_warn(&pdev->dev,
64670ac8
SC		 5022 "failed waiting for board to become ready "
5023 "after hard reset\n");
fe5389c8
SC		 5024 goto unmap_cfgtable;
5025 }
fe5389c8 5026
580ada3c
SC		 5027 rc = controller_reset_failed(vaddr);
5028 if (rc < 0)
5029 goto unmap_cfgtable;
5030 if (rc) {
64670ac8
SC		 5031 dev_warn(&pdev->dev, "Unable to successfully reset "
5032 "controller. Will try soft reset.\n");
5033 rc = -ENOTSUPP;
580ada3c 5034 } else {
64670ac8 5035 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5036 }
5037
5038unmap_cfgtable:
5039 iounmap(cfgtable);
5040
5041unmap_vaddr:
5042 iounmap(vaddr);
5043 return rc;
edd16368
SC		 5044}
5045
5046/*
5047 * We cannot read the structure directly, for portability we must use
5048 * the io functions.
5049 * This is for debug only.
5050 */
edd16368
SC		 5051static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5052{
58f8665c 5053#ifdef HPSA_DEBUG
edd16368
SC		 5054 int i;
5055 char temp_name[17];
5056
5057 dev_info(dev, "Controller Configuration information\n");
5058 dev_info(dev, "------------------------------------\n");
5059 for (i = 0; i < 4; i++)
5060 temp_name[i] = readb(&(tb->Signature[i]));
5061 temp_name[4] = '\0';
5062 dev_info(dev, " Signature = %s\n", temp_name);
5063 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5064 dev_info(dev, " Transport methods supported = 0x%x\n",
5065 readl(&(tb->TransportSupport)));
5066 dev_info(dev, " Transport methods active = 0x%x\n",
5067 readl(&(tb->TransportActive)));
5068 dev_info(dev, " Requested transport Method = 0x%x\n",
5069 readl(&(tb->HostWrite.TransportRequest)));
5070 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5071 readl(&(tb->HostWrite.CoalIntDelay)));
5072 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5073 readl(&(tb->HostWrite.CoalIntCount)));
5074 dev_info(dev, " Max outstanding commands = 0x%d\n",
5075 readl(&(tb->CmdsOutMax)));
5076 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5077 for (i = 0; i < 16; i++)
5078 temp_name[i] = readb(&(tb->ServerName[i]));
5079 temp_name[16] = '\0';
5080 dev_info(dev, " Server Name = %s\n", temp_name);
5081 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5082 readl(&(tb->HeartBeat)));
edd16368 5083#endif /* HPSA_DEBUG */
58f8665c 5084}
edd16368
SC		 5085
5086static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5087{
5088 int i, offset, mem_type, bar_type;
5089
5090 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5091 return 0;
5092 offset = 0;
5093 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5094 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5095 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5096 offset += 4;
5097 else {
5098 mem_type = pci_resource_flags(pdev, i) &
5099 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5100 switch (mem_type) {
5101 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5102 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5103 offset += 4; /* 32 bit */
5104 break;
5105 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5106 offset += 8;
5107 break;
5108 default: /* reserved in PCI 2.2 */
5109 dev_warn(&pdev->dev,
5110 "base address is invalid\n");
5111 return -1;
5112 break;
5113 }
5114 }
5115 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5116 return i + 1;
5117 }
5118 return -1;
5119}
5120
5121/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5122 * controllers that are capable. If not, we use IO-APIC mode.
5123 */
5124
6f039790 5125static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5126{
5127#ifdef CONFIG_PCI_MSI
254f796b
MG		 5128 int err, i;
5129 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5130
5131 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5132 hpsa_msix_entries[i].vector = 0;
5133 hpsa_msix_entries[i].entry = i;
5134 }
edd16368
SC		 5135
5136 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5137 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5138 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5139 goto default_int_mode;
55c06c71
SC		 5140 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5141 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5142 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5143 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5144 h->msix_vector);
edd16368 5145 if (err > 0) {
55c06c71 5146 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5147 "available\n", err);
eee0f03a
HR		 5148 h->msix_vector = err;
5149 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5150 h->msix_vector);
5151 }
5152 if (!err) {
5153 for (i = 0; i < h->msix_vector; i++)
5154 h->intr[i] = hpsa_msix_entries[i].vector;
5155 return;
edd16368 5156 } else {
55c06c71 5157 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5158 err);
eee0f03a 5159 h->msix_vector = 0;
edd16368
SC		 5160 goto default_int_mode;
5161 }
5162 }
55c06c71
SC		 5163 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5164 dev_info(&h->pdev->dev, "MSI\n");
5165 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5166 h->msi_vector = 1;
5167 else
55c06c71 5168 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5169 }
5170default_int_mode:
5171#endif /* CONFIG_PCI_MSI */
5172 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5173 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5174}
5175
6f039790 5176static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5177{
5178 int i;
5179 u32 subsystem_vendor_id, subsystem_device_id;
5180
5181 subsystem_vendor_id = pdev->subsystem_vendor;
5182 subsystem_device_id = pdev->subsystem_device;
5183 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5184 subsystem_vendor_id;
5185
5186 for (i = 0; i < ARRAY_SIZE(products); i++)
5187 if (*board_id == products[i].board_id)
5188 return i;
5189
6798cc0a
SC		 5190 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5191 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5192 !hpsa_allow_any) {
e5c880d1
SC		 5193 dev_warn(&pdev->dev, "unrecognized board ID: "
5194 "0x%08x, ignoring.\n", *board_id);
5195 return -ENODEV;
5196 }
5197 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5198}
5199
6f039790
GKH		 5200static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5201 unsigned long *memory_bar)
3a7774ce
SC		 5202{
5203 int i;
5204
5205 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5206 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5207 /* addressing mode bits already removed */
12d2cd47
SC		 5208 *memory_bar = pci_resource_start(pdev, i);
5209 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5210 *memory_bar);
5211 return 0;
5212 }
12d2cd47 5213 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5214 return -ENODEV;
5215}
5216
6f039790
GKH		 5217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5218 int wait_for_ready)
2c4c8c8b 5219{
fe5389c8 5220 int i, iterations;
2c4c8c8b 5221 u32 scratchpad;
fe5389c8
SC		 5222 if (wait_for_ready)
5223 iterations = HPSA_BOARD_READY_ITERATIONS;
5224 else
5225 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5226
fe5389c8
SC		 5227 for (i = 0; i < iterations; i++) {
5228 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5229 if (wait_for_ready) {
5230 if (scratchpad == HPSA_FIRMWARE_READY)
5231 return 0;
5232 } else {
5233 if (scratchpad != HPSA_FIRMWARE_READY)
5234 return 0;
5235 }
2c4c8c8b
SC		 5236 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5237 }
fe5389c8 5238 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5239 return -ENODEV;
5240}
5241
6f039790
GKH		 5242static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5243 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5244 u64 *cfg_offset)
a51fd47f
SC		 5245{
5246 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5247 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5248 *cfg_base_addr &= (u32) 0x0000ffff;
5249 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5250 if (*cfg_base_addr_index == -1) {
5251 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5252 return -ENODEV;
5253 }
5254 return 0;
5255}
5256
6f039790 5257static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5258{
01a02ffc
SC		 5259 u64 cfg_offset;
5260 u32 cfg_base_addr;
5261 u64 cfg_base_addr_index;
303932fd 5262 u32 trans_offset;
a51fd47f 5263 int rc;
77c4495c 5264
a51fd47f
SC		 5265 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5266 &cfg_base_addr_index, &cfg_offset);
5267 if (rc)
5268 return rc;
77c4495c 5269 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5270 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5271 if (!h->cfgtable)
5272 return -ENOMEM;
580ada3c
SC		 5273 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5274 if (rc)
5275 return rc;
77c4495c 5276 /* Find performant mode table. */
a51fd47f 5277 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5278 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5279 cfg_base_addr_index)+cfg_offset+trans_offset,
5280 sizeof(*h->transtable));
5281 if (!h->transtable)
5282 return -ENOMEM;
5283 return 0;
5284}
5285
6f039790 5286static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5287{
5288 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5289
5290 /* Limit commands in memory limited kdump scenario. */
5291 if (reset_devices && h->max_commands > 32)
5292 h->max_commands = 32;
5293
cba3d38b
SC		 5294 if (h->max_commands < 16) {
5295 dev_warn(&h->pdev->dev, "Controller reports "
5296 "max supported commands of %d, an obvious lie. "
5297 "Using 16. Ensure that firmware is up to date.\n",
5298 h->max_commands);
5299 h->max_commands = 16;
5300 }
5301}
5302
b93d7536
SC		 5303/* Interrogate the hardware for some limits:
5304 * max commands, max SG elements without chaining, and with chaining,
5305 * SG chain block size, etc.
5306 */
6f039790 5307static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5308{
cba3d38b 5309 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5310 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5311 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5312 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5313 /*
5314 * Limit in-command s/g elements to 32 save dma'able memory.
5315 * Howvever spec says if 0, use 31
5316 */
5317 h->max_cmd_sg_entries = 31;
5318 if (h->maxsgentries > 512) {
5319 h->max_cmd_sg_entries = 32;
5320 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5321 h->maxsgentries--; /* save one for chain pointer */
5322 } else {
5323 h->maxsgentries = 31; /* default to traditional values */
5324 h->chainsize = 0;
5325 }
75167d2c
SC		 5326
5327 /* Find out what task management functions are supported and cache */
5328 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5329 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5330 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5331 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5332 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5333}
5334
76c46e49
SC		 5335static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5336{
0fc9fd40 5337 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5338 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5339 return false;
5340 }
5341 return true;
5342}
5343
97a5e98c 5344static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5345{
97a5e98c 5346 u32 driver_support;
f7c39101 5347
28e13446
SC		 5348#ifdef CONFIG_X86
5349 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5350 driver_support = readl(&(h->cfgtable->driver_support));
5351 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5352#endif
28e13446
SC		 5353 driver_support |= ENABLE_UNIT_ATTN;
5354 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5355}
5356
3d0eab67
SC		 5357/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5358 * in a prefetch beyond physical memory.
5359 */
5360static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5361{
5362 u32 dma_prefetch;
5363
5364 if (h->board_id != 0x3225103C)
5365 return;
5366 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5367 dma_prefetch |= 0x8000;
5368 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5369}
5370
76438d08
SC		 5371static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5372{
5373 int i;
5374 u32 doorbell_value;
5375 unsigned long flags;
5376 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5377 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5378 spin_lock_irqsave(&h->lock, flags);
5379 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5380 spin_unlock_irqrestore(&h->lock, flags);
5381 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5382 break;
5383 /* delay and try again */
5384 msleep(20);
5385 }
5386}
5387
6f039790 5388static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5389{
5390 int i;
6eaf46fd
SC		 5391 u32 doorbell_value;
5392 unsigned long flags;
eb6b2ae9
SC		 5393
5394 /* under certain very rare conditions, this can take awhile.
5395 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5396 * as we enter this code.)
5397 */
5398 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5399 spin_lock_irqsave(&h->lock, flags);
5400 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5401 spin_unlock_irqrestore(&h->lock, flags);
382be668 5402 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5403 break;
5404 /* delay and try again */
60d3f5b0 5405 usleep_range(10000, 20000);
eb6b2ae9 5406 }
3f4336f3
SC		 5407}
5408
6f039790 5409static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5410{
5411 u32 trans_support;
5412
5413 trans_support = readl(&(h->cfgtable->TransportSupport));
5414 if (!(trans_support & SIMPLE_MODE))
5415 return -ENOTSUPP;
5416
5417 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5418
3f4336f3
SC		 5419 /* Update the field, and then ring the doorbell */
5420 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 5421 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 5422 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5423 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5424 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5425 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5426 goto error;
960a30e7 5427 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5428 return 0;
283b4a9b
SC		 5429error:
5430 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5431 return -ENODEV;
eb6b2ae9
SC		 5432}
5433
6f039790 5434static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5435{
eb6b2ae9 5436 int prod_index, err;
edd16368 5437
e5c880d1
SC		 5438 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5439 if (prod_index < 0)
5440 return -ENODEV;
5441 h->product_name = products[prod_index].product_name;
5442 h->access = *(products[prod_index].access);
edd16368 5443
e5a44df8
MG		 5444 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5445 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5446
55c06c71 5447 err = pci_enable_device(h->pdev);
edd16368 5448 if (err) {
55c06c71 5449 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5450 return err;
5451 }
5452
5cb460a6
SC		 5453 /* Enable bus mastering (pci_disable_device may disable this) */
5454 pci_set_master(h->pdev);
5455
f79cfec6 5456 err = pci_request_regions(h->pdev, HPSA);
edd16368 5457 if (err) {
55c06c71
SC		 5458 dev_err(&h->pdev->dev,
5459 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5460 return err;
5461 }
6b3f4c52 5462 hpsa_interrupt_mode(h);
12d2cd47 5463 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5464 if (err)
edd16368 5465 goto err_out_free_res;
edd16368 5466 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5467 if (!h->vaddr) {
5468 err = -ENOMEM;
5469 goto err_out_free_res;
5470 }
fe5389c8 5471 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5472 if (err)
edd16368 5473 goto err_out_free_res;
77c4495c
SC		 5474 err = hpsa_find_cfgtables(h);
5475 if (err)
edd16368 5476 goto err_out_free_res;
b93d7536 5477 hpsa_find_board_params(h);
edd16368 5478
76c46e49 5479 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5480 err = -ENODEV;
5481 goto err_out_free_res;
5482 }
97a5e98c 5483 hpsa_set_driver_support_bits(h);
3d0eab67 5484 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5485 err = hpsa_enter_simple_mode(h);
5486 if (err)
edd16368 5487 goto err_out_free_res;
edd16368
SC		 5488 return 0;
5489
5490err_out_free_res:
204892e9
SC		 5491 if (h->transtable)
5492 iounmap(h->transtable);
5493 if (h->cfgtable)
5494 iounmap(h->cfgtable);
5495 if (h->vaddr)
5496 iounmap(h->vaddr);
f0bd0b68 5497 pci_disable_device(h->pdev);
55c06c71 5498 pci_release_regions(h->pdev);
edd16368
SC		 5499 return err;
5500}
5501
6f039790 5502static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5503{
5504 int rc;
5505
5506#define HBA_INQUIRY_BYTE_COUNT 64
5507 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5508 if (!h->hba_inquiry_data)
5509 return;
5510 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5511 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5512 if (rc != 0) {
5513 kfree(h->hba_inquiry_data);
5514 h->hba_inquiry_data = NULL;
5515 }
5516}
5517
6f039790 5518static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5519{
1df8552a 5520 int rc, i;
4c2a8c40
SC		 5521
5522 if (!reset_devices)
5523 return 0;
5524
1df8552a
SC		 5525 /* Reset the controller with a PCI power-cycle or via doorbell */
5526 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5527
1df8552a
SC		 5528 /* -ENOTSUPP here means we cannot reset the controller
5529 * but it's already (and still) up and running in
18867659
SC		 5530 * "performant mode". Or, it might be 640x, which can't reset
5531 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5532 */
5533 if (rc == -ENOTSUPP)
64670ac8 5534 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5535 if (rc)
5536 return -ENODEV;
4c2a8c40
SC		 5537
5538 /* Now try to get the controller to respond to a no-op */
2b870cb3 5539 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5540 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5541 if (hpsa_noop(pdev) == 0)
5542 break;
5543 else
5544 dev_warn(&pdev->dev, "no-op failed%s\n",
5545 (i < 11 ? "; re-trying" : ""));
5546 }
5547 return 0;
5548}
5549
6f039790 5550static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5551{
5552 h->cmd_pool_bits = kzalloc(
5553 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5554 sizeof(unsigned long), GFP_KERNEL);
5555 h->cmd_pool = pci_alloc_consistent(h->pdev,
5556 h->nr_cmds * sizeof(*h->cmd_pool),
5557 &(h->cmd_pool_dhandle));
5558 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5559 h->nr_cmds * sizeof(*h->errinfo_pool),
5560 &(h->errinfo_pool_dhandle));
5561 if ((h->cmd_pool_bits == NULL)
5562 || (h->cmd_pool == NULL)
5563 || (h->errinfo_pool == NULL)) {
5564 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5565 return -ENOMEM;
5566 }
5567 return 0;
5568}
5569
5570static void hpsa_free_cmd_pool(struct ctlr_info *h)
5571{
5572 kfree(h->cmd_pool_bits);
5573 if (h->cmd_pool)
5574 pci_free_consistent(h->pdev,
5575 h->nr_cmds * sizeof(struct CommandList),
5576 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 5577 if (h->ioaccel2_cmd_pool)
5578 pci_free_consistent(h->pdev,
5579 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
5580 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 5581 if (h->errinfo_pool)
5582 pci_free_consistent(h->pdev,
5583 h->nr_cmds * sizeof(struct ErrorInfo),
5584 h->errinfo_pool,
5585 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5586 if (h->ioaccel_cmd_pool)
5587 pci_free_consistent(h->pdev,
5588 h->nr_cmds * sizeof(struct io_accel1_cmd),
5589 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5590}
5591
0ae01a32
SC		 5592static int hpsa_request_irq(struct ctlr_info *h,
5593 irqreturn_t (*msixhandler)(int, void *),
5594 irqreturn_t (*intxhandler)(int, void *))
5595{
254f796b 5596 int rc, i;
0ae01a32 5597
254f796b
MG		 5598 /*
5599 * initialize h->q[x] = x so that interrupt handlers know which
5600 * queue to process.
5601 */
5602 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5603 h->q[i] = (u8) i;
5604
eee0f03a 5605 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5606 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5607 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5608 rc = request_irq(h->intr[i], msixhandler,
5609 0, h->devname,
5610 &h->q[i]);
5611 } else {
5612 /* Use single reply pool */
eee0f03a 5613 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5614 rc = request_irq(h->intr[h->intr_mode],
5615 msixhandler, 0, h->devname,
5616 &h->q[h->intr_mode]);
5617 } else {
5618 rc = request_irq(h->intr[h->intr_mode],
5619 intxhandler, IRQF_SHARED, h->devname,
5620 &h->q[h->intr_mode]);
5621 }
5622 }
0ae01a32
SC		 5623 if (rc) {
5624 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5625 h->intr[h->intr_mode], h->devname);
5626 return -ENODEV;
5627 }
5628 return 0;
5629}
5630
6f039790 5631static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5632{
5633 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
5634 HPSA_RESET_TYPE_CONTROLLER)) {
5635 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
5636 return -EIO;
5637 }
5638
5639 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
5640 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
5641 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
5642 return -1;
5643 }
5644
5645 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
5646 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
5647 dev_warn(&h->pdev->dev, "Board failed to become ready "
5648 "after soft reset.\n");
5649 return -1;
5650 }
5651
5652 return 0;
5653}
5654
254f796b
MG		 5655static void free_irqs(struct ctlr_info *h)
5656{
5657 int i;
5658
5659 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
5660 /* Single reply queue, only one irq to free */
5661 i = h->intr_mode;
5662 free_irq(h->intr[i], &h->q[i]);
5663 return;
5664 }
5665
eee0f03a 5666 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5667 free_irq(h->intr[i], &h->q[i]);
5668}
5669
0097f0f4 5670static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 5671{
254f796b 5672 free_irqs(h);
64670ac8 5673#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 5674 if (h->msix_vector) {
5675 if (h->pdev->msix_enabled)
5676 pci_disable_msix(h->pdev);
5677 } else if (h->msi_vector) {
5678 if (h->pdev->msi_enabled)
5679 pci_disable_msi(h->pdev);
5680 }
64670ac8 5681#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 5682}
5683
5684static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
5685{
5686 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 5687 hpsa_free_sg_chain_blocks(h);
5688 hpsa_free_cmd_pool(h);
e1f7de0c 5689 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 5690 kfree(h->blockFetchTable);
5691 pci_free_consistent(h->pdev, h->reply_pool_size,
5692 h->reply_pool, h->reply_pool_dhandle);
5693 if (h->vaddr)
5694 iounmap(h->vaddr);
5695 if (h->transtable)
5696 iounmap(h->transtable);
5697 if (h->cfgtable)
5698 iounmap(h->cfgtable);
5699 pci_release_regions(h->pdev);
5700 kfree(h);
5701}
5702
a0c12413
SC		 5703/* Called when controller lockup detected. */
5704static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
5705{
5706 struct CommandList *c = NULL;
5707
5708 assert_spin_locked(&h->lock);
5709 /* Mark all outstanding commands as failed and complete them. */
5710 while (!list_empty(list)) {
5711 c = list_entry(list->next, struct CommandList, list);
5712 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 5713 finish_cmd(c);
a0c12413
SC		 5714 }
5715}
5716
5717static void controller_lockup_detected(struct ctlr_info *h)
5718{
5719 unsigned long flags;
5720
a0c12413
SC		 5721 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5722 spin_lock_irqsave(&h->lock, flags);
5723 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
5724 spin_unlock_irqrestore(&h->lock, flags);
5725 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
5726 h->lockup_detected);
5727 pci_disable_device(h->pdev);
5728 spin_lock_irqsave(&h->lock, flags);
5729 fail_all_cmds_on_list(h, &h->cmpQ);
5730 fail_all_cmds_on_list(h, &h->reqQ);
5731 spin_unlock_irqrestore(&h->lock, flags);
5732}
5733
a0c12413
SC		 5734static void detect_controller_lockup(struct ctlr_info *h)
5735{
5736 u64 now;
5737 u32 heartbeat;
5738 unsigned long flags;
5739
a0c12413
SC		 5740 now = get_jiffies_64();
5741 /* If we've received an interrupt recently, we're ok. */
5742 if (time_after64(h->last_intr_timestamp +
e85c5974 5743 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5744 return;
5745
5746 /*
5747 * If we've already checked the heartbeat recently, we're ok.
5748 * This could happen if someone sends us a signal. We
5749 * otherwise don't care about signals in this thread.
5750 */
5751 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 5752 (h->heartbeat_sample_interval), now))
a0c12413
SC		 5753 return;
5754
5755 /* If heartbeat has not changed since we last looked, we're not ok. */
5756 spin_lock_irqsave(&h->lock, flags);
5757 heartbeat = readl(&h->cfgtable->HeartBeat);
5758 spin_unlock_irqrestore(&h->lock, flags);
5759 if (h->last_heartbeat == heartbeat) {
5760 controller_lockup_detected(h);
5761 return;
5762 }
5763
5764 /* We're ok. */
5765 h->last_heartbeat = heartbeat;
5766 h->last_heartbeat_timestamp = now;
5767}
5768
76438d08
SC		 5769static int hpsa_kickoff_rescan(struct ctlr_info *h)
5770{
5771 int i;
5772 char *event_type;
5773
5774 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 5775 if ((h->transMethod & (CFGTBL_Trans_io_accel1
5776 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 5777 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
5778 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
5779
5780 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
5781 event_type = "state change";
5782 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
5783 event_type = "configuration change";
5784 /* Stop sending new RAID offload reqs via the IO accelerator */
5785 scsi_block_requests(h->scsi_host);
5786 for (i = 0; i < h->ndevices; i++)
5787 h->dev[i]->offload_enabled = 0;
5788 hpsa_drain_commands(h);
5789 /* Set 'accelerator path config change' bit */
5790 dev_warn(&h->pdev->dev,
5791 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
5792 h->events, event_type);
5793 writel(h->events, &(h->cfgtable->clear_event_notify));
5794 /* Set the "clear event notify field update" bit 6 */
5795 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
5796 /* Wait until ctlr clears 'clear event notify field', bit 6 */
5797 hpsa_wait_for_clear_event_notify_ack(h);
5798 scsi_unblock_requests(h->scsi_host);
5799 } else {
5800 /* Acknowledge controller notification events. */
5801 writel(h->events, &(h->cfgtable->clear_event_notify));
5802 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
5803 hpsa_wait_for_clear_event_notify_ack(h);
5804#if 0
5805 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5806 hpsa_wait_for_mode_change_ack(h);
5807#endif
5808 }
5809
5810 /* Something in the device list may have changed to trigger
5811 * the event, so do a rescan.
5812 */
5813 hpsa_scan_start(h->scsi_host);
5814 /* release reference taken on scsi host in check_controller_events */
5815 scsi_host_put(h->scsi_host);
5816 return 0;
5817}
5818
5819/* Check a register on the controller to see if there are configuration
5820 * changes (added/changed/removed logical drives, etc.) which mean that
5821 * we should rescan the controller for devices. If so, add the controller
5822 * to the list of controllers needing to be rescanned, and gets a
5823 * reference to the associated scsi_host.
5824 */
5825static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
5826{
5827 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
5828 return;
5829
5830 h->events = readl(&(h->cfgtable->event_notify));
5831 if (!h->events)
5832 return;
5833
5834 /*
5835 * Take a reference on scsi host for the duration of the scan
5836 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
5837 * as only a single thread accesses this list.
5838 */
5839 scsi_host_get(h->scsi_host);
5840 hpsa_kickoff_rescan(h);
5841}
5842
8a98db73 5843static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 5844{
5845 unsigned long flags;
8a98db73
SC		 5846 struct ctlr_info *h = container_of(to_delayed_work(work),
5847 struct ctlr_info, monitor_ctlr_work);
5848 detect_controller_lockup(h);
5849 if (h->lockup_detected)
5850 return;
76438d08 5851 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 5852 spin_lock_irqsave(&h->lock, flags);
5853 if (h->remove_in_progress) {
5854 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5855 return;
5856 }
8a98db73
SC		 5857 schedule_delayed_work(&h->monitor_ctlr_work,
5858 h->heartbeat_sample_interval);
5859 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 5860}
5861
6f039790 5862static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 5863{
4c2a8c40 5864 int dac, rc;
edd16368 5865 struct ctlr_info *h;
64670ac8
SC		 5866 int try_soft_reset = 0;
5867 unsigned long flags;
edd16368
SC		 5868
5869 if (number_of_controllers == 0)
5870 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 5871
4c2a8c40 5872 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 5873 if (rc) {
5874 if (rc != -ENOTSUPP)
5875 return rc;
5876 /* If the reset fails in a particular way (it has no way to do
5877 * a proper hard reset, so returns -ENOTSUPP) we can try to do
5878 * a soft reset once we get the controller configured up to the
5879 * point that it can accept a command.
5880 */
5881 try_soft_reset = 1;
5882 rc = 0;
5883 }
5884
5885reinit_after_soft_reset:
edd16368 5886
303932fd
DB		 5887 /* Command structures must be aligned on a 32-byte boundary because
5888 * the 5 lower bits of the address are used by the hardware. and by
5889 * the driver. See comments in hpsa.h for more info.
5890 */
283b4a9b 5891#define COMMANDLIST_ALIGNMENT 128
303932fd 5892 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 5893 h = kzalloc(sizeof(*h), GFP_KERNEL);
5894 if (!h)
ecd9aad4 5895 return -ENOMEM;
edd16368 5896
55c06c71 5897 h->pdev = pdev;
a9a3a273 5898 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 5899 INIT_LIST_HEAD(&h->cmpQ);
5900 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 5901 spin_lock_init(&h->lock);
5902 spin_lock_init(&h->scan_lock);
0390f0c0 5903 spin_lock_init(&h->passthru_count_lock);
55c06c71 5904 rc = hpsa_pci_init(h);
ecd9aad4 5905 if (rc != 0)
edd16368
SC		 5906 goto clean1;
5907
f79cfec6 5908 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 5909 h->ctlr = number_of_controllers;
5910 number_of_controllers++;
edd16368
SC		 5911
5912 /* configure PCI DMA stuff */
ecd9aad4
SC		 5913 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
5914 if (rc == 0) {
edd16368 5915 dac = 1;
ecd9aad4
SC		 5916 } else {
5917 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5918 if (rc == 0) {
5919 dac = 0;
5920 } else {
5921 dev_err(&pdev->dev, "no suitable DMA available\n");
5922 goto clean1;
5923 }
edd16368
SC		 5924 }
5925
5926 /* make sure the board interrupts are off */
5927 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 5928
0ae01a32 5929 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 5930 goto clean2;
303932fd
DB		 5931 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
5932 h->devname, pdev->device,
a9a3a273 5933 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 5934 if (hpsa_allocate_cmd_pool(h))
edd16368 5935 goto clean4;
33a2ffce
SC		 5936 if (hpsa_allocate_sg_chain_blocks(h))
5937 goto clean4;
a08a8471
SC		 5938 init_waitqueue_head(&h->scan_wait_queue);
5939 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 5940
5941 pci_set_drvdata(pdev, h);
9a41338e
SC		 5942 h->ndevices = 0;
5943 h->scsi_host = NULL;
5944 spin_lock_init(&h->devlock);
64670ac8
SC		 5945 hpsa_put_ctlr_into_performant_mode(h);
5946
5947 /* At this point, the controller is ready to take commands.
5948 * Now, if reset_devices and the hard reset didn't work, try
5949 * the soft reset and see if that works.
5950 */
5951 if (try_soft_reset) {
5952
5953 /* This is kind of gross. We may or may not get a completion
5954 * from the soft reset command, and if we do, then the value
5955 * from the fifo may or may not be valid. So, we wait 10 secs
5956 * after the reset throwing away any completions we get during
5957 * that time. Unregister the interrupt handler and register
5958 * fake ones to scoop up any residual completions.
5959 */
5960 spin_lock_irqsave(&h->lock, flags);
5961 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5962 spin_unlock_irqrestore(&h->lock, flags);
254f796b 5963 free_irqs(h);
64670ac8
SC		 5964 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
5965 hpsa_intx_discard_completions);
5966 if (rc) {
5967 dev_warn(&h->pdev->dev, "Failed to request_irq after "
5968 "soft reset.\n");
5969 goto clean4;
5970 }
5971
5972 rc = hpsa_kdump_soft_reset(h);
5973 if (rc)
5974 /* Neither hard nor soft reset worked, we're hosed. */
5975 goto clean4;
5976
5977 dev_info(&h->pdev->dev, "Board READY.\n");
5978 dev_info(&h->pdev->dev,
5979 "Waiting for stale completions to drain.\n");
5980 h->access.set_intr_mask(h, HPSA_INTR_ON);
5981 msleep(10000);
5982 h->access.set_intr_mask(h, HPSA_INTR_OFF);
5983
5984 rc = controller_reset_failed(h->cfgtable);
5985 if (rc)
5986 dev_info(&h->pdev->dev,
5987 "Soft reset appears to have failed.\n");
5988
5989 /* since the controller's reset, we have to go back and re-init
5990 * everything. Easiest to just forget what we've done and do it
5991 * all over again.
5992 */
5993 hpsa_undo_allocations_after_kdump_soft_reset(h);
5994 try_soft_reset = 0;
5995 if (rc)
5996 /* don't go to clean4, we already unallocated */
5997 return -ENODEV;
5998
5999 goto reinit_after_soft_reset;
6000 }
edd16368
SC		 6001
6002 /* Turn the interrupts on so we can service requests */
6003 h->access.set_intr_mask(h, HPSA_INTR_ON);
6004
339b2b14 6005 hpsa_hba_inquiry(h);
edd16368 6006 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6007
6008 /* Monitor the controller for firmware lockups */
6009 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6010 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6011 schedule_delayed_work(&h->monitor_ctlr_work,
6012 h->heartbeat_sample_interval);
88bf6d62 6013 return 0;
edd16368
SC		 6014
6015clean4:
33a2ffce 6016 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6017 hpsa_free_cmd_pool(h);
254f796b 6018 free_irqs(h);
edd16368
SC		 6019clean2:
6020clean1:
edd16368 6021 kfree(h);
ecd9aad4 6022 return rc;
edd16368
SC		 6023}
6024
6025static void hpsa_flush_cache(struct ctlr_info *h)
6026{
6027 char *flush_buf;
6028 struct CommandList *c;
702890e3
SC		 6029 unsigned long flags;
6030
6031 /* Don't bother trying to flush the cache if locked up */
6032 spin_lock_irqsave(&h->lock, flags);
6033 if (unlikely(h->lockup_detected)) {
6034 spin_unlock_irqrestore(&h->lock, flags);
6035 return;
6036 }
6037 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6038
6039 flush_buf = kzalloc(4, GFP_KERNEL);
6040 if (!flush_buf)
6041 return;
6042
6043 c = cmd_special_alloc(h);
6044 if (!c) {
6045 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6046 goto out_of_memory;
6047 }
a2dac136
SC		 6048 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6049 RAID_CTLR_LUNID, TYPE_CMD)) {
6050 goto out;
6051 }
edd16368
SC		 6052 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6053 if (c->err_info->CommandStatus != 0)
a2dac136 6054out:
edd16368
SC		 6055 dev_warn(&h->pdev->dev,
6056 "error flushing cache on controller\n");
6057 cmd_special_free(h, c);
6058out_of_memory:
6059 kfree(flush_buf);
6060}
6061
6062static void hpsa_shutdown(struct pci_dev *pdev)
6063{
6064 struct ctlr_info *h;
6065
6066 h = pci_get_drvdata(pdev);
6067 /* Turn board interrupts off and send the flush cache command
6068 * sendcmd will turn off interrupt, and send the flush...
6069 * To write all data in the battery backed cache to disks
6070 */
6071 hpsa_flush_cache(h);
6072 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6073 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6074}
6075
6f039790 6076static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6077{
6078 int i;
6079
6080 for (i = 0; i < h->ndevices; i++)
6081 kfree(h->dev[i]);
6082}
6083
6f039790 6084static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6085{
6086 struct ctlr_info *h;
8a98db73 6087 unsigned long flags;
edd16368
SC		 6088
6089 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6090 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6091 return;
6092 }
6093 h = pci_get_drvdata(pdev);
8a98db73
SC		 6094
6095 /* Get rid of any controller monitoring work items */
6096 spin_lock_irqsave(&h->lock, flags);
6097 h->remove_in_progress = 1;
6098 cancel_delayed_work(&h->monitor_ctlr_work);
6099 spin_unlock_irqrestore(&h->lock, flags);
6100
edd16368
SC		 6101 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6102 hpsa_shutdown(pdev);
6103 iounmap(h->vaddr);
204892e9
SC		 6104 iounmap(h->transtable);
6105 iounmap(h->cfgtable);
55e14e76 6106 hpsa_free_device_info(h);
33a2ffce 6107 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6108 pci_free_consistent(h->pdev,
6109 h->nr_cmds * sizeof(struct CommandList),
6110 h->cmd_pool, h->cmd_pool_dhandle);
6111 pci_free_consistent(h->pdev,
6112 h->nr_cmds * sizeof(struct ErrorInfo),
6113 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6114 pci_free_consistent(h->pdev, h->reply_pool_size,
6115 h->reply_pool, h->reply_pool_dhandle);
edd16368 6116 kfree(h->cmd_pool_bits);
303932fd 6117 kfree(h->blockFetchTable);
e1f7de0c 6118 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6119 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6120 kfree(h->hba_inquiry_data);
f0bd0b68 6121 pci_disable_device(pdev);
edd16368 6122 pci_release_regions(pdev);
edd16368
SC		 6123 kfree(h);
6124}
6125
6126static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6127 __attribute__((unused)) pm_message_t state)
6128{
6129 return -ENOSYS;
6130}
6131
6132static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6133{
6134 return -ENOSYS;
6135}
6136
6137static struct pci_driver hpsa_pci_driver = {
f79cfec6 6138 .name = HPSA,
edd16368 6139 .probe = hpsa_init_one,
6f039790 6140 .remove = hpsa_remove_one,
edd16368
SC		 6141 .id_table = hpsa_pci_device_id, /* id_table */
6142 .shutdown = hpsa_shutdown,
6143 .suspend = hpsa_suspend,
6144 .resume = hpsa_resume,
6145};
6146
303932fd
DB		 6147/* Fill in bucket_map[], given nsgs (the max number of
6148 * scatter gather elements supported) and bucket[],
6149 * which is an array of 8 integers. The bucket[] array
6150 * contains 8 different DMA transfer sizes (in 16
6151 * byte increments) which the controller uses to fetch
6152 * commands. This function fills in bucket_map[], which
6153 * maps a given number of scatter gather elements to one of
6154 * the 8 DMA transfer sizes. The point of it is to allow the
6155 * controller to only do as much DMA as needed to fetch the
6156 * command, with the DMA transfer size encoded in the lower
6157 * bits of the command address.
6158 */
6159static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6160 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6161{
6162 int i, j, b, size;
6163
303932fd
DB		 6164 /* Note, bucket_map must have nsgs+1 entries. */
6165 for (i = 0; i <= nsgs; i++) {
6166 /* Compute size of a command with i SG entries */
e1f7de0c 6167 size = i + min_blocks;
303932fd
DB		 6168 b = num_buckets; /* Assume the biggest bucket */
6169 /* Find the bucket that is just big enough */
e1f7de0c 6170 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6171 if (bucket[j] >= size) {
6172 b = j;
6173 break;
6174 }
6175 }
6176 /* for a command with i SG entries, use bucket b. */
6177 bucket_map[i] = b;
6178 }
6179}
6180
e1f7de0c 6181static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6182{
6c311b57
SC		 6183 int i;
6184 unsigned long register_value;
e1f7de0c
MG		 6185 unsigned long transMethod = CFGTBL_Trans_Performant |
6186 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6187 CFGTBL_Trans_enable_directed_msix |
6188 (trans_support & (CFGTBL_Trans_io_accel1 |
6189 CFGTBL_Trans_io_accel2));
e1f7de0c 6190 struct access_method access = SA5_performant_access;
def342bd
SC		 6191
6192 /* This is a bit complicated. There are 8 registers on
6193 * the controller which we write to to tell it 8 different
6194 * sizes of commands which there may be. It's a way of
6195 * reducing the DMA done to fetch each command. Encoded into
6196 * each command's tag are 3 bits which communicate to the controller
6197 * which of the eight sizes that command fits within. The size of
6198 * each command depends on how many scatter gather entries there are.
6199 * Each SG entry requires 16 bytes. The eight registers are programmed
6200 * with the number of 16-byte blocks a command of that size requires.
6201 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6202 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6203 * blocks. Note, this only extends to the SG entries contained
6204 * within the command block, and does not extend to chained blocks
6205 * of SG elements. bft[] contains the eight values we write to
6206 * the registers. They are not evenly distributed, but have more
6207 * sizes for small commands, and fewer sizes for larger commands.
6208 */
d66ae08b 6209 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6210#define MIN_IOACCEL2_BFT_ENTRY 5
6211#define HPSA_IOACCEL2_HEADER_SZ 4
6212 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6213 13, 14, 15, 16, 17, 18, 19,
6214 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6215 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6216 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6217 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6218 16 * MIN_IOACCEL2_BFT_ENTRY);
6219 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6220 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6221 /* 5 = 1 s/g entry or 4k
6222 * 6 = 2 s/g entry or 8k
6223 * 8 = 4 s/g entry or 16k
6224 * 10 = 6 s/g entry or 24k
6225 */
303932fd 6226
303932fd
DB		 6227 /* Controller spec: zero out this buffer. */
6228 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6229
d66ae08b
SC		 6230 bft[7] = SG_ENTRIES_IN_CMD + 4;
6231 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6232 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6233 for (i = 0; i < 8; i++)
6234 writel(bft[i], &h->transtable->BlockFetch[i]);
6235
6236 /* size of controller ring buffer */
6237 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6238 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6239 writel(0, &h->transtable->RepQCtrAddrLow32);
6240 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6241
6242 for (i = 0; i < h->nreply_queues; i++) {
6243 writel(0, &h->transtable->RepQAddr[i].upper);
6244 writel(h->reply_pool_dhandle +
6245 (h->max_commands * sizeof(u64) * i),
6246 &h->transtable->RepQAddr[i].lower);
6247 }
6248
b9af4937 6249 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6250 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6251 /*
6252 * enable outbound interrupt coalescing in accelerator mode;
6253 */
6254 if (trans_support & CFGTBL_Trans_io_accel1) {
6255 access = SA5_ioaccel_mode1_access;
6256 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6257 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6258 } else {
6259 if (trans_support & CFGTBL_Trans_io_accel2) {
6260 access = SA5_ioaccel_mode2_access;
6261 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6262 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6263 }
e1f7de0c 6264 }
303932fd 6265 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6266 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6267 register_value = readl(&(h->cfgtable->TransportActive));
6268 if (!(register_value & CFGTBL_Trans_Performant)) {
6269 dev_warn(&h->pdev->dev, "unable to get board into"
6270 " performant mode\n");
6271 return;
6272 }
960a30e7 6273 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6274 h->access = access;
6275 h->transMethod = transMethod;
6276
b9af4937
SC		 6277 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6278 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6279 return;
6280
b9af4937
SC		 6281 if (trans_support & CFGTBL_Trans_io_accel1) {
6282 /* Set up I/O accelerator mode */
6283 for (i = 0; i < h->nreply_queues; i++) {
6284 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6285 h->reply_queue[i].current_entry =
6286 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6287 }
6288 bft[7] = h->ioaccel_maxsg + 8;
6289 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6290 h->ioaccel1_blockFetchTable);
e1f7de0c 6291
b9af4937
SC		 6292 /* initialize all reply queue entries to unused */
6293 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6294 h->reply_pool_size);
e1f7de0c 6295
b9af4937
SC		 6296 /* set all the constant fields in the accelerator command
6297 * frames once at init time to save CPU cycles later.
6298 */
6299 for (i = 0; i < h->nr_cmds; i++) {
6300 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6301
6302 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6303 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6304 (i * sizeof(struct ErrorInfo)));
6305 cp->err_info_len = sizeof(struct ErrorInfo);
6306 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6307 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6308 cp->timeout_sec = 0;
6309 cp->ReplyQueue = 0;
6310 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6311 DIRECT_LOOKUP_BIT;
6312 cp->Tag.upper = 0;
6313 cp->host_addr.lower =
6314 (u32) (h->ioaccel_cmd_pool_dhandle +
6315 (i * sizeof(struct io_accel1_cmd)));
6316 cp->host_addr.upper = 0;
6317 }
6318 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6319 u64 cfg_offset, cfg_base_addr_index;
6320 u32 bft2_offset, cfg_base_addr;
6321 int rc;
6322
6323 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6324 &cfg_base_addr_index, &cfg_offset);
6325 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6326 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6327 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6328 4, h->ioaccel2_blockFetchTable);
6329 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6330 BUILD_BUG_ON(offsetof(struct CfgTable,
6331 io_accel_request_size_offset) != 0xb8);
6332 h->ioaccel2_bft2_regs =
6333 remap_pci_mem(pci_resource_start(h->pdev,
6334 cfg_base_addr_index) +
6335 cfg_offset + bft2_offset,
6336 ARRAY_SIZE(bft2) *
6337 sizeof(*h->ioaccel2_bft2_regs));
6338 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6339 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6340 }
b9af4937
SC		 6341 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6342 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6343}
6344
6345static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6346{
283b4a9b
SC		 6347 h->ioaccel_maxsg =
6348 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6349 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6350 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6351
e1f7de0c
MG		 6352 /* Command structures must be aligned on a 128-byte boundary
6353 * because the 7 lower bits of the address are used by the
6354 * hardware.
6355 */
6356#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6357 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6358 IOACCEL1_COMMANDLIST_ALIGNMENT);
6359 h->ioaccel_cmd_pool =
6360 pci_alloc_consistent(h->pdev,
6361 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6362 &(h->ioaccel_cmd_pool_dhandle));
6363
6364 h->ioaccel1_blockFetchTable =
283b4a9b 6365 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6366 sizeof(u32)), GFP_KERNEL);
6367
6368 if ((h->ioaccel_cmd_pool == NULL) ||
6369 (h->ioaccel1_blockFetchTable == NULL))
6370 goto clean_up;
6371
6372 memset(h->ioaccel_cmd_pool, 0,
6373 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6374 return 0;
6375
6376clean_up:
6377 if (h->ioaccel_cmd_pool)
6378 pci_free_consistent(h->pdev,
6379 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6380 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6381 kfree(h->ioaccel1_blockFetchTable);
6382 return 1;
6c311b57
SC		 6383}
6384
aca9012a
SC		 6385static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6386{
6387 /* Allocate ioaccel2 mode command blocks and block fetch table */
6388
6389 h->ioaccel_maxsg =
6390 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6391 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6392 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6393
6394#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6395 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6396 IOACCEL2_COMMANDLIST_ALIGNMENT);
6397 h->ioaccel2_cmd_pool =
6398 pci_alloc_consistent(h->pdev,
6399 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6400 &(h->ioaccel2_cmd_pool_dhandle));
6401
6402 h->ioaccel2_blockFetchTable =
6403 kmalloc(((h->ioaccel_maxsg + 1) *
6404 sizeof(u32)), GFP_KERNEL);
6405
6406 if ((h->ioaccel2_cmd_pool == NULL) ||
6407 (h->ioaccel2_blockFetchTable == NULL))
6408 goto clean_up;
6409
6410 memset(h->ioaccel2_cmd_pool, 0,
6411 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
6412 return 0;
6413
6414clean_up:
6415 if (h->ioaccel2_cmd_pool)
6416 pci_free_consistent(h->pdev,
6417 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6418 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
6419 kfree(h->ioaccel2_blockFetchTable);
6420 return 1;
6421}
6422
6f039790 6423static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 6424{
6425 u32 trans_support;
e1f7de0c
MG		 6426 unsigned long transMethod = CFGTBL_Trans_Performant |
6427 CFGTBL_Trans_use_short_tags;
254f796b 6428 int i;
6c311b57 6429
02ec19c8
SC		 6430 if (hpsa_simple_mode)
6431 return;
6432
e1f7de0c
MG		 6433 /* Check for I/O accelerator mode support */
6434 if (trans_support & CFGTBL_Trans_io_accel1) {
6435 transMethod |= CFGTBL_Trans_io_accel1 |
6436 CFGTBL_Trans_enable_directed_msix;
6437 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
6438 goto clean_up;
aca9012a
SC		 6439 } else {
6440 if (trans_support & CFGTBL_Trans_io_accel2) {
6441 transMethod |= CFGTBL_Trans_io_accel2 |
6442 CFGTBL_Trans_enable_directed_msix;
6443 if (ioaccel2_alloc_cmds_and_bft(h))
6444 goto clean_up;
6445 }
e1f7de0c
MG		 6446 }
6447
6448 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 6449 trans_support = readl(&(h->cfgtable->TransportSupport));
6450 if (!(trans_support & PERFORMANT_MODE))
6451 return;
6452
eee0f03a 6453 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 6454 hpsa_get_max_perf_mode_cmds(h);
6c311b57 6455 /* Performant mode ring buffer and supporting data structures */
254f796b 6456 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 6457 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
6458 &(h->reply_pool_dhandle));
6459
254f796b
MG		 6460 for (i = 0; i < h->nreply_queues; i++) {
6461 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
6462 h->reply_queue[i].size = h->max_commands;
6463 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
6464 h->reply_queue[i].current_entry = 0;
6465 }
6466
6c311b57 6467 /* Need a block fetch table for performant mode */
d66ae08b 6468 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 6469 sizeof(u32)), GFP_KERNEL);
6470
6471 if ((h->reply_pool == NULL)
6472 || (h->blockFetchTable == NULL))
6473 goto clean_up;
6474
e1f7de0c 6475 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 6476 return;
6477
6478clean_up:
6479 if (h->reply_pool)
6480 pci_free_consistent(h->pdev, h->reply_pool_size,
6481 h->reply_pool, h->reply_pool_dhandle);
6482 kfree(h->blockFetchTable);
6483}
6484
76438d08
SC		 6485static void hpsa_drain_commands(struct ctlr_info *h)
6486{
6487 int cmds_out;
6488 unsigned long flags;
6489
6490 do { /* wait for all outstanding commands to drain out */
6491 spin_lock_irqsave(&h->lock, flags);
6492 cmds_out = h->commands_outstanding;
6493 spin_unlock_irqrestore(&h->lock, flags);
6494 if (cmds_out <= 0)
6495 break;
6496 msleep(100);
6497 } while (1);
6498}
6499
edd16368
SC		 6500/*
6501 * This is it. Register the PCI driver information for the cards we control
6502 * the OS will call our registered routines when it finds one of our cards.
6503 */
6504static int __init hpsa_init(void)
6505{
31468401 6506 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 6507}
6508
6509static void __exit hpsa_cleanup(void)
6510{
6511 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 6512}
6513
e1f7de0c
MG		 6514static void __attribute__((unused)) verify_offsets(void)
6515{
b66cc250
MM		 6516#define VERIFY_OFFSET(member, offset) \
6517 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
6518
6519 VERIFY_OFFSET(IU_type, 0);
6520 VERIFY_OFFSET(direction, 1);
6521 VERIFY_OFFSET(reply_queue, 2);
6522 /* VERIFY_OFFSET(reserved1, 3); */
6523 VERIFY_OFFSET(scsi_nexus, 4);
6524 VERIFY_OFFSET(Tag, 8);
6525 VERIFY_OFFSET(cdb, 16);
6526 VERIFY_OFFSET(cciss_lun, 32);
6527 VERIFY_OFFSET(data_len, 40);
6528 VERIFY_OFFSET(cmd_priority_task_attr, 44);
6529 VERIFY_OFFSET(sg_count, 45);
6530 /* VERIFY_OFFSET(reserved3 */
6531 VERIFY_OFFSET(err_ptr, 48);
6532 VERIFY_OFFSET(err_len, 56);
6533 /* VERIFY_OFFSET(reserved4 */
6534 VERIFY_OFFSET(sg, 64);
6535
6536#undef VERIFY_OFFSET
6537
e1f7de0c
MG		 6538#define VERIFY_OFFSET(member, offset) \
6539 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
6540
6541 VERIFY_OFFSET(dev_handle, 0x00);
6542 VERIFY_OFFSET(reserved1, 0x02);
6543 VERIFY_OFFSET(function, 0x03);
6544 VERIFY_OFFSET(reserved2, 0x04);
6545 VERIFY_OFFSET(err_info, 0x0C);
6546 VERIFY_OFFSET(reserved3, 0x10);
6547 VERIFY_OFFSET(err_info_len, 0x12);
6548 VERIFY_OFFSET(reserved4, 0x13);
6549 VERIFY_OFFSET(sgl_offset, 0x14);
6550 VERIFY_OFFSET(reserved5, 0x15);
6551 VERIFY_OFFSET(transfer_len, 0x1C);
6552 VERIFY_OFFSET(reserved6, 0x20);
6553 VERIFY_OFFSET(io_flags, 0x24);
6554 VERIFY_OFFSET(reserved7, 0x26);
6555 VERIFY_OFFSET(LUN, 0x34);
6556 VERIFY_OFFSET(control, 0x3C);
6557 VERIFY_OFFSET(CDB, 0x40);
6558 VERIFY_OFFSET(reserved8, 0x50);
6559 VERIFY_OFFSET(host_context_flags, 0x60);
6560 VERIFY_OFFSET(timeout_sec, 0x62);
6561 VERIFY_OFFSET(ReplyQueue, 0x64);
6562 VERIFY_OFFSET(reserved9, 0x65);
6563 VERIFY_OFFSET(Tag, 0x68);
6564 VERIFY_OFFSET(host_addr, 0x70);
6565 VERIFY_OFFSET(CISS_LUN, 0x78);
6566 VERIFY_OFFSET(SG, 0x78 + 8);
6567#undef VERIFY_OFFSET
6568}
6569
edd16368
SC		 6570module_init(hpsa_init);
6571module_exit(hpsa_cleanup);
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