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hpsa: add more ioaccel2 error handling, including underrun statuses.
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
59/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 60#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 61#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 62#define HPSA "hpsa"
edd16368 63
007e7aa9
RE		 64/* How long to wait for CISS doorbell communication */
65#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
66#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
67#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
68#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 69#define MAX_IOCTL_CONFIG_WAIT 1000
70
71/*define how many times we will try a command because of bus resets */
72#define MAX_CMD_RETRIES 3
73
74/* Embedded module documentation macros - see modules.h */
75MODULE_AUTHOR("Hewlett-Packard Company");
76MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
77 HPSA_DRIVER_VERSION);
78MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
79MODULE_VERSION(HPSA_DRIVER_VERSION);
80MODULE_LICENSE("GPL");
81
82static int hpsa_allow_any;
83module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_allow_any,
85 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 86static int hpsa_simple_mode;
87module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
88MODULE_PARM_DESC(hpsa_simple_mode,
89 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 90
91/* define the PCI info for the cards we can control */
92static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 133 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
137 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 138 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 139 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 140 {0,}
141};
142
143MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
144
145/* board_id = Subsystem Device ID & Vendor ID
146 * product = Marketing Name for the board
147 * access = Address of the struct of function pointers
148 */
149static struct board_type products[] = {
edd16368
SC		 150 {0x3241103C, "Smart Array P212", &SA5_access},
151 {0x3243103C, "Smart Array P410", &SA5_access},
152 {0x3245103C, "Smart Array P410i", &SA5_access},
153 {0x3247103C, "Smart Array P411", &SA5_access},
154 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 155 {0x324A103C, "Smart Array P712m", &SA5_access},
156 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 157 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 158 {0x3350103C, "Smart Array P222", &SA5_access},
159 {0x3351103C, "Smart Array P420", &SA5_access},
160 {0x3352103C, "Smart Array P421", &SA5_access},
161 {0x3353103C, "Smart Array P822", &SA5_access},
162 {0x3354103C, "Smart Array P420i", &SA5_access},
163 {0x3355103C, "Smart Array P220i", &SA5_access},
164 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 165 {0x1921103C, "Smart Array P830i", &SA5_access},
166 {0x1922103C, "Smart Array P430", &SA5_access},
167 {0x1923103C, "Smart Array P431", &SA5_access},
168 {0x1924103C, "Smart Array P830", &SA5_access},
169 {0x1926103C, "Smart Array P731m", &SA5_access},
170 {0x1928103C, "Smart Array P230i", &SA5_access},
171 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 172 {0x21BD103C, "Smart Array P244br", &SA5_access},
173 {0x21BE103C, "Smart Array P741m", &SA5_access},
174 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
175 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 176 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 177 {0x21C2103C, "Smart Array P440", &SA5_access},
178 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 179 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 180 {0x21C5103C, "Smart Array P841", &SA5_access},
181 {0x21C6103C, "Smart HBA H244br", &SA5_access},
182 {0x21C7103C, "Smart HBA H240", &SA5_access},
183 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 184 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 185 {0x21CA103C, "Smart Array P246br", &SA5_access},
186 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 187 {0x21CC103C, "Smart Array", &SA5_access},
188 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 189 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 190 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
191 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
192 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
193 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
194 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 195 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
196};
197
198static int number_of_controllers;
199
10f66018
SC		 200static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
201static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 202static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 203
204#ifdef CONFIG_COMPAT
42a91641
DB		 205static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
206 void __user *arg);
edd16368
SC		 207#endif
208
209static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 210static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 211static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 212 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 213 int cmd_type);
2c143342 214static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 215#define VPD_PAGE (1 << 8)
edd16368 216
f281233d 217static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 218static void hpsa_scan_start(struct Scsi_Host *);
219static int hpsa_scan_finished(struct Scsi_Host *sh,
220 unsigned long elapsed_time);
7c0a0229 221static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 222
223static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 224static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 225static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 226static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 227static void hpsa_slave_destroy(struct scsi_device *sdev);
228
edd16368 229static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 230static int check_for_unit_attention(struct ctlr_info *h,
231 struct CommandList *c);
232static void check_ioctl_unit_attention(struct ctlr_info *h,
233 struct CommandList *c);
303932fd
DB		 234/* performant mode helper functions */
235static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 236 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 237static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
1fb7c98a
RE		 238static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h);
239static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h);
254f796b 240static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 241static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
242 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
243 u64 *cfg_offset);
244static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
245 unsigned long *memory_bar);
246static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
247static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
248 int wait_for_ready);
75167d2c 249static inline void finish_cmd(struct CommandList *c);
c706a795 250static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 251#define BOARD_NOT_READY 0
252#define BOARD_READY 1
23100dd9 253static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 254static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 255static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
256 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 257 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 258static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 259static u32 lockup_detected(struct ctlr_info *h);
260static int detect_controller_lockup(struct ctlr_info *h);
edd16368 261
edd16368
SC		 262static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
263{
264 unsigned long *priv = shost_priv(sdev->host);
265 return (struct ctlr_info *) *priv;
266}
267
a23513e8
SC		 268static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
269{
270 unsigned long *priv = shost_priv(sh);
271 return (struct ctlr_info *) *priv;
272}
273
9437ac43
SC		 274/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
275static void decode_sense_data(const u8 *sense_data, int sense_data_len,
276 u8 *sense_key, u8 *asc, u8 *ascq)
277{
278 struct scsi_sense_hdr sshdr;
279 bool rc;
280
281 *sense_key = -1;
282 *asc = -1;
283 *ascq = -1;
284
285 if (sense_data_len < 1)
286 return;
287
288 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
289 if (rc) {
290 *sense_key = sshdr.sense_key;
291 *asc = sshdr.asc;
292 *ascq = sshdr.ascq;
293 }
294}
295
edd16368
SC		 296static int check_for_unit_attention(struct ctlr_info *h,
297 struct CommandList *c)
298{
9437ac43
SC		 299 u8 sense_key, asc, ascq;
300 int sense_len;
301
302 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
303 sense_len = sizeof(c->err_info->SenseInfo);
304 else
305 sense_len = c->err_info->SenseLen;
306
307 decode_sense_data(c->err_info->SenseInfo, sense_len,
308 &sense_key, &asc, &ascq);
309 if (sense_key != UNIT_ATTENTION || asc == -1)
edd16368
SC		 310 return 0;
311
9437ac43 312 switch (asc) {
edd16368 313 case STATE_CHANGED:
9437ac43
SC		 314 dev_warn(&h->pdev->dev,
315 HPSA "%d: a state change detected, command retried\n",
316 h->ctlr);
edd16368
SC		 317 break;
318 case LUN_FAILED:
7f73695a
SC		 319 dev_warn(&h->pdev->dev,
320 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 321 break;
322 case REPORT_LUNS_CHANGED:
7f73695a
SC		 323 dev_warn(&h->pdev->dev,
324 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 325 /*
4f4eb9f1
ST		 326 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
327 * target (array) devices.
edd16368
SC		 328 */
329 break;
330 case POWER_OR_RESET:
f79cfec6 331 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 332 "or device reset detected\n", h->ctlr);
333 break;
334 case UNIT_ATTENTION_CLEARED:
f79cfec6 335 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 336 "cleared by another initiator\n", h->ctlr);
337 break;
338 default:
f79cfec6 339 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 340 "unit attention detected\n", h->ctlr);
341 break;
342 }
343 return 1;
344}
345
852af20a
MB		 346static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
347{
348 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
349 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
350 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
351 return 0;
352 dev_warn(&h->pdev->dev, HPSA "device busy");
353 return 1;
354}
355
e985c58f
SC		 356static u32 lockup_detected(struct ctlr_info *h);
357static ssize_t host_show_lockup_detected(struct device *dev,
358 struct device_attribute *attr, char *buf)
359{
360 int ld;
361 struct ctlr_info *h;
362 struct Scsi_Host *shost = class_to_shost(dev);
363
364 h = shost_to_hba(shost);
365 ld = lockup_detected(h);
366
367 return sprintf(buf, "ld=%d\n", ld);
368}
369
da0697bd
ST		 370static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
371 struct device_attribute *attr,
372 const char *buf, size_t count)
373{
374 int status, len;
375 struct ctlr_info *h;
376 struct Scsi_Host *shost = class_to_shost(dev);
377 char tmpbuf[10];
378
379 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
380 return -EACCES;
381 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
382 strncpy(tmpbuf, buf, len);
383 tmpbuf[len] = '\0';
384 if (sscanf(tmpbuf, "%d", &status) != 1)
385 return -EINVAL;
386 h = shost_to_hba(shost);
387 h->acciopath_status = !!status;
388 dev_warn(&h->pdev->dev,
389 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
390 h->acciopath_status ? "enabled" : "disabled");
391 return count;
392}
393
2ba8bfc8
SC		 394static ssize_t host_store_raid_offload_debug(struct device *dev,
395 struct device_attribute *attr,
396 const char *buf, size_t count)
397{
398 int debug_level, len;
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401 char tmpbuf[10];
402
403 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
404 return -EACCES;
405 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
406 strncpy(tmpbuf, buf, len);
407 tmpbuf[len] = '\0';
408 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
409 return -EINVAL;
410 if (debug_level < 0)
411 debug_level = 0;
412 h = shost_to_hba(shost);
413 h->raid_offload_debug = debug_level;
414 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
415 h->raid_offload_debug);
416 return count;
417}
418
edd16368
SC		 419static ssize_t host_store_rescan(struct device *dev,
420 struct device_attribute *attr,
421 const char *buf, size_t count)
422{
423 struct ctlr_info *h;
424 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 425 h = shost_to_hba(shost);
31468401 426 hpsa_scan_start(h->scsi_host);
edd16368
SC		 427 return count;
428}
429
d28ce020
SC		 430static ssize_t host_show_firmware_revision(struct device *dev,
431 struct device_attribute *attr, char *buf)
432{
433 struct ctlr_info *h;
434 struct Scsi_Host *shost = class_to_shost(dev);
435 unsigned char *fwrev;
436
437 h = shost_to_hba(shost);
438 if (!h->hba_inquiry_data)
439 return 0;
440 fwrev = &h->hba_inquiry_data[32];
441 return snprintf(buf, 20, "%c%c%c%c\n",
442 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
443}
444
94a13649
SC		 445static ssize_t host_show_commands_outstanding(struct device *dev,
446 struct device_attribute *attr, char *buf)
447{
448 struct Scsi_Host *shost = class_to_shost(dev);
449 struct ctlr_info *h = shost_to_hba(shost);
450
0cbf768e
SC		 451 return snprintf(buf, 20, "%d\n",
452 atomic_read(&h->commands_outstanding));
94a13649
SC		 453}
454
745a7a25
SC		 455static ssize_t host_show_transport_mode(struct device *dev,
456 struct device_attribute *attr, char *buf)
457{
458 struct ctlr_info *h;
459 struct Scsi_Host *shost = class_to_shost(dev);
460
461 h = shost_to_hba(shost);
462 return snprintf(buf, 20, "%s\n",
960a30e7 463 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 464 "performant" : "simple");
465}
466
da0697bd
ST		 467static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
468 struct device_attribute *attr, char *buf)
469{
470 struct ctlr_info *h;
471 struct Scsi_Host *shost = class_to_shost(dev);
472
473 h = shost_to_hba(shost);
474 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
475 (h->acciopath_status == 1) ? "enabled" : "disabled");
476}
477
46380786 478/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 479static u32 unresettable_controller[] = {
480 0x324a103C, /* Smart Array P712m */
9b5c48c2 481 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 482 0x3223103C, /* Smart Array P800 */
483 0x3234103C, /* Smart Array P400 */
484 0x3235103C, /* Smart Array P400i */
485 0x3211103C, /* Smart Array E200i */
486 0x3212103C, /* Smart Array E200 */
487 0x3213103C, /* Smart Array E200i */
488 0x3214103C, /* Smart Array E200i */
489 0x3215103C, /* Smart Array E200i */
490 0x3237103C, /* Smart Array E500 */
491 0x323D103C, /* Smart Array P700m */
7af0abbc 492 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 493 0x409C0E11, /* Smart Array 6400 */
494 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 495 0x40700E11, /* Smart Array 5300 */
496 0x40820E11, /* Smart Array 532 */
497 0x40830E11, /* Smart Array 5312 */
498 0x409A0E11, /* Smart Array 641 */
499 0x409B0E11, /* Smart Array 642 */
500 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 501};
502
46380786
SC		 503/* List of controllers which cannot even be soft reset */
504static u32 soft_unresettable_controller[] = {
7af0abbc 505 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 506 0x40700E11, /* Smart Array 5300 */
507 0x40820E11, /* Smart Array 532 */
508 0x40830E11, /* Smart Array 5312 */
509 0x409A0E11, /* Smart Array 641 */
510 0x409B0E11, /* Smart Array 642 */
511 0x40910E11, /* Smart Array 6i */
46380786
SC		 512 /* Exclude 640x boards. These are two pci devices in one slot
513 * which share a battery backed cache module. One controls the
514 * cache, the other accesses the cache through the one that controls
515 * it. If we reset the one controlling the cache, the other will
516 * likely not be happy. Just forbid resetting this conjoined mess.
517 * The 640x isn't really supported by hpsa anyway.
518 */
519 0x409C0E11, /* Smart Array 6400 */
520 0x409D0E11, /* Smart Array 6400 EM */
521};
522
9b5c48c2
SC		 523static u32 needs_abort_tags_swizzled[] = {
524 0x323D103C, /* Smart Array P700m */
525 0x324a103C, /* Smart Array P712m */
526 0x324b103C, /* SmartArray P711m */
527};
528
529static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 530{
531 int i;
532
9b5c48c2
SC		 533 for (i = 0; i < nelems; i++)
534 if (a[i] == board_id)
535 return 1;
536 return 0;
46380786
SC		 537}
538
9b5c48c2 539static int ctlr_is_hard_resettable(u32 board_id)
46380786 540{
9b5c48c2
SC		 541 return !board_id_in_array(unresettable_controller,
542 ARRAY_SIZE(unresettable_controller), board_id);
543}
46380786 544
9b5c48c2
SC		 545static int ctlr_is_soft_resettable(u32 board_id)
546{
547 return !board_id_in_array(soft_unresettable_controller,
548 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 549}
550
46380786
SC		 551static int ctlr_is_resettable(u32 board_id)
552{
553 return ctlr_is_hard_resettable(board_id) ||
554 ctlr_is_soft_resettable(board_id);
555}
556
9b5c48c2
SC		 557static int ctlr_needs_abort_tags_swizzled(u32 board_id)
558{
559 return board_id_in_array(needs_abort_tags_swizzled,
560 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
561}
562
941b1cda
SC		 563static ssize_t host_show_resettable(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct Scsi_Host *shost = class_to_shost(dev);
568
569 h = shost_to_hba(shost);
46380786 570 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 571}
572
edd16368
SC		 573static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
574{
575 return (scsi3addr[3] & 0xC0) == 0x40;
576}
577
f2ef0ce7
RE		 578static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
579 "1(+0)ADM", "UNKNOWN"
edd16368 580};
6b80b18f
ST		 581#define HPSA_RAID_0 0
582#define HPSA_RAID_4 1
583#define HPSA_RAID_1 2 /* also used for RAID 10 */
584#define HPSA_RAID_5 3 /* also used for RAID 50 */
585#define HPSA_RAID_51 4
586#define HPSA_RAID_6 5 /* also used for RAID 60 */
587#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 588#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
589
590static ssize_t raid_level_show(struct device *dev,
591 struct device_attribute *attr, char *buf)
592{
593 ssize_t l = 0;
82a72c0a 594 unsigned char rlevel;
edd16368
SC		 595 struct ctlr_info *h;
596 struct scsi_device *sdev;
597 struct hpsa_scsi_dev_t *hdev;
598 unsigned long flags;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608
609 /* Is this even a logical drive? */
610 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
611 spin_unlock_irqrestore(&h->lock, flags);
612 l = snprintf(buf, PAGE_SIZE, "N/A\n");
613 return l;
614 }
615
616 rlevel = hdev->raid_level;
617 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 618 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 619 rlevel = RAID_UNKNOWN;
620 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
621 return l;
622}
623
624static ssize_t lunid_show(struct device *dev,
625 struct device_attribute *attr, char *buf)
626{
627 struct ctlr_info *h;
628 struct scsi_device *sdev;
629 struct hpsa_scsi_dev_t *hdev;
630 unsigned long flags;
631 unsigned char lunid[8];
632
633 sdev = to_scsi_device(dev);
634 h = sdev_to_hba(sdev);
635 spin_lock_irqsave(&h->lock, flags);
636 hdev = sdev->hostdata;
637 if (!hdev) {
638 spin_unlock_irqrestore(&h->lock, flags);
639 return -ENODEV;
640 }
641 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
642 spin_unlock_irqrestore(&h->lock, flags);
643 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
644 lunid[0], lunid[1], lunid[2], lunid[3],
645 lunid[4], lunid[5], lunid[6], lunid[7]);
646}
647
648static ssize_t unique_id_show(struct device *dev,
649 struct device_attribute *attr, char *buf)
650{
651 struct ctlr_info *h;
652 struct scsi_device *sdev;
653 struct hpsa_scsi_dev_t *hdev;
654 unsigned long flags;
655 unsigned char sn[16];
656
657 sdev = to_scsi_device(dev);
658 h = sdev_to_hba(sdev);
659 spin_lock_irqsave(&h->lock, flags);
660 hdev = sdev->hostdata;
661 if (!hdev) {
662 spin_unlock_irqrestore(&h->lock, flags);
663 return -ENODEV;
664 }
665 memcpy(sn, hdev->device_id, sizeof(sn));
666 spin_unlock_irqrestore(&h->lock, flags);
667 return snprintf(buf, 16 * 2 + 2,
668 "%02X%02X%02X%02X%02X%02X%02X%02X"
669 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
670 sn[0], sn[1], sn[2], sn[3],
671 sn[4], sn[5], sn[6], sn[7],
672 sn[8], sn[9], sn[10], sn[11],
673 sn[12], sn[13], sn[14], sn[15]);
674}
675
c1988684
ST		 676static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
677 struct device_attribute *attr, char *buf)
678{
679 struct ctlr_info *h;
680 struct scsi_device *sdev;
681 struct hpsa_scsi_dev_t *hdev;
682 unsigned long flags;
683 int offload_enabled;
684
685 sdev = to_scsi_device(dev);
686 h = sdev_to_hba(sdev);
687 spin_lock_irqsave(&h->lock, flags);
688 hdev = sdev->hostdata;
689 if (!hdev) {
690 spin_unlock_irqrestore(&h->lock, flags);
691 return -ENODEV;
692 }
693 offload_enabled = hdev->offload_enabled;
694 spin_unlock_irqrestore(&h->lock, flags);
695 return snprintf(buf, 20, "%d\n", offload_enabled);
696}
697
3f5eac3a
SC		 698static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
699static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
700static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
701static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 702static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
703 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 704static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
705 host_show_hp_ssd_smart_path_status,
706 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 707static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
708 host_store_raid_offload_debug);
3f5eac3a
SC		 709static DEVICE_ATTR(firmware_revision, S_IRUGO,
710 host_show_firmware_revision, NULL);
711static DEVICE_ATTR(commands_outstanding, S_IRUGO,
712 host_show_commands_outstanding, NULL);
713static DEVICE_ATTR(transport_mode, S_IRUGO,
714 host_show_transport_mode, NULL);
941b1cda
SC		 715static DEVICE_ATTR(resettable, S_IRUGO,
716 host_show_resettable, NULL);
e985c58f
SC		 717static DEVICE_ATTR(lockup_detected, S_IRUGO,
718 host_show_lockup_detected, NULL);
3f5eac3a
SC		 719
720static struct device_attribute *hpsa_sdev_attrs[] = {
721 &dev_attr_raid_level,
722 &dev_attr_lunid,
723 &dev_attr_unique_id,
c1988684 724 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 725 &dev_attr_lockup_detected,
3f5eac3a
SC		 726 NULL,
727};
728
729static struct device_attribute *hpsa_shost_attrs[] = {
730 &dev_attr_rescan,
731 &dev_attr_firmware_revision,
732 &dev_attr_commands_outstanding,
733 &dev_attr_transport_mode,
941b1cda 734 &dev_attr_resettable,
da0697bd 735 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 736 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 737 NULL,
738};
739
41ce4c35
SC		 740#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
741 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
742
3f5eac3a
SC		 743static struct scsi_host_template hpsa_driver_template = {
744 .module = THIS_MODULE,
f79cfec6
SC		 745 .name = HPSA,
746 .proc_name = HPSA,
3f5eac3a
SC		 747 .queuecommand = hpsa_scsi_queue_command,
748 .scan_start = hpsa_scan_start,
749 .scan_finished = hpsa_scan_finished,
7c0a0229 750 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 751 .this_id = -1,
752 .use_clustering = ENABLE_CLUSTERING,
75167d2c 753 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 754 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
755 .ioctl = hpsa_ioctl,
756 .slave_alloc = hpsa_slave_alloc,
41ce4c35 757 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 758 .slave_destroy = hpsa_slave_destroy,
759#ifdef CONFIG_COMPAT
760 .compat_ioctl = hpsa_compat_ioctl,
761#endif
762 .sdev_attrs = hpsa_sdev_attrs,
763 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 764 .max_sectors = 8192,
54b2b50c 765 .no_write_same = 1,
3f5eac3a
SC		 766};
767
254f796b 768static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 769{
770 u32 a;
072b0518 771 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 772
e1f7de0c
MG		 773 if (h->transMethod & CFGTBL_Trans_io_accel1)
774 return h->access.command_completed(h, q);
775
3f5eac3a 776 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 777 return h->access.command_completed(h, q);
3f5eac3a 778
254f796b
MG		 779 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
780 a = rq->head[rq->current_entry];
781 rq->current_entry++;
0cbf768e 782 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 783 } else {
784 a = FIFO_EMPTY;
785 }
786 /* Check for wraparound */
254f796b
MG		 787 if (rq->current_entry == h->max_commands) {
788 rq->current_entry = 0;
789 rq->wraparound ^= 1;
3f5eac3a
SC		 790 }
791 return a;
792}
793
c349775e
ST		 794/*
795 * There are some special bits in the bus address of the
796 * command that we have to set for the controller to know
797 * how to process the command:
798 *
799 * Normal performant mode:
800 * bit 0: 1 means performant mode, 0 means simple mode.
801 * bits 1-3 = block fetch table entry
802 * bits 4-6 = command type (== 0)
803 *
804 * ioaccel1 mode:
805 * bit 0 = "performant mode" bit.
806 * bits 1-3 = block fetch table entry
807 * bits 4-6 = command type (== 110)
808 * (command type is needed because ioaccel1 mode
809 * commands are submitted through the same register as normal
810 * mode commands, so this is how the controller knows whether
811 * the command is normal mode or ioaccel1 mode.)
812 *
813 * ioaccel2 mode:
814 * bit 0 = "performant mode" bit.
815 * bits 1-4 = block fetch table entry (note extra bit)
816 * bits 4-6 = not needed, because ioaccel2 mode has
817 * a separate special register for submitting commands.
818 */
819
25163bd5
WS		 820/*
821 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 822 * set bit 0 for pull model, bits 3-1 for block fetch
823 * register number
824 */
25163bd5
WS		 825#define DEFAULT_REPLY_QUEUE (-1)
826static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
827 int reply_queue)
3f5eac3a 828{
254f796b 829 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 830 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 831 if (unlikely(!h->msix_vector))
832 return;
833 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 834 c->Header.ReplyQueue =
804a5cb5 835 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 836 else
837 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 838 }
3f5eac3a
SC		 839}
840
c349775e 841static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 842 struct CommandList *c,
843 int reply_queue)
c349775e
ST		 844{
845 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
846
25163bd5
WS		 847 /*
848 * Tell the controller to post the reply to the queue for this
c349775e
ST		 849 * processor. This seems to give the best I/O throughput.
850 */
25163bd5
WS		 851 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
852 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
853 else
854 cp->ReplyQueue = reply_queue % h->nreply_queues;
855 /*
856 * Set the bits in the address sent down to include:
c349775e
ST		 857 * - performant mode bit (bit 0)
858 * - pull count (bits 1-3)
859 * - command type (bits 4-6)
860 */
861 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
862 IOACCEL1_BUSADDR_CMDTYPE;
863}
864
865static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 866 struct CommandList *c,
867 int reply_queue)
c349775e
ST		 868{
869 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
870
25163bd5
WS		 871 /*
872 * Tell the controller to post the reply to the queue for this
c349775e
ST		 873 * processor. This seems to give the best I/O throughput.
874 */
25163bd5
WS		 875 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
876 cp->reply_queue = smp_processor_id() % h->nreply_queues;
877 else
878 cp->reply_queue = reply_queue % h->nreply_queues;
879 /*
880 * Set the bits in the address sent down to include:
c349775e
ST		 881 * - performant mode bit not used in ioaccel mode 2
882 * - pull count (bits 0-3)
883 * - command type isn't needed for ioaccel2
884 */
885 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
886}
887
e85c5974
SC		 888static int is_firmware_flash_cmd(u8 *cdb)
889{
890 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
891}
892
893/*
894 * During firmware flash, the heartbeat register may not update as frequently
895 * as it should. So we dial down lockup detection during firmware flash. and
896 * dial it back up when firmware flash completes.
897 */
898#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
899#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
900static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
901 struct CommandList *c)
902{
903 if (!is_firmware_flash_cmd(c->Request.CDB))
904 return;
905 atomic_inc(&h->firmware_flash_in_progress);
906 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
907}
908
909static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
910 struct CommandList *c)
911{
912 if (is_firmware_flash_cmd(c->Request.CDB) &&
913 atomic_dec_and_test(&h->firmware_flash_in_progress))
914 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
915}
916
25163bd5
WS		 917static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
918 struct CommandList *c, int reply_queue)
3f5eac3a 919{
c05e8866
SC		 920 dial_down_lockup_detection_during_fw_flash(h, c);
921 atomic_inc(&h->commands_outstanding);
c349775e
ST		 922 switch (c->cmd_type) {
923 case CMD_IOACCEL1:
25163bd5 924 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 925 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 926 break;
927 case CMD_IOACCEL2:
25163bd5 928 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 929 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e
ST		 930 break;
931 default:
25163bd5 932 set_performant_mode(h, c, reply_queue);
c05e8866 933 h->access.submit_command(h, c);
c349775e 934 }
3f5eac3a
SC		 935}
936
25163bd5
WS		 937static void enqueue_cmd_and_start_io(struct ctlr_info *h,
938 struct CommandList *c)
939{
940 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
941}
942
3f5eac3a
SC		 943static inline int is_hba_lunid(unsigned char scsi3addr[])
944{
945 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
946}
947
948static inline int is_scsi_rev_5(struct ctlr_info *h)
949{
950 if (!h->hba_inquiry_data)
951 return 0;
952 if ((h->hba_inquiry_data[2] & 0x07) == 5)
953 return 1;
954 return 0;
955}
956
edd16368
SC		 957static int hpsa_find_target_lun(struct ctlr_info *h,
958 unsigned char scsi3addr[], int bus, int *target, int *lun)
959{
960 /* finds an unused bus, target, lun for a new physical device
961 * assumes h->devlock is held
962 */
963 int i, found = 0;
cfe5badc 964 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 965
263d9401 966 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 967
968 for (i = 0; i < h->ndevices; i++) {
969 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 970 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 971 }
972
263d9401
AM		 973 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
974 if (i < HPSA_MAX_DEVICES) {
975 /* *bus = 1; */
976 *target = i;
977 *lun = 0;
978 found = 1;
edd16368
SC		 979 }
980 return !found;
981}
982
0d96ef5f
WS		 983static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
984 struct hpsa_scsi_dev_t *dev, char *description)
985{
986 dev_printk(level, &h->pdev->dev,
987 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
988 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
989 description,
990 scsi_device_type(dev->devtype),
991 dev->vendor,
992 dev->model,
993 dev->raid_level > RAID_UNKNOWN ?
994 "RAID-?" : raid_label[dev->raid_level],
995 dev->offload_config ? '+' : '-',
996 dev->offload_enabled ? '+' : '-',
997 dev->expose_state);
998}
999
edd16368
SC		 1000/* Add an entry into h->dev[] array. */
1001static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1002 struct hpsa_scsi_dev_t *device,
1003 struct hpsa_scsi_dev_t *added[], int *nadded)
1004{
1005 /* assumes h->devlock is held */
1006 int n = h->ndevices;
1007 int i;
1008 unsigned char addr1[8], addr2[8];
1009 struct hpsa_scsi_dev_t *sd;
1010
cfe5badc 1011 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1012 dev_err(&h->pdev->dev, "too many devices, some will be "
1013 "inaccessible.\n");
1014 return -1;
1015 }
1016
1017 /* physical devices do not have lun or target assigned until now. */
1018 if (device->lun != -1)
1019 /* Logical device, lun is already assigned. */
1020 goto lun_assigned;
1021
1022 /* If this device a non-zero lun of a multi-lun device
1023 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1024 * unit no, zero otherwise.
edd16368
SC		 1025 */
1026 if (device->scsi3addr[4] == 0) {
1027 /* This is not a non-zero lun of a multi-lun device */
1028 if (hpsa_find_target_lun(h, device->scsi3addr,
1029 device->bus, &device->target, &device->lun) != 0)
1030 return -1;
1031 goto lun_assigned;
1032 }
1033
1034 /* This is a non-zero lun of a multi-lun device.
1035 * Search through our list and find the device which
1036 * has the same 8 byte LUN address, excepting byte 4.
1037 * Assign the same bus and target for this new LUN.
1038 * Use the logical unit number from the firmware.
1039 */
1040 memcpy(addr1, device->scsi3addr, 8);
1041 addr1[4] = 0;
1042 for (i = 0; i < n; i++) {
1043 sd = h->dev[i];
1044 memcpy(addr2, sd->scsi3addr, 8);
1045 addr2[4] = 0;
1046 /* differ only in byte 4? */
1047 if (memcmp(addr1, addr2, 8) == 0) {
1048 device->bus = sd->bus;
1049 device->target = sd->target;
1050 device->lun = device->scsi3addr[4];
1051 break;
1052 }
1053 }
1054 if (device->lun == -1) {
1055 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1056 " suspect firmware bug or unsupported hardware "
1057 "configuration.\n");
1058 return -1;
1059 }
1060
1061lun_assigned:
1062
1063 h->dev[n] = device;
1064 h->ndevices++;
1065 added[*nadded] = device;
1066 (*nadded)++;
0d96ef5f
WS		 1067 hpsa_show_dev_msg(KERN_INFO, h, device,
1068 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1069 device->offload_to_be_enabled = device->offload_enabled;
1070 device->offload_enabled = 0;
edd16368
SC		 1071 return 0;
1072}
1073
bd9244f7
ST		 1074/* Update an entry in h->dev[] array. */
1075static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1076 int entry, struct hpsa_scsi_dev_t *new_entry)
1077{
a473d86c 1078 int offload_enabled;
bd9244f7
ST		 1079 /* assumes h->devlock is held */
1080 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1081
1082 /* Raid level changed. */
1083 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1084
03383736
DB		 1085 /* Raid offload parameters changed. Careful about the ordering. */
1086 if (new_entry->offload_config && new_entry->offload_enabled) {
1087 /*
1088 * if drive is newly offload_enabled, we want to copy the
1089 * raid map data first. If previously offload_enabled and
1090 * offload_config were set, raid map data had better be
1091 * the same as it was before. if raid map data is changed
1092 * then it had better be the case that
1093 * h->dev[entry]->offload_enabled is currently 0.
1094 */
1095 h->dev[entry]->raid_map = new_entry->raid_map;
1096 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1097 }
a3144e0b
JH		 1098 if (new_entry->hba_ioaccel_enabled) {
1099 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1100 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1101 }
1102 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1103 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1104 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1105 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1106
41ce4c35
SC		 1107 /*
1108 * We can turn off ioaccel offload now, but need to delay turning
1109 * it on until we can update h->dev[entry]->phys_disk[], but we
1110 * can't do that until all the devices are updated.
1111 */
1112 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1113 if (!new_entry->offload_enabled)
1114 h->dev[entry]->offload_enabled = 0;
1115
a473d86c
RE		 1116 offload_enabled = h->dev[entry]->offload_enabled;
1117 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1118 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1119 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1120}
1121
2a8ccf31
SC		 1122/* Replace an entry from h->dev[] array. */
1123static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1124 int entry, struct hpsa_scsi_dev_t *new_entry,
1125 struct hpsa_scsi_dev_t *added[], int *nadded,
1126 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1127{
1128 /* assumes h->devlock is held */
cfe5badc 1129 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1130 removed[*nremoved] = h->dev[entry];
1131 (*nremoved)++;
01350d05
SC		 1132
1133 /*
1134 * New physical devices won't have target/lun assigned yet
1135 * so we need to preserve the values in the slot we are replacing.
1136 */
1137 if (new_entry->target == -1) {
1138 new_entry->target = h->dev[entry]->target;
1139 new_entry->lun = h->dev[entry]->lun;
1140 }
1141
2a8ccf31
SC		 1142 h->dev[entry] = new_entry;
1143 added[*nadded] = new_entry;
1144 (*nadded)++;
0d96ef5f 1145 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1146 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1147 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1148}
1149
edd16368
SC		 1150/* Remove an entry from h->dev[] array. */
1151static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1152 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1153{
1154 /* assumes h->devlock is held */
1155 int i;
1156 struct hpsa_scsi_dev_t *sd;
1157
cfe5badc 1158 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1159
1160 sd = h->dev[entry];
1161 removed[*nremoved] = h->dev[entry];
1162 (*nremoved)++;
1163
1164 for (i = entry; i < h->ndevices-1; i++)
1165 h->dev[i] = h->dev[i+1];
1166 h->ndevices--;
0d96ef5f 1167 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1168}
1169
1170#define SCSI3ADDR_EQ(a, b) ( \
1171 (a)[7] == (b)[7] && \
1172 (a)[6] == (b)[6] && \
1173 (a)[5] == (b)[5] && \
1174 (a)[4] == (b)[4] && \
1175 (a)[3] == (b)[3] && \
1176 (a)[2] == (b)[2] && \
1177 (a)[1] == (b)[1] && \
1178 (a)[0] == (b)[0])
1179
1180static void fixup_botched_add(struct ctlr_info *h,
1181 struct hpsa_scsi_dev_t *added)
1182{
1183 /* called when scsi_add_device fails in order to re-adjust
1184 * h->dev[] to match the mid layer's view.
1185 */
1186 unsigned long flags;
1187 int i, j;
1188
1189 spin_lock_irqsave(&h->lock, flags);
1190 for (i = 0; i < h->ndevices; i++) {
1191 if (h->dev[i] == added) {
1192 for (j = i; j < h->ndevices-1; j++)
1193 h->dev[j] = h->dev[j+1];
1194 h->ndevices--;
1195 break;
1196 }
1197 }
1198 spin_unlock_irqrestore(&h->lock, flags);
1199 kfree(added);
1200}
1201
1202static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1203 struct hpsa_scsi_dev_t *dev2)
1204{
edd16368
SC		 1205 /* we compare everything except lun and target as these
1206 * are not yet assigned. Compare parts likely
1207 * to differ first
1208 */
1209 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1210 sizeof(dev1->scsi3addr)) != 0)
1211 return 0;
1212 if (memcmp(dev1->device_id, dev2->device_id,
1213 sizeof(dev1->device_id)) != 0)
1214 return 0;
1215 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1216 return 0;
1217 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1218 return 0;
edd16368
SC		 1219 if (dev1->devtype != dev2->devtype)
1220 return 0;
edd16368
SC		 1221 if (dev1->bus != dev2->bus)
1222 return 0;
1223 return 1;
1224}
1225
bd9244f7
ST		 1226static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1227 struct hpsa_scsi_dev_t *dev2)
1228{
1229 /* Device attributes that can change, but don't mean
1230 * that the device is a different device, nor that the OS
1231 * needs to be told anything about the change.
1232 */
1233 if (dev1->raid_level != dev2->raid_level)
1234 return 1;
250fb125
SC		 1235 if (dev1->offload_config != dev2->offload_config)
1236 return 1;
1237 if (dev1->offload_enabled != dev2->offload_enabled)
1238 return 1;
03383736
DB		 1239 if (dev1->queue_depth != dev2->queue_depth)
1240 return 1;
bd9244f7
ST		 1241 return 0;
1242}
1243
edd16368
SC		 1244/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1245 * and return needle location in *index. If scsi3addr matches, but not
1246 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1247 * location in *index.
1248 * In the case of a minor device attribute change, such as RAID level, just
1249 * return DEVICE_UPDATED, along with the updated device's location in index.
1250 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1251 */
1252static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1253 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1254 int *index)
1255{
1256 int i;
1257#define DEVICE_NOT_FOUND 0
1258#define DEVICE_CHANGED 1
1259#define DEVICE_SAME 2
bd9244f7 1260#define DEVICE_UPDATED 3
edd16368 1261 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1262 if (haystack[i] == NULL) /* previously removed. */
1263 continue;
edd16368
SC		 1264 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1265 *index = i;
bd9244f7
ST		 1266 if (device_is_the_same(needle, haystack[i])) {
1267 if (device_updated(needle, haystack[i]))
1268 return DEVICE_UPDATED;
edd16368 1269 return DEVICE_SAME;
bd9244f7 1270 } else {
9846590e
SC		 1271 /* Keep offline devices offline */
1272 if (needle->volume_offline)
1273 return DEVICE_NOT_FOUND;
edd16368 1274 return DEVICE_CHANGED;
bd9244f7 1275 }
edd16368
SC		 1276 }
1277 }
1278 *index = -1;
1279 return DEVICE_NOT_FOUND;
1280}
1281
9846590e
SC		 1282static void hpsa_monitor_offline_device(struct ctlr_info *h,
1283 unsigned char scsi3addr[])
1284{
1285 struct offline_device_entry *device;
1286 unsigned long flags;
1287
1288 /* Check to see if device is already on the list */
1289 spin_lock_irqsave(&h->offline_device_lock, flags);
1290 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1291 if (memcmp(device->scsi3addr, scsi3addr,
1292 sizeof(device->scsi3addr)) == 0) {
1293 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1294 return;
1295 }
1296 }
1297 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1298
1299 /* Device is not on the list, add it. */
1300 device = kmalloc(sizeof(*device), GFP_KERNEL);
1301 if (!device) {
1302 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1303 return;
1304 }
1305 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1306 spin_lock_irqsave(&h->offline_device_lock, flags);
1307 list_add_tail(&device->offline_list, &h->offline_device_list);
1308 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1309}
1310
1311/* Print a message explaining various offline volume states */
1312static void hpsa_show_volume_status(struct ctlr_info *h,
1313 struct hpsa_scsi_dev_t *sd)
1314{
1315 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1316 dev_info(&h->pdev->dev,
1317 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1318 h->scsi_host->host_no,
1319 sd->bus, sd->target, sd->lun);
1320 switch (sd->volume_offline) {
1321 case HPSA_LV_OK:
1322 break;
1323 case HPSA_LV_UNDERGOING_ERASE:
1324 dev_info(&h->pdev->dev,
1325 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1326 h->scsi_host->host_no,
1327 sd->bus, sd->target, sd->lun);
1328 break;
1329 case HPSA_LV_UNDERGOING_RPI:
1330 dev_info(&h->pdev->dev,
1331 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1332 h->scsi_host->host_no,
1333 sd->bus, sd->target, sd->lun);
1334 break;
1335 case HPSA_LV_PENDING_RPI:
1336 dev_info(&h->pdev->dev,
1337 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1338 h->scsi_host->host_no,
1339 sd->bus, sd->target, sd->lun);
1340 break;
1341 case HPSA_LV_ENCRYPTED_NO_KEY:
1342 dev_info(&h->pdev->dev,
1343 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1344 h->scsi_host->host_no,
1345 sd->bus, sd->target, sd->lun);
1346 break;
1347 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1348 dev_info(&h->pdev->dev,
1349 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1350 h->scsi_host->host_no,
1351 sd->bus, sd->target, sd->lun);
1352 break;
1353 case HPSA_LV_UNDERGOING_ENCRYPTION:
1354 dev_info(&h->pdev->dev,
1355 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1356 h->scsi_host->host_no,
1357 sd->bus, sd->target, sd->lun);
1358 break;
1359 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1360 dev_info(&h->pdev->dev,
1361 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1362 h->scsi_host->host_no,
1363 sd->bus, sd->target, sd->lun);
1364 break;
1365 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1366 dev_info(&h->pdev->dev,
1367 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1368 h->scsi_host->host_no,
1369 sd->bus, sd->target, sd->lun);
1370 break;
1371 case HPSA_LV_PENDING_ENCRYPTION:
1372 dev_info(&h->pdev->dev,
1373 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1374 h->scsi_host->host_no,
1375 sd->bus, sd->target, sd->lun);
1376 break;
1377 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1378 dev_info(&h->pdev->dev,
1379 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1380 h->scsi_host->host_no,
1381 sd->bus, sd->target, sd->lun);
1382 break;
1383 }
1384}
1385
03383736
DB		 1386/*
1387 * Figure the list of physical drive pointers for a logical drive with
1388 * raid offload configured.
1389 */
1390static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1391 struct hpsa_scsi_dev_t *dev[], int ndevices,
1392 struct hpsa_scsi_dev_t *logical_drive)
1393{
1394 struct raid_map_data *map = &logical_drive->raid_map;
1395 struct raid_map_disk_data *dd = &map->data[0];
1396 int i, j;
1397 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1398 le16_to_cpu(map->metadata_disks_per_row);
1399 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1400 le16_to_cpu(map->layout_map_count) *
1401 total_disks_per_row;
1402 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1403 total_disks_per_row;
1404 int qdepth;
1405
1406 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1407 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1408
1409 qdepth = 0;
1410 for (i = 0; i < nraid_map_entries; i++) {
1411 logical_drive->phys_disk[i] = NULL;
1412 if (!logical_drive->offload_config)
1413 continue;
1414 for (j = 0; j < ndevices; j++) {
1415 if (dev[j]->devtype != TYPE_DISK)
1416 continue;
1417 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1418 continue;
1419 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1420 continue;
1421
1422 logical_drive->phys_disk[i] = dev[j];
1423 if (i < nphys_disk)
1424 qdepth = min(h->nr_cmds, qdepth +
1425 logical_drive->phys_disk[i]->queue_depth);
1426 break;
1427 }
1428
1429 /*
1430 * This can happen if a physical drive is removed and
1431 * the logical drive is degraded. In that case, the RAID
1432 * map data will refer to a physical disk which isn't actually
1433 * present. And in that case offload_enabled should already
1434 * be 0, but we'll turn it off here just in case
1435 */
1436 if (!logical_drive->phys_disk[i]) {
1437 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1438 logical_drive->offload_to_be_enabled = 0;
1439 logical_drive->queue_depth = 8;
03383736
DB		 1440 }
1441 }
1442 if (nraid_map_entries)
1443 /*
1444 * This is correct for reads, too high for full stripe writes,
1445 * way too high for partial stripe writes
1446 */
1447 logical_drive->queue_depth = qdepth;
1448 else
1449 logical_drive->queue_depth = h->nr_cmds;
1450}
1451
1452static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1453 struct hpsa_scsi_dev_t *dev[], int ndevices)
1454{
1455 int i;
1456
1457 for (i = 0; i < ndevices; i++) {
1458 if (dev[i]->devtype != TYPE_DISK)
1459 continue;
1460 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1461 continue;
41ce4c35
SC		 1462
1463 /*
1464 * If offload is currently enabled, the RAID map and
1465 * phys_disk[] assignment *better* not be changing
1466 * and since it isn't changing, we do not need to
1467 * update it.
1468 */
1469 if (dev[i]->offload_enabled)
1470 continue;
1471
03383736
DB		 1472 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1473 }
1474}
1475
4967bd3e 1476static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1477 struct hpsa_scsi_dev_t *sd[], int nsds)
1478{
1479 /* sd contains scsi3 addresses and devtypes, and inquiry
1480 * data. This function takes what's in sd to be the current
1481 * reality and updates h->dev[] to reflect that reality.
1482 */
1483 int i, entry, device_change, changes = 0;
1484 struct hpsa_scsi_dev_t *csd;
1485 unsigned long flags;
1486 struct hpsa_scsi_dev_t **added, **removed;
1487 int nadded, nremoved;
1488 struct Scsi_Host *sh = NULL;
1489
cfe5badc
ST		 1490 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1491 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1492
1493 if (!added || !removed) {
1494 dev_warn(&h->pdev->dev, "out of memory in "
1495 "adjust_hpsa_scsi_table\n");
1496 goto free_and_out;
1497 }
1498
1499 spin_lock_irqsave(&h->devlock, flags);
1500
1501 /* find any devices in h->dev[] that are not in
1502 * sd[] and remove them from h->dev[], and for any
1503 * devices which have changed, remove the old device
1504 * info and add the new device info.
bd9244f7
ST		 1505 * If minor device attributes change, just update
1506 * the existing device structure.
edd16368
SC		 1507 */
1508 i = 0;
1509 nremoved = 0;
1510 nadded = 0;
1511 while (i < h->ndevices) {
1512 csd = h->dev[i];
1513 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1514 if (device_change == DEVICE_NOT_FOUND) {
1515 changes++;
1516 hpsa_scsi_remove_entry(h, hostno, i,
1517 removed, &nremoved);
1518 continue; /* remove ^^^, hence i not incremented */
1519 } else if (device_change == DEVICE_CHANGED) {
1520 changes++;
2a8ccf31
SC		 1521 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1522 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1523 /* Set it to NULL to prevent it from being freed
1524 * at the bottom of hpsa_update_scsi_devices()
1525 */
1526 sd[entry] = NULL;
bd9244f7
ST		 1527 } else if (device_change == DEVICE_UPDATED) {
1528 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1529 }
1530 i++;
1531 }
1532
1533 /* Now, make sure every device listed in sd[] is also
1534 * listed in h->dev[], adding them if they aren't found
1535 */
1536
1537 for (i = 0; i < nsds; i++) {
1538 if (!sd[i]) /* if already added above. */
1539 continue;
9846590e
SC		 1540
1541 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1542 * as the SCSI mid-layer does not handle such devices well.
1543 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1544 * at 160Hz, and prevents the system from coming up.
1545 */
1546 if (sd[i]->volume_offline) {
1547 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1548 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1549 continue;
1550 }
1551
edd16368
SC		 1552 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1553 h->ndevices, &entry);
1554 if (device_change == DEVICE_NOT_FOUND) {
1555 changes++;
1556 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1557 added, &nadded) != 0)
1558 break;
1559 sd[i] = NULL; /* prevent from being freed later. */
1560 } else if (device_change == DEVICE_CHANGED) {
1561 /* should never happen... */
1562 changes++;
1563 dev_warn(&h->pdev->dev,
1564 "device unexpectedly changed.\n");
1565 /* but if it does happen, we just ignore that device */
1566 }
1567 }
41ce4c35
SC		 1568 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1569
1570 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1571 * any logical drives that need it enabled.
1572 */
1573 for (i = 0; i < h->ndevices; i++)
1574 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1575
edd16368
SC		 1576 spin_unlock_irqrestore(&h->devlock, flags);
1577
9846590e
SC		 1578 /* Monitor devices which are in one of several NOT READY states to be
1579 * brought online later. This must be done without holding h->devlock,
1580 * so don't touch h->dev[]
1581 */
1582 for (i = 0; i < nsds; i++) {
1583 if (!sd[i]) /* if already added above. */
1584 continue;
1585 if (sd[i]->volume_offline)
1586 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1587 }
1588
edd16368
SC		 1589 /* Don't notify scsi mid layer of any changes the first time through
1590 * (or if there are no changes) scsi_scan_host will do it later the
1591 * first time through.
1592 */
1593 if (hostno == -1 || !changes)
1594 goto free_and_out;
1595
1596 sh = h->scsi_host;
1597 /* Notify scsi mid layer of any removed devices */
1598 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1599 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1600 struct scsi_device *sdev =
1601 scsi_device_lookup(sh, removed[i]->bus,
1602 removed[i]->target, removed[i]->lun);
1603 if (sdev != NULL) {
1604 scsi_remove_device(sdev);
1605 scsi_device_put(sdev);
1606 } else {
1607 /*
1608 * We don't expect to get here.
1609 * future cmds to this device will get selection
1610 * timeout as if the device was gone.
1611 */
0d96ef5f
WS		 1612 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1613 "didn't find device for removal.");
41ce4c35 1614 }
edd16368
SC		 1615 }
1616 kfree(removed[i]);
1617 removed[i] = NULL;
1618 }
1619
1620 /* Notify scsi mid layer of any added devices */
1621 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1622 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1623 continue;
edd16368
SC		 1624 if (scsi_add_device(sh, added[i]->bus,
1625 added[i]->target, added[i]->lun) == 0)
1626 continue;
0d96ef5f
WS		 1627 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1628 "addition failed, device not added.");
edd16368
SC		 1629 /* now we have to remove it from h->dev,
1630 * since it didn't get added to scsi mid layer
1631 */
1632 fixup_botched_add(h, added[i]);
1633 }
1634
1635free_and_out:
1636 kfree(added);
1637 kfree(removed);
edd16368
SC		 1638}
1639
1640/*
9e03aa2f 1641 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1642 * Assume's h->devlock is held.
1643 */
1644static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1645 int bus, int target, int lun)
1646{
1647 int i;
1648 struct hpsa_scsi_dev_t *sd;
1649
1650 for (i = 0; i < h->ndevices; i++) {
1651 sd = h->dev[i];
1652 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1653 return sd;
1654 }
1655 return NULL;
1656}
1657
edd16368
SC		 1658static int hpsa_slave_alloc(struct scsi_device *sdev)
1659{
1660 struct hpsa_scsi_dev_t *sd;
1661 unsigned long flags;
1662 struct ctlr_info *h;
1663
1664 h = sdev_to_hba(sdev);
1665 spin_lock_irqsave(&h->devlock, flags);
1666 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1667 sdev_id(sdev), sdev->lun);
41ce4c35 1668 if (likely(sd)) {
03383736 1669 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1670 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1671 } else
1672 sdev->hostdata = NULL;
edd16368
SC		 1673 spin_unlock_irqrestore(&h->devlock, flags);
1674 return 0;
1675}
1676
41ce4c35
SC		 1677/* configure scsi device based on internal per-device structure */
1678static int hpsa_slave_configure(struct scsi_device *sdev)
1679{
1680 struct hpsa_scsi_dev_t *sd;
1681 int queue_depth;
1682
1683 sd = sdev->hostdata;
1684 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1685
1686 if (sd)
1687 queue_depth = sd->queue_depth != 0 ?
1688 sd->queue_depth : sdev->host->can_queue;
1689 else
1690 queue_depth = sdev->host->can_queue;
1691
1692 scsi_change_queue_depth(sdev, queue_depth);
1693
1694 return 0;
1695}
1696
edd16368
SC		 1697static void hpsa_slave_destroy(struct scsi_device *sdev)
1698{
bcc44255 1699 /* nothing to do. */
edd16368
SC		 1700}
1701
d9a729f3
WS		 1702static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1703{
1704 int i;
1705
1706 if (!h->ioaccel2_cmd_sg_list)
1707 return;
1708 for (i = 0; i < h->nr_cmds; i++) {
1709 kfree(h->ioaccel2_cmd_sg_list[i]);
1710 h->ioaccel2_cmd_sg_list[i] = NULL;
1711 }
1712 kfree(h->ioaccel2_cmd_sg_list);
1713 h->ioaccel2_cmd_sg_list = NULL;
1714}
1715
1716static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1717{
1718 int i;
1719
1720 if (h->chainsize <= 0)
1721 return 0;
1722
1723 h->ioaccel2_cmd_sg_list =
1724 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1725 GFP_KERNEL);
1726 if (!h->ioaccel2_cmd_sg_list)
1727 return -ENOMEM;
1728 for (i = 0; i < h->nr_cmds; i++) {
1729 h->ioaccel2_cmd_sg_list[i] =
1730 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1731 h->maxsgentries, GFP_KERNEL);
1732 if (!h->ioaccel2_cmd_sg_list[i])
1733 goto clean;
1734 }
1735 return 0;
1736
1737clean:
1738 hpsa_free_ioaccel2_sg_chain_blocks(h);
1739 return -ENOMEM;
1740}
1741
33a2ffce
SC		 1742static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1743{
1744 int i;
1745
1746 if (!h->cmd_sg_list)
1747 return;
1748 for (i = 0; i < h->nr_cmds; i++) {
1749 kfree(h->cmd_sg_list[i]);
1750 h->cmd_sg_list[i] = NULL;
1751 }
1752 kfree(h->cmd_sg_list);
1753 h->cmd_sg_list = NULL;
1754}
1755
1756static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1757{
1758 int i;
1759
1760 if (h->chainsize <= 0)
1761 return 0;
1762
1763 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1764 GFP_KERNEL);
3d4e6af8
RE		 1765 if (!h->cmd_sg_list) {
1766 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1767 return -ENOMEM;
3d4e6af8 1768 }
33a2ffce
SC		 1769 for (i = 0; i < h->nr_cmds; i++) {
1770 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1771 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1772 if (!h->cmd_sg_list[i]) {
1773 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1774 goto clean;
3d4e6af8 1775 }
33a2ffce
SC		 1776 }
1777 return 0;
1778
1779clean:
1780 hpsa_free_sg_chain_blocks(h);
1781 return -ENOMEM;
1782}
1783
d9a729f3
WS		 1784static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1785 struct io_accel2_cmd *cp, struct CommandList *c)
1786{
1787 struct ioaccel2_sg_element *chain_block;
1788 u64 temp64;
1789 u32 chain_size;
1790
1791 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1792 chain_size = le32_to_cpu(cp->data_len);
1793 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1794 PCI_DMA_TODEVICE);
1795 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1796 /* prevent subsequent unmapping */
1797 cp->sg->address = 0;
1798 return -1;
1799 }
1800 cp->sg->address = cpu_to_le64(temp64);
1801 return 0;
1802}
1803
1804static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1805 struct io_accel2_cmd *cp)
1806{
1807 struct ioaccel2_sg_element *chain_sg;
1808 u64 temp64;
1809 u32 chain_size;
1810
1811 chain_sg = cp->sg;
1812 temp64 = le64_to_cpu(chain_sg->address);
1813 chain_size = le32_to_cpu(cp->data_len);
1814 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1815}
1816
e2bea6df 1817static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1818 struct CommandList *c)
1819{
1820 struct SGDescriptor *chain_sg, *chain_block;
1821 u64 temp64;
50a0decf 1822 u32 chain_len;
33a2ffce
SC		 1823
1824 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1825 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1826 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1827 chain_len = sizeof(*chain_sg) *
2b08b3e9 1828 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1829 chain_sg->Len = cpu_to_le32(chain_len);
1830 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1831 PCI_DMA_TODEVICE);
e2bea6df
SC		 1832 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1833 /* prevent subsequent unmapping */
50a0decf 1834 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1835 return -1;
1836 }
50a0decf 1837 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1838 return 0;
33a2ffce
SC		 1839}
1840
1841static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1842 struct CommandList *c)
1843{
1844 struct SGDescriptor *chain_sg;
33a2ffce 1845
50a0decf 1846 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1847 return;
1848
1849 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1850 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1851 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1852}
1853
a09c1441
ST		 1854
1855/* Decode the various types of errors on ioaccel2 path.
1856 * Return 1 for any error that should generate a RAID path retry.
1857 * Return 0 for errors that don't require a RAID path retry.
1858 */
1859static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1860 struct CommandList *c,
1861 struct scsi_cmnd *cmd,
1862 struct io_accel2_cmd *c2)
1863{
1864 int data_len;
a09c1441 1865 int retry = 0;
c40820d5 1866 u32 ioaccel2_resid = 0;
c349775e
ST		 1867
1868 switch (c2->error_data.serv_response) {
1869 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1870 switch (c2->error_data.status) {
1871 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1872 break;
1873 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1874 dev_warn(&h->pdev->dev,
1875 "%s: task complete with check condition.\n",
1876 "HP SSD Smart Path");
ee6b1889 1877 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1878 if (c2->error_data.data_present !=
ee6b1889
SC		 1879 IOACCEL2_SENSE_DATA_PRESENT) {
1880 memset(cmd->sense_buffer, 0,
1881 SCSI_SENSE_BUFFERSIZE);
c349775e 1882 break;
ee6b1889 1883 }
c349775e
ST		 1884 /* copy the sense data */
1885 data_len = c2->error_data.sense_data_len;
1886 if (data_len > SCSI_SENSE_BUFFERSIZE)
1887 data_len = SCSI_SENSE_BUFFERSIZE;
1888 if (data_len > sizeof(c2->error_data.sense_data_buff))
1889 data_len =
1890 sizeof(c2->error_data.sense_data_buff);
1891 memcpy(cmd->sense_buffer,
1892 c2->error_data.sense_data_buff, data_len);
a09c1441 1893 retry = 1;
c349775e
ST		 1894 break;
1895 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1896 dev_warn(&h->pdev->dev,
1897 "%s: task complete with BUSY status.\n",
1898 "HP SSD Smart Path");
a09c1441 1899 retry = 1;
c349775e
ST		 1900 break;
1901 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1902 dev_warn(&h->pdev->dev,
1903 "%s: task complete with reservation conflict.\n",
1904 "HP SSD Smart Path");
a09c1441 1905 retry = 1;
c349775e
ST		 1906 break;
1907 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1908 retry = 1;
c349775e
ST		 1909 break;
1910 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1911 dev_warn(&h->pdev->dev,
1912 "%s: task complete with aborted status.\n",
1913 "HP SSD Smart Path");
a09c1441 1914 retry = 1;
c349775e
ST		 1915 break;
1916 default:
1917 dev_warn(&h->pdev->dev,
1918 "%s: task complete with unrecognized status: 0x%02x\n",
1919 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1920 retry = 1;
c349775e
ST		 1921 break;
1922 }
1923 break;
1924 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 1925 switch (c2->error_data.status) {
1926 case IOACCEL2_STATUS_SR_IO_ERROR:
1927 case IOACCEL2_STATUS_SR_IO_ABORTED:
1928 case IOACCEL2_STATUS_SR_OVERRUN:
1929 retry = 1;
1930 break;
1931 case IOACCEL2_STATUS_SR_UNDERRUN:
1932 cmd->result = (DID_OK << 16); /* host byte */
1933 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
1934 ioaccel2_resid = get_unaligned_le32(
1935 &c2->error_data.resid_cnt[0]);
1936 scsi_set_resid(cmd, ioaccel2_resid);
1937 break;
1938 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
1939 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
1940 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
1941 /* We will get an event from ctlr to trigger rescan */
1942 retry = 1;
1943 break;
1944 default:
1945 retry = 1;
1946 dev_warn(&h->pdev->dev,
1947 "unexpected delivery or target failure, status = 0x%02x\n",
1948 c2->error_data.status);
1949 }
c349775e
ST		 1950 break;
1951 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1952 break;
1953 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1954 break;
1955 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1956 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1957 retry = 1;
c349775e
ST		 1958 break;
1959 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1960 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1961 break;
1962 default:
1963 dev_warn(&h->pdev->dev,
1964 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1965 "HP SSD Smart Path",
1966 c2->error_data.serv_response);
1967 retry = 1;
c349775e
ST		 1968 break;
1969 }
a09c1441
ST		 1970
1971 return retry; /* retry on raid path? */
c349775e
ST		 1972}
1973
1974static void process_ioaccel2_completion(struct ctlr_info *h,
1975 struct CommandList *c, struct scsi_cmnd *cmd,
1976 struct hpsa_scsi_dev_t *dev)
1977{
1978 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1979
1980 /* check for good status */
1981 if (likely(c2->error_data.serv_response == 0 &&
1982 c2->error_data.status == 0)) {
1983 cmd_free(h, c);
1984 cmd->scsi_done(cmd);
1985 return;
1986 }
1987
1988 /* Any RAID offload error results in retry which will use
1989 * the normal I/O path so the controller can handle whatever's
1990 * wrong.
1991 */
1992 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1993 c2->error_data.serv_response ==
1994 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1995 if (c2->error_data.status ==
1996 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1997 dev->offload_enabled = 0;
1998 goto retry_cmd;
a09c1441 1999 }
080ef1cc
DB		 2000
2001 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
2002 goto retry_cmd;
2003
c349775e
ST		 2004 cmd_free(h, c);
2005 cmd->scsi_done(cmd);
080ef1cc
DB		 2006 return;
2007
2008retry_cmd:
2009 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2010 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 2011}
2012
9437ac43
SC		 2013/* Returns 0 on success, < 0 otherwise. */
2014static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2015 struct CommandList *cp)
2016{
2017 u8 tmf_status = cp->err_info->ScsiStatus;
2018
2019 switch (tmf_status) {
2020 case CISS_TMF_COMPLETE:
2021 /*
2022 * CISS_TMF_COMPLETE never happens, instead,
2023 * ei->CommandStatus == 0 for this case.
2024 */
2025 case CISS_TMF_SUCCESS:
2026 return 0;
2027 case CISS_TMF_INVALID_FRAME:
2028 case CISS_TMF_NOT_SUPPORTED:
2029 case CISS_TMF_FAILED:
2030 case CISS_TMF_WRONG_LUN:
2031 case CISS_TMF_OVERLAPPED_TAG:
2032 break;
2033 default:
2034 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2035 tmf_status);
2036 break;
2037 }
2038 return -tmf_status;
2039}
2040
1fb011fb 2041static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2042{
2043 struct scsi_cmnd *cmd;
2044 struct ctlr_info *h;
2045 struct ErrorInfo *ei;
283b4a9b 2046 struct hpsa_scsi_dev_t *dev;
d9a729f3 2047 struct io_accel2_cmd *c2;
edd16368 2048
9437ac43
SC		 2049 u8 sense_key;
2050 u8 asc; /* additional sense code */
2051 u8 ascq; /* additional sense code qualifier */
db111e18 2052 unsigned long sense_data_size;
edd16368
SC		 2053
2054 ei = cp->err_info;
7fa3030c 2055 cmd = cp->scsi_cmd;
edd16368 2056 h = cp->h;
283b4a9b 2057 dev = cmd->device->hostdata;
d9a729f3 2058 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2059
2060 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2061 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2062 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2063 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2064
d9a729f3
WS		 2065 if ((cp->cmd_type == CMD_IOACCEL2) &&
2066 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2067 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2068
edd16368
SC		 2069 cmd->result = (DID_OK << 16); /* host byte */
2070 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2071
03383736
DB		 2072 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2073 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2074
25163bd5
WS		 2075 /*
2076 * We check for lockup status here as it may be set for
2077 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2078 * fail_all_oustanding_cmds()
2079 */
2080 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2081 /* DID_NO_CONNECT will prevent a retry */
2082 cmd->result = DID_NO_CONNECT << 16;
2083 cmd_free(h, cp);
2084 cmd->scsi_done(cmd);
2085 return;
2086 }
2087
c349775e
ST		 2088 if (cp->cmd_type == CMD_IOACCEL2)
2089 return process_ioaccel2_completion(h, cp, cmd, dev);
2090
6aa4c361
RE		 2091 scsi_set_resid(cmd, ei->ResidualCnt);
2092 if (ei->CommandStatus == 0) {
03383736
DB		 2093 if (cp->cmd_type == CMD_IOACCEL1)
2094 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 2095 cmd_free(h, cp);
2096 cmd->scsi_done(cmd);
2097 return;
2098 }
2099
e1f7de0c
MG		 2100 /* For I/O accelerator commands, copy over some fields to the normal
2101 * CISS header used below for error handling.
2102 */
2103 if (cp->cmd_type == CMD_IOACCEL1) {
2104 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2105 cp->Header.SGList = scsi_sg_count(cmd);
2106 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2107 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2108 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2109 cp->Header.tag = c->tag;
e1f7de0c
MG		 2110 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2111 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2112
2113 /* Any RAID offload error results in retry which will use
2114 * the normal I/O path so the controller can handle whatever's
2115 * wrong.
2116 */
2117 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2118 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2119 dev->offload_enabled = 0;
080ef1cc
DB		 2120 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
2121 queue_work_on(raw_smp_processor_id(),
2122 h->resubmit_wq, &cp->work);
283b4a9b
SC		 2123 return;
2124 }
e1f7de0c
MG		 2125 }
2126
edd16368
SC		 2127 /* an error has occurred */
2128 switch (ei->CommandStatus) {
2129
2130 case CMD_TARGET_STATUS:
9437ac43
SC		 2131 cmd->result |= ei->ScsiStatus;
2132 /* copy the sense data */
2133 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2134 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2135 else
2136 sense_data_size = sizeof(ei->SenseInfo);
2137 if (ei->SenseLen < sense_data_size)
2138 sense_data_size = ei->SenseLen;
2139 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2140 if (ei->ScsiStatus)
2141 decode_sense_data(ei->SenseInfo, sense_data_size,
2142 &sense_key, &asc, &ascq);
edd16368 2143 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2144 if (sense_key == ABORTED_COMMAND) {
2e311fba 2145 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2146 break;
2147 }
edd16368
SC		 2148 break;
2149 }
edd16368
SC		 2150 /* Problem was not a check condition
2151 * Pass it up to the upper layers...
2152 */
2153 if (ei->ScsiStatus) {
2154 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2155 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2156 "Returning result: 0x%x\n",
2157 cp, ei->ScsiStatus,
2158 sense_key, asc, ascq,
2159 cmd->result);
2160 } else { /* scsi status is zero??? How??? */
2161 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2162 "Returning no connection.\n", cp),
2163
2164 /* Ordinarily, this case should never happen,
2165 * but there is a bug in some released firmware
2166 * revisions that allows it to happen if, for
2167 * example, a 4100 backplane loses power and
2168 * the tape drive is in it. We assume that
2169 * it's a fatal error of some kind because we
2170 * can't show that it wasn't. We will make it
2171 * look like selection timeout since that is
2172 * the most common reason for this to occur,
2173 * and it's severe enough.
2174 */
2175
2176 cmd->result = DID_NO_CONNECT << 16;
2177 }
2178 break;
2179
2180 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2181 break;
2182 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2183 dev_warn(&h->pdev->dev,
2184 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2185 break;
2186 case CMD_INVALID: {
2187 /* print_bytes(cp, sizeof(*cp), 1, 0);
2188 print_cmd(cp); */
2189 /* We get CMD_INVALID if you address a non-existent device
2190 * instead of a selection timeout (no response). You will
2191 * see this if you yank out a drive, then try to access it.
2192 * This is kind of a shame because it means that any other
2193 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2194 * missing target. */
2195 cmd->result = DID_NO_CONNECT << 16;
2196 }
2197 break;
2198 case CMD_PROTOCOL_ERR:
256d0eaa 2199 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2200 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2201 cp->Request.CDB);
edd16368
SC		 2202 break;
2203 case CMD_HARDWARE_ERR:
2204 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2205 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2206 cp->Request.CDB);
edd16368
SC		 2207 break;
2208 case CMD_CONNECTION_LOST:
2209 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2210 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2211 cp->Request.CDB);
edd16368
SC		 2212 break;
2213 case CMD_ABORTED:
2214 cmd->result = DID_ABORT << 16;
f42e81e1
SC		 2215 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2216 cp->Request.CDB, ei->ScsiStatus);
edd16368
SC		 2217 break;
2218 case CMD_ABORT_FAILED:
2219 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2220 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2221 cp->Request.CDB);
edd16368
SC		 2222 break;
2223 case CMD_UNSOLICITED_ABORT:
f6e76055 2224 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2225 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2226 cp->Request.CDB);
edd16368
SC		 2227 break;
2228 case CMD_TIMEOUT:
2229 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2230 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2231 cp->Request.CDB);
edd16368 2232 break;
1d5e2ed0
SC		 2233 case CMD_UNABORTABLE:
2234 cmd->result = DID_ERROR << 16;
2235 dev_warn(&h->pdev->dev, "Command unabortable\n");
2236 break;
9437ac43
SC		 2237 case CMD_TMF_STATUS:
2238 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2239 cmd->result = DID_ERROR << 16;
2240 break;
283b4a9b
SC		 2241 case CMD_IOACCEL_DISABLED:
2242 /* This only handles the direct pass-through case since RAID
2243 * offload is handled above. Just attempt a retry.
2244 */
2245 cmd->result = DID_SOFT_ERROR << 16;
2246 dev_warn(&h->pdev->dev,
2247 "cp %p had HP SSD Smart Path error\n", cp);
2248 break;
edd16368
SC		 2249 default:
2250 cmd->result = DID_ERROR << 16;
2251 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2252 cp, ei->CommandStatus);
2253 }
edd16368 2254 cmd_free(h, cp);
2cc5bfaf 2255 cmd->scsi_done(cmd);
edd16368
SC		 2256}
2257
edd16368
SC		 2258static void hpsa_pci_unmap(struct pci_dev *pdev,
2259 struct CommandList *c, int sg_used, int data_direction)
2260{
2261 int i;
edd16368 2262
50a0decf
SC		 2263 for (i = 0; i < sg_used; i++)
2264 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2265 le32_to_cpu(c->SG[i].Len),
2266 data_direction);
edd16368
SC		 2267}
2268
a2dac136 2269static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2270 struct CommandList *cp,
2271 unsigned char *buf,
2272 size_t buflen,
2273 int data_direction)
2274{
01a02ffc 2275 u64 addr64;
edd16368
SC		 2276
2277 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2278 cp->Header.SGList = 0;
50a0decf 2279 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2280 return 0;
edd16368
SC		 2281 }
2282
50a0decf 2283 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2284 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2285 /* Prevent subsequent unmap of something never mapped */
eceaae18 2286 cp->Header.SGList = 0;
50a0decf 2287 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2288 return -1;
eceaae18 2289 }
50a0decf
SC		 2290 cp->SG[0].Addr = cpu_to_le64(addr64);
2291 cp->SG[0].Len = cpu_to_le32(buflen);
2292 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2293 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2294 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2295 return 0;
edd16368
SC		 2296}
2297
25163bd5
WS		 2298#define NO_TIMEOUT ((unsigned long) -1)
2299#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2300static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2301 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2302{
2303 DECLARE_COMPLETION_ONSTACK(wait);
2304
2305 c->waiting = &wait;
25163bd5
WS		 2306 __enqueue_cmd_and_start_io(h, c, reply_queue);
2307 if (timeout_msecs == NO_TIMEOUT) {
2308 /* TODO: get rid of this no-timeout thing */
2309 wait_for_completion_io(&wait);
2310 return IO_OK;
2311 }
2312 if (!wait_for_completion_io_timeout(&wait,
2313 msecs_to_jiffies(timeout_msecs))) {
2314 dev_warn(&h->pdev->dev, "Command timed out.\n");
2315 return -ETIMEDOUT;
2316 }
2317 return IO_OK;
2318}
2319
2320static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2321 int reply_queue, unsigned long timeout_msecs)
2322{
2323 if (unlikely(lockup_detected(h))) {
2324 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2325 return IO_OK;
2326 }
2327 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2328}
2329
094963da
SC		 2330static u32 lockup_detected(struct ctlr_info *h)
2331{
2332 int cpu;
2333 u32 rc, *lockup_detected;
2334
2335 cpu = get_cpu();
2336 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2337 rc = *lockup_detected;
2338 put_cpu();
2339 return rc;
2340}
2341
9c2fc160 2342#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2343static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2344 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2345{
9c2fc160 2346 int backoff_time = 10, retry_count = 0;
25163bd5 2347 int rc;
edd16368
SC		 2348
2349 do {
7630abd0 2350 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2351 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2352 timeout_msecs);
2353 if (rc)
2354 break;
edd16368 2355 retry_count++;
9c2fc160
SC		 2356 if (retry_count > 3) {
2357 msleep(backoff_time);
2358 if (backoff_time < 1000)
2359 backoff_time *= 2;
2360 }
852af20a 2361 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2362 check_for_busy(h, c)) &&
2363 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2364 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2365 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2366 rc = -EIO;
2367 return rc;
edd16368
SC		 2368}
2369
d1e8beac
SC		 2370static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2371 struct CommandList *c)
edd16368 2372{
d1e8beac
SC		 2373 const u8 *cdb = c->Request.CDB;
2374 const u8 *lun = c->Header.LUN.LunAddrBytes;
2375
2376 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2377 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2378 txt, lun[0], lun[1], lun[2], lun[3],
2379 lun[4], lun[5], lun[6], lun[7],
2380 cdb[0], cdb[1], cdb[2], cdb[3],
2381 cdb[4], cdb[5], cdb[6], cdb[7],
2382 cdb[8], cdb[9], cdb[10], cdb[11],
2383 cdb[12], cdb[13], cdb[14], cdb[15]);
2384}
2385
2386static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2387 struct CommandList *cp)
2388{
2389 const struct ErrorInfo *ei = cp->err_info;
edd16368 2390 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2391 u8 sense_key, asc, ascq;
2392 int sense_len;
edd16368 2393
edd16368
SC		 2394 switch (ei->CommandStatus) {
2395 case CMD_TARGET_STATUS:
9437ac43
SC		 2396 if (ei->SenseLen > sizeof(ei->SenseInfo))
2397 sense_len = sizeof(ei->SenseInfo);
2398 else
2399 sense_len = ei->SenseLen;
2400 decode_sense_data(ei->SenseInfo, sense_len,
2401 &sense_key, &asc, &ascq);
d1e8beac
SC		 2402 hpsa_print_cmd(h, "SCSI status", cp);
2403 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2404 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2405 sense_key, asc, ascq);
d1e8beac 2406 else
9437ac43 2407 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2408 if (ei->ScsiStatus == 0)
2409 dev_warn(d, "SCSI status is abnormally zero. "
2410 "(probably indicates selection timeout "
2411 "reported incorrectly due to a known "
2412 "firmware bug, circa July, 2001.)\n");
2413 break;
2414 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2415 break;
2416 case CMD_DATA_OVERRUN:
d1e8beac 2417 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2418 break;
2419 case CMD_INVALID: {
2420 /* controller unfortunately reports SCSI passthru's
2421 * to non-existent targets as invalid commands.
2422 */
d1e8beac
SC		 2423 hpsa_print_cmd(h, "invalid command", cp);
2424 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2425 }
2426 break;
2427 case CMD_PROTOCOL_ERR:
d1e8beac 2428 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2429 break;
2430 case CMD_HARDWARE_ERR:
d1e8beac 2431 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2432 break;
2433 case CMD_CONNECTION_LOST:
d1e8beac 2434 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2435 break;
2436 case CMD_ABORTED:
d1e8beac 2437 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2438 break;
2439 case CMD_ABORT_FAILED:
d1e8beac 2440 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2441 break;
2442 case CMD_UNSOLICITED_ABORT:
d1e8beac 2443 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2444 break;
2445 case CMD_TIMEOUT:
d1e8beac 2446 hpsa_print_cmd(h, "timed out", cp);
edd16368 2447 break;
1d5e2ed0 2448 case CMD_UNABORTABLE:
d1e8beac 2449 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2450 break;
25163bd5
WS		 2451 case CMD_CTLR_LOCKUP:
2452 hpsa_print_cmd(h, "controller lockup detected", cp);
2453 break;
edd16368 2454 default:
d1e8beac
SC		 2455 hpsa_print_cmd(h, "unknown status", cp);
2456 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2457 ei->CommandStatus);
2458 }
2459}
2460
2461static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2462 u16 page, unsigned char *buf,
edd16368
SC		 2463 unsigned char bufsize)
2464{
2465 int rc = IO_OK;
2466 struct CommandList *c;
2467 struct ErrorInfo *ei;
2468
45fcb86e 2469 c = cmd_alloc(h);
edd16368 2470
574f05d3 2471 if (c == NULL) {
45fcb86e 2472 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2473 return -ENOMEM;
edd16368
SC		 2474 }
2475
a2dac136
SC		 2476 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2477 page, scsi3addr, TYPE_CMD)) {
2478 rc = -1;
2479 goto out;
2480 }
25163bd5
WS		 2481 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2482 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2483 if (rc)
2484 goto out;
edd16368
SC		 2485 ei = c->err_info;
2486 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2487 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2488 rc = -1;
2489 }
a2dac136 2490out:
45fcb86e 2491 cmd_free(h, c);
edd16368
SC		 2492 return rc;
2493}
2494
316b221a
SC		 2495static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2496 unsigned char *scsi3addr, unsigned char page,
2497 struct bmic_controller_parameters *buf, size_t bufsize)
2498{
2499 int rc = IO_OK;
2500 struct CommandList *c;
2501 struct ErrorInfo *ei;
2502
45fcb86e 2503 c = cmd_alloc(h);
316b221a 2504 if (c == NULL) { /* trouble... */
45fcb86e 2505 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2506 return -ENOMEM;
2507 }
2508
2509 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2510 page, scsi3addr, TYPE_CMD)) {
2511 rc = -1;
2512 goto out;
2513 }
25163bd5
WS		 2514 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2515 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2516 if (rc)
2517 goto out;
316b221a
SC		 2518 ei = c->err_info;
2519 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2520 hpsa_scsi_interpret_error(h, c);
2521 rc = -1;
2522 }
2523out:
45fcb86e 2524 cmd_free(h, c);
316b221a
SC		 2525 return rc;
2526 }
2527
bf711ac6 2528static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2529 u8 reset_type, int reply_queue)
edd16368
SC		 2530{
2531 int rc = IO_OK;
2532 struct CommandList *c;
2533 struct ErrorInfo *ei;
2534
45fcb86e 2535 c = cmd_alloc(h);
edd16368
SC		 2536
2537 if (c == NULL) { /* trouble... */
45fcb86e 2538 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2539 return -ENOMEM;
edd16368
SC		 2540 }
2541
a2dac136 2542 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2543 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2544 scsi3addr, TYPE_MSG);
2545 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2546 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2547 if (rc) {
2548 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2549 goto out;
2550 }
edd16368
SC		 2551 /* no unmap needed here because no data xfer. */
2552
2553 ei = c->err_info;
2554 if (ei->CommandStatus != 0) {
d1e8beac 2555 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2556 rc = -1;
2557 }
25163bd5 2558out:
45fcb86e 2559 cmd_free(h, c);
edd16368
SC		 2560 return rc;
2561}
2562
2563static void hpsa_get_raid_level(struct ctlr_info *h,
2564 unsigned char *scsi3addr, unsigned char *raid_level)
2565{
2566 int rc;
2567 unsigned char *buf;
2568
2569 *raid_level = RAID_UNKNOWN;
2570 buf = kzalloc(64, GFP_KERNEL);
2571 if (!buf)
2572 return;
b7bb24eb 2573 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2574 if (rc == 0)
2575 *raid_level = buf[8];
2576 if (*raid_level > RAID_UNKNOWN)
2577 *raid_level = RAID_UNKNOWN;
2578 kfree(buf);
2579 return;
2580}
2581
283b4a9b
SC		 2582#define HPSA_MAP_DEBUG
2583#ifdef HPSA_MAP_DEBUG
2584static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2585 struct raid_map_data *map_buff)
2586{
2587 struct raid_map_disk_data *dd = &map_buff->data[0];
2588 int map, row, col;
2589 u16 map_cnt, row_cnt, disks_per_row;
2590
2591 if (rc != 0)
2592 return;
2593
2ba8bfc8
SC		 2594 /* Show details only if debugging has been activated. */
2595 if (h->raid_offload_debug < 2)
2596 return;
2597
283b4a9b
SC		 2598 dev_info(&h->pdev->dev, "structure_size = %u\n",
2599 le32_to_cpu(map_buff->structure_size));
2600 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2601 le32_to_cpu(map_buff->volume_blk_size));
2602 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2603 le64_to_cpu(map_buff->volume_blk_cnt));
2604 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2605 map_buff->phys_blk_shift);
2606 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2607 map_buff->parity_rotation_shift);
2608 dev_info(&h->pdev->dev, "strip_size = %u\n",
2609 le16_to_cpu(map_buff->strip_size));
2610 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2611 le64_to_cpu(map_buff->disk_starting_blk));
2612 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2613 le64_to_cpu(map_buff->disk_blk_cnt));
2614 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2615 le16_to_cpu(map_buff->data_disks_per_row));
2616 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2617 le16_to_cpu(map_buff->metadata_disks_per_row));
2618 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2619 le16_to_cpu(map_buff->row_cnt));
2620 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2621 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2622 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2623 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2624 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2625 le16_to_cpu(map_buff->flags) &
2626 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2627 dev_info(&h->pdev->dev, "dekindex = %u\n",
2628 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2629 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2630 for (map = 0; map < map_cnt; map++) {
2631 dev_info(&h->pdev->dev, "Map%u:\n", map);
2632 row_cnt = le16_to_cpu(map_buff->row_cnt);
2633 for (row = 0; row < row_cnt; row++) {
2634 dev_info(&h->pdev->dev, " Row%u:\n", row);
2635 disks_per_row =
2636 le16_to_cpu(map_buff->data_disks_per_row);
2637 for (col = 0; col < disks_per_row; col++, dd++)
2638 dev_info(&h->pdev->dev,
2639 " D%02u: h=0x%04x xor=%u,%u\n",
2640 col, dd->ioaccel_handle,
2641 dd->xor_mult[0], dd->xor_mult[1]);
2642 disks_per_row =
2643 le16_to_cpu(map_buff->metadata_disks_per_row);
2644 for (col = 0; col < disks_per_row; col++, dd++)
2645 dev_info(&h->pdev->dev,
2646 " M%02u: h=0x%04x xor=%u,%u\n",
2647 col, dd->ioaccel_handle,
2648 dd->xor_mult[0], dd->xor_mult[1]);
2649 }
2650 }
2651}
2652#else
2653static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2654 __attribute__((unused)) int rc,
2655 __attribute__((unused)) struct raid_map_data *map_buff)
2656{
2657}
2658#endif
2659
2660static int hpsa_get_raid_map(struct ctlr_info *h,
2661 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2662{
2663 int rc = 0;
2664 struct CommandList *c;
2665 struct ErrorInfo *ei;
2666
45fcb86e 2667 c = cmd_alloc(h);
283b4a9b 2668 if (c == NULL) {
45fcb86e 2669 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2670 return -ENOMEM;
2671 }
2672 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2673 sizeof(this_device->raid_map), 0,
2674 scsi3addr, TYPE_CMD)) {
2675 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
25163bd5
WS		 2676 rc = -ENOMEM;
2677 goto out;
283b4a9b 2678 }
25163bd5
WS		 2679 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2680 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2681 if (rc)
2682 goto out;
283b4a9b
SC		 2683 ei = c->err_info;
2684 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2685 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2686 rc = -1;
2687 goto out;
283b4a9b 2688 }
45fcb86e 2689 cmd_free(h, c);
283b4a9b
SC		 2690
2691 /* @todo in the future, dynamically allocate RAID map memory */
2692 if (le32_to_cpu(this_device->raid_map.structure_size) >
2693 sizeof(this_device->raid_map)) {
2694 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2695 rc = -1;
2696 }
2697 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2698 return rc;
25163bd5
WS		 2699out:
2700 cmd_free(h, c);
2701 return rc;
283b4a9b
SC		 2702}
2703
03383736
DB		 2704static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2705 unsigned char scsi3addr[], u16 bmic_device_index,
2706 struct bmic_identify_physical_device *buf, size_t bufsize)
2707{
2708 int rc = IO_OK;
2709 struct CommandList *c;
2710 struct ErrorInfo *ei;
2711
2712 c = cmd_alloc(h);
2713 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2714 0, RAID_CTLR_LUNID, TYPE_CMD);
2715 if (rc)
2716 goto out;
2717
2718 c->Request.CDB[2] = bmic_device_index & 0xff;
2719 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2720
25163bd5
WS		 2721 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2722 NO_TIMEOUT);
03383736
DB		 2723 ei = c->err_info;
2724 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2725 hpsa_scsi_interpret_error(h, c);
2726 rc = -1;
2727 }
2728out:
2729 cmd_free(h, c);
2730 return rc;
2731}
2732
1b70150a
SC		 2733static int hpsa_vpd_page_supported(struct ctlr_info *h,
2734 unsigned char scsi3addr[], u8 page)
2735{
2736 int rc;
2737 int i;
2738 int pages;
2739 unsigned char *buf, bufsize;
2740
2741 buf = kzalloc(256, GFP_KERNEL);
2742 if (!buf)
2743 return 0;
2744
2745 /* Get the size of the page list first */
2746 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2747 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2748 buf, HPSA_VPD_HEADER_SZ);
2749 if (rc != 0)
2750 goto exit_unsupported;
2751 pages = buf[3];
2752 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2753 bufsize = pages + HPSA_VPD_HEADER_SZ;
2754 else
2755 bufsize = 255;
2756
2757 /* Get the whole VPD page list */
2758 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2759 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2760 buf, bufsize);
2761 if (rc != 0)
2762 goto exit_unsupported;
2763
2764 pages = buf[3];
2765 for (i = 1; i <= pages; i++)
2766 if (buf[3 + i] == page)
2767 goto exit_supported;
2768exit_unsupported:
2769 kfree(buf);
2770 return 0;
2771exit_supported:
2772 kfree(buf);
2773 return 1;
2774}
2775
283b4a9b
SC		 2776static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2777 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2778{
2779 int rc;
2780 unsigned char *buf;
2781 u8 ioaccel_status;
2782
2783 this_device->offload_config = 0;
2784 this_device->offload_enabled = 0;
41ce4c35 2785 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2786
2787 buf = kzalloc(64, GFP_KERNEL);
2788 if (!buf)
2789 return;
1b70150a
SC		 2790 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2791 goto out;
283b4a9b 2792 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2793 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2794 if (rc != 0)
2795 goto out;
2796
2797#define IOACCEL_STATUS_BYTE 4
2798#define OFFLOAD_CONFIGURED_BIT 0x01
2799#define OFFLOAD_ENABLED_BIT 0x02
2800 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2801 this_device->offload_config =
2802 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2803 if (this_device->offload_config) {
2804 this_device->offload_enabled =
2805 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2806 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2807 this_device->offload_enabled = 0;
2808 }
41ce4c35 2809 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 2810out:
2811 kfree(buf);
2812 return;
2813}
2814
edd16368
SC		 2815/* Get the device id from inquiry page 0x83 */
2816static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2817 unsigned char *device_id, int buflen)
2818{
2819 int rc;
2820 unsigned char *buf;
2821
2822 if (buflen > 16)
2823 buflen = 16;
2824 buf = kzalloc(64, GFP_KERNEL);
2825 if (!buf)
a84d794d 2826 return -ENOMEM;
b7bb24eb 2827 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2828 if (rc == 0)
2829 memcpy(device_id, &buf[8], buflen);
2830 kfree(buf);
2831 return rc != 0;
2832}
2833
2834static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2835 void *buf, int bufsize,
edd16368
SC		 2836 int extended_response)
2837{
2838 int rc = IO_OK;
2839 struct CommandList *c;
2840 unsigned char scsi3addr[8];
2841 struct ErrorInfo *ei;
2842
45fcb86e 2843 c = cmd_alloc(h);
edd16368 2844 if (c == NULL) { /* trouble... */
45fcb86e 2845 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2846 return -1;
2847 }
e89c0ae7
SC		 2848 /* address the controller */
2849 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2850 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2851 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2852 rc = -1;
2853 goto out;
2854 }
edd16368
SC		 2855 if (extended_response)
2856 c->Request.CDB[1] = extended_response;
25163bd5
WS		 2857 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2858 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2859 if (rc)
2860 goto out;
edd16368
SC		 2861 ei = c->err_info;
2862 if (ei->CommandStatus != 0 &&
2863 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2864 hpsa_scsi_interpret_error(h, c);
edd16368 2865 rc = -1;
283b4a9b 2866 } else {
03383736
DB		 2867 struct ReportLUNdata *rld = buf;
2868
2869 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2870 dev_err(&h->pdev->dev,
2871 "report luns requested format %u, got %u\n",
2872 extended_response,
03383736 2873 rld->extended_response_flag);
283b4a9b
SC		 2874 rc = -1;
2875 }
edd16368 2876 }
a2dac136 2877out:
45fcb86e 2878 cmd_free(h, c);
edd16368
SC		 2879 return rc;
2880}
2881
2882static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2883 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2884{
03383736
DB		 2885 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2886 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2887}
2888
2889static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2890 struct ReportLUNdata *buf, int bufsize)
2891{
2892 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2893}
2894
2895static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2896 int bus, int target, int lun)
2897{
2898 device->bus = bus;
2899 device->target = target;
2900 device->lun = lun;
2901}
2902
9846590e
SC		 2903/* Use VPD inquiry to get details of volume status */
2904static int hpsa_get_volume_status(struct ctlr_info *h,
2905 unsigned char scsi3addr[])
2906{
2907 int rc;
2908 int status;
2909 int size;
2910 unsigned char *buf;
2911
2912 buf = kzalloc(64, GFP_KERNEL);
2913 if (!buf)
2914 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2915
2916 /* Does controller have VPD for logical volume status? */
24a4b078 2917 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2918 goto exit_failed;
9846590e
SC		 2919
2920 /* Get the size of the VPD return buffer */
2921 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2922 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2923 if (rc != 0)
9846590e 2924 goto exit_failed;
9846590e
SC		 2925 size = buf[3];
2926
2927 /* Now get the whole VPD buffer */
2928 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2929 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2930 if (rc != 0)
9846590e 2931 goto exit_failed;
9846590e
SC		 2932 status = buf[4]; /* status byte */
2933
2934 kfree(buf);
2935 return status;
2936exit_failed:
2937 kfree(buf);
2938 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2939}
2940
2941/* Determine offline status of a volume.
2942 * Return either:
2943 * 0 (not offline)
67955ba3 2944 * 0xff (offline for unknown reasons)
9846590e
SC		 2945 * # (integer code indicating one of several NOT READY states
2946 * describing why a volume is to be kept offline)
2947 */
67955ba3 2948static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2949 unsigned char scsi3addr[])
2950{
2951 struct CommandList *c;
9437ac43
SC		 2952 unsigned char *sense;
2953 u8 sense_key, asc, ascq;
2954 int sense_len;
25163bd5 2955 int rc, ldstat = 0;
9846590e
SC		 2956 u16 cmd_status;
2957 u8 scsi_status;
2958#define ASC_LUN_NOT_READY 0x04
2959#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2960#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2961
2962 c = cmd_alloc(h);
2963 if (!c)
2964 return 0;
2965 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 2966 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2967 if (rc) {
2968 cmd_free(h, c);
2969 return 0;
2970 }
9846590e 2971 sense = c->err_info->SenseInfo;
9437ac43
SC		 2972 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
2973 sense_len = sizeof(c->err_info->SenseInfo);
2974 else
2975 sense_len = c->err_info->SenseLen;
2976 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 2977 cmd_status = c->err_info->CommandStatus;
2978 scsi_status = c->err_info->ScsiStatus;
2979 cmd_free(h, c);
2980 /* Is the volume 'not ready'? */
2981 if (cmd_status != CMD_TARGET_STATUS ||
2982 scsi_status != SAM_STAT_CHECK_CONDITION ||
2983 sense_key != NOT_READY ||
2984 asc != ASC_LUN_NOT_READY) {
2985 return 0;
2986 }
2987
2988 /* Determine the reason for not ready state */
2989 ldstat = hpsa_get_volume_status(h, scsi3addr);
2990
2991 /* Keep volume offline in certain cases: */
2992 switch (ldstat) {
2993 case HPSA_LV_UNDERGOING_ERASE:
2994 case HPSA_LV_UNDERGOING_RPI:
2995 case HPSA_LV_PENDING_RPI:
2996 case HPSA_LV_ENCRYPTED_NO_KEY:
2997 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2998 case HPSA_LV_UNDERGOING_ENCRYPTION:
2999 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3000 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3001 return ldstat;
3002 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3003 /* If VPD status page isn't available,
3004 * use ASC/ASCQ to determine state
3005 */
3006 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3007 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3008 return ldstat;
3009 break;
3010 default:
3011 break;
3012 }
3013 return 0;
3014}
3015
9b5c48c2
SC		 3016/*
3017 * Find out if a logical device supports aborts by simply trying one.
3018 * Smart Array may claim not to support aborts on logical drives, but
3019 * if a MSA2000 * is connected, the drives on that will be presented
3020 * by the Smart Array as logical drives, and aborts may be sent to
3021 * those devices successfully. So the simplest way to find out is
3022 * to simply try an abort and see how the device responds.
3023 */
3024static int hpsa_device_supports_aborts(struct ctlr_info *h,
3025 unsigned char *scsi3addr)
3026{
3027 struct CommandList *c;
3028 struct ErrorInfo *ei;
3029 int rc = 0;
3030
3031 u64 tag = (u64) -1; /* bogus tag */
3032
3033 /* Assume that physical devices support aborts */
3034 if (!is_logical_dev_addr_mode(scsi3addr))
3035 return 1;
3036
3037 c = cmd_alloc(h);
3038 if (!c)
3039 return -ENOMEM;
3040 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3041 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3042 /* no unmap needed here because no data xfer. */
3043 ei = c->err_info;
3044 switch (ei->CommandStatus) {
3045 case CMD_INVALID:
3046 rc = 0;
3047 break;
3048 case CMD_UNABORTABLE:
3049 case CMD_ABORT_FAILED:
3050 rc = 1;
3051 break;
9437ac43
SC		 3052 case CMD_TMF_STATUS:
3053 rc = hpsa_evaluate_tmf_status(h, c);
3054 break;
9b5c48c2
SC		 3055 default:
3056 rc = 0;
3057 break;
3058 }
3059 cmd_free(h, c);
3060 return rc;
3061}
3062
edd16368 3063static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3064 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3065 unsigned char *is_OBDR_device)
edd16368 3066{
0b0e1d6c
SC		 3067
3068#define OBDR_SIG_OFFSET 43
3069#define OBDR_TAPE_SIG "$DR-10"
3070#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3071#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3072
ea6d3bc3 3073 unsigned char *inq_buff;
0b0e1d6c 3074 unsigned char *obdr_sig;
edd16368 3075
ea6d3bc3 3076 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3077 if (!inq_buff)
3078 goto bail_out;
3079
edd16368
SC		 3080 /* Do an inquiry to the device to see what it is. */
3081 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3082 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3083 /* Inquiry failed (msg printed already) */
3084 dev_err(&h->pdev->dev,
3085 "hpsa_update_device_info: inquiry failed\n");
3086 goto bail_out;
3087 }
3088
edd16368
SC		 3089 this_device->devtype = (inq_buff[0] & 0x1f);
3090 memcpy(this_device->scsi3addr, scsi3addr, 8);
3091 memcpy(this_device->vendor, &inq_buff[8],
3092 sizeof(this_device->vendor));
3093 memcpy(this_device->model, &inq_buff[16],
3094 sizeof(this_device->model));
edd16368
SC		 3095 memset(this_device->device_id, 0,
3096 sizeof(this_device->device_id));
3097 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3098 sizeof(this_device->device_id));
3099
3100 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3101 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3102 int volume_offline;
3103
edd16368 3104 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3105 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3106 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3107 volume_offline = hpsa_volume_offline(h, scsi3addr);
3108 if (volume_offline < 0 || volume_offline > 0xff)
3109 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3110 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3111 } else {
edd16368 3112 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3113 this_device->offload_config = 0;
3114 this_device->offload_enabled = 0;
41ce4c35 3115 this_device->offload_to_be_enabled = 0;
a3144e0b 3116 this_device->hba_ioaccel_enabled = 0;
9846590e 3117 this_device->volume_offline = 0;
03383736 3118 this_device->queue_depth = h->nr_cmds;
283b4a9b 3119 }
edd16368 3120
0b0e1d6c
SC		 3121 if (is_OBDR_device) {
3122 /* See if this is a One-Button-Disaster-Recovery device
3123 * by looking for "$DR-10" at offset 43 in inquiry data.
3124 */
3125 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3126 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3127 strncmp(obdr_sig, OBDR_TAPE_SIG,
3128 OBDR_SIG_LEN) == 0);
3129 }
edd16368
SC		 3130 kfree(inq_buff);
3131 return 0;
3132
3133bail_out:
3134 kfree(inq_buff);
3135 return 1;
3136}
3137
9b5c48c2
SC		 3138static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3139 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3140{
3141 unsigned long flags;
3142 int rc, entry;
3143 /*
3144 * See if this device supports aborts. If we already know
3145 * the device, we already know if it supports aborts, otherwise
3146 * we have to find out if it supports aborts by trying one.
3147 */
3148 spin_lock_irqsave(&h->devlock, flags);
3149 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3150 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3151 entry >= 0 && entry < h->ndevices) {
3152 dev->supports_aborts = h->dev[entry]->supports_aborts;
3153 spin_unlock_irqrestore(&h->devlock, flags);
3154 } else {
3155 spin_unlock_irqrestore(&h->devlock, flags);
3156 dev->supports_aborts =
3157 hpsa_device_supports_aborts(h, scsi3addr);
3158 if (dev->supports_aborts < 0)
3159 dev->supports_aborts = 0;
3160 }
3161}
3162
4f4eb9f1 3163static unsigned char *ext_target_model[] = {
edd16368
SC		 3164 "MSA2012",
3165 "MSA2024",
3166 "MSA2312",
3167 "MSA2324",
fda38518 3168 "P2000 G3 SAS",
e06c8e5c 3169 "MSA 2040 SAS",
edd16368
SC		 3170 NULL,
3171};
3172
4f4eb9f1 3173static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3174{
3175 int i;
3176
4f4eb9f1
ST		 3177 for (i = 0; ext_target_model[i]; i++)
3178 if (strncmp(device->model, ext_target_model[i],
3179 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3180 return 1;
3181 return 0;
3182}
3183
3184/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3185 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3186 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3187 * Logical drive target and lun are assigned at this time, but
3188 * physical device lun and target assignment are deferred (assigned
3189 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3190 */
3191static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3192 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3193{
1f310bde
SC		 3194 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3195
3196 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3197 /* physical device, target and lun filled in later */
edd16368 3198 if (is_hba_lunid(lunaddrbytes))
1f310bde 3199 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3200 else
1f310bde
SC		 3201 /* defer target, lun assignment for physical devices */
3202 hpsa_set_bus_target_lun(device, 2, -1, -1);
3203 return;
3204 }
3205 /* It's a logical device */
4f4eb9f1
ST		 3206 if (is_ext_target(h, device)) {
3207 /* external target way, put logicals on bus 1
1f310bde
SC		 3208 * and match target/lun numbers box
3209 * reports, other smart array, bus 0, target 0, match lunid
3210 */
3211 hpsa_set_bus_target_lun(device,
3212 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3213 return;
edd16368 3214 }
1f310bde 3215 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3216}
3217
3218/*
3219 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3220 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3221 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3222 * it for some reason. *tmpdevice is the target we're adding,
3223 * this_device is a pointer into the current element of currentsd[]
3224 * that we're building up in update_scsi_devices(), below.
3225 * lunzerobits is a bitmap that tracks which targets already have a
3226 * lun 0 assigned.
3227 * Returns 1 if an enclosure was added, 0 if not.
3228 */
4f4eb9f1 3229static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3230 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3231 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3232 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3233{
3234 unsigned char scsi3addr[8];
3235
1f310bde 3236 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3237 return 0; /* There is already a lun 0 on this target. */
3238
3239 if (!is_logical_dev_addr_mode(lunaddrbytes))
3240 return 0; /* It's the logical targets that may lack lun 0. */
3241
4f4eb9f1
ST		 3242 if (!is_ext_target(h, tmpdevice))
3243 return 0; /* Only external target devices have this problem. */
edd16368 3244
1f310bde 3245 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3246 return 0;
3247
c4f8a299 3248 memset(scsi3addr, 0, 8);
1f310bde 3249 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3250 if (is_hba_lunid(scsi3addr))
3251 return 0; /* Don't add the RAID controller here. */
3252
339b2b14
SC		 3253 if (is_scsi_rev_5(h))
3254 return 0; /* p1210m doesn't need to do this. */
3255
4f4eb9f1 3256 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3257 dev_warn(&h->pdev->dev, "Maximum number of external "
3258 "target devices exceeded. Check your hardware "
edd16368
SC		 3259 "configuration.");
3260 return 0;
3261 }
3262
0b0e1d6c 3263 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3264 return 0;
4f4eb9f1 3265 (*n_ext_target_devs)++;
1f310bde
SC		 3266 hpsa_set_bus_target_lun(this_device,
3267 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3268 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3269 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3270 return 1;
3271}
3272
54b6e9e9
ST		 3273/*
3274 * Get address of physical disk used for an ioaccel2 mode command:
3275 * 1. Extract ioaccel2 handle from the command.
3276 * 2. Find a matching ioaccel2 handle from list of physical disks.
3277 * 3. Return:
3278 * 1 and set scsi3addr to address of matching physical
3279 * 0 if no matching physical disk was found.
3280 */
3281static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3282 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3283{
41ce4c35
SC		 3284 struct io_accel2_cmd *c2 =
3285 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3286 unsigned long flags;
54b6e9e9 3287 int i;
54b6e9e9 3288
41ce4c35
SC		 3289 spin_lock_irqsave(&h->devlock, flags);
3290 for (i = 0; i < h->ndevices; i++)
3291 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3292 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3293 sizeof(h->dev[i]->scsi3addr));
3294 spin_unlock_irqrestore(&h->devlock, flags);
3295 return 1;
3296 }
3297 spin_unlock_irqrestore(&h->devlock, flags);
3298 return 0;
54b6e9e9 3299}
41ce4c35 3300
edd16368
SC		 3301/*
3302 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3303 * logdev. The number of luns in physdev and logdev are returned in
3304 * *nphysicals and *nlogicals, respectively.
3305 * Returns 0 on success, -1 otherwise.
3306 */
3307static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3308 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3309 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3310{
03383736 3311 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3312 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3313 return -1;
3314 }
03383736 3315 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3316 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3317 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3318 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3319 *nphysicals = HPSA_MAX_PHYS_LUN;
3320 }
03383736 3321 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3322 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3323 return -1;
3324 }
6df1e954 3325 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3326 /* Reject Logicals in excess of our max capability. */
3327 if (*nlogicals > HPSA_MAX_LUN) {
3328 dev_warn(&h->pdev->dev,
3329 "maximum logical LUNs (%d) exceeded. "
3330 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3331 *nlogicals - HPSA_MAX_LUN);
3332 *nlogicals = HPSA_MAX_LUN;
3333 }
3334 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3335 dev_warn(&h->pdev->dev,
3336 "maximum logical + physical LUNs (%d) exceeded. "
3337 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3338 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3339 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3340 }
3341 return 0;
3342}
3343
42a91641
DB		 3344static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3345 int i, int nphysicals, int nlogicals,
a93aa1fe 3346 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3347 struct ReportLUNdata *logdev_list)
3348{
3349 /* Helper function, figure out where the LUN ID info is coming from
3350 * given index i, lists of physical and logical devices, where in
3351 * the list the raid controller is supposed to appear (first or last)
3352 */
3353
3354 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3355 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3356
3357 if (i == raid_ctlr_position)
3358 return RAID_CTLR_LUNID;
3359
3360 if (i < logicals_start)
d5b5d964
SC		 3361 return &physdev_list->LUN[i -
3362 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3363
3364 if (i < last_device)
3365 return &logdev_list->LUN[i - nphysicals -
3366 (raid_ctlr_position == 0)][0];
3367 BUG();
3368 return NULL;
3369}
3370
316b221a
SC		 3371static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3372{
3373 int rc;
6e8e8088 3374 int hba_mode_enabled;
316b221a
SC		 3375 struct bmic_controller_parameters *ctlr_params;
3376 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3377 GFP_KERNEL);
3378
3379 if (!ctlr_params)
96444fbb 3380 return -ENOMEM;
316b221a
SC		 3381 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3382 sizeof(struct bmic_controller_parameters));
96444fbb 3383 if (rc) {
316b221a 3384 kfree(ctlr_params);
96444fbb 3385 return rc;
316b221a 3386 }
6e8e8088
JH		 3387
3388 hba_mode_enabled =
3389 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3390 kfree(ctlr_params);
3391 return hba_mode_enabled;
316b221a
SC		 3392}
3393
03383736
DB		 3394/* get physical drive ioaccel handle and queue depth */
3395static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3396 struct hpsa_scsi_dev_t *dev,
3397 u8 *lunaddrbytes,
3398 struct bmic_identify_physical_device *id_phys)
3399{
3400 int rc;
3401 struct ext_report_lun_entry *rle =
3402 (struct ext_report_lun_entry *) lunaddrbytes;
3403
3404 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3405 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3406 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3407 memset(id_phys, 0, sizeof(*id_phys));
3408 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3409 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3410 sizeof(*id_phys));
3411 if (!rc)
3412 /* Reserve space for FW operations */
3413#define DRIVE_CMDS_RESERVED_FOR_FW 2
3414#define DRIVE_QUEUE_DEPTH 7
3415 dev->queue_depth =
3416 le16_to_cpu(id_phys->current_queue_depth_limit) -
3417 DRIVE_CMDS_RESERVED_FOR_FW;
3418 else
3419 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3420 atomic_set(&dev->ioaccel_cmds_out, 0);
3421}
3422
edd16368
SC		 3423static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3424{
3425 /* the idea here is we could get notified
3426 * that some devices have changed, so we do a report
3427 * physical luns and report logical luns cmd, and adjust
3428 * our list of devices accordingly.
3429 *
3430 * The scsi3addr's of devices won't change so long as the
3431 * adapter is not reset. That means we can rescan and
3432 * tell which devices we already know about, vs. new
3433 * devices, vs. disappearing devices.
3434 */
a93aa1fe 3435 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3436 struct ReportLUNdata *logdev_list = NULL;
03383736 3437 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3438 u32 nphysicals = 0;
3439 u32 nlogicals = 0;
3440 u32 ndev_allocated = 0;
edd16368
SC		 3441 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3442 int ncurrent = 0;
4f4eb9f1 3443 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3444 int raid_ctlr_position;
2bbf5c7f 3445 int rescan_hba_mode;
aca4a520 3446 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3447
cfe5badc 3448 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3449 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3450 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3451 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3452 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3453
03383736
DB		 3454 if (!currentsd || !physdev_list || !logdev_list ||
3455 !tmpdevice || !id_phys) {
edd16368
SC		 3456 dev_err(&h->pdev->dev, "out of memory\n");
3457 goto out;
3458 }
3459 memset(lunzerobits, 0, sizeof(lunzerobits));
3460
316b221a 3461 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3462 if (rescan_hba_mode < 0)
3463 goto out;
316b221a
SC		 3464
3465 if (!h->hba_mode_enabled && rescan_hba_mode)
3466 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3467 else if (h->hba_mode_enabled && !rescan_hba_mode)
3468 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3469
3470 h->hba_mode_enabled = rescan_hba_mode;
3471
03383736
DB		 3472 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3473 logdev_list, &nlogicals))
edd16368
SC		 3474 goto out;
3475
aca4a520
ST		 3476 /* We might see up to the maximum number of logical and physical disks
3477 * plus external target devices, and a device for the local RAID
3478 * controller.
edd16368 3479 */
aca4a520 3480 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3481
3482 /* Allocate the per device structures */
3483 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3484 if (i >= HPSA_MAX_DEVICES) {
3485 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3486 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3487 ndevs_to_allocate - HPSA_MAX_DEVICES);
3488 break;
3489 }
3490
edd16368
SC		 3491 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3492 if (!currentsd[i]) {
3493 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3494 __FILE__, __LINE__);
3495 goto out;
3496 }
3497 ndev_allocated++;
3498 }
3499
8645291b 3500 if (is_scsi_rev_5(h))
339b2b14
SC		 3501 raid_ctlr_position = 0;
3502 else
3503 raid_ctlr_position = nphysicals + nlogicals;
3504
edd16368 3505 /* adjust our table of devices */
4f4eb9f1 3506 n_ext_target_devs = 0;
edd16368 3507 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3508 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3509
3510 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3511 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3512 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3513
3514 /* skip masked non-disk devices */
3515 if (MASKED_DEVICE(lunaddrbytes))
3516 if (i < nphysicals + (raid_ctlr_position == 0) &&
3517 NON_DISK_PHYS_DEV(lunaddrbytes))
3518 continue;
edd16368
SC		 3519
3520 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3521 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3522 &is_OBDR))
edd16368 3523 continue; /* skip it if we can't talk to it. */
1f310bde 3524 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3525 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3526 this_device = currentsd[ncurrent];
3527
3528 /*
4f4eb9f1 3529 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3530 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3531 * is nonetheless an enclosure device there. We have to
3532 * present that otherwise linux won't find anything if
3533 * there is no lun 0.
3534 */
4f4eb9f1 3535 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3536 lunaddrbytes, lunzerobits,
4f4eb9f1 3537 &n_ext_target_devs)) {
edd16368
SC		 3538 ncurrent++;
3539 this_device = currentsd[ncurrent];
3540 }
3541
3542 *this_device = *tmpdevice;
edd16368 3543
41ce4c35
SC		 3544 /* do not expose masked devices */
3545 if (MASKED_DEVICE(lunaddrbytes) &&
3546 i < nphysicals + (raid_ctlr_position == 0)) {
3547 if (h->hba_mode_enabled)
3548 dev_warn(&h->pdev->dev,
3549 "Masked physical device detected\n");
3550 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3551 } else {
3552 this_device->expose_state =
3553 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3554 }
3555
edd16368 3556 switch (this_device->devtype) {
0b0e1d6c 3557 case TYPE_ROM:
edd16368
SC		 3558 /* We don't *really* support actual CD-ROM devices,
3559 * just "One Button Disaster Recovery" tape drive
3560 * which temporarily pretends to be a CD-ROM drive.
3561 * So we check that the device is really an OBDR tape
3562 * device by checking for "$DR-10" in bytes 43-48 of
3563 * the inquiry data.
3564 */
0b0e1d6c
SC		 3565 if (is_OBDR)
3566 ncurrent++;
edd16368
SC		 3567 break;
3568 case TYPE_DISK:
ecf418d1 3569 if (i >= nphysicals) {
316b221a
SC		 3570 ncurrent++;
3571 break;
283b4a9b 3572 }
ecf418d1
JH		 3573
3574 if (h->hba_mode_enabled)
3575 /* never use raid mapper in HBA mode */
3576 this_device->offload_enabled = 0;
3577 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3578 h->transMethod & CFGTBL_Trans_io_accel2))
3579 break;
3580
3581 hpsa_get_ioaccel_drive_info(h, this_device,
3582 lunaddrbytes, id_phys);
3583 atomic_set(&this_device->ioaccel_cmds_out, 0);
3584 ncurrent++;
edd16368
SC		 3585 break;
3586 case TYPE_TAPE:
3587 case TYPE_MEDIUM_CHANGER:
3588 ncurrent++;
3589 break;
41ce4c35
SC		 3590 case TYPE_ENCLOSURE:
3591 if (h->hba_mode_enabled)
3592 ncurrent++;
3593 break;
edd16368
SC		 3594 case TYPE_RAID:
3595 /* Only present the Smartarray HBA as a RAID controller.
3596 * If it's a RAID controller other than the HBA itself
3597 * (an external RAID controller, MSA500 or similar)
3598 * don't present it.
3599 */
3600 if (!is_hba_lunid(lunaddrbytes))
3601 break;
3602 ncurrent++;
3603 break;
3604 default:
3605 break;
3606 }
cfe5badc 3607 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3608 break;
3609 }
3610 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3611out:
3612 kfree(tmpdevice);
3613 for (i = 0; i < ndev_allocated; i++)
3614 kfree(currentsd[i]);
3615 kfree(currentsd);
edd16368
SC		 3616 kfree(physdev_list);
3617 kfree(logdev_list);
03383736 3618 kfree(id_phys);
edd16368
SC		 3619}
3620
ec5cbf04
WS		 3621static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3622 struct scatterlist *sg)
3623{
3624 u64 addr64 = (u64) sg_dma_address(sg);
3625 unsigned int len = sg_dma_len(sg);
3626
3627 desc->Addr = cpu_to_le64(addr64);
3628 desc->Len = cpu_to_le32(len);
3629 desc->Ext = 0;
3630}
3631
c7ee65b3
WS		 3632/*
3633 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3634 * dma mapping and fills in the scatter gather entries of the
3635 * hpsa command, cp.
3636 */
33a2ffce 3637static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3638 struct CommandList *cp,
3639 struct scsi_cmnd *cmd)
3640{
edd16368 3641 struct scatterlist *sg;
33a2ffce
SC		 3642 int use_sg, i, sg_index, chained;
3643 struct SGDescriptor *curr_sg;
edd16368 3644
33a2ffce 3645 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3646
3647 use_sg = scsi_dma_map(cmd);
3648 if (use_sg < 0)
3649 return use_sg;
3650
3651 if (!use_sg)
3652 goto sglist_finished;
3653
33a2ffce
SC		 3654 curr_sg = cp->SG;
3655 chained = 0;
3656 sg_index = 0;
edd16368 3657 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3658 if (i == h->max_cmd_sg_entries - 1 &&
3659 use_sg > h->max_cmd_sg_entries) {
3660 chained = 1;
3661 curr_sg = h->cmd_sg_list[cp->cmdindex];
3662 sg_index = 0;
3663 }
ec5cbf04 3664 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3665 curr_sg++;
3666 }
ec5cbf04
WS		 3667
3668 /* Back the pointer up to the last entry and mark it as "last". */
50a0decf 3669 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3670
3671 if (use_sg + chained > h->maxSG)
3672 h->maxSG = use_sg + chained;
3673
3674 if (chained) {
3675 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3676 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3677 if (hpsa_map_sg_chain_block(h, cp)) {
3678 scsi_dma_unmap(cmd);
3679 return -1;
3680 }
33a2ffce 3681 return 0;
edd16368
SC		 3682 }
3683
3684sglist_finished:
3685
01a02ffc 3686 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3687 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3688 return 0;
3689}
3690
283b4a9b
SC		 3691#define IO_ACCEL_INELIGIBLE (1)
3692static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3693{
3694 int is_write = 0;
3695 u32 block;
3696 u32 block_cnt;
3697
3698 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3699 switch (cdb[0]) {
3700 case WRITE_6:
3701 case WRITE_12:
3702 is_write = 1;
3703 case READ_6:
3704 case READ_12:
3705 if (*cdb_len == 6) {
3706 block = (((u32) cdb[2]) << 8) | cdb[3];
3707 block_cnt = cdb[4];
3708 } else {
3709 BUG_ON(*cdb_len != 12);
3710 block = (((u32) cdb[2]) << 24) |
3711 (((u32) cdb[3]) << 16) |
3712 (((u32) cdb[4]) << 8) |
3713 cdb[5];
3714 block_cnt =
3715 (((u32) cdb[6]) << 24) |
3716 (((u32) cdb[7]) << 16) |
3717 (((u32) cdb[8]) << 8) |
3718 cdb[9];
3719 }
3720 if (block_cnt > 0xffff)
3721 return IO_ACCEL_INELIGIBLE;
3722
3723 cdb[0] = is_write ? WRITE_10 : READ_10;
3724 cdb[1] = 0;
3725 cdb[2] = (u8) (block >> 24);
3726 cdb[3] = (u8) (block >> 16);
3727 cdb[4] = (u8) (block >> 8);
3728 cdb[5] = (u8) (block);
3729 cdb[6] = 0;
3730 cdb[7] = (u8) (block_cnt >> 8);
3731 cdb[8] = (u8) (block_cnt);
3732 cdb[9] = 0;
3733 *cdb_len = 10;
3734 break;
3735 }
3736 return 0;
3737}
3738
c349775e 3739static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3740 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3741 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3742{
3743 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3744 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3745 unsigned int len;
3746 unsigned int total_len = 0;
3747 struct scatterlist *sg;
3748 u64 addr64;
3749 int use_sg, i;
3750 struct SGDescriptor *curr_sg;
3751 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3752
283b4a9b 3753 /* TODO: implement chaining support */
03383736
DB		 3754 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3755 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3756 return IO_ACCEL_INELIGIBLE;
03383736 3757 }
283b4a9b 3758
e1f7de0c
MG		 3759 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3760
03383736
DB		 3761 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3762 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3763 return IO_ACCEL_INELIGIBLE;
03383736 3764 }
283b4a9b 3765
e1f7de0c
MG		 3766 c->cmd_type = CMD_IOACCEL1;
3767
3768 /* Adjust the DMA address to point to the accelerated command buffer */
3769 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3770 (c->cmdindex * sizeof(*cp));
3771 BUG_ON(c->busaddr & 0x0000007F);
3772
3773 use_sg = scsi_dma_map(cmd);
03383736
DB		 3774 if (use_sg < 0) {
3775 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3776 return use_sg;
03383736 3777 }
e1f7de0c
MG		 3778
3779 if (use_sg) {
3780 curr_sg = cp->SG;
3781 scsi_for_each_sg(cmd, sg, use_sg, i) {
3782 addr64 = (u64) sg_dma_address(sg);
3783 len = sg_dma_len(sg);
3784 total_len += len;
50a0decf
SC		 3785 curr_sg->Addr = cpu_to_le64(addr64);
3786 curr_sg->Len = cpu_to_le32(len);
3787 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3788 curr_sg++;
3789 }
50a0decf 3790 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3791
3792 switch (cmd->sc_data_direction) {
3793 case DMA_TO_DEVICE:
3794 control |= IOACCEL1_CONTROL_DATA_OUT;
3795 break;
3796 case DMA_FROM_DEVICE:
3797 control |= IOACCEL1_CONTROL_DATA_IN;
3798 break;
3799 case DMA_NONE:
3800 control |= IOACCEL1_CONTROL_NODATAXFER;
3801 break;
3802 default:
3803 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3804 cmd->sc_data_direction);
3805 BUG();
3806 break;
3807 }
3808 } else {
3809 control |= IOACCEL1_CONTROL_NODATAXFER;
3810 }
3811
c349775e 3812 c->Header.SGList = use_sg;
e1f7de0c 3813 /* Fill out the command structure to submit */
2b08b3e9
DB		 3814 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3815 cp->transfer_len = cpu_to_le32(total_len);
3816 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3817 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3818 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3819 memcpy(cp->CDB, cdb, cdb_len);
3820 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3821 /* Tag was already set at init time. */
283b4a9b 3822 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3823 return 0;
3824}
edd16368 3825
283b4a9b
SC		 3826/*
3827 * Queue a command directly to a device behind the controller using the
3828 * I/O accelerator path.
3829 */
3830static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3831 struct CommandList *c)
3832{
3833 struct scsi_cmnd *cmd = c->scsi_cmd;
3834 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3835
03383736
DB		 3836 c->phys_disk = dev;
3837
283b4a9b 3838 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3839 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3840}
3841
dd0e19f3
ST		 3842/*
3843 * Set encryption parameters for the ioaccel2 request
3844 */
3845static void set_encrypt_ioaccel2(struct ctlr_info *h,
3846 struct CommandList *c, struct io_accel2_cmd *cp)
3847{
3848 struct scsi_cmnd *cmd = c->scsi_cmd;
3849 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3850 struct raid_map_data *map = &dev->raid_map;
3851 u64 first_block;
3852
dd0e19f3 3853 /* Are we doing encryption on this device */
2b08b3e9 3854 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3855 return;
3856 /* Set the data encryption key index. */
3857 cp->dekindex = map->dekindex;
3858
3859 /* Set the encryption enable flag, encoded into direction field. */
3860 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3861
3862 /* Set encryption tweak values based on logical block address
3863 * If block size is 512, tweak value is LBA.
3864 * For other block sizes, tweak is (LBA * block size)/ 512)
3865 */
3866 switch (cmd->cmnd[0]) {
3867 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3868 case WRITE_6:
3869 case READ_6:
2b08b3e9 3870 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3871 break;
3872 case WRITE_10:
3873 case READ_10:
dd0e19f3
ST		 3874 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3875 case WRITE_12:
3876 case READ_12:
2b08b3e9 3877 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3878 break;
3879 case WRITE_16:
3880 case READ_16:
2b08b3e9 3881 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3882 break;
3883 default:
3884 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3885 "ERROR: %s: size (0x%x) not supported for encryption\n",
3886 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3887 BUG();
3888 break;
3889 }
2b08b3e9
DB		 3890
3891 if (le32_to_cpu(map->volume_blk_size) != 512)
3892 first_block = first_block *
3893 le32_to_cpu(map->volume_blk_size)/512;
3894
3895 cp->tweak_lower = cpu_to_le32(first_block);
3896 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3897}
3898
c349775e
ST		 3899static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3900 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3901 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3902{
3903 struct scsi_cmnd *cmd = c->scsi_cmd;
3904 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3905 struct ioaccel2_sg_element *curr_sg;
3906 int use_sg, i;
3907 struct scatterlist *sg;
3908 u64 addr64;
3909 u32 len;
3910 u32 total_len = 0;
3911
d9a729f3 3912 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 3913
03383736
DB		 3914 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3915 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3916 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3917 }
3918
c349775e
ST		 3919 c->cmd_type = CMD_IOACCEL2;
3920 /* Adjust the DMA address to point to the accelerated command buffer */
3921 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3922 (c->cmdindex * sizeof(*cp));
3923 BUG_ON(c->busaddr & 0x0000007F);
3924
3925 memset(cp, 0, sizeof(*cp));
3926 cp->IU_type = IOACCEL2_IU_TYPE;
3927
3928 use_sg = scsi_dma_map(cmd);
03383736
DB		 3929 if (use_sg < 0) {
3930 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3931 return use_sg;
03383736 3932 }
c349775e
ST		 3933
3934 if (use_sg) {
c349775e 3935 curr_sg = cp->sg;
d9a729f3
WS		 3936 if (use_sg > h->ioaccel_maxsg) {
3937 addr64 = le64_to_cpu(
3938 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
3939 curr_sg->address = cpu_to_le64(addr64);
3940 curr_sg->length = 0;
3941 curr_sg->reserved[0] = 0;
3942 curr_sg->reserved[1] = 0;
3943 curr_sg->reserved[2] = 0;
3944 curr_sg->chain_indicator = 0x80;
3945
3946 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
3947 }
c349775e
ST		 3948 scsi_for_each_sg(cmd, sg, use_sg, i) {
3949 addr64 = (u64) sg_dma_address(sg);
3950 len = sg_dma_len(sg);
3951 total_len += len;
3952 curr_sg->address = cpu_to_le64(addr64);
3953 curr_sg->length = cpu_to_le32(len);
3954 curr_sg->reserved[0] = 0;
3955 curr_sg->reserved[1] = 0;
3956 curr_sg->reserved[2] = 0;
3957 curr_sg->chain_indicator = 0;
3958 curr_sg++;
3959 }
3960
3961 switch (cmd->sc_data_direction) {
3962 case DMA_TO_DEVICE:
dd0e19f3
ST		 3963 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3964 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3965 break;
3966 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3967 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3968 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3969 break;
3970 case DMA_NONE:
dd0e19f3
ST		 3971 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3972 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3973 break;
3974 default:
3975 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3976 cmd->sc_data_direction);
3977 BUG();
3978 break;
3979 }
3980 } else {
dd0e19f3
ST		 3981 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3982 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3983 }
dd0e19f3
ST		 3984
3985 /* Set encryption parameters, if necessary */
3986 set_encrypt_ioaccel2(h, c, cp);
3987
2b08b3e9 3988 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3989 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3990 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 3991
c349775e
ST		 3992 cp->data_len = cpu_to_le32(total_len);
3993 cp->err_ptr = cpu_to_le64(c->busaddr +
3994 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3995 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 3996
d9a729f3
WS		 3997 /* fill in sg elements */
3998 if (use_sg > h->ioaccel_maxsg) {
3999 cp->sg_count = 1;
4000 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4001 atomic_dec(&phys_disk->ioaccel_cmds_out);
4002 scsi_dma_unmap(cmd);
4003 return -1;
4004 }
4005 } else
4006 cp->sg_count = (u8) use_sg;
4007
c349775e
ST		 4008 enqueue_cmd_and_start_io(h, c);
4009 return 0;
4010}
4011
4012/*
4013 * Queue a command to the correct I/O accelerator path.
4014 */
4015static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4016 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4017 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4018{
03383736
DB		 4019 /* Try to honor the device's queue depth */
4020 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4021 phys_disk->queue_depth) {
4022 atomic_dec(&phys_disk->ioaccel_cmds_out);
4023 return IO_ACCEL_INELIGIBLE;
4024 }
c349775e
ST		 4025 if (h->transMethod & CFGTBL_Trans_io_accel1)
4026 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4027 cdb, cdb_len, scsi3addr,
4028 phys_disk);
c349775e
ST		 4029 else
4030 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4031 cdb, cdb_len, scsi3addr,
4032 phys_disk);
c349775e
ST		 4033}
4034
6b80b18f
ST		 4035static void raid_map_helper(struct raid_map_data *map,
4036 int offload_to_mirror, u32 *map_index, u32 *current_group)
4037{
4038 if (offload_to_mirror == 0) {
4039 /* use physical disk in the first mirrored group. */
2b08b3e9 4040 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4041 return;
4042 }
4043 do {
4044 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4045 *current_group = *map_index /
4046 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4047 if (offload_to_mirror == *current_group)
4048 continue;
2b08b3e9 4049 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4050 /* select map index from next group */
2b08b3e9 4051 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4052 (*current_group)++;
4053 } else {
4054 /* select map index from first group */
2b08b3e9 4055 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4056 *current_group = 0;
4057 }
4058 } while (offload_to_mirror != *current_group);
4059}
4060
283b4a9b
SC		 4061/*
4062 * Attempt to perform offload RAID mapping for a logical volume I/O.
4063 */
4064static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4065 struct CommandList *c)
4066{
4067 struct scsi_cmnd *cmd = c->scsi_cmd;
4068 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4069 struct raid_map_data *map = &dev->raid_map;
4070 struct raid_map_disk_data *dd = &map->data[0];
4071 int is_write = 0;
4072 u32 map_index;
4073 u64 first_block, last_block;
4074 u32 block_cnt;
4075 u32 blocks_per_row;
4076 u64 first_row, last_row;
4077 u32 first_row_offset, last_row_offset;
4078 u32 first_column, last_column;
6b80b18f
ST		 4079 u64 r0_first_row, r0_last_row;
4080 u32 r5or6_blocks_per_row;
4081 u64 r5or6_first_row, r5or6_last_row;
4082 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4083 u32 r5or6_first_column, r5or6_last_column;
4084 u32 total_disks_per_row;
4085 u32 stripesize;
4086 u32 first_group, last_group, current_group;
283b4a9b
SC		 4087 u32 map_row;
4088 u32 disk_handle;
4089 u64 disk_block;
4090 u32 disk_block_cnt;
4091 u8 cdb[16];
4092 u8 cdb_len;
2b08b3e9 4093 u16 strip_size;
283b4a9b
SC		 4094#if BITS_PER_LONG == 32
4095 u64 tmpdiv;
4096#endif
6b80b18f 4097 int offload_to_mirror;
283b4a9b 4098
283b4a9b
SC		 4099 /* check for valid opcode, get LBA and block count */
4100 switch (cmd->cmnd[0]) {
4101 case WRITE_6:
4102 is_write = 1;
4103 case READ_6:
4104 first_block =
4105 (((u64) cmd->cmnd[2]) << 8) |
4106 cmd->cmnd[3];
4107 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4108 if (block_cnt == 0)
4109 block_cnt = 256;
283b4a9b
SC		 4110 break;
4111 case WRITE_10:
4112 is_write = 1;
4113 case READ_10:
4114 first_block =
4115 (((u64) cmd->cmnd[2]) << 24) |
4116 (((u64) cmd->cmnd[3]) << 16) |
4117 (((u64) cmd->cmnd[4]) << 8) |
4118 cmd->cmnd[5];
4119 block_cnt =
4120 (((u32) cmd->cmnd[7]) << 8) |
4121 cmd->cmnd[8];
4122 break;
4123 case WRITE_12:
4124 is_write = 1;
4125 case READ_12:
4126 first_block =
4127 (((u64) cmd->cmnd[2]) << 24) |
4128 (((u64) cmd->cmnd[3]) << 16) |
4129 (((u64) cmd->cmnd[4]) << 8) |
4130 cmd->cmnd[5];
4131 block_cnt =
4132 (((u32) cmd->cmnd[6]) << 24) |
4133 (((u32) cmd->cmnd[7]) << 16) |
4134 (((u32) cmd->cmnd[8]) << 8) |
4135 cmd->cmnd[9];
4136 break;
4137 case WRITE_16:
4138 is_write = 1;
4139 case READ_16:
4140 first_block =
4141 (((u64) cmd->cmnd[2]) << 56) |
4142 (((u64) cmd->cmnd[3]) << 48) |
4143 (((u64) cmd->cmnd[4]) << 40) |
4144 (((u64) cmd->cmnd[5]) << 32) |
4145 (((u64) cmd->cmnd[6]) << 24) |
4146 (((u64) cmd->cmnd[7]) << 16) |
4147 (((u64) cmd->cmnd[8]) << 8) |
4148 cmd->cmnd[9];
4149 block_cnt =
4150 (((u32) cmd->cmnd[10]) << 24) |
4151 (((u32) cmd->cmnd[11]) << 16) |
4152 (((u32) cmd->cmnd[12]) << 8) |
4153 cmd->cmnd[13];
4154 break;
4155 default:
4156 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4157 }
283b4a9b
SC		 4158 last_block = first_block + block_cnt - 1;
4159
4160 /* check for write to non-RAID-0 */
4161 if (is_write && dev->raid_level != 0)
4162 return IO_ACCEL_INELIGIBLE;
4163
4164 /* check for invalid block or wraparound */
2b08b3e9
DB		 4165 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4166 last_block < first_block)
283b4a9b
SC		 4167 return IO_ACCEL_INELIGIBLE;
4168
4169 /* calculate stripe information for the request */
2b08b3e9
DB		 4170 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4171 le16_to_cpu(map->strip_size);
4172 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4173#if BITS_PER_LONG == 32
4174 tmpdiv = first_block;
4175 (void) do_div(tmpdiv, blocks_per_row);
4176 first_row = tmpdiv;
4177 tmpdiv = last_block;
4178 (void) do_div(tmpdiv, blocks_per_row);
4179 last_row = tmpdiv;
4180 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4181 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4182 tmpdiv = first_row_offset;
2b08b3e9 4183 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4184 first_column = tmpdiv;
4185 tmpdiv = last_row_offset;
2b08b3e9 4186 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4187 last_column = tmpdiv;
4188#else
4189 first_row = first_block / blocks_per_row;
4190 last_row = last_block / blocks_per_row;
4191 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4192 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4193 first_column = first_row_offset / strip_size;
4194 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4195#endif
4196
4197 /* if this isn't a single row/column then give to the controller */
4198 if ((first_row != last_row) || (first_column != last_column))
4199 return IO_ACCEL_INELIGIBLE;
4200
4201 /* proceeding with driver mapping */
2b08b3e9
DB		 4202 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4203 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4204 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4205 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4206 map_index = (map_row * total_disks_per_row) + first_column;
4207
4208 switch (dev->raid_level) {
4209 case HPSA_RAID_0:
4210 break; /* nothing special to do */
4211 case HPSA_RAID_1:
4212 /* Handles load balance across RAID 1 members.
4213 * (2-drive R1 and R10 with even # of drives.)
4214 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4215 */
2b08b3e9 4216 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4217 if (dev->offload_to_mirror)
2b08b3e9 4218 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4219 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4220 break;
4221 case HPSA_RAID_ADM:
4222 /* Handles N-way mirrors (R1-ADM)
4223 * and R10 with # of drives divisible by 3.)
4224 */
2b08b3e9 4225 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4226
4227 offload_to_mirror = dev->offload_to_mirror;
4228 raid_map_helper(map, offload_to_mirror,
4229 &map_index, &current_group);
4230 /* set mirror group to use next time */
4231 offload_to_mirror =
2b08b3e9
DB		 4232 (offload_to_mirror >=
4233 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4234 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4235 dev->offload_to_mirror = offload_to_mirror;
4236 /* Avoid direct use of dev->offload_to_mirror within this
4237 * function since multiple threads might simultaneously
4238 * increment it beyond the range of dev->layout_map_count -1.
4239 */
4240 break;
4241 case HPSA_RAID_5:
4242 case HPSA_RAID_6:
2b08b3e9 4243 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4244 break;
4245
4246 /* Verify first and last block are in same RAID group */
4247 r5or6_blocks_per_row =
2b08b3e9
DB		 4248 le16_to_cpu(map->strip_size) *
4249 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4250 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4251 stripesize = r5or6_blocks_per_row *
4252 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4253#if BITS_PER_LONG == 32
4254 tmpdiv = first_block;
4255 first_group = do_div(tmpdiv, stripesize);
4256 tmpdiv = first_group;
4257 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4258 first_group = tmpdiv;
4259 tmpdiv = last_block;
4260 last_group = do_div(tmpdiv, stripesize);
4261 tmpdiv = last_group;
4262 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4263 last_group = tmpdiv;
4264#else
4265 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4266 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4267#endif
000ff7c2 4268 if (first_group != last_group)
6b80b18f
ST		 4269 return IO_ACCEL_INELIGIBLE;
4270
4271 /* Verify request is in a single row of RAID 5/6 */
4272#if BITS_PER_LONG == 32
4273 tmpdiv = first_block;
4274 (void) do_div(tmpdiv, stripesize);
4275 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4276 tmpdiv = last_block;
4277 (void) do_div(tmpdiv, stripesize);
4278 r5or6_last_row = r0_last_row = tmpdiv;
4279#else
4280 first_row = r5or6_first_row = r0_first_row =
4281 first_block / stripesize;
4282 r5or6_last_row = r0_last_row = last_block / stripesize;
4283#endif
4284 if (r5or6_first_row != r5or6_last_row)
4285 return IO_ACCEL_INELIGIBLE;
4286
4287
4288 /* Verify request is in a single column */
4289#if BITS_PER_LONG == 32
4290 tmpdiv = first_block;
4291 first_row_offset = do_div(tmpdiv, stripesize);
4292 tmpdiv = first_row_offset;
4293 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4294 r5or6_first_row_offset = first_row_offset;
4295 tmpdiv = last_block;
4296 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4297 tmpdiv = r5or6_last_row_offset;
4298 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4299 tmpdiv = r5or6_first_row_offset;
4300 (void) do_div(tmpdiv, map->strip_size);
4301 first_column = r5or6_first_column = tmpdiv;
4302 tmpdiv = r5or6_last_row_offset;
4303 (void) do_div(tmpdiv, map->strip_size);
4304 r5or6_last_column = tmpdiv;
4305#else
4306 first_row_offset = r5or6_first_row_offset =
4307 (u32)((first_block % stripesize) %
4308 r5or6_blocks_per_row);
4309
4310 r5or6_last_row_offset =
4311 (u32)((last_block % stripesize) %
4312 r5or6_blocks_per_row);
4313
4314 first_column = r5or6_first_column =
2b08b3e9 4315 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4316 r5or6_last_column =
2b08b3e9 4317 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4318#endif
4319 if (r5or6_first_column != r5or6_last_column)
4320 return IO_ACCEL_INELIGIBLE;
4321
4322 /* Request is eligible */
4323 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4324 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4325
4326 map_index = (first_group *
2b08b3e9 4327 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4328 (map_row * total_disks_per_row) + first_column;
4329 break;
4330 default:
4331 return IO_ACCEL_INELIGIBLE;
283b4a9b 4332 }
6b80b18f 4333
07543e0c
SC		 4334 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4335 return IO_ACCEL_INELIGIBLE;
4336
03383736
DB		 4337 c->phys_disk = dev->phys_disk[map_index];
4338
283b4a9b 4339 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4340 disk_block = le64_to_cpu(map->disk_starting_blk) +
4341 first_row * le16_to_cpu(map->strip_size) +
4342 (first_row_offset - first_column *
4343 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4344 disk_block_cnt = block_cnt;
4345
4346 /* handle differing logical/physical block sizes */
4347 if (map->phys_blk_shift) {
4348 disk_block <<= map->phys_blk_shift;
4349 disk_block_cnt <<= map->phys_blk_shift;
4350 }
4351 BUG_ON(disk_block_cnt > 0xffff);
4352
4353 /* build the new CDB for the physical disk I/O */
4354 if (disk_block > 0xffffffff) {
4355 cdb[0] = is_write ? WRITE_16 : READ_16;
4356 cdb[1] = 0;
4357 cdb[2] = (u8) (disk_block >> 56);
4358 cdb[3] = (u8) (disk_block >> 48);
4359 cdb[4] = (u8) (disk_block >> 40);
4360 cdb[5] = (u8) (disk_block >> 32);
4361 cdb[6] = (u8) (disk_block >> 24);
4362 cdb[7] = (u8) (disk_block >> 16);
4363 cdb[8] = (u8) (disk_block >> 8);
4364 cdb[9] = (u8) (disk_block);
4365 cdb[10] = (u8) (disk_block_cnt >> 24);
4366 cdb[11] = (u8) (disk_block_cnt >> 16);
4367 cdb[12] = (u8) (disk_block_cnt >> 8);
4368 cdb[13] = (u8) (disk_block_cnt);
4369 cdb[14] = 0;
4370 cdb[15] = 0;
4371 cdb_len = 16;
4372 } else {
4373 cdb[0] = is_write ? WRITE_10 : READ_10;
4374 cdb[1] = 0;
4375 cdb[2] = (u8) (disk_block >> 24);
4376 cdb[3] = (u8) (disk_block >> 16);
4377 cdb[4] = (u8) (disk_block >> 8);
4378 cdb[5] = (u8) (disk_block);
4379 cdb[6] = 0;
4380 cdb[7] = (u8) (disk_block_cnt >> 8);
4381 cdb[8] = (u8) (disk_block_cnt);
4382 cdb[9] = 0;
4383 cdb_len = 10;
4384 }
4385 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4386 dev->scsi3addr,
4387 dev->phys_disk[map_index]);
283b4a9b
SC		 4388}
4389
25163bd5
WS		 4390/*
4391 * Submit commands down the "normal" RAID stack path
4392 * All callers to hpsa_ciss_submit must check lockup_detected
4393 * beforehand, before (opt.) and after calling cmd_alloc
4394 */
574f05d3
SC		 4395static int hpsa_ciss_submit(struct ctlr_info *h,
4396 struct CommandList *c, struct scsi_cmnd *cmd,
4397 unsigned char scsi3addr[])
edd16368 4398{
edd16368 4399 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4400 c->cmd_type = CMD_SCSI;
4401 c->scsi_cmd = cmd;
4402 c->Header.ReplyQueue = 0; /* unused in simple mode */
4403 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4404 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4405
4406 /* Fill in the request block... */
4407
4408 c->Request.Timeout = 0;
edd16368
SC		 4409 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4410 c->Request.CDBLen = cmd->cmd_len;
4411 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4412 switch (cmd->sc_data_direction) {
4413 case DMA_TO_DEVICE:
a505b86f
SC		 4414 c->Request.type_attr_dir =
4415 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4416 break;
4417 case DMA_FROM_DEVICE:
a505b86f
SC		 4418 c->Request.type_attr_dir =
4419 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4420 break;
4421 case DMA_NONE:
a505b86f
SC		 4422 c->Request.type_attr_dir =
4423 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4424 break;
4425 case DMA_BIDIRECTIONAL:
4426 /* This can happen if a buggy application does a scsi passthru
4427 * and sets both inlen and outlen to non-zero. ( see
4428 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4429 */
4430
a505b86f
SC		 4431 c->Request.type_attr_dir =
4432 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4433 /* This is technically wrong, and hpsa controllers should
4434 * reject it with CMD_INVALID, which is the most correct
4435 * response, but non-fibre backends appear to let it
4436 * slide by, and give the same results as if this field
4437 * were set correctly. Either way is acceptable for
4438 * our purposes here.
4439 */
4440
4441 break;
4442
4443 default:
4444 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4445 cmd->sc_data_direction);
4446 BUG();
4447 break;
4448 }
4449
33a2ffce 4450 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4451 cmd_free(h, c);
4452 return SCSI_MLQUEUE_HOST_BUSY;
4453 }
4454 enqueue_cmd_and_start_io(h, c);
4455 /* the cmd'll come back via intr handler in complete_scsi_command() */
4456 return 0;
4457}
4458
360c73bd
SC		 4459static void hpsa_cmd_init(struct ctlr_info *h, int index,
4460 struct CommandList *c)
4461{
4462 dma_addr_t cmd_dma_handle, err_dma_handle;
4463
4464 /* Zero out all of commandlist except the last field, refcount */
4465 memset(c, 0, offsetof(struct CommandList, refcount));
4466 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4467 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4468 c->err_info = h->errinfo_pool + index;
4469 memset(c->err_info, 0, sizeof(*c->err_info));
4470 err_dma_handle = h->errinfo_pool_dhandle
4471 + index * sizeof(*c->err_info);
4472 c->cmdindex = index;
4473 c->busaddr = (u32) cmd_dma_handle;
4474 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4475 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4476 c->h = h;
4477}
4478
4479static void hpsa_preinitialize_commands(struct ctlr_info *h)
4480{
4481 int i;
4482
4483 for (i = 0; i < h->nr_cmds; i++) {
4484 struct CommandList *c = h->cmd_pool + i;
4485
4486 hpsa_cmd_init(h, i, c);
4487 atomic_set(&c->refcount, 0);
4488 }
4489}
4490
4491static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4492 struct CommandList *c)
4493{
4494 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4495
4496 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4497 memset(c->err_info, 0, sizeof(*c->err_info));
4498 c->busaddr = (u32) cmd_dma_handle;
4499}
4500
592a0ad5
WS		 4501static int hpsa_ioaccel_submit(struct ctlr_info *h,
4502 struct CommandList *c, struct scsi_cmnd *cmd,
4503 unsigned char *scsi3addr)
4504{
4505 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4506 int rc = IO_ACCEL_INELIGIBLE;
4507
4508 cmd->host_scribble = (unsigned char *) c;
4509
4510 if (dev->offload_enabled) {
4511 hpsa_cmd_init(h, c->cmdindex, c);
4512 c->cmd_type = CMD_SCSI;
4513 c->scsi_cmd = cmd;
4514 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4515 if (rc < 0) /* scsi_dma_map failed. */
4516 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4517 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4518 hpsa_cmd_init(h, c->cmdindex, c);
4519 c->cmd_type = CMD_SCSI;
4520 c->scsi_cmd = cmd;
4521 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4522 if (rc < 0) /* scsi_dma_map failed. */
4523 rc = SCSI_MLQUEUE_HOST_BUSY;
4524 }
4525 return rc;
4526}
4527
080ef1cc
DB		 4528static void hpsa_command_resubmit_worker(struct work_struct *work)
4529{
4530 struct scsi_cmnd *cmd;
4531 struct hpsa_scsi_dev_t *dev;
4532 struct CommandList *c =
4533 container_of(work, struct CommandList, work);
4534
4535 cmd = c->scsi_cmd;
4536 dev = cmd->device->hostdata;
4537 if (!dev) {
4538 cmd->result = DID_NO_CONNECT << 16;
592a0ad5 4539 cmd_free(c->h, c);
080ef1cc
DB		 4540 cmd->scsi_done(cmd);
4541 return;
4542 }
592a0ad5
WS		 4543 if (c->cmd_type == CMD_IOACCEL2) {
4544 struct ctlr_info *h = c->h;
4545 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4546 int rc;
4547
4548 if (c2->error_data.serv_response ==
4549 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4550 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4551 if (rc == 0)
4552 return;
4553 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4554 /*
4555 * If we get here, it means dma mapping failed.
4556 * Try again via scsi mid layer, which will
4557 * then get SCSI_MLQUEUE_HOST_BUSY.
4558 */
4559 cmd->result = DID_IMM_RETRY << 16;
4560 cmd->scsi_done(cmd);
4561 cmd_free(h, c); /* FIX-ME: on merge, change
4562 * to cmd_tagged_free() and
4563 * ultimately to
4564 * hpsa_cmd_free_and_done(). */
4565 return;
4566 }
4567 /* else, fall thru and resubmit down CISS path */
4568 }
4569 }
360c73bd 4570 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4571 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4572 /*
4573 * If we get here, it means dma mapping failed. Try
4574 * again via scsi mid layer, which will then get
4575 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4576 *
4577 * hpsa_ciss_submit will have already freed c
4578 * if it encountered a dma mapping failure.
080ef1cc
DB		 4579 */
4580 cmd->result = DID_IMM_RETRY << 16;
4581 cmd->scsi_done(cmd);
4582 }
4583}
4584
574f05d3
SC		 4585/* Running in struct Scsi_Host->host_lock less mode */
4586static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4587{
4588 struct ctlr_info *h;
4589 struct hpsa_scsi_dev_t *dev;
4590 unsigned char scsi3addr[8];
4591 struct CommandList *c;
4592 int rc = 0;
4593
4594 /* Get the ptr to our adapter structure out of cmd->host. */
4595 h = sdev_to_hba(cmd->device);
4596 dev = cmd->device->hostdata;
4597 if (!dev) {
4598 cmd->result = DID_NO_CONNECT << 16;
4599 cmd->scsi_done(cmd);
4600 return 0;
4601 }
4602 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4603
4604 if (unlikely(lockup_detected(h))) {
25163bd5 4605 cmd->result = DID_NO_CONNECT << 16;
574f05d3
SC		 4606 cmd->scsi_done(cmd);
4607 return 0;
4608 }
4609 c = cmd_alloc(h);
4610 if (c == NULL) { /* trouble... */
4611 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4612 return SCSI_MLQUEUE_HOST_BUSY;
4613 }
407863cb 4614 if (unlikely(lockup_detected(h))) {
25163bd5 4615 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4616 cmd_free(h, c);
4617 cmd->scsi_done(cmd);
4618 return 0;
4619 }
574f05d3 4620
407863cb
SC		 4621 /*
4622 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4623 * Retries always go down the normal I/O path.
4624 */
4625 if (likely(cmd->retries == 0 &&
4626 cmd->request->cmd_type == REQ_TYPE_FS &&
4627 h->acciopath_status)) {
592a0ad5
WS		 4628 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4629 if (rc == 0)
4630 return 0;
4631 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4632 cmd_free(h, c); /* FIX-ME: on merge, change to
4633 * cmd_tagged_free(), and ultimately
4634 * to hpsa_cmd_resolve_and_free(). */
4635 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4636 }
4637 }
4638 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4639}
4640
8ebc9248 4641static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4642{
4643 unsigned long flags;
4644
8ebc9248
WS		 4645 spin_lock_irqsave(&h->scan_lock, flags);
4646 h->scan_finished = 1;
4647 wake_up_all(&h->scan_wait_queue);
4648 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4649}
4650
a08a8471
SC		 4651static void hpsa_scan_start(struct Scsi_Host *sh)
4652{
4653 struct ctlr_info *h = shost_to_hba(sh);
4654 unsigned long flags;
4655
8ebc9248
WS		 4656 /*
4657 * Don't let rescans be initiated on a controller known to be locked
4658 * up. If the controller locks up *during* a rescan, that thread is
4659 * probably hosed, but at least we can prevent new rescan threads from
4660 * piling up on a locked up controller.
4661 */
4662 if (unlikely(lockup_detected(h)))
4663 return hpsa_scan_complete(h);
5f389360 4664
a08a8471
SC		 4665 /* wait until any scan already in progress is finished. */
4666 while (1) {
4667 spin_lock_irqsave(&h->scan_lock, flags);
4668 if (h->scan_finished)
4669 break;
4670 spin_unlock_irqrestore(&h->scan_lock, flags);
4671 wait_event(h->scan_wait_queue, h->scan_finished);
4672 /* Note: We don't need to worry about a race between this
4673 * thread and driver unload because the midlayer will
4674 * have incremented the reference count, so unload won't
4675 * happen if we're in here.
4676 */
4677 }
4678 h->scan_finished = 0; /* mark scan as in progress */
4679 spin_unlock_irqrestore(&h->scan_lock, flags);
4680
8ebc9248
WS		 4681 if (unlikely(lockup_detected(h)))
4682 return hpsa_scan_complete(h);
5f389360 4683
a08a8471
SC		 4684 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4685
8ebc9248 4686 hpsa_scan_complete(h);
a08a8471
SC		 4687}
4688
7c0a0229
DB		 4689static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4690{
03383736
DB		 4691 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4692
4693 if (!logical_drive)
4694 return -ENODEV;
7c0a0229
DB		 4695
4696 if (qdepth < 1)
4697 qdepth = 1;
03383736
DB		 4698 else if (qdepth > logical_drive->queue_depth)
4699 qdepth = logical_drive->queue_depth;
4700
4701 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4702}
4703
a08a8471
SC		 4704static int hpsa_scan_finished(struct Scsi_Host *sh,
4705 unsigned long elapsed_time)
4706{
4707 struct ctlr_info *h = shost_to_hba(sh);
4708 unsigned long flags;
4709 int finished;
4710
4711 spin_lock_irqsave(&h->scan_lock, flags);
4712 finished = h->scan_finished;
4713 spin_unlock_irqrestore(&h->scan_lock, flags);
4714 return finished;
4715}
4716
edd16368
SC		 4717static void hpsa_unregister_scsi(struct ctlr_info *h)
4718{
4719 /* we are being forcibly unloaded, and may not refuse. */
4720 scsi_remove_host(h->scsi_host);
4721 scsi_host_put(h->scsi_host);
4722 h->scsi_host = NULL;
4723}
4724
4725static int hpsa_register_scsi(struct ctlr_info *h)
4726{
b705690d
SC		 4727 struct Scsi_Host *sh;
4728 int error;
edd16368 4729
b705690d
SC		 4730 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4731 if (sh == NULL)
4732 goto fail;
4733
4734 sh->io_port = 0;
4735 sh->n_io_port = 0;
4736 sh->this_id = -1;
4737 sh->max_channel = 3;
4738 sh->max_cmd_len = MAX_COMMAND_SIZE;
4739 sh->max_lun = HPSA_MAX_LUN;
4740 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4741 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4742 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4743 sh->sg_tablesize = h->maxsgentries;
4744 h->scsi_host = sh;
4745 sh->hostdata[0] = (unsigned long) h;
4746 sh->irq = h->intr[h->intr_mode];
4747 sh->unique_id = sh->irq;
4748 error = scsi_add_host(sh, &h->pdev->dev);
4749 if (error)
4750 goto fail_host_put;
4751 scsi_scan_host(sh);
4752 return 0;
4753
4754 fail_host_put:
4755 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4756 " failed for controller %d\n", __func__, h->ctlr);
4757 scsi_host_put(sh);
4758 return error;
4759 fail:
4760 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4761 " failed for controller %d\n", __func__, h->ctlr);
4762 return -ENOMEM;
edd16368
SC		 4763}
4764
4765static int wait_for_device_to_become_ready(struct ctlr_info *h,
4766 unsigned char lunaddr[])
4767{
8919358e 4768 int rc;
edd16368
SC		 4769 int count = 0;
4770 int waittime = 1; /* seconds */
4771 struct CommandList *c;
4772
45fcb86e 4773 c = cmd_alloc(h);
edd16368
SC		 4774 if (!c) {
4775 dev_warn(&h->pdev->dev, "out of memory in "
4776 "wait_for_device_to_become_ready.\n");
4777 return IO_ERROR;
4778 }
4779
4780 /* Send test unit ready until device ready, or give up. */
4781 while (count < HPSA_TUR_RETRY_LIMIT) {
4782
4783 /* Wait for a bit. do this first, because if we send
4784 * the TUR right away, the reset will just abort it.
4785 */
4786 msleep(1000 * waittime);
4787 count++;
8919358e 4788 rc = 0; /* Device ready. */
edd16368
SC		 4789
4790 /* Increase wait time with each try, up to a point. */
4791 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4792 waittime = waittime * 2;
4793
a2dac136
SC		 4794 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4795 (void) fill_cmd(c, TEST_UNIT_READY, h,
4796 NULL, 0, 0, lunaddr, TYPE_CMD);
25163bd5
WS		 4797 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
4798 NO_TIMEOUT);
4799 if (rc)
4800 goto do_it_again;
edd16368
SC		 4801 /* no unmap needed here because no data xfer. */
4802
4803 if (c->err_info->CommandStatus == CMD_SUCCESS)
4804 break;
4805
4806 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4807 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4808 (c->err_info->SenseInfo[2] == NO_SENSE ||
4809 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4810 break;
25163bd5 4811do_it_again:
edd16368
SC		 4812 dev_warn(&h->pdev->dev, "waiting %d secs "
4813 "for device to become ready.\n", waittime);
4814 rc = 1; /* device not ready. */
4815 }
4816
4817 if (rc)
4818 dev_warn(&h->pdev->dev, "giving up on device.\n");
4819 else
4820 dev_warn(&h->pdev->dev, "device is ready.\n");
4821
45fcb86e 4822 cmd_free(h, c);
edd16368
SC		 4823 return rc;
4824}
4825
4826/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4827 * complaining. Doing a host- or bus-reset can't do anything good here.
4828 */
4829static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4830{
4831 int rc;
4832 struct ctlr_info *h;
4833 struct hpsa_scsi_dev_t *dev;
4834
4835 /* find the controller to which the command to be aborted was sent */
4836 h = sdev_to_hba(scsicmd->device);
4837 if (h == NULL) /* paranoia */
4838 return FAILED;
e345893b
DB		 4839
4840 if (lockup_detected(h))
4841 return FAILED;
4842
edd16368
SC		 4843 dev = scsicmd->device->hostdata;
4844 if (!dev) {
4845 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4846 "device lookup failed.\n");
4847 return FAILED;
4848 }
25163bd5
WS		 4849
4850 /* if controller locked up, we can guarantee command won't complete */
4851 if (lockup_detected(h)) {
4852 dev_warn(&h->pdev->dev,
4853 "scsi %d:%d:%d:%d RESET FAILED, lockup detected\n",
4854 h->scsi_host->host_no, dev->bus, dev->target,
4855 dev->lun);
4856 return FAILED;
4857 }
4858
4859 /* this reset request might be the result of a lockup; check */
4860 if (detect_controller_lockup(h)) {
4861 dev_warn(&h->pdev->dev,
4862 "scsi %d:%d:%d:%d RESET FAILED, new lockup detected\n",
4863 h->scsi_host->host_no, dev->bus, dev->target,
4864 dev->lun);
4865 return FAILED;
4866 }
4867
4868 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
4869
edd16368 4870 /* send a reset to the SCSI LUN which the command was sent to */
25163bd5
WS		 4871 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
4872 DEFAULT_REPLY_QUEUE);
edd16368
SC		 4873 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4874 return SUCCESS;
4875
25163bd5
WS		 4876 dev_warn(&h->pdev->dev,
4877 "scsi %d:%d:%d:%d reset failed\n",
4878 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 4879 return FAILED;
4880}
4881
6cba3f19
SC		 4882static void swizzle_abort_tag(u8 *tag)
4883{
4884 u8 original_tag[8];
4885
4886 memcpy(original_tag, tag, 8);
4887 tag[0] = original_tag[3];
4888 tag[1] = original_tag[2];
4889 tag[2] = original_tag[1];
4890 tag[3] = original_tag[0];
4891 tag[4] = original_tag[7];
4892 tag[5] = original_tag[6];
4893 tag[6] = original_tag[5];
4894 tag[7] = original_tag[4];
4895}
4896
17eb87d2 4897static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4898 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4899{
2b08b3e9 4900 u64 tag;
17eb87d2
ST		 4901 if (c->cmd_type == CMD_IOACCEL1) {
4902 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4903 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4904 tag = le64_to_cpu(cm1->tag);
4905 *tagupper = cpu_to_le32(tag >> 32);
4906 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4907 return;
4908 }
4909 if (c->cmd_type == CMD_IOACCEL2) {
4910 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4911 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4912 /* upper tag not used in ioaccel2 mode */
4913 memset(tagupper, 0, sizeof(*tagupper));
4914 *taglower = cm2->Tag;
54b6e9e9 4915 return;
17eb87d2 4916 }
2b08b3e9
DB		 4917 tag = le64_to_cpu(c->Header.tag);
4918 *tagupper = cpu_to_le32(tag >> 32);
4919 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4920}
4921
75167d2c 4922static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 4923 struct CommandList *abort, int reply_queue)
75167d2c
SC		 4924{
4925 int rc = IO_OK;
4926 struct CommandList *c;
4927 struct ErrorInfo *ei;
2b08b3e9 4928 __le32 tagupper, taglower;
75167d2c 4929
45fcb86e 4930 c = cmd_alloc(h);
75167d2c 4931 if (c == NULL) { /* trouble... */
45fcb86e 4932 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4933 return -ENOMEM;
4934 }
4935
a2dac136 4936 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 4937 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 4938 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 4939 if (h->needs_abort_tags_swizzled)
6cba3f19 4940 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 4941 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 4942 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4943 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 4944 __func__, tagupper, taglower);
75167d2c
SC		 4945 /* no unmap needed here because no data xfer. */
4946
4947 ei = c->err_info;
4948 switch (ei->CommandStatus) {
4949 case CMD_SUCCESS:
4950 break;
9437ac43
SC		 4951 case CMD_TMF_STATUS:
4952 rc = hpsa_evaluate_tmf_status(h, c);
4953 break;
75167d2c
SC		 4954 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4955 rc = -1;
4956 break;
4957 default:
4958 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4959 __func__, tagupper, taglower);
d1e8beac 4960 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4961 rc = -1;
4962 break;
4963 }
45fcb86e 4964 cmd_free(h, c);
dd0e19f3
ST		 4965 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4966 __func__, tagupper, taglower);
75167d2c
SC		 4967 return rc;
4968}
4969
54b6e9e9
ST		 4970/* ioaccel2 path firmware cannot handle abort task requests.
4971 * Change abort requests to physical target reset, and send to the
4972 * address of the physical disk used for the ioaccel 2 command.
4973 * Return 0 on success (IO_OK)
4974 * -1 on failure
4975 */
4976
4977static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 4978 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 4979{
4980 int rc = IO_OK;
4981 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4982 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4983 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4984 unsigned char *psa = &phys_scsi3addr[0];
4985
4986 /* Get a pointer to the hpsa logical device. */
7fa3030c 4987 scmd = abort->scsi_cmd;
54b6e9e9
ST		 4988 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4989 if (dev == NULL) {
4990 dev_warn(&h->pdev->dev,
4991 "Cannot abort: no device pointer for command.\n");
4992 return -1; /* not abortable */
4993 }
4994
2ba8bfc8
SC		 4995 if (h->raid_offload_debug > 0)
4996 dev_info(&h->pdev->dev,
0d96ef5f 4997 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 4998 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 4999 "Reset as abort",
2ba8bfc8
SC		 5000 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5001 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5002
54b6e9e9
ST		 5003 if (!dev->offload_enabled) {
5004 dev_warn(&h->pdev->dev,
5005 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5006 return -1; /* not abortable */
5007 }
5008
5009 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5010 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5011 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5012 return -1; /* not abortable */
5013 }
5014
5015 /* send the reset */
2ba8bfc8
SC		 5016 if (h->raid_offload_debug > 0)
5017 dev_info(&h->pdev->dev,
5018 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5019 psa[0], psa[1], psa[2], psa[3],
5020 psa[4], psa[5], psa[6], psa[7]);
25163bd5 5021 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5022 if (rc != 0) {
5023 dev_warn(&h->pdev->dev,
5024 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5025 psa[0], psa[1], psa[2], psa[3],
5026 psa[4], psa[5], psa[6], psa[7]);
5027 return rc; /* failed to reset */
5028 }
5029
5030 /* wait for device to recover */
5031 if (wait_for_device_to_become_ready(h, psa) != 0) {
5032 dev_warn(&h->pdev->dev,
5033 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5034 psa[0], psa[1], psa[2], psa[3],
5035 psa[4], psa[5], psa[6], psa[7]);
5036 return -1; /* failed to recover */
5037 }
5038
5039 /* device recovered */
5040 dev_info(&h->pdev->dev,
5041 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5042 psa[0], psa[1], psa[2], psa[3],
5043 psa[4], psa[5], psa[6], psa[7]);
5044
5045 return rc; /* success */
5046}
5047
6cba3f19 5048static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5049 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5050{
54b6e9e9
ST		 5051 /* ioccelerator mode 2 commands should be aborted via the
5052 * accelerated path, since RAID path is unaware of these commands,
5053 * but underlying firmware can't handle abort TMF.
5054 * Change abort to physical device reset.
5055 */
5056 if (abort->cmd_type == CMD_IOACCEL2)
25163bd5
WS		 5057 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
5058 abort, reply_queue);
9b5c48c2 5059 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5060}
54b6e9e9 5061
25163bd5
WS		 5062/* Find out which reply queue a command was meant to return on */
5063static int hpsa_extract_reply_queue(struct ctlr_info *h,
5064 struct CommandList *c)
5065{
5066 if (c->cmd_type == CMD_IOACCEL2)
5067 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5068 return c->Header.ReplyQueue;
6cba3f19
SC		 5069}
5070
9b5c48c2
SC		 5071/*
5072 * Limit concurrency of abort commands to prevent
5073 * over-subscription of commands
5074 */
5075static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5076{
5077#define ABORT_CMD_WAIT_MSECS 5000
5078 return !wait_event_timeout(h->abort_cmd_wait_queue,
5079 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5080 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5081}
5082
75167d2c
SC		 5083/* Send an abort for the specified command.
5084 * If the device and controller support it,
5085 * send a task abort request.
5086 */
5087static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5088{
5089
5090 int i, rc;
5091 struct ctlr_info *h;
5092 struct hpsa_scsi_dev_t *dev;
5093 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5094 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5095 char msg[256]; /* For debug messaging. */
5096 int ml = 0;
2b08b3e9 5097 __le32 tagupper, taglower;
25163bd5
WS		 5098 int refcount, reply_queue;
5099
5100 if (sc == NULL)
5101 return FAILED;
75167d2c 5102
9b5c48c2
SC		 5103 if (sc->device == NULL)
5104 return FAILED;
5105
75167d2c
SC		 5106 /* Find the controller of the command to be aborted */
5107 h = sdev_to_hba(sc->device);
9b5c48c2 5108 if (h == NULL)
75167d2c
SC		 5109 return FAILED;
5110
25163bd5
WS		 5111 /* Find the device of the command to be aborted */
5112 dev = sc->device->hostdata;
5113 if (!dev) {
5114 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5115 msg);
e345893b 5116 return FAILED;
25163bd5
WS		 5117 }
5118
5119 /* If controller locked up, we can guarantee command won't complete */
5120 if (lockup_detected(h)) {
5121 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5122 "ABORT FAILED, lockup detected");
5123 return FAILED;
5124 }
5125
5126 /* This is a good time to check if controller lockup has occurred */
5127 if (detect_controller_lockup(h)) {
5128 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5129 "ABORT FAILED, new lockup detected");
5130 return FAILED;
5131 }
e345893b 5132
75167d2c
SC		 5133 /* Check that controller supports some kind of task abort */
5134 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5135 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5136 return FAILED;
5137
5138 memset(msg, 0, sizeof(msg));
0d96ef5f 5139 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s",
75167d2c 5140 h->scsi_host->host_no, sc->device->channel,
0d96ef5f
WS		 5141 sc->device->id, sc->device->lun,
5142 "Aborting command");
75167d2c 5143
75167d2c
SC		 5144 /* Get SCSI command to be aborted */
5145 abort = (struct CommandList *) sc->host_scribble;
5146 if (abort == NULL) {
281a7fd0
WS		 5147 /* This can happen if the command already completed. */
5148 return SUCCESS;
5149 }
5150 refcount = atomic_inc_return(&abort->refcount);
5151 if (refcount == 1) { /* Command is done already. */
5152 cmd_free(h, abort);
5153 return SUCCESS;
75167d2c 5154 }
9b5c48c2
SC		 5155
5156 /* Don't bother trying the abort if we know it won't work. */
5157 if (abort->cmd_type != CMD_IOACCEL2 &&
5158 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5159 cmd_free(h, abort);
5160 return FAILED;
5161 }
5162
17eb87d2 5163 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5164 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5165 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5166 as = abort->scsi_cmd;
75167d2c
SC		 5167 if (as != NULL)
5168 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
5169 as->cmnd[0], as->serial_number);
5170 dev_dbg(&h->pdev->dev, "%s\n", msg);
0d96ef5f 5171 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
75167d2c
SC		 5172 /*
5173 * Command is in flight, or possibly already completed
5174 * by the firmware (but not to the scsi mid layer) but we can't
5175 * distinguish which. Send the abort down.
5176 */
9b5c48c2
SC		 5177 if (wait_for_available_abort_cmd(h)) {
5178 dev_warn(&h->pdev->dev,
5179 "Timed out waiting for an abort command to become available.\n");
5180 cmd_free(h, abort);
5181 return FAILED;
5182 }
25163bd5 5183 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5184 atomic_inc(&h->abort_cmds_available);
5185 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5186 if (rc != 0) {
0d96ef5f
WS		 5187 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5188 "FAILED to abort command");
281a7fd0 5189 cmd_free(h, abort);
75167d2c
SC		 5190 return FAILED;
5191 }
5192 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
5193
5194 /* If the abort(s) above completed and actually aborted the
5195 * command, then the command to be aborted should already be
5196 * completed. If not, wait around a bit more to see if they
5197 * manage to complete normally.
5198 */
5199#define ABORT_COMPLETE_WAIT_SECS 30
5200 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 5201 refcount = atomic_read(&abort->refcount);
5202 if (refcount < 2) {
5203 cmd_free(h, abort);
75167d2c 5204 return SUCCESS;
281a7fd0
WS		 5205 } else {
5206 msleep(100);
5207 }
75167d2c
SC		 5208 }
5209 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
5210 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 5211 cmd_free(h, abort);
75167d2c
SC		 5212 return FAILED;
5213}
5214
edd16368
SC		 5215/*
5216 * For operations that cannot sleep, a command block is allocated at init,
5217 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5218 * which ones are free or in use. Lock must be held when calling this.
5219 * cmd_free() is the complement.
5220 */
281a7fd0 5221
edd16368
SC		 5222static struct CommandList *cmd_alloc(struct ctlr_info *h)
5223{
5224 struct CommandList *c;
360c73bd 5225 int refcount, i;
33811026 5226 unsigned long offset;
4c413128 5227
33811026
RE		 5228 /*
5229 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5230 * multiple threads could get in here, and one thread could
5231 * be scanning through the list of bits looking for a free
5232 * one, but the free ones are always behind him, and other
5233 * threads sneak in behind him and eat them before he can
5234 * get to them, so that while there is always a free one, a
5235 * very unlucky thread might be starved anyway, never able to
5236 * beat the other threads. In reality, this happens so
5237 * infrequently as to be indistinguishable from never.
5238 */
edd16368 5239
33811026 5240 offset = h->last_allocation; /* benignly racy */
281a7fd0
WS		 5241 for (;;) {
5242 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
5243 if (unlikely(i == h->nr_cmds)) {
5244 offset = 0;
5245 continue;
5246 }
5247 c = h->cmd_pool + i;
5248 refcount = atomic_inc_return(&c->refcount);
5249 if (unlikely(refcount > 1)) {
5250 cmd_free(h, c); /* already in use */
5251 offset = (i + 1) % h->nr_cmds;
5252 continue;
5253 }
5254 set_bit(i & (BITS_PER_LONG - 1),
5255 h->cmd_pool_bits + (i / BITS_PER_LONG));
5256 break; /* it's ours now. */
5257 }
33811026 5258 h->last_allocation = i; /* benignly racy */
360c73bd 5259 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5260 return c;
5261}
5262
edd16368
SC		 5263static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5264{
281a7fd0
WS		 5265 if (atomic_dec_and_test(&c->refcount)) {
5266 int i;
edd16368 5267
281a7fd0
WS		 5268 i = c - h->cmd_pool;
5269 clear_bit(i & (BITS_PER_LONG - 1),
5270 h->cmd_pool_bits + (i / BITS_PER_LONG));
5271 }
edd16368
SC		 5272}
5273
edd16368
SC		 5274#ifdef CONFIG_COMPAT
5275
42a91641
DB		 5276static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5277 void __user *arg)
edd16368
SC		 5278{
5279 IOCTL32_Command_struct __user *arg32 =
5280 (IOCTL32_Command_struct __user *) arg;
5281 IOCTL_Command_struct arg64;
5282 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5283 int err;
5284 u32 cp;
5285
938abd84 5286 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5287 err = 0;
5288 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5289 sizeof(arg64.LUN_info));
5290 err |= copy_from_user(&arg64.Request, &arg32->Request,
5291 sizeof(arg64.Request));
5292 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5293 sizeof(arg64.error_info));
5294 err |= get_user(arg64.buf_size, &arg32->buf_size);
5295 err |= get_user(cp, &arg32->buf);
5296 arg64.buf = compat_ptr(cp);
5297 err |= copy_to_user(p, &arg64, sizeof(arg64));
5298
5299 if (err)
5300 return -EFAULT;
5301
42a91641 5302 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5303 if (err)
5304 return err;
5305 err |= copy_in_user(&arg32->error_info, &p->error_info,
5306 sizeof(arg32->error_info));
5307 if (err)
5308 return -EFAULT;
5309 return err;
5310}
5311
5312static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5313 int cmd, void __user *arg)
edd16368
SC		 5314{
5315 BIG_IOCTL32_Command_struct __user *arg32 =
5316 (BIG_IOCTL32_Command_struct __user *) arg;
5317 BIG_IOCTL_Command_struct arg64;
5318 BIG_IOCTL_Command_struct __user *p =
5319 compat_alloc_user_space(sizeof(arg64));
5320 int err;
5321 u32 cp;
5322
938abd84 5323 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5324 err = 0;
5325 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5326 sizeof(arg64.LUN_info));
5327 err |= copy_from_user(&arg64.Request, &arg32->Request,
5328 sizeof(arg64.Request));
5329 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5330 sizeof(arg64.error_info));
5331 err |= get_user(arg64.buf_size, &arg32->buf_size);
5332 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5333 err |= get_user(cp, &arg32->buf);
5334 arg64.buf = compat_ptr(cp);
5335 err |= copy_to_user(p, &arg64, sizeof(arg64));
5336
5337 if (err)
5338 return -EFAULT;
5339
42a91641 5340 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5341 if (err)
5342 return err;
5343 err |= copy_in_user(&arg32->error_info, &p->error_info,
5344 sizeof(arg32->error_info));
5345 if (err)
5346 return -EFAULT;
5347 return err;
5348}
71fe75a7 5349
42a91641 5350static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5351{
5352 switch (cmd) {
5353 case CCISS_GETPCIINFO:
5354 case CCISS_GETINTINFO:
5355 case CCISS_SETINTINFO:
5356 case CCISS_GETNODENAME:
5357 case CCISS_SETNODENAME:
5358 case CCISS_GETHEARTBEAT:
5359 case CCISS_GETBUSTYPES:
5360 case CCISS_GETFIRMVER:
5361 case CCISS_GETDRIVVER:
5362 case CCISS_REVALIDVOLS:
5363 case CCISS_DEREGDISK:
5364 case CCISS_REGNEWDISK:
5365 case CCISS_REGNEWD:
5366 case CCISS_RESCANDISK:
5367 case CCISS_GETLUNINFO:
5368 return hpsa_ioctl(dev, cmd, arg);
5369
5370 case CCISS_PASSTHRU32:
5371 return hpsa_ioctl32_passthru(dev, cmd, arg);
5372 case CCISS_BIG_PASSTHRU32:
5373 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5374
5375 default:
5376 return -ENOIOCTLCMD;
5377 }
5378}
edd16368
SC		 5379#endif
5380
5381static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5382{
5383 struct hpsa_pci_info pciinfo;
5384
5385 if (!argp)
5386 return -EINVAL;
5387 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5388 pciinfo.bus = h->pdev->bus->number;
5389 pciinfo.dev_fn = h->pdev->devfn;
5390 pciinfo.board_id = h->board_id;
5391 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5392 return -EFAULT;
5393 return 0;
5394}
5395
5396static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5397{
5398 DriverVer_type DriverVer;
5399 unsigned char vmaj, vmin, vsubmin;
5400 int rc;
5401
5402 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5403 &vmaj, &vmin, &vsubmin);
5404 if (rc != 3) {
5405 dev_info(&h->pdev->dev, "driver version string '%s' "
5406 "unrecognized.", HPSA_DRIVER_VERSION);
5407 vmaj = 0;
5408 vmin = 0;
5409 vsubmin = 0;
5410 }
5411 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5412 if (!argp)
5413 return -EINVAL;
5414 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5415 return -EFAULT;
5416 return 0;
5417}
5418
5419static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5420{
5421 IOCTL_Command_struct iocommand;
5422 struct CommandList *c;
5423 char *buff = NULL;
50a0decf 5424 u64 temp64;
c1f63c8f 5425 int rc = 0;
edd16368
SC		 5426
5427 if (!argp)
5428 return -EINVAL;
5429 if (!capable(CAP_SYS_RAWIO))
5430 return -EPERM;
5431 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5432 return -EFAULT;
5433 if ((iocommand.buf_size < 1) &&
5434 (iocommand.Request.Type.Direction != XFER_NONE)) {
5435 return -EINVAL;
5436 }
5437 if (iocommand.buf_size > 0) {
5438 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5439 if (buff == NULL)
5440 return -EFAULT;
9233fb10 5441 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5442 /* Copy the data into the buffer we created */
5443 if (copy_from_user(buff, iocommand.buf,
5444 iocommand.buf_size)) {
c1f63c8f
SC		 5445 rc = -EFAULT;
5446 goto out_kfree;
b03a7771
SC		 5447 }
5448 } else {
5449 memset(buff, 0, iocommand.buf_size);
edd16368 5450 }
b03a7771 5451 }
45fcb86e 5452 c = cmd_alloc(h);
edd16368 5453 if (c == NULL) {
c1f63c8f
SC		 5454 rc = -ENOMEM;
5455 goto out_kfree;
edd16368
SC		 5456 }
5457 /* Fill in the command type */
5458 c->cmd_type = CMD_IOCTL_PEND;
5459 /* Fill in Command Header */
5460 c->Header.ReplyQueue = 0; /* unused in simple mode */
5461 if (iocommand.buf_size > 0) { /* buffer to fill */
5462 c->Header.SGList = 1;
50a0decf 5463 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5464 } else { /* no buffers to fill */
5465 c->Header.SGList = 0;
50a0decf 5466 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5467 }
5468 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5469
5470 /* Fill in Request block */
5471 memcpy(&c->Request, &iocommand.Request,
5472 sizeof(c->Request));
5473
5474 /* Fill in the scatter gather information */
5475 if (iocommand.buf_size > 0) {
50a0decf 5476 temp64 = pci_map_single(h->pdev, buff,
edd16368 5477 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5478 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5479 c->SG[0].Addr = cpu_to_le64(0);
5480 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5481 rc = -ENOMEM;
5482 goto out;
5483 }
50a0decf
SC		 5484 c->SG[0].Addr = cpu_to_le64(temp64);
5485 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5486 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5487 }
25163bd5 5488 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5489 if (iocommand.buf_size > 0)
5490 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5491 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5492 if (rc) {
5493 rc = -EIO;
5494 goto out;
5495 }
edd16368
SC		 5496
5497 /* Copy the error information out */
5498 memcpy(&iocommand.error_info, c->err_info,
5499 sizeof(iocommand.error_info));
5500 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5501 rc = -EFAULT;
5502 goto out;
edd16368 5503 }
9233fb10 5504 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5505 iocommand.buf_size > 0) {
edd16368
SC		 5506 /* Copy the data out of the buffer we created */
5507 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5508 rc = -EFAULT;
5509 goto out;
edd16368
SC		 5510 }
5511 }
c1f63c8f 5512out:
45fcb86e 5513 cmd_free(h, c);
c1f63c8f
SC		 5514out_kfree:
5515 kfree(buff);
5516 return rc;
edd16368
SC		 5517}
5518
5519static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5520{
5521 BIG_IOCTL_Command_struct *ioc;
5522 struct CommandList *c;
5523 unsigned char **buff = NULL;
5524 int *buff_size = NULL;
50a0decf 5525 u64 temp64;
edd16368
SC		 5526 BYTE sg_used = 0;
5527 int status = 0;
01a02ffc
SC		 5528 u32 left;
5529 u32 sz;
edd16368
SC		 5530 BYTE __user *data_ptr;
5531
5532 if (!argp)
5533 return -EINVAL;
5534 if (!capable(CAP_SYS_RAWIO))
5535 return -EPERM;
5536 ioc = (BIG_IOCTL_Command_struct *)
5537 kmalloc(sizeof(*ioc), GFP_KERNEL);
5538 if (!ioc) {
5539 status = -ENOMEM;
5540 goto cleanup1;
5541 }
5542 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5543 status = -EFAULT;
5544 goto cleanup1;
5545 }
5546 if ((ioc->buf_size < 1) &&
5547 (ioc->Request.Type.Direction != XFER_NONE)) {
5548 status = -EINVAL;
5549 goto cleanup1;
5550 }
5551 /* Check kmalloc limits using all SGs */
5552 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5553 status = -EINVAL;
5554 goto cleanup1;
5555 }
d66ae08b 5556 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5557 status = -EINVAL;
5558 goto cleanup1;
5559 }
d66ae08b 5560 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5561 if (!buff) {
5562 status = -ENOMEM;
5563 goto cleanup1;
5564 }
d66ae08b 5565 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5566 if (!buff_size) {
5567 status = -ENOMEM;
5568 goto cleanup1;
5569 }
5570 left = ioc->buf_size;
5571 data_ptr = ioc->buf;
5572 while (left) {
5573 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5574 buff_size[sg_used] = sz;
5575 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5576 if (buff[sg_used] == NULL) {
5577 status = -ENOMEM;
5578 goto cleanup1;
5579 }
9233fb10 5580 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5581 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5582 status = -EFAULT;
edd16368
SC		 5583 goto cleanup1;
5584 }
5585 } else
5586 memset(buff[sg_used], 0, sz);
5587 left -= sz;
5588 data_ptr += sz;
5589 sg_used++;
5590 }
45fcb86e 5591 c = cmd_alloc(h);
edd16368
SC		 5592 if (c == NULL) {
5593 status = -ENOMEM;
5594 goto cleanup1;
5595 }
5596 c->cmd_type = CMD_IOCTL_PEND;
5597 c->Header.ReplyQueue = 0;
50a0decf
SC		 5598 c->Header.SGList = (u8) sg_used;
5599 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5600 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5601 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5602 if (ioc->buf_size > 0) {
5603 int i;
5604 for (i = 0; i < sg_used; i++) {
50a0decf 5605 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5606 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5607 if (dma_mapping_error(&h->pdev->dev,
5608 (dma_addr_t) temp64)) {
5609 c->SG[i].Addr = cpu_to_le64(0);
5610 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5611 hpsa_pci_unmap(h->pdev, c, i,
5612 PCI_DMA_BIDIRECTIONAL);
5613 status = -ENOMEM;
e2d4a1f6 5614 goto cleanup0;
bcc48ffa 5615 }
50a0decf
SC		 5616 c->SG[i].Addr = cpu_to_le64(temp64);
5617 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5618 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5619 }
50a0decf 5620 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5621 }
25163bd5 5622 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 5623 if (sg_used)
5624 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 5625 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5626 if (status) {
5627 status = -EIO;
5628 goto cleanup0;
5629 }
5630
edd16368
SC		 5631 /* Copy the error information out */
5632 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5633 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5634 status = -EFAULT;
e2d4a1f6 5635 goto cleanup0;
edd16368 5636 }
9233fb10 5637 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5638 int i;
5639
edd16368
SC		 5640 /* Copy the data out of the buffer we created */
5641 BYTE __user *ptr = ioc->buf;
5642 for (i = 0; i < sg_used; i++) {
5643 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5644 status = -EFAULT;
e2d4a1f6 5645 goto cleanup0;
edd16368
SC		 5646 }
5647 ptr += buff_size[i];
5648 }
5649 }
edd16368 5650 status = 0;
e2d4a1f6 5651cleanup0:
45fcb86e 5652 cmd_free(h, c);
edd16368
SC		 5653cleanup1:
5654 if (buff) {
2b08b3e9
DB		 5655 int i;
5656
edd16368
SC		 5657 for (i = 0; i < sg_used; i++)
5658 kfree(buff[i]);
5659 kfree(buff);
5660 }
5661 kfree(buff_size);
5662 kfree(ioc);
5663 return status;
5664}
5665
5666static void check_ioctl_unit_attention(struct ctlr_info *h,
5667 struct CommandList *c)
5668{
5669 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5670 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5671 (void) check_for_unit_attention(h, c);
5672}
0390f0c0 5673
edd16368
SC		 5674/*
5675 * ioctl
5676 */
42a91641 5677static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5678{
5679 struct ctlr_info *h;
5680 void __user *argp = (void __user *)arg;
0390f0c0 5681 int rc;
edd16368
SC		 5682
5683 h = sdev_to_hba(dev);
5684
5685 switch (cmd) {
5686 case CCISS_DEREGDISK:
5687 case CCISS_REGNEWDISK:
5688 case CCISS_REGNEWD:
a08a8471 5689 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5690 return 0;
5691 case CCISS_GETPCIINFO:
5692 return hpsa_getpciinfo_ioctl(h, argp);
5693 case CCISS_GETDRIVVER:
5694 return hpsa_getdrivver_ioctl(h, argp);
5695 case CCISS_PASSTHRU:
34f0c627 5696 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5697 return -EAGAIN;
5698 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 5699 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5700 return rc;
edd16368 5701 case CCISS_BIG_PASSTHRU:
34f0c627 5702 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5703 return -EAGAIN;
5704 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 5705 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5706 return rc;
edd16368
SC		 5707 default:
5708 return -ENOTTY;
5709 }
5710}
5711
6f039790
GKH		 5712static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5713 u8 reset_type)
64670ac8
SC		 5714{
5715 struct CommandList *c;
5716
5717 c = cmd_alloc(h);
5718 if (!c)
5719 return -ENOMEM;
a2dac136
SC		 5720 /* fill_cmd can't fail here, no data buffer to map */
5721 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5722 RAID_CTLR_LUNID, TYPE_MSG);
5723 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5724 c->waiting = NULL;
5725 enqueue_cmd_and_start_io(h, c);
5726 /* Don't wait for completion, the reset won't complete. Don't free
5727 * the command either. This is the last command we will send before
5728 * re-initializing everything, so it doesn't matter and won't leak.
5729 */
5730 return 0;
5731}
5732
a2dac136 5733static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5734 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5735 int cmd_type)
5736{
5737 int pci_dir = XFER_NONE;
9b5c48c2 5738 u64 tag; /* for commands to be aborted */
edd16368
SC		 5739
5740 c->cmd_type = CMD_IOCTL_PEND;
5741 c->Header.ReplyQueue = 0;
5742 if (buff != NULL && size > 0) {
5743 c->Header.SGList = 1;
50a0decf 5744 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5745 } else {
5746 c->Header.SGList = 0;
50a0decf 5747 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5748 }
edd16368
SC		 5749 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5750
edd16368
SC		 5751 if (cmd_type == TYPE_CMD) {
5752 switch (cmd) {
5753 case HPSA_INQUIRY:
5754 /* are we trying to read a vital product page */
b7bb24eb 5755 if (page_code & VPD_PAGE) {
edd16368 5756 c->Request.CDB[1] = 0x01;
b7bb24eb 5757 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5758 }
5759 c->Request.CDBLen = 6;
a505b86f
SC		 5760 c->Request.type_attr_dir =
5761 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5762 c->Request.Timeout = 0;
5763 c->Request.CDB[0] = HPSA_INQUIRY;
5764 c->Request.CDB[4] = size & 0xFF;
5765 break;
5766 case HPSA_REPORT_LOG:
5767 case HPSA_REPORT_PHYS:
5768 /* Talking to controller so It's a physical command
5769 mode = 00 target = 0. Nothing to write.
5770 */
5771 c->Request.CDBLen = 12;
a505b86f
SC		 5772 c->Request.type_attr_dir =
5773 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5774 c->Request.Timeout = 0;
5775 c->Request.CDB[0] = cmd;
5776 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5777 c->Request.CDB[7] = (size >> 16) & 0xFF;
5778 c->Request.CDB[8] = (size >> 8) & 0xFF;
5779 c->Request.CDB[9] = size & 0xFF;
5780 break;
edd16368
SC		 5781 case HPSA_CACHE_FLUSH:
5782 c->Request.CDBLen = 12;
a505b86f
SC		 5783 c->Request.type_attr_dir =
5784 TYPE_ATTR_DIR(cmd_type,
5785 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5786 c->Request.Timeout = 0;
5787 c->Request.CDB[0] = BMIC_WRITE;
5788 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5789 c->Request.CDB[7] = (size >> 8) & 0xFF;
5790 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5791 break;
5792 case TEST_UNIT_READY:
5793 c->Request.CDBLen = 6;
a505b86f
SC		 5794 c->Request.type_attr_dir =
5795 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5796 c->Request.Timeout = 0;
5797 break;
283b4a9b
SC		 5798 case HPSA_GET_RAID_MAP:
5799 c->Request.CDBLen = 12;
a505b86f
SC		 5800 c->Request.type_attr_dir =
5801 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5802 c->Request.Timeout = 0;
5803 c->Request.CDB[0] = HPSA_CISS_READ;
5804 c->Request.CDB[1] = cmd;
5805 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5806 c->Request.CDB[7] = (size >> 16) & 0xFF;
5807 c->Request.CDB[8] = (size >> 8) & 0xFF;
5808 c->Request.CDB[9] = size & 0xFF;
5809 break;
316b221a
SC		 5810 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5811 c->Request.CDBLen = 10;
a505b86f
SC		 5812 c->Request.type_attr_dir =
5813 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5814 c->Request.Timeout = 0;
5815 c->Request.CDB[0] = BMIC_READ;
5816 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5817 c->Request.CDB[7] = (size >> 16) & 0xFF;
5818 c->Request.CDB[8] = (size >> 8) & 0xFF;
5819 break;
03383736
DB		 5820 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5821 c->Request.CDBLen = 10;
5822 c->Request.type_attr_dir =
5823 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5824 c->Request.Timeout = 0;
5825 c->Request.CDB[0] = BMIC_READ;
5826 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5827 c->Request.CDB[7] = (size >> 16) & 0xFF;
5828 c->Request.CDB[8] = (size >> 8) & 0XFF;
5829 break;
edd16368
SC		 5830 default:
5831 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5832 BUG();
a2dac136 5833 return -1;
edd16368
SC		 5834 }
5835 } else if (cmd_type == TYPE_MSG) {
5836 switch (cmd) {
5837
5838 case HPSA_DEVICE_RESET_MSG:
5839 c->Request.CDBLen = 16;
a505b86f
SC		 5840 c->Request.type_attr_dir =
5841 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5842 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5843 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5844 c->Request.CDB[0] = cmd;
21e89afd 5845 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5846 /* If bytes 4-7 are zero, it means reset the */
5847 /* LunID device */
5848 c->Request.CDB[4] = 0x00;
5849 c->Request.CDB[5] = 0x00;
5850 c->Request.CDB[6] = 0x00;
5851 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5852 break;
5853 case HPSA_ABORT_MSG:
9b5c48c2 5854 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 5855 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 5856 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
5857 tag, c->Header.tag);
75167d2c 5858 c->Request.CDBLen = 16;
a505b86f
SC		 5859 c->Request.type_attr_dir =
5860 TYPE_ATTR_DIR(cmd_type,
5861 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5862 c->Request.Timeout = 0; /* Don't time out */
5863 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5864 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5865 c->Request.CDB[2] = 0x00; /* reserved */
5866 c->Request.CDB[3] = 0x00; /* reserved */
5867 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 5868 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 5869 c->Request.CDB[12] = 0x00; /* reserved */
5870 c->Request.CDB[13] = 0x00; /* reserved */
5871 c->Request.CDB[14] = 0x00; /* reserved */
5872 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5873 break;
edd16368
SC		 5874 default:
5875 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5876 cmd);
5877 BUG();
5878 }
5879 } else {
5880 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5881 BUG();
5882 }
5883
a505b86f 5884 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5885 case XFER_READ:
5886 pci_dir = PCI_DMA_FROMDEVICE;
5887 break;
5888 case XFER_WRITE:
5889 pci_dir = PCI_DMA_TODEVICE;
5890 break;
5891 case XFER_NONE:
5892 pci_dir = PCI_DMA_NONE;
5893 break;
5894 default:
5895 pci_dir = PCI_DMA_BIDIRECTIONAL;
5896 }
a2dac136
SC		 5897 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5898 return -1;
5899 return 0;
edd16368
SC		 5900}
5901
5902/*
5903 * Map (physical) PCI mem into (virtual) kernel space
5904 */
5905static void __iomem *remap_pci_mem(ulong base, ulong size)
5906{
5907 ulong page_base = ((ulong) base) & PAGE_MASK;
5908 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5909 void __iomem *page_remapped = ioremap_nocache(page_base,
5910 page_offs + size);
edd16368
SC		 5911
5912 return page_remapped ? (page_remapped + page_offs) : NULL;
5913}
5914
254f796b 5915static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5916{
254f796b 5917 return h->access.command_completed(h, q);
edd16368
SC		 5918}
5919
900c5440 5920static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5921{
5922 return h->access.intr_pending(h);
5923}
5924
5925static inline long interrupt_not_for_us(struct ctlr_info *h)
5926{
10f66018
SC		 5927 return (h->access.intr_pending(h) == 0) ||
5928 (h->interrupts_enabled == 0);
edd16368
SC		 5929}
5930
01a02ffc
SC		 5931static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5932 u32 raw_tag)
edd16368
SC		 5933{
5934 if (unlikely(tag_index >= h->nr_cmds)) {
5935 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5936 return 1;
5937 }
5938 return 0;
5939}
5940
5a3d16f5 5941static inline void finish_cmd(struct CommandList *c)
edd16368 5942{
e85c5974 5943 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5944 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5945 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5946 complete_scsi_command(c);
edd16368
SC		 5947 else if (c->cmd_type == CMD_IOCTL_PEND)
5948 complete(c->waiting);
a104c99f
SC		 5949}
5950
a9a3a273
SC		 5951
5952static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5953{
a9a3a273
SC		 5954#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5955#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5956 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5957 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5958 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5959}
5960
303932fd 5961/* process completion of an indexed ("direct lookup") command */
1d94f94d 5962static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5963 u32 raw_tag)
5964{
5965 u32 tag_index;
5966 struct CommandList *c;
5967
f2405db8 5968 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5969 if (!bad_tag(h, tag_index, raw_tag)) {
5970 c = h->cmd_pool + tag_index;
5971 finish_cmd(c);
5972 }
303932fd
DB		 5973}
5974
64670ac8
SC		 5975/* Some controllers, like p400, will give us one interrupt
5976 * after a soft reset, even if we turned interrupts off.
5977 * Only need to check for this in the hpsa_xxx_discard_completions
5978 * functions.
5979 */
5980static int ignore_bogus_interrupt(struct ctlr_info *h)
5981{
5982 if (likely(!reset_devices))
5983 return 0;
5984
5985 if (likely(h->interrupts_enabled))
5986 return 0;
5987
5988 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5989 "(known firmware bug.) Ignoring.\n");
5990
5991 return 1;
5992}
5993
254f796b
MG		 5994/*
5995 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5996 * Relies on (h-q[x] == x) being true for x such that
5997 * 0 <= x < MAX_REPLY_QUEUES.
5998 */
5999static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6000{
254f796b
MG		 6001 return container_of((queue - *queue), struct ctlr_info, q[0]);
6002}
6003
6004static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6005{
6006 struct ctlr_info *h = queue_to_hba(queue);
6007 u8 q = *(u8 *) queue;
64670ac8
SC		 6008 u32 raw_tag;
6009
6010 if (ignore_bogus_interrupt(h))
6011 return IRQ_NONE;
6012
6013 if (interrupt_not_for_us(h))
6014 return IRQ_NONE;
a0c12413 6015 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6016 while (interrupt_pending(h)) {
254f796b 6017 raw_tag = get_next_completion(h, q);
64670ac8 6018 while (raw_tag != FIFO_EMPTY)
254f796b 6019 raw_tag = next_command(h, q);
64670ac8 6020 }
64670ac8
SC		 6021 return IRQ_HANDLED;
6022}
6023
254f796b 6024static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6025{
254f796b 6026 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6027 u32 raw_tag;
254f796b 6028 u8 q = *(u8 *) queue;
64670ac8
SC		 6029
6030 if (ignore_bogus_interrupt(h))
6031 return IRQ_NONE;
6032
a0c12413 6033 h->last_intr_timestamp = get_jiffies_64();
254f796b 6034 raw_tag = get_next_completion(h, q);
64670ac8 6035 while (raw_tag != FIFO_EMPTY)
254f796b 6036 raw_tag = next_command(h, q);
64670ac8
SC		 6037 return IRQ_HANDLED;
6038}
6039
254f796b 6040static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6041{
254f796b 6042 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6043 u32 raw_tag;
254f796b 6044 u8 q = *(u8 *) queue;
edd16368
SC		 6045
6046 if (interrupt_not_for_us(h))
6047 return IRQ_NONE;
a0c12413 6048 h->last_intr_timestamp = get_jiffies_64();
10f66018 6049 while (interrupt_pending(h)) {
254f796b 6050 raw_tag = get_next_completion(h, q);
10f66018 6051 while (raw_tag != FIFO_EMPTY) {
f2405db8 6052 process_indexed_cmd(h, raw_tag);
254f796b 6053 raw_tag = next_command(h, q);
10f66018
SC		 6054 }
6055 }
10f66018
SC		 6056 return IRQ_HANDLED;
6057}
6058
254f796b 6059static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6060{
254f796b 6061 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6062 u32 raw_tag;
254f796b 6063 u8 q = *(u8 *) queue;
10f66018 6064
a0c12413 6065 h->last_intr_timestamp = get_jiffies_64();
254f796b 6066 raw_tag = get_next_completion(h, q);
303932fd 6067 while (raw_tag != FIFO_EMPTY) {
f2405db8 6068 process_indexed_cmd(h, raw_tag);
254f796b 6069 raw_tag = next_command(h, q);
edd16368 6070 }
edd16368
SC		 6071 return IRQ_HANDLED;
6072}
6073
a9a3a273
SC		 6074/* Send a message CDB to the firmware. Careful, this only works
6075 * in simple mode, not performant mode due to the tag lookup.
6076 * We only ever use this immediately after a controller reset.
6077 */
6f039790
GKH		 6078static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6079 unsigned char type)
edd16368
SC		 6080{
6081 struct Command {
6082 struct CommandListHeader CommandHeader;
6083 struct RequestBlock Request;
6084 struct ErrDescriptor ErrorDescriptor;
6085 };
6086 struct Command *cmd;
6087 static const size_t cmd_sz = sizeof(*cmd) +
6088 sizeof(cmd->ErrorDescriptor);
6089 dma_addr_t paddr64;
2b08b3e9
DB		 6090 __le32 paddr32;
6091 u32 tag;
edd16368
SC		 6092 void __iomem *vaddr;
6093 int i, err;
6094
6095 vaddr = pci_ioremap_bar(pdev, 0);
6096 if (vaddr == NULL)
6097 return -ENOMEM;
6098
6099 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6100 * CCISS commands, so they must be allocated from the lower 4GiB of
6101 * memory.
6102 */
6103 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6104 if (err) {
6105 iounmap(vaddr);
1eaec8f3 6106 return err;
edd16368
SC		 6107 }
6108
6109 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6110 if (cmd == NULL) {
6111 iounmap(vaddr);
6112 return -ENOMEM;
6113 }
6114
6115 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6116 * although there's no guarantee, we assume that the address is at
6117 * least 4-byte aligned (most likely, it's page-aligned).
6118 */
2b08b3e9 6119 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6120
6121 cmd->CommandHeader.ReplyQueue = 0;
6122 cmd->CommandHeader.SGList = 0;
50a0decf 6123 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6124 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6125 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6126
6127 cmd->Request.CDBLen = 16;
a505b86f
SC		 6128 cmd->Request.type_attr_dir =
6129 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6130 cmd->Request.Timeout = 0; /* Don't time out */
6131 cmd->Request.CDB[0] = opcode;
6132 cmd->Request.CDB[1] = type;
6133 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6134 cmd->ErrorDescriptor.Addr =
2b08b3e9 6135 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6136 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6137
2b08b3e9 6138 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6139
6140 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6141 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6142 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6143 break;
6144 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6145 }
6146
6147 iounmap(vaddr);
6148
6149 /* we leak the DMA buffer here ... no choice since the controller could
6150 * still complete the command.
6151 */
6152 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6153 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6154 opcode, type);
6155 return -ETIMEDOUT;
6156 }
6157
6158 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6159
6160 if (tag & HPSA_ERROR_BIT) {
6161 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6162 opcode, type);
6163 return -EIO;
6164 }
6165
6166 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6167 opcode, type);
6168 return 0;
6169}
6170
edd16368
SC		 6171#define hpsa_noop(p) hpsa_message(p, 3, 0)
6172
1df8552a 6173static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6174 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6175{
1df8552a
SC		 6176
6177 if (use_doorbell) {
6178 /* For everything after the P600, the PCI power state method
6179 * of resetting the controller doesn't work, so we have this
6180 * other way using the doorbell register.
6181 */
6182 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6183 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6184
00701a96 6185 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6186 * doorbell reset and before any attempt to talk to the board
6187 * at all to ensure that this actually works and doesn't fall
6188 * over in some weird corner cases.
6189 */
00701a96 6190 msleep(10000);
1df8552a
SC		 6191 } else { /* Try to do it the PCI power state way */
6192
6193 /* Quoting from the Open CISS Specification: "The Power
6194 * Management Control/Status Register (CSR) controls the power
6195 * state of the device. The normal operating state is D0,
6196 * CSR=00h. The software off state is D3, CSR=03h. To reset
6197 * the controller, place the interface device in D3 then to D0,
6198 * this causes a secondary PCI reset which will reset the
6199 * controller." */
2662cab8
DB		 6200
6201 int rc = 0;
6202
1df8552a 6203 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6204
1df8552a 6205 /* enter the D3hot power management state */
2662cab8
DB		 6206 rc = pci_set_power_state(pdev, PCI_D3hot);
6207 if (rc)
6208 return rc;
1df8552a
SC		 6209
6210 msleep(500);
6211
6212 /* enter the D0 power management state */
2662cab8
DB		 6213 rc = pci_set_power_state(pdev, PCI_D0);
6214 if (rc)
6215 return rc;
c4853efe
MM		 6216
6217 /*
6218 * The P600 requires a small delay when changing states.
6219 * Otherwise we may think the board did not reset and we bail.
6220 * This for kdump only and is particular to the P600.
6221 */
6222 msleep(500);
1df8552a
SC		 6223 }
6224 return 0;
6225}
6226
6f039790 6227static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6228{
6229 memset(driver_version, 0, len);
f79cfec6 6230 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6231}
6232
6f039790 6233static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6234{
6235 char *driver_version;
6236 int i, size = sizeof(cfgtable->driver_version);
6237
6238 driver_version = kmalloc(size, GFP_KERNEL);
6239 if (!driver_version)
6240 return -ENOMEM;
6241
6242 init_driver_version(driver_version, size);
6243 for (i = 0; i < size; i++)
6244 writeb(driver_version[i], &cfgtable->driver_version[i]);
6245 kfree(driver_version);
6246 return 0;
6247}
6248
6f039790
GKH		 6249static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6250 unsigned char *driver_ver)
580ada3c
SC		 6251{
6252 int i;
6253
6254 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6255 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6256}
6257
6f039790 6258static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6259{
6260
6261 char *driver_ver, *old_driver_ver;
6262 int rc, size = sizeof(cfgtable->driver_version);
6263
6264 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6265 if (!old_driver_ver)
6266 return -ENOMEM;
6267 driver_ver = old_driver_ver + size;
6268
6269 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6270 * should have been changed, otherwise we know the reset failed.
6271 */
6272 init_driver_version(old_driver_ver, size);
6273 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6274 rc = !memcmp(driver_ver, old_driver_ver, size);
6275 kfree(old_driver_ver);
6276 return rc;
6277}
edd16368 6278/* This does a hard reset of the controller using PCI power management
1df8552a 6279 * states or the using the doorbell register.
edd16368 6280 */
6b6c1cd7 6281static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6282{
1df8552a
SC		 6283 u64 cfg_offset;
6284 u32 cfg_base_addr;
6285 u64 cfg_base_addr_index;
6286 void __iomem *vaddr;
6287 unsigned long paddr;
580ada3c 6288 u32 misc_fw_support;
270d05de 6289 int rc;
1df8552a 6290 struct CfgTable __iomem *cfgtable;
cf0b08d0 6291 u32 use_doorbell;
270d05de 6292 u16 command_register;
edd16368 6293
1df8552a
SC		 6294 /* For controllers as old as the P600, this is very nearly
6295 * the same thing as
edd16368
SC		 6296 *
6297 * pci_save_state(pci_dev);
6298 * pci_set_power_state(pci_dev, PCI_D3hot);
6299 * pci_set_power_state(pci_dev, PCI_D0);
6300 * pci_restore_state(pci_dev);
6301 *
1df8552a
SC		 6302 * For controllers newer than the P600, the pci power state
6303 * method of resetting doesn't work so we have another way
6304 * using the doorbell register.
edd16368 6305 */
18867659 6306
60f923b9
RE		 6307 if (!ctlr_is_resettable(board_id)) {
6308 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6309 return -ENODEV;
6310 }
46380786
SC		 6311
6312 /* if controller is soft- but not hard resettable... */
6313 if (!ctlr_is_hard_resettable(board_id))
6314 return -ENOTSUPP; /* try soft reset later. */
18867659 6315
270d05de
SC		 6316 /* Save the PCI command register */
6317 pci_read_config_word(pdev, 4, &command_register);
270d05de 6318 pci_save_state(pdev);
edd16368 6319
1df8552a
SC		 6320 /* find the first memory BAR, so we can find the cfg table */
6321 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6322 if (rc)
6323 return rc;
6324 vaddr = remap_pci_mem(paddr, 0x250);
6325 if (!vaddr)
6326 return -ENOMEM;
edd16368 6327
1df8552a
SC		 6328 /* find cfgtable in order to check if reset via doorbell is supported */
6329 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6330 &cfg_base_addr_index, &cfg_offset);
6331 if (rc)
6332 goto unmap_vaddr;
6333 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6334 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6335 if (!cfgtable) {
6336 rc = -ENOMEM;
6337 goto unmap_vaddr;
6338 }
580ada3c
SC		 6339 rc = write_driver_ver_to_cfgtable(cfgtable);
6340 if (rc)
03741d95 6341 goto unmap_cfgtable;
edd16368 6342
cf0b08d0
SC		 6343 /* If reset via doorbell register is supported, use that.
6344 * There are two such methods. Favor the newest method.
6345 */
1df8552a 6346 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6347 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6348 if (use_doorbell) {
6349 use_doorbell = DOORBELL_CTLR_RESET2;
6350 } else {
6351 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6352 if (use_doorbell) {
050f7147
SC		 6353 dev_warn(&pdev->dev,
6354 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6355 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6356 goto unmap_cfgtable;
6357 }
6358 }
edd16368 6359
1df8552a
SC		 6360 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6361 if (rc)
6362 goto unmap_cfgtable;
edd16368 6363
270d05de 6364 pci_restore_state(pdev);
270d05de 6365 pci_write_config_word(pdev, 4, command_register);
edd16368 6366
1df8552a
SC		 6367 /* Some devices (notably the HP Smart Array 5i Controller)
6368 need a little pause here */
6369 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6370
fe5389c8
SC		 6371 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6372 if (rc) {
6373 dev_warn(&pdev->dev,
050f7147 6374 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6375 goto unmap_cfgtable;
6376 }
fe5389c8 6377
580ada3c
SC		 6378 rc = controller_reset_failed(vaddr);
6379 if (rc < 0)
6380 goto unmap_cfgtable;
6381 if (rc) {
64670ac8
SC		 6382 dev_warn(&pdev->dev, "Unable to successfully reset "
6383 "controller. Will try soft reset.\n");
6384 rc = -ENOTSUPP;
580ada3c 6385 } else {
64670ac8 6386 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6387 }
6388
6389unmap_cfgtable:
6390 iounmap(cfgtable);
6391
6392unmap_vaddr:
6393 iounmap(vaddr);
6394 return rc;
edd16368
SC		 6395}
6396
6397/*
6398 * We cannot read the structure directly, for portability we must use
6399 * the io functions.
6400 * This is for debug only.
6401 */
42a91641 6402static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6403{
58f8665c 6404#ifdef HPSA_DEBUG
edd16368
SC		 6405 int i;
6406 char temp_name[17];
6407
6408 dev_info(dev, "Controller Configuration information\n");
6409 dev_info(dev, "------------------------------------\n");
6410 for (i = 0; i < 4; i++)
6411 temp_name[i] = readb(&(tb->Signature[i]));
6412 temp_name[4] = '\0';
6413 dev_info(dev, " Signature = %s\n", temp_name);
6414 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6415 dev_info(dev, " Transport methods supported = 0x%x\n",
6416 readl(&(tb->TransportSupport)));
6417 dev_info(dev, " Transport methods active = 0x%x\n",
6418 readl(&(tb->TransportActive)));
6419 dev_info(dev, " Requested transport Method = 0x%x\n",
6420 readl(&(tb->HostWrite.TransportRequest)));
6421 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6422 readl(&(tb->HostWrite.CoalIntDelay)));
6423 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6424 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6425 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6426 readl(&(tb->CmdsOutMax)));
6427 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6428 for (i = 0; i < 16; i++)
6429 temp_name[i] = readb(&(tb->ServerName[i]));
6430 temp_name[16] = '\0';
6431 dev_info(dev, " Server Name = %s\n", temp_name);
6432 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6433 readl(&(tb->HeartBeat)));
edd16368 6434#endif /* HPSA_DEBUG */
58f8665c 6435}
edd16368
SC		 6436
6437static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6438{
6439 int i, offset, mem_type, bar_type;
6440
6441 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6442 return 0;
6443 offset = 0;
6444 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6445 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6446 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6447 offset += 4;
6448 else {
6449 mem_type = pci_resource_flags(pdev, i) &
6450 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6451 switch (mem_type) {
6452 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6453 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6454 offset += 4; /* 32 bit */
6455 break;
6456 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6457 offset += 8;
6458 break;
6459 default: /* reserved in PCI 2.2 */
6460 dev_warn(&pdev->dev,
6461 "base address is invalid\n");
6462 return -1;
6463 break;
6464 }
6465 }
6466 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6467 return i + 1;
6468 }
6469 return -1;
6470}
6471
cc64c817
RE		 6472static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6473{
6474 if (h->msix_vector) {
6475 if (h->pdev->msix_enabled)
6476 pci_disable_msix(h->pdev);
6477 } else if (h->msi_vector) {
6478 if (h->pdev->msi_enabled)
6479 pci_disable_msi(h->pdev);
6480 }
6481}
6482
edd16368 6483/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6484 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6485 */
6f039790 6486static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6487{
6488#ifdef CONFIG_PCI_MSI
254f796b
MG		 6489 int err, i;
6490 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6491
6492 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6493 hpsa_msix_entries[i].vector = 0;
6494 hpsa_msix_entries[i].entry = i;
6495 }
edd16368
SC		 6496
6497 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6498 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6499 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6500 goto default_int_mode;
55c06c71 6501 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6502 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6503 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6504 if (h->msix_vector > num_online_cpus())
6505 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6506 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6507 1, h->msix_vector);
6508 if (err < 0) {
6509 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6510 h->msix_vector = 0;
6511 goto single_msi_mode;
6512 } else if (err < h->msix_vector) {
55c06c71 6513 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6514 "available\n", err);
edd16368 6515 }
18fce3c4
AG		 6516 h->msix_vector = err;
6517 for (i = 0; i < h->msix_vector; i++)
6518 h->intr[i] = hpsa_msix_entries[i].vector;
6519 return;
edd16368 6520 }
18fce3c4 6521single_msi_mode:
55c06c71 6522 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6523 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6524 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6525 h->msi_vector = 1;
6526 else
55c06c71 6527 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6528 }
6529default_int_mode:
6530#endif /* CONFIG_PCI_MSI */
6531 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6532 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6533}
6534
6f039790 6535static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6536{
6537 int i;
6538 u32 subsystem_vendor_id, subsystem_device_id;
6539
6540 subsystem_vendor_id = pdev->subsystem_vendor;
6541 subsystem_device_id = pdev->subsystem_device;
6542 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6543 subsystem_vendor_id;
6544
6545 for (i = 0; i < ARRAY_SIZE(products); i++)
6546 if (*board_id == products[i].board_id)
6547 return i;
6548
6798cc0a
SC		 6549 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6550 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6551 !hpsa_allow_any) {
e5c880d1
SC		 6552 dev_warn(&pdev->dev, "unrecognized board ID: "
6553 "0x%08x, ignoring.\n", *board_id);
6554 return -ENODEV;
6555 }
6556 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6557}
6558
6f039790
GKH		 6559static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6560 unsigned long *memory_bar)
3a7774ce
SC		 6561{
6562 int i;
6563
6564 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6565 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6566 /* addressing mode bits already removed */
12d2cd47
SC		 6567 *memory_bar = pci_resource_start(pdev, i);
6568 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6569 *memory_bar);
6570 return 0;
6571 }
12d2cd47 6572 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6573 return -ENODEV;
6574}
6575
6f039790
GKH		 6576static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6577 int wait_for_ready)
2c4c8c8b 6578{
fe5389c8 6579 int i, iterations;
2c4c8c8b 6580 u32 scratchpad;
fe5389c8
SC		 6581 if (wait_for_ready)
6582 iterations = HPSA_BOARD_READY_ITERATIONS;
6583 else
6584 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6585
fe5389c8
SC		 6586 for (i = 0; i < iterations; i++) {
6587 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6588 if (wait_for_ready) {
6589 if (scratchpad == HPSA_FIRMWARE_READY)
6590 return 0;
6591 } else {
6592 if (scratchpad != HPSA_FIRMWARE_READY)
6593 return 0;
6594 }
2c4c8c8b
SC		 6595 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6596 }
fe5389c8 6597 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6598 return -ENODEV;
6599}
6600
6f039790
GKH		 6601static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6602 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6603 u64 *cfg_offset)
a51fd47f
SC		 6604{
6605 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6606 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6607 *cfg_base_addr &= (u32) 0x0000ffff;
6608 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6609 if (*cfg_base_addr_index == -1) {
6610 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6611 return -ENODEV;
6612 }
6613 return 0;
6614}
6615
195f2c65
RE		 6616static void hpsa_free_cfgtables(struct ctlr_info *h)
6617{
6618 if (h->transtable)
6619 iounmap(h->transtable);
6620 if (h->cfgtable)
6621 iounmap(h->cfgtable);
6622}
6623
6624/* Find and map CISS config table and transfer table
6625+ * several items must be unmapped (freed) later
6626+ * */
6f039790 6627static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6628{
01a02ffc
SC		 6629 u64 cfg_offset;
6630 u32 cfg_base_addr;
6631 u64 cfg_base_addr_index;
303932fd 6632 u32 trans_offset;
a51fd47f 6633 int rc;
77c4495c 6634
a51fd47f
SC		 6635 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6636 &cfg_base_addr_index, &cfg_offset);
6637 if (rc)
6638 return rc;
77c4495c 6639 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6640 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6641 if (!h->cfgtable) {
6642 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6643 return -ENOMEM;
cd3c81c4 6644 }
580ada3c
SC		 6645 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6646 if (rc)
6647 return rc;
77c4495c 6648 /* Find performant mode table. */
a51fd47f 6649 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6650 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6651 cfg_base_addr_index)+cfg_offset+trans_offset,
6652 sizeof(*h->transtable));
195f2c65
RE		 6653 if (!h->transtable) {
6654 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
6655 hpsa_free_cfgtables(h);
77c4495c 6656 return -ENOMEM;
195f2c65 6657 }
77c4495c
SC		 6658 return 0;
6659}
6660
6f039790 6661static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 6662{
41ce4c35
SC		 6663#define MIN_MAX_COMMANDS 16
6664 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
6665
6666 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 6667
6668 /* Limit commands in memory limited kdump scenario. */
6669 if (reset_devices && h->max_commands > 32)
6670 h->max_commands = 32;
6671
41ce4c35
SC		 6672 if (h->max_commands < MIN_MAX_COMMANDS) {
6673 dev_warn(&h->pdev->dev,
6674 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
6675 h->max_commands,
6676 MIN_MAX_COMMANDS);
6677 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 6678 }
6679}
6680
c7ee65b3
WS		 6681/* If the controller reports that the total max sg entries is greater than 512,
6682 * then we know that chained SG blocks work. (Original smart arrays did not
6683 * support chained SG blocks and would return zero for max sg entries.)
6684 */
6685static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6686{
6687 return h->maxsgentries > 512;
6688}
6689
b93d7536
SC		 6690/* Interrogate the hardware for some limits:
6691 * max commands, max SG elements without chaining, and with chaining,
6692 * SG chain block size, etc.
6693 */
6f039790 6694static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6695{
cba3d38b 6696 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6697 h->nr_cmds = h->max_commands;
b93d7536 6698 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6699 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6700 if (hpsa_supports_chained_sg_blocks(h)) {
6701 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6702 h->max_cmd_sg_entries = 32;
1a63ea6f 6703 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6704 h->maxsgentries--; /* save one for chain pointer */
6705 } else {
c7ee65b3
WS		 6706 /*
6707 * Original smart arrays supported at most 31 s/g entries
6708 * embedded inline in the command (trying to use more
6709 * would lock up the controller)
6710 */
6711 h->max_cmd_sg_entries = 31;
1a63ea6f 6712 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6713 h->chainsize = 0;
b93d7536 6714 }
75167d2c
SC		 6715
6716 /* Find out what task management functions are supported and cache */
6717 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6718 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6719 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6720 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6721 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6722}
6723
76c46e49
SC		 6724static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6725{
0fc9fd40 6726 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6727 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6728 return false;
6729 }
6730 return true;
6731}
6732
97a5e98c 6733static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6734{
97a5e98c 6735 u32 driver_support;
f7c39101 6736
97a5e98c 6737 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6738 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6739#ifdef CONFIG_X86
97a5e98c 6740 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6741#endif
28e13446
SC		 6742 driver_support |= ENABLE_UNIT_ATTN;
6743 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6744}
6745
3d0eab67
SC		 6746/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6747 * in a prefetch beyond physical memory.
6748 */
6749static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6750{
6751 u32 dma_prefetch;
6752
6753 if (h->board_id != 0x3225103C)
6754 return;
6755 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6756 dma_prefetch |= 0x8000;
6757 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6758}
6759
c706a795 6760static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 6761{
6762 int i;
6763 u32 doorbell_value;
6764 unsigned long flags;
6765 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 6766 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 6767 spin_lock_irqsave(&h->lock, flags);
6768 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6769 spin_unlock_irqrestore(&h->lock, flags);
6770 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 6771 goto done;
76438d08 6772 /* delay and try again */
007e7aa9 6773 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 6774 }
c706a795
RE		 6775 return -ENODEV;
6776done:
6777 return 0;
76438d08
SC		 6778}
6779
c706a795 6780static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6781{
6782 int i;
6eaf46fd
SC		 6783 u32 doorbell_value;
6784 unsigned long flags;
eb6b2ae9
SC		 6785
6786 /* under certain very rare conditions, this can take awhile.
6787 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6788 * as we enter this code.)
6789 */
007e7aa9 6790 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 6791 if (h->remove_in_progress)
6792 goto done;
6eaf46fd
SC		 6793 spin_lock_irqsave(&h->lock, flags);
6794 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6795 spin_unlock_irqrestore(&h->lock, flags);
382be668 6796 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 6797 goto done;
eb6b2ae9 6798 /* delay and try again */
007e7aa9 6799 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 6800 }
c706a795
RE		 6801 return -ENODEV;
6802done:
6803 return 0;
3f4336f3
SC		 6804}
6805
c706a795 6806/* return -ENODEV or other reason on error, 0 on success */
6f039790 6807static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6808{
6809 u32 trans_support;
6810
6811 trans_support = readl(&(h->cfgtable->TransportSupport));
6812 if (!(trans_support & SIMPLE_MODE))
6813 return -ENOTSUPP;
6814
6815 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6816
3f4336f3
SC		 6817 /* Update the field, and then ring the doorbell */
6818 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6819 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 6820 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 6821 if (hpsa_wait_for_mode_change_ack(h))
6822 goto error;
eb6b2ae9 6823 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6824 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6825 goto error;
960a30e7 6826 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6827 return 0;
283b4a9b 6828error:
050f7147 6829 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6830 return -ENODEV;
eb6b2ae9
SC		 6831}
6832
195f2c65
RE		 6833/* free items allocated or mapped by hpsa_pci_init */
6834static void hpsa_free_pci_init(struct ctlr_info *h)
6835{
6836 hpsa_free_cfgtables(h); /* pci_init 4 */
6837 iounmap(h->vaddr); /* pci_init 3 */
6838 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
6839 pci_release_regions(h->pdev); /* pci_init 2 */
6840 pci_disable_device(h->pdev); /* pci_init 1 */
6841}
6842
6843/* several items must be freed later */
6f039790 6844static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6845{
eb6b2ae9 6846 int prod_index, err;
edd16368 6847
e5c880d1
SC		 6848 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6849 if (prod_index < 0)
60f923b9 6850 return prod_index;
e5c880d1
SC		 6851 h->product_name = products[prod_index].product_name;
6852 h->access = *(products[prod_index].access);
edd16368 6853
9b5c48c2
SC		 6854 h->needs_abort_tags_swizzled =
6855 ctlr_needs_abort_tags_swizzled(h->board_id);
6856
e5a44df8
MG		 6857 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6858 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6859
55c06c71 6860 err = pci_enable_device(h->pdev);
edd16368 6861 if (err) {
195f2c65 6862 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
edd16368
SC		 6863 return err;
6864 }
6865
f79cfec6 6866 err = pci_request_regions(h->pdev, HPSA);
edd16368 6867 if (err) {
55c06c71 6868 dev_err(&h->pdev->dev,
195f2c65
RE		 6869 "failed to obtain PCI resources\n");
6870 goto clean1; /* pci */
edd16368 6871 }
4fa604e1
RE		 6872
6873 pci_set_master(h->pdev);
6874
6b3f4c52 6875 hpsa_interrupt_mode(h);
12d2cd47 6876 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6877 if (err)
195f2c65 6878 goto clean2; /* intmode+region, pci */
edd16368 6879 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 6880 if (!h->vaddr) {
195f2c65 6881 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 6882 err = -ENOMEM;
195f2c65 6883 goto clean2; /* intmode+region, pci */
204892e9 6884 }
fe5389c8 6885 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6886 if (err)
195f2c65 6887 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 6888 err = hpsa_find_cfgtables(h);
6889 if (err)
195f2c65 6890 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 6891 hpsa_find_board_params(h);
edd16368 6892
76c46e49 6893 if (!hpsa_CISS_signature_present(h)) {
edd16368 6894 err = -ENODEV;
195f2c65 6895 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 6896 }
97a5e98c 6897 hpsa_set_driver_support_bits(h);
3d0eab67 6898 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6899 err = hpsa_enter_simple_mode(h);
6900 if (err)
195f2c65 6901 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 6902 return 0;
6903
195f2c65
RE		 6904clean4: /* cfgtables, vaddr, intmode+region, pci */
6905 hpsa_free_cfgtables(h);
6906clean3: /* vaddr, intmode+region, pci */
6907 iounmap(h->vaddr);
6908clean2: /* intmode+region, pci */
6909 hpsa_disable_interrupt_mode(h);
55c06c71 6910 pci_release_regions(h->pdev);
195f2c65
RE		 6911clean1: /* pci */
6912 pci_disable_device(h->pdev);
edd16368
SC		 6913 return err;
6914}
6915
6f039790 6916static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6917{
6918 int rc;
6919
6920#define HBA_INQUIRY_BYTE_COUNT 64
6921 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6922 if (!h->hba_inquiry_data)
6923 return;
6924 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6925 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6926 if (rc != 0) {
6927 kfree(h->hba_inquiry_data);
6928 h->hba_inquiry_data = NULL;
6929 }
6930}
6931
6b6c1cd7 6932static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 6933{
1df8552a 6934 int rc, i;
3b747298 6935 void __iomem *vaddr;
4c2a8c40
SC		 6936
6937 if (!reset_devices)
6938 return 0;
6939
132aa220
TH		 6940 /* kdump kernel is loading, we don't know in which state is
6941 * the pci interface. The dev->enable_cnt is equal zero
6942 * so we call enable+disable, wait a while and switch it on.
6943 */
6944 rc = pci_enable_device(pdev);
6945 if (rc) {
6946 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6947 return -ENODEV;
6948 }
6949 pci_disable_device(pdev);
6950 msleep(260); /* a randomly chosen number */
6951 rc = pci_enable_device(pdev);
6952 if (rc) {
6953 dev_warn(&pdev->dev, "failed to enable device.\n");
6954 return -ENODEV;
6955 }
4fa604e1 6956
859c75ab 6957 pci_set_master(pdev);
4fa604e1 6958
3b747298
TH		 6959 vaddr = pci_ioremap_bar(pdev, 0);
6960 if (vaddr == NULL) {
6961 rc = -ENOMEM;
6962 goto out_disable;
6963 }
6964 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6965 iounmap(vaddr);
6966
1df8552a 6967 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 6968 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 6969
1df8552a
SC		 6970 /* -ENOTSUPP here means we cannot reset the controller
6971 * but it's already (and still) up and running in
18867659
SC		 6972 * "performant mode". Or, it might be 640x, which can't reset
6973 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6974 */
adf1b3a3 6975 if (rc)
132aa220 6976 goto out_disable;
4c2a8c40
SC		 6977
6978 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6979 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6980 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6981 if (hpsa_noop(pdev) == 0)
6982 break;
6983 else
6984 dev_warn(&pdev->dev, "no-op failed%s\n",
6985 (i < 11 ? "; re-trying" : ""));
6986 }
132aa220
TH		 6987
6988out_disable:
6989
6990 pci_disable_device(pdev);
6991 return rc;
4c2a8c40
SC		 6992}
6993
1fb7c98a
RE		 6994static void hpsa_free_cmd_pool(struct ctlr_info *h)
6995{
6996 kfree(h->cmd_pool_bits);
6997 if (h->cmd_pool)
6998 pci_free_consistent(h->pdev,
6999 h->nr_cmds * sizeof(struct CommandList),
7000 h->cmd_pool,
7001 h->cmd_pool_dhandle);
7002 if (h->errinfo_pool)
7003 pci_free_consistent(h->pdev,
7004 h->nr_cmds * sizeof(struct ErrorInfo),
7005 h->errinfo_pool,
7006 h->errinfo_pool_dhandle);
7007}
7008
d37ffbe4 7009static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7010{
7011 h->cmd_pool_bits = kzalloc(
7012 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7013 sizeof(unsigned long), GFP_KERNEL);
7014 h->cmd_pool = pci_alloc_consistent(h->pdev,
7015 h->nr_cmds * sizeof(*h->cmd_pool),
7016 &(h->cmd_pool_dhandle));
7017 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7018 h->nr_cmds * sizeof(*h->errinfo_pool),
7019 &(h->errinfo_pool_dhandle));
7020 if ((h->cmd_pool_bits == NULL)
7021 || (h->cmd_pool == NULL)
7022 || (h->errinfo_pool == NULL)) {
7023 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7024 goto clean_up;
2e9d1b36 7025 }
360c73bd 7026 hpsa_preinitialize_commands(h);
2e9d1b36 7027 return 0;
2c143342
RE		 7028clean_up:
7029 hpsa_free_cmd_pool(h);
7030 return -ENOMEM;
2e9d1b36
SC		 7031}
7032
41b3cf08
SC		 7033static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7034{
ec429952 7035 int i, cpu;
41b3cf08
SC		 7036
7037 cpu = cpumask_first(cpu_online_mask);
7038 for (i = 0; i < h->msix_vector; i++) {
ec429952 7039 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7040 cpu = cpumask_next(cpu, cpu_online_mask);
7041 }
7042}
7043
ec501a18
RE		 7044/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7045static void hpsa_free_irqs(struct ctlr_info *h)
7046{
7047 int i;
7048
7049 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7050 /* Single reply queue, only one irq to free */
7051 i = h->intr_mode;
7052 irq_set_affinity_hint(h->intr[i], NULL);
7053 free_irq(h->intr[i], &h->q[i]);
7054 return;
7055 }
7056
7057 for (i = 0; i < h->msix_vector; i++) {
7058 irq_set_affinity_hint(h->intr[i], NULL);
7059 free_irq(h->intr[i], &h->q[i]);
7060 }
a4e17fc1
RE		 7061 for (; i < MAX_REPLY_QUEUES; i++)
7062 h->q[i] = 0;
ec501a18
RE		 7063}
7064
9ee61794
RE		 7065/* returns 0 on success; cleans up and returns -Enn on error */
7066static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7067 irqreturn_t (*msixhandler)(int, void *),
7068 irqreturn_t (*intxhandler)(int, void *))
7069{
254f796b 7070 int rc, i;
0ae01a32 7071
254f796b
MG		 7072 /*
7073 * initialize h->q[x] = x so that interrupt handlers know which
7074 * queue to process.
7075 */
7076 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7077 h->q[i] = (u8) i;
7078
eee0f03a 7079 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7080 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7081 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 7082 rc = request_irq(h->intr[i], msixhandler,
7083 0, h->devname,
7084 &h->q[i]);
a4e17fc1
RE		 7085 if (rc) {
7086 int j;
7087
7088 dev_err(&h->pdev->dev,
7089 "failed to get irq %d for %s\n",
7090 h->intr[i], h->devname);
7091 for (j = 0; j < i; j++) {
7092 free_irq(h->intr[j], &h->q[j]);
7093 h->q[j] = 0;
7094 }
7095 for (; j < MAX_REPLY_QUEUES; j++)
7096 h->q[j] = 0;
7097 return rc;
7098 }
7099 }
41b3cf08 7100 hpsa_irq_affinity_hints(h);
254f796b
MG		 7101 } else {
7102 /* Use single reply pool */
eee0f03a 7103 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 7104 rc = request_irq(h->intr[h->intr_mode],
7105 msixhandler, 0, h->devname,
7106 &h->q[h->intr_mode]);
7107 } else {
7108 rc = request_irq(h->intr[h->intr_mode],
7109 intxhandler, IRQF_SHARED, h->devname,
7110 &h->q[h->intr_mode]);
7111 }
7112 }
0ae01a32 7113 if (rc) {
195f2c65 7114 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7115 h->intr[h->intr_mode], h->devname);
195f2c65 7116 hpsa_free_irqs(h);
0ae01a32
SC		 7117 return -ENODEV;
7118 }
7119 return 0;
7120}
7121
6f039790 7122static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 7123{
7124 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
7125 HPSA_RESET_TYPE_CONTROLLER)) {
7126 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
7127 return -EIO;
7128 }
7129
7130 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
7131 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
7132 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
7133 return -1;
7134 }
7135
7136 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
7137 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
7138 dev_warn(&h->pdev->dev, "Board failed to become ready "
7139 "after soft reset.\n");
7140 return -1;
7141 }
7142
7143 return 0;
7144}
7145
072b0518
SC		 7146static void hpsa_free_reply_queues(struct ctlr_info *h)
7147{
7148 int i;
7149
7150 for (i = 0; i < h->nreply_queues; i++) {
7151 if (!h->reply_queue[i].head)
7152 continue;
1fb7c98a
RE		 7153 pci_free_consistent(h->pdev,
7154 h->reply_queue_size,
7155 h->reply_queue[i].head,
7156 h->reply_queue[i].busaddr);
072b0518
SC		 7157 h->reply_queue[i].head = NULL;
7158 h->reply_queue[i].busaddr = 0;
7159 }
7160}
7161
0097f0f4
SC		 7162static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7163{
cc64c817 7164 hpsa_free_irqs(h);
64670ac8
SC		 7165 hpsa_free_sg_chain_blocks(h);
7166 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7167 kfree(h->blockFetchTable); /* perf 2 */
7168 hpsa_free_reply_queues(h); /* perf 1 */
7169 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7170 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
195f2c65
RE		 7171 hpsa_free_cfgtables(h); /* pci_init 4 */
7172 iounmap(h->vaddr); /* pci_init 3 */
7173 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
132aa220 7174 pci_disable_device(h->pdev);
195f2c65 7175 pci_release_regions(h->pdev); /* pci_init 2 */
64670ac8
SC		 7176 kfree(h);
7177}
7178
a0c12413 7179/* Called when controller lockup detected. */
f2405db8 7180static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7181{
281a7fd0
WS		 7182 int i, refcount;
7183 struct CommandList *c;
25163bd5 7184 int failcount = 0;
a0c12413 7185
080ef1cc 7186 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7187 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7188 c = h->cmd_pool + i;
281a7fd0
WS		 7189 refcount = atomic_inc_return(&c->refcount);
7190 if (refcount > 1) {
25163bd5 7191 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7192 finish_cmd(c);
433b5f4d 7193 atomic_dec(&h->commands_outstanding);
25163bd5 7194 failcount++;
281a7fd0
WS		 7195 }
7196 cmd_free(h, c);
a0c12413 7197 }
25163bd5
WS		 7198 dev_warn(&h->pdev->dev,
7199 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7200}
7201
094963da
SC		 7202static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7203{
c8ed0010 7204 int cpu;
094963da 7205
c8ed0010 7206 for_each_online_cpu(cpu) {
094963da
SC		 7207 u32 *lockup_detected;
7208 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7209 *lockup_detected = value;
094963da
SC		 7210 }
7211 wmb(); /* be sure the per-cpu variables are out to memory */
7212}
7213
a0c12413
SC		 7214static void controller_lockup_detected(struct ctlr_info *h)
7215{
7216 unsigned long flags;
094963da 7217 u32 lockup_detected;
a0c12413 7218
a0c12413
SC		 7219 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7220 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7221 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7222 if (!lockup_detected) {
7223 /* no heartbeat, but controller gave us a zero. */
7224 dev_warn(&h->pdev->dev,
25163bd5
WS		 7225 "lockup detected after %d but scratchpad register is zero\n",
7226 h->heartbeat_sample_interval / HZ);
094963da
SC		 7227 lockup_detected = 0xffffffff;
7228 }
7229 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7230 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7231 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7232 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7233 pci_disable_device(h->pdev);
f2405db8 7234 fail_all_outstanding_cmds(h);
a0c12413
SC		 7235}
7236
25163bd5 7237static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7238{
7239 u64 now;
7240 u32 heartbeat;
7241 unsigned long flags;
7242
a0c12413
SC		 7243 now = get_jiffies_64();
7244 /* If we've received an interrupt recently, we're ok. */
7245 if (time_after64(h->last_intr_timestamp +
e85c5974 7246 (h->heartbeat_sample_interval), now))
25163bd5 7247 return false;
a0c12413
SC		 7248
7249 /*
7250 * If we've already checked the heartbeat recently, we're ok.
7251 * This could happen if someone sends us a signal. We
7252 * otherwise don't care about signals in this thread.
7253 */
7254 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7255 (h->heartbeat_sample_interval), now))
25163bd5 7256 return false;
a0c12413
SC		 7257
7258 /* If heartbeat has not changed since we last looked, we're not ok. */
7259 spin_lock_irqsave(&h->lock, flags);
7260 heartbeat = readl(&h->cfgtable->HeartBeat);
7261 spin_unlock_irqrestore(&h->lock, flags);
7262 if (h->last_heartbeat == heartbeat) {
7263 controller_lockup_detected(h);
25163bd5 7264 return true;
a0c12413
SC		 7265 }
7266
7267 /* We're ok. */
7268 h->last_heartbeat = heartbeat;
7269 h->last_heartbeat_timestamp = now;
25163bd5 7270 return false;
a0c12413
SC		 7271}
7272
9846590e 7273static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7274{
7275 int i;
7276 char *event_type;
7277
e4aa3e6a
SC		 7278 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7279 return;
7280
76438d08 7281 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7282 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7283 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7284 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7285 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7286
7287 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7288 event_type = "state change";
7289 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7290 event_type = "configuration change";
7291 /* Stop sending new RAID offload reqs via the IO accelerator */
7292 scsi_block_requests(h->scsi_host);
7293 for (i = 0; i < h->ndevices; i++)
7294 h->dev[i]->offload_enabled = 0;
23100dd9 7295 hpsa_drain_accel_commands(h);
76438d08
SC		 7296 /* Set 'accelerator path config change' bit */
7297 dev_warn(&h->pdev->dev,
7298 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7299 h->events, event_type);
7300 writel(h->events, &(h->cfgtable->clear_event_notify));
7301 /* Set the "clear event notify field update" bit 6 */
7302 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7303 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7304 hpsa_wait_for_clear_event_notify_ack(h);
7305 scsi_unblock_requests(h->scsi_host);
7306 } else {
7307 /* Acknowledge controller notification events. */
7308 writel(h->events, &(h->cfgtable->clear_event_notify));
7309 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7310 hpsa_wait_for_clear_event_notify_ack(h);
7311#if 0
7312 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7313 hpsa_wait_for_mode_change_ack(h);
7314#endif
7315 }
9846590e 7316 return;
76438d08
SC		 7317}
7318
7319/* Check a register on the controller to see if there are configuration
7320 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7321 * we should rescan the controller for devices.
7322 * Also check flag for driver-initiated rescan.
76438d08 7323 */
9846590e 7324static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7325{
7326 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7327 return 0;
76438d08
SC		 7328
7329 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7330 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7331}
76438d08 7332
9846590e
SC		 7333/*
7334 * Check if any of the offline devices have become ready
7335 */
7336static int hpsa_offline_devices_ready(struct ctlr_info *h)
7337{
7338 unsigned long flags;
7339 struct offline_device_entry *d;
7340 struct list_head *this, *tmp;
7341
7342 spin_lock_irqsave(&h->offline_device_lock, flags);
7343 list_for_each_safe(this, tmp, &h->offline_device_list) {
7344 d = list_entry(this, struct offline_device_entry,
7345 offline_list);
7346 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7347 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7348 spin_lock_irqsave(&h->offline_device_lock, flags);
7349 list_del(&d->offline_list);
7350 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7351 return 1;
d1fea47c 7352 }
9846590e
SC		 7353 spin_lock_irqsave(&h->offline_device_lock, flags);
7354 }
7355 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7356 return 0;
76438d08
SC		 7357}
7358
6636e7f4 7359static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7360{
7361 unsigned long flags;
8a98db73 7362 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7363 struct ctlr_info, rescan_ctlr_work);
7364
7365
7366 if (h->remove_in_progress)
8a98db73 7367 return;
9846590e
SC		 7368
7369 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7370 scsi_host_get(h->scsi_host);
9846590e
SC		 7371 hpsa_ack_ctlr_events(h);
7372 hpsa_scan_start(h->scsi_host);
7373 scsi_host_put(h->scsi_host);
7374 }
8a98db73 7375 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7376 if (!h->remove_in_progress)
7377 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7378 h->heartbeat_sample_interval);
7379 spin_unlock_irqrestore(&h->lock, flags);
7380}
7381
7382static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7383{
7384 unsigned long flags;
7385 struct ctlr_info *h = container_of(to_delayed_work(work),
7386 struct ctlr_info, monitor_ctlr_work);
7387
7388 detect_controller_lockup(h);
7389 if (lockup_detected(h))
a0c12413 7390 return;
6636e7f4
DB		 7391
7392 spin_lock_irqsave(&h->lock, flags);
7393 if (!h->remove_in_progress)
7394 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7395 h->heartbeat_sample_interval);
7396 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7397}
7398
6636e7f4
DB		 7399static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7400 char *name)
7401{
7402 struct workqueue_struct *wq = NULL;
6636e7f4 7403
397ea9cb 7404 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7405 if (!wq)
7406 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7407
7408 return wq;
7409}
7410
6f039790 7411static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7412{
4c2a8c40 7413 int dac, rc;
edd16368 7414 struct ctlr_info *h;
64670ac8
SC		 7415 int try_soft_reset = 0;
7416 unsigned long flags;
6b6c1cd7 7417 u32 board_id;
edd16368
SC		 7418
7419 if (number_of_controllers == 0)
7420 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7421
6b6c1cd7
TH		 7422 rc = hpsa_lookup_board_id(pdev, &board_id);
7423 if (rc < 0) {
7424 dev_warn(&pdev->dev, "Board ID not found\n");
7425 return rc;
7426 }
7427
7428 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7429 if (rc) {
7430 if (rc != -ENOTSUPP)
7431 return rc;
7432 /* If the reset fails in a particular way (it has no way to do
7433 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7434 * a soft reset once we get the controller configured up to the
7435 * point that it can accept a command.
7436 */
7437 try_soft_reset = 1;
7438 rc = 0;
7439 }
7440
7441reinit_after_soft_reset:
edd16368 7442
303932fd
DB		 7443 /* Command structures must be aligned on a 32-byte boundary because
7444 * the 5 lower bits of the address are used by the hardware. and by
7445 * the driver. See comments in hpsa.h for more info.
7446 */
303932fd 7447 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 7448 h = kzalloc(sizeof(*h), GFP_KERNEL);
7449 if (!h)
ecd9aad4 7450 return -ENOMEM;
edd16368 7451
55c06c71 7452 h->pdev = pdev;
a9a3a273 7453 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7454 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7455 spin_lock_init(&h->lock);
9846590e 7456 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7457 spin_lock_init(&h->scan_lock);
34f0c627 7458 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7459 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da 7460
6636e7f4
DB		 7461 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
7462 if (!h->rescan_ctlr_wq) {
7463 rc = -ENOMEM;
7464 goto clean1;
7465 }
7466
7467 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
080ef1cc 7468 if (!h->resubmit_wq) {
080ef1cc
DB		 7469 rc = -ENOMEM;
7470 goto clean1;
7471 }
6636e7f4 7472
094963da
SC		 7473 /* Allocate and clear per-cpu variable lockup_detected */
7474 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 7475 if (!h->lockup_detected) {
7476 rc = -ENOMEM;
094963da 7477 goto clean1;
2a5ac326 7478 }
094963da
SC		 7479 set_lockup_detected_for_all_cpus(h, 0);
7480
55c06c71 7481 rc = hpsa_pci_init(h);
ecd9aad4 7482 if (rc != 0)
edd16368
SC		 7483 goto clean1;
7484
f79cfec6 7485 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7486 h->ctlr = number_of_controllers;
7487 number_of_controllers++;
edd16368
SC		 7488
7489 /* configure PCI DMA stuff */
ecd9aad4
SC		 7490 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7491 if (rc == 0) {
edd16368 7492 dac = 1;
ecd9aad4
SC		 7493 } else {
7494 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7495 if (rc == 0) {
7496 dac = 0;
7497 } else {
7498 dev_err(&pdev->dev, "no suitable DMA available\n");
195f2c65 7499 goto clean2;
ecd9aad4 7500 }
edd16368
SC		 7501 }
7502
7503 /* make sure the board interrupts are off */
7504 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7505
9ee61794 7506 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7507 goto clean2;
303932fd
DB		 7508 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7509 h->devname, pdev->device,
a9a3a273 7510 h->intr[h->intr_mode], dac ? "" : " not");
d37ffbe4 7511 rc = hpsa_alloc_cmd_pool(h);
8947fd10
RE		 7512 if (rc)
7513 goto clean2_and_free_irqs;
33a2ffce
SC		 7514 if (hpsa_allocate_sg_chain_blocks(h))
7515 goto clean4;
a08a8471 7516 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7517 init_waitqueue_head(&h->abort_cmd_wait_queue);
a08a8471 7518 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7519
7520 pci_set_drvdata(pdev, h);
9a41338e 7521 h->ndevices = 0;
316b221a 7522 h->hba_mode_enabled = 0;
9a41338e
SC		 7523 h->scsi_host = NULL;
7524 spin_lock_init(&h->devlock);
64670ac8
SC		 7525 hpsa_put_ctlr_into_performant_mode(h);
7526
7527 /* At this point, the controller is ready to take commands.
7528 * Now, if reset_devices and the hard reset didn't work, try
7529 * the soft reset and see if that works.
7530 */
7531 if (try_soft_reset) {
7532
7533 /* This is kind of gross. We may or may not get a completion
7534 * from the soft reset command, and if we do, then the value
7535 * from the fifo may or may not be valid. So, we wait 10 secs
7536 * after the reset throwing away any completions we get during
7537 * that time. Unregister the interrupt handler and register
7538 * fake ones to scoop up any residual completions.
7539 */
7540 spin_lock_irqsave(&h->lock, flags);
7541 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7542 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 7543 hpsa_free_irqs(h);
9ee61794 7544 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 7545 hpsa_intx_discard_completions);
7546 if (rc) {
9ee61794
RE		 7547 dev_warn(&h->pdev->dev,
7548 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 7549 goto clean4;
7550 }
7551
7552 rc = hpsa_kdump_soft_reset(h);
7553 if (rc)
7554 /* Neither hard nor soft reset worked, we're hosed. */
7555 goto clean4;
7556
7557 dev_info(&h->pdev->dev, "Board READY.\n");
7558 dev_info(&h->pdev->dev,
7559 "Waiting for stale completions to drain.\n");
7560 h->access.set_intr_mask(h, HPSA_INTR_ON);
7561 msleep(10000);
7562 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7563
7564 rc = controller_reset_failed(h->cfgtable);
7565 if (rc)
7566 dev_info(&h->pdev->dev,
7567 "Soft reset appears to have failed.\n");
7568
7569 /* since the controller's reset, we have to go back and re-init
7570 * everything. Easiest to just forget what we've done and do it
7571 * all over again.
7572 */
7573 hpsa_undo_allocations_after_kdump_soft_reset(h);
7574 try_soft_reset = 0;
7575 if (rc)
7576 /* don't go to clean4, we already unallocated */
7577 return -ENODEV;
7578
7579 goto reinit_after_soft_reset;
7580 }
edd16368 7581
316b221a
SC		 7582 /* Enable Accelerated IO path at driver layer */
7583 h->acciopath_status = 1;
da0697bd 7584
e863d68e 7585
edd16368
SC		 7586 /* Turn the interrupts on so we can service requests */
7587 h->access.set_intr_mask(h, HPSA_INTR_ON);
7588
339b2b14 7589 hpsa_hba_inquiry(h);
4a4384ce
SC		 7590 rc = hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
7591 if (rc)
7592 goto clean4;
8a98db73
SC		 7593
7594 /* Monitor the controller for firmware lockups */
7595 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7596 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7597 schedule_delayed_work(&h->monitor_ctlr_work,
7598 h->heartbeat_sample_interval);
6636e7f4
DB		 7599 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
7600 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7601 h->heartbeat_sample_interval);
88bf6d62 7602 return 0;
edd16368
SC		 7603
7604clean4:
33a2ffce 7605 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7606 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7607 hpsa_free_ioaccel1_cmd_and_bft(h);
7608 hpsa_free_ioaccel2_cmd_and_bft(h);
8947fd10 7609clean2_and_free_irqs:
ec501a18 7610 hpsa_free_irqs(h);
edd16368 7611clean2:
195f2c65 7612 hpsa_free_pci_init(h);
edd16368 7613clean1:
080ef1cc
DB		 7614 if (h->resubmit_wq)
7615 destroy_workqueue(h->resubmit_wq);
6636e7f4
DB		 7616 if (h->rescan_ctlr_wq)
7617 destroy_workqueue(h->rescan_ctlr_wq);
094963da
SC		 7618 if (h->lockup_detected)
7619 free_percpu(h->lockup_detected);
edd16368 7620 kfree(h);
ecd9aad4 7621 return rc;
edd16368
SC		 7622}
7623
7624static void hpsa_flush_cache(struct ctlr_info *h)
7625{
7626 char *flush_buf;
7627 struct CommandList *c;
25163bd5 7628 int rc;
702890e3
SC		 7629
7630 /* Don't bother trying to flush the cache if locked up */
25163bd5 7631 /* FIXME not necessary if do_simple_cmd does the check */
094963da 7632 if (unlikely(lockup_detected(h)))
702890e3 7633 return;
edd16368
SC		 7634 flush_buf = kzalloc(4, GFP_KERNEL);
7635 if (!flush_buf)
7636 return;
7637
45fcb86e 7638 c = cmd_alloc(h);
edd16368 7639 if (!c) {
45fcb86e 7640 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7641 goto out_of_memory;
7642 }
a2dac136
SC		 7643 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7644 RAID_CTLR_LUNID, TYPE_CMD)) {
7645 goto out;
7646 }
25163bd5
WS		 7647 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
7648 PCI_DMA_TODEVICE, NO_TIMEOUT);
7649 if (rc)
7650 goto out;
edd16368 7651 if (c->err_info->CommandStatus != 0)
a2dac136 7652out:
edd16368
SC		 7653 dev_warn(&h->pdev->dev,
7654 "error flushing cache on controller\n");
45fcb86e 7655 cmd_free(h, c);
edd16368
SC		 7656out_of_memory:
7657 kfree(flush_buf);
7658}
7659
7660static void hpsa_shutdown(struct pci_dev *pdev)
7661{
7662 struct ctlr_info *h;
7663
7664 h = pci_get_drvdata(pdev);
7665 /* Turn board interrupts off and send the flush cache command
7666 * sendcmd will turn off interrupt, and send the flush...
7667 * To write all data in the battery backed cache to disks
7668 */
7669 hpsa_flush_cache(h);
7670 h->access.set_intr_mask(h, HPSA_INTR_OFF);
cc64c817
RE		 7671 hpsa_free_irqs(h);
7672 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 7673}
7674
6f039790 7675static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7676{
7677 int i;
7678
7679 for (i = 0; i < h->ndevices; i++)
7680 kfree(h->dev[i]);
7681}
7682
6f039790 7683static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7684{
7685 struct ctlr_info *h;
8a98db73 7686 unsigned long flags;
edd16368
SC		 7687
7688 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7689 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7690 return;
7691 }
7692 h = pci_get_drvdata(pdev);
8a98db73
SC		 7693
7694 /* Get rid of any controller monitoring work items */
7695 spin_lock_irqsave(&h->lock, flags);
7696 h->remove_in_progress = 1;
8a98db73 7697 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 7698 cancel_delayed_work_sync(&h->monitor_ctlr_work);
7699 cancel_delayed_work_sync(&h->rescan_ctlr_work);
7700 destroy_workqueue(h->rescan_ctlr_wq);
7701 destroy_workqueue(h->resubmit_wq);
edd16368 7702 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
cc64c817 7703
195f2c65
RE		 7704 /* includes hpsa_free_irqs */
7705 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 7706 hpsa_shutdown(pdev);
cc64c817 7707
55e14e76 7708 hpsa_free_device_info(h);
33a2ffce 7709 hpsa_free_sg_chain_blocks(h);
1fb7c98a
RE		 7710 kfree(h->blockFetchTable); /* perf 2 */
7711 hpsa_free_reply_queues(h); /* perf 1 */
7712 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7713 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
7714 hpsa_free_cmd_pool(h); /* init_one 5 */
339b2b14 7715 kfree(h->hba_inquiry_data);
195f2c65
RE		 7716
7717 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
7718 hpsa_free_pci_init(h);
7719
094963da 7720 free_percpu(h->lockup_detected);
edd16368
SC		 7721 kfree(h);
7722}
7723
7724static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7725 __attribute__((unused)) pm_message_t state)
7726{
7727 return -ENOSYS;
7728}
7729
7730static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7731{
7732 return -ENOSYS;
7733}
7734
7735static struct pci_driver hpsa_pci_driver = {
f79cfec6 7736 .name = HPSA,
edd16368 7737 .probe = hpsa_init_one,
6f039790 7738 .remove = hpsa_remove_one,
edd16368
SC		 7739 .id_table = hpsa_pci_device_id, /* id_table */
7740 .shutdown = hpsa_shutdown,
7741 .suspend = hpsa_suspend,
7742 .resume = hpsa_resume,
7743};
7744
303932fd
DB		 7745/* Fill in bucket_map[], given nsgs (the max number of
7746 * scatter gather elements supported) and bucket[],
7747 * which is an array of 8 integers. The bucket[] array
7748 * contains 8 different DMA transfer sizes (in 16
7749 * byte increments) which the controller uses to fetch
7750 * commands. This function fills in bucket_map[], which
7751 * maps a given number of scatter gather elements to one of
7752 * the 8 DMA transfer sizes. The point of it is to allow the
7753 * controller to only do as much DMA as needed to fetch the
7754 * command, with the DMA transfer size encoded in the lower
7755 * bits of the command address.
7756 */
7757static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7758 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7759{
7760 int i, j, b, size;
7761
303932fd
DB		 7762 /* Note, bucket_map must have nsgs+1 entries. */
7763 for (i = 0; i <= nsgs; i++) {
7764 /* Compute size of a command with i SG entries */
e1f7de0c 7765 size = i + min_blocks;
303932fd
DB		 7766 b = num_buckets; /* Assume the biggest bucket */
7767 /* Find the bucket that is just big enough */
e1f7de0c 7768 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7769 if (bucket[j] >= size) {
7770 b = j;
7771 break;
7772 }
7773 }
7774 /* for a command with i SG entries, use bucket b. */
7775 bucket_map[i] = b;
7776 }
7777}
7778
c706a795
RE		 7779/* return -ENODEV or other reason on error, 0 on success */
7780static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7781{
6c311b57
SC		 7782 int i;
7783 unsigned long register_value;
e1f7de0c
MG		 7784 unsigned long transMethod = CFGTBL_Trans_Performant |
7785 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7786 CFGTBL_Trans_enable_directed_msix |
7787 (trans_support & (CFGTBL_Trans_io_accel1 |
7788 CFGTBL_Trans_io_accel2));
e1f7de0c 7789 struct access_method access = SA5_performant_access;
def342bd
SC		 7790
7791 /* This is a bit complicated. There are 8 registers on
7792 * the controller which we write to to tell it 8 different
7793 * sizes of commands which there may be. It's a way of
7794 * reducing the DMA done to fetch each command. Encoded into
7795 * each command's tag are 3 bits which communicate to the controller
7796 * which of the eight sizes that command fits within. The size of
7797 * each command depends on how many scatter gather entries there are.
7798 * Each SG entry requires 16 bytes. The eight registers are programmed
7799 * with the number of 16-byte blocks a command of that size requires.
7800 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7801 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7802 * blocks. Note, this only extends to the SG entries contained
7803 * within the command block, and does not extend to chained blocks
7804 * of SG elements. bft[] contains the eight values we write to
7805 * the registers. They are not evenly distributed, but have more
7806 * sizes for small commands, and fewer sizes for larger commands.
7807 */
d66ae08b 7808 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7809#define MIN_IOACCEL2_BFT_ENTRY 5
7810#define HPSA_IOACCEL2_HEADER_SZ 4
7811 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7812 13, 14, 15, 16, 17, 18, 19,
7813 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7814 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7815 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7816 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7817 16 * MIN_IOACCEL2_BFT_ENTRY);
7818 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7819 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7820 /* 5 = 1 s/g entry or 4k
7821 * 6 = 2 s/g entry or 8k
7822 * 8 = 4 s/g entry or 16k
7823 * 10 = 6 s/g entry or 24k
7824 */
303932fd 7825
b3a52e79
SC		 7826 /* If the controller supports either ioaccel method then
7827 * we can also use the RAID stack submit path that does not
7828 * perform the superfluous readl() after each command submission.
7829 */
7830 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7831 access = SA5_performant_access_no_read;
7832
303932fd 7833 /* Controller spec: zero out this buffer. */
072b0518
SC		 7834 for (i = 0; i < h->nreply_queues; i++)
7835 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7836
d66ae08b
SC		 7837 bft[7] = SG_ENTRIES_IN_CMD + 4;
7838 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7839 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7840 for (i = 0; i < 8; i++)
7841 writel(bft[i], &h->transtable->BlockFetch[i]);
7842
7843 /* size of controller ring buffer */
7844 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7845 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7846 writel(0, &h->transtable->RepQCtrAddrLow32);
7847 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7848
7849 for (i = 0; i < h->nreply_queues; i++) {
7850 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7851 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7852 &h->transtable->RepQAddr[i].lower);
7853 }
7854
b9af4937 7855 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7856 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7857 /*
7858 * enable outbound interrupt coalescing in accelerator mode;
7859 */
7860 if (trans_support & CFGTBL_Trans_io_accel1) {
7861 access = SA5_ioaccel_mode1_access;
7862 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7863 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7864 } else {
7865 if (trans_support & CFGTBL_Trans_io_accel2) {
7866 access = SA5_ioaccel_mode2_access;
7867 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7868 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7869 }
e1f7de0c 7870 }
303932fd 7871 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7872 if (hpsa_wait_for_mode_change_ack(h)) {
7873 dev_err(&h->pdev->dev,
7874 "performant mode problem - doorbell timeout\n");
7875 return -ENODEV;
7876 }
303932fd
DB		 7877 register_value = readl(&(h->cfgtable->TransportActive));
7878 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7879 dev_err(&h->pdev->dev,
7880 "performant mode problem - transport not active\n");
c706a795 7881 return -ENODEV;
303932fd 7882 }
960a30e7 7883 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7884 h->access = access;
7885 h->transMethod = transMethod;
7886
b9af4937
SC		 7887 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7888 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 7889 return 0;
e1f7de0c 7890
b9af4937
SC		 7891 if (trans_support & CFGTBL_Trans_io_accel1) {
7892 /* Set up I/O accelerator mode */
7893 for (i = 0; i < h->nreply_queues; i++) {
7894 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7895 h->reply_queue[i].current_entry =
7896 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7897 }
7898 bft[7] = h->ioaccel_maxsg + 8;
7899 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7900 h->ioaccel1_blockFetchTable);
e1f7de0c 7901
b9af4937 7902 /* initialize all reply queue entries to unused */
072b0518
SC		 7903 for (i = 0; i < h->nreply_queues; i++)
7904 memset(h->reply_queue[i].head,
7905 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7906 h->reply_queue_size);
e1f7de0c 7907
b9af4937
SC		 7908 /* set all the constant fields in the accelerator command
7909 * frames once at init time to save CPU cycles later.
7910 */
7911 for (i = 0; i < h->nr_cmds; i++) {
7912 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7913
7914 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7915 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7916 (i * sizeof(struct ErrorInfo)));
7917 cp->err_info_len = sizeof(struct ErrorInfo);
7918 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7919 cp->host_context_flags =
7920 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7921 cp->timeout_sec = 0;
7922 cp->ReplyQueue = 0;
50a0decf 7923 cp->tag =
f2405db8 7924 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7925 cp->host_addr =
7926 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7927 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7928 }
7929 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7930 u64 cfg_offset, cfg_base_addr_index;
7931 u32 bft2_offset, cfg_base_addr;
7932 int rc;
7933
7934 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7935 &cfg_base_addr_index, &cfg_offset);
7936 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7937 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7938 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7939 4, h->ioaccel2_blockFetchTable);
7940 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7941 BUILD_BUG_ON(offsetof(struct CfgTable,
7942 io_accel_request_size_offset) != 0xb8);
7943 h->ioaccel2_bft2_regs =
7944 remap_pci_mem(pci_resource_start(h->pdev,
7945 cfg_base_addr_index) +
7946 cfg_offset + bft2_offset,
7947 ARRAY_SIZE(bft2) *
7948 sizeof(*h->ioaccel2_bft2_regs));
7949 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7950 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7951 }
b9af4937 7952 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7953 if (hpsa_wait_for_mode_change_ack(h)) {
7954 dev_err(&h->pdev->dev,
7955 "performant mode problem - enabling ioaccel mode\n");
7956 return -ENODEV;
7957 }
7958 return 0;
e1f7de0c
MG		 7959}
7960
1fb7c98a
RE		 7961/* Free ioaccel1 mode command blocks and block fetch table */
7962static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
7963{
7964 if (h->ioaccel_cmd_pool)
7965 pci_free_consistent(h->pdev,
7966 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7967 h->ioaccel_cmd_pool,
7968 h->ioaccel_cmd_pool_dhandle);
7969 kfree(h->ioaccel1_blockFetchTable);
7970}
7971
d37ffbe4
RE		 7972/* Allocate ioaccel1 mode command blocks and block fetch table */
7973static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 7974{
283b4a9b
SC		 7975 h->ioaccel_maxsg =
7976 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7977 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7978 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7979
e1f7de0c
MG		 7980 /* Command structures must be aligned on a 128-byte boundary
7981 * because the 7 lower bits of the address are used by the
7982 * hardware.
7983 */
e1f7de0c
MG		 7984 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7985 IOACCEL1_COMMANDLIST_ALIGNMENT);
7986 h->ioaccel_cmd_pool =
7987 pci_alloc_consistent(h->pdev,
7988 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7989 &(h->ioaccel_cmd_pool_dhandle));
7990
7991 h->ioaccel1_blockFetchTable =
283b4a9b 7992 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7993 sizeof(u32)), GFP_KERNEL);
7994
7995 if ((h->ioaccel_cmd_pool == NULL) ||
7996 (h->ioaccel1_blockFetchTable == NULL))
7997 goto clean_up;
7998
7999 memset(h->ioaccel_cmd_pool, 0,
8000 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8001 return 0;
8002
8003clean_up:
1fb7c98a 8004 hpsa_free_ioaccel1_cmd_and_bft(h);
e1f7de0c 8005 return 1;
6c311b57
SC		 8006}
8007
1fb7c98a
RE		 8008/* Free ioaccel2 mode command blocks and block fetch table */
8009static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8010{
d9a729f3
WS		 8011 hpsa_free_ioaccel2_sg_chain_blocks(h);
8012
1fb7c98a
RE		 8013 if (h->ioaccel2_cmd_pool)
8014 pci_free_consistent(h->pdev,
8015 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8016 h->ioaccel2_cmd_pool,
8017 h->ioaccel2_cmd_pool_dhandle);
8018 kfree(h->ioaccel2_blockFetchTable);
8019}
8020
d37ffbe4
RE		 8021/* Allocate ioaccel2 mode command blocks and block fetch table */
8022static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8023{
d9a729f3
WS		 8024 int rc;
8025
aca9012a
SC		 8026 /* Allocate ioaccel2 mode command blocks and block fetch table */
8027
8028 h->ioaccel_maxsg =
8029 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8030 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8031 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8032
aca9012a
SC		 8033 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8034 IOACCEL2_COMMANDLIST_ALIGNMENT);
8035 h->ioaccel2_cmd_pool =
8036 pci_alloc_consistent(h->pdev,
8037 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8038 &(h->ioaccel2_cmd_pool_dhandle));
8039
8040 h->ioaccel2_blockFetchTable =
8041 kmalloc(((h->ioaccel_maxsg + 1) *
8042 sizeof(u32)), GFP_KERNEL);
8043
8044 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8045 (h->ioaccel2_blockFetchTable == NULL)) {
8046 rc = -ENOMEM;
8047 goto clean_up;
8048 }
8049
8050 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8051 if (rc)
aca9012a
SC		 8052 goto clean_up;
8053
8054 memset(h->ioaccel2_cmd_pool, 0,
8055 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8056 return 0;
8057
8058clean_up:
1fb7c98a 8059 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8060 return rc;
aca9012a
SC		 8061}
8062
6f039790 8063static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8064{
8065 u32 trans_support;
e1f7de0c
MG		 8066 unsigned long transMethod = CFGTBL_Trans_Performant |
8067 CFGTBL_Trans_use_short_tags;
254f796b 8068 int i;
6c311b57 8069
02ec19c8
SC		 8070 if (hpsa_simple_mode)
8071 return;
8072
67c99a72 8073 trans_support = readl(&(h->cfgtable->TransportSupport));
8074 if (!(trans_support & PERFORMANT_MODE))
8075 return;
8076
e1f7de0c
MG		 8077 /* Check for I/O accelerator mode support */
8078 if (trans_support & CFGTBL_Trans_io_accel1) {
8079 transMethod |= CFGTBL_Trans_io_accel1 |
8080 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 8081 if (hpsa_alloc_ioaccel1_cmd_and_bft(h))
e1f7de0c 8082 goto clean_up;
aca9012a
SC		 8083 } else {
8084 if (trans_support & CFGTBL_Trans_io_accel2) {
8085 transMethod |= CFGTBL_Trans_io_accel2 |
8086 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 8087 if (hpsa_alloc_ioaccel2_cmd_and_bft(h))
aca9012a
SC		 8088 goto clean_up;
8089 }
e1f7de0c
MG		 8090 }
8091
eee0f03a 8092 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8093 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8094 /* Performant mode ring buffer and supporting data structures */
072b0518 8095 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8096
254f796b 8097 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8098 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8099 h->reply_queue_size,
8100 &(h->reply_queue[i].busaddr));
8101 if (!h->reply_queue[i].head)
8102 goto clean_up;
254f796b
MG		 8103 h->reply_queue[i].size = h->max_commands;
8104 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8105 h->reply_queue[i].current_entry = 0;
8106 }
8107
6c311b57 8108 /* Need a block fetch table for performant mode */
d66ae08b 8109 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8110 sizeof(u32)), GFP_KERNEL);
072b0518 8111 if (!h->blockFetchTable)
6c311b57
SC		 8112 goto clean_up;
8113
e1f7de0c 8114 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 8115 return;
8116
8117clean_up:
072b0518 8118 hpsa_free_reply_queues(h);
303932fd
DB		 8119 kfree(h->blockFetchTable);
8120}
8121
23100dd9 8122static int is_accelerated_cmd(struct CommandList *c)
76438d08 8123{
23100dd9
SC		 8124 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8125}
8126
8127static void hpsa_drain_accel_commands(struct ctlr_info *h)
8128{
8129 struct CommandList *c = NULL;
f2405db8 8130 int i, accel_cmds_out;
281a7fd0 8131 int refcount;
76438d08 8132
f2405db8 8133 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8134 accel_cmds_out = 0;
f2405db8 8135 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8136 c = h->cmd_pool + i;
281a7fd0
WS		 8137 refcount = atomic_inc_return(&c->refcount);
8138 if (refcount > 1) /* Command is allocated */
8139 accel_cmds_out += is_accelerated_cmd(c);
8140 cmd_free(h, c);
f2405db8 8141 }
23100dd9 8142 if (accel_cmds_out <= 0)
281a7fd0 8143 break;
76438d08
SC		 8144 msleep(100);
8145 } while (1);
8146}
8147
edd16368
SC		 8148/*
8149 * This is it. Register the PCI driver information for the cards we control
8150 * the OS will call our registered routines when it finds one of our cards.
8151 */
8152static int __init hpsa_init(void)
8153{
31468401 8154 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8155}
8156
8157static void __exit hpsa_cleanup(void)
8158{
8159 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8160}
8161
e1f7de0c
MG		 8162static void __attribute__((unused)) verify_offsets(void)
8163{
dd0e19f3
ST		 8164#define VERIFY_OFFSET(member, offset) \
8165 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8166
8167 VERIFY_OFFSET(structure_size, 0);
8168 VERIFY_OFFSET(volume_blk_size, 4);
8169 VERIFY_OFFSET(volume_blk_cnt, 8);
8170 VERIFY_OFFSET(phys_blk_shift, 16);
8171 VERIFY_OFFSET(parity_rotation_shift, 17);
8172 VERIFY_OFFSET(strip_size, 18);
8173 VERIFY_OFFSET(disk_starting_blk, 20);
8174 VERIFY_OFFSET(disk_blk_cnt, 28);
8175 VERIFY_OFFSET(data_disks_per_row, 36);
8176 VERIFY_OFFSET(metadata_disks_per_row, 38);
8177 VERIFY_OFFSET(row_cnt, 40);
8178 VERIFY_OFFSET(layout_map_count, 42);
8179 VERIFY_OFFSET(flags, 44);
8180 VERIFY_OFFSET(dekindex, 46);
8181 /* VERIFY_OFFSET(reserved, 48 */
8182 VERIFY_OFFSET(data, 64);
8183
8184#undef VERIFY_OFFSET
8185
b66cc250
MM		 8186#define VERIFY_OFFSET(member, offset) \
8187 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8188
8189 VERIFY_OFFSET(IU_type, 0);
8190 VERIFY_OFFSET(direction, 1);
8191 VERIFY_OFFSET(reply_queue, 2);
8192 /* VERIFY_OFFSET(reserved1, 3); */
8193 VERIFY_OFFSET(scsi_nexus, 4);
8194 VERIFY_OFFSET(Tag, 8);
8195 VERIFY_OFFSET(cdb, 16);
8196 VERIFY_OFFSET(cciss_lun, 32);
8197 VERIFY_OFFSET(data_len, 40);
8198 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8199 VERIFY_OFFSET(sg_count, 45);
8200 /* VERIFY_OFFSET(reserved3 */
8201 VERIFY_OFFSET(err_ptr, 48);
8202 VERIFY_OFFSET(err_len, 56);
8203 /* VERIFY_OFFSET(reserved4 */
8204 VERIFY_OFFSET(sg, 64);
8205
8206#undef VERIFY_OFFSET
8207
e1f7de0c
MG		 8208#define VERIFY_OFFSET(member, offset) \
8209 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8210
8211 VERIFY_OFFSET(dev_handle, 0x00);
8212 VERIFY_OFFSET(reserved1, 0x02);
8213 VERIFY_OFFSET(function, 0x03);
8214 VERIFY_OFFSET(reserved2, 0x04);
8215 VERIFY_OFFSET(err_info, 0x0C);
8216 VERIFY_OFFSET(reserved3, 0x10);
8217 VERIFY_OFFSET(err_info_len, 0x12);
8218 VERIFY_OFFSET(reserved4, 0x13);
8219 VERIFY_OFFSET(sgl_offset, 0x14);
8220 VERIFY_OFFSET(reserved5, 0x15);
8221 VERIFY_OFFSET(transfer_len, 0x1C);
8222 VERIFY_OFFSET(reserved6, 0x20);
8223 VERIFY_OFFSET(io_flags, 0x24);
8224 VERIFY_OFFSET(reserved7, 0x26);
8225 VERIFY_OFFSET(LUN, 0x34);
8226 VERIFY_OFFSET(control, 0x3C);
8227 VERIFY_OFFSET(CDB, 0x40);
8228 VERIFY_OFFSET(reserved8, 0x50);
8229 VERIFY_OFFSET(host_context_flags, 0x60);
8230 VERIFY_OFFSET(timeout_sec, 0x62);
8231 VERIFY_OFFSET(ReplyQueue, 0x64);
8232 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8233 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8234 VERIFY_OFFSET(host_addr, 0x70);
8235 VERIFY_OFFSET(CISS_LUN, 0x78);
8236 VERIFY_OFFSET(SG, 0x78 + 8);
8237#undef VERIFY_OFFSET
8238}
8239
edd16368
SC		 8240module_init(hpsa_init);
8241module_exit(hpsa_cleanup);
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