]>
Commit | Line | Data |
---|---|---|
edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
94c7bc31 | 3 | * Copyright 2016 Microsemi Corporation |
1358f6dc DB |
4 | * Copyright 2014-2015 PMC-Sierra, Inc. |
5 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
14 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
15 | * | |
94c7bc31 | 16 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
edd16368 SC |
17 | * |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
e5a44df8 | 24 | #include <linux/pci-aspm.h> |
edd16368 SC |
25 | #include <linux/kernel.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/timer.h> | |
edd16368 SC |
30 | #include <linux/init.h> |
31 | #include <linux/spinlock.h> | |
edd16368 SC |
32 | #include <linux/compat.h> |
33 | #include <linux/blktrace_api.h> | |
34 | #include <linux/uaccess.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/moduleparam.h> | |
39 | #include <scsi/scsi.h> | |
40 | #include <scsi/scsi_cmnd.h> | |
41 | #include <scsi/scsi_device.h> | |
42 | #include <scsi/scsi_host.h> | |
667e23d4 | 43 | #include <scsi/scsi_tcq.h> |
9437ac43 | 44 | #include <scsi/scsi_eh.h> |
d04e62b9 | 45 | #include <scsi/scsi_transport_sas.h> |
73153fe5 | 46 | #include <scsi/scsi_dbg.h> |
edd16368 SC |
47 | #include <linux/cciss_ioctl.h> |
48 | #include <linux/string.h> | |
49 | #include <linux/bitmap.h> | |
60063497 | 50 | #include <linux/atomic.h> |
a0c12413 | 51 | #include <linux/jiffies.h> |
42a91641 | 52 | #include <linux/percpu-defs.h> |
094963da | 53 | #include <linux/percpu.h> |
2b08b3e9 | 54 | #include <asm/unaligned.h> |
283b4a9b | 55 | #include <asm/div64.h> |
edd16368 SC |
56 | #include "hpsa_cmd.h" |
57 | #include "hpsa.h" | |
58 | ||
ec2c3aa9 DB |
59 | /* |
60 | * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' | |
61 | * with an optional trailing '-' followed by a byte value (0-255). | |
62 | */ | |
63 | #define HPSA_DRIVER_VERSION "3.4.14-0" | |
edd16368 | 64 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 65 | #define HPSA "hpsa" |
edd16368 | 66 | |
007e7aa9 RE |
67 | /* How long to wait for CISS doorbell communication */ |
68 | #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ | |
69 | #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ | |
70 | #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ | |
71 | #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ | |
edd16368 SC |
72 | #define MAX_IOCTL_CONFIG_WAIT 1000 |
73 | ||
74 | /*define how many times we will try a command because of bus resets */ | |
75 | #define MAX_CMD_RETRIES 3 | |
76 | ||
77 | /* Embedded module documentation macros - see modules.h */ | |
78 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
79 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
80 | HPSA_DRIVER_VERSION); | |
81 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
82 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
83 | MODULE_LICENSE("GPL"); | |
84 | ||
85 | static int hpsa_allow_any; | |
86 | module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR); | |
87 | MODULE_PARM_DESC(hpsa_allow_any, | |
88 | "Allow hpsa driver to access unknown HP Smart Array hardware"); | |
02ec19c8 SC |
89 | static int hpsa_simple_mode; |
90 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
91 | MODULE_PARM_DESC(hpsa_simple_mode, | |
92 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
93 | |
94 | /* define the PCI info for the cards we can control */ | |
95 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
fe0c9610 MM |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
fe0c9610 MM |
115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
121 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
122 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
123 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
124 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
125 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
126 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
3b7a45e5 | 127 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, |
97b9f53d MM |
128 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, |
129 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
130 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
3b7a45e5 JH |
131 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, |
132 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, | |
133 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, | |
134 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, | |
135 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, | |
fdfa4b6d | 136 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, |
cbb47dcb DB |
137 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, |
138 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, | |
139 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, | |
140 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, | |
141 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, | |
8e616a5e SC |
142 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, |
143 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, | |
144 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, | |
145 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, | |
146 | {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, | |
7c03b870 | 147 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 148 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
edd16368 SC |
149 | {0,} |
150 | }; | |
151 | ||
152 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
153 | ||
154 | /* board_id = Subsystem Device ID & Vendor ID | |
155 | * product = Marketing Name for the board | |
156 | * access = Address of the struct of function pointers | |
157 | */ | |
158 | static struct board_type products[] = { | |
edd16368 SC |
159 | {0x3241103C, "Smart Array P212", &SA5_access}, |
160 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
161 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
162 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
163 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
164 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
165 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
7d2cce58 | 166 | {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ |
fe0c9610 MM |
167 | {0x3350103C, "Smart Array P222", &SA5_access}, |
168 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
169 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
170 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
171 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
172 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
173 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
1fd6c8e3 MM |
174 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
175 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
176 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
177 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
178 | {0x1926103C, "Smart Array P731m", &SA5_access}, | |
179 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
180 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
27fb8137 DB |
181 | {0x21BD103C, "Smart Array P244br", &SA5_access}, |
182 | {0x21BE103C, "Smart Array P741m", &SA5_access}, | |
183 | {0x21BF103C, "Smart HBA H240ar", &SA5_access}, | |
184 | {0x21C0103C, "Smart Array P440ar", &SA5_access}, | |
c8ae0ab1 | 185 | {0x21C1103C, "Smart Array P840ar", &SA5_access}, |
27fb8137 DB |
186 | {0x21C2103C, "Smart Array P440", &SA5_access}, |
187 | {0x21C3103C, "Smart Array P441", &SA5_access}, | |
97b9f53d | 188 | {0x21C4103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
189 | {0x21C5103C, "Smart Array P841", &SA5_access}, |
190 | {0x21C6103C, "Smart HBA H244br", &SA5_access}, | |
191 | {0x21C7103C, "Smart HBA H240", &SA5_access}, | |
192 | {0x21C8103C, "Smart HBA H241", &SA5_access}, | |
97b9f53d | 193 | {0x21C9103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
194 | {0x21CA103C, "Smart Array P246br", &SA5_access}, |
195 | {0x21CB103C, "Smart Array P840", &SA5_access}, | |
3b7a45e5 JH |
196 | {0x21CC103C, "Smart Array", &SA5_access}, |
197 | {0x21CD103C, "Smart Array", &SA5_access}, | |
27fb8137 | 198 | {0x21CE103C, "Smart HBA", &SA5_access}, |
fdfa4b6d | 199 | {0x05809005, "SmartHBA-SA", &SA5_access}, |
cbb47dcb DB |
200 | {0x05819005, "SmartHBA-SA 8i", &SA5_access}, |
201 | {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, | |
202 | {0x05839005, "SmartHBA-SA 8e", &SA5_access}, | |
203 | {0x05849005, "SmartHBA-SA 16i", &SA5_access}, | |
204 | {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, | |
8e616a5e SC |
205 | {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, |
206 | {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, | |
207 | {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, | |
208 | {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, | |
209 | {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, | |
edd16368 SC |
210 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
211 | }; | |
212 | ||
d04e62b9 KB |
213 | static struct scsi_transport_template *hpsa_sas_transport_template; |
214 | static int hpsa_add_sas_host(struct ctlr_info *h); | |
215 | static void hpsa_delete_sas_host(struct ctlr_info *h); | |
216 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
217 | struct hpsa_scsi_dev_t *device); | |
218 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); | |
219 | static struct hpsa_scsi_dev_t | |
220 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
221 | struct sas_rphy *rphy); | |
222 | ||
a58e7e53 WS |
223 | #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) |
224 | static const struct scsi_cmnd hpsa_cmd_busy; | |
225 | #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) | |
226 | static const struct scsi_cmnd hpsa_cmd_idle; | |
edd16368 SC |
227 | static int number_of_controllers; |
228 | ||
10f66018 SC |
229 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
230 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
42a91641 | 231 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg); |
edd16368 SC |
232 | |
233 | #ifdef CONFIG_COMPAT | |
42a91641 DB |
234 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, |
235 | void __user *arg); | |
edd16368 SC |
236 | #endif |
237 | ||
238 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
edd16368 | 239 | static struct CommandList *cmd_alloc(struct ctlr_info *h); |
73153fe5 WS |
240 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); |
241 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
242 | struct scsi_cmnd *scmd); | |
a2dac136 | 243 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 244 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 | 245 | int cmd_type); |
2c143342 | 246 | static void hpsa_free_cmd_pool(struct ctlr_info *h); |
b7bb24eb | 247 | #define VPD_PAGE (1 << 8) |
b48d9804 | 248 | #define HPSA_SIMPLE_ERROR_BITS 0x03 |
edd16368 | 249 | |
f281233d | 250 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
251 | static void hpsa_scan_start(struct Scsi_Host *); |
252 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
253 | unsigned long elapsed_time); | |
7c0a0229 | 254 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); |
edd16368 SC |
255 | |
256 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
75167d2c | 257 | static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd); |
edd16368 | 258 | static int hpsa_slave_alloc(struct scsi_device *sdev); |
41ce4c35 | 259 | static int hpsa_slave_configure(struct scsi_device *sdev); |
edd16368 SC |
260 | static void hpsa_slave_destroy(struct scsi_device *sdev); |
261 | ||
8aa60681 | 262 | static void hpsa_update_scsi_devices(struct ctlr_info *h); |
edd16368 SC |
263 | static int check_for_unit_attention(struct ctlr_info *h, |
264 | struct CommandList *c); | |
265 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
266 | struct CommandList *c); | |
303932fd DB |
267 | /* performant mode helper functions */ |
268 | static void calc_bucket_map(int *bucket, int num_buckets, | |
2b08b3e9 | 269 | int nsgs, int min_blocks, u32 *bucket_map); |
105a3dbc RE |
270 | static void hpsa_free_performant_mode(struct ctlr_info *h); |
271 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); | |
254f796b | 272 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
273 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
274 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
275 | u64 *cfg_offset); | |
276 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
277 | unsigned long *memory_bar); | |
278 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id); | |
279 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, | |
280 | int wait_for_ready); | |
75167d2c | 281 | static inline void finish_cmd(struct CommandList *c); |
c706a795 | 282 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); |
fe5389c8 SC |
283 | #define BOARD_NOT_READY 0 |
284 | #define BOARD_READY 1 | |
23100dd9 | 285 | static void hpsa_drain_accel_commands(struct ctlr_info *h); |
76438d08 | 286 | static void hpsa_flush_cache(struct ctlr_info *h); |
c349775e ST |
287 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, |
288 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 289 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); |
080ef1cc | 290 | static void hpsa_command_resubmit_worker(struct work_struct *work); |
25163bd5 WS |
291 | static u32 lockup_detected(struct ctlr_info *h); |
292 | static int detect_controller_lockup(struct ctlr_info *h); | |
c2adae44 | 293 | static void hpsa_disable_rld_caching(struct ctlr_info *h); |
d04e62b9 KB |
294 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, |
295 | struct ReportExtendedLUNdata *buf, int bufsize); | |
34592254 | 296 | static int hpsa_luns_changed(struct ctlr_info *h); |
edd16368 | 297 | |
edd16368 SC |
298 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
299 | { | |
300 | unsigned long *priv = shost_priv(sdev->host); | |
301 | return (struct ctlr_info *) *priv; | |
302 | } | |
303 | ||
a23513e8 SC |
304 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
305 | { | |
306 | unsigned long *priv = shost_priv(sh); | |
307 | return (struct ctlr_info *) *priv; | |
308 | } | |
309 | ||
a58e7e53 WS |
310 | static inline bool hpsa_is_cmd_idle(struct CommandList *c) |
311 | { | |
312 | return c->scsi_cmd == SCSI_CMD_IDLE; | |
313 | } | |
314 | ||
d604f533 WS |
315 | static inline bool hpsa_is_pending_event(struct CommandList *c) |
316 | { | |
317 | return c->abort_pending || c->reset_pending; | |
318 | } | |
319 | ||
9437ac43 SC |
320 | /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ |
321 | static void decode_sense_data(const u8 *sense_data, int sense_data_len, | |
322 | u8 *sense_key, u8 *asc, u8 *ascq) | |
323 | { | |
324 | struct scsi_sense_hdr sshdr; | |
325 | bool rc; | |
326 | ||
327 | *sense_key = -1; | |
328 | *asc = -1; | |
329 | *ascq = -1; | |
330 | ||
331 | if (sense_data_len < 1) | |
332 | return; | |
333 | ||
334 | rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); | |
335 | if (rc) { | |
336 | *sense_key = sshdr.sense_key; | |
337 | *asc = sshdr.asc; | |
338 | *ascq = sshdr.ascq; | |
339 | } | |
340 | } | |
341 | ||
edd16368 SC |
342 | static int check_for_unit_attention(struct ctlr_info *h, |
343 | struct CommandList *c) | |
344 | { | |
9437ac43 SC |
345 | u8 sense_key, asc, ascq; |
346 | int sense_len; | |
347 | ||
348 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) | |
349 | sense_len = sizeof(c->err_info->SenseInfo); | |
350 | else | |
351 | sense_len = c->err_info->SenseLen; | |
352 | ||
353 | decode_sense_data(c->err_info->SenseInfo, sense_len, | |
354 | &sense_key, &asc, &ascq); | |
81c27557 | 355 | if (sense_key != UNIT_ATTENTION || asc == 0xff) |
edd16368 SC |
356 | return 0; |
357 | ||
9437ac43 | 358 | switch (asc) { |
edd16368 | 359 | case STATE_CHANGED: |
9437ac43 | 360 | dev_warn(&h->pdev->dev, |
2946e82b RE |
361 | "%s: a state change detected, command retried\n", |
362 | h->devname); | |
edd16368 SC |
363 | break; |
364 | case LUN_FAILED: | |
7f73695a | 365 | dev_warn(&h->pdev->dev, |
2946e82b | 366 | "%s: LUN failure detected\n", h->devname); |
edd16368 SC |
367 | break; |
368 | case REPORT_LUNS_CHANGED: | |
7f73695a | 369 | dev_warn(&h->pdev->dev, |
2946e82b | 370 | "%s: report LUN data changed\n", h->devname); |
edd16368 | 371 | /* |
4f4eb9f1 ST |
372 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
373 | * target (array) devices. | |
edd16368 SC |
374 | */ |
375 | break; | |
376 | case POWER_OR_RESET: | |
2946e82b RE |
377 | dev_warn(&h->pdev->dev, |
378 | "%s: a power on or device reset detected\n", | |
379 | h->devname); | |
edd16368 SC |
380 | break; |
381 | case UNIT_ATTENTION_CLEARED: | |
2946e82b RE |
382 | dev_warn(&h->pdev->dev, |
383 | "%s: unit attention cleared by another initiator\n", | |
384 | h->devname); | |
edd16368 SC |
385 | break; |
386 | default: | |
2946e82b RE |
387 | dev_warn(&h->pdev->dev, |
388 | "%s: unknown unit attention detected\n", | |
389 | h->devname); | |
edd16368 SC |
390 | break; |
391 | } | |
392 | return 1; | |
393 | } | |
394 | ||
852af20a MB |
395 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
396 | { | |
397 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
398 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
399 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
400 | return 0; | |
401 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
402 | return 1; | |
403 | } | |
404 | ||
e985c58f SC |
405 | static u32 lockup_detected(struct ctlr_info *h); |
406 | static ssize_t host_show_lockup_detected(struct device *dev, | |
407 | struct device_attribute *attr, char *buf) | |
408 | { | |
409 | int ld; | |
410 | struct ctlr_info *h; | |
411 | struct Scsi_Host *shost = class_to_shost(dev); | |
412 | ||
413 | h = shost_to_hba(shost); | |
414 | ld = lockup_detected(h); | |
415 | ||
416 | return sprintf(buf, "ld=%d\n", ld); | |
417 | } | |
418 | ||
da0697bd ST |
419 | static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, |
420 | struct device_attribute *attr, | |
421 | const char *buf, size_t count) | |
422 | { | |
423 | int status, len; | |
424 | struct ctlr_info *h; | |
425 | struct Scsi_Host *shost = class_to_shost(dev); | |
426 | char tmpbuf[10]; | |
427 | ||
428 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
429 | return -EACCES; | |
430 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
431 | strncpy(tmpbuf, buf, len); | |
432 | tmpbuf[len] = '\0'; | |
433 | if (sscanf(tmpbuf, "%d", &status) != 1) | |
434 | return -EINVAL; | |
435 | h = shost_to_hba(shost); | |
436 | h->acciopath_status = !!status; | |
437 | dev_warn(&h->pdev->dev, | |
438 | "hpsa: HP SSD Smart Path %s via sysfs update.\n", | |
439 | h->acciopath_status ? "enabled" : "disabled"); | |
440 | return count; | |
441 | } | |
442 | ||
2ba8bfc8 SC |
443 | static ssize_t host_store_raid_offload_debug(struct device *dev, |
444 | struct device_attribute *attr, | |
445 | const char *buf, size_t count) | |
446 | { | |
447 | int debug_level, len; | |
448 | struct ctlr_info *h; | |
449 | struct Scsi_Host *shost = class_to_shost(dev); | |
450 | char tmpbuf[10]; | |
451 | ||
452 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
453 | return -EACCES; | |
454 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
455 | strncpy(tmpbuf, buf, len); | |
456 | tmpbuf[len] = '\0'; | |
457 | if (sscanf(tmpbuf, "%d", &debug_level) != 1) | |
458 | return -EINVAL; | |
459 | if (debug_level < 0) | |
460 | debug_level = 0; | |
461 | h = shost_to_hba(shost); | |
462 | h->raid_offload_debug = debug_level; | |
463 | dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", | |
464 | h->raid_offload_debug); | |
465 | return count; | |
466 | } | |
467 | ||
edd16368 SC |
468 | static ssize_t host_store_rescan(struct device *dev, |
469 | struct device_attribute *attr, | |
470 | const char *buf, size_t count) | |
471 | { | |
472 | struct ctlr_info *h; | |
473 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 474 | h = shost_to_hba(shost); |
31468401 | 475 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
476 | return count; |
477 | } | |
478 | ||
d28ce020 SC |
479 | static ssize_t host_show_firmware_revision(struct device *dev, |
480 | struct device_attribute *attr, char *buf) | |
481 | { | |
482 | struct ctlr_info *h; | |
483 | struct Scsi_Host *shost = class_to_shost(dev); | |
484 | unsigned char *fwrev; | |
485 | ||
486 | h = shost_to_hba(shost); | |
487 | if (!h->hba_inquiry_data) | |
488 | return 0; | |
489 | fwrev = &h->hba_inquiry_data[32]; | |
490 | return snprintf(buf, 20, "%c%c%c%c\n", | |
491 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
492 | } | |
493 | ||
94a13649 SC |
494 | static ssize_t host_show_commands_outstanding(struct device *dev, |
495 | struct device_attribute *attr, char *buf) | |
496 | { | |
497 | struct Scsi_Host *shost = class_to_shost(dev); | |
498 | struct ctlr_info *h = shost_to_hba(shost); | |
499 | ||
0cbf768e SC |
500 | return snprintf(buf, 20, "%d\n", |
501 | atomic_read(&h->commands_outstanding)); | |
94a13649 SC |
502 | } |
503 | ||
745a7a25 SC |
504 | static ssize_t host_show_transport_mode(struct device *dev, |
505 | struct device_attribute *attr, char *buf) | |
506 | { | |
507 | struct ctlr_info *h; | |
508 | struct Scsi_Host *shost = class_to_shost(dev); | |
509 | ||
510 | h = shost_to_hba(shost); | |
511 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 512 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
513 | "performant" : "simple"); |
514 | } | |
515 | ||
da0697bd ST |
516 | static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, |
517 | struct device_attribute *attr, char *buf) | |
518 | { | |
519 | struct ctlr_info *h; | |
520 | struct Scsi_Host *shost = class_to_shost(dev); | |
521 | ||
522 | h = shost_to_hba(shost); | |
523 | return snprintf(buf, 30, "HP SSD Smart Path %s\n", | |
524 | (h->acciopath_status == 1) ? "enabled" : "disabled"); | |
525 | } | |
526 | ||
46380786 | 527 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
528 | static u32 unresettable_controller[] = { |
529 | 0x324a103C, /* Smart Array P712m */ | |
9b5c48c2 | 530 | 0x324b103C, /* Smart Array P711m */ |
941b1cda SC |
531 | 0x3223103C, /* Smart Array P800 */ |
532 | 0x3234103C, /* Smart Array P400 */ | |
533 | 0x3235103C, /* Smart Array P400i */ | |
534 | 0x3211103C, /* Smart Array E200i */ | |
535 | 0x3212103C, /* Smart Array E200 */ | |
536 | 0x3213103C, /* Smart Array E200i */ | |
537 | 0x3214103C, /* Smart Array E200i */ | |
538 | 0x3215103C, /* Smart Array E200i */ | |
539 | 0x3237103C, /* Smart Array E500 */ | |
540 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 541 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
542 | 0x409C0E11, /* Smart Array 6400 */ |
543 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
544 | 0x40700E11, /* Smart Array 5300 */ |
545 | 0x40820E11, /* Smart Array 532 */ | |
546 | 0x40830E11, /* Smart Array 5312 */ | |
547 | 0x409A0E11, /* Smart Array 641 */ | |
548 | 0x409B0E11, /* Smart Array 642 */ | |
549 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
550 | }; |
551 | ||
46380786 SC |
552 | /* List of controllers which cannot even be soft reset */ |
553 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 554 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
555 | 0x40700E11, /* Smart Array 5300 */ |
556 | 0x40820E11, /* Smart Array 532 */ | |
557 | 0x40830E11, /* Smart Array 5312 */ | |
558 | 0x409A0E11, /* Smart Array 641 */ | |
559 | 0x409B0E11, /* Smart Array 642 */ | |
560 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
561 | /* Exclude 640x boards. These are two pci devices in one slot |
562 | * which share a battery backed cache module. One controls the | |
563 | * cache, the other accesses the cache through the one that controls | |
564 | * it. If we reset the one controlling the cache, the other will | |
565 | * likely not be happy. Just forbid resetting this conjoined mess. | |
566 | * The 640x isn't really supported by hpsa anyway. | |
567 | */ | |
568 | 0x409C0E11, /* Smart Array 6400 */ | |
569 | 0x409D0E11, /* Smart Array 6400 EM */ | |
570 | }; | |
571 | ||
9b5c48c2 SC |
572 | static u32 needs_abort_tags_swizzled[] = { |
573 | 0x323D103C, /* Smart Array P700m */ | |
574 | 0x324a103C, /* Smart Array P712m */ | |
575 | 0x324b103C, /* SmartArray P711m */ | |
576 | }; | |
577 | ||
578 | static int board_id_in_array(u32 a[], int nelems, u32 board_id) | |
941b1cda SC |
579 | { |
580 | int i; | |
581 | ||
9b5c48c2 SC |
582 | for (i = 0; i < nelems; i++) |
583 | if (a[i] == board_id) | |
584 | return 1; | |
585 | return 0; | |
46380786 SC |
586 | } |
587 | ||
9b5c48c2 | 588 | static int ctlr_is_hard_resettable(u32 board_id) |
46380786 | 589 | { |
9b5c48c2 SC |
590 | return !board_id_in_array(unresettable_controller, |
591 | ARRAY_SIZE(unresettable_controller), board_id); | |
592 | } | |
46380786 | 593 | |
9b5c48c2 SC |
594 | static int ctlr_is_soft_resettable(u32 board_id) |
595 | { | |
596 | return !board_id_in_array(soft_unresettable_controller, | |
597 | ARRAY_SIZE(soft_unresettable_controller), board_id); | |
941b1cda SC |
598 | } |
599 | ||
46380786 SC |
600 | static int ctlr_is_resettable(u32 board_id) |
601 | { | |
602 | return ctlr_is_hard_resettable(board_id) || | |
603 | ctlr_is_soft_resettable(board_id); | |
604 | } | |
605 | ||
9b5c48c2 SC |
606 | static int ctlr_needs_abort_tags_swizzled(u32 board_id) |
607 | { | |
608 | return board_id_in_array(needs_abort_tags_swizzled, | |
609 | ARRAY_SIZE(needs_abort_tags_swizzled), board_id); | |
610 | } | |
611 | ||
941b1cda SC |
612 | static ssize_t host_show_resettable(struct device *dev, |
613 | struct device_attribute *attr, char *buf) | |
614 | { | |
615 | struct ctlr_info *h; | |
616 | struct Scsi_Host *shost = class_to_shost(dev); | |
617 | ||
618 | h = shost_to_hba(shost); | |
46380786 | 619 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
620 | } |
621 | ||
edd16368 SC |
622 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
623 | { | |
624 | return (scsi3addr[3] & 0xC0) == 0x40; | |
625 | } | |
626 | ||
f2ef0ce7 | 627 | static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", |
7c59a0d4 | 628 | "1(+0)ADM", "UNKNOWN", "PHYS DRV" |
edd16368 | 629 | }; |
6b80b18f ST |
630 | #define HPSA_RAID_0 0 |
631 | #define HPSA_RAID_4 1 | |
632 | #define HPSA_RAID_1 2 /* also used for RAID 10 */ | |
633 | #define HPSA_RAID_5 3 /* also used for RAID 50 */ | |
634 | #define HPSA_RAID_51 4 | |
635 | #define HPSA_RAID_6 5 /* also used for RAID 60 */ | |
636 | #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ | |
7c59a0d4 DB |
637 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) |
638 | #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) | |
edd16368 | 639 | |
f3f01730 KB |
640 | static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) |
641 | { | |
642 | return !device->physical_device; | |
643 | } | |
edd16368 SC |
644 | |
645 | static ssize_t raid_level_show(struct device *dev, | |
646 | struct device_attribute *attr, char *buf) | |
647 | { | |
648 | ssize_t l = 0; | |
82a72c0a | 649 | unsigned char rlevel; |
edd16368 SC |
650 | struct ctlr_info *h; |
651 | struct scsi_device *sdev; | |
652 | struct hpsa_scsi_dev_t *hdev; | |
653 | unsigned long flags; | |
654 | ||
655 | sdev = to_scsi_device(dev); | |
656 | h = sdev_to_hba(sdev); | |
657 | spin_lock_irqsave(&h->lock, flags); | |
658 | hdev = sdev->hostdata; | |
659 | if (!hdev) { | |
660 | spin_unlock_irqrestore(&h->lock, flags); | |
661 | return -ENODEV; | |
662 | } | |
663 | ||
664 | /* Is this even a logical drive? */ | |
f3f01730 | 665 | if (!is_logical_device(hdev)) { |
edd16368 SC |
666 | spin_unlock_irqrestore(&h->lock, flags); |
667 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
668 | return l; | |
669 | } | |
670 | ||
671 | rlevel = hdev->raid_level; | |
672 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 673 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
674 | rlevel = RAID_UNKNOWN; |
675 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
676 | return l; | |
677 | } | |
678 | ||
679 | static ssize_t lunid_show(struct device *dev, | |
680 | struct device_attribute *attr, char *buf) | |
681 | { | |
682 | struct ctlr_info *h; | |
683 | struct scsi_device *sdev; | |
684 | struct hpsa_scsi_dev_t *hdev; | |
685 | unsigned long flags; | |
686 | unsigned char lunid[8]; | |
687 | ||
688 | sdev = to_scsi_device(dev); | |
689 | h = sdev_to_hba(sdev); | |
690 | spin_lock_irqsave(&h->lock, flags); | |
691 | hdev = sdev->hostdata; | |
692 | if (!hdev) { | |
693 | spin_unlock_irqrestore(&h->lock, flags); | |
694 | return -ENODEV; | |
695 | } | |
696 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
697 | spin_unlock_irqrestore(&h->lock, flags); | |
698 | return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
699 | lunid[0], lunid[1], lunid[2], lunid[3], | |
700 | lunid[4], lunid[5], lunid[6], lunid[7]); | |
701 | } | |
702 | ||
703 | static ssize_t unique_id_show(struct device *dev, | |
704 | struct device_attribute *attr, char *buf) | |
705 | { | |
706 | struct ctlr_info *h; | |
707 | struct scsi_device *sdev; | |
708 | struct hpsa_scsi_dev_t *hdev; | |
709 | unsigned long flags; | |
710 | unsigned char sn[16]; | |
711 | ||
712 | sdev = to_scsi_device(dev); | |
713 | h = sdev_to_hba(sdev); | |
714 | spin_lock_irqsave(&h->lock, flags); | |
715 | hdev = sdev->hostdata; | |
716 | if (!hdev) { | |
717 | spin_unlock_irqrestore(&h->lock, flags); | |
718 | return -ENODEV; | |
719 | } | |
720 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
721 | spin_unlock_irqrestore(&h->lock, flags); | |
722 | return snprintf(buf, 16 * 2 + 2, | |
723 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
724 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
725 | sn[0], sn[1], sn[2], sn[3], | |
726 | sn[4], sn[5], sn[6], sn[7], | |
727 | sn[8], sn[9], sn[10], sn[11], | |
728 | sn[12], sn[13], sn[14], sn[15]); | |
729 | } | |
730 | ||
ded1be4a JH |
731 | static ssize_t sas_address_show(struct device *dev, |
732 | struct device_attribute *attr, char *buf) | |
733 | { | |
734 | struct ctlr_info *h; | |
735 | struct scsi_device *sdev; | |
736 | struct hpsa_scsi_dev_t *hdev; | |
737 | unsigned long flags; | |
738 | u64 sas_address; | |
739 | ||
740 | sdev = to_scsi_device(dev); | |
741 | h = sdev_to_hba(sdev); | |
742 | spin_lock_irqsave(&h->lock, flags); | |
743 | hdev = sdev->hostdata; | |
744 | if (!hdev || is_logical_device(hdev) || !hdev->expose_device) { | |
745 | spin_unlock_irqrestore(&h->lock, flags); | |
746 | return -ENODEV; | |
747 | } | |
748 | sas_address = hdev->sas_address; | |
749 | spin_unlock_irqrestore(&h->lock, flags); | |
750 | ||
751 | return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address); | |
752 | } | |
753 | ||
c1988684 ST |
754 | static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, |
755 | struct device_attribute *attr, char *buf) | |
756 | { | |
757 | struct ctlr_info *h; | |
758 | struct scsi_device *sdev; | |
759 | struct hpsa_scsi_dev_t *hdev; | |
760 | unsigned long flags; | |
761 | int offload_enabled; | |
762 | ||
763 | sdev = to_scsi_device(dev); | |
764 | h = sdev_to_hba(sdev); | |
765 | spin_lock_irqsave(&h->lock, flags); | |
766 | hdev = sdev->hostdata; | |
767 | if (!hdev) { | |
768 | spin_unlock_irqrestore(&h->lock, flags); | |
769 | return -ENODEV; | |
770 | } | |
771 | offload_enabled = hdev->offload_enabled; | |
772 | spin_unlock_irqrestore(&h->lock, flags); | |
773 | return snprintf(buf, 20, "%d\n", offload_enabled); | |
774 | } | |
775 | ||
8270b862 | 776 | #define MAX_PATHS 8 |
8270b862 JH |
777 | static ssize_t path_info_show(struct device *dev, |
778 | struct device_attribute *attr, char *buf) | |
779 | { | |
780 | struct ctlr_info *h; | |
781 | struct scsi_device *sdev; | |
782 | struct hpsa_scsi_dev_t *hdev; | |
783 | unsigned long flags; | |
784 | int i; | |
785 | int output_len = 0; | |
786 | u8 box; | |
787 | u8 bay; | |
788 | u8 path_map_index = 0; | |
789 | char *active; | |
790 | unsigned char phys_connector[2]; | |
8270b862 | 791 | |
8270b862 JH |
792 | sdev = to_scsi_device(dev); |
793 | h = sdev_to_hba(sdev); | |
794 | spin_lock_irqsave(&h->devlock, flags); | |
795 | hdev = sdev->hostdata; | |
796 | if (!hdev) { | |
797 | spin_unlock_irqrestore(&h->devlock, flags); | |
798 | return -ENODEV; | |
799 | } | |
800 | ||
801 | bay = hdev->bay; | |
802 | for (i = 0; i < MAX_PATHS; i++) { | |
803 | path_map_index = 1<<i; | |
804 | if (i == hdev->active_path_index) | |
805 | active = "Active"; | |
806 | else if (hdev->path_map & path_map_index) | |
807 | active = "Inactive"; | |
808 | else | |
809 | continue; | |
810 | ||
1faf072c RV |
811 | output_len += scnprintf(buf + output_len, |
812 | PAGE_SIZE - output_len, | |
813 | "[%d:%d:%d:%d] %20.20s ", | |
8270b862 JH |
814 | h->scsi_host->host_no, |
815 | hdev->bus, hdev->target, hdev->lun, | |
816 | scsi_device_type(hdev->devtype)); | |
817 | ||
cca8f13b | 818 | if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) { |
2708f295 | 819 | output_len += scnprintf(buf + output_len, |
1faf072c RV |
820 | PAGE_SIZE - output_len, |
821 | "%s\n", active); | |
8270b862 JH |
822 | continue; |
823 | } | |
824 | ||
825 | box = hdev->box[i]; | |
826 | memcpy(&phys_connector, &hdev->phys_connector[i], | |
827 | sizeof(phys_connector)); | |
828 | if (phys_connector[0] < '0') | |
829 | phys_connector[0] = '0'; | |
830 | if (phys_connector[1] < '0') | |
831 | phys_connector[1] = '0'; | |
cca8f13b | 832 | output_len += scnprintf(buf + output_len, |
1faf072c | 833 | PAGE_SIZE - output_len, |
8270b862 JH |
834 | "PORT: %.2s ", |
835 | phys_connector); | |
af15ed36 DB |
836 | if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) && |
837 | hdev->expose_device) { | |
8270b862 | 838 | if (box == 0 || box == 0xFF) { |
2708f295 | 839 | output_len += scnprintf(buf + output_len, |
1faf072c | 840 | PAGE_SIZE - output_len, |
8270b862 JH |
841 | "BAY: %hhu %s\n", |
842 | bay, active); | |
843 | } else { | |
2708f295 | 844 | output_len += scnprintf(buf + output_len, |
1faf072c | 845 | PAGE_SIZE - output_len, |
8270b862 JH |
846 | "BOX: %hhu BAY: %hhu %s\n", |
847 | box, bay, active); | |
848 | } | |
849 | } else if (box != 0 && box != 0xFF) { | |
2708f295 | 850 | output_len += scnprintf(buf + output_len, |
1faf072c | 851 | PAGE_SIZE - output_len, "BOX: %hhu %s\n", |
8270b862 JH |
852 | box, active); |
853 | } else | |
2708f295 | 854 | output_len += scnprintf(buf + output_len, |
1faf072c | 855 | PAGE_SIZE - output_len, "%s\n", active); |
8270b862 JH |
856 | } |
857 | ||
858 | spin_unlock_irqrestore(&h->devlock, flags); | |
1faf072c | 859 | return output_len; |
8270b862 JH |
860 | } |
861 | ||
3f5eac3a SC |
862 | static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); |
863 | static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); | |
864 | static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); | |
865 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); | |
ded1be4a | 866 | static DEVICE_ATTR(sas_address, S_IRUGO, sas_address_show, NULL); |
c1988684 ST |
867 | static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, |
868 | host_show_hp_ssd_smart_path_enabled, NULL); | |
8270b862 | 869 | static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL); |
da0697bd ST |
870 | static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, |
871 | host_show_hp_ssd_smart_path_status, | |
872 | host_store_hp_ssd_smart_path_status); | |
2ba8bfc8 SC |
873 | static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, |
874 | host_store_raid_offload_debug); | |
3f5eac3a SC |
875 | static DEVICE_ATTR(firmware_revision, S_IRUGO, |
876 | host_show_firmware_revision, NULL); | |
877 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
878 | host_show_commands_outstanding, NULL); | |
879 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
880 | host_show_transport_mode, NULL); | |
941b1cda SC |
881 | static DEVICE_ATTR(resettable, S_IRUGO, |
882 | host_show_resettable, NULL); | |
e985c58f SC |
883 | static DEVICE_ATTR(lockup_detected, S_IRUGO, |
884 | host_show_lockup_detected, NULL); | |
3f5eac3a SC |
885 | |
886 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
887 | &dev_attr_raid_level, | |
888 | &dev_attr_lunid, | |
889 | &dev_attr_unique_id, | |
c1988684 | 890 | &dev_attr_hp_ssd_smart_path_enabled, |
8270b862 | 891 | &dev_attr_path_info, |
ded1be4a | 892 | &dev_attr_sas_address, |
3f5eac3a SC |
893 | NULL, |
894 | }; | |
895 | ||
896 | static struct device_attribute *hpsa_shost_attrs[] = { | |
897 | &dev_attr_rescan, | |
898 | &dev_attr_firmware_revision, | |
899 | &dev_attr_commands_outstanding, | |
900 | &dev_attr_transport_mode, | |
941b1cda | 901 | &dev_attr_resettable, |
da0697bd | 902 | &dev_attr_hp_ssd_smart_path_status, |
2ba8bfc8 | 903 | &dev_attr_raid_offload_debug, |
fb53c439 | 904 | &dev_attr_lockup_detected, |
3f5eac3a SC |
905 | NULL, |
906 | }; | |
907 | ||
41ce4c35 SC |
908 | #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \ |
909 | HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS) | |
910 | ||
3f5eac3a SC |
911 | static struct scsi_host_template hpsa_driver_template = { |
912 | .module = THIS_MODULE, | |
f79cfec6 SC |
913 | .name = HPSA, |
914 | .proc_name = HPSA, | |
3f5eac3a SC |
915 | .queuecommand = hpsa_scsi_queue_command, |
916 | .scan_start = hpsa_scan_start, | |
917 | .scan_finished = hpsa_scan_finished, | |
7c0a0229 | 918 | .change_queue_depth = hpsa_change_queue_depth, |
3f5eac3a SC |
919 | .this_id = -1, |
920 | .use_clustering = ENABLE_CLUSTERING, | |
75167d2c | 921 | .eh_abort_handler = hpsa_eh_abort_handler, |
3f5eac3a SC |
922 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
923 | .ioctl = hpsa_ioctl, | |
924 | .slave_alloc = hpsa_slave_alloc, | |
41ce4c35 | 925 | .slave_configure = hpsa_slave_configure, |
3f5eac3a SC |
926 | .slave_destroy = hpsa_slave_destroy, |
927 | #ifdef CONFIG_COMPAT | |
928 | .compat_ioctl = hpsa_compat_ioctl, | |
929 | #endif | |
930 | .sdev_attrs = hpsa_sdev_attrs, | |
931 | .shost_attrs = hpsa_shost_attrs, | |
c0d6a4d1 | 932 | .max_sectors = 8192, |
54b2b50c | 933 | .no_write_same = 1, |
3f5eac3a SC |
934 | }; |
935 | ||
254f796b | 936 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
937 | { |
938 | u32 a; | |
072b0518 | 939 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
3f5eac3a | 940 | |
e1f7de0c MG |
941 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
942 | return h->access.command_completed(h, q); | |
943 | ||
3f5eac3a | 944 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 945 | return h->access.command_completed(h, q); |
3f5eac3a | 946 | |
254f796b MG |
947 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
948 | a = rq->head[rq->current_entry]; | |
949 | rq->current_entry++; | |
0cbf768e | 950 | atomic_dec(&h->commands_outstanding); |
3f5eac3a SC |
951 | } else { |
952 | a = FIFO_EMPTY; | |
953 | } | |
954 | /* Check for wraparound */ | |
254f796b MG |
955 | if (rq->current_entry == h->max_commands) { |
956 | rq->current_entry = 0; | |
957 | rq->wraparound ^= 1; | |
3f5eac3a SC |
958 | } |
959 | return a; | |
960 | } | |
961 | ||
c349775e ST |
962 | /* |
963 | * There are some special bits in the bus address of the | |
964 | * command that we have to set for the controller to know | |
965 | * how to process the command: | |
966 | * | |
967 | * Normal performant mode: | |
968 | * bit 0: 1 means performant mode, 0 means simple mode. | |
969 | * bits 1-3 = block fetch table entry | |
970 | * bits 4-6 = command type (== 0) | |
971 | * | |
972 | * ioaccel1 mode: | |
973 | * bit 0 = "performant mode" bit. | |
974 | * bits 1-3 = block fetch table entry | |
975 | * bits 4-6 = command type (== 110) | |
976 | * (command type is needed because ioaccel1 mode | |
977 | * commands are submitted through the same register as normal | |
978 | * mode commands, so this is how the controller knows whether | |
979 | * the command is normal mode or ioaccel1 mode.) | |
980 | * | |
981 | * ioaccel2 mode: | |
982 | * bit 0 = "performant mode" bit. | |
983 | * bits 1-4 = block fetch table entry (note extra bit) | |
984 | * bits 4-6 = not needed, because ioaccel2 mode has | |
985 | * a separate special register for submitting commands. | |
986 | */ | |
987 | ||
25163bd5 WS |
988 | /* |
989 | * set_performant_mode: Modify the tag for cciss performant | |
3f5eac3a SC |
990 | * set bit 0 for pull model, bits 3-1 for block fetch |
991 | * register number | |
992 | */ | |
25163bd5 WS |
993 | #define DEFAULT_REPLY_QUEUE (-1) |
994 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, | |
995 | int reply_queue) | |
3f5eac3a | 996 | { |
254f796b | 997 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 998 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
25163bd5 WS |
999 | if (unlikely(!h->msix_vector)) |
1000 | return; | |
1001 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) | |
254f796b | 1002 | c->Header.ReplyQueue = |
804a5cb5 | 1003 | raw_smp_processor_id() % h->nreply_queues; |
25163bd5 WS |
1004 | else |
1005 | c->Header.ReplyQueue = reply_queue % h->nreply_queues; | |
254f796b | 1006 | } |
3f5eac3a SC |
1007 | } |
1008 | ||
c349775e | 1009 | static void set_ioaccel1_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
1010 | struct CommandList *c, |
1011 | int reply_queue) | |
c349775e ST |
1012 | { |
1013 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
1014 | ||
25163bd5 WS |
1015 | /* |
1016 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
1017 | * processor. This seems to give the best I/O throughput. |
1018 | */ | |
25163bd5 WS |
1019 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) |
1020 | cp->ReplyQueue = smp_processor_id() % h->nreply_queues; | |
1021 | else | |
1022 | cp->ReplyQueue = reply_queue % h->nreply_queues; | |
1023 | /* | |
1024 | * Set the bits in the address sent down to include: | |
c349775e ST |
1025 | * - performant mode bit (bit 0) |
1026 | * - pull count (bits 1-3) | |
1027 | * - command type (bits 4-6) | |
1028 | */ | |
1029 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | | |
1030 | IOACCEL1_BUSADDR_CMDTYPE; | |
1031 | } | |
1032 | ||
8be986cc SC |
1033 | static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, |
1034 | struct CommandList *c, | |
1035 | int reply_queue) | |
1036 | { | |
1037 | struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) | |
1038 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1039 | ||
1040 | /* Tell the controller to post the reply to the queue for this | |
1041 | * processor. This seems to give the best I/O throughput. | |
1042 | */ | |
1043 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) | |
1044 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
1045 | else | |
1046 | cp->reply_queue = reply_queue % h->nreply_queues; | |
1047 | /* Set the bits in the address sent down to include: | |
1048 | * - performant mode bit not used in ioaccel mode 2 | |
1049 | * - pull count (bits 0-3) | |
1050 | * - command type isn't needed for ioaccel2 | |
1051 | */ | |
1052 | c->busaddr |= h->ioaccel2_blockFetchTable[0]; | |
1053 | } | |
1054 | ||
c349775e | 1055 | static void set_ioaccel2_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
1056 | struct CommandList *c, |
1057 | int reply_queue) | |
c349775e ST |
1058 | { |
1059 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1060 | ||
25163bd5 WS |
1061 | /* |
1062 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
1063 | * processor. This seems to give the best I/O throughput. |
1064 | */ | |
25163bd5 WS |
1065 | if (likely(reply_queue == DEFAULT_REPLY_QUEUE)) |
1066 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
1067 | else | |
1068 | cp->reply_queue = reply_queue % h->nreply_queues; | |
1069 | /* | |
1070 | * Set the bits in the address sent down to include: | |
c349775e ST |
1071 | * - performant mode bit not used in ioaccel mode 2 |
1072 | * - pull count (bits 0-3) | |
1073 | * - command type isn't needed for ioaccel2 | |
1074 | */ | |
1075 | c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); | |
1076 | } | |
1077 | ||
e85c5974 SC |
1078 | static int is_firmware_flash_cmd(u8 *cdb) |
1079 | { | |
1080 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
1081 | } | |
1082 | ||
1083 | /* | |
1084 | * During firmware flash, the heartbeat register may not update as frequently | |
1085 | * as it should. So we dial down lockup detection during firmware flash. and | |
1086 | * dial it back up when firmware flash completes. | |
1087 | */ | |
1088 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
1089 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
1090 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, | |
1091 | struct CommandList *c) | |
1092 | { | |
1093 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
1094 | return; | |
1095 | atomic_inc(&h->firmware_flash_in_progress); | |
1096 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
1097 | } | |
1098 | ||
1099 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
1100 | struct CommandList *c) | |
1101 | { | |
1102 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
1103 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
1104 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
1105 | } | |
1106 | ||
25163bd5 WS |
1107 | static void __enqueue_cmd_and_start_io(struct ctlr_info *h, |
1108 | struct CommandList *c, int reply_queue) | |
3f5eac3a | 1109 | { |
c05e8866 SC |
1110 | dial_down_lockup_detection_during_fw_flash(h, c); |
1111 | atomic_inc(&h->commands_outstanding); | |
c349775e ST |
1112 | switch (c->cmd_type) { |
1113 | case CMD_IOACCEL1: | |
25163bd5 | 1114 | set_ioaccel1_performant_mode(h, c, reply_queue); |
c05e8866 | 1115 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
1116 | break; |
1117 | case CMD_IOACCEL2: | |
25163bd5 | 1118 | set_ioaccel2_performant_mode(h, c, reply_queue); |
c05e8866 | 1119 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); |
c349775e | 1120 | break; |
8be986cc SC |
1121 | case IOACCEL2_TMF: |
1122 | set_ioaccel2_tmf_performant_mode(h, c, reply_queue); | |
1123 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); | |
1124 | break; | |
c349775e | 1125 | default: |
25163bd5 | 1126 | set_performant_mode(h, c, reply_queue); |
c05e8866 | 1127 | h->access.submit_command(h, c); |
c349775e | 1128 | } |
3f5eac3a SC |
1129 | } |
1130 | ||
a58e7e53 | 1131 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) |
25163bd5 | 1132 | { |
d604f533 | 1133 | if (unlikely(hpsa_is_pending_event(c))) |
a58e7e53 WS |
1134 | return finish_cmd(c); |
1135 | ||
25163bd5 WS |
1136 | __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); |
1137 | } | |
1138 | ||
3f5eac3a SC |
1139 | static inline int is_hba_lunid(unsigned char scsi3addr[]) |
1140 | { | |
1141 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
1142 | } | |
1143 | ||
1144 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
1145 | { | |
1146 | if (!h->hba_inquiry_data) | |
1147 | return 0; | |
1148 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
1149 | return 1; | |
1150 | return 0; | |
1151 | } | |
1152 | ||
edd16368 SC |
1153 | static int hpsa_find_target_lun(struct ctlr_info *h, |
1154 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
1155 | { | |
1156 | /* finds an unused bus, target, lun for a new physical device | |
1157 | * assumes h->devlock is held | |
1158 | */ | |
1159 | int i, found = 0; | |
cfe5badc | 1160 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 1161 | |
263d9401 | 1162 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
1163 | |
1164 | for (i = 0; i < h->ndevices; i++) { | |
1165 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 1166 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
1167 | } |
1168 | ||
263d9401 AM |
1169 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
1170 | if (i < HPSA_MAX_DEVICES) { | |
1171 | /* *bus = 1; */ | |
1172 | *target = i; | |
1173 | *lun = 0; | |
1174 | found = 1; | |
edd16368 SC |
1175 | } |
1176 | return !found; | |
1177 | } | |
1178 | ||
1d33d85d | 1179 | static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, |
0d96ef5f WS |
1180 | struct hpsa_scsi_dev_t *dev, char *description) |
1181 | { | |
7c59a0d4 DB |
1182 | #define LABEL_SIZE 25 |
1183 | char label[LABEL_SIZE]; | |
1184 | ||
9975ec9d DB |
1185 | if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) |
1186 | return; | |
1187 | ||
7c59a0d4 DB |
1188 | switch (dev->devtype) { |
1189 | case TYPE_RAID: | |
1190 | snprintf(label, LABEL_SIZE, "controller"); | |
1191 | break; | |
1192 | case TYPE_ENCLOSURE: | |
1193 | snprintf(label, LABEL_SIZE, "enclosure"); | |
1194 | break; | |
1195 | case TYPE_DISK: | |
af15ed36 | 1196 | case TYPE_ZBC: |
7c59a0d4 DB |
1197 | if (dev->external) |
1198 | snprintf(label, LABEL_SIZE, "external"); | |
1199 | else if (!is_logical_dev_addr_mode(dev->scsi3addr)) | |
1200 | snprintf(label, LABEL_SIZE, "%s", | |
1201 | raid_label[PHYSICAL_DRIVE]); | |
1202 | else | |
1203 | snprintf(label, LABEL_SIZE, "RAID-%s", | |
1204 | dev->raid_level > RAID_UNKNOWN ? "?" : | |
1205 | raid_label[dev->raid_level]); | |
1206 | break; | |
1207 | case TYPE_ROM: | |
1208 | snprintf(label, LABEL_SIZE, "rom"); | |
1209 | break; | |
1210 | case TYPE_TAPE: | |
1211 | snprintf(label, LABEL_SIZE, "tape"); | |
1212 | break; | |
1213 | case TYPE_MEDIUM_CHANGER: | |
1214 | snprintf(label, LABEL_SIZE, "changer"); | |
1215 | break; | |
1216 | default: | |
1217 | snprintf(label, LABEL_SIZE, "UNKNOWN"); | |
1218 | break; | |
1219 | } | |
1220 | ||
0d96ef5f | 1221 | dev_printk(level, &h->pdev->dev, |
7c59a0d4 | 1222 | "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", |
0d96ef5f WS |
1223 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, |
1224 | description, | |
1225 | scsi_device_type(dev->devtype), | |
1226 | dev->vendor, | |
1227 | dev->model, | |
7c59a0d4 | 1228 | label, |
0d96ef5f WS |
1229 | dev->offload_config ? '+' : '-', |
1230 | dev->offload_enabled ? '+' : '-', | |
2a168208 | 1231 | dev->expose_device); |
0d96ef5f WS |
1232 | } |
1233 | ||
edd16368 | 1234 | /* Add an entry into h->dev[] array. */ |
8aa60681 | 1235 | static int hpsa_scsi_add_entry(struct ctlr_info *h, |
edd16368 SC |
1236 | struct hpsa_scsi_dev_t *device, |
1237 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
1238 | { | |
1239 | /* assumes h->devlock is held */ | |
1240 | int n = h->ndevices; | |
1241 | int i; | |
1242 | unsigned char addr1[8], addr2[8]; | |
1243 | struct hpsa_scsi_dev_t *sd; | |
1244 | ||
cfe5badc | 1245 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
1246 | dev_err(&h->pdev->dev, "too many devices, some will be " |
1247 | "inaccessible.\n"); | |
1248 | return -1; | |
1249 | } | |
1250 | ||
1251 | /* physical devices do not have lun or target assigned until now. */ | |
1252 | if (device->lun != -1) | |
1253 | /* Logical device, lun is already assigned. */ | |
1254 | goto lun_assigned; | |
1255 | ||
1256 | /* If this device a non-zero lun of a multi-lun device | |
1257 | * byte 4 of the 8-byte LUN addr will contain the logical | |
2b08b3e9 | 1258 | * unit no, zero otherwise. |
edd16368 SC |
1259 | */ |
1260 | if (device->scsi3addr[4] == 0) { | |
1261 | /* This is not a non-zero lun of a multi-lun device */ | |
1262 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
1263 | device->bus, &device->target, &device->lun) != 0) | |
1264 | return -1; | |
1265 | goto lun_assigned; | |
1266 | } | |
1267 | ||
1268 | /* This is a non-zero lun of a multi-lun device. | |
1269 | * Search through our list and find the device which | |
9a4178b7 | 1270 | * has the same 8 byte LUN address, excepting byte 4 and 5. |
edd16368 SC |
1271 | * Assign the same bus and target for this new LUN. |
1272 | * Use the logical unit number from the firmware. | |
1273 | */ | |
1274 | memcpy(addr1, device->scsi3addr, 8); | |
1275 | addr1[4] = 0; | |
9a4178b7 | 1276 | addr1[5] = 0; |
edd16368 SC |
1277 | for (i = 0; i < n; i++) { |
1278 | sd = h->dev[i]; | |
1279 | memcpy(addr2, sd->scsi3addr, 8); | |
1280 | addr2[4] = 0; | |
9a4178b7 | 1281 | addr2[5] = 0; |
1282 | /* differ only in byte 4 and 5? */ | |
edd16368 SC |
1283 | if (memcmp(addr1, addr2, 8) == 0) { |
1284 | device->bus = sd->bus; | |
1285 | device->target = sd->target; | |
1286 | device->lun = device->scsi3addr[4]; | |
1287 | break; | |
1288 | } | |
1289 | } | |
1290 | if (device->lun == -1) { | |
1291 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
1292 | " suspect firmware bug or unsupported hardware " | |
1293 | "configuration.\n"); | |
1294 | return -1; | |
1295 | } | |
1296 | ||
1297 | lun_assigned: | |
1298 | ||
1299 | h->dev[n] = device; | |
1300 | h->ndevices++; | |
1301 | added[*nadded] = device; | |
1302 | (*nadded)++; | |
0d96ef5f | 1303 | hpsa_show_dev_msg(KERN_INFO, h, device, |
2a168208 | 1304 | device->expose_device ? "added" : "masked"); |
a473d86c RE |
1305 | device->offload_to_be_enabled = device->offload_enabled; |
1306 | device->offload_enabled = 0; | |
edd16368 SC |
1307 | return 0; |
1308 | } | |
1309 | ||
bd9244f7 | 1310 | /* Update an entry in h->dev[] array. */ |
8aa60681 | 1311 | static void hpsa_scsi_update_entry(struct ctlr_info *h, |
bd9244f7 ST |
1312 | int entry, struct hpsa_scsi_dev_t *new_entry) |
1313 | { | |
a473d86c | 1314 | int offload_enabled; |
bd9244f7 ST |
1315 | /* assumes h->devlock is held */ |
1316 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
1317 | ||
1318 | /* Raid level changed. */ | |
1319 | h->dev[entry]->raid_level = new_entry->raid_level; | |
250fb125 | 1320 | |
03383736 DB |
1321 | /* Raid offload parameters changed. Careful about the ordering. */ |
1322 | if (new_entry->offload_config && new_entry->offload_enabled) { | |
1323 | /* | |
1324 | * if drive is newly offload_enabled, we want to copy the | |
1325 | * raid map data first. If previously offload_enabled and | |
1326 | * offload_config were set, raid map data had better be | |
1327 | * the same as it was before. if raid map data is changed | |
1328 | * then it had better be the case that | |
1329 | * h->dev[entry]->offload_enabled is currently 0. | |
1330 | */ | |
1331 | h->dev[entry]->raid_map = new_entry->raid_map; | |
1332 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
03383736 | 1333 | } |
a3144e0b JH |
1334 | if (new_entry->hba_ioaccel_enabled) { |
1335 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
1336 | wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ | |
1337 | } | |
1338 | h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; | |
250fb125 | 1339 | h->dev[entry]->offload_config = new_entry->offload_config; |
9fb0de2d | 1340 | h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; |
03383736 | 1341 | h->dev[entry]->queue_depth = new_entry->queue_depth; |
250fb125 | 1342 | |
41ce4c35 SC |
1343 | /* |
1344 | * We can turn off ioaccel offload now, but need to delay turning | |
1345 | * it on until we can update h->dev[entry]->phys_disk[], but we | |
1346 | * can't do that until all the devices are updated. | |
1347 | */ | |
1348 | h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled; | |
1349 | if (!new_entry->offload_enabled) | |
1350 | h->dev[entry]->offload_enabled = 0; | |
1351 | ||
a473d86c RE |
1352 | offload_enabled = h->dev[entry]->offload_enabled; |
1353 | h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled; | |
0d96ef5f | 1354 | hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); |
a473d86c | 1355 | h->dev[entry]->offload_enabled = offload_enabled; |
bd9244f7 ST |
1356 | } |
1357 | ||
2a8ccf31 | 1358 | /* Replace an entry from h->dev[] array. */ |
8aa60681 | 1359 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, |
2a8ccf31 SC |
1360 | int entry, struct hpsa_scsi_dev_t *new_entry, |
1361 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
1362 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
1363 | { | |
1364 | /* assumes h->devlock is held */ | |
cfe5badc | 1365 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
1366 | removed[*nremoved] = h->dev[entry]; |
1367 | (*nremoved)++; | |
01350d05 SC |
1368 | |
1369 | /* | |
1370 | * New physical devices won't have target/lun assigned yet | |
1371 | * so we need to preserve the values in the slot we are replacing. | |
1372 | */ | |
1373 | if (new_entry->target == -1) { | |
1374 | new_entry->target = h->dev[entry]->target; | |
1375 | new_entry->lun = h->dev[entry]->lun; | |
1376 | } | |
1377 | ||
2a8ccf31 SC |
1378 | h->dev[entry] = new_entry; |
1379 | added[*nadded] = new_entry; | |
1380 | (*nadded)++; | |
0d96ef5f | 1381 | hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); |
a473d86c RE |
1382 | new_entry->offload_to_be_enabled = new_entry->offload_enabled; |
1383 | new_entry->offload_enabled = 0; | |
2a8ccf31 SC |
1384 | } |
1385 | ||
edd16368 | 1386 | /* Remove an entry from h->dev[] array. */ |
8aa60681 | 1387 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, |
edd16368 SC |
1388 | struct hpsa_scsi_dev_t *removed[], int *nremoved) |
1389 | { | |
1390 | /* assumes h->devlock is held */ | |
1391 | int i; | |
1392 | struct hpsa_scsi_dev_t *sd; | |
1393 | ||
cfe5badc | 1394 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
1395 | |
1396 | sd = h->dev[entry]; | |
1397 | removed[*nremoved] = h->dev[entry]; | |
1398 | (*nremoved)++; | |
1399 | ||
1400 | for (i = entry; i < h->ndevices-1; i++) | |
1401 | h->dev[i] = h->dev[i+1]; | |
1402 | h->ndevices--; | |
0d96ef5f | 1403 | hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); |
edd16368 SC |
1404 | } |
1405 | ||
1406 | #define SCSI3ADDR_EQ(a, b) ( \ | |
1407 | (a)[7] == (b)[7] && \ | |
1408 | (a)[6] == (b)[6] && \ | |
1409 | (a)[5] == (b)[5] && \ | |
1410 | (a)[4] == (b)[4] && \ | |
1411 | (a)[3] == (b)[3] && \ | |
1412 | (a)[2] == (b)[2] && \ | |
1413 | (a)[1] == (b)[1] && \ | |
1414 | (a)[0] == (b)[0]) | |
1415 | ||
1416 | static void fixup_botched_add(struct ctlr_info *h, | |
1417 | struct hpsa_scsi_dev_t *added) | |
1418 | { | |
1419 | /* called when scsi_add_device fails in order to re-adjust | |
1420 | * h->dev[] to match the mid layer's view. | |
1421 | */ | |
1422 | unsigned long flags; | |
1423 | int i, j; | |
1424 | ||
1425 | spin_lock_irqsave(&h->lock, flags); | |
1426 | for (i = 0; i < h->ndevices; i++) { | |
1427 | if (h->dev[i] == added) { | |
1428 | for (j = i; j < h->ndevices-1; j++) | |
1429 | h->dev[j] = h->dev[j+1]; | |
1430 | h->ndevices--; | |
1431 | break; | |
1432 | } | |
1433 | } | |
1434 | spin_unlock_irqrestore(&h->lock, flags); | |
1435 | kfree(added); | |
1436 | } | |
1437 | ||
1438 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
1439 | struct hpsa_scsi_dev_t *dev2) | |
1440 | { | |
edd16368 SC |
1441 | /* we compare everything except lun and target as these |
1442 | * are not yet assigned. Compare parts likely | |
1443 | * to differ first | |
1444 | */ | |
1445 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
1446 | sizeof(dev1->scsi3addr)) != 0) | |
1447 | return 0; | |
1448 | if (memcmp(dev1->device_id, dev2->device_id, | |
1449 | sizeof(dev1->device_id)) != 0) | |
1450 | return 0; | |
1451 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
1452 | return 0; | |
1453 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
1454 | return 0; | |
edd16368 SC |
1455 | if (dev1->devtype != dev2->devtype) |
1456 | return 0; | |
edd16368 SC |
1457 | if (dev1->bus != dev2->bus) |
1458 | return 0; | |
1459 | return 1; | |
1460 | } | |
1461 | ||
bd9244f7 ST |
1462 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
1463 | struct hpsa_scsi_dev_t *dev2) | |
1464 | { | |
1465 | /* Device attributes that can change, but don't mean | |
1466 | * that the device is a different device, nor that the OS | |
1467 | * needs to be told anything about the change. | |
1468 | */ | |
1469 | if (dev1->raid_level != dev2->raid_level) | |
1470 | return 1; | |
250fb125 SC |
1471 | if (dev1->offload_config != dev2->offload_config) |
1472 | return 1; | |
1473 | if (dev1->offload_enabled != dev2->offload_enabled) | |
1474 | return 1; | |
93849508 DB |
1475 | if (!is_logical_dev_addr_mode(dev1->scsi3addr)) |
1476 | if (dev1->queue_depth != dev2->queue_depth) | |
1477 | return 1; | |
bd9244f7 ST |
1478 | return 0; |
1479 | } | |
1480 | ||
edd16368 SC |
1481 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
1482 | * and return needle location in *index. If scsi3addr matches, but not | |
1483 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
1484 | * location in *index. |
1485 | * In the case of a minor device attribute change, such as RAID level, just | |
1486 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
1487 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
1488 | */ |
1489 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
1490 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
1491 | int *index) | |
1492 | { | |
1493 | int i; | |
1494 | #define DEVICE_NOT_FOUND 0 | |
1495 | #define DEVICE_CHANGED 1 | |
1496 | #define DEVICE_SAME 2 | |
bd9244f7 | 1497 | #define DEVICE_UPDATED 3 |
1d33d85d DB |
1498 | if (needle == NULL) |
1499 | return DEVICE_NOT_FOUND; | |
1500 | ||
edd16368 | 1501 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
1502 | if (haystack[i] == NULL) /* previously removed. */ |
1503 | continue; | |
edd16368 SC |
1504 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
1505 | *index = i; | |
bd9244f7 ST |
1506 | if (device_is_the_same(needle, haystack[i])) { |
1507 | if (device_updated(needle, haystack[i])) | |
1508 | return DEVICE_UPDATED; | |
edd16368 | 1509 | return DEVICE_SAME; |
bd9244f7 | 1510 | } else { |
9846590e SC |
1511 | /* Keep offline devices offline */ |
1512 | if (needle->volume_offline) | |
1513 | return DEVICE_NOT_FOUND; | |
edd16368 | 1514 | return DEVICE_CHANGED; |
bd9244f7 | 1515 | } |
edd16368 SC |
1516 | } |
1517 | } | |
1518 | *index = -1; | |
1519 | return DEVICE_NOT_FOUND; | |
1520 | } | |
1521 | ||
9846590e SC |
1522 | static void hpsa_monitor_offline_device(struct ctlr_info *h, |
1523 | unsigned char scsi3addr[]) | |
1524 | { | |
1525 | struct offline_device_entry *device; | |
1526 | unsigned long flags; | |
1527 | ||
1528 | /* Check to see if device is already on the list */ | |
1529 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1530 | list_for_each_entry(device, &h->offline_device_list, offline_list) { | |
1531 | if (memcmp(device->scsi3addr, scsi3addr, | |
1532 | sizeof(device->scsi3addr)) == 0) { | |
1533 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1534 | return; | |
1535 | } | |
1536 | } | |
1537 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1538 | ||
1539 | /* Device is not on the list, add it. */ | |
1540 | device = kmalloc(sizeof(*device), GFP_KERNEL); | |
1541 | if (!device) { | |
1542 | dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__); | |
1543 | return; | |
1544 | } | |
1545 | memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); | |
1546 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1547 | list_add_tail(&device->offline_list, &h->offline_device_list); | |
1548 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1549 | } | |
1550 | ||
1551 | /* Print a message explaining various offline volume states */ | |
1552 | static void hpsa_show_volume_status(struct ctlr_info *h, | |
1553 | struct hpsa_scsi_dev_t *sd) | |
1554 | { | |
1555 | if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) | |
1556 | dev_info(&h->pdev->dev, | |
1557 | "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", | |
1558 | h->scsi_host->host_no, | |
1559 | sd->bus, sd->target, sd->lun); | |
1560 | switch (sd->volume_offline) { | |
1561 | case HPSA_LV_OK: | |
1562 | break; | |
1563 | case HPSA_LV_UNDERGOING_ERASE: | |
1564 | dev_info(&h->pdev->dev, | |
1565 | "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", | |
1566 | h->scsi_host->host_no, | |
1567 | sd->bus, sd->target, sd->lun); | |
1568 | break; | |
5ca01204 SB |
1569 | case HPSA_LV_NOT_AVAILABLE: |
1570 | dev_info(&h->pdev->dev, | |
1571 | "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", | |
1572 | h->scsi_host->host_no, | |
1573 | sd->bus, sd->target, sd->lun); | |
1574 | break; | |
9846590e SC |
1575 | case HPSA_LV_UNDERGOING_RPI: |
1576 | dev_info(&h->pdev->dev, | |
5ca01204 | 1577 | "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", |
9846590e SC |
1578 | h->scsi_host->host_no, |
1579 | sd->bus, sd->target, sd->lun); | |
1580 | break; | |
1581 | case HPSA_LV_PENDING_RPI: | |
1582 | dev_info(&h->pdev->dev, | |
5ca01204 SB |
1583 | "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", |
1584 | h->scsi_host->host_no, | |
1585 | sd->bus, sd->target, sd->lun); | |
9846590e SC |
1586 | break; |
1587 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
1588 | dev_info(&h->pdev->dev, | |
1589 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", | |
1590 | h->scsi_host->host_no, | |
1591 | sd->bus, sd->target, sd->lun); | |
1592 | break; | |
1593 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
1594 | dev_info(&h->pdev->dev, | |
1595 | "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", | |
1596 | h->scsi_host->host_no, | |
1597 | sd->bus, sd->target, sd->lun); | |
1598 | break; | |
1599 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
1600 | dev_info(&h->pdev->dev, | |
1601 | "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", | |
1602 | h->scsi_host->host_no, | |
1603 | sd->bus, sd->target, sd->lun); | |
1604 | break; | |
1605 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
1606 | dev_info(&h->pdev->dev, | |
1607 | "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", | |
1608 | h->scsi_host->host_no, | |
1609 | sd->bus, sd->target, sd->lun); | |
1610 | break; | |
1611 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
1612 | dev_info(&h->pdev->dev, | |
1613 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", | |
1614 | h->scsi_host->host_no, | |
1615 | sd->bus, sd->target, sd->lun); | |
1616 | break; | |
1617 | case HPSA_LV_PENDING_ENCRYPTION: | |
1618 | dev_info(&h->pdev->dev, | |
1619 | "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", | |
1620 | h->scsi_host->host_no, | |
1621 | sd->bus, sd->target, sd->lun); | |
1622 | break; | |
1623 | case HPSA_LV_PENDING_ENCRYPTION_REKEYING: | |
1624 | dev_info(&h->pdev->dev, | |
1625 | "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", | |
1626 | h->scsi_host->host_no, | |
1627 | sd->bus, sd->target, sd->lun); | |
1628 | break; | |
1629 | } | |
1630 | } | |
1631 | ||
03383736 DB |
1632 | /* |
1633 | * Figure the list of physical drive pointers for a logical drive with | |
1634 | * raid offload configured. | |
1635 | */ | |
1636 | static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, | |
1637 | struct hpsa_scsi_dev_t *dev[], int ndevices, | |
1638 | struct hpsa_scsi_dev_t *logical_drive) | |
1639 | { | |
1640 | struct raid_map_data *map = &logical_drive->raid_map; | |
1641 | struct raid_map_disk_data *dd = &map->data[0]; | |
1642 | int i, j; | |
1643 | int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + | |
1644 | le16_to_cpu(map->metadata_disks_per_row); | |
1645 | int nraid_map_entries = le16_to_cpu(map->row_cnt) * | |
1646 | le16_to_cpu(map->layout_map_count) * | |
1647 | total_disks_per_row; | |
1648 | int nphys_disk = le16_to_cpu(map->layout_map_count) * | |
1649 | total_disks_per_row; | |
1650 | int qdepth; | |
1651 | ||
1652 | if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) | |
1653 | nraid_map_entries = RAID_MAP_MAX_ENTRIES; | |
1654 | ||
d604f533 WS |
1655 | logical_drive->nphysical_disks = nraid_map_entries; |
1656 | ||
03383736 DB |
1657 | qdepth = 0; |
1658 | for (i = 0; i < nraid_map_entries; i++) { | |
1659 | logical_drive->phys_disk[i] = NULL; | |
1660 | if (!logical_drive->offload_config) | |
1661 | continue; | |
1662 | for (j = 0; j < ndevices; j++) { | |
1d33d85d DB |
1663 | if (dev[j] == NULL) |
1664 | continue; | |
03383736 DB |
1665 | if (dev[j]->devtype != TYPE_DISK) |
1666 | continue; | |
af15ed36 DB |
1667 | if (dev[j]->devtype != TYPE_ZBC) |
1668 | continue; | |
f3f01730 | 1669 | if (is_logical_device(dev[j])) |
03383736 DB |
1670 | continue; |
1671 | if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) | |
1672 | continue; | |
1673 | ||
1674 | logical_drive->phys_disk[i] = dev[j]; | |
1675 | if (i < nphys_disk) | |
1676 | qdepth = min(h->nr_cmds, qdepth + | |
1677 | logical_drive->phys_disk[i]->queue_depth); | |
1678 | break; | |
1679 | } | |
1680 | ||
1681 | /* | |
1682 | * This can happen if a physical drive is removed and | |
1683 | * the logical drive is degraded. In that case, the RAID | |
1684 | * map data will refer to a physical disk which isn't actually | |
1685 | * present. And in that case offload_enabled should already | |
1686 | * be 0, but we'll turn it off here just in case | |
1687 | */ | |
1688 | if (!logical_drive->phys_disk[i]) { | |
1689 | logical_drive->offload_enabled = 0; | |
41ce4c35 SC |
1690 | logical_drive->offload_to_be_enabled = 0; |
1691 | logical_drive->queue_depth = 8; | |
03383736 DB |
1692 | } |
1693 | } | |
1694 | if (nraid_map_entries) | |
1695 | /* | |
1696 | * This is correct for reads, too high for full stripe writes, | |
1697 | * way too high for partial stripe writes | |
1698 | */ | |
1699 | logical_drive->queue_depth = qdepth; | |
1700 | else | |
1701 | logical_drive->queue_depth = h->nr_cmds; | |
1702 | } | |
1703 | ||
1704 | static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, | |
1705 | struct hpsa_scsi_dev_t *dev[], int ndevices) | |
1706 | { | |
1707 | int i; | |
1708 | ||
1709 | for (i = 0; i < ndevices; i++) { | |
1d33d85d DB |
1710 | if (dev[i] == NULL) |
1711 | continue; | |
03383736 DB |
1712 | if (dev[i]->devtype != TYPE_DISK) |
1713 | continue; | |
af15ed36 DB |
1714 | if (dev[i]->devtype != TYPE_ZBC) |
1715 | continue; | |
f3f01730 | 1716 | if (!is_logical_device(dev[i])) |
03383736 | 1717 | continue; |
41ce4c35 SC |
1718 | |
1719 | /* | |
1720 | * If offload is currently enabled, the RAID map and | |
1721 | * phys_disk[] assignment *better* not be changing | |
1722 | * and since it isn't changing, we do not need to | |
1723 | * update it. | |
1724 | */ | |
1725 | if (dev[i]->offload_enabled) | |
1726 | continue; | |
1727 | ||
03383736 DB |
1728 | hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); |
1729 | } | |
1730 | } | |
1731 | ||
096ccff4 KB |
1732 | static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
1733 | { | |
1734 | int rc = 0; | |
1735 | ||
1736 | if (!h->scsi_host) | |
1737 | return 1; | |
1738 | ||
d04e62b9 KB |
1739 | if (is_logical_device(device)) /* RAID */ |
1740 | rc = scsi_add_device(h->scsi_host, device->bus, | |
096ccff4 | 1741 | device->target, device->lun); |
d04e62b9 KB |
1742 | else /* HBA */ |
1743 | rc = hpsa_add_sas_device(h->sas_host, device); | |
1744 | ||
096ccff4 KB |
1745 | return rc; |
1746 | } | |
1747 | ||
1748 | static void hpsa_remove_device(struct ctlr_info *h, | |
1749 | struct hpsa_scsi_dev_t *device) | |
1750 | { | |
1751 | struct scsi_device *sdev = NULL; | |
1752 | ||
1753 | if (!h->scsi_host) | |
1754 | return; | |
1755 | ||
d04e62b9 KB |
1756 | if (is_logical_device(device)) { /* RAID */ |
1757 | sdev = scsi_device_lookup(h->scsi_host, device->bus, | |
096ccff4 | 1758 | device->target, device->lun); |
d04e62b9 KB |
1759 | if (sdev) { |
1760 | scsi_remove_device(sdev); | |
1761 | scsi_device_put(sdev); | |
1762 | } else { | |
1763 | /* | |
1764 | * We don't expect to get here. Future commands | |
1765 | * to this device will get a selection timeout as | |
1766 | * if the device were gone. | |
1767 | */ | |
1768 | hpsa_show_dev_msg(KERN_WARNING, h, device, | |
096ccff4 | 1769 | "didn't find device for removal."); |
d04e62b9 KB |
1770 | } |
1771 | } else /* HBA */ | |
1772 | hpsa_remove_sas_device(device); | |
096ccff4 KB |
1773 | } |
1774 | ||
8aa60681 | 1775 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, |
edd16368 SC |
1776 | struct hpsa_scsi_dev_t *sd[], int nsds) |
1777 | { | |
1778 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
1779 | * data. This function takes what's in sd to be the current | |
1780 | * reality and updates h->dev[] to reflect that reality. | |
1781 | */ | |
1782 | int i, entry, device_change, changes = 0; | |
1783 | struct hpsa_scsi_dev_t *csd; | |
1784 | unsigned long flags; | |
1785 | struct hpsa_scsi_dev_t **added, **removed; | |
1786 | int nadded, nremoved; | |
edd16368 | 1787 | |
da03ded0 DB |
1788 | /* |
1789 | * A reset can cause a device status to change | |
1790 | * re-schedule the scan to see what happened. | |
1791 | */ | |
1792 | if (h->reset_in_progress) { | |
1793 | h->drv_req_rescan = 1; | |
1794 | return; | |
1795 | } | |
edd16368 | 1796 | |
cfe5badc ST |
1797 | added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); |
1798 | removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); | |
edd16368 SC |
1799 | |
1800 | if (!added || !removed) { | |
1801 | dev_warn(&h->pdev->dev, "out of memory in " | |
1802 | "adjust_hpsa_scsi_table\n"); | |
1803 | goto free_and_out; | |
1804 | } | |
1805 | ||
1806 | spin_lock_irqsave(&h->devlock, flags); | |
1807 | ||
1808 | /* find any devices in h->dev[] that are not in | |
1809 | * sd[] and remove them from h->dev[], and for any | |
1810 | * devices which have changed, remove the old device | |
1811 | * info and add the new device info. | |
bd9244f7 ST |
1812 | * If minor device attributes change, just update |
1813 | * the existing device structure. | |
edd16368 SC |
1814 | */ |
1815 | i = 0; | |
1816 | nremoved = 0; | |
1817 | nadded = 0; | |
1818 | while (i < h->ndevices) { | |
1819 | csd = h->dev[i]; | |
1820 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
1821 | if (device_change == DEVICE_NOT_FOUND) { | |
1822 | changes++; | |
8aa60681 | 1823 | hpsa_scsi_remove_entry(h, i, removed, &nremoved); |
edd16368 SC |
1824 | continue; /* remove ^^^, hence i not incremented */ |
1825 | } else if (device_change == DEVICE_CHANGED) { | |
1826 | changes++; | |
8aa60681 | 1827 | hpsa_scsi_replace_entry(h, i, sd[entry], |
2a8ccf31 | 1828 | added, &nadded, removed, &nremoved); |
c7f172dc SC |
1829 | /* Set it to NULL to prevent it from being freed |
1830 | * at the bottom of hpsa_update_scsi_devices() | |
1831 | */ | |
1832 | sd[entry] = NULL; | |
bd9244f7 | 1833 | } else if (device_change == DEVICE_UPDATED) { |
8aa60681 | 1834 | hpsa_scsi_update_entry(h, i, sd[entry]); |
edd16368 SC |
1835 | } |
1836 | i++; | |
1837 | } | |
1838 | ||
1839 | /* Now, make sure every device listed in sd[] is also | |
1840 | * listed in h->dev[], adding them if they aren't found | |
1841 | */ | |
1842 | ||
1843 | for (i = 0; i < nsds; i++) { | |
1844 | if (!sd[i]) /* if already added above. */ | |
1845 | continue; | |
9846590e SC |
1846 | |
1847 | /* Don't add devices which are NOT READY, FORMAT IN PROGRESS | |
1848 | * as the SCSI mid-layer does not handle such devices well. | |
1849 | * It relentlessly loops sending TUR at 3Hz, then READ(10) | |
1850 | * at 160Hz, and prevents the system from coming up. | |
1851 | */ | |
1852 | if (sd[i]->volume_offline) { | |
1853 | hpsa_show_volume_status(h, sd[i]); | |
0d96ef5f | 1854 | hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); |
9846590e SC |
1855 | continue; |
1856 | } | |
1857 | ||
edd16368 SC |
1858 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, |
1859 | h->ndevices, &entry); | |
1860 | if (device_change == DEVICE_NOT_FOUND) { | |
1861 | changes++; | |
8aa60681 | 1862 | if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) |
edd16368 SC |
1863 | break; |
1864 | sd[i] = NULL; /* prevent from being freed later. */ | |
1865 | } else if (device_change == DEVICE_CHANGED) { | |
1866 | /* should never happen... */ | |
1867 | changes++; | |
1868 | dev_warn(&h->pdev->dev, | |
1869 | "device unexpectedly changed.\n"); | |
1870 | /* but if it does happen, we just ignore that device */ | |
1871 | } | |
1872 | } | |
41ce4c35 SC |
1873 | hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); |
1874 | ||
1875 | /* Now that h->dev[]->phys_disk[] is coherent, we can enable | |
1876 | * any logical drives that need it enabled. | |
1877 | */ | |
1d33d85d DB |
1878 | for (i = 0; i < h->ndevices; i++) { |
1879 | if (h->dev[i] == NULL) | |
1880 | continue; | |
41ce4c35 | 1881 | h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; |
1d33d85d | 1882 | } |
41ce4c35 | 1883 | |
edd16368 SC |
1884 | spin_unlock_irqrestore(&h->devlock, flags); |
1885 | ||
9846590e SC |
1886 | /* Monitor devices which are in one of several NOT READY states to be |
1887 | * brought online later. This must be done without holding h->devlock, | |
1888 | * so don't touch h->dev[] | |
1889 | */ | |
1890 | for (i = 0; i < nsds; i++) { | |
1891 | if (!sd[i]) /* if already added above. */ | |
1892 | continue; | |
1893 | if (sd[i]->volume_offline) | |
1894 | hpsa_monitor_offline_device(h, sd[i]->scsi3addr); | |
1895 | } | |
1896 | ||
edd16368 SC |
1897 | /* Don't notify scsi mid layer of any changes the first time through |
1898 | * (or if there are no changes) scsi_scan_host will do it later the | |
1899 | * first time through. | |
1900 | */ | |
8aa60681 | 1901 | if (!changes) |
edd16368 SC |
1902 | goto free_and_out; |
1903 | ||
edd16368 SC |
1904 | /* Notify scsi mid layer of any removed devices */ |
1905 | for (i = 0; i < nremoved; i++) { | |
1d33d85d DB |
1906 | if (removed[i] == NULL) |
1907 | continue; | |
096ccff4 KB |
1908 | if (removed[i]->expose_device) |
1909 | hpsa_remove_device(h, removed[i]); | |
edd16368 SC |
1910 | kfree(removed[i]); |
1911 | removed[i] = NULL; | |
1912 | } | |
1913 | ||
1914 | /* Notify scsi mid layer of any added devices */ | |
1915 | for (i = 0; i < nadded; i++) { | |
096ccff4 KB |
1916 | int rc = 0; |
1917 | ||
1d33d85d DB |
1918 | if (added[i] == NULL) |
1919 | continue; | |
2a168208 | 1920 | if (!(added[i]->expose_device)) |
41ce4c35 | 1921 | continue; |
096ccff4 KB |
1922 | rc = hpsa_add_device(h, added[i]); |
1923 | if (!rc) | |
edd16368 | 1924 | continue; |
096ccff4 KB |
1925 | dev_warn(&h->pdev->dev, |
1926 | "addition failed %d, device not added.", rc); | |
edd16368 SC |
1927 | /* now we have to remove it from h->dev, |
1928 | * since it didn't get added to scsi mid layer | |
1929 | */ | |
1930 | fixup_botched_add(h, added[i]); | |
853633e8 | 1931 | h->drv_req_rescan = 1; |
edd16368 SC |
1932 | } |
1933 | ||
1934 | free_and_out: | |
1935 | kfree(added); | |
1936 | kfree(removed); | |
edd16368 SC |
1937 | } |
1938 | ||
1939 | /* | |
9e03aa2f | 1940 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
1941 | * Assume's h->devlock is held. |
1942 | */ | |
1943 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
1944 | int bus, int target, int lun) | |
1945 | { | |
1946 | int i; | |
1947 | struct hpsa_scsi_dev_t *sd; | |
1948 | ||
1949 | for (i = 0; i < h->ndevices; i++) { | |
1950 | sd = h->dev[i]; | |
1951 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
1952 | return sd; | |
1953 | } | |
1954 | return NULL; | |
1955 | } | |
1956 | ||
edd16368 SC |
1957 | static int hpsa_slave_alloc(struct scsi_device *sdev) |
1958 | { | |
1959 | struct hpsa_scsi_dev_t *sd; | |
1960 | unsigned long flags; | |
1961 | struct ctlr_info *h; | |
1962 | ||
1963 | h = sdev_to_hba(sdev); | |
1964 | spin_lock_irqsave(&h->devlock, flags); | |
d04e62b9 KB |
1965 | if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { |
1966 | struct scsi_target *starget; | |
1967 | struct sas_rphy *rphy; | |
1968 | ||
1969 | starget = scsi_target(sdev); | |
1970 | rphy = target_to_rphy(starget); | |
1971 | sd = hpsa_find_device_by_sas_rphy(h, rphy); | |
1972 | if (sd) { | |
1973 | sd->target = sdev_id(sdev); | |
1974 | sd->lun = sdev->lun; | |
1975 | } | |
1976 | } else | |
1977 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), | |
1978 | sdev_id(sdev), sdev->lun); | |
1979 | ||
1980 | if (sd && sd->expose_device) { | |
03383736 | 1981 | atomic_set(&sd->ioaccel_cmds_out, 0); |
d04e62b9 | 1982 | sdev->hostdata = sd; |
41ce4c35 SC |
1983 | } else |
1984 | sdev->hostdata = NULL; | |
edd16368 SC |
1985 | spin_unlock_irqrestore(&h->devlock, flags); |
1986 | return 0; | |
1987 | } | |
1988 | ||
41ce4c35 SC |
1989 | /* configure scsi device based on internal per-device structure */ |
1990 | static int hpsa_slave_configure(struct scsi_device *sdev) | |
1991 | { | |
1992 | struct hpsa_scsi_dev_t *sd; | |
1993 | int queue_depth; | |
1994 | ||
1995 | sd = sdev->hostdata; | |
2a168208 | 1996 | sdev->no_uld_attach = !sd || !sd->expose_device; |
41ce4c35 SC |
1997 | |
1998 | if (sd) | |
1999 | queue_depth = sd->queue_depth != 0 ? | |
2000 | sd->queue_depth : sdev->host->can_queue; | |
2001 | else | |
2002 | queue_depth = sdev->host->can_queue; | |
2003 | ||
2004 | scsi_change_queue_depth(sdev, queue_depth); | |
2005 | ||
2006 | return 0; | |
2007 | } | |
2008 | ||
edd16368 SC |
2009 | static void hpsa_slave_destroy(struct scsi_device *sdev) |
2010 | { | |
bcc44255 | 2011 | /* nothing to do. */ |
edd16368 SC |
2012 | } |
2013 | ||
d9a729f3 WS |
2014 | static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) |
2015 | { | |
2016 | int i; | |
2017 | ||
2018 | if (!h->ioaccel2_cmd_sg_list) | |
2019 | return; | |
2020 | for (i = 0; i < h->nr_cmds; i++) { | |
2021 | kfree(h->ioaccel2_cmd_sg_list[i]); | |
2022 | h->ioaccel2_cmd_sg_list[i] = NULL; | |
2023 | } | |
2024 | kfree(h->ioaccel2_cmd_sg_list); | |
2025 | h->ioaccel2_cmd_sg_list = NULL; | |
2026 | } | |
2027 | ||
2028 | static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) | |
2029 | { | |
2030 | int i; | |
2031 | ||
2032 | if (h->chainsize <= 0) | |
2033 | return 0; | |
2034 | ||
2035 | h->ioaccel2_cmd_sg_list = | |
2036 | kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds, | |
2037 | GFP_KERNEL); | |
2038 | if (!h->ioaccel2_cmd_sg_list) | |
2039 | return -ENOMEM; | |
2040 | for (i = 0; i < h->nr_cmds; i++) { | |
2041 | h->ioaccel2_cmd_sg_list[i] = | |
2042 | kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) * | |
2043 | h->maxsgentries, GFP_KERNEL); | |
2044 | if (!h->ioaccel2_cmd_sg_list[i]) | |
2045 | goto clean; | |
2046 | } | |
2047 | return 0; | |
2048 | ||
2049 | clean: | |
2050 | hpsa_free_ioaccel2_sg_chain_blocks(h); | |
2051 | return -ENOMEM; | |
2052 | } | |
2053 | ||
33a2ffce SC |
2054 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
2055 | { | |
2056 | int i; | |
2057 | ||
2058 | if (!h->cmd_sg_list) | |
2059 | return; | |
2060 | for (i = 0; i < h->nr_cmds; i++) { | |
2061 | kfree(h->cmd_sg_list[i]); | |
2062 | h->cmd_sg_list[i] = NULL; | |
2063 | } | |
2064 | kfree(h->cmd_sg_list); | |
2065 | h->cmd_sg_list = NULL; | |
2066 | } | |
2067 | ||
105a3dbc | 2068 | static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) |
33a2ffce SC |
2069 | { |
2070 | int i; | |
2071 | ||
2072 | if (h->chainsize <= 0) | |
2073 | return 0; | |
2074 | ||
2075 | h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, | |
2076 | GFP_KERNEL); | |
3d4e6af8 RE |
2077 | if (!h->cmd_sg_list) { |
2078 | dev_err(&h->pdev->dev, "Failed to allocate SG list\n"); | |
33a2ffce | 2079 | return -ENOMEM; |
3d4e6af8 | 2080 | } |
33a2ffce SC |
2081 | for (i = 0; i < h->nr_cmds; i++) { |
2082 | h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * | |
2083 | h->chainsize, GFP_KERNEL); | |
3d4e6af8 RE |
2084 | if (!h->cmd_sg_list[i]) { |
2085 | dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n"); | |
33a2ffce | 2086 | goto clean; |
3d4e6af8 | 2087 | } |
33a2ffce SC |
2088 | } |
2089 | return 0; | |
2090 | ||
2091 | clean: | |
2092 | hpsa_free_sg_chain_blocks(h); | |
2093 | return -ENOMEM; | |
2094 | } | |
2095 | ||
d9a729f3 WS |
2096 | static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, |
2097 | struct io_accel2_cmd *cp, struct CommandList *c) | |
2098 | { | |
2099 | struct ioaccel2_sg_element *chain_block; | |
2100 | u64 temp64; | |
2101 | u32 chain_size; | |
2102 | ||
2103 | chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
a736e9b6 | 2104 | chain_size = le32_to_cpu(cp->sg[0].length); |
d9a729f3 WS |
2105 | temp64 = pci_map_single(h->pdev, chain_block, chain_size, |
2106 | PCI_DMA_TODEVICE); | |
2107 | if (dma_mapping_error(&h->pdev->dev, temp64)) { | |
2108 | /* prevent subsequent unmapping */ | |
2109 | cp->sg->address = 0; | |
2110 | return -1; | |
2111 | } | |
2112 | cp->sg->address = cpu_to_le64(temp64); | |
2113 | return 0; | |
2114 | } | |
2115 | ||
2116 | static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, | |
2117 | struct io_accel2_cmd *cp) | |
2118 | { | |
2119 | struct ioaccel2_sg_element *chain_sg; | |
2120 | u64 temp64; | |
2121 | u32 chain_size; | |
2122 | ||
2123 | chain_sg = cp->sg; | |
2124 | temp64 = le64_to_cpu(chain_sg->address); | |
a736e9b6 | 2125 | chain_size = le32_to_cpu(cp->sg[0].length); |
d9a729f3 WS |
2126 | pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE); |
2127 | } | |
2128 | ||
e2bea6df | 2129 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
2130 | struct CommandList *c) |
2131 | { | |
2132 | struct SGDescriptor *chain_sg, *chain_block; | |
2133 | u64 temp64; | |
50a0decf | 2134 | u32 chain_len; |
33a2ffce SC |
2135 | |
2136 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
2137 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
50a0decf SC |
2138 | chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); |
2139 | chain_len = sizeof(*chain_sg) * | |
2b08b3e9 | 2140 | (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); |
50a0decf SC |
2141 | chain_sg->Len = cpu_to_le32(chain_len); |
2142 | temp64 = pci_map_single(h->pdev, chain_block, chain_len, | |
33a2ffce | 2143 | PCI_DMA_TODEVICE); |
e2bea6df SC |
2144 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
2145 | /* prevent subsequent unmapping */ | |
50a0decf | 2146 | chain_sg->Addr = cpu_to_le64(0); |
e2bea6df SC |
2147 | return -1; |
2148 | } | |
50a0decf | 2149 | chain_sg->Addr = cpu_to_le64(temp64); |
e2bea6df | 2150 | return 0; |
33a2ffce SC |
2151 | } |
2152 | ||
2153 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
2154 | struct CommandList *c) | |
2155 | { | |
2156 | struct SGDescriptor *chain_sg; | |
33a2ffce | 2157 | |
50a0decf | 2158 | if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) |
33a2ffce SC |
2159 | return; |
2160 | ||
2161 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
50a0decf SC |
2162 | pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr), |
2163 | le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE); | |
33a2ffce SC |
2164 | } |
2165 | ||
a09c1441 ST |
2166 | |
2167 | /* Decode the various types of errors on ioaccel2 path. | |
2168 | * Return 1 for any error that should generate a RAID path retry. | |
2169 | * Return 0 for errors that don't require a RAID path retry. | |
2170 | */ | |
2171 | static int handle_ioaccel_mode2_error(struct ctlr_info *h, | |
c349775e ST |
2172 | struct CommandList *c, |
2173 | struct scsi_cmnd *cmd, | |
2174 | struct io_accel2_cmd *c2) | |
2175 | { | |
2176 | int data_len; | |
a09c1441 | 2177 | int retry = 0; |
c40820d5 | 2178 | u32 ioaccel2_resid = 0; |
c349775e ST |
2179 | |
2180 | switch (c2->error_data.serv_response) { | |
2181 | case IOACCEL2_SERV_RESPONSE_COMPLETE: | |
2182 | switch (c2->error_data.status) { | |
2183 | case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: | |
2184 | break; | |
2185 | case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: | |
ee6b1889 | 2186 | cmd->result |= SAM_STAT_CHECK_CONDITION; |
c349775e | 2187 | if (c2->error_data.data_present != |
ee6b1889 SC |
2188 | IOACCEL2_SENSE_DATA_PRESENT) { |
2189 | memset(cmd->sense_buffer, 0, | |
2190 | SCSI_SENSE_BUFFERSIZE); | |
c349775e | 2191 | break; |
ee6b1889 | 2192 | } |
c349775e ST |
2193 | /* copy the sense data */ |
2194 | data_len = c2->error_data.sense_data_len; | |
2195 | if (data_len > SCSI_SENSE_BUFFERSIZE) | |
2196 | data_len = SCSI_SENSE_BUFFERSIZE; | |
2197 | if (data_len > sizeof(c2->error_data.sense_data_buff)) | |
2198 | data_len = | |
2199 | sizeof(c2->error_data.sense_data_buff); | |
2200 | memcpy(cmd->sense_buffer, | |
2201 | c2->error_data.sense_data_buff, data_len); | |
a09c1441 | 2202 | retry = 1; |
c349775e ST |
2203 | break; |
2204 | case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: | |
a09c1441 | 2205 | retry = 1; |
c349775e ST |
2206 | break; |
2207 | case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: | |
a09c1441 | 2208 | retry = 1; |
c349775e ST |
2209 | break; |
2210 | case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: | |
4a8da22b | 2211 | retry = 1; |
c349775e ST |
2212 | break; |
2213 | case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: | |
a09c1441 | 2214 | retry = 1; |
c349775e ST |
2215 | break; |
2216 | default: | |
a09c1441 | 2217 | retry = 1; |
c349775e ST |
2218 | break; |
2219 | } | |
2220 | break; | |
2221 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
c40820d5 JH |
2222 | switch (c2->error_data.status) { |
2223 | case IOACCEL2_STATUS_SR_IO_ERROR: | |
2224 | case IOACCEL2_STATUS_SR_IO_ABORTED: | |
2225 | case IOACCEL2_STATUS_SR_OVERRUN: | |
2226 | retry = 1; | |
2227 | break; | |
2228 | case IOACCEL2_STATUS_SR_UNDERRUN: | |
2229 | cmd->result = (DID_OK << 16); /* host byte */ | |
2230 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
2231 | ioaccel2_resid = get_unaligned_le32( | |
2232 | &c2->error_data.resid_cnt[0]); | |
2233 | scsi_set_resid(cmd, ioaccel2_resid); | |
2234 | break; | |
2235 | case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: | |
2236 | case IOACCEL2_STATUS_SR_INVALID_DEVICE: | |
2237 | case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: | |
2238 | /* We will get an event from ctlr to trigger rescan */ | |
2239 | retry = 1; | |
2240 | break; | |
2241 | default: | |
2242 | retry = 1; | |
c40820d5 | 2243 | } |
c349775e ST |
2244 | break; |
2245 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
2246 | break; | |
2247 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
2248 | break; | |
2249 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
a09c1441 | 2250 | retry = 1; |
c349775e ST |
2251 | break; |
2252 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
c349775e ST |
2253 | break; |
2254 | default: | |
a09c1441 | 2255 | retry = 1; |
c349775e ST |
2256 | break; |
2257 | } | |
a09c1441 ST |
2258 | |
2259 | return retry; /* retry on raid path? */ | |
c349775e ST |
2260 | } |
2261 | ||
a58e7e53 WS |
2262 | static void hpsa_cmd_resolve_events(struct ctlr_info *h, |
2263 | struct CommandList *c) | |
2264 | { | |
d604f533 WS |
2265 | bool do_wake = false; |
2266 | ||
a58e7e53 WS |
2267 | /* |
2268 | * Prevent the following race in the abort handler: | |
2269 | * | |
2270 | * 1. LLD is requested to abort a SCSI command | |
2271 | * 2. The SCSI command completes | |
2272 | * 3. The struct CommandList associated with step 2 is made available | |
2273 | * 4. New I/O request to LLD to another LUN re-uses struct CommandList | |
2274 | * 5. Abort handler follows scsi_cmnd->host_scribble and | |
2275 | * finds struct CommandList and tries to aborts it | |
2276 | * Now we have aborted the wrong command. | |
2277 | * | |
d604f533 WS |
2278 | * Reset c->scsi_cmd here so that the abort or reset handler will know |
2279 | * this command has completed. Then, check to see if the handler is | |
a58e7e53 WS |
2280 | * waiting for this command, and, if so, wake it. |
2281 | */ | |
2282 | c->scsi_cmd = SCSI_CMD_IDLE; | |
d604f533 | 2283 | mb(); /* Declare command idle before checking for pending events. */ |
a58e7e53 | 2284 | if (c->abort_pending) { |
d604f533 | 2285 | do_wake = true; |
a58e7e53 | 2286 | c->abort_pending = false; |
a58e7e53 | 2287 | } |
d604f533 WS |
2288 | if (c->reset_pending) { |
2289 | unsigned long flags; | |
2290 | struct hpsa_scsi_dev_t *dev; | |
2291 | ||
2292 | /* | |
2293 | * There appears to be a reset pending; lock the lock and | |
2294 | * reconfirm. If so, then decrement the count of outstanding | |
2295 | * commands and wake the reset command if this is the last one. | |
2296 | */ | |
2297 | spin_lock_irqsave(&h->lock, flags); | |
2298 | dev = c->reset_pending; /* Re-fetch under the lock. */ | |
2299 | if (dev && atomic_dec_and_test(&dev->reset_cmds_out)) | |
2300 | do_wake = true; | |
2301 | c->reset_pending = NULL; | |
2302 | spin_unlock_irqrestore(&h->lock, flags); | |
2303 | } | |
2304 | ||
2305 | if (do_wake) | |
2306 | wake_up_all(&h->event_sync_wait_queue); | |
a58e7e53 WS |
2307 | } |
2308 | ||
73153fe5 WS |
2309 | static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, |
2310 | struct CommandList *c) | |
2311 | { | |
2312 | hpsa_cmd_resolve_events(h, c); | |
2313 | cmd_tagged_free(h, c); | |
2314 | } | |
2315 | ||
8a0ff92c WS |
2316 | static void hpsa_cmd_free_and_done(struct ctlr_info *h, |
2317 | struct CommandList *c, struct scsi_cmnd *cmd) | |
2318 | { | |
73153fe5 | 2319 | hpsa_cmd_resolve_and_free(h, c); |
8a0ff92c WS |
2320 | cmd->scsi_done(cmd); |
2321 | } | |
2322 | ||
2323 | static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) | |
2324 | { | |
2325 | INIT_WORK(&c->work, hpsa_command_resubmit_worker); | |
2326 | queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); | |
2327 | } | |
2328 | ||
a58e7e53 WS |
2329 | static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd) |
2330 | { | |
2331 | cmd->result = DID_ABORT << 16; | |
2332 | } | |
2333 | ||
2334 | static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c, | |
2335 | struct scsi_cmnd *cmd) | |
2336 | { | |
2337 | hpsa_set_scsi_cmd_aborted(cmd); | |
2338 | dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n", | |
2339 | c->Request.CDB, c->err_info->ScsiStatus); | |
73153fe5 | 2340 | hpsa_cmd_resolve_and_free(h, c); |
a58e7e53 WS |
2341 | } |
2342 | ||
c349775e ST |
2343 | static void process_ioaccel2_completion(struct ctlr_info *h, |
2344 | struct CommandList *c, struct scsi_cmnd *cmd, | |
2345 | struct hpsa_scsi_dev_t *dev) | |
2346 | { | |
2347 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2348 | ||
2349 | /* check for good status */ | |
2350 | if (likely(c2->error_data.serv_response == 0 && | |
8a0ff92c WS |
2351 | c2->error_data.status == 0)) |
2352 | return hpsa_cmd_free_and_done(h, c, cmd); | |
c349775e | 2353 | |
8a0ff92c WS |
2354 | /* |
2355 | * Any RAID offload error results in retry which will use | |
c349775e ST |
2356 | * the normal I/O path so the controller can handle whatever's |
2357 | * wrong. | |
2358 | */ | |
f3f01730 | 2359 | if (is_logical_device(dev) && |
c349775e ST |
2360 | c2->error_data.serv_response == |
2361 | IOACCEL2_SERV_RESPONSE_FAILURE) { | |
080ef1cc DB |
2362 | if (c2->error_data.status == |
2363 | IOACCEL2_STATUS_SR_IOACCEL_DISABLED) | |
2364 | dev->offload_enabled = 0; | |
8a0ff92c WS |
2365 | |
2366 | return hpsa_retry_cmd(h, c); | |
a09c1441 | 2367 | } |
080ef1cc DB |
2368 | |
2369 | if (handle_ioaccel_mode2_error(h, c, cmd, c2)) | |
8a0ff92c | 2370 | return hpsa_retry_cmd(h, c); |
080ef1cc | 2371 | |
8a0ff92c | 2372 | return hpsa_cmd_free_and_done(h, c, cmd); |
c349775e ST |
2373 | } |
2374 | ||
9437ac43 SC |
2375 | /* Returns 0 on success, < 0 otherwise. */ |
2376 | static int hpsa_evaluate_tmf_status(struct ctlr_info *h, | |
2377 | struct CommandList *cp) | |
2378 | { | |
2379 | u8 tmf_status = cp->err_info->ScsiStatus; | |
2380 | ||
2381 | switch (tmf_status) { | |
2382 | case CISS_TMF_COMPLETE: | |
2383 | /* | |
2384 | * CISS_TMF_COMPLETE never happens, instead, | |
2385 | * ei->CommandStatus == 0 for this case. | |
2386 | */ | |
2387 | case CISS_TMF_SUCCESS: | |
2388 | return 0; | |
2389 | case CISS_TMF_INVALID_FRAME: | |
2390 | case CISS_TMF_NOT_SUPPORTED: | |
2391 | case CISS_TMF_FAILED: | |
2392 | case CISS_TMF_WRONG_LUN: | |
2393 | case CISS_TMF_OVERLAPPED_TAG: | |
2394 | break; | |
2395 | default: | |
2396 | dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", | |
2397 | tmf_status); | |
2398 | break; | |
2399 | } | |
2400 | return -tmf_status; | |
2401 | } | |
2402 | ||
1fb011fb | 2403 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
2404 | { |
2405 | struct scsi_cmnd *cmd; | |
2406 | struct ctlr_info *h; | |
2407 | struct ErrorInfo *ei; | |
283b4a9b | 2408 | struct hpsa_scsi_dev_t *dev; |
d9a729f3 | 2409 | struct io_accel2_cmd *c2; |
edd16368 | 2410 | |
9437ac43 SC |
2411 | u8 sense_key; |
2412 | u8 asc; /* additional sense code */ | |
2413 | u8 ascq; /* additional sense code qualifier */ | |
db111e18 | 2414 | unsigned long sense_data_size; |
edd16368 SC |
2415 | |
2416 | ei = cp->err_info; | |
7fa3030c | 2417 | cmd = cp->scsi_cmd; |
edd16368 | 2418 | h = cp->h; |
283b4a9b | 2419 | dev = cmd->device->hostdata; |
d9a729f3 | 2420 | c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; |
edd16368 SC |
2421 | |
2422 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c | 2423 | if ((cp->cmd_type == CMD_SCSI) && |
2b08b3e9 | 2424 | (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) |
33a2ffce | 2425 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 | 2426 | |
d9a729f3 WS |
2427 | if ((cp->cmd_type == CMD_IOACCEL2) && |
2428 | (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) | |
2429 | hpsa_unmap_ioaccel2_sg_chain_block(h, c2); | |
2430 | ||
edd16368 SC |
2431 | cmd->result = (DID_OK << 16); /* host byte */ |
2432 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
c349775e | 2433 | |
03383736 DB |
2434 | if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) |
2435 | atomic_dec(&cp->phys_disk->ioaccel_cmds_out); | |
2436 | ||
25163bd5 WS |
2437 | /* |
2438 | * We check for lockup status here as it may be set for | |
2439 | * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by | |
2440 | * fail_all_oustanding_cmds() | |
2441 | */ | |
2442 | if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { | |
2443 | /* DID_NO_CONNECT will prevent a retry */ | |
2444 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 2445 | return hpsa_cmd_free_and_done(h, cp, cmd); |
25163bd5 WS |
2446 | } |
2447 | ||
d604f533 WS |
2448 | if ((unlikely(hpsa_is_pending_event(cp)))) { |
2449 | if (cp->reset_pending) | |
2450 | return hpsa_cmd_resolve_and_free(h, cp); | |
2451 | if (cp->abort_pending) | |
2452 | return hpsa_cmd_abort_and_free(h, cp, cmd); | |
2453 | } | |
2454 | ||
c349775e ST |
2455 | if (cp->cmd_type == CMD_IOACCEL2) |
2456 | return process_ioaccel2_completion(h, cp, cmd, dev); | |
2457 | ||
6aa4c361 | 2458 | scsi_set_resid(cmd, ei->ResidualCnt); |
8a0ff92c WS |
2459 | if (ei->CommandStatus == 0) |
2460 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
6aa4c361 | 2461 | |
e1f7de0c MG |
2462 | /* For I/O accelerator commands, copy over some fields to the normal |
2463 | * CISS header used below for error handling. | |
2464 | */ | |
2465 | if (cp->cmd_type == CMD_IOACCEL1) { | |
2466 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
2b08b3e9 DB |
2467 | cp->Header.SGList = scsi_sg_count(cmd); |
2468 | cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); | |
2469 | cp->Request.CDBLen = le16_to_cpu(c->io_flags) & | |
2470 | IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
50a0decf | 2471 | cp->Header.tag = c->tag; |
e1f7de0c MG |
2472 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); |
2473 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
283b4a9b SC |
2474 | |
2475 | /* Any RAID offload error results in retry which will use | |
2476 | * the normal I/O path so the controller can handle whatever's | |
2477 | * wrong. | |
2478 | */ | |
f3f01730 | 2479 | if (is_logical_device(dev)) { |
283b4a9b SC |
2480 | if (ei->CommandStatus == CMD_IOACCEL_DISABLED) |
2481 | dev->offload_enabled = 0; | |
d604f533 | 2482 | return hpsa_retry_cmd(h, cp); |
283b4a9b | 2483 | } |
e1f7de0c MG |
2484 | } |
2485 | ||
edd16368 SC |
2486 | /* an error has occurred */ |
2487 | switch (ei->CommandStatus) { | |
2488 | ||
2489 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2490 | cmd->result |= ei->ScsiStatus; |
2491 | /* copy the sense data */ | |
2492 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) | |
2493 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
2494 | else | |
2495 | sense_data_size = sizeof(ei->SenseInfo); | |
2496 | if (ei->SenseLen < sense_data_size) | |
2497 | sense_data_size = ei->SenseLen; | |
2498 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
2499 | if (ei->ScsiStatus) | |
2500 | decode_sense_data(ei->SenseInfo, sense_data_size, | |
2501 | &sense_key, &asc, &ascq); | |
edd16368 | 2502 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { |
1d3b3609 | 2503 | if (sense_key == ABORTED_COMMAND) { |
2e311fba | 2504 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 MG |
2505 | break; |
2506 | } | |
edd16368 SC |
2507 | break; |
2508 | } | |
edd16368 SC |
2509 | /* Problem was not a check condition |
2510 | * Pass it up to the upper layers... | |
2511 | */ | |
2512 | if (ei->ScsiStatus) { | |
2513 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
2514 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
2515 | "Returning result: 0x%x\n", | |
2516 | cp, ei->ScsiStatus, | |
2517 | sense_key, asc, ascq, | |
2518 | cmd->result); | |
2519 | } else { /* scsi status is zero??? How??? */ | |
2520 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
2521 | "Returning no connection.\n", cp), | |
2522 | ||
2523 | /* Ordinarily, this case should never happen, | |
2524 | * but there is a bug in some released firmware | |
2525 | * revisions that allows it to happen if, for | |
2526 | * example, a 4100 backplane loses power and | |
2527 | * the tape drive is in it. We assume that | |
2528 | * it's a fatal error of some kind because we | |
2529 | * can't show that it wasn't. We will make it | |
2530 | * look like selection timeout since that is | |
2531 | * the most common reason for this to occur, | |
2532 | * and it's severe enough. | |
2533 | */ | |
2534 | ||
2535 | cmd->result = DID_NO_CONNECT << 16; | |
2536 | } | |
2537 | break; | |
2538 | ||
2539 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
2540 | break; | |
2541 | case CMD_DATA_OVERRUN: | |
f42e81e1 SC |
2542 | dev_warn(&h->pdev->dev, |
2543 | "CDB %16phN data overrun\n", cp->Request.CDB); | |
edd16368 SC |
2544 | break; |
2545 | case CMD_INVALID: { | |
2546 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
2547 | print_cmd(cp); */ | |
2548 | /* We get CMD_INVALID if you address a non-existent device | |
2549 | * instead of a selection timeout (no response). You will | |
2550 | * see this if you yank out a drive, then try to access it. | |
2551 | * This is kind of a shame because it means that any other | |
2552 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
2553 | * missing target. */ | |
2554 | cmd->result = DID_NO_CONNECT << 16; | |
2555 | } | |
2556 | break; | |
2557 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 2558 | cmd->result = DID_ERROR << 16; |
f42e81e1 SC |
2559 | dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", |
2560 | cp->Request.CDB); | |
edd16368 SC |
2561 | break; |
2562 | case CMD_HARDWARE_ERR: | |
2563 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2564 | dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", |
2565 | cp->Request.CDB); | |
edd16368 SC |
2566 | break; |
2567 | case CMD_CONNECTION_LOST: | |
2568 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2569 | dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", |
2570 | cp->Request.CDB); | |
edd16368 SC |
2571 | break; |
2572 | case CMD_ABORTED: | |
a58e7e53 WS |
2573 | /* Return now to avoid calling scsi_done(). */ |
2574 | return hpsa_cmd_abort_and_free(h, cp, cmd); | |
edd16368 SC |
2575 | case CMD_ABORT_FAILED: |
2576 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2577 | dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", |
2578 | cp->Request.CDB); | |
edd16368 SC |
2579 | break; |
2580 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 | 2581 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
f42e81e1 SC |
2582 | dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", |
2583 | cp->Request.CDB); | |
edd16368 SC |
2584 | break; |
2585 | case CMD_TIMEOUT: | |
2586 | cmd->result = DID_TIME_OUT << 16; | |
f42e81e1 SC |
2587 | dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", |
2588 | cp->Request.CDB); | |
edd16368 | 2589 | break; |
1d5e2ed0 SC |
2590 | case CMD_UNABORTABLE: |
2591 | cmd->result = DID_ERROR << 16; | |
2592 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
2593 | break; | |
9437ac43 SC |
2594 | case CMD_TMF_STATUS: |
2595 | if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ | |
2596 | cmd->result = DID_ERROR << 16; | |
2597 | break; | |
283b4a9b SC |
2598 | case CMD_IOACCEL_DISABLED: |
2599 | /* This only handles the direct pass-through case since RAID | |
2600 | * offload is handled above. Just attempt a retry. | |
2601 | */ | |
2602 | cmd->result = DID_SOFT_ERROR << 16; | |
2603 | dev_warn(&h->pdev->dev, | |
2604 | "cp %p had HP SSD Smart Path error\n", cp); | |
2605 | break; | |
edd16368 SC |
2606 | default: |
2607 | cmd->result = DID_ERROR << 16; | |
2608 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
2609 | cp, ei->CommandStatus); | |
2610 | } | |
8a0ff92c WS |
2611 | |
2612 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
edd16368 SC |
2613 | } |
2614 | ||
edd16368 SC |
2615 | static void hpsa_pci_unmap(struct pci_dev *pdev, |
2616 | struct CommandList *c, int sg_used, int data_direction) | |
2617 | { | |
2618 | int i; | |
edd16368 | 2619 | |
50a0decf SC |
2620 | for (i = 0; i < sg_used; i++) |
2621 | pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr), | |
2622 | le32_to_cpu(c->SG[i].Len), | |
2623 | data_direction); | |
edd16368 SC |
2624 | } |
2625 | ||
a2dac136 | 2626 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
2627 | struct CommandList *cp, |
2628 | unsigned char *buf, | |
2629 | size_t buflen, | |
2630 | int data_direction) | |
2631 | { | |
01a02ffc | 2632 | u64 addr64; |
edd16368 SC |
2633 | |
2634 | if (buflen == 0 || data_direction == PCI_DMA_NONE) { | |
2635 | cp->Header.SGList = 0; | |
50a0decf | 2636 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2637 | return 0; |
edd16368 SC |
2638 | } |
2639 | ||
50a0decf | 2640 | addr64 = pci_map_single(pdev, buf, buflen, data_direction); |
eceaae18 | 2641 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 2642 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 | 2643 | cp->Header.SGList = 0; |
50a0decf | 2644 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2645 | return -1; |
eceaae18 | 2646 | } |
50a0decf SC |
2647 | cp->SG[0].Addr = cpu_to_le64(addr64); |
2648 | cp->SG[0].Len = cpu_to_le32(buflen); | |
2649 | cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ | |
2650 | cp->Header.SGList = 1; /* no. SGs contig in this cmd */ | |
2651 | cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ | |
a2dac136 | 2652 | return 0; |
edd16368 SC |
2653 | } |
2654 | ||
25163bd5 WS |
2655 | #define NO_TIMEOUT ((unsigned long) -1) |
2656 | #define DEFAULT_TIMEOUT 30000 /* milliseconds */ | |
2657 | static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
2658 | struct CommandList *c, int reply_queue, unsigned long timeout_msecs) | |
edd16368 SC |
2659 | { |
2660 | DECLARE_COMPLETION_ONSTACK(wait); | |
2661 | ||
2662 | c->waiting = &wait; | |
25163bd5 WS |
2663 | __enqueue_cmd_and_start_io(h, c, reply_queue); |
2664 | if (timeout_msecs == NO_TIMEOUT) { | |
2665 | /* TODO: get rid of this no-timeout thing */ | |
2666 | wait_for_completion_io(&wait); | |
2667 | return IO_OK; | |
2668 | } | |
2669 | if (!wait_for_completion_io_timeout(&wait, | |
2670 | msecs_to_jiffies(timeout_msecs))) { | |
2671 | dev_warn(&h->pdev->dev, "Command timed out.\n"); | |
2672 | return -ETIMEDOUT; | |
2673 | } | |
2674 | return IO_OK; | |
2675 | } | |
2676 | ||
2677 | static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, | |
2678 | int reply_queue, unsigned long timeout_msecs) | |
2679 | { | |
2680 | if (unlikely(lockup_detected(h))) { | |
2681 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; | |
2682 | return IO_OK; | |
2683 | } | |
2684 | return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); | |
edd16368 SC |
2685 | } |
2686 | ||
094963da SC |
2687 | static u32 lockup_detected(struct ctlr_info *h) |
2688 | { | |
2689 | int cpu; | |
2690 | u32 rc, *lockup_detected; | |
2691 | ||
2692 | cpu = get_cpu(); | |
2693 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
2694 | rc = *lockup_detected; | |
2695 | put_cpu(); | |
2696 | return rc; | |
2697 | } | |
2698 | ||
9c2fc160 | 2699 | #define MAX_DRIVER_CMD_RETRIES 25 |
25163bd5 WS |
2700 | static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
2701 | struct CommandList *c, int data_direction, unsigned long timeout_msecs) | |
edd16368 | 2702 | { |
9c2fc160 | 2703 | int backoff_time = 10, retry_count = 0; |
25163bd5 | 2704 | int rc; |
edd16368 SC |
2705 | |
2706 | do { | |
7630abd0 | 2707 | memset(c->err_info, 0, sizeof(*c->err_info)); |
25163bd5 WS |
2708 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
2709 | timeout_msecs); | |
2710 | if (rc) | |
2711 | break; | |
edd16368 | 2712 | retry_count++; |
9c2fc160 SC |
2713 | if (retry_count > 3) { |
2714 | msleep(backoff_time); | |
2715 | if (backoff_time < 1000) | |
2716 | backoff_time *= 2; | |
2717 | } | |
852af20a | 2718 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
2719 | check_for_busy(h, c)) && |
2720 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 | 2721 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
25163bd5 WS |
2722 | if (retry_count > MAX_DRIVER_CMD_RETRIES) |
2723 | rc = -EIO; | |
2724 | return rc; | |
edd16368 SC |
2725 | } |
2726 | ||
d1e8beac SC |
2727 | static void hpsa_print_cmd(struct ctlr_info *h, char *txt, |
2728 | struct CommandList *c) | |
edd16368 | 2729 | { |
d1e8beac SC |
2730 | const u8 *cdb = c->Request.CDB; |
2731 | const u8 *lun = c->Header.LUN.LunAddrBytes; | |
2732 | ||
2733 | dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x" | |
2734 | " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
2735 | txt, lun[0], lun[1], lun[2], lun[3], | |
2736 | lun[4], lun[5], lun[6], lun[7], | |
2737 | cdb[0], cdb[1], cdb[2], cdb[3], | |
2738 | cdb[4], cdb[5], cdb[6], cdb[7], | |
2739 | cdb[8], cdb[9], cdb[10], cdb[11], | |
2740 | cdb[12], cdb[13], cdb[14], cdb[15]); | |
2741 | } | |
2742 | ||
2743 | static void hpsa_scsi_interpret_error(struct ctlr_info *h, | |
2744 | struct CommandList *cp) | |
2745 | { | |
2746 | const struct ErrorInfo *ei = cp->err_info; | |
edd16368 | 2747 | struct device *d = &cp->h->pdev->dev; |
9437ac43 SC |
2748 | u8 sense_key, asc, ascq; |
2749 | int sense_len; | |
edd16368 | 2750 | |
edd16368 SC |
2751 | switch (ei->CommandStatus) { |
2752 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2753 | if (ei->SenseLen > sizeof(ei->SenseInfo)) |
2754 | sense_len = sizeof(ei->SenseInfo); | |
2755 | else | |
2756 | sense_len = ei->SenseLen; | |
2757 | decode_sense_data(ei->SenseInfo, sense_len, | |
2758 | &sense_key, &asc, &ascq); | |
d1e8beac SC |
2759 | hpsa_print_cmd(h, "SCSI status", cp); |
2760 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) | |
9437ac43 SC |
2761 | dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", |
2762 | sense_key, asc, ascq); | |
d1e8beac | 2763 | else |
9437ac43 | 2764 | dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); |
edd16368 SC |
2765 | if (ei->ScsiStatus == 0) |
2766 | dev_warn(d, "SCSI status is abnormally zero. " | |
2767 | "(probably indicates selection timeout " | |
2768 | "reported incorrectly due to a known " | |
2769 | "firmware bug, circa July, 2001.)\n"); | |
2770 | break; | |
2771 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
edd16368 SC |
2772 | break; |
2773 | case CMD_DATA_OVERRUN: | |
d1e8beac | 2774 | hpsa_print_cmd(h, "overrun condition", cp); |
edd16368 SC |
2775 | break; |
2776 | case CMD_INVALID: { | |
2777 | /* controller unfortunately reports SCSI passthru's | |
2778 | * to non-existent targets as invalid commands. | |
2779 | */ | |
d1e8beac SC |
2780 | hpsa_print_cmd(h, "invalid command", cp); |
2781 | dev_warn(d, "probably means device no longer present\n"); | |
edd16368 SC |
2782 | } |
2783 | break; | |
2784 | case CMD_PROTOCOL_ERR: | |
d1e8beac | 2785 | hpsa_print_cmd(h, "protocol error", cp); |
edd16368 SC |
2786 | break; |
2787 | case CMD_HARDWARE_ERR: | |
d1e8beac | 2788 | hpsa_print_cmd(h, "hardware error", cp); |
edd16368 SC |
2789 | break; |
2790 | case CMD_CONNECTION_LOST: | |
d1e8beac | 2791 | hpsa_print_cmd(h, "connection lost", cp); |
edd16368 SC |
2792 | break; |
2793 | case CMD_ABORTED: | |
d1e8beac | 2794 | hpsa_print_cmd(h, "aborted", cp); |
edd16368 SC |
2795 | break; |
2796 | case CMD_ABORT_FAILED: | |
d1e8beac | 2797 | hpsa_print_cmd(h, "abort failed", cp); |
edd16368 SC |
2798 | break; |
2799 | case CMD_UNSOLICITED_ABORT: | |
d1e8beac | 2800 | hpsa_print_cmd(h, "unsolicited abort", cp); |
edd16368 SC |
2801 | break; |
2802 | case CMD_TIMEOUT: | |
d1e8beac | 2803 | hpsa_print_cmd(h, "timed out", cp); |
edd16368 | 2804 | break; |
1d5e2ed0 | 2805 | case CMD_UNABORTABLE: |
d1e8beac | 2806 | hpsa_print_cmd(h, "unabortable", cp); |
1d5e2ed0 | 2807 | break; |
25163bd5 WS |
2808 | case CMD_CTLR_LOCKUP: |
2809 | hpsa_print_cmd(h, "controller lockup detected", cp); | |
2810 | break; | |
edd16368 | 2811 | default: |
d1e8beac SC |
2812 | hpsa_print_cmd(h, "unknown status", cp); |
2813 | dev_warn(d, "Unknown command status %x\n", | |
edd16368 SC |
2814 | ei->CommandStatus); |
2815 | } | |
2816 | } | |
2817 | ||
2818 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, | |
b7bb24eb | 2819 | u16 page, unsigned char *buf, |
edd16368 SC |
2820 | unsigned char bufsize) |
2821 | { | |
2822 | int rc = IO_OK; | |
2823 | struct CommandList *c; | |
2824 | struct ErrorInfo *ei; | |
2825 | ||
45fcb86e | 2826 | c = cmd_alloc(h); |
edd16368 | 2827 | |
a2dac136 SC |
2828 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
2829 | page, scsi3addr, TYPE_CMD)) { | |
2830 | rc = -1; | |
2831 | goto out; | |
2832 | } | |
25163bd5 | 2833 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
c448ecfa | 2834 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
25163bd5 WS |
2835 | if (rc) |
2836 | goto out; | |
edd16368 SC |
2837 | ei = c->err_info; |
2838 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 2839 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2840 | rc = -1; |
2841 | } | |
a2dac136 | 2842 | out: |
45fcb86e | 2843 | cmd_free(h, c); |
edd16368 SC |
2844 | return rc; |
2845 | } | |
2846 | ||
bf711ac6 | 2847 | static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
25163bd5 | 2848 | u8 reset_type, int reply_queue) |
edd16368 SC |
2849 | { |
2850 | int rc = IO_OK; | |
2851 | struct CommandList *c; | |
2852 | struct ErrorInfo *ei; | |
2853 | ||
45fcb86e | 2854 | c = cmd_alloc(h); |
edd16368 | 2855 | |
edd16368 | 2856 | |
a2dac136 | 2857 | /* fill_cmd can't fail here, no data buffer to map. */ |
0b9b7b6e | 2858 | (void) fill_cmd(c, reset_type, h, NULL, 0, 0, |
bf711ac6 | 2859 | scsi3addr, TYPE_MSG); |
c448ecfa | 2860 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); |
25163bd5 WS |
2861 | if (rc) { |
2862 | dev_warn(&h->pdev->dev, "Failed to send reset command\n"); | |
2863 | goto out; | |
2864 | } | |
edd16368 SC |
2865 | /* no unmap needed here because no data xfer. */ |
2866 | ||
2867 | ei = c->err_info; | |
2868 | if (ei->CommandStatus != 0) { | |
d1e8beac | 2869 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2870 | rc = -1; |
2871 | } | |
25163bd5 | 2872 | out: |
45fcb86e | 2873 | cmd_free(h, c); |
edd16368 SC |
2874 | return rc; |
2875 | } | |
2876 | ||
d604f533 WS |
2877 | static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, |
2878 | struct hpsa_scsi_dev_t *dev, | |
2879 | unsigned char *scsi3addr) | |
2880 | { | |
2881 | int i; | |
2882 | bool match = false; | |
2883 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2884 | struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; | |
2885 | ||
2886 | if (hpsa_is_cmd_idle(c)) | |
2887 | return false; | |
2888 | ||
2889 | switch (c->cmd_type) { | |
2890 | case CMD_SCSI: | |
2891 | case CMD_IOCTL_PEND: | |
2892 | match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, | |
2893 | sizeof(c->Header.LUN.LunAddrBytes)); | |
2894 | break; | |
2895 | ||
2896 | case CMD_IOACCEL1: | |
2897 | case CMD_IOACCEL2: | |
2898 | if (c->phys_disk == dev) { | |
2899 | /* HBA mode match */ | |
2900 | match = true; | |
2901 | } else { | |
2902 | /* Possible RAID mode -- check each phys dev. */ | |
2903 | /* FIXME: Do we need to take out a lock here? If | |
2904 | * so, we could just call hpsa_get_pdisk_of_ioaccel2() | |
2905 | * instead. */ | |
2906 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
2907 | /* FIXME: an alternate test might be | |
2908 | * | |
2909 | * match = dev->phys_disk[i]->ioaccel_handle | |
2910 | * == c2->scsi_nexus; */ | |
2911 | match = dev->phys_disk[i] == c->phys_disk; | |
2912 | } | |
2913 | } | |
2914 | break; | |
2915 | ||
2916 | case IOACCEL2_TMF: | |
2917 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
2918 | match = dev->phys_disk[i]->ioaccel_handle == | |
2919 | le32_to_cpu(ac->it_nexus); | |
2920 | } | |
2921 | break; | |
2922 | ||
2923 | case 0: /* The command is in the middle of being initialized. */ | |
2924 | match = false; | |
2925 | break; | |
2926 | ||
2927 | default: | |
2928 | dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", | |
2929 | c->cmd_type); | |
2930 | BUG(); | |
2931 | } | |
2932 | ||
2933 | return match; | |
2934 | } | |
2935 | ||
2936 | static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, | |
2937 | unsigned char *scsi3addr, u8 reset_type, int reply_queue) | |
2938 | { | |
2939 | int i; | |
2940 | int rc = 0; | |
2941 | ||
2942 | /* We can really only handle one reset at a time */ | |
2943 | if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { | |
2944 | dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); | |
2945 | return -EINTR; | |
2946 | } | |
2947 | ||
2948 | BUG_ON(atomic_read(&dev->reset_cmds_out) != 0); | |
2949 | ||
2950 | for (i = 0; i < h->nr_cmds; i++) { | |
2951 | struct CommandList *c = h->cmd_pool + i; | |
2952 | int refcount = atomic_inc_return(&c->refcount); | |
2953 | ||
2954 | if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) { | |
2955 | unsigned long flags; | |
2956 | ||
2957 | /* | |
2958 | * Mark the target command as having a reset pending, | |
2959 | * then lock a lock so that the command cannot complete | |
2960 | * while we're considering it. If the command is not | |
2961 | * idle then count it; otherwise revoke the event. | |
2962 | */ | |
2963 | c->reset_pending = dev; | |
2964 | spin_lock_irqsave(&h->lock, flags); /* Implied MB */ | |
2965 | if (!hpsa_is_cmd_idle(c)) | |
2966 | atomic_inc(&dev->reset_cmds_out); | |
2967 | else | |
2968 | c->reset_pending = NULL; | |
2969 | spin_unlock_irqrestore(&h->lock, flags); | |
2970 | } | |
2971 | ||
2972 | cmd_free(h, c); | |
2973 | } | |
2974 | ||
2975 | rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue); | |
2976 | if (!rc) | |
2977 | wait_event(h->event_sync_wait_queue, | |
2978 | atomic_read(&dev->reset_cmds_out) == 0 || | |
2979 | lockup_detected(h)); | |
2980 | ||
2981 | if (unlikely(lockup_detected(h))) { | |
77678d3a DB |
2982 | dev_warn(&h->pdev->dev, |
2983 | "Controller lockup detected during reset wait\n"); | |
2984 | rc = -ENODEV; | |
2985 | } | |
d604f533 WS |
2986 | |
2987 | if (unlikely(rc)) | |
2988 | atomic_set(&dev->reset_cmds_out, 0); | |
2989 | ||
2990 | mutex_unlock(&h->reset_mutex); | |
2991 | return rc; | |
2992 | } | |
2993 | ||
edd16368 SC |
2994 | static void hpsa_get_raid_level(struct ctlr_info *h, |
2995 | unsigned char *scsi3addr, unsigned char *raid_level) | |
2996 | { | |
2997 | int rc; | |
2998 | unsigned char *buf; | |
2999 | ||
3000 | *raid_level = RAID_UNKNOWN; | |
3001 | buf = kzalloc(64, GFP_KERNEL); | |
3002 | if (!buf) | |
3003 | return; | |
b7bb24eb | 3004 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64); |
edd16368 SC |
3005 | if (rc == 0) |
3006 | *raid_level = buf[8]; | |
3007 | if (*raid_level > RAID_UNKNOWN) | |
3008 | *raid_level = RAID_UNKNOWN; | |
3009 | kfree(buf); | |
3010 | return; | |
3011 | } | |
3012 | ||
283b4a9b SC |
3013 | #define HPSA_MAP_DEBUG |
3014 | #ifdef HPSA_MAP_DEBUG | |
3015 | static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, | |
3016 | struct raid_map_data *map_buff) | |
3017 | { | |
3018 | struct raid_map_disk_data *dd = &map_buff->data[0]; | |
3019 | int map, row, col; | |
3020 | u16 map_cnt, row_cnt, disks_per_row; | |
3021 | ||
3022 | if (rc != 0) | |
3023 | return; | |
3024 | ||
2ba8bfc8 SC |
3025 | /* Show details only if debugging has been activated. */ |
3026 | if (h->raid_offload_debug < 2) | |
3027 | return; | |
3028 | ||
283b4a9b SC |
3029 | dev_info(&h->pdev->dev, "structure_size = %u\n", |
3030 | le32_to_cpu(map_buff->structure_size)); | |
3031 | dev_info(&h->pdev->dev, "volume_blk_size = %u\n", | |
3032 | le32_to_cpu(map_buff->volume_blk_size)); | |
3033 | dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", | |
3034 | le64_to_cpu(map_buff->volume_blk_cnt)); | |
3035 | dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", | |
3036 | map_buff->phys_blk_shift); | |
3037 | dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", | |
3038 | map_buff->parity_rotation_shift); | |
3039 | dev_info(&h->pdev->dev, "strip_size = %u\n", | |
3040 | le16_to_cpu(map_buff->strip_size)); | |
3041 | dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", | |
3042 | le64_to_cpu(map_buff->disk_starting_blk)); | |
3043 | dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", | |
3044 | le64_to_cpu(map_buff->disk_blk_cnt)); | |
3045 | dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", | |
3046 | le16_to_cpu(map_buff->data_disks_per_row)); | |
3047 | dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", | |
3048 | le16_to_cpu(map_buff->metadata_disks_per_row)); | |
3049 | dev_info(&h->pdev->dev, "row_cnt = %u\n", | |
3050 | le16_to_cpu(map_buff->row_cnt)); | |
3051 | dev_info(&h->pdev->dev, "layout_map_count = %u\n", | |
3052 | le16_to_cpu(map_buff->layout_map_count)); | |
2b08b3e9 | 3053 | dev_info(&h->pdev->dev, "flags = 0x%x\n", |
dd0e19f3 | 3054 | le16_to_cpu(map_buff->flags)); |
2b08b3e9 DB |
3055 | dev_info(&h->pdev->dev, "encrypytion = %s\n", |
3056 | le16_to_cpu(map_buff->flags) & | |
3057 | RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); | |
dd0e19f3 ST |
3058 | dev_info(&h->pdev->dev, "dekindex = %u\n", |
3059 | le16_to_cpu(map_buff->dekindex)); | |
283b4a9b SC |
3060 | map_cnt = le16_to_cpu(map_buff->layout_map_count); |
3061 | for (map = 0; map < map_cnt; map++) { | |
3062 | dev_info(&h->pdev->dev, "Map%u:\n", map); | |
3063 | row_cnt = le16_to_cpu(map_buff->row_cnt); | |
3064 | for (row = 0; row < row_cnt; row++) { | |
3065 | dev_info(&h->pdev->dev, " Row%u:\n", row); | |
3066 | disks_per_row = | |
3067 | le16_to_cpu(map_buff->data_disks_per_row); | |
3068 | for (col = 0; col < disks_per_row; col++, dd++) | |
3069 | dev_info(&h->pdev->dev, | |
3070 | " D%02u: h=0x%04x xor=%u,%u\n", | |
3071 | col, dd->ioaccel_handle, | |
3072 | dd->xor_mult[0], dd->xor_mult[1]); | |
3073 | disks_per_row = | |
3074 | le16_to_cpu(map_buff->metadata_disks_per_row); | |
3075 | for (col = 0; col < disks_per_row; col++, dd++) | |
3076 | dev_info(&h->pdev->dev, | |
3077 | " M%02u: h=0x%04x xor=%u,%u\n", | |
3078 | col, dd->ioaccel_handle, | |
3079 | dd->xor_mult[0], dd->xor_mult[1]); | |
3080 | } | |
3081 | } | |
3082 | } | |
3083 | #else | |
3084 | static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, | |
3085 | __attribute__((unused)) int rc, | |
3086 | __attribute__((unused)) struct raid_map_data *map_buff) | |
3087 | { | |
3088 | } | |
3089 | #endif | |
3090 | ||
3091 | static int hpsa_get_raid_map(struct ctlr_info *h, | |
3092 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3093 | { | |
3094 | int rc = 0; | |
3095 | struct CommandList *c; | |
3096 | struct ErrorInfo *ei; | |
3097 | ||
45fcb86e | 3098 | c = cmd_alloc(h); |
bf43caf3 | 3099 | |
283b4a9b SC |
3100 | if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, |
3101 | sizeof(this_device->raid_map), 0, | |
3102 | scsi3addr, TYPE_CMD)) { | |
2dd02d74 RE |
3103 | dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); |
3104 | cmd_free(h, c); | |
3105 | return -1; | |
283b4a9b | 3106 | } |
25163bd5 | 3107 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
c448ecfa | 3108 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
25163bd5 WS |
3109 | if (rc) |
3110 | goto out; | |
283b4a9b SC |
3111 | ei = c->err_info; |
3112 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3113 | hpsa_scsi_interpret_error(h, c); |
25163bd5 WS |
3114 | rc = -1; |
3115 | goto out; | |
283b4a9b | 3116 | } |
45fcb86e | 3117 | cmd_free(h, c); |
283b4a9b SC |
3118 | |
3119 | /* @todo in the future, dynamically allocate RAID map memory */ | |
3120 | if (le32_to_cpu(this_device->raid_map.structure_size) > | |
3121 | sizeof(this_device->raid_map)) { | |
3122 | dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); | |
3123 | rc = -1; | |
3124 | } | |
3125 | hpsa_debug_map_buff(h, rc, &this_device->raid_map); | |
3126 | return rc; | |
25163bd5 WS |
3127 | out: |
3128 | cmd_free(h, c); | |
3129 | return rc; | |
283b4a9b SC |
3130 | } |
3131 | ||
d04e62b9 KB |
3132 | static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, |
3133 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3134 | struct bmic_sense_subsystem_info *buf, size_t bufsize) | |
3135 | { | |
3136 | int rc = IO_OK; | |
3137 | struct CommandList *c; | |
3138 | struct ErrorInfo *ei; | |
3139 | ||
3140 | c = cmd_alloc(h); | |
3141 | ||
3142 | rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, | |
3143 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3144 | if (rc) | |
3145 | goto out; | |
3146 | ||
3147 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3148 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3149 | ||
3150 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
c448ecfa | 3151 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
d04e62b9 KB |
3152 | if (rc) |
3153 | goto out; | |
3154 | ei = c->err_info; | |
3155 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3156 | hpsa_scsi_interpret_error(h, c); | |
3157 | rc = -1; | |
3158 | } | |
3159 | out: | |
3160 | cmd_free(h, c); | |
3161 | return rc; | |
3162 | } | |
3163 | ||
66749d0d ST |
3164 | static int hpsa_bmic_id_controller(struct ctlr_info *h, |
3165 | struct bmic_identify_controller *buf, size_t bufsize) | |
3166 | { | |
3167 | int rc = IO_OK; | |
3168 | struct CommandList *c; | |
3169 | struct ErrorInfo *ei; | |
3170 | ||
3171 | c = cmd_alloc(h); | |
3172 | ||
3173 | rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, | |
3174 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3175 | if (rc) | |
3176 | goto out; | |
3177 | ||
3178 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
c448ecfa | 3179 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
66749d0d ST |
3180 | if (rc) |
3181 | goto out; | |
3182 | ei = c->err_info; | |
3183 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3184 | hpsa_scsi_interpret_error(h, c); | |
3185 | rc = -1; | |
3186 | } | |
3187 | out: | |
3188 | cmd_free(h, c); | |
3189 | return rc; | |
3190 | } | |
3191 | ||
03383736 DB |
3192 | static int hpsa_bmic_id_physical_device(struct ctlr_info *h, |
3193 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3194 | struct bmic_identify_physical_device *buf, size_t bufsize) | |
3195 | { | |
3196 | int rc = IO_OK; | |
3197 | struct CommandList *c; | |
3198 | struct ErrorInfo *ei; | |
3199 | ||
3200 | c = cmd_alloc(h); | |
3201 | rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, | |
3202 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3203 | if (rc) | |
3204 | goto out; | |
3205 | ||
3206 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3207 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3208 | ||
25163bd5 | 3209 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, |
c448ecfa | 3210 | DEFAULT_TIMEOUT); |
03383736 DB |
3211 | ei = c->err_info; |
3212 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3213 | hpsa_scsi_interpret_error(h, c); | |
3214 | rc = -1; | |
3215 | } | |
3216 | out: | |
3217 | cmd_free(h, c); | |
d04e62b9 | 3218 | |
03383736 DB |
3219 | return rc; |
3220 | } | |
3221 | ||
cca8f13b DB |
3222 | /* |
3223 | * get enclosure information | |
3224 | * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number | |
3225 | * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure | |
3226 | * Uses id_physical_device to determine the box_index. | |
3227 | */ | |
3228 | static void hpsa_get_enclosure_info(struct ctlr_info *h, | |
3229 | unsigned char *scsi3addr, | |
3230 | struct ReportExtendedLUNdata *rlep, int rle_index, | |
3231 | struct hpsa_scsi_dev_t *encl_dev) | |
3232 | { | |
3233 | int rc = -1; | |
3234 | struct CommandList *c = NULL; | |
3235 | struct ErrorInfo *ei = NULL; | |
3236 | struct bmic_sense_storage_box_params *bssbp = NULL; | |
3237 | struct bmic_identify_physical_device *id_phys = NULL; | |
3238 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; | |
3239 | u16 bmic_device_index = 0; | |
3240 | ||
3241 | bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]); | |
3242 | ||
17a9e54a DB |
3243 | if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) { |
3244 | rc = IO_OK; | |
cca8f13b | 3245 | goto out; |
17a9e54a | 3246 | } |
cca8f13b DB |
3247 | |
3248 | bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL); | |
3249 | if (!bssbp) | |
3250 | goto out; | |
3251 | ||
3252 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); | |
3253 | if (!id_phys) | |
3254 | goto out; | |
3255 | ||
3256 | rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index, | |
3257 | id_phys, sizeof(*id_phys)); | |
3258 | if (rc) { | |
3259 | dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n", | |
3260 | __func__, encl_dev->external, bmic_device_index); | |
3261 | goto out; | |
3262 | } | |
3263 | ||
3264 | c = cmd_alloc(h); | |
3265 | ||
3266 | rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp, | |
3267 | sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3268 | ||
3269 | if (rc) | |
3270 | goto out; | |
3271 | ||
3272 | if (id_phys->phys_connector[1] == 'E') | |
3273 | c->Request.CDB[5] = id_phys->box_index; | |
3274 | else | |
3275 | c->Request.CDB[5] = 0; | |
3276 | ||
3277 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE, | |
c448ecfa | 3278 | DEFAULT_TIMEOUT); |
cca8f13b DB |
3279 | if (rc) |
3280 | goto out; | |
3281 | ||
3282 | ei = c->err_info; | |
3283 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3284 | rc = -1; | |
3285 | goto out; | |
3286 | } | |
3287 | ||
3288 | encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port; | |
3289 | memcpy(&encl_dev->phys_connector[id_phys->active_path_number], | |
3290 | bssbp->phys_connector, sizeof(bssbp->phys_connector)); | |
3291 | ||
3292 | rc = IO_OK; | |
3293 | out: | |
3294 | kfree(bssbp); | |
3295 | kfree(id_phys); | |
3296 | ||
3297 | if (c) | |
3298 | cmd_free(h, c); | |
3299 | ||
3300 | if (rc != IO_OK) | |
3301 | hpsa_show_dev_msg(KERN_INFO, h, encl_dev, | |
3302 | "Error, could not get enclosure information\n"); | |
3303 | } | |
3304 | ||
d04e62b9 KB |
3305 | static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, |
3306 | unsigned char *scsi3addr) | |
3307 | { | |
3308 | struct ReportExtendedLUNdata *physdev; | |
3309 | u32 nphysicals; | |
3310 | u64 sa = 0; | |
3311 | int i; | |
3312 | ||
3313 | physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); | |
3314 | if (!physdev) | |
3315 | return 0; | |
3316 | ||
3317 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { | |
3318 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); | |
3319 | kfree(physdev); | |
3320 | return 0; | |
3321 | } | |
3322 | nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; | |
3323 | ||
3324 | for (i = 0; i < nphysicals; i++) | |
3325 | if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { | |
3326 | sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); | |
3327 | break; | |
3328 | } | |
3329 | ||
3330 | kfree(physdev); | |
3331 | ||
3332 | return sa; | |
3333 | } | |
3334 | ||
3335 | static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, | |
3336 | struct hpsa_scsi_dev_t *dev) | |
3337 | { | |
3338 | int rc; | |
3339 | u64 sa = 0; | |
3340 | ||
3341 | if (is_hba_lunid(scsi3addr)) { | |
3342 | struct bmic_sense_subsystem_info *ssi; | |
3343 | ||
3344 | ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); | |
3345 | if (ssi == NULL) { | |
3346 | dev_warn(&h->pdev->dev, | |
3347 | "%s: out of memory\n", __func__); | |
3348 | return; | |
3349 | } | |
3350 | ||
3351 | rc = hpsa_bmic_sense_subsystem_information(h, | |
3352 | scsi3addr, 0, ssi, sizeof(*ssi)); | |
3353 | if (rc == 0) { | |
3354 | sa = get_unaligned_be64(ssi->primary_world_wide_id); | |
3355 | h->sas_address = sa; | |
3356 | } | |
3357 | ||
3358 | kfree(ssi); | |
3359 | } else | |
3360 | sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); | |
3361 | ||
3362 | dev->sas_address = sa; | |
3363 | } | |
3364 | ||
3365 | /* Get a device id from inquiry page 0x83 */ | |
1b70150a SC |
3366 | static int hpsa_vpd_page_supported(struct ctlr_info *h, |
3367 | unsigned char scsi3addr[], u8 page) | |
3368 | { | |
3369 | int rc; | |
3370 | int i; | |
3371 | int pages; | |
3372 | unsigned char *buf, bufsize; | |
3373 | ||
3374 | buf = kzalloc(256, GFP_KERNEL); | |
3375 | if (!buf) | |
3376 | return 0; | |
3377 | ||
3378 | /* Get the size of the page list first */ | |
3379 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3380 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3381 | buf, HPSA_VPD_HEADER_SZ); | |
3382 | if (rc != 0) | |
3383 | goto exit_unsupported; | |
3384 | pages = buf[3]; | |
3385 | if ((pages + HPSA_VPD_HEADER_SZ) <= 255) | |
3386 | bufsize = pages + HPSA_VPD_HEADER_SZ; | |
3387 | else | |
3388 | bufsize = 255; | |
3389 | ||
3390 | /* Get the whole VPD page list */ | |
3391 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3392 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3393 | buf, bufsize); | |
3394 | if (rc != 0) | |
3395 | goto exit_unsupported; | |
3396 | ||
3397 | pages = buf[3]; | |
3398 | for (i = 1; i <= pages; i++) | |
3399 | if (buf[3 + i] == page) | |
3400 | goto exit_supported; | |
3401 | exit_unsupported: | |
3402 | kfree(buf); | |
3403 | return 0; | |
3404 | exit_supported: | |
3405 | kfree(buf); | |
3406 | return 1; | |
3407 | } | |
3408 | ||
283b4a9b SC |
3409 | static void hpsa_get_ioaccel_status(struct ctlr_info *h, |
3410 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3411 | { | |
3412 | int rc; | |
3413 | unsigned char *buf; | |
3414 | u8 ioaccel_status; | |
3415 | ||
3416 | this_device->offload_config = 0; | |
3417 | this_device->offload_enabled = 0; | |
41ce4c35 | 3418 | this_device->offload_to_be_enabled = 0; |
283b4a9b SC |
3419 | |
3420 | buf = kzalloc(64, GFP_KERNEL); | |
3421 | if (!buf) | |
3422 | return; | |
1b70150a SC |
3423 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) |
3424 | goto out; | |
283b4a9b | 3425 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, |
b7bb24eb | 3426 | VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); |
283b4a9b SC |
3427 | if (rc != 0) |
3428 | goto out; | |
3429 | ||
3430 | #define IOACCEL_STATUS_BYTE 4 | |
3431 | #define OFFLOAD_CONFIGURED_BIT 0x01 | |
3432 | #define OFFLOAD_ENABLED_BIT 0x02 | |
3433 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
3434 | this_device->offload_config = | |
3435 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
3436 | if (this_device->offload_config) { | |
3437 | this_device->offload_enabled = | |
3438 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); | |
3439 | if (hpsa_get_raid_map(h, scsi3addr, this_device)) | |
3440 | this_device->offload_enabled = 0; | |
3441 | } | |
41ce4c35 | 3442 | this_device->offload_to_be_enabled = this_device->offload_enabled; |
283b4a9b SC |
3443 | out: |
3444 | kfree(buf); | |
3445 | return; | |
3446 | } | |
3447 | ||
edd16368 SC |
3448 | /* Get the device id from inquiry page 0x83 */ |
3449 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
75d23d89 | 3450 | unsigned char *device_id, int index, int buflen) |
edd16368 SC |
3451 | { |
3452 | int rc; | |
3453 | unsigned char *buf; | |
3454 | ||
3455 | if (buflen > 16) | |
3456 | buflen = 16; | |
3457 | buf = kzalloc(64, GFP_KERNEL); | |
3458 | if (!buf) | |
a84d794d | 3459 | return -ENOMEM; |
b7bb24eb | 3460 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64); |
edd16368 | 3461 | if (rc == 0) |
75d23d89 DB |
3462 | memcpy(device_id, &buf[index], buflen); |
3463 | ||
edd16368 | 3464 | kfree(buf); |
75d23d89 | 3465 | |
edd16368 SC |
3466 | return rc != 0; |
3467 | } | |
3468 | ||
3469 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
03383736 | 3470 | void *buf, int bufsize, |
edd16368 SC |
3471 | int extended_response) |
3472 | { | |
3473 | int rc = IO_OK; | |
3474 | struct CommandList *c; | |
3475 | unsigned char scsi3addr[8]; | |
3476 | struct ErrorInfo *ei; | |
3477 | ||
45fcb86e | 3478 | c = cmd_alloc(h); |
bf43caf3 | 3479 | |
e89c0ae7 SC |
3480 | /* address the controller */ |
3481 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
3482 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
3483 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
3484 | rc = -1; | |
3485 | goto out; | |
3486 | } | |
edd16368 SC |
3487 | if (extended_response) |
3488 | c->Request.CDB[1] = extended_response; | |
25163bd5 | 3489 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
c448ecfa | 3490 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
25163bd5 WS |
3491 | if (rc) |
3492 | goto out; | |
edd16368 SC |
3493 | ei = c->err_info; |
3494 | if (ei->CommandStatus != 0 && | |
3495 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3496 | hpsa_scsi_interpret_error(h, c); |
edd16368 | 3497 | rc = -1; |
283b4a9b | 3498 | } else { |
03383736 DB |
3499 | struct ReportLUNdata *rld = buf; |
3500 | ||
3501 | if (rld->extended_response_flag != extended_response) { | |
283b4a9b SC |
3502 | dev_err(&h->pdev->dev, |
3503 | "report luns requested format %u, got %u\n", | |
3504 | extended_response, | |
03383736 | 3505 | rld->extended_response_flag); |
283b4a9b SC |
3506 | rc = -1; |
3507 | } | |
edd16368 | 3508 | } |
a2dac136 | 3509 | out: |
45fcb86e | 3510 | cmd_free(h, c); |
edd16368 SC |
3511 | return rc; |
3512 | } | |
3513 | ||
3514 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
03383736 | 3515 | struct ReportExtendedLUNdata *buf, int bufsize) |
edd16368 | 3516 | { |
03383736 DB |
3517 | return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, |
3518 | HPSA_REPORT_PHYS_EXTENDED); | |
edd16368 SC |
3519 | } |
3520 | ||
3521 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
3522 | struct ReportLUNdata *buf, int bufsize) | |
3523 | { | |
3524 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
3525 | } | |
3526 | ||
3527 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
3528 | int bus, int target, int lun) | |
3529 | { | |
3530 | device->bus = bus; | |
3531 | device->target = target; | |
3532 | device->lun = lun; | |
3533 | } | |
3534 | ||
9846590e SC |
3535 | /* Use VPD inquiry to get details of volume status */ |
3536 | static int hpsa_get_volume_status(struct ctlr_info *h, | |
3537 | unsigned char scsi3addr[]) | |
3538 | { | |
3539 | int rc; | |
3540 | int status; | |
3541 | int size; | |
3542 | unsigned char *buf; | |
3543 | ||
3544 | buf = kzalloc(64, GFP_KERNEL); | |
3545 | if (!buf) | |
3546 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3547 | ||
3548 | /* Does controller have VPD for logical volume status? */ | |
24a4b078 | 3549 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) |
9846590e | 3550 | goto exit_failed; |
9846590e SC |
3551 | |
3552 | /* Get the size of the VPD return buffer */ | |
3553 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3554 | buf, HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3555 | if (rc != 0) |
9846590e | 3556 | goto exit_failed; |
9846590e SC |
3557 | size = buf[3]; |
3558 | ||
3559 | /* Now get the whole VPD buffer */ | |
3560 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3561 | buf, size + HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3562 | if (rc != 0) |
9846590e | 3563 | goto exit_failed; |
9846590e SC |
3564 | status = buf[4]; /* status byte */ |
3565 | ||
3566 | kfree(buf); | |
3567 | return status; | |
3568 | exit_failed: | |
3569 | kfree(buf); | |
3570 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3571 | } | |
3572 | ||
3573 | /* Determine offline status of a volume. | |
3574 | * Return either: | |
3575 | * 0 (not offline) | |
67955ba3 | 3576 | * 0xff (offline for unknown reasons) |
9846590e SC |
3577 | * # (integer code indicating one of several NOT READY states |
3578 | * describing why a volume is to be kept offline) | |
3579 | */ | |
67955ba3 | 3580 | static int hpsa_volume_offline(struct ctlr_info *h, |
9846590e SC |
3581 | unsigned char scsi3addr[]) |
3582 | { | |
3583 | struct CommandList *c; | |
9437ac43 SC |
3584 | unsigned char *sense; |
3585 | u8 sense_key, asc, ascq; | |
3586 | int sense_len; | |
25163bd5 | 3587 | int rc, ldstat = 0; |
9846590e SC |
3588 | u16 cmd_status; |
3589 | u8 scsi_status; | |
3590 | #define ASC_LUN_NOT_READY 0x04 | |
3591 | #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 | |
3592 | #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 | |
3593 | ||
3594 | c = cmd_alloc(h); | |
bf43caf3 | 3595 | |
9846590e | 3596 | (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); |
c448ecfa DB |
3597 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
3598 | DEFAULT_TIMEOUT); | |
25163bd5 WS |
3599 | if (rc) { |
3600 | cmd_free(h, c); | |
3601 | return 0; | |
3602 | } | |
9846590e | 3603 | sense = c->err_info->SenseInfo; |
9437ac43 SC |
3604 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) |
3605 | sense_len = sizeof(c->err_info->SenseInfo); | |
3606 | else | |
3607 | sense_len = c->err_info->SenseLen; | |
3608 | decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); | |
9846590e SC |
3609 | cmd_status = c->err_info->CommandStatus; |
3610 | scsi_status = c->err_info->ScsiStatus; | |
3611 | cmd_free(h, c); | |
3612 | /* Is the volume 'not ready'? */ | |
3613 | if (cmd_status != CMD_TARGET_STATUS || | |
3614 | scsi_status != SAM_STAT_CHECK_CONDITION || | |
3615 | sense_key != NOT_READY || | |
3616 | asc != ASC_LUN_NOT_READY) { | |
3617 | return 0; | |
3618 | } | |
3619 | ||
3620 | /* Determine the reason for not ready state */ | |
3621 | ldstat = hpsa_get_volume_status(h, scsi3addr); | |
3622 | ||
3623 | /* Keep volume offline in certain cases: */ | |
3624 | switch (ldstat) { | |
3625 | case HPSA_LV_UNDERGOING_ERASE: | |
5ca01204 | 3626 | case HPSA_LV_NOT_AVAILABLE: |
9846590e SC |
3627 | case HPSA_LV_UNDERGOING_RPI: |
3628 | case HPSA_LV_PENDING_RPI: | |
3629 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
3630 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
3631 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
3632 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
3633 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
3634 | return ldstat; | |
3635 | case HPSA_VPD_LV_STATUS_UNSUPPORTED: | |
3636 | /* If VPD status page isn't available, | |
3637 | * use ASC/ASCQ to determine state | |
3638 | */ | |
3639 | if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || | |
3640 | (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) | |
3641 | return ldstat; | |
3642 | break; | |
3643 | default: | |
3644 | break; | |
3645 | } | |
3646 | return 0; | |
3647 | } | |
3648 | ||
9b5c48c2 SC |
3649 | /* |
3650 | * Find out if a logical device supports aborts by simply trying one. | |
3651 | * Smart Array may claim not to support aborts on logical drives, but | |
3652 | * if a MSA2000 * is connected, the drives on that will be presented | |
3653 | * by the Smart Array as logical drives, and aborts may be sent to | |
3654 | * those devices successfully. So the simplest way to find out is | |
3655 | * to simply try an abort and see how the device responds. | |
3656 | */ | |
3657 | static int hpsa_device_supports_aborts(struct ctlr_info *h, | |
3658 | unsigned char *scsi3addr) | |
3659 | { | |
3660 | struct CommandList *c; | |
3661 | struct ErrorInfo *ei; | |
3662 | int rc = 0; | |
3663 | ||
3664 | u64 tag = (u64) -1; /* bogus tag */ | |
3665 | ||
3666 | /* Assume that physical devices support aborts */ | |
3667 | if (!is_logical_dev_addr_mode(scsi3addr)) | |
3668 | return 1; | |
3669 | ||
3670 | c = cmd_alloc(h); | |
bf43caf3 | 3671 | |
9b5c48c2 | 3672 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG); |
c448ecfa DB |
3673 | (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
3674 | DEFAULT_TIMEOUT); | |
9b5c48c2 SC |
3675 | /* no unmap needed here because no data xfer. */ |
3676 | ei = c->err_info; | |
3677 | switch (ei->CommandStatus) { | |
3678 | case CMD_INVALID: | |
3679 | rc = 0; | |
3680 | break; | |
3681 | case CMD_UNABORTABLE: | |
3682 | case CMD_ABORT_FAILED: | |
3683 | rc = 1; | |
3684 | break; | |
9437ac43 SC |
3685 | case CMD_TMF_STATUS: |
3686 | rc = hpsa_evaluate_tmf_status(h, c); | |
3687 | break; | |
9b5c48c2 SC |
3688 | default: |
3689 | rc = 0; | |
3690 | break; | |
3691 | } | |
3692 | cmd_free(h, c); | |
3693 | return rc; | |
3694 | } | |
3695 | ||
edd16368 | 3696 | static int hpsa_update_device_info(struct ctlr_info *h, |
0b0e1d6c SC |
3697 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
3698 | unsigned char *is_OBDR_device) | |
edd16368 | 3699 | { |
0b0e1d6c SC |
3700 | |
3701 | #define OBDR_SIG_OFFSET 43 | |
3702 | #define OBDR_TAPE_SIG "$DR-10" | |
3703 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
3704 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
3705 | ||
ea6d3bc3 | 3706 | unsigned char *inq_buff; |
0b0e1d6c | 3707 | unsigned char *obdr_sig; |
683fc444 | 3708 | int rc = 0; |
edd16368 | 3709 | |
ea6d3bc3 | 3710 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
683fc444 DB |
3711 | if (!inq_buff) { |
3712 | rc = -ENOMEM; | |
edd16368 | 3713 | goto bail_out; |
683fc444 | 3714 | } |
edd16368 | 3715 | |
edd16368 SC |
3716 | /* Do an inquiry to the device to see what it is. */ |
3717 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
3718 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
3719 | /* Inquiry failed (msg printed already) */ | |
3720 | dev_err(&h->pdev->dev, | |
3721 | "hpsa_update_device_info: inquiry failed\n"); | |
683fc444 | 3722 | rc = -EIO; |
edd16368 SC |
3723 | goto bail_out; |
3724 | } | |
3725 | ||
4af61e4f DB |
3726 | scsi_sanitize_inquiry_string(&inq_buff[8], 8); |
3727 | scsi_sanitize_inquiry_string(&inq_buff[16], 16); | |
75d23d89 | 3728 | |
edd16368 SC |
3729 | this_device->devtype = (inq_buff[0] & 0x1f); |
3730 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
3731 | memcpy(this_device->vendor, &inq_buff[8], | |
3732 | sizeof(this_device->vendor)); | |
3733 | memcpy(this_device->model, &inq_buff[16], | |
3734 | sizeof(this_device->model)); | |
edd16368 SC |
3735 | memset(this_device->device_id, 0, |
3736 | sizeof(this_device->device_id)); | |
75d23d89 | 3737 | hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, |
edd16368 SC |
3738 | sizeof(this_device->device_id)); |
3739 | ||
af15ed36 DB |
3740 | if ((this_device->devtype == TYPE_DISK || |
3741 | this_device->devtype == TYPE_ZBC) && | |
283b4a9b | 3742 | is_logical_dev_addr_mode(scsi3addr)) { |
67955ba3 SC |
3743 | int volume_offline; |
3744 | ||
edd16368 | 3745 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); |
283b4a9b SC |
3746 | if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) |
3747 | hpsa_get_ioaccel_status(h, scsi3addr, this_device); | |
67955ba3 SC |
3748 | volume_offline = hpsa_volume_offline(h, scsi3addr); |
3749 | if (volume_offline < 0 || volume_offline > 0xff) | |
3750 | volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3751 | this_device->volume_offline = volume_offline & 0xff; | |
283b4a9b | 3752 | } else { |
edd16368 | 3753 | this_device->raid_level = RAID_UNKNOWN; |
283b4a9b SC |
3754 | this_device->offload_config = 0; |
3755 | this_device->offload_enabled = 0; | |
41ce4c35 | 3756 | this_device->offload_to_be_enabled = 0; |
a3144e0b | 3757 | this_device->hba_ioaccel_enabled = 0; |
9846590e | 3758 | this_device->volume_offline = 0; |
03383736 | 3759 | this_device->queue_depth = h->nr_cmds; |
283b4a9b | 3760 | } |
edd16368 | 3761 | |
0b0e1d6c SC |
3762 | if (is_OBDR_device) { |
3763 | /* See if this is a One-Button-Disaster-Recovery device | |
3764 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
3765 | */ | |
3766 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
3767 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
3768 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
3769 | OBDR_SIG_LEN) == 0); | |
3770 | } | |
edd16368 SC |
3771 | kfree(inq_buff); |
3772 | return 0; | |
3773 | ||
3774 | bail_out: | |
3775 | kfree(inq_buff); | |
683fc444 | 3776 | return rc; |
edd16368 SC |
3777 | } |
3778 | ||
9b5c48c2 SC |
3779 | static void hpsa_update_device_supports_aborts(struct ctlr_info *h, |
3780 | struct hpsa_scsi_dev_t *dev, u8 *scsi3addr) | |
3781 | { | |
3782 | unsigned long flags; | |
3783 | int rc, entry; | |
3784 | /* | |
3785 | * See if this device supports aborts. If we already know | |
3786 | * the device, we already know if it supports aborts, otherwise | |
3787 | * we have to find out if it supports aborts by trying one. | |
3788 | */ | |
3789 | spin_lock_irqsave(&h->devlock, flags); | |
3790 | rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry); | |
3791 | if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) && | |
3792 | entry >= 0 && entry < h->ndevices) { | |
3793 | dev->supports_aborts = h->dev[entry]->supports_aborts; | |
3794 | spin_unlock_irqrestore(&h->devlock, flags); | |
3795 | } else { | |
3796 | spin_unlock_irqrestore(&h->devlock, flags); | |
3797 | dev->supports_aborts = | |
3798 | hpsa_device_supports_aborts(h, scsi3addr); | |
3799 | if (dev->supports_aborts < 0) | |
3800 | dev->supports_aborts = 0; | |
3801 | } | |
3802 | } | |
3803 | ||
c795505a KB |
3804 | /* |
3805 | * Helper function to assign bus, target, lun mapping of devices. | |
edd16368 SC |
3806 | * Logical drive target and lun are assigned at this time, but |
3807 | * physical device lun and target assignment are deferred (assigned | |
3808 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
c795505a | 3809 | */ |
edd16368 | 3810 | static void figure_bus_target_lun(struct ctlr_info *h, |
1f310bde | 3811 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 3812 | { |
c795505a | 3813 | u32 lunid = get_unaligned_le32(lunaddrbytes); |
1f310bde SC |
3814 | |
3815 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
3816 | /* physical device, target and lun filled in later */ | |
edd16368 | 3817 | if (is_hba_lunid(lunaddrbytes)) |
c795505a KB |
3818 | hpsa_set_bus_target_lun(device, |
3819 | HPSA_HBA_BUS, 0, lunid & 0x3fff); | |
edd16368 | 3820 | else |
1f310bde | 3821 | /* defer target, lun assignment for physical devices */ |
c795505a KB |
3822 | hpsa_set_bus_target_lun(device, |
3823 | HPSA_PHYSICAL_DEVICE_BUS, -1, -1); | |
1f310bde SC |
3824 | return; |
3825 | } | |
3826 | /* It's a logical device */ | |
66749d0d | 3827 | if (device->external) { |
1f310bde | 3828 | hpsa_set_bus_target_lun(device, |
c795505a KB |
3829 | HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, |
3830 | lunid & 0x00ff); | |
1f310bde | 3831 | return; |
edd16368 | 3832 | } |
c795505a KB |
3833 | hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, |
3834 | 0, lunid & 0x3fff); | |
edd16368 SC |
3835 | } |
3836 | ||
edd16368 | 3837 | |
54b6e9e9 ST |
3838 | /* |
3839 | * Get address of physical disk used for an ioaccel2 mode command: | |
3840 | * 1. Extract ioaccel2 handle from the command. | |
3841 | * 2. Find a matching ioaccel2 handle from list of physical disks. | |
3842 | * 3. Return: | |
3843 | * 1 and set scsi3addr to address of matching physical | |
3844 | * 0 if no matching physical disk was found. | |
3845 | */ | |
3846 | static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h, | |
3847 | struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr) | |
3848 | { | |
41ce4c35 SC |
3849 | struct io_accel2_cmd *c2 = |
3850 | &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex]; | |
3851 | unsigned long flags; | |
54b6e9e9 | 3852 | int i; |
54b6e9e9 | 3853 | |
41ce4c35 SC |
3854 | spin_lock_irqsave(&h->devlock, flags); |
3855 | for (i = 0; i < h->ndevices; i++) | |
3856 | if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) { | |
3857 | memcpy(scsi3addr, h->dev[i]->scsi3addr, | |
3858 | sizeof(h->dev[i]->scsi3addr)); | |
3859 | spin_unlock_irqrestore(&h->devlock, flags); | |
3860 | return 1; | |
3861 | } | |
3862 | spin_unlock_irqrestore(&h->devlock, flags); | |
3863 | return 0; | |
54b6e9e9 | 3864 | } |
41ce4c35 | 3865 | |
66749d0d ST |
3866 | static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, |
3867 | int i, int nphysicals, int nlocal_logicals) | |
3868 | { | |
3869 | /* In report logicals, local logicals are listed first, | |
3870 | * then any externals. | |
3871 | */ | |
3872 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
3873 | ||
3874 | if (i == raid_ctlr_position) | |
3875 | return 0; | |
3876 | ||
3877 | if (i < logicals_start) | |
3878 | return 0; | |
3879 | ||
3880 | /* i is in logicals range, but still within local logicals */ | |
3881 | if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) | |
3882 | return 0; | |
3883 | ||
3884 | return 1; /* it's an external lun */ | |
3885 | } | |
3886 | ||
edd16368 SC |
3887 | /* |
3888 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
3889 | * logdev. The number of luns in physdev and logdev are returned in | |
3890 | * *nphysicals and *nlogicals, respectively. | |
3891 | * Returns 0 on success, -1 otherwise. | |
3892 | */ | |
3893 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
03383736 | 3894 | struct ReportExtendedLUNdata *physdev, u32 *nphysicals, |
01a02ffc | 3895 | struct ReportLUNdata *logdev, u32 *nlogicals) |
edd16368 | 3896 | { |
03383736 | 3897 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { |
edd16368 SC |
3898 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
3899 | return -1; | |
3900 | } | |
03383736 | 3901 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; |
edd16368 | 3902 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
03383736 DB |
3903 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", |
3904 | HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); | |
edd16368 SC |
3905 | *nphysicals = HPSA_MAX_PHYS_LUN; |
3906 | } | |
03383736 | 3907 | if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { |
edd16368 SC |
3908 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); |
3909 | return -1; | |
3910 | } | |
6df1e954 | 3911 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
3912 | /* Reject Logicals in excess of our max capability. */ |
3913 | if (*nlogicals > HPSA_MAX_LUN) { | |
3914 | dev_warn(&h->pdev->dev, | |
3915 | "maximum logical LUNs (%d) exceeded. " | |
3916 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
3917 | *nlogicals - HPSA_MAX_LUN); | |
3918 | *nlogicals = HPSA_MAX_LUN; | |
3919 | } | |
3920 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
3921 | dev_warn(&h->pdev->dev, | |
3922 | "maximum logical + physical LUNs (%d) exceeded. " | |
3923 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
3924 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
3925 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
3926 | } | |
3927 | return 0; | |
3928 | } | |
3929 | ||
42a91641 DB |
3930 | static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, |
3931 | int i, int nphysicals, int nlogicals, | |
a93aa1fe | 3932 | struct ReportExtendedLUNdata *physdev_list, |
339b2b14 SC |
3933 | struct ReportLUNdata *logdev_list) |
3934 | { | |
3935 | /* Helper function, figure out where the LUN ID info is coming from | |
3936 | * given index i, lists of physical and logical devices, where in | |
3937 | * the list the raid controller is supposed to appear (first or last) | |
3938 | */ | |
3939 | ||
3940 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
3941 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
3942 | ||
3943 | if (i == raid_ctlr_position) | |
3944 | return RAID_CTLR_LUNID; | |
3945 | ||
3946 | if (i < logicals_start) | |
d5b5d964 SC |
3947 | return &physdev_list->LUN[i - |
3948 | (raid_ctlr_position == 0)].lunid[0]; | |
339b2b14 SC |
3949 | |
3950 | if (i < last_device) | |
3951 | return &logdev_list->LUN[i - nphysicals - | |
3952 | (raid_ctlr_position == 0)][0]; | |
3953 | BUG(); | |
3954 | return NULL; | |
3955 | } | |
3956 | ||
03383736 DB |
3957 | /* get physical drive ioaccel handle and queue depth */ |
3958 | static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, | |
3959 | struct hpsa_scsi_dev_t *dev, | |
f2039b03 | 3960 | struct ReportExtendedLUNdata *rlep, int rle_index, |
03383736 DB |
3961 | struct bmic_identify_physical_device *id_phys) |
3962 | { | |
3963 | int rc; | |
f2039b03 | 3964 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; |
03383736 DB |
3965 | |
3966 | dev->ioaccel_handle = rle->ioaccel_handle; | |
f2039b03 | 3967 | if ((rle->device_flags & 0x08) && dev->ioaccel_handle) |
a3144e0b | 3968 | dev->hba_ioaccel_enabled = 1; |
03383736 | 3969 | memset(id_phys, 0, sizeof(*id_phys)); |
f2039b03 DB |
3970 | rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], |
3971 | GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, | |
03383736 DB |
3972 | sizeof(*id_phys)); |
3973 | if (!rc) | |
3974 | /* Reserve space for FW operations */ | |
3975 | #define DRIVE_CMDS_RESERVED_FOR_FW 2 | |
3976 | #define DRIVE_QUEUE_DEPTH 7 | |
3977 | dev->queue_depth = | |
3978 | le16_to_cpu(id_phys->current_queue_depth_limit) - | |
3979 | DRIVE_CMDS_RESERVED_FOR_FW; | |
3980 | else | |
3981 | dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ | |
03383736 DB |
3982 | } |
3983 | ||
8270b862 | 3984 | static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, |
f2039b03 | 3985 | struct ReportExtendedLUNdata *rlep, int rle_index, |
8270b862 JH |
3986 | struct bmic_identify_physical_device *id_phys) |
3987 | { | |
f2039b03 DB |
3988 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; |
3989 | ||
3990 | if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) | |
8270b862 JH |
3991 | this_device->hba_ioaccel_enabled = 1; |
3992 | ||
3993 | memcpy(&this_device->active_path_index, | |
3994 | &id_phys->active_path_number, | |
3995 | sizeof(this_device->active_path_index)); | |
3996 | memcpy(&this_device->path_map, | |
3997 | &id_phys->redundant_path_present_map, | |
3998 | sizeof(this_device->path_map)); | |
3999 | memcpy(&this_device->box, | |
4000 | &id_phys->alternate_paths_phys_box_on_port, | |
4001 | sizeof(this_device->box)); | |
4002 | memcpy(&this_device->phys_connector, | |
4003 | &id_phys->alternate_paths_phys_connector, | |
4004 | sizeof(this_device->phys_connector)); | |
4005 | memcpy(&this_device->bay, | |
4006 | &id_phys->phys_bay_in_box, | |
4007 | sizeof(this_device->bay)); | |
4008 | } | |
4009 | ||
66749d0d ST |
4010 | /* get number of local logical disks. */ |
4011 | static int hpsa_set_local_logical_count(struct ctlr_info *h, | |
4012 | struct bmic_identify_controller *id_ctlr, | |
4013 | u32 *nlocals) | |
4014 | { | |
4015 | int rc; | |
4016 | ||
4017 | if (!id_ctlr) { | |
4018 | dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", | |
4019 | __func__); | |
4020 | return -ENOMEM; | |
4021 | } | |
4022 | memset(id_ctlr, 0, sizeof(*id_ctlr)); | |
4023 | rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); | |
4024 | if (!rc) | |
4025 | if (id_ctlr->configured_logical_drive_count < 256) | |
4026 | *nlocals = id_ctlr->configured_logical_drive_count; | |
4027 | else | |
4028 | *nlocals = le16_to_cpu( | |
4029 | id_ctlr->extended_logical_unit_count); | |
4030 | else | |
4031 | *nlocals = -1; | |
4032 | return rc; | |
4033 | } | |
4034 | ||
4035 | ||
8aa60681 | 4036 | static void hpsa_update_scsi_devices(struct ctlr_info *h) |
edd16368 SC |
4037 | { |
4038 | /* the idea here is we could get notified | |
4039 | * that some devices have changed, so we do a report | |
4040 | * physical luns and report logical luns cmd, and adjust | |
4041 | * our list of devices accordingly. | |
4042 | * | |
4043 | * The scsi3addr's of devices won't change so long as the | |
4044 | * adapter is not reset. That means we can rescan and | |
4045 | * tell which devices we already know about, vs. new | |
4046 | * devices, vs. disappearing devices. | |
4047 | */ | |
a93aa1fe | 4048 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 4049 | struct ReportLUNdata *logdev_list = NULL; |
03383736 | 4050 | struct bmic_identify_physical_device *id_phys = NULL; |
66749d0d | 4051 | struct bmic_identify_controller *id_ctlr = NULL; |
01a02ffc SC |
4052 | u32 nphysicals = 0; |
4053 | u32 nlogicals = 0; | |
66749d0d | 4054 | u32 nlocal_logicals = 0; |
01a02ffc | 4055 | u32 ndev_allocated = 0; |
edd16368 SC |
4056 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
4057 | int ncurrent = 0; | |
4f4eb9f1 | 4058 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 4059 | int raid_ctlr_position; |
04fa2f44 | 4060 | bool physical_device; |
aca4a520 | 4061 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 4062 | |
cfe5badc | 4063 | currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); |
92084715 SC |
4064 | physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); |
4065 | logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); | |
edd16368 | 4066 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
03383736 | 4067 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); |
66749d0d | 4068 | id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); |
edd16368 | 4069 | |
03383736 | 4070 | if (!currentsd || !physdev_list || !logdev_list || |
66749d0d | 4071 | !tmpdevice || !id_phys || !id_ctlr) { |
edd16368 SC |
4072 | dev_err(&h->pdev->dev, "out of memory\n"); |
4073 | goto out; | |
4074 | } | |
4075 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
4076 | ||
853633e8 DB |
4077 | h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ |
4078 | ||
03383736 | 4079 | if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, |
853633e8 DB |
4080 | logdev_list, &nlogicals)) { |
4081 | h->drv_req_rescan = 1; | |
edd16368 | 4082 | goto out; |
853633e8 | 4083 | } |
edd16368 | 4084 | |
66749d0d ST |
4085 | /* Set number of local logicals (non PTRAID) */ |
4086 | if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { | |
4087 | dev_warn(&h->pdev->dev, | |
4088 | "%s: Can't determine number of local logical devices.\n", | |
4089 | __func__); | |
4090 | } | |
edd16368 | 4091 | |
aca4a520 ST |
4092 | /* We might see up to the maximum number of logical and physical disks |
4093 | * plus external target devices, and a device for the local RAID | |
4094 | * controller. | |
edd16368 | 4095 | */ |
aca4a520 | 4096 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 SC |
4097 | |
4098 | /* Allocate the per device structures */ | |
4099 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
4100 | if (i >= HPSA_MAX_DEVICES) { |
4101 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
4102 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
4103 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
4104 | break; | |
4105 | } | |
4106 | ||
edd16368 SC |
4107 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
4108 | if (!currentsd[i]) { | |
4109 | dev_warn(&h->pdev->dev, "out of memory at %s:%d\n", | |
4110 | __FILE__, __LINE__); | |
853633e8 | 4111 | h->drv_req_rescan = 1; |
edd16368 SC |
4112 | goto out; |
4113 | } | |
4114 | ndev_allocated++; | |
4115 | } | |
4116 | ||
8645291b | 4117 | if (is_scsi_rev_5(h)) |
339b2b14 SC |
4118 | raid_ctlr_position = 0; |
4119 | else | |
4120 | raid_ctlr_position = nphysicals + nlogicals; | |
4121 | ||
edd16368 | 4122 | /* adjust our table of devices */ |
4f4eb9f1 | 4123 | n_ext_target_devs = 0; |
edd16368 | 4124 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 4125 | u8 *lunaddrbytes, is_OBDR = 0; |
683fc444 | 4126 | int rc = 0; |
f2039b03 | 4127 | int phys_dev_index = i - (raid_ctlr_position == 0); |
edd16368 | 4128 | |
04fa2f44 | 4129 | physical_device = i < nphysicals + (raid_ctlr_position == 0); |
edd16368 SC |
4130 | |
4131 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
4132 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
4133 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
41ce4c35 SC |
4134 | |
4135 | /* skip masked non-disk devices */ | |
04fa2f44 | 4136 | if (MASKED_DEVICE(lunaddrbytes) && physical_device && |
cca8f13b DB |
4137 | (physdev_list->LUN[phys_dev_index].device_type != 0x06) && |
4138 | (physdev_list->LUN[phys_dev_index].device_flags & 0x01)) | |
04fa2f44 | 4139 | continue; |
edd16368 SC |
4140 | |
4141 | /* Get device type, vendor, model, device id */ | |
683fc444 DB |
4142 | rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
4143 | &is_OBDR); | |
4144 | if (rc == -ENOMEM) { | |
4145 | dev_warn(&h->pdev->dev, | |
4146 | "Out of memory, rescan deferred.\n"); | |
853633e8 | 4147 | h->drv_req_rescan = 1; |
683fc444 | 4148 | goto out; |
853633e8 | 4149 | } |
683fc444 DB |
4150 | if (rc) { |
4151 | dev_warn(&h->pdev->dev, | |
4152 | "Inquiry failed, skipping device.\n"); | |
4153 | continue; | |
4154 | } | |
4155 | ||
66749d0d ST |
4156 | /* Determine if this is a lun from an external target array */ |
4157 | tmpdevice->external = | |
4158 | figure_external_status(h, raid_ctlr_position, i, | |
4159 | nphysicals, nlocal_logicals); | |
4160 | ||
1f310bde | 4161 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
9b5c48c2 | 4162 | hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes); |
edd16368 SC |
4163 | this_device = currentsd[ncurrent]; |
4164 | ||
34592254 ST |
4165 | /* Turn on discovery_polling if there are ext target devices. |
4166 | * Event-based change notification is unreliable for those. | |
edd16368 | 4167 | */ |
34592254 ST |
4168 | if (!h->discovery_polling) { |
4169 | if (tmpdevice->external) { | |
4170 | h->discovery_polling = 1; | |
4171 | dev_info(&h->pdev->dev, | |
4172 | "External target, activate discovery polling.\n"); | |
4173 | } | |
edd16368 SC |
4174 | } |
4175 | ||
34592254 | 4176 | |
edd16368 | 4177 | *this_device = *tmpdevice; |
04fa2f44 | 4178 | this_device->physical_device = physical_device; |
edd16368 | 4179 | |
04fa2f44 KB |
4180 | /* |
4181 | * Expose all devices except for physical devices that | |
4182 | * are masked. | |
4183 | */ | |
4184 | if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) | |
2a168208 KB |
4185 | this_device->expose_device = 0; |
4186 | else | |
4187 | this_device->expose_device = 1; | |
41ce4c35 | 4188 | |
d04e62b9 KB |
4189 | |
4190 | /* | |
4191 | * Get the SAS address for physical devices that are exposed. | |
4192 | */ | |
4193 | if (this_device->physical_device && this_device->expose_device) | |
4194 | hpsa_get_sas_address(h, lunaddrbytes, this_device); | |
41ce4c35 | 4195 | |
edd16368 | 4196 | switch (this_device->devtype) { |
0b0e1d6c | 4197 | case TYPE_ROM: |
edd16368 SC |
4198 | /* We don't *really* support actual CD-ROM devices, |
4199 | * just "One Button Disaster Recovery" tape drive | |
4200 | * which temporarily pretends to be a CD-ROM drive. | |
4201 | * So we check that the device is really an OBDR tape | |
4202 | * device by checking for "$DR-10" in bytes 43-48 of | |
4203 | * the inquiry data. | |
4204 | */ | |
0b0e1d6c SC |
4205 | if (is_OBDR) |
4206 | ncurrent++; | |
edd16368 SC |
4207 | break; |
4208 | case TYPE_DISK: | |
af15ed36 | 4209 | case TYPE_ZBC: |
04fa2f44 | 4210 | if (this_device->physical_device) { |
b9092b79 KB |
4211 | /* The disk is in HBA mode. */ |
4212 | /* Never use RAID mapper in HBA mode. */ | |
ecf418d1 | 4213 | this_device->offload_enabled = 0; |
b9092b79 | 4214 | hpsa_get_ioaccel_drive_info(h, this_device, |
f2039b03 DB |
4215 | physdev_list, phys_dev_index, id_phys); |
4216 | hpsa_get_path_info(this_device, | |
4217 | physdev_list, phys_dev_index, id_phys); | |
b9092b79 | 4218 | } |
ecf418d1 | 4219 | ncurrent++; |
edd16368 SC |
4220 | break; |
4221 | case TYPE_TAPE: | |
4222 | case TYPE_MEDIUM_CHANGER: | |
cca8f13b DB |
4223 | ncurrent++; |
4224 | break; | |
41ce4c35 | 4225 | case TYPE_ENCLOSURE: |
17a9e54a DB |
4226 | if (!this_device->external) |
4227 | hpsa_get_enclosure_info(h, lunaddrbytes, | |
cca8f13b DB |
4228 | physdev_list, phys_dev_index, |
4229 | this_device); | |
b9092b79 | 4230 | ncurrent++; |
41ce4c35 | 4231 | break; |
edd16368 SC |
4232 | case TYPE_RAID: |
4233 | /* Only present the Smartarray HBA as a RAID controller. | |
4234 | * If it's a RAID controller other than the HBA itself | |
4235 | * (an external RAID controller, MSA500 or similar) | |
4236 | * don't present it. | |
4237 | */ | |
4238 | if (!is_hba_lunid(lunaddrbytes)) | |
4239 | break; | |
4240 | ncurrent++; | |
4241 | break; | |
4242 | default: | |
4243 | break; | |
4244 | } | |
cfe5badc | 4245 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
4246 | break; |
4247 | } | |
d04e62b9 KB |
4248 | |
4249 | if (h->sas_host == NULL) { | |
4250 | int rc = 0; | |
4251 | ||
4252 | rc = hpsa_add_sas_host(h); | |
4253 | if (rc) { | |
4254 | dev_warn(&h->pdev->dev, | |
4255 | "Could not add sas host %d\n", rc); | |
4256 | goto out; | |
4257 | } | |
4258 | } | |
4259 | ||
8aa60681 | 4260 | adjust_hpsa_scsi_table(h, currentsd, ncurrent); |
edd16368 SC |
4261 | out: |
4262 | kfree(tmpdevice); | |
4263 | for (i = 0; i < ndev_allocated; i++) | |
4264 | kfree(currentsd[i]); | |
4265 | kfree(currentsd); | |
edd16368 SC |
4266 | kfree(physdev_list); |
4267 | kfree(logdev_list); | |
66749d0d | 4268 | kfree(id_ctlr); |
03383736 | 4269 | kfree(id_phys); |
edd16368 SC |
4270 | } |
4271 | ||
ec5cbf04 WS |
4272 | static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, |
4273 | struct scatterlist *sg) | |
4274 | { | |
4275 | u64 addr64 = (u64) sg_dma_address(sg); | |
4276 | unsigned int len = sg_dma_len(sg); | |
4277 | ||
4278 | desc->Addr = cpu_to_le64(addr64); | |
4279 | desc->Len = cpu_to_le32(len); | |
4280 | desc->Ext = 0; | |
4281 | } | |
4282 | ||
c7ee65b3 WS |
4283 | /* |
4284 | * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
edd16368 SC |
4285 | * dma mapping and fills in the scatter gather entries of the |
4286 | * hpsa command, cp. | |
4287 | */ | |
33a2ffce | 4288 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
4289 | struct CommandList *cp, |
4290 | struct scsi_cmnd *cmd) | |
4291 | { | |
edd16368 | 4292 | struct scatterlist *sg; |
b3a7ba7c | 4293 | int use_sg, i, sg_limit, chained, last_sg; |
33a2ffce | 4294 | struct SGDescriptor *curr_sg; |
edd16368 | 4295 | |
33a2ffce | 4296 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
4297 | |
4298 | use_sg = scsi_dma_map(cmd); | |
4299 | if (use_sg < 0) | |
4300 | return use_sg; | |
4301 | ||
4302 | if (!use_sg) | |
4303 | goto sglist_finished; | |
4304 | ||
b3a7ba7c WS |
4305 | /* |
4306 | * If the number of entries is greater than the max for a single list, | |
4307 | * then we have a chained list; we will set up all but one entry in the | |
4308 | * first list (the last entry is saved for link information); | |
4309 | * otherwise, we don't have a chained list and we'll set up at each of | |
4310 | * the entries in the one list. | |
4311 | */ | |
33a2ffce | 4312 | curr_sg = cp->SG; |
b3a7ba7c WS |
4313 | chained = use_sg > h->max_cmd_sg_entries; |
4314 | sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; | |
4315 | last_sg = scsi_sg_count(cmd) - 1; | |
4316 | scsi_for_each_sg(cmd, sg, sg_limit, i) { | |
ec5cbf04 | 4317 | hpsa_set_sg_descriptor(curr_sg, sg); |
33a2ffce SC |
4318 | curr_sg++; |
4319 | } | |
ec5cbf04 | 4320 | |
b3a7ba7c WS |
4321 | if (chained) { |
4322 | /* | |
4323 | * Continue with the chained list. Set curr_sg to the chained | |
4324 | * list. Modify the limit to the total count less the entries | |
4325 | * we've already set up. Resume the scan at the list entry | |
4326 | * where the previous loop left off. | |
4327 | */ | |
4328 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
4329 | sg_limit = use_sg - sg_limit; | |
4330 | for_each_sg(sg, sg, sg_limit, i) { | |
4331 | hpsa_set_sg_descriptor(curr_sg, sg); | |
4332 | curr_sg++; | |
4333 | } | |
4334 | } | |
4335 | ||
ec5cbf04 | 4336 | /* Back the pointer up to the last entry and mark it as "last". */ |
b3a7ba7c | 4337 | (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); |
33a2ffce SC |
4338 | |
4339 | if (use_sg + chained > h->maxSG) | |
4340 | h->maxSG = use_sg + chained; | |
4341 | ||
4342 | if (chained) { | |
4343 | cp->Header.SGList = h->max_cmd_sg_entries; | |
50a0decf | 4344 | cp->Header.SGTotal = cpu_to_le16(use_sg + 1); |
e2bea6df SC |
4345 | if (hpsa_map_sg_chain_block(h, cp)) { |
4346 | scsi_dma_unmap(cmd); | |
4347 | return -1; | |
4348 | } | |
33a2ffce | 4349 | return 0; |
edd16368 SC |
4350 | } |
4351 | ||
4352 | sglist_finished: | |
4353 | ||
01a02ffc | 4354 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
c7ee65b3 | 4355 | cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ |
edd16368 SC |
4356 | return 0; |
4357 | } | |
4358 | ||
283b4a9b SC |
4359 | #define IO_ACCEL_INELIGIBLE (1) |
4360 | static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) | |
4361 | { | |
4362 | int is_write = 0; | |
4363 | u32 block; | |
4364 | u32 block_cnt; | |
4365 | ||
4366 | /* Perform some CDB fixups if needed using 10 byte reads/writes only */ | |
4367 | switch (cdb[0]) { | |
4368 | case WRITE_6: | |
4369 | case WRITE_12: | |
4370 | is_write = 1; | |
4371 | case READ_6: | |
4372 | case READ_12: | |
4373 | if (*cdb_len == 6) { | |
c8a6c9a6 | 4374 | block = get_unaligned_be16(&cdb[2]); |
283b4a9b | 4375 | block_cnt = cdb[4]; |
c8a6c9a6 DB |
4376 | if (block_cnt == 0) |
4377 | block_cnt = 256; | |
283b4a9b SC |
4378 | } else { |
4379 | BUG_ON(*cdb_len != 12); | |
c8a6c9a6 DB |
4380 | block = get_unaligned_be32(&cdb[2]); |
4381 | block_cnt = get_unaligned_be32(&cdb[6]); | |
283b4a9b SC |
4382 | } |
4383 | if (block_cnt > 0xffff) | |
4384 | return IO_ACCEL_INELIGIBLE; | |
4385 | ||
4386 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
4387 | cdb[1] = 0; | |
4388 | cdb[2] = (u8) (block >> 24); | |
4389 | cdb[3] = (u8) (block >> 16); | |
4390 | cdb[4] = (u8) (block >> 8); | |
4391 | cdb[5] = (u8) (block); | |
4392 | cdb[6] = 0; | |
4393 | cdb[7] = (u8) (block_cnt >> 8); | |
4394 | cdb[8] = (u8) (block_cnt); | |
4395 | cdb[9] = 0; | |
4396 | *cdb_len = 10; | |
4397 | break; | |
4398 | } | |
4399 | return 0; | |
4400 | } | |
4401 | ||
c349775e | 4402 | static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, |
283b4a9b | 4403 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, |
03383736 | 4404 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
e1f7de0c MG |
4405 | { |
4406 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
e1f7de0c MG |
4407 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; |
4408 | unsigned int len; | |
4409 | unsigned int total_len = 0; | |
4410 | struct scatterlist *sg; | |
4411 | u64 addr64; | |
4412 | int use_sg, i; | |
4413 | struct SGDescriptor *curr_sg; | |
4414 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
4415 | ||
283b4a9b | 4416 | /* TODO: implement chaining support */ |
03383736 DB |
4417 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { |
4418 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4419 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4420 | } |
283b4a9b | 4421 | |
e1f7de0c MG |
4422 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); |
4423 | ||
03383736 DB |
4424 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4425 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4426 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4427 | } |
283b4a9b | 4428 | |
e1f7de0c MG |
4429 | c->cmd_type = CMD_IOACCEL1; |
4430 | ||
4431 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4432 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
4433 | (c->cmdindex * sizeof(*cp)); | |
4434 | BUG_ON(c->busaddr & 0x0000007F); | |
4435 | ||
4436 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4437 | if (use_sg < 0) { |
4438 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
e1f7de0c | 4439 | return use_sg; |
03383736 | 4440 | } |
e1f7de0c MG |
4441 | |
4442 | if (use_sg) { | |
4443 | curr_sg = cp->SG; | |
4444 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
4445 | addr64 = (u64) sg_dma_address(sg); | |
4446 | len = sg_dma_len(sg); | |
4447 | total_len += len; | |
50a0decf SC |
4448 | curr_sg->Addr = cpu_to_le64(addr64); |
4449 | curr_sg->Len = cpu_to_le32(len); | |
4450 | curr_sg->Ext = cpu_to_le32(0); | |
e1f7de0c MG |
4451 | curr_sg++; |
4452 | } | |
50a0decf | 4453 | (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); |
e1f7de0c MG |
4454 | |
4455 | switch (cmd->sc_data_direction) { | |
4456 | case DMA_TO_DEVICE: | |
4457 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
4458 | break; | |
4459 | case DMA_FROM_DEVICE: | |
4460 | control |= IOACCEL1_CONTROL_DATA_IN; | |
4461 | break; | |
4462 | case DMA_NONE: | |
4463 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4464 | break; | |
4465 | default: | |
4466 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4467 | cmd->sc_data_direction); | |
4468 | BUG(); | |
4469 | break; | |
4470 | } | |
4471 | } else { | |
4472 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4473 | } | |
4474 | ||
c349775e | 4475 | c->Header.SGList = use_sg; |
e1f7de0c | 4476 | /* Fill out the command structure to submit */ |
2b08b3e9 DB |
4477 | cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); |
4478 | cp->transfer_len = cpu_to_le32(total_len); | |
4479 | cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | | |
4480 | (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); | |
4481 | cp->control = cpu_to_le32(control); | |
283b4a9b SC |
4482 | memcpy(cp->CDB, cdb, cdb_len); |
4483 | memcpy(cp->CISS_LUN, scsi3addr, 8); | |
c349775e | 4484 | /* Tag was already set at init time. */ |
283b4a9b | 4485 | enqueue_cmd_and_start_io(h, c); |
e1f7de0c MG |
4486 | return 0; |
4487 | } | |
edd16368 | 4488 | |
283b4a9b SC |
4489 | /* |
4490 | * Queue a command directly to a device behind the controller using the | |
4491 | * I/O accelerator path. | |
4492 | */ | |
4493 | static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, | |
4494 | struct CommandList *c) | |
4495 | { | |
4496 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4497 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4498 | ||
03383736 DB |
4499 | c->phys_disk = dev; |
4500 | ||
283b4a9b | 4501 | return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, |
03383736 | 4502 | cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); |
283b4a9b SC |
4503 | } |
4504 | ||
dd0e19f3 ST |
4505 | /* |
4506 | * Set encryption parameters for the ioaccel2 request | |
4507 | */ | |
4508 | static void set_encrypt_ioaccel2(struct ctlr_info *h, | |
4509 | struct CommandList *c, struct io_accel2_cmd *cp) | |
4510 | { | |
4511 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4512 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4513 | struct raid_map_data *map = &dev->raid_map; | |
4514 | u64 first_block; | |
4515 | ||
dd0e19f3 | 4516 | /* Are we doing encryption on this device */ |
2b08b3e9 | 4517 | if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) |
dd0e19f3 ST |
4518 | return; |
4519 | /* Set the data encryption key index. */ | |
4520 | cp->dekindex = map->dekindex; | |
4521 | ||
4522 | /* Set the encryption enable flag, encoded into direction field. */ | |
4523 | cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; | |
4524 | ||
4525 | /* Set encryption tweak values based on logical block address | |
4526 | * If block size is 512, tweak value is LBA. | |
4527 | * For other block sizes, tweak is (LBA * block size)/ 512) | |
4528 | */ | |
4529 | switch (cmd->cmnd[0]) { | |
4530 | /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ | |
4531 | case WRITE_6: | |
4532 | case READ_6: | |
2b08b3e9 | 4533 | first_block = get_unaligned_be16(&cmd->cmnd[2]); |
dd0e19f3 ST |
4534 | break; |
4535 | case WRITE_10: | |
4536 | case READ_10: | |
dd0e19f3 ST |
4537 | /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ |
4538 | case WRITE_12: | |
4539 | case READ_12: | |
2b08b3e9 | 4540 | first_block = get_unaligned_be32(&cmd->cmnd[2]); |
dd0e19f3 ST |
4541 | break; |
4542 | case WRITE_16: | |
4543 | case READ_16: | |
2b08b3e9 | 4544 | first_block = get_unaligned_be64(&cmd->cmnd[2]); |
dd0e19f3 ST |
4545 | break; |
4546 | default: | |
4547 | dev_err(&h->pdev->dev, | |
2b08b3e9 DB |
4548 | "ERROR: %s: size (0x%x) not supported for encryption\n", |
4549 | __func__, cmd->cmnd[0]); | |
dd0e19f3 ST |
4550 | BUG(); |
4551 | break; | |
4552 | } | |
2b08b3e9 DB |
4553 | |
4554 | if (le32_to_cpu(map->volume_blk_size) != 512) | |
4555 | first_block = first_block * | |
4556 | le32_to_cpu(map->volume_blk_size)/512; | |
4557 | ||
4558 | cp->tweak_lower = cpu_to_le32(first_block); | |
4559 | cp->tweak_upper = cpu_to_le32(first_block >> 32); | |
dd0e19f3 ST |
4560 | } |
4561 | ||
c349775e ST |
4562 | static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, |
4563 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 4564 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e ST |
4565 | { |
4566 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4567 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
4568 | struct ioaccel2_sg_element *curr_sg; | |
4569 | int use_sg, i; | |
4570 | struct scatterlist *sg; | |
4571 | u64 addr64; | |
4572 | u32 len; | |
4573 | u32 total_len = 0; | |
4574 | ||
d9a729f3 | 4575 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
c349775e | 4576 | |
03383736 DB |
4577 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4578 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4579 | return IO_ACCEL_INELIGIBLE; |
03383736 DB |
4580 | } |
4581 | ||
c349775e ST |
4582 | c->cmd_type = CMD_IOACCEL2; |
4583 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4584 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
4585 | (c->cmdindex * sizeof(*cp)); | |
4586 | BUG_ON(c->busaddr & 0x0000007F); | |
4587 | ||
4588 | memset(cp, 0, sizeof(*cp)); | |
4589 | cp->IU_type = IOACCEL2_IU_TYPE; | |
4590 | ||
4591 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4592 | if (use_sg < 0) { |
4593 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4594 | return use_sg; |
03383736 | 4595 | } |
c349775e ST |
4596 | |
4597 | if (use_sg) { | |
c349775e | 4598 | curr_sg = cp->sg; |
d9a729f3 WS |
4599 | if (use_sg > h->ioaccel_maxsg) { |
4600 | addr64 = le64_to_cpu( | |
4601 | h->ioaccel2_cmd_sg_list[c->cmdindex]->address); | |
4602 | curr_sg->address = cpu_to_le64(addr64); | |
4603 | curr_sg->length = 0; | |
4604 | curr_sg->reserved[0] = 0; | |
4605 | curr_sg->reserved[1] = 0; | |
4606 | curr_sg->reserved[2] = 0; | |
4607 | curr_sg->chain_indicator = 0x80; | |
4608 | ||
4609 | curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
4610 | } | |
c349775e ST |
4611 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
4612 | addr64 = (u64) sg_dma_address(sg); | |
4613 | len = sg_dma_len(sg); | |
4614 | total_len += len; | |
4615 | curr_sg->address = cpu_to_le64(addr64); | |
4616 | curr_sg->length = cpu_to_le32(len); | |
4617 | curr_sg->reserved[0] = 0; | |
4618 | curr_sg->reserved[1] = 0; | |
4619 | curr_sg->reserved[2] = 0; | |
4620 | curr_sg->chain_indicator = 0; | |
4621 | curr_sg++; | |
4622 | } | |
4623 | ||
4624 | switch (cmd->sc_data_direction) { | |
4625 | case DMA_TO_DEVICE: | |
dd0e19f3 ST |
4626 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4627 | cp->direction |= IOACCEL2_DIR_DATA_OUT; | |
c349775e ST |
4628 | break; |
4629 | case DMA_FROM_DEVICE: | |
dd0e19f3 ST |
4630 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4631 | cp->direction |= IOACCEL2_DIR_DATA_IN; | |
c349775e ST |
4632 | break; |
4633 | case DMA_NONE: | |
dd0e19f3 ST |
4634 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4635 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e ST |
4636 | break; |
4637 | default: | |
4638 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4639 | cmd->sc_data_direction); | |
4640 | BUG(); | |
4641 | break; | |
4642 | } | |
4643 | } else { | |
dd0e19f3 ST |
4644 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4645 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e | 4646 | } |
dd0e19f3 ST |
4647 | |
4648 | /* Set encryption parameters, if necessary */ | |
4649 | set_encrypt_ioaccel2(h, c, cp); | |
4650 | ||
2b08b3e9 | 4651 | cp->scsi_nexus = cpu_to_le32(ioaccel_handle); |
f2405db8 | 4652 | cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); |
c349775e | 4653 | memcpy(cp->cdb, cdb, sizeof(cp->cdb)); |
c349775e | 4654 | |
c349775e ST |
4655 | cp->data_len = cpu_to_le32(total_len); |
4656 | cp->err_ptr = cpu_to_le64(c->busaddr + | |
4657 | offsetof(struct io_accel2_cmd, error_data)); | |
50a0decf | 4658 | cp->err_len = cpu_to_le32(sizeof(cp->error_data)); |
c349775e | 4659 | |
d9a729f3 WS |
4660 | /* fill in sg elements */ |
4661 | if (use_sg > h->ioaccel_maxsg) { | |
4662 | cp->sg_count = 1; | |
a736e9b6 | 4663 | cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); |
d9a729f3 WS |
4664 | if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { |
4665 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4666 | scsi_dma_unmap(cmd); | |
4667 | return -1; | |
4668 | } | |
4669 | } else | |
4670 | cp->sg_count = (u8) use_sg; | |
4671 | ||
c349775e ST |
4672 | enqueue_cmd_and_start_io(h, c); |
4673 | return 0; | |
4674 | } | |
4675 | ||
4676 | /* | |
4677 | * Queue a command to the correct I/O accelerator path. | |
4678 | */ | |
4679 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
4680 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 4681 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e | 4682 | { |
03383736 DB |
4683 | /* Try to honor the device's queue depth */ |
4684 | if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > | |
4685 | phys_disk->queue_depth) { | |
4686 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4687 | return IO_ACCEL_INELIGIBLE; | |
4688 | } | |
c349775e ST |
4689 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
4690 | return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
4691 | cdb, cdb_len, scsi3addr, |
4692 | phys_disk); | |
c349775e ST |
4693 | else |
4694 | return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
4695 | cdb, cdb_len, scsi3addr, |
4696 | phys_disk); | |
c349775e ST |
4697 | } |
4698 | ||
6b80b18f ST |
4699 | static void raid_map_helper(struct raid_map_data *map, |
4700 | int offload_to_mirror, u32 *map_index, u32 *current_group) | |
4701 | { | |
4702 | if (offload_to_mirror == 0) { | |
4703 | /* use physical disk in the first mirrored group. */ | |
2b08b3e9 | 4704 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4705 | return; |
4706 | } | |
4707 | do { | |
4708 | /* determine mirror group that *map_index indicates */ | |
2b08b3e9 DB |
4709 | *current_group = *map_index / |
4710 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f ST |
4711 | if (offload_to_mirror == *current_group) |
4712 | continue; | |
2b08b3e9 | 4713 | if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { |
6b80b18f | 4714 | /* select map index from next group */ |
2b08b3e9 | 4715 | *map_index += le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4716 | (*current_group)++; |
4717 | } else { | |
4718 | /* select map index from first group */ | |
2b08b3e9 | 4719 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
4720 | *current_group = 0; |
4721 | } | |
4722 | } while (offload_to_mirror != *current_group); | |
4723 | } | |
4724 | ||
283b4a9b SC |
4725 | /* |
4726 | * Attempt to perform offload RAID mapping for a logical volume I/O. | |
4727 | */ | |
4728 | static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, | |
4729 | struct CommandList *c) | |
4730 | { | |
4731 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4732 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4733 | struct raid_map_data *map = &dev->raid_map; | |
4734 | struct raid_map_disk_data *dd = &map->data[0]; | |
4735 | int is_write = 0; | |
4736 | u32 map_index; | |
4737 | u64 first_block, last_block; | |
4738 | u32 block_cnt; | |
4739 | u32 blocks_per_row; | |
4740 | u64 first_row, last_row; | |
4741 | u32 first_row_offset, last_row_offset; | |
4742 | u32 first_column, last_column; | |
6b80b18f ST |
4743 | u64 r0_first_row, r0_last_row; |
4744 | u32 r5or6_blocks_per_row; | |
4745 | u64 r5or6_first_row, r5or6_last_row; | |
4746 | u32 r5or6_first_row_offset, r5or6_last_row_offset; | |
4747 | u32 r5or6_first_column, r5or6_last_column; | |
4748 | u32 total_disks_per_row; | |
4749 | u32 stripesize; | |
4750 | u32 first_group, last_group, current_group; | |
283b4a9b SC |
4751 | u32 map_row; |
4752 | u32 disk_handle; | |
4753 | u64 disk_block; | |
4754 | u32 disk_block_cnt; | |
4755 | u8 cdb[16]; | |
4756 | u8 cdb_len; | |
2b08b3e9 | 4757 | u16 strip_size; |
283b4a9b SC |
4758 | #if BITS_PER_LONG == 32 |
4759 | u64 tmpdiv; | |
4760 | #endif | |
6b80b18f | 4761 | int offload_to_mirror; |
283b4a9b | 4762 | |
283b4a9b SC |
4763 | /* check for valid opcode, get LBA and block count */ |
4764 | switch (cmd->cmnd[0]) { | |
4765 | case WRITE_6: | |
4766 | is_write = 1; | |
4767 | case READ_6: | |
c8a6c9a6 | 4768 | first_block = get_unaligned_be16(&cmd->cmnd[2]); |
283b4a9b | 4769 | block_cnt = cmd->cmnd[4]; |
3fa89a04 SC |
4770 | if (block_cnt == 0) |
4771 | block_cnt = 256; | |
283b4a9b SC |
4772 | break; |
4773 | case WRITE_10: | |
4774 | is_write = 1; | |
4775 | case READ_10: | |
4776 | first_block = | |
4777 | (((u64) cmd->cmnd[2]) << 24) | | |
4778 | (((u64) cmd->cmnd[3]) << 16) | | |
4779 | (((u64) cmd->cmnd[4]) << 8) | | |
4780 | cmd->cmnd[5]; | |
4781 | block_cnt = | |
4782 | (((u32) cmd->cmnd[7]) << 8) | | |
4783 | cmd->cmnd[8]; | |
4784 | break; | |
4785 | case WRITE_12: | |
4786 | is_write = 1; | |
4787 | case READ_12: | |
4788 | first_block = | |
4789 | (((u64) cmd->cmnd[2]) << 24) | | |
4790 | (((u64) cmd->cmnd[3]) << 16) | | |
4791 | (((u64) cmd->cmnd[4]) << 8) | | |
4792 | cmd->cmnd[5]; | |
4793 | block_cnt = | |
4794 | (((u32) cmd->cmnd[6]) << 24) | | |
4795 | (((u32) cmd->cmnd[7]) << 16) | | |
4796 | (((u32) cmd->cmnd[8]) << 8) | | |
4797 | cmd->cmnd[9]; | |
4798 | break; | |
4799 | case WRITE_16: | |
4800 | is_write = 1; | |
4801 | case READ_16: | |
4802 | first_block = | |
4803 | (((u64) cmd->cmnd[2]) << 56) | | |
4804 | (((u64) cmd->cmnd[3]) << 48) | | |
4805 | (((u64) cmd->cmnd[4]) << 40) | | |
4806 | (((u64) cmd->cmnd[5]) << 32) | | |
4807 | (((u64) cmd->cmnd[6]) << 24) | | |
4808 | (((u64) cmd->cmnd[7]) << 16) | | |
4809 | (((u64) cmd->cmnd[8]) << 8) | | |
4810 | cmd->cmnd[9]; | |
4811 | block_cnt = | |
4812 | (((u32) cmd->cmnd[10]) << 24) | | |
4813 | (((u32) cmd->cmnd[11]) << 16) | | |
4814 | (((u32) cmd->cmnd[12]) << 8) | | |
4815 | cmd->cmnd[13]; | |
4816 | break; | |
4817 | default: | |
4818 | return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ | |
4819 | } | |
283b4a9b SC |
4820 | last_block = first_block + block_cnt - 1; |
4821 | ||
4822 | /* check for write to non-RAID-0 */ | |
4823 | if (is_write && dev->raid_level != 0) | |
4824 | return IO_ACCEL_INELIGIBLE; | |
4825 | ||
4826 | /* check for invalid block or wraparound */ | |
2b08b3e9 DB |
4827 | if (last_block >= le64_to_cpu(map->volume_blk_cnt) || |
4828 | last_block < first_block) | |
283b4a9b SC |
4829 | return IO_ACCEL_INELIGIBLE; |
4830 | ||
4831 | /* calculate stripe information for the request */ | |
2b08b3e9 DB |
4832 | blocks_per_row = le16_to_cpu(map->data_disks_per_row) * |
4833 | le16_to_cpu(map->strip_size); | |
4834 | strip_size = le16_to_cpu(map->strip_size); | |
283b4a9b SC |
4835 | #if BITS_PER_LONG == 32 |
4836 | tmpdiv = first_block; | |
4837 | (void) do_div(tmpdiv, blocks_per_row); | |
4838 | first_row = tmpdiv; | |
4839 | tmpdiv = last_block; | |
4840 | (void) do_div(tmpdiv, blocks_per_row); | |
4841 | last_row = tmpdiv; | |
4842 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
4843 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
4844 | tmpdiv = first_row_offset; | |
2b08b3e9 | 4845 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
4846 | first_column = tmpdiv; |
4847 | tmpdiv = last_row_offset; | |
2b08b3e9 | 4848 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
4849 | last_column = tmpdiv; |
4850 | #else | |
4851 | first_row = first_block / blocks_per_row; | |
4852 | last_row = last_block / blocks_per_row; | |
4853 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
4854 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2b08b3e9 DB |
4855 | first_column = first_row_offset / strip_size; |
4856 | last_column = last_row_offset / strip_size; | |
283b4a9b SC |
4857 | #endif |
4858 | ||
4859 | /* if this isn't a single row/column then give to the controller */ | |
4860 | if ((first_row != last_row) || (first_column != last_column)) | |
4861 | return IO_ACCEL_INELIGIBLE; | |
4862 | ||
4863 | /* proceeding with driver mapping */ | |
2b08b3e9 DB |
4864 | total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + |
4865 | le16_to_cpu(map->metadata_disks_per_row); | |
283b4a9b | 4866 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % |
2b08b3e9 | 4867 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
4868 | map_index = (map_row * total_disks_per_row) + first_column; |
4869 | ||
4870 | switch (dev->raid_level) { | |
4871 | case HPSA_RAID_0: | |
4872 | break; /* nothing special to do */ | |
4873 | case HPSA_RAID_1: | |
4874 | /* Handles load balance across RAID 1 members. | |
4875 | * (2-drive R1 and R10 with even # of drives.) | |
4876 | * Appropriate for SSDs, not optimal for HDDs | |
283b4a9b | 4877 | */ |
2b08b3e9 | 4878 | BUG_ON(le16_to_cpu(map->layout_map_count) != 2); |
283b4a9b | 4879 | if (dev->offload_to_mirror) |
2b08b3e9 | 4880 | map_index += le16_to_cpu(map->data_disks_per_row); |
283b4a9b | 4881 | dev->offload_to_mirror = !dev->offload_to_mirror; |
6b80b18f ST |
4882 | break; |
4883 | case HPSA_RAID_ADM: | |
4884 | /* Handles N-way mirrors (R1-ADM) | |
4885 | * and R10 with # of drives divisible by 3.) | |
4886 | */ | |
2b08b3e9 | 4887 | BUG_ON(le16_to_cpu(map->layout_map_count) != 3); |
6b80b18f ST |
4888 | |
4889 | offload_to_mirror = dev->offload_to_mirror; | |
4890 | raid_map_helper(map, offload_to_mirror, | |
4891 | &map_index, ¤t_group); | |
4892 | /* set mirror group to use next time */ | |
4893 | offload_to_mirror = | |
2b08b3e9 DB |
4894 | (offload_to_mirror >= |
4895 | le16_to_cpu(map->layout_map_count) - 1) | |
6b80b18f | 4896 | ? 0 : offload_to_mirror + 1; |
6b80b18f ST |
4897 | dev->offload_to_mirror = offload_to_mirror; |
4898 | /* Avoid direct use of dev->offload_to_mirror within this | |
4899 | * function since multiple threads might simultaneously | |
4900 | * increment it beyond the range of dev->layout_map_count -1. | |
4901 | */ | |
4902 | break; | |
4903 | case HPSA_RAID_5: | |
4904 | case HPSA_RAID_6: | |
2b08b3e9 | 4905 | if (le16_to_cpu(map->layout_map_count) <= 1) |
6b80b18f ST |
4906 | break; |
4907 | ||
4908 | /* Verify first and last block are in same RAID group */ | |
4909 | r5or6_blocks_per_row = | |
2b08b3e9 DB |
4910 | le16_to_cpu(map->strip_size) * |
4911 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f | 4912 | BUG_ON(r5or6_blocks_per_row == 0); |
2b08b3e9 DB |
4913 | stripesize = r5or6_blocks_per_row * |
4914 | le16_to_cpu(map->layout_map_count); | |
6b80b18f ST |
4915 | #if BITS_PER_LONG == 32 |
4916 | tmpdiv = first_block; | |
4917 | first_group = do_div(tmpdiv, stripesize); | |
4918 | tmpdiv = first_group; | |
4919 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
4920 | first_group = tmpdiv; | |
4921 | tmpdiv = last_block; | |
4922 | last_group = do_div(tmpdiv, stripesize); | |
4923 | tmpdiv = last_group; | |
4924 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
4925 | last_group = tmpdiv; | |
4926 | #else | |
4927 | first_group = (first_block % stripesize) / r5or6_blocks_per_row; | |
4928 | last_group = (last_block % stripesize) / r5or6_blocks_per_row; | |
6b80b18f | 4929 | #endif |
000ff7c2 | 4930 | if (first_group != last_group) |
6b80b18f ST |
4931 | return IO_ACCEL_INELIGIBLE; |
4932 | ||
4933 | /* Verify request is in a single row of RAID 5/6 */ | |
4934 | #if BITS_PER_LONG == 32 | |
4935 | tmpdiv = first_block; | |
4936 | (void) do_div(tmpdiv, stripesize); | |
4937 | first_row = r5or6_first_row = r0_first_row = tmpdiv; | |
4938 | tmpdiv = last_block; | |
4939 | (void) do_div(tmpdiv, stripesize); | |
4940 | r5or6_last_row = r0_last_row = tmpdiv; | |
4941 | #else | |
4942 | first_row = r5or6_first_row = r0_first_row = | |
4943 | first_block / stripesize; | |
4944 | r5or6_last_row = r0_last_row = last_block / stripesize; | |
4945 | #endif | |
4946 | if (r5or6_first_row != r5or6_last_row) | |
4947 | return IO_ACCEL_INELIGIBLE; | |
4948 | ||
4949 | ||
4950 | /* Verify request is in a single column */ | |
4951 | #if BITS_PER_LONG == 32 | |
4952 | tmpdiv = first_block; | |
4953 | first_row_offset = do_div(tmpdiv, stripesize); | |
4954 | tmpdiv = first_row_offset; | |
4955 | first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); | |
4956 | r5or6_first_row_offset = first_row_offset; | |
4957 | tmpdiv = last_block; | |
4958 | r5or6_last_row_offset = do_div(tmpdiv, stripesize); | |
4959 | tmpdiv = r5or6_last_row_offset; | |
4960 | r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); | |
4961 | tmpdiv = r5or6_first_row_offset; | |
4962 | (void) do_div(tmpdiv, map->strip_size); | |
4963 | first_column = r5or6_first_column = tmpdiv; | |
4964 | tmpdiv = r5or6_last_row_offset; | |
4965 | (void) do_div(tmpdiv, map->strip_size); | |
4966 | r5or6_last_column = tmpdiv; | |
4967 | #else | |
4968 | first_row_offset = r5or6_first_row_offset = | |
4969 | (u32)((first_block % stripesize) % | |
4970 | r5or6_blocks_per_row); | |
4971 | ||
4972 | r5or6_last_row_offset = | |
4973 | (u32)((last_block % stripesize) % | |
4974 | r5or6_blocks_per_row); | |
4975 | ||
4976 | first_column = r5or6_first_column = | |
2b08b3e9 | 4977 | r5or6_first_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f | 4978 | r5or6_last_column = |
2b08b3e9 | 4979 | r5or6_last_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f ST |
4980 | #endif |
4981 | if (r5or6_first_column != r5or6_last_column) | |
4982 | return IO_ACCEL_INELIGIBLE; | |
4983 | ||
4984 | /* Request is eligible */ | |
4985 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % | |
2b08b3e9 | 4986 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
4987 | |
4988 | map_index = (first_group * | |
2b08b3e9 | 4989 | (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + |
6b80b18f ST |
4990 | (map_row * total_disks_per_row) + first_column; |
4991 | break; | |
4992 | default: | |
4993 | return IO_ACCEL_INELIGIBLE; | |
283b4a9b | 4994 | } |
6b80b18f | 4995 | |
07543e0c SC |
4996 | if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) |
4997 | return IO_ACCEL_INELIGIBLE; | |
4998 | ||
03383736 | 4999 | c->phys_disk = dev->phys_disk[map_index]; |
c3390df4 DB |
5000 | if (!c->phys_disk) |
5001 | return IO_ACCEL_INELIGIBLE; | |
03383736 | 5002 | |
283b4a9b | 5003 | disk_handle = dd[map_index].ioaccel_handle; |
2b08b3e9 DB |
5004 | disk_block = le64_to_cpu(map->disk_starting_blk) + |
5005 | first_row * le16_to_cpu(map->strip_size) + | |
5006 | (first_row_offset - first_column * | |
5007 | le16_to_cpu(map->strip_size)); | |
283b4a9b SC |
5008 | disk_block_cnt = block_cnt; |
5009 | ||
5010 | /* handle differing logical/physical block sizes */ | |
5011 | if (map->phys_blk_shift) { | |
5012 | disk_block <<= map->phys_blk_shift; | |
5013 | disk_block_cnt <<= map->phys_blk_shift; | |
5014 | } | |
5015 | BUG_ON(disk_block_cnt > 0xffff); | |
5016 | ||
5017 | /* build the new CDB for the physical disk I/O */ | |
5018 | if (disk_block > 0xffffffff) { | |
5019 | cdb[0] = is_write ? WRITE_16 : READ_16; | |
5020 | cdb[1] = 0; | |
5021 | cdb[2] = (u8) (disk_block >> 56); | |
5022 | cdb[3] = (u8) (disk_block >> 48); | |
5023 | cdb[4] = (u8) (disk_block >> 40); | |
5024 | cdb[5] = (u8) (disk_block >> 32); | |
5025 | cdb[6] = (u8) (disk_block >> 24); | |
5026 | cdb[7] = (u8) (disk_block >> 16); | |
5027 | cdb[8] = (u8) (disk_block >> 8); | |
5028 | cdb[9] = (u8) (disk_block); | |
5029 | cdb[10] = (u8) (disk_block_cnt >> 24); | |
5030 | cdb[11] = (u8) (disk_block_cnt >> 16); | |
5031 | cdb[12] = (u8) (disk_block_cnt >> 8); | |
5032 | cdb[13] = (u8) (disk_block_cnt); | |
5033 | cdb[14] = 0; | |
5034 | cdb[15] = 0; | |
5035 | cdb_len = 16; | |
5036 | } else { | |
5037 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
5038 | cdb[1] = 0; | |
5039 | cdb[2] = (u8) (disk_block >> 24); | |
5040 | cdb[3] = (u8) (disk_block >> 16); | |
5041 | cdb[4] = (u8) (disk_block >> 8); | |
5042 | cdb[5] = (u8) (disk_block); | |
5043 | cdb[6] = 0; | |
5044 | cdb[7] = (u8) (disk_block_cnt >> 8); | |
5045 | cdb[8] = (u8) (disk_block_cnt); | |
5046 | cdb[9] = 0; | |
5047 | cdb_len = 10; | |
5048 | } | |
5049 | return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, | |
03383736 DB |
5050 | dev->scsi3addr, |
5051 | dev->phys_disk[map_index]); | |
283b4a9b SC |
5052 | } |
5053 | ||
25163bd5 WS |
5054 | /* |
5055 | * Submit commands down the "normal" RAID stack path | |
5056 | * All callers to hpsa_ciss_submit must check lockup_detected | |
5057 | * beforehand, before (opt.) and after calling cmd_alloc | |
5058 | */ | |
574f05d3 SC |
5059 | static int hpsa_ciss_submit(struct ctlr_info *h, |
5060 | struct CommandList *c, struct scsi_cmnd *cmd, | |
5061 | unsigned char scsi3addr[]) | |
edd16368 | 5062 | { |
edd16368 | 5063 | cmd->host_scribble = (unsigned char *) c; |
edd16368 SC |
5064 | c->cmd_type = CMD_SCSI; |
5065 | c->scsi_cmd = cmd; | |
5066 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
5067 | memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); | |
f2405db8 | 5068 | c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); |
edd16368 SC |
5069 | |
5070 | /* Fill in the request block... */ | |
5071 | ||
5072 | c->Request.Timeout = 0; | |
edd16368 SC |
5073 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); |
5074 | c->Request.CDBLen = cmd->cmd_len; | |
5075 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
edd16368 SC |
5076 | switch (cmd->sc_data_direction) { |
5077 | case DMA_TO_DEVICE: | |
a505b86f SC |
5078 | c->Request.type_attr_dir = |
5079 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
5080 | break; |
5081 | case DMA_FROM_DEVICE: | |
a505b86f SC |
5082 | c->Request.type_attr_dir = |
5083 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
5084 | break; |
5085 | case DMA_NONE: | |
a505b86f SC |
5086 | c->Request.type_attr_dir = |
5087 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
5088 | break; |
5089 | case DMA_BIDIRECTIONAL: | |
5090 | /* This can happen if a buggy application does a scsi passthru | |
5091 | * and sets both inlen and outlen to non-zero. ( see | |
5092 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
5093 | */ | |
5094 | ||
a505b86f SC |
5095 | c->Request.type_attr_dir = |
5096 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); | |
edd16368 SC |
5097 | /* This is technically wrong, and hpsa controllers should |
5098 | * reject it with CMD_INVALID, which is the most correct | |
5099 | * response, but non-fibre backends appear to let it | |
5100 | * slide by, and give the same results as if this field | |
5101 | * were set correctly. Either way is acceptable for | |
5102 | * our purposes here. | |
5103 | */ | |
5104 | ||
5105 | break; | |
5106 | ||
5107 | default: | |
5108 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
5109 | cmd->sc_data_direction); | |
5110 | BUG(); | |
5111 | break; | |
5112 | } | |
5113 | ||
33a2ffce | 5114 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
73153fe5 | 5115 | hpsa_cmd_resolve_and_free(h, c); |
edd16368 SC |
5116 | return SCSI_MLQUEUE_HOST_BUSY; |
5117 | } | |
5118 | enqueue_cmd_and_start_io(h, c); | |
5119 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
5120 | return 0; | |
5121 | } | |
5122 | ||
360c73bd SC |
5123 | static void hpsa_cmd_init(struct ctlr_info *h, int index, |
5124 | struct CommandList *c) | |
5125 | { | |
5126 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
5127 | ||
5128 | /* Zero out all of commandlist except the last field, refcount */ | |
5129 | memset(c, 0, offsetof(struct CommandList, refcount)); | |
5130 | c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); | |
5131 | cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5132 | c->err_info = h->errinfo_pool + index; | |
5133 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5134 | err_dma_handle = h->errinfo_pool_dhandle | |
5135 | + index * sizeof(*c->err_info); | |
5136 | c->cmdindex = index; | |
5137 | c->busaddr = (u32) cmd_dma_handle; | |
5138 | c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); | |
5139 | c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); | |
5140 | c->h = h; | |
a58e7e53 | 5141 | c->scsi_cmd = SCSI_CMD_IDLE; |
360c73bd SC |
5142 | } |
5143 | ||
5144 | static void hpsa_preinitialize_commands(struct ctlr_info *h) | |
5145 | { | |
5146 | int i; | |
5147 | ||
5148 | for (i = 0; i < h->nr_cmds; i++) { | |
5149 | struct CommandList *c = h->cmd_pool + i; | |
5150 | ||
5151 | hpsa_cmd_init(h, i, c); | |
5152 | atomic_set(&c->refcount, 0); | |
5153 | } | |
5154 | } | |
5155 | ||
5156 | static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, | |
5157 | struct CommandList *c) | |
5158 | { | |
5159 | dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5160 | ||
73153fe5 WS |
5161 | BUG_ON(c->cmdindex != index); |
5162 | ||
360c73bd SC |
5163 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); |
5164 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5165 | c->busaddr = (u32) cmd_dma_handle; | |
5166 | } | |
5167 | ||
592a0ad5 WS |
5168 | static int hpsa_ioaccel_submit(struct ctlr_info *h, |
5169 | struct CommandList *c, struct scsi_cmnd *cmd, | |
5170 | unsigned char *scsi3addr) | |
5171 | { | |
5172 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
5173 | int rc = IO_ACCEL_INELIGIBLE; | |
5174 | ||
5175 | cmd->host_scribble = (unsigned char *) c; | |
5176 | ||
5177 | if (dev->offload_enabled) { | |
5178 | hpsa_cmd_init(h, c->cmdindex, c); | |
5179 | c->cmd_type = CMD_SCSI; | |
5180 | c->scsi_cmd = cmd; | |
5181 | rc = hpsa_scsi_ioaccel_raid_map(h, c); | |
5182 | if (rc < 0) /* scsi_dma_map failed. */ | |
5183 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
a3144e0b | 5184 | } else if (dev->hba_ioaccel_enabled) { |
592a0ad5 WS |
5185 | hpsa_cmd_init(h, c->cmdindex, c); |
5186 | c->cmd_type = CMD_SCSI; | |
5187 | c->scsi_cmd = cmd; | |
5188 | rc = hpsa_scsi_ioaccel_direct_map(h, c); | |
5189 | if (rc < 0) /* scsi_dma_map failed. */ | |
5190 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
5191 | } | |
5192 | return rc; | |
5193 | } | |
5194 | ||
080ef1cc DB |
5195 | static void hpsa_command_resubmit_worker(struct work_struct *work) |
5196 | { | |
5197 | struct scsi_cmnd *cmd; | |
5198 | struct hpsa_scsi_dev_t *dev; | |
8a0ff92c | 5199 | struct CommandList *c = container_of(work, struct CommandList, work); |
080ef1cc DB |
5200 | |
5201 | cmd = c->scsi_cmd; | |
5202 | dev = cmd->device->hostdata; | |
5203 | if (!dev) { | |
5204 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 5205 | return hpsa_cmd_free_and_done(c->h, c, cmd); |
080ef1cc | 5206 | } |
d604f533 WS |
5207 | if (c->reset_pending) |
5208 | return hpsa_cmd_resolve_and_free(c->h, c); | |
a58e7e53 WS |
5209 | if (c->abort_pending) |
5210 | return hpsa_cmd_abort_and_free(c->h, c, cmd); | |
592a0ad5 WS |
5211 | if (c->cmd_type == CMD_IOACCEL2) { |
5212 | struct ctlr_info *h = c->h; | |
5213 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5214 | int rc; | |
5215 | ||
5216 | if (c2->error_data.serv_response == | |
5217 | IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { | |
5218 | rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr); | |
5219 | if (rc == 0) | |
5220 | return; | |
5221 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
5222 | /* | |
5223 | * If we get here, it means dma mapping failed. | |
5224 | * Try again via scsi mid layer, which will | |
5225 | * then get SCSI_MLQUEUE_HOST_BUSY. | |
5226 | */ | |
5227 | cmd->result = DID_IMM_RETRY << 16; | |
8a0ff92c | 5228 | return hpsa_cmd_free_and_done(h, c, cmd); |
592a0ad5 WS |
5229 | } |
5230 | /* else, fall thru and resubmit down CISS path */ | |
5231 | } | |
5232 | } | |
360c73bd | 5233 | hpsa_cmd_partial_init(c->h, c->cmdindex, c); |
080ef1cc DB |
5234 | if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) { |
5235 | /* | |
5236 | * If we get here, it means dma mapping failed. Try | |
5237 | * again via scsi mid layer, which will then get | |
5238 | * SCSI_MLQUEUE_HOST_BUSY. | |
592a0ad5 WS |
5239 | * |
5240 | * hpsa_ciss_submit will have already freed c | |
5241 | * if it encountered a dma mapping failure. | |
080ef1cc DB |
5242 | */ |
5243 | cmd->result = DID_IMM_RETRY << 16; | |
5244 | cmd->scsi_done(cmd); | |
5245 | } | |
5246 | } | |
5247 | ||
574f05d3 SC |
5248 | /* Running in struct Scsi_Host->host_lock less mode */ |
5249 | static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) | |
5250 | { | |
5251 | struct ctlr_info *h; | |
5252 | struct hpsa_scsi_dev_t *dev; | |
5253 | unsigned char scsi3addr[8]; | |
5254 | struct CommandList *c; | |
5255 | int rc = 0; | |
5256 | ||
5257 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
5258 | h = sdev_to_hba(cmd->device); | |
73153fe5 WS |
5259 | |
5260 | BUG_ON(cmd->request->tag < 0); | |
5261 | ||
574f05d3 SC |
5262 | dev = cmd->device->hostdata; |
5263 | if (!dev) { | |
5264 | cmd->result = DID_NO_CONNECT << 16; | |
5265 | cmd->scsi_done(cmd); | |
5266 | return 0; | |
5267 | } | |
574f05d3 | 5268 | |
73153fe5 | 5269 | memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); |
bf43caf3 | 5270 | |
407863cb | 5271 | if (unlikely(lockup_detected(h))) { |
25163bd5 | 5272 | cmd->result = DID_NO_CONNECT << 16; |
407863cb SC |
5273 | cmd->scsi_done(cmd); |
5274 | return 0; | |
5275 | } | |
73153fe5 | 5276 | c = cmd_tagged_alloc(h, cmd); |
574f05d3 | 5277 | |
407863cb SC |
5278 | /* |
5279 | * Call alternate submit routine for I/O accelerated commands. | |
574f05d3 SC |
5280 | * Retries always go down the normal I/O path. |
5281 | */ | |
5282 | if (likely(cmd->retries == 0 && | |
5283 | cmd->request->cmd_type == REQ_TYPE_FS && | |
5284 | h->acciopath_status)) { | |
592a0ad5 WS |
5285 | rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr); |
5286 | if (rc == 0) | |
5287 | return 0; | |
5288 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
73153fe5 | 5289 | hpsa_cmd_resolve_and_free(h, c); |
592a0ad5 | 5290 | return SCSI_MLQUEUE_HOST_BUSY; |
574f05d3 SC |
5291 | } |
5292 | } | |
5293 | return hpsa_ciss_submit(h, c, cmd, scsi3addr); | |
5294 | } | |
5295 | ||
8ebc9248 | 5296 | static void hpsa_scan_complete(struct ctlr_info *h) |
5f389360 SC |
5297 | { |
5298 | unsigned long flags; | |
5299 | ||
8ebc9248 WS |
5300 | spin_lock_irqsave(&h->scan_lock, flags); |
5301 | h->scan_finished = 1; | |
5302 | wake_up_all(&h->scan_wait_queue); | |
5303 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5f389360 SC |
5304 | } |
5305 | ||
a08a8471 SC |
5306 | static void hpsa_scan_start(struct Scsi_Host *sh) |
5307 | { | |
5308 | struct ctlr_info *h = shost_to_hba(sh); | |
5309 | unsigned long flags; | |
5310 | ||
8ebc9248 WS |
5311 | /* |
5312 | * Don't let rescans be initiated on a controller known to be locked | |
5313 | * up. If the controller locks up *during* a rescan, that thread is | |
5314 | * probably hosed, but at least we can prevent new rescan threads from | |
5315 | * piling up on a locked up controller. | |
5316 | */ | |
5317 | if (unlikely(lockup_detected(h))) | |
5318 | return hpsa_scan_complete(h); | |
5f389360 | 5319 | |
a08a8471 SC |
5320 | /* wait until any scan already in progress is finished. */ |
5321 | while (1) { | |
5322 | spin_lock_irqsave(&h->scan_lock, flags); | |
5323 | if (h->scan_finished) | |
5324 | break; | |
5325 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5326 | wait_event(h->scan_wait_queue, h->scan_finished); | |
5327 | /* Note: We don't need to worry about a race between this | |
5328 | * thread and driver unload because the midlayer will | |
5329 | * have incremented the reference count, so unload won't | |
5330 | * happen if we're in here. | |
5331 | */ | |
5332 | } | |
5333 | h->scan_finished = 0; /* mark scan as in progress */ | |
5334 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5335 | ||
8ebc9248 WS |
5336 | if (unlikely(lockup_detected(h))) |
5337 | return hpsa_scan_complete(h); | |
5f389360 | 5338 | |
8aa60681 | 5339 | hpsa_update_scsi_devices(h); |
a08a8471 | 5340 | |
8ebc9248 | 5341 | hpsa_scan_complete(h); |
a08a8471 SC |
5342 | } |
5343 | ||
7c0a0229 DB |
5344 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) |
5345 | { | |
03383736 DB |
5346 | struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; |
5347 | ||
5348 | if (!logical_drive) | |
5349 | return -ENODEV; | |
7c0a0229 DB |
5350 | |
5351 | if (qdepth < 1) | |
5352 | qdepth = 1; | |
03383736 DB |
5353 | else if (qdepth > logical_drive->queue_depth) |
5354 | qdepth = logical_drive->queue_depth; | |
5355 | ||
5356 | return scsi_change_queue_depth(sdev, qdepth); | |
7c0a0229 DB |
5357 | } |
5358 | ||
a08a8471 SC |
5359 | static int hpsa_scan_finished(struct Scsi_Host *sh, |
5360 | unsigned long elapsed_time) | |
5361 | { | |
5362 | struct ctlr_info *h = shost_to_hba(sh); | |
5363 | unsigned long flags; | |
5364 | int finished; | |
5365 | ||
5366 | spin_lock_irqsave(&h->scan_lock, flags); | |
5367 | finished = h->scan_finished; | |
5368 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5369 | return finished; | |
5370 | } | |
5371 | ||
2946e82b | 5372 | static int hpsa_scsi_host_alloc(struct ctlr_info *h) |
edd16368 | 5373 | { |
b705690d | 5374 | struct Scsi_Host *sh; |
edd16368 | 5375 | |
b705690d | 5376 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
2946e82b RE |
5377 | if (sh == NULL) { |
5378 | dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); | |
5379 | return -ENOMEM; | |
5380 | } | |
b705690d SC |
5381 | |
5382 | sh->io_port = 0; | |
5383 | sh->n_io_port = 0; | |
5384 | sh->this_id = -1; | |
5385 | sh->max_channel = 3; | |
5386 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
5387 | sh->max_lun = HPSA_MAX_LUN; | |
5388 | sh->max_id = HPSA_MAX_LUN; | |
41ce4c35 | 5389 | sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; |
03383736 | 5390 | sh->cmd_per_lun = sh->can_queue; |
b705690d | 5391 | sh->sg_tablesize = h->maxsgentries; |
d04e62b9 | 5392 | sh->transportt = hpsa_sas_transport_template; |
b705690d SC |
5393 | sh->hostdata[0] = (unsigned long) h; |
5394 | sh->irq = h->intr[h->intr_mode]; | |
5395 | sh->unique_id = sh->irq; | |
64d513ac | 5396 | |
2946e82b | 5397 | h->scsi_host = sh; |
b705690d | 5398 | return 0; |
2946e82b | 5399 | } |
b705690d | 5400 | |
2946e82b RE |
5401 | static int hpsa_scsi_add_host(struct ctlr_info *h) |
5402 | { | |
5403 | int rv; | |
5404 | ||
5405 | rv = scsi_add_host(h->scsi_host, &h->pdev->dev); | |
5406 | if (rv) { | |
5407 | dev_err(&h->pdev->dev, "scsi_add_host failed\n"); | |
5408 | return rv; | |
5409 | } | |
5410 | scsi_scan_host(h->scsi_host); | |
5411 | return 0; | |
edd16368 SC |
5412 | } |
5413 | ||
73153fe5 WS |
5414 | /* |
5415 | * The block layer has already gone to the trouble of picking out a unique, | |
5416 | * small-integer tag for this request. We use an offset from that value as | |
5417 | * an index to select our command block. (The offset allows us to reserve the | |
5418 | * low-numbered entries for our own uses.) | |
5419 | */ | |
5420 | static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) | |
5421 | { | |
5422 | int idx = scmd->request->tag; | |
5423 | ||
5424 | if (idx < 0) | |
5425 | return idx; | |
5426 | ||
5427 | /* Offset to leave space for internal cmds. */ | |
5428 | return idx += HPSA_NRESERVED_CMDS; | |
5429 | } | |
5430 | ||
b69324ff WS |
5431 | /* |
5432 | * Send a TEST_UNIT_READY command to the specified LUN using the specified | |
5433 | * reply queue; returns zero if the unit is ready, and non-zero otherwise. | |
5434 | */ | |
5435 | static int hpsa_send_test_unit_ready(struct ctlr_info *h, | |
5436 | struct CommandList *c, unsigned char lunaddr[], | |
5437 | int reply_queue) | |
5438 | { | |
5439 | int rc; | |
5440 | ||
5441 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ | |
5442 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
5443 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
c448ecfa | 5444 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); |
b69324ff WS |
5445 | if (rc) |
5446 | return rc; | |
5447 | /* no unmap needed here because no data xfer. */ | |
5448 | ||
5449 | /* Check if the unit is already ready. */ | |
5450 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
5451 | return 0; | |
5452 | ||
5453 | /* | |
5454 | * The first command sent after reset will receive "unit attention" to | |
5455 | * indicate that the LUN has been reset...this is actually what we're | |
5456 | * looking for (but, success is good too). | |
5457 | */ | |
5458 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
5459 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
5460 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
5461 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
5462 | return 0; | |
5463 | ||
5464 | return 1; | |
5465 | } | |
5466 | ||
5467 | /* | |
5468 | * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; | |
5469 | * returns zero when the unit is ready, and non-zero when giving up. | |
5470 | */ | |
5471 | static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, | |
5472 | struct CommandList *c, | |
5473 | unsigned char lunaddr[], int reply_queue) | |
edd16368 | 5474 | { |
8919358e | 5475 | int rc; |
edd16368 SC |
5476 | int count = 0; |
5477 | int waittime = 1; /* seconds */ | |
edd16368 SC |
5478 | |
5479 | /* Send test unit ready until device ready, or give up. */ | |
b69324ff | 5480 | for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { |
edd16368 | 5481 | |
b69324ff WS |
5482 | /* |
5483 | * Wait for a bit. do this first, because if we send | |
edd16368 SC |
5484 | * the TUR right away, the reset will just abort it. |
5485 | */ | |
5486 | msleep(1000 * waittime); | |
b69324ff WS |
5487 | |
5488 | rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); | |
5489 | if (!rc) | |
5490 | break; | |
edd16368 SC |
5491 | |
5492 | /* Increase wait time with each try, up to a point. */ | |
5493 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
b69324ff | 5494 | waittime *= 2; |
edd16368 | 5495 | |
b69324ff WS |
5496 | dev_warn(&h->pdev->dev, |
5497 | "waiting %d secs for device to become ready.\n", | |
5498 | waittime); | |
5499 | } | |
edd16368 | 5500 | |
b69324ff WS |
5501 | return rc; |
5502 | } | |
edd16368 | 5503 | |
b69324ff WS |
5504 | static int wait_for_device_to_become_ready(struct ctlr_info *h, |
5505 | unsigned char lunaddr[], | |
5506 | int reply_queue) | |
5507 | { | |
5508 | int first_queue; | |
5509 | int last_queue; | |
5510 | int rq; | |
5511 | int rc = 0; | |
5512 | struct CommandList *c; | |
5513 | ||
5514 | c = cmd_alloc(h); | |
5515 | ||
5516 | /* | |
5517 | * If no specific reply queue was requested, then send the TUR | |
5518 | * repeatedly, requesting a reply on each reply queue; otherwise execute | |
5519 | * the loop exactly once using only the specified queue. | |
5520 | */ | |
5521 | if (reply_queue == DEFAULT_REPLY_QUEUE) { | |
5522 | first_queue = 0; | |
5523 | last_queue = h->nreply_queues - 1; | |
5524 | } else { | |
5525 | first_queue = reply_queue; | |
5526 | last_queue = reply_queue; | |
5527 | } | |
5528 | ||
5529 | for (rq = first_queue; rq <= last_queue; rq++) { | |
5530 | rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); | |
5531 | if (rc) | |
edd16368 | 5532 | break; |
edd16368 SC |
5533 | } |
5534 | ||
5535 | if (rc) | |
5536 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
5537 | else | |
5538 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
5539 | ||
45fcb86e | 5540 | cmd_free(h, c); |
edd16368 SC |
5541 | return rc; |
5542 | } | |
5543 | ||
5544 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
5545 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
5546 | */ | |
5547 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
5548 | { | |
5549 | int rc; | |
5550 | struct ctlr_info *h; | |
5551 | struct hpsa_scsi_dev_t *dev; | |
0b9b7b6e | 5552 | u8 reset_type; |
2dc127bb | 5553 | char msg[48]; |
edd16368 SC |
5554 | |
5555 | /* find the controller to which the command to be aborted was sent */ | |
5556 | h = sdev_to_hba(scsicmd->device); | |
5557 | if (h == NULL) /* paranoia */ | |
5558 | return FAILED; | |
e345893b DB |
5559 | |
5560 | if (lockup_detected(h)) | |
5561 | return FAILED; | |
5562 | ||
edd16368 SC |
5563 | dev = scsicmd->device->hostdata; |
5564 | if (!dev) { | |
d604f533 | 5565 | dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); |
edd16368 SC |
5566 | return FAILED; |
5567 | } | |
25163bd5 WS |
5568 | |
5569 | /* if controller locked up, we can guarantee command won't complete */ | |
5570 | if (lockup_detected(h)) { | |
2dc127bb DC |
5571 | snprintf(msg, sizeof(msg), |
5572 | "cmd %d RESET FAILED, lockup detected", | |
5573 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 5574 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
25163bd5 WS |
5575 | return FAILED; |
5576 | } | |
5577 | ||
5578 | /* this reset request might be the result of a lockup; check */ | |
5579 | if (detect_controller_lockup(h)) { | |
2dc127bb DC |
5580 | snprintf(msg, sizeof(msg), |
5581 | "cmd %d RESET FAILED, new lockup detected", | |
5582 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 5583 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
25163bd5 WS |
5584 | return FAILED; |
5585 | } | |
5586 | ||
d604f533 WS |
5587 | /* Do not attempt on controller */ |
5588 | if (is_hba_lunid(dev->scsi3addr)) | |
5589 | return SUCCESS; | |
5590 | ||
0b9b7b6e ST |
5591 | if (is_logical_dev_addr_mode(dev->scsi3addr)) |
5592 | reset_type = HPSA_DEVICE_RESET_MSG; | |
5593 | else | |
5594 | reset_type = HPSA_PHYS_TARGET_RESET; | |
5595 | ||
5596 | sprintf(msg, "resetting %s", | |
5597 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); | |
5598 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); | |
25163bd5 | 5599 | |
da03ded0 | 5600 | h->reset_in_progress = 1; |
25163bd5 | 5601 | |
edd16368 | 5602 | /* send a reset to the SCSI LUN which the command was sent to */ |
0b9b7b6e | 5603 | rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type, |
d604f533 | 5604 | DEFAULT_REPLY_QUEUE); |
0b9b7b6e ST |
5605 | sprintf(msg, "reset %s %s", |
5606 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", | |
5607 | rc == 0 ? "completed successfully" : "failed"); | |
d604f533 | 5608 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
da03ded0 | 5609 | h->reset_in_progress = 0; |
d604f533 | 5610 | return rc == 0 ? SUCCESS : FAILED; |
edd16368 SC |
5611 | } |
5612 | ||
6cba3f19 SC |
5613 | static void swizzle_abort_tag(u8 *tag) |
5614 | { | |
5615 | u8 original_tag[8]; | |
5616 | ||
5617 | memcpy(original_tag, tag, 8); | |
5618 | tag[0] = original_tag[3]; | |
5619 | tag[1] = original_tag[2]; | |
5620 | tag[2] = original_tag[1]; | |
5621 | tag[3] = original_tag[0]; | |
5622 | tag[4] = original_tag[7]; | |
5623 | tag[5] = original_tag[6]; | |
5624 | tag[6] = original_tag[5]; | |
5625 | tag[7] = original_tag[4]; | |
5626 | } | |
5627 | ||
17eb87d2 | 5628 | static void hpsa_get_tag(struct ctlr_info *h, |
2b08b3e9 | 5629 | struct CommandList *c, __le32 *taglower, __le32 *tagupper) |
17eb87d2 | 5630 | { |
2b08b3e9 | 5631 | u64 tag; |
17eb87d2 ST |
5632 | if (c->cmd_type == CMD_IOACCEL1) { |
5633 | struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *) | |
5634 | &h->ioaccel_cmd_pool[c->cmdindex]; | |
2b08b3e9 DB |
5635 | tag = le64_to_cpu(cm1->tag); |
5636 | *tagupper = cpu_to_le32(tag >> 32); | |
5637 | *taglower = cpu_to_le32(tag); | |
54b6e9e9 ST |
5638 | return; |
5639 | } | |
5640 | if (c->cmd_type == CMD_IOACCEL2) { | |
5641 | struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *) | |
5642 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
dd0e19f3 ST |
5643 | /* upper tag not used in ioaccel2 mode */ |
5644 | memset(tagupper, 0, sizeof(*tagupper)); | |
5645 | *taglower = cm2->Tag; | |
54b6e9e9 | 5646 | return; |
17eb87d2 | 5647 | } |
2b08b3e9 DB |
5648 | tag = le64_to_cpu(c->Header.tag); |
5649 | *tagupper = cpu_to_le32(tag >> 32); | |
5650 | *taglower = cpu_to_le32(tag); | |
17eb87d2 ST |
5651 | } |
5652 | ||
75167d2c | 5653 | static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr, |
9b5c48c2 | 5654 | struct CommandList *abort, int reply_queue) |
75167d2c SC |
5655 | { |
5656 | int rc = IO_OK; | |
5657 | struct CommandList *c; | |
5658 | struct ErrorInfo *ei; | |
2b08b3e9 | 5659 | __le32 tagupper, taglower; |
75167d2c | 5660 | |
45fcb86e | 5661 | c = cmd_alloc(h); |
75167d2c | 5662 | |
a2dac136 | 5663 | /* fill_cmd can't fail here, no buffer to map */ |
9b5c48c2 | 5664 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag, |
a2dac136 | 5665 | 0, 0, scsi3addr, TYPE_MSG); |
9b5c48c2 | 5666 | if (h->needs_abort_tags_swizzled) |
6cba3f19 | 5667 | swizzle_abort_tag(&c->Request.CDB[4]); |
c448ecfa | 5668 | (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); |
17eb87d2 | 5669 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
25163bd5 | 5670 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n", |
17eb87d2 | 5671 | __func__, tagupper, taglower); |
75167d2c SC |
5672 | /* no unmap needed here because no data xfer. */ |
5673 | ||
5674 | ei = c->err_info; | |
5675 | switch (ei->CommandStatus) { | |
5676 | case CMD_SUCCESS: | |
5677 | break; | |
9437ac43 SC |
5678 | case CMD_TMF_STATUS: |
5679 | rc = hpsa_evaluate_tmf_status(h, c); | |
5680 | break; | |
75167d2c SC |
5681 | case CMD_UNABORTABLE: /* Very common, don't make noise. */ |
5682 | rc = -1; | |
5683 | break; | |
5684 | default: | |
5685 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n", | |
17eb87d2 | 5686 | __func__, tagupper, taglower); |
d1e8beac | 5687 | hpsa_scsi_interpret_error(h, c); |
75167d2c SC |
5688 | rc = -1; |
5689 | break; | |
5690 | } | |
45fcb86e | 5691 | cmd_free(h, c); |
dd0e19f3 ST |
5692 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", |
5693 | __func__, tagupper, taglower); | |
75167d2c SC |
5694 | return rc; |
5695 | } | |
5696 | ||
8be986cc SC |
5697 | static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h, |
5698 | struct CommandList *command_to_abort, int reply_queue) | |
5699 | { | |
5700 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5701 | struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; | |
5702 | struct io_accel2_cmd *c2a = | |
5703 | &h->ioaccel2_cmd_pool[command_to_abort->cmdindex]; | |
a58e7e53 | 5704 | struct scsi_cmnd *scmd = command_to_abort->scsi_cmd; |
8be986cc SC |
5705 | struct hpsa_scsi_dev_t *dev = scmd->device->hostdata; |
5706 | ||
5707 | /* | |
5708 | * We're overlaying struct hpsa_tmf_struct on top of something which | |
5709 | * was allocated as a struct io_accel2_cmd, so we better be sure it | |
5710 | * actually fits, and doesn't overrun the error info space. | |
5711 | */ | |
5712 | BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) > | |
5713 | sizeof(struct io_accel2_cmd)); | |
5714 | BUG_ON(offsetof(struct io_accel2_cmd, error_data) < | |
5715 | offsetof(struct hpsa_tmf_struct, error_len) + | |
5716 | sizeof(ac->error_len)); | |
5717 | ||
5718 | c->cmd_type = IOACCEL2_TMF; | |
a58e7e53 WS |
5719 | c->scsi_cmd = SCSI_CMD_BUSY; |
5720 | ||
8be986cc SC |
5721 | /* Adjust the DMA address to point to the accelerated command buffer */ |
5722 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
5723 | (c->cmdindex * sizeof(struct io_accel2_cmd)); | |
5724 | BUG_ON(c->busaddr & 0x0000007F); | |
5725 | ||
5726 | memset(ac, 0, sizeof(*c2)); /* yes this is correct */ | |
5727 | ac->iu_type = IOACCEL2_IU_TMF_TYPE; | |
5728 | ac->reply_queue = reply_queue; | |
5729 | ac->tmf = IOACCEL2_TMF_ABORT; | |
5730 | ac->it_nexus = cpu_to_le32(dev->ioaccel_handle); | |
5731 | memset(ac->lun_id, 0, sizeof(ac->lun_id)); | |
5732 | ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT); | |
5733 | ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag)); | |
5734 | ac->error_ptr = cpu_to_le64(c->busaddr + | |
5735 | offsetof(struct io_accel2_cmd, error_data)); | |
5736 | ac->error_len = cpu_to_le32(sizeof(c2->error_data)); | |
5737 | } | |
5738 | ||
54b6e9e9 ST |
5739 | /* ioaccel2 path firmware cannot handle abort task requests. |
5740 | * Change abort requests to physical target reset, and send to the | |
5741 | * address of the physical disk used for the ioaccel 2 command. | |
5742 | * Return 0 on success (IO_OK) | |
5743 | * -1 on failure | |
5744 | */ | |
5745 | ||
5746 | static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h, | |
25163bd5 | 5747 | unsigned char *scsi3addr, struct CommandList *abort, int reply_queue) |
54b6e9e9 ST |
5748 | { |
5749 | int rc = IO_OK; | |
5750 | struct scsi_cmnd *scmd; /* scsi command within request being aborted */ | |
5751 | struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */ | |
5752 | unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */ | |
5753 | unsigned char *psa = &phys_scsi3addr[0]; | |
5754 | ||
5755 | /* Get a pointer to the hpsa logical device. */ | |
7fa3030c | 5756 | scmd = abort->scsi_cmd; |
54b6e9e9 ST |
5757 | dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata); |
5758 | if (dev == NULL) { | |
5759 | dev_warn(&h->pdev->dev, | |
5760 | "Cannot abort: no device pointer for command.\n"); | |
5761 | return -1; /* not abortable */ | |
5762 | } | |
5763 | ||
2ba8bfc8 SC |
5764 | if (h->raid_offload_debug > 0) |
5765 | dev_info(&h->pdev->dev, | |
0d96ef5f | 5766 | "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", |
2ba8bfc8 | 5767 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, |
0d96ef5f | 5768 | "Reset as abort", |
2ba8bfc8 SC |
5769 | scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3], |
5770 | scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]); | |
5771 | ||
54b6e9e9 ST |
5772 | if (!dev->offload_enabled) { |
5773 | dev_warn(&h->pdev->dev, | |
5774 | "Can't abort: device is not operating in HP SSD Smart Path mode.\n"); | |
5775 | return -1; /* not abortable */ | |
5776 | } | |
5777 | ||
5778 | /* Incoming scsi3addr is logical addr. We need physical disk addr. */ | |
5779 | if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) { | |
5780 | dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n"); | |
5781 | return -1; /* not abortable */ | |
5782 | } | |
5783 | ||
5784 | /* send the reset */ | |
2ba8bfc8 SC |
5785 | if (h->raid_offload_debug > 0) |
5786 | dev_info(&h->pdev->dev, | |
5787 | "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5788 | psa[0], psa[1], psa[2], psa[3], | |
5789 | psa[4], psa[5], psa[6], psa[7]); | |
d604f533 | 5790 | rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue); |
54b6e9e9 ST |
5791 | if (rc != 0) { |
5792 | dev_warn(&h->pdev->dev, | |
5793 | "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5794 | psa[0], psa[1], psa[2], psa[3], | |
5795 | psa[4], psa[5], psa[6], psa[7]); | |
5796 | return rc; /* failed to reset */ | |
5797 | } | |
5798 | ||
5799 | /* wait for device to recover */ | |
b69324ff | 5800 | if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) { |
54b6e9e9 ST |
5801 | dev_warn(&h->pdev->dev, |
5802 | "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5803 | psa[0], psa[1], psa[2], psa[3], | |
5804 | psa[4], psa[5], psa[6], psa[7]); | |
5805 | return -1; /* failed to recover */ | |
5806 | } | |
5807 | ||
5808 | /* device recovered */ | |
5809 | dev_info(&h->pdev->dev, | |
5810 | "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
5811 | psa[0], psa[1], psa[2], psa[3], | |
5812 | psa[4], psa[5], psa[6], psa[7]); | |
5813 | ||
5814 | return rc; /* success */ | |
5815 | } | |
5816 | ||
8be986cc SC |
5817 | static int hpsa_send_abort_ioaccel2(struct ctlr_info *h, |
5818 | struct CommandList *abort, int reply_queue) | |
5819 | { | |
5820 | int rc = IO_OK; | |
5821 | struct CommandList *c; | |
5822 | __le32 taglower, tagupper; | |
5823 | struct hpsa_scsi_dev_t *dev; | |
5824 | struct io_accel2_cmd *c2; | |
5825 | ||
5826 | dev = abort->scsi_cmd->device->hostdata; | |
5827 | if (!dev->offload_enabled && !dev->hba_ioaccel_enabled) | |
5828 | return -1; | |
5829 | ||
5830 | c = cmd_alloc(h); | |
5831 | setup_ioaccel2_abort_cmd(c, h, abort, reply_queue); | |
5832 | c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
c448ecfa | 5833 | (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, DEFAULT_TIMEOUT); |
8be986cc SC |
5834 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
5835 | dev_dbg(&h->pdev->dev, | |
5836 | "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n", | |
5837 | __func__, tagupper, taglower); | |
5838 | /* no unmap needed here because no data xfer. */ | |
5839 | ||
5840 | dev_dbg(&h->pdev->dev, | |
5841 | "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n", | |
5842 | __func__, tagupper, taglower, c2->error_data.serv_response); | |
5843 | switch (c2->error_data.serv_response) { | |
5844 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
5845 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
5846 | rc = 0; | |
5847 | break; | |
5848 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
5849 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
5850 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
5851 | rc = -1; | |
5852 | break; | |
5853 | default: | |
5854 | dev_warn(&h->pdev->dev, | |
5855 | "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n", | |
5856 | __func__, tagupper, taglower, | |
5857 | c2->error_data.serv_response); | |
5858 | rc = -1; | |
5859 | } | |
5860 | cmd_free(h, c); | |
5861 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__, | |
5862 | tagupper, taglower); | |
5863 | return rc; | |
5864 | } | |
5865 | ||
6cba3f19 | 5866 | static int hpsa_send_abort_both_ways(struct ctlr_info *h, |
39f3deb2 | 5867 | struct hpsa_scsi_dev_t *dev, struct CommandList *abort, int reply_queue) |
6cba3f19 | 5868 | { |
8be986cc SC |
5869 | /* |
5870 | * ioccelerator mode 2 commands should be aborted via the | |
54b6e9e9 | 5871 | * accelerated path, since RAID path is unaware of these commands, |
8be986cc SC |
5872 | * but not all underlying firmware can handle abort TMF. |
5873 | * Change abort to physical device reset when abort TMF is unsupported. | |
54b6e9e9 | 5874 | */ |
8be986cc | 5875 | if (abort->cmd_type == CMD_IOACCEL2) { |
39f3deb2 DB |
5876 | if ((HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags) || |
5877 | dev->physical_device) | |
8be986cc SC |
5878 | return hpsa_send_abort_ioaccel2(h, abort, |
5879 | reply_queue); | |
5880 | else | |
39f3deb2 DB |
5881 | return hpsa_send_reset_as_abort_ioaccel2(h, |
5882 | dev->scsi3addr, | |
25163bd5 | 5883 | abort, reply_queue); |
8be986cc | 5884 | } |
39f3deb2 | 5885 | return hpsa_send_abort(h, dev->scsi3addr, abort, reply_queue); |
25163bd5 | 5886 | } |
54b6e9e9 | 5887 | |
25163bd5 WS |
5888 | /* Find out which reply queue a command was meant to return on */ |
5889 | static int hpsa_extract_reply_queue(struct ctlr_info *h, | |
5890 | struct CommandList *c) | |
5891 | { | |
5892 | if (c->cmd_type == CMD_IOACCEL2) | |
5893 | return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue; | |
5894 | return c->Header.ReplyQueue; | |
6cba3f19 SC |
5895 | } |
5896 | ||
9b5c48c2 SC |
5897 | /* |
5898 | * Limit concurrency of abort commands to prevent | |
5899 | * over-subscription of commands | |
5900 | */ | |
5901 | static inline int wait_for_available_abort_cmd(struct ctlr_info *h) | |
5902 | { | |
5903 | #define ABORT_CMD_WAIT_MSECS 5000 | |
5904 | return !wait_event_timeout(h->abort_cmd_wait_queue, | |
5905 | atomic_dec_if_positive(&h->abort_cmds_available) >= 0, | |
5906 | msecs_to_jiffies(ABORT_CMD_WAIT_MSECS)); | |
5907 | } | |
5908 | ||
75167d2c SC |
5909 | /* Send an abort for the specified command. |
5910 | * If the device and controller support it, | |
5911 | * send a task abort request. | |
5912 | */ | |
5913 | static int hpsa_eh_abort_handler(struct scsi_cmnd *sc) | |
5914 | { | |
5915 | ||
a58e7e53 | 5916 | int rc; |
75167d2c SC |
5917 | struct ctlr_info *h; |
5918 | struct hpsa_scsi_dev_t *dev; | |
5919 | struct CommandList *abort; /* pointer to command to be aborted */ | |
75167d2c SC |
5920 | struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */ |
5921 | char msg[256]; /* For debug messaging. */ | |
5922 | int ml = 0; | |
2b08b3e9 | 5923 | __le32 tagupper, taglower; |
25163bd5 WS |
5924 | int refcount, reply_queue; |
5925 | ||
5926 | if (sc == NULL) | |
5927 | return FAILED; | |
75167d2c | 5928 | |
9b5c48c2 SC |
5929 | if (sc->device == NULL) |
5930 | return FAILED; | |
5931 | ||
75167d2c SC |
5932 | /* Find the controller of the command to be aborted */ |
5933 | h = sdev_to_hba(sc->device); | |
9b5c48c2 | 5934 | if (h == NULL) |
75167d2c SC |
5935 | return FAILED; |
5936 | ||
25163bd5 WS |
5937 | /* Find the device of the command to be aborted */ |
5938 | dev = sc->device->hostdata; | |
5939 | if (!dev) { | |
5940 | dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n", | |
5941 | msg); | |
e345893b | 5942 | return FAILED; |
25163bd5 WS |
5943 | } |
5944 | ||
5945 | /* If controller locked up, we can guarantee command won't complete */ | |
5946 | if (lockup_detected(h)) { | |
5947 | hpsa_show_dev_msg(KERN_WARNING, h, dev, | |
5948 | "ABORT FAILED, lockup detected"); | |
5949 | return FAILED; | |
5950 | } | |
5951 | ||
5952 | /* This is a good time to check if controller lockup has occurred */ | |
5953 | if (detect_controller_lockup(h)) { | |
5954 | hpsa_show_dev_msg(KERN_WARNING, h, dev, | |
5955 | "ABORT FAILED, new lockup detected"); | |
5956 | return FAILED; | |
5957 | } | |
e345893b | 5958 | |
75167d2c SC |
5959 | /* Check that controller supports some kind of task abort */ |
5960 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) && | |
5961 | !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
5962 | return FAILED; | |
5963 | ||
5964 | memset(msg, 0, sizeof(msg)); | |
4b761557 | 5965 | ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p", |
75167d2c | 5966 | h->scsi_host->host_no, sc->device->channel, |
0d96ef5f | 5967 | sc->device->id, sc->device->lun, |
4b761557 | 5968 | "Aborting command", sc); |
75167d2c | 5969 | |
75167d2c SC |
5970 | /* Get SCSI command to be aborted */ |
5971 | abort = (struct CommandList *) sc->host_scribble; | |
5972 | if (abort == NULL) { | |
281a7fd0 WS |
5973 | /* This can happen if the command already completed. */ |
5974 | return SUCCESS; | |
5975 | } | |
5976 | refcount = atomic_inc_return(&abort->refcount); | |
5977 | if (refcount == 1) { /* Command is done already. */ | |
5978 | cmd_free(h, abort); | |
5979 | return SUCCESS; | |
75167d2c | 5980 | } |
9b5c48c2 SC |
5981 | |
5982 | /* Don't bother trying the abort if we know it won't work. */ | |
5983 | if (abort->cmd_type != CMD_IOACCEL2 && | |
5984 | abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) { | |
5985 | cmd_free(h, abort); | |
5986 | return FAILED; | |
5987 | } | |
5988 | ||
a58e7e53 WS |
5989 | /* |
5990 | * Check that we're aborting the right command. | |
5991 | * It's possible the CommandList already completed and got re-used. | |
5992 | */ | |
5993 | if (abort->scsi_cmd != sc) { | |
5994 | cmd_free(h, abort); | |
5995 | return SUCCESS; | |
5996 | } | |
5997 | ||
5998 | abort->abort_pending = true; | |
17eb87d2 | 5999 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
25163bd5 | 6000 | reply_queue = hpsa_extract_reply_queue(h, abort); |
17eb87d2 | 6001 | ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower); |
7fa3030c | 6002 | as = abort->scsi_cmd; |
75167d2c | 6003 | if (as != NULL) |
4b761557 RE |
6004 | ml += sprintf(msg+ml, |
6005 | "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ", | |
6006 | as->cmd_len, as->cmnd[0], as->cmnd[1], | |
6007 | as->serial_number); | |
6008 | dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg); | |
0d96ef5f | 6009 | hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command"); |
4b761557 | 6010 | |
75167d2c SC |
6011 | /* |
6012 | * Command is in flight, or possibly already completed | |
6013 | * by the firmware (but not to the scsi mid layer) but we can't | |
6014 | * distinguish which. Send the abort down. | |
6015 | */ | |
9b5c48c2 SC |
6016 | if (wait_for_available_abort_cmd(h)) { |
6017 | dev_warn(&h->pdev->dev, | |
4b761557 RE |
6018 | "%s FAILED, timeout waiting for an abort command to become available.\n", |
6019 | msg); | |
9b5c48c2 SC |
6020 | cmd_free(h, abort); |
6021 | return FAILED; | |
6022 | } | |
39f3deb2 | 6023 | rc = hpsa_send_abort_both_ways(h, dev, abort, reply_queue); |
9b5c48c2 SC |
6024 | atomic_inc(&h->abort_cmds_available); |
6025 | wake_up_all(&h->abort_cmd_wait_queue); | |
75167d2c | 6026 | if (rc != 0) { |
4b761557 | 6027 | dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg); |
0d96ef5f | 6028 | hpsa_show_dev_msg(KERN_WARNING, h, dev, |
4b761557 | 6029 | "FAILED to abort command"); |
281a7fd0 | 6030 | cmd_free(h, abort); |
75167d2c SC |
6031 | return FAILED; |
6032 | } | |
4b761557 | 6033 | dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg); |
d604f533 | 6034 | wait_event(h->event_sync_wait_queue, |
a58e7e53 | 6035 | abort->scsi_cmd != sc || lockup_detected(h)); |
281a7fd0 | 6036 | cmd_free(h, abort); |
a58e7e53 | 6037 | return !lockup_detected(h) ? SUCCESS : FAILED; |
75167d2c SC |
6038 | } |
6039 | ||
73153fe5 WS |
6040 | /* |
6041 | * For operations with an associated SCSI command, a command block is allocated | |
6042 | * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the | |
6043 | * block request tag as an index into a table of entries. cmd_tagged_free() is | |
6044 | * the complement, although cmd_free() may be called instead. | |
6045 | */ | |
6046 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
6047 | struct scsi_cmnd *scmd) | |
6048 | { | |
6049 | int idx = hpsa_get_cmd_index(scmd); | |
6050 | struct CommandList *c = h->cmd_pool + idx; | |
6051 | ||
6052 | if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { | |
6053 | dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", | |
6054 | idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); | |
6055 | /* The index value comes from the block layer, so if it's out of | |
6056 | * bounds, it's probably not our bug. | |
6057 | */ | |
6058 | BUG(); | |
6059 | } | |
6060 | ||
6061 | atomic_inc(&c->refcount); | |
6062 | if (unlikely(!hpsa_is_cmd_idle(c))) { | |
6063 | /* | |
6064 | * We expect that the SCSI layer will hand us a unique tag | |
6065 | * value. Thus, there should never be a collision here between | |
6066 | * two requests...because if the selected command isn't idle | |
6067 | * then someone is going to be very disappointed. | |
6068 | */ | |
6069 | dev_err(&h->pdev->dev, | |
6070 | "tag collision (tag=%d) in cmd_tagged_alloc().\n", | |
6071 | idx); | |
6072 | if (c->scsi_cmd != NULL) | |
6073 | scsi_print_command(c->scsi_cmd); | |
6074 | scsi_print_command(scmd); | |
6075 | } | |
6076 | ||
6077 | hpsa_cmd_partial_init(h, idx, c); | |
6078 | return c; | |
6079 | } | |
6080 | ||
6081 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) | |
6082 | { | |
6083 | /* | |
6084 | * Release our reference to the block. We don't need to do anything | |
6085 | * else to free it, because it is accessed by index. (There's no point | |
6086 | * in checking the result of the decrement, since we cannot guarantee | |
6087 | * that there isn't a concurrent abort which is also accessing it.) | |
6088 | */ | |
6089 | (void)atomic_dec(&c->refcount); | |
6090 | } | |
6091 | ||
edd16368 SC |
6092 | /* |
6093 | * For operations that cannot sleep, a command block is allocated at init, | |
6094 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
6095 | * which ones are free or in use. Lock must be held when calling this. | |
6096 | * cmd_free() is the complement. | |
bf43caf3 RE |
6097 | * This function never gives up and returns NULL. If it hangs, |
6098 | * another thread must call cmd_free() to free some tags. | |
edd16368 | 6099 | */ |
281a7fd0 | 6100 | |
edd16368 SC |
6101 | static struct CommandList *cmd_alloc(struct ctlr_info *h) |
6102 | { | |
6103 | struct CommandList *c; | |
360c73bd | 6104 | int refcount, i; |
73153fe5 | 6105 | int offset = 0; |
4c413128 | 6106 | |
33811026 RE |
6107 | /* |
6108 | * There is some *extremely* small but non-zero chance that that | |
4c413128 SC |
6109 | * multiple threads could get in here, and one thread could |
6110 | * be scanning through the list of bits looking for a free | |
6111 | * one, but the free ones are always behind him, and other | |
6112 | * threads sneak in behind him and eat them before he can | |
6113 | * get to them, so that while there is always a free one, a | |
6114 | * very unlucky thread might be starved anyway, never able to | |
6115 | * beat the other threads. In reality, this happens so | |
6116 | * infrequently as to be indistinguishable from never. | |
73153fe5 WS |
6117 | * |
6118 | * Note that we start allocating commands before the SCSI host structure | |
6119 | * is initialized. Since the search starts at bit zero, this | |
6120 | * all works, since we have at least one command structure available; | |
6121 | * however, it means that the structures with the low indexes have to be | |
6122 | * reserved for driver-initiated requests, while requests from the block | |
6123 | * layer will use the higher indexes. | |
4c413128 | 6124 | */ |
edd16368 | 6125 | |
281a7fd0 | 6126 | for (;;) { |
73153fe5 WS |
6127 | i = find_next_zero_bit(h->cmd_pool_bits, |
6128 | HPSA_NRESERVED_CMDS, | |
6129 | offset); | |
6130 | if (unlikely(i >= HPSA_NRESERVED_CMDS)) { | |
281a7fd0 WS |
6131 | offset = 0; |
6132 | continue; | |
6133 | } | |
6134 | c = h->cmd_pool + i; | |
6135 | refcount = atomic_inc_return(&c->refcount); | |
6136 | if (unlikely(refcount > 1)) { | |
6137 | cmd_free(h, c); /* already in use */ | |
73153fe5 | 6138 | offset = (i + 1) % HPSA_NRESERVED_CMDS; |
281a7fd0 WS |
6139 | continue; |
6140 | } | |
6141 | set_bit(i & (BITS_PER_LONG - 1), | |
6142 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6143 | break; /* it's ours now. */ | |
6144 | } | |
360c73bd | 6145 | hpsa_cmd_partial_init(h, i, c); |
edd16368 SC |
6146 | return c; |
6147 | } | |
6148 | ||
73153fe5 WS |
6149 | /* |
6150 | * This is the complementary operation to cmd_alloc(). Note, however, in some | |
6151 | * corner cases it may also be used to free blocks allocated by | |
6152 | * cmd_tagged_alloc() in which case the ref-count decrement does the trick and | |
6153 | * the clear-bit is harmless. | |
6154 | */ | |
edd16368 SC |
6155 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) |
6156 | { | |
281a7fd0 WS |
6157 | if (atomic_dec_and_test(&c->refcount)) { |
6158 | int i; | |
edd16368 | 6159 | |
281a7fd0 WS |
6160 | i = c - h->cmd_pool; |
6161 | clear_bit(i & (BITS_PER_LONG - 1), | |
6162 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6163 | } | |
edd16368 SC |
6164 | } |
6165 | ||
edd16368 SC |
6166 | #ifdef CONFIG_COMPAT |
6167 | ||
42a91641 DB |
6168 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, |
6169 | void __user *arg) | |
edd16368 SC |
6170 | { |
6171 | IOCTL32_Command_struct __user *arg32 = | |
6172 | (IOCTL32_Command_struct __user *) arg; | |
6173 | IOCTL_Command_struct arg64; | |
6174 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
6175 | int err; | |
6176 | u32 cp; | |
6177 | ||
938abd84 | 6178 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6179 | err = 0; |
6180 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6181 | sizeof(arg64.LUN_info)); | |
6182 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6183 | sizeof(arg64.Request)); | |
6184 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6185 | sizeof(arg64.error_info)); | |
6186 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6187 | err |= get_user(cp, &arg32->buf); | |
6188 | arg64.buf = compat_ptr(cp); | |
6189 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6190 | ||
6191 | if (err) | |
6192 | return -EFAULT; | |
6193 | ||
42a91641 | 6194 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); |
edd16368 SC |
6195 | if (err) |
6196 | return err; | |
6197 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6198 | sizeof(arg32->error_info)); | |
6199 | if (err) | |
6200 | return -EFAULT; | |
6201 | return err; | |
6202 | } | |
6203 | ||
6204 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
42a91641 | 6205 | int cmd, void __user *arg) |
edd16368 SC |
6206 | { |
6207 | BIG_IOCTL32_Command_struct __user *arg32 = | |
6208 | (BIG_IOCTL32_Command_struct __user *) arg; | |
6209 | BIG_IOCTL_Command_struct arg64; | |
6210 | BIG_IOCTL_Command_struct __user *p = | |
6211 | compat_alloc_user_space(sizeof(arg64)); | |
6212 | int err; | |
6213 | u32 cp; | |
6214 | ||
938abd84 | 6215 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6216 | err = 0; |
6217 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6218 | sizeof(arg64.LUN_info)); | |
6219 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6220 | sizeof(arg64.Request)); | |
6221 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6222 | sizeof(arg64.error_info)); | |
6223 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6224 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
6225 | err |= get_user(cp, &arg32->buf); | |
6226 | arg64.buf = compat_ptr(cp); | |
6227 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6228 | ||
6229 | if (err) | |
6230 | return -EFAULT; | |
6231 | ||
42a91641 | 6232 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); |
edd16368 SC |
6233 | if (err) |
6234 | return err; | |
6235 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6236 | sizeof(arg32->error_info)); | |
6237 | if (err) | |
6238 | return -EFAULT; | |
6239 | return err; | |
6240 | } | |
71fe75a7 | 6241 | |
42a91641 | 6242 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
71fe75a7 SC |
6243 | { |
6244 | switch (cmd) { | |
6245 | case CCISS_GETPCIINFO: | |
6246 | case CCISS_GETINTINFO: | |
6247 | case CCISS_SETINTINFO: | |
6248 | case CCISS_GETNODENAME: | |
6249 | case CCISS_SETNODENAME: | |
6250 | case CCISS_GETHEARTBEAT: | |
6251 | case CCISS_GETBUSTYPES: | |
6252 | case CCISS_GETFIRMVER: | |
6253 | case CCISS_GETDRIVVER: | |
6254 | case CCISS_REVALIDVOLS: | |
6255 | case CCISS_DEREGDISK: | |
6256 | case CCISS_REGNEWDISK: | |
6257 | case CCISS_REGNEWD: | |
6258 | case CCISS_RESCANDISK: | |
6259 | case CCISS_GETLUNINFO: | |
6260 | return hpsa_ioctl(dev, cmd, arg); | |
6261 | ||
6262 | case CCISS_PASSTHRU32: | |
6263 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
6264 | case CCISS_BIG_PASSTHRU32: | |
6265 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
6266 | ||
6267 | default: | |
6268 | return -ENOIOCTLCMD; | |
6269 | } | |
6270 | } | |
edd16368 SC |
6271 | #endif |
6272 | ||
6273 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
6274 | { | |
6275 | struct hpsa_pci_info pciinfo; | |
6276 | ||
6277 | if (!argp) | |
6278 | return -EINVAL; | |
6279 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
6280 | pciinfo.bus = h->pdev->bus->number; | |
6281 | pciinfo.dev_fn = h->pdev->devfn; | |
6282 | pciinfo.board_id = h->board_id; | |
6283 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
6284 | return -EFAULT; | |
6285 | return 0; | |
6286 | } | |
6287 | ||
6288 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
6289 | { | |
6290 | DriverVer_type DriverVer; | |
6291 | unsigned char vmaj, vmin, vsubmin; | |
6292 | int rc; | |
6293 | ||
6294 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
6295 | &vmaj, &vmin, &vsubmin); | |
6296 | if (rc != 3) { | |
6297 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
6298 | "unrecognized.", HPSA_DRIVER_VERSION); | |
6299 | vmaj = 0; | |
6300 | vmin = 0; | |
6301 | vsubmin = 0; | |
6302 | } | |
6303 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
6304 | if (!argp) | |
6305 | return -EINVAL; | |
6306 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
6307 | return -EFAULT; | |
6308 | return 0; | |
6309 | } | |
6310 | ||
6311 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6312 | { | |
6313 | IOCTL_Command_struct iocommand; | |
6314 | struct CommandList *c; | |
6315 | char *buff = NULL; | |
50a0decf | 6316 | u64 temp64; |
c1f63c8f | 6317 | int rc = 0; |
edd16368 SC |
6318 | |
6319 | if (!argp) | |
6320 | return -EINVAL; | |
6321 | if (!capable(CAP_SYS_RAWIO)) | |
6322 | return -EPERM; | |
6323 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
6324 | return -EFAULT; | |
6325 | if ((iocommand.buf_size < 1) && | |
6326 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
6327 | return -EINVAL; | |
6328 | } | |
6329 | if (iocommand.buf_size > 0) { | |
6330 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
6331 | if (buff == NULL) | |
2dd02d74 | 6332 | return -ENOMEM; |
9233fb10 | 6333 | if (iocommand.Request.Type.Direction & XFER_WRITE) { |
b03a7771 SC |
6334 | /* Copy the data into the buffer we created */ |
6335 | if (copy_from_user(buff, iocommand.buf, | |
6336 | iocommand.buf_size)) { | |
c1f63c8f SC |
6337 | rc = -EFAULT; |
6338 | goto out_kfree; | |
b03a7771 SC |
6339 | } |
6340 | } else { | |
6341 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 6342 | } |
b03a7771 | 6343 | } |
45fcb86e | 6344 | c = cmd_alloc(h); |
bf43caf3 | 6345 | |
edd16368 SC |
6346 | /* Fill in the command type */ |
6347 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6348 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6349 | /* Fill in Command Header */ |
6350 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
6351 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
6352 | c->Header.SGList = 1; | |
50a0decf | 6353 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6354 | } else { /* no buffers to fill */ |
6355 | c->Header.SGList = 0; | |
50a0decf | 6356 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 SC |
6357 | } |
6358 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
edd16368 SC |
6359 | |
6360 | /* Fill in Request block */ | |
6361 | memcpy(&c->Request, &iocommand.Request, | |
6362 | sizeof(c->Request)); | |
6363 | ||
6364 | /* Fill in the scatter gather information */ | |
6365 | if (iocommand.buf_size > 0) { | |
50a0decf | 6366 | temp64 = pci_map_single(h->pdev, buff, |
edd16368 | 6367 | iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
6368 | if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { |
6369 | c->SG[0].Addr = cpu_to_le64(0); | |
6370 | c->SG[0].Len = cpu_to_le32(0); | |
bcc48ffa SC |
6371 | rc = -ENOMEM; |
6372 | goto out; | |
6373 | } | |
50a0decf SC |
6374 | c->SG[0].Addr = cpu_to_le64(temp64); |
6375 | c->SG[0].Len = cpu_to_le32(iocommand.buf_size); | |
6376 | c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ | |
edd16368 | 6377 | } |
c448ecfa DB |
6378 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
6379 | DEFAULT_TIMEOUT); | |
c2dd32e0 SC |
6380 | if (iocommand.buf_size > 0) |
6381 | hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); | |
edd16368 | 6382 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6383 | if (rc) { |
6384 | rc = -EIO; | |
6385 | goto out; | |
6386 | } | |
edd16368 SC |
6387 | |
6388 | /* Copy the error information out */ | |
6389 | memcpy(&iocommand.error_info, c->err_info, | |
6390 | sizeof(iocommand.error_info)); | |
6391 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
6392 | rc = -EFAULT; |
6393 | goto out; | |
edd16368 | 6394 | } |
9233fb10 | 6395 | if ((iocommand.Request.Type.Direction & XFER_READ) && |
b03a7771 | 6396 | iocommand.buf_size > 0) { |
edd16368 SC |
6397 | /* Copy the data out of the buffer we created */ |
6398 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
6399 | rc = -EFAULT; |
6400 | goto out; | |
edd16368 SC |
6401 | } |
6402 | } | |
c1f63c8f | 6403 | out: |
45fcb86e | 6404 | cmd_free(h, c); |
c1f63c8f SC |
6405 | out_kfree: |
6406 | kfree(buff); | |
6407 | return rc; | |
edd16368 SC |
6408 | } |
6409 | ||
6410 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6411 | { | |
6412 | BIG_IOCTL_Command_struct *ioc; | |
6413 | struct CommandList *c; | |
6414 | unsigned char **buff = NULL; | |
6415 | int *buff_size = NULL; | |
50a0decf | 6416 | u64 temp64; |
edd16368 SC |
6417 | BYTE sg_used = 0; |
6418 | int status = 0; | |
01a02ffc SC |
6419 | u32 left; |
6420 | u32 sz; | |
edd16368 SC |
6421 | BYTE __user *data_ptr; |
6422 | ||
6423 | if (!argp) | |
6424 | return -EINVAL; | |
6425 | if (!capable(CAP_SYS_RAWIO)) | |
6426 | return -EPERM; | |
6427 | ioc = (BIG_IOCTL_Command_struct *) | |
6428 | kmalloc(sizeof(*ioc), GFP_KERNEL); | |
6429 | if (!ioc) { | |
6430 | status = -ENOMEM; | |
6431 | goto cleanup1; | |
6432 | } | |
6433 | if (copy_from_user(ioc, argp, sizeof(*ioc))) { | |
6434 | status = -EFAULT; | |
6435 | goto cleanup1; | |
6436 | } | |
6437 | if ((ioc->buf_size < 1) && | |
6438 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
6439 | status = -EINVAL; | |
6440 | goto cleanup1; | |
6441 | } | |
6442 | /* Check kmalloc limits using all SGs */ | |
6443 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
6444 | status = -EINVAL; | |
6445 | goto cleanup1; | |
6446 | } | |
d66ae08b | 6447 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
6448 | status = -EINVAL; |
6449 | goto cleanup1; | |
6450 | } | |
d66ae08b | 6451 | buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); |
edd16368 SC |
6452 | if (!buff) { |
6453 | status = -ENOMEM; | |
6454 | goto cleanup1; | |
6455 | } | |
d66ae08b | 6456 | buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); |
edd16368 SC |
6457 | if (!buff_size) { |
6458 | status = -ENOMEM; | |
6459 | goto cleanup1; | |
6460 | } | |
6461 | left = ioc->buf_size; | |
6462 | data_ptr = ioc->buf; | |
6463 | while (left) { | |
6464 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
6465 | buff_size[sg_used] = sz; | |
6466 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
6467 | if (buff[sg_used] == NULL) { | |
6468 | status = -ENOMEM; | |
6469 | goto cleanup1; | |
6470 | } | |
9233fb10 | 6471 | if (ioc->Request.Type.Direction & XFER_WRITE) { |
edd16368 | 6472 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { |
0758f4f7 | 6473 | status = -EFAULT; |
edd16368 SC |
6474 | goto cleanup1; |
6475 | } | |
6476 | } else | |
6477 | memset(buff[sg_used], 0, sz); | |
6478 | left -= sz; | |
6479 | data_ptr += sz; | |
6480 | sg_used++; | |
6481 | } | |
45fcb86e | 6482 | c = cmd_alloc(h); |
bf43caf3 | 6483 | |
edd16368 | 6484 | c->cmd_type = CMD_IOCTL_PEND; |
a58e7e53 | 6485 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 | 6486 | c->Header.ReplyQueue = 0; |
50a0decf SC |
6487 | c->Header.SGList = (u8) sg_used; |
6488 | c->Header.SGTotal = cpu_to_le16(sg_used); | |
edd16368 | 6489 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
edd16368 SC |
6490 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); |
6491 | if (ioc->buf_size > 0) { | |
6492 | int i; | |
6493 | for (i = 0; i < sg_used; i++) { | |
50a0decf | 6494 | temp64 = pci_map_single(h->pdev, buff[i], |
edd16368 | 6495 | buff_size[i], PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
6496 | if (dma_mapping_error(&h->pdev->dev, |
6497 | (dma_addr_t) temp64)) { | |
6498 | c->SG[i].Addr = cpu_to_le64(0); | |
6499 | c->SG[i].Len = cpu_to_le32(0); | |
bcc48ffa SC |
6500 | hpsa_pci_unmap(h->pdev, c, i, |
6501 | PCI_DMA_BIDIRECTIONAL); | |
6502 | status = -ENOMEM; | |
e2d4a1f6 | 6503 | goto cleanup0; |
bcc48ffa | 6504 | } |
50a0decf SC |
6505 | c->SG[i].Addr = cpu_to_le64(temp64); |
6506 | c->SG[i].Len = cpu_to_le32(buff_size[i]); | |
6507 | c->SG[i].Ext = cpu_to_le32(0); | |
edd16368 | 6508 | } |
50a0decf | 6509 | c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); |
edd16368 | 6510 | } |
c448ecfa DB |
6511 | status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
6512 | DEFAULT_TIMEOUT); | |
b03a7771 SC |
6513 | if (sg_used) |
6514 | hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); | |
edd16368 | 6515 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6516 | if (status) { |
6517 | status = -EIO; | |
6518 | goto cleanup0; | |
6519 | } | |
6520 | ||
edd16368 SC |
6521 | /* Copy the error information out */ |
6522 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
6523 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 6524 | status = -EFAULT; |
e2d4a1f6 | 6525 | goto cleanup0; |
edd16368 | 6526 | } |
9233fb10 | 6527 | if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { |
2b08b3e9 DB |
6528 | int i; |
6529 | ||
edd16368 SC |
6530 | /* Copy the data out of the buffer we created */ |
6531 | BYTE __user *ptr = ioc->buf; | |
6532 | for (i = 0; i < sg_used; i++) { | |
6533 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 6534 | status = -EFAULT; |
e2d4a1f6 | 6535 | goto cleanup0; |
edd16368 SC |
6536 | } |
6537 | ptr += buff_size[i]; | |
6538 | } | |
6539 | } | |
edd16368 | 6540 | status = 0; |
e2d4a1f6 | 6541 | cleanup0: |
45fcb86e | 6542 | cmd_free(h, c); |
edd16368 SC |
6543 | cleanup1: |
6544 | if (buff) { | |
2b08b3e9 DB |
6545 | int i; |
6546 | ||
edd16368 SC |
6547 | for (i = 0; i < sg_used; i++) |
6548 | kfree(buff[i]); | |
6549 | kfree(buff); | |
6550 | } | |
6551 | kfree(buff_size); | |
6552 | kfree(ioc); | |
6553 | return status; | |
6554 | } | |
6555 | ||
6556 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
6557 | struct CommandList *c) | |
6558 | { | |
6559 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
6560 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
6561 | (void) check_for_unit_attention(h, c); | |
6562 | } | |
0390f0c0 | 6563 | |
edd16368 SC |
6564 | /* |
6565 | * ioctl | |
6566 | */ | |
42a91641 | 6567 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
edd16368 SC |
6568 | { |
6569 | struct ctlr_info *h; | |
6570 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 6571 | int rc; |
edd16368 SC |
6572 | |
6573 | h = sdev_to_hba(dev); | |
6574 | ||
6575 | switch (cmd) { | |
6576 | case CCISS_DEREGDISK: | |
6577 | case CCISS_REGNEWDISK: | |
6578 | case CCISS_REGNEWD: | |
a08a8471 | 6579 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
6580 | return 0; |
6581 | case CCISS_GETPCIINFO: | |
6582 | return hpsa_getpciinfo_ioctl(h, argp); | |
6583 | case CCISS_GETDRIVVER: | |
6584 | return hpsa_getdrivver_ioctl(h, argp); | |
6585 | case CCISS_PASSTHRU: | |
34f0c627 | 6586 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6587 | return -EAGAIN; |
6588 | rc = hpsa_passthru_ioctl(h, argp); | |
34f0c627 | 6589 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6590 | return rc; |
edd16368 | 6591 | case CCISS_BIG_PASSTHRU: |
34f0c627 | 6592 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6593 | return -EAGAIN; |
6594 | rc = hpsa_big_passthru_ioctl(h, argp); | |
34f0c627 | 6595 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6596 | return rc; |
edd16368 SC |
6597 | default: |
6598 | return -ENOTTY; | |
6599 | } | |
6600 | } | |
6601 | ||
bf43caf3 | 6602 | static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
6f039790 | 6603 | u8 reset_type) |
64670ac8 SC |
6604 | { |
6605 | struct CommandList *c; | |
6606 | ||
6607 | c = cmd_alloc(h); | |
bf43caf3 | 6608 | |
a2dac136 SC |
6609 | /* fill_cmd can't fail here, no data buffer to map */ |
6610 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
6611 | RAID_CTLR_LUNID, TYPE_MSG); |
6612 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
6613 | c->waiting = NULL; | |
6614 | enqueue_cmd_and_start_io(h, c); | |
6615 | /* Don't wait for completion, the reset won't complete. Don't free | |
6616 | * the command either. This is the last command we will send before | |
6617 | * re-initializing everything, so it doesn't matter and won't leak. | |
6618 | */ | |
bf43caf3 | 6619 | return; |
64670ac8 SC |
6620 | } |
6621 | ||
a2dac136 | 6622 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 6623 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 SC |
6624 | int cmd_type) |
6625 | { | |
6626 | int pci_dir = XFER_NONE; | |
9b5c48c2 | 6627 | u64 tag; /* for commands to be aborted */ |
edd16368 SC |
6628 | |
6629 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6630 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6631 | c->Header.ReplyQueue = 0; |
6632 | if (buff != NULL && size > 0) { | |
6633 | c->Header.SGList = 1; | |
50a0decf | 6634 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6635 | } else { |
6636 | c->Header.SGList = 0; | |
50a0decf | 6637 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 | 6638 | } |
edd16368 SC |
6639 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); |
6640 | ||
edd16368 SC |
6641 | if (cmd_type == TYPE_CMD) { |
6642 | switch (cmd) { | |
6643 | case HPSA_INQUIRY: | |
6644 | /* are we trying to read a vital product page */ | |
b7bb24eb | 6645 | if (page_code & VPD_PAGE) { |
edd16368 | 6646 | c->Request.CDB[1] = 0x01; |
b7bb24eb | 6647 | c->Request.CDB[2] = (page_code & 0xff); |
edd16368 SC |
6648 | } |
6649 | c->Request.CDBLen = 6; | |
a505b86f SC |
6650 | c->Request.type_attr_dir = |
6651 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6652 | c->Request.Timeout = 0; |
6653 | c->Request.CDB[0] = HPSA_INQUIRY; | |
6654 | c->Request.CDB[4] = size & 0xFF; | |
6655 | break; | |
6656 | case HPSA_REPORT_LOG: | |
6657 | case HPSA_REPORT_PHYS: | |
6658 | /* Talking to controller so It's a physical command | |
6659 | mode = 00 target = 0. Nothing to write. | |
6660 | */ | |
6661 | c->Request.CDBLen = 12; | |
a505b86f SC |
6662 | c->Request.type_attr_dir = |
6663 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6664 | c->Request.Timeout = 0; |
6665 | c->Request.CDB[0] = cmd; | |
6666 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6667 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6668 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6669 | c->Request.CDB[9] = size & 0xFF; | |
6670 | break; | |
c2adae44 ST |
6671 | case BMIC_SENSE_DIAG_OPTIONS: |
6672 | c->Request.CDBLen = 16; | |
6673 | c->Request.type_attr_dir = | |
6674 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6675 | c->Request.Timeout = 0; | |
6676 | /* Spec says this should be BMIC_WRITE */ | |
6677 | c->Request.CDB[0] = BMIC_READ; | |
6678 | c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; | |
6679 | break; | |
6680 | case BMIC_SET_DIAG_OPTIONS: | |
6681 | c->Request.CDBLen = 16; | |
6682 | c->Request.type_attr_dir = | |
6683 | TYPE_ATTR_DIR(cmd_type, | |
6684 | ATTR_SIMPLE, XFER_WRITE); | |
6685 | c->Request.Timeout = 0; | |
6686 | c->Request.CDB[0] = BMIC_WRITE; | |
6687 | c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; | |
6688 | break; | |
edd16368 SC |
6689 | case HPSA_CACHE_FLUSH: |
6690 | c->Request.CDBLen = 12; | |
a505b86f SC |
6691 | c->Request.type_attr_dir = |
6692 | TYPE_ATTR_DIR(cmd_type, | |
6693 | ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
6694 | c->Request.Timeout = 0; |
6695 | c->Request.CDB[0] = BMIC_WRITE; | |
6696 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
6697 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
6698 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
6699 | break; |
6700 | case TEST_UNIT_READY: | |
6701 | c->Request.CDBLen = 6; | |
a505b86f SC |
6702 | c->Request.type_attr_dir = |
6703 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
6704 | c->Request.Timeout = 0; |
6705 | break; | |
283b4a9b SC |
6706 | case HPSA_GET_RAID_MAP: |
6707 | c->Request.CDBLen = 12; | |
a505b86f SC |
6708 | c->Request.type_attr_dir = |
6709 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
283b4a9b SC |
6710 | c->Request.Timeout = 0; |
6711 | c->Request.CDB[0] = HPSA_CISS_READ; | |
6712 | c->Request.CDB[1] = cmd; | |
6713 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6714 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6715 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6716 | c->Request.CDB[9] = size & 0xFF; | |
6717 | break; | |
316b221a SC |
6718 | case BMIC_SENSE_CONTROLLER_PARAMETERS: |
6719 | c->Request.CDBLen = 10; | |
a505b86f SC |
6720 | c->Request.type_attr_dir = |
6721 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
316b221a SC |
6722 | c->Request.Timeout = 0; |
6723 | c->Request.CDB[0] = BMIC_READ; | |
6724 | c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; | |
6725 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6726 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6727 | break; | |
03383736 DB |
6728 | case BMIC_IDENTIFY_PHYSICAL_DEVICE: |
6729 | c->Request.CDBLen = 10; | |
6730 | c->Request.type_attr_dir = | |
6731 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6732 | c->Request.Timeout = 0; | |
6733 | c->Request.CDB[0] = BMIC_READ; | |
6734 | c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; | |
6735 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6736 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6737 | break; | |
d04e62b9 KB |
6738 | case BMIC_SENSE_SUBSYSTEM_INFORMATION: |
6739 | c->Request.CDBLen = 10; | |
6740 | c->Request.type_attr_dir = | |
6741 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6742 | c->Request.Timeout = 0; | |
6743 | c->Request.CDB[0] = BMIC_READ; | |
6744 | c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; | |
6745 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6746 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6747 | break; | |
cca8f13b DB |
6748 | case BMIC_SENSE_STORAGE_BOX_PARAMS: |
6749 | c->Request.CDBLen = 10; | |
6750 | c->Request.type_attr_dir = | |
6751 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6752 | c->Request.Timeout = 0; | |
6753 | c->Request.CDB[0] = BMIC_READ; | |
6754 | c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS; | |
6755 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6756 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6757 | break; | |
66749d0d ST |
6758 | case BMIC_IDENTIFY_CONTROLLER: |
6759 | c->Request.CDBLen = 10; | |
6760 | c->Request.type_attr_dir = | |
6761 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6762 | c->Request.Timeout = 0; | |
6763 | c->Request.CDB[0] = BMIC_READ; | |
6764 | c->Request.CDB[1] = 0; | |
6765 | c->Request.CDB[2] = 0; | |
6766 | c->Request.CDB[3] = 0; | |
6767 | c->Request.CDB[4] = 0; | |
6768 | c->Request.CDB[5] = 0; | |
6769 | c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; | |
6770 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6771 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6772 | c->Request.CDB[9] = 0; | |
6773 | break; | |
edd16368 SC |
6774 | default: |
6775 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
6776 | BUG(); | |
a2dac136 | 6777 | return -1; |
edd16368 SC |
6778 | } |
6779 | } else if (cmd_type == TYPE_MSG) { | |
6780 | switch (cmd) { | |
6781 | ||
0b9b7b6e ST |
6782 | case HPSA_PHYS_TARGET_RESET: |
6783 | c->Request.CDBLen = 16; | |
6784 | c->Request.type_attr_dir = | |
6785 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
6786 | c->Request.Timeout = 0; /* Don't time out */ | |
6787 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); | |
6788 | c->Request.CDB[0] = HPSA_RESET; | |
6789 | c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; | |
6790 | /* Physical target reset needs no control bytes 4-7*/ | |
6791 | c->Request.CDB[4] = 0x00; | |
6792 | c->Request.CDB[5] = 0x00; | |
6793 | c->Request.CDB[6] = 0x00; | |
6794 | c->Request.CDB[7] = 0x00; | |
6795 | break; | |
edd16368 SC |
6796 | case HPSA_DEVICE_RESET_MSG: |
6797 | c->Request.CDBLen = 16; | |
a505b86f SC |
6798 | c->Request.type_attr_dir = |
6799 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 | 6800 | c->Request.Timeout = 0; /* Don't time out */ |
64670ac8 SC |
6801 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
6802 | c->Request.CDB[0] = cmd; | |
21e89afd | 6803 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
6804 | /* If bytes 4-7 are zero, it means reset the */ |
6805 | /* LunID device */ | |
6806 | c->Request.CDB[4] = 0x00; | |
6807 | c->Request.CDB[5] = 0x00; | |
6808 | c->Request.CDB[6] = 0x00; | |
6809 | c->Request.CDB[7] = 0x00; | |
75167d2c SC |
6810 | break; |
6811 | case HPSA_ABORT_MSG: | |
9b5c48c2 | 6812 | memcpy(&tag, buff, sizeof(tag)); |
2b08b3e9 | 6813 | dev_dbg(&h->pdev->dev, |
9b5c48c2 SC |
6814 | "Abort Tag:0x%016llx using rqst Tag:0x%016llx", |
6815 | tag, c->Header.tag); | |
75167d2c | 6816 | c->Request.CDBLen = 16; |
a505b86f SC |
6817 | c->Request.type_attr_dir = |
6818 | TYPE_ATTR_DIR(cmd_type, | |
6819 | ATTR_SIMPLE, XFER_WRITE); | |
75167d2c SC |
6820 | c->Request.Timeout = 0; /* Don't time out */ |
6821 | c->Request.CDB[0] = HPSA_TASK_MANAGEMENT; | |
6822 | c->Request.CDB[1] = HPSA_TMF_ABORT_TASK; | |
6823 | c->Request.CDB[2] = 0x00; /* reserved */ | |
6824 | c->Request.CDB[3] = 0x00; /* reserved */ | |
6825 | /* Tag to abort goes in CDB[4]-CDB[11] */ | |
9b5c48c2 | 6826 | memcpy(&c->Request.CDB[4], &tag, sizeof(tag)); |
75167d2c SC |
6827 | c->Request.CDB[12] = 0x00; /* reserved */ |
6828 | c->Request.CDB[13] = 0x00; /* reserved */ | |
6829 | c->Request.CDB[14] = 0x00; /* reserved */ | |
6830 | c->Request.CDB[15] = 0x00; /* reserved */ | |
edd16368 | 6831 | break; |
edd16368 SC |
6832 | default: |
6833 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
6834 | cmd); | |
6835 | BUG(); | |
6836 | } | |
6837 | } else { | |
6838 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
6839 | BUG(); | |
6840 | } | |
6841 | ||
a505b86f | 6842 | switch (GET_DIR(c->Request.type_attr_dir)) { |
edd16368 SC |
6843 | case XFER_READ: |
6844 | pci_dir = PCI_DMA_FROMDEVICE; | |
6845 | break; | |
6846 | case XFER_WRITE: | |
6847 | pci_dir = PCI_DMA_TODEVICE; | |
6848 | break; | |
6849 | case XFER_NONE: | |
6850 | pci_dir = PCI_DMA_NONE; | |
6851 | break; | |
6852 | default: | |
6853 | pci_dir = PCI_DMA_BIDIRECTIONAL; | |
6854 | } | |
a2dac136 SC |
6855 | if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) |
6856 | return -1; | |
6857 | return 0; | |
edd16368 SC |
6858 | } |
6859 | ||
6860 | /* | |
6861 | * Map (physical) PCI mem into (virtual) kernel space | |
6862 | */ | |
6863 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
6864 | { | |
6865 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
6866 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
6867 | void __iomem *page_remapped = ioremap_nocache(page_base, |
6868 | page_offs + size); | |
edd16368 SC |
6869 | |
6870 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
6871 | } | |
6872 | ||
254f796b | 6873 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 6874 | { |
254f796b | 6875 | return h->access.command_completed(h, q); |
edd16368 SC |
6876 | } |
6877 | ||
900c5440 | 6878 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
6879 | { |
6880 | return h->access.intr_pending(h); | |
6881 | } | |
6882 | ||
6883 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
6884 | { | |
10f66018 SC |
6885 | return (h->access.intr_pending(h) == 0) || |
6886 | (h->interrupts_enabled == 0); | |
edd16368 SC |
6887 | } |
6888 | ||
01a02ffc SC |
6889 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
6890 | u32 raw_tag) | |
edd16368 SC |
6891 | { |
6892 | if (unlikely(tag_index >= h->nr_cmds)) { | |
6893 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
6894 | return 1; | |
6895 | } | |
6896 | return 0; | |
6897 | } | |
6898 | ||
5a3d16f5 | 6899 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 6900 | { |
e85c5974 | 6901 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
c349775e ST |
6902 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI |
6903 | || c->cmd_type == CMD_IOACCEL2)) | |
1fb011fb | 6904 | complete_scsi_command(c); |
8be986cc | 6905 | else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) |
edd16368 | 6906 | complete(c->waiting); |
a104c99f SC |
6907 | } |
6908 | ||
303932fd | 6909 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 6910 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
6911 | u32 raw_tag) |
6912 | { | |
6913 | u32 tag_index; | |
6914 | struct CommandList *c; | |
6915 | ||
f2405db8 | 6916 | tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; |
1d94f94d SC |
6917 | if (!bad_tag(h, tag_index, raw_tag)) { |
6918 | c = h->cmd_pool + tag_index; | |
6919 | finish_cmd(c); | |
6920 | } | |
303932fd DB |
6921 | } |
6922 | ||
64670ac8 SC |
6923 | /* Some controllers, like p400, will give us one interrupt |
6924 | * after a soft reset, even if we turned interrupts off. | |
6925 | * Only need to check for this in the hpsa_xxx_discard_completions | |
6926 | * functions. | |
6927 | */ | |
6928 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
6929 | { | |
6930 | if (likely(!reset_devices)) | |
6931 | return 0; | |
6932 | ||
6933 | if (likely(h->interrupts_enabled)) | |
6934 | return 0; | |
6935 | ||
6936 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
6937 | "(known firmware bug.) Ignoring.\n"); | |
6938 | ||
6939 | return 1; | |
6940 | } | |
6941 | ||
254f796b MG |
6942 | /* |
6943 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
6944 | * Relies on (h-q[x] == x) being true for x such that | |
6945 | * 0 <= x < MAX_REPLY_QUEUES. | |
6946 | */ | |
6947 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 6948 | { |
254f796b MG |
6949 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
6950 | } | |
6951 | ||
6952 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
6953 | { | |
6954 | struct ctlr_info *h = queue_to_hba(queue); | |
6955 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
6956 | u32 raw_tag; |
6957 | ||
6958 | if (ignore_bogus_interrupt(h)) | |
6959 | return IRQ_NONE; | |
6960 | ||
6961 | if (interrupt_not_for_us(h)) | |
6962 | return IRQ_NONE; | |
a0c12413 | 6963 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 6964 | while (interrupt_pending(h)) { |
254f796b | 6965 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6966 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6967 | raw_tag = next_command(h, q); |
64670ac8 | 6968 | } |
64670ac8 SC |
6969 | return IRQ_HANDLED; |
6970 | } | |
6971 | ||
254f796b | 6972 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 6973 | { |
254f796b | 6974 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 6975 | u32 raw_tag; |
254f796b | 6976 | u8 q = *(u8 *) queue; |
64670ac8 SC |
6977 | |
6978 | if (ignore_bogus_interrupt(h)) | |
6979 | return IRQ_NONE; | |
6980 | ||
a0c12413 | 6981 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 6982 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6983 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6984 | raw_tag = next_command(h, q); |
64670ac8 SC |
6985 | return IRQ_HANDLED; |
6986 | } | |
6987 | ||
254f796b | 6988 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 6989 | { |
254f796b | 6990 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 6991 | u32 raw_tag; |
254f796b | 6992 | u8 q = *(u8 *) queue; |
edd16368 SC |
6993 | |
6994 | if (interrupt_not_for_us(h)) | |
6995 | return IRQ_NONE; | |
a0c12413 | 6996 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 6997 | while (interrupt_pending(h)) { |
254f796b | 6998 | raw_tag = get_next_completion(h, q); |
10f66018 | 6999 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 7000 | process_indexed_cmd(h, raw_tag); |
254f796b | 7001 | raw_tag = next_command(h, q); |
10f66018 SC |
7002 | } |
7003 | } | |
10f66018 SC |
7004 | return IRQ_HANDLED; |
7005 | } | |
7006 | ||
254f796b | 7007 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 7008 | { |
254f796b | 7009 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 7010 | u32 raw_tag; |
254f796b | 7011 | u8 q = *(u8 *) queue; |
10f66018 | 7012 | |
a0c12413 | 7013 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 7014 | raw_tag = get_next_completion(h, q); |
303932fd | 7015 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 7016 | process_indexed_cmd(h, raw_tag); |
254f796b | 7017 | raw_tag = next_command(h, q); |
edd16368 | 7018 | } |
edd16368 SC |
7019 | return IRQ_HANDLED; |
7020 | } | |
7021 | ||
a9a3a273 SC |
7022 | /* Send a message CDB to the firmware. Careful, this only works |
7023 | * in simple mode, not performant mode due to the tag lookup. | |
7024 | * We only ever use this immediately after a controller reset. | |
7025 | */ | |
6f039790 GKH |
7026 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
7027 | unsigned char type) | |
edd16368 SC |
7028 | { |
7029 | struct Command { | |
7030 | struct CommandListHeader CommandHeader; | |
7031 | struct RequestBlock Request; | |
7032 | struct ErrDescriptor ErrorDescriptor; | |
7033 | }; | |
7034 | struct Command *cmd; | |
7035 | static const size_t cmd_sz = sizeof(*cmd) + | |
7036 | sizeof(cmd->ErrorDescriptor); | |
7037 | dma_addr_t paddr64; | |
2b08b3e9 DB |
7038 | __le32 paddr32; |
7039 | u32 tag; | |
edd16368 SC |
7040 | void __iomem *vaddr; |
7041 | int i, err; | |
7042 | ||
7043 | vaddr = pci_ioremap_bar(pdev, 0); | |
7044 | if (vaddr == NULL) | |
7045 | return -ENOMEM; | |
7046 | ||
7047 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
7048 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
7049 | * memory. | |
7050 | */ | |
7051 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
7052 | if (err) { | |
7053 | iounmap(vaddr); | |
1eaec8f3 | 7054 | return err; |
edd16368 SC |
7055 | } |
7056 | ||
7057 | cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); | |
7058 | if (cmd == NULL) { | |
7059 | iounmap(vaddr); | |
7060 | return -ENOMEM; | |
7061 | } | |
7062 | ||
7063 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
7064 | * although there's no guarantee, we assume that the address is at | |
7065 | * least 4-byte aligned (most likely, it's page-aligned). | |
7066 | */ | |
2b08b3e9 | 7067 | paddr32 = cpu_to_le32(paddr64); |
edd16368 SC |
7068 | |
7069 | cmd->CommandHeader.ReplyQueue = 0; | |
7070 | cmd->CommandHeader.SGList = 0; | |
50a0decf | 7071 | cmd->CommandHeader.SGTotal = cpu_to_le16(0); |
2b08b3e9 | 7072 | cmd->CommandHeader.tag = cpu_to_le64(paddr64); |
edd16368 SC |
7073 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); |
7074 | ||
7075 | cmd->Request.CDBLen = 16; | |
a505b86f SC |
7076 | cmd->Request.type_attr_dir = |
7077 | TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); | |
edd16368 SC |
7078 | cmd->Request.Timeout = 0; /* Don't time out */ |
7079 | cmd->Request.CDB[0] = opcode; | |
7080 | cmd->Request.CDB[1] = type; | |
7081 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
50a0decf | 7082 | cmd->ErrorDescriptor.Addr = |
2b08b3e9 | 7083 | cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); |
50a0decf | 7084 | cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); |
edd16368 | 7085 | |
2b08b3e9 | 7086 | writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); |
edd16368 SC |
7087 | |
7088 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
7089 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
2b08b3e9 | 7090 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) |
edd16368 SC |
7091 | break; |
7092 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
7093 | } | |
7094 | ||
7095 | iounmap(vaddr); | |
7096 | ||
7097 | /* we leak the DMA buffer here ... no choice since the controller could | |
7098 | * still complete the command. | |
7099 | */ | |
7100 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
7101 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
7102 | opcode, type); | |
7103 | return -ETIMEDOUT; | |
7104 | } | |
7105 | ||
7106 | pci_free_consistent(pdev, cmd_sz, cmd, paddr64); | |
7107 | ||
7108 | if (tag & HPSA_ERROR_BIT) { | |
7109 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
7110 | opcode, type); | |
7111 | return -EIO; | |
7112 | } | |
7113 | ||
7114 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
7115 | opcode, type); | |
7116 | return 0; | |
7117 | } | |
7118 | ||
edd16368 SC |
7119 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
7120 | ||
1df8552a | 7121 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
42a91641 | 7122 | void __iomem *vaddr, u32 use_doorbell) |
1df8552a | 7123 | { |
1df8552a SC |
7124 | |
7125 | if (use_doorbell) { | |
7126 | /* For everything after the P600, the PCI power state method | |
7127 | * of resetting the controller doesn't work, so we have this | |
7128 | * other way using the doorbell register. | |
7129 | */ | |
7130 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 7131 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 | 7132 | |
00701a96 | 7133 | /* PMC hardware guys tell us we need a 10 second delay after |
85009239 SC |
7134 | * doorbell reset and before any attempt to talk to the board |
7135 | * at all to ensure that this actually works and doesn't fall | |
7136 | * over in some weird corner cases. | |
7137 | */ | |
00701a96 | 7138 | msleep(10000); |
1df8552a SC |
7139 | } else { /* Try to do it the PCI power state way */ |
7140 | ||
7141 | /* Quoting from the Open CISS Specification: "The Power | |
7142 | * Management Control/Status Register (CSR) controls the power | |
7143 | * state of the device. The normal operating state is D0, | |
7144 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
7145 | * the controller, place the interface device in D3 then to D0, | |
7146 | * this causes a secondary PCI reset which will reset the | |
7147 | * controller." */ | |
2662cab8 DB |
7148 | |
7149 | int rc = 0; | |
7150 | ||
1df8552a | 7151 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); |
2662cab8 | 7152 | |
1df8552a | 7153 | /* enter the D3hot power management state */ |
2662cab8 DB |
7154 | rc = pci_set_power_state(pdev, PCI_D3hot); |
7155 | if (rc) | |
7156 | return rc; | |
1df8552a SC |
7157 | |
7158 | msleep(500); | |
7159 | ||
7160 | /* enter the D0 power management state */ | |
2662cab8 DB |
7161 | rc = pci_set_power_state(pdev, PCI_D0); |
7162 | if (rc) | |
7163 | return rc; | |
c4853efe MM |
7164 | |
7165 | /* | |
7166 | * The P600 requires a small delay when changing states. | |
7167 | * Otherwise we may think the board did not reset and we bail. | |
7168 | * This for kdump only and is particular to the P600. | |
7169 | */ | |
7170 | msleep(500); | |
1df8552a SC |
7171 | } |
7172 | return 0; | |
7173 | } | |
7174 | ||
6f039790 | 7175 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
7176 | { |
7177 | memset(driver_version, 0, len); | |
f79cfec6 | 7178 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
7179 | } |
7180 | ||
6f039790 | 7181 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7182 | { |
7183 | char *driver_version; | |
7184 | int i, size = sizeof(cfgtable->driver_version); | |
7185 | ||
7186 | driver_version = kmalloc(size, GFP_KERNEL); | |
7187 | if (!driver_version) | |
7188 | return -ENOMEM; | |
7189 | ||
7190 | init_driver_version(driver_version, size); | |
7191 | for (i = 0; i < size; i++) | |
7192 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
7193 | kfree(driver_version); | |
7194 | return 0; | |
7195 | } | |
7196 | ||
6f039790 GKH |
7197 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
7198 | unsigned char *driver_ver) | |
580ada3c SC |
7199 | { |
7200 | int i; | |
7201 | ||
7202 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
7203 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
7204 | } | |
7205 | ||
6f039790 | 7206 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7207 | { |
7208 | ||
7209 | char *driver_ver, *old_driver_ver; | |
7210 | int rc, size = sizeof(cfgtable->driver_version); | |
7211 | ||
7212 | old_driver_ver = kmalloc(2 * size, GFP_KERNEL); | |
7213 | if (!old_driver_ver) | |
7214 | return -ENOMEM; | |
7215 | driver_ver = old_driver_ver + size; | |
7216 | ||
7217 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
7218 | * should have been changed, otherwise we know the reset failed. | |
7219 | */ | |
7220 | init_driver_version(old_driver_ver, size); | |
7221 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
7222 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
7223 | kfree(old_driver_ver); | |
7224 | return rc; | |
7225 | } | |
edd16368 | 7226 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 7227 | * states or the using the doorbell register. |
edd16368 | 7228 | */ |
6b6c1cd7 | 7229 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) |
edd16368 | 7230 | { |
1df8552a SC |
7231 | u64 cfg_offset; |
7232 | u32 cfg_base_addr; | |
7233 | u64 cfg_base_addr_index; | |
7234 | void __iomem *vaddr; | |
7235 | unsigned long paddr; | |
580ada3c | 7236 | u32 misc_fw_support; |
270d05de | 7237 | int rc; |
1df8552a | 7238 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 7239 | u32 use_doorbell; |
270d05de | 7240 | u16 command_register; |
edd16368 | 7241 | |
1df8552a SC |
7242 | /* For controllers as old as the P600, this is very nearly |
7243 | * the same thing as | |
edd16368 SC |
7244 | * |
7245 | * pci_save_state(pci_dev); | |
7246 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
7247 | * pci_set_power_state(pci_dev, PCI_D0); | |
7248 | * pci_restore_state(pci_dev); | |
7249 | * | |
1df8552a SC |
7250 | * For controllers newer than the P600, the pci power state |
7251 | * method of resetting doesn't work so we have another way | |
7252 | * using the doorbell register. | |
edd16368 | 7253 | */ |
18867659 | 7254 | |
60f923b9 RE |
7255 | if (!ctlr_is_resettable(board_id)) { |
7256 | dev_warn(&pdev->dev, "Controller not resettable\n"); | |
25c1e56a SC |
7257 | return -ENODEV; |
7258 | } | |
46380786 SC |
7259 | |
7260 | /* if controller is soft- but not hard resettable... */ | |
7261 | if (!ctlr_is_hard_resettable(board_id)) | |
7262 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 7263 | |
270d05de SC |
7264 | /* Save the PCI command register */ |
7265 | pci_read_config_word(pdev, 4, &command_register); | |
270d05de | 7266 | pci_save_state(pdev); |
edd16368 | 7267 | |
1df8552a SC |
7268 | /* find the first memory BAR, so we can find the cfg table */ |
7269 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
7270 | if (rc) | |
7271 | return rc; | |
7272 | vaddr = remap_pci_mem(paddr, 0x250); | |
7273 | if (!vaddr) | |
7274 | return -ENOMEM; | |
edd16368 | 7275 | |
1df8552a SC |
7276 | /* find cfgtable in order to check if reset via doorbell is supported */ |
7277 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
7278 | &cfg_base_addr_index, &cfg_offset); | |
7279 | if (rc) | |
7280 | goto unmap_vaddr; | |
7281 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
7282 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
7283 | if (!cfgtable) { | |
7284 | rc = -ENOMEM; | |
7285 | goto unmap_vaddr; | |
7286 | } | |
580ada3c SC |
7287 | rc = write_driver_ver_to_cfgtable(cfgtable); |
7288 | if (rc) | |
03741d95 | 7289 | goto unmap_cfgtable; |
edd16368 | 7290 | |
cf0b08d0 SC |
7291 | /* If reset via doorbell register is supported, use that. |
7292 | * There are two such methods. Favor the newest method. | |
7293 | */ | |
1df8552a | 7294 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
7295 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
7296 | if (use_doorbell) { | |
7297 | use_doorbell = DOORBELL_CTLR_RESET2; | |
7298 | } else { | |
7299 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
7300 | if (use_doorbell) { | |
050f7147 SC |
7301 | dev_warn(&pdev->dev, |
7302 | "Soft reset not supported. Firmware update is required.\n"); | |
64670ac8 | 7303 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
7304 | goto unmap_cfgtable; |
7305 | } | |
7306 | } | |
edd16368 | 7307 | |
1df8552a SC |
7308 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
7309 | if (rc) | |
7310 | goto unmap_cfgtable; | |
edd16368 | 7311 | |
270d05de | 7312 | pci_restore_state(pdev); |
270d05de | 7313 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 7314 | |
1df8552a SC |
7315 | /* Some devices (notably the HP Smart Array 5i Controller) |
7316 | need a little pause here */ | |
7317 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
7318 | ||
fe5389c8 SC |
7319 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
7320 | if (rc) { | |
7321 | dev_warn(&pdev->dev, | |
050f7147 | 7322 | "Failed waiting for board to become ready after hard reset\n"); |
fe5389c8 SC |
7323 | goto unmap_cfgtable; |
7324 | } | |
fe5389c8 | 7325 | |
580ada3c SC |
7326 | rc = controller_reset_failed(vaddr); |
7327 | if (rc < 0) | |
7328 | goto unmap_cfgtable; | |
7329 | if (rc) { | |
64670ac8 SC |
7330 | dev_warn(&pdev->dev, "Unable to successfully reset " |
7331 | "controller. Will try soft reset.\n"); | |
7332 | rc = -ENOTSUPP; | |
580ada3c | 7333 | } else { |
64670ac8 | 7334 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
7335 | } |
7336 | ||
7337 | unmap_cfgtable: | |
7338 | iounmap(cfgtable); | |
7339 | ||
7340 | unmap_vaddr: | |
7341 | iounmap(vaddr); | |
7342 | return rc; | |
edd16368 SC |
7343 | } |
7344 | ||
7345 | /* | |
7346 | * We cannot read the structure directly, for portability we must use | |
7347 | * the io functions. | |
7348 | * This is for debug only. | |
7349 | */ | |
42a91641 | 7350 | static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) |
edd16368 | 7351 | { |
58f8665c | 7352 | #ifdef HPSA_DEBUG |
edd16368 SC |
7353 | int i; |
7354 | char temp_name[17]; | |
7355 | ||
7356 | dev_info(dev, "Controller Configuration information\n"); | |
7357 | dev_info(dev, "------------------------------------\n"); | |
7358 | for (i = 0; i < 4; i++) | |
7359 | temp_name[i] = readb(&(tb->Signature[i])); | |
7360 | temp_name[4] = '\0'; | |
7361 | dev_info(dev, " Signature = %s\n", temp_name); | |
7362 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
7363 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
7364 | readl(&(tb->TransportSupport))); | |
7365 | dev_info(dev, " Transport methods active = 0x%x\n", | |
7366 | readl(&(tb->TransportActive))); | |
7367 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
7368 | readl(&(tb->HostWrite.TransportRequest))); | |
7369 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
7370 | readl(&(tb->HostWrite.CoalIntDelay))); | |
7371 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
7372 | readl(&(tb->HostWrite.CoalIntCount))); | |
69d6e33d | 7373 | dev_info(dev, " Max outstanding commands = %d\n", |
edd16368 SC |
7374 | readl(&(tb->CmdsOutMax))); |
7375 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
7376 | for (i = 0; i < 16; i++) | |
7377 | temp_name[i] = readb(&(tb->ServerName[i])); | |
7378 | temp_name[16] = '\0'; | |
7379 | dev_info(dev, " Server Name = %s\n", temp_name); | |
7380 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
7381 | readl(&(tb->HeartBeat))); | |
edd16368 | 7382 | #endif /* HPSA_DEBUG */ |
58f8665c | 7383 | } |
edd16368 SC |
7384 | |
7385 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
7386 | { | |
7387 | int i, offset, mem_type, bar_type; | |
7388 | ||
7389 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
7390 | return 0; | |
7391 | offset = 0; | |
7392 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
7393 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
7394 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
7395 | offset += 4; | |
7396 | else { | |
7397 | mem_type = pci_resource_flags(pdev, i) & | |
7398 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
7399 | switch (mem_type) { | |
7400 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
7401 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
7402 | offset += 4; /* 32 bit */ | |
7403 | break; | |
7404 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
7405 | offset += 8; | |
7406 | break; | |
7407 | default: /* reserved in PCI 2.2 */ | |
7408 | dev_warn(&pdev->dev, | |
7409 | "base address is invalid\n"); | |
7410 | return -1; | |
7411 | break; | |
7412 | } | |
7413 | } | |
7414 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
7415 | return i + 1; | |
7416 | } | |
7417 | return -1; | |
7418 | } | |
7419 | ||
cc64c817 RE |
7420 | static void hpsa_disable_interrupt_mode(struct ctlr_info *h) |
7421 | { | |
7422 | if (h->msix_vector) { | |
7423 | if (h->pdev->msix_enabled) | |
7424 | pci_disable_msix(h->pdev); | |
105a3dbc | 7425 | h->msix_vector = 0; |
cc64c817 RE |
7426 | } else if (h->msi_vector) { |
7427 | if (h->pdev->msi_enabled) | |
7428 | pci_disable_msi(h->pdev); | |
105a3dbc | 7429 | h->msi_vector = 0; |
cc64c817 RE |
7430 | } |
7431 | } | |
7432 | ||
edd16368 | 7433 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on |
050f7147 | 7434 | * controllers that are capable. If not, we use legacy INTx mode. |
edd16368 | 7435 | */ |
6f039790 | 7436 | static void hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 SC |
7437 | { |
7438 | #ifdef CONFIG_PCI_MSI | |
254f796b MG |
7439 | int err, i; |
7440 | struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES]; | |
7441 | ||
7442 | for (i = 0; i < MAX_REPLY_QUEUES; i++) { | |
7443 | hpsa_msix_entries[i].vector = 0; | |
7444 | hpsa_msix_entries[i].entry = i; | |
7445 | } | |
edd16368 SC |
7446 | |
7447 | /* Some boards advertise MSI but don't really support it */ | |
6b3f4c52 SC |
7448 | if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) || |
7449 | (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11)) | |
edd16368 | 7450 | goto default_int_mode; |
55c06c71 | 7451 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) { |
050f7147 | 7452 | dev_info(&h->pdev->dev, "MSI-X capable controller\n"); |
eee0f03a | 7453 | h->msix_vector = MAX_REPLY_QUEUES; |
f89439bc SC |
7454 | if (h->msix_vector > num_online_cpus()) |
7455 | h->msix_vector = num_online_cpus(); | |
18fce3c4 AG |
7456 | err = pci_enable_msix_range(h->pdev, hpsa_msix_entries, |
7457 | 1, h->msix_vector); | |
7458 | if (err < 0) { | |
7459 | dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err); | |
7460 | h->msix_vector = 0; | |
7461 | goto single_msi_mode; | |
7462 | } else if (err < h->msix_vector) { | |
55c06c71 | 7463 | dev_warn(&h->pdev->dev, "only %d MSI-X vectors " |
edd16368 | 7464 | "available\n", err); |
edd16368 | 7465 | } |
18fce3c4 AG |
7466 | h->msix_vector = err; |
7467 | for (i = 0; i < h->msix_vector; i++) | |
7468 | h->intr[i] = hpsa_msix_entries[i].vector; | |
7469 | return; | |
edd16368 | 7470 | } |
18fce3c4 | 7471 | single_msi_mode: |
55c06c71 | 7472 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) { |
050f7147 | 7473 | dev_info(&h->pdev->dev, "MSI capable controller\n"); |
55c06c71 | 7474 | if (!pci_enable_msi(h->pdev)) |
edd16368 SC |
7475 | h->msi_vector = 1; |
7476 | else | |
55c06c71 | 7477 | dev_warn(&h->pdev->dev, "MSI init failed\n"); |
edd16368 SC |
7478 | } |
7479 | default_int_mode: | |
7480 | #endif /* CONFIG_PCI_MSI */ | |
7481 | /* if we get here we're going to use the default interrupt mode */ | |
a9a3a273 | 7482 | h->intr[h->intr_mode] = h->pdev->irq; |
edd16368 SC |
7483 | } |
7484 | ||
6f039790 | 7485 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id) |
e5c880d1 SC |
7486 | { |
7487 | int i; | |
7488 | u32 subsystem_vendor_id, subsystem_device_id; | |
7489 | ||
7490 | subsystem_vendor_id = pdev->subsystem_vendor; | |
7491 | subsystem_device_id = pdev->subsystem_device; | |
7492 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
7493 | subsystem_vendor_id; | |
7494 | ||
7495 | for (i = 0; i < ARRAY_SIZE(products); i++) | |
7496 | if (*board_id == products[i].board_id) | |
7497 | return i; | |
7498 | ||
6798cc0a SC |
7499 | if ((subsystem_vendor_id != PCI_VENDOR_ID_HP && |
7500 | subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) || | |
7501 | !hpsa_allow_any) { | |
e5c880d1 SC |
7502 | dev_warn(&pdev->dev, "unrecognized board ID: " |
7503 | "0x%08x, ignoring.\n", *board_id); | |
7504 | return -ENODEV; | |
7505 | } | |
7506 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ | |
7507 | } | |
7508 | ||
6f039790 GKH |
7509 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
7510 | unsigned long *memory_bar) | |
3a7774ce SC |
7511 | { |
7512 | int i; | |
7513 | ||
7514 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 7515 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 7516 | /* addressing mode bits already removed */ |
12d2cd47 SC |
7517 | *memory_bar = pci_resource_start(pdev, i); |
7518 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
7519 | *memory_bar); |
7520 | return 0; | |
7521 | } | |
12d2cd47 | 7522 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
7523 | return -ENODEV; |
7524 | } | |
7525 | ||
6f039790 GKH |
7526 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
7527 | int wait_for_ready) | |
2c4c8c8b | 7528 | { |
fe5389c8 | 7529 | int i, iterations; |
2c4c8c8b | 7530 | u32 scratchpad; |
fe5389c8 SC |
7531 | if (wait_for_ready) |
7532 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
7533 | else | |
7534 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 7535 | |
fe5389c8 SC |
7536 | for (i = 0; i < iterations; i++) { |
7537 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
7538 | if (wait_for_ready) { | |
7539 | if (scratchpad == HPSA_FIRMWARE_READY) | |
7540 | return 0; | |
7541 | } else { | |
7542 | if (scratchpad != HPSA_FIRMWARE_READY) | |
7543 | return 0; | |
7544 | } | |
2c4c8c8b SC |
7545 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
7546 | } | |
fe5389c8 | 7547 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
7548 | return -ENODEV; |
7549 | } | |
7550 | ||
6f039790 GKH |
7551 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
7552 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
7553 | u64 *cfg_offset) | |
a51fd47f SC |
7554 | { |
7555 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
7556 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
7557 | *cfg_base_addr &= (u32) 0x0000ffff; | |
7558 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
7559 | if (*cfg_base_addr_index == -1) { | |
7560 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
7561 | return -ENODEV; | |
7562 | } | |
7563 | return 0; | |
7564 | } | |
7565 | ||
195f2c65 RE |
7566 | static void hpsa_free_cfgtables(struct ctlr_info *h) |
7567 | { | |
105a3dbc | 7568 | if (h->transtable) { |
195f2c65 | 7569 | iounmap(h->transtable); |
105a3dbc RE |
7570 | h->transtable = NULL; |
7571 | } | |
7572 | if (h->cfgtable) { | |
195f2c65 | 7573 | iounmap(h->cfgtable); |
105a3dbc RE |
7574 | h->cfgtable = NULL; |
7575 | } | |
195f2c65 RE |
7576 | } |
7577 | ||
7578 | /* Find and map CISS config table and transfer table | |
7579 | + * several items must be unmapped (freed) later | |
7580 | + * */ | |
6f039790 | 7581 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 7582 | { |
01a02ffc SC |
7583 | u64 cfg_offset; |
7584 | u32 cfg_base_addr; | |
7585 | u64 cfg_base_addr_index; | |
303932fd | 7586 | u32 trans_offset; |
a51fd47f | 7587 | int rc; |
77c4495c | 7588 | |
a51fd47f SC |
7589 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
7590 | &cfg_base_addr_index, &cfg_offset); | |
7591 | if (rc) | |
7592 | return rc; | |
77c4495c | 7593 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 7594 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
cd3c81c4 RE |
7595 | if (!h->cfgtable) { |
7596 | dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); | |
77c4495c | 7597 | return -ENOMEM; |
cd3c81c4 | 7598 | } |
580ada3c SC |
7599 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
7600 | if (rc) | |
7601 | return rc; | |
77c4495c | 7602 | /* Find performant mode table. */ |
a51fd47f | 7603 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
7604 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
7605 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
7606 | sizeof(*h->transtable)); | |
195f2c65 RE |
7607 | if (!h->transtable) { |
7608 | dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); | |
7609 | hpsa_free_cfgtables(h); | |
77c4495c | 7610 | return -ENOMEM; |
195f2c65 | 7611 | } |
77c4495c SC |
7612 | return 0; |
7613 | } | |
7614 | ||
6f039790 | 7615 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b | 7616 | { |
41ce4c35 SC |
7617 | #define MIN_MAX_COMMANDS 16 |
7618 | BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); | |
7619 | ||
7620 | h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); | |
72ceeaec SC |
7621 | |
7622 | /* Limit commands in memory limited kdump scenario. */ | |
7623 | if (reset_devices && h->max_commands > 32) | |
7624 | h->max_commands = 32; | |
7625 | ||
41ce4c35 SC |
7626 | if (h->max_commands < MIN_MAX_COMMANDS) { |
7627 | dev_warn(&h->pdev->dev, | |
7628 | "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", | |
7629 | h->max_commands, | |
7630 | MIN_MAX_COMMANDS); | |
7631 | h->max_commands = MIN_MAX_COMMANDS; | |
cba3d38b SC |
7632 | } |
7633 | } | |
7634 | ||
c7ee65b3 WS |
7635 | /* If the controller reports that the total max sg entries is greater than 512, |
7636 | * then we know that chained SG blocks work. (Original smart arrays did not | |
7637 | * support chained SG blocks and would return zero for max sg entries.) | |
7638 | */ | |
7639 | static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) | |
7640 | { | |
7641 | return h->maxsgentries > 512; | |
7642 | } | |
7643 | ||
b93d7536 SC |
7644 | /* Interrogate the hardware for some limits: |
7645 | * max commands, max SG elements without chaining, and with chaining, | |
7646 | * SG chain block size, etc. | |
7647 | */ | |
6f039790 | 7648 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 7649 | { |
cba3d38b | 7650 | hpsa_get_max_perf_mode_cmds(h); |
45fcb86e | 7651 | h->nr_cmds = h->max_commands; |
b93d7536 | 7652 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); |
283b4a9b | 7653 | h->fw_support = readl(&(h->cfgtable->misc_fw_support)); |
c7ee65b3 WS |
7654 | if (hpsa_supports_chained_sg_blocks(h)) { |
7655 | /* Limit in-command s/g elements to 32 save dma'able memory. */ | |
b93d7536 | 7656 | h->max_cmd_sg_entries = 32; |
1a63ea6f | 7657 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; |
b93d7536 SC |
7658 | h->maxsgentries--; /* save one for chain pointer */ |
7659 | } else { | |
c7ee65b3 WS |
7660 | /* |
7661 | * Original smart arrays supported at most 31 s/g entries | |
7662 | * embedded inline in the command (trying to use more | |
7663 | * would lock up the controller) | |
7664 | */ | |
7665 | h->max_cmd_sg_entries = 31; | |
1a63ea6f | 7666 | h->maxsgentries = 31; /* default to traditional values */ |
c7ee65b3 | 7667 | h->chainsize = 0; |
b93d7536 | 7668 | } |
75167d2c SC |
7669 | |
7670 | /* Find out what task management functions are supported and cache */ | |
7671 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
0e7a7fce ST |
7672 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) |
7673 | dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); | |
7674 | if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
7675 | dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); | |
8be986cc SC |
7676 | if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) |
7677 | dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); | |
b93d7536 SC |
7678 | } |
7679 | ||
76c46e49 SC |
7680 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
7681 | { | |
0fc9fd40 | 7682 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
050f7147 | 7683 | dev_err(&h->pdev->dev, "not a valid CISS config table\n"); |
76c46e49 SC |
7684 | return false; |
7685 | } | |
7686 | return true; | |
7687 | } | |
7688 | ||
97a5e98c | 7689 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 7690 | { |
97a5e98c | 7691 | u32 driver_support; |
f7c39101 | 7692 | |
97a5e98c | 7693 | driver_support = readl(&(h->cfgtable->driver_support)); |
0b9e7b74 AB |
7694 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ |
7695 | #ifdef CONFIG_X86 | |
97a5e98c | 7696 | driver_support |= ENABLE_SCSI_PREFETCH; |
f7c39101 | 7697 | #endif |
28e13446 SC |
7698 | driver_support |= ENABLE_UNIT_ATTN; |
7699 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
7700 | } |
7701 | ||
3d0eab67 SC |
7702 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
7703 | * in a prefetch beyond physical memory. | |
7704 | */ | |
7705 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
7706 | { | |
7707 | u32 dma_prefetch; | |
7708 | ||
7709 | if (h->board_id != 0x3225103C) | |
7710 | return; | |
7711 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
7712 | dma_prefetch |= 0x8000; | |
7713 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
7714 | } | |
7715 | ||
c706a795 | 7716 | static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) |
76438d08 SC |
7717 | { |
7718 | int i; | |
7719 | u32 doorbell_value; | |
7720 | unsigned long flags; | |
7721 | /* wait until the clear_event_notify bit 6 is cleared by controller. */ | |
007e7aa9 | 7722 | for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { |
76438d08 SC |
7723 | spin_lock_irqsave(&h->lock, flags); |
7724 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7725 | spin_unlock_irqrestore(&h->lock, flags); | |
7726 | if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) | |
c706a795 | 7727 | goto done; |
76438d08 | 7728 | /* delay and try again */ |
007e7aa9 | 7729 | msleep(CLEAR_EVENT_WAIT_INTERVAL); |
76438d08 | 7730 | } |
c706a795 RE |
7731 | return -ENODEV; |
7732 | done: | |
7733 | return 0; | |
76438d08 SC |
7734 | } |
7735 | ||
c706a795 | 7736 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
7737 | { |
7738 | int i; | |
6eaf46fd SC |
7739 | u32 doorbell_value; |
7740 | unsigned long flags; | |
eb6b2ae9 SC |
7741 | |
7742 | /* under certain very rare conditions, this can take awhile. | |
7743 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
7744 | * as we enter this code.) | |
7745 | */ | |
007e7aa9 | 7746 | for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { |
25163bd5 WS |
7747 | if (h->remove_in_progress) |
7748 | goto done; | |
6eaf46fd SC |
7749 | spin_lock_irqsave(&h->lock, flags); |
7750 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7751 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 7752 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
c706a795 | 7753 | goto done; |
eb6b2ae9 | 7754 | /* delay and try again */ |
007e7aa9 | 7755 | msleep(MODE_CHANGE_WAIT_INTERVAL); |
eb6b2ae9 | 7756 | } |
c706a795 RE |
7757 | return -ENODEV; |
7758 | done: | |
7759 | return 0; | |
3f4336f3 SC |
7760 | } |
7761 | ||
c706a795 | 7762 | /* return -ENODEV or other reason on error, 0 on success */ |
6f039790 | 7763 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
7764 | { |
7765 | u32 trans_support; | |
7766 | ||
7767 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
7768 | if (!(trans_support & SIMPLE_MODE)) | |
7769 | return -ENOTSUPP; | |
7770 | ||
7771 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
283b4a9b | 7772 | |
3f4336f3 SC |
7773 | /* Update the field, and then ring the doorbell */ |
7774 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
b9af4937 | 7775 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
3f4336f3 | 7776 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
7777 | if (hpsa_wait_for_mode_change_ack(h)) |
7778 | goto error; | |
eb6b2ae9 | 7779 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
283b4a9b SC |
7780 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) |
7781 | goto error; | |
960a30e7 | 7782 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 | 7783 | return 0; |
283b4a9b | 7784 | error: |
050f7147 | 7785 | dev_err(&h->pdev->dev, "failed to enter simple mode\n"); |
283b4a9b | 7786 | return -ENODEV; |
eb6b2ae9 SC |
7787 | } |
7788 | ||
195f2c65 RE |
7789 | /* free items allocated or mapped by hpsa_pci_init */ |
7790 | static void hpsa_free_pci_init(struct ctlr_info *h) | |
7791 | { | |
7792 | hpsa_free_cfgtables(h); /* pci_init 4 */ | |
7793 | iounmap(h->vaddr); /* pci_init 3 */ | |
105a3dbc | 7794 | h->vaddr = NULL; |
195f2c65 | 7795 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
943a7021 RE |
7796 | /* |
7797 | * call pci_disable_device before pci_release_regions per | |
7798 | * Documentation/PCI/pci.txt | |
7799 | */ | |
195f2c65 | 7800 | pci_disable_device(h->pdev); /* pci_init 1 */ |
943a7021 | 7801 | pci_release_regions(h->pdev); /* pci_init 2 */ |
195f2c65 RE |
7802 | } |
7803 | ||
7804 | /* several items must be freed later */ | |
6f039790 | 7805 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 7806 | { |
eb6b2ae9 | 7807 | int prod_index, err; |
edd16368 | 7808 | |
e5c880d1 SC |
7809 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id); |
7810 | if (prod_index < 0) | |
60f923b9 | 7811 | return prod_index; |
e5c880d1 SC |
7812 | h->product_name = products[prod_index].product_name; |
7813 | h->access = *(products[prod_index].access); | |
edd16368 | 7814 | |
9b5c48c2 SC |
7815 | h->needs_abort_tags_swizzled = |
7816 | ctlr_needs_abort_tags_swizzled(h->board_id); | |
7817 | ||
e5a44df8 MG |
7818 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
7819 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
7820 | ||
55c06c71 | 7821 | err = pci_enable_device(h->pdev); |
edd16368 | 7822 | if (err) { |
195f2c65 | 7823 | dev_err(&h->pdev->dev, "failed to enable PCI device\n"); |
943a7021 | 7824 | pci_disable_device(h->pdev); |
edd16368 SC |
7825 | return err; |
7826 | } | |
7827 | ||
f79cfec6 | 7828 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 7829 | if (err) { |
55c06c71 | 7830 | dev_err(&h->pdev->dev, |
195f2c65 | 7831 | "failed to obtain PCI resources\n"); |
943a7021 RE |
7832 | pci_disable_device(h->pdev); |
7833 | return err; | |
edd16368 | 7834 | } |
4fa604e1 RE |
7835 | |
7836 | pci_set_master(h->pdev); | |
7837 | ||
6b3f4c52 | 7838 | hpsa_interrupt_mode(h); |
12d2cd47 | 7839 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 7840 | if (err) |
195f2c65 | 7841 | goto clean2; /* intmode+region, pci */ |
edd16368 | 7842 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 | 7843 | if (!h->vaddr) { |
195f2c65 | 7844 | dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); |
204892e9 | 7845 | err = -ENOMEM; |
195f2c65 | 7846 | goto clean2; /* intmode+region, pci */ |
204892e9 | 7847 | } |
fe5389c8 | 7848 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 7849 | if (err) |
195f2c65 | 7850 | goto clean3; /* vaddr, intmode+region, pci */ |
77c4495c SC |
7851 | err = hpsa_find_cfgtables(h); |
7852 | if (err) | |
195f2c65 | 7853 | goto clean3; /* vaddr, intmode+region, pci */ |
b93d7536 | 7854 | hpsa_find_board_params(h); |
edd16368 | 7855 | |
76c46e49 | 7856 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 | 7857 | err = -ENODEV; |
195f2c65 | 7858 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 | 7859 | } |
97a5e98c | 7860 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 7861 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
7862 | err = hpsa_enter_simple_mode(h); |
7863 | if (err) | |
195f2c65 | 7864 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 SC |
7865 | return 0; |
7866 | ||
195f2c65 RE |
7867 | clean4: /* cfgtables, vaddr, intmode+region, pci */ |
7868 | hpsa_free_cfgtables(h); | |
7869 | clean3: /* vaddr, intmode+region, pci */ | |
7870 | iounmap(h->vaddr); | |
105a3dbc | 7871 | h->vaddr = NULL; |
195f2c65 RE |
7872 | clean2: /* intmode+region, pci */ |
7873 | hpsa_disable_interrupt_mode(h); | |
943a7021 RE |
7874 | /* |
7875 | * call pci_disable_device before pci_release_regions per | |
7876 | * Documentation/PCI/pci.txt | |
7877 | */ | |
195f2c65 | 7878 | pci_disable_device(h->pdev); |
943a7021 | 7879 | pci_release_regions(h->pdev); |
edd16368 SC |
7880 | return err; |
7881 | } | |
7882 | ||
6f039790 | 7883 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
7884 | { |
7885 | int rc; | |
7886 | ||
7887 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
7888 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
7889 | if (!h->hba_inquiry_data) | |
7890 | return; | |
7891 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
7892 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
7893 | if (rc != 0) { | |
7894 | kfree(h->hba_inquiry_data); | |
7895 | h->hba_inquiry_data = NULL; | |
7896 | } | |
7897 | } | |
7898 | ||
6b6c1cd7 | 7899 | static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) |
4c2a8c40 | 7900 | { |
1df8552a | 7901 | int rc, i; |
3b747298 | 7902 | void __iomem *vaddr; |
4c2a8c40 SC |
7903 | |
7904 | if (!reset_devices) | |
7905 | return 0; | |
7906 | ||
132aa220 TH |
7907 | /* kdump kernel is loading, we don't know in which state is |
7908 | * the pci interface. The dev->enable_cnt is equal zero | |
7909 | * so we call enable+disable, wait a while and switch it on. | |
7910 | */ | |
7911 | rc = pci_enable_device(pdev); | |
7912 | if (rc) { | |
7913 | dev_warn(&pdev->dev, "Failed to enable PCI device\n"); | |
7914 | return -ENODEV; | |
7915 | } | |
7916 | pci_disable_device(pdev); | |
7917 | msleep(260); /* a randomly chosen number */ | |
7918 | rc = pci_enable_device(pdev); | |
7919 | if (rc) { | |
7920 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
7921 | return -ENODEV; | |
7922 | } | |
4fa604e1 | 7923 | |
859c75ab | 7924 | pci_set_master(pdev); |
4fa604e1 | 7925 | |
3b747298 TH |
7926 | vaddr = pci_ioremap_bar(pdev, 0); |
7927 | if (vaddr == NULL) { | |
7928 | rc = -ENOMEM; | |
7929 | goto out_disable; | |
7930 | } | |
7931 | writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
7932 | iounmap(vaddr); | |
7933 | ||
1df8552a | 7934 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
6b6c1cd7 | 7935 | rc = hpsa_kdump_hard_reset_controller(pdev, board_id); |
4c2a8c40 | 7936 | |
1df8552a SC |
7937 | /* -ENOTSUPP here means we cannot reset the controller |
7938 | * but it's already (and still) up and running in | |
18867659 SC |
7939 | * "performant mode". Or, it might be 640x, which can't reset |
7940 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a | 7941 | */ |
adf1b3a3 | 7942 | if (rc) |
132aa220 | 7943 | goto out_disable; |
4c2a8c40 SC |
7944 | |
7945 | /* Now try to get the controller to respond to a no-op */ | |
1ba66c9c | 7946 | dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
7947 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
7948 | if (hpsa_noop(pdev) == 0) | |
7949 | break; | |
7950 | else | |
7951 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
7952 | (i < 11 ? "; re-trying" : "")); | |
7953 | } | |
132aa220 TH |
7954 | |
7955 | out_disable: | |
7956 | ||
7957 | pci_disable_device(pdev); | |
7958 | return rc; | |
4c2a8c40 SC |
7959 | } |
7960 | ||
1fb7c98a RE |
7961 | static void hpsa_free_cmd_pool(struct ctlr_info *h) |
7962 | { | |
7963 | kfree(h->cmd_pool_bits); | |
105a3dbc RE |
7964 | h->cmd_pool_bits = NULL; |
7965 | if (h->cmd_pool) { | |
1fb7c98a RE |
7966 | pci_free_consistent(h->pdev, |
7967 | h->nr_cmds * sizeof(struct CommandList), | |
7968 | h->cmd_pool, | |
7969 | h->cmd_pool_dhandle); | |
105a3dbc RE |
7970 | h->cmd_pool = NULL; |
7971 | h->cmd_pool_dhandle = 0; | |
7972 | } | |
7973 | if (h->errinfo_pool) { | |
1fb7c98a RE |
7974 | pci_free_consistent(h->pdev, |
7975 | h->nr_cmds * sizeof(struct ErrorInfo), | |
7976 | h->errinfo_pool, | |
7977 | h->errinfo_pool_dhandle); | |
105a3dbc RE |
7978 | h->errinfo_pool = NULL; |
7979 | h->errinfo_pool_dhandle = 0; | |
7980 | } | |
1fb7c98a RE |
7981 | } |
7982 | ||
d37ffbe4 | 7983 | static int hpsa_alloc_cmd_pool(struct ctlr_info *h) |
2e9d1b36 SC |
7984 | { |
7985 | h->cmd_pool_bits = kzalloc( | |
7986 | DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * | |
7987 | sizeof(unsigned long), GFP_KERNEL); | |
7988 | h->cmd_pool = pci_alloc_consistent(h->pdev, | |
7989 | h->nr_cmds * sizeof(*h->cmd_pool), | |
7990 | &(h->cmd_pool_dhandle)); | |
7991 | h->errinfo_pool = pci_alloc_consistent(h->pdev, | |
7992 | h->nr_cmds * sizeof(*h->errinfo_pool), | |
7993 | &(h->errinfo_pool_dhandle)); | |
7994 | if ((h->cmd_pool_bits == NULL) | |
7995 | || (h->cmd_pool == NULL) | |
7996 | || (h->errinfo_pool == NULL)) { | |
7997 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
2c143342 | 7998 | goto clean_up; |
2e9d1b36 | 7999 | } |
360c73bd | 8000 | hpsa_preinitialize_commands(h); |
2e9d1b36 | 8001 | return 0; |
2c143342 RE |
8002 | clean_up: |
8003 | hpsa_free_cmd_pool(h); | |
8004 | return -ENOMEM; | |
2e9d1b36 SC |
8005 | } |
8006 | ||
41b3cf08 SC |
8007 | static void hpsa_irq_affinity_hints(struct ctlr_info *h) |
8008 | { | |
ec429952 | 8009 | int i, cpu; |
41b3cf08 SC |
8010 | |
8011 | cpu = cpumask_first(cpu_online_mask); | |
8012 | for (i = 0; i < h->msix_vector; i++) { | |
ec429952 | 8013 | irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu)); |
41b3cf08 SC |
8014 | cpu = cpumask_next(cpu, cpu_online_mask); |
8015 | } | |
8016 | } | |
8017 | ||
ec501a18 RE |
8018 | /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ |
8019 | static void hpsa_free_irqs(struct ctlr_info *h) | |
8020 | { | |
8021 | int i; | |
8022 | ||
8023 | if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) { | |
8024 | /* Single reply queue, only one irq to free */ | |
8025 | i = h->intr_mode; | |
8026 | irq_set_affinity_hint(h->intr[i], NULL); | |
8027 | free_irq(h->intr[i], &h->q[i]); | |
105a3dbc | 8028 | h->q[i] = 0; |
ec501a18 RE |
8029 | return; |
8030 | } | |
8031 | ||
8032 | for (i = 0; i < h->msix_vector; i++) { | |
8033 | irq_set_affinity_hint(h->intr[i], NULL); | |
8034 | free_irq(h->intr[i], &h->q[i]); | |
105a3dbc | 8035 | h->q[i] = 0; |
ec501a18 | 8036 | } |
a4e17fc1 RE |
8037 | for (; i < MAX_REPLY_QUEUES; i++) |
8038 | h->q[i] = 0; | |
ec501a18 RE |
8039 | } |
8040 | ||
9ee61794 RE |
8041 | /* returns 0 on success; cleans up and returns -Enn on error */ |
8042 | static int hpsa_request_irqs(struct ctlr_info *h, | |
0ae01a32 SC |
8043 | irqreturn_t (*msixhandler)(int, void *), |
8044 | irqreturn_t (*intxhandler)(int, void *)) | |
8045 | { | |
254f796b | 8046 | int rc, i; |
0ae01a32 | 8047 | |
254f796b MG |
8048 | /* |
8049 | * initialize h->q[x] = x so that interrupt handlers know which | |
8050 | * queue to process. | |
8051 | */ | |
8052 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
8053 | h->q[i] = (u8) i; | |
8054 | ||
eee0f03a | 8055 | if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) { |
254f796b | 8056 | /* If performant mode and MSI-X, use multiple reply queues */ |
a4e17fc1 | 8057 | for (i = 0; i < h->msix_vector; i++) { |
8b47004a | 8058 | sprintf(h->intrname[i], "%s-msix%d", h->devname, i); |
254f796b | 8059 | rc = request_irq(h->intr[i], msixhandler, |
8b47004a | 8060 | 0, h->intrname[i], |
254f796b | 8061 | &h->q[i]); |
a4e17fc1 RE |
8062 | if (rc) { |
8063 | int j; | |
8064 | ||
8065 | dev_err(&h->pdev->dev, | |
8066 | "failed to get irq %d for %s\n", | |
8067 | h->intr[i], h->devname); | |
8068 | for (j = 0; j < i; j++) { | |
8069 | free_irq(h->intr[j], &h->q[j]); | |
8070 | h->q[j] = 0; | |
8071 | } | |
8072 | for (; j < MAX_REPLY_QUEUES; j++) | |
8073 | h->q[j] = 0; | |
8074 | return rc; | |
8075 | } | |
8076 | } | |
41b3cf08 | 8077 | hpsa_irq_affinity_hints(h); |
254f796b MG |
8078 | } else { |
8079 | /* Use single reply pool */ | |
eee0f03a | 8080 | if (h->msix_vector > 0 || h->msi_vector) { |
8b47004a RE |
8081 | if (h->msix_vector) |
8082 | sprintf(h->intrname[h->intr_mode], | |
8083 | "%s-msix", h->devname); | |
8084 | else | |
8085 | sprintf(h->intrname[h->intr_mode], | |
8086 | "%s-msi", h->devname); | |
254f796b | 8087 | rc = request_irq(h->intr[h->intr_mode], |
8b47004a RE |
8088 | msixhandler, 0, |
8089 | h->intrname[h->intr_mode], | |
254f796b MG |
8090 | &h->q[h->intr_mode]); |
8091 | } else { | |
8b47004a RE |
8092 | sprintf(h->intrname[h->intr_mode], |
8093 | "%s-intx", h->devname); | |
254f796b | 8094 | rc = request_irq(h->intr[h->intr_mode], |
8b47004a RE |
8095 | intxhandler, IRQF_SHARED, |
8096 | h->intrname[h->intr_mode], | |
254f796b MG |
8097 | &h->q[h->intr_mode]); |
8098 | } | |
105a3dbc | 8099 | irq_set_affinity_hint(h->intr[h->intr_mode], NULL); |
254f796b | 8100 | } |
0ae01a32 | 8101 | if (rc) { |
195f2c65 | 8102 | dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", |
0ae01a32 | 8103 | h->intr[h->intr_mode], h->devname); |
195f2c65 | 8104 | hpsa_free_irqs(h); |
0ae01a32 SC |
8105 | return -ENODEV; |
8106 | } | |
8107 | return 0; | |
8108 | } | |
8109 | ||
6f039790 | 8110 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 | 8111 | { |
39c53f55 | 8112 | int rc; |
bf43caf3 | 8113 | hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER); |
64670ac8 SC |
8114 | |
8115 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
39c53f55 RE |
8116 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); |
8117 | if (rc) { | |
64670ac8 | 8118 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); |
39c53f55 | 8119 | return rc; |
64670ac8 SC |
8120 | } |
8121 | ||
8122 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
39c53f55 RE |
8123 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
8124 | if (rc) { | |
64670ac8 SC |
8125 | dev_warn(&h->pdev->dev, "Board failed to become ready " |
8126 | "after soft reset.\n"); | |
39c53f55 | 8127 | return rc; |
64670ac8 SC |
8128 | } |
8129 | ||
8130 | return 0; | |
8131 | } | |
8132 | ||
072b0518 SC |
8133 | static void hpsa_free_reply_queues(struct ctlr_info *h) |
8134 | { | |
8135 | int i; | |
8136 | ||
8137 | for (i = 0; i < h->nreply_queues; i++) { | |
8138 | if (!h->reply_queue[i].head) | |
8139 | continue; | |
1fb7c98a RE |
8140 | pci_free_consistent(h->pdev, |
8141 | h->reply_queue_size, | |
8142 | h->reply_queue[i].head, | |
8143 | h->reply_queue[i].busaddr); | |
072b0518 SC |
8144 | h->reply_queue[i].head = NULL; |
8145 | h->reply_queue[i].busaddr = 0; | |
8146 | } | |
105a3dbc | 8147 | h->reply_queue_size = 0; |
072b0518 SC |
8148 | } |
8149 | ||
0097f0f4 SC |
8150 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) |
8151 | { | |
105a3dbc RE |
8152 | hpsa_free_performant_mode(h); /* init_one 7 */ |
8153 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
8154 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
8155 | hpsa_free_irqs(h); /* init_one 4 */ | |
2946e82b RE |
8156 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
8157 | h->scsi_host = NULL; /* init_one 3 */ | |
8158 | hpsa_free_pci_init(h); /* init_one 2_5 */ | |
9ecd953a RE |
8159 | free_percpu(h->lockup_detected); /* init_one 2 */ |
8160 | h->lockup_detected = NULL; /* init_one 2 */ | |
8161 | if (h->resubmit_wq) { | |
8162 | destroy_workqueue(h->resubmit_wq); /* init_one 1 */ | |
8163 | h->resubmit_wq = NULL; | |
8164 | } | |
8165 | if (h->rescan_ctlr_wq) { | |
8166 | destroy_workqueue(h->rescan_ctlr_wq); | |
8167 | h->rescan_ctlr_wq = NULL; | |
8168 | } | |
105a3dbc | 8169 | kfree(h); /* init_one 1 */ |
64670ac8 SC |
8170 | } |
8171 | ||
a0c12413 | 8172 | /* Called when controller lockup detected. */ |
f2405db8 | 8173 | static void fail_all_outstanding_cmds(struct ctlr_info *h) |
a0c12413 | 8174 | { |
281a7fd0 WS |
8175 | int i, refcount; |
8176 | struct CommandList *c; | |
25163bd5 | 8177 | int failcount = 0; |
a0c12413 | 8178 | |
080ef1cc | 8179 | flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ |
f2405db8 | 8180 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 8181 | c = h->cmd_pool + i; |
281a7fd0 WS |
8182 | refcount = atomic_inc_return(&c->refcount); |
8183 | if (refcount > 1) { | |
25163bd5 | 8184 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; |
281a7fd0 | 8185 | finish_cmd(c); |
433b5f4d | 8186 | atomic_dec(&h->commands_outstanding); |
25163bd5 | 8187 | failcount++; |
281a7fd0 WS |
8188 | } |
8189 | cmd_free(h, c); | |
a0c12413 | 8190 | } |
25163bd5 WS |
8191 | dev_warn(&h->pdev->dev, |
8192 | "failed %d commands in fail_all\n", failcount); | |
a0c12413 SC |
8193 | } |
8194 | ||
094963da SC |
8195 | static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) |
8196 | { | |
c8ed0010 | 8197 | int cpu; |
094963da | 8198 | |
c8ed0010 | 8199 | for_each_online_cpu(cpu) { |
094963da SC |
8200 | u32 *lockup_detected; |
8201 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
8202 | *lockup_detected = value; | |
094963da SC |
8203 | } |
8204 | wmb(); /* be sure the per-cpu variables are out to memory */ | |
8205 | } | |
8206 | ||
a0c12413 SC |
8207 | static void controller_lockup_detected(struct ctlr_info *h) |
8208 | { | |
8209 | unsigned long flags; | |
094963da | 8210 | u32 lockup_detected; |
a0c12413 | 8211 | |
a0c12413 SC |
8212 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
8213 | spin_lock_irqsave(&h->lock, flags); | |
094963da SC |
8214 | lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
8215 | if (!lockup_detected) { | |
8216 | /* no heartbeat, but controller gave us a zero. */ | |
8217 | dev_warn(&h->pdev->dev, | |
25163bd5 WS |
8218 | "lockup detected after %d but scratchpad register is zero\n", |
8219 | h->heartbeat_sample_interval / HZ); | |
094963da SC |
8220 | lockup_detected = 0xffffffff; |
8221 | } | |
8222 | set_lockup_detected_for_all_cpus(h, lockup_detected); | |
a0c12413 | 8223 | spin_unlock_irqrestore(&h->lock, flags); |
25163bd5 WS |
8224 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", |
8225 | lockup_detected, h->heartbeat_sample_interval / HZ); | |
a0c12413 | 8226 | pci_disable_device(h->pdev); |
f2405db8 | 8227 | fail_all_outstanding_cmds(h); |
a0c12413 SC |
8228 | } |
8229 | ||
25163bd5 | 8230 | static int detect_controller_lockup(struct ctlr_info *h) |
a0c12413 SC |
8231 | { |
8232 | u64 now; | |
8233 | u32 heartbeat; | |
8234 | unsigned long flags; | |
8235 | ||
a0c12413 SC |
8236 | now = get_jiffies_64(); |
8237 | /* If we've received an interrupt recently, we're ok. */ | |
8238 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 8239 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8240 | return false; |
a0c12413 SC |
8241 | |
8242 | /* | |
8243 | * If we've already checked the heartbeat recently, we're ok. | |
8244 | * This could happen if someone sends us a signal. We | |
8245 | * otherwise don't care about signals in this thread. | |
8246 | */ | |
8247 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 8248 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8249 | return false; |
a0c12413 SC |
8250 | |
8251 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
8252 | spin_lock_irqsave(&h->lock, flags); | |
8253 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
8254 | spin_unlock_irqrestore(&h->lock, flags); | |
8255 | if (h->last_heartbeat == heartbeat) { | |
8256 | controller_lockup_detected(h); | |
25163bd5 | 8257 | return true; |
a0c12413 SC |
8258 | } |
8259 | ||
8260 | /* We're ok. */ | |
8261 | h->last_heartbeat = heartbeat; | |
8262 | h->last_heartbeat_timestamp = now; | |
25163bd5 | 8263 | return false; |
a0c12413 SC |
8264 | } |
8265 | ||
9846590e | 8266 | static void hpsa_ack_ctlr_events(struct ctlr_info *h) |
76438d08 SC |
8267 | { |
8268 | int i; | |
8269 | char *event_type; | |
8270 | ||
e4aa3e6a SC |
8271 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
8272 | return; | |
8273 | ||
76438d08 | 8274 | /* Ask the controller to clear the events we're handling. */ |
1f7cee8c SC |
8275 | if ((h->transMethod & (CFGTBL_Trans_io_accel1 |
8276 | | CFGTBL_Trans_io_accel2)) && | |
76438d08 SC |
8277 | (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || |
8278 | h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { | |
8279 | ||
8280 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) | |
8281 | event_type = "state change"; | |
8282 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) | |
8283 | event_type = "configuration change"; | |
8284 | /* Stop sending new RAID offload reqs via the IO accelerator */ | |
8285 | scsi_block_requests(h->scsi_host); | |
8286 | for (i = 0; i < h->ndevices; i++) | |
8287 | h->dev[i]->offload_enabled = 0; | |
23100dd9 | 8288 | hpsa_drain_accel_commands(h); |
76438d08 SC |
8289 | /* Set 'accelerator path config change' bit */ |
8290 | dev_warn(&h->pdev->dev, | |
8291 | "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", | |
8292 | h->events, event_type); | |
8293 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8294 | /* Set the "clear event notify field update" bit 6 */ | |
8295 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8296 | /* Wait until ctlr clears 'clear event notify field', bit 6 */ | |
8297 | hpsa_wait_for_clear_event_notify_ack(h); | |
8298 | scsi_unblock_requests(h->scsi_host); | |
8299 | } else { | |
8300 | /* Acknowledge controller notification events. */ | |
8301 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8302 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8303 | hpsa_wait_for_clear_event_notify_ack(h); | |
8304 | #if 0 | |
8305 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); | |
8306 | hpsa_wait_for_mode_change_ack(h); | |
8307 | #endif | |
8308 | } | |
9846590e | 8309 | return; |
76438d08 SC |
8310 | } |
8311 | ||
8312 | /* Check a register on the controller to see if there are configuration | |
8313 | * changes (added/changed/removed logical drives, etc.) which mean that | |
e863d68e ST |
8314 | * we should rescan the controller for devices. |
8315 | * Also check flag for driver-initiated rescan. | |
76438d08 | 8316 | */ |
9846590e | 8317 | static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) |
76438d08 | 8318 | { |
853633e8 DB |
8319 | if (h->drv_req_rescan) { |
8320 | h->drv_req_rescan = 0; | |
8321 | return 1; | |
8322 | } | |
8323 | ||
76438d08 | 8324 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
9846590e | 8325 | return 0; |
76438d08 SC |
8326 | |
8327 | h->events = readl(&(h->cfgtable->event_notify)); | |
9846590e SC |
8328 | return h->events & RESCAN_REQUIRED_EVENT_BITS; |
8329 | } | |
76438d08 | 8330 | |
9846590e SC |
8331 | /* |
8332 | * Check if any of the offline devices have become ready | |
8333 | */ | |
8334 | static int hpsa_offline_devices_ready(struct ctlr_info *h) | |
8335 | { | |
8336 | unsigned long flags; | |
8337 | struct offline_device_entry *d; | |
8338 | struct list_head *this, *tmp; | |
8339 | ||
8340 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8341 | list_for_each_safe(this, tmp, &h->offline_device_list) { | |
8342 | d = list_entry(this, struct offline_device_entry, | |
8343 | offline_list); | |
8344 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
d1fea47c SC |
8345 | if (!hpsa_volume_offline(h, d->scsi3addr)) { |
8346 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8347 | list_del(&d->offline_list); | |
8348 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
9846590e | 8349 | return 1; |
d1fea47c | 8350 | } |
9846590e SC |
8351 | spin_lock_irqsave(&h->offline_device_lock, flags); |
8352 | } | |
8353 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
8354 | return 0; | |
76438d08 SC |
8355 | } |
8356 | ||
34592254 ST |
8357 | static int hpsa_luns_changed(struct ctlr_info *h) |
8358 | { | |
8359 | int rc = 1; /* assume there are changes */ | |
8360 | struct ReportLUNdata *logdev = NULL; | |
8361 | ||
8362 | /* if we can't find out if lun data has changed, | |
8363 | * assume that it has. | |
8364 | */ | |
8365 | ||
8366 | if (!h->lastlogicals) | |
8367 | goto out; | |
8368 | ||
8369 | logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); | |
8370 | if (!logdev) { | |
8371 | dev_warn(&h->pdev->dev, | |
8372 | "Out of memory, can't track lun changes.\n"); | |
8373 | goto out; | |
8374 | } | |
8375 | if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { | |
8376 | dev_warn(&h->pdev->dev, | |
8377 | "report luns failed, can't track lun changes.\n"); | |
8378 | goto out; | |
8379 | } | |
8380 | if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { | |
8381 | dev_info(&h->pdev->dev, | |
8382 | "Lun changes detected.\n"); | |
8383 | memcpy(h->lastlogicals, logdev, sizeof(*logdev)); | |
8384 | goto out; | |
8385 | } else | |
8386 | rc = 0; /* no changes detected. */ | |
8387 | out: | |
8388 | kfree(logdev); | |
8389 | return rc; | |
8390 | } | |
8391 | ||
6636e7f4 | 8392 | static void hpsa_rescan_ctlr_worker(struct work_struct *work) |
a0c12413 SC |
8393 | { |
8394 | unsigned long flags; | |
8a98db73 | 8395 | struct ctlr_info *h = container_of(to_delayed_work(work), |
6636e7f4 DB |
8396 | struct ctlr_info, rescan_ctlr_work); |
8397 | ||
8398 | ||
8399 | if (h->remove_in_progress) | |
8a98db73 | 8400 | return; |
9846590e SC |
8401 | |
8402 | if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) { | |
8403 | scsi_host_get(h->scsi_host); | |
9846590e SC |
8404 | hpsa_ack_ctlr_events(h); |
8405 | hpsa_scan_start(h->scsi_host); | |
8406 | scsi_host_put(h->scsi_host); | |
34592254 | 8407 | } else if (h->discovery_polling) { |
c2adae44 | 8408 | hpsa_disable_rld_caching(h); |
34592254 ST |
8409 | if (hpsa_luns_changed(h)) { |
8410 | struct Scsi_Host *sh = NULL; | |
8411 | ||
8412 | dev_info(&h->pdev->dev, | |
8413 | "driver discovery polling rescan.\n"); | |
8414 | sh = scsi_host_get(h->scsi_host); | |
8415 | if (sh != NULL) { | |
8416 | hpsa_scan_start(sh); | |
8417 | scsi_host_put(sh); | |
8418 | } | |
8419 | } | |
9846590e | 8420 | } |
8a98db73 | 8421 | spin_lock_irqsave(&h->lock, flags); |
6636e7f4 DB |
8422 | if (!h->remove_in_progress) |
8423 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8424 | h->heartbeat_sample_interval); | |
8425 | spin_unlock_irqrestore(&h->lock, flags); | |
8426 | } | |
8427 | ||
8428 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) | |
8429 | { | |
8430 | unsigned long flags; | |
8431 | struct ctlr_info *h = container_of(to_delayed_work(work), | |
8432 | struct ctlr_info, monitor_ctlr_work); | |
8433 | ||
8434 | detect_controller_lockup(h); | |
8435 | if (lockup_detected(h)) | |
a0c12413 | 8436 | return; |
6636e7f4 DB |
8437 | |
8438 | spin_lock_irqsave(&h->lock, flags); | |
8439 | if (!h->remove_in_progress) | |
8440 | schedule_delayed_work(&h->monitor_ctlr_work, | |
8a98db73 SC |
8441 | h->heartbeat_sample_interval); |
8442 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
8443 | } |
8444 | ||
6636e7f4 DB |
8445 | static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, |
8446 | char *name) | |
8447 | { | |
8448 | struct workqueue_struct *wq = NULL; | |
6636e7f4 | 8449 | |
397ea9cb | 8450 | wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); |
6636e7f4 DB |
8451 | if (!wq) |
8452 | dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); | |
8453 | ||
8454 | return wq; | |
8455 | } | |
8456 | ||
6f039790 | 8457 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 8458 | { |
4c2a8c40 | 8459 | int dac, rc; |
edd16368 | 8460 | struct ctlr_info *h; |
64670ac8 SC |
8461 | int try_soft_reset = 0; |
8462 | unsigned long flags; | |
6b6c1cd7 | 8463 | u32 board_id; |
edd16368 SC |
8464 | |
8465 | if (number_of_controllers == 0) | |
8466 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 8467 | |
6b6c1cd7 TH |
8468 | rc = hpsa_lookup_board_id(pdev, &board_id); |
8469 | if (rc < 0) { | |
8470 | dev_warn(&pdev->dev, "Board ID not found\n"); | |
8471 | return rc; | |
8472 | } | |
8473 | ||
8474 | rc = hpsa_init_reset_devices(pdev, board_id); | |
64670ac8 SC |
8475 | if (rc) { |
8476 | if (rc != -ENOTSUPP) | |
8477 | return rc; | |
8478 | /* If the reset fails in a particular way (it has no way to do | |
8479 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
8480 | * a soft reset once we get the controller configured up to the | |
8481 | * point that it can accept a command. | |
8482 | */ | |
8483 | try_soft_reset = 1; | |
8484 | rc = 0; | |
8485 | } | |
8486 | ||
8487 | reinit_after_soft_reset: | |
edd16368 | 8488 | |
303932fd DB |
8489 | /* Command structures must be aligned on a 32-byte boundary because |
8490 | * the 5 lower bits of the address are used by the hardware. and by | |
8491 | * the driver. See comments in hpsa.h for more info. | |
8492 | */ | |
303932fd | 8493 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); |
edd16368 | 8494 | h = kzalloc(sizeof(*h), GFP_KERNEL); |
105a3dbc RE |
8495 | if (!h) { |
8496 | dev_err(&pdev->dev, "Failed to allocate controller head\n"); | |
ecd9aad4 | 8497 | return -ENOMEM; |
105a3dbc | 8498 | } |
edd16368 | 8499 | |
55c06c71 | 8500 | h->pdev = pdev; |
105a3dbc | 8501 | |
a9a3a273 | 8502 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9846590e | 8503 | INIT_LIST_HEAD(&h->offline_device_list); |
6eaf46fd | 8504 | spin_lock_init(&h->lock); |
9846590e | 8505 | spin_lock_init(&h->offline_device_lock); |
6eaf46fd | 8506 | spin_lock_init(&h->scan_lock); |
34f0c627 | 8507 | atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); |
9b5c48c2 | 8508 | atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS); |
094963da SC |
8509 | |
8510 | /* Allocate and clear per-cpu variable lockup_detected */ | |
8511 | h->lockup_detected = alloc_percpu(u32); | |
2a5ac326 | 8512 | if (!h->lockup_detected) { |
105a3dbc | 8513 | dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); |
2a5ac326 | 8514 | rc = -ENOMEM; |
2efa5929 | 8515 | goto clean1; /* aer/h */ |
2a5ac326 | 8516 | } |
094963da SC |
8517 | set_lockup_detected_for_all_cpus(h, 0); |
8518 | ||
55c06c71 | 8519 | rc = hpsa_pci_init(h); |
105a3dbc | 8520 | if (rc) |
2946e82b RE |
8521 | goto clean2; /* lu, aer/h */ |
8522 | ||
8523 | /* relies on h-> settings made by hpsa_pci_init, including | |
8524 | * interrupt_mode h->intr */ | |
8525 | rc = hpsa_scsi_host_alloc(h); | |
8526 | if (rc) | |
8527 | goto clean2_5; /* pci, lu, aer/h */ | |
edd16368 | 8528 | |
2946e82b | 8529 | sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); |
edd16368 SC |
8530 | h->ctlr = number_of_controllers; |
8531 | number_of_controllers++; | |
edd16368 SC |
8532 | |
8533 | /* configure PCI DMA stuff */ | |
ecd9aad4 SC |
8534 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
8535 | if (rc == 0) { | |
edd16368 | 8536 | dac = 1; |
ecd9aad4 SC |
8537 | } else { |
8538 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
8539 | if (rc == 0) { | |
8540 | dac = 0; | |
8541 | } else { | |
8542 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
2946e82b | 8543 | goto clean3; /* shost, pci, lu, aer/h */ |
ecd9aad4 | 8544 | } |
edd16368 SC |
8545 | } |
8546 | ||
8547 | /* make sure the board interrupts are off */ | |
8548 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 8549 | |
105a3dbc RE |
8550 | rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); |
8551 | if (rc) | |
2946e82b | 8552 | goto clean3; /* shost, pci, lu, aer/h */ |
d37ffbe4 | 8553 | rc = hpsa_alloc_cmd_pool(h); |
8947fd10 | 8554 | if (rc) |
2946e82b | 8555 | goto clean4; /* irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8556 | rc = hpsa_alloc_sg_chain_blocks(h); |
8557 | if (rc) | |
2946e82b | 8558 | goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ |
a08a8471 | 8559 | init_waitqueue_head(&h->scan_wait_queue); |
9b5c48c2 | 8560 | init_waitqueue_head(&h->abort_cmd_wait_queue); |
d604f533 WS |
8561 | init_waitqueue_head(&h->event_sync_wait_queue); |
8562 | mutex_init(&h->reset_mutex); | |
a08a8471 | 8563 | h->scan_finished = 1; /* no scan currently in progress */ |
edd16368 SC |
8564 | |
8565 | pci_set_drvdata(pdev, h); | |
9a41338e | 8566 | h->ndevices = 0; |
2946e82b | 8567 | |
9a41338e | 8568 | spin_lock_init(&h->devlock); |
105a3dbc RE |
8569 | rc = hpsa_put_ctlr_into_performant_mode(h); |
8570 | if (rc) | |
2946e82b RE |
8571 | goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ |
8572 | ||
2efa5929 RE |
8573 | /* create the resubmit workqueue */ |
8574 | h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); | |
8575 | if (!h->rescan_ctlr_wq) { | |
8576 | rc = -ENOMEM; | |
8577 | goto clean7; | |
8578 | } | |
8579 | ||
8580 | h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); | |
8581 | if (!h->resubmit_wq) { | |
8582 | rc = -ENOMEM; | |
8583 | goto clean7; /* aer/h */ | |
8584 | } | |
64670ac8 | 8585 | |
105a3dbc RE |
8586 | /* |
8587 | * At this point, the controller is ready to take commands. | |
64670ac8 SC |
8588 | * Now, if reset_devices and the hard reset didn't work, try |
8589 | * the soft reset and see if that works. | |
8590 | */ | |
8591 | if (try_soft_reset) { | |
8592 | ||
8593 | /* This is kind of gross. We may or may not get a completion | |
8594 | * from the soft reset command, and if we do, then the value | |
8595 | * from the fifo may or may not be valid. So, we wait 10 secs | |
8596 | * after the reset throwing away any completions we get during | |
8597 | * that time. Unregister the interrupt handler and register | |
8598 | * fake ones to scoop up any residual completions. | |
8599 | */ | |
8600 | spin_lock_irqsave(&h->lock, flags); | |
8601 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8602 | spin_unlock_irqrestore(&h->lock, flags); | |
ec501a18 | 8603 | hpsa_free_irqs(h); |
9ee61794 | 8604 | rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, |
64670ac8 SC |
8605 | hpsa_intx_discard_completions); |
8606 | if (rc) { | |
9ee61794 RE |
8607 | dev_warn(&h->pdev->dev, |
8608 | "Failed to request_irq after soft reset.\n"); | |
d498757c | 8609 | /* |
b2ef480c RE |
8610 | * cannot goto clean7 or free_irqs will be called |
8611 | * again. Instead, do its work | |
8612 | */ | |
8613 | hpsa_free_performant_mode(h); /* clean7 */ | |
8614 | hpsa_free_sg_chain_blocks(h); /* clean6 */ | |
8615 | hpsa_free_cmd_pool(h); /* clean5 */ | |
8616 | /* | |
8617 | * skip hpsa_free_irqs(h) clean4 since that | |
8618 | * was just called before request_irqs failed | |
d498757c RE |
8619 | */ |
8620 | goto clean3; | |
64670ac8 SC |
8621 | } |
8622 | ||
8623 | rc = hpsa_kdump_soft_reset(h); | |
8624 | if (rc) | |
8625 | /* Neither hard nor soft reset worked, we're hosed. */ | |
7ef7323f | 8626 | goto clean7; |
64670ac8 SC |
8627 | |
8628 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
8629 | dev_info(&h->pdev->dev, | |
8630 | "Waiting for stale completions to drain.\n"); | |
8631 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8632 | msleep(10000); | |
8633 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8634 | ||
8635 | rc = controller_reset_failed(h->cfgtable); | |
8636 | if (rc) | |
8637 | dev_info(&h->pdev->dev, | |
8638 | "Soft reset appears to have failed.\n"); | |
8639 | ||
8640 | /* since the controller's reset, we have to go back and re-init | |
8641 | * everything. Easiest to just forget what we've done and do it | |
8642 | * all over again. | |
8643 | */ | |
8644 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
8645 | try_soft_reset = 0; | |
8646 | if (rc) | |
b2ef480c | 8647 | /* don't goto clean, we already unallocated */ |
64670ac8 SC |
8648 | return -ENODEV; |
8649 | ||
8650 | goto reinit_after_soft_reset; | |
8651 | } | |
edd16368 | 8652 | |
105a3dbc RE |
8653 | /* Enable Accelerated IO path at driver layer */ |
8654 | h->acciopath_status = 1; | |
34592254 ST |
8655 | /* Disable discovery polling.*/ |
8656 | h->discovery_polling = 0; | |
da0697bd | 8657 | |
e863d68e | 8658 | |
edd16368 SC |
8659 | /* Turn the interrupts on so we can service requests */ |
8660 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8661 | ||
339b2b14 | 8662 | hpsa_hba_inquiry(h); |
8a98db73 | 8663 | |
34592254 ST |
8664 | h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); |
8665 | if (!h->lastlogicals) | |
8666 | dev_info(&h->pdev->dev, | |
8667 | "Can't track change to report lun data\n"); | |
8668 | ||
cf477237 DB |
8669 | /* hook into SCSI subsystem */ |
8670 | rc = hpsa_scsi_add_host(h); | |
8671 | if (rc) | |
8672 | goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ | |
8673 | ||
8a98db73 SC |
8674 | /* Monitor the controller for firmware lockups */ |
8675 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
8676 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
8677 | schedule_delayed_work(&h->monitor_ctlr_work, | |
8678 | h->heartbeat_sample_interval); | |
6636e7f4 DB |
8679 | INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); |
8680 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8681 | h->heartbeat_sample_interval); | |
88bf6d62 | 8682 | return 0; |
edd16368 | 8683 | |
2946e82b | 8684 | clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8685 | hpsa_free_performant_mode(h); |
8686 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8687 | clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ | |
33a2ffce | 8688 | hpsa_free_sg_chain_blocks(h); |
2946e82b | 8689 | clean5: /* cmd, irq, shost, pci, lu, aer/h */ |
2e9d1b36 | 8690 | hpsa_free_cmd_pool(h); |
2946e82b | 8691 | clean4: /* irq, shost, pci, lu, aer/h */ |
ec501a18 | 8692 | hpsa_free_irqs(h); |
2946e82b RE |
8693 | clean3: /* shost, pci, lu, aer/h */ |
8694 | scsi_host_put(h->scsi_host); | |
8695 | h->scsi_host = NULL; | |
8696 | clean2_5: /* pci, lu, aer/h */ | |
195f2c65 | 8697 | hpsa_free_pci_init(h); |
2946e82b | 8698 | clean2: /* lu, aer/h */ |
105a3dbc RE |
8699 | if (h->lockup_detected) { |
8700 | free_percpu(h->lockup_detected); | |
8701 | h->lockup_detected = NULL; | |
8702 | } | |
8703 | clean1: /* wq/aer/h */ | |
8704 | if (h->resubmit_wq) { | |
080ef1cc | 8705 | destroy_workqueue(h->resubmit_wq); |
105a3dbc RE |
8706 | h->resubmit_wq = NULL; |
8707 | } | |
8708 | if (h->rescan_ctlr_wq) { | |
6636e7f4 | 8709 | destroy_workqueue(h->rescan_ctlr_wq); |
105a3dbc RE |
8710 | h->rescan_ctlr_wq = NULL; |
8711 | } | |
edd16368 | 8712 | kfree(h); |
ecd9aad4 | 8713 | return rc; |
edd16368 SC |
8714 | } |
8715 | ||
8716 | static void hpsa_flush_cache(struct ctlr_info *h) | |
8717 | { | |
8718 | char *flush_buf; | |
8719 | struct CommandList *c; | |
25163bd5 | 8720 | int rc; |
702890e3 | 8721 | |
094963da | 8722 | if (unlikely(lockup_detected(h))) |
702890e3 | 8723 | return; |
edd16368 SC |
8724 | flush_buf = kzalloc(4, GFP_KERNEL); |
8725 | if (!flush_buf) | |
8726 | return; | |
8727 | ||
45fcb86e | 8728 | c = cmd_alloc(h); |
bf43caf3 | 8729 | |
a2dac136 SC |
8730 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
8731 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
8732 | goto out; | |
8733 | } | |
25163bd5 | 8734 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, |
c448ecfa | 8735 | PCI_DMA_TODEVICE, DEFAULT_TIMEOUT); |
25163bd5 WS |
8736 | if (rc) |
8737 | goto out; | |
edd16368 | 8738 | if (c->err_info->CommandStatus != 0) |
a2dac136 | 8739 | out: |
edd16368 SC |
8740 | dev_warn(&h->pdev->dev, |
8741 | "error flushing cache on controller\n"); | |
45fcb86e | 8742 | cmd_free(h, c); |
edd16368 SC |
8743 | kfree(flush_buf); |
8744 | } | |
8745 | ||
c2adae44 ST |
8746 | /* Make controller gather fresh report lun data each time we |
8747 | * send down a report luns request | |
8748 | */ | |
8749 | static void hpsa_disable_rld_caching(struct ctlr_info *h) | |
8750 | { | |
8751 | u32 *options; | |
8752 | struct CommandList *c; | |
8753 | int rc; | |
8754 | ||
8755 | /* Don't bother trying to set diag options if locked up */ | |
8756 | if (unlikely(h->lockup_detected)) | |
8757 | return; | |
8758 | ||
8759 | options = kzalloc(sizeof(*options), GFP_KERNEL); | |
8760 | if (!options) { | |
8761 | dev_err(&h->pdev->dev, | |
8762 | "Error: failed to disable rld caching, during alloc.\n"); | |
8763 | return; | |
8764 | } | |
8765 | ||
8766 | c = cmd_alloc(h); | |
8767 | ||
8768 | /* first, get the current diag options settings */ | |
8769 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8770 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8771 | goto errout; | |
8772 | ||
8773 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
c448ecfa | 8774 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
c2adae44 ST |
8775 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8776 | goto errout; | |
8777 | ||
8778 | /* Now, set the bit for disabling the RLD caching */ | |
8779 | *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; | |
8780 | ||
8781 | if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, | |
8782 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8783 | goto errout; | |
8784 | ||
8785 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
c448ecfa | 8786 | PCI_DMA_TODEVICE, DEFAULT_TIMEOUT); |
c2adae44 ST |
8787 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8788 | goto errout; | |
8789 | ||
8790 | /* Now verify that it got set: */ | |
8791 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8792 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8793 | goto errout; | |
8794 | ||
8795 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, | |
c448ecfa | 8796 | PCI_DMA_FROMDEVICE, DEFAULT_TIMEOUT); |
c2adae44 ST |
8797 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8798 | goto errout; | |
8799 | ||
d8a080c3 | 8800 | if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) |
c2adae44 ST |
8801 | goto out; |
8802 | ||
8803 | errout: | |
8804 | dev_err(&h->pdev->dev, | |
8805 | "Error: failed to disable report lun data caching.\n"); | |
8806 | out: | |
8807 | cmd_free(h, c); | |
8808 | kfree(options); | |
8809 | } | |
8810 | ||
edd16368 SC |
8811 | static void hpsa_shutdown(struct pci_dev *pdev) |
8812 | { | |
8813 | struct ctlr_info *h; | |
8814 | ||
8815 | h = pci_get_drvdata(pdev); | |
8816 | /* Turn board interrupts off and send the flush cache command | |
8817 | * sendcmd will turn off interrupt, and send the flush... | |
8818 | * To write all data in the battery backed cache to disks | |
8819 | */ | |
8820 | hpsa_flush_cache(h); | |
8821 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
105a3dbc | 8822 | hpsa_free_irqs(h); /* init_one 4 */ |
cc64c817 | 8823 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
edd16368 SC |
8824 | } |
8825 | ||
6f039790 | 8826 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
8827 | { |
8828 | int i; | |
8829 | ||
105a3dbc | 8830 | for (i = 0; i < h->ndevices; i++) { |
55e14e76 | 8831 | kfree(h->dev[i]); |
105a3dbc RE |
8832 | h->dev[i] = NULL; |
8833 | } | |
55e14e76 SC |
8834 | } |
8835 | ||
6f039790 | 8836 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
8837 | { |
8838 | struct ctlr_info *h; | |
8a98db73 | 8839 | unsigned long flags; |
edd16368 SC |
8840 | |
8841 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 8842 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
8843 | return; |
8844 | } | |
8845 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
8846 | |
8847 | /* Get rid of any controller monitoring work items */ | |
8848 | spin_lock_irqsave(&h->lock, flags); | |
8849 | h->remove_in_progress = 1; | |
8a98db73 | 8850 | spin_unlock_irqrestore(&h->lock, flags); |
6636e7f4 DB |
8851 | cancel_delayed_work_sync(&h->monitor_ctlr_work); |
8852 | cancel_delayed_work_sync(&h->rescan_ctlr_work); | |
8853 | destroy_workqueue(h->rescan_ctlr_wq); | |
8854 | destroy_workqueue(h->resubmit_wq); | |
cc64c817 | 8855 | |
2d041306 DB |
8856 | /* |
8857 | * Call before disabling interrupts. | |
8858 | * scsi_remove_host can trigger I/O operations especially | |
8859 | * when multipath is enabled. There can be SYNCHRONIZE CACHE | |
8860 | * operations which cannot complete and will hang the system. | |
8861 | */ | |
8862 | if (h->scsi_host) | |
8863 | scsi_remove_host(h->scsi_host); /* init_one 8 */ | |
105a3dbc | 8864 | /* includes hpsa_free_irqs - init_one 4 */ |
195f2c65 | 8865 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
edd16368 | 8866 | hpsa_shutdown(pdev); |
cc64c817 | 8867 | |
105a3dbc RE |
8868 | hpsa_free_device_info(h); /* scan */ |
8869 | ||
2946e82b RE |
8870 | kfree(h->hba_inquiry_data); /* init_one 10 */ |
8871 | h->hba_inquiry_data = NULL; /* init_one 10 */ | |
2946e82b | 8872 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
105a3dbc RE |
8873 | hpsa_free_performant_mode(h); /* init_one 7 */ |
8874 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
8875 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
34592254 | 8876 | kfree(h->lastlogicals); |
105a3dbc RE |
8877 | |
8878 | /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ | |
195f2c65 | 8879 | |
2946e82b RE |
8880 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
8881 | h->scsi_host = NULL; /* init_one 3 */ | |
8882 | ||
195f2c65 | 8883 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
2946e82b | 8884 | hpsa_free_pci_init(h); /* init_one 2.5 */ |
195f2c65 | 8885 | |
105a3dbc RE |
8886 | free_percpu(h->lockup_detected); /* init_one 2 */ |
8887 | h->lockup_detected = NULL; /* init_one 2 */ | |
8888 | /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ | |
d04e62b9 KB |
8889 | |
8890 | hpsa_delete_sas_host(h); | |
8891 | ||
105a3dbc | 8892 | kfree(h); /* init_one 1 */ |
edd16368 SC |
8893 | } |
8894 | ||
8895 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
8896 | __attribute__((unused)) pm_message_t state) | |
8897 | { | |
8898 | return -ENOSYS; | |
8899 | } | |
8900 | ||
8901 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
8902 | { | |
8903 | return -ENOSYS; | |
8904 | } | |
8905 | ||
8906 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 8907 | .name = HPSA, |
edd16368 | 8908 | .probe = hpsa_init_one, |
6f039790 | 8909 | .remove = hpsa_remove_one, |
edd16368 SC |
8910 | .id_table = hpsa_pci_device_id, /* id_table */ |
8911 | .shutdown = hpsa_shutdown, | |
8912 | .suspend = hpsa_suspend, | |
8913 | .resume = hpsa_resume, | |
8914 | }; | |
8915 | ||
303932fd DB |
8916 | /* Fill in bucket_map[], given nsgs (the max number of |
8917 | * scatter gather elements supported) and bucket[], | |
8918 | * which is an array of 8 integers. The bucket[] array | |
8919 | * contains 8 different DMA transfer sizes (in 16 | |
8920 | * byte increments) which the controller uses to fetch | |
8921 | * commands. This function fills in bucket_map[], which | |
8922 | * maps a given number of scatter gather elements to one of | |
8923 | * the 8 DMA transfer sizes. The point of it is to allow the | |
8924 | * controller to only do as much DMA as needed to fetch the | |
8925 | * command, with the DMA transfer size encoded in the lower | |
8926 | * bits of the command address. | |
8927 | */ | |
8928 | static void calc_bucket_map(int bucket[], int num_buckets, | |
2b08b3e9 | 8929 | int nsgs, int min_blocks, u32 *bucket_map) |
303932fd DB |
8930 | { |
8931 | int i, j, b, size; | |
8932 | ||
303932fd DB |
8933 | /* Note, bucket_map must have nsgs+1 entries. */ |
8934 | for (i = 0; i <= nsgs; i++) { | |
8935 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 8936 | size = i + min_blocks; |
303932fd DB |
8937 | b = num_buckets; /* Assume the biggest bucket */ |
8938 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 8939 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
8940 | if (bucket[j] >= size) { |
8941 | b = j; | |
8942 | break; | |
8943 | } | |
8944 | } | |
8945 | /* for a command with i SG entries, use bucket b. */ | |
8946 | bucket_map[i] = b; | |
8947 | } | |
8948 | } | |
8949 | ||
105a3dbc RE |
8950 | /* |
8951 | * return -ENODEV on err, 0 on success (or no action) | |
8952 | * allocates numerous items that must be freed later | |
8953 | */ | |
c706a795 | 8954 | static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 8955 | { |
6c311b57 SC |
8956 | int i; |
8957 | unsigned long register_value; | |
e1f7de0c MG |
8958 | unsigned long transMethod = CFGTBL_Trans_Performant | |
8959 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
b9af4937 SC |
8960 | CFGTBL_Trans_enable_directed_msix | |
8961 | (trans_support & (CFGTBL_Trans_io_accel1 | | |
8962 | CFGTBL_Trans_io_accel2)); | |
e1f7de0c | 8963 | struct access_method access = SA5_performant_access; |
def342bd SC |
8964 | |
8965 | /* This is a bit complicated. There are 8 registers on | |
8966 | * the controller which we write to to tell it 8 different | |
8967 | * sizes of commands which there may be. It's a way of | |
8968 | * reducing the DMA done to fetch each command. Encoded into | |
8969 | * each command's tag are 3 bits which communicate to the controller | |
8970 | * which of the eight sizes that command fits within. The size of | |
8971 | * each command depends on how many scatter gather entries there are. | |
8972 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
8973 | * with the number of 16-byte blocks a command of that size requires. | |
8974 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 8975 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
8976 | * blocks. Note, this only extends to the SG entries contained |
8977 | * within the command block, and does not extend to chained blocks | |
8978 | * of SG elements. bft[] contains the eight values we write to | |
8979 | * the registers. They are not evenly distributed, but have more | |
8980 | * sizes for small commands, and fewer sizes for larger commands. | |
8981 | */ | |
d66ae08b | 8982 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
b9af4937 SC |
8983 | #define MIN_IOACCEL2_BFT_ENTRY 5 |
8984 | #define HPSA_IOACCEL2_HEADER_SZ 4 | |
8985 | int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, | |
8986 | 13, 14, 15, 16, 17, 18, 19, | |
8987 | HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; | |
8988 | BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); | |
8989 | BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); | |
8990 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > | |
8991 | 16 * MIN_IOACCEL2_BFT_ENTRY); | |
8992 | BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); | |
d66ae08b | 8993 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); |
303932fd DB |
8994 | /* 5 = 1 s/g entry or 4k |
8995 | * 6 = 2 s/g entry or 8k | |
8996 | * 8 = 4 s/g entry or 16k | |
8997 | * 10 = 6 s/g entry or 24k | |
8998 | */ | |
303932fd | 8999 | |
b3a52e79 SC |
9000 | /* If the controller supports either ioaccel method then |
9001 | * we can also use the RAID stack submit path that does not | |
9002 | * perform the superfluous readl() after each command submission. | |
9003 | */ | |
9004 | if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) | |
9005 | access = SA5_performant_access_no_read; | |
9006 | ||
303932fd | 9007 | /* Controller spec: zero out this buffer. */ |
072b0518 SC |
9008 | for (i = 0; i < h->nreply_queues; i++) |
9009 | memset(h->reply_queue[i].head, 0, h->reply_queue_size); | |
303932fd | 9010 | |
d66ae08b SC |
9011 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
9012 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 9013 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
9014 | for (i = 0; i < 8; i++) |
9015 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
9016 | ||
9017 | /* size of controller ring buffer */ | |
9018 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 9019 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
9020 | writel(0, &h->transtable->RepQCtrAddrLow32); |
9021 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
9022 | |
9023 | for (i = 0; i < h->nreply_queues; i++) { | |
9024 | writel(0, &h->transtable->RepQAddr[i].upper); | |
072b0518 | 9025 | writel(h->reply_queue[i].busaddr, |
254f796b MG |
9026 | &h->transtable->RepQAddr[i].lower); |
9027 | } | |
9028 | ||
b9af4937 | 9029 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
e1f7de0c MG |
9030 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
9031 | /* | |
9032 | * enable outbound interrupt coalescing in accelerator mode; | |
9033 | */ | |
9034 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
9035 | access = SA5_ioaccel_mode1_access; | |
9036 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
9037 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
c349775e ST |
9038 | } else { |
9039 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
9040 | access = SA5_ioaccel_mode2_access; | |
9041 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
9042 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
9043 | } | |
e1f7de0c | 9044 | } |
303932fd | 9045 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
9046 | if (hpsa_wait_for_mode_change_ack(h)) { |
9047 | dev_err(&h->pdev->dev, | |
9048 | "performant mode problem - doorbell timeout\n"); | |
9049 | return -ENODEV; | |
9050 | } | |
303932fd DB |
9051 | register_value = readl(&(h->cfgtable->TransportActive)); |
9052 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
050f7147 SC |
9053 | dev_err(&h->pdev->dev, |
9054 | "performant mode problem - transport not active\n"); | |
c706a795 | 9055 | return -ENODEV; |
303932fd | 9056 | } |
960a30e7 | 9057 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
9058 | h->access = access; |
9059 | h->transMethod = transMethod; | |
9060 | ||
b9af4937 SC |
9061 | if (!((trans_support & CFGTBL_Trans_io_accel1) || |
9062 | (trans_support & CFGTBL_Trans_io_accel2))) | |
c706a795 | 9063 | return 0; |
e1f7de0c | 9064 | |
b9af4937 SC |
9065 | if (trans_support & CFGTBL_Trans_io_accel1) { |
9066 | /* Set up I/O accelerator mode */ | |
9067 | for (i = 0; i < h->nreply_queues; i++) { | |
9068 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
9069 | h->reply_queue[i].current_entry = | |
9070 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
9071 | } | |
9072 | bft[7] = h->ioaccel_maxsg + 8; | |
9073 | calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, | |
9074 | h->ioaccel1_blockFetchTable); | |
e1f7de0c | 9075 | |
b9af4937 | 9076 | /* initialize all reply queue entries to unused */ |
072b0518 SC |
9077 | for (i = 0; i < h->nreply_queues; i++) |
9078 | memset(h->reply_queue[i].head, | |
9079 | (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
9080 | h->reply_queue_size); | |
e1f7de0c | 9081 | |
b9af4937 SC |
9082 | /* set all the constant fields in the accelerator command |
9083 | * frames once at init time to save CPU cycles later. | |
9084 | */ | |
9085 | for (i = 0; i < h->nr_cmds; i++) { | |
9086 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
9087 | ||
9088 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
9089 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
9090 | (i * sizeof(struct ErrorInfo))); | |
9091 | cp->err_info_len = sizeof(struct ErrorInfo); | |
9092 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
2b08b3e9 DB |
9093 | cp->host_context_flags = |
9094 | cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); | |
b9af4937 SC |
9095 | cp->timeout_sec = 0; |
9096 | cp->ReplyQueue = 0; | |
50a0decf | 9097 | cp->tag = |
f2405db8 | 9098 | cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); |
50a0decf SC |
9099 | cp->host_addr = |
9100 | cpu_to_le64(h->ioaccel_cmd_pool_dhandle + | |
b9af4937 | 9101 | (i * sizeof(struct io_accel1_cmd))); |
b9af4937 SC |
9102 | } |
9103 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
9104 | u64 cfg_offset, cfg_base_addr_index; | |
9105 | u32 bft2_offset, cfg_base_addr; | |
9106 | int rc; | |
9107 | ||
9108 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, | |
9109 | &cfg_base_addr_index, &cfg_offset); | |
9110 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); | |
9111 | bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; | |
9112 | calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, | |
9113 | 4, h->ioaccel2_blockFetchTable); | |
9114 | bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); | |
9115 | BUILD_BUG_ON(offsetof(struct CfgTable, | |
9116 | io_accel_request_size_offset) != 0xb8); | |
9117 | h->ioaccel2_bft2_regs = | |
9118 | remap_pci_mem(pci_resource_start(h->pdev, | |
9119 | cfg_base_addr_index) + | |
9120 | cfg_offset + bft2_offset, | |
9121 | ARRAY_SIZE(bft2) * | |
9122 | sizeof(*h->ioaccel2_bft2_regs)); | |
9123 | for (i = 0; i < ARRAY_SIZE(bft2); i++) | |
9124 | writel(bft2[i], &h->ioaccel2_bft2_regs[i]); | |
e1f7de0c | 9125 | } |
b9af4937 | 9126 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
9127 | if (hpsa_wait_for_mode_change_ack(h)) { |
9128 | dev_err(&h->pdev->dev, | |
9129 | "performant mode problem - enabling ioaccel mode\n"); | |
9130 | return -ENODEV; | |
9131 | } | |
9132 | return 0; | |
e1f7de0c MG |
9133 | } |
9134 | ||
1fb7c98a RE |
9135 | /* Free ioaccel1 mode command blocks and block fetch table */ |
9136 | static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
9137 | { | |
105a3dbc | 9138 | if (h->ioaccel_cmd_pool) { |
1fb7c98a RE |
9139 | pci_free_consistent(h->pdev, |
9140 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
9141 | h->ioaccel_cmd_pool, | |
9142 | h->ioaccel_cmd_pool_dhandle); | |
105a3dbc RE |
9143 | h->ioaccel_cmd_pool = NULL; |
9144 | h->ioaccel_cmd_pool_dhandle = 0; | |
9145 | } | |
1fb7c98a | 9146 | kfree(h->ioaccel1_blockFetchTable); |
105a3dbc | 9147 | h->ioaccel1_blockFetchTable = NULL; |
1fb7c98a RE |
9148 | } |
9149 | ||
d37ffbe4 RE |
9150 | /* Allocate ioaccel1 mode command blocks and block fetch table */ |
9151 | static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
e1f7de0c | 9152 | { |
283b4a9b SC |
9153 | h->ioaccel_maxsg = |
9154 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9155 | if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) | |
9156 | h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; | |
9157 | ||
e1f7de0c MG |
9158 | /* Command structures must be aligned on a 128-byte boundary |
9159 | * because the 7 lower bits of the address are used by the | |
9160 | * hardware. | |
9161 | */ | |
e1f7de0c MG |
9162 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % |
9163 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
9164 | h->ioaccel_cmd_pool = | |
9165 | pci_alloc_consistent(h->pdev, | |
9166 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
9167 | &(h->ioaccel_cmd_pool_dhandle)); | |
9168 | ||
9169 | h->ioaccel1_blockFetchTable = | |
283b4a9b | 9170 | kmalloc(((h->ioaccel_maxsg + 1) * |
e1f7de0c MG |
9171 | sizeof(u32)), GFP_KERNEL); |
9172 | ||
9173 | if ((h->ioaccel_cmd_pool == NULL) || | |
9174 | (h->ioaccel1_blockFetchTable == NULL)) | |
9175 | goto clean_up; | |
9176 | ||
9177 | memset(h->ioaccel_cmd_pool, 0, | |
9178 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
9179 | return 0; | |
9180 | ||
9181 | clean_up: | |
1fb7c98a | 9182 | hpsa_free_ioaccel1_cmd_and_bft(h); |
2dd02d74 | 9183 | return -ENOMEM; |
6c311b57 SC |
9184 | } |
9185 | ||
1fb7c98a RE |
9186 | /* Free ioaccel2 mode command blocks and block fetch table */ |
9187 | static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
9188 | { | |
d9a729f3 WS |
9189 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
9190 | ||
105a3dbc | 9191 | if (h->ioaccel2_cmd_pool) { |
1fb7c98a RE |
9192 | pci_free_consistent(h->pdev, |
9193 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
9194 | h->ioaccel2_cmd_pool, | |
9195 | h->ioaccel2_cmd_pool_dhandle); | |
105a3dbc RE |
9196 | h->ioaccel2_cmd_pool = NULL; |
9197 | h->ioaccel2_cmd_pool_dhandle = 0; | |
9198 | } | |
1fb7c98a | 9199 | kfree(h->ioaccel2_blockFetchTable); |
105a3dbc | 9200 | h->ioaccel2_blockFetchTable = NULL; |
1fb7c98a RE |
9201 | } |
9202 | ||
d37ffbe4 RE |
9203 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9204 | static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
aca9012a | 9205 | { |
d9a729f3 WS |
9206 | int rc; |
9207 | ||
aca9012a SC |
9208 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9209 | ||
9210 | h->ioaccel_maxsg = | |
9211 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9212 | if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) | |
9213 | h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; | |
9214 | ||
aca9012a SC |
9215 | BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % |
9216 | IOACCEL2_COMMANDLIST_ALIGNMENT); | |
9217 | h->ioaccel2_cmd_pool = | |
9218 | pci_alloc_consistent(h->pdev, | |
9219 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
9220 | &(h->ioaccel2_cmd_pool_dhandle)); | |
9221 | ||
9222 | h->ioaccel2_blockFetchTable = | |
9223 | kmalloc(((h->ioaccel_maxsg + 1) * | |
9224 | sizeof(u32)), GFP_KERNEL); | |
9225 | ||
9226 | if ((h->ioaccel2_cmd_pool == NULL) || | |
d9a729f3 WS |
9227 | (h->ioaccel2_blockFetchTable == NULL)) { |
9228 | rc = -ENOMEM; | |
9229 | goto clean_up; | |
9230 | } | |
9231 | ||
9232 | rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); | |
9233 | if (rc) | |
aca9012a SC |
9234 | goto clean_up; |
9235 | ||
9236 | memset(h->ioaccel2_cmd_pool, 0, | |
9237 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); | |
9238 | return 0; | |
9239 | ||
9240 | clean_up: | |
1fb7c98a | 9241 | hpsa_free_ioaccel2_cmd_and_bft(h); |
d9a729f3 | 9242 | return rc; |
aca9012a SC |
9243 | } |
9244 | ||
105a3dbc RE |
9245 | /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ |
9246 | static void hpsa_free_performant_mode(struct ctlr_info *h) | |
9247 | { | |
9248 | kfree(h->blockFetchTable); | |
9249 | h->blockFetchTable = NULL; | |
9250 | hpsa_free_reply_queues(h); | |
9251 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9252 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9253 | } | |
9254 | ||
9255 | /* return -ENODEV on error, 0 on success (or no action) | |
9256 | * allocates numerous items that must be freed later | |
9257 | */ | |
9258 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) | |
6c311b57 SC |
9259 | { |
9260 | u32 trans_support; | |
e1f7de0c MG |
9261 | unsigned long transMethod = CFGTBL_Trans_Performant | |
9262 | CFGTBL_Trans_use_short_tags; | |
105a3dbc | 9263 | int i, rc; |
6c311b57 | 9264 | |
02ec19c8 | 9265 | if (hpsa_simple_mode) |
105a3dbc | 9266 | return 0; |
02ec19c8 | 9267 | |
67c99a72 | 9268 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
9269 | if (!(trans_support & PERFORMANT_MODE)) | |
105a3dbc | 9270 | return 0; |
67c99a72 | 9271 | |
e1f7de0c MG |
9272 | /* Check for I/O accelerator mode support */ |
9273 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
9274 | transMethod |= CFGTBL_Trans_io_accel1 | | |
9275 | CFGTBL_Trans_enable_directed_msix; | |
105a3dbc RE |
9276 | rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); |
9277 | if (rc) | |
9278 | return rc; | |
9279 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
9280 | transMethod |= CFGTBL_Trans_io_accel2 | | |
aca9012a | 9281 | CFGTBL_Trans_enable_directed_msix; |
105a3dbc RE |
9282 | rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); |
9283 | if (rc) | |
9284 | return rc; | |
e1f7de0c MG |
9285 | } |
9286 | ||
eee0f03a | 9287 | h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1; |
cba3d38b | 9288 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 9289 | /* Performant mode ring buffer and supporting data structures */ |
072b0518 | 9290 | h->reply_queue_size = h->max_commands * sizeof(u64); |
6c311b57 | 9291 | |
254f796b | 9292 | for (i = 0; i < h->nreply_queues; i++) { |
072b0518 SC |
9293 | h->reply_queue[i].head = pci_alloc_consistent(h->pdev, |
9294 | h->reply_queue_size, | |
9295 | &(h->reply_queue[i].busaddr)); | |
105a3dbc RE |
9296 | if (!h->reply_queue[i].head) { |
9297 | rc = -ENOMEM; | |
9298 | goto clean1; /* rq, ioaccel */ | |
9299 | } | |
254f796b MG |
9300 | h->reply_queue[i].size = h->max_commands; |
9301 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
9302 | h->reply_queue[i].current_entry = 0; | |
9303 | } | |
9304 | ||
6c311b57 | 9305 | /* Need a block fetch table for performant mode */ |
d66ae08b | 9306 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 | 9307 | sizeof(u32)), GFP_KERNEL); |
105a3dbc RE |
9308 | if (!h->blockFetchTable) { |
9309 | rc = -ENOMEM; | |
9310 | goto clean1; /* rq, ioaccel */ | |
9311 | } | |
6c311b57 | 9312 | |
105a3dbc RE |
9313 | rc = hpsa_enter_performant_mode(h, trans_support); |
9314 | if (rc) | |
9315 | goto clean2; /* bft, rq, ioaccel */ | |
9316 | return 0; | |
303932fd | 9317 | |
105a3dbc | 9318 | clean2: /* bft, rq, ioaccel */ |
303932fd | 9319 | kfree(h->blockFetchTable); |
105a3dbc RE |
9320 | h->blockFetchTable = NULL; |
9321 | clean1: /* rq, ioaccel */ | |
9322 | hpsa_free_reply_queues(h); | |
9323 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9324 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9325 | return rc; | |
303932fd DB |
9326 | } |
9327 | ||
23100dd9 | 9328 | static int is_accelerated_cmd(struct CommandList *c) |
76438d08 | 9329 | { |
23100dd9 SC |
9330 | return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; |
9331 | } | |
9332 | ||
9333 | static void hpsa_drain_accel_commands(struct ctlr_info *h) | |
9334 | { | |
9335 | struct CommandList *c = NULL; | |
f2405db8 | 9336 | int i, accel_cmds_out; |
281a7fd0 | 9337 | int refcount; |
76438d08 | 9338 | |
f2405db8 | 9339 | do { /* wait for all outstanding ioaccel commands to drain out */ |
23100dd9 | 9340 | accel_cmds_out = 0; |
f2405db8 | 9341 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 9342 | c = h->cmd_pool + i; |
281a7fd0 WS |
9343 | refcount = atomic_inc_return(&c->refcount); |
9344 | if (refcount > 1) /* Command is allocated */ | |
9345 | accel_cmds_out += is_accelerated_cmd(c); | |
9346 | cmd_free(h, c); | |
f2405db8 | 9347 | } |
23100dd9 | 9348 | if (accel_cmds_out <= 0) |
281a7fd0 | 9349 | break; |
76438d08 SC |
9350 | msleep(100); |
9351 | } while (1); | |
9352 | } | |
9353 | ||
d04e62b9 KB |
9354 | static struct hpsa_sas_phy *hpsa_alloc_sas_phy( |
9355 | struct hpsa_sas_port *hpsa_sas_port) | |
9356 | { | |
9357 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9358 | struct sas_phy *phy; | |
9359 | ||
9360 | hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); | |
9361 | if (!hpsa_sas_phy) | |
9362 | return NULL; | |
9363 | ||
9364 | phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, | |
9365 | hpsa_sas_port->next_phy_index); | |
9366 | if (!phy) { | |
9367 | kfree(hpsa_sas_phy); | |
9368 | return NULL; | |
9369 | } | |
9370 | ||
9371 | hpsa_sas_port->next_phy_index++; | |
9372 | hpsa_sas_phy->phy = phy; | |
9373 | hpsa_sas_phy->parent_port = hpsa_sas_port; | |
9374 | ||
9375 | return hpsa_sas_phy; | |
9376 | } | |
9377 | ||
9378 | static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9379 | { | |
9380 | struct sas_phy *phy = hpsa_sas_phy->phy; | |
9381 | ||
9382 | sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); | |
9383 | sas_phy_free(phy); | |
9384 | if (hpsa_sas_phy->added_to_port) | |
9385 | list_del(&hpsa_sas_phy->phy_list_entry); | |
9386 | kfree(hpsa_sas_phy); | |
9387 | } | |
9388 | ||
9389 | static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9390 | { | |
9391 | int rc; | |
9392 | struct hpsa_sas_port *hpsa_sas_port; | |
9393 | struct sas_phy *phy; | |
9394 | struct sas_identify *identify; | |
9395 | ||
9396 | hpsa_sas_port = hpsa_sas_phy->parent_port; | |
9397 | phy = hpsa_sas_phy->phy; | |
9398 | ||
9399 | identify = &phy->identify; | |
9400 | memset(identify, 0, sizeof(*identify)); | |
9401 | identify->sas_address = hpsa_sas_port->sas_address; | |
9402 | identify->device_type = SAS_END_DEVICE; | |
9403 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9404 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9405 | phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9406 | phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9407 | phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9408 | phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9409 | phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9410 | ||
9411 | rc = sas_phy_add(hpsa_sas_phy->phy); | |
9412 | if (rc) | |
9413 | return rc; | |
9414 | ||
9415 | sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); | |
9416 | list_add_tail(&hpsa_sas_phy->phy_list_entry, | |
9417 | &hpsa_sas_port->phy_list_head); | |
9418 | hpsa_sas_phy->added_to_port = true; | |
9419 | ||
9420 | return 0; | |
9421 | } | |
9422 | ||
9423 | static int | |
9424 | hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, | |
9425 | struct sas_rphy *rphy) | |
9426 | { | |
9427 | struct sas_identify *identify; | |
9428 | ||
9429 | identify = &rphy->identify; | |
9430 | identify->sas_address = hpsa_sas_port->sas_address; | |
9431 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9432 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9433 | ||
9434 | return sas_rphy_add(rphy); | |
9435 | } | |
9436 | ||
9437 | static struct hpsa_sas_port | |
9438 | *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, | |
9439 | u64 sas_address) | |
9440 | { | |
9441 | int rc; | |
9442 | struct hpsa_sas_port *hpsa_sas_port; | |
9443 | struct sas_port *port; | |
9444 | ||
9445 | hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); | |
9446 | if (!hpsa_sas_port) | |
9447 | return NULL; | |
9448 | ||
9449 | INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); | |
9450 | hpsa_sas_port->parent_node = hpsa_sas_node; | |
9451 | ||
9452 | port = sas_port_alloc_num(hpsa_sas_node->parent_dev); | |
9453 | if (!port) | |
9454 | goto free_hpsa_port; | |
9455 | ||
9456 | rc = sas_port_add(port); | |
9457 | if (rc) | |
9458 | goto free_sas_port; | |
9459 | ||
9460 | hpsa_sas_port->port = port; | |
9461 | hpsa_sas_port->sas_address = sas_address; | |
9462 | list_add_tail(&hpsa_sas_port->port_list_entry, | |
9463 | &hpsa_sas_node->port_list_head); | |
9464 | ||
9465 | return hpsa_sas_port; | |
9466 | ||
9467 | free_sas_port: | |
9468 | sas_port_free(port); | |
9469 | free_hpsa_port: | |
9470 | kfree(hpsa_sas_port); | |
9471 | ||
9472 | return NULL; | |
9473 | } | |
9474 | ||
9475 | static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) | |
9476 | { | |
9477 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9478 | struct hpsa_sas_phy *next; | |
9479 | ||
9480 | list_for_each_entry_safe(hpsa_sas_phy, next, | |
9481 | &hpsa_sas_port->phy_list_head, phy_list_entry) | |
9482 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9483 | ||
9484 | sas_port_delete(hpsa_sas_port->port); | |
9485 | list_del(&hpsa_sas_port->port_list_entry); | |
9486 | kfree(hpsa_sas_port); | |
9487 | } | |
9488 | ||
9489 | static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) | |
9490 | { | |
9491 | struct hpsa_sas_node *hpsa_sas_node; | |
9492 | ||
9493 | hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); | |
9494 | if (hpsa_sas_node) { | |
9495 | hpsa_sas_node->parent_dev = parent_dev; | |
9496 | INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); | |
9497 | } | |
9498 | ||
9499 | return hpsa_sas_node; | |
9500 | } | |
9501 | ||
9502 | static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) | |
9503 | { | |
9504 | struct hpsa_sas_port *hpsa_sas_port; | |
9505 | struct hpsa_sas_port *next; | |
9506 | ||
9507 | if (!hpsa_sas_node) | |
9508 | return; | |
9509 | ||
9510 | list_for_each_entry_safe(hpsa_sas_port, next, | |
9511 | &hpsa_sas_node->port_list_head, port_list_entry) | |
9512 | hpsa_free_sas_port(hpsa_sas_port); | |
9513 | ||
9514 | kfree(hpsa_sas_node); | |
9515 | } | |
9516 | ||
9517 | static struct hpsa_scsi_dev_t | |
9518 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
9519 | struct sas_rphy *rphy) | |
9520 | { | |
9521 | int i; | |
9522 | struct hpsa_scsi_dev_t *device; | |
9523 | ||
9524 | for (i = 0; i < h->ndevices; i++) { | |
9525 | device = h->dev[i]; | |
9526 | if (!device->sas_port) | |
9527 | continue; | |
9528 | if (device->sas_port->rphy == rphy) | |
9529 | return device; | |
9530 | } | |
9531 | ||
9532 | return NULL; | |
9533 | } | |
9534 | ||
9535 | static int hpsa_add_sas_host(struct ctlr_info *h) | |
9536 | { | |
9537 | int rc; | |
9538 | struct device *parent_dev; | |
9539 | struct hpsa_sas_node *hpsa_sas_node; | |
9540 | struct hpsa_sas_port *hpsa_sas_port; | |
9541 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9542 | ||
9543 | parent_dev = &h->scsi_host->shost_gendev; | |
9544 | ||
9545 | hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); | |
9546 | if (!hpsa_sas_node) | |
9547 | return -ENOMEM; | |
9548 | ||
9549 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); | |
9550 | if (!hpsa_sas_port) { | |
9551 | rc = -ENODEV; | |
9552 | goto free_sas_node; | |
9553 | } | |
9554 | ||
9555 | hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); | |
9556 | if (!hpsa_sas_phy) { | |
9557 | rc = -ENODEV; | |
9558 | goto free_sas_port; | |
9559 | } | |
9560 | ||
9561 | rc = hpsa_sas_port_add_phy(hpsa_sas_phy); | |
9562 | if (rc) | |
9563 | goto free_sas_phy; | |
9564 | ||
9565 | h->sas_host = hpsa_sas_node; | |
9566 | ||
9567 | return 0; | |
9568 | ||
9569 | free_sas_phy: | |
9570 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9571 | free_sas_port: | |
9572 | hpsa_free_sas_port(hpsa_sas_port); | |
9573 | free_sas_node: | |
9574 | hpsa_free_sas_node(hpsa_sas_node); | |
9575 | ||
9576 | return rc; | |
9577 | } | |
9578 | ||
9579 | static void hpsa_delete_sas_host(struct ctlr_info *h) | |
9580 | { | |
9581 | hpsa_free_sas_node(h->sas_host); | |
9582 | } | |
9583 | ||
9584 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
9585 | struct hpsa_scsi_dev_t *device) | |
9586 | { | |
9587 | int rc; | |
9588 | struct hpsa_sas_port *hpsa_sas_port; | |
9589 | struct sas_rphy *rphy; | |
9590 | ||
9591 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); | |
9592 | if (!hpsa_sas_port) | |
9593 | return -ENOMEM; | |
9594 | ||
9595 | rphy = sas_end_device_alloc(hpsa_sas_port->port); | |
9596 | if (!rphy) { | |
9597 | rc = -ENODEV; | |
9598 | goto free_sas_port; | |
9599 | } | |
9600 | ||
9601 | hpsa_sas_port->rphy = rphy; | |
9602 | device->sas_port = hpsa_sas_port; | |
9603 | ||
9604 | rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); | |
9605 | if (rc) | |
9606 | goto free_sas_port; | |
9607 | ||
9608 | return 0; | |
9609 | ||
9610 | free_sas_port: | |
9611 | hpsa_free_sas_port(hpsa_sas_port); | |
9612 | device->sas_port = NULL; | |
9613 | ||
9614 | return rc; | |
9615 | } | |
9616 | ||
9617 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) | |
9618 | { | |
9619 | if (device->sas_port) { | |
9620 | hpsa_free_sas_port(device->sas_port); | |
9621 | device->sas_port = NULL; | |
9622 | } | |
9623 | } | |
9624 | ||
9625 | static int | |
9626 | hpsa_sas_get_linkerrors(struct sas_phy *phy) | |
9627 | { | |
9628 | return 0; | |
9629 | } | |
9630 | ||
9631 | static int | |
9632 | hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) | |
9633 | { | |
aa105695 | 9634 | *identifier = 0; |
d04e62b9 KB |
9635 | return 0; |
9636 | } | |
9637 | ||
9638 | static int | |
9639 | hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) | |
9640 | { | |
9641 | return -ENXIO; | |
9642 | } | |
9643 | ||
9644 | static int | |
9645 | hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) | |
9646 | { | |
9647 | return 0; | |
9648 | } | |
9649 | ||
9650 | static int | |
9651 | hpsa_sas_phy_enable(struct sas_phy *phy, int enable) | |
9652 | { | |
9653 | return 0; | |
9654 | } | |
9655 | ||
9656 | static int | |
9657 | hpsa_sas_phy_setup(struct sas_phy *phy) | |
9658 | { | |
9659 | return 0; | |
9660 | } | |
9661 | ||
9662 | static void | |
9663 | hpsa_sas_phy_release(struct sas_phy *phy) | |
9664 | { | |
9665 | } | |
9666 | ||
9667 | static int | |
9668 | hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) | |
9669 | { | |
9670 | return -EINVAL; | |
9671 | } | |
9672 | ||
9673 | /* SMP = Serial Management Protocol */ | |
9674 | static int | |
9675 | hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy, | |
9676 | struct request *req) | |
9677 | { | |
9678 | return -EINVAL; | |
9679 | } | |
9680 | ||
9681 | static struct sas_function_template hpsa_sas_transport_functions = { | |
9682 | .get_linkerrors = hpsa_sas_get_linkerrors, | |
9683 | .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, | |
9684 | .get_bay_identifier = hpsa_sas_get_bay_identifier, | |
9685 | .phy_reset = hpsa_sas_phy_reset, | |
9686 | .phy_enable = hpsa_sas_phy_enable, | |
9687 | .phy_setup = hpsa_sas_phy_setup, | |
9688 | .phy_release = hpsa_sas_phy_release, | |
9689 | .set_phy_speed = hpsa_sas_phy_speed, | |
9690 | .smp_handler = hpsa_sas_smp_handler, | |
9691 | }; | |
9692 | ||
edd16368 SC |
9693 | /* |
9694 | * This is it. Register the PCI driver information for the cards we control | |
9695 | * the OS will call our registered routines when it finds one of our cards. | |
9696 | */ | |
9697 | static int __init hpsa_init(void) | |
9698 | { | |
d04e62b9 KB |
9699 | int rc; |
9700 | ||
9701 | hpsa_sas_transport_template = | |
9702 | sas_attach_transport(&hpsa_sas_transport_functions); | |
9703 | if (!hpsa_sas_transport_template) | |
9704 | return -ENODEV; | |
9705 | ||
9706 | rc = pci_register_driver(&hpsa_pci_driver); | |
9707 | ||
9708 | if (rc) | |
9709 | sas_release_transport(hpsa_sas_transport_template); | |
9710 | ||
9711 | return rc; | |
edd16368 SC |
9712 | } |
9713 | ||
9714 | static void __exit hpsa_cleanup(void) | |
9715 | { | |
9716 | pci_unregister_driver(&hpsa_pci_driver); | |
d04e62b9 | 9717 | sas_release_transport(hpsa_sas_transport_template); |
edd16368 SC |
9718 | } |
9719 | ||
e1f7de0c MG |
9720 | static void __attribute__((unused)) verify_offsets(void) |
9721 | { | |
dd0e19f3 ST |
9722 | #define VERIFY_OFFSET(member, offset) \ |
9723 | BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) | |
9724 | ||
9725 | VERIFY_OFFSET(structure_size, 0); | |
9726 | VERIFY_OFFSET(volume_blk_size, 4); | |
9727 | VERIFY_OFFSET(volume_blk_cnt, 8); | |
9728 | VERIFY_OFFSET(phys_blk_shift, 16); | |
9729 | VERIFY_OFFSET(parity_rotation_shift, 17); | |
9730 | VERIFY_OFFSET(strip_size, 18); | |
9731 | VERIFY_OFFSET(disk_starting_blk, 20); | |
9732 | VERIFY_OFFSET(disk_blk_cnt, 28); | |
9733 | VERIFY_OFFSET(data_disks_per_row, 36); | |
9734 | VERIFY_OFFSET(metadata_disks_per_row, 38); | |
9735 | VERIFY_OFFSET(row_cnt, 40); | |
9736 | VERIFY_OFFSET(layout_map_count, 42); | |
9737 | VERIFY_OFFSET(flags, 44); | |
9738 | VERIFY_OFFSET(dekindex, 46); | |
9739 | /* VERIFY_OFFSET(reserved, 48 */ | |
9740 | VERIFY_OFFSET(data, 64); | |
9741 | ||
9742 | #undef VERIFY_OFFSET | |
9743 | ||
b66cc250 MM |
9744 | #define VERIFY_OFFSET(member, offset) \ |
9745 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) | |
9746 | ||
9747 | VERIFY_OFFSET(IU_type, 0); | |
9748 | VERIFY_OFFSET(direction, 1); | |
9749 | VERIFY_OFFSET(reply_queue, 2); | |
9750 | /* VERIFY_OFFSET(reserved1, 3); */ | |
9751 | VERIFY_OFFSET(scsi_nexus, 4); | |
9752 | VERIFY_OFFSET(Tag, 8); | |
9753 | VERIFY_OFFSET(cdb, 16); | |
9754 | VERIFY_OFFSET(cciss_lun, 32); | |
9755 | VERIFY_OFFSET(data_len, 40); | |
9756 | VERIFY_OFFSET(cmd_priority_task_attr, 44); | |
9757 | VERIFY_OFFSET(sg_count, 45); | |
9758 | /* VERIFY_OFFSET(reserved3 */ | |
9759 | VERIFY_OFFSET(err_ptr, 48); | |
9760 | VERIFY_OFFSET(err_len, 56); | |
9761 | /* VERIFY_OFFSET(reserved4 */ | |
9762 | VERIFY_OFFSET(sg, 64); | |
9763 | ||
9764 | #undef VERIFY_OFFSET | |
9765 | ||
e1f7de0c MG |
9766 | #define VERIFY_OFFSET(member, offset) \ |
9767 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
9768 | ||
9769 | VERIFY_OFFSET(dev_handle, 0x00); | |
9770 | VERIFY_OFFSET(reserved1, 0x02); | |
9771 | VERIFY_OFFSET(function, 0x03); | |
9772 | VERIFY_OFFSET(reserved2, 0x04); | |
9773 | VERIFY_OFFSET(err_info, 0x0C); | |
9774 | VERIFY_OFFSET(reserved3, 0x10); | |
9775 | VERIFY_OFFSET(err_info_len, 0x12); | |
9776 | VERIFY_OFFSET(reserved4, 0x13); | |
9777 | VERIFY_OFFSET(sgl_offset, 0x14); | |
9778 | VERIFY_OFFSET(reserved5, 0x15); | |
9779 | VERIFY_OFFSET(transfer_len, 0x1C); | |
9780 | VERIFY_OFFSET(reserved6, 0x20); | |
9781 | VERIFY_OFFSET(io_flags, 0x24); | |
9782 | VERIFY_OFFSET(reserved7, 0x26); | |
9783 | VERIFY_OFFSET(LUN, 0x34); | |
9784 | VERIFY_OFFSET(control, 0x3C); | |
9785 | VERIFY_OFFSET(CDB, 0x40); | |
9786 | VERIFY_OFFSET(reserved8, 0x50); | |
9787 | VERIFY_OFFSET(host_context_flags, 0x60); | |
9788 | VERIFY_OFFSET(timeout_sec, 0x62); | |
9789 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
9790 | VERIFY_OFFSET(reserved9, 0x65); | |
50a0decf | 9791 | VERIFY_OFFSET(tag, 0x68); |
e1f7de0c MG |
9792 | VERIFY_OFFSET(host_addr, 0x70); |
9793 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
9794 | VERIFY_OFFSET(SG, 0x78 + 8); | |
9795 | #undef VERIFY_OFFSET | |
9796 | } | |
9797 | ||
edd16368 SC |
9798 | module_init(hpsa_init); |
9799 | module_exit(hpsa_cleanup); |