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hpsa: cleanup reset
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CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
73153fe5 47#include <scsi/scsi_dbg.h>
edd16368
SC		 48#include <linux/cciss_ioctl.h>
49#include <linux/string.h>
50#include <linux/bitmap.h>
60063497 51#include <linux/atomic.h>
a0c12413 52#include <linux/jiffies.h>
42a91641 53#include <linux/percpu-defs.h>
094963da 54#include <linux/percpu.h>
2b08b3e9 55#include <asm/unaligned.h>
283b4a9b 56#include <asm/div64.h>
edd16368
SC		 57#include "hpsa_cmd.h"
58#include "hpsa.h"
59
60/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 61#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 62#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 63#define HPSA "hpsa"
edd16368 64
007e7aa9
RE		 65/* How long to wait for CISS doorbell communication */
66#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
67#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
68#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
69#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 70#define MAX_IOCTL_CONFIG_WAIT 1000
71
72/*define how many times we will try a command because of bus resets */
73#define MAX_CMD_RETRIES 3
74
75/* Embedded module documentation macros - see modules.h */
76MODULE_AUTHOR("Hewlett-Packard Company");
77MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
78 HPSA_DRIVER_VERSION);
79MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
80MODULE_VERSION(HPSA_DRIVER_VERSION);
81MODULE_LICENSE("GPL");
82
83static int hpsa_allow_any;
84module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
85MODULE_PARM_DESC(hpsa_allow_any,
86 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 87static int hpsa_simple_mode;
88module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
89MODULE_PARM_DESC(hpsa_simple_mode,
90 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 91
92/* define the PCI info for the cards we can control */
93static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
138 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 139 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 140 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 141 {0,}
142};
143
144MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
145
146/* board_id = Subsystem Device ID & Vendor ID
147 * product = Marketing Name for the board
148 * access = Address of the struct of function pointers
149 */
150static struct board_type products[] = {
edd16368
SC		 151 {0x3241103C, "Smart Array P212", &SA5_access},
152 {0x3243103C, "Smart Array P410", &SA5_access},
153 {0x3245103C, "Smart Array P410i", &SA5_access},
154 {0x3247103C, "Smart Array P411", &SA5_access},
155 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 156 {0x324A103C, "Smart Array P712m", &SA5_access},
157 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 158 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 159 {0x3350103C, "Smart Array P222", &SA5_access},
160 {0x3351103C, "Smart Array P420", &SA5_access},
161 {0x3352103C, "Smart Array P421", &SA5_access},
162 {0x3353103C, "Smart Array P822", &SA5_access},
163 {0x3354103C, "Smart Array P420i", &SA5_access},
164 {0x3355103C, "Smart Array P220i", &SA5_access},
165 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 166 {0x1921103C, "Smart Array P830i", &SA5_access},
167 {0x1922103C, "Smart Array P430", &SA5_access},
168 {0x1923103C, "Smart Array P431", &SA5_access},
169 {0x1924103C, "Smart Array P830", &SA5_access},
170 {0x1926103C, "Smart Array P731m", &SA5_access},
171 {0x1928103C, "Smart Array P230i", &SA5_access},
172 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 173 {0x21BD103C, "Smart Array P244br", &SA5_access},
174 {0x21BE103C, "Smart Array P741m", &SA5_access},
175 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
176 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 177 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 178 {0x21C2103C, "Smart Array P440", &SA5_access},
179 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 180 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 181 {0x21C5103C, "Smart Array P841", &SA5_access},
182 {0x21C6103C, "Smart HBA H244br", &SA5_access},
183 {0x21C7103C, "Smart HBA H240", &SA5_access},
184 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 185 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 186 {0x21CA103C, "Smart Array P246br", &SA5_access},
187 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 188 {0x21CC103C, "Smart Array", &SA5_access},
189 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 190 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 191 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
192 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
193 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
194 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
195 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 196 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
197};
198
a58e7e53
WS		 199#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
200static const struct scsi_cmnd hpsa_cmd_busy;
201#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
202static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 203static int number_of_controllers;
204
10f66018
SC		 205static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
206static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 207static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 208
209#ifdef CONFIG_COMPAT
42a91641
DB		 210static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
211 void __user *arg);
edd16368
SC		 212#endif
213
214static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 215static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 216static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
217static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
218 struct scsi_cmnd *scmd);
a2dac136 219static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 220 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 221 int cmd_type);
2c143342 222static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 223#define VPD_PAGE (1 << 8)
edd16368 224
f281233d 225static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 226static void hpsa_scan_start(struct Scsi_Host *);
227static int hpsa_scan_finished(struct Scsi_Host *sh,
228 unsigned long elapsed_time);
7c0a0229 229static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 230
231static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 232static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 233static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 234static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 235static void hpsa_slave_destroy(struct scsi_device *sdev);
236
edd16368 237static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 238static int check_for_unit_attention(struct ctlr_info *h,
239 struct CommandList *c);
240static void check_ioctl_unit_attention(struct ctlr_info *h,
241 struct CommandList *c);
303932fd
DB		 242/* performant mode helper functions */
243static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 244 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 245static void hpsa_free_performant_mode(struct ctlr_info *h);
246static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 247static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 248static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
249 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
250 u64 *cfg_offset);
251static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
252 unsigned long *memory_bar);
253static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
254static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
255 int wait_for_ready);
75167d2c 256static inline void finish_cmd(struct CommandList *c);
c706a795 257static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 258#define BOARD_NOT_READY 0
259#define BOARD_READY 1
23100dd9 260static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 261static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 262static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
263 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 264 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 265static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 266static u32 lockup_detected(struct ctlr_info *h);
267static int detect_controller_lockup(struct ctlr_info *h);
edd16368 268
edd16368
SC		 269static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
270{
271 unsigned long *priv = shost_priv(sdev->host);
272 return (struct ctlr_info *) *priv;
273}
274
a23513e8
SC		 275static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
276{
277 unsigned long *priv = shost_priv(sh);
278 return (struct ctlr_info *) *priv;
279}
280
a58e7e53
WS		 281static inline bool hpsa_is_cmd_idle(struct CommandList *c)
282{
283 return c->scsi_cmd == SCSI_CMD_IDLE;
284}
285
d604f533
WS		 286static inline bool hpsa_is_pending_event(struct CommandList *c)
287{
288 return c->abort_pending || c->reset_pending;
289}
290
9437ac43
SC		 291/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
292static void decode_sense_data(const u8 *sense_data, int sense_data_len,
293 u8 *sense_key, u8 *asc, u8 *ascq)
294{
295 struct scsi_sense_hdr sshdr;
296 bool rc;
297
298 *sense_key = -1;
299 *asc = -1;
300 *ascq = -1;
301
302 if (sense_data_len < 1)
303 return;
304
305 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
306 if (rc) {
307 *sense_key = sshdr.sense_key;
308 *asc = sshdr.asc;
309 *ascq = sshdr.ascq;
310 }
311}
312
edd16368
SC		 313static int check_for_unit_attention(struct ctlr_info *h,
314 struct CommandList *c)
315{
9437ac43
SC		 316 u8 sense_key, asc, ascq;
317 int sense_len;
318
319 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
320 sense_len = sizeof(c->err_info->SenseInfo);
321 else
322 sense_len = c->err_info->SenseLen;
323
324 decode_sense_data(c->err_info->SenseInfo, sense_len,
325 &sense_key, &asc, &ascq);
326 if (sense_key != UNIT_ATTENTION || asc == -1)
edd16368
SC		 327 return 0;
328
9437ac43 329 switch (asc) {
edd16368 330 case STATE_CHANGED:
9437ac43 331 dev_warn(&h->pdev->dev,
2946e82b
RE		 332 "%s: a state change detected, command retried\n",
333 h->devname);
edd16368
SC		 334 break;
335 case LUN_FAILED:
7f73695a 336 dev_warn(&h->pdev->dev,
2946e82b 337 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 338 break;
339 case REPORT_LUNS_CHANGED:
7f73695a 340 dev_warn(&h->pdev->dev,
2946e82b 341 "%s: report LUN data changed\n", h->devname);
edd16368 342 /*
4f4eb9f1
ST		 343 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
344 * target (array) devices.
edd16368
SC		 345 */
346 break;
347 case POWER_OR_RESET:
2946e82b
RE		 348 dev_warn(&h->pdev->dev,
349 "%s: a power on or device reset detected\n",
350 h->devname);
edd16368
SC		 351 break;
352 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 353 dev_warn(&h->pdev->dev,
354 "%s: unit attention cleared by another initiator\n",
355 h->devname);
edd16368
SC		 356 break;
357 default:
2946e82b
RE		 358 dev_warn(&h->pdev->dev,
359 "%s: unknown unit attention detected\n",
360 h->devname);
edd16368
SC		 361 break;
362 }
363 return 1;
364}
365
852af20a
MB		 366static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
367{
368 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
369 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
370 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
371 return 0;
372 dev_warn(&h->pdev->dev, HPSA "device busy");
373 return 1;
374}
375
e985c58f
SC		 376static u32 lockup_detected(struct ctlr_info *h);
377static ssize_t host_show_lockup_detected(struct device *dev,
378 struct device_attribute *attr, char *buf)
379{
380 int ld;
381 struct ctlr_info *h;
382 struct Scsi_Host *shost = class_to_shost(dev);
383
384 h = shost_to_hba(shost);
385 ld = lockup_detected(h);
386
387 return sprintf(buf, "ld=%d\n", ld);
388}
389
da0697bd
ST		 390static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
391 struct device_attribute *attr,
392 const char *buf, size_t count)
393{
394 int status, len;
395 struct ctlr_info *h;
396 struct Scsi_Host *shost = class_to_shost(dev);
397 char tmpbuf[10];
398
399 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
400 return -EACCES;
401 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
402 strncpy(tmpbuf, buf, len);
403 tmpbuf[len] = '\0';
404 if (sscanf(tmpbuf, "%d", &status) != 1)
405 return -EINVAL;
406 h = shost_to_hba(shost);
407 h->acciopath_status = !!status;
408 dev_warn(&h->pdev->dev,
409 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
410 h->acciopath_status ? "enabled" : "disabled");
411 return count;
412}
413
2ba8bfc8
SC		 414static ssize_t host_store_raid_offload_debug(struct device *dev,
415 struct device_attribute *attr,
416 const char *buf, size_t count)
417{
418 int debug_level, len;
419 struct ctlr_info *h;
420 struct Scsi_Host *shost = class_to_shost(dev);
421 char tmpbuf[10];
422
423 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
424 return -EACCES;
425 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
426 strncpy(tmpbuf, buf, len);
427 tmpbuf[len] = '\0';
428 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
429 return -EINVAL;
430 if (debug_level < 0)
431 debug_level = 0;
432 h = shost_to_hba(shost);
433 h->raid_offload_debug = debug_level;
434 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
435 h->raid_offload_debug);
436 return count;
437}
438
edd16368
SC		 439static ssize_t host_store_rescan(struct device *dev,
440 struct device_attribute *attr,
441 const char *buf, size_t count)
442{
443 struct ctlr_info *h;
444 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 445 h = shost_to_hba(shost);
31468401 446 hpsa_scan_start(h->scsi_host);
edd16368
SC		 447 return count;
448}
449
d28ce020
SC		 450static ssize_t host_show_firmware_revision(struct device *dev,
451 struct device_attribute *attr, char *buf)
452{
453 struct ctlr_info *h;
454 struct Scsi_Host *shost = class_to_shost(dev);
455 unsigned char *fwrev;
456
457 h = shost_to_hba(shost);
458 if (!h->hba_inquiry_data)
459 return 0;
460 fwrev = &h->hba_inquiry_data[32];
461 return snprintf(buf, 20, "%c%c%c%c\n",
462 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
463}
464
94a13649
SC		 465static ssize_t host_show_commands_outstanding(struct device *dev,
466 struct device_attribute *attr, char *buf)
467{
468 struct Scsi_Host *shost = class_to_shost(dev);
469 struct ctlr_info *h = shost_to_hba(shost);
470
0cbf768e
SC		 471 return snprintf(buf, 20, "%d\n",
472 atomic_read(&h->commands_outstanding));
94a13649
SC		 473}
474
745a7a25
SC		 475static ssize_t host_show_transport_mode(struct device *dev,
476 struct device_attribute *attr, char *buf)
477{
478 struct ctlr_info *h;
479 struct Scsi_Host *shost = class_to_shost(dev);
480
481 h = shost_to_hba(shost);
482 return snprintf(buf, 20, "%s\n",
960a30e7 483 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 484 "performant" : "simple");
485}
486
da0697bd
ST		 487static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
488 struct device_attribute *attr, char *buf)
489{
490 struct ctlr_info *h;
491 struct Scsi_Host *shost = class_to_shost(dev);
492
493 h = shost_to_hba(shost);
494 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
495 (h->acciopath_status == 1) ? "enabled" : "disabled");
496}
497
46380786 498/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 499static u32 unresettable_controller[] = {
500 0x324a103C, /* Smart Array P712m */
9b5c48c2 501 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 502 0x3223103C, /* Smart Array P800 */
503 0x3234103C, /* Smart Array P400 */
504 0x3235103C, /* Smart Array P400i */
505 0x3211103C, /* Smart Array E200i */
506 0x3212103C, /* Smart Array E200 */
507 0x3213103C, /* Smart Array E200i */
508 0x3214103C, /* Smart Array E200i */
509 0x3215103C, /* Smart Array E200i */
510 0x3237103C, /* Smart Array E500 */
511 0x323D103C, /* Smart Array P700m */
7af0abbc 512 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 513 0x409C0E11, /* Smart Array 6400 */
514 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 515 0x40700E11, /* Smart Array 5300 */
516 0x40820E11, /* Smart Array 532 */
517 0x40830E11, /* Smart Array 5312 */
518 0x409A0E11, /* Smart Array 641 */
519 0x409B0E11, /* Smart Array 642 */
520 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 521};
522
46380786
SC		 523/* List of controllers which cannot even be soft reset */
524static u32 soft_unresettable_controller[] = {
7af0abbc 525 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
46380786
SC		 532 /* Exclude 640x boards. These are two pci devices in one slot
533 * which share a battery backed cache module. One controls the
534 * cache, the other accesses the cache through the one that controls
535 * it. If we reset the one controlling the cache, the other will
536 * likely not be happy. Just forbid resetting this conjoined mess.
537 * The 640x isn't really supported by hpsa anyway.
538 */
539 0x409C0E11, /* Smart Array 6400 */
540 0x409D0E11, /* Smart Array 6400 EM */
541};
542
9b5c48c2
SC		 543static u32 needs_abort_tags_swizzled[] = {
544 0x323D103C, /* Smart Array P700m */
545 0x324a103C, /* Smart Array P712m */
546 0x324b103C, /* SmartArray P711m */
547};
548
549static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 550{
551 int i;
552
9b5c48c2
SC		 553 for (i = 0; i < nelems; i++)
554 if (a[i] == board_id)
555 return 1;
556 return 0;
46380786
SC		 557}
558
9b5c48c2 559static int ctlr_is_hard_resettable(u32 board_id)
46380786 560{
9b5c48c2
SC		 561 return !board_id_in_array(unresettable_controller,
562 ARRAY_SIZE(unresettable_controller), board_id);
563}
46380786 564
9b5c48c2
SC		 565static int ctlr_is_soft_resettable(u32 board_id)
566{
567 return !board_id_in_array(soft_unresettable_controller,
568 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 569}
570
46380786
SC		 571static int ctlr_is_resettable(u32 board_id)
572{
573 return ctlr_is_hard_resettable(board_id) ||
574 ctlr_is_soft_resettable(board_id);
575}
576
9b5c48c2
SC		 577static int ctlr_needs_abort_tags_swizzled(u32 board_id)
578{
579 return board_id_in_array(needs_abort_tags_swizzled,
580 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
581}
582
941b1cda
SC		 583static ssize_t host_show_resettable(struct device *dev,
584 struct device_attribute *attr, char *buf)
585{
586 struct ctlr_info *h;
587 struct Scsi_Host *shost = class_to_shost(dev);
588
589 h = shost_to_hba(shost);
46380786 590 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 591}
592
edd16368
SC		 593static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
594{
595 return (scsi3addr[3] & 0xC0) == 0x40;
596}
597
f2ef0ce7
RE		 598static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
599 "1(+0)ADM", "UNKNOWN"
edd16368 600};
6b80b18f
ST		 601#define HPSA_RAID_0 0
602#define HPSA_RAID_4 1
603#define HPSA_RAID_1 2 /* also used for RAID 10 */
604#define HPSA_RAID_5 3 /* also used for RAID 50 */
605#define HPSA_RAID_51 4
606#define HPSA_RAID_6 5 /* also used for RAID 60 */
607#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 608#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
609
610static ssize_t raid_level_show(struct device *dev,
611 struct device_attribute *attr, char *buf)
612{
613 ssize_t l = 0;
82a72c0a 614 unsigned char rlevel;
edd16368
SC		 615 struct ctlr_info *h;
616 struct scsi_device *sdev;
617 struct hpsa_scsi_dev_t *hdev;
618 unsigned long flags;
619
620 sdev = to_scsi_device(dev);
621 h = sdev_to_hba(sdev);
622 spin_lock_irqsave(&h->lock, flags);
623 hdev = sdev->hostdata;
624 if (!hdev) {
625 spin_unlock_irqrestore(&h->lock, flags);
626 return -ENODEV;
627 }
628
629 /* Is this even a logical drive? */
630 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
631 spin_unlock_irqrestore(&h->lock, flags);
632 l = snprintf(buf, PAGE_SIZE, "N/A\n");
633 return l;
634 }
635
636 rlevel = hdev->raid_level;
637 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 638 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 639 rlevel = RAID_UNKNOWN;
640 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
641 return l;
642}
643
644static ssize_t lunid_show(struct device *dev,
645 struct device_attribute *attr, char *buf)
646{
647 struct ctlr_info *h;
648 struct scsi_device *sdev;
649 struct hpsa_scsi_dev_t *hdev;
650 unsigned long flags;
651 unsigned char lunid[8];
652
653 sdev = to_scsi_device(dev);
654 h = sdev_to_hba(sdev);
655 spin_lock_irqsave(&h->lock, flags);
656 hdev = sdev->hostdata;
657 if (!hdev) {
658 spin_unlock_irqrestore(&h->lock, flags);
659 return -ENODEV;
660 }
661 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
662 spin_unlock_irqrestore(&h->lock, flags);
663 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
664 lunid[0], lunid[1], lunid[2], lunid[3],
665 lunid[4], lunid[5], lunid[6], lunid[7]);
666}
667
668static ssize_t unique_id_show(struct device *dev,
669 struct device_attribute *attr, char *buf)
670{
671 struct ctlr_info *h;
672 struct scsi_device *sdev;
673 struct hpsa_scsi_dev_t *hdev;
674 unsigned long flags;
675 unsigned char sn[16];
676
677 sdev = to_scsi_device(dev);
678 h = sdev_to_hba(sdev);
679 spin_lock_irqsave(&h->lock, flags);
680 hdev = sdev->hostdata;
681 if (!hdev) {
682 spin_unlock_irqrestore(&h->lock, flags);
683 return -ENODEV;
684 }
685 memcpy(sn, hdev->device_id, sizeof(sn));
686 spin_unlock_irqrestore(&h->lock, flags);
687 return snprintf(buf, 16 * 2 + 2,
688 "%02X%02X%02X%02X%02X%02X%02X%02X"
689 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
690 sn[0], sn[1], sn[2], sn[3],
691 sn[4], sn[5], sn[6], sn[7],
692 sn[8], sn[9], sn[10], sn[11],
693 sn[12], sn[13], sn[14], sn[15]);
694}
695
c1988684
ST		 696static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
697 struct device_attribute *attr, char *buf)
698{
699 struct ctlr_info *h;
700 struct scsi_device *sdev;
701 struct hpsa_scsi_dev_t *hdev;
702 unsigned long flags;
703 int offload_enabled;
704
705 sdev = to_scsi_device(dev);
706 h = sdev_to_hba(sdev);
707 spin_lock_irqsave(&h->lock, flags);
708 hdev = sdev->hostdata;
709 if (!hdev) {
710 spin_unlock_irqrestore(&h->lock, flags);
711 return -ENODEV;
712 }
713 offload_enabled = hdev->offload_enabled;
714 spin_unlock_irqrestore(&h->lock, flags);
715 return snprintf(buf, 20, "%d\n", offload_enabled);
716}
717
3f5eac3a
SC		 718static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
719static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
720static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
721static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 722static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
723 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 724static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
725 host_show_hp_ssd_smart_path_status,
726 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 727static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
728 host_store_raid_offload_debug);
3f5eac3a
SC		 729static DEVICE_ATTR(firmware_revision, S_IRUGO,
730 host_show_firmware_revision, NULL);
731static DEVICE_ATTR(commands_outstanding, S_IRUGO,
732 host_show_commands_outstanding, NULL);
733static DEVICE_ATTR(transport_mode, S_IRUGO,
734 host_show_transport_mode, NULL);
941b1cda
SC		 735static DEVICE_ATTR(resettable, S_IRUGO,
736 host_show_resettable, NULL);
e985c58f
SC		 737static DEVICE_ATTR(lockup_detected, S_IRUGO,
738 host_show_lockup_detected, NULL);
3f5eac3a
SC		 739
740static struct device_attribute *hpsa_sdev_attrs[] = {
741 &dev_attr_raid_level,
742 &dev_attr_lunid,
743 &dev_attr_unique_id,
c1988684 744 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 745 &dev_attr_lockup_detected,
3f5eac3a
SC		 746 NULL,
747};
748
749static struct device_attribute *hpsa_shost_attrs[] = {
750 &dev_attr_rescan,
751 &dev_attr_firmware_revision,
752 &dev_attr_commands_outstanding,
753 &dev_attr_transport_mode,
941b1cda 754 &dev_attr_resettable,
da0697bd 755 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 756 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 757 NULL,
758};
759
41ce4c35
SC		 760#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
761 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
762
3f5eac3a
SC		 763static struct scsi_host_template hpsa_driver_template = {
764 .module = THIS_MODULE,
f79cfec6
SC		 765 .name = HPSA,
766 .proc_name = HPSA,
3f5eac3a
SC		 767 .queuecommand = hpsa_scsi_queue_command,
768 .scan_start = hpsa_scan_start,
769 .scan_finished = hpsa_scan_finished,
7c0a0229 770 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 771 .this_id = -1,
772 .use_clustering = ENABLE_CLUSTERING,
75167d2c 773 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 774 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
775 .ioctl = hpsa_ioctl,
776 .slave_alloc = hpsa_slave_alloc,
41ce4c35 777 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 778 .slave_destroy = hpsa_slave_destroy,
779#ifdef CONFIG_COMPAT
780 .compat_ioctl = hpsa_compat_ioctl,
781#endif
782 .sdev_attrs = hpsa_sdev_attrs,
783 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 784 .max_sectors = 8192,
54b2b50c 785 .no_write_same = 1,
3f5eac3a
SC		 786};
787
254f796b 788static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 789{
790 u32 a;
072b0518 791 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 792
e1f7de0c
MG		 793 if (h->transMethod & CFGTBL_Trans_io_accel1)
794 return h->access.command_completed(h, q);
795
3f5eac3a 796 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 797 return h->access.command_completed(h, q);
3f5eac3a 798
254f796b
MG		 799 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
800 a = rq->head[rq->current_entry];
801 rq->current_entry++;
0cbf768e 802 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 803 } else {
804 a = FIFO_EMPTY;
805 }
806 /* Check for wraparound */
254f796b
MG		 807 if (rq->current_entry == h->max_commands) {
808 rq->current_entry = 0;
809 rq->wraparound ^= 1;
3f5eac3a
SC		 810 }
811 return a;
812}
813
c349775e
ST		 814/*
815 * There are some special bits in the bus address of the
816 * command that we have to set for the controller to know
817 * how to process the command:
818 *
819 * Normal performant mode:
820 * bit 0: 1 means performant mode, 0 means simple mode.
821 * bits 1-3 = block fetch table entry
822 * bits 4-6 = command type (== 0)
823 *
824 * ioaccel1 mode:
825 * bit 0 = "performant mode" bit.
826 * bits 1-3 = block fetch table entry
827 * bits 4-6 = command type (== 110)
828 * (command type is needed because ioaccel1 mode
829 * commands are submitted through the same register as normal
830 * mode commands, so this is how the controller knows whether
831 * the command is normal mode or ioaccel1 mode.)
832 *
833 * ioaccel2 mode:
834 * bit 0 = "performant mode" bit.
835 * bits 1-4 = block fetch table entry (note extra bit)
836 * bits 4-6 = not needed, because ioaccel2 mode has
837 * a separate special register for submitting commands.
838 */
839
25163bd5
WS		 840/*
841 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 842 * set bit 0 for pull model, bits 3-1 for block fetch
843 * register number
844 */
25163bd5
WS		 845#define DEFAULT_REPLY_QUEUE (-1)
846static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
847 int reply_queue)
3f5eac3a 848{
254f796b 849 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 850 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 851 if (unlikely(!h->msix_vector))
852 return;
853 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 854 c->Header.ReplyQueue =
804a5cb5 855 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 856 else
857 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 858 }
3f5eac3a
SC		 859}
860
c349775e 861static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 862 struct CommandList *c,
863 int reply_queue)
c349775e
ST		 864{
865 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
866
25163bd5
WS		 867 /*
868 * Tell the controller to post the reply to the queue for this
c349775e
ST		 869 * processor. This seems to give the best I/O throughput.
870 */
25163bd5
WS		 871 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
872 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
873 else
874 cp->ReplyQueue = reply_queue % h->nreply_queues;
875 /*
876 * Set the bits in the address sent down to include:
c349775e
ST		 877 * - performant mode bit (bit 0)
878 * - pull count (bits 1-3)
879 * - command type (bits 4-6)
880 */
881 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
882 IOACCEL1_BUSADDR_CMDTYPE;
883}
884
8be986cc
SC		 885static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
886 struct CommandList *c,
887 int reply_queue)
888{
889 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
890 &h->ioaccel2_cmd_pool[c->cmdindex];
891
892 /* Tell the controller to post the reply to the queue for this
893 * processor. This seems to give the best I/O throughput.
894 */
895 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
896 cp->reply_queue = smp_processor_id() % h->nreply_queues;
897 else
898 cp->reply_queue = reply_queue % h->nreply_queues;
899 /* Set the bits in the address sent down to include:
900 * - performant mode bit not used in ioaccel mode 2
901 * - pull count (bits 0-3)
902 * - command type isn't needed for ioaccel2
903 */
904 c->busaddr |= h->ioaccel2_blockFetchTable[0];
905}
906
c349775e 907static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 908 struct CommandList *c,
909 int reply_queue)
c349775e
ST		 910{
911 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
912
25163bd5
WS		 913 /*
914 * Tell the controller to post the reply to the queue for this
c349775e
ST		 915 * processor. This seems to give the best I/O throughput.
916 */
25163bd5
WS		 917 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
918 cp->reply_queue = smp_processor_id() % h->nreply_queues;
919 else
920 cp->reply_queue = reply_queue % h->nreply_queues;
921 /*
922 * Set the bits in the address sent down to include:
c349775e
ST		 923 * - performant mode bit not used in ioaccel mode 2
924 * - pull count (bits 0-3)
925 * - command type isn't needed for ioaccel2
926 */
927 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
928}
929
e85c5974
SC		 930static int is_firmware_flash_cmd(u8 *cdb)
931{
932 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
933}
934
935/*
936 * During firmware flash, the heartbeat register may not update as frequently
937 * as it should. So we dial down lockup detection during firmware flash. and
938 * dial it back up when firmware flash completes.
939 */
940#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
941#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
942static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
943 struct CommandList *c)
944{
945 if (!is_firmware_flash_cmd(c->Request.CDB))
946 return;
947 atomic_inc(&h->firmware_flash_in_progress);
948 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
949}
950
951static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
952 struct CommandList *c)
953{
954 if (is_firmware_flash_cmd(c->Request.CDB) &&
955 atomic_dec_and_test(&h->firmware_flash_in_progress))
956 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
957}
958
25163bd5
WS		 959static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
960 struct CommandList *c, int reply_queue)
3f5eac3a 961{
c05e8866
SC		 962 dial_down_lockup_detection_during_fw_flash(h, c);
963 atomic_inc(&h->commands_outstanding);
c349775e
ST		 964 switch (c->cmd_type) {
965 case CMD_IOACCEL1:
25163bd5 966 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 967 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 968 break;
969 case CMD_IOACCEL2:
25163bd5 970 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 971 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 972 break;
8be986cc
SC		 973 case IOACCEL2_TMF:
974 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
975 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
976 break;
c349775e 977 default:
25163bd5 978 set_performant_mode(h, c, reply_queue);
c05e8866 979 h->access.submit_command(h, c);
c349775e 980 }
3f5eac3a
SC		 981}
982
a58e7e53 983static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 984{
d604f533 985 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 986 return finish_cmd(c);
987
25163bd5
WS		 988 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
989}
990
3f5eac3a
SC		 991static inline int is_hba_lunid(unsigned char scsi3addr[])
992{
993 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
994}
995
996static inline int is_scsi_rev_5(struct ctlr_info *h)
997{
998 if (!h->hba_inquiry_data)
999 return 0;
1000 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1001 return 1;
1002 return 0;
1003}
1004
edd16368
SC		 1005static int hpsa_find_target_lun(struct ctlr_info *h,
1006 unsigned char scsi3addr[], int bus, int *target, int *lun)
1007{
1008 /* finds an unused bus, target, lun for a new physical device
1009 * assumes h->devlock is held
1010 */
1011 int i, found = 0;
cfe5badc 1012 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1013
263d9401 1014 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1015
1016 for (i = 0; i < h->ndevices; i++) {
1017 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1018 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1019 }
1020
263d9401
AM		 1021 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1022 if (i < HPSA_MAX_DEVICES) {
1023 /* *bus = 1; */
1024 *target = i;
1025 *lun = 0;
1026 found = 1;
edd16368
SC		 1027 }
1028 return !found;
1029}
1030
0d96ef5f
WS		 1031static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
1032 struct hpsa_scsi_dev_t *dev, char *description)
1033{
1034 dev_printk(level, &h->pdev->dev,
1035 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1036 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1037 description,
1038 scsi_device_type(dev->devtype),
1039 dev->vendor,
1040 dev->model,
1041 dev->raid_level > RAID_UNKNOWN ?
1042 "RAID-?" : raid_label[dev->raid_level],
1043 dev->offload_config ? '+' : '-',
1044 dev->offload_enabled ? '+' : '-',
1045 dev->expose_state);
1046}
1047
edd16368
SC		 1048/* Add an entry into h->dev[] array. */
1049static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1050 struct hpsa_scsi_dev_t *device,
1051 struct hpsa_scsi_dev_t *added[], int *nadded)
1052{
1053 /* assumes h->devlock is held */
1054 int n = h->ndevices;
1055 int i;
1056 unsigned char addr1[8], addr2[8];
1057 struct hpsa_scsi_dev_t *sd;
1058
cfe5badc 1059 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1060 dev_err(&h->pdev->dev, "too many devices, some will be "
1061 "inaccessible.\n");
1062 return -1;
1063 }
1064
1065 /* physical devices do not have lun or target assigned until now. */
1066 if (device->lun != -1)
1067 /* Logical device, lun is already assigned. */
1068 goto lun_assigned;
1069
1070 /* If this device a non-zero lun of a multi-lun device
1071 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1072 * unit no, zero otherwise.
edd16368
SC		 1073 */
1074 if (device->scsi3addr[4] == 0) {
1075 /* This is not a non-zero lun of a multi-lun device */
1076 if (hpsa_find_target_lun(h, device->scsi3addr,
1077 device->bus, &device->target, &device->lun) != 0)
1078 return -1;
1079 goto lun_assigned;
1080 }
1081
1082 /* This is a non-zero lun of a multi-lun device.
1083 * Search through our list and find the device which
1084 * has the same 8 byte LUN address, excepting byte 4.
1085 * Assign the same bus and target for this new LUN.
1086 * Use the logical unit number from the firmware.
1087 */
1088 memcpy(addr1, device->scsi3addr, 8);
1089 addr1[4] = 0;
1090 for (i = 0; i < n; i++) {
1091 sd = h->dev[i];
1092 memcpy(addr2, sd->scsi3addr, 8);
1093 addr2[4] = 0;
1094 /* differ only in byte 4? */
1095 if (memcmp(addr1, addr2, 8) == 0) {
1096 device->bus = sd->bus;
1097 device->target = sd->target;
1098 device->lun = device->scsi3addr[4];
1099 break;
1100 }
1101 }
1102 if (device->lun == -1) {
1103 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1104 " suspect firmware bug or unsupported hardware "
1105 "configuration.\n");
1106 return -1;
1107 }
1108
1109lun_assigned:
1110
1111 h->dev[n] = device;
1112 h->ndevices++;
1113 added[*nadded] = device;
1114 (*nadded)++;
0d96ef5f
WS		 1115 hpsa_show_dev_msg(KERN_INFO, h, device,
1116 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1117 device->offload_to_be_enabled = device->offload_enabled;
1118 device->offload_enabled = 0;
edd16368
SC		 1119 return 0;
1120}
1121
bd9244f7
ST		 1122/* Update an entry in h->dev[] array. */
1123static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1124 int entry, struct hpsa_scsi_dev_t *new_entry)
1125{
a473d86c 1126 int offload_enabled;
bd9244f7
ST		 1127 /* assumes h->devlock is held */
1128 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1129
1130 /* Raid level changed. */
1131 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1132
03383736
DB		 1133 /* Raid offload parameters changed. Careful about the ordering. */
1134 if (new_entry->offload_config && new_entry->offload_enabled) {
1135 /*
1136 * if drive is newly offload_enabled, we want to copy the
1137 * raid map data first. If previously offload_enabled and
1138 * offload_config were set, raid map data had better be
1139 * the same as it was before. if raid map data is changed
1140 * then it had better be the case that
1141 * h->dev[entry]->offload_enabled is currently 0.
1142 */
1143 h->dev[entry]->raid_map = new_entry->raid_map;
1144 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1145 }
a3144e0b
JH		 1146 if (new_entry->hba_ioaccel_enabled) {
1147 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1148 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1149 }
1150 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1151 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1152 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1153 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1154
41ce4c35
SC		 1155 /*
1156 * We can turn off ioaccel offload now, but need to delay turning
1157 * it on until we can update h->dev[entry]->phys_disk[], but we
1158 * can't do that until all the devices are updated.
1159 */
1160 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1161 if (!new_entry->offload_enabled)
1162 h->dev[entry]->offload_enabled = 0;
1163
a473d86c
RE		 1164 offload_enabled = h->dev[entry]->offload_enabled;
1165 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1166 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1167 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1168}
1169
2a8ccf31
SC		 1170/* Replace an entry from h->dev[] array. */
1171static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1172 int entry, struct hpsa_scsi_dev_t *new_entry,
1173 struct hpsa_scsi_dev_t *added[], int *nadded,
1174 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1175{
1176 /* assumes h->devlock is held */
cfe5badc 1177 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1178 removed[*nremoved] = h->dev[entry];
1179 (*nremoved)++;
01350d05
SC		 1180
1181 /*
1182 * New physical devices won't have target/lun assigned yet
1183 * so we need to preserve the values in the slot we are replacing.
1184 */
1185 if (new_entry->target == -1) {
1186 new_entry->target = h->dev[entry]->target;
1187 new_entry->lun = h->dev[entry]->lun;
1188 }
1189
2a8ccf31
SC		 1190 h->dev[entry] = new_entry;
1191 added[*nadded] = new_entry;
1192 (*nadded)++;
0d96ef5f 1193 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1194 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1195 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1196}
1197
edd16368
SC		 1198/* Remove an entry from h->dev[] array. */
1199static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1200 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1201{
1202 /* assumes h->devlock is held */
1203 int i;
1204 struct hpsa_scsi_dev_t *sd;
1205
cfe5badc 1206 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1207
1208 sd = h->dev[entry];
1209 removed[*nremoved] = h->dev[entry];
1210 (*nremoved)++;
1211
1212 for (i = entry; i < h->ndevices-1; i++)
1213 h->dev[i] = h->dev[i+1];
1214 h->ndevices--;
0d96ef5f 1215 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1216}
1217
1218#define SCSI3ADDR_EQ(a, b) ( \
1219 (a)[7] == (b)[7] && \
1220 (a)[6] == (b)[6] && \
1221 (a)[5] == (b)[5] && \
1222 (a)[4] == (b)[4] && \
1223 (a)[3] == (b)[3] && \
1224 (a)[2] == (b)[2] && \
1225 (a)[1] == (b)[1] && \
1226 (a)[0] == (b)[0])
1227
1228static void fixup_botched_add(struct ctlr_info *h,
1229 struct hpsa_scsi_dev_t *added)
1230{
1231 /* called when scsi_add_device fails in order to re-adjust
1232 * h->dev[] to match the mid layer's view.
1233 */
1234 unsigned long flags;
1235 int i, j;
1236
1237 spin_lock_irqsave(&h->lock, flags);
1238 for (i = 0; i < h->ndevices; i++) {
1239 if (h->dev[i] == added) {
1240 for (j = i; j < h->ndevices-1; j++)
1241 h->dev[j] = h->dev[j+1];
1242 h->ndevices--;
1243 break;
1244 }
1245 }
1246 spin_unlock_irqrestore(&h->lock, flags);
1247 kfree(added);
1248}
1249
1250static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1251 struct hpsa_scsi_dev_t *dev2)
1252{
edd16368
SC		 1253 /* we compare everything except lun and target as these
1254 * are not yet assigned. Compare parts likely
1255 * to differ first
1256 */
1257 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1258 sizeof(dev1->scsi3addr)) != 0)
1259 return 0;
1260 if (memcmp(dev1->device_id, dev2->device_id,
1261 sizeof(dev1->device_id)) != 0)
1262 return 0;
1263 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1264 return 0;
1265 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1266 return 0;
edd16368
SC		 1267 if (dev1->devtype != dev2->devtype)
1268 return 0;
edd16368
SC		 1269 if (dev1->bus != dev2->bus)
1270 return 0;
1271 return 1;
1272}
1273
bd9244f7
ST		 1274static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1275 struct hpsa_scsi_dev_t *dev2)
1276{
1277 /* Device attributes that can change, but don't mean
1278 * that the device is a different device, nor that the OS
1279 * needs to be told anything about the change.
1280 */
1281 if (dev1->raid_level != dev2->raid_level)
1282 return 1;
250fb125
SC		 1283 if (dev1->offload_config != dev2->offload_config)
1284 return 1;
1285 if (dev1->offload_enabled != dev2->offload_enabled)
1286 return 1;
03383736
DB		 1287 if (dev1->queue_depth != dev2->queue_depth)
1288 return 1;
bd9244f7
ST		 1289 return 0;
1290}
1291
edd16368
SC		 1292/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1293 * and return needle location in *index. If scsi3addr matches, but not
1294 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1295 * location in *index.
1296 * In the case of a minor device attribute change, such as RAID level, just
1297 * return DEVICE_UPDATED, along with the updated device's location in index.
1298 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1299 */
1300static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1301 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1302 int *index)
1303{
1304 int i;
1305#define DEVICE_NOT_FOUND 0
1306#define DEVICE_CHANGED 1
1307#define DEVICE_SAME 2
bd9244f7 1308#define DEVICE_UPDATED 3
edd16368 1309 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1310 if (haystack[i] == NULL) /* previously removed. */
1311 continue;
edd16368
SC		 1312 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1313 *index = i;
bd9244f7
ST		 1314 if (device_is_the_same(needle, haystack[i])) {
1315 if (device_updated(needle, haystack[i]))
1316 return DEVICE_UPDATED;
edd16368 1317 return DEVICE_SAME;
bd9244f7 1318 } else {
9846590e
SC		 1319 /* Keep offline devices offline */
1320 if (needle->volume_offline)
1321 return DEVICE_NOT_FOUND;
edd16368 1322 return DEVICE_CHANGED;
bd9244f7 1323 }
edd16368
SC		 1324 }
1325 }
1326 *index = -1;
1327 return DEVICE_NOT_FOUND;
1328}
1329
9846590e
SC		 1330static void hpsa_monitor_offline_device(struct ctlr_info *h,
1331 unsigned char scsi3addr[])
1332{
1333 struct offline_device_entry *device;
1334 unsigned long flags;
1335
1336 /* Check to see if device is already on the list */
1337 spin_lock_irqsave(&h->offline_device_lock, flags);
1338 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1339 if (memcmp(device->scsi3addr, scsi3addr,
1340 sizeof(device->scsi3addr)) == 0) {
1341 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1342 return;
1343 }
1344 }
1345 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1346
1347 /* Device is not on the list, add it. */
1348 device = kmalloc(sizeof(*device), GFP_KERNEL);
1349 if (!device) {
1350 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1351 return;
1352 }
1353 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1354 spin_lock_irqsave(&h->offline_device_lock, flags);
1355 list_add_tail(&device->offline_list, &h->offline_device_list);
1356 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1357}
1358
1359/* Print a message explaining various offline volume states */
1360static void hpsa_show_volume_status(struct ctlr_info *h,
1361 struct hpsa_scsi_dev_t *sd)
1362{
1363 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1364 dev_info(&h->pdev->dev,
1365 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1366 h->scsi_host->host_no,
1367 sd->bus, sd->target, sd->lun);
1368 switch (sd->volume_offline) {
1369 case HPSA_LV_OK:
1370 break;
1371 case HPSA_LV_UNDERGOING_ERASE:
1372 dev_info(&h->pdev->dev,
1373 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1374 h->scsi_host->host_no,
1375 sd->bus, sd->target, sd->lun);
1376 break;
1377 case HPSA_LV_UNDERGOING_RPI:
1378 dev_info(&h->pdev->dev,
1379 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1380 h->scsi_host->host_no,
1381 sd->bus, sd->target, sd->lun);
1382 break;
1383 case HPSA_LV_PENDING_RPI:
1384 dev_info(&h->pdev->dev,
1385 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1386 h->scsi_host->host_no,
1387 sd->bus, sd->target, sd->lun);
1388 break;
1389 case HPSA_LV_ENCRYPTED_NO_KEY:
1390 dev_info(&h->pdev->dev,
1391 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1392 h->scsi_host->host_no,
1393 sd->bus, sd->target, sd->lun);
1394 break;
1395 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1396 dev_info(&h->pdev->dev,
1397 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1398 h->scsi_host->host_no,
1399 sd->bus, sd->target, sd->lun);
1400 break;
1401 case HPSA_LV_UNDERGOING_ENCRYPTION:
1402 dev_info(&h->pdev->dev,
1403 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1404 h->scsi_host->host_no,
1405 sd->bus, sd->target, sd->lun);
1406 break;
1407 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1408 dev_info(&h->pdev->dev,
1409 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1410 h->scsi_host->host_no,
1411 sd->bus, sd->target, sd->lun);
1412 break;
1413 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1414 dev_info(&h->pdev->dev,
1415 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1416 h->scsi_host->host_no,
1417 sd->bus, sd->target, sd->lun);
1418 break;
1419 case HPSA_LV_PENDING_ENCRYPTION:
1420 dev_info(&h->pdev->dev,
1421 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1422 h->scsi_host->host_no,
1423 sd->bus, sd->target, sd->lun);
1424 break;
1425 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1426 dev_info(&h->pdev->dev,
1427 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1428 h->scsi_host->host_no,
1429 sd->bus, sd->target, sd->lun);
1430 break;
1431 }
1432}
1433
03383736
DB		 1434/*
1435 * Figure the list of physical drive pointers for a logical drive with
1436 * raid offload configured.
1437 */
1438static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1439 struct hpsa_scsi_dev_t *dev[], int ndevices,
1440 struct hpsa_scsi_dev_t *logical_drive)
1441{
1442 struct raid_map_data *map = &logical_drive->raid_map;
1443 struct raid_map_disk_data *dd = &map->data[0];
1444 int i, j;
1445 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1446 le16_to_cpu(map->metadata_disks_per_row);
1447 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1448 le16_to_cpu(map->layout_map_count) *
1449 total_disks_per_row;
1450 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1451 total_disks_per_row;
1452 int qdepth;
1453
1454 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1455 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1456
d604f533
WS		 1457 logical_drive->nphysical_disks = nraid_map_entries;
1458
03383736
DB		 1459 qdepth = 0;
1460 for (i = 0; i < nraid_map_entries; i++) {
1461 logical_drive->phys_disk[i] = NULL;
1462 if (!logical_drive->offload_config)
1463 continue;
1464 for (j = 0; j < ndevices; j++) {
1465 if (dev[j]->devtype != TYPE_DISK)
1466 continue;
1467 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1468 continue;
1469 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1470 continue;
1471
1472 logical_drive->phys_disk[i] = dev[j];
1473 if (i < nphys_disk)
1474 qdepth = min(h->nr_cmds, qdepth +
1475 logical_drive->phys_disk[i]->queue_depth);
1476 break;
1477 }
1478
1479 /*
1480 * This can happen if a physical drive is removed and
1481 * the logical drive is degraded. In that case, the RAID
1482 * map data will refer to a physical disk which isn't actually
1483 * present. And in that case offload_enabled should already
1484 * be 0, but we'll turn it off here just in case
1485 */
1486 if (!logical_drive->phys_disk[i]) {
1487 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1488 logical_drive->offload_to_be_enabled = 0;
1489 logical_drive->queue_depth = 8;
03383736
DB		 1490 }
1491 }
1492 if (nraid_map_entries)
1493 /*
1494 * This is correct for reads, too high for full stripe writes,
1495 * way too high for partial stripe writes
1496 */
1497 logical_drive->queue_depth = qdepth;
1498 else
1499 logical_drive->queue_depth = h->nr_cmds;
1500}
1501
1502static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1503 struct hpsa_scsi_dev_t *dev[], int ndevices)
1504{
1505 int i;
1506
1507 for (i = 0; i < ndevices; i++) {
1508 if (dev[i]->devtype != TYPE_DISK)
1509 continue;
1510 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1511 continue;
41ce4c35
SC		 1512
1513 /*
1514 * If offload is currently enabled, the RAID map and
1515 * phys_disk[] assignment *better* not be changing
1516 * and since it isn't changing, we do not need to
1517 * update it.
1518 */
1519 if (dev[i]->offload_enabled)
1520 continue;
1521
03383736
DB		 1522 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1523 }
1524}
1525
4967bd3e 1526static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1527 struct hpsa_scsi_dev_t *sd[], int nsds)
1528{
1529 /* sd contains scsi3 addresses and devtypes, and inquiry
1530 * data. This function takes what's in sd to be the current
1531 * reality and updates h->dev[] to reflect that reality.
1532 */
1533 int i, entry, device_change, changes = 0;
1534 struct hpsa_scsi_dev_t *csd;
1535 unsigned long flags;
1536 struct hpsa_scsi_dev_t **added, **removed;
1537 int nadded, nremoved;
1538 struct Scsi_Host *sh = NULL;
1539
cfe5badc
ST		 1540 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1541 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1542
1543 if (!added || !removed) {
1544 dev_warn(&h->pdev->dev, "out of memory in "
1545 "adjust_hpsa_scsi_table\n");
1546 goto free_and_out;
1547 }
1548
1549 spin_lock_irqsave(&h->devlock, flags);
1550
1551 /* find any devices in h->dev[] that are not in
1552 * sd[] and remove them from h->dev[], and for any
1553 * devices which have changed, remove the old device
1554 * info and add the new device info.
bd9244f7
ST		 1555 * If minor device attributes change, just update
1556 * the existing device structure.
edd16368
SC		 1557 */
1558 i = 0;
1559 nremoved = 0;
1560 nadded = 0;
1561 while (i < h->ndevices) {
1562 csd = h->dev[i];
1563 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1564 if (device_change == DEVICE_NOT_FOUND) {
1565 changes++;
1566 hpsa_scsi_remove_entry(h, hostno, i,
1567 removed, &nremoved);
1568 continue; /* remove ^^^, hence i not incremented */
1569 } else if (device_change == DEVICE_CHANGED) {
1570 changes++;
2a8ccf31
SC		 1571 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1572 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1573 /* Set it to NULL to prevent it from being freed
1574 * at the bottom of hpsa_update_scsi_devices()
1575 */
1576 sd[entry] = NULL;
bd9244f7
ST		 1577 } else if (device_change == DEVICE_UPDATED) {
1578 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1579 }
1580 i++;
1581 }
1582
1583 /* Now, make sure every device listed in sd[] is also
1584 * listed in h->dev[], adding them if they aren't found
1585 */
1586
1587 for (i = 0; i < nsds; i++) {
1588 if (!sd[i]) /* if already added above. */
1589 continue;
9846590e
SC		 1590
1591 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1592 * as the SCSI mid-layer does not handle such devices well.
1593 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1594 * at 160Hz, and prevents the system from coming up.
1595 */
1596 if (sd[i]->volume_offline) {
1597 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1598 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1599 continue;
1600 }
1601
edd16368
SC		 1602 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1603 h->ndevices, &entry);
1604 if (device_change == DEVICE_NOT_FOUND) {
1605 changes++;
1606 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1607 added, &nadded) != 0)
1608 break;
1609 sd[i] = NULL; /* prevent from being freed later. */
1610 } else if (device_change == DEVICE_CHANGED) {
1611 /* should never happen... */
1612 changes++;
1613 dev_warn(&h->pdev->dev,
1614 "device unexpectedly changed.\n");
1615 /* but if it does happen, we just ignore that device */
1616 }
1617 }
41ce4c35
SC		 1618 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1619
1620 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1621 * any logical drives that need it enabled.
1622 */
1623 for (i = 0; i < h->ndevices; i++)
1624 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1625
edd16368
SC		 1626 spin_unlock_irqrestore(&h->devlock, flags);
1627
9846590e
SC		 1628 /* Monitor devices which are in one of several NOT READY states to be
1629 * brought online later. This must be done without holding h->devlock,
1630 * so don't touch h->dev[]
1631 */
1632 for (i = 0; i < nsds; i++) {
1633 if (!sd[i]) /* if already added above. */
1634 continue;
1635 if (sd[i]->volume_offline)
1636 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1637 }
1638
edd16368
SC		 1639 /* Don't notify scsi mid layer of any changes the first time through
1640 * (or if there are no changes) scsi_scan_host will do it later the
1641 * first time through.
1642 */
1643 if (hostno == -1 || !changes)
1644 goto free_and_out;
1645
1646 sh = h->scsi_host;
1647 /* Notify scsi mid layer of any removed devices */
1648 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1649 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1650 struct scsi_device *sdev =
1651 scsi_device_lookup(sh, removed[i]->bus,
1652 removed[i]->target, removed[i]->lun);
1653 if (sdev != NULL) {
1654 scsi_remove_device(sdev);
1655 scsi_device_put(sdev);
1656 } else {
1657 /*
1658 * We don't expect to get here.
1659 * future cmds to this device will get selection
1660 * timeout as if the device was gone.
1661 */
0d96ef5f
WS		 1662 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1663 "didn't find device for removal.");
41ce4c35 1664 }
edd16368
SC		 1665 }
1666 kfree(removed[i]);
1667 removed[i] = NULL;
1668 }
1669
1670 /* Notify scsi mid layer of any added devices */
1671 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1672 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1673 continue;
edd16368
SC		 1674 if (scsi_add_device(sh, added[i]->bus,
1675 added[i]->target, added[i]->lun) == 0)
1676 continue;
0d96ef5f
WS		 1677 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1678 "addition failed, device not added.");
edd16368
SC		 1679 /* now we have to remove it from h->dev,
1680 * since it didn't get added to scsi mid layer
1681 */
1682 fixup_botched_add(h, added[i]);
105a3dbc 1683 added[i] = NULL;
edd16368
SC		 1684 }
1685
1686free_and_out:
1687 kfree(added);
1688 kfree(removed);
edd16368
SC		 1689}
1690
1691/*
9e03aa2f 1692 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1693 * Assume's h->devlock is held.
1694 */
1695static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1696 int bus, int target, int lun)
1697{
1698 int i;
1699 struct hpsa_scsi_dev_t *sd;
1700
1701 for (i = 0; i < h->ndevices; i++) {
1702 sd = h->dev[i];
1703 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1704 return sd;
1705 }
1706 return NULL;
1707}
1708
edd16368
SC		 1709static int hpsa_slave_alloc(struct scsi_device *sdev)
1710{
1711 struct hpsa_scsi_dev_t *sd;
1712 unsigned long flags;
1713 struct ctlr_info *h;
1714
1715 h = sdev_to_hba(sdev);
1716 spin_lock_irqsave(&h->devlock, flags);
1717 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1718 sdev_id(sdev), sdev->lun);
41ce4c35 1719 if (likely(sd)) {
03383736 1720 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1721 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1722 } else
1723 sdev->hostdata = NULL;
edd16368
SC		 1724 spin_unlock_irqrestore(&h->devlock, flags);
1725 return 0;
1726}
1727
41ce4c35
SC		 1728/* configure scsi device based on internal per-device structure */
1729static int hpsa_slave_configure(struct scsi_device *sdev)
1730{
1731 struct hpsa_scsi_dev_t *sd;
1732 int queue_depth;
1733
1734 sd = sdev->hostdata;
1735 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1736
1737 if (sd)
1738 queue_depth = sd->queue_depth != 0 ?
1739 sd->queue_depth : sdev->host->can_queue;
1740 else
1741 queue_depth = sdev->host->can_queue;
1742
1743 scsi_change_queue_depth(sdev, queue_depth);
1744
1745 return 0;
1746}
1747
edd16368
SC		 1748static void hpsa_slave_destroy(struct scsi_device *sdev)
1749{
bcc44255 1750 /* nothing to do. */
edd16368
SC		 1751}
1752
d9a729f3
WS		 1753static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1754{
1755 int i;
1756
1757 if (!h->ioaccel2_cmd_sg_list)
1758 return;
1759 for (i = 0; i < h->nr_cmds; i++) {
1760 kfree(h->ioaccel2_cmd_sg_list[i]);
1761 h->ioaccel2_cmd_sg_list[i] = NULL;
1762 }
1763 kfree(h->ioaccel2_cmd_sg_list);
1764 h->ioaccel2_cmd_sg_list = NULL;
1765}
1766
1767static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1768{
1769 int i;
1770
1771 if (h->chainsize <= 0)
1772 return 0;
1773
1774 h->ioaccel2_cmd_sg_list =
1775 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1776 GFP_KERNEL);
1777 if (!h->ioaccel2_cmd_sg_list)
1778 return -ENOMEM;
1779 for (i = 0; i < h->nr_cmds; i++) {
1780 h->ioaccel2_cmd_sg_list[i] =
1781 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1782 h->maxsgentries, GFP_KERNEL);
1783 if (!h->ioaccel2_cmd_sg_list[i])
1784 goto clean;
1785 }
1786 return 0;
1787
1788clean:
1789 hpsa_free_ioaccel2_sg_chain_blocks(h);
1790 return -ENOMEM;
1791}
1792
33a2ffce
SC		 1793static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1794{
1795 int i;
1796
1797 if (!h->cmd_sg_list)
1798 return;
1799 for (i = 0; i < h->nr_cmds; i++) {
1800 kfree(h->cmd_sg_list[i]);
1801 h->cmd_sg_list[i] = NULL;
1802 }
1803 kfree(h->cmd_sg_list);
1804 h->cmd_sg_list = NULL;
1805}
1806
105a3dbc 1807static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1808{
1809 int i;
1810
1811 if (h->chainsize <= 0)
1812 return 0;
1813
1814 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1815 GFP_KERNEL);
3d4e6af8
RE		 1816 if (!h->cmd_sg_list) {
1817 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1818 return -ENOMEM;
3d4e6af8 1819 }
33a2ffce
SC		 1820 for (i = 0; i < h->nr_cmds; i++) {
1821 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1822 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1823 if (!h->cmd_sg_list[i]) {
1824 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1825 goto clean;
3d4e6af8 1826 }
33a2ffce
SC		 1827 }
1828 return 0;
1829
1830clean:
1831 hpsa_free_sg_chain_blocks(h);
1832 return -ENOMEM;
1833}
1834
d9a729f3
WS		 1835static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1836 struct io_accel2_cmd *cp, struct CommandList *c)
1837{
1838 struct ioaccel2_sg_element *chain_block;
1839 u64 temp64;
1840 u32 chain_size;
1841
1842 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1843 chain_size = le32_to_cpu(cp->data_len);
1844 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1845 PCI_DMA_TODEVICE);
1846 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1847 /* prevent subsequent unmapping */
1848 cp->sg->address = 0;
1849 return -1;
1850 }
1851 cp->sg->address = cpu_to_le64(temp64);
1852 return 0;
1853}
1854
1855static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1856 struct io_accel2_cmd *cp)
1857{
1858 struct ioaccel2_sg_element *chain_sg;
1859 u64 temp64;
1860 u32 chain_size;
1861
1862 chain_sg = cp->sg;
1863 temp64 = le64_to_cpu(chain_sg->address);
1864 chain_size = le32_to_cpu(cp->data_len);
1865 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1866}
1867
e2bea6df 1868static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1869 struct CommandList *c)
1870{
1871 struct SGDescriptor *chain_sg, *chain_block;
1872 u64 temp64;
50a0decf 1873 u32 chain_len;
33a2ffce
SC		 1874
1875 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1876 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1877 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1878 chain_len = sizeof(*chain_sg) *
2b08b3e9 1879 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1880 chain_sg->Len = cpu_to_le32(chain_len);
1881 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1882 PCI_DMA_TODEVICE);
e2bea6df
SC		 1883 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1884 /* prevent subsequent unmapping */
50a0decf 1885 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1886 return -1;
1887 }
50a0decf 1888 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1889 return 0;
33a2ffce
SC		 1890}
1891
1892static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1893 struct CommandList *c)
1894{
1895 struct SGDescriptor *chain_sg;
33a2ffce 1896
50a0decf 1897 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1898 return;
1899
1900 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1901 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1902 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1903}
1904
a09c1441
ST		 1905
1906/* Decode the various types of errors on ioaccel2 path.
1907 * Return 1 for any error that should generate a RAID path retry.
1908 * Return 0 for errors that don't require a RAID path retry.
1909 */
1910static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1911 struct CommandList *c,
1912 struct scsi_cmnd *cmd,
1913 struct io_accel2_cmd *c2)
1914{
1915 int data_len;
a09c1441 1916 int retry = 0;
c40820d5 1917 u32 ioaccel2_resid = 0;
c349775e
ST		 1918
1919 switch (c2->error_data.serv_response) {
1920 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1921 switch (c2->error_data.status) {
1922 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1923 break;
1924 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 1925 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1926 if (c2->error_data.data_present !=
ee6b1889
SC		 1927 IOACCEL2_SENSE_DATA_PRESENT) {
1928 memset(cmd->sense_buffer, 0,
1929 SCSI_SENSE_BUFFERSIZE);
c349775e 1930 break;
ee6b1889 1931 }
c349775e
ST		 1932 /* copy the sense data */
1933 data_len = c2->error_data.sense_data_len;
1934 if (data_len > SCSI_SENSE_BUFFERSIZE)
1935 data_len = SCSI_SENSE_BUFFERSIZE;
1936 if (data_len > sizeof(c2->error_data.sense_data_buff))
1937 data_len =
1938 sizeof(c2->error_data.sense_data_buff);
1939 memcpy(cmd->sense_buffer,
1940 c2->error_data.sense_data_buff, data_len);
a09c1441 1941 retry = 1;
c349775e
ST		 1942 break;
1943 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 1944 retry = 1;
c349775e
ST		 1945 break;
1946 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 1947 retry = 1;
c349775e
ST		 1948 break;
1949 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1950 retry = 1;
c349775e
ST		 1951 break;
1952 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 1953 retry = 1;
c349775e
ST		 1954 break;
1955 default:
a09c1441 1956 retry = 1;
c349775e
ST		 1957 break;
1958 }
1959 break;
1960 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 1961 switch (c2->error_data.status) {
1962 case IOACCEL2_STATUS_SR_IO_ERROR:
1963 case IOACCEL2_STATUS_SR_IO_ABORTED:
1964 case IOACCEL2_STATUS_SR_OVERRUN:
1965 retry = 1;
1966 break;
1967 case IOACCEL2_STATUS_SR_UNDERRUN:
1968 cmd->result = (DID_OK << 16); /* host byte */
1969 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
1970 ioaccel2_resid = get_unaligned_le32(
1971 &c2->error_data.resid_cnt[0]);
1972 scsi_set_resid(cmd, ioaccel2_resid);
1973 break;
1974 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
1975 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
1976 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
1977 /* We will get an event from ctlr to trigger rescan */
1978 retry = 1;
1979 break;
1980 default:
1981 retry = 1;
c40820d5 1982 }
c349775e
ST		 1983 break;
1984 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1985 break;
1986 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1987 break;
1988 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 1989 retry = 1;
c349775e
ST		 1990 break;
1991 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 1992 break;
1993 default:
a09c1441 1994 retry = 1;
c349775e
ST		 1995 break;
1996 }
a09c1441
ST		 1997
1998 return retry; /* retry on raid path? */
c349775e
ST		 1999}
2000
a58e7e53
WS		 2001static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2002 struct CommandList *c)
2003{
d604f533
WS		 2004 bool do_wake = false;
2005
a58e7e53
WS		 2006 /*
2007 * Prevent the following race in the abort handler:
2008 *
2009 * 1. LLD is requested to abort a SCSI command
2010 * 2. The SCSI command completes
2011 * 3. The struct CommandList associated with step 2 is made available
2012 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2013 * 5. Abort handler follows scsi_cmnd->host_scribble and
2014 * finds struct CommandList and tries to aborts it
2015 * Now we have aborted the wrong command.
2016 *
d604f533
WS		 2017 * Reset c->scsi_cmd here so that the abort or reset handler will know
2018 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2019 * waiting for this command, and, if so, wake it.
2020 */
2021 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2022 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2023 if (c->abort_pending) {
d604f533 2024 do_wake = true;
a58e7e53 2025 c->abort_pending = false;
a58e7e53 2026 }
d604f533
WS		 2027 if (c->reset_pending) {
2028 unsigned long flags;
2029 struct hpsa_scsi_dev_t *dev;
2030
2031 /*
2032 * There appears to be a reset pending; lock the lock and
2033 * reconfirm. If so, then decrement the count of outstanding
2034 * commands and wake the reset command if this is the last one.
2035 */
2036 spin_lock_irqsave(&h->lock, flags);
2037 dev = c->reset_pending; /* Re-fetch under the lock. */
2038 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2039 do_wake = true;
2040 c->reset_pending = NULL;
2041 spin_unlock_irqrestore(&h->lock, flags);
2042 }
2043
2044 if (do_wake)
2045 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2046}
2047
73153fe5
WS		 2048static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2049 struct CommandList *c)
2050{
2051 hpsa_cmd_resolve_events(h, c);
2052 cmd_tagged_free(h, c);
2053}
2054
8a0ff92c
WS		 2055static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2056 struct CommandList *c, struct scsi_cmnd *cmd)
2057{
73153fe5 2058 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2059 cmd->scsi_done(cmd);
2060}
2061
2062static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2063{
2064 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2065 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2066}
2067
a58e7e53
WS		 2068static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2069{
2070 cmd->result = DID_ABORT << 16;
2071}
2072
2073static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2074 struct scsi_cmnd *cmd)
2075{
2076 hpsa_set_scsi_cmd_aborted(cmd);
2077 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2078 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2079 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2080}
2081
c349775e
ST		 2082static void process_ioaccel2_completion(struct ctlr_info *h,
2083 struct CommandList *c, struct scsi_cmnd *cmd,
2084 struct hpsa_scsi_dev_t *dev)
2085{
2086 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2087
2088 /* check for good status */
2089 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2090 c2->error_data.status == 0))
2091 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2092
8a0ff92c
WS		 2093 /*
2094 * Any RAID offload error results in retry which will use
c349775e
ST		 2095 * the normal I/O path so the controller can handle whatever's
2096 * wrong.
2097 */
2098 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
2099 c2->error_data.serv_response ==
2100 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2101 if (c2->error_data.status ==
2102 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2103 dev->offload_enabled = 0;
8a0ff92c
WS		 2104
2105 return hpsa_retry_cmd(h, c);
a09c1441 2106 }
080ef1cc
DB		 2107
2108 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2109 return hpsa_retry_cmd(h, c);
080ef1cc 2110
8a0ff92c 2111 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2112}
2113
9437ac43
SC		 2114/* Returns 0 on success, < 0 otherwise. */
2115static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2116 struct CommandList *cp)
2117{
2118 u8 tmf_status = cp->err_info->ScsiStatus;
2119
2120 switch (tmf_status) {
2121 case CISS_TMF_COMPLETE:
2122 /*
2123 * CISS_TMF_COMPLETE never happens, instead,
2124 * ei->CommandStatus == 0 for this case.
2125 */
2126 case CISS_TMF_SUCCESS:
2127 return 0;
2128 case CISS_TMF_INVALID_FRAME:
2129 case CISS_TMF_NOT_SUPPORTED:
2130 case CISS_TMF_FAILED:
2131 case CISS_TMF_WRONG_LUN:
2132 case CISS_TMF_OVERLAPPED_TAG:
2133 break;
2134 default:
2135 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2136 tmf_status);
2137 break;
2138 }
2139 return -tmf_status;
2140}
2141
1fb011fb 2142static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2143{
2144 struct scsi_cmnd *cmd;
2145 struct ctlr_info *h;
2146 struct ErrorInfo *ei;
283b4a9b 2147 struct hpsa_scsi_dev_t *dev;
d9a729f3 2148 struct io_accel2_cmd *c2;
edd16368 2149
9437ac43
SC		 2150 u8 sense_key;
2151 u8 asc; /* additional sense code */
2152 u8 ascq; /* additional sense code qualifier */
db111e18 2153 unsigned long sense_data_size;
edd16368
SC		 2154
2155 ei = cp->err_info;
7fa3030c 2156 cmd = cp->scsi_cmd;
edd16368 2157 h = cp->h;
283b4a9b 2158 dev = cmd->device->hostdata;
d9a729f3 2159 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2160
2161 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2162 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2163 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2164 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2165
d9a729f3
WS		 2166 if ((cp->cmd_type == CMD_IOACCEL2) &&
2167 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2168 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2169
edd16368
SC		 2170 cmd->result = (DID_OK << 16); /* host byte */
2171 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2172
03383736
DB		 2173 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2174 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2175
25163bd5
WS		 2176 /*
2177 * We check for lockup status here as it may be set for
2178 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2179 * fail_all_oustanding_cmds()
2180 */
2181 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2182 /* DID_NO_CONNECT will prevent a retry */
2183 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2184 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2185 }
2186
d604f533
WS		 2187 if ((unlikely(hpsa_is_pending_event(cp)))) {
2188 if (cp->reset_pending)
2189 return hpsa_cmd_resolve_and_free(h, cp);
2190 if (cp->abort_pending)
2191 return hpsa_cmd_abort_and_free(h, cp, cmd);
2192 }
2193
c349775e
ST		 2194 if (cp->cmd_type == CMD_IOACCEL2)
2195 return process_ioaccel2_completion(h, cp, cmd, dev);
2196
6aa4c361 2197 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2198 if (ei->CommandStatus == 0)
2199 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2200
e1f7de0c
MG		 2201 /* For I/O accelerator commands, copy over some fields to the normal
2202 * CISS header used below for error handling.
2203 */
2204 if (cp->cmd_type == CMD_IOACCEL1) {
2205 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2206 cp->Header.SGList = scsi_sg_count(cmd);
2207 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2208 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2209 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2210 cp->Header.tag = c->tag;
e1f7de0c
MG		 2211 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2212 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2213
2214 /* Any RAID offload error results in retry which will use
2215 * the normal I/O path so the controller can handle whatever's
2216 * wrong.
2217 */
2218 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2219 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2220 dev->offload_enabled = 0;
d604f533 2221 return hpsa_retry_cmd(h, cp);
283b4a9b 2222 }
e1f7de0c
MG		 2223 }
2224
edd16368
SC		 2225 /* an error has occurred */
2226 switch (ei->CommandStatus) {
2227
2228 case CMD_TARGET_STATUS:
9437ac43
SC		 2229 cmd->result |= ei->ScsiStatus;
2230 /* copy the sense data */
2231 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2232 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2233 else
2234 sense_data_size = sizeof(ei->SenseInfo);
2235 if (ei->SenseLen < sense_data_size)
2236 sense_data_size = ei->SenseLen;
2237 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2238 if (ei->ScsiStatus)
2239 decode_sense_data(ei->SenseInfo, sense_data_size,
2240 &sense_key, &asc, &ascq);
edd16368 2241 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2242 if (sense_key == ABORTED_COMMAND) {
2e311fba 2243 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2244 break;
2245 }
edd16368
SC		 2246 break;
2247 }
edd16368
SC		 2248 /* Problem was not a check condition
2249 * Pass it up to the upper layers...
2250 */
2251 if (ei->ScsiStatus) {
2252 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2253 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2254 "Returning result: 0x%x\n",
2255 cp, ei->ScsiStatus,
2256 sense_key, asc, ascq,
2257 cmd->result);
2258 } else { /* scsi status is zero??? How??? */
2259 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2260 "Returning no connection.\n", cp),
2261
2262 /* Ordinarily, this case should never happen,
2263 * but there is a bug in some released firmware
2264 * revisions that allows it to happen if, for
2265 * example, a 4100 backplane loses power and
2266 * the tape drive is in it. We assume that
2267 * it's a fatal error of some kind because we
2268 * can't show that it wasn't. We will make it
2269 * look like selection timeout since that is
2270 * the most common reason for this to occur,
2271 * and it's severe enough.
2272 */
2273
2274 cmd->result = DID_NO_CONNECT << 16;
2275 }
2276 break;
2277
2278 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2279 break;
2280 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2281 dev_warn(&h->pdev->dev,
2282 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2283 break;
2284 case CMD_INVALID: {
2285 /* print_bytes(cp, sizeof(*cp), 1, 0);
2286 print_cmd(cp); */
2287 /* We get CMD_INVALID if you address a non-existent device
2288 * instead of a selection timeout (no response). You will
2289 * see this if you yank out a drive, then try to access it.
2290 * This is kind of a shame because it means that any other
2291 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2292 * missing target. */
2293 cmd->result = DID_NO_CONNECT << 16;
2294 }
2295 break;
2296 case CMD_PROTOCOL_ERR:
256d0eaa 2297 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2298 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2299 cp->Request.CDB);
edd16368
SC		 2300 break;
2301 case CMD_HARDWARE_ERR:
2302 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2303 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2304 cp->Request.CDB);
edd16368
SC		 2305 break;
2306 case CMD_CONNECTION_LOST:
2307 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2308 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2309 cp->Request.CDB);
edd16368
SC		 2310 break;
2311 case CMD_ABORTED:
a58e7e53
WS		 2312 /* Return now to avoid calling scsi_done(). */
2313 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2314 case CMD_ABORT_FAILED:
2315 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2316 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2317 cp->Request.CDB);
edd16368
SC		 2318 break;
2319 case CMD_UNSOLICITED_ABORT:
f6e76055 2320 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2321 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2322 cp->Request.CDB);
edd16368
SC		 2323 break;
2324 case CMD_TIMEOUT:
2325 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2326 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2327 cp->Request.CDB);
edd16368 2328 break;
1d5e2ed0
SC		 2329 case CMD_UNABORTABLE:
2330 cmd->result = DID_ERROR << 16;
2331 dev_warn(&h->pdev->dev, "Command unabortable\n");
2332 break;
9437ac43
SC		 2333 case CMD_TMF_STATUS:
2334 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2335 cmd->result = DID_ERROR << 16;
2336 break;
283b4a9b
SC		 2337 case CMD_IOACCEL_DISABLED:
2338 /* This only handles the direct pass-through case since RAID
2339 * offload is handled above. Just attempt a retry.
2340 */
2341 cmd->result = DID_SOFT_ERROR << 16;
2342 dev_warn(&h->pdev->dev,
2343 "cp %p had HP SSD Smart Path error\n", cp);
2344 break;
edd16368
SC		 2345 default:
2346 cmd->result = DID_ERROR << 16;
2347 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2348 cp, ei->CommandStatus);
2349 }
8a0ff92c
WS		 2350
2351 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2352}
2353
edd16368
SC		 2354static void hpsa_pci_unmap(struct pci_dev *pdev,
2355 struct CommandList *c, int sg_used, int data_direction)
2356{
2357 int i;
edd16368 2358
50a0decf
SC		 2359 for (i = 0; i < sg_used; i++)
2360 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2361 le32_to_cpu(c->SG[i].Len),
2362 data_direction);
edd16368
SC		 2363}
2364
a2dac136 2365static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2366 struct CommandList *cp,
2367 unsigned char *buf,
2368 size_t buflen,
2369 int data_direction)
2370{
01a02ffc 2371 u64 addr64;
edd16368
SC		 2372
2373 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2374 cp->Header.SGList = 0;
50a0decf 2375 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2376 return 0;
edd16368
SC		 2377 }
2378
50a0decf 2379 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2380 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2381 /* Prevent subsequent unmap of something never mapped */
eceaae18 2382 cp->Header.SGList = 0;
50a0decf 2383 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2384 return -1;
eceaae18 2385 }
50a0decf
SC		 2386 cp->SG[0].Addr = cpu_to_le64(addr64);
2387 cp->SG[0].Len = cpu_to_le32(buflen);
2388 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2389 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2390 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2391 return 0;
edd16368
SC		 2392}
2393
25163bd5
WS		 2394#define NO_TIMEOUT ((unsigned long) -1)
2395#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2396static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2397 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2398{
2399 DECLARE_COMPLETION_ONSTACK(wait);
2400
2401 c->waiting = &wait;
25163bd5
WS		 2402 __enqueue_cmd_and_start_io(h, c, reply_queue);
2403 if (timeout_msecs == NO_TIMEOUT) {
2404 /* TODO: get rid of this no-timeout thing */
2405 wait_for_completion_io(&wait);
2406 return IO_OK;
2407 }
2408 if (!wait_for_completion_io_timeout(&wait,
2409 msecs_to_jiffies(timeout_msecs))) {
2410 dev_warn(&h->pdev->dev, "Command timed out.\n");
2411 return -ETIMEDOUT;
2412 }
2413 return IO_OK;
2414}
2415
2416static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2417 int reply_queue, unsigned long timeout_msecs)
2418{
2419 if (unlikely(lockup_detected(h))) {
2420 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2421 return IO_OK;
2422 }
2423 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2424}
2425
094963da
SC		 2426static u32 lockup_detected(struct ctlr_info *h)
2427{
2428 int cpu;
2429 u32 rc, *lockup_detected;
2430
2431 cpu = get_cpu();
2432 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2433 rc = *lockup_detected;
2434 put_cpu();
2435 return rc;
2436}
2437
9c2fc160 2438#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2439static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2440 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2441{
9c2fc160 2442 int backoff_time = 10, retry_count = 0;
25163bd5 2443 int rc;
edd16368
SC		 2444
2445 do {
7630abd0 2446 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2447 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2448 timeout_msecs);
2449 if (rc)
2450 break;
edd16368 2451 retry_count++;
9c2fc160
SC		 2452 if (retry_count > 3) {
2453 msleep(backoff_time);
2454 if (backoff_time < 1000)
2455 backoff_time *= 2;
2456 }
852af20a 2457 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2458 check_for_busy(h, c)) &&
2459 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2460 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2461 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2462 rc = -EIO;
2463 return rc;
edd16368
SC		 2464}
2465
d1e8beac
SC		 2466static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2467 struct CommandList *c)
edd16368 2468{
d1e8beac
SC		 2469 const u8 *cdb = c->Request.CDB;
2470 const u8 *lun = c->Header.LUN.LunAddrBytes;
2471
2472 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2473 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2474 txt, lun[0], lun[1], lun[2], lun[3],
2475 lun[4], lun[5], lun[6], lun[7],
2476 cdb[0], cdb[1], cdb[2], cdb[3],
2477 cdb[4], cdb[5], cdb[6], cdb[7],
2478 cdb[8], cdb[9], cdb[10], cdb[11],
2479 cdb[12], cdb[13], cdb[14], cdb[15]);
2480}
2481
2482static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2483 struct CommandList *cp)
2484{
2485 const struct ErrorInfo *ei = cp->err_info;
edd16368 2486 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2487 u8 sense_key, asc, ascq;
2488 int sense_len;
edd16368 2489
edd16368
SC		 2490 switch (ei->CommandStatus) {
2491 case CMD_TARGET_STATUS:
9437ac43
SC		 2492 if (ei->SenseLen > sizeof(ei->SenseInfo))
2493 sense_len = sizeof(ei->SenseInfo);
2494 else
2495 sense_len = ei->SenseLen;
2496 decode_sense_data(ei->SenseInfo, sense_len,
2497 &sense_key, &asc, &ascq);
d1e8beac
SC		 2498 hpsa_print_cmd(h, "SCSI status", cp);
2499 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2500 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2501 sense_key, asc, ascq);
d1e8beac 2502 else
9437ac43 2503 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2504 if (ei->ScsiStatus == 0)
2505 dev_warn(d, "SCSI status is abnormally zero. "
2506 "(probably indicates selection timeout "
2507 "reported incorrectly due to a known "
2508 "firmware bug, circa July, 2001.)\n");
2509 break;
2510 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2511 break;
2512 case CMD_DATA_OVERRUN:
d1e8beac 2513 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2514 break;
2515 case CMD_INVALID: {
2516 /* controller unfortunately reports SCSI passthru's
2517 * to non-existent targets as invalid commands.
2518 */
d1e8beac
SC		 2519 hpsa_print_cmd(h, "invalid command", cp);
2520 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2521 }
2522 break;
2523 case CMD_PROTOCOL_ERR:
d1e8beac 2524 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2525 break;
2526 case CMD_HARDWARE_ERR:
d1e8beac 2527 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2528 break;
2529 case CMD_CONNECTION_LOST:
d1e8beac 2530 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2531 break;
2532 case CMD_ABORTED:
d1e8beac 2533 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2534 break;
2535 case CMD_ABORT_FAILED:
d1e8beac 2536 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2537 break;
2538 case CMD_UNSOLICITED_ABORT:
d1e8beac 2539 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2540 break;
2541 case CMD_TIMEOUT:
d1e8beac 2542 hpsa_print_cmd(h, "timed out", cp);
edd16368 2543 break;
1d5e2ed0 2544 case CMD_UNABORTABLE:
d1e8beac 2545 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2546 break;
25163bd5
WS		 2547 case CMD_CTLR_LOCKUP:
2548 hpsa_print_cmd(h, "controller lockup detected", cp);
2549 break;
edd16368 2550 default:
d1e8beac
SC		 2551 hpsa_print_cmd(h, "unknown status", cp);
2552 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2553 ei->CommandStatus);
2554 }
2555}
2556
2557static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2558 u16 page, unsigned char *buf,
edd16368
SC		 2559 unsigned char bufsize)
2560{
2561 int rc = IO_OK;
2562 struct CommandList *c;
2563 struct ErrorInfo *ei;
2564
45fcb86e 2565 c = cmd_alloc(h);
edd16368 2566
a2dac136
SC		 2567 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2568 page, scsi3addr, TYPE_CMD)) {
2569 rc = -1;
2570 goto out;
2571 }
25163bd5
WS		 2572 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2573 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2574 if (rc)
2575 goto out;
edd16368
SC		 2576 ei = c->err_info;
2577 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2578 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2579 rc = -1;
2580 }
a2dac136 2581out:
45fcb86e 2582 cmd_free(h, c);
edd16368
SC		 2583 return rc;
2584}
2585
316b221a
SC		 2586static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2587 unsigned char *scsi3addr, unsigned char page,
2588 struct bmic_controller_parameters *buf, size_t bufsize)
2589{
2590 int rc = IO_OK;
2591 struct CommandList *c;
2592 struct ErrorInfo *ei;
2593
45fcb86e 2594 c = cmd_alloc(h);
316b221a
SC		 2595 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2596 page, scsi3addr, TYPE_CMD)) {
2597 rc = -1;
2598 goto out;
2599 }
25163bd5
WS		 2600 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2601 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2602 if (rc)
2603 goto out;
316b221a
SC		 2604 ei = c->err_info;
2605 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2606 hpsa_scsi_interpret_error(h, c);
2607 rc = -1;
2608 }
2609out:
45fcb86e 2610 cmd_free(h, c);
316b221a 2611 return rc;
bf43caf3 2612}
316b221a 2613
bf711ac6 2614static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2615 u8 reset_type, int reply_queue)
edd16368
SC		 2616{
2617 int rc = IO_OK;
2618 struct CommandList *c;
2619 struct ErrorInfo *ei;
2620
45fcb86e 2621 c = cmd_alloc(h);
edd16368 2622
edd16368 2623
a2dac136 2624 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2625 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2626 scsi3addr, TYPE_MSG);
2627 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2628 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2629 if (rc) {
2630 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2631 goto out;
2632 }
edd16368
SC		 2633 /* no unmap needed here because no data xfer. */
2634
2635 ei = c->err_info;
2636 if (ei->CommandStatus != 0) {
d1e8beac 2637 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2638 rc = -1;
2639 }
25163bd5 2640out:
45fcb86e 2641 cmd_free(h, c);
edd16368
SC		 2642 return rc;
2643}
2644
d604f533
WS		 2645static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2646 struct hpsa_scsi_dev_t *dev,
2647 unsigned char *scsi3addr)
2648{
2649 int i;
2650 bool match = false;
2651 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2652 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2653
2654 if (hpsa_is_cmd_idle(c))
2655 return false;
2656
2657 switch (c->cmd_type) {
2658 case CMD_SCSI:
2659 case CMD_IOCTL_PEND:
2660 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2661 sizeof(c->Header.LUN.LunAddrBytes));
2662 break;
2663
2664 case CMD_IOACCEL1:
2665 case CMD_IOACCEL2:
2666 if (c->phys_disk == dev) {
2667 /* HBA mode match */
2668 match = true;
2669 } else {
2670 /* Possible RAID mode -- check each phys dev. */
2671 /* FIXME: Do we need to take out a lock here? If
2672 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2673 * instead. */
2674 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2675 /* FIXME: an alternate test might be
2676 *
2677 * match = dev->phys_disk[i]->ioaccel_handle
2678 * == c2->scsi_nexus; */
2679 match = dev->phys_disk[i] == c->phys_disk;
2680 }
2681 }
2682 break;
2683
2684 case IOACCEL2_TMF:
2685 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2686 match = dev->phys_disk[i]->ioaccel_handle ==
2687 le32_to_cpu(ac->it_nexus);
2688 }
2689 break;
2690
2691 case 0: /* The command is in the middle of being initialized. */
2692 match = false;
2693 break;
2694
2695 default:
2696 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2697 c->cmd_type);
2698 BUG();
2699 }
2700
2701 return match;
2702}
2703
2704static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2705 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2706{
2707 int i;
2708 int rc = 0;
2709
2710 /* We can really only handle one reset at a time */
2711 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2712 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2713 return -EINTR;
2714 }
2715
2716 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2717
2718 for (i = 0; i < h->nr_cmds; i++) {
2719 struct CommandList *c = h->cmd_pool + i;
2720 int refcount = atomic_inc_return(&c->refcount);
2721
2722 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2723 unsigned long flags;
2724
2725 /*
2726 * Mark the target command as having a reset pending,
2727 * then lock a lock so that the command cannot complete
2728 * while we're considering it. If the command is not
2729 * idle then count it; otherwise revoke the event.
2730 */
2731 c->reset_pending = dev;
2732 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2733 if (!hpsa_is_cmd_idle(c))
2734 atomic_inc(&dev->reset_cmds_out);
2735 else
2736 c->reset_pending = NULL;
2737 spin_unlock_irqrestore(&h->lock, flags);
2738 }
2739
2740 cmd_free(h, c);
2741 }
2742
2743 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2744 if (!rc)
2745 wait_event(h->event_sync_wait_queue,
2746 atomic_read(&dev->reset_cmds_out) == 0 ||
2747 lockup_detected(h));
2748
2749 if (unlikely(lockup_detected(h))) {
2750 dev_warn(&h->pdev->dev,
2751 "Controller lockup detected during reset wait\n");
2752 mutex_unlock(&h->reset_mutex);
2753 rc = -ENODEV;
2754 }
2755
2756 if (unlikely(rc))
2757 atomic_set(&dev->reset_cmds_out, 0);
2758
2759 mutex_unlock(&h->reset_mutex);
2760 return rc;
2761}
2762
edd16368
SC		 2763static void hpsa_get_raid_level(struct ctlr_info *h,
2764 unsigned char *scsi3addr, unsigned char *raid_level)
2765{
2766 int rc;
2767 unsigned char *buf;
2768
2769 *raid_level = RAID_UNKNOWN;
2770 buf = kzalloc(64, GFP_KERNEL);
2771 if (!buf)
2772 return;
b7bb24eb 2773 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2774 if (rc == 0)
2775 *raid_level = buf[8];
2776 if (*raid_level > RAID_UNKNOWN)
2777 *raid_level = RAID_UNKNOWN;
2778 kfree(buf);
2779 return;
2780}
2781
283b4a9b
SC		 2782#define HPSA_MAP_DEBUG
2783#ifdef HPSA_MAP_DEBUG
2784static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2785 struct raid_map_data *map_buff)
2786{
2787 struct raid_map_disk_data *dd = &map_buff->data[0];
2788 int map, row, col;
2789 u16 map_cnt, row_cnt, disks_per_row;
2790
2791 if (rc != 0)
2792 return;
2793
2ba8bfc8
SC		 2794 /* Show details only if debugging has been activated. */
2795 if (h->raid_offload_debug < 2)
2796 return;
2797
283b4a9b
SC		 2798 dev_info(&h->pdev->dev, "structure_size = %u\n",
2799 le32_to_cpu(map_buff->structure_size));
2800 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2801 le32_to_cpu(map_buff->volume_blk_size));
2802 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2803 le64_to_cpu(map_buff->volume_blk_cnt));
2804 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2805 map_buff->phys_blk_shift);
2806 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2807 map_buff->parity_rotation_shift);
2808 dev_info(&h->pdev->dev, "strip_size = %u\n",
2809 le16_to_cpu(map_buff->strip_size));
2810 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2811 le64_to_cpu(map_buff->disk_starting_blk));
2812 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2813 le64_to_cpu(map_buff->disk_blk_cnt));
2814 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2815 le16_to_cpu(map_buff->data_disks_per_row));
2816 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2817 le16_to_cpu(map_buff->metadata_disks_per_row));
2818 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2819 le16_to_cpu(map_buff->row_cnt));
2820 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2821 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2822 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2823 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2824 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2825 le16_to_cpu(map_buff->flags) &
2826 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2827 dev_info(&h->pdev->dev, "dekindex = %u\n",
2828 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2829 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2830 for (map = 0; map < map_cnt; map++) {
2831 dev_info(&h->pdev->dev, "Map%u:\n", map);
2832 row_cnt = le16_to_cpu(map_buff->row_cnt);
2833 for (row = 0; row < row_cnt; row++) {
2834 dev_info(&h->pdev->dev, " Row%u:\n", row);
2835 disks_per_row =
2836 le16_to_cpu(map_buff->data_disks_per_row);
2837 for (col = 0; col < disks_per_row; col++, dd++)
2838 dev_info(&h->pdev->dev,
2839 " D%02u: h=0x%04x xor=%u,%u\n",
2840 col, dd->ioaccel_handle,
2841 dd->xor_mult[0], dd->xor_mult[1]);
2842 disks_per_row =
2843 le16_to_cpu(map_buff->metadata_disks_per_row);
2844 for (col = 0; col < disks_per_row; col++, dd++)
2845 dev_info(&h->pdev->dev,
2846 " M%02u: h=0x%04x xor=%u,%u\n",
2847 col, dd->ioaccel_handle,
2848 dd->xor_mult[0], dd->xor_mult[1]);
2849 }
2850 }
2851}
2852#else
2853static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2854 __attribute__((unused)) int rc,
2855 __attribute__((unused)) struct raid_map_data *map_buff)
2856{
2857}
2858#endif
2859
2860static int hpsa_get_raid_map(struct ctlr_info *h,
2861 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2862{
2863 int rc = 0;
2864 struct CommandList *c;
2865 struct ErrorInfo *ei;
2866
45fcb86e 2867 c = cmd_alloc(h);
bf43caf3 2868
283b4a9b
SC		 2869 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2870 sizeof(this_device->raid_map), 0,
2871 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2872 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2873 cmd_free(h, c);
2874 return -1;
283b4a9b 2875 }
25163bd5
WS		 2876 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2877 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2878 if (rc)
2879 goto out;
283b4a9b
SC		 2880 ei = c->err_info;
2881 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2882 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2883 rc = -1;
2884 goto out;
283b4a9b 2885 }
45fcb86e 2886 cmd_free(h, c);
283b4a9b
SC		 2887
2888 /* @todo in the future, dynamically allocate RAID map memory */
2889 if (le32_to_cpu(this_device->raid_map.structure_size) >
2890 sizeof(this_device->raid_map)) {
2891 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2892 rc = -1;
2893 }
2894 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2895 return rc;
25163bd5
WS		 2896out:
2897 cmd_free(h, c);
2898 return rc;
283b4a9b
SC		 2899}
2900
03383736
DB		 2901static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2902 unsigned char scsi3addr[], u16 bmic_device_index,
2903 struct bmic_identify_physical_device *buf, size_t bufsize)
2904{
2905 int rc = IO_OK;
2906 struct CommandList *c;
2907 struct ErrorInfo *ei;
2908
2909 c = cmd_alloc(h);
2910 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2911 0, RAID_CTLR_LUNID, TYPE_CMD);
2912 if (rc)
2913 goto out;
2914
2915 c->Request.CDB[2] = bmic_device_index & 0xff;
2916 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2917
25163bd5
WS		 2918 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2919 NO_TIMEOUT);
03383736
DB		 2920 ei = c->err_info;
2921 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2922 hpsa_scsi_interpret_error(h, c);
2923 rc = -1;
2924 }
2925out:
2926 cmd_free(h, c);
2927 return rc;
2928}
2929
1b70150a
SC		 2930static int hpsa_vpd_page_supported(struct ctlr_info *h,
2931 unsigned char scsi3addr[], u8 page)
2932{
2933 int rc;
2934 int i;
2935 int pages;
2936 unsigned char *buf, bufsize;
2937
2938 buf = kzalloc(256, GFP_KERNEL);
2939 if (!buf)
2940 return 0;
2941
2942 /* Get the size of the page list first */
2943 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2944 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2945 buf, HPSA_VPD_HEADER_SZ);
2946 if (rc != 0)
2947 goto exit_unsupported;
2948 pages = buf[3];
2949 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2950 bufsize = pages + HPSA_VPD_HEADER_SZ;
2951 else
2952 bufsize = 255;
2953
2954 /* Get the whole VPD page list */
2955 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2956 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2957 buf, bufsize);
2958 if (rc != 0)
2959 goto exit_unsupported;
2960
2961 pages = buf[3];
2962 for (i = 1; i <= pages; i++)
2963 if (buf[3 + i] == page)
2964 goto exit_supported;
2965exit_unsupported:
2966 kfree(buf);
2967 return 0;
2968exit_supported:
2969 kfree(buf);
2970 return 1;
2971}
2972
283b4a9b
SC		 2973static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2974 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2975{
2976 int rc;
2977 unsigned char *buf;
2978 u8 ioaccel_status;
2979
2980 this_device->offload_config = 0;
2981 this_device->offload_enabled = 0;
41ce4c35 2982 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2983
2984 buf = kzalloc(64, GFP_KERNEL);
2985 if (!buf)
2986 return;
1b70150a
SC		 2987 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2988 goto out;
283b4a9b 2989 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2990 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2991 if (rc != 0)
2992 goto out;
2993
2994#define IOACCEL_STATUS_BYTE 4
2995#define OFFLOAD_CONFIGURED_BIT 0x01
2996#define OFFLOAD_ENABLED_BIT 0x02
2997 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2998 this_device->offload_config =
2999 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3000 if (this_device->offload_config) {
3001 this_device->offload_enabled =
3002 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3003 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3004 this_device->offload_enabled = 0;
3005 }
41ce4c35 3006 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3007out:
3008 kfree(buf);
3009 return;
3010}
3011
edd16368
SC		 3012/* Get the device id from inquiry page 0x83 */
3013static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3014 unsigned char *device_id, int buflen)
3015{
3016 int rc;
3017 unsigned char *buf;
3018
3019 if (buflen > 16)
3020 buflen = 16;
3021 buf = kzalloc(64, GFP_KERNEL);
3022 if (!buf)
a84d794d 3023 return -ENOMEM;
b7bb24eb 3024 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3025 if (rc == 0)
3026 memcpy(device_id, &buf[8], buflen);
3027 kfree(buf);
3028 return rc != 0;
3029}
3030
3031static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3032 void *buf, int bufsize,
edd16368
SC		 3033 int extended_response)
3034{
3035 int rc = IO_OK;
3036 struct CommandList *c;
3037 unsigned char scsi3addr[8];
3038 struct ErrorInfo *ei;
3039
45fcb86e 3040 c = cmd_alloc(h);
bf43caf3 3041
e89c0ae7
SC		 3042 /* address the controller */
3043 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3044 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3045 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3046 rc = -1;
3047 goto out;
3048 }
edd16368
SC		 3049 if (extended_response)
3050 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3051 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3052 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3053 if (rc)
3054 goto out;
edd16368
SC		 3055 ei = c->err_info;
3056 if (ei->CommandStatus != 0 &&
3057 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3058 hpsa_scsi_interpret_error(h, c);
edd16368 3059 rc = -1;
283b4a9b 3060 } else {
03383736
DB		 3061 struct ReportLUNdata *rld = buf;
3062
3063 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3064 dev_err(&h->pdev->dev,
3065 "report luns requested format %u, got %u\n",
3066 extended_response,
03383736 3067 rld->extended_response_flag);
283b4a9b
SC		 3068 rc = -1;
3069 }
edd16368 3070 }
a2dac136 3071out:
45fcb86e 3072 cmd_free(h, c);
edd16368
SC		 3073 return rc;
3074}
3075
3076static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3077 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3078{
03383736
DB		 3079 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3080 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3081}
3082
3083static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3084 struct ReportLUNdata *buf, int bufsize)
3085{
3086 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3087}
3088
3089static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3090 int bus, int target, int lun)
3091{
3092 device->bus = bus;
3093 device->target = target;
3094 device->lun = lun;
3095}
3096
9846590e
SC		 3097/* Use VPD inquiry to get details of volume status */
3098static int hpsa_get_volume_status(struct ctlr_info *h,
3099 unsigned char scsi3addr[])
3100{
3101 int rc;
3102 int status;
3103 int size;
3104 unsigned char *buf;
3105
3106 buf = kzalloc(64, GFP_KERNEL);
3107 if (!buf)
3108 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3109
3110 /* Does controller have VPD for logical volume status? */
24a4b078 3111 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3112 goto exit_failed;
9846590e
SC		 3113
3114 /* Get the size of the VPD return buffer */
3115 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3116 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3117 if (rc != 0)
9846590e 3118 goto exit_failed;
9846590e
SC		 3119 size = buf[3];
3120
3121 /* Now get the whole VPD buffer */
3122 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3123 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3124 if (rc != 0)
9846590e 3125 goto exit_failed;
9846590e
SC		 3126 status = buf[4]; /* status byte */
3127
3128 kfree(buf);
3129 return status;
3130exit_failed:
3131 kfree(buf);
3132 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3133}
3134
3135/* Determine offline status of a volume.
3136 * Return either:
3137 * 0 (not offline)
67955ba3 3138 * 0xff (offline for unknown reasons)
9846590e
SC		 3139 * # (integer code indicating one of several NOT READY states
3140 * describing why a volume is to be kept offline)
3141 */
67955ba3 3142static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3143 unsigned char scsi3addr[])
3144{
3145 struct CommandList *c;
9437ac43
SC		 3146 unsigned char *sense;
3147 u8 sense_key, asc, ascq;
3148 int sense_len;
25163bd5 3149 int rc, ldstat = 0;
9846590e
SC		 3150 u16 cmd_status;
3151 u8 scsi_status;
3152#define ASC_LUN_NOT_READY 0x04
3153#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3154#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3155
3156 c = cmd_alloc(h);
bf43caf3 3157
9846590e 3158 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3159 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3160 if (rc) {
3161 cmd_free(h, c);
3162 return 0;
3163 }
9846590e 3164 sense = c->err_info->SenseInfo;
9437ac43
SC		 3165 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3166 sense_len = sizeof(c->err_info->SenseInfo);
3167 else
3168 sense_len = c->err_info->SenseLen;
3169 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3170 cmd_status = c->err_info->CommandStatus;
3171 scsi_status = c->err_info->ScsiStatus;
3172 cmd_free(h, c);
3173 /* Is the volume 'not ready'? */
3174 if (cmd_status != CMD_TARGET_STATUS ||
3175 scsi_status != SAM_STAT_CHECK_CONDITION ||
3176 sense_key != NOT_READY ||
3177 asc != ASC_LUN_NOT_READY) {
3178 return 0;
3179 }
3180
3181 /* Determine the reason for not ready state */
3182 ldstat = hpsa_get_volume_status(h, scsi3addr);
3183
3184 /* Keep volume offline in certain cases: */
3185 switch (ldstat) {
3186 case HPSA_LV_UNDERGOING_ERASE:
3187 case HPSA_LV_UNDERGOING_RPI:
3188 case HPSA_LV_PENDING_RPI:
3189 case HPSA_LV_ENCRYPTED_NO_KEY:
3190 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3191 case HPSA_LV_UNDERGOING_ENCRYPTION:
3192 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3193 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3194 return ldstat;
3195 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3196 /* If VPD status page isn't available,
3197 * use ASC/ASCQ to determine state
3198 */
3199 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3200 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3201 return ldstat;
3202 break;
3203 default:
3204 break;
3205 }
3206 return 0;
3207}
3208
9b5c48c2
SC		 3209/*
3210 * Find out if a logical device supports aborts by simply trying one.
3211 * Smart Array may claim not to support aborts on logical drives, but
3212 * if a MSA2000 * is connected, the drives on that will be presented
3213 * by the Smart Array as logical drives, and aborts may be sent to
3214 * those devices successfully. So the simplest way to find out is
3215 * to simply try an abort and see how the device responds.
3216 */
3217static int hpsa_device_supports_aborts(struct ctlr_info *h,
3218 unsigned char *scsi3addr)
3219{
3220 struct CommandList *c;
3221 struct ErrorInfo *ei;
3222 int rc = 0;
3223
3224 u64 tag = (u64) -1; /* bogus tag */
3225
3226 /* Assume that physical devices support aborts */
3227 if (!is_logical_dev_addr_mode(scsi3addr))
3228 return 1;
3229
3230 c = cmd_alloc(h);
bf43caf3 3231
9b5c48c2
SC		 3232 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3233 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3234 /* no unmap needed here because no data xfer. */
3235 ei = c->err_info;
3236 switch (ei->CommandStatus) {
3237 case CMD_INVALID:
3238 rc = 0;
3239 break;
3240 case CMD_UNABORTABLE:
3241 case CMD_ABORT_FAILED:
3242 rc = 1;
3243 break;
9437ac43
SC		 3244 case CMD_TMF_STATUS:
3245 rc = hpsa_evaluate_tmf_status(h, c);
3246 break;
9b5c48c2
SC		 3247 default:
3248 rc = 0;
3249 break;
3250 }
3251 cmd_free(h, c);
3252 return rc;
3253}
3254
edd16368 3255static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3256 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3257 unsigned char *is_OBDR_device)
edd16368 3258{
0b0e1d6c
SC		 3259
3260#define OBDR_SIG_OFFSET 43
3261#define OBDR_TAPE_SIG "$DR-10"
3262#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3263#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3264
ea6d3bc3 3265 unsigned char *inq_buff;
0b0e1d6c 3266 unsigned char *obdr_sig;
edd16368 3267
ea6d3bc3 3268 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3269 if (!inq_buff)
3270 goto bail_out;
3271
edd16368
SC		 3272 /* Do an inquiry to the device to see what it is. */
3273 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3274 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3275 /* Inquiry failed (msg printed already) */
3276 dev_err(&h->pdev->dev,
3277 "hpsa_update_device_info: inquiry failed\n");
3278 goto bail_out;
3279 }
3280
edd16368
SC		 3281 this_device->devtype = (inq_buff[0] & 0x1f);
3282 memcpy(this_device->scsi3addr, scsi3addr, 8);
3283 memcpy(this_device->vendor, &inq_buff[8],
3284 sizeof(this_device->vendor));
3285 memcpy(this_device->model, &inq_buff[16],
3286 sizeof(this_device->model));
edd16368
SC		 3287 memset(this_device->device_id, 0,
3288 sizeof(this_device->device_id));
3289 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3290 sizeof(this_device->device_id));
3291
3292 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3293 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3294 int volume_offline;
3295
edd16368 3296 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3297 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3298 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3299 volume_offline = hpsa_volume_offline(h, scsi3addr);
3300 if (volume_offline < 0 || volume_offline > 0xff)
3301 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3302 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3303 } else {
edd16368 3304 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3305 this_device->offload_config = 0;
3306 this_device->offload_enabled = 0;
41ce4c35 3307 this_device->offload_to_be_enabled = 0;
a3144e0b 3308 this_device->hba_ioaccel_enabled = 0;
9846590e 3309 this_device->volume_offline = 0;
03383736 3310 this_device->queue_depth = h->nr_cmds;
283b4a9b 3311 }
edd16368 3312
0b0e1d6c
SC		 3313 if (is_OBDR_device) {
3314 /* See if this is a One-Button-Disaster-Recovery device
3315 * by looking for "$DR-10" at offset 43 in inquiry data.
3316 */
3317 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3318 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3319 strncmp(obdr_sig, OBDR_TAPE_SIG,
3320 OBDR_SIG_LEN) == 0);
3321 }
edd16368
SC		 3322 kfree(inq_buff);
3323 return 0;
3324
3325bail_out:
3326 kfree(inq_buff);
3327 return 1;
3328}
3329
9b5c48c2
SC		 3330static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3331 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3332{
3333 unsigned long flags;
3334 int rc, entry;
3335 /*
3336 * See if this device supports aborts. If we already know
3337 * the device, we already know if it supports aborts, otherwise
3338 * we have to find out if it supports aborts by trying one.
3339 */
3340 spin_lock_irqsave(&h->devlock, flags);
3341 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3342 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3343 entry >= 0 && entry < h->ndevices) {
3344 dev->supports_aborts = h->dev[entry]->supports_aborts;
3345 spin_unlock_irqrestore(&h->devlock, flags);
3346 } else {
3347 spin_unlock_irqrestore(&h->devlock, flags);
3348 dev->supports_aborts =
3349 hpsa_device_supports_aborts(h, scsi3addr);
3350 if (dev->supports_aborts < 0)
3351 dev->supports_aborts = 0;
3352 }
3353}
3354
4f4eb9f1 3355static unsigned char *ext_target_model[] = {
edd16368
SC		 3356 "MSA2012",
3357 "MSA2024",
3358 "MSA2312",
3359 "MSA2324",
fda38518 3360 "P2000 G3 SAS",
e06c8e5c 3361 "MSA 2040 SAS",
edd16368
SC		 3362 NULL,
3363};
3364
4f4eb9f1 3365static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3366{
3367 int i;
3368
4f4eb9f1
ST		 3369 for (i = 0; ext_target_model[i]; i++)
3370 if (strncmp(device->model, ext_target_model[i],
3371 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3372 return 1;
3373 return 0;
3374}
3375
3376/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3377 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3378 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3379 * Logical drive target and lun are assigned at this time, but
3380 * physical device lun and target assignment are deferred (assigned
3381 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3382 */
3383static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3384 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3385{
1f310bde
SC		 3386 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3387
3388 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3389 /* physical device, target and lun filled in later */
edd16368 3390 if (is_hba_lunid(lunaddrbytes))
1f310bde 3391 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3392 else
1f310bde
SC		 3393 /* defer target, lun assignment for physical devices */
3394 hpsa_set_bus_target_lun(device, 2, -1, -1);
3395 return;
3396 }
3397 /* It's a logical device */
4f4eb9f1
ST		 3398 if (is_ext_target(h, device)) {
3399 /* external target way, put logicals on bus 1
1f310bde
SC		 3400 * and match target/lun numbers box
3401 * reports, other smart array, bus 0, target 0, match lunid
3402 */
3403 hpsa_set_bus_target_lun(device,
3404 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3405 return;
edd16368 3406 }
1f310bde 3407 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3408}
3409
3410/*
3411 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3412 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3413 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3414 * it for some reason. *tmpdevice is the target we're adding,
3415 * this_device is a pointer into the current element of currentsd[]
3416 * that we're building up in update_scsi_devices(), below.
3417 * lunzerobits is a bitmap that tracks which targets already have a
3418 * lun 0 assigned.
3419 * Returns 1 if an enclosure was added, 0 if not.
3420 */
4f4eb9f1 3421static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3422 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3423 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3424 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3425{
3426 unsigned char scsi3addr[8];
3427
1f310bde 3428 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3429 return 0; /* There is already a lun 0 on this target. */
3430
3431 if (!is_logical_dev_addr_mode(lunaddrbytes))
3432 return 0; /* It's the logical targets that may lack lun 0. */
3433
4f4eb9f1
ST		 3434 if (!is_ext_target(h, tmpdevice))
3435 return 0; /* Only external target devices have this problem. */
edd16368 3436
1f310bde 3437 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3438 return 0;
3439
c4f8a299 3440 memset(scsi3addr, 0, 8);
1f310bde 3441 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3442 if (is_hba_lunid(scsi3addr))
3443 return 0; /* Don't add the RAID controller here. */
3444
339b2b14
SC		 3445 if (is_scsi_rev_5(h))
3446 return 0; /* p1210m doesn't need to do this. */
3447
4f4eb9f1 3448 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3449 dev_warn(&h->pdev->dev, "Maximum number of external "
3450 "target devices exceeded. Check your hardware "
edd16368
SC		 3451 "configuration.");
3452 return 0;
3453 }
3454
0b0e1d6c 3455 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3456 return 0;
4f4eb9f1 3457 (*n_ext_target_devs)++;
1f310bde
SC		 3458 hpsa_set_bus_target_lun(this_device,
3459 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3460 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3461 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3462 return 1;
3463}
3464
54b6e9e9
ST		 3465/*
3466 * Get address of physical disk used for an ioaccel2 mode command:
3467 * 1. Extract ioaccel2 handle from the command.
3468 * 2. Find a matching ioaccel2 handle from list of physical disks.
3469 * 3. Return:
3470 * 1 and set scsi3addr to address of matching physical
3471 * 0 if no matching physical disk was found.
3472 */
3473static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3474 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3475{
41ce4c35
SC		 3476 struct io_accel2_cmd *c2 =
3477 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3478 unsigned long flags;
54b6e9e9 3479 int i;
54b6e9e9 3480
41ce4c35
SC		 3481 spin_lock_irqsave(&h->devlock, flags);
3482 for (i = 0; i < h->ndevices; i++)
3483 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3484 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3485 sizeof(h->dev[i]->scsi3addr));
3486 spin_unlock_irqrestore(&h->devlock, flags);
3487 return 1;
3488 }
3489 spin_unlock_irqrestore(&h->devlock, flags);
3490 return 0;
54b6e9e9 3491}
41ce4c35 3492
edd16368
SC		 3493/*
3494 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3495 * logdev. The number of luns in physdev and logdev are returned in
3496 * *nphysicals and *nlogicals, respectively.
3497 * Returns 0 on success, -1 otherwise.
3498 */
3499static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3500 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3501 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3502{
03383736 3503 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3504 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3505 return -1;
3506 }
03383736 3507 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3508 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3509 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3510 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3511 *nphysicals = HPSA_MAX_PHYS_LUN;
3512 }
03383736 3513 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3514 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3515 return -1;
3516 }
6df1e954 3517 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3518 /* Reject Logicals in excess of our max capability. */
3519 if (*nlogicals > HPSA_MAX_LUN) {
3520 dev_warn(&h->pdev->dev,
3521 "maximum logical LUNs (%d) exceeded. "
3522 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3523 *nlogicals - HPSA_MAX_LUN);
3524 *nlogicals = HPSA_MAX_LUN;
3525 }
3526 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3527 dev_warn(&h->pdev->dev,
3528 "maximum logical + physical LUNs (%d) exceeded. "
3529 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3530 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3531 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3532 }
3533 return 0;
3534}
3535
42a91641
DB		 3536static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3537 int i, int nphysicals, int nlogicals,
a93aa1fe 3538 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3539 struct ReportLUNdata *logdev_list)
3540{
3541 /* Helper function, figure out where the LUN ID info is coming from
3542 * given index i, lists of physical and logical devices, where in
3543 * the list the raid controller is supposed to appear (first or last)
3544 */
3545
3546 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3547 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3548
3549 if (i == raid_ctlr_position)
3550 return RAID_CTLR_LUNID;
3551
3552 if (i < logicals_start)
d5b5d964
SC		 3553 return &physdev_list->LUN[i -
3554 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3555
3556 if (i < last_device)
3557 return &logdev_list->LUN[i - nphysicals -
3558 (raid_ctlr_position == 0)][0];
3559 BUG();
3560 return NULL;
3561}
3562
316b221a
SC		 3563static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3564{
3565 int rc;
6e8e8088 3566 int hba_mode_enabled;
316b221a
SC		 3567 struct bmic_controller_parameters *ctlr_params;
3568 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3569 GFP_KERNEL);
3570
3571 if (!ctlr_params)
96444fbb 3572 return -ENOMEM;
316b221a
SC		 3573 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3574 sizeof(struct bmic_controller_parameters));
96444fbb 3575 if (rc) {
316b221a 3576 kfree(ctlr_params);
96444fbb 3577 return rc;
316b221a 3578 }
6e8e8088
JH		 3579
3580 hba_mode_enabled =
3581 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3582 kfree(ctlr_params);
3583 return hba_mode_enabled;
316b221a
SC		 3584}
3585
03383736
DB		 3586/* get physical drive ioaccel handle and queue depth */
3587static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3588 struct hpsa_scsi_dev_t *dev,
3589 u8 *lunaddrbytes,
3590 struct bmic_identify_physical_device *id_phys)
3591{
3592 int rc;
3593 struct ext_report_lun_entry *rle =
3594 (struct ext_report_lun_entry *) lunaddrbytes;
3595
3596 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3597 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3598 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3599 memset(id_phys, 0, sizeof(*id_phys));
3600 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3601 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3602 sizeof(*id_phys));
3603 if (!rc)
3604 /* Reserve space for FW operations */
3605#define DRIVE_CMDS_RESERVED_FOR_FW 2
3606#define DRIVE_QUEUE_DEPTH 7
3607 dev->queue_depth =
3608 le16_to_cpu(id_phys->current_queue_depth_limit) -
3609 DRIVE_CMDS_RESERVED_FOR_FW;
3610 else
3611 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3612 atomic_set(&dev->ioaccel_cmds_out, 0);
d604f533 3613 atomic_set(&dev->reset_cmds_out, 0);
03383736
DB		 3614}
3615
edd16368
SC		 3616static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3617{
3618 /* the idea here is we could get notified
3619 * that some devices have changed, so we do a report
3620 * physical luns and report logical luns cmd, and adjust
3621 * our list of devices accordingly.
3622 *
3623 * The scsi3addr's of devices won't change so long as the
3624 * adapter is not reset. That means we can rescan and
3625 * tell which devices we already know about, vs. new
3626 * devices, vs. disappearing devices.
3627 */
a93aa1fe 3628 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3629 struct ReportLUNdata *logdev_list = NULL;
03383736 3630 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3631 u32 nphysicals = 0;
3632 u32 nlogicals = 0;
3633 u32 ndev_allocated = 0;
edd16368
SC		 3634 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3635 int ncurrent = 0;
4f4eb9f1 3636 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3637 int raid_ctlr_position;
2bbf5c7f 3638 int rescan_hba_mode;
aca4a520 3639 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3640
cfe5badc 3641 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3642 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3643 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3644 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3645 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3646
03383736
DB		 3647 if (!currentsd || !physdev_list || !logdev_list ||
3648 !tmpdevice || !id_phys) {
edd16368
SC		 3649 dev_err(&h->pdev->dev, "out of memory\n");
3650 goto out;
3651 }
3652 memset(lunzerobits, 0, sizeof(lunzerobits));
3653
316b221a 3654 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3655 if (rescan_hba_mode < 0)
3656 goto out;
316b221a
SC		 3657
3658 if (!h->hba_mode_enabled && rescan_hba_mode)
3659 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3660 else if (h->hba_mode_enabled && !rescan_hba_mode)
3661 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3662
3663 h->hba_mode_enabled = rescan_hba_mode;
3664
03383736
DB		 3665 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3666 logdev_list, &nlogicals))
edd16368
SC		 3667 goto out;
3668
aca4a520
ST		 3669 /* We might see up to the maximum number of logical and physical disks
3670 * plus external target devices, and a device for the local RAID
3671 * controller.
edd16368 3672 */
aca4a520 3673 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3674
3675 /* Allocate the per device structures */
3676 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3677 if (i >= HPSA_MAX_DEVICES) {
3678 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3679 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3680 ndevs_to_allocate - HPSA_MAX_DEVICES);
3681 break;
3682 }
3683
edd16368
SC		 3684 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3685 if (!currentsd[i]) {
3686 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3687 __FILE__, __LINE__);
3688 goto out;
3689 }
3690 ndev_allocated++;
3691 }
3692
8645291b 3693 if (is_scsi_rev_5(h))
339b2b14
SC		 3694 raid_ctlr_position = 0;
3695 else
3696 raid_ctlr_position = nphysicals + nlogicals;
3697
edd16368 3698 /* adjust our table of devices */
4f4eb9f1 3699 n_ext_target_devs = 0;
edd16368 3700 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3701 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3702
3703 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3704 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3705 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3706
3707 /* skip masked non-disk devices */
3708 if (MASKED_DEVICE(lunaddrbytes))
3709 if (i < nphysicals + (raid_ctlr_position == 0) &&
3710 NON_DISK_PHYS_DEV(lunaddrbytes))
3711 continue;
edd16368
SC		 3712
3713 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3714 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3715 &is_OBDR))
edd16368 3716 continue; /* skip it if we can't talk to it. */
1f310bde 3717 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3718 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3719 this_device = currentsd[ncurrent];
3720
3721 /*
4f4eb9f1 3722 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3723 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3724 * is nonetheless an enclosure device there. We have to
3725 * present that otherwise linux won't find anything if
3726 * there is no lun 0.
3727 */
4f4eb9f1 3728 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3729 lunaddrbytes, lunzerobits,
4f4eb9f1 3730 &n_ext_target_devs)) {
edd16368
SC		 3731 ncurrent++;
3732 this_device = currentsd[ncurrent];
3733 }
3734
3735 *this_device = *tmpdevice;
edd16368 3736
41ce4c35
SC		 3737 /* do not expose masked devices */
3738 if (MASKED_DEVICE(lunaddrbytes) &&
3739 i < nphysicals + (raid_ctlr_position == 0)) {
3740 if (h->hba_mode_enabled)
3741 dev_warn(&h->pdev->dev,
3742 "Masked physical device detected\n");
3743 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3744 } else {
3745 this_device->expose_state =
3746 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3747 }
3748
edd16368 3749 switch (this_device->devtype) {
0b0e1d6c 3750 case TYPE_ROM:
edd16368
SC		 3751 /* We don't *really* support actual CD-ROM devices,
3752 * just "One Button Disaster Recovery" tape drive
3753 * which temporarily pretends to be a CD-ROM drive.
3754 * So we check that the device is really an OBDR tape
3755 * device by checking for "$DR-10" in bytes 43-48 of
3756 * the inquiry data.
3757 */
0b0e1d6c
SC		 3758 if (is_OBDR)
3759 ncurrent++;
edd16368
SC		 3760 break;
3761 case TYPE_DISK:
ecf418d1 3762 if (i >= nphysicals) {
316b221a
SC		 3763 ncurrent++;
3764 break;
283b4a9b 3765 }
ecf418d1
JH		 3766
3767 if (h->hba_mode_enabled)
3768 /* never use raid mapper in HBA mode */
3769 this_device->offload_enabled = 0;
3770 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3771 h->transMethod & CFGTBL_Trans_io_accel2))
3772 break;
3773
3774 hpsa_get_ioaccel_drive_info(h, this_device,
3775 lunaddrbytes, id_phys);
3776 atomic_set(&this_device->ioaccel_cmds_out, 0);
3777 ncurrent++;
edd16368
SC		 3778 break;
3779 case TYPE_TAPE:
3780 case TYPE_MEDIUM_CHANGER:
3781 ncurrent++;
3782 break;
41ce4c35
SC		 3783 case TYPE_ENCLOSURE:
3784 if (h->hba_mode_enabled)
3785 ncurrent++;
3786 break;
edd16368
SC		 3787 case TYPE_RAID:
3788 /* Only present the Smartarray HBA as a RAID controller.
3789 * If it's a RAID controller other than the HBA itself
3790 * (an external RAID controller, MSA500 or similar)
3791 * don't present it.
3792 */
3793 if (!is_hba_lunid(lunaddrbytes))
3794 break;
3795 ncurrent++;
3796 break;
3797 default:
3798 break;
3799 }
cfe5badc 3800 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3801 break;
3802 }
3803 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3804out:
3805 kfree(tmpdevice);
3806 for (i = 0; i < ndev_allocated; i++)
3807 kfree(currentsd[i]);
3808 kfree(currentsd);
edd16368
SC		 3809 kfree(physdev_list);
3810 kfree(logdev_list);
03383736 3811 kfree(id_phys);
edd16368
SC		 3812}
3813
ec5cbf04
WS		 3814static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3815 struct scatterlist *sg)
3816{
3817 u64 addr64 = (u64) sg_dma_address(sg);
3818 unsigned int len = sg_dma_len(sg);
3819
3820 desc->Addr = cpu_to_le64(addr64);
3821 desc->Len = cpu_to_le32(len);
3822 desc->Ext = 0;
3823}
3824
c7ee65b3
WS		 3825/*
3826 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3827 * dma mapping and fills in the scatter gather entries of the
3828 * hpsa command, cp.
3829 */
33a2ffce 3830static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3831 struct CommandList *cp,
3832 struct scsi_cmnd *cmd)
3833{
edd16368 3834 struct scatterlist *sg;
b3a7ba7c 3835 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3836 struct SGDescriptor *curr_sg;
edd16368 3837
33a2ffce 3838 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3839
3840 use_sg = scsi_dma_map(cmd);
3841 if (use_sg < 0)
3842 return use_sg;
3843
3844 if (!use_sg)
3845 goto sglist_finished;
3846
b3a7ba7c
WS		 3847 /*
3848 * If the number of entries is greater than the max for a single list,
3849 * then we have a chained list; we will set up all but one entry in the
3850 * first list (the last entry is saved for link information);
3851 * otherwise, we don't have a chained list and we'll set up at each of
3852 * the entries in the one list.
3853 */
33a2ffce 3854 curr_sg = cp->SG;
b3a7ba7c
WS		 3855 chained = use_sg > h->max_cmd_sg_entries;
3856 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3857 last_sg = scsi_sg_count(cmd) - 1;
3858 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3859 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3860 curr_sg++;
3861 }
ec5cbf04 3862
b3a7ba7c
WS		 3863 if (chained) {
3864 /*
3865 * Continue with the chained list. Set curr_sg to the chained
3866 * list. Modify the limit to the total count less the entries
3867 * we've already set up. Resume the scan at the list entry
3868 * where the previous loop left off.
3869 */
3870 curr_sg = h->cmd_sg_list[cp->cmdindex];
3871 sg_limit = use_sg - sg_limit;
3872 for_each_sg(sg, sg, sg_limit, i) {
3873 hpsa_set_sg_descriptor(curr_sg, sg);
3874 curr_sg++;
3875 }
3876 }
3877
ec5cbf04 3878 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3879 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3880
3881 if (use_sg + chained > h->maxSG)
3882 h->maxSG = use_sg + chained;
3883
3884 if (chained) {
3885 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3886 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3887 if (hpsa_map_sg_chain_block(h, cp)) {
3888 scsi_dma_unmap(cmd);
3889 return -1;
3890 }
33a2ffce 3891 return 0;
edd16368
SC		 3892 }
3893
3894sglist_finished:
3895
01a02ffc 3896 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3897 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3898 return 0;
3899}
3900
283b4a9b
SC		 3901#define IO_ACCEL_INELIGIBLE (1)
3902static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3903{
3904 int is_write = 0;
3905 u32 block;
3906 u32 block_cnt;
3907
3908 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3909 switch (cdb[0]) {
3910 case WRITE_6:
3911 case WRITE_12:
3912 is_write = 1;
3913 case READ_6:
3914 case READ_12:
3915 if (*cdb_len == 6) {
3916 block = (((u32) cdb[2]) << 8) | cdb[3];
3917 block_cnt = cdb[4];
3918 } else {
3919 BUG_ON(*cdb_len != 12);
3920 block = (((u32) cdb[2]) << 24) |
3921 (((u32) cdb[3]) << 16) |
3922 (((u32) cdb[4]) << 8) |
3923 cdb[5];
3924 block_cnt =
3925 (((u32) cdb[6]) << 24) |
3926 (((u32) cdb[7]) << 16) |
3927 (((u32) cdb[8]) << 8) |
3928 cdb[9];
3929 }
3930 if (block_cnt > 0xffff)
3931 return IO_ACCEL_INELIGIBLE;
3932
3933 cdb[0] = is_write ? WRITE_10 : READ_10;
3934 cdb[1] = 0;
3935 cdb[2] = (u8) (block >> 24);
3936 cdb[3] = (u8) (block >> 16);
3937 cdb[4] = (u8) (block >> 8);
3938 cdb[5] = (u8) (block);
3939 cdb[6] = 0;
3940 cdb[7] = (u8) (block_cnt >> 8);
3941 cdb[8] = (u8) (block_cnt);
3942 cdb[9] = 0;
3943 *cdb_len = 10;
3944 break;
3945 }
3946 return 0;
3947}
3948
c349775e 3949static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3950 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3951 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3952{
3953 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3954 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3955 unsigned int len;
3956 unsigned int total_len = 0;
3957 struct scatterlist *sg;
3958 u64 addr64;
3959 int use_sg, i;
3960 struct SGDescriptor *curr_sg;
3961 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3962
283b4a9b 3963 /* TODO: implement chaining support */
03383736
DB		 3964 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3965 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3966 return IO_ACCEL_INELIGIBLE;
03383736 3967 }
283b4a9b 3968
e1f7de0c
MG		 3969 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3970
03383736
DB		 3971 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3972 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3973 return IO_ACCEL_INELIGIBLE;
03383736 3974 }
283b4a9b 3975
e1f7de0c
MG		 3976 c->cmd_type = CMD_IOACCEL1;
3977
3978 /* Adjust the DMA address to point to the accelerated command buffer */
3979 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3980 (c->cmdindex * sizeof(*cp));
3981 BUG_ON(c->busaddr & 0x0000007F);
3982
3983 use_sg = scsi_dma_map(cmd);
03383736
DB		 3984 if (use_sg < 0) {
3985 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3986 return use_sg;
03383736 3987 }
e1f7de0c
MG		 3988
3989 if (use_sg) {
3990 curr_sg = cp->SG;
3991 scsi_for_each_sg(cmd, sg, use_sg, i) {
3992 addr64 = (u64) sg_dma_address(sg);
3993 len = sg_dma_len(sg);
3994 total_len += len;
50a0decf
SC		 3995 curr_sg->Addr = cpu_to_le64(addr64);
3996 curr_sg->Len = cpu_to_le32(len);
3997 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3998 curr_sg++;
3999 }
50a0decf 4000 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4001
4002 switch (cmd->sc_data_direction) {
4003 case DMA_TO_DEVICE:
4004 control |= IOACCEL1_CONTROL_DATA_OUT;
4005 break;
4006 case DMA_FROM_DEVICE:
4007 control |= IOACCEL1_CONTROL_DATA_IN;
4008 break;
4009 case DMA_NONE:
4010 control |= IOACCEL1_CONTROL_NODATAXFER;
4011 break;
4012 default:
4013 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4014 cmd->sc_data_direction);
4015 BUG();
4016 break;
4017 }
4018 } else {
4019 control |= IOACCEL1_CONTROL_NODATAXFER;
4020 }
4021
c349775e 4022 c->Header.SGList = use_sg;
e1f7de0c 4023 /* Fill out the command structure to submit */
2b08b3e9
DB		 4024 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4025 cp->transfer_len = cpu_to_le32(total_len);
4026 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4027 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4028 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4029 memcpy(cp->CDB, cdb, cdb_len);
4030 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4031 /* Tag was already set at init time. */
283b4a9b 4032 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4033 return 0;
4034}
edd16368 4035
283b4a9b
SC		 4036/*
4037 * Queue a command directly to a device behind the controller using the
4038 * I/O accelerator path.
4039 */
4040static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4041 struct CommandList *c)
4042{
4043 struct scsi_cmnd *cmd = c->scsi_cmd;
4044 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4045
03383736
DB		 4046 c->phys_disk = dev;
4047
283b4a9b 4048 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4049 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4050}
4051
dd0e19f3
ST		 4052/*
4053 * Set encryption parameters for the ioaccel2 request
4054 */
4055static void set_encrypt_ioaccel2(struct ctlr_info *h,
4056 struct CommandList *c, struct io_accel2_cmd *cp)
4057{
4058 struct scsi_cmnd *cmd = c->scsi_cmd;
4059 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4060 struct raid_map_data *map = &dev->raid_map;
4061 u64 first_block;
4062
dd0e19f3 4063 /* Are we doing encryption on this device */
2b08b3e9 4064 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4065 return;
4066 /* Set the data encryption key index. */
4067 cp->dekindex = map->dekindex;
4068
4069 /* Set the encryption enable flag, encoded into direction field. */
4070 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4071
4072 /* Set encryption tweak values based on logical block address
4073 * If block size is 512, tweak value is LBA.
4074 * For other block sizes, tweak is (LBA * block size)/ 512)
4075 */
4076 switch (cmd->cmnd[0]) {
4077 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4078 case WRITE_6:
4079 case READ_6:
2b08b3e9 4080 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4081 break;
4082 case WRITE_10:
4083 case READ_10:
dd0e19f3
ST		 4084 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4085 case WRITE_12:
4086 case READ_12:
2b08b3e9 4087 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4088 break;
4089 case WRITE_16:
4090 case READ_16:
2b08b3e9 4091 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4092 break;
4093 default:
4094 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4095 "ERROR: %s: size (0x%x) not supported for encryption\n",
4096 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4097 BUG();
4098 break;
4099 }
2b08b3e9
DB		 4100
4101 if (le32_to_cpu(map->volume_blk_size) != 512)
4102 first_block = first_block *
4103 le32_to_cpu(map->volume_blk_size)/512;
4104
4105 cp->tweak_lower = cpu_to_le32(first_block);
4106 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4107}
4108
c349775e
ST		 4109static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4110 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4111 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4112{
4113 struct scsi_cmnd *cmd = c->scsi_cmd;
4114 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4115 struct ioaccel2_sg_element *curr_sg;
4116 int use_sg, i;
4117 struct scatterlist *sg;
4118 u64 addr64;
4119 u32 len;
4120 u32 total_len = 0;
4121
d9a729f3 4122 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4123
03383736
DB		 4124 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4125 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4126 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4127 }
4128
c349775e
ST		 4129 c->cmd_type = CMD_IOACCEL2;
4130 /* Adjust the DMA address to point to the accelerated command buffer */
4131 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4132 (c->cmdindex * sizeof(*cp));
4133 BUG_ON(c->busaddr & 0x0000007F);
4134
4135 memset(cp, 0, sizeof(*cp));
4136 cp->IU_type = IOACCEL2_IU_TYPE;
4137
4138 use_sg = scsi_dma_map(cmd);
03383736
DB		 4139 if (use_sg < 0) {
4140 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4141 return use_sg;
03383736 4142 }
c349775e
ST		 4143
4144 if (use_sg) {
c349775e 4145 curr_sg = cp->sg;
d9a729f3
WS		 4146 if (use_sg > h->ioaccel_maxsg) {
4147 addr64 = le64_to_cpu(
4148 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4149 curr_sg->address = cpu_to_le64(addr64);
4150 curr_sg->length = 0;
4151 curr_sg->reserved[0] = 0;
4152 curr_sg->reserved[1] = 0;
4153 curr_sg->reserved[2] = 0;
4154 curr_sg->chain_indicator = 0x80;
4155
4156 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4157 }
c349775e
ST		 4158 scsi_for_each_sg(cmd, sg, use_sg, i) {
4159 addr64 = (u64) sg_dma_address(sg);
4160 len = sg_dma_len(sg);
4161 total_len += len;
4162 curr_sg->address = cpu_to_le64(addr64);
4163 curr_sg->length = cpu_to_le32(len);
4164 curr_sg->reserved[0] = 0;
4165 curr_sg->reserved[1] = 0;
4166 curr_sg->reserved[2] = 0;
4167 curr_sg->chain_indicator = 0;
4168 curr_sg++;
4169 }
4170
4171 switch (cmd->sc_data_direction) {
4172 case DMA_TO_DEVICE:
dd0e19f3
ST		 4173 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4174 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4175 break;
4176 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4177 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4178 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4179 break;
4180 case DMA_NONE:
dd0e19f3
ST		 4181 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4182 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4183 break;
4184 default:
4185 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4186 cmd->sc_data_direction);
4187 BUG();
4188 break;
4189 }
4190 } else {
dd0e19f3
ST		 4191 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4192 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4193 }
dd0e19f3
ST		 4194
4195 /* Set encryption parameters, if necessary */
4196 set_encrypt_ioaccel2(h, c, cp);
4197
2b08b3e9 4198 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4199 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4200 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4201
c349775e
ST		 4202 cp->data_len = cpu_to_le32(total_len);
4203 cp->err_ptr = cpu_to_le64(c->busaddr +
4204 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4205 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4206
d9a729f3
WS		 4207 /* fill in sg elements */
4208 if (use_sg > h->ioaccel_maxsg) {
4209 cp->sg_count = 1;
4210 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4211 atomic_dec(&phys_disk->ioaccel_cmds_out);
4212 scsi_dma_unmap(cmd);
4213 return -1;
4214 }
4215 } else
4216 cp->sg_count = (u8) use_sg;
4217
c349775e
ST		 4218 enqueue_cmd_and_start_io(h, c);
4219 return 0;
4220}
4221
4222/*
4223 * Queue a command to the correct I/O accelerator path.
4224 */
4225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4227 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4228{
03383736
DB		 4229 /* Try to honor the device's queue depth */
4230 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4231 phys_disk->queue_depth) {
4232 atomic_dec(&phys_disk->ioaccel_cmds_out);
4233 return IO_ACCEL_INELIGIBLE;
4234 }
c349775e
ST		 4235 if (h->transMethod & CFGTBL_Trans_io_accel1)
4236 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4237 cdb, cdb_len, scsi3addr,
4238 phys_disk);
c349775e
ST		 4239 else
4240 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4241 cdb, cdb_len, scsi3addr,
4242 phys_disk);
c349775e
ST		 4243}
4244
6b80b18f
ST		 4245static void raid_map_helper(struct raid_map_data *map,
4246 int offload_to_mirror, u32 *map_index, u32 *current_group)
4247{
4248 if (offload_to_mirror == 0) {
4249 /* use physical disk in the first mirrored group. */
2b08b3e9 4250 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4251 return;
4252 }
4253 do {
4254 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4255 *current_group = *map_index /
4256 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4257 if (offload_to_mirror == *current_group)
4258 continue;
2b08b3e9 4259 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4260 /* select map index from next group */
2b08b3e9 4261 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4262 (*current_group)++;
4263 } else {
4264 /* select map index from first group */
2b08b3e9 4265 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4266 *current_group = 0;
4267 }
4268 } while (offload_to_mirror != *current_group);
4269}
4270
283b4a9b
SC		 4271/*
4272 * Attempt to perform offload RAID mapping for a logical volume I/O.
4273 */
4274static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4275 struct CommandList *c)
4276{
4277 struct scsi_cmnd *cmd = c->scsi_cmd;
4278 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4279 struct raid_map_data *map = &dev->raid_map;
4280 struct raid_map_disk_data *dd = &map->data[0];
4281 int is_write = 0;
4282 u32 map_index;
4283 u64 first_block, last_block;
4284 u32 block_cnt;
4285 u32 blocks_per_row;
4286 u64 first_row, last_row;
4287 u32 first_row_offset, last_row_offset;
4288 u32 first_column, last_column;
6b80b18f
ST		 4289 u64 r0_first_row, r0_last_row;
4290 u32 r5or6_blocks_per_row;
4291 u64 r5or6_first_row, r5or6_last_row;
4292 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4293 u32 r5or6_first_column, r5or6_last_column;
4294 u32 total_disks_per_row;
4295 u32 stripesize;
4296 u32 first_group, last_group, current_group;
283b4a9b
SC		 4297 u32 map_row;
4298 u32 disk_handle;
4299 u64 disk_block;
4300 u32 disk_block_cnt;
4301 u8 cdb[16];
4302 u8 cdb_len;
2b08b3e9 4303 u16 strip_size;
283b4a9b
SC		 4304#if BITS_PER_LONG == 32
4305 u64 tmpdiv;
4306#endif
6b80b18f 4307 int offload_to_mirror;
283b4a9b 4308
283b4a9b
SC		 4309 /* check for valid opcode, get LBA and block count */
4310 switch (cmd->cmnd[0]) {
4311 case WRITE_6:
4312 is_write = 1;
4313 case READ_6:
4314 first_block =
4315 (((u64) cmd->cmnd[2]) << 8) |
4316 cmd->cmnd[3];
4317 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4318 if (block_cnt == 0)
4319 block_cnt = 256;
283b4a9b
SC		 4320 break;
4321 case WRITE_10:
4322 is_write = 1;
4323 case READ_10:
4324 first_block =
4325 (((u64) cmd->cmnd[2]) << 24) |
4326 (((u64) cmd->cmnd[3]) << 16) |
4327 (((u64) cmd->cmnd[4]) << 8) |
4328 cmd->cmnd[5];
4329 block_cnt =
4330 (((u32) cmd->cmnd[7]) << 8) |
4331 cmd->cmnd[8];
4332 break;
4333 case WRITE_12:
4334 is_write = 1;
4335 case READ_12:
4336 first_block =
4337 (((u64) cmd->cmnd[2]) << 24) |
4338 (((u64) cmd->cmnd[3]) << 16) |
4339 (((u64) cmd->cmnd[4]) << 8) |
4340 cmd->cmnd[5];
4341 block_cnt =
4342 (((u32) cmd->cmnd[6]) << 24) |
4343 (((u32) cmd->cmnd[7]) << 16) |
4344 (((u32) cmd->cmnd[8]) << 8) |
4345 cmd->cmnd[9];
4346 break;
4347 case WRITE_16:
4348 is_write = 1;
4349 case READ_16:
4350 first_block =
4351 (((u64) cmd->cmnd[2]) << 56) |
4352 (((u64) cmd->cmnd[3]) << 48) |
4353 (((u64) cmd->cmnd[4]) << 40) |
4354 (((u64) cmd->cmnd[5]) << 32) |
4355 (((u64) cmd->cmnd[6]) << 24) |
4356 (((u64) cmd->cmnd[7]) << 16) |
4357 (((u64) cmd->cmnd[8]) << 8) |
4358 cmd->cmnd[9];
4359 block_cnt =
4360 (((u32) cmd->cmnd[10]) << 24) |
4361 (((u32) cmd->cmnd[11]) << 16) |
4362 (((u32) cmd->cmnd[12]) << 8) |
4363 cmd->cmnd[13];
4364 break;
4365 default:
4366 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4367 }
283b4a9b
SC		 4368 last_block = first_block + block_cnt - 1;
4369
4370 /* check for write to non-RAID-0 */
4371 if (is_write && dev->raid_level != 0)
4372 return IO_ACCEL_INELIGIBLE;
4373
4374 /* check for invalid block or wraparound */
2b08b3e9
DB		 4375 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4376 last_block < first_block)
283b4a9b
SC		 4377 return IO_ACCEL_INELIGIBLE;
4378
4379 /* calculate stripe information for the request */
2b08b3e9
DB		 4380 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4381 le16_to_cpu(map->strip_size);
4382 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4383#if BITS_PER_LONG == 32
4384 tmpdiv = first_block;
4385 (void) do_div(tmpdiv, blocks_per_row);
4386 first_row = tmpdiv;
4387 tmpdiv = last_block;
4388 (void) do_div(tmpdiv, blocks_per_row);
4389 last_row = tmpdiv;
4390 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4391 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4392 tmpdiv = first_row_offset;
2b08b3e9 4393 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4394 first_column = tmpdiv;
4395 tmpdiv = last_row_offset;
2b08b3e9 4396 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4397 last_column = tmpdiv;
4398#else
4399 first_row = first_block / blocks_per_row;
4400 last_row = last_block / blocks_per_row;
4401 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4402 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4403 first_column = first_row_offset / strip_size;
4404 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4405#endif
4406
4407 /* if this isn't a single row/column then give to the controller */
4408 if ((first_row != last_row) || (first_column != last_column))
4409 return IO_ACCEL_INELIGIBLE;
4410
4411 /* proceeding with driver mapping */
2b08b3e9
DB		 4412 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4413 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4414 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4415 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4416 map_index = (map_row * total_disks_per_row) + first_column;
4417
4418 switch (dev->raid_level) {
4419 case HPSA_RAID_0:
4420 break; /* nothing special to do */
4421 case HPSA_RAID_1:
4422 /* Handles load balance across RAID 1 members.
4423 * (2-drive R1 and R10 with even # of drives.)
4424 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4425 */
2b08b3e9 4426 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4427 if (dev->offload_to_mirror)
2b08b3e9 4428 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4429 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4430 break;
4431 case HPSA_RAID_ADM:
4432 /* Handles N-way mirrors (R1-ADM)
4433 * and R10 with # of drives divisible by 3.)
4434 */
2b08b3e9 4435 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4436
4437 offload_to_mirror = dev->offload_to_mirror;
4438 raid_map_helper(map, offload_to_mirror,
4439 &map_index, &current_group);
4440 /* set mirror group to use next time */
4441 offload_to_mirror =
2b08b3e9
DB		 4442 (offload_to_mirror >=
4443 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4444 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4445 dev->offload_to_mirror = offload_to_mirror;
4446 /* Avoid direct use of dev->offload_to_mirror within this
4447 * function since multiple threads might simultaneously
4448 * increment it beyond the range of dev->layout_map_count -1.
4449 */
4450 break;
4451 case HPSA_RAID_5:
4452 case HPSA_RAID_6:
2b08b3e9 4453 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4454 break;
4455
4456 /* Verify first and last block are in same RAID group */
4457 r5or6_blocks_per_row =
2b08b3e9
DB		 4458 le16_to_cpu(map->strip_size) *
4459 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4460 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4461 stripesize = r5or6_blocks_per_row *
4462 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4463#if BITS_PER_LONG == 32
4464 tmpdiv = first_block;
4465 first_group = do_div(tmpdiv, stripesize);
4466 tmpdiv = first_group;
4467 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4468 first_group = tmpdiv;
4469 tmpdiv = last_block;
4470 last_group = do_div(tmpdiv, stripesize);
4471 tmpdiv = last_group;
4472 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4473 last_group = tmpdiv;
4474#else
4475 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4476 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4477#endif
000ff7c2 4478 if (first_group != last_group)
6b80b18f
ST		 4479 return IO_ACCEL_INELIGIBLE;
4480
4481 /* Verify request is in a single row of RAID 5/6 */
4482#if BITS_PER_LONG == 32
4483 tmpdiv = first_block;
4484 (void) do_div(tmpdiv, stripesize);
4485 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4486 tmpdiv = last_block;
4487 (void) do_div(tmpdiv, stripesize);
4488 r5or6_last_row = r0_last_row = tmpdiv;
4489#else
4490 first_row = r5or6_first_row = r0_first_row =
4491 first_block / stripesize;
4492 r5or6_last_row = r0_last_row = last_block / stripesize;
4493#endif
4494 if (r5or6_first_row != r5or6_last_row)
4495 return IO_ACCEL_INELIGIBLE;
4496
4497
4498 /* Verify request is in a single column */
4499#if BITS_PER_LONG == 32
4500 tmpdiv = first_block;
4501 first_row_offset = do_div(tmpdiv, stripesize);
4502 tmpdiv = first_row_offset;
4503 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4504 r5or6_first_row_offset = first_row_offset;
4505 tmpdiv = last_block;
4506 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4507 tmpdiv = r5or6_last_row_offset;
4508 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4509 tmpdiv = r5or6_first_row_offset;
4510 (void) do_div(tmpdiv, map->strip_size);
4511 first_column = r5or6_first_column = tmpdiv;
4512 tmpdiv = r5or6_last_row_offset;
4513 (void) do_div(tmpdiv, map->strip_size);
4514 r5or6_last_column = tmpdiv;
4515#else
4516 first_row_offset = r5or6_first_row_offset =
4517 (u32)((first_block % stripesize) %
4518 r5or6_blocks_per_row);
4519
4520 r5or6_last_row_offset =
4521 (u32)((last_block % stripesize) %
4522 r5or6_blocks_per_row);
4523
4524 first_column = r5or6_first_column =
2b08b3e9 4525 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4526 r5or6_last_column =
2b08b3e9 4527 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4528#endif
4529 if (r5or6_first_column != r5or6_last_column)
4530 return IO_ACCEL_INELIGIBLE;
4531
4532 /* Request is eligible */
4533 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4534 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4535
4536 map_index = (first_group *
2b08b3e9 4537 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4538 (map_row * total_disks_per_row) + first_column;
4539 break;
4540 default:
4541 return IO_ACCEL_INELIGIBLE;
283b4a9b 4542 }
6b80b18f 4543
07543e0c
SC		 4544 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4545 return IO_ACCEL_INELIGIBLE;
4546
03383736
DB		 4547 c->phys_disk = dev->phys_disk[map_index];
4548
283b4a9b 4549 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4550 disk_block = le64_to_cpu(map->disk_starting_blk) +
4551 first_row * le16_to_cpu(map->strip_size) +
4552 (first_row_offset - first_column *
4553 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4554 disk_block_cnt = block_cnt;
4555
4556 /* handle differing logical/physical block sizes */
4557 if (map->phys_blk_shift) {
4558 disk_block <<= map->phys_blk_shift;
4559 disk_block_cnt <<= map->phys_blk_shift;
4560 }
4561 BUG_ON(disk_block_cnt > 0xffff);
4562
4563 /* build the new CDB for the physical disk I/O */
4564 if (disk_block > 0xffffffff) {
4565 cdb[0] = is_write ? WRITE_16 : READ_16;
4566 cdb[1] = 0;
4567 cdb[2] = (u8) (disk_block >> 56);
4568 cdb[3] = (u8) (disk_block >> 48);
4569 cdb[4] = (u8) (disk_block >> 40);
4570 cdb[5] = (u8) (disk_block >> 32);
4571 cdb[6] = (u8) (disk_block >> 24);
4572 cdb[7] = (u8) (disk_block >> 16);
4573 cdb[8] = (u8) (disk_block >> 8);
4574 cdb[9] = (u8) (disk_block);
4575 cdb[10] = (u8) (disk_block_cnt >> 24);
4576 cdb[11] = (u8) (disk_block_cnt >> 16);
4577 cdb[12] = (u8) (disk_block_cnt >> 8);
4578 cdb[13] = (u8) (disk_block_cnt);
4579 cdb[14] = 0;
4580 cdb[15] = 0;
4581 cdb_len = 16;
4582 } else {
4583 cdb[0] = is_write ? WRITE_10 : READ_10;
4584 cdb[1] = 0;
4585 cdb[2] = (u8) (disk_block >> 24);
4586 cdb[3] = (u8) (disk_block >> 16);
4587 cdb[4] = (u8) (disk_block >> 8);
4588 cdb[5] = (u8) (disk_block);
4589 cdb[6] = 0;
4590 cdb[7] = (u8) (disk_block_cnt >> 8);
4591 cdb[8] = (u8) (disk_block_cnt);
4592 cdb[9] = 0;
4593 cdb_len = 10;
4594 }
4595 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4596 dev->scsi3addr,
4597 dev->phys_disk[map_index]);
283b4a9b
SC		 4598}
4599
25163bd5
WS		 4600/*
4601 * Submit commands down the "normal" RAID stack path
4602 * All callers to hpsa_ciss_submit must check lockup_detected
4603 * beforehand, before (opt.) and after calling cmd_alloc
4604 */
574f05d3
SC		 4605static int hpsa_ciss_submit(struct ctlr_info *h,
4606 struct CommandList *c, struct scsi_cmnd *cmd,
4607 unsigned char scsi3addr[])
edd16368 4608{
edd16368 4609 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4610 c->cmd_type = CMD_SCSI;
4611 c->scsi_cmd = cmd;
4612 c->Header.ReplyQueue = 0; /* unused in simple mode */
4613 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4614 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4615
4616 /* Fill in the request block... */
4617
4618 c->Request.Timeout = 0;
edd16368
SC		 4619 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4620 c->Request.CDBLen = cmd->cmd_len;
4621 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4622 switch (cmd->sc_data_direction) {
4623 case DMA_TO_DEVICE:
a505b86f
SC		 4624 c->Request.type_attr_dir =
4625 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4626 break;
4627 case DMA_FROM_DEVICE:
a505b86f
SC		 4628 c->Request.type_attr_dir =
4629 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4630 break;
4631 case DMA_NONE:
a505b86f
SC		 4632 c->Request.type_attr_dir =
4633 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4634 break;
4635 case DMA_BIDIRECTIONAL:
4636 /* This can happen if a buggy application does a scsi passthru
4637 * and sets both inlen and outlen to non-zero. ( see
4638 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4639 */
4640
a505b86f
SC		 4641 c->Request.type_attr_dir =
4642 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4643 /* This is technically wrong, and hpsa controllers should
4644 * reject it with CMD_INVALID, which is the most correct
4645 * response, but non-fibre backends appear to let it
4646 * slide by, and give the same results as if this field
4647 * were set correctly. Either way is acceptable for
4648 * our purposes here.
4649 */
4650
4651 break;
4652
4653 default:
4654 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4655 cmd->sc_data_direction);
4656 BUG();
4657 break;
4658 }
4659
33a2ffce 4660 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4661 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4662 return SCSI_MLQUEUE_HOST_BUSY;
4663 }
4664 enqueue_cmd_and_start_io(h, c);
4665 /* the cmd'll come back via intr handler in complete_scsi_command() */
4666 return 0;
4667}
4668
360c73bd
SC		 4669static void hpsa_cmd_init(struct ctlr_info *h, int index,
4670 struct CommandList *c)
4671{
4672 dma_addr_t cmd_dma_handle, err_dma_handle;
4673
4674 /* Zero out all of commandlist except the last field, refcount */
4675 memset(c, 0, offsetof(struct CommandList, refcount));
4676 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4677 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4678 c->err_info = h->errinfo_pool + index;
4679 memset(c->err_info, 0, sizeof(*c->err_info));
4680 err_dma_handle = h->errinfo_pool_dhandle
4681 + index * sizeof(*c->err_info);
4682 c->cmdindex = index;
4683 c->busaddr = (u32) cmd_dma_handle;
4684 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4685 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4686 c->h = h;
a58e7e53 4687 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4688}
4689
4690static void hpsa_preinitialize_commands(struct ctlr_info *h)
4691{
4692 int i;
4693
4694 for (i = 0; i < h->nr_cmds; i++) {
4695 struct CommandList *c = h->cmd_pool + i;
4696
4697 hpsa_cmd_init(h, i, c);
4698 atomic_set(&c->refcount, 0);
4699 }
4700}
4701
4702static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4703 struct CommandList *c)
4704{
4705 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4706
73153fe5
WS		 4707 BUG_ON(c->cmdindex != index);
4708
360c73bd
SC		 4709 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4710 memset(c->err_info, 0, sizeof(*c->err_info));
4711 c->busaddr = (u32) cmd_dma_handle;
4712}
4713
592a0ad5
WS		 4714static int hpsa_ioaccel_submit(struct ctlr_info *h,
4715 struct CommandList *c, struct scsi_cmnd *cmd,
4716 unsigned char *scsi3addr)
4717{
4718 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4719 int rc = IO_ACCEL_INELIGIBLE;
4720
4721 cmd->host_scribble = (unsigned char *) c;
4722
4723 if (dev->offload_enabled) {
4724 hpsa_cmd_init(h, c->cmdindex, c);
4725 c->cmd_type = CMD_SCSI;
4726 c->scsi_cmd = cmd;
4727 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4728 if (rc < 0) /* scsi_dma_map failed. */
4729 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4730 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4731 hpsa_cmd_init(h, c->cmdindex, c);
4732 c->cmd_type = CMD_SCSI;
4733 c->scsi_cmd = cmd;
4734 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4735 if (rc < 0) /* scsi_dma_map failed. */
4736 rc = SCSI_MLQUEUE_HOST_BUSY;
4737 }
4738 return rc;
4739}
4740
080ef1cc
DB		 4741static void hpsa_command_resubmit_worker(struct work_struct *work)
4742{
4743 struct scsi_cmnd *cmd;
4744 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4745 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4746
4747 cmd = c->scsi_cmd;
4748 dev = cmd->device->hostdata;
4749 if (!dev) {
4750 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4751 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4752 }
d604f533
WS		 4753 if (c->reset_pending)
4754 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4755 if (c->abort_pending)
4756 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4757 if (c->cmd_type == CMD_IOACCEL2) {
4758 struct ctlr_info *h = c->h;
4759 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4760 int rc;
4761
4762 if (c2->error_data.serv_response ==
4763 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4764 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4765 if (rc == 0)
4766 return;
4767 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4768 /*
4769 * If we get here, it means dma mapping failed.
4770 * Try again via scsi mid layer, which will
4771 * then get SCSI_MLQUEUE_HOST_BUSY.
4772 */
4773 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4774 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4775 }
4776 /* else, fall thru and resubmit down CISS path */
4777 }
4778 }
360c73bd 4779 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4780 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4781 /*
4782 * If we get here, it means dma mapping failed. Try
4783 * again via scsi mid layer, which will then get
4784 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4785 *
4786 * hpsa_ciss_submit will have already freed c
4787 * if it encountered a dma mapping failure.
080ef1cc
DB		 4788 */
4789 cmd->result = DID_IMM_RETRY << 16;
4790 cmd->scsi_done(cmd);
4791 }
4792}
4793
574f05d3
SC		 4794/* Running in struct Scsi_Host->host_lock less mode */
4795static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4796{
4797 struct ctlr_info *h;
4798 struct hpsa_scsi_dev_t *dev;
4799 unsigned char scsi3addr[8];
4800 struct CommandList *c;
4801 int rc = 0;
4802
4803 /* Get the ptr to our adapter structure out of cmd->host. */
4804 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4805
4806 BUG_ON(cmd->request->tag < 0);
4807
574f05d3
SC		 4808 dev = cmd->device->hostdata;
4809 if (!dev) {
4810 cmd->result = DID_NO_CONNECT << 16;
4811 cmd->scsi_done(cmd);
4812 return 0;
4813 }
574f05d3 4814
73153fe5 4815 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4816
407863cb 4817 if (unlikely(lockup_detected(h))) {
25163bd5 4818 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4819 cmd->scsi_done(cmd);
4820 return 0;
4821 }
73153fe5 4822 c = cmd_tagged_alloc(h, cmd);
574f05d3 4823
407863cb
SC		 4824 /*
4825 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4826 * Retries always go down the normal I/O path.
4827 */
4828 if (likely(cmd->retries == 0 &&
4829 cmd->request->cmd_type == REQ_TYPE_FS &&
4830 h->acciopath_status)) {
592a0ad5
WS		 4831 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4832 if (rc == 0)
4833 return 0;
4834 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4835 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4836 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4837 }
4838 }
4839 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4840}
4841
8ebc9248 4842static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4843{
4844 unsigned long flags;
4845
8ebc9248
WS		 4846 spin_lock_irqsave(&h->scan_lock, flags);
4847 h->scan_finished = 1;
4848 wake_up_all(&h->scan_wait_queue);
4849 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4850}
4851
a08a8471
SC		 4852static void hpsa_scan_start(struct Scsi_Host *sh)
4853{
4854 struct ctlr_info *h = shost_to_hba(sh);
4855 unsigned long flags;
4856
8ebc9248
WS		 4857 /*
4858 * Don't let rescans be initiated on a controller known to be locked
4859 * up. If the controller locks up *during* a rescan, that thread is
4860 * probably hosed, but at least we can prevent new rescan threads from
4861 * piling up on a locked up controller.
4862 */
4863 if (unlikely(lockup_detected(h)))
4864 return hpsa_scan_complete(h);
5f389360 4865
a08a8471
SC		 4866 /* wait until any scan already in progress is finished. */
4867 while (1) {
4868 spin_lock_irqsave(&h->scan_lock, flags);
4869 if (h->scan_finished)
4870 break;
4871 spin_unlock_irqrestore(&h->scan_lock, flags);
4872 wait_event(h->scan_wait_queue, h->scan_finished);
4873 /* Note: We don't need to worry about a race between this
4874 * thread and driver unload because the midlayer will
4875 * have incremented the reference count, so unload won't
4876 * happen if we're in here.
4877 */
4878 }
4879 h->scan_finished = 0; /* mark scan as in progress */
4880 spin_unlock_irqrestore(&h->scan_lock, flags);
4881
8ebc9248
WS		 4882 if (unlikely(lockup_detected(h)))
4883 return hpsa_scan_complete(h);
5f389360 4884
a08a8471
SC		 4885 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4886
8ebc9248 4887 hpsa_scan_complete(h);
a08a8471
SC		 4888}
4889
7c0a0229
DB		 4890static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4891{
03383736
DB		 4892 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4893
4894 if (!logical_drive)
4895 return -ENODEV;
7c0a0229
DB		 4896
4897 if (qdepth < 1)
4898 qdepth = 1;
03383736
DB		 4899 else if (qdepth > logical_drive->queue_depth)
4900 qdepth = logical_drive->queue_depth;
4901
4902 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4903}
4904
a08a8471
SC		 4905static int hpsa_scan_finished(struct Scsi_Host *sh,
4906 unsigned long elapsed_time)
4907{
4908 struct ctlr_info *h = shost_to_hba(sh);
4909 unsigned long flags;
4910 int finished;
4911
4912 spin_lock_irqsave(&h->scan_lock, flags);
4913 finished = h->scan_finished;
4914 spin_unlock_irqrestore(&h->scan_lock, flags);
4915 return finished;
4916}
4917
2946e82b 4918static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 4919{
b705690d
SC		 4920 struct Scsi_Host *sh;
4921 int error;
edd16368 4922
b705690d 4923 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 4924 if (sh == NULL) {
4925 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
4926 return -ENOMEM;
4927 }
b705690d
SC		 4928
4929 sh->io_port = 0;
4930 sh->n_io_port = 0;
4931 sh->this_id = -1;
4932 sh->max_channel = 3;
4933 sh->max_cmd_len = MAX_COMMAND_SIZE;
4934 sh->max_lun = HPSA_MAX_LUN;
4935 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4936 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4937 sh->cmd_per_lun = sh->can_queue;
b705690d 4938 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 4939 sh->hostdata[0] = (unsigned long) h;
4940 sh->irq = h->intr[h->intr_mode];
4941 sh->unique_id = sh->irq;
73153fe5
WS		 4942 error = scsi_init_shared_tag_map(sh, sh->can_queue);
4943 if (error) {
4944 dev_err(&h->pdev->dev,
4945 "%s: scsi_init_shared_tag_map failed for controller %d\n",
4946 __func__, h->ctlr);
2946e82b
RE		 4947 scsi_host_put(sh);
4948 return error;
73153fe5 4949 }
2946e82b 4950 h->scsi_host = sh;
b705690d 4951 return 0;
2946e82b 4952}
b705690d 4953
2946e82b
RE		 4954static int hpsa_scsi_add_host(struct ctlr_info *h)
4955{
4956 int rv;
4957
4958 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
4959 if (rv) {
4960 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
4961 return rv;
4962 }
4963 scsi_scan_host(h->scsi_host);
4964 return 0;
edd16368
SC		 4965}
4966
73153fe5
WS		 4967/*
4968 * The block layer has already gone to the trouble of picking out a unique,
4969 * small-integer tag for this request. We use an offset from that value as
4970 * an index to select our command block. (The offset allows us to reserve the
4971 * low-numbered entries for our own uses.)
4972 */
4973static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
4974{
4975 int idx = scmd->request->tag;
4976
4977 if (idx < 0)
4978 return idx;
4979
4980 /* Offset to leave space for internal cmds. */
4981 return idx += HPSA_NRESERVED_CMDS;
4982}
4983
b69324ff
WS		 4984/*
4985 * Send a TEST_UNIT_READY command to the specified LUN using the specified
4986 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
4987 */
4988static int hpsa_send_test_unit_ready(struct ctlr_info *h,
4989 struct CommandList *c, unsigned char lunaddr[],
4990 int reply_queue)
4991{
4992 int rc;
4993
4994 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4995 (void) fill_cmd(c, TEST_UNIT_READY, h,
4996 NULL, 0, 0, lunaddr, TYPE_CMD);
4997 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
4998 if (rc)
4999 return rc;
5000 /* no unmap needed here because no data xfer. */
5001
5002 /* Check if the unit is already ready. */
5003 if (c->err_info->CommandStatus == CMD_SUCCESS)
5004 return 0;
5005
5006 /*
5007 * The first command sent after reset will receive "unit attention" to
5008 * indicate that the LUN has been reset...this is actually what we're
5009 * looking for (but, success is good too).
5010 */
5011 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5012 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5013 (c->err_info->SenseInfo[2] == NO_SENSE ||
5014 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5015 return 0;
5016
5017 return 1;
5018}
5019
5020/*
5021 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5022 * returns zero when the unit is ready, and non-zero when giving up.
5023 */
5024static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5025 struct CommandList *c,
5026 unsigned char lunaddr[], int reply_queue)
edd16368 5027{
8919358e 5028 int rc;
edd16368
SC		 5029 int count = 0;
5030 int waittime = 1; /* seconds */
edd16368
SC		 5031
5032 /* Send test unit ready until device ready, or give up. */
b69324ff 5033 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5034
b69324ff
WS		 5035 /*
5036 * Wait for a bit. do this first, because if we send
edd16368
SC		 5037 * the TUR right away, the reset will just abort it.
5038 */
5039 msleep(1000 * waittime);
b69324ff
WS		 5040
5041 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5042 if (!rc)
5043 break;
edd16368
SC		 5044
5045 /* Increase wait time with each try, up to a point. */
5046 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5047 waittime *= 2;
edd16368 5048
b69324ff
WS		 5049 dev_warn(&h->pdev->dev,
5050 "waiting %d secs for device to become ready.\n",
5051 waittime);
5052 }
edd16368 5053
b69324ff
WS		 5054 return rc;
5055}
edd16368 5056
b69324ff
WS		 5057static int wait_for_device_to_become_ready(struct ctlr_info *h,
5058 unsigned char lunaddr[],
5059 int reply_queue)
5060{
5061 int first_queue;
5062 int last_queue;
5063 int rq;
5064 int rc = 0;
5065 struct CommandList *c;
5066
5067 c = cmd_alloc(h);
5068
5069 /*
5070 * If no specific reply queue was requested, then send the TUR
5071 * repeatedly, requesting a reply on each reply queue; otherwise execute
5072 * the loop exactly once using only the specified queue.
5073 */
5074 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5075 first_queue = 0;
5076 last_queue = h->nreply_queues - 1;
5077 } else {
5078 first_queue = reply_queue;
5079 last_queue = reply_queue;
5080 }
5081
5082 for (rq = first_queue; rq <= last_queue; rq++) {
5083 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5084 if (rc)
edd16368 5085 break;
edd16368
SC		 5086 }
5087
5088 if (rc)
5089 dev_warn(&h->pdev->dev, "giving up on device.\n");
5090 else
5091 dev_warn(&h->pdev->dev, "device is ready.\n");
5092
45fcb86e 5093 cmd_free(h, c);
edd16368
SC		 5094 return rc;
5095}
5096
5097/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5098 * complaining. Doing a host- or bus-reset can't do anything good here.
5099 */
5100static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5101{
5102 int rc;
5103 struct ctlr_info *h;
5104 struct hpsa_scsi_dev_t *dev;
73153fe5 5105 char msg[40];
edd16368
SC		 5106
5107 /* find the controller to which the command to be aborted was sent */
5108 h = sdev_to_hba(scsicmd->device);
5109 if (h == NULL) /* paranoia */
5110 return FAILED;
e345893b
DB		 5111
5112 if (lockup_detected(h))
5113 return FAILED;
5114
edd16368
SC		 5115 dev = scsicmd->device->hostdata;
5116 if (!dev) {
d604f533 5117 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5118 return FAILED;
5119 }
25163bd5
WS		 5120
5121 /* if controller locked up, we can guarantee command won't complete */
5122 if (lockup_detected(h)) {
73153fe5
WS		 5123 sprintf(msg, "cmd %d RESET FAILED, lockup detected",
5124 hpsa_get_cmd_index(scsicmd));
5125 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5126 return FAILED;
5127 }
5128
5129 /* this reset request might be the result of a lockup; check */
5130 if (detect_controller_lockup(h)) {
73153fe5
WS		 5131 sprintf(msg, "cmd %d RESET FAILED, new lockup detected",
5132 hpsa_get_cmd_index(scsicmd));
5133 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5134 return FAILED;
5135 }
5136
d604f533
WS		 5137 /* Do not attempt on controller */
5138 if (is_hba_lunid(dev->scsi3addr))
5139 return SUCCESS;
5140
25163bd5
WS		 5141 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
5142
edd16368 5143 /* send a reset to the SCSI LUN which the command was sent to */
d604f533
WS		 5144 rc = hpsa_do_reset(h, dev, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
5145 DEFAULT_REPLY_QUEUE);
5146 sprintf(msg, "reset %s", rc == 0 ? "completed successfully" : "failed");
5147 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
5148 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5149}
5150
6cba3f19
SC		 5151static void swizzle_abort_tag(u8 *tag)
5152{
5153 u8 original_tag[8];
5154
5155 memcpy(original_tag, tag, 8);
5156 tag[0] = original_tag[3];
5157 tag[1] = original_tag[2];
5158 tag[2] = original_tag[1];
5159 tag[3] = original_tag[0];
5160 tag[4] = original_tag[7];
5161 tag[5] = original_tag[6];
5162 tag[6] = original_tag[5];
5163 tag[7] = original_tag[4];
5164}
5165
17eb87d2 5166static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5167 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5168{
2b08b3e9 5169 u64 tag;
17eb87d2
ST		 5170 if (c->cmd_type == CMD_IOACCEL1) {
5171 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5172 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5173 tag = le64_to_cpu(cm1->tag);
5174 *tagupper = cpu_to_le32(tag >> 32);
5175 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5176 return;
5177 }
5178 if (c->cmd_type == CMD_IOACCEL2) {
5179 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5180 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5181 /* upper tag not used in ioaccel2 mode */
5182 memset(tagupper, 0, sizeof(*tagupper));
5183 *taglower = cm2->Tag;
54b6e9e9 5184 return;
17eb87d2 5185 }
2b08b3e9
DB		 5186 tag = le64_to_cpu(c->Header.tag);
5187 *tagupper = cpu_to_le32(tag >> 32);
5188 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5189}
5190
75167d2c 5191static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5192 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5193{
5194 int rc = IO_OK;
5195 struct CommandList *c;
5196 struct ErrorInfo *ei;
2b08b3e9 5197 __le32 tagupper, taglower;
75167d2c 5198
45fcb86e 5199 c = cmd_alloc(h);
75167d2c 5200
a2dac136 5201 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5202 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5203 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5204 if (h->needs_abort_tags_swizzled)
6cba3f19 5205 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5206 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5207 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5208 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5209 __func__, tagupper, taglower);
75167d2c
SC		 5210 /* no unmap needed here because no data xfer. */
5211
5212 ei = c->err_info;
5213 switch (ei->CommandStatus) {
5214 case CMD_SUCCESS:
5215 break;
9437ac43
SC		 5216 case CMD_TMF_STATUS:
5217 rc = hpsa_evaluate_tmf_status(h, c);
5218 break;
75167d2c
SC		 5219 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5220 rc = -1;
5221 break;
5222 default:
5223 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5224 __func__, tagupper, taglower);
d1e8beac 5225 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5226 rc = -1;
5227 break;
5228 }
45fcb86e 5229 cmd_free(h, c);
dd0e19f3
ST		 5230 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5231 __func__, tagupper, taglower);
75167d2c
SC		 5232 return rc;
5233}
5234
8be986cc
SC		 5235static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5236 struct CommandList *command_to_abort, int reply_queue)
5237{
5238 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5239 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5240 struct io_accel2_cmd *c2a =
5241 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5242 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5243 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5244
5245 /*
5246 * We're overlaying struct hpsa_tmf_struct on top of something which
5247 * was allocated as a struct io_accel2_cmd, so we better be sure it
5248 * actually fits, and doesn't overrun the error info space.
5249 */
5250 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5251 sizeof(struct io_accel2_cmd));
5252 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5253 offsetof(struct hpsa_tmf_struct, error_len) +
5254 sizeof(ac->error_len));
5255
5256 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5257 c->scsi_cmd = SCSI_CMD_BUSY;
5258
8be986cc
SC		 5259 /* Adjust the DMA address to point to the accelerated command buffer */
5260 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5261 (c->cmdindex * sizeof(struct io_accel2_cmd));
5262 BUG_ON(c->busaddr & 0x0000007F);
5263
5264 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5265 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5266 ac->reply_queue = reply_queue;
5267 ac->tmf = IOACCEL2_TMF_ABORT;
5268 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5269 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5270 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5271 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5272 ac->error_ptr = cpu_to_le64(c->busaddr +
5273 offsetof(struct io_accel2_cmd, error_data));
5274 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5275}
5276
54b6e9e9
ST		 5277/* ioaccel2 path firmware cannot handle abort task requests.
5278 * Change abort requests to physical target reset, and send to the
5279 * address of the physical disk used for the ioaccel 2 command.
5280 * Return 0 on success (IO_OK)
5281 * -1 on failure
5282 */
5283
5284static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5285 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5286{
5287 int rc = IO_OK;
5288 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5289 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5290 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5291 unsigned char *psa = &phys_scsi3addr[0];
5292
5293 /* Get a pointer to the hpsa logical device. */
7fa3030c 5294 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5295 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5296 if (dev == NULL) {
5297 dev_warn(&h->pdev->dev,
5298 "Cannot abort: no device pointer for command.\n");
5299 return -1; /* not abortable */
5300 }
5301
2ba8bfc8
SC		 5302 if (h->raid_offload_debug > 0)
5303 dev_info(&h->pdev->dev,
0d96ef5f 5304 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5305 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5306 "Reset as abort",
2ba8bfc8
SC		 5307 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5308 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5309
54b6e9e9
ST		 5310 if (!dev->offload_enabled) {
5311 dev_warn(&h->pdev->dev,
5312 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5313 return -1; /* not abortable */
5314 }
5315
5316 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5317 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5318 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5319 return -1; /* not abortable */
5320 }
5321
5322 /* send the reset */
2ba8bfc8
SC		 5323 if (h->raid_offload_debug > 0)
5324 dev_info(&h->pdev->dev,
5325 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5326 psa[0], psa[1], psa[2], psa[3],
5327 psa[4], psa[5], psa[6], psa[7]);
d604f533 5328 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5329 if (rc != 0) {
5330 dev_warn(&h->pdev->dev,
5331 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5332 psa[0], psa[1], psa[2], psa[3],
5333 psa[4], psa[5], psa[6], psa[7]);
5334 return rc; /* failed to reset */
5335 }
5336
5337 /* wait for device to recover */
b69324ff 5338 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5339 dev_warn(&h->pdev->dev,
5340 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5341 psa[0], psa[1], psa[2], psa[3],
5342 psa[4], psa[5], psa[6], psa[7]);
5343 return -1; /* failed to recover */
5344 }
5345
5346 /* device recovered */
5347 dev_info(&h->pdev->dev,
5348 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5349 psa[0], psa[1], psa[2], psa[3],
5350 psa[4], psa[5], psa[6], psa[7]);
5351
5352 return rc; /* success */
5353}
5354
8be986cc
SC		 5355static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5356 struct CommandList *abort, int reply_queue)
5357{
5358 int rc = IO_OK;
5359 struct CommandList *c;
5360 __le32 taglower, tagupper;
5361 struct hpsa_scsi_dev_t *dev;
5362 struct io_accel2_cmd *c2;
5363
5364 dev = abort->scsi_cmd->device->hostdata;
5365 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5366 return -1;
5367
5368 c = cmd_alloc(h);
5369 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5370 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5371 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5372 hpsa_get_tag(h, abort, &taglower, &tagupper);
5373 dev_dbg(&h->pdev->dev,
5374 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5375 __func__, tagupper, taglower);
5376 /* no unmap needed here because no data xfer. */
5377
5378 dev_dbg(&h->pdev->dev,
5379 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5380 __func__, tagupper, taglower, c2->error_data.serv_response);
5381 switch (c2->error_data.serv_response) {
5382 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5383 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5384 rc = 0;
5385 break;
5386 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5387 case IOACCEL2_SERV_RESPONSE_FAILURE:
5388 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5389 rc = -1;
5390 break;
5391 default:
5392 dev_warn(&h->pdev->dev,
5393 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5394 __func__, tagupper, taglower,
5395 c2->error_data.serv_response);
5396 rc = -1;
5397 }
5398 cmd_free(h, c);
5399 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5400 tagupper, taglower);
5401 return rc;
5402}
5403
6cba3f19 5404static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5405 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5406{
8be986cc
SC		 5407 /*
5408 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5409 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5410 * but not all underlying firmware can handle abort TMF.
5411 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5412 */
8be986cc
SC		 5413 if (abort->cmd_type == CMD_IOACCEL2) {
5414 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5415 return hpsa_send_abort_ioaccel2(h, abort,
5416 reply_queue);
5417 else
5418 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5419 abort, reply_queue);
8be986cc 5420 }
9b5c48c2 5421 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5422}
54b6e9e9 5423
25163bd5
WS		 5424/* Find out which reply queue a command was meant to return on */
5425static int hpsa_extract_reply_queue(struct ctlr_info *h,
5426 struct CommandList *c)
5427{
5428 if (c->cmd_type == CMD_IOACCEL2)
5429 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5430 return c->Header.ReplyQueue;
6cba3f19
SC		 5431}
5432
9b5c48c2
SC		 5433/*
5434 * Limit concurrency of abort commands to prevent
5435 * over-subscription of commands
5436 */
5437static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5438{
5439#define ABORT_CMD_WAIT_MSECS 5000
5440 return !wait_event_timeout(h->abort_cmd_wait_queue,
5441 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5442 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5443}
5444
75167d2c
SC		 5445/* Send an abort for the specified command.
5446 * If the device and controller support it,
5447 * send a task abort request.
5448 */
5449static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5450{
5451
a58e7e53 5452 int rc;
75167d2c
SC		 5453 struct ctlr_info *h;
5454 struct hpsa_scsi_dev_t *dev;
5455 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5456 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5457 char msg[256]; /* For debug messaging. */
5458 int ml = 0;
2b08b3e9 5459 __le32 tagupper, taglower;
25163bd5
WS		 5460 int refcount, reply_queue;
5461
5462 if (sc == NULL)
5463 return FAILED;
75167d2c 5464
9b5c48c2
SC		 5465 if (sc->device == NULL)
5466 return FAILED;
5467
75167d2c
SC		 5468 /* Find the controller of the command to be aborted */
5469 h = sdev_to_hba(sc->device);
9b5c48c2 5470 if (h == NULL)
75167d2c
SC		 5471 return FAILED;
5472
25163bd5
WS		 5473 /* Find the device of the command to be aborted */
5474 dev = sc->device->hostdata;
5475 if (!dev) {
5476 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5477 msg);
e345893b 5478 return FAILED;
25163bd5
WS		 5479 }
5480
5481 /* If controller locked up, we can guarantee command won't complete */
5482 if (lockup_detected(h)) {
5483 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5484 "ABORT FAILED, lockup detected");
5485 return FAILED;
5486 }
5487
5488 /* This is a good time to check if controller lockup has occurred */
5489 if (detect_controller_lockup(h)) {
5490 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5491 "ABORT FAILED, new lockup detected");
5492 return FAILED;
5493 }
e345893b 5494
75167d2c
SC		 5495 /* Check that controller supports some kind of task abort */
5496 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5497 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5498 return FAILED;
5499
5500 memset(msg, 0, sizeof(msg));
4b761557 5501 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5502 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5503 sc->device->id, sc->device->lun,
4b761557 5504 "Aborting command", sc);
75167d2c 5505
75167d2c
SC		 5506 /* Get SCSI command to be aborted */
5507 abort = (struct CommandList *) sc->host_scribble;
5508 if (abort == NULL) {
281a7fd0
WS		 5509 /* This can happen if the command already completed. */
5510 return SUCCESS;
5511 }
5512 refcount = atomic_inc_return(&abort->refcount);
5513 if (refcount == 1) { /* Command is done already. */
5514 cmd_free(h, abort);
5515 return SUCCESS;
75167d2c 5516 }
9b5c48c2
SC		 5517
5518 /* Don't bother trying the abort if we know it won't work. */
5519 if (abort->cmd_type != CMD_IOACCEL2 &&
5520 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5521 cmd_free(h, abort);
5522 return FAILED;
5523 }
5524
a58e7e53
WS		 5525 /*
5526 * Check that we're aborting the right command.
5527 * It's possible the CommandList already completed and got re-used.
5528 */
5529 if (abort->scsi_cmd != sc) {
5530 cmd_free(h, abort);
5531 return SUCCESS;
5532 }
5533
5534 abort->abort_pending = true;
17eb87d2 5535 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5536 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5537 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5538 as = abort->scsi_cmd;
75167d2c 5539 if (as != NULL)
4b761557
RE		 5540 ml += sprintf(msg+ml,
5541 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5542 as->cmd_len, as->cmnd[0], as->cmnd[1],
5543 as->serial_number);
5544 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5545 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5546
75167d2c
SC		 5547 /*
5548 * Command is in flight, or possibly already completed
5549 * by the firmware (but not to the scsi mid layer) but we can't
5550 * distinguish which. Send the abort down.
5551 */
9b5c48c2
SC		 5552 if (wait_for_available_abort_cmd(h)) {
5553 dev_warn(&h->pdev->dev,
4b761557
RE		 5554 "%s FAILED, timeout waiting for an abort command to become available.\n",
5555 msg);
9b5c48c2
SC		 5556 cmd_free(h, abort);
5557 return FAILED;
5558 }
25163bd5 5559 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5560 atomic_inc(&h->abort_cmds_available);
5561 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5562 if (rc != 0) {
4b761557 5563 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5564 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5565 "FAILED to abort command");
281a7fd0 5566 cmd_free(h, abort);
75167d2c
SC		 5567 return FAILED;
5568 }
4b761557 5569 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5570 wait_event(h->event_sync_wait_queue,
a58e7e53 5571 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5572 cmd_free(h, abort);
a58e7e53 5573 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5574}
5575
73153fe5
WS		 5576/*
5577 * For operations with an associated SCSI command, a command block is allocated
5578 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5579 * block request tag as an index into a table of entries. cmd_tagged_free() is
5580 * the complement, although cmd_free() may be called instead.
5581 */
5582static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5583 struct scsi_cmnd *scmd)
5584{
5585 int idx = hpsa_get_cmd_index(scmd);
5586 struct CommandList *c = h->cmd_pool + idx;
5587
5588 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5589 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5590 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5591 /* The index value comes from the block layer, so if it's out of
5592 * bounds, it's probably not our bug.
5593 */
5594 BUG();
5595 }
5596
5597 atomic_inc(&c->refcount);
5598 if (unlikely(!hpsa_is_cmd_idle(c))) {
5599 /*
5600 * We expect that the SCSI layer will hand us a unique tag
5601 * value. Thus, there should never be a collision here between
5602 * two requests...because if the selected command isn't idle
5603 * then someone is going to be very disappointed.
5604 */
5605 dev_err(&h->pdev->dev,
5606 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5607 idx);
5608 if (c->scsi_cmd != NULL)
5609 scsi_print_command(c->scsi_cmd);
5610 scsi_print_command(scmd);
5611 }
5612
5613 hpsa_cmd_partial_init(h, idx, c);
5614 return c;
5615}
5616
5617static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5618{
5619 /*
5620 * Release our reference to the block. We don't need to do anything
5621 * else to free it, because it is accessed by index. (There's no point
5622 * in checking the result of the decrement, since we cannot guarantee
5623 * that there isn't a concurrent abort which is also accessing it.)
5624 */
5625 (void)atomic_dec(&c->refcount);
5626}
5627
edd16368
SC		 5628/*
5629 * For operations that cannot sleep, a command block is allocated at init,
5630 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5631 * which ones are free or in use. Lock must be held when calling this.
5632 * cmd_free() is the complement.
bf43caf3
RE		 5633 * This function never gives up and returns NULL. If it hangs,
5634 * another thread must call cmd_free() to free some tags.
edd16368 5635 */
281a7fd0 5636
edd16368
SC		 5637static struct CommandList *cmd_alloc(struct ctlr_info *h)
5638{
5639 struct CommandList *c;
360c73bd 5640 int refcount, i;
73153fe5 5641 int offset = 0;
4c413128 5642
33811026
RE		 5643 /*
5644 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5645 * multiple threads could get in here, and one thread could
5646 * be scanning through the list of bits looking for a free
5647 * one, but the free ones are always behind him, and other
5648 * threads sneak in behind him and eat them before he can
5649 * get to them, so that while there is always a free one, a
5650 * very unlucky thread might be starved anyway, never able to
5651 * beat the other threads. In reality, this happens so
5652 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5653 *
5654 * Note that we start allocating commands before the SCSI host structure
5655 * is initialized. Since the search starts at bit zero, this
5656 * all works, since we have at least one command structure available;
5657 * however, it means that the structures with the low indexes have to be
5658 * reserved for driver-initiated requests, while requests from the block
5659 * layer will use the higher indexes.
4c413128 5660 */
edd16368 5661
281a7fd0 5662 for (;;) {
73153fe5
WS		 5663 i = find_next_zero_bit(h->cmd_pool_bits,
5664 HPSA_NRESERVED_CMDS,
5665 offset);
5666 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5667 offset = 0;
5668 continue;
5669 }
5670 c = h->cmd_pool + i;
5671 refcount = atomic_inc_return(&c->refcount);
5672 if (unlikely(refcount > 1)) {
5673 cmd_free(h, c); /* already in use */
73153fe5 5674 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5675 continue;
5676 }
5677 set_bit(i & (BITS_PER_LONG - 1),
5678 h->cmd_pool_bits + (i / BITS_PER_LONG));
5679 break; /* it's ours now. */
5680 }
360c73bd 5681 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5682 return c;
5683}
5684
73153fe5
WS		 5685/*
5686 * This is the complementary operation to cmd_alloc(). Note, however, in some
5687 * corner cases it may also be used to free blocks allocated by
5688 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5689 * the clear-bit is harmless.
5690 */
edd16368
SC		 5691static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5692{
281a7fd0
WS		 5693 if (atomic_dec_and_test(&c->refcount)) {
5694 int i;
edd16368 5695
281a7fd0
WS		 5696 i = c - h->cmd_pool;
5697 clear_bit(i & (BITS_PER_LONG - 1),
5698 h->cmd_pool_bits + (i / BITS_PER_LONG));
5699 }
edd16368
SC		 5700}
5701
edd16368
SC		 5702#ifdef CONFIG_COMPAT
5703
42a91641
DB		 5704static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5705 void __user *arg)
edd16368
SC		 5706{
5707 IOCTL32_Command_struct __user *arg32 =
5708 (IOCTL32_Command_struct __user *) arg;
5709 IOCTL_Command_struct arg64;
5710 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5711 int err;
5712 u32 cp;
5713
938abd84 5714 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5715 err = 0;
5716 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5717 sizeof(arg64.LUN_info));
5718 err |= copy_from_user(&arg64.Request, &arg32->Request,
5719 sizeof(arg64.Request));
5720 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5721 sizeof(arg64.error_info));
5722 err |= get_user(arg64.buf_size, &arg32->buf_size);
5723 err |= get_user(cp, &arg32->buf);
5724 arg64.buf = compat_ptr(cp);
5725 err |= copy_to_user(p, &arg64, sizeof(arg64));
5726
5727 if (err)
5728 return -EFAULT;
5729
42a91641 5730 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5731 if (err)
5732 return err;
5733 err |= copy_in_user(&arg32->error_info, &p->error_info,
5734 sizeof(arg32->error_info));
5735 if (err)
5736 return -EFAULT;
5737 return err;
5738}
5739
5740static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5741 int cmd, void __user *arg)
edd16368
SC		 5742{
5743 BIG_IOCTL32_Command_struct __user *arg32 =
5744 (BIG_IOCTL32_Command_struct __user *) arg;
5745 BIG_IOCTL_Command_struct arg64;
5746 BIG_IOCTL_Command_struct __user *p =
5747 compat_alloc_user_space(sizeof(arg64));
5748 int err;
5749 u32 cp;
5750
938abd84 5751 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5752 err = 0;
5753 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5754 sizeof(arg64.LUN_info));
5755 err |= copy_from_user(&arg64.Request, &arg32->Request,
5756 sizeof(arg64.Request));
5757 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5758 sizeof(arg64.error_info));
5759 err |= get_user(arg64.buf_size, &arg32->buf_size);
5760 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5761 err |= get_user(cp, &arg32->buf);
5762 arg64.buf = compat_ptr(cp);
5763 err |= copy_to_user(p, &arg64, sizeof(arg64));
5764
5765 if (err)
5766 return -EFAULT;
5767
42a91641 5768 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5769 if (err)
5770 return err;
5771 err |= copy_in_user(&arg32->error_info, &p->error_info,
5772 sizeof(arg32->error_info));
5773 if (err)
5774 return -EFAULT;
5775 return err;
5776}
71fe75a7 5777
42a91641 5778static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5779{
5780 switch (cmd) {
5781 case CCISS_GETPCIINFO:
5782 case CCISS_GETINTINFO:
5783 case CCISS_SETINTINFO:
5784 case CCISS_GETNODENAME:
5785 case CCISS_SETNODENAME:
5786 case CCISS_GETHEARTBEAT:
5787 case CCISS_GETBUSTYPES:
5788 case CCISS_GETFIRMVER:
5789 case CCISS_GETDRIVVER:
5790 case CCISS_REVALIDVOLS:
5791 case CCISS_DEREGDISK:
5792 case CCISS_REGNEWDISK:
5793 case CCISS_REGNEWD:
5794 case CCISS_RESCANDISK:
5795 case CCISS_GETLUNINFO:
5796 return hpsa_ioctl(dev, cmd, arg);
5797
5798 case CCISS_PASSTHRU32:
5799 return hpsa_ioctl32_passthru(dev, cmd, arg);
5800 case CCISS_BIG_PASSTHRU32:
5801 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5802
5803 default:
5804 return -ENOIOCTLCMD;
5805 }
5806}
edd16368
SC		 5807#endif
5808
5809static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5810{
5811 struct hpsa_pci_info pciinfo;
5812
5813 if (!argp)
5814 return -EINVAL;
5815 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5816 pciinfo.bus = h->pdev->bus->number;
5817 pciinfo.dev_fn = h->pdev->devfn;
5818 pciinfo.board_id = h->board_id;
5819 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5820 return -EFAULT;
5821 return 0;
5822}
5823
5824static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5825{
5826 DriverVer_type DriverVer;
5827 unsigned char vmaj, vmin, vsubmin;
5828 int rc;
5829
5830 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5831 &vmaj, &vmin, &vsubmin);
5832 if (rc != 3) {
5833 dev_info(&h->pdev->dev, "driver version string '%s' "
5834 "unrecognized.", HPSA_DRIVER_VERSION);
5835 vmaj = 0;
5836 vmin = 0;
5837 vsubmin = 0;
5838 }
5839 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5840 if (!argp)
5841 return -EINVAL;
5842 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5843 return -EFAULT;
5844 return 0;
5845}
5846
5847static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5848{
5849 IOCTL_Command_struct iocommand;
5850 struct CommandList *c;
5851 char *buff = NULL;
50a0decf 5852 u64 temp64;
c1f63c8f 5853 int rc = 0;
edd16368
SC		 5854
5855 if (!argp)
5856 return -EINVAL;
5857 if (!capable(CAP_SYS_RAWIO))
5858 return -EPERM;
5859 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5860 return -EFAULT;
5861 if ((iocommand.buf_size < 1) &&
5862 (iocommand.Request.Type.Direction != XFER_NONE)) {
5863 return -EINVAL;
5864 }
5865 if (iocommand.buf_size > 0) {
5866 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5867 if (buff == NULL)
2dd02d74 5868 return -ENOMEM;
9233fb10 5869 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5870 /* Copy the data into the buffer we created */
5871 if (copy_from_user(buff, iocommand.buf,
5872 iocommand.buf_size)) {
c1f63c8f
SC		 5873 rc = -EFAULT;
5874 goto out_kfree;
b03a7771
SC		 5875 }
5876 } else {
5877 memset(buff, 0, iocommand.buf_size);
edd16368 5878 }
b03a7771 5879 }
45fcb86e 5880 c = cmd_alloc(h);
bf43caf3 5881
edd16368
SC		 5882 /* Fill in the command type */
5883 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 5884 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 5885 /* Fill in Command Header */
5886 c->Header.ReplyQueue = 0; /* unused in simple mode */
5887 if (iocommand.buf_size > 0) { /* buffer to fill */
5888 c->Header.SGList = 1;
50a0decf 5889 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5890 } else { /* no buffers to fill */
5891 c->Header.SGList = 0;
50a0decf 5892 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5893 }
5894 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5895
5896 /* Fill in Request block */
5897 memcpy(&c->Request, &iocommand.Request,
5898 sizeof(c->Request));
5899
5900 /* Fill in the scatter gather information */
5901 if (iocommand.buf_size > 0) {
50a0decf 5902 temp64 = pci_map_single(h->pdev, buff,
edd16368 5903 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5904 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5905 c->SG[0].Addr = cpu_to_le64(0);
5906 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5907 rc = -ENOMEM;
5908 goto out;
5909 }
50a0decf
SC		 5910 c->SG[0].Addr = cpu_to_le64(temp64);
5911 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5912 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5913 }
25163bd5 5914 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5915 if (iocommand.buf_size > 0)
5916 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5917 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5918 if (rc) {
5919 rc = -EIO;
5920 goto out;
5921 }
edd16368
SC		 5922
5923 /* Copy the error information out */
5924 memcpy(&iocommand.error_info, c->err_info,
5925 sizeof(iocommand.error_info));
5926 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5927 rc = -EFAULT;
5928 goto out;
edd16368 5929 }
9233fb10 5930 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5931 iocommand.buf_size > 0) {
edd16368
SC		 5932 /* Copy the data out of the buffer we created */
5933 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5934 rc = -EFAULT;
5935 goto out;
edd16368
SC		 5936 }
5937 }
c1f63c8f 5938out:
45fcb86e 5939 cmd_free(h, c);
c1f63c8f
SC		 5940out_kfree:
5941 kfree(buff);
5942 return rc;
edd16368
SC		 5943}
5944
5945static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5946{
5947 BIG_IOCTL_Command_struct *ioc;
5948 struct CommandList *c;
5949 unsigned char **buff = NULL;
5950 int *buff_size = NULL;
50a0decf 5951 u64 temp64;
edd16368
SC		 5952 BYTE sg_used = 0;
5953 int status = 0;
01a02ffc
SC		 5954 u32 left;
5955 u32 sz;
edd16368
SC		 5956 BYTE __user *data_ptr;
5957
5958 if (!argp)
5959 return -EINVAL;
5960 if (!capable(CAP_SYS_RAWIO))
5961 return -EPERM;
5962 ioc = (BIG_IOCTL_Command_struct *)
5963 kmalloc(sizeof(*ioc), GFP_KERNEL);
5964 if (!ioc) {
5965 status = -ENOMEM;
5966 goto cleanup1;
5967 }
5968 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5969 status = -EFAULT;
5970 goto cleanup1;
5971 }
5972 if ((ioc->buf_size < 1) &&
5973 (ioc->Request.Type.Direction != XFER_NONE)) {
5974 status = -EINVAL;
5975 goto cleanup1;
5976 }
5977 /* Check kmalloc limits using all SGs */
5978 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5979 status = -EINVAL;
5980 goto cleanup1;
5981 }
d66ae08b 5982 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5983 status = -EINVAL;
5984 goto cleanup1;
5985 }
d66ae08b 5986 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5987 if (!buff) {
5988 status = -ENOMEM;
5989 goto cleanup1;
5990 }
d66ae08b 5991 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5992 if (!buff_size) {
5993 status = -ENOMEM;
5994 goto cleanup1;
5995 }
5996 left = ioc->buf_size;
5997 data_ptr = ioc->buf;
5998 while (left) {
5999 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6000 buff_size[sg_used] = sz;
6001 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6002 if (buff[sg_used] == NULL) {
6003 status = -ENOMEM;
6004 goto cleanup1;
6005 }
9233fb10 6006 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6007 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6008 status = -EFAULT;
edd16368
SC		 6009 goto cleanup1;
6010 }
6011 } else
6012 memset(buff[sg_used], 0, sz);
6013 left -= sz;
6014 data_ptr += sz;
6015 sg_used++;
6016 }
45fcb86e 6017 c = cmd_alloc(h);
bf43caf3 6018
edd16368 6019 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6020 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6021 c->Header.ReplyQueue = 0;
50a0decf
SC		 6022 c->Header.SGList = (u8) sg_used;
6023 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6024 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6025 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6026 if (ioc->buf_size > 0) {
6027 int i;
6028 for (i = 0; i < sg_used; i++) {
50a0decf 6029 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6030 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6031 if (dma_mapping_error(&h->pdev->dev,
6032 (dma_addr_t) temp64)) {
6033 c->SG[i].Addr = cpu_to_le64(0);
6034 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6035 hpsa_pci_unmap(h->pdev, c, i,
6036 PCI_DMA_BIDIRECTIONAL);
6037 status = -ENOMEM;
e2d4a1f6 6038 goto cleanup0;
bcc48ffa 6039 }
50a0decf
SC		 6040 c->SG[i].Addr = cpu_to_le64(temp64);
6041 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6042 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6043 }
50a0decf 6044 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6045 }
25163bd5 6046 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6047 if (sg_used)
6048 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6049 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6050 if (status) {
6051 status = -EIO;
6052 goto cleanup0;
6053 }
6054
edd16368
SC		 6055 /* Copy the error information out */
6056 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6057 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6058 status = -EFAULT;
e2d4a1f6 6059 goto cleanup0;
edd16368 6060 }
9233fb10 6061 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6062 int i;
6063
edd16368
SC		 6064 /* Copy the data out of the buffer we created */
6065 BYTE __user *ptr = ioc->buf;
6066 for (i = 0; i < sg_used; i++) {
6067 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6068 status = -EFAULT;
e2d4a1f6 6069 goto cleanup0;
edd16368
SC		 6070 }
6071 ptr += buff_size[i];
6072 }
6073 }
edd16368 6074 status = 0;
e2d4a1f6 6075cleanup0:
45fcb86e 6076 cmd_free(h, c);
edd16368
SC		 6077cleanup1:
6078 if (buff) {
2b08b3e9
DB		 6079 int i;
6080
edd16368
SC		 6081 for (i = 0; i < sg_used; i++)
6082 kfree(buff[i]);
6083 kfree(buff);
6084 }
6085 kfree(buff_size);
6086 kfree(ioc);
6087 return status;
6088}
6089
6090static void check_ioctl_unit_attention(struct ctlr_info *h,
6091 struct CommandList *c)
6092{
6093 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6094 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6095 (void) check_for_unit_attention(h, c);
6096}
0390f0c0 6097
edd16368
SC		 6098/*
6099 * ioctl
6100 */
42a91641 6101static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6102{
6103 struct ctlr_info *h;
6104 void __user *argp = (void __user *)arg;
0390f0c0 6105 int rc;
edd16368
SC		 6106
6107 h = sdev_to_hba(dev);
6108
6109 switch (cmd) {
6110 case CCISS_DEREGDISK:
6111 case CCISS_REGNEWDISK:
6112 case CCISS_REGNEWD:
a08a8471 6113 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6114 return 0;
6115 case CCISS_GETPCIINFO:
6116 return hpsa_getpciinfo_ioctl(h, argp);
6117 case CCISS_GETDRIVVER:
6118 return hpsa_getdrivver_ioctl(h, argp);
6119 case CCISS_PASSTHRU:
34f0c627 6120 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6121 return -EAGAIN;
6122 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6123 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6124 return rc;
edd16368 6125 case CCISS_BIG_PASSTHRU:
34f0c627 6126 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6127 return -EAGAIN;
6128 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6129 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6130 return rc;
edd16368
SC		 6131 default:
6132 return -ENOTTY;
6133 }
6134}
6135
bf43caf3 6136static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6137 u8 reset_type)
64670ac8
SC		 6138{
6139 struct CommandList *c;
6140
6141 c = cmd_alloc(h);
bf43caf3 6142
a2dac136
SC		 6143 /* fill_cmd can't fail here, no data buffer to map */
6144 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6145 RAID_CTLR_LUNID, TYPE_MSG);
6146 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6147 c->waiting = NULL;
6148 enqueue_cmd_and_start_io(h, c);
6149 /* Don't wait for completion, the reset won't complete. Don't free
6150 * the command either. This is the last command we will send before
6151 * re-initializing everything, so it doesn't matter and won't leak.
6152 */
bf43caf3 6153 return;
64670ac8
SC		 6154}
6155
a2dac136 6156static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6157 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6158 int cmd_type)
6159{
6160 int pci_dir = XFER_NONE;
9b5c48c2 6161 u64 tag; /* for commands to be aborted */
edd16368
SC		 6162
6163 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6164 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6165 c->Header.ReplyQueue = 0;
6166 if (buff != NULL && size > 0) {
6167 c->Header.SGList = 1;
50a0decf 6168 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6169 } else {
6170 c->Header.SGList = 0;
50a0decf 6171 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6172 }
edd16368
SC		 6173 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6174
edd16368
SC		 6175 if (cmd_type == TYPE_CMD) {
6176 switch (cmd) {
6177 case HPSA_INQUIRY:
6178 /* are we trying to read a vital product page */
b7bb24eb 6179 if (page_code & VPD_PAGE) {
edd16368 6180 c->Request.CDB[1] = 0x01;
b7bb24eb 6181 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6182 }
6183 c->Request.CDBLen = 6;
a505b86f
SC		 6184 c->Request.type_attr_dir =
6185 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6186 c->Request.Timeout = 0;
6187 c->Request.CDB[0] = HPSA_INQUIRY;
6188 c->Request.CDB[4] = size & 0xFF;
6189 break;
6190 case HPSA_REPORT_LOG:
6191 case HPSA_REPORT_PHYS:
6192 /* Talking to controller so It's a physical command
6193 mode = 00 target = 0. Nothing to write.
6194 */
6195 c->Request.CDBLen = 12;
a505b86f
SC		 6196 c->Request.type_attr_dir =
6197 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6198 c->Request.Timeout = 0;
6199 c->Request.CDB[0] = cmd;
6200 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6201 c->Request.CDB[7] = (size >> 16) & 0xFF;
6202 c->Request.CDB[8] = (size >> 8) & 0xFF;
6203 c->Request.CDB[9] = size & 0xFF;
6204 break;
edd16368
SC		 6205 case HPSA_CACHE_FLUSH:
6206 c->Request.CDBLen = 12;
a505b86f
SC		 6207 c->Request.type_attr_dir =
6208 TYPE_ATTR_DIR(cmd_type,
6209 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6210 c->Request.Timeout = 0;
6211 c->Request.CDB[0] = BMIC_WRITE;
6212 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6213 c->Request.CDB[7] = (size >> 8) & 0xFF;
6214 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6215 break;
6216 case TEST_UNIT_READY:
6217 c->Request.CDBLen = 6;
a505b86f
SC		 6218 c->Request.type_attr_dir =
6219 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6220 c->Request.Timeout = 0;
6221 break;
283b4a9b
SC		 6222 case HPSA_GET_RAID_MAP:
6223 c->Request.CDBLen = 12;
a505b86f
SC		 6224 c->Request.type_attr_dir =
6225 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6226 c->Request.Timeout = 0;
6227 c->Request.CDB[0] = HPSA_CISS_READ;
6228 c->Request.CDB[1] = cmd;
6229 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6230 c->Request.CDB[7] = (size >> 16) & 0xFF;
6231 c->Request.CDB[8] = (size >> 8) & 0xFF;
6232 c->Request.CDB[9] = size & 0xFF;
6233 break;
316b221a
SC		 6234 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6235 c->Request.CDBLen = 10;
a505b86f
SC		 6236 c->Request.type_attr_dir =
6237 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6238 c->Request.Timeout = 0;
6239 c->Request.CDB[0] = BMIC_READ;
6240 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6241 c->Request.CDB[7] = (size >> 16) & 0xFF;
6242 c->Request.CDB[8] = (size >> 8) & 0xFF;
6243 break;
03383736
DB		 6244 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6245 c->Request.CDBLen = 10;
6246 c->Request.type_attr_dir =
6247 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6248 c->Request.Timeout = 0;
6249 c->Request.CDB[0] = BMIC_READ;
6250 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6251 c->Request.CDB[7] = (size >> 16) & 0xFF;
6252 c->Request.CDB[8] = (size >> 8) & 0XFF;
6253 break;
edd16368
SC		 6254 default:
6255 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6256 BUG();
a2dac136 6257 return -1;
edd16368
SC		 6258 }
6259 } else if (cmd_type == TYPE_MSG) {
6260 switch (cmd) {
6261
6262 case HPSA_DEVICE_RESET_MSG:
6263 c->Request.CDBLen = 16;
a505b86f
SC		 6264 c->Request.type_attr_dir =
6265 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6266 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6267 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6268 c->Request.CDB[0] = cmd;
21e89afd 6269 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6270 /* If bytes 4-7 are zero, it means reset the */
6271 /* LunID device */
6272 c->Request.CDB[4] = 0x00;
6273 c->Request.CDB[5] = 0x00;
6274 c->Request.CDB[6] = 0x00;
6275 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6276 break;
6277 case HPSA_ABORT_MSG:
9b5c48c2 6278 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6279 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6280 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6281 tag, c->Header.tag);
75167d2c 6282 c->Request.CDBLen = 16;
a505b86f
SC		 6283 c->Request.type_attr_dir =
6284 TYPE_ATTR_DIR(cmd_type,
6285 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6286 c->Request.Timeout = 0; /* Don't time out */
6287 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6288 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6289 c->Request.CDB[2] = 0x00; /* reserved */
6290 c->Request.CDB[3] = 0x00; /* reserved */
6291 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6292 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6293 c->Request.CDB[12] = 0x00; /* reserved */
6294 c->Request.CDB[13] = 0x00; /* reserved */
6295 c->Request.CDB[14] = 0x00; /* reserved */
6296 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6297 break;
edd16368
SC		 6298 default:
6299 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6300 cmd);
6301 BUG();
6302 }
6303 } else {
6304 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6305 BUG();
6306 }
6307
a505b86f 6308 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6309 case XFER_READ:
6310 pci_dir = PCI_DMA_FROMDEVICE;
6311 break;
6312 case XFER_WRITE:
6313 pci_dir = PCI_DMA_TODEVICE;
6314 break;
6315 case XFER_NONE:
6316 pci_dir = PCI_DMA_NONE;
6317 break;
6318 default:
6319 pci_dir = PCI_DMA_BIDIRECTIONAL;
6320 }
a2dac136
SC		 6321 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6322 return -1;
6323 return 0;
edd16368
SC		 6324}
6325
6326/*
6327 * Map (physical) PCI mem into (virtual) kernel space
6328 */
6329static void __iomem *remap_pci_mem(ulong base, ulong size)
6330{
6331 ulong page_base = ((ulong) base) & PAGE_MASK;
6332 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6333 void __iomem *page_remapped = ioremap_nocache(page_base,
6334 page_offs + size);
edd16368
SC		 6335
6336 return page_remapped ? (page_remapped + page_offs) : NULL;
6337}
6338
254f796b 6339static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6340{
254f796b 6341 return h->access.command_completed(h, q);
edd16368
SC		 6342}
6343
900c5440 6344static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6345{
6346 return h->access.intr_pending(h);
6347}
6348
6349static inline long interrupt_not_for_us(struct ctlr_info *h)
6350{
10f66018
SC		 6351 return (h->access.intr_pending(h) == 0) ||
6352 (h->interrupts_enabled == 0);
edd16368
SC		 6353}
6354
01a02ffc
SC		 6355static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6356 u32 raw_tag)
edd16368
SC		 6357{
6358 if (unlikely(tag_index >= h->nr_cmds)) {
6359 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6360 return 1;
6361 }
6362 return 0;
6363}
6364
5a3d16f5 6365static inline void finish_cmd(struct CommandList *c)
edd16368 6366{
e85c5974 6367 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6368 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6369 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6370 complete_scsi_command(c);
8be986cc 6371 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6372 complete(c->waiting);
a104c99f
SC		 6373}
6374
a9a3a273
SC		 6375
6376static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 6377{
a9a3a273
SC		 6378#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
6379#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 6380 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 6381 return tag & ~HPSA_SIMPLE_ERROR_BITS;
6382 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 6383}
6384
303932fd 6385/* process completion of an indexed ("direct lookup") command */
1d94f94d 6386static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6387 u32 raw_tag)
6388{
6389 u32 tag_index;
6390 struct CommandList *c;
6391
f2405db8 6392 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6393 if (!bad_tag(h, tag_index, raw_tag)) {
6394 c = h->cmd_pool + tag_index;
6395 finish_cmd(c);
6396 }
303932fd
DB		 6397}
6398
64670ac8
SC		 6399/* Some controllers, like p400, will give us one interrupt
6400 * after a soft reset, even if we turned interrupts off.
6401 * Only need to check for this in the hpsa_xxx_discard_completions
6402 * functions.
6403 */
6404static int ignore_bogus_interrupt(struct ctlr_info *h)
6405{
6406 if (likely(!reset_devices))
6407 return 0;
6408
6409 if (likely(h->interrupts_enabled))
6410 return 0;
6411
6412 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6413 "(known firmware bug.) Ignoring.\n");
6414
6415 return 1;
6416}
6417
254f796b
MG		 6418/*
6419 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6420 * Relies on (h-q[x] == x) being true for x such that
6421 * 0 <= x < MAX_REPLY_QUEUES.
6422 */
6423static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6424{
254f796b
MG		 6425 return container_of((queue - *queue), struct ctlr_info, q[0]);
6426}
6427
6428static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6429{
6430 struct ctlr_info *h = queue_to_hba(queue);
6431 u8 q = *(u8 *) queue;
64670ac8
SC		 6432 u32 raw_tag;
6433
6434 if (ignore_bogus_interrupt(h))
6435 return IRQ_NONE;
6436
6437 if (interrupt_not_for_us(h))
6438 return IRQ_NONE;
a0c12413 6439 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6440 while (interrupt_pending(h)) {
254f796b 6441 raw_tag = get_next_completion(h, q);
64670ac8 6442 while (raw_tag != FIFO_EMPTY)
254f796b 6443 raw_tag = next_command(h, q);
64670ac8 6444 }
64670ac8
SC		 6445 return IRQ_HANDLED;
6446}
6447
254f796b 6448static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6449{
254f796b 6450 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6451 u32 raw_tag;
254f796b 6452 u8 q = *(u8 *) queue;
64670ac8
SC		 6453
6454 if (ignore_bogus_interrupt(h))
6455 return IRQ_NONE;
6456
a0c12413 6457 h->last_intr_timestamp = get_jiffies_64();
254f796b 6458 raw_tag = get_next_completion(h, q);
64670ac8 6459 while (raw_tag != FIFO_EMPTY)
254f796b 6460 raw_tag = next_command(h, q);
64670ac8
SC		 6461 return IRQ_HANDLED;
6462}
6463
254f796b 6464static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6465{
254f796b 6466 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6467 u32 raw_tag;
254f796b 6468 u8 q = *(u8 *) queue;
edd16368
SC		 6469
6470 if (interrupt_not_for_us(h))
6471 return IRQ_NONE;
a0c12413 6472 h->last_intr_timestamp = get_jiffies_64();
10f66018 6473 while (interrupt_pending(h)) {
254f796b 6474 raw_tag = get_next_completion(h, q);
10f66018 6475 while (raw_tag != FIFO_EMPTY) {
f2405db8 6476 process_indexed_cmd(h, raw_tag);
254f796b 6477 raw_tag = next_command(h, q);
10f66018
SC		 6478 }
6479 }
10f66018
SC		 6480 return IRQ_HANDLED;
6481}
6482
254f796b 6483static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6484{
254f796b 6485 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6486 u32 raw_tag;
254f796b 6487 u8 q = *(u8 *) queue;
10f66018 6488
a0c12413 6489 h->last_intr_timestamp = get_jiffies_64();
254f796b 6490 raw_tag = get_next_completion(h, q);
303932fd 6491 while (raw_tag != FIFO_EMPTY) {
f2405db8 6492 process_indexed_cmd(h, raw_tag);
254f796b 6493 raw_tag = next_command(h, q);
edd16368 6494 }
edd16368
SC		 6495 return IRQ_HANDLED;
6496}
6497
a9a3a273
SC		 6498/* Send a message CDB to the firmware. Careful, this only works
6499 * in simple mode, not performant mode due to the tag lookup.
6500 * We only ever use this immediately after a controller reset.
6501 */
6f039790
GKH		 6502static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6503 unsigned char type)
edd16368
SC		 6504{
6505 struct Command {
6506 struct CommandListHeader CommandHeader;
6507 struct RequestBlock Request;
6508 struct ErrDescriptor ErrorDescriptor;
6509 };
6510 struct Command *cmd;
6511 static const size_t cmd_sz = sizeof(*cmd) +
6512 sizeof(cmd->ErrorDescriptor);
6513 dma_addr_t paddr64;
2b08b3e9
DB		 6514 __le32 paddr32;
6515 u32 tag;
edd16368
SC		 6516 void __iomem *vaddr;
6517 int i, err;
6518
6519 vaddr = pci_ioremap_bar(pdev, 0);
6520 if (vaddr == NULL)
6521 return -ENOMEM;
6522
6523 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6524 * CCISS commands, so they must be allocated from the lower 4GiB of
6525 * memory.
6526 */
6527 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6528 if (err) {
6529 iounmap(vaddr);
1eaec8f3 6530 return err;
edd16368
SC		 6531 }
6532
6533 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6534 if (cmd == NULL) {
6535 iounmap(vaddr);
6536 return -ENOMEM;
6537 }
6538
6539 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6540 * although there's no guarantee, we assume that the address is at
6541 * least 4-byte aligned (most likely, it's page-aligned).
6542 */
2b08b3e9 6543 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6544
6545 cmd->CommandHeader.ReplyQueue = 0;
6546 cmd->CommandHeader.SGList = 0;
50a0decf 6547 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6548 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6549 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6550
6551 cmd->Request.CDBLen = 16;
a505b86f
SC		 6552 cmd->Request.type_attr_dir =
6553 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6554 cmd->Request.Timeout = 0; /* Don't time out */
6555 cmd->Request.CDB[0] = opcode;
6556 cmd->Request.CDB[1] = type;
6557 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6558 cmd->ErrorDescriptor.Addr =
2b08b3e9 6559 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6560 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6561
2b08b3e9 6562 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6563
6564 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6565 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6566 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6567 break;
6568 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6569 }
6570
6571 iounmap(vaddr);
6572
6573 /* we leak the DMA buffer here ... no choice since the controller could
6574 * still complete the command.
6575 */
6576 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6577 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6578 opcode, type);
6579 return -ETIMEDOUT;
6580 }
6581
6582 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6583
6584 if (tag & HPSA_ERROR_BIT) {
6585 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6586 opcode, type);
6587 return -EIO;
6588 }
6589
6590 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6591 opcode, type);
6592 return 0;
6593}
6594
edd16368
SC		 6595#define hpsa_noop(p) hpsa_message(p, 3, 0)
6596
1df8552a 6597static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6598 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6599{
1df8552a
SC		 6600
6601 if (use_doorbell) {
6602 /* For everything after the P600, the PCI power state method
6603 * of resetting the controller doesn't work, so we have this
6604 * other way using the doorbell register.
6605 */
6606 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6607 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6608
00701a96 6609 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6610 * doorbell reset and before any attempt to talk to the board
6611 * at all to ensure that this actually works and doesn't fall
6612 * over in some weird corner cases.
6613 */
00701a96 6614 msleep(10000);
1df8552a
SC		 6615 } else { /* Try to do it the PCI power state way */
6616
6617 /* Quoting from the Open CISS Specification: "The Power
6618 * Management Control/Status Register (CSR) controls the power
6619 * state of the device. The normal operating state is D0,
6620 * CSR=00h. The software off state is D3, CSR=03h. To reset
6621 * the controller, place the interface device in D3 then to D0,
6622 * this causes a secondary PCI reset which will reset the
6623 * controller." */
2662cab8
DB		 6624
6625 int rc = 0;
6626
1df8552a 6627 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6628
1df8552a 6629 /* enter the D3hot power management state */
2662cab8
DB		 6630 rc = pci_set_power_state(pdev, PCI_D3hot);
6631 if (rc)
6632 return rc;
1df8552a
SC		 6633
6634 msleep(500);
6635
6636 /* enter the D0 power management state */
2662cab8
DB		 6637 rc = pci_set_power_state(pdev, PCI_D0);
6638 if (rc)
6639 return rc;
c4853efe
MM		 6640
6641 /*
6642 * The P600 requires a small delay when changing states.
6643 * Otherwise we may think the board did not reset and we bail.
6644 * This for kdump only and is particular to the P600.
6645 */
6646 msleep(500);
1df8552a
SC		 6647 }
6648 return 0;
6649}
6650
6f039790 6651static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6652{
6653 memset(driver_version, 0, len);
f79cfec6 6654 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6655}
6656
6f039790 6657static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6658{
6659 char *driver_version;
6660 int i, size = sizeof(cfgtable->driver_version);
6661
6662 driver_version = kmalloc(size, GFP_KERNEL);
6663 if (!driver_version)
6664 return -ENOMEM;
6665
6666 init_driver_version(driver_version, size);
6667 for (i = 0; i < size; i++)
6668 writeb(driver_version[i], &cfgtable->driver_version[i]);
6669 kfree(driver_version);
6670 return 0;
6671}
6672
6f039790
GKH		 6673static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6674 unsigned char *driver_ver)
580ada3c
SC		 6675{
6676 int i;
6677
6678 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6679 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6680}
6681
6f039790 6682static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6683{
6684
6685 char *driver_ver, *old_driver_ver;
6686 int rc, size = sizeof(cfgtable->driver_version);
6687
6688 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6689 if (!old_driver_ver)
6690 return -ENOMEM;
6691 driver_ver = old_driver_ver + size;
6692
6693 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6694 * should have been changed, otherwise we know the reset failed.
6695 */
6696 init_driver_version(old_driver_ver, size);
6697 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6698 rc = !memcmp(driver_ver, old_driver_ver, size);
6699 kfree(old_driver_ver);
6700 return rc;
6701}
edd16368 6702/* This does a hard reset of the controller using PCI power management
1df8552a 6703 * states or the using the doorbell register.
edd16368 6704 */
6b6c1cd7 6705static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6706{
1df8552a
SC		 6707 u64 cfg_offset;
6708 u32 cfg_base_addr;
6709 u64 cfg_base_addr_index;
6710 void __iomem *vaddr;
6711 unsigned long paddr;
580ada3c 6712 u32 misc_fw_support;
270d05de 6713 int rc;
1df8552a 6714 struct CfgTable __iomem *cfgtable;
cf0b08d0 6715 u32 use_doorbell;
270d05de 6716 u16 command_register;
edd16368 6717
1df8552a
SC		 6718 /* For controllers as old as the P600, this is very nearly
6719 * the same thing as
edd16368
SC		 6720 *
6721 * pci_save_state(pci_dev);
6722 * pci_set_power_state(pci_dev, PCI_D3hot);
6723 * pci_set_power_state(pci_dev, PCI_D0);
6724 * pci_restore_state(pci_dev);
6725 *
1df8552a
SC		 6726 * For controllers newer than the P600, the pci power state
6727 * method of resetting doesn't work so we have another way
6728 * using the doorbell register.
edd16368 6729 */
18867659 6730
60f923b9
RE		 6731 if (!ctlr_is_resettable(board_id)) {
6732 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6733 return -ENODEV;
6734 }
46380786
SC		 6735
6736 /* if controller is soft- but not hard resettable... */
6737 if (!ctlr_is_hard_resettable(board_id))
6738 return -ENOTSUPP; /* try soft reset later. */
18867659 6739
270d05de
SC		 6740 /* Save the PCI command register */
6741 pci_read_config_word(pdev, 4, &command_register);
270d05de 6742 pci_save_state(pdev);
edd16368 6743
1df8552a
SC		 6744 /* find the first memory BAR, so we can find the cfg table */
6745 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6746 if (rc)
6747 return rc;
6748 vaddr = remap_pci_mem(paddr, 0x250);
6749 if (!vaddr)
6750 return -ENOMEM;
edd16368 6751
1df8552a
SC		 6752 /* find cfgtable in order to check if reset via doorbell is supported */
6753 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6754 &cfg_base_addr_index, &cfg_offset);
6755 if (rc)
6756 goto unmap_vaddr;
6757 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6758 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6759 if (!cfgtable) {
6760 rc = -ENOMEM;
6761 goto unmap_vaddr;
6762 }
580ada3c
SC		 6763 rc = write_driver_ver_to_cfgtable(cfgtable);
6764 if (rc)
03741d95 6765 goto unmap_cfgtable;
edd16368 6766
cf0b08d0
SC		 6767 /* If reset via doorbell register is supported, use that.
6768 * There are two such methods. Favor the newest method.
6769 */
1df8552a 6770 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6771 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6772 if (use_doorbell) {
6773 use_doorbell = DOORBELL_CTLR_RESET2;
6774 } else {
6775 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6776 if (use_doorbell) {
050f7147
SC		 6777 dev_warn(&pdev->dev,
6778 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6779 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6780 goto unmap_cfgtable;
6781 }
6782 }
edd16368 6783
1df8552a
SC		 6784 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6785 if (rc)
6786 goto unmap_cfgtable;
edd16368 6787
270d05de 6788 pci_restore_state(pdev);
270d05de 6789 pci_write_config_word(pdev, 4, command_register);
edd16368 6790
1df8552a
SC		 6791 /* Some devices (notably the HP Smart Array 5i Controller)
6792 need a little pause here */
6793 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6794
fe5389c8
SC		 6795 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6796 if (rc) {
6797 dev_warn(&pdev->dev,
050f7147 6798 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6799 goto unmap_cfgtable;
6800 }
fe5389c8 6801
580ada3c
SC		 6802 rc = controller_reset_failed(vaddr);
6803 if (rc < 0)
6804 goto unmap_cfgtable;
6805 if (rc) {
64670ac8
SC		 6806 dev_warn(&pdev->dev, "Unable to successfully reset "
6807 "controller. Will try soft reset.\n");
6808 rc = -ENOTSUPP;
580ada3c 6809 } else {
64670ac8 6810 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6811 }
6812
6813unmap_cfgtable:
6814 iounmap(cfgtable);
6815
6816unmap_vaddr:
6817 iounmap(vaddr);
6818 return rc;
edd16368
SC		 6819}
6820
6821/*
6822 * We cannot read the structure directly, for portability we must use
6823 * the io functions.
6824 * This is for debug only.
6825 */
42a91641 6826static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6827{
58f8665c 6828#ifdef HPSA_DEBUG
edd16368
SC		 6829 int i;
6830 char temp_name[17];
6831
6832 dev_info(dev, "Controller Configuration information\n");
6833 dev_info(dev, "------------------------------------\n");
6834 for (i = 0; i < 4; i++)
6835 temp_name[i] = readb(&(tb->Signature[i]));
6836 temp_name[4] = '\0';
6837 dev_info(dev, " Signature = %s\n", temp_name);
6838 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6839 dev_info(dev, " Transport methods supported = 0x%x\n",
6840 readl(&(tb->TransportSupport)));
6841 dev_info(dev, " Transport methods active = 0x%x\n",
6842 readl(&(tb->TransportActive)));
6843 dev_info(dev, " Requested transport Method = 0x%x\n",
6844 readl(&(tb->HostWrite.TransportRequest)));
6845 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6846 readl(&(tb->HostWrite.CoalIntDelay)));
6847 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6848 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6849 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6850 readl(&(tb->CmdsOutMax)));
6851 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6852 for (i = 0; i < 16; i++)
6853 temp_name[i] = readb(&(tb->ServerName[i]));
6854 temp_name[16] = '\0';
6855 dev_info(dev, " Server Name = %s\n", temp_name);
6856 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6857 readl(&(tb->HeartBeat)));
edd16368 6858#endif /* HPSA_DEBUG */
58f8665c 6859}
edd16368
SC		 6860
6861static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6862{
6863 int i, offset, mem_type, bar_type;
6864
6865 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6866 return 0;
6867 offset = 0;
6868 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6869 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6870 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6871 offset += 4;
6872 else {
6873 mem_type = pci_resource_flags(pdev, i) &
6874 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6875 switch (mem_type) {
6876 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6877 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6878 offset += 4; /* 32 bit */
6879 break;
6880 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6881 offset += 8;
6882 break;
6883 default: /* reserved in PCI 2.2 */
6884 dev_warn(&pdev->dev,
6885 "base address is invalid\n");
6886 return -1;
6887 break;
6888 }
6889 }
6890 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6891 return i + 1;
6892 }
6893 return -1;
6894}
6895
cc64c817
RE		 6896static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6897{
6898 if (h->msix_vector) {
6899 if (h->pdev->msix_enabled)
6900 pci_disable_msix(h->pdev);
105a3dbc 6901 h->msix_vector = 0;
cc64c817
RE		 6902 } else if (h->msi_vector) {
6903 if (h->pdev->msi_enabled)
6904 pci_disable_msi(h->pdev);
105a3dbc 6905 h->msi_vector = 0;
cc64c817
RE		 6906 }
6907}
6908
edd16368 6909/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6910 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6911 */
6f039790 6912static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6913{
6914#ifdef CONFIG_PCI_MSI
254f796b
MG		 6915 int err, i;
6916 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6917
6918 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6919 hpsa_msix_entries[i].vector = 0;
6920 hpsa_msix_entries[i].entry = i;
6921 }
edd16368
SC		 6922
6923 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6924 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6925 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6926 goto default_int_mode;
55c06c71 6927 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6928 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6929 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6930 if (h->msix_vector > num_online_cpus())
6931 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6932 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6933 1, h->msix_vector);
6934 if (err < 0) {
6935 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6936 h->msix_vector = 0;
6937 goto single_msi_mode;
6938 } else if (err < h->msix_vector) {
55c06c71 6939 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6940 "available\n", err);
edd16368 6941 }
18fce3c4
AG		 6942 h->msix_vector = err;
6943 for (i = 0; i < h->msix_vector; i++)
6944 h->intr[i] = hpsa_msix_entries[i].vector;
6945 return;
edd16368 6946 }
18fce3c4 6947single_msi_mode:
55c06c71 6948 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6949 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6950 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6951 h->msi_vector = 1;
6952 else
55c06c71 6953 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6954 }
6955default_int_mode:
6956#endif /* CONFIG_PCI_MSI */
6957 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6958 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6959}
6960
6f039790 6961static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6962{
6963 int i;
6964 u32 subsystem_vendor_id, subsystem_device_id;
6965
6966 subsystem_vendor_id = pdev->subsystem_vendor;
6967 subsystem_device_id = pdev->subsystem_device;
6968 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6969 subsystem_vendor_id;
6970
6971 for (i = 0; i < ARRAY_SIZE(products); i++)
6972 if (*board_id == products[i].board_id)
6973 return i;
6974
6798cc0a
SC		 6975 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6976 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6977 !hpsa_allow_any) {
e5c880d1
SC		 6978 dev_warn(&pdev->dev, "unrecognized board ID: "
6979 "0x%08x, ignoring.\n", *board_id);
6980 return -ENODEV;
6981 }
6982 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6983}
6984
6f039790
GKH		 6985static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6986 unsigned long *memory_bar)
3a7774ce
SC		 6987{
6988 int i;
6989
6990 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6991 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6992 /* addressing mode bits already removed */
12d2cd47
SC		 6993 *memory_bar = pci_resource_start(pdev, i);
6994 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6995 *memory_bar);
6996 return 0;
6997 }
12d2cd47 6998 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6999 return -ENODEV;
7000}
7001
6f039790
GKH		 7002static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7003 int wait_for_ready)
2c4c8c8b 7004{
fe5389c8 7005 int i, iterations;
2c4c8c8b 7006 u32 scratchpad;
fe5389c8
SC		 7007 if (wait_for_ready)
7008 iterations = HPSA_BOARD_READY_ITERATIONS;
7009 else
7010 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7011
fe5389c8
SC		 7012 for (i = 0; i < iterations; i++) {
7013 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7014 if (wait_for_ready) {
7015 if (scratchpad == HPSA_FIRMWARE_READY)
7016 return 0;
7017 } else {
7018 if (scratchpad != HPSA_FIRMWARE_READY)
7019 return 0;
7020 }
2c4c8c8b
SC		 7021 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7022 }
fe5389c8 7023 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7024 return -ENODEV;
7025}
7026
6f039790
GKH		 7027static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7028 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7029 u64 *cfg_offset)
a51fd47f
SC		 7030{
7031 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7032 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7033 *cfg_base_addr &= (u32) 0x0000ffff;
7034 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7035 if (*cfg_base_addr_index == -1) {
7036 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7037 return -ENODEV;
7038 }
7039 return 0;
7040}
7041
195f2c65
RE		 7042static void hpsa_free_cfgtables(struct ctlr_info *h)
7043{
105a3dbc 7044 if (h->transtable) {
195f2c65 7045 iounmap(h->transtable);
105a3dbc
RE		 7046 h->transtable = NULL;
7047 }
7048 if (h->cfgtable) {
195f2c65 7049 iounmap(h->cfgtable);
105a3dbc
RE		 7050 h->cfgtable = NULL;
7051 }
195f2c65
RE		 7052}
7053
7054/* Find and map CISS config table and transfer table
7055+ * several items must be unmapped (freed) later
7056+ * */
6f039790 7057static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7058{
01a02ffc
SC		 7059 u64 cfg_offset;
7060 u32 cfg_base_addr;
7061 u64 cfg_base_addr_index;
303932fd 7062 u32 trans_offset;
a51fd47f 7063 int rc;
77c4495c 7064
a51fd47f
SC		 7065 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7066 &cfg_base_addr_index, &cfg_offset);
7067 if (rc)
7068 return rc;
77c4495c 7069 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7070 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7071 if (!h->cfgtable) {
7072 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7073 return -ENOMEM;
cd3c81c4 7074 }
580ada3c
SC		 7075 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7076 if (rc)
7077 return rc;
77c4495c 7078 /* Find performant mode table. */
a51fd47f 7079 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7080 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7081 cfg_base_addr_index)+cfg_offset+trans_offset,
7082 sizeof(*h->transtable));
195f2c65
RE		 7083 if (!h->transtable) {
7084 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7085 hpsa_free_cfgtables(h);
77c4495c 7086 return -ENOMEM;
195f2c65 7087 }
77c4495c
SC		 7088 return 0;
7089}
7090
6f039790 7091static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7092{
41ce4c35
SC		 7093#define MIN_MAX_COMMANDS 16
7094 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7095
7096 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7097
7098 /* Limit commands in memory limited kdump scenario. */
7099 if (reset_devices && h->max_commands > 32)
7100 h->max_commands = 32;
7101
41ce4c35
SC		 7102 if (h->max_commands < MIN_MAX_COMMANDS) {
7103 dev_warn(&h->pdev->dev,
7104 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7105 h->max_commands,
7106 MIN_MAX_COMMANDS);
7107 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7108 }
7109}
7110
c7ee65b3
WS		 7111/* If the controller reports that the total max sg entries is greater than 512,
7112 * then we know that chained SG blocks work. (Original smart arrays did not
7113 * support chained SG blocks and would return zero for max sg entries.)
7114 */
7115static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7116{
7117 return h->maxsgentries > 512;
7118}
7119
b93d7536
SC		 7120/* Interrogate the hardware for some limits:
7121 * max commands, max SG elements without chaining, and with chaining,
7122 * SG chain block size, etc.
7123 */
6f039790 7124static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7125{
cba3d38b 7126 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7127 h->nr_cmds = h->max_commands;
b93d7536 7128 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7129 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7130 if (hpsa_supports_chained_sg_blocks(h)) {
7131 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7132 h->max_cmd_sg_entries = 32;
1a63ea6f 7133 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7134 h->maxsgentries--; /* save one for chain pointer */
7135 } else {
c7ee65b3
WS		 7136 /*
7137 * Original smart arrays supported at most 31 s/g entries
7138 * embedded inline in the command (trying to use more
7139 * would lock up the controller)
7140 */
7141 h->max_cmd_sg_entries = 31;
1a63ea6f 7142 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7143 h->chainsize = 0;
b93d7536 7144 }
75167d2c
SC		 7145
7146 /* Find out what task management functions are supported and cache */
7147 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7148 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7149 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7150 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7151 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7152 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7153 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7154}
7155
76c46e49
SC		 7156static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7157{
0fc9fd40 7158 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7159 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7160 return false;
7161 }
7162 return true;
7163}
7164
97a5e98c 7165static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7166{
97a5e98c 7167 u32 driver_support;
f7c39101 7168
97a5e98c 7169 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7170 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7171#ifdef CONFIG_X86
97a5e98c 7172 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7173#endif
28e13446
SC		 7174 driver_support |= ENABLE_UNIT_ATTN;
7175 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7176}
7177
3d0eab67
SC		 7178/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7179 * in a prefetch beyond physical memory.
7180 */
7181static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7182{
7183 u32 dma_prefetch;
7184
7185 if (h->board_id != 0x3225103C)
7186 return;
7187 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7188 dma_prefetch |= 0x8000;
7189 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7190}
7191
c706a795 7192static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7193{
7194 int i;
7195 u32 doorbell_value;
7196 unsigned long flags;
7197 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7198 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7199 spin_lock_irqsave(&h->lock, flags);
7200 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7201 spin_unlock_irqrestore(&h->lock, flags);
7202 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7203 goto done;
76438d08 7204 /* delay and try again */
007e7aa9 7205 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7206 }
c706a795
RE		 7207 return -ENODEV;
7208done:
7209 return 0;
76438d08
SC		 7210}
7211
c706a795 7212static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7213{
7214 int i;
6eaf46fd
SC		 7215 u32 doorbell_value;
7216 unsigned long flags;
eb6b2ae9
SC		 7217
7218 /* under certain very rare conditions, this can take awhile.
7219 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7220 * as we enter this code.)
7221 */
007e7aa9 7222 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7223 if (h->remove_in_progress)
7224 goto done;
6eaf46fd
SC		 7225 spin_lock_irqsave(&h->lock, flags);
7226 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7227 spin_unlock_irqrestore(&h->lock, flags);
382be668 7228 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7229 goto done;
eb6b2ae9 7230 /* delay and try again */
007e7aa9 7231 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7232 }
c706a795
RE		 7233 return -ENODEV;
7234done:
7235 return 0;
3f4336f3
SC		 7236}
7237
c706a795 7238/* return -ENODEV or other reason on error, 0 on success */
6f039790 7239static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7240{
7241 u32 trans_support;
7242
7243 trans_support = readl(&(h->cfgtable->TransportSupport));
7244 if (!(trans_support & SIMPLE_MODE))
7245 return -ENOTSUPP;
7246
7247 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7248
3f4336f3
SC		 7249 /* Update the field, and then ring the doorbell */
7250 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7251 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7252 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7253 if (hpsa_wait_for_mode_change_ack(h))
7254 goto error;
eb6b2ae9 7255 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7256 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7257 goto error;
960a30e7 7258 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7259 return 0;
283b4a9b 7260error:
050f7147 7261 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7262 return -ENODEV;
eb6b2ae9
SC		 7263}
7264
195f2c65
RE		 7265/* free items allocated or mapped by hpsa_pci_init */
7266static void hpsa_free_pci_init(struct ctlr_info *h)
7267{
7268 hpsa_free_cfgtables(h); /* pci_init 4 */
7269 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7270 h->vaddr = NULL;
195f2c65 7271 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7272 /*
7273 * call pci_disable_device before pci_release_regions per
7274 * Documentation/PCI/pci.txt
7275 */
195f2c65 7276 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7277 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7278}
7279
7280/* several items must be freed later */
6f039790 7281static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7282{
eb6b2ae9 7283 int prod_index, err;
edd16368 7284
e5c880d1
SC		 7285 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7286 if (prod_index < 0)
60f923b9 7287 return prod_index;
e5c880d1
SC		 7288 h->product_name = products[prod_index].product_name;
7289 h->access = *(products[prod_index].access);
edd16368 7290
9b5c48c2
SC		 7291 h->needs_abort_tags_swizzled =
7292 ctlr_needs_abort_tags_swizzled(h->board_id);
7293
e5a44df8
MG		 7294 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7295 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7296
55c06c71 7297 err = pci_enable_device(h->pdev);
edd16368 7298 if (err) {
195f2c65 7299 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7300 pci_disable_device(h->pdev);
edd16368
SC		 7301 return err;
7302 }
7303
f79cfec6 7304 err = pci_request_regions(h->pdev, HPSA);
edd16368 7305 if (err) {
55c06c71 7306 dev_err(&h->pdev->dev,
195f2c65 7307 "failed to obtain PCI resources\n");
943a7021
RE		 7308 pci_disable_device(h->pdev);
7309 return err;
edd16368 7310 }
4fa604e1
RE		 7311
7312 pci_set_master(h->pdev);
7313
6b3f4c52 7314 hpsa_interrupt_mode(h);
12d2cd47 7315 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7316 if (err)
195f2c65 7317 goto clean2; /* intmode+region, pci */
edd16368 7318 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7319 if (!h->vaddr) {
195f2c65 7320 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7321 err = -ENOMEM;
195f2c65 7322 goto clean2; /* intmode+region, pci */
204892e9 7323 }
fe5389c8 7324 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7325 if (err)
195f2c65 7326 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7327 err = hpsa_find_cfgtables(h);
7328 if (err)
195f2c65 7329 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7330 hpsa_find_board_params(h);
edd16368 7331
76c46e49 7332 if (!hpsa_CISS_signature_present(h)) {
edd16368 7333 err = -ENODEV;
195f2c65 7334 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7335 }
97a5e98c 7336 hpsa_set_driver_support_bits(h);
3d0eab67 7337 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7338 err = hpsa_enter_simple_mode(h);
7339 if (err)
195f2c65 7340 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7341 return 0;
7342
195f2c65
RE		 7343clean4: /* cfgtables, vaddr, intmode+region, pci */
7344 hpsa_free_cfgtables(h);
7345clean3: /* vaddr, intmode+region, pci */
7346 iounmap(h->vaddr);
105a3dbc 7347 h->vaddr = NULL;
195f2c65
RE		 7348clean2: /* intmode+region, pci */
7349 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7350 /*
7351 * call pci_disable_device before pci_release_regions per
7352 * Documentation/PCI/pci.txt
7353 */
195f2c65 7354 pci_disable_device(h->pdev);
943a7021 7355 pci_release_regions(h->pdev);
edd16368
SC		 7356 return err;
7357}
7358
6f039790 7359static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7360{
7361 int rc;
7362
7363#define HBA_INQUIRY_BYTE_COUNT 64
7364 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7365 if (!h->hba_inquiry_data)
7366 return;
7367 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7368 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7369 if (rc != 0) {
7370 kfree(h->hba_inquiry_data);
7371 h->hba_inquiry_data = NULL;
7372 }
7373}
7374
6b6c1cd7 7375static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7376{
1df8552a 7377 int rc, i;
3b747298 7378 void __iomem *vaddr;
4c2a8c40
SC		 7379
7380 if (!reset_devices)
7381 return 0;
7382
132aa220
TH		 7383 /* kdump kernel is loading, we don't know in which state is
7384 * the pci interface. The dev->enable_cnt is equal zero
7385 * so we call enable+disable, wait a while and switch it on.
7386 */
7387 rc = pci_enable_device(pdev);
7388 if (rc) {
7389 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7390 return -ENODEV;
7391 }
7392 pci_disable_device(pdev);
7393 msleep(260); /* a randomly chosen number */
7394 rc = pci_enable_device(pdev);
7395 if (rc) {
7396 dev_warn(&pdev->dev, "failed to enable device.\n");
7397 return -ENODEV;
7398 }
4fa604e1 7399
859c75ab 7400 pci_set_master(pdev);
4fa604e1 7401
3b747298
TH		 7402 vaddr = pci_ioremap_bar(pdev, 0);
7403 if (vaddr == NULL) {
7404 rc = -ENOMEM;
7405 goto out_disable;
7406 }
7407 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7408 iounmap(vaddr);
7409
1df8552a 7410 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7411 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7412
1df8552a
SC		 7413 /* -ENOTSUPP here means we cannot reset the controller
7414 * but it's already (and still) up and running in
18867659
SC		 7415 * "performant mode". Or, it might be 640x, which can't reset
7416 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7417 */
adf1b3a3 7418 if (rc)
132aa220 7419 goto out_disable;
4c2a8c40
SC		 7420
7421 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7422 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7423 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7424 if (hpsa_noop(pdev) == 0)
7425 break;
7426 else
7427 dev_warn(&pdev->dev, "no-op failed%s\n",
7428 (i < 11 ? "; re-trying" : ""));
7429 }
132aa220
TH		 7430
7431out_disable:
7432
7433 pci_disable_device(pdev);
7434 return rc;
4c2a8c40
SC		 7435}
7436
1fb7c98a
RE		 7437static void hpsa_free_cmd_pool(struct ctlr_info *h)
7438{
7439 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7440 h->cmd_pool_bits = NULL;
7441 if (h->cmd_pool) {
1fb7c98a
RE		 7442 pci_free_consistent(h->pdev,
7443 h->nr_cmds * sizeof(struct CommandList),
7444 h->cmd_pool,
7445 h->cmd_pool_dhandle);
105a3dbc
RE		 7446 h->cmd_pool = NULL;
7447 h->cmd_pool_dhandle = 0;
7448 }
7449 if (h->errinfo_pool) {
1fb7c98a
RE		 7450 pci_free_consistent(h->pdev,
7451 h->nr_cmds * sizeof(struct ErrorInfo),
7452 h->errinfo_pool,
7453 h->errinfo_pool_dhandle);
105a3dbc
RE		 7454 h->errinfo_pool = NULL;
7455 h->errinfo_pool_dhandle = 0;
7456 }
1fb7c98a
RE		 7457}
7458
d37ffbe4 7459static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7460{
7461 h->cmd_pool_bits = kzalloc(
7462 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7463 sizeof(unsigned long), GFP_KERNEL);
7464 h->cmd_pool = pci_alloc_consistent(h->pdev,
7465 h->nr_cmds * sizeof(*h->cmd_pool),
7466 &(h->cmd_pool_dhandle));
7467 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7468 h->nr_cmds * sizeof(*h->errinfo_pool),
7469 &(h->errinfo_pool_dhandle));
7470 if ((h->cmd_pool_bits == NULL)
7471 || (h->cmd_pool == NULL)
7472 || (h->errinfo_pool == NULL)) {
7473 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7474 goto clean_up;
2e9d1b36 7475 }
360c73bd 7476 hpsa_preinitialize_commands(h);
2e9d1b36 7477 return 0;
2c143342
RE		 7478clean_up:
7479 hpsa_free_cmd_pool(h);
7480 return -ENOMEM;
2e9d1b36
SC		 7481}
7482
41b3cf08
SC		 7483static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7484{
ec429952 7485 int i, cpu;
41b3cf08
SC		 7486
7487 cpu = cpumask_first(cpu_online_mask);
7488 for (i = 0; i < h->msix_vector; i++) {
ec429952 7489 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7490 cpu = cpumask_next(cpu, cpu_online_mask);
7491 }
7492}
7493
ec501a18
RE		 7494/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7495static void hpsa_free_irqs(struct ctlr_info *h)
7496{
7497 int i;
7498
7499 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7500 /* Single reply queue, only one irq to free */
7501 i = h->intr_mode;
7502 irq_set_affinity_hint(h->intr[i], NULL);
7503 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7504 h->q[i] = 0;
ec501a18
RE		 7505 return;
7506 }
7507
7508 for (i = 0; i < h->msix_vector; i++) {
7509 irq_set_affinity_hint(h->intr[i], NULL);
7510 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7511 h->q[i] = 0;
ec501a18 7512 }
a4e17fc1
RE		 7513 for (; i < MAX_REPLY_QUEUES; i++)
7514 h->q[i] = 0;
ec501a18
RE		 7515}
7516
9ee61794
RE		 7517/* returns 0 on success; cleans up and returns -Enn on error */
7518static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7519 irqreturn_t (*msixhandler)(int, void *),
7520 irqreturn_t (*intxhandler)(int, void *))
7521{
254f796b 7522 int rc, i;
0ae01a32 7523
254f796b
MG		 7524 /*
7525 * initialize h->q[x] = x so that interrupt handlers know which
7526 * queue to process.
7527 */
7528 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7529 h->q[i] = (u8) i;
7530
eee0f03a 7531 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7532 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7533 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7534 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7535 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7536 0, h->intrname[i],
254f796b 7537 &h->q[i]);
a4e17fc1
RE		 7538 if (rc) {
7539 int j;
7540
7541 dev_err(&h->pdev->dev,
7542 "failed to get irq %d for %s\n",
7543 h->intr[i], h->devname);
7544 for (j = 0; j < i; j++) {
7545 free_irq(h->intr[j], &h->q[j]);
7546 h->q[j] = 0;
7547 }
7548 for (; j < MAX_REPLY_QUEUES; j++)
7549 h->q[j] = 0;
7550 return rc;
7551 }
7552 }
41b3cf08 7553 hpsa_irq_affinity_hints(h);
254f796b
MG		 7554 } else {
7555 /* Use single reply pool */
eee0f03a 7556 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7557 if (h->msix_vector)
7558 sprintf(h->intrname[h->intr_mode],
7559 "%s-msix", h->devname);
7560 else
7561 sprintf(h->intrname[h->intr_mode],
7562 "%s-msi", h->devname);
254f796b 7563 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7564 msixhandler, 0,
7565 h->intrname[h->intr_mode],
254f796b
MG		 7566 &h->q[h->intr_mode]);
7567 } else {
8b47004a
RE		 7568 sprintf(h->intrname[h->intr_mode],
7569 "%s-intx", h->devname);
254f796b 7570 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7571 intxhandler, IRQF_SHARED,
7572 h->intrname[h->intr_mode],
254f796b
MG		 7573 &h->q[h->intr_mode]);
7574 }
105a3dbc 7575 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7576 }
0ae01a32 7577 if (rc) {
195f2c65 7578 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7579 h->intr[h->intr_mode], h->devname);
195f2c65 7580 hpsa_free_irqs(h);
0ae01a32
SC		 7581 return -ENODEV;
7582 }
7583 return 0;
7584}
7585
6f039790 7586static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7587{
39c53f55 7588 int rc;
bf43caf3 7589 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7590
7591 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7592 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7593 if (rc) {
64670ac8 7594 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7595 return rc;
64670ac8
SC		 7596 }
7597
7598 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7599 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7600 if (rc) {
64670ac8
SC		 7601 dev_warn(&h->pdev->dev, "Board failed to become ready "
7602 "after soft reset.\n");
39c53f55 7603 return rc;
64670ac8
SC		 7604 }
7605
7606 return 0;
7607}
7608
072b0518
SC		 7609static void hpsa_free_reply_queues(struct ctlr_info *h)
7610{
7611 int i;
7612
7613 for (i = 0; i < h->nreply_queues; i++) {
7614 if (!h->reply_queue[i].head)
7615 continue;
1fb7c98a
RE		 7616 pci_free_consistent(h->pdev,
7617 h->reply_queue_size,
7618 h->reply_queue[i].head,
7619 h->reply_queue[i].busaddr);
072b0518
SC		 7620 h->reply_queue[i].head = NULL;
7621 h->reply_queue[i].busaddr = 0;
7622 }
105a3dbc 7623 h->reply_queue_size = 0;
072b0518
SC		 7624}
7625
0097f0f4
SC		 7626static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7627{
105a3dbc
RE		 7628 hpsa_free_performant_mode(h); /* init_one 7 */
7629 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7630 hpsa_free_cmd_pool(h); /* init_one 5 */
7631 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7632 scsi_host_put(h->scsi_host); /* init_one 3 */
7633 h->scsi_host = NULL; /* init_one 3 */
7634 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7635 free_percpu(h->lockup_detected); /* init_one 2 */
7636 h->lockup_detected = NULL; /* init_one 2 */
7637 if (h->resubmit_wq) {
7638 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7639 h->resubmit_wq = NULL;
7640 }
7641 if (h->rescan_ctlr_wq) {
7642 destroy_workqueue(h->rescan_ctlr_wq);
7643 h->rescan_ctlr_wq = NULL;
7644 }
105a3dbc 7645 kfree(h); /* init_one 1 */
64670ac8
SC		 7646}
7647
a0c12413 7648/* Called when controller lockup detected. */
f2405db8 7649static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7650{
281a7fd0
WS		 7651 int i, refcount;
7652 struct CommandList *c;
25163bd5 7653 int failcount = 0;
a0c12413 7654
080ef1cc 7655 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7656 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7657 c = h->cmd_pool + i;
281a7fd0
WS		 7658 refcount = atomic_inc_return(&c->refcount);
7659 if (refcount > 1) {
25163bd5 7660 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7661 finish_cmd(c);
433b5f4d 7662 atomic_dec(&h->commands_outstanding);
25163bd5 7663 failcount++;
281a7fd0
WS		 7664 }
7665 cmd_free(h, c);
a0c12413 7666 }
25163bd5
WS		 7667 dev_warn(&h->pdev->dev,
7668 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7669}
7670
094963da
SC		 7671static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7672{
c8ed0010 7673 int cpu;
094963da 7674
c8ed0010 7675 for_each_online_cpu(cpu) {
094963da
SC		 7676 u32 *lockup_detected;
7677 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7678 *lockup_detected = value;
094963da
SC		 7679 }
7680 wmb(); /* be sure the per-cpu variables are out to memory */
7681}
7682
a0c12413
SC		 7683static void controller_lockup_detected(struct ctlr_info *h)
7684{
7685 unsigned long flags;
094963da 7686 u32 lockup_detected;
a0c12413 7687
a0c12413
SC		 7688 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7689 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7690 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7691 if (!lockup_detected) {
7692 /* no heartbeat, but controller gave us a zero. */
7693 dev_warn(&h->pdev->dev,
25163bd5
WS		 7694 "lockup detected after %d but scratchpad register is zero\n",
7695 h->heartbeat_sample_interval / HZ);
094963da
SC		 7696 lockup_detected = 0xffffffff;
7697 }
7698 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7699 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7700 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7701 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7702 pci_disable_device(h->pdev);
f2405db8 7703 fail_all_outstanding_cmds(h);
a0c12413
SC		 7704}
7705
25163bd5 7706static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7707{
7708 u64 now;
7709 u32 heartbeat;
7710 unsigned long flags;
7711
a0c12413
SC		 7712 now = get_jiffies_64();
7713 /* If we've received an interrupt recently, we're ok. */
7714 if (time_after64(h->last_intr_timestamp +
e85c5974 7715 (h->heartbeat_sample_interval), now))
25163bd5 7716 return false;
a0c12413
SC		 7717
7718 /*
7719 * If we've already checked the heartbeat recently, we're ok.
7720 * This could happen if someone sends us a signal. We
7721 * otherwise don't care about signals in this thread.
7722 */
7723 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7724 (h->heartbeat_sample_interval), now))
25163bd5 7725 return false;
a0c12413
SC		 7726
7727 /* If heartbeat has not changed since we last looked, we're not ok. */
7728 spin_lock_irqsave(&h->lock, flags);
7729 heartbeat = readl(&h->cfgtable->HeartBeat);
7730 spin_unlock_irqrestore(&h->lock, flags);
7731 if (h->last_heartbeat == heartbeat) {
7732 controller_lockup_detected(h);
25163bd5 7733 return true;
a0c12413
SC		 7734 }
7735
7736 /* We're ok. */
7737 h->last_heartbeat = heartbeat;
7738 h->last_heartbeat_timestamp = now;
25163bd5 7739 return false;
a0c12413
SC		 7740}
7741
9846590e 7742static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7743{
7744 int i;
7745 char *event_type;
7746
e4aa3e6a
SC		 7747 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7748 return;
7749
76438d08 7750 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7751 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7752 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7753 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7754 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7755
7756 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7757 event_type = "state change";
7758 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7759 event_type = "configuration change";
7760 /* Stop sending new RAID offload reqs via the IO accelerator */
7761 scsi_block_requests(h->scsi_host);
7762 for (i = 0; i < h->ndevices; i++)
7763 h->dev[i]->offload_enabled = 0;
23100dd9 7764 hpsa_drain_accel_commands(h);
76438d08
SC		 7765 /* Set 'accelerator path config change' bit */
7766 dev_warn(&h->pdev->dev,
7767 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7768 h->events, event_type);
7769 writel(h->events, &(h->cfgtable->clear_event_notify));
7770 /* Set the "clear event notify field update" bit 6 */
7771 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7772 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7773 hpsa_wait_for_clear_event_notify_ack(h);
7774 scsi_unblock_requests(h->scsi_host);
7775 } else {
7776 /* Acknowledge controller notification events. */
7777 writel(h->events, &(h->cfgtable->clear_event_notify));
7778 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7779 hpsa_wait_for_clear_event_notify_ack(h);
7780#if 0
7781 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7782 hpsa_wait_for_mode_change_ack(h);
7783#endif
7784 }
9846590e 7785 return;
76438d08
SC		 7786}
7787
7788/* Check a register on the controller to see if there are configuration
7789 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7790 * we should rescan the controller for devices.
7791 * Also check flag for driver-initiated rescan.
76438d08 7792 */
9846590e 7793static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7794{
7795 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7796 return 0;
76438d08
SC		 7797
7798 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7799 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7800}
76438d08 7801
9846590e
SC		 7802/*
7803 * Check if any of the offline devices have become ready
7804 */
7805static int hpsa_offline_devices_ready(struct ctlr_info *h)
7806{
7807 unsigned long flags;
7808 struct offline_device_entry *d;
7809 struct list_head *this, *tmp;
7810
7811 spin_lock_irqsave(&h->offline_device_lock, flags);
7812 list_for_each_safe(this, tmp, &h->offline_device_list) {
7813 d = list_entry(this, struct offline_device_entry,
7814 offline_list);
7815 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7816 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7817 spin_lock_irqsave(&h->offline_device_lock, flags);
7818 list_del(&d->offline_list);
7819 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7820 return 1;
d1fea47c 7821 }
9846590e
SC		 7822 spin_lock_irqsave(&h->offline_device_lock, flags);
7823 }
7824 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7825 return 0;
76438d08
SC		 7826}
7827
6636e7f4 7828static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7829{
7830 unsigned long flags;
8a98db73 7831 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7832 struct ctlr_info, rescan_ctlr_work);
7833
7834
7835 if (h->remove_in_progress)
8a98db73 7836 return;
9846590e
SC		 7837
7838 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7839 scsi_host_get(h->scsi_host);
9846590e
SC		 7840 hpsa_ack_ctlr_events(h);
7841 hpsa_scan_start(h->scsi_host);
7842 scsi_host_put(h->scsi_host);
7843 }
8a98db73 7844 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7845 if (!h->remove_in_progress)
7846 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7847 h->heartbeat_sample_interval);
7848 spin_unlock_irqrestore(&h->lock, flags);
7849}
7850
7851static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7852{
7853 unsigned long flags;
7854 struct ctlr_info *h = container_of(to_delayed_work(work),
7855 struct ctlr_info, monitor_ctlr_work);
7856
7857 detect_controller_lockup(h);
7858 if (lockup_detected(h))
a0c12413 7859 return;
6636e7f4
DB		 7860
7861 spin_lock_irqsave(&h->lock, flags);
7862 if (!h->remove_in_progress)
7863 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7864 h->heartbeat_sample_interval);
7865 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7866}
7867
6636e7f4
DB		 7868static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7869 char *name)
7870{
7871 struct workqueue_struct *wq = NULL;
6636e7f4 7872
397ea9cb 7873 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7874 if (!wq)
7875 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7876
7877 return wq;
7878}
7879
6f039790 7880static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7881{
4c2a8c40 7882 int dac, rc;
edd16368 7883 struct ctlr_info *h;
64670ac8
SC		 7884 int try_soft_reset = 0;
7885 unsigned long flags;
6b6c1cd7 7886 u32 board_id;
edd16368
SC		 7887
7888 if (number_of_controllers == 0)
7889 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7890
6b6c1cd7
TH		 7891 rc = hpsa_lookup_board_id(pdev, &board_id);
7892 if (rc < 0) {
7893 dev_warn(&pdev->dev, "Board ID not found\n");
7894 return rc;
7895 }
7896
7897 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7898 if (rc) {
7899 if (rc != -ENOTSUPP)
7900 return rc;
7901 /* If the reset fails in a particular way (it has no way to do
7902 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7903 * a soft reset once we get the controller configured up to the
7904 * point that it can accept a command.
7905 */
7906 try_soft_reset = 1;
7907 rc = 0;
7908 }
7909
7910reinit_after_soft_reset:
edd16368 7911
303932fd
DB		 7912 /* Command structures must be aligned on a 32-byte boundary because
7913 * the 5 lower bits of the address are used by the hardware. and by
7914 * the driver. See comments in hpsa.h for more info.
7915 */
303932fd 7916 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 7917 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 7918 if (!h) {
7919 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 7920 return -ENOMEM;
105a3dbc 7921 }
edd16368 7922
55c06c71 7923 h->pdev = pdev;
105a3dbc 7924
a9a3a273 7925 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7926 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7927 spin_lock_init(&h->lock);
9846590e 7928 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7929 spin_lock_init(&h->scan_lock);
34f0c627 7930 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7931 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 7932
7933 /* Allocate and clear per-cpu variable lockup_detected */
7934 h->lockup_detected = alloc_percpu(u32);
2a5ac326 7935 if (!h->lockup_detected) {
105a3dbc 7936 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 7937 rc = -ENOMEM;
2efa5929 7938 goto clean1; /* aer/h */
2a5ac326 7939 }
094963da
SC		 7940 set_lockup_detected_for_all_cpus(h, 0);
7941
55c06c71 7942 rc = hpsa_pci_init(h);
105a3dbc 7943 if (rc)
2946e82b
RE		 7944 goto clean2; /* lu, aer/h */
7945
7946 /* relies on h-> settings made by hpsa_pci_init, including
7947 * interrupt_mode h->intr */
7948 rc = hpsa_scsi_host_alloc(h);
7949 if (rc)
7950 goto clean2_5; /* pci, lu, aer/h */
edd16368 7951
2946e82b 7952 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 7953 h->ctlr = number_of_controllers;
7954 number_of_controllers++;
edd16368
SC		 7955
7956 /* configure PCI DMA stuff */
ecd9aad4
SC		 7957 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7958 if (rc == 0) {
edd16368 7959 dac = 1;
ecd9aad4
SC		 7960 } else {
7961 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7962 if (rc == 0) {
7963 dac = 0;
7964 } else {
7965 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 7966 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 7967 }
edd16368
SC		 7968 }
7969
7970 /* make sure the board interrupts are off */
7971 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7972
105a3dbc
RE		 7973 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
7974 if (rc)
2946e82b 7975 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 7976 rc = hpsa_alloc_cmd_pool(h);
8947fd10 7977 if (rc)
2946e82b 7978 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 7979 rc = hpsa_alloc_sg_chain_blocks(h);
7980 if (rc)
2946e82b 7981 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 7982 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7983 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 7984 init_waitqueue_head(&h->event_sync_wait_queue);
7985 mutex_init(&h->reset_mutex);
a08a8471 7986 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7987
7988 pci_set_drvdata(pdev, h);
9a41338e 7989 h->ndevices = 0;
316b221a 7990 h->hba_mode_enabled = 0;
2946e82b 7991
9a41338e 7992 spin_lock_init(&h->devlock);
105a3dbc
RE		 7993 rc = hpsa_put_ctlr_into_performant_mode(h);
7994 if (rc)
2946e82b
RE		 7995 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
7996
7997 /* hook into SCSI subsystem */
7998 rc = hpsa_scsi_add_host(h);
7999 if (rc)
8000 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8001
8002 /* create the resubmit workqueue */
8003 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8004 if (!h->rescan_ctlr_wq) {
8005 rc = -ENOMEM;
8006 goto clean7;
8007 }
8008
8009 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8010 if (!h->resubmit_wq) {
8011 rc = -ENOMEM;
8012 goto clean7; /* aer/h */
8013 }
64670ac8 8014
105a3dbc
RE		 8015 /*
8016 * At this point, the controller is ready to take commands.
64670ac8
SC		 8017 * Now, if reset_devices and the hard reset didn't work, try
8018 * the soft reset and see if that works.
8019 */
8020 if (try_soft_reset) {
8021
8022 /* This is kind of gross. We may or may not get a completion
8023 * from the soft reset command, and if we do, then the value
8024 * from the fifo may or may not be valid. So, we wait 10 secs
8025 * after the reset throwing away any completions we get during
8026 * that time. Unregister the interrupt handler and register
8027 * fake ones to scoop up any residual completions.
8028 */
8029 spin_lock_irqsave(&h->lock, flags);
8030 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8031 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8032 hpsa_free_irqs(h);
9ee61794 8033 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8034 hpsa_intx_discard_completions);
8035 if (rc) {
9ee61794
RE		 8036 dev_warn(&h->pdev->dev,
8037 "Failed to request_irq after soft reset.\n");
d498757c 8038 /*
b2ef480c
RE		 8039 * cannot goto clean7 or free_irqs will be called
8040 * again. Instead, do its work
8041 */
8042 hpsa_free_performant_mode(h); /* clean7 */
8043 hpsa_free_sg_chain_blocks(h); /* clean6 */
8044 hpsa_free_cmd_pool(h); /* clean5 */
8045 /*
8046 * skip hpsa_free_irqs(h) clean4 since that
8047 * was just called before request_irqs failed
d498757c
RE		 8048 */
8049 goto clean3;
64670ac8
SC		 8050 }
8051
8052 rc = hpsa_kdump_soft_reset(h);
8053 if (rc)
8054 /* Neither hard nor soft reset worked, we're hosed. */
2946e82b 8055 goto clean9;
64670ac8
SC		 8056
8057 dev_info(&h->pdev->dev, "Board READY.\n");
8058 dev_info(&h->pdev->dev,
8059 "Waiting for stale completions to drain.\n");
8060 h->access.set_intr_mask(h, HPSA_INTR_ON);
8061 msleep(10000);
8062 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8063
8064 rc = controller_reset_failed(h->cfgtable);
8065 if (rc)
8066 dev_info(&h->pdev->dev,
8067 "Soft reset appears to have failed.\n");
8068
8069 /* since the controller's reset, we have to go back and re-init
8070 * everything. Easiest to just forget what we've done and do it
8071 * all over again.
8072 */
8073 hpsa_undo_allocations_after_kdump_soft_reset(h);
8074 try_soft_reset = 0;
8075 if (rc)
b2ef480c 8076 /* don't goto clean, we already unallocated */
64670ac8
SC		 8077 return -ENODEV;
8078
8079 goto reinit_after_soft_reset;
8080 }
edd16368 8081
105a3dbc
RE		 8082 /* Enable Accelerated IO path at driver layer */
8083 h->acciopath_status = 1;
da0697bd 8084
e863d68e 8085
edd16368
SC		 8086 /* Turn the interrupts on so we can service requests */
8087 h->access.set_intr_mask(h, HPSA_INTR_ON);
8088
339b2b14 8089 hpsa_hba_inquiry(h);
8a98db73
SC		 8090
8091 /* Monitor the controller for firmware lockups */
8092 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8093 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8094 schedule_delayed_work(&h->monitor_ctlr_work,
8095 h->heartbeat_sample_interval);
6636e7f4
DB		 8096 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8097 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8098 h->heartbeat_sample_interval);
88bf6d62 8099 return 0;
edd16368 8100
2946e82b 8101clean9: /* wq, sh, perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc 8102 kfree(h->hba_inquiry_data);
2946e82b 8103clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8104 hpsa_free_performant_mode(h);
8105 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8106clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8107 hpsa_free_sg_chain_blocks(h);
2946e82b 8108clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8109 hpsa_free_cmd_pool(h);
2946e82b 8110clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8111 hpsa_free_irqs(h);
2946e82b
RE		 8112clean3: /* shost, pci, lu, aer/h */
8113 scsi_host_put(h->scsi_host);
8114 h->scsi_host = NULL;
8115clean2_5: /* pci, lu, aer/h */
195f2c65 8116 hpsa_free_pci_init(h);
2946e82b 8117clean2: /* lu, aer/h */
105a3dbc
RE		 8118 if (h->lockup_detected) {
8119 free_percpu(h->lockup_detected);
8120 h->lockup_detected = NULL;
8121 }
8122clean1: /* wq/aer/h */
8123 if (h->resubmit_wq) {
080ef1cc 8124 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8125 h->resubmit_wq = NULL;
8126 }
8127 if (h->rescan_ctlr_wq) {
6636e7f4 8128 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8129 h->rescan_ctlr_wq = NULL;
8130 }
edd16368 8131 kfree(h);
ecd9aad4 8132 return rc;
edd16368
SC		 8133}
8134
8135static void hpsa_flush_cache(struct ctlr_info *h)
8136{
8137 char *flush_buf;
8138 struct CommandList *c;
25163bd5 8139 int rc;
702890e3 8140
094963da 8141 if (unlikely(lockup_detected(h)))
702890e3 8142 return;
edd16368
SC		 8143 flush_buf = kzalloc(4, GFP_KERNEL);
8144 if (!flush_buf)
8145 return;
8146
45fcb86e 8147 c = cmd_alloc(h);
bf43caf3 8148
a2dac136
SC		 8149 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8150 RAID_CTLR_LUNID, TYPE_CMD)) {
8151 goto out;
8152 }
25163bd5
WS		 8153 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8154 PCI_DMA_TODEVICE, NO_TIMEOUT);
8155 if (rc)
8156 goto out;
edd16368 8157 if (c->err_info->CommandStatus != 0)
a2dac136 8158out:
edd16368
SC		 8159 dev_warn(&h->pdev->dev,
8160 "error flushing cache on controller\n");
45fcb86e 8161 cmd_free(h, c);
edd16368
SC		 8162 kfree(flush_buf);
8163}
8164
8165static void hpsa_shutdown(struct pci_dev *pdev)
8166{
8167 struct ctlr_info *h;
8168
8169 h = pci_get_drvdata(pdev);
8170 /* Turn board interrupts off and send the flush cache command
8171 * sendcmd will turn off interrupt, and send the flush...
8172 * To write all data in the battery backed cache to disks
8173 */
8174 hpsa_flush_cache(h);
8175 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8176 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8177 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8178}
8179
6f039790 8180static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8181{
8182 int i;
8183
105a3dbc 8184 for (i = 0; i < h->ndevices; i++) {
55e14e76 8185 kfree(h->dev[i]);
105a3dbc
RE		 8186 h->dev[i] = NULL;
8187 }
55e14e76
SC		 8188}
8189
6f039790 8190static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8191{
8192 struct ctlr_info *h;
8a98db73 8193 unsigned long flags;
edd16368
SC		 8194
8195 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8196 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8197 return;
8198 }
8199 h = pci_get_drvdata(pdev);
8a98db73
SC		 8200
8201 /* Get rid of any controller monitoring work items */
8202 spin_lock_irqsave(&h->lock, flags);
8203 h->remove_in_progress = 1;
8a98db73 8204 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8205 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8206 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8207 destroy_workqueue(h->rescan_ctlr_wq);
8208 destroy_workqueue(h->resubmit_wq);
cc64c817 8209
105a3dbc 8210 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8211 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8212 hpsa_shutdown(pdev);
cc64c817 8213
105a3dbc
RE		 8214 hpsa_free_device_info(h); /* scan */
8215
2946e82b
RE		 8216 kfree(h->hba_inquiry_data); /* init_one 10 */
8217 h->hba_inquiry_data = NULL; /* init_one 10 */
8218 if (h->scsi_host)
8219 scsi_remove_host(h->scsi_host); /* init_one 8 */
8220 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8221 hpsa_free_performant_mode(h); /* init_one 7 */
8222 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8223 hpsa_free_cmd_pool(h); /* init_one 5 */
8224
8225 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8226
2946e82b
RE		 8227 scsi_host_put(h->scsi_host); /* init_one 3 */
8228 h->scsi_host = NULL; /* init_one 3 */
8229
195f2c65 8230 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8231 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8232
105a3dbc
RE		 8233 free_percpu(h->lockup_detected); /* init_one 2 */
8234 h->lockup_detected = NULL; /* init_one 2 */
8235 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8236 kfree(h); /* init_one 1 */
edd16368
SC		 8237}
8238
8239static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8240 __attribute__((unused)) pm_message_t state)
8241{
8242 return -ENOSYS;
8243}
8244
8245static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8246{
8247 return -ENOSYS;
8248}
8249
8250static struct pci_driver hpsa_pci_driver = {
f79cfec6 8251 .name = HPSA,
edd16368 8252 .probe = hpsa_init_one,
6f039790 8253 .remove = hpsa_remove_one,
edd16368
SC		 8254 .id_table = hpsa_pci_device_id, /* id_table */
8255 .shutdown = hpsa_shutdown,
8256 .suspend = hpsa_suspend,
8257 .resume = hpsa_resume,
8258};
8259
303932fd
DB		 8260/* Fill in bucket_map[], given nsgs (the max number of
8261 * scatter gather elements supported) and bucket[],
8262 * which is an array of 8 integers. The bucket[] array
8263 * contains 8 different DMA transfer sizes (in 16
8264 * byte increments) which the controller uses to fetch
8265 * commands. This function fills in bucket_map[], which
8266 * maps a given number of scatter gather elements to one of
8267 * the 8 DMA transfer sizes. The point of it is to allow the
8268 * controller to only do as much DMA as needed to fetch the
8269 * command, with the DMA transfer size encoded in the lower
8270 * bits of the command address.
8271 */
8272static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8273 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8274{
8275 int i, j, b, size;
8276
303932fd
DB		 8277 /* Note, bucket_map must have nsgs+1 entries. */
8278 for (i = 0; i <= nsgs; i++) {
8279 /* Compute size of a command with i SG entries */
e1f7de0c 8280 size = i + min_blocks;
303932fd
DB		 8281 b = num_buckets; /* Assume the biggest bucket */
8282 /* Find the bucket that is just big enough */
e1f7de0c 8283 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8284 if (bucket[j] >= size) {
8285 b = j;
8286 break;
8287 }
8288 }
8289 /* for a command with i SG entries, use bucket b. */
8290 bucket_map[i] = b;
8291 }
8292}
8293
105a3dbc
RE		 8294/*
8295 * return -ENODEV on err, 0 on success (or no action)
8296 * allocates numerous items that must be freed later
8297 */
c706a795 8298static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8299{
6c311b57
SC		 8300 int i;
8301 unsigned long register_value;
e1f7de0c
MG		 8302 unsigned long transMethod = CFGTBL_Trans_Performant |
8303 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8304 CFGTBL_Trans_enable_directed_msix |
8305 (trans_support & (CFGTBL_Trans_io_accel1 |
8306 CFGTBL_Trans_io_accel2));
e1f7de0c 8307 struct access_method access = SA5_performant_access;
def342bd
SC		 8308
8309 /* This is a bit complicated. There are 8 registers on
8310 * the controller which we write to to tell it 8 different
8311 * sizes of commands which there may be. It's a way of
8312 * reducing the DMA done to fetch each command. Encoded into
8313 * each command's tag are 3 bits which communicate to the controller
8314 * which of the eight sizes that command fits within. The size of
8315 * each command depends on how many scatter gather entries there are.
8316 * Each SG entry requires 16 bytes. The eight registers are programmed
8317 * with the number of 16-byte blocks a command of that size requires.
8318 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8319 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8320 * blocks. Note, this only extends to the SG entries contained
8321 * within the command block, and does not extend to chained blocks
8322 * of SG elements. bft[] contains the eight values we write to
8323 * the registers. They are not evenly distributed, but have more
8324 * sizes for small commands, and fewer sizes for larger commands.
8325 */
d66ae08b 8326 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8327#define MIN_IOACCEL2_BFT_ENTRY 5
8328#define HPSA_IOACCEL2_HEADER_SZ 4
8329 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8330 13, 14, 15, 16, 17, 18, 19,
8331 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8332 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8333 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8334 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8335 16 * MIN_IOACCEL2_BFT_ENTRY);
8336 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8337 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8338 /* 5 = 1 s/g entry or 4k
8339 * 6 = 2 s/g entry or 8k
8340 * 8 = 4 s/g entry or 16k
8341 * 10 = 6 s/g entry or 24k
8342 */
303932fd 8343
b3a52e79
SC		 8344 /* If the controller supports either ioaccel method then
8345 * we can also use the RAID stack submit path that does not
8346 * perform the superfluous readl() after each command submission.
8347 */
8348 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8349 access = SA5_performant_access_no_read;
8350
303932fd 8351 /* Controller spec: zero out this buffer. */
072b0518
SC		 8352 for (i = 0; i < h->nreply_queues; i++)
8353 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8354
d66ae08b
SC		 8355 bft[7] = SG_ENTRIES_IN_CMD + 4;
8356 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8357 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8358 for (i = 0; i < 8; i++)
8359 writel(bft[i], &h->transtable->BlockFetch[i]);
8360
8361 /* size of controller ring buffer */
8362 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8363 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8364 writel(0, &h->transtable->RepQCtrAddrLow32);
8365 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8366
8367 for (i = 0; i < h->nreply_queues; i++) {
8368 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8369 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8370 &h->transtable->RepQAddr[i].lower);
8371 }
8372
b9af4937 8373 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8374 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8375 /*
8376 * enable outbound interrupt coalescing in accelerator mode;
8377 */
8378 if (trans_support & CFGTBL_Trans_io_accel1) {
8379 access = SA5_ioaccel_mode1_access;
8380 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8381 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8382 } else {
8383 if (trans_support & CFGTBL_Trans_io_accel2) {
8384 access = SA5_ioaccel_mode2_access;
8385 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8386 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8387 }
e1f7de0c 8388 }
303932fd 8389 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8390 if (hpsa_wait_for_mode_change_ack(h)) {
8391 dev_err(&h->pdev->dev,
8392 "performant mode problem - doorbell timeout\n");
8393 return -ENODEV;
8394 }
303932fd
DB		 8395 register_value = readl(&(h->cfgtable->TransportActive));
8396 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8397 dev_err(&h->pdev->dev,
8398 "performant mode problem - transport not active\n");
c706a795 8399 return -ENODEV;
303932fd 8400 }
960a30e7 8401 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8402 h->access = access;
8403 h->transMethod = transMethod;
8404
b9af4937
SC		 8405 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8406 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8407 return 0;
e1f7de0c 8408
b9af4937
SC		 8409 if (trans_support & CFGTBL_Trans_io_accel1) {
8410 /* Set up I/O accelerator mode */
8411 for (i = 0; i < h->nreply_queues; i++) {
8412 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8413 h->reply_queue[i].current_entry =
8414 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8415 }
8416 bft[7] = h->ioaccel_maxsg + 8;
8417 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8418 h->ioaccel1_blockFetchTable);
e1f7de0c 8419
b9af4937 8420 /* initialize all reply queue entries to unused */
072b0518
SC		 8421 for (i = 0; i < h->nreply_queues; i++)
8422 memset(h->reply_queue[i].head,
8423 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8424 h->reply_queue_size);
e1f7de0c 8425
b9af4937
SC		 8426 /* set all the constant fields in the accelerator command
8427 * frames once at init time to save CPU cycles later.
8428 */
8429 for (i = 0; i < h->nr_cmds; i++) {
8430 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8431
8432 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8433 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8434 (i * sizeof(struct ErrorInfo)));
8435 cp->err_info_len = sizeof(struct ErrorInfo);
8436 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8437 cp->host_context_flags =
8438 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8439 cp->timeout_sec = 0;
8440 cp->ReplyQueue = 0;
50a0decf 8441 cp->tag =
f2405db8 8442 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8443 cp->host_addr =
8444 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8445 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8446 }
8447 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8448 u64 cfg_offset, cfg_base_addr_index;
8449 u32 bft2_offset, cfg_base_addr;
8450 int rc;
8451
8452 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8453 &cfg_base_addr_index, &cfg_offset);
8454 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8455 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8456 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8457 4, h->ioaccel2_blockFetchTable);
8458 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8459 BUILD_BUG_ON(offsetof(struct CfgTable,
8460 io_accel_request_size_offset) != 0xb8);
8461 h->ioaccel2_bft2_regs =
8462 remap_pci_mem(pci_resource_start(h->pdev,
8463 cfg_base_addr_index) +
8464 cfg_offset + bft2_offset,
8465 ARRAY_SIZE(bft2) *
8466 sizeof(*h->ioaccel2_bft2_regs));
8467 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8468 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8469 }
b9af4937 8470 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8471 if (hpsa_wait_for_mode_change_ack(h)) {
8472 dev_err(&h->pdev->dev,
8473 "performant mode problem - enabling ioaccel mode\n");
8474 return -ENODEV;
8475 }
8476 return 0;
e1f7de0c
MG		 8477}
8478
1fb7c98a
RE		 8479/* Free ioaccel1 mode command blocks and block fetch table */
8480static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8481{
105a3dbc 8482 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8483 pci_free_consistent(h->pdev,
8484 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8485 h->ioaccel_cmd_pool,
8486 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8487 h->ioaccel_cmd_pool = NULL;
8488 h->ioaccel_cmd_pool_dhandle = 0;
8489 }
1fb7c98a 8490 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8491 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8492}
8493
d37ffbe4
RE		 8494/* Allocate ioaccel1 mode command blocks and block fetch table */
8495static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8496{
283b4a9b
SC		 8497 h->ioaccel_maxsg =
8498 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8499 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8500 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8501
e1f7de0c
MG		 8502 /* Command structures must be aligned on a 128-byte boundary
8503 * because the 7 lower bits of the address are used by the
8504 * hardware.
8505 */
e1f7de0c
MG		 8506 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8507 IOACCEL1_COMMANDLIST_ALIGNMENT);
8508 h->ioaccel_cmd_pool =
8509 pci_alloc_consistent(h->pdev,
8510 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8511 &(h->ioaccel_cmd_pool_dhandle));
8512
8513 h->ioaccel1_blockFetchTable =
283b4a9b 8514 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8515 sizeof(u32)), GFP_KERNEL);
8516
8517 if ((h->ioaccel_cmd_pool == NULL) ||
8518 (h->ioaccel1_blockFetchTable == NULL))
8519 goto clean_up;
8520
8521 memset(h->ioaccel_cmd_pool, 0,
8522 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8523 return 0;
8524
8525clean_up:
1fb7c98a 8526 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8527 return -ENOMEM;
6c311b57
SC		 8528}
8529
1fb7c98a
RE		 8530/* Free ioaccel2 mode command blocks and block fetch table */
8531static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8532{
d9a729f3
WS		 8533 hpsa_free_ioaccel2_sg_chain_blocks(h);
8534
105a3dbc 8535 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8536 pci_free_consistent(h->pdev,
8537 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8538 h->ioaccel2_cmd_pool,
8539 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8540 h->ioaccel2_cmd_pool = NULL;
8541 h->ioaccel2_cmd_pool_dhandle = 0;
8542 }
1fb7c98a 8543 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8544 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8545}
8546
d37ffbe4
RE		 8547/* Allocate ioaccel2 mode command blocks and block fetch table */
8548static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8549{
d9a729f3
WS		 8550 int rc;
8551
aca9012a
SC		 8552 /* Allocate ioaccel2 mode command blocks and block fetch table */
8553
8554 h->ioaccel_maxsg =
8555 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8556 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8557 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8558
aca9012a
SC		 8559 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8560 IOACCEL2_COMMANDLIST_ALIGNMENT);
8561 h->ioaccel2_cmd_pool =
8562 pci_alloc_consistent(h->pdev,
8563 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8564 &(h->ioaccel2_cmd_pool_dhandle));
8565
8566 h->ioaccel2_blockFetchTable =
8567 kmalloc(((h->ioaccel_maxsg + 1) *
8568 sizeof(u32)), GFP_KERNEL);
8569
8570 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8571 (h->ioaccel2_blockFetchTable == NULL)) {
8572 rc = -ENOMEM;
8573 goto clean_up;
8574 }
8575
8576 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8577 if (rc)
aca9012a
SC		 8578 goto clean_up;
8579
8580 memset(h->ioaccel2_cmd_pool, 0,
8581 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8582 return 0;
8583
8584clean_up:
1fb7c98a 8585 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8586 return rc;
aca9012a
SC		 8587}
8588
105a3dbc
RE		 8589/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8590static void hpsa_free_performant_mode(struct ctlr_info *h)
8591{
8592 kfree(h->blockFetchTable);
8593 h->blockFetchTable = NULL;
8594 hpsa_free_reply_queues(h);
8595 hpsa_free_ioaccel1_cmd_and_bft(h);
8596 hpsa_free_ioaccel2_cmd_and_bft(h);
8597}
8598
8599/* return -ENODEV on error, 0 on success (or no action)
8600 * allocates numerous items that must be freed later
8601 */
8602static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8603{
8604 u32 trans_support;
e1f7de0c
MG		 8605 unsigned long transMethod = CFGTBL_Trans_Performant |
8606 CFGTBL_Trans_use_short_tags;
105a3dbc 8607 int i, rc;
6c311b57 8608
02ec19c8 8609 if (hpsa_simple_mode)
105a3dbc 8610 return 0;
02ec19c8 8611
67c99a72 8612 trans_support = readl(&(h->cfgtable->TransportSupport));
8613 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8614 return 0;
67c99a72 8615
e1f7de0c
MG		 8616 /* Check for I/O accelerator mode support */
8617 if (trans_support & CFGTBL_Trans_io_accel1) {
8618 transMethod |= CFGTBL_Trans_io_accel1 |
8619 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8620 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8621 if (rc)
8622 return rc;
8623 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8624 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8625 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8626 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8627 if (rc)
8628 return rc;
e1f7de0c
MG		 8629 }
8630
eee0f03a 8631 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8632 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8633 /* Performant mode ring buffer and supporting data structures */
072b0518 8634 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8635
254f796b 8636 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8637 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8638 h->reply_queue_size,
8639 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8640 if (!h->reply_queue[i].head) {
8641 rc = -ENOMEM;
8642 goto clean1; /* rq, ioaccel */
8643 }
254f796b
MG		 8644 h->reply_queue[i].size = h->max_commands;
8645 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8646 h->reply_queue[i].current_entry = 0;
8647 }
8648
6c311b57 8649 /* Need a block fetch table for performant mode */
d66ae08b 8650 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8651 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8652 if (!h->blockFetchTable) {
8653 rc = -ENOMEM;
8654 goto clean1; /* rq, ioaccel */
8655 }
6c311b57 8656
105a3dbc
RE		 8657 rc = hpsa_enter_performant_mode(h, trans_support);
8658 if (rc)
8659 goto clean2; /* bft, rq, ioaccel */
8660 return 0;
303932fd 8661
105a3dbc 8662clean2: /* bft, rq, ioaccel */
303932fd 8663 kfree(h->blockFetchTable);
105a3dbc
RE		 8664 h->blockFetchTable = NULL;
8665clean1: /* rq, ioaccel */
8666 hpsa_free_reply_queues(h);
8667 hpsa_free_ioaccel1_cmd_and_bft(h);
8668 hpsa_free_ioaccel2_cmd_and_bft(h);
8669 return rc;
303932fd
DB		 8670}
8671
23100dd9 8672static int is_accelerated_cmd(struct CommandList *c)
76438d08 8673{
23100dd9
SC		 8674 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8675}
8676
8677static void hpsa_drain_accel_commands(struct ctlr_info *h)
8678{
8679 struct CommandList *c = NULL;
f2405db8 8680 int i, accel_cmds_out;
281a7fd0 8681 int refcount;
76438d08 8682
f2405db8 8683 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8684 accel_cmds_out = 0;
f2405db8 8685 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8686 c = h->cmd_pool + i;
281a7fd0
WS		 8687 refcount = atomic_inc_return(&c->refcount);
8688 if (refcount > 1) /* Command is allocated */
8689 accel_cmds_out += is_accelerated_cmd(c);
8690 cmd_free(h, c);
f2405db8 8691 }
23100dd9 8692 if (accel_cmds_out <= 0)
281a7fd0 8693 break;
76438d08
SC		 8694 msleep(100);
8695 } while (1);
8696}
8697
edd16368
SC		 8698/*
8699 * This is it. Register the PCI driver information for the cards we control
8700 * the OS will call our registered routines when it finds one of our cards.
8701 */
8702static int __init hpsa_init(void)
8703{
31468401 8704 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8705}
8706
8707static void __exit hpsa_cleanup(void)
8708{
8709 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8710}
8711
e1f7de0c
MG		 8712static void __attribute__((unused)) verify_offsets(void)
8713{
dd0e19f3
ST		 8714#define VERIFY_OFFSET(member, offset) \
8715 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8716
8717 VERIFY_OFFSET(structure_size, 0);
8718 VERIFY_OFFSET(volume_blk_size, 4);
8719 VERIFY_OFFSET(volume_blk_cnt, 8);
8720 VERIFY_OFFSET(phys_blk_shift, 16);
8721 VERIFY_OFFSET(parity_rotation_shift, 17);
8722 VERIFY_OFFSET(strip_size, 18);
8723 VERIFY_OFFSET(disk_starting_blk, 20);
8724 VERIFY_OFFSET(disk_blk_cnt, 28);
8725 VERIFY_OFFSET(data_disks_per_row, 36);
8726 VERIFY_OFFSET(metadata_disks_per_row, 38);
8727 VERIFY_OFFSET(row_cnt, 40);
8728 VERIFY_OFFSET(layout_map_count, 42);
8729 VERIFY_OFFSET(flags, 44);
8730 VERIFY_OFFSET(dekindex, 46);
8731 /* VERIFY_OFFSET(reserved, 48 */
8732 VERIFY_OFFSET(data, 64);
8733
8734#undef VERIFY_OFFSET
8735
b66cc250
MM		 8736#define VERIFY_OFFSET(member, offset) \
8737 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8738
8739 VERIFY_OFFSET(IU_type, 0);
8740 VERIFY_OFFSET(direction, 1);
8741 VERIFY_OFFSET(reply_queue, 2);
8742 /* VERIFY_OFFSET(reserved1, 3); */
8743 VERIFY_OFFSET(scsi_nexus, 4);
8744 VERIFY_OFFSET(Tag, 8);
8745 VERIFY_OFFSET(cdb, 16);
8746 VERIFY_OFFSET(cciss_lun, 32);
8747 VERIFY_OFFSET(data_len, 40);
8748 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8749 VERIFY_OFFSET(sg_count, 45);
8750 /* VERIFY_OFFSET(reserved3 */
8751 VERIFY_OFFSET(err_ptr, 48);
8752 VERIFY_OFFSET(err_len, 56);
8753 /* VERIFY_OFFSET(reserved4 */
8754 VERIFY_OFFSET(sg, 64);
8755
8756#undef VERIFY_OFFSET
8757
e1f7de0c
MG		 8758#define VERIFY_OFFSET(member, offset) \
8759 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8760
8761 VERIFY_OFFSET(dev_handle, 0x00);
8762 VERIFY_OFFSET(reserved1, 0x02);
8763 VERIFY_OFFSET(function, 0x03);
8764 VERIFY_OFFSET(reserved2, 0x04);
8765 VERIFY_OFFSET(err_info, 0x0C);
8766 VERIFY_OFFSET(reserved3, 0x10);
8767 VERIFY_OFFSET(err_info_len, 0x12);
8768 VERIFY_OFFSET(reserved4, 0x13);
8769 VERIFY_OFFSET(sgl_offset, 0x14);
8770 VERIFY_OFFSET(reserved5, 0x15);
8771 VERIFY_OFFSET(transfer_len, 0x1C);
8772 VERIFY_OFFSET(reserved6, 0x20);
8773 VERIFY_OFFSET(io_flags, 0x24);
8774 VERIFY_OFFSET(reserved7, 0x26);
8775 VERIFY_OFFSET(LUN, 0x34);
8776 VERIFY_OFFSET(control, 0x3C);
8777 VERIFY_OFFSET(CDB, 0x40);
8778 VERIFY_OFFSET(reserved8, 0x50);
8779 VERIFY_OFFSET(host_context_flags, 0x60);
8780 VERIFY_OFFSET(timeout_sec, 0x62);
8781 VERIFY_OFFSET(ReplyQueue, 0x64);
8782 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8783 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8784 VERIFY_OFFSET(host_addr, 0x70);
8785 VERIFY_OFFSET(CISS_LUN, 0x78);
8786 VERIFY_OFFSET(SG, 0x78 + 8);
8787#undef VERIFY_OFFSET
8788}
8789
edd16368
SC		 8790module_init(hpsa_init);
8791module_exit(hpsa_cleanup);
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