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hpsa: add ioaccel sg chaining for the ioaccel2 path
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
9437ac43 46#include <scsi/scsi_eh.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
59/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
9a993302 60#define HPSA_DRIVER_VERSION "3.4.4-1"
edd16368 61#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 62#define HPSA "hpsa"
edd16368 63
007e7aa9
RE		 64/* How long to wait for CISS doorbell communication */
65#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
66#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
67#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
68#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 69#define MAX_IOCTL_CONFIG_WAIT 1000
70
71/*define how many times we will try a command because of bus resets */
72#define MAX_CMD_RETRIES 3
73
74/* Embedded module documentation macros - see modules.h */
75MODULE_AUTHOR("Hewlett-Packard Company");
76MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
77 HPSA_DRIVER_VERSION);
78MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
79MODULE_VERSION(HPSA_DRIVER_VERSION);
80MODULE_LICENSE("GPL");
81
82static int hpsa_allow_any;
83module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
84MODULE_PARM_DESC(hpsa_allow_any,
85 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 86static int hpsa_simple_mode;
87module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
88MODULE_PARM_DESC(hpsa_simple_mode,
89 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 90
91/* define the PCI info for the cards we can control */
92static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
8e616a5e
SC		 133 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
134 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
135 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
136 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
137 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 138 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 139 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 140 {0,}
141};
142
143MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
144
145/* board_id = Subsystem Device ID & Vendor ID
146 * product = Marketing Name for the board
147 * access = Address of the struct of function pointers
148 */
149static struct board_type products[] = {
edd16368
SC		 150 {0x3241103C, "Smart Array P212", &SA5_access},
151 {0x3243103C, "Smart Array P410", &SA5_access},
152 {0x3245103C, "Smart Array P410i", &SA5_access},
153 {0x3247103C, "Smart Array P411", &SA5_access},
154 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 155 {0x324A103C, "Smart Array P712m", &SA5_access},
156 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 157 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 158 {0x3350103C, "Smart Array P222", &SA5_access},
159 {0x3351103C, "Smart Array P420", &SA5_access},
160 {0x3352103C, "Smart Array P421", &SA5_access},
161 {0x3353103C, "Smart Array P822", &SA5_access},
162 {0x3354103C, "Smart Array P420i", &SA5_access},
163 {0x3355103C, "Smart Array P220i", &SA5_access},
164 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 165 {0x1921103C, "Smart Array P830i", &SA5_access},
166 {0x1922103C, "Smart Array P430", &SA5_access},
167 {0x1923103C, "Smart Array P431", &SA5_access},
168 {0x1924103C, "Smart Array P830", &SA5_access},
169 {0x1926103C, "Smart Array P731m", &SA5_access},
170 {0x1928103C, "Smart Array P230i", &SA5_access},
171 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 172 {0x21BD103C, "Smart Array P244br", &SA5_access},
173 {0x21BE103C, "Smart Array P741m", &SA5_access},
174 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
175 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 176 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 177 {0x21C2103C, "Smart Array P440", &SA5_access},
178 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 179 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 180 {0x21C5103C, "Smart Array P841", &SA5_access},
181 {0x21C6103C, "Smart HBA H244br", &SA5_access},
182 {0x21C7103C, "Smart HBA H240", &SA5_access},
183 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 184 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 185 {0x21CA103C, "Smart Array P246br", &SA5_access},
186 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 187 {0x21CC103C, "Smart Array", &SA5_access},
188 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 189 {0x21CE103C, "Smart HBA", &SA5_access},
8e616a5e
SC		 190 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
191 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
192 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
193 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
194 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 195 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
196};
197
198static int number_of_controllers;
199
10f66018
SC		 200static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
201static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 202static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 203
204#ifdef CONFIG_COMPAT
42a91641
DB		 205static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
206 void __user *arg);
edd16368
SC		 207#endif
208
209static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 210static struct CommandList *cmd_alloc(struct ctlr_info *h);
a2dac136 211static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 212 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 213 int cmd_type);
2c143342 214static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 215#define VPD_PAGE (1 << 8)
edd16368 216
f281233d 217static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 218static void hpsa_scan_start(struct Scsi_Host *);
219static int hpsa_scan_finished(struct Scsi_Host *sh,
220 unsigned long elapsed_time);
7c0a0229 221static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 222
223static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 224static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 225static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 226static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 227static void hpsa_slave_destroy(struct scsi_device *sdev);
228
edd16368 229static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 230static int check_for_unit_attention(struct ctlr_info *h,
231 struct CommandList *c);
232static void check_ioctl_unit_attention(struct ctlr_info *h,
233 struct CommandList *c);
303932fd
DB		 234/* performant mode helper functions */
235static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 236 int nsgs, int min_blocks, u32 *bucket_map);
6f039790 237static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
1fb7c98a
RE		 238static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h);
239static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h);
254f796b 240static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 241static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
242 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
243 u64 *cfg_offset);
244static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
245 unsigned long *memory_bar);
246static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
247static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
248 int wait_for_ready);
75167d2c 249static inline void finish_cmd(struct CommandList *c);
c706a795 250static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 251#define BOARD_NOT_READY 0
252#define BOARD_READY 1
23100dd9 253static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 254static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 255static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
256 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 257 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 258static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 259static u32 lockup_detected(struct ctlr_info *h);
260static int detect_controller_lockup(struct ctlr_info *h);
edd16368 261
edd16368
SC		 262static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
263{
264 unsigned long *priv = shost_priv(sdev->host);
265 return (struct ctlr_info *) *priv;
266}
267
a23513e8
SC		 268static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
269{
270 unsigned long *priv = shost_priv(sh);
271 return (struct ctlr_info *) *priv;
272}
273
9437ac43
SC		 274/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
275static void decode_sense_data(const u8 *sense_data, int sense_data_len,
276 u8 *sense_key, u8 *asc, u8 *ascq)
277{
278 struct scsi_sense_hdr sshdr;
279 bool rc;
280
281 *sense_key = -1;
282 *asc = -1;
283 *ascq = -1;
284
285 if (sense_data_len < 1)
286 return;
287
288 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
289 if (rc) {
290 *sense_key = sshdr.sense_key;
291 *asc = sshdr.asc;
292 *ascq = sshdr.ascq;
293 }
294}
295
edd16368
SC		 296static int check_for_unit_attention(struct ctlr_info *h,
297 struct CommandList *c)
298{
9437ac43
SC		 299 u8 sense_key, asc, ascq;
300 int sense_len;
301
302 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
303 sense_len = sizeof(c->err_info->SenseInfo);
304 else
305 sense_len = c->err_info->SenseLen;
306
307 decode_sense_data(c->err_info->SenseInfo, sense_len,
308 &sense_key, &asc, &ascq);
309 if (sense_key != UNIT_ATTENTION || asc == -1)
edd16368
SC		 310 return 0;
311
9437ac43 312 switch (asc) {
edd16368 313 case STATE_CHANGED:
9437ac43
SC		 314 dev_warn(&h->pdev->dev,
315 HPSA "%d: a state change detected, command retried\n",
316 h->ctlr);
edd16368
SC		 317 break;
318 case LUN_FAILED:
7f73695a
SC		 319 dev_warn(&h->pdev->dev,
320 HPSA "%d: LUN failure detected\n", h->ctlr);
edd16368
SC		 321 break;
322 case REPORT_LUNS_CHANGED:
7f73695a
SC		 323 dev_warn(&h->pdev->dev,
324 HPSA "%d: report LUN data changed\n", h->ctlr);
edd16368 325 /*
4f4eb9f1
ST		 326 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
327 * target (array) devices.
edd16368
SC		 328 */
329 break;
330 case POWER_OR_RESET:
f79cfec6 331 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 332 "or device reset detected\n", h->ctlr);
333 break;
334 case UNIT_ATTENTION_CLEARED:
f79cfec6 335 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 336 "cleared by another initiator\n", h->ctlr);
337 break;
338 default:
f79cfec6 339 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 340 "unit attention detected\n", h->ctlr);
341 break;
342 }
343 return 1;
344}
345
852af20a
MB		 346static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
347{
348 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
349 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
350 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
351 return 0;
352 dev_warn(&h->pdev->dev, HPSA "device busy");
353 return 1;
354}
355
e985c58f
SC		 356static u32 lockup_detected(struct ctlr_info *h);
357static ssize_t host_show_lockup_detected(struct device *dev,
358 struct device_attribute *attr, char *buf)
359{
360 int ld;
361 struct ctlr_info *h;
362 struct Scsi_Host *shost = class_to_shost(dev);
363
364 h = shost_to_hba(shost);
365 ld = lockup_detected(h);
366
367 return sprintf(buf, "ld=%d\n", ld);
368}
369
da0697bd
ST		 370static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
371 struct device_attribute *attr,
372 const char *buf, size_t count)
373{
374 int status, len;
375 struct ctlr_info *h;
376 struct Scsi_Host *shost = class_to_shost(dev);
377 char tmpbuf[10];
378
379 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
380 return -EACCES;
381 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
382 strncpy(tmpbuf, buf, len);
383 tmpbuf[len] = '\0';
384 if (sscanf(tmpbuf, "%d", &status) != 1)
385 return -EINVAL;
386 h = shost_to_hba(shost);
387 h->acciopath_status = !!status;
388 dev_warn(&h->pdev->dev,
389 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
390 h->acciopath_status ? "enabled" : "disabled");
391 return count;
392}
393
2ba8bfc8
SC		 394static ssize_t host_store_raid_offload_debug(struct device *dev,
395 struct device_attribute *attr,
396 const char *buf, size_t count)
397{
398 int debug_level, len;
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401 char tmpbuf[10];
402
403 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
404 return -EACCES;
405 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
406 strncpy(tmpbuf, buf, len);
407 tmpbuf[len] = '\0';
408 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
409 return -EINVAL;
410 if (debug_level < 0)
411 debug_level = 0;
412 h = shost_to_hba(shost);
413 h->raid_offload_debug = debug_level;
414 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
415 h->raid_offload_debug);
416 return count;
417}
418
edd16368
SC		 419static ssize_t host_store_rescan(struct device *dev,
420 struct device_attribute *attr,
421 const char *buf, size_t count)
422{
423 struct ctlr_info *h;
424 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 425 h = shost_to_hba(shost);
31468401 426 hpsa_scan_start(h->scsi_host);
edd16368
SC		 427 return count;
428}
429
d28ce020
SC		 430static ssize_t host_show_firmware_revision(struct device *dev,
431 struct device_attribute *attr, char *buf)
432{
433 struct ctlr_info *h;
434 struct Scsi_Host *shost = class_to_shost(dev);
435 unsigned char *fwrev;
436
437 h = shost_to_hba(shost);
438 if (!h->hba_inquiry_data)
439 return 0;
440 fwrev = &h->hba_inquiry_data[32];
441 return snprintf(buf, 20, "%c%c%c%c\n",
442 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
443}
444
94a13649
SC		 445static ssize_t host_show_commands_outstanding(struct device *dev,
446 struct device_attribute *attr, char *buf)
447{
448 struct Scsi_Host *shost = class_to_shost(dev);
449 struct ctlr_info *h = shost_to_hba(shost);
450
0cbf768e
SC		 451 return snprintf(buf, 20, "%d\n",
452 atomic_read(&h->commands_outstanding));
94a13649
SC		 453}
454
745a7a25
SC		 455static ssize_t host_show_transport_mode(struct device *dev,
456 struct device_attribute *attr, char *buf)
457{
458 struct ctlr_info *h;
459 struct Scsi_Host *shost = class_to_shost(dev);
460
461 h = shost_to_hba(shost);
462 return snprintf(buf, 20, "%s\n",
960a30e7 463 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 464 "performant" : "simple");
465}
466
da0697bd
ST		 467static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
468 struct device_attribute *attr, char *buf)
469{
470 struct ctlr_info *h;
471 struct Scsi_Host *shost = class_to_shost(dev);
472
473 h = shost_to_hba(shost);
474 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
475 (h->acciopath_status == 1) ? "enabled" : "disabled");
476}
477
46380786 478/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 479static u32 unresettable_controller[] = {
480 0x324a103C, /* Smart Array P712m */
9b5c48c2 481 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 482 0x3223103C, /* Smart Array P800 */
483 0x3234103C, /* Smart Array P400 */
484 0x3235103C, /* Smart Array P400i */
485 0x3211103C, /* Smart Array E200i */
486 0x3212103C, /* Smart Array E200 */
487 0x3213103C, /* Smart Array E200i */
488 0x3214103C, /* Smart Array E200i */
489 0x3215103C, /* Smart Array E200i */
490 0x3237103C, /* Smart Array E500 */
491 0x323D103C, /* Smart Array P700m */
7af0abbc 492 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 493 0x409C0E11, /* Smart Array 6400 */
494 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 495 0x40700E11, /* Smart Array 5300 */
496 0x40820E11, /* Smart Array 532 */
497 0x40830E11, /* Smart Array 5312 */
498 0x409A0E11, /* Smart Array 641 */
499 0x409B0E11, /* Smart Array 642 */
500 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 501};
502
46380786
SC		 503/* List of controllers which cannot even be soft reset */
504static u32 soft_unresettable_controller[] = {
7af0abbc 505 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 506 0x40700E11, /* Smart Array 5300 */
507 0x40820E11, /* Smart Array 532 */
508 0x40830E11, /* Smart Array 5312 */
509 0x409A0E11, /* Smart Array 641 */
510 0x409B0E11, /* Smart Array 642 */
511 0x40910E11, /* Smart Array 6i */
46380786
SC		 512 /* Exclude 640x boards. These are two pci devices in one slot
513 * which share a battery backed cache module. One controls the
514 * cache, the other accesses the cache through the one that controls
515 * it. If we reset the one controlling the cache, the other will
516 * likely not be happy. Just forbid resetting this conjoined mess.
517 * The 640x isn't really supported by hpsa anyway.
518 */
519 0x409C0E11, /* Smart Array 6400 */
520 0x409D0E11, /* Smart Array 6400 EM */
521};
522
9b5c48c2
SC		 523static u32 needs_abort_tags_swizzled[] = {
524 0x323D103C, /* Smart Array P700m */
525 0x324a103C, /* Smart Array P712m */
526 0x324b103C, /* SmartArray P711m */
527};
528
529static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 530{
531 int i;
532
9b5c48c2
SC		 533 for (i = 0; i < nelems; i++)
534 if (a[i] == board_id)
535 return 1;
536 return 0;
46380786
SC		 537}
538
9b5c48c2 539static int ctlr_is_hard_resettable(u32 board_id)
46380786 540{
9b5c48c2
SC		 541 return !board_id_in_array(unresettable_controller,
542 ARRAY_SIZE(unresettable_controller), board_id);
543}
46380786 544
9b5c48c2
SC		 545static int ctlr_is_soft_resettable(u32 board_id)
546{
547 return !board_id_in_array(soft_unresettable_controller,
548 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 549}
550
46380786
SC		 551static int ctlr_is_resettable(u32 board_id)
552{
553 return ctlr_is_hard_resettable(board_id) ||
554 ctlr_is_soft_resettable(board_id);
555}
556
9b5c48c2
SC		 557static int ctlr_needs_abort_tags_swizzled(u32 board_id)
558{
559 return board_id_in_array(needs_abort_tags_swizzled,
560 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
561}
562
941b1cda
SC		 563static ssize_t host_show_resettable(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct Scsi_Host *shost = class_to_shost(dev);
568
569 h = shost_to_hba(shost);
46380786 570 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 571}
572
edd16368
SC		 573static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
574{
575 return (scsi3addr[3] & 0xC0) == 0x40;
576}
577
f2ef0ce7
RE		 578static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
579 "1(+0)ADM", "UNKNOWN"
edd16368 580};
6b80b18f
ST		 581#define HPSA_RAID_0 0
582#define HPSA_RAID_4 1
583#define HPSA_RAID_1 2 /* also used for RAID 10 */
584#define HPSA_RAID_5 3 /* also used for RAID 50 */
585#define HPSA_RAID_51 4
586#define HPSA_RAID_6 5 /* also used for RAID 60 */
587#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 588#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
589
590static ssize_t raid_level_show(struct device *dev,
591 struct device_attribute *attr, char *buf)
592{
593 ssize_t l = 0;
82a72c0a 594 unsigned char rlevel;
edd16368
SC		 595 struct ctlr_info *h;
596 struct scsi_device *sdev;
597 struct hpsa_scsi_dev_t *hdev;
598 unsigned long flags;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608
609 /* Is this even a logical drive? */
610 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
611 spin_unlock_irqrestore(&h->lock, flags);
612 l = snprintf(buf, PAGE_SIZE, "N/A\n");
613 return l;
614 }
615
616 rlevel = hdev->raid_level;
617 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 618 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 619 rlevel = RAID_UNKNOWN;
620 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
621 return l;
622}
623
624static ssize_t lunid_show(struct device *dev,
625 struct device_attribute *attr, char *buf)
626{
627 struct ctlr_info *h;
628 struct scsi_device *sdev;
629 struct hpsa_scsi_dev_t *hdev;
630 unsigned long flags;
631 unsigned char lunid[8];
632
633 sdev = to_scsi_device(dev);
634 h = sdev_to_hba(sdev);
635 spin_lock_irqsave(&h->lock, flags);
636 hdev = sdev->hostdata;
637 if (!hdev) {
638 spin_unlock_irqrestore(&h->lock, flags);
639 return -ENODEV;
640 }
641 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
642 spin_unlock_irqrestore(&h->lock, flags);
643 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
644 lunid[0], lunid[1], lunid[2], lunid[3],
645 lunid[4], lunid[5], lunid[6], lunid[7]);
646}
647
648static ssize_t unique_id_show(struct device *dev,
649 struct device_attribute *attr, char *buf)
650{
651 struct ctlr_info *h;
652 struct scsi_device *sdev;
653 struct hpsa_scsi_dev_t *hdev;
654 unsigned long flags;
655 unsigned char sn[16];
656
657 sdev = to_scsi_device(dev);
658 h = sdev_to_hba(sdev);
659 spin_lock_irqsave(&h->lock, flags);
660 hdev = sdev->hostdata;
661 if (!hdev) {
662 spin_unlock_irqrestore(&h->lock, flags);
663 return -ENODEV;
664 }
665 memcpy(sn, hdev->device_id, sizeof(sn));
666 spin_unlock_irqrestore(&h->lock, flags);
667 return snprintf(buf, 16 * 2 + 2,
668 "%02X%02X%02X%02X%02X%02X%02X%02X"
669 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
670 sn[0], sn[1], sn[2], sn[3],
671 sn[4], sn[5], sn[6], sn[7],
672 sn[8], sn[9], sn[10], sn[11],
673 sn[12], sn[13], sn[14], sn[15]);
674}
675
c1988684
ST		 676static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
677 struct device_attribute *attr, char *buf)
678{
679 struct ctlr_info *h;
680 struct scsi_device *sdev;
681 struct hpsa_scsi_dev_t *hdev;
682 unsigned long flags;
683 int offload_enabled;
684
685 sdev = to_scsi_device(dev);
686 h = sdev_to_hba(sdev);
687 spin_lock_irqsave(&h->lock, flags);
688 hdev = sdev->hostdata;
689 if (!hdev) {
690 spin_unlock_irqrestore(&h->lock, flags);
691 return -ENODEV;
692 }
693 offload_enabled = hdev->offload_enabled;
694 spin_unlock_irqrestore(&h->lock, flags);
695 return snprintf(buf, 20, "%d\n", offload_enabled);
696}
697
3f5eac3a
SC		 698static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
699static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
700static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
701static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 702static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
703 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 704static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
705 host_show_hp_ssd_smart_path_status,
706 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 707static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
708 host_store_raid_offload_debug);
3f5eac3a
SC		 709static DEVICE_ATTR(firmware_revision, S_IRUGO,
710 host_show_firmware_revision, NULL);
711static DEVICE_ATTR(commands_outstanding, S_IRUGO,
712 host_show_commands_outstanding, NULL);
713static DEVICE_ATTR(transport_mode, S_IRUGO,
714 host_show_transport_mode, NULL);
941b1cda
SC		 715static DEVICE_ATTR(resettable, S_IRUGO,
716 host_show_resettable, NULL);
e985c58f
SC		 717static DEVICE_ATTR(lockup_detected, S_IRUGO,
718 host_show_lockup_detected, NULL);
3f5eac3a
SC		 719
720static struct device_attribute *hpsa_sdev_attrs[] = {
721 &dev_attr_raid_level,
722 &dev_attr_lunid,
723 &dev_attr_unique_id,
c1988684 724 &dev_attr_hp_ssd_smart_path_enabled,
e985c58f 725 &dev_attr_lockup_detected,
3f5eac3a
SC		 726 NULL,
727};
728
729static struct device_attribute *hpsa_shost_attrs[] = {
730 &dev_attr_rescan,
731 &dev_attr_firmware_revision,
732 &dev_attr_commands_outstanding,
733 &dev_attr_transport_mode,
941b1cda 734 &dev_attr_resettable,
da0697bd 735 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 736 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 737 NULL,
738};
739
41ce4c35
SC		 740#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
741 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
742
3f5eac3a
SC		 743static struct scsi_host_template hpsa_driver_template = {
744 .module = THIS_MODULE,
f79cfec6
SC		 745 .name = HPSA,
746 .proc_name = HPSA,
3f5eac3a
SC		 747 .queuecommand = hpsa_scsi_queue_command,
748 .scan_start = hpsa_scan_start,
749 .scan_finished = hpsa_scan_finished,
7c0a0229 750 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 751 .this_id = -1,
752 .use_clustering = ENABLE_CLUSTERING,
75167d2c 753 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 754 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
755 .ioctl = hpsa_ioctl,
756 .slave_alloc = hpsa_slave_alloc,
41ce4c35 757 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 758 .slave_destroy = hpsa_slave_destroy,
759#ifdef CONFIG_COMPAT
760 .compat_ioctl = hpsa_compat_ioctl,
761#endif
762 .sdev_attrs = hpsa_sdev_attrs,
763 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 764 .max_sectors = 8192,
54b2b50c 765 .no_write_same = 1,
3f5eac3a
SC		 766};
767
254f796b 768static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 769{
770 u32 a;
072b0518 771 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 772
e1f7de0c
MG		 773 if (h->transMethod & CFGTBL_Trans_io_accel1)
774 return h->access.command_completed(h, q);
775
3f5eac3a 776 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 777 return h->access.command_completed(h, q);
3f5eac3a 778
254f796b
MG		 779 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
780 a = rq->head[rq->current_entry];
781 rq->current_entry++;
0cbf768e 782 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 783 } else {
784 a = FIFO_EMPTY;
785 }
786 /* Check for wraparound */
254f796b
MG		 787 if (rq->current_entry == h->max_commands) {
788 rq->current_entry = 0;
789 rq->wraparound ^= 1;
3f5eac3a
SC		 790 }
791 return a;
792}
793
c349775e
ST		 794/*
795 * There are some special bits in the bus address of the
796 * command that we have to set for the controller to know
797 * how to process the command:
798 *
799 * Normal performant mode:
800 * bit 0: 1 means performant mode, 0 means simple mode.
801 * bits 1-3 = block fetch table entry
802 * bits 4-6 = command type (== 0)
803 *
804 * ioaccel1 mode:
805 * bit 0 = "performant mode" bit.
806 * bits 1-3 = block fetch table entry
807 * bits 4-6 = command type (== 110)
808 * (command type is needed because ioaccel1 mode
809 * commands are submitted through the same register as normal
810 * mode commands, so this is how the controller knows whether
811 * the command is normal mode or ioaccel1 mode.)
812 *
813 * ioaccel2 mode:
814 * bit 0 = "performant mode" bit.
815 * bits 1-4 = block fetch table entry (note extra bit)
816 * bits 4-6 = not needed, because ioaccel2 mode has
817 * a separate special register for submitting commands.
818 */
819
25163bd5
WS		 820/*
821 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 822 * set bit 0 for pull model, bits 3-1 for block fetch
823 * register number
824 */
25163bd5
WS		 825#define DEFAULT_REPLY_QUEUE (-1)
826static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
827 int reply_queue)
3f5eac3a 828{
254f796b 829 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 830 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 831 if (unlikely(!h->msix_vector))
832 return;
833 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 834 c->Header.ReplyQueue =
804a5cb5 835 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 836 else
837 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 838 }
3f5eac3a
SC		 839}
840
c349775e 841static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 842 struct CommandList *c,
843 int reply_queue)
c349775e
ST		 844{
845 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
846
25163bd5
WS		 847 /*
848 * Tell the controller to post the reply to the queue for this
c349775e
ST		 849 * processor. This seems to give the best I/O throughput.
850 */
25163bd5
WS		 851 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
852 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
853 else
854 cp->ReplyQueue = reply_queue % h->nreply_queues;
855 /*
856 * Set the bits in the address sent down to include:
c349775e
ST		 857 * - performant mode bit (bit 0)
858 * - pull count (bits 1-3)
859 * - command type (bits 4-6)
860 */
861 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
862 IOACCEL1_BUSADDR_CMDTYPE;
863}
864
865static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 866 struct CommandList *c,
867 int reply_queue)
c349775e
ST		 868{
869 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
870
25163bd5
WS		 871 /*
872 * Tell the controller to post the reply to the queue for this
c349775e
ST		 873 * processor. This seems to give the best I/O throughput.
874 */
25163bd5
WS		 875 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
876 cp->reply_queue = smp_processor_id() % h->nreply_queues;
877 else
878 cp->reply_queue = reply_queue % h->nreply_queues;
879 /*
880 * Set the bits in the address sent down to include:
c349775e
ST		 881 * - performant mode bit not used in ioaccel mode 2
882 * - pull count (bits 0-3)
883 * - command type isn't needed for ioaccel2
884 */
885 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
886}
887
e85c5974
SC		 888static int is_firmware_flash_cmd(u8 *cdb)
889{
890 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
891}
892
893/*
894 * During firmware flash, the heartbeat register may not update as frequently
895 * as it should. So we dial down lockup detection during firmware flash. and
896 * dial it back up when firmware flash completes.
897 */
898#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
899#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
900static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
901 struct CommandList *c)
902{
903 if (!is_firmware_flash_cmd(c->Request.CDB))
904 return;
905 atomic_inc(&h->firmware_flash_in_progress);
906 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
907}
908
909static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
910 struct CommandList *c)
911{
912 if (is_firmware_flash_cmd(c->Request.CDB) &&
913 atomic_dec_and_test(&h->firmware_flash_in_progress))
914 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
915}
916
25163bd5
WS		 917static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
918 struct CommandList *c, int reply_queue)
3f5eac3a 919{
c05e8866
SC		 920 dial_down_lockup_detection_during_fw_flash(h, c);
921 atomic_inc(&h->commands_outstanding);
c349775e
ST		 922 switch (c->cmd_type) {
923 case CMD_IOACCEL1:
25163bd5 924 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 925 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 926 break;
927 case CMD_IOACCEL2:
25163bd5 928 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 929 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e
ST		 930 break;
931 default:
25163bd5 932 set_performant_mode(h, c, reply_queue);
c05e8866 933 h->access.submit_command(h, c);
c349775e 934 }
3f5eac3a
SC		 935}
936
25163bd5
WS		 937static void enqueue_cmd_and_start_io(struct ctlr_info *h,
938 struct CommandList *c)
939{
940 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
941}
942
3f5eac3a
SC		 943static inline int is_hba_lunid(unsigned char scsi3addr[])
944{
945 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
946}
947
948static inline int is_scsi_rev_5(struct ctlr_info *h)
949{
950 if (!h->hba_inquiry_data)
951 return 0;
952 if ((h->hba_inquiry_data[2] & 0x07) == 5)
953 return 1;
954 return 0;
955}
956
edd16368
SC		 957static int hpsa_find_target_lun(struct ctlr_info *h,
958 unsigned char scsi3addr[], int bus, int *target, int *lun)
959{
960 /* finds an unused bus, target, lun for a new physical device
961 * assumes h->devlock is held
962 */
963 int i, found = 0;
cfe5badc 964 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 965
263d9401 966 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 967
968 for (i = 0; i < h->ndevices; i++) {
969 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 970 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 971 }
972
263d9401
AM		 973 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
974 if (i < HPSA_MAX_DEVICES) {
975 /* *bus = 1; */
976 *target = i;
977 *lun = 0;
978 found = 1;
edd16368
SC		 979 }
980 return !found;
981}
982
0d96ef5f
WS		 983static inline void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
984 struct hpsa_scsi_dev_t *dev, char *description)
985{
986 dev_printk(level, &h->pdev->dev,
987 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
988 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
989 description,
990 scsi_device_type(dev->devtype),
991 dev->vendor,
992 dev->model,
993 dev->raid_level > RAID_UNKNOWN ?
994 "RAID-?" : raid_label[dev->raid_level],
995 dev->offload_config ? '+' : '-',
996 dev->offload_enabled ? '+' : '-',
997 dev->expose_state);
998}
999
edd16368
SC		 1000/* Add an entry into h->dev[] array. */
1001static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
1002 struct hpsa_scsi_dev_t *device,
1003 struct hpsa_scsi_dev_t *added[], int *nadded)
1004{
1005 /* assumes h->devlock is held */
1006 int n = h->ndevices;
1007 int i;
1008 unsigned char addr1[8], addr2[8];
1009 struct hpsa_scsi_dev_t *sd;
1010
cfe5badc 1011 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1012 dev_err(&h->pdev->dev, "too many devices, some will be "
1013 "inaccessible.\n");
1014 return -1;
1015 }
1016
1017 /* physical devices do not have lun or target assigned until now. */
1018 if (device->lun != -1)
1019 /* Logical device, lun is already assigned. */
1020 goto lun_assigned;
1021
1022 /* If this device a non-zero lun of a multi-lun device
1023 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1024 * unit no, zero otherwise.
edd16368
SC		 1025 */
1026 if (device->scsi3addr[4] == 0) {
1027 /* This is not a non-zero lun of a multi-lun device */
1028 if (hpsa_find_target_lun(h, device->scsi3addr,
1029 device->bus, &device->target, &device->lun) != 0)
1030 return -1;
1031 goto lun_assigned;
1032 }
1033
1034 /* This is a non-zero lun of a multi-lun device.
1035 * Search through our list and find the device which
1036 * has the same 8 byte LUN address, excepting byte 4.
1037 * Assign the same bus and target for this new LUN.
1038 * Use the logical unit number from the firmware.
1039 */
1040 memcpy(addr1, device->scsi3addr, 8);
1041 addr1[4] = 0;
1042 for (i = 0; i < n; i++) {
1043 sd = h->dev[i];
1044 memcpy(addr2, sd->scsi3addr, 8);
1045 addr2[4] = 0;
1046 /* differ only in byte 4? */
1047 if (memcmp(addr1, addr2, 8) == 0) {
1048 device->bus = sd->bus;
1049 device->target = sd->target;
1050 device->lun = device->scsi3addr[4];
1051 break;
1052 }
1053 }
1054 if (device->lun == -1) {
1055 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1056 " suspect firmware bug or unsupported hardware "
1057 "configuration.\n");
1058 return -1;
1059 }
1060
1061lun_assigned:
1062
1063 h->dev[n] = device;
1064 h->ndevices++;
1065 added[*nadded] = device;
1066 (*nadded)++;
0d96ef5f
WS		 1067 hpsa_show_dev_msg(KERN_INFO, h, device,
1068 device->expose_state & HPSA_SCSI_ADD ? "added" : "masked");
a473d86c
RE		 1069 device->offload_to_be_enabled = device->offload_enabled;
1070 device->offload_enabled = 0;
edd16368
SC		 1071 return 0;
1072}
1073
bd9244f7
ST		 1074/* Update an entry in h->dev[] array. */
1075static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
1076 int entry, struct hpsa_scsi_dev_t *new_entry)
1077{
a473d86c 1078 int offload_enabled;
bd9244f7
ST		 1079 /* assumes h->devlock is held */
1080 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1081
1082 /* Raid level changed. */
1083 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1084
03383736
DB		 1085 /* Raid offload parameters changed. Careful about the ordering. */
1086 if (new_entry->offload_config && new_entry->offload_enabled) {
1087 /*
1088 * if drive is newly offload_enabled, we want to copy the
1089 * raid map data first. If previously offload_enabled and
1090 * offload_config were set, raid map data had better be
1091 * the same as it was before. if raid map data is changed
1092 * then it had better be the case that
1093 * h->dev[entry]->offload_enabled is currently 0.
1094 */
1095 h->dev[entry]->raid_map = new_entry->raid_map;
1096 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1097 }
a3144e0b
JH		 1098 if (new_entry->hba_ioaccel_enabled) {
1099 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1100 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1101 }
1102 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1103 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1104 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1105 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1106
41ce4c35
SC		 1107 /*
1108 * We can turn off ioaccel offload now, but need to delay turning
1109 * it on until we can update h->dev[entry]->phys_disk[], but we
1110 * can't do that until all the devices are updated.
1111 */
1112 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1113 if (!new_entry->offload_enabled)
1114 h->dev[entry]->offload_enabled = 0;
1115
a473d86c
RE		 1116 offload_enabled = h->dev[entry]->offload_enabled;
1117 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1118 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1119 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1120}
1121
2a8ccf31
SC		 1122/* Replace an entry from h->dev[] array. */
1123static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
1124 int entry, struct hpsa_scsi_dev_t *new_entry,
1125 struct hpsa_scsi_dev_t *added[], int *nadded,
1126 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1127{
1128 /* assumes h->devlock is held */
cfe5badc 1129 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1130 removed[*nremoved] = h->dev[entry];
1131 (*nremoved)++;
01350d05
SC		 1132
1133 /*
1134 * New physical devices won't have target/lun assigned yet
1135 * so we need to preserve the values in the slot we are replacing.
1136 */
1137 if (new_entry->target == -1) {
1138 new_entry->target = h->dev[entry]->target;
1139 new_entry->lun = h->dev[entry]->lun;
1140 }
1141
2a8ccf31
SC		 1142 h->dev[entry] = new_entry;
1143 added[*nadded] = new_entry;
1144 (*nadded)++;
0d96ef5f 1145 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1146 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1147 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1148}
1149
edd16368
SC		 1150/* Remove an entry from h->dev[] array. */
1151static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1152 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1153{
1154 /* assumes h->devlock is held */
1155 int i;
1156 struct hpsa_scsi_dev_t *sd;
1157
cfe5badc 1158 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1159
1160 sd = h->dev[entry];
1161 removed[*nremoved] = h->dev[entry];
1162 (*nremoved)++;
1163
1164 for (i = entry; i < h->ndevices-1; i++)
1165 h->dev[i] = h->dev[i+1];
1166 h->ndevices--;
0d96ef5f 1167 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1168}
1169
1170#define SCSI3ADDR_EQ(a, b) ( \
1171 (a)[7] == (b)[7] && \
1172 (a)[6] == (b)[6] && \
1173 (a)[5] == (b)[5] && \
1174 (a)[4] == (b)[4] && \
1175 (a)[3] == (b)[3] && \
1176 (a)[2] == (b)[2] && \
1177 (a)[1] == (b)[1] && \
1178 (a)[0] == (b)[0])
1179
1180static void fixup_botched_add(struct ctlr_info *h,
1181 struct hpsa_scsi_dev_t *added)
1182{
1183 /* called when scsi_add_device fails in order to re-adjust
1184 * h->dev[] to match the mid layer's view.
1185 */
1186 unsigned long flags;
1187 int i, j;
1188
1189 spin_lock_irqsave(&h->lock, flags);
1190 for (i = 0; i < h->ndevices; i++) {
1191 if (h->dev[i] == added) {
1192 for (j = i; j < h->ndevices-1; j++)
1193 h->dev[j] = h->dev[j+1];
1194 h->ndevices--;
1195 break;
1196 }
1197 }
1198 spin_unlock_irqrestore(&h->lock, flags);
1199 kfree(added);
1200}
1201
1202static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1203 struct hpsa_scsi_dev_t *dev2)
1204{
edd16368
SC		 1205 /* we compare everything except lun and target as these
1206 * are not yet assigned. Compare parts likely
1207 * to differ first
1208 */
1209 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1210 sizeof(dev1->scsi3addr)) != 0)
1211 return 0;
1212 if (memcmp(dev1->device_id, dev2->device_id,
1213 sizeof(dev1->device_id)) != 0)
1214 return 0;
1215 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1216 return 0;
1217 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1218 return 0;
edd16368
SC		 1219 if (dev1->devtype != dev2->devtype)
1220 return 0;
edd16368
SC		 1221 if (dev1->bus != dev2->bus)
1222 return 0;
1223 return 1;
1224}
1225
bd9244f7
ST		 1226static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1227 struct hpsa_scsi_dev_t *dev2)
1228{
1229 /* Device attributes that can change, but don't mean
1230 * that the device is a different device, nor that the OS
1231 * needs to be told anything about the change.
1232 */
1233 if (dev1->raid_level != dev2->raid_level)
1234 return 1;
250fb125
SC		 1235 if (dev1->offload_config != dev2->offload_config)
1236 return 1;
1237 if (dev1->offload_enabled != dev2->offload_enabled)
1238 return 1;
03383736
DB		 1239 if (dev1->queue_depth != dev2->queue_depth)
1240 return 1;
bd9244f7
ST		 1241 return 0;
1242}
1243
edd16368
SC		 1244/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1245 * and return needle location in *index. If scsi3addr matches, but not
1246 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1247 * location in *index.
1248 * In the case of a minor device attribute change, such as RAID level, just
1249 * return DEVICE_UPDATED, along with the updated device's location in index.
1250 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1251 */
1252static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1253 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1254 int *index)
1255{
1256 int i;
1257#define DEVICE_NOT_FOUND 0
1258#define DEVICE_CHANGED 1
1259#define DEVICE_SAME 2
bd9244f7 1260#define DEVICE_UPDATED 3
edd16368 1261 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1262 if (haystack[i] == NULL) /* previously removed. */
1263 continue;
edd16368
SC		 1264 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1265 *index = i;
bd9244f7
ST		 1266 if (device_is_the_same(needle, haystack[i])) {
1267 if (device_updated(needle, haystack[i]))
1268 return DEVICE_UPDATED;
edd16368 1269 return DEVICE_SAME;
bd9244f7 1270 } else {
9846590e
SC		 1271 /* Keep offline devices offline */
1272 if (needle->volume_offline)
1273 return DEVICE_NOT_FOUND;
edd16368 1274 return DEVICE_CHANGED;
bd9244f7 1275 }
edd16368
SC		 1276 }
1277 }
1278 *index = -1;
1279 return DEVICE_NOT_FOUND;
1280}
1281
9846590e
SC		 1282static void hpsa_monitor_offline_device(struct ctlr_info *h,
1283 unsigned char scsi3addr[])
1284{
1285 struct offline_device_entry *device;
1286 unsigned long flags;
1287
1288 /* Check to see if device is already on the list */
1289 spin_lock_irqsave(&h->offline_device_lock, flags);
1290 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1291 if (memcmp(device->scsi3addr, scsi3addr,
1292 sizeof(device->scsi3addr)) == 0) {
1293 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1294 return;
1295 }
1296 }
1297 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1298
1299 /* Device is not on the list, add it. */
1300 device = kmalloc(sizeof(*device), GFP_KERNEL);
1301 if (!device) {
1302 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1303 return;
1304 }
1305 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1306 spin_lock_irqsave(&h->offline_device_lock, flags);
1307 list_add_tail(&device->offline_list, &h->offline_device_list);
1308 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1309}
1310
1311/* Print a message explaining various offline volume states */
1312static void hpsa_show_volume_status(struct ctlr_info *h,
1313 struct hpsa_scsi_dev_t *sd)
1314{
1315 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1316 dev_info(&h->pdev->dev,
1317 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1318 h->scsi_host->host_no,
1319 sd->bus, sd->target, sd->lun);
1320 switch (sd->volume_offline) {
1321 case HPSA_LV_OK:
1322 break;
1323 case HPSA_LV_UNDERGOING_ERASE:
1324 dev_info(&h->pdev->dev,
1325 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1326 h->scsi_host->host_no,
1327 sd->bus, sd->target, sd->lun);
1328 break;
1329 case HPSA_LV_UNDERGOING_RPI:
1330 dev_info(&h->pdev->dev,
1331 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n",
1332 h->scsi_host->host_no,
1333 sd->bus, sd->target, sd->lun);
1334 break;
1335 case HPSA_LV_PENDING_RPI:
1336 dev_info(&h->pdev->dev,
1337 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1338 h->scsi_host->host_no,
1339 sd->bus, sd->target, sd->lun);
1340 break;
1341 case HPSA_LV_ENCRYPTED_NO_KEY:
1342 dev_info(&h->pdev->dev,
1343 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1344 h->scsi_host->host_no,
1345 sd->bus, sd->target, sd->lun);
1346 break;
1347 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1348 dev_info(&h->pdev->dev,
1349 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1350 h->scsi_host->host_no,
1351 sd->bus, sd->target, sd->lun);
1352 break;
1353 case HPSA_LV_UNDERGOING_ENCRYPTION:
1354 dev_info(&h->pdev->dev,
1355 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1356 h->scsi_host->host_no,
1357 sd->bus, sd->target, sd->lun);
1358 break;
1359 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1360 dev_info(&h->pdev->dev,
1361 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1362 h->scsi_host->host_no,
1363 sd->bus, sd->target, sd->lun);
1364 break;
1365 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1366 dev_info(&h->pdev->dev,
1367 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1368 h->scsi_host->host_no,
1369 sd->bus, sd->target, sd->lun);
1370 break;
1371 case HPSA_LV_PENDING_ENCRYPTION:
1372 dev_info(&h->pdev->dev,
1373 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1374 h->scsi_host->host_no,
1375 sd->bus, sd->target, sd->lun);
1376 break;
1377 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1378 dev_info(&h->pdev->dev,
1379 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1380 h->scsi_host->host_no,
1381 sd->bus, sd->target, sd->lun);
1382 break;
1383 }
1384}
1385
03383736
DB		 1386/*
1387 * Figure the list of physical drive pointers for a logical drive with
1388 * raid offload configured.
1389 */
1390static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1391 struct hpsa_scsi_dev_t *dev[], int ndevices,
1392 struct hpsa_scsi_dev_t *logical_drive)
1393{
1394 struct raid_map_data *map = &logical_drive->raid_map;
1395 struct raid_map_disk_data *dd = &map->data[0];
1396 int i, j;
1397 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1398 le16_to_cpu(map->metadata_disks_per_row);
1399 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1400 le16_to_cpu(map->layout_map_count) *
1401 total_disks_per_row;
1402 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1403 total_disks_per_row;
1404 int qdepth;
1405
1406 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1407 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1408
1409 qdepth = 0;
1410 for (i = 0; i < nraid_map_entries; i++) {
1411 logical_drive->phys_disk[i] = NULL;
1412 if (!logical_drive->offload_config)
1413 continue;
1414 for (j = 0; j < ndevices; j++) {
1415 if (dev[j]->devtype != TYPE_DISK)
1416 continue;
1417 if (is_logical_dev_addr_mode(dev[j]->scsi3addr))
1418 continue;
1419 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1420 continue;
1421
1422 logical_drive->phys_disk[i] = dev[j];
1423 if (i < nphys_disk)
1424 qdepth = min(h->nr_cmds, qdepth +
1425 logical_drive->phys_disk[i]->queue_depth);
1426 break;
1427 }
1428
1429 /*
1430 * This can happen if a physical drive is removed and
1431 * the logical drive is degraded. In that case, the RAID
1432 * map data will refer to a physical disk which isn't actually
1433 * present. And in that case offload_enabled should already
1434 * be 0, but we'll turn it off here just in case
1435 */
1436 if (!logical_drive->phys_disk[i]) {
1437 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1438 logical_drive->offload_to_be_enabled = 0;
1439 logical_drive->queue_depth = 8;
03383736
DB		 1440 }
1441 }
1442 if (nraid_map_entries)
1443 /*
1444 * This is correct for reads, too high for full stripe writes,
1445 * way too high for partial stripe writes
1446 */
1447 logical_drive->queue_depth = qdepth;
1448 else
1449 logical_drive->queue_depth = h->nr_cmds;
1450}
1451
1452static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1453 struct hpsa_scsi_dev_t *dev[], int ndevices)
1454{
1455 int i;
1456
1457 for (i = 0; i < ndevices; i++) {
1458 if (dev[i]->devtype != TYPE_DISK)
1459 continue;
1460 if (!is_logical_dev_addr_mode(dev[i]->scsi3addr))
1461 continue;
41ce4c35
SC		 1462
1463 /*
1464 * If offload is currently enabled, the RAID map and
1465 * phys_disk[] assignment *better* not be changing
1466 * and since it isn't changing, we do not need to
1467 * update it.
1468 */
1469 if (dev[i]->offload_enabled)
1470 continue;
1471
03383736
DB		 1472 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1473 }
1474}
1475
4967bd3e 1476static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1477 struct hpsa_scsi_dev_t *sd[], int nsds)
1478{
1479 /* sd contains scsi3 addresses and devtypes, and inquiry
1480 * data. This function takes what's in sd to be the current
1481 * reality and updates h->dev[] to reflect that reality.
1482 */
1483 int i, entry, device_change, changes = 0;
1484 struct hpsa_scsi_dev_t *csd;
1485 unsigned long flags;
1486 struct hpsa_scsi_dev_t **added, **removed;
1487 int nadded, nremoved;
1488 struct Scsi_Host *sh = NULL;
1489
cfe5badc
ST		 1490 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1491 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1492
1493 if (!added || !removed) {
1494 dev_warn(&h->pdev->dev, "out of memory in "
1495 "adjust_hpsa_scsi_table\n");
1496 goto free_and_out;
1497 }
1498
1499 spin_lock_irqsave(&h->devlock, flags);
1500
1501 /* find any devices in h->dev[] that are not in
1502 * sd[] and remove them from h->dev[], and for any
1503 * devices which have changed, remove the old device
1504 * info and add the new device info.
bd9244f7
ST		 1505 * If minor device attributes change, just update
1506 * the existing device structure.
edd16368
SC		 1507 */
1508 i = 0;
1509 nremoved = 0;
1510 nadded = 0;
1511 while (i < h->ndevices) {
1512 csd = h->dev[i];
1513 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1514 if (device_change == DEVICE_NOT_FOUND) {
1515 changes++;
1516 hpsa_scsi_remove_entry(h, hostno, i,
1517 removed, &nremoved);
1518 continue; /* remove ^^^, hence i not incremented */
1519 } else if (device_change == DEVICE_CHANGED) {
1520 changes++;
2a8ccf31
SC		 1521 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1522 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1523 /* Set it to NULL to prevent it from being freed
1524 * at the bottom of hpsa_update_scsi_devices()
1525 */
1526 sd[entry] = NULL;
bd9244f7
ST		 1527 } else if (device_change == DEVICE_UPDATED) {
1528 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1529 }
1530 i++;
1531 }
1532
1533 /* Now, make sure every device listed in sd[] is also
1534 * listed in h->dev[], adding them if they aren't found
1535 */
1536
1537 for (i = 0; i < nsds; i++) {
1538 if (!sd[i]) /* if already added above. */
1539 continue;
9846590e
SC		 1540
1541 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1542 * as the SCSI mid-layer does not handle such devices well.
1543 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1544 * at 160Hz, and prevents the system from coming up.
1545 */
1546 if (sd[i]->volume_offline) {
1547 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1548 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1549 continue;
1550 }
1551
edd16368
SC		 1552 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1553 h->ndevices, &entry);
1554 if (device_change == DEVICE_NOT_FOUND) {
1555 changes++;
1556 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1557 added, &nadded) != 0)
1558 break;
1559 sd[i] = NULL; /* prevent from being freed later. */
1560 } else if (device_change == DEVICE_CHANGED) {
1561 /* should never happen... */
1562 changes++;
1563 dev_warn(&h->pdev->dev,
1564 "device unexpectedly changed.\n");
1565 /* but if it does happen, we just ignore that device */
1566 }
1567 }
41ce4c35
SC		 1568 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1569
1570 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1571 * any logical drives that need it enabled.
1572 */
1573 for (i = 0; i < h->ndevices; i++)
1574 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1575
edd16368
SC		 1576 spin_unlock_irqrestore(&h->devlock, flags);
1577
9846590e
SC		 1578 /* Monitor devices which are in one of several NOT READY states to be
1579 * brought online later. This must be done without holding h->devlock,
1580 * so don't touch h->dev[]
1581 */
1582 for (i = 0; i < nsds; i++) {
1583 if (!sd[i]) /* if already added above. */
1584 continue;
1585 if (sd[i]->volume_offline)
1586 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1587 }
1588
edd16368
SC		 1589 /* Don't notify scsi mid layer of any changes the first time through
1590 * (or if there are no changes) scsi_scan_host will do it later the
1591 * first time through.
1592 */
1593 if (hostno == -1 || !changes)
1594 goto free_and_out;
1595
1596 sh = h->scsi_host;
1597 /* Notify scsi mid layer of any removed devices */
1598 for (i = 0; i < nremoved; i++) {
41ce4c35
SC		 1599 if (removed[i]->expose_state & HPSA_SCSI_ADD) {
1600 struct scsi_device *sdev =
1601 scsi_device_lookup(sh, removed[i]->bus,
1602 removed[i]->target, removed[i]->lun);
1603 if (sdev != NULL) {
1604 scsi_remove_device(sdev);
1605 scsi_device_put(sdev);
1606 } else {
1607 /*
1608 * We don't expect to get here.
1609 * future cmds to this device will get selection
1610 * timeout as if the device was gone.
1611 */
0d96ef5f
WS		 1612 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1613 "didn't find device for removal.");
41ce4c35 1614 }
edd16368
SC		 1615 }
1616 kfree(removed[i]);
1617 removed[i] = NULL;
1618 }
1619
1620 /* Notify scsi mid layer of any added devices */
1621 for (i = 0; i < nadded; i++) {
41ce4c35
SC		 1622 if (!(added[i]->expose_state & HPSA_SCSI_ADD))
1623 continue;
edd16368
SC		 1624 if (scsi_add_device(sh, added[i]->bus,
1625 added[i]->target, added[i]->lun) == 0)
1626 continue;
0d96ef5f
WS		 1627 hpsa_show_dev_msg(KERN_WARNING, h, added[i],
1628 "addition failed, device not added.");
edd16368
SC		 1629 /* now we have to remove it from h->dev,
1630 * since it didn't get added to scsi mid layer
1631 */
1632 fixup_botched_add(h, added[i]);
1633 }
1634
1635free_and_out:
1636 kfree(added);
1637 kfree(removed);
edd16368
SC		 1638}
1639
1640/*
9e03aa2f 1641 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1642 * Assume's h->devlock is held.
1643 */
1644static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1645 int bus, int target, int lun)
1646{
1647 int i;
1648 struct hpsa_scsi_dev_t *sd;
1649
1650 for (i = 0; i < h->ndevices; i++) {
1651 sd = h->dev[i];
1652 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1653 return sd;
1654 }
1655 return NULL;
1656}
1657
edd16368
SC		 1658static int hpsa_slave_alloc(struct scsi_device *sdev)
1659{
1660 struct hpsa_scsi_dev_t *sd;
1661 unsigned long flags;
1662 struct ctlr_info *h;
1663
1664 h = sdev_to_hba(sdev);
1665 spin_lock_irqsave(&h->devlock, flags);
1666 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1667 sdev_id(sdev), sdev->lun);
41ce4c35 1668 if (likely(sd)) {
03383736 1669 atomic_set(&sd->ioaccel_cmds_out, 0);
41ce4c35
SC		 1670 sdev->hostdata = (sd->expose_state & HPSA_SCSI_ADD) ? sd : NULL;
1671 } else
1672 sdev->hostdata = NULL;
edd16368
SC		 1673 spin_unlock_irqrestore(&h->devlock, flags);
1674 return 0;
1675}
1676
41ce4c35
SC		 1677/* configure scsi device based on internal per-device structure */
1678static int hpsa_slave_configure(struct scsi_device *sdev)
1679{
1680 struct hpsa_scsi_dev_t *sd;
1681 int queue_depth;
1682
1683 sd = sdev->hostdata;
1684 sdev->no_uld_attach = !sd || !(sd->expose_state & HPSA_ULD_ATTACH);
1685
1686 if (sd)
1687 queue_depth = sd->queue_depth != 0 ?
1688 sd->queue_depth : sdev->host->can_queue;
1689 else
1690 queue_depth = sdev->host->can_queue;
1691
1692 scsi_change_queue_depth(sdev, queue_depth);
1693
1694 return 0;
1695}
1696
edd16368
SC		 1697static void hpsa_slave_destroy(struct scsi_device *sdev)
1698{
bcc44255 1699 /* nothing to do. */
edd16368
SC		 1700}
1701
d9a729f3
WS		 1702static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1703{
1704 int i;
1705
1706 if (!h->ioaccel2_cmd_sg_list)
1707 return;
1708 for (i = 0; i < h->nr_cmds; i++) {
1709 kfree(h->ioaccel2_cmd_sg_list[i]);
1710 h->ioaccel2_cmd_sg_list[i] = NULL;
1711 }
1712 kfree(h->ioaccel2_cmd_sg_list);
1713 h->ioaccel2_cmd_sg_list = NULL;
1714}
1715
1716static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1717{
1718 int i;
1719
1720 if (h->chainsize <= 0)
1721 return 0;
1722
1723 h->ioaccel2_cmd_sg_list =
1724 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1725 GFP_KERNEL);
1726 if (!h->ioaccel2_cmd_sg_list)
1727 return -ENOMEM;
1728 for (i = 0; i < h->nr_cmds; i++) {
1729 h->ioaccel2_cmd_sg_list[i] =
1730 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1731 h->maxsgentries, GFP_KERNEL);
1732 if (!h->ioaccel2_cmd_sg_list[i])
1733 goto clean;
1734 }
1735 return 0;
1736
1737clean:
1738 hpsa_free_ioaccel2_sg_chain_blocks(h);
1739 return -ENOMEM;
1740}
1741
33a2ffce
SC		 1742static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1743{
1744 int i;
1745
1746 if (!h->cmd_sg_list)
1747 return;
1748 for (i = 0; i < h->nr_cmds; i++) {
1749 kfree(h->cmd_sg_list[i]);
1750 h->cmd_sg_list[i] = NULL;
1751 }
1752 kfree(h->cmd_sg_list);
1753 h->cmd_sg_list = NULL;
1754}
1755
1756static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1757{
1758 int i;
1759
1760 if (h->chainsize <= 0)
1761 return 0;
1762
1763 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1764 GFP_KERNEL);
3d4e6af8
RE		 1765 if (!h->cmd_sg_list) {
1766 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1767 return -ENOMEM;
3d4e6af8 1768 }
33a2ffce
SC		 1769 for (i = 0; i < h->nr_cmds; i++) {
1770 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1771 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1772 if (!h->cmd_sg_list[i]) {
1773 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1774 goto clean;
3d4e6af8 1775 }
33a2ffce
SC		 1776 }
1777 return 0;
1778
1779clean:
1780 hpsa_free_sg_chain_blocks(h);
1781 return -ENOMEM;
1782}
1783
d9a729f3
WS		 1784static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1785 struct io_accel2_cmd *cp, struct CommandList *c)
1786{
1787 struct ioaccel2_sg_element *chain_block;
1788 u64 temp64;
1789 u32 chain_size;
1790
1791 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
1792 chain_size = le32_to_cpu(cp->data_len);
1793 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1794 PCI_DMA_TODEVICE);
1795 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1796 /* prevent subsequent unmapping */
1797 cp->sg->address = 0;
1798 return -1;
1799 }
1800 cp->sg->address = cpu_to_le64(temp64);
1801 return 0;
1802}
1803
1804static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
1805 struct io_accel2_cmd *cp)
1806{
1807 struct ioaccel2_sg_element *chain_sg;
1808 u64 temp64;
1809 u32 chain_size;
1810
1811 chain_sg = cp->sg;
1812 temp64 = le64_to_cpu(chain_sg->address);
1813 chain_size = le32_to_cpu(cp->data_len);
1814 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
1815}
1816
e2bea6df 1817static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1818 struct CommandList *c)
1819{
1820 struct SGDescriptor *chain_sg, *chain_block;
1821 u64 temp64;
50a0decf 1822 u32 chain_len;
33a2ffce
SC		 1823
1824 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1825 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 1826 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
1827 chain_len = sizeof(*chain_sg) *
2b08b3e9 1828 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 1829 chain_sg->Len = cpu_to_le32(chain_len);
1830 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 1831 PCI_DMA_TODEVICE);
e2bea6df
SC		 1832 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1833 /* prevent subsequent unmapping */
50a0decf 1834 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 1835 return -1;
1836 }
50a0decf 1837 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 1838 return 0;
33a2ffce
SC		 1839}
1840
1841static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1842 struct CommandList *c)
1843{
1844 struct SGDescriptor *chain_sg;
33a2ffce 1845
50a0decf 1846 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 1847 return;
1848
1849 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 1850 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
1851 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 1852}
1853
a09c1441
ST		 1854
1855/* Decode the various types of errors on ioaccel2 path.
1856 * Return 1 for any error that should generate a RAID path retry.
1857 * Return 0 for errors that don't require a RAID path retry.
1858 */
1859static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1860 struct CommandList *c,
1861 struct scsi_cmnd *cmd,
1862 struct io_accel2_cmd *c2)
1863{
1864 int data_len;
a09c1441 1865 int retry = 0;
c349775e
ST		 1866
1867 switch (c2->error_data.serv_response) {
1868 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1869 switch (c2->error_data.status) {
1870 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1871 break;
1872 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1873 dev_warn(&h->pdev->dev,
1874 "%s: task complete with check condition.\n",
1875 "HP SSD Smart Path");
ee6b1889 1876 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 1877 if (c2->error_data.data_present !=
ee6b1889
SC		 1878 IOACCEL2_SENSE_DATA_PRESENT) {
1879 memset(cmd->sense_buffer, 0,
1880 SCSI_SENSE_BUFFERSIZE);
c349775e 1881 break;
ee6b1889 1882 }
c349775e
ST		 1883 /* copy the sense data */
1884 data_len = c2->error_data.sense_data_len;
1885 if (data_len > SCSI_SENSE_BUFFERSIZE)
1886 data_len = SCSI_SENSE_BUFFERSIZE;
1887 if (data_len > sizeof(c2->error_data.sense_data_buff))
1888 data_len =
1889 sizeof(c2->error_data.sense_data_buff);
1890 memcpy(cmd->sense_buffer,
1891 c2->error_data.sense_data_buff, data_len);
a09c1441 1892 retry = 1;
c349775e
ST		 1893 break;
1894 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1895 dev_warn(&h->pdev->dev,
1896 "%s: task complete with BUSY status.\n",
1897 "HP SSD Smart Path");
a09c1441 1898 retry = 1;
c349775e
ST		 1899 break;
1900 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1901 dev_warn(&h->pdev->dev,
1902 "%s: task complete with reservation conflict.\n",
1903 "HP SSD Smart Path");
a09c1441 1904 retry = 1;
c349775e
ST		 1905 break;
1906 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 1907 retry = 1;
c349775e
ST		 1908 break;
1909 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1910 dev_warn(&h->pdev->dev,
1911 "%s: task complete with aborted status.\n",
1912 "HP SSD Smart Path");
a09c1441 1913 retry = 1;
c349775e
ST		 1914 break;
1915 default:
1916 dev_warn(&h->pdev->dev,
1917 "%s: task complete with unrecognized status: 0x%02x\n",
1918 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1919 retry = 1;
c349775e
ST		 1920 break;
1921 }
1922 break;
1923 case IOACCEL2_SERV_RESPONSE_FAILURE:
1924 /* don't expect to get here. */
1925 dev_warn(&h->pdev->dev,
1926 "unexpected delivery or target failure, status = 0x%02x\n",
1927 c2->error_data.status);
a09c1441 1928 retry = 1;
c349775e
ST		 1929 break;
1930 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1931 break;
1932 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1933 break;
1934 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1935 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1936 retry = 1;
c349775e
ST		 1937 break;
1938 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1939 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1940 break;
1941 default:
1942 dev_warn(&h->pdev->dev,
1943 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1944 "HP SSD Smart Path",
1945 c2->error_data.serv_response);
1946 retry = 1;
c349775e
ST		 1947 break;
1948 }
a09c1441
ST		 1949
1950 return retry; /* retry on raid path? */
c349775e
ST		 1951}
1952
1953static void process_ioaccel2_completion(struct ctlr_info *h,
1954 struct CommandList *c, struct scsi_cmnd *cmd,
1955 struct hpsa_scsi_dev_t *dev)
1956{
1957 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1958
1959 /* check for good status */
1960 if (likely(c2->error_data.serv_response == 0 &&
1961 c2->error_data.status == 0)) {
1962 cmd_free(h, c);
1963 cmd->scsi_done(cmd);
1964 return;
1965 }
1966
1967 /* Any RAID offload error results in retry which will use
1968 * the normal I/O path so the controller can handle whatever's
1969 * wrong.
1970 */
1971 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1972 c2->error_data.serv_response ==
1973 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 1974 if (c2->error_data.status ==
1975 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1976 dev->offload_enabled = 0;
1977 goto retry_cmd;
a09c1441 1978 }
080ef1cc
DB		 1979
1980 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
1981 goto retry_cmd;
1982
c349775e
ST		 1983 cmd_free(h, c);
1984 cmd->scsi_done(cmd);
080ef1cc
DB		 1985 return;
1986
1987retry_cmd:
1988 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
1989 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
c349775e
ST		 1990}
1991
9437ac43
SC		 1992/* Returns 0 on success, < 0 otherwise. */
1993static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
1994 struct CommandList *cp)
1995{
1996 u8 tmf_status = cp->err_info->ScsiStatus;
1997
1998 switch (tmf_status) {
1999 case CISS_TMF_COMPLETE:
2000 /*
2001 * CISS_TMF_COMPLETE never happens, instead,
2002 * ei->CommandStatus == 0 for this case.
2003 */
2004 case CISS_TMF_SUCCESS:
2005 return 0;
2006 case CISS_TMF_INVALID_FRAME:
2007 case CISS_TMF_NOT_SUPPORTED:
2008 case CISS_TMF_FAILED:
2009 case CISS_TMF_WRONG_LUN:
2010 case CISS_TMF_OVERLAPPED_TAG:
2011 break;
2012 default:
2013 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2014 tmf_status);
2015 break;
2016 }
2017 return -tmf_status;
2018}
2019
1fb011fb 2020static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2021{
2022 struct scsi_cmnd *cmd;
2023 struct ctlr_info *h;
2024 struct ErrorInfo *ei;
283b4a9b 2025 struct hpsa_scsi_dev_t *dev;
d9a729f3 2026 struct io_accel2_cmd *c2;
edd16368 2027
9437ac43
SC		 2028 u8 sense_key;
2029 u8 asc; /* additional sense code */
2030 u8 ascq; /* additional sense code qualifier */
db111e18 2031 unsigned long sense_data_size;
edd16368
SC		 2032
2033 ei = cp->err_info;
7fa3030c 2034 cmd = cp->scsi_cmd;
edd16368 2035 h = cp->h;
283b4a9b 2036 dev = cmd->device->hostdata;
d9a729f3 2037 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2038
2039 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2040 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2041 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2042 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2043
d9a729f3
WS		 2044 if ((cp->cmd_type == CMD_IOACCEL2) &&
2045 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2046 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2047
edd16368
SC		 2048 cmd->result = (DID_OK << 16); /* host byte */
2049 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2050
03383736
DB		 2051 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2052 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2053
25163bd5
WS		 2054 /*
2055 * We check for lockup status here as it may be set for
2056 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2057 * fail_all_oustanding_cmds()
2058 */
2059 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2060 /* DID_NO_CONNECT will prevent a retry */
2061 cmd->result = DID_NO_CONNECT << 16;
2062 cmd_free(h, cp);
2063 cmd->scsi_done(cmd);
2064 return;
2065 }
2066
c349775e
ST		 2067 if (cp->cmd_type == CMD_IOACCEL2)
2068 return process_ioaccel2_completion(h, cp, cmd, dev);
2069
6aa4c361
RE		 2070 scsi_set_resid(cmd, ei->ResidualCnt);
2071 if (ei->CommandStatus == 0) {
03383736
DB		 2072 if (cp->cmd_type == CMD_IOACCEL1)
2073 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
6aa4c361
RE		 2074 cmd_free(h, cp);
2075 cmd->scsi_done(cmd);
2076 return;
2077 }
2078
e1f7de0c
MG		 2079 /* For I/O accelerator commands, copy over some fields to the normal
2080 * CISS header used below for error handling.
2081 */
2082 if (cp->cmd_type == CMD_IOACCEL1) {
2083 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2084 cp->Header.SGList = scsi_sg_count(cmd);
2085 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2086 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2087 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2088 cp->Header.tag = c->tag;
e1f7de0c
MG		 2089 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2090 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2091
2092 /* Any RAID offload error results in retry which will use
2093 * the normal I/O path so the controller can handle whatever's
2094 * wrong.
2095 */
2096 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
2097 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2098 dev->offload_enabled = 0;
080ef1cc
DB		 2099 INIT_WORK(&cp->work, hpsa_command_resubmit_worker);
2100 queue_work_on(raw_smp_processor_id(),
2101 h->resubmit_wq, &cp->work);
283b4a9b
SC		 2102 return;
2103 }
e1f7de0c
MG		 2104 }
2105
edd16368
SC		 2106 /* an error has occurred */
2107 switch (ei->CommandStatus) {
2108
2109 case CMD_TARGET_STATUS:
9437ac43
SC		 2110 cmd->result |= ei->ScsiStatus;
2111 /* copy the sense data */
2112 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2113 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2114 else
2115 sense_data_size = sizeof(ei->SenseInfo);
2116 if (ei->SenseLen < sense_data_size)
2117 sense_data_size = ei->SenseLen;
2118 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2119 if (ei->ScsiStatus)
2120 decode_sense_data(ei->SenseInfo, sense_data_size,
2121 &sense_key, &asc, &ascq);
edd16368 2122 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2123 if (sense_key == ABORTED_COMMAND) {
2e311fba 2124 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2125 break;
2126 }
edd16368
SC		 2127 break;
2128 }
edd16368
SC		 2129 /* Problem was not a check condition
2130 * Pass it up to the upper layers...
2131 */
2132 if (ei->ScsiStatus) {
2133 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2134 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2135 "Returning result: 0x%x\n",
2136 cp, ei->ScsiStatus,
2137 sense_key, asc, ascq,
2138 cmd->result);
2139 } else { /* scsi status is zero??? How??? */
2140 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2141 "Returning no connection.\n", cp),
2142
2143 /* Ordinarily, this case should never happen,
2144 * but there is a bug in some released firmware
2145 * revisions that allows it to happen if, for
2146 * example, a 4100 backplane loses power and
2147 * the tape drive is in it. We assume that
2148 * it's a fatal error of some kind because we
2149 * can't show that it wasn't. We will make it
2150 * look like selection timeout since that is
2151 * the most common reason for this to occur,
2152 * and it's severe enough.
2153 */
2154
2155 cmd->result = DID_NO_CONNECT << 16;
2156 }
2157 break;
2158
2159 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2160 break;
2161 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2162 dev_warn(&h->pdev->dev,
2163 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2164 break;
2165 case CMD_INVALID: {
2166 /* print_bytes(cp, sizeof(*cp), 1, 0);
2167 print_cmd(cp); */
2168 /* We get CMD_INVALID if you address a non-existent device
2169 * instead of a selection timeout (no response). You will
2170 * see this if you yank out a drive, then try to access it.
2171 * This is kind of a shame because it means that any other
2172 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2173 * missing target. */
2174 cmd->result = DID_NO_CONNECT << 16;
2175 }
2176 break;
2177 case CMD_PROTOCOL_ERR:
256d0eaa 2178 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2179 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2180 cp->Request.CDB);
edd16368
SC		 2181 break;
2182 case CMD_HARDWARE_ERR:
2183 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2184 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2185 cp->Request.CDB);
edd16368
SC		 2186 break;
2187 case CMD_CONNECTION_LOST:
2188 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2189 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2190 cp->Request.CDB);
edd16368
SC		 2191 break;
2192 case CMD_ABORTED:
2193 cmd->result = DID_ABORT << 16;
f42e81e1
SC		 2194 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2195 cp->Request.CDB, ei->ScsiStatus);
edd16368
SC		 2196 break;
2197 case CMD_ABORT_FAILED:
2198 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2199 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2200 cp->Request.CDB);
edd16368
SC		 2201 break;
2202 case CMD_UNSOLICITED_ABORT:
f6e76055 2203 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2204 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2205 cp->Request.CDB);
edd16368
SC		 2206 break;
2207 case CMD_TIMEOUT:
2208 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2209 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2210 cp->Request.CDB);
edd16368 2211 break;
1d5e2ed0
SC		 2212 case CMD_UNABORTABLE:
2213 cmd->result = DID_ERROR << 16;
2214 dev_warn(&h->pdev->dev, "Command unabortable\n");
2215 break;
9437ac43
SC		 2216 case CMD_TMF_STATUS:
2217 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2218 cmd->result = DID_ERROR << 16;
2219 break;
283b4a9b
SC		 2220 case CMD_IOACCEL_DISABLED:
2221 /* This only handles the direct pass-through case since RAID
2222 * offload is handled above. Just attempt a retry.
2223 */
2224 cmd->result = DID_SOFT_ERROR << 16;
2225 dev_warn(&h->pdev->dev,
2226 "cp %p had HP SSD Smart Path error\n", cp);
2227 break;
edd16368
SC		 2228 default:
2229 cmd->result = DID_ERROR << 16;
2230 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2231 cp, ei->CommandStatus);
2232 }
edd16368 2233 cmd_free(h, cp);
2cc5bfaf 2234 cmd->scsi_done(cmd);
edd16368
SC		 2235}
2236
edd16368
SC		 2237static void hpsa_pci_unmap(struct pci_dev *pdev,
2238 struct CommandList *c, int sg_used, int data_direction)
2239{
2240 int i;
edd16368 2241
50a0decf
SC		 2242 for (i = 0; i < sg_used; i++)
2243 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2244 le32_to_cpu(c->SG[i].Len),
2245 data_direction);
edd16368
SC		 2246}
2247
a2dac136 2248static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2249 struct CommandList *cp,
2250 unsigned char *buf,
2251 size_t buflen,
2252 int data_direction)
2253{
01a02ffc 2254 u64 addr64;
edd16368
SC		 2255
2256 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2257 cp->Header.SGList = 0;
50a0decf 2258 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2259 return 0;
edd16368
SC		 2260 }
2261
50a0decf 2262 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2263 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2264 /* Prevent subsequent unmap of something never mapped */
eceaae18 2265 cp->Header.SGList = 0;
50a0decf 2266 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2267 return -1;
eceaae18 2268 }
50a0decf
SC		 2269 cp->SG[0].Addr = cpu_to_le64(addr64);
2270 cp->SG[0].Len = cpu_to_le32(buflen);
2271 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2272 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2273 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2274 return 0;
edd16368
SC		 2275}
2276
25163bd5
WS		 2277#define NO_TIMEOUT ((unsigned long) -1)
2278#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2279static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2280 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2281{
2282 DECLARE_COMPLETION_ONSTACK(wait);
2283
2284 c->waiting = &wait;
25163bd5
WS		 2285 __enqueue_cmd_and_start_io(h, c, reply_queue);
2286 if (timeout_msecs == NO_TIMEOUT) {
2287 /* TODO: get rid of this no-timeout thing */
2288 wait_for_completion_io(&wait);
2289 return IO_OK;
2290 }
2291 if (!wait_for_completion_io_timeout(&wait,
2292 msecs_to_jiffies(timeout_msecs))) {
2293 dev_warn(&h->pdev->dev, "Command timed out.\n");
2294 return -ETIMEDOUT;
2295 }
2296 return IO_OK;
2297}
2298
2299static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2300 int reply_queue, unsigned long timeout_msecs)
2301{
2302 if (unlikely(lockup_detected(h))) {
2303 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2304 return IO_OK;
2305 }
2306 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2307}
2308
094963da
SC		 2309static u32 lockup_detected(struct ctlr_info *h)
2310{
2311 int cpu;
2312 u32 rc, *lockup_detected;
2313
2314 cpu = get_cpu();
2315 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2316 rc = *lockup_detected;
2317 put_cpu();
2318 return rc;
2319}
2320
9c2fc160 2321#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2322static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2323 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2324{
9c2fc160 2325 int backoff_time = 10, retry_count = 0;
25163bd5 2326 int rc;
edd16368
SC		 2327
2328 do {
7630abd0 2329 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2330 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2331 timeout_msecs);
2332 if (rc)
2333 break;
edd16368 2334 retry_count++;
9c2fc160
SC		 2335 if (retry_count > 3) {
2336 msleep(backoff_time);
2337 if (backoff_time < 1000)
2338 backoff_time *= 2;
2339 }
852af20a 2340 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2341 check_for_busy(h, c)) &&
2342 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2343 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2344 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2345 rc = -EIO;
2346 return rc;
edd16368
SC		 2347}
2348
d1e8beac
SC		 2349static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2350 struct CommandList *c)
edd16368 2351{
d1e8beac
SC		 2352 const u8 *cdb = c->Request.CDB;
2353 const u8 *lun = c->Header.LUN.LunAddrBytes;
2354
2355 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2356 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2357 txt, lun[0], lun[1], lun[2], lun[3],
2358 lun[4], lun[5], lun[6], lun[7],
2359 cdb[0], cdb[1], cdb[2], cdb[3],
2360 cdb[4], cdb[5], cdb[6], cdb[7],
2361 cdb[8], cdb[9], cdb[10], cdb[11],
2362 cdb[12], cdb[13], cdb[14], cdb[15]);
2363}
2364
2365static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2366 struct CommandList *cp)
2367{
2368 const struct ErrorInfo *ei = cp->err_info;
edd16368 2369 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2370 u8 sense_key, asc, ascq;
2371 int sense_len;
edd16368 2372
edd16368
SC		 2373 switch (ei->CommandStatus) {
2374 case CMD_TARGET_STATUS:
9437ac43
SC		 2375 if (ei->SenseLen > sizeof(ei->SenseInfo))
2376 sense_len = sizeof(ei->SenseInfo);
2377 else
2378 sense_len = ei->SenseLen;
2379 decode_sense_data(ei->SenseInfo, sense_len,
2380 &sense_key, &asc, &ascq);
d1e8beac
SC		 2381 hpsa_print_cmd(h, "SCSI status", cp);
2382 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2383 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2384 sense_key, asc, ascq);
d1e8beac 2385 else
9437ac43 2386 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2387 if (ei->ScsiStatus == 0)
2388 dev_warn(d, "SCSI status is abnormally zero. "
2389 "(probably indicates selection timeout "
2390 "reported incorrectly due to a known "
2391 "firmware bug, circa July, 2001.)\n");
2392 break;
2393 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2394 break;
2395 case CMD_DATA_OVERRUN:
d1e8beac 2396 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2397 break;
2398 case CMD_INVALID: {
2399 /* controller unfortunately reports SCSI passthru's
2400 * to non-existent targets as invalid commands.
2401 */
d1e8beac
SC		 2402 hpsa_print_cmd(h, "invalid command", cp);
2403 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2404 }
2405 break;
2406 case CMD_PROTOCOL_ERR:
d1e8beac 2407 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2408 break;
2409 case CMD_HARDWARE_ERR:
d1e8beac 2410 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2411 break;
2412 case CMD_CONNECTION_LOST:
d1e8beac 2413 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2414 break;
2415 case CMD_ABORTED:
d1e8beac 2416 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2417 break;
2418 case CMD_ABORT_FAILED:
d1e8beac 2419 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2420 break;
2421 case CMD_UNSOLICITED_ABORT:
d1e8beac 2422 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2423 break;
2424 case CMD_TIMEOUT:
d1e8beac 2425 hpsa_print_cmd(h, "timed out", cp);
edd16368 2426 break;
1d5e2ed0 2427 case CMD_UNABORTABLE:
d1e8beac 2428 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2429 break;
25163bd5
WS		 2430 case CMD_CTLR_LOCKUP:
2431 hpsa_print_cmd(h, "controller lockup detected", cp);
2432 break;
edd16368 2433 default:
d1e8beac
SC		 2434 hpsa_print_cmd(h, "unknown status", cp);
2435 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2436 ei->CommandStatus);
2437 }
2438}
2439
2440static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2441 u16 page, unsigned char *buf,
edd16368
SC		 2442 unsigned char bufsize)
2443{
2444 int rc = IO_OK;
2445 struct CommandList *c;
2446 struct ErrorInfo *ei;
2447
45fcb86e 2448 c = cmd_alloc(h);
edd16368 2449
574f05d3 2450 if (c == NULL) {
45fcb86e 2451 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
ecd9aad4 2452 return -ENOMEM;
edd16368
SC		 2453 }
2454
a2dac136
SC		 2455 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2456 page, scsi3addr, TYPE_CMD)) {
2457 rc = -1;
2458 goto out;
2459 }
25163bd5
WS		 2460 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2461 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2462 if (rc)
2463 goto out;
edd16368
SC		 2464 ei = c->err_info;
2465 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2466 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2467 rc = -1;
2468 }
a2dac136 2469out:
45fcb86e 2470 cmd_free(h, c);
edd16368
SC		 2471 return rc;
2472}
2473
316b221a
SC		 2474static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h,
2475 unsigned char *scsi3addr, unsigned char page,
2476 struct bmic_controller_parameters *buf, size_t bufsize)
2477{
2478 int rc = IO_OK;
2479 struct CommandList *c;
2480 struct ErrorInfo *ei;
2481
45fcb86e 2482 c = cmd_alloc(h);
316b221a 2483 if (c == NULL) { /* trouble... */
45fcb86e 2484 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
316b221a
SC		 2485 return -ENOMEM;
2486 }
2487
2488 if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize,
2489 page, scsi3addr, TYPE_CMD)) {
2490 rc = -1;
2491 goto out;
2492 }
25163bd5
WS		 2493 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2494 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2495 if (rc)
2496 goto out;
316b221a
SC		 2497 ei = c->err_info;
2498 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2499 hpsa_scsi_interpret_error(h, c);
2500 rc = -1;
2501 }
2502out:
45fcb86e 2503 cmd_free(h, c);
316b221a
SC		 2504 return rc;
2505 }
2506
bf711ac6 2507static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2508 u8 reset_type, int reply_queue)
edd16368
SC		 2509{
2510 int rc = IO_OK;
2511 struct CommandList *c;
2512 struct ErrorInfo *ei;
2513
45fcb86e 2514 c = cmd_alloc(h);
edd16368
SC		 2515
2516 if (c == NULL) { /* trouble... */
45fcb86e 2517 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
e9ea04a6 2518 return -ENOMEM;
edd16368
SC		 2519 }
2520
a2dac136 2521 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2522 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2523 scsi3addr, TYPE_MSG);
2524 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
25163bd5
WS		 2525 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2526 if (rc) {
2527 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2528 goto out;
2529 }
edd16368
SC		 2530 /* no unmap needed here because no data xfer. */
2531
2532 ei = c->err_info;
2533 if (ei->CommandStatus != 0) {
d1e8beac 2534 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2535 rc = -1;
2536 }
25163bd5 2537out:
45fcb86e 2538 cmd_free(h, c);
edd16368
SC		 2539 return rc;
2540}
2541
2542static void hpsa_get_raid_level(struct ctlr_info *h,
2543 unsigned char *scsi3addr, unsigned char *raid_level)
2544{
2545 int rc;
2546 unsigned char *buf;
2547
2548 *raid_level = RAID_UNKNOWN;
2549 buf = kzalloc(64, GFP_KERNEL);
2550 if (!buf)
2551 return;
b7bb24eb 2552 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2553 if (rc == 0)
2554 *raid_level = buf[8];
2555 if (*raid_level > RAID_UNKNOWN)
2556 *raid_level = RAID_UNKNOWN;
2557 kfree(buf);
2558 return;
2559}
2560
283b4a9b
SC		 2561#define HPSA_MAP_DEBUG
2562#ifdef HPSA_MAP_DEBUG
2563static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2564 struct raid_map_data *map_buff)
2565{
2566 struct raid_map_disk_data *dd = &map_buff->data[0];
2567 int map, row, col;
2568 u16 map_cnt, row_cnt, disks_per_row;
2569
2570 if (rc != 0)
2571 return;
2572
2ba8bfc8
SC		 2573 /* Show details only if debugging has been activated. */
2574 if (h->raid_offload_debug < 2)
2575 return;
2576
283b4a9b
SC		 2577 dev_info(&h->pdev->dev, "structure_size = %u\n",
2578 le32_to_cpu(map_buff->structure_size));
2579 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2580 le32_to_cpu(map_buff->volume_blk_size));
2581 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2582 le64_to_cpu(map_buff->volume_blk_cnt));
2583 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2584 map_buff->phys_blk_shift);
2585 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2586 map_buff->parity_rotation_shift);
2587 dev_info(&h->pdev->dev, "strip_size = %u\n",
2588 le16_to_cpu(map_buff->strip_size));
2589 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2590 le64_to_cpu(map_buff->disk_starting_blk));
2591 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2592 le64_to_cpu(map_buff->disk_blk_cnt));
2593 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2594 le16_to_cpu(map_buff->data_disks_per_row));
2595 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2596 le16_to_cpu(map_buff->metadata_disks_per_row));
2597 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2598 le16_to_cpu(map_buff->row_cnt));
2599 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2600 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2601 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2602 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2603 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2604 le16_to_cpu(map_buff->flags) &
2605 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2606 dev_info(&h->pdev->dev, "dekindex = %u\n",
2607 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2608 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2609 for (map = 0; map < map_cnt; map++) {
2610 dev_info(&h->pdev->dev, "Map%u:\n", map);
2611 row_cnt = le16_to_cpu(map_buff->row_cnt);
2612 for (row = 0; row < row_cnt; row++) {
2613 dev_info(&h->pdev->dev, " Row%u:\n", row);
2614 disks_per_row =
2615 le16_to_cpu(map_buff->data_disks_per_row);
2616 for (col = 0; col < disks_per_row; col++, dd++)
2617 dev_info(&h->pdev->dev,
2618 " D%02u: h=0x%04x xor=%u,%u\n",
2619 col, dd->ioaccel_handle,
2620 dd->xor_mult[0], dd->xor_mult[1]);
2621 disks_per_row =
2622 le16_to_cpu(map_buff->metadata_disks_per_row);
2623 for (col = 0; col < disks_per_row; col++, dd++)
2624 dev_info(&h->pdev->dev,
2625 " M%02u: h=0x%04x xor=%u,%u\n",
2626 col, dd->ioaccel_handle,
2627 dd->xor_mult[0], dd->xor_mult[1]);
2628 }
2629 }
2630}
2631#else
2632static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2633 __attribute__((unused)) int rc,
2634 __attribute__((unused)) struct raid_map_data *map_buff)
2635{
2636}
2637#endif
2638
2639static int hpsa_get_raid_map(struct ctlr_info *h,
2640 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2641{
2642 int rc = 0;
2643 struct CommandList *c;
2644 struct ErrorInfo *ei;
2645
45fcb86e 2646 c = cmd_alloc(h);
283b4a9b 2647 if (c == NULL) {
45fcb86e 2648 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
283b4a9b
SC		 2649 return -ENOMEM;
2650 }
2651 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2652 sizeof(this_device->raid_map), 0,
2653 scsi3addr, TYPE_CMD)) {
2654 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
25163bd5
WS		 2655 rc = -ENOMEM;
2656 goto out;
283b4a9b 2657 }
25163bd5
WS		 2658 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2659 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2660 if (rc)
2661 goto out;
283b4a9b
SC		 2662 ei = c->err_info;
2663 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2664 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 2665 rc = -1;
2666 goto out;
283b4a9b 2667 }
45fcb86e 2668 cmd_free(h, c);
283b4a9b
SC		 2669
2670 /* @todo in the future, dynamically allocate RAID map memory */
2671 if (le32_to_cpu(this_device->raid_map.structure_size) >
2672 sizeof(this_device->raid_map)) {
2673 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2674 rc = -1;
2675 }
2676 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2677 return rc;
25163bd5
WS		 2678out:
2679 cmd_free(h, c);
2680 return rc;
283b4a9b
SC		 2681}
2682
03383736
DB		 2683static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
2684 unsigned char scsi3addr[], u16 bmic_device_index,
2685 struct bmic_identify_physical_device *buf, size_t bufsize)
2686{
2687 int rc = IO_OK;
2688 struct CommandList *c;
2689 struct ErrorInfo *ei;
2690
2691 c = cmd_alloc(h);
2692 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
2693 0, RAID_CTLR_LUNID, TYPE_CMD);
2694 if (rc)
2695 goto out;
2696
2697 c->Request.CDB[2] = bmic_device_index & 0xff;
2698 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
2699
25163bd5
WS		 2700 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
2701 NO_TIMEOUT);
03383736
DB		 2702 ei = c->err_info;
2703 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2704 hpsa_scsi_interpret_error(h, c);
2705 rc = -1;
2706 }
2707out:
2708 cmd_free(h, c);
2709 return rc;
2710}
2711
1b70150a
SC		 2712static int hpsa_vpd_page_supported(struct ctlr_info *h,
2713 unsigned char scsi3addr[], u8 page)
2714{
2715 int rc;
2716 int i;
2717 int pages;
2718 unsigned char *buf, bufsize;
2719
2720 buf = kzalloc(256, GFP_KERNEL);
2721 if (!buf)
2722 return 0;
2723
2724 /* Get the size of the page list first */
2725 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2726 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2727 buf, HPSA_VPD_HEADER_SZ);
2728 if (rc != 0)
2729 goto exit_unsupported;
2730 pages = buf[3];
2731 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2732 bufsize = pages + HPSA_VPD_HEADER_SZ;
2733 else
2734 bufsize = 255;
2735
2736 /* Get the whole VPD page list */
2737 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2738 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2739 buf, bufsize);
2740 if (rc != 0)
2741 goto exit_unsupported;
2742
2743 pages = buf[3];
2744 for (i = 1; i <= pages; i++)
2745 if (buf[3 + i] == page)
2746 goto exit_supported;
2747exit_unsupported:
2748 kfree(buf);
2749 return 0;
2750exit_supported:
2751 kfree(buf);
2752 return 1;
2753}
2754
283b4a9b
SC		 2755static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2756 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2757{
2758 int rc;
2759 unsigned char *buf;
2760 u8 ioaccel_status;
2761
2762 this_device->offload_config = 0;
2763 this_device->offload_enabled = 0;
41ce4c35 2764 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 2765
2766 buf = kzalloc(64, GFP_KERNEL);
2767 if (!buf)
2768 return;
1b70150a
SC		 2769 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2770 goto out;
283b4a9b 2771 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2772 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2773 if (rc != 0)
2774 goto out;
2775
2776#define IOACCEL_STATUS_BYTE 4
2777#define OFFLOAD_CONFIGURED_BIT 0x01
2778#define OFFLOAD_ENABLED_BIT 0x02
2779 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2780 this_device->offload_config =
2781 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2782 if (this_device->offload_config) {
2783 this_device->offload_enabled =
2784 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2785 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2786 this_device->offload_enabled = 0;
2787 }
41ce4c35 2788 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 2789out:
2790 kfree(buf);
2791 return;
2792}
2793
edd16368
SC		 2794/* Get the device id from inquiry page 0x83 */
2795static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2796 unsigned char *device_id, int buflen)
2797{
2798 int rc;
2799 unsigned char *buf;
2800
2801 if (buflen > 16)
2802 buflen = 16;
2803 buf = kzalloc(64, GFP_KERNEL);
2804 if (!buf)
a84d794d 2805 return -ENOMEM;
b7bb24eb 2806 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2807 if (rc == 0)
2808 memcpy(device_id, &buf[8], buflen);
2809 kfree(buf);
2810 return rc != 0;
2811}
2812
2813static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 2814 void *buf, int bufsize,
edd16368
SC		 2815 int extended_response)
2816{
2817 int rc = IO_OK;
2818 struct CommandList *c;
2819 unsigned char scsi3addr[8];
2820 struct ErrorInfo *ei;
2821
45fcb86e 2822 c = cmd_alloc(h);
edd16368 2823 if (c == NULL) { /* trouble... */
45fcb86e 2824 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 2825 return -1;
2826 }
e89c0ae7
SC		 2827 /* address the controller */
2828 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2829 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2830 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2831 rc = -1;
2832 goto out;
2833 }
edd16368
SC		 2834 if (extended_response)
2835 c->Request.CDB[1] = extended_response;
25163bd5
WS		 2836 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2837 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2838 if (rc)
2839 goto out;
edd16368
SC		 2840 ei = c->err_info;
2841 if (ei->CommandStatus != 0 &&
2842 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2843 hpsa_scsi_interpret_error(h, c);
edd16368 2844 rc = -1;
283b4a9b 2845 } else {
03383736
DB		 2846 struct ReportLUNdata *rld = buf;
2847
2848 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 2849 dev_err(&h->pdev->dev,
2850 "report luns requested format %u, got %u\n",
2851 extended_response,
03383736 2852 rld->extended_response_flag);
283b4a9b
SC		 2853 rc = -1;
2854 }
edd16368 2855 }
a2dac136 2856out:
45fcb86e 2857 cmd_free(h, c);
edd16368
SC		 2858 return rc;
2859}
2860
2861static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 2862 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 2863{
03383736
DB		 2864 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
2865 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 2866}
2867
2868static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2869 struct ReportLUNdata *buf, int bufsize)
2870{
2871 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2872}
2873
2874static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2875 int bus, int target, int lun)
2876{
2877 device->bus = bus;
2878 device->target = target;
2879 device->lun = lun;
2880}
2881
9846590e
SC		 2882/* Use VPD inquiry to get details of volume status */
2883static int hpsa_get_volume_status(struct ctlr_info *h,
2884 unsigned char scsi3addr[])
2885{
2886 int rc;
2887 int status;
2888 int size;
2889 unsigned char *buf;
2890
2891 buf = kzalloc(64, GFP_KERNEL);
2892 if (!buf)
2893 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2894
2895 /* Does controller have VPD for logical volume status? */
24a4b078 2896 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 2897 goto exit_failed;
9846590e
SC		 2898
2899 /* Get the size of the VPD return buffer */
2900 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2901 buf, HPSA_VPD_HEADER_SZ);
24a4b078 2902 if (rc != 0)
9846590e 2903 goto exit_failed;
9846590e
SC		 2904 size = buf[3];
2905
2906 /* Now get the whole VPD buffer */
2907 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
2908 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 2909 if (rc != 0)
9846590e 2910 goto exit_failed;
9846590e
SC		 2911 status = buf[4]; /* status byte */
2912
2913 kfree(buf);
2914 return status;
2915exit_failed:
2916 kfree(buf);
2917 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
2918}
2919
2920/* Determine offline status of a volume.
2921 * Return either:
2922 * 0 (not offline)
67955ba3 2923 * 0xff (offline for unknown reasons)
9846590e
SC		 2924 * # (integer code indicating one of several NOT READY states
2925 * describing why a volume is to be kept offline)
2926 */
67955ba3 2927static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 2928 unsigned char scsi3addr[])
2929{
2930 struct CommandList *c;
9437ac43
SC		 2931 unsigned char *sense;
2932 u8 sense_key, asc, ascq;
2933 int sense_len;
25163bd5 2934 int rc, ldstat = 0;
9846590e
SC		 2935 u16 cmd_status;
2936 u8 scsi_status;
2937#define ASC_LUN_NOT_READY 0x04
2938#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
2939#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
2940
2941 c = cmd_alloc(h);
2942 if (!c)
2943 return 0;
2944 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 2945 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
2946 if (rc) {
2947 cmd_free(h, c);
2948 return 0;
2949 }
9846590e 2950 sense = c->err_info->SenseInfo;
9437ac43
SC		 2951 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
2952 sense_len = sizeof(c->err_info->SenseInfo);
2953 else
2954 sense_len = c->err_info->SenseLen;
2955 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 2956 cmd_status = c->err_info->CommandStatus;
2957 scsi_status = c->err_info->ScsiStatus;
2958 cmd_free(h, c);
2959 /* Is the volume 'not ready'? */
2960 if (cmd_status != CMD_TARGET_STATUS ||
2961 scsi_status != SAM_STAT_CHECK_CONDITION ||
2962 sense_key != NOT_READY ||
2963 asc != ASC_LUN_NOT_READY) {
2964 return 0;
2965 }
2966
2967 /* Determine the reason for not ready state */
2968 ldstat = hpsa_get_volume_status(h, scsi3addr);
2969
2970 /* Keep volume offline in certain cases: */
2971 switch (ldstat) {
2972 case HPSA_LV_UNDERGOING_ERASE:
2973 case HPSA_LV_UNDERGOING_RPI:
2974 case HPSA_LV_PENDING_RPI:
2975 case HPSA_LV_ENCRYPTED_NO_KEY:
2976 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
2977 case HPSA_LV_UNDERGOING_ENCRYPTION:
2978 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
2979 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
2980 return ldstat;
2981 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
2982 /* If VPD status page isn't available,
2983 * use ASC/ASCQ to determine state
2984 */
2985 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
2986 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
2987 return ldstat;
2988 break;
2989 default:
2990 break;
2991 }
2992 return 0;
2993}
2994
9b5c48c2
SC		 2995/*
2996 * Find out if a logical device supports aborts by simply trying one.
2997 * Smart Array may claim not to support aborts on logical drives, but
2998 * if a MSA2000 * is connected, the drives on that will be presented
2999 * by the Smart Array as logical drives, and aborts may be sent to
3000 * those devices successfully. So the simplest way to find out is
3001 * to simply try an abort and see how the device responds.
3002 */
3003static int hpsa_device_supports_aborts(struct ctlr_info *h,
3004 unsigned char *scsi3addr)
3005{
3006 struct CommandList *c;
3007 struct ErrorInfo *ei;
3008 int rc = 0;
3009
3010 u64 tag = (u64) -1; /* bogus tag */
3011
3012 /* Assume that physical devices support aborts */
3013 if (!is_logical_dev_addr_mode(scsi3addr))
3014 return 1;
3015
3016 c = cmd_alloc(h);
3017 if (!c)
3018 return -ENOMEM;
3019 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3020 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3021 /* no unmap needed here because no data xfer. */
3022 ei = c->err_info;
3023 switch (ei->CommandStatus) {
3024 case CMD_INVALID:
3025 rc = 0;
3026 break;
3027 case CMD_UNABORTABLE:
3028 case CMD_ABORT_FAILED:
3029 rc = 1;
3030 break;
9437ac43
SC		 3031 case CMD_TMF_STATUS:
3032 rc = hpsa_evaluate_tmf_status(h, c);
3033 break;
9b5c48c2
SC		 3034 default:
3035 rc = 0;
3036 break;
3037 }
3038 cmd_free(h, c);
3039 return rc;
3040}
3041
edd16368 3042static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3043 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3044 unsigned char *is_OBDR_device)
edd16368 3045{
0b0e1d6c
SC		 3046
3047#define OBDR_SIG_OFFSET 43
3048#define OBDR_TAPE_SIG "$DR-10"
3049#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3050#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3051
ea6d3bc3 3052 unsigned char *inq_buff;
0b0e1d6c 3053 unsigned char *obdr_sig;
edd16368 3054
ea6d3bc3 3055 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 3056 if (!inq_buff)
3057 goto bail_out;
3058
edd16368
SC		 3059 /* Do an inquiry to the device to see what it is. */
3060 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3061 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3062 /* Inquiry failed (msg printed already) */
3063 dev_err(&h->pdev->dev,
3064 "hpsa_update_device_info: inquiry failed\n");
3065 goto bail_out;
3066 }
3067
edd16368
SC		 3068 this_device->devtype = (inq_buff[0] & 0x1f);
3069 memcpy(this_device->scsi3addr, scsi3addr, 8);
3070 memcpy(this_device->vendor, &inq_buff[8],
3071 sizeof(this_device->vendor));
3072 memcpy(this_device->model, &inq_buff[16],
3073 sizeof(this_device->model));
edd16368
SC		 3074 memset(this_device->device_id, 0,
3075 sizeof(this_device->device_id));
3076 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3077 sizeof(this_device->device_id));
3078
3079 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3080 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3081 int volume_offline;
3082
edd16368 3083 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3084 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3085 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3086 volume_offline = hpsa_volume_offline(h, scsi3addr);
3087 if (volume_offline < 0 || volume_offline > 0xff)
3088 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3089 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3090 } else {
edd16368 3091 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3092 this_device->offload_config = 0;
3093 this_device->offload_enabled = 0;
41ce4c35 3094 this_device->offload_to_be_enabled = 0;
a3144e0b 3095 this_device->hba_ioaccel_enabled = 0;
9846590e 3096 this_device->volume_offline = 0;
03383736 3097 this_device->queue_depth = h->nr_cmds;
283b4a9b 3098 }
edd16368 3099
0b0e1d6c
SC		 3100 if (is_OBDR_device) {
3101 /* See if this is a One-Button-Disaster-Recovery device
3102 * by looking for "$DR-10" at offset 43 in inquiry data.
3103 */
3104 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3105 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3106 strncmp(obdr_sig, OBDR_TAPE_SIG,
3107 OBDR_SIG_LEN) == 0);
3108 }
edd16368
SC		 3109 kfree(inq_buff);
3110 return 0;
3111
3112bail_out:
3113 kfree(inq_buff);
3114 return 1;
3115}
3116
9b5c48c2
SC		 3117static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3118 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3119{
3120 unsigned long flags;
3121 int rc, entry;
3122 /*
3123 * See if this device supports aborts. If we already know
3124 * the device, we already know if it supports aborts, otherwise
3125 * we have to find out if it supports aborts by trying one.
3126 */
3127 spin_lock_irqsave(&h->devlock, flags);
3128 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3129 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3130 entry >= 0 && entry < h->ndevices) {
3131 dev->supports_aborts = h->dev[entry]->supports_aborts;
3132 spin_unlock_irqrestore(&h->devlock, flags);
3133 } else {
3134 spin_unlock_irqrestore(&h->devlock, flags);
3135 dev->supports_aborts =
3136 hpsa_device_supports_aborts(h, scsi3addr);
3137 if (dev->supports_aborts < 0)
3138 dev->supports_aborts = 0;
3139 }
3140}
3141
4f4eb9f1 3142static unsigned char *ext_target_model[] = {
edd16368
SC		 3143 "MSA2012",
3144 "MSA2024",
3145 "MSA2312",
3146 "MSA2324",
fda38518 3147 "P2000 G3 SAS",
e06c8e5c 3148 "MSA 2040 SAS",
edd16368
SC		 3149 NULL,
3150};
3151
4f4eb9f1 3152static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3153{
3154 int i;
3155
4f4eb9f1
ST		 3156 for (i = 0; ext_target_model[i]; i++)
3157 if (strncmp(device->model, ext_target_model[i],
3158 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3159 return 1;
3160 return 0;
3161}
3162
3163/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3164 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3165 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3166 * Logical drive target and lun are assigned at this time, but
3167 * physical device lun and target assignment are deferred (assigned
3168 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3169 */
3170static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3171 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3172{
1f310bde
SC		 3173 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3174
3175 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3176 /* physical device, target and lun filled in later */
edd16368 3177 if (is_hba_lunid(lunaddrbytes))
1f310bde 3178 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3179 else
1f310bde
SC		 3180 /* defer target, lun assignment for physical devices */
3181 hpsa_set_bus_target_lun(device, 2, -1, -1);
3182 return;
3183 }
3184 /* It's a logical device */
4f4eb9f1
ST		 3185 if (is_ext_target(h, device)) {
3186 /* external target way, put logicals on bus 1
1f310bde
SC		 3187 * and match target/lun numbers box
3188 * reports, other smart array, bus 0, target 0, match lunid
3189 */
3190 hpsa_set_bus_target_lun(device,
3191 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3192 return;
edd16368 3193 }
1f310bde 3194 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3195}
3196
3197/*
3198 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3199 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3200 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3201 * it for some reason. *tmpdevice is the target we're adding,
3202 * this_device is a pointer into the current element of currentsd[]
3203 * that we're building up in update_scsi_devices(), below.
3204 * lunzerobits is a bitmap that tracks which targets already have a
3205 * lun 0 assigned.
3206 * Returns 1 if an enclosure was added, 0 if not.
3207 */
4f4eb9f1 3208static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3209 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3210 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3211 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3212{
3213 unsigned char scsi3addr[8];
3214
1f310bde 3215 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3216 return 0; /* There is already a lun 0 on this target. */
3217
3218 if (!is_logical_dev_addr_mode(lunaddrbytes))
3219 return 0; /* It's the logical targets that may lack lun 0. */
3220
4f4eb9f1
ST		 3221 if (!is_ext_target(h, tmpdevice))
3222 return 0; /* Only external target devices have this problem. */
edd16368 3223
1f310bde 3224 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3225 return 0;
3226
c4f8a299 3227 memset(scsi3addr, 0, 8);
1f310bde 3228 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3229 if (is_hba_lunid(scsi3addr))
3230 return 0; /* Don't add the RAID controller here. */
3231
339b2b14
SC		 3232 if (is_scsi_rev_5(h))
3233 return 0; /* p1210m doesn't need to do this. */
3234
4f4eb9f1 3235 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3236 dev_warn(&h->pdev->dev, "Maximum number of external "
3237 "target devices exceeded. Check your hardware "
edd16368
SC		 3238 "configuration.");
3239 return 0;
3240 }
3241
0b0e1d6c 3242 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3243 return 0;
4f4eb9f1 3244 (*n_ext_target_devs)++;
1f310bde
SC		 3245 hpsa_set_bus_target_lun(this_device,
3246 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3247 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3248 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3249 return 1;
3250}
3251
54b6e9e9
ST		 3252/*
3253 * Get address of physical disk used for an ioaccel2 mode command:
3254 * 1. Extract ioaccel2 handle from the command.
3255 * 2. Find a matching ioaccel2 handle from list of physical disks.
3256 * 3. Return:
3257 * 1 and set scsi3addr to address of matching physical
3258 * 0 if no matching physical disk was found.
3259 */
3260static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3261 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3262{
41ce4c35
SC		 3263 struct io_accel2_cmd *c2 =
3264 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3265 unsigned long flags;
54b6e9e9 3266 int i;
54b6e9e9 3267
41ce4c35
SC		 3268 spin_lock_irqsave(&h->devlock, flags);
3269 for (i = 0; i < h->ndevices; i++)
3270 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3271 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3272 sizeof(h->dev[i]->scsi3addr));
3273 spin_unlock_irqrestore(&h->devlock, flags);
3274 return 1;
3275 }
3276 spin_unlock_irqrestore(&h->devlock, flags);
3277 return 0;
54b6e9e9 3278}
41ce4c35 3279
edd16368
SC		 3280/*
3281 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3282 * logdev. The number of luns in physdev and logdev are returned in
3283 * *nphysicals and *nlogicals, respectively.
3284 * Returns 0 on success, -1 otherwise.
3285 */
3286static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3287 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3288 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3289{
03383736 3290 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3291 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3292 return -1;
3293 }
03383736 3294 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3295 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3296 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3297 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3298 *nphysicals = HPSA_MAX_PHYS_LUN;
3299 }
03383736 3300 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3301 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3302 return -1;
3303 }
6df1e954 3304 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3305 /* Reject Logicals in excess of our max capability. */
3306 if (*nlogicals > HPSA_MAX_LUN) {
3307 dev_warn(&h->pdev->dev,
3308 "maximum logical LUNs (%d) exceeded. "
3309 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3310 *nlogicals - HPSA_MAX_LUN);
3311 *nlogicals = HPSA_MAX_LUN;
3312 }
3313 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3314 dev_warn(&h->pdev->dev,
3315 "maximum logical + physical LUNs (%d) exceeded. "
3316 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3317 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3318 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3319 }
3320 return 0;
3321}
3322
42a91641
DB		 3323static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3324 int i, int nphysicals, int nlogicals,
a93aa1fe 3325 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3326 struct ReportLUNdata *logdev_list)
3327{
3328 /* Helper function, figure out where the LUN ID info is coming from
3329 * given index i, lists of physical and logical devices, where in
3330 * the list the raid controller is supposed to appear (first or last)
3331 */
3332
3333 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3334 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3335
3336 if (i == raid_ctlr_position)
3337 return RAID_CTLR_LUNID;
3338
3339 if (i < logicals_start)
d5b5d964
SC		 3340 return &physdev_list->LUN[i -
3341 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3342
3343 if (i < last_device)
3344 return &logdev_list->LUN[i - nphysicals -
3345 (raid_ctlr_position == 0)][0];
3346 BUG();
3347 return NULL;
3348}
3349
316b221a
SC		 3350static int hpsa_hba_mode_enabled(struct ctlr_info *h)
3351{
3352 int rc;
6e8e8088 3353 int hba_mode_enabled;
316b221a
SC		 3354 struct bmic_controller_parameters *ctlr_params;
3355 ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters),
3356 GFP_KERNEL);
3357
3358 if (!ctlr_params)
96444fbb 3359 return -ENOMEM;
316b221a
SC		 3360 rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params,
3361 sizeof(struct bmic_controller_parameters));
96444fbb 3362 if (rc) {
316b221a 3363 kfree(ctlr_params);
96444fbb 3364 return rc;
316b221a 3365 }
6e8e8088
JH		 3366
3367 hba_mode_enabled =
3368 ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0);
3369 kfree(ctlr_params);
3370 return hba_mode_enabled;
316b221a
SC		 3371}
3372
03383736
DB		 3373/* get physical drive ioaccel handle and queue depth */
3374static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3375 struct hpsa_scsi_dev_t *dev,
3376 u8 *lunaddrbytes,
3377 struct bmic_identify_physical_device *id_phys)
3378{
3379 int rc;
3380 struct ext_report_lun_entry *rle =
3381 (struct ext_report_lun_entry *) lunaddrbytes;
3382
3383 dev->ioaccel_handle = rle->ioaccel_handle;
a3144e0b
JH		 3384 if (PHYS_IOACCEL(lunaddrbytes) && dev->ioaccel_handle)
3385 dev->hba_ioaccel_enabled = 1;
03383736
DB		 3386 memset(id_phys, 0, sizeof(*id_phys));
3387 rc = hpsa_bmic_id_physical_device(h, lunaddrbytes,
3388 GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys,
3389 sizeof(*id_phys));
3390 if (!rc)
3391 /* Reserve space for FW operations */
3392#define DRIVE_CMDS_RESERVED_FOR_FW 2
3393#define DRIVE_QUEUE_DEPTH 7
3394 dev->queue_depth =
3395 le16_to_cpu(id_phys->current_queue_depth_limit) -
3396 DRIVE_CMDS_RESERVED_FOR_FW;
3397 else
3398 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
3399 atomic_set(&dev->ioaccel_cmds_out, 0);
3400}
3401
edd16368
SC		 3402static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
3403{
3404 /* the idea here is we could get notified
3405 * that some devices have changed, so we do a report
3406 * physical luns and report logical luns cmd, and adjust
3407 * our list of devices accordingly.
3408 *
3409 * The scsi3addr's of devices won't change so long as the
3410 * adapter is not reset. That means we can rescan and
3411 * tell which devices we already know about, vs. new
3412 * devices, vs. disappearing devices.
3413 */
a93aa1fe 3414 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3415 struct ReportLUNdata *logdev_list = NULL;
03383736 3416 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3417 u32 nphysicals = 0;
3418 u32 nlogicals = 0;
3419 u32 ndev_allocated = 0;
edd16368
SC		 3420 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3421 int ncurrent = 0;
4f4eb9f1 3422 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3423 int raid_ctlr_position;
2bbf5c7f 3424 int rescan_hba_mode;
aca4a520 3425 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3426
cfe5badc 3427 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3428 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3429 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3430 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3431 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3432
03383736
DB		 3433 if (!currentsd || !physdev_list || !logdev_list ||
3434 !tmpdevice || !id_phys) {
edd16368
SC		 3435 dev_err(&h->pdev->dev, "out of memory\n");
3436 goto out;
3437 }
3438 memset(lunzerobits, 0, sizeof(lunzerobits));
3439
316b221a 3440 rescan_hba_mode = hpsa_hba_mode_enabled(h);
96444fbb
JH		 3441 if (rescan_hba_mode < 0)
3442 goto out;
316b221a
SC		 3443
3444 if (!h->hba_mode_enabled && rescan_hba_mode)
3445 dev_warn(&h->pdev->dev, "HBA mode enabled\n");
3446 else if (h->hba_mode_enabled && !rescan_hba_mode)
3447 dev_warn(&h->pdev->dev, "HBA mode disabled\n");
3448
3449 h->hba_mode_enabled = rescan_hba_mode;
3450
03383736
DB		 3451 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
3452 logdev_list, &nlogicals))
edd16368
SC		 3453 goto out;
3454
aca4a520
ST		 3455 /* We might see up to the maximum number of logical and physical disks
3456 * plus external target devices, and a device for the local RAID
3457 * controller.
edd16368 3458 */
aca4a520 3459 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3460
3461 /* Allocate the per device structures */
3462 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3463 if (i >= HPSA_MAX_DEVICES) {
3464 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3465 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3466 ndevs_to_allocate - HPSA_MAX_DEVICES);
3467 break;
3468 }
3469
edd16368
SC		 3470 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3471 if (!currentsd[i]) {
3472 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3473 __FILE__, __LINE__);
3474 goto out;
3475 }
3476 ndev_allocated++;
3477 }
3478
8645291b 3479 if (is_scsi_rev_5(h))
339b2b14
SC		 3480 raid_ctlr_position = 0;
3481 else
3482 raid_ctlr_position = nphysicals + nlogicals;
3483
edd16368 3484 /* adjust our table of devices */
4f4eb9f1 3485 n_ext_target_devs = 0;
edd16368 3486 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3487 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 3488
3489 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3490 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3491 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3492
3493 /* skip masked non-disk devices */
3494 if (MASKED_DEVICE(lunaddrbytes))
3495 if (i < nphysicals + (raid_ctlr_position == 0) &&
3496 NON_DISK_PHYS_DEV(lunaddrbytes))
3497 continue;
edd16368
SC		 3498
3499 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 3500 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3501 &is_OBDR))
edd16368 3502 continue; /* skip it if we can't talk to it. */
1f310bde 3503 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3504 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3505 this_device = currentsd[ncurrent];
3506
3507 /*
4f4eb9f1 3508 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3509 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3510 * is nonetheless an enclosure device there. We have to
3511 * present that otherwise linux won't find anything if
3512 * there is no lun 0.
3513 */
4f4eb9f1 3514 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3515 lunaddrbytes, lunzerobits,
4f4eb9f1 3516 &n_ext_target_devs)) {
edd16368
SC		 3517 ncurrent++;
3518 this_device = currentsd[ncurrent];
3519 }
3520
3521 *this_device = *tmpdevice;
edd16368 3522
41ce4c35
SC		 3523 /* do not expose masked devices */
3524 if (MASKED_DEVICE(lunaddrbytes) &&
3525 i < nphysicals + (raid_ctlr_position == 0)) {
3526 if (h->hba_mode_enabled)
3527 dev_warn(&h->pdev->dev,
3528 "Masked physical device detected\n");
3529 this_device->expose_state = HPSA_DO_NOT_EXPOSE;
3530 } else {
3531 this_device->expose_state =
3532 HPSA_SG_ATTACH | HPSA_ULD_ATTACH;
3533 }
3534
edd16368 3535 switch (this_device->devtype) {
0b0e1d6c 3536 case TYPE_ROM:
edd16368
SC		 3537 /* We don't *really* support actual CD-ROM devices,
3538 * just "One Button Disaster Recovery" tape drive
3539 * which temporarily pretends to be a CD-ROM drive.
3540 * So we check that the device is really an OBDR tape
3541 * device by checking for "$DR-10" in bytes 43-48 of
3542 * the inquiry data.
3543 */
0b0e1d6c
SC		 3544 if (is_OBDR)
3545 ncurrent++;
edd16368
SC		 3546 break;
3547 case TYPE_DISK:
ecf418d1 3548 if (i >= nphysicals) {
316b221a
SC		 3549 ncurrent++;
3550 break;
283b4a9b 3551 }
ecf418d1
JH		 3552
3553 if (h->hba_mode_enabled)
3554 /* never use raid mapper in HBA mode */
3555 this_device->offload_enabled = 0;
3556 else if (!(h->transMethod & CFGTBL_Trans_io_accel1 ||
3557 h->transMethod & CFGTBL_Trans_io_accel2))
3558 break;
3559
3560 hpsa_get_ioaccel_drive_info(h, this_device,
3561 lunaddrbytes, id_phys);
3562 atomic_set(&this_device->ioaccel_cmds_out, 0);
3563 ncurrent++;
edd16368
SC		 3564 break;
3565 case TYPE_TAPE:
3566 case TYPE_MEDIUM_CHANGER:
3567 ncurrent++;
3568 break;
41ce4c35
SC		 3569 case TYPE_ENCLOSURE:
3570 if (h->hba_mode_enabled)
3571 ncurrent++;
3572 break;
edd16368
SC		 3573 case TYPE_RAID:
3574 /* Only present the Smartarray HBA as a RAID controller.
3575 * If it's a RAID controller other than the HBA itself
3576 * (an external RAID controller, MSA500 or similar)
3577 * don't present it.
3578 */
3579 if (!is_hba_lunid(lunaddrbytes))
3580 break;
3581 ncurrent++;
3582 break;
3583 default:
3584 break;
3585 }
cfe5badc 3586 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3587 break;
3588 }
3589 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
3590out:
3591 kfree(tmpdevice);
3592 for (i = 0; i < ndev_allocated; i++)
3593 kfree(currentsd[i]);
3594 kfree(currentsd);
edd16368
SC		 3595 kfree(physdev_list);
3596 kfree(logdev_list);
03383736 3597 kfree(id_phys);
edd16368
SC		 3598}
3599
ec5cbf04
WS		 3600static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3601 struct scatterlist *sg)
3602{
3603 u64 addr64 = (u64) sg_dma_address(sg);
3604 unsigned int len = sg_dma_len(sg);
3605
3606 desc->Addr = cpu_to_le64(addr64);
3607 desc->Len = cpu_to_le32(len);
3608 desc->Ext = 0;
3609}
3610
c7ee65b3
WS		 3611/*
3612 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3613 * dma mapping and fills in the scatter gather entries of the
3614 * hpsa command, cp.
3615 */
33a2ffce 3616static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3617 struct CommandList *cp,
3618 struct scsi_cmnd *cmd)
3619{
edd16368 3620 struct scatterlist *sg;
33a2ffce
SC		 3621 int use_sg, i, sg_index, chained;
3622 struct SGDescriptor *curr_sg;
edd16368 3623
33a2ffce 3624 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3625
3626 use_sg = scsi_dma_map(cmd);
3627 if (use_sg < 0)
3628 return use_sg;
3629
3630 if (!use_sg)
3631 goto sglist_finished;
3632
33a2ffce
SC		 3633 curr_sg = cp->SG;
3634 chained = 0;
3635 sg_index = 0;
edd16368 3636 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 3637 if (i == h->max_cmd_sg_entries - 1 &&
3638 use_sg > h->max_cmd_sg_entries) {
3639 chained = 1;
3640 curr_sg = h->cmd_sg_list[cp->cmdindex];
3641 sg_index = 0;
3642 }
ec5cbf04 3643 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3644 curr_sg++;
3645 }
ec5cbf04
WS		 3646
3647 /* Back the pointer up to the last entry and mark it as "last". */
50a0decf 3648 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3649
3650 if (use_sg + chained > h->maxSG)
3651 h->maxSG = use_sg + chained;
3652
3653 if (chained) {
3654 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 3655 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 3656 if (hpsa_map_sg_chain_block(h, cp)) {
3657 scsi_dma_unmap(cmd);
3658 return -1;
3659 }
33a2ffce 3660 return 0;
edd16368
SC		 3661 }
3662
3663sglist_finished:
3664
01a02ffc 3665 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 3666 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 3667 return 0;
3668}
3669
283b4a9b
SC		 3670#define IO_ACCEL_INELIGIBLE (1)
3671static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
3672{
3673 int is_write = 0;
3674 u32 block;
3675 u32 block_cnt;
3676
3677 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
3678 switch (cdb[0]) {
3679 case WRITE_6:
3680 case WRITE_12:
3681 is_write = 1;
3682 case READ_6:
3683 case READ_12:
3684 if (*cdb_len == 6) {
3685 block = (((u32) cdb[2]) << 8) | cdb[3];
3686 block_cnt = cdb[4];
3687 } else {
3688 BUG_ON(*cdb_len != 12);
3689 block = (((u32) cdb[2]) << 24) |
3690 (((u32) cdb[3]) << 16) |
3691 (((u32) cdb[4]) << 8) |
3692 cdb[5];
3693 block_cnt =
3694 (((u32) cdb[6]) << 24) |
3695 (((u32) cdb[7]) << 16) |
3696 (((u32) cdb[8]) << 8) |
3697 cdb[9];
3698 }
3699 if (block_cnt > 0xffff)
3700 return IO_ACCEL_INELIGIBLE;
3701
3702 cdb[0] = is_write ? WRITE_10 : READ_10;
3703 cdb[1] = 0;
3704 cdb[2] = (u8) (block >> 24);
3705 cdb[3] = (u8) (block >> 16);
3706 cdb[4] = (u8) (block >> 8);
3707 cdb[5] = (u8) (block);
3708 cdb[6] = 0;
3709 cdb[7] = (u8) (block_cnt >> 8);
3710 cdb[8] = (u8) (block_cnt);
3711 cdb[9] = 0;
3712 *cdb_len = 10;
3713 break;
3714 }
3715 return 0;
3716}
3717
c349775e 3718static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 3719 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3720 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 3721{
3722 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 3723 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
3724 unsigned int len;
3725 unsigned int total_len = 0;
3726 struct scatterlist *sg;
3727 u64 addr64;
3728 int use_sg, i;
3729 struct SGDescriptor *curr_sg;
3730 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
3731
283b4a9b 3732 /* TODO: implement chaining support */
03383736
DB		 3733 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
3734 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3735 return IO_ACCEL_INELIGIBLE;
03383736 3736 }
283b4a9b 3737
e1f7de0c
MG		 3738 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
3739
03383736
DB		 3740 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3741 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 3742 return IO_ACCEL_INELIGIBLE;
03383736 3743 }
283b4a9b 3744
e1f7de0c
MG		 3745 c->cmd_type = CMD_IOACCEL1;
3746
3747 /* Adjust the DMA address to point to the accelerated command buffer */
3748 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
3749 (c->cmdindex * sizeof(*cp));
3750 BUG_ON(c->busaddr & 0x0000007F);
3751
3752 use_sg = scsi_dma_map(cmd);
03383736
DB		 3753 if (use_sg < 0) {
3754 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 3755 return use_sg;
03383736 3756 }
e1f7de0c
MG		 3757
3758 if (use_sg) {
3759 curr_sg = cp->SG;
3760 scsi_for_each_sg(cmd, sg, use_sg, i) {
3761 addr64 = (u64) sg_dma_address(sg);
3762 len = sg_dma_len(sg);
3763 total_len += len;
50a0decf
SC		 3764 curr_sg->Addr = cpu_to_le64(addr64);
3765 curr_sg->Len = cpu_to_le32(len);
3766 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 3767 curr_sg++;
3768 }
50a0decf 3769 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 3770
3771 switch (cmd->sc_data_direction) {
3772 case DMA_TO_DEVICE:
3773 control |= IOACCEL1_CONTROL_DATA_OUT;
3774 break;
3775 case DMA_FROM_DEVICE:
3776 control |= IOACCEL1_CONTROL_DATA_IN;
3777 break;
3778 case DMA_NONE:
3779 control |= IOACCEL1_CONTROL_NODATAXFER;
3780 break;
3781 default:
3782 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3783 cmd->sc_data_direction);
3784 BUG();
3785 break;
3786 }
3787 } else {
3788 control |= IOACCEL1_CONTROL_NODATAXFER;
3789 }
3790
c349775e 3791 c->Header.SGList = use_sg;
e1f7de0c 3792 /* Fill out the command structure to submit */
2b08b3e9
DB		 3793 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
3794 cp->transfer_len = cpu_to_le32(total_len);
3795 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
3796 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
3797 cp->control = cpu_to_le32(control);
283b4a9b
SC		 3798 memcpy(cp->CDB, cdb, cdb_len);
3799 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3800 /* Tag was already set at init time. */
283b4a9b 3801 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3802 return 0;
3803}
edd16368 3804
283b4a9b
SC		 3805/*
3806 * Queue a command directly to a device behind the controller using the
3807 * I/O accelerator path.
3808 */
3809static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3810 struct CommandList *c)
3811{
3812 struct scsi_cmnd *cmd = c->scsi_cmd;
3813 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3814
03383736
DB		 3815 c->phys_disk = dev;
3816
283b4a9b 3817 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 3818 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 3819}
3820
dd0e19f3
ST		 3821/*
3822 * Set encryption parameters for the ioaccel2 request
3823 */
3824static void set_encrypt_ioaccel2(struct ctlr_info *h,
3825 struct CommandList *c, struct io_accel2_cmd *cp)
3826{
3827 struct scsi_cmnd *cmd = c->scsi_cmd;
3828 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3829 struct raid_map_data *map = &dev->raid_map;
3830 u64 first_block;
3831
dd0e19f3 3832 /* Are we doing encryption on this device */
2b08b3e9 3833 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 3834 return;
3835 /* Set the data encryption key index. */
3836 cp->dekindex = map->dekindex;
3837
3838 /* Set the encryption enable flag, encoded into direction field. */
3839 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3840
3841 /* Set encryption tweak values based on logical block address
3842 * If block size is 512, tweak value is LBA.
3843 * For other block sizes, tweak is (LBA * block size)/ 512)
3844 */
3845 switch (cmd->cmnd[0]) {
3846 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3847 case WRITE_6:
3848 case READ_6:
2b08b3e9 3849 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 3850 break;
3851 case WRITE_10:
3852 case READ_10:
dd0e19f3
ST		 3853 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3854 case WRITE_12:
3855 case READ_12:
2b08b3e9 3856 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 3857 break;
3858 case WRITE_16:
3859 case READ_16:
2b08b3e9 3860 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 3861 break;
3862 default:
3863 dev_err(&h->pdev->dev,
2b08b3e9
DB		 3864 "ERROR: %s: size (0x%x) not supported for encryption\n",
3865 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 3866 BUG();
3867 break;
3868 }
2b08b3e9
DB		 3869
3870 if (le32_to_cpu(map->volume_blk_size) != 512)
3871 first_block = first_block *
3872 le32_to_cpu(map->volume_blk_size)/512;
3873
3874 cp->tweak_lower = cpu_to_le32(first_block);
3875 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 3876}
3877
c349775e
ST		 3878static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3879 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3880 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 3881{
3882 struct scsi_cmnd *cmd = c->scsi_cmd;
3883 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3884 struct ioaccel2_sg_element *curr_sg;
3885 int use_sg, i;
3886 struct scatterlist *sg;
3887 u64 addr64;
3888 u32 len;
3889 u32 total_len = 0;
3890
d9a729f3 3891 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 3892
03383736
DB		 3893 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
3894 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3895 return IO_ACCEL_INELIGIBLE;
03383736
DB		 3896 }
3897
c349775e
ST		 3898 c->cmd_type = CMD_IOACCEL2;
3899 /* Adjust the DMA address to point to the accelerated command buffer */
3900 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3901 (c->cmdindex * sizeof(*cp));
3902 BUG_ON(c->busaddr & 0x0000007F);
3903
3904 memset(cp, 0, sizeof(*cp));
3905 cp->IU_type = IOACCEL2_IU_TYPE;
3906
3907 use_sg = scsi_dma_map(cmd);
03383736
DB		 3908 if (use_sg < 0) {
3909 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 3910 return use_sg;
03383736 3911 }
c349775e
ST		 3912
3913 if (use_sg) {
c349775e 3914 curr_sg = cp->sg;
d9a729f3
WS		 3915 if (use_sg > h->ioaccel_maxsg) {
3916 addr64 = le64_to_cpu(
3917 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
3918 curr_sg->address = cpu_to_le64(addr64);
3919 curr_sg->length = 0;
3920 curr_sg->reserved[0] = 0;
3921 curr_sg->reserved[1] = 0;
3922 curr_sg->reserved[2] = 0;
3923 curr_sg->chain_indicator = 0x80;
3924
3925 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
3926 }
c349775e
ST		 3927 scsi_for_each_sg(cmd, sg, use_sg, i) {
3928 addr64 = (u64) sg_dma_address(sg);
3929 len = sg_dma_len(sg);
3930 total_len += len;
3931 curr_sg->address = cpu_to_le64(addr64);
3932 curr_sg->length = cpu_to_le32(len);
3933 curr_sg->reserved[0] = 0;
3934 curr_sg->reserved[1] = 0;
3935 curr_sg->reserved[2] = 0;
3936 curr_sg->chain_indicator = 0;
3937 curr_sg++;
3938 }
3939
3940 switch (cmd->sc_data_direction) {
3941 case DMA_TO_DEVICE:
dd0e19f3
ST		 3942 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3943 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3944 break;
3945 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3946 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3947 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3948 break;
3949 case DMA_NONE:
dd0e19f3
ST		 3950 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3951 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3952 break;
3953 default:
3954 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3955 cmd->sc_data_direction);
3956 BUG();
3957 break;
3958 }
3959 } else {
dd0e19f3
ST		 3960 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3961 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3962 }
dd0e19f3
ST		 3963
3964 /* Set encryption parameters, if necessary */
3965 set_encrypt_ioaccel2(h, c, cp);
3966
2b08b3e9 3967 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 3968 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 3969 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 3970
c349775e
ST		 3971 cp->data_len = cpu_to_le32(total_len);
3972 cp->err_ptr = cpu_to_le64(c->busaddr +
3973 offsetof(struct io_accel2_cmd, error_data));
50a0decf 3974 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 3975
d9a729f3
WS		 3976 /* fill in sg elements */
3977 if (use_sg > h->ioaccel_maxsg) {
3978 cp->sg_count = 1;
3979 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
3980 atomic_dec(&phys_disk->ioaccel_cmds_out);
3981 scsi_dma_unmap(cmd);
3982 return -1;
3983 }
3984 } else
3985 cp->sg_count = (u8) use_sg;
3986
c349775e
ST		 3987 enqueue_cmd_and_start_io(h, c);
3988 return 0;
3989}
3990
3991/*
3992 * Queue a command to the correct I/O accelerator path.
3993 */
3994static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3995 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 3996 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 3997{
03383736
DB		 3998 /* Try to honor the device's queue depth */
3999 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4000 phys_disk->queue_depth) {
4001 atomic_dec(&phys_disk->ioaccel_cmds_out);
4002 return IO_ACCEL_INELIGIBLE;
4003 }
c349775e
ST		 4004 if (h->transMethod & CFGTBL_Trans_io_accel1)
4005 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4006 cdb, cdb_len, scsi3addr,
4007 phys_disk);
c349775e
ST		 4008 else
4009 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4010 cdb, cdb_len, scsi3addr,
4011 phys_disk);
c349775e
ST		 4012}
4013
6b80b18f
ST		 4014static void raid_map_helper(struct raid_map_data *map,
4015 int offload_to_mirror, u32 *map_index, u32 *current_group)
4016{
4017 if (offload_to_mirror == 0) {
4018 /* use physical disk in the first mirrored group. */
2b08b3e9 4019 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4020 return;
4021 }
4022 do {
4023 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4024 *current_group = *map_index /
4025 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4026 if (offload_to_mirror == *current_group)
4027 continue;
2b08b3e9 4028 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4029 /* select map index from next group */
2b08b3e9 4030 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4031 (*current_group)++;
4032 } else {
4033 /* select map index from first group */
2b08b3e9 4034 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4035 *current_group = 0;
4036 }
4037 } while (offload_to_mirror != *current_group);
4038}
4039
283b4a9b
SC		 4040/*
4041 * Attempt to perform offload RAID mapping for a logical volume I/O.
4042 */
4043static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4044 struct CommandList *c)
4045{
4046 struct scsi_cmnd *cmd = c->scsi_cmd;
4047 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4048 struct raid_map_data *map = &dev->raid_map;
4049 struct raid_map_disk_data *dd = &map->data[0];
4050 int is_write = 0;
4051 u32 map_index;
4052 u64 first_block, last_block;
4053 u32 block_cnt;
4054 u32 blocks_per_row;
4055 u64 first_row, last_row;
4056 u32 first_row_offset, last_row_offset;
4057 u32 first_column, last_column;
6b80b18f
ST		 4058 u64 r0_first_row, r0_last_row;
4059 u32 r5or6_blocks_per_row;
4060 u64 r5or6_first_row, r5or6_last_row;
4061 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4062 u32 r5or6_first_column, r5or6_last_column;
4063 u32 total_disks_per_row;
4064 u32 stripesize;
4065 u32 first_group, last_group, current_group;
283b4a9b
SC		 4066 u32 map_row;
4067 u32 disk_handle;
4068 u64 disk_block;
4069 u32 disk_block_cnt;
4070 u8 cdb[16];
4071 u8 cdb_len;
2b08b3e9 4072 u16 strip_size;
283b4a9b
SC		 4073#if BITS_PER_LONG == 32
4074 u64 tmpdiv;
4075#endif
6b80b18f 4076 int offload_to_mirror;
283b4a9b 4077
283b4a9b
SC		 4078 /* check for valid opcode, get LBA and block count */
4079 switch (cmd->cmnd[0]) {
4080 case WRITE_6:
4081 is_write = 1;
4082 case READ_6:
4083 first_block =
4084 (((u64) cmd->cmnd[2]) << 8) |
4085 cmd->cmnd[3];
4086 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4087 if (block_cnt == 0)
4088 block_cnt = 256;
283b4a9b
SC		 4089 break;
4090 case WRITE_10:
4091 is_write = 1;
4092 case READ_10:
4093 first_block =
4094 (((u64) cmd->cmnd[2]) << 24) |
4095 (((u64) cmd->cmnd[3]) << 16) |
4096 (((u64) cmd->cmnd[4]) << 8) |
4097 cmd->cmnd[5];
4098 block_cnt =
4099 (((u32) cmd->cmnd[7]) << 8) |
4100 cmd->cmnd[8];
4101 break;
4102 case WRITE_12:
4103 is_write = 1;
4104 case READ_12:
4105 first_block =
4106 (((u64) cmd->cmnd[2]) << 24) |
4107 (((u64) cmd->cmnd[3]) << 16) |
4108 (((u64) cmd->cmnd[4]) << 8) |
4109 cmd->cmnd[5];
4110 block_cnt =
4111 (((u32) cmd->cmnd[6]) << 24) |
4112 (((u32) cmd->cmnd[7]) << 16) |
4113 (((u32) cmd->cmnd[8]) << 8) |
4114 cmd->cmnd[9];
4115 break;
4116 case WRITE_16:
4117 is_write = 1;
4118 case READ_16:
4119 first_block =
4120 (((u64) cmd->cmnd[2]) << 56) |
4121 (((u64) cmd->cmnd[3]) << 48) |
4122 (((u64) cmd->cmnd[4]) << 40) |
4123 (((u64) cmd->cmnd[5]) << 32) |
4124 (((u64) cmd->cmnd[6]) << 24) |
4125 (((u64) cmd->cmnd[7]) << 16) |
4126 (((u64) cmd->cmnd[8]) << 8) |
4127 cmd->cmnd[9];
4128 block_cnt =
4129 (((u32) cmd->cmnd[10]) << 24) |
4130 (((u32) cmd->cmnd[11]) << 16) |
4131 (((u32) cmd->cmnd[12]) << 8) |
4132 cmd->cmnd[13];
4133 break;
4134 default:
4135 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4136 }
283b4a9b
SC		 4137 last_block = first_block + block_cnt - 1;
4138
4139 /* check for write to non-RAID-0 */
4140 if (is_write && dev->raid_level != 0)
4141 return IO_ACCEL_INELIGIBLE;
4142
4143 /* check for invalid block or wraparound */
2b08b3e9
DB		 4144 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4145 last_block < first_block)
283b4a9b
SC		 4146 return IO_ACCEL_INELIGIBLE;
4147
4148 /* calculate stripe information for the request */
2b08b3e9
DB		 4149 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4150 le16_to_cpu(map->strip_size);
4151 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4152#if BITS_PER_LONG == 32
4153 tmpdiv = first_block;
4154 (void) do_div(tmpdiv, blocks_per_row);
4155 first_row = tmpdiv;
4156 tmpdiv = last_block;
4157 (void) do_div(tmpdiv, blocks_per_row);
4158 last_row = tmpdiv;
4159 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4160 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4161 tmpdiv = first_row_offset;
2b08b3e9 4162 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4163 first_column = tmpdiv;
4164 tmpdiv = last_row_offset;
2b08b3e9 4165 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4166 last_column = tmpdiv;
4167#else
4168 first_row = first_block / blocks_per_row;
4169 last_row = last_block / blocks_per_row;
4170 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4171 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4172 first_column = first_row_offset / strip_size;
4173 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4174#endif
4175
4176 /* if this isn't a single row/column then give to the controller */
4177 if ((first_row != last_row) || (first_column != last_column))
4178 return IO_ACCEL_INELIGIBLE;
4179
4180 /* proceeding with driver mapping */
2b08b3e9
DB		 4181 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4182 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4183 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4184 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4185 map_index = (map_row * total_disks_per_row) + first_column;
4186
4187 switch (dev->raid_level) {
4188 case HPSA_RAID_0:
4189 break; /* nothing special to do */
4190 case HPSA_RAID_1:
4191 /* Handles load balance across RAID 1 members.
4192 * (2-drive R1 and R10 with even # of drives.)
4193 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4194 */
2b08b3e9 4195 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4196 if (dev->offload_to_mirror)
2b08b3e9 4197 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4198 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4199 break;
4200 case HPSA_RAID_ADM:
4201 /* Handles N-way mirrors (R1-ADM)
4202 * and R10 with # of drives divisible by 3.)
4203 */
2b08b3e9 4204 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4205
4206 offload_to_mirror = dev->offload_to_mirror;
4207 raid_map_helper(map, offload_to_mirror,
4208 &map_index, &current_group);
4209 /* set mirror group to use next time */
4210 offload_to_mirror =
2b08b3e9
DB		 4211 (offload_to_mirror >=
4212 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4213 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4214 dev->offload_to_mirror = offload_to_mirror;
4215 /* Avoid direct use of dev->offload_to_mirror within this
4216 * function since multiple threads might simultaneously
4217 * increment it beyond the range of dev->layout_map_count -1.
4218 */
4219 break;
4220 case HPSA_RAID_5:
4221 case HPSA_RAID_6:
2b08b3e9 4222 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4223 break;
4224
4225 /* Verify first and last block are in same RAID group */
4226 r5or6_blocks_per_row =
2b08b3e9
DB		 4227 le16_to_cpu(map->strip_size) *
4228 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4229 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4230 stripesize = r5or6_blocks_per_row *
4231 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4232#if BITS_PER_LONG == 32
4233 tmpdiv = first_block;
4234 first_group = do_div(tmpdiv, stripesize);
4235 tmpdiv = first_group;
4236 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4237 first_group = tmpdiv;
4238 tmpdiv = last_block;
4239 last_group = do_div(tmpdiv, stripesize);
4240 tmpdiv = last_group;
4241 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4242 last_group = tmpdiv;
4243#else
4244 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4245 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4246#endif
000ff7c2 4247 if (first_group != last_group)
6b80b18f
ST		 4248 return IO_ACCEL_INELIGIBLE;
4249
4250 /* Verify request is in a single row of RAID 5/6 */
4251#if BITS_PER_LONG == 32
4252 tmpdiv = first_block;
4253 (void) do_div(tmpdiv, stripesize);
4254 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4255 tmpdiv = last_block;
4256 (void) do_div(tmpdiv, stripesize);
4257 r5or6_last_row = r0_last_row = tmpdiv;
4258#else
4259 first_row = r5or6_first_row = r0_first_row =
4260 first_block / stripesize;
4261 r5or6_last_row = r0_last_row = last_block / stripesize;
4262#endif
4263 if (r5or6_first_row != r5or6_last_row)
4264 return IO_ACCEL_INELIGIBLE;
4265
4266
4267 /* Verify request is in a single column */
4268#if BITS_PER_LONG == 32
4269 tmpdiv = first_block;
4270 first_row_offset = do_div(tmpdiv, stripesize);
4271 tmpdiv = first_row_offset;
4272 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4273 r5or6_first_row_offset = first_row_offset;
4274 tmpdiv = last_block;
4275 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4276 tmpdiv = r5or6_last_row_offset;
4277 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4278 tmpdiv = r5or6_first_row_offset;
4279 (void) do_div(tmpdiv, map->strip_size);
4280 first_column = r5or6_first_column = tmpdiv;
4281 tmpdiv = r5or6_last_row_offset;
4282 (void) do_div(tmpdiv, map->strip_size);
4283 r5or6_last_column = tmpdiv;
4284#else
4285 first_row_offset = r5or6_first_row_offset =
4286 (u32)((first_block % stripesize) %
4287 r5or6_blocks_per_row);
4288
4289 r5or6_last_row_offset =
4290 (u32)((last_block % stripesize) %
4291 r5or6_blocks_per_row);
4292
4293 first_column = r5or6_first_column =
2b08b3e9 4294 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4295 r5or6_last_column =
2b08b3e9 4296 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4297#endif
4298 if (r5or6_first_column != r5or6_last_column)
4299 return IO_ACCEL_INELIGIBLE;
4300
4301 /* Request is eligible */
4302 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4303 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4304
4305 map_index = (first_group *
2b08b3e9 4306 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4307 (map_row * total_disks_per_row) + first_column;
4308 break;
4309 default:
4310 return IO_ACCEL_INELIGIBLE;
283b4a9b 4311 }
6b80b18f 4312
07543e0c
SC		 4313 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4314 return IO_ACCEL_INELIGIBLE;
4315
03383736
DB		 4316 c->phys_disk = dev->phys_disk[map_index];
4317
283b4a9b 4318 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4319 disk_block = le64_to_cpu(map->disk_starting_blk) +
4320 first_row * le16_to_cpu(map->strip_size) +
4321 (first_row_offset - first_column *
4322 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4323 disk_block_cnt = block_cnt;
4324
4325 /* handle differing logical/physical block sizes */
4326 if (map->phys_blk_shift) {
4327 disk_block <<= map->phys_blk_shift;
4328 disk_block_cnt <<= map->phys_blk_shift;
4329 }
4330 BUG_ON(disk_block_cnt > 0xffff);
4331
4332 /* build the new CDB for the physical disk I/O */
4333 if (disk_block > 0xffffffff) {
4334 cdb[0] = is_write ? WRITE_16 : READ_16;
4335 cdb[1] = 0;
4336 cdb[2] = (u8) (disk_block >> 56);
4337 cdb[3] = (u8) (disk_block >> 48);
4338 cdb[4] = (u8) (disk_block >> 40);
4339 cdb[5] = (u8) (disk_block >> 32);
4340 cdb[6] = (u8) (disk_block >> 24);
4341 cdb[7] = (u8) (disk_block >> 16);
4342 cdb[8] = (u8) (disk_block >> 8);
4343 cdb[9] = (u8) (disk_block);
4344 cdb[10] = (u8) (disk_block_cnt >> 24);
4345 cdb[11] = (u8) (disk_block_cnt >> 16);
4346 cdb[12] = (u8) (disk_block_cnt >> 8);
4347 cdb[13] = (u8) (disk_block_cnt);
4348 cdb[14] = 0;
4349 cdb[15] = 0;
4350 cdb_len = 16;
4351 } else {
4352 cdb[0] = is_write ? WRITE_10 : READ_10;
4353 cdb[1] = 0;
4354 cdb[2] = (u8) (disk_block >> 24);
4355 cdb[3] = (u8) (disk_block >> 16);
4356 cdb[4] = (u8) (disk_block >> 8);
4357 cdb[5] = (u8) (disk_block);
4358 cdb[6] = 0;
4359 cdb[7] = (u8) (disk_block_cnt >> 8);
4360 cdb[8] = (u8) (disk_block_cnt);
4361 cdb[9] = 0;
4362 cdb_len = 10;
4363 }
4364 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4365 dev->scsi3addr,
4366 dev->phys_disk[map_index]);
283b4a9b
SC		 4367}
4368
25163bd5
WS		 4369/*
4370 * Submit commands down the "normal" RAID stack path
4371 * All callers to hpsa_ciss_submit must check lockup_detected
4372 * beforehand, before (opt.) and after calling cmd_alloc
4373 */
574f05d3
SC		 4374static int hpsa_ciss_submit(struct ctlr_info *h,
4375 struct CommandList *c, struct scsi_cmnd *cmd,
4376 unsigned char scsi3addr[])
edd16368 4377{
edd16368 4378 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4379 c->cmd_type = CMD_SCSI;
4380 c->scsi_cmd = cmd;
4381 c->Header.ReplyQueue = 0; /* unused in simple mode */
4382 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4383 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4384
4385 /* Fill in the request block... */
4386
4387 c->Request.Timeout = 0;
edd16368
SC		 4388 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4389 c->Request.CDBLen = cmd->cmd_len;
4390 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4391 switch (cmd->sc_data_direction) {
4392 case DMA_TO_DEVICE:
a505b86f
SC		 4393 c->Request.type_attr_dir =
4394 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4395 break;
4396 case DMA_FROM_DEVICE:
a505b86f
SC		 4397 c->Request.type_attr_dir =
4398 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4399 break;
4400 case DMA_NONE:
a505b86f
SC		 4401 c->Request.type_attr_dir =
4402 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4403 break;
4404 case DMA_BIDIRECTIONAL:
4405 /* This can happen if a buggy application does a scsi passthru
4406 * and sets both inlen and outlen to non-zero. ( see
4407 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4408 */
4409
a505b86f
SC		 4410 c->Request.type_attr_dir =
4411 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4412 /* This is technically wrong, and hpsa controllers should
4413 * reject it with CMD_INVALID, which is the most correct
4414 * response, but non-fibre backends appear to let it
4415 * slide by, and give the same results as if this field
4416 * were set correctly. Either way is acceptable for
4417 * our purposes here.
4418 */
4419
4420 break;
4421
4422 default:
4423 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4424 cmd->sc_data_direction);
4425 BUG();
4426 break;
4427 }
4428
33a2ffce 4429 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 4430 cmd_free(h, c);
4431 return SCSI_MLQUEUE_HOST_BUSY;
4432 }
4433 enqueue_cmd_and_start_io(h, c);
4434 /* the cmd'll come back via intr handler in complete_scsi_command() */
4435 return 0;
4436}
4437
360c73bd
SC		 4438static void hpsa_cmd_init(struct ctlr_info *h, int index,
4439 struct CommandList *c)
4440{
4441 dma_addr_t cmd_dma_handle, err_dma_handle;
4442
4443 /* Zero out all of commandlist except the last field, refcount */
4444 memset(c, 0, offsetof(struct CommandList, refcount));
4445 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4446 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4447 c->err_info = h->errinfo_pool + index;
4448 memset(c->err_info, 0, sizeof(*c->err_info));
4449 err_dma_handle = h->errinfo_pool_dhandle
4450 + index * sizeof(*c->err_info);
4451 c->cmdindex = index;
4452 c->busaddr = (u32) cmd_dma_handle;
4453 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4454 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4455 c->h = h;
4456}
4457
4458static void hpsa_preinitialize_commands(struct ctlr_info *h)
4459{
4460 int i;
4461
4462 for (i = 0; i < h->nr_cmds; i++) {
4463 struct CommandList *c = h->cmd_pool + i;
4464
4465 hpsa_cmd_init(h, i, c);
4466 atomic_set(&c->refcount, 0);
4467 }
4468}
4469
4470static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4471 struct CommandList *c)
4472{
4473 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4474
4475 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4476 memset(c->err_info, 0, sizeof(*c->err_info));
4477 c->busaddr = (u32) cmd_dma_handle;
4478}
4479
592a0ad5
WS		 4480static int hpsa_ioaccel_submit(struct ctlr_info *h,
4481 struct CommandList *c, struct scsi_cmnd *cmd,
4482 unsigned char *scsi3addr)
4483{
4484 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4485 int rc = IO_ACCEL_INELIGIBLE;
4486
4487 cmd->host_scribble = (unsigned char *) c;
4488
4489 if (dev->offload_enabled) {
4490 hpsa_cmd_init(h, c->cmdindex, c);
4491 c->cmd_type = CMD_SCSI;
4492 c->scsi_cmd = cmd;
4493 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4494 if (rc < 0) /* scsi_dma_map failed. */
4495 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4496 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4497 hpsa_cmd_init(h, c->cmdindex, c);
4498 c->cmd_type = CMD_SCSI;
4499 c->scsi_cmd = cmd;
4500 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4501 if (rc < 0) /* scsi_dma_map failed. */
4502 rc = SCSI_MLQUEUE_HOST_BUSY;
4503 }
4504 return rc;
4505}
4506
080ef1cc
DB		 4507static void hpsa_command_resubmit_worker(struct work_struct *work)
4508{
4509 struct scsi_cmnd *cmd;
4510 struct hpsa_scsi_dev_t *dev;
4511 struct CommandList *c =
4512 container_of(work, struct CommandList, work);
4513
4514 cmd = c->scsi_cmd;
4515 dev = cmd->device->hostdata;
4516 if (!dev) {
4517 cmd->result = DID_NO_CONNECT << 16;
592a0ad5 4518 cmd_free(c->h, c);
080ef1cc
DB		 4519 cmd->scsi_done(cmd);
4520 return;
4521 }
592a0ad5
WS		 4522 if (c->cmd_type == CMD_IOACCEL2) {
4523 struct ctlr_info *h = c->h;
4524 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4525 int rc;
4526
4527 if (c2->error_data.serv_response ==
4528 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4529 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4530 if (rc == 0)
4531 return;
4532 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4533 /*
4534 * If we get here, it means dma mapping failed.
4535 * Try again via scsi mid layer, which will
4536 * then get SCSI_MLQUEUE_HOST_BUSY.
4537 */
4538 cmd->result = DID_IMM_RETRY << 16;
4539 cmd->scsi_done(cmd);
4540 cmd_free(h, c); /* FIX-ME: on merge, change
4541 * to cmd_tagged_free() and
4542 * ultimately to
4543 * hpsa_cmd_free_and_done(). */
4544 return;
4545 }
4546 /* else, fall thru and resubmit down CISS path */
4547 }
4548 }
360c73bd 4549 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4550 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4551 /*
4552 * If we get here, it means dma mapping failed. Try
4553 * again via scsi mid layer, which will then get
4554 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4555 *
4556 * hpsa_ciss_submit will have already freed c
4557 * if it encountered a dma mapping failure.
080ef1cc
DB		 4558 */
4559 cmd->result = DID_IMM_RETRY << 16;
4560 cmd->scsi_done(cmd);
4561 }
4562}
4563
574f05d3
SC		 4564/* Running in struct Scsi_Host->host_lock less mode */
4565static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4566{
4567 struct ctlr_info *h;
4568 struct hpsa_scsi_dev_t *dev;
4569 unsigned char scsi3addr[8];
4570 struct CommandList *c;
4571 int rc = 0;
4572
4573 /* Get the ptr to our adapter structure out of cmd->host. */
4574 h = sdev_to_hba(cmd->device);
4575 dev = cmd->device->hostdata;
4576 if (!dev) {
4577 cmd->result = DID_NO_CONNECT << 16;
4578 cmd->scsi_done(cmd);
4579 return 0;
4580 }
4581 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
4582
4583 if (unlikely(lockup_detected(h))) {
25163bd5 4584 cmd->result = DID_NO_CONNECT << 16;
574f05d3
SC		 4585 cmd->scsi_done(cmd);
4586 return 0;
4587 }
4588 c = cmd_alloc(h);
4589 if (c == NULL) { /* trouble... */
4590 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
4591 return SCSI_MLQUEUE_HOST_BUSY;
4592 }
407863cb 4593 if (unlikely(lockup_detected(h))) {
25163bd5 4594 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4595 cmd_free(h, c);
4596 cmd->scsi_done(cmd);
4597 return 0;
4598 }
574f05d3 4599
407863cb
SC		 4600 /*
4601 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4602 * Retries always go down the normal I/O path.
4603 */
4604 if (likely(cmd->retries == 0 &&
4605 cmd->request->cmd_type == REQ_TYPE_FS &&
4606 h->acciopath_status)) {
592a0ad5
WS		 4607 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4608 if (rc == 0)
4609 return 0;
4610 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4611 cmd_free(h, c); /* FIX-ME: on merge, change to
4612 * cmd_tagged_free(), and ultimately
4613 * to hpsa_cmd_resolve_and_free(). */
4614 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4615 }
4616 }
4617 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4618}
4619
8ebc9248 4620static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4621{
4622 unsigned long flags;
4623
8ebc9248
WS		 4624 spin_lock_irqsave(&h->scan_lock, flags);
4625 h->scan_finished = 1;
4626 wake_up_all(&h->scan_wait_queue);
4627 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4628}
4629
a08a8471
SC		 4630static void hpsa_scan_start(struct Scsi_Host *sh)
4631{
4632 struct ctlr_info *h = shost_to_hba(sh);
4633 unsigned long flags;
4634
8ebc9248
WS		 4635 /*
4636 * Don't let rescans be initiated on a controller known to be locked
4637 * up. If the controller locks up *during* a rescan, that thread is
4638 * probably hosed, but at least we can prevent new rescan threads from
4639 * piling up on a locked up controller.
4640 */
4641 if (unlikely(lockup_detected(h)))
4642 return hpsa_scan_complete(h);
5f389360 4643
a08a8471
SC		 4644 /* wait until any scan already in progress is finished. */
4645 while (1) {
4646 spin_lock_irqsave(&h->scan_lock, flags);
4647 if (h->scan_finished)
4648 break;
4649 spin_unlock_irqrestore(&h->scan_lock, flags);
4650 wait_event(h->scan_wait_queue, h->scan_finished);
4651 /* Note: We don't need to worry about a race between this
4652 * thread and driver unload because the midlayer will
4653 * have incremented the reference count, so unload won't
4654 * happen if we're in here.
4655 */
4656 }
4657 h->scan_finished = 0; /* mark scan as in progress */
4658 spin_unlock_irqrestore(&h->scan_lock, flags);
4659
8ebc9248
WS		 4660 if (unlikely(lockup_detected(h)))
4661 return hpsa_scan_complete(h);
5f389360 4662
a08a8471
SC		 4663 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
4664
8ebc9248 4665 hpsa_scan_complete(h);
a08a8471
SC		 4666}
4667
7c0a0229
DB		 4668static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
4669{
03383736
DB		 4670 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
4671
4672 if (!logical_drive)
4673 return -ENODEV;
7c0a0229
DB		 4674
4675 if (qdepth < 1)
4676 qdepth = 1;
03383736
DB		 4677 else if (qdepth > logical_drive->queue_depth)
4678 qdepth = logical_drive->queue_depth;
4679
4680 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 4681}
4682
a08a8471
SC		 4683static int hpsa_scan_finished(struct Scsi_Host *sh,
4684 unsigned long elapsed_time)
4685{
4686 struct ctlr_info *h = shost_to_hba(sh);
4687 unsigned long flags;
4688 int finished;
4689
4690 spin_lock_irqsave(&h->scan_lock, flags);
4691 finished = h->scan_finished;
4692 spin_unlock_irqrestore(&h->scan_lock, flags);
4693 return finished;
4694}
4695
edd16368
SC		 4696static void hpsa_unregister_scsi(struct ctlr_info *h)
4697{
4698 /* we are being forcibly unloaded, and may not refuse. */
4699 scsi_remove_host(h->scsi_host);
4700 scsi_host_put(h->scsi_host);
4701 h->scsi_host = NULL;
4702}
4703
4704static int hpsa_register_scsi(struct ctlr_info *h)
4705{
b705690d
SC		 4706 struct Scsi_Host *sh;
4707 int error;
edd16368 4708
b705690d
SC		 4709 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
4710 if (sh == NULL)
4711 goto fail;
4712
4713 sh->io_port = 0;
4714 sh->n_io_port = 0;
4715 sh->this_id = -1;
4716 sh->max_channel = 3;
4717 sh->max_cmd_len = MAX_COMMAND_SIZE;
4718 sh->max_lun = HPSA_MAX_LUN;
4719 sh->max_id = HPSA_MAX_LUN;
41ce4c35 4720 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 4721 sh->cmd_per_lun = sh->can_queue;
b705690d
SC		 4722 sh->sg_tablesize = h->maxsgentries;
4723 h->scsi_host = sh;
4724 sh->hostdata[0] = (unsigned long) h;
4725 sh->irq = h->intr[h->intr_mode];
4726 sh->unique_id = sh->irq;
4727 error = scsi_add_host(sh, &h->pdev->dev);
4728 if (error)
4729 goto fail_host_put;
4730 scsi_scan_host(sh);
4731 return 0;
4732
4733 fail_host_put:
4734 dev_err(&h->pdev->dev, "%s: scsi_add_host"
4735 " failed for controller %d\n", __func__, h->ctlr);
4736 scsi_host_put(sh);
4737 return error;
4738 fail:
4739 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
4740 " failed for controller %d\n", __func__, h->ctlr);
4741 return -ENOMEM;
edd16368
SC		 4742}
4743
4744static int wait_for_device_to_become_ready(struct ctlr_info *h,
4745 unsigned char lunaddr[])
4746{
8919358e 4747 int rc;
edd16368
SC		 4748 int count = 0;
4749 int waittime = 1; /* seconds */
4750 struct CommandList *c;
4751
45fcb86e 4752 c = cmd_alloc(h);
edd16368
SC		 4753 if (!c) {
4754 dev_warn(&h->pdev->dev, "out of memory in "
4755 "wait_for_device_to_become_ready.\n");
4756 return IO_ERROR;
4757 }
4758
4759 /* Send test unit ready until device ready, or give up. */
4760 while (count < HPSA_TUR_RETRY_LIMIT) {
4761
4762 /* Wait for a bit. do this first, because if we send
4763 * the TUR right away, the reset will just abort it.
4764 */
4765 msleep(1000 * waittime);
4766 count++;
8919358e 4767 rc = 0; /* Device ready. */
edd16368
SC		 4768
4769 /* Increase wait time with each try, up to a point. */
4770 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
4771 waittime = waittime * 2;
4772
a2dac136
SC		 4773 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
4774 (void) fill_cmd(c, TEST_UNIT_READY, h,
4775 NULL, 0, 0, lunaddr, TYPE_CMD);
25163bd5
WS		 4776 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
4777 NO_TIMEOUT);
4778 if (rc)
4779 goto do_it_again;
edd16368
SC		 4780 /* no unmap needed here because no data xfer. */
4781
4782 if (c->err_info->CommandStatus == CMD_SUCCESS)
4783 break;
4784
4785 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4786 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
4787 (c->err_info->SenseInfo[2] == NO_SENSE ||
4788 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
4789 break;
25163bd5 4790do_it_again:
edd16368
SC		 4791 dev_warn(&h->pdev->dev, "waiting %d secs "
4792 "for device to become ready.\n", waittime);
4793 rc = 1; /* device not ready. */
4794 }
4795
4796 if (rc)
4797 dev_warn(&h->pdev->dev, "giving up on device.\n");
4798 else
4799 dev_warn(&h->pdev->dev, "device is ready.\n");
4800
45fcb86e 4801 cmd_free(h, c);
edd16368
SC		 4802 return rc;
4803}
4804
4805/* Need at least one of these error handlers to keep ../scsi/hosts.c from
4806 * complaining. Doing a host- or bus-reset can't do anything good here.
4807 */
4808static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
4809{
4810 int rc;
4811 struct ctlr_info *h;
4812 struct hpsa_scsi_dev_t *dev;
4813
4814 /* find the controller to which the command to be aborted was sent */
4815 h = sdev_to_hba(scsicmd->device);
4816 if (h == NULL) /* paranoia */
4817 return FAILED;
e345893b
DB		 4818
4819 if (lockup_detected(h))
4820 return FAILED;
4821
edd16368
SC		 4822 dev = scsicmd->device->hostdata;
4823 if (!dev) {
4824 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
4825 "device lookup failed.\n");
4826 return FAILED;
4827 }
25163bd5
WS		 4828
4829 /* if controller locked up, we can guarantee command won't complete */
4830 if (lockup_detected(h)) {
4831 dev_warn(&h->pdev->dev,
4832 "scsi %d:%d:%d:%d RESET FAILED, lockup detected\n",
4833 h->scsi_host->host_no, dev->bus, dev->target,
4834 dev->lun);
4835 return FAILED;
4836 }
4837
4838 /* this reset request might be the result of a lockup; check */
4839 if (detect_controller_lockup(h)) {
4840 dev_warn(&h->pdev->dev,
4841 "scsi %d:%d:%d:%d RESET FAILED, new lockup detected\n",
4842 h->scsi_host->host_no, dev->bus, dev->target,
4843 dev->lun);
4844 return FAILED;
4845 }
4846
4847 hpsa_show_dev_msg(KERN_WARNING, h, dev, "resetting");
4848
edd16368 4849 /* send a reset to the SCSI LUN which the command was sent to */
25163bd5
WS		 4850 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN,
4851 DEFAULT_REPLY_QUEUE);
edd16368
SC		 4852 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
4853 return SUCCESS;
4854
25163bd5
WS		 4855 dev_warn(&h->pdev->dev,
4856 "scsi %d:%d:%d:%d reset failed\n",
4857 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368
SC		 4858 return FAILED;
4859}
4860
6cba3f19
SC		 4861static void swizzle_abort_tag(u8 *tag)
4862{
4863 u8 original_tag[8];
4864
4865 memcpy(original_tag, tag, 8);
4866 tag[0] = original_tag[3];
4867 tag[1] = original_tag[2];
4868 tag[2] = original_tag[1];
4869 tag[3] = original_tag[0];
4870 tag[4] = original_tag[7];
4871 tag[5] = original_tag[6];
4872 tag[6] = original_tag[5];
4873 tag[7] = original_tag[4];
4874}
4875
17eb87d2 4876static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 4877 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 4878{
2b08b3e9 4879 u64 tag;
17eb87d2
ST		 4880 if (c->cmd_type == CMD_IOACCEL1) {
4881 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4882 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 4883 tag = le64_to_cpu(cm1->tag);
4884 *tagupper = cpu_to_le32(tag >> 32);
4885 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 4886 return;
4887 }
4888 if (c->cmd_type == CMD_IOACCEL2) {
4889 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4890 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4891 /* upper tag not used in ioaccel2 mode */
4892 memset(tagupper, 0, sizeof(*tagupper));
4893 *taglower = cm2->Tag;
54b6e9e9 4894 return;
17eb87d2 4895 }
2b08b3e9
DB		 4896 tag = le64_to_cpu(c->Header.tag);
4897 *tagupper = cpu_to_le32(tag >> 32);
4898 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 4899}
4900
75167d2c 4901static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 4902 struct CommandList *abort, int reply_queue)
75167d2c
SC		 4903{
4904 int rc = IO_OK;
4905 struct CommandList *c;
4906 struct ErrorInfo *ei;
2b08b3e9 4907 __le32 tagupper, taglower;
75167d2c 4908
45fcb86e 4909 c = cmd_alloc(h);
75167d2c 4910 if (c == NULL) { /* trouble... */
45fcb86e 4911 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
75167d2c
SC		 4912 return -ENOMEM;
4913 }
4914
a2dac136 4915 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 4916 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 4917 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 4918 if (h->needs_abort_tags_swizzled)
6cba3f19 4919 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 4920 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 4921 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 4922 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 4923 __func__, tagupper, taglower);
75167d2c
SC		 4924 /* no unmap needed here because no data xfer. */
4925
4926 ei = c->err_info;
4927 switch (ei->CommandStatus) {
4928 case CMD_SUCCESS:
4929 break;
9437ac43
SC		 4930 case CMD_TMF_STATUS:
4931 rc = hpsa_evaluate_tmf_status(h, c);
4932 break;
75167d2c
SC		 4933 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4934 rc = -1;
4935 break;
4936 default:
4937 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4938 __func__, tagupper, taglower);
d1e8beac 4939 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4940 rc = -1;
4941 break;
4942 }
45fcb86e 4943 cmd_free(h, c);
dd0e19f3
ST		 4944 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4945 __func__, tagupper, taglower);
75167d2c
SC		 4946 return rc;
4947}
4948
54b6e9e9
ST		 4949/* ioaccel2 path firmware cannot handle abort task requests.
4950 * Change abort requests to physical target reset, and send to the
4951 * address of the physical disk used for the ioaccel 2 command.
4952 * Return 0 on success (IO_OK)
4953 * -1 on failure
4954 */
4955
4956static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 4957 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 4958{
4959 int rc = IO_OK;
4960 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4961 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4962 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4963 unsigned char *psa = &phys_scsi3addr[0];
4964
4965 /* Get a pointer to the hpsa logical device. */
7fa3030c 4966 scmd = abort->scsi_cmd;
54b6e9e9
ST		 4967 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4968 if (dev == NULL) {
4969 dev_warn(&h->pdev->dev,
4970 "Cannot abort: no device pointer for command.\n");
4971 return -1; /* not abortable */
4972 }
4973
2ba8bfc8
SC		 4974 if (h->raid_offload_debug > 0)
4975 dev_info(&h->pdev->dev,
0d96ef5f 4976 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 4977 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 4978 "Reset as abort",
2ba8bfc8
SC		 4979 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4980 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4981
54b6e9e9
ST		 4982 if (!dev->offload_enabled) {
4983 dev_warn(&h->pdev->dev,
4984 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4985 return -1; /* not abortable */
4986 }
4987
4988 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4989 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4990 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4991 return -1; /* not abortable */
4992 }
4993
4994 /* send the reset */
2ba8bfc8
SC		 4995 if (h->raid_offload_debug > 0)
4996 dev_info(&h->pdev->dev,
4997 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4998 psa[0], psa[1], psa[2], psa[3],
4999 psa[4], psa[5], psa[6], psa[7]);
25163bd5 5000 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5001 if (rc != 0) {
5002 dev_warn(&h->pdev->dev,
5003 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5004 psa[0], psa[1], psa[2], psa[3],
5005 psa[4], psa[5], psa[6], psa[7]);
5006 return rc; /* failed to reset */
5007 }
5008
5009 /* wait for device to recover */
5010 if (wait_for_device_to_become_ready(h, psa) != 0) {
5011 dev_warn(&h->pdev->dev,
5012 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5013 psa[0], psa[1], psa[2], psa[3],
5014 psa[4], psa[5], psa[6], psa[7]);
5015 return -1; /* failed to recover */
5016 }
5017
5018 /* device recovered */
5019 dev_info(&h->pdev->dev,
5020 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5021 psa[0], psa[1], psa[2], psa[3],
5022 psa[4], psa[5], psa[6], psa[7]);
5023
5024 return rc; /* success */
5025}
5026
6cba3f19 5027static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5028 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5029{
54b6e9e9
ST		 5030 /* ioccelerator mode 2 commands should be aborted via the
5031 * accelerated path, since RAID path is unaware of these commands,
5032 * but underlying firmware can't handle abort TMF.
5033 * Change abort to physical device reset.
5034 */
5035 if (abort->cmd_type == CMD_IOACCEL2)
25163bd5
WS		 5036 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
5037 abort, reply_queue);
9b5c48c2 5038 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5039}
54b6e9e9 5040
25163bd5
WS		 5041/* Find out which reply queue a command was meant to return on */
5042static int hpsa_extract_reply_queue(struct ctlr_info *h,
5043 struct CommandList *c)
5044{
5045 if (c->cmd_type == CMD_IOACCEL2)
5046 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5047 return c->Header.ReplyQueue;
6cba3f19
SC		 5048}
5049
9b5c48c2
SC		 5050/*
5051 * Limit concurrency of abort commands to prevent
5052 * over-subscription of commands
5053 */
5054static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5055{
5056#define ABORT_CMD_WAIT_MSECS 5000
5057 return !wait_event_timeout(h->abort_cmd_wait_queue,
5058 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5059 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5060}
5061
75167d2c
SC		 5062/* Send an abort for the specified command.
5063 * If the device and controller support it,
5064 * send a task abort request.
5065 */
5066static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5067{
5068
5069 int i, rc;
5070 struct ctlr_info *h;
5071 struct hpsa_scsi_dev_t *dev;
5072 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5073 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5074 char msg[256]; /* For debug messaging. */
5075 int ml = 0;
2b08b3e9 5076 __le32 tagupper, taglower;
25163bd5
WS		 5077 int refcount, reply_queue;
5078
5079 if (sc == NULL)
5080 return FAILED;
75167d2c 5081
9b5c48c2
SC		 5082 if (sc->device == NULL)
5083 return FAILED;
5084
75167d2c
SC		 5085 /* Find the controller of the command to be aborted */
5086 h = sdev_to_hba(sc->device);
9b5c48c2 5087 if (h == NULL)
75167d2c
SC		 5088 return FAILED;
5089
25163bd5
WS		 5090 /* Find the device of the command to be aborted */
5091 dev = sc->device->hostdata;
5092 if (!dev) {
5093 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5094 msg);
e345893b 5095 return FAILED;
25163bd5
WS		 5096 }
5097
5098 /* If controller locked up, we can guarantee command won't complete */
5099 if (lockup_detected(h)) {
5100 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5101 "ABORT FAILED, lockup detected");
5102 return FAILED;
5103 }
5104
5105 /* This is a good time to check if controller lockup has occurred */
5106 if (detect_controller_lockup(h)) {
5107 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5108 "ABORT FAILED, new lockup detected");
5109 return FAILED;
5110 }
e345893b 5111
75167d2c
SC		 5112 /* Check that controller supports some kind of task abort */
5113 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5114 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5115 return FAILED;
5116
5117 memset(msg, 0, sizeof(msg));
0d96ef5f 5118 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s",
75167d2c 5119 h->scsi_host->host_no, sc->device->channel,
0d96ef5f
WS		 5120 sc->device->id, sc->device->lun,
5121 "Aborting command");
75167d2c 5122
75167d2c
SC		 5123 /* Get SCSI command to be aborted */
5124 abort = (struct CommandList *) sc->host_scribble;
5125 if (abort == NULL) {
281a7fd0
WS		 5126 /* This can happen if the command already completed. */
5127 return SUCCESS;
5128 }
5129 refcount = atomic_inc_return(&abort->refcount);
5130 if (refcount == 1) { /* Command is done already. */
5131 cmd_free(h, abort);
5132 return SUCCESS;
75167d2c 5133 }
9b5c48c2
SC		 5134
5135 /* Don't bother trying the abort if we know it won't work. */
5136 if (abort->cmd_type != CMD_IOACCEL2 &&
5137 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5138 cmd_free(h, abort);
5139 return FAILED;
5140 }
5141
17eb87d2 5142 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5143 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5144 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5145 as = abort->scsi_cmd;
75167d2c
SC		 5146 if (as != NULL)
5147 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
5148 as->cmnd[0], as->serial_number);
5149 dev_dbg(&h->pdev->dev, "%s\n", msg);
0d96ef5f 5150 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
75167d2c
SC		 5151 /*
5152 * Command is in flight, or possibly already completed
5153 * by the firmware (but not to the scsi mid layer) but we can't
5154 * distinguish which. Send the abort down.
5155 */
9b5c48c2
SC		 5156 if (wait_for_available_abort_cmd(h)) {
5157 dev_warn(&h->pdev->dev,
5158 "Timed out waiting for an abort command to become available.\n");
5159 cmd_free(h, abort);
5160 return FAILED;
5161 }
25163bd5 5162 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5163 atomic_inc(&h->abort_cmds_available);
5164 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5165 if (rc != 0) {
0d96ef5f
WS		 5166 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5167 "FAILED to abort command");
281a7fd0 5168 cmd_free(h, abort);
75167d2c
SC		 5169 return FAILED;
5170 }
5171 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
5172
5173 /* If the abort(s) above completed and actually aborted the
5174 * command, then the command to be aborted should already be
5175 * completed. If not, wait around a bit more to see if they
5176 * manage to complete normally.
5177 */
5178#define ABORT_COMPLETE_WAIT_SECS 30
5179 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
281a7fd0
WS		 5180 refcount = atomic_read(&abort->refcount);
5181 if (refcount < 2) {
5182 cmd_free(h, abort);
75167d2c 5183 return SUCCESS;
281a7fd0
WS		 5184 } else {
5185 msleep(100);
5186 }
75167d2c
SC		 5187 }
5188 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
5189 msg, ABORT_COMPLETE_WAIT_SECS);
281a7fd0 5190 cmd_free(h, abort);
75167d2c
SC		 5191 return FAILED;
5192}
5193
edd16368
SC		 5194/*
5195 * For operations that cannot sleep, a command block is allocated at init,
5196 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5197 * which ones are free or in use. Lock must be held when calling this.
5198 * cmd_free() is the complement.
5199 */
281a7fd0 5200
edd16368
SC		 5201static struct CommandList *cmd_alloc(struct ctlr_info *h)
5202{
5203 struct CommandList *c;
360c73bd 5204 int refcount, i;
33811026 5205 unsigned long offset;
4c413128 5206
33811026
RE		 5207 /*
5208 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5209 * multiple threads could get in here, and one thread could
5210 * be scanning through the list of bits looking for a free
5211 * one, but the free ones are always behind him, and other
5212 * threads sneak in behind him and eat them before he can
5213 * get to them, so that while there is always a free one, a
5214 * very unlucky thread might be starved anyway, never able to
5215 * beat the other threads. In reality, this happens so
5216 * infrequently as to be indistinguishable from never.
5217 */
edd16368 5218
33811026 5219 offset = h->last_allocation; /* benignly racy */
281a7fd0
WS		 5220 for (;;) {
5221 i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset);
5222 if (unlikely(i == h->nr_cmds)) {
5223 offset = 0;
5224 continue;
5225 }
5226 c = h->cmd_pool + i;
5227 refcount = atomic_inc_return(&c->refcount);
5228 if (unlikely(refcount > 1)) {
5229 cmd_free(h, c); /* already in use */
5230 offset = (i + 1) % h->nr_cmds;
5231 continue;
5232 }
5233 set_bit(i & (BITS_PER_LONG - 1),
5234 h->cmd_pool_bits + (i / BITS_PER_LONG));
5235 break; /* it's ours now. */
5236 }
33811026 5237 h->last_allocation = i; /* benignly racy */
360c73bd 5238 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5239 return c;
5240}
5241
edd16368
SC		 5242static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5243{
281a7fd0
WS		 5244 if (atomic_dec_and_test(&c->refcount)) {
5245 int i;
edd16368 5246
281a7fd0
WS		 5247 i = c - h->cmd_pool;
5248 clear_bit(i & (BITS_PER_LONG - 1),
5249 h->cmd_pool_bits + (i / BITS_PER_LONG));
5250 }
edd16368
SC		 5251}
5252
edd16368
SC		 5253#ifdef CONFIG_COMPAT
5254
42a91641
DB		 5255static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5256 void __user *arg)
edd16368
SC		 5257{
5258 IOCTL32_Command_struct __user *arg32 =
5259 (IOCTL32_Command_struct __user *) arg;
5260 IOCTL_Command_struct arg64;
5261 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5262 int err;
5263 u32 cp;
5264
938abd84 5265 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5266 err = 0;
5267 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5268 sizeof(arg64.LUN_info));
5269 err |= copy_from_user(&arg64.Request, &arg32->Request,
5270 sizeof(arg64.Request));
5271 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5272 sizeof(arg64.error_info));
5273 err |= get_user(arg64.buf_size, &arg32->buf_size);
5274 err |= get_user(cp, &arg32->buf);
5275 arg64.buf = compat_ptr(cp);
5276 err |= copy_to_user(p, &arg64, sizeof(arg64));
5277
5278 if (err)
5279 return -EFAULT;
5280
42a91641 5281 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5282 if (err)
5283 return err;
5284 err |= copy_in_user(&arg32->error_info, &p->error_info,
5285 sizeof(arg32->error_info));
5286 if (err)
5287 return -EFAULT;
5288 return err;
5289}
5290
5291static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5292 int cmd, void __user *arg)
edd16368
SC		 5293{
5294 BIG_IOCTL32_Command_struct __user *arg32 =
5295 (BIG_IOCTL32_Command_struct __user *) arg;
5296 BIG_IOCTL_Command_struct arg64;
5297 BIG_IOCTL_Command_struct __user *p =
5298 compat_alloc_user_space(sizeof(arg64));
5299 int err;
5300 u32 cp;
5301
938abd84 5302 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5303 err = 0;
5304 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5305 sizeof(arg64.LUN_info));
5306 err |= copy_from_user(&arg64.Request, &arg32->Request,
5307 sizeof(arg64.Request));
5308 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5309 sizeof(arg64.error_info));
5310 err |= get_user(arg64.buf_size, &arg32->buf_size);
5311 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5312 err |= get_user(cp, &arg32->buf);
5313 arg64.buf = compat_ptr(cp);
5314 err |= copy_to_user(p, &arg64, sizeof(arg64));
5315
5316 if (err)
5317 return -EFAULT;
5318
42a91641 5319 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5320 if (err)
5321 return err;
5322 err |= copy_in_user(&arg32->error_info, &p->error_info,
5323 sizeof(arg32->error_info));
5324 if (err)
5325 return -EFAULT;
5326 return err;
5327}
71fe75a7 5328
42a91641 5329static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5330{
5331 switch (cmd) {
5332 case CCISS_GETPCIINFO:
5333 case CCISS_GETINTINFO:
5334 case CCISS_SETINTINFO:
5335 case CCISS_GETNODENAME:
5336 case CCISS_SETNODENAME:
5337 case CCISS_GETHEARTBEAT:
5338 case CCISS_GETBUSTYPES:
5339 case CCISS_GETFIRMVER:
5340 case CCISS_GETDRIVVER:
5341 case CCISS_REVALIDVOLS:
5342 case CCISS_DEREGDISK:
5343 case CCISS_REGNEWDISK:
5344 case CCISS_REGNEWD:
5345 case CCISS_RESCANDISK:
5346 case CCISS_GETLUNINFO:
5347 return hpsa_ioctl(dev, cmd, arg);
5348
5349 case CCISS_PASSTHRU32:
5350 return hpsa_ioctl32_passthru(dev, cmd, arg);
5351 case CCISS_BIG_PASSTHRU32:
5352 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5353
5354 default:
5355 return -ENOIOCTLCMD;
5356 }
5357}
edd16368
SC		 5358#endif
5359
5360static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5361{
5362 struct hpsa_pci_info pciinfo;
5363
5364 if (!argp)
5365 return -EINVAL;
5366 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5367 pciinfo.bus = h->pdev->bus->number;
5368 pciinfo.dev_fn = h->pdev->devfn;
5369 pciinfo.board_id = h->board_id;
5370 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5371 return -EFAULT;
5372 return 0;
5373}
5374
5375static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5376{
5377 DriverVer_type DriverVer;
5378 unsigned char vmaj, vmin, vsubmin;
5379 int rc;
5380
5381 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5382 &vmaj, &vmin, &vsubmin);
5383 if (rc != 3) {
5384 dev_info(&h->pdev->dev, "driver version string '%s' "
5385 "unrecognized.", HPSA_DRIVER_VERSION);
5386 vmaj = 0;
5387 vmin = 0;
5388 vsubmin = 0;
5389 }
5390 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5391 if (!argp)
5392 return -EINVAL;
5393 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5394 return -EFAULT;
5395 return 0;
5396}
5397
5398static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5399{
5400 IOCTL_Command_struct iocommand;
5401 struct CommandList *c;
5402 char *buff = NULL;
50a0decf 5403 u64 temp64;
c1f63c8f 5404 int rc = 0;
edd16368
SC		 5405
5406 if (!argp)
5407 return -EINVAL;
5408 if (!capable(CAP_SYS_RAWIO))
5409 return -EPERM;
5410 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5411 return -EFAULT;
5412 if ((iocommand.buf_size < 1) &&
5413 (iocommand.Request.Type.Direction != XFER_NONE)) {
5414 return -EINVAL;
5415 }
5416 if (iocommand.buf_size > 0) {
5417 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5418 if (buff == NULL)
5419 return -EFAULT;
9233fb10 5420 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5421 /* Copy the data into the buffer we created */
5422 if (copy_from_user(buff, iocommand.buf,
5423 iocommand.buf_size)) {
c1f63c8f
SC		 5424 rc = -EFAULT;
5425 goto out_kfree;
b03a7771
SC		 5426 }
5427 } else {
5428 memset(buff, 0, iocommand.buf_size);
edd16368 5429 }
b03a7771 5430 }
45fcb86e 5431 c = cmd_alloc(h);
edd16368 5432 if (c == NULL) {
c1f63c8f
SC		 5433 rc = -ENOMEM;
5434 goto out_kfree;
edd16368
SC		 5435 }
5436 /* Fill in the command type */
5437 c->cmd_type = CMD_IOCTL_PEND;
5438 /* Fill in Command Header */
5439 c->Header.ReplyQueue = 0; /* unused in simple mode */
5440 if (iocommand.buf_size > 0) { /* buffer to fill */
5441 c->Header.SGList = 1;
50a0decf 5442 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5443 } else { /* no buffers to fill */
5444 c->Header.SGList = 0;
50a0decf 5445 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 5446 }
5447 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5448
5449 /* Fill in Request block */
5450 memcpy(&c->Request, &iocommand.Request,
5451 sizeof(c->Request));
5452
5453 /* Fill in the scatter gather information */
5454 if (iocommand.buf_size > 0) {
50a0decf 5455 temp64 = pci_map_single(h->pdev, buff,
edd16368 5456 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5457 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
5458 c->SG[0].Addr = cpu_to_le64(0);
5459 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 5460 rc = -ENOMEM;
5461 goto out;
5462 }
50a0decf
SC		 5463 c->SG[0].Addr = cpu_to_le64(temp64);
5464 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
5465 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 5466 }
25163bd5 5467 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 5468 if (iocommand.buf_size > 0)
5469 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 5470 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5471 if (rc) {
5472 rc = -EIO;
5473 goto out;
5474 }
edd16368
SC		 5475
5476 /* Copy the error information out */
5477 memcpy(&iocommand.error_info, c->err_info,
5478 sizeof(iocommand.error_info));
5479 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 5480 rc = -EFAULT;
5481 goto out;
edd16368 5482 }
9233fb10 5483 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 5484 iocommand.buf_size > 0) {
edd16368
SC		 5485 /* Copy the data out of the buffer we created */
5486 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 5487 rc = -EFAULT;
5488 goto out;
edd16368
SC		 5489 }
5490 }
c1f63c8f 5491out:
45fcb86e 5492 cmd_free(h, c);
c1f63c8f
SC		 5493out_kfree:
5494 kfree(buff);
5495 return rc;
edd16368
SC		 5496}
5497
5498static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5499{
5500 BIG_IOCTL_Command_struct *ioc;
5501 struct CommandList *c;
5502 unsigned char **buff = NULL;
5503 int *buff_size = NULL;
50a0decf 5504 u64 temp64;
edd16368
SC		 5505 BYTE sg_used = 0;
5506 int status = 0;
01a02ffc
SC		 5507 u32 left;
5508 u32 sz;
edd16368
SC		 5509 BYTE __user *data_ptr;
5510
5511 if (!argp)
5512 return -EINVAL;
5513 if (!capable(CAP_SYS_RAWIO))
5514 return -EPERM;
5515 ioc = (BIG_IOCTL_Command_struct *)
5516 kmalloc(sizeof(*ioc), GFP_KERNEL);
5517 if (!ioc) {
5518 status = -ENOMEM;
5519 goto cleanup1;
5520 }
5521 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
5522 status = -EFAULT;
5523 goto cleanup1;
5524 }
5525 if ((ioc->buf_size < 1) &&
5526 (ioc->Request.Type.Direction != XFER_NONE)) {
5527 status = -EINVAL;
5528 goto cleanup1;
5529 }
5530 /* Check kmalloc limits using all SGs */
5531 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
5532 status = -EINVAL;
5533 goto cleanup1;
5534 }
d66ae08b 5535 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 5536 status = -EINVAL;
5537 goto cleanup1;
5538 }
d66ae08b 5539 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 5540 if (!buff) {
5541 status = -ENOMEM;
5542 goto cleanup1;
5543 }
d66ae08b 5544 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 5545 if (!buff_size) {
5546 status = -ENOMEM;
5547 goto cleanup1;
5548 }
5549 left = ioc->buf_size;
5550 data_ptr = ioc->buf;
5551 while (left) {
5552 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
5553 buff_size[sg_used] = sz;
5554 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
5555 if (buff[sg_used] == NULL) {
5556 status = -ENOMEM;
5557 goto cleanup1;
5558 }
9233fb10 5559 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 5560 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 5561 status = -EFAULT;
edd16368
SC		 5562 goto cleanup1;
5563 }
5564 } else
5565 memset(buff[sg_used], 0, sz);
5566 left -= sz;
5567 data_ptr += sz;
5568 sg_used++;
5569 }
45fcb86e 5570 c = cmd_alloc(h);
edd16368
SC		 5571 if (c == NULL) {
5572 status = -ENOMEM;
5573 goto cleanup1;
5574 }
5575 c->cmd_type = CMD_IOCTL_PEND;
5576 c->Header.ReplyQueue = 0;
50a0decf
SC		 5577 c->Header.SGList = (u8) sg_used;
5578 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 5579 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 5580 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
5581 if (ioc->buf_size > 0) {
5582 int i;
5583 for (i = 0; i < sg_used; i++) {
50a0decf 5584 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 5585 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 5586 if (dma_mapping_error(&h->pdev->dev,
5587 (dma_addr_t) temp64)) {
5588 c->SG[i].Addr = cpu_to_le64(0);
5589 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 5590 hpsa_pci_unmap(h->pdev, c, i,
5591 PCI_DMA_BIDIRECTIONAL);
5592 status = -ENOMEM;
e2d4a1f6 5593 goto cleanup0;
bcc48ffa 5594 }
50a0decf
SC		 5595 c->SG[i].Addr = cpu_to_le64(temp64);
5596 c->SG[i].Len = cpu_to_le32(buff_size[i]);
5597 c->SG[i].Ext = cpu_to_le32(0);
edd16368 5598 }
50a0decf 5599 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 5600 }
25163bd5 5601 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 5602 if (sg_used)
5603 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 5604 check_ioctl_unit_attention(h, c);
25163bd5
WS		 5605 if (status) {
5606 status = -EIO;
5607 goto cleanup0;
5608 }
5609
edd16368
SC		 5610 /* Copy the error information out */
5611 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
5612 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 5613 status = -EFAULT;
e2d4a1f6 5614 goto cleanup0;
edd16368 5615 }
9233fb10 5616 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 5617 int i;
5618
edd16368
SC		 5619 /* Copy the data out of the buffer we created */
5620 BYTE __user *ptr = ioc->buf;
5621 for (i = 0; i < sg_used; i++) {
5622 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 5623 status = -EFAULT;
e2d4a1f6 5624 goto cleanup0;
edd16368
SC		 5625 }
5626 ptr += buff_size[i];
5627 }
5628 }
edd16368 5629 status = 0;
e2d4a1f6 5630cleanup0:
45fcb86e 5631 cmd_free(h, c);
edd16368
SC		 5632cleanup1:
5633 if (buff) {
2b08b3e9
DB		 5634 int i;
5635
edd16368
SC		 5636 for (i = 0; i < sg_used; i++)
5637 kfree(buff[i]);
5638 kfree(buff);
5639 }
5640 kfree(buff_size);
5641 kfree(ioc);
5642 return status;
5643}
5644
5645static void check_ioctl_unit_attention(struct ctlr_info *h,
5646 struct CommandList *c)
5647{
5648 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5649 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
5650 (void) check_for_unit_attention(h, c);
5651}
0390f0c0 5652
edd16368
SC		 5653/*
5654 * ioctl
5655 */
42a91641 5656static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 5657{
5658 struct ctlr_info *h;
5659 void __user *argp = (void __user *)arg;
0390f0c0 5660 int rc;
edd16368
SC		 5661
5662 h = sdev_to_hba(dev);
5663
5664 switch (cmd) {
5665 case CCISS_DEREGDISK:
5666 case CCISS_REGNEWDISK:
5667 case CCISS_REGNEWD:
a08a8471 5668 hpsa_scan_start(h->scsi_host);
edd16368
SC		 5669 return 0;
5670 case CCISS_GETPCIINFO:
5671 return hpsa_getpciinfo_ioctl(h, argp);
5672 case CCISS_GETDRIVVER:
5673 return hpsa_getdrivver_ioctl(h, argp);
5674 case CCISS_PASSTHRU:
34f0c627 5675 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5676 return -EAGAIN;
5677 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 5678 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5679 return rc;
edd16368 5680 case CCISS_BIG_PASSTHRU:
34f0c627 5681 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 5682 return -EAGAIN;
5683 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 5684 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 5685 return rc;
edd16368
SC		 5686 default:
5687 return -ENOTTY;
5688 }
5689}
5690
6f039790
GKH		 5691static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
5692 u8 reset_type)
64670ac8
SC		 5693{
5694 struct CommandList *c;
5695
5696 c = cmd_alloc(h);
5697 if (!c)
5698 return -ENOMEM;
a2dac136
SC		 5699 /* fill_cmd can't fail here, no data buffer to map */
5700 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 5701 RAID_CTLR_LUNID, TYPE_MSG);
5702 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
5703 c->waiting = NULL;
5704 enqueue_cmd_and_start_io(h, c);
5705 /* Don't wait for completion, the reset won't complete. Don't free
5706 * the command either. This is the last command we will send before
5707 * re-initializing everything, so it doesn't matter and won't leak.
5708 */
5709 return 0;
5710}
5711
a2dac136 5712static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 5713 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 5714 int cmd_type)
5715{
5716 int pci_dir = XFER_NONE;
9b5c48c2 5717 u64 tag; /* for commands to be aborted */
edd16368
SC		 5718
5719 c->cmd_type = CMD_IOCTL_PEND;
5720 c->Header.ReplyQueue = 0;
5721 if (buff != NULL && size > 0) {
5722 c->Header.SGList = 1;
50a0decf 5723 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 5724 } else {
5725 c->Header.SGList = 0;
50a0decf 5726 c->Header.SGTotal = cpu_to_le16(0);
edd16368 5727 }
edd16368
SC		 5728 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
5729
edd16368
SC		 5730 if (cmd_type == TYPE_CMD) {
5731 switch (cmd) {
5732 case HPSA_INQUIRY:
5733 /* are we trying to read a vital product page */
b7bb24eb 5734 if (page_code & VPD_PAGE) {
edd16368 5735 c->Request.CDB[1] = 0x01;
b7bb24eb 5736 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 5737 }
5738 c->Request.CDBLen = 6;
a505b86f
SC		 5739 c->Request.type_attr_dir =
5740 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5741 c->Request.Timeout = 0;
5742 c->Request.CDB[0] = HPSA_INQUIRY;
5743 c->Request.CDB[4] = size & 0xFF;
5744 break;
5745 case HPSA_REPORT_LOG:
5746 case HPSA_REPORT_PHYS:
5747 /* Talking to controller so It's a physical command
5748 mode = 00 target = 0. Nothing to write.
5749 */
5750 c->Request.CDBLen = 12;
a505b86f
SC		 5751 c->Request.type_attr_dir =
5752 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5753 c->Request.Timeout = 0;
5754 c->Request.CDB[0] = cmd;
5755 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5756 c->Request.CDB[7] = (size >> 16) & 0xFF;
5757 c->Request.CDB[8] = (size >> 8) & 0xFF;
5758 c->Request.CDB[9] = size & 0xFF;
5759 break;
edd16368
SC		 5760 case HPSA_CACHE_FLUSH:
5761 c->Request.CDBLen = 12;
a505b86f
SC		 5762 c->Request.type_attr_dir =
5763 TYPE_ATTR_DIR(cmd_type,
5764 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5765 c->Request.Timeout = 0;
5766 c->Request.CDB[0] = BMIC_WRITE;
5767 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 5768 c->Request.CDB[7] = (size >> 8) & 0xFF;
5769 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 5770 break;
5771 case TEST_UNIT_READY:
5772 c->Request.CDBLen = 6;
a505b86f
SC		 5773 c->Request.type_attr_dir =
5774 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5775 c->Request.Timeout = 0;
5776 break;
283b4a9b
SC		 5777 case HPSA_GET_RAID_MAP:
5778 c->Request.CDBLen = 12;
a505b86f
SC		 5779 c->Request.type_attr_dir =
5780 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 5781 c->Request.Timeout = 0;
5782 c->Request.CDB[0] = HPSA_CISS_READ;
5783 c->Request.CDB[1] = cmd;
5784 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5785 c->Request.CDB[7] = (size >> 16) & 0xFF;
5786 c->Request.CDB[8] = (size >> 8) & 0xFF;
5787 c->Request.CDB[9] = size & 0xFF;
5788 break;
316b221a
SC		 5789 case BMIC_SENSE_CONTROLLER_PARAMETERS:
5790 c->Request.CDBLen = 10;
a505b86f
SC		 5791 c->Request.type_attr_dir =
5792 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 5793 c->Request.Timeout = 0;
5794 c->Request.CDB[0] = BMIC_READ;
5795 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
5796 c->Request.CDB[7] = (size >> 16) & 0xFF;
5797 c->Request.CDB[8] = (size >> 8) & 0xFF;
5798 break;
03383736
DB		 5799 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
5800 c->Request.CDBLen = 10;
5801 c->Request.type_attr_dir =
5802 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
5803 c->Request.Timeout = 0;
5804 c->Request.CDB[0] = BMIC_READ;
5805 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
5806 c->Request.CDB[7] = (size >> 16) & 0xFF;
5807 c->Request.CDB[8] = (size >> 8) & 0XFF;
5808 break;
edd16368
SC		 5809 default:
5810 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5811 BUG();
a2dac136 5812 return -1;
edd16368
SC		 5813 }
5814 } else if (cmd_type == TYPE_MSG) {
5815 switch (cmd) {
5816
5817 case HPSA_DEVICE_RESET_MSG:
5818 c->Request.CDBLen = 16;
a505b86f
SC		 5819 c->Request.type_attr_dir =
5820 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 5821 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5822 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5823 c->Request.CDB[0] = cmd;
21e89afd 5824 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5825 /* If bytes 4-7 are zero, it means reset the */
5826 /* LunID device */
5827 c->Request.CDB[4] = 0x00;
5828 c->Request.CDB[5] = 0x00;
5829 c->Request.CDB[6] = 0x00;
5830 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5831 break;
5832 case HPSA_ABORT_MSG:
9b5c48c2 5833 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 5834 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 5835 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
5836 tag, c->Header.tag);
75167d2c 5837 c->Request.CDBLen = 16;
a505b86f
SC		 5838 c->Request.type_attr_dir =
5839 TYPE_ATTR_DIR(cmd_type,
5840 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 5841 c->Request.Timeout = 0; /* Don't time out */
5842 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5843 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5844 c->Request.CDB[2] = 0x00; /* reserved */
5845 c->Request.CDB[3] = 0x00; /* reserved */
5846 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 5847 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 5848 c->Request.CDB[12] = 0x00; /* reserved */
5849 c->Request.CDB[13] = 0x00; /* reserved */
5850 c->Request.CDB[14] = 0x00; /* reserved */
5851 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5852 break;
edd16368
SC		 5853 default:
5854 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5855 cmd);
5856 BUG();
5857 }
5858 } else {
5859 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5860 BUG();
5861 }
5862
a505b86f 5863 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 5864 case XFER_READ:
5865 pci_dir = PCI_DMA_FROMDEVICE;
5866 break;
5867 case XFER_WRITE:
5868 pci_dir = PCI_DMA_TODEVICE;
5869 break;
5870 case XFER_NONE:
5871 pci_dir = PCI_DMA_NONE;
5872 break;
5873 default:
5874 pci_dir = PCI_DMA_BIDIRECTIONAL;
5875 }
a2dac136
SC		 5876 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5877 return -1;
5878 return 0;
edd16368
SC		 5879}
5880
5881/*
5882 * Map (physical) PCI mem into (virtual) kernel space
5883 */
5884static void __iomem *remap_pci_mem(ulong base, ulong size)
5885{
5886 ulong page_base = ((ulong) base) & PAGE_MASK;
5887 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5888 void __iomem *page_remapped = ioremap_nocache(page_base,
5889 page_offs + size);
edd16368
SC		 5890
5891 return page_remapped ? (page_remapped + page_offs) : NULL;
5892}
5893
254f796b 5894static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5895{
254f796b 5896 return h->access.command_completed(h, q);
edd16368
SC		 5897}
5898
900c5440 5899static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5900{
5901 return h->access.intr_pending(h);
5902}
5903
5904static inline long interrupt_not_for_us(struct ctlr_info *h)
5905{
10f66018
SC		 5906 return (h->access.intr_pending(h) == 0) ||
5907 (h->interrupts_enabled == 0);
edd16368
SC		 5908}
5909
01a02ffc
SC		 5910static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5911 u32 raw_tag)
edd16368
SC		 5912{
5913 if (unlikely(tag_index >= h->nr_cmds)) {
5914 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5915 return 1;
5916 }
5917 return 0;
5918}
5919
5a3d16f5 5920static inline void finish_cmd(struct CommandList *c)
edd16368 5921{
e85c5974 5922 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5923 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5924 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5925 complete_scsi_command(c);
edd16368
SC		 5926 else if (c->cmd_type == CMD_IOCTL_PEND)
5927 complete(c->waiting);
a104c99f
SC		 5928}
5929
a9a3a273
SC		 5930
5931static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5932{
a9a3a273
SC		 5933#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5934#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5935 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5936 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5937 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5938}
5939
303932fd 5940/* process completion of an indexed ("direct lookup") command */
1d94f94d 5941static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5942 u32 raw_tag)
5943{
5944 u32 tag_index;
5945 struct CommandList *c;
5946
f2405db8 5947 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 5948 if (!bad_tag(h, tag_index, raw_tag)) {
5949 c = h->cmd_pool + tag_index;
5950 finish_cmd(c);
5951 }
303932fd
DB		 5952}
5953
64670ac8
SC		 5954/* Some controllers, like p400, will give us one interrupt
5955 * after a soft reset, even if we turned interrupts off.
5956 * Only need to check for this in the hpsa_xxx_discard_completions
5957 * functions.
5958 */
5959static int ignore_bogus_interrupt(struct ctlr_info *h)
5960{
5961 if (likely(!reset_devices))
5962 return 0;
5963
5964 if (likely(h->interrupts_enabled))
5965 return 0;
5966
5967 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5968 "(known firmware bug.) Ignoring.\n");
5969
5970 return 1;
5971}
5972
254f796b
MG		 5973/*
5974 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5975 * Relies on (h-q[x] == x) being true for x such that
5976 * 0 <= x < MAX_REPLY_QUEUES.
5977 */
5978static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5979{
254f796b
MG		 5980 return container_of((queue - *queue), struct ctlr_info, q[0]);
5981}
5982
5983static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5984{
5985 struct ctlr_info *h = queue_to_hba(queue);
5986 u8 q = *(u8 *) queue;
64670ac8
SC		 5987 u32 raw_tag;
5988
5989 if (ignore_bogus_interrupt(h))
5990 return IRQ_NONE;
5991
5992 if (interrupt_not_for_us(h))
5993 return IRQ_NONE;
a0c12413 5994 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5995 while (interrupt_pending(h)) {
254f796b 5996 raw_tag = get_next_completion(h, q);
64670ac8 5997 while (raw_tag != FIFO_EMPTY)
254f796b 5998 raw_tag = next_command(h, q);
64670ac8 5999 }
64670ac8
SC		 6000 return IRQ_HANDLED;
6001}
6002
254f796b 6003static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6004{
254f796b 6005 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6006 u32 raw_tag;
254f796b 6007 u8 q = *(u8 *) queue;
64670ac8
SC		 6008
6009 if (ignore_bogus_interrupt(h))
6010 return IRQ_NONE;
6011
a0c12413 6012 h->last_intr_timestamp = get_jiffies_64();
254f796b 6013 raw_tag = get_next_completion(h, q);
64670ac8 6014 while (raw_tag != FIFO_EMPTY)
254f796b 6015 raw_tag = next_command(h, q);
64670ac8
SC		 6016 return IRQ_HANDLED;
6017}
6018
254f796b 6019static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6020{
254f796b 6021 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6022 u32 raw_tag;
254f796b 6023 u8 q = *(u8 *) queue;
edd16368
SC		 6024
6025 if (interrupt_not_for_us(h))
6026 return IRQ_NONE;
a0c12413 6027 h->last_intr_timestamp = get_jiffies_64();
10f66018 6028 while (interrupt_pending(h)) {
254f796b 6029 raw_tag = get_next_completion(h, q);
10f66018 6030 while (raw_tag != FIFO_EMPTY) {
f2405db8 6031 process_indexed_cmd(h, raw_tag);
254f796b 6032 raw_tag = next_command(h, q);
10f66018
SC		 6033 }
6034 }
10f66018
SC		 6035 return IRQ_HANDLED;
6036}
6037
254f796b 6038static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6039{
254f796b 6040 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6041 u32 raw_tag;
254f796b 6042 u8 q = *(u8 *) queue;
10f66018 6043
a0c12413 6044 h->last_intr_timestamp = get_jiffies_64();
254f796b 6045 raw_tag = get_next_completion(h, q);
303932fd 6046 while (raw_tag != FIFO_EMPTY) {
f2405db8 6047 process_indexed_cmd(h, raw_tag);
254f796b 6048 raw_tag = next_command(h, q);
edd16368 6049 }
edd16368
SC		 6050 return IRQ_HANDLED;
6051}
6052
a9a3a273
SC		 6053/* Send a message CDB to the firmware. Careful, this only works
6054 * in simple mode, not performant mode due to the tag lookup.
6055 * We only ever use this immediately after a controller reset.
6056 */
6f039790
GKH		 6057static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6058 unsigned char type)
edd16368
SC		 6059{
6060 struct Command {
6061 struct CommandListHeader CommandHeader;
6062 struct RequestBlock Request;
6063 struct ErrDescriptor ErrorDescriptor;
6064 };
6065 struct Command *cmd;
6066 static const size_t cmd_sz = sizeof(*cmd) +
6067 sizeof(cmd->ErrorDescriptor);
6068 dma_addr_t paddr64;
2b08b3e9
DB		 6069 __le32 paddr32;
6070 u32 tag;
edd16368
SC		 6071 void __iomem *vaddr;
6072 int i, err;
6073
6074 vaddr = pci_ioremap_bar(pdev, 0);
6075 if (vaddr == NULL)
6076 return -ENOMEM;
6077
6078 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6079 * CCISS commands, so they must be allocated from the lower 4GiB of
6080 * memory.
6081 */
6082 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6083 if (err) {
6084 iounmap(vaddr);
1eaec8f3 6085 return err;
edd16368
SC		 6086 }
6087
6088 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6089 if (cmd == NULL) {
6090 iounmap(vaddr);
6091 return -ENOMEM;
6092 }
6093
6094 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6095 * although there's no guarantee, we assume that the address is at
6096 * least 4-byte aligned (most likely, it's page-aligned).
6097 */
2b08b3e9 6098 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6099
6100 cmd->CommandHeader.ReplyQueue = 0;
6101 cmd->CommandHeader.SGList = 0;
50a0decf 6102 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6103 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6104 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6105
6106 cmd->Request.CDBLen = 16;
a505b86f
SC		 6107 cmd->Request.type_attr_dir =
6108 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6109 cmd->Request.Timeout = 0; /* Don't time out */
6110 cmd->Request.CDB[0] = opcode;
6111 cmd->Request.CDB[1] = type;
6112 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6113 cmd->ErrorDescriptor.Addr =
2b08b3e9 6114 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6115 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6116
2b08b3e9 6117 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6118
6119 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6120 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6121 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6122 break;
6123 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6124 }
6125
6126 iounmap(vaddr);
6127
6128 /* we leak the DMA buffer here ... no choice since the controller could
6129 * still complete the command.
6130 */
6131 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6132 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6133 opcode, type);
6134 return -ETIMEDOUT;
6135 }
6136
6137 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6138
6139 if (tag & HPSA_ERROR_BIT) {
6140 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6141 opcode, type);
6142 return -EIO;
6143 }
6144
6145 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6146 opcode, type);
6147 return 0;
6148}
6149
edd16368
SC		 6150#define hpsa_noop(p) hpsa_message(p, 3, 0)
6151
1df8552a 6152static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6153 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6154{
1df8552a
SC		 6155
6156 if (use_doorbell) {
6157 /* For everything after the P600, the PCI power state method
6158 * of resetting the controller doesn't work, so we have this
6159 * other way using the doorbell register.
6160 */
6161 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6162 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6163
00701a96 6164 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6165 * doorbell reset and before any attempt to talk to the board
6166 * at all to ensure that this actually works and doesn't fall
6167 * over in some weird corner cases.
6168 */
00701a96 6169 msleep(10000);
1df8552a
SC		 6170 } else { /* Try to do it the PCI power state way */
6171
6172 /* Quoting from the Open CISS Specification: "The Power
6173 * Management Control/Status Register (CSR) controls the power
6174 * state of the device. The normal operating state is D0,
6175 * CSR=00h. The software off state is D3, CSR=03h. To reset
6176 * the controller, place the interface device in D3 then to D0,
6177 * this causes a secondary PCI reset which will reset the
6178 * controller." */
2662cab8
DB		 6179
6180 int rc = 0;
6181
1df8552a 6182 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6183
1df8552a 6184 /* enter the D3hot power management state */
2662cab8
DB		 6185 rc = pci_set_power_state(pdev, PCI_D3hot);
6186 if (rc)
6187 return rc;
1df8552a
SC		 6188
6189 msleep(500);
6190
6191 /* enter the D0 power management state */
2662cab8
DB		 6192 rc = pci_set_power_state(pdev, PCI_D0);
6193 if (rc)
6194 return rc;
c4853efe
MM		 6195
6196 /*
6197 * The P600 requires a small delay when changing states.
6198 * Otherwise we may think the board did not reset and we bail.
6199 * This for kdump only and is particular to the P600.
6200 */
6201 msleep(500);
1df8552a
SC		 6202 }
6203 return 0;
6204}
6205
6f039790 6206static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6207{
6208 memset(driver_version, 0, len);
f79cfec6 6209 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6210}
6211
6f039790 6212static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6213{
6214 char *driver_version;
6215 int i, size = sizeof(cfgtable->driver_version);
6216
6217 driver_version = kmalloc(size, GFP_KERNEL);
6218 if (!driver_version)
6219 return -ENOMEM;
6220
6221 init_driver_version(driver_version, size);
6222 for (i = 0; i < size; i++)
6223 writeb(driver_version[i], &cfgtable->driver_version[i]);
6224 kfree(driver_version);
6225 return 0;
6226}
6227
6f039790
GKH		 6228static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6229 unsigned char *driver_ver)
580ada3c
SC		 6230{
6231 int i;
6232
6233 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6234 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6235}
6236
6f039790 6237static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6238{
6239
6240 char *driver_ver, *old_driver_ver;
6241 int rc, size = sizeof(cfgtable->driver_version);
6242
6243 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6244 if (!old_driver_ver)
6245 return -ENOMEM;
6246 driver_ver = old_driver_ver + size;
6247
6248 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6249 * should have been changed, otherwise we know the reset failed.
6250 */
6251 init_driver_version(old_driver_ver, size);
6252 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6253 rc = !memcmp(driver_ver, old_driver_ver, size);
6254 kfree(old_driver_ver);
6255 return rc;
6256}
edd16368 6257/* This does a hard reset of the controller using PCI power management
1df8552a 6258 * states or the using the doorbell register.
edd16368 6259 */
6b6c1cd7 6260static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6261{
1df8552a
SC		 6262 u64 cfg_offset;
6263 u32 cfg_base_addr;
6264 u64 cfg_base_addr_index;
6265 void __iomem *vaddr;
6266 unsigned long paddr;
580ada3c 6267 u32 misc_fw_support;
270d05de 6268 int rc;
1df8552a 6269 struct CfgTable __iomem *cfgtable;
cf0b08d0 6270 u32 use_doorbell;
270d05de 6271 u16 command_register;
edd16368 6272
1df8552a
SC		 6273 /* For controllers as old as the P600, this is very nearly
6274 * the same thing as
edd16368
SC		 6275 *
6276 * pci_save_state(pci_dev);
6277 * pci_set_power_state(pci_dev, PCI_D3hot);
6278 * pci_set_power_state(pci_dev, PCI_D0);
6279 * pci_restore_state(pci_dev);
6280 *
1df8552a
SC		 6281 * For controllers newer than the P600, the pci power state
6282 * method of resetting doesn't work so we have another way
6283 * using the doorbell register.
edd16368 6284 */
18867659 6285
60f923b9
RE		 6286 if (!ctlr_is_resettable(board_id)) {
6287 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6288 return -ENODEV;
6289 }
46380786
SC		 6290
6291 /* if controller is soft- but not hard resettable... */
6292 if (!ctlr_is_hard_resettable(board_id))
6293 return -ENOTSUPP; /* try soft reset later. */
18867659 6294
270d05de
SC		 6295 /* Save the PCI command register */
6296 pci_read_config_word(pdev, 4, &command_register);
270d05de 6297 pci_save_state(pdev);
edd16368 6298
1df8552a
SC		 6299 /* find the first memory BAR, so we can find the cfg table */
6300 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6301 if (rc)
6302 return rc;
6303 vaddr = remap_pci_mem(paddr, 0x250);
6304 if (!vaddr)
6305 return -ENOMEM;
edd16368 6306
1df8552a
SC		 6307 /* find cfgtable in order to check if reset via doorbell is supported */
6308 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6309 &cfg_base_addr_index, &cfg_offset);
6310 if (rc)
6311 goto unmap_vaddr;
6312 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6313 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6314 if (!cfgtable) {
6315 rc = -ENOMEM;
6316 goto unmap_vaddr;
6317 }
580ada3c
SC		 6318 rc = write_driver_ver_to_cfgtable(cfgtable);
6319 if (rc)
03741d95 6320 goto unmap_cfgtable;
edd16368 6321
cf0b08d0
SC		 6322 /* If reset via doorbell register is supported, use that.
6323 * There are two such methods. Favor the newest method.
6324 */
1df8552a 6325 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6326 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6327 if (use_doorbell) {
6328 use_doorbell = DOORBELL_CTLR_RESET2;
6329 } else {
6330 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6331 if (use_doorbell) {
050f7147
SC		 6332 dev_warn(&pdev->dev,
6333 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6334 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6335 goto unmap_cfgtable;
6336 }
6337 }
edd16368 6338
1df8552a
SC		 6339 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6340 if (rc)
6341 goto unmap_cfgtable;
edd16368 6342
270d05de 6343 pci_restore_state(pdev);
270d05de 6344 pci_write_config_word(pdev, 4, command_register);
edd16368 6345
1df8552a
SC		 6346 /* Some devices (notably the HP Smart Array 5i Controller)
6347 need a little pause here */
6348 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6349
fe5389c8
SC		 6350 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6351 if (rc) {
6352 dev_warn(&pdev->dev,
050f7147 6353 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6354 goto unmap_cfgtable;
6355 }
fe5389c8 6356
580ada3c
SC		 6357 rc = controller_reset_failed(vaddr);
6358 if (rc < 0)
6359 goto unmap_cfgtable;
6360 if (rc) {
64670ac8
SC		 6361 dev_warn(&pdev->dev, "Unable to successfully reset "
6362 "controller. Will try soft reset.\n");
6363 rc = -ENOTSUPP;
580ada3c 6364 } else {
64670ac8 6365 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6366 }
6367
6368unmap_cfgtable:
6369 iounmap(cfgtable);
6370
6371unmap_vaddr:
6372 iounmap(vaddr);
6373 return rc;
edd16368
SC		 6374}
6375
6376/*
6377 * We cannot read the structure directly, for portability we must use
6378 * the io functions.
6379 * This is for debug only.
6380 */
42a91641 6381static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6382{
58f8665c 6383#ifdef HPSA_DEBUG
edd16368
SC		 6384 int i;
6385 char temp_name[17];
6386
6387 dev_info(dev, "Controller Configuration information\n");
6388 dev_info(dev, "------------------------------------\n");
6389 for (i = 0; i < 4; i++)
6390 temp_name[i] = readb(&(tb->Signature[i]));
6391 temp_name[4] = '\0';
6392 dev_info(dev, " Signature = %s\n", temp_name);
6393 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6394 dev_info(dev, " Transport methods supported = 0x%x\n",
6395 readl(&(tb->TransportSupport)));
6396 dev_info(dev, " Transport methods active = 0x%x\n",
6397 readl(&(tb->TransportActive)));
6398 dev_info(dev, " Requested transport Method = 0x%x\n",
6399 readl(&(tb->HostWrite.TransportRequest)));
6400 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6401 readl(&(tb->HostWrite.CoalIntDelay)));
6402 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6403 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6404 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6405 readl(&(tb->CmdsOutMax)));
6406 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6407 for (i = 0; i < 16; i++)
6408 temp_name[i] = readb(&(tb->ServerName[i]));
6409 temp_name[16] = '\0';
6410 dev_info(dev, " Server Name = %s\n", temp_name);
6411 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6412 readl(&(tb->HeartBeat)));
edd16368 6413#endif /* HPSA_DEBUG */
58f8665c 6414}
edd16368
SC		 6415
6416static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6417{
6418 int i, offset, mem_type, bar_type;
6419
6420 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6421 return 0;
6422 offset = 0;
6423 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
6424 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
6425 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
6426 offset += 4;
6427 else {
6428 mem_type = pci_resource_flags(pdev, i) &
6429 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
6430 switch (mem_type) {
6431 case PCI_BASE_ADDRESS_MEM_TYPE_32:
6432 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
6433 offset += 4; /* 32 bit */
6434 break;
6435 case PCI_BASE_ADDRESS_MEM_TYPE_64:
6436 offset += 8;
6437 break;
6438 default: /* reserved in PCI 2.2 */
6439 dev_warn(&pdev->dev,
6440 "base address is invalid\n");
6441 return -1;
6442 break;
6443 }
6444 }
6445 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
6446 return i + 1;
6447 }
6448 return -1;
6449}
6450
cc64c817
RE		 6451static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
6452{
6453 if (h->msix_vector) {
6454 if (h->pdev->msix_enabled)
6455 pci_disable_msix(h->pdev);
6456 } else if (h->msi_vector) {
6457 if (h->pdev->msi_enabled)
6458 pci_disable_msi(h->pdev);
6459 }
6460}
6461
edd16368 6462/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 6463 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 6464 */
6f039790 6465static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 6466{
6467#ifdef CONFIG_PCI_MSI
254f796b
MG		 6468 int err, i;
6469 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
6470
6471 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
6472 hpsa_msix_entries[i].vector = 0;
6473 hpsa_msix_entries[i].entry = i;
6474 }
edd16368
SC		 6475
6476 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 6477 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
6478 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 6479 goto default_int_mode;
55c06c71 6480 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 6481 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 6482 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 6483 if (h->msix_vector > num_online_cpus())
6484 h->msix_vector = num_online_cpus();
18fce3c4
AG		 6485 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
6486 1, h->msix_vector);
6487 if (err < 0) {
6488 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
6489 h->msix_vector = 0;
6490 goto single_msi_mode;
6491 } else if (err < h->msix_vector) {
55c06c71 6492 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 6493 "available\n", err);
edd16368 6494 }
18fce3c4
AG		 6495 h->msix_vector = err;
6496 for (i = 0; i < h->msix_vector; i++)
6497 h->intr[i] = hpsa_msix_entries[i].vector;
6498 return;
edd16368 6499 }
18fce3c4 6500single_msi_mode:
55c06c71 6501 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 6502 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 6503 if (!pci_enable_msi(h->pdev))
edd16368
SC		 6504 h->msi_vector = 1;
6505 else
55c06c71 6506 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 6507 }
6508default_int_mode:
6509#endif /* CONFIG_PCI_MSI */
6510 /* if we get here we're going to use the default interrupt mode */
a9a3a273 6511 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 6512}
6513
6f039790 6514static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 6515{
6516 int i;
6517 u32 subsystem_vendor_id, subsystem_device_id;
6518
6519 subsystem_vendor_id = pdev->subsystem_vendor;
6520 subsystem_device_id = pdev->subsystem_device;
6521 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
6522 subsystem_vendor_id;
6523
6524 for (i = 0; i < ARRAY_SIZE(products); i++)
6525 if (*board_id == products[i].board_id)
6526 return i;
6527
6798cc0a
SC		 6528 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
6529 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
6530 !hpsa_allow_any) {
e5c880d1
SC		 6531 dev_warn(&pdev->dev, "unrecognized board ID: "
6532 "0x%08x, ignoring.\n", *board_id);
6533 return -ENODEV;
6534 }
6535 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
6536}
6537
6f039790
GKH		 6538static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
6539 unsigned long *memory_bar)
3a7774ce
SC		 6540{
6541 int i;
6542
6543 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 6544 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 6545 /* addressing mode bits already removed */
12d2cd47
SC		 6546 *memory_bar = pci_resource_start(pdev, i);
6547 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 6548 *memory_bar);
6549 return 0;
6550 }
12d2cd47 6551 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 6552 return -ENODEV;
6553}
6554
6f039790
GKH		 6555static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
6556 int wait_for_ready)
2c4c8c8b 6557{
fe5389c8 6558 int i, iterations;
2c4c8c8b 6559 u32 scratchpad;
fe5389c8
SC		 6560 if (wait_for_ready)
6561 iterations = HPSA_BOARD_READY_ITERATIONS;
6562 else
6563 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 6564
fe5389c8
SC		 6565 for (i = 0; i < iterations; i++) {
6566 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
6567 if (wait_for_ready) {
6568 if (scratchpad == HPSA_FIRMWARE_READY)
6569 return 0;
6570 } else {
6571 if (scratchpad != HPSA_FIRMWARE_READY)
6572 return 0;
6573 }
2c4c8c8b
SC		 6574 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
6575 }
fe5389c8 6576 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 6577 return -ENODEV;
6578}
6579
6f039790
GKH		 6580static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
6581 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
6582 u64 *cfg_offset)
a51fd47f
SC		 6583{
6584 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
6585 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
6586 *cfg_base_addr &= (u32) 0x0000ffff;
6587 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
6588 if (*cfg_base_addr_index == -1) {
6589 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
6590 return -ENODEV;
6591 }
6592 return 0;
6593}
6594
195f2c65
RE		 6595static void hpsa_free_cfgtables(struct ctlr_info *h)
6596{
6597 if (h->transtable)
6598 iounmap(h->transtable);
6599 if (h->cfgtable)
6600 iounmap(h->cfgtable);
6601}
6602
6603/* Find and map CISS config table and transfer table
6604+ * several items must be unmapped (freed) later
6605+ * */
6f039790 6606static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 6607{
01a02ffc
SC		 6608 u64 cfg_offset;
6609 u32 cfg_base_addr;
6610 u64 cfg_base_addr_index;
303932fd 6611 u32 trans_offset;
a51fd47f 6612 int rc;
77c4495c 6613
a51fd47f
SC		 6614 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6615 &cfg_base_addr_index, &cfg_offset);
6616 if (rc)
6617 return rc;
77c4495c 6618 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 6619 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 6620 if (!h->cfgtable) {
6621 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 6622 return -ENOMEM;
cd3c81c4 6623 }
580ada3c
SC		 6624 rc = write_driver_ver_to_cfgtable(h->cfgtable);
6625 if (rc)
6626 return rc;
77c4495c 6627 /* Find performant mode table. */
a51fd47f 6628 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 6629 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
6630 cfg_base_addr_index)+cfg_offset+trans_offset,
6631 sizeof(*h->transtable));
195f2c65
RE		 6632 if (!h->transtable) {
6633 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
6634 hpsa_free_cfgtables(h);
77c4495c 6635 return -ENOMEM;
195f2c65 6636 }
77c4495c
SC		 6637 return 0;
6638}
6639
6f039790 6640static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 6641{
41ce4c35
SC		 6642#define MIN_MAX_COMMANDS 16
6643 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
6644
6645 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 6646
6647 /* Limit commands in memory limited kdump scenario. */
6648 if (reset_devices && h->max_commands > 32)
6649 h->max_commands = 32;
6650
41ce4c35
SC		 6651 if (h->max_commands < MIN_MAX_COMMANDS) {
6652 dev_warn(&h->pdev->dev,
6653 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
6654 h->max_commands,
6655 MIN_MAX_COMMANDS);
6656 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 6657 }
6658}
6659
c7ee65b3
WS		 6660/* If the controller reports that the total max sg entries is greater than 512,
6661 * then we know that chained SG blocks work. (Original smart arrays did not
6662 * support chained SG blocks and would return zero for max sg entries.)
6663 */
6664static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
6665{
6666 return h->maxsgentries > 512;
6667}
6668
b93d7536
SC		 6669/* Interrogate the hardware for some limits:
6670 * max commands, max SG elements without chaining, and with chaining,
6671 * SG chain block size, etc.
6672 */
6f039790 6673static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 6674{
cba3d38b 6675 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 6676 h->nr_cmds = h->max_commands;
b93d7536 6677 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 6678 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 6679 if (hpsa_supports_chained_sg_blocks(h)) {
6680 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 6681 h->max_cmd_sg_entries = 32;
1a63ea6f 6682 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 6683 h->maxsgentries--; /* save one for chain pointer */
6684 } else {
c7ee65b3
WS		 6685 /*
6686 * Original smart arrays supported at most 31 s/g entries
6687 * embedded inline in the command (trying to use more
6688 * would lock up the controller)
6689 */
6690 h->max_cmd_sg_entries = 31;
1a63ea6f 6691 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 6692 h->chainsize = 0;
b93d7536 6693 }
75167d2c
SC		 6694
6695 /* Find out what task management functions are supported and cache */
6696 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6697 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6698 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6699 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6700 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6701}
6702
76c46e49
SC		 6703static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6704{
0fc9fd40 6705 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 6706 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 6707 return false;
6708 }
6709 return true;
6710}
6711
97a5e98c 6712static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6713{
97a5e98c 6714 u32 driver_support;
f7c39101 6715
97a5e98c 6716 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 6717 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
6718#ifdef CONFIG_X86
97a5e98c 6719 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6720#endif
28e13446
SC		 6721 driver_support |= ENABLE_UNIT_ATTN;
6722 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6723}
6724
3d0eab67
SC		 6725/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6726 * in a prefetch beyond physical memory.
6727 */
6728static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6729{
6730 u32 dma_prefetch;
6731
6732 if (h->board_id != 0x3225103C)
6733 return;
6734 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6735 dma_prefetch |= 0x8000;
6736 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6737}
6738
c706a795 6739static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 6740{
6741 int i;
6742 u32 doorbell_value;
6743 unsigned long flags;
6744 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 6745 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 6746 spin_lock_irqsave(&h->lock, flags);
6747 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6748 spin_unlock_irqrestore(&h->lock, flags);
6749 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 6750 goto done;
76438d08 6751 /* delay and try again */
007e7aa9 6752 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 6753 }
c706a795
RE		 6754 return -ENODEV;
6755done:
6756 return 0;
76438d08
SC		 6757}
6758
c706a795 6759static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6760{
6761 int i;
6eaf46fd
SC		 6762 u32 doorbell_value;
6763 unsigned long flags;
eb6b2ae9
SC		 6764
6765 /* under certain very rare conditions, this can take awhile.
6766 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6767 * as we enter this code.)
6768 */
007e7aa9 6769 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 6770 if (h->remove_in_progress)
6771 goto done;
6eaf46fd
SC		 6772 spin_lock_irqsave(&h->lock, flags);
6773 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6774 spin_unlock_irqrestore(&h->lock, flags);
382be668 6775 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 6776 goto done;
eb6b2ae9 6777 /* delay and try again */
007e7aa9 6778 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 6779 }
c706a795
RE		 6780 return -ENODEV;
6781done:
6782 return 0;
3f4336f3
SC		 6783}
6784
c706a795 6785/* return -ENODEV or other reason on error, 0 on success */
6f039790 6786static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6787{
6788 u32 trans_support;
6789
6790 trans_support = readl(&(h->cfgtable->TransportSupport));
6791 if (!(trans_support & SIMPLE_MODE))
6792 return -ENOTSUPP;
6793
6794 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6795
3f4336f3
SC		 6796 /* Update the field, and then ring the doorbell */
6797 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6798 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 6799 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 6800 if (hpsa_wait_for_mode_change_ack(h))
6801 goto error;
eb6b2ae9 6802 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6803 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6804 goto error;
960a30e7 6805 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6806 return 0;
283b4a9b 6807error:
050f7147 6808 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 6809 return -ENODEV;
eb6b2ae9
SC		 6810}
6811
195f2c65
RE		 6812/* free items allocated or mapped by hpsa_pci_init */
6813static void hpsa_free_pci_init(struct ctlr_info *h)
6814{
6815 hpsa_free_cfgtables(h); /* pci_init 4 */
6816 iounmap(h->vaddr); /* pci_init 3 */
6817 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
6818 pci_release_regions(h->pdev); /* pci_init 2 */
6819 pci_disable_device(h->pdev); /* pci_init 1 */
6820}
6821
6822/* several items must be freed later */
6f039790 6823static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6824{
eb6b2ae9 6825 int prod_index, err;
edd16368 6826
e5c880d1
SC		 6827 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6828 if (prod_index < 0)
60f923b9 6829 return prod_index;
e5c880d1
SC		 6830 h->product_name = products[prod_index].product_name;
6831 h->access = *(products[prod_index].access);
edd16368 6832
9b5c48c2
SC		 6833 h->needs_abort_tags_swizzled =
6834 ctlr_needs_abort_tags_swizzled(h->board_id);
6835
e5a44df8
MG		 6836 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6837 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6838
55c06c71 6839 err = pci_enable_device(h->pdev);
edd16368 6840 if (err) {
195f2c65 6841 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
edd16368
SC		 6842 return err;
6843 }
6844
f79cfec6 6845 err = pci_request_regions(h->pdev, HPSA);
edd16368 6846 if (err) {
55c06c71 6847 dev_err(&h->pdev->dev,
195f2c65
RE		 6848 "failed to obtain PCI resources\n");
6849 goto clean1; /* pci */
edd16368 6850 }
4fa604e1
RE		 6851
6852 pci_set_master(h->pdev);
6853
6b3f4c52 6854 hpsa_interrupt_mode(h);
12d2cd47 6855 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6856 if (err)
195f2c65 6857 goto clean2; /* intmode+region, pci */
edd16368 6858 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 6859 if (!h->vaddr) {
195f2c65 6860 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 6861 err = -ENOMEM;
195f2c65 6862 goto clean2; /* intmode+region, pci */
204892e9 6863 }
fe5389c8 6864 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6865 if (err)
195f2c65 6866 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 6867 err = hpsa_find_cfgtables(h);
6868 if (err)
195f2c65 6869 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 6870 hpsa_find_board_params(h);
edd16368 6871
76c46e49 6872 if (!hpsa_CISS_signature_present(h)) {
edd16368 6873 err = -ENODEV;
195f2c65 6874 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 6875 }
97a5e98c 6876 hpsa_set_driver_support_bits(h);
3d0eab67 6877 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6878 err = hpsa_enter_simple_mode(h);
6879 if (err)
195f2c65 6880 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 6881 return 0;
6882
195f2c65
RE		 6883clean4: /* cfgtables, vaddr, intmode+region, pci */
6884 hpsa_free_cfgtables(h);
6885clean3: /* vaddr, intmode+region, pci */
6886 iounmap(h->vaddr);
6887clean2: /* intmode+region, pci */
6888 hpsa_disable_interrupt_mode(h);
55c06c71 6889 pci_release_regions(h->pdev);
195f2c65
RE		 6890clean1: /* pci */
6891 pci_disable_device(h->pdev);
edd16368
SC		 6892 return err;
6893}
6894
6f039790 6895static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6896{
6897 int rc;
6898
6899#define HBA_INQUIRY_BYTE_COUNT 64
6900 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6901 if (!h->hba_inquiry_data)
6902 return;
6903 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6904 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6905 if (rc != 0) {
6906 kfree(h->hba_inquiry_data);
6907 h->hba_inquiry_data = NULL;
6908 }
6909}
6910
6b6c1cd7 6911static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 6912{
1df8552a 6913 int rc, i;
3b747298 6914 void __iomem *vaddr;
4c2a8c40
SC		 6915
6916 if (!reset_devices)
6917 return 0;
6918
132aa220
TH		 6919 /* kdump kernel is loading, we don't know in which state is
6920 * the pci interface. The dev->enable_cnt is equal zero
6921 * so we call enable+disable, wait a while and switch it on.
6922 */
6923 rc = pci_enable_device(pdev);
6924 if (rc) {
6925 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
6926 return -ENODEV;
6927 }
6928 pci_disable_device(pdev);
6929 msleep(260); /* a randomly chosen number */
6930 rc = pci_enable_device(pdev);
6931 if (rc) {
6932 dev_warn(&pdev->dev, "failed to enable device.\n");
6933 return -ENODEV;
6934 }
4fa604e1 6935
859c75ab 6936 pci_set_master(pdev);
4fa604e1 6937
3b747298
TH		 6938 vaddr = pci_ioremap_bar(pdev, 0);
6939 if (vaddr == NULL) {
6940 rc = -ENOMEM;
6941 goto out_disable;
6942 }
6943 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
6944 iounmap(vaddr);
6945
1df8552a 6946 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 6947 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 6948
1df8552a
SC		 6949 /* -ENOTSUPP here means we cannot reset the controller
6950 * but it's already (and still) up and running in
18867659
SC		 6951 * "performant mode". Or, it might be 640x, which can't reset
6952 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 6953 */
adf1b3a3 6954 if (rc)
132aa220 6955 goto out_disable;
4c2a8c40
SC		 6956
6957 /* Now try to get the controller to respond to a no-op */
1ba66c9c 6958 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6959 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6960 if (hpsa_noop(pdev) == 0)
6961 break;
6962 else
6963 dev_warn(&pdev->dev, "no-op failed%s\n",
6964 (i < 11 ? "; re-trying" : ""));
6965 }
132aa220
TH		 6966
6967out_disable:
6968
6969 pci_disable_device(pdev);
6970 return rc;
4c2a8c40
SC		 6971}
6972
1fb7c98a
RE		 6973static void hpsa_free_cmd_pool(struct ctlr_info *h)
6974{
6975 kfree(h->cmd_pool_bits);
6976 if (h->cmd_pool)
6977 pci_free_consistent(h->pdev,
6978 h->nr_cmds * sizeof(struct CommandList),
6979 h->cmd_pool,
6980 h->cmd_pool_dhandle);
6981 if (h->errinfo_pool)
6982 pci_free_consistent(h->pdev,
6983 h->nr_cmds * sizeof(struct ErrorInfo),
6984 h->errinfo_pool,
6985 h->errinfo_pool_dhandle);
6986}
6987
d37ffbe4 6988static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6989{
6990 h->cmd_pool_bits = kzalloc(
6991 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6992 sizeof(unsigned long), GFP_KERNEL);
6993 h->cmd_pool = pci_alloc_consistent(h->pdev,
6994 h->nr_cmds * sizeof(*h->cmd_pool),
6995 &(h->cmd_pool_dhandle));
6996 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6997 h->nr_cmds * sizeof(*h->errinfo_pool),
6998 &(h->errinfo_pool_dhandle));
6999 if ((h->cmd_pool_bits == NULL)
7000 || (h->cmd_pool == NULL)
7001 || (h->errinfo_pool == NULL)) {
7002 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7003 goto clean_up;
2e9d1b36 7004 }
360c73bd 7005 hpsa_preinitialize_commands(h);
2e9d1b36 7006 return 0;
2c143342
RE		 7007clean_up:
7008 hpsa_free_cmd_pool(h);
7009 return -ENOMEM;
2e9d1b36
SC		 7010}
7011
41b3cf08
SC		 7012static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7013{
ec429952 7014 int i, cpu;
41b3cf08
SC		 7015
7016 cpu = cpumask_first(cpu_online_mask);
7017 for (i = 0; i < h->msix_vector; i++) {
ec429952 7018 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7019 cpu = cpumask_next(cpu, cpu_online_mask);
7020 }
7021}
7022
ec501a18
RE		 7023/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7024static void hpsa_free_irqs(struct ctlr_info *h)
7025{
7026 int i;
7027
7028 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7029 /* Single reply queue, only one irq to free */
7030 i = h->intr_mode;
7031 irq_set_affinity_hint(h->intr[i], NULL);
7032 free_irq(h->intr[i], &h->q[i]);
7033 return;
7034 }
7035
7036 for (i = 0; i < h->msix_vector; i++) {
7037 irq_set_affinity_hint(h->intr[i], NULL);
7038 free_irq(h->intr[i], &h->q[i]);
7039 }
a4e17fc1
RE		 7040 for (; i < MAX_REPLY_QUEUES; i++)
7041 h->q[i] = 0;
ec501a18
RE		 7042}
7043
9ee61794
RE		 7044/* returns 0 on success; cleans up and returns -Enn on error */
7045static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7046 irqreturn_t (*msixhandler)(int, void *),
7047 irqreturn_t (*intxhandler)(int, void *))
7048{
254f796b 7049 int rc, i;
0ae01a32 7050
254f796b
MG		 7051 /*
7052 * initialize h->q[x] = x so that interrupt handlers know which
7053 * queue to process.
7054 */
7055 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7056 h->q[i] = (u8) i;
7057
eee0f03a 7058 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7059 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7060 for (i = 0; i < h->msix_vector; i++) {
254f796b
MG		 7061 rc = request_irq(h->intr[i], msixhandler,
7062 0, h->devname,
7063 &h->q[i]);
a4e17fc1
RE		 7064 if (rc) {
7065 int j;
7066
7067 dev_err(&h->pdev->dev,
7068 "failed to get irq %d for %s\n",
7069 h->intr[i], h->devname);
7070 for (j = 0; j < i; j++) {
7071 free_irq(h->intr[j], &h->q[j]);
7072 h->q[j] = 0;
7073 }
7074 for (; j < MAX_REPLY_QUEUES; j++)
7075 h->q[j] = 0;
7076 return rc;
7077 }
7078 }
41b3cf08 7079 hpsa_irq_affinity_hints(h);
254f796b
MG		 7080 } else {
7081 /* Use single reply pool */
eee0f03a 7082 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 7083 rc = request_irq(h->intr[h->intr_mode],
7084 msixhandler, 0, h->devname,
7085 &h->q[h->intr_mode]);
7086 } else {
7087 rc = request_irq(h->intr[h->intr_mode],
7088 intxhandler, IRQF_SHARED, h->devname,
7089 &h->q[h->intr_mode]);
7090 }
7091 }
0ae01a32 7092 if (rc) {
195f2c65 7093 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7094 h->intr[h->intr_mode], h->devname);
195f2c65 7095 hpsa_free_irqs(h);
0ae01a32
SC		 7096 return -ENODEV;
7097 }
7098 return 0;
7099}
7100
6f039790 7101static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 7102{
7103 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
7104 HPSA_RESET_TYPE_CONTROLLER)) {
7105 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
7106 return -EIO;
7107 }
7108
7109 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
7110 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
7111 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
7112 return -1;
7113 }
7114
7115 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
7116 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
7117 dev_warn(&h->pdev->dev, "Board failed to become ready "
7118 "after soft reset.\n");
7119 return -1;
7120 }
7121
7122 return 0;
7123}
7124
072b0518
SC		 7125static void hpsa_free_reply_queues(struct ctlr_info *h)
7126{
7127 int i;
7128
7129 for (i = 0; i < h->nreply_queues; i++) {
7130 if (!h->reply_queue[i].head)
7131 continue;
1fb7c98a
RE		 7132 pci_free_consistent(h->pdev,
7133 h->reply_queue_size,
7134 h->reply_queue[i].head,
7135 h->reply_queue[i].busaddr);
072b0518
SC		 7136 h->reply_queue[i].head = NULL;
7137 h->reply_queue[i].busaddr = 0;
7138 }
7139}
7140
0097f0f4
SC		 7141static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7142{
cc64c817 7143 hpsa_free_irqs(h);
64670ac8
SC		 7144 hpsa_free_sg_chain_blocks(h);
7145 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7146 kfree(h->blockFetchTable); /* perf 2 */
7147 hpsa_free_reply_queues(h); /* perf 1 */
7148 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7149 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
195f2c65
RE		 7150 hpsa_free_cfgtables(h); /* pci_init 4 */
7151 iounmap(h->vaddr); /* pci_init 3 */
7152 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
132aa220 7153 pci_disable_device(h->pdev);
195f2c65 7154 pci_release_regions(h->pdev); /* pci_init 2 */
64670ac8
SC		 7155 kfree(h);
7156}
7157
a0c12413 7158/* Called when controller lockup detected. */
f2405db8 7159static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7160{
281a7fd0
WS		 7161 int i, refcount;
7162 struct CommandList *c;
25163bd5 7163 int failcount = 0;
a0c12413 7164
080ef1cc 7165 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7166 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7167 c = h->cmd_pool + i;
281a7fd0
WS		 7168 refcount = atomic_inc_return(&c->refcount);
7169 if (refcount > 1) {
25163bd5 7170 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7171 finish_cmd(c);
433b5f4d 7172 atomic_dec(&h->commands_outstanding);
25163bd5 7173 failcount++;
281a7fd0
WS		 7174 }
7175 cmd_free(h, c);
a0c12413 7176 }
25163bd5
WS		 7177 dev_warn(&h->pdev->dev,
7178 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7179}
7180
094963da
SC		 7181static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7182{
c8ed0010 7183 int cpu;
094963da 7184
c8ed0010 7185 for_each_online_cpu(cpu) {
094963da
SC		 7186 u32 *lockup_detected;
7187 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7188 *lockup_detected = value;
094963da
SC		 7189 }
7190 wmb(); /* be sure the per-cpu variables are out to memory */
7191}
7192
a0c12413
SC		 7193static void controller_lockup_detected(struct ctlr_info *h)
7194{
7195 unsigned long flags;
094963da 7196 u32 lockup_detected;
a0c12413 7197
a0c12413
SC		 7198 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7199 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7200 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7201 if (!lockup_detected) {
7202 /* no heartbeat, but controller gave us a zero. */
7203 dev_warn(&h->pdev->dev,
25163bd5
WS		 7204 "lockup detected after %d but scratchpad register is zero\n",
7205 h->heartbeat_sample_interval / HZ);
094963da
SC		 7206 lockup_detected = 0xffffffff;
7207 }
7208 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7209 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7210 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7211 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7212 pci_disable_device(h->pdev);
f2405db8 7213 fail_all_outstanding_cmds(h);
a0c12413
SC		 7214}
7215
25163bd5 7216static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7217{
7218 u64 now;
7219 u32 heartbeat;
7220 unsigned long flags;
7221
a0c12413
SC		 7222 now = get_jiffies_64();
7223 /* If we've received an interrupt recently, we're ok. */
7224 if (time_after64(h->last_intr_timestamp +
e85c5974 7225 (h->heartbeat_sample_interval), now))
25163bd5 7226 return false;
a0c12413
SC		 7227
7228 /*
7229 * If we've already checked the heartbeat recently, we're ok.
7230 * This could happen if someone sends us a signal. We
7231 * otherwise don't care about signals in this thread.
7232 */
7233 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7234 (h->heartbeat_sample_interval), now))
25163bd5 7235 return false;
a0c12413
SC		 7236
7237 /* If heartbeat has not changed since we last looked, we're not ok. */
7238 spin_lock_irqsave(&h->lock, flags);
7239 heartbeat = readl(&h->cfgtable->HeartBeat);
7240 spin_unlock_irqrestore(&h->lock, flags);
7241 if (h->last_heartbeat == heartbeat) {
7242 controller_lockup_detected(h);
25163bd5 7243 return true;
a0c12413
SC		 7244 }
7245
7246 /* We're ok. */
7247 h->last_heartbeat = heartbeat;
7248 h->last_heartbeat_timestamp = now;
25163bd5 7249 return false;
a0c12413
SC		 7250}
7251
9846590e 7252static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7253{
7254 int i;
7255 char *event_type;
7256
e4aa3e6a
SC		 7257 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7258 return;
7259
76438d08 7260 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7261 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7262 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7263 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7264 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7265
7266 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7267 event_type = "state change";
7268 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7269 event_type = "configuration change";
7270 /* Stop sending new RAID offload reqs via the IO accelerator */
7271 scsi_block_requests(h->scsi_host);
7272 for (i = 0; i < h->ndevices; i++)
7273 h->dev[i]->offload_enabled = 0;
23100dd9 7274 hpsa_drain_accel_commands(h);
76438d08
SC		 7275 /* Set 'accelerator path config change' bit */
7276 dev_warn(&h->pdev->dev,
7277 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7278 h->events, event_type);
7279 writel(h->events, &(h->cfgtable->clear_event_notify));
7280 /* Set the "clear event notify field update" bit 6 */
7281 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7282 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7283 hpsa_wait_for_clear_event_notify_ack(h);
7284 scsi_unblock_requests(h->scsi_host);
7285 } else {
7286 /* Acknowledge controller notification events. */
7287 writel(h->events, &(h->cfgtable->clear_event_notify));
7288 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7289 hpsa_wait_for_clear_event_notify_ack(h);
7290#if 0
7291 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7292 hpsa_wait_for_mode_change_ack(h);
7293#endif
7294 }
9846590e 7295 return;
76438d08
SC		 7296}
7297
7298/* Check a register on the controller to see if there are configuration
7299 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7300 * we should rescan the controller for devices.
7301 * Also check flag for driver-initiated rescan.
76438d08 7302 */
9846590e 7303static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08
SC		 7304{
7305 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7306 return 0;
76438d08
SC		 7307
7308 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7309 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7310}
76438d08 7311
9846590e
SC		 7312/*
7313 * Check if any of the offline devices have become ready
7314 */
7315static int hpsa_offline_devices_ready(struct ctlr_info *h)
7316{
7317 unsigned long flags;
7318 struct offline_device_entry *d;
7319 struct list_head *this, *tmp;
7320
7321 spin_lock_irqsave(&h->offline_device_lock, flags);
7322 list_for_each_safe(this, tmp, &h->offline_device_list) {
7323 d = list_entry(this, struct offline_device_entry,
7324 offline_list);
7325 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7326 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7327 spin_lock_irqsave(&h->offline_device_lock, flags);
7328 list_del(&d->offline_list);
7329 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7330 return 1;
d1fea47c 7331 }
9846590e
SC		 7332 spin_lock_irqsave(&h->offline_device_lock, flags);
7333 }
7334 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7335 return 0;
76438d08
SC		 7336}
7337
6636e7f4 7338static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7339{
7340 unsigned long flags;
8a98db73 7341 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7342 struct ctlr_info, rescan_ctlr_work);
7343
7344
7345 if (h->remove_in_progress)
8a98db73 7346 return;
9846590e
SC		 7347
7348 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7349 scsi_host_get(h->scsi_host);
9846590e
SC		 7350 hpsa_ack_ctlr_events(h);
7351 hpsa_scan_start(h->scsi_host);
7352 scsi_host_put(h->scsi_host);
7353 }
8a98db73 7354 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7355 if (!h->remove_in_progress)
7356 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7357 h->heartbeat_sample_interval);
7358 spin_unlock_irqrestore(&h->lock, flags);
7359}
7360
7361static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7362{
7363 unsigned long flags;
7364 struct ctlr_info *h = container_of(to_delayed_work(work),
7365 struct ctlr_info, monitor_ctlr_work);
7366
7367 detect_controller_lockup(h);
7368 if (lockup_detected(h))
a0c12413 7369 return;
6636e7f4
DB		 7370
7371 spin_lock_irqsave(&h->lock, flags);
7372 if (!h->remove_in_progress)
7373 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 7374 h->heartbeat_sample_interval);
7375 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 7376}
7377
6636e7f4
DB		 7378static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
7379 char *name)
7380{
7381 struct workqueue_struct *wq = NULL;
6636e7f4 7382
397ea9cb 7383 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 7384 if (!wq)
7385 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
7386
7387 return wq;
7388}
7389
6f039790 7390static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 7391{
4c2a8c40 7392 int dac, rc;
edd16368 7393 struct ctlr_info *h;
64670ac8
SC		 7394 int try_soft_reset = 0;
7395 unsigned long flags;
6b6c1cd7 7396 u32 board_id;
edd16368
SC		 7397
7398 if (number_of_controllers == 0)
7399 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 7400
6b6c1cd7
TH		 7401 rc = hpsa_lookup_board_id(pdev, &board_id);
7402 if (rc < 0) {
7403 dev_warn(&pdev->dev, "Board ID not found\n");
7404 return rc;
7405 }
7406
7407 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 7408 if (rc) {
7409 if (rc != -ENOTSUPP)
7410 return rc;
7411 /* If the reset fails in a particular way (it has no way to do
7412 * a proper hard reset, so returns -ENOTSUPP) we can try to do
7413 * a soft reset once we get the controller configured up to the
7414 * point that it can accept a command.
7415 */
7416 try_soft_reset = 1;
7417 rc = 0;
7418 }
7419
7420reinit_after_soft_reset:
edd16368 7421
303932fd
DB		 7422 /* Command structures must be aligned on a 32-byte boundary because
7423 * the 5 lower bits of the address are used by the hardware. and by
7424 * the driver. See comments in hpsa.h for more info.
7425 */
303932fd 7426 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 7427 h = kzalloc(sizeof(*h), GFP_KERNEL);
7428 if (!h)
ecd9aad4 7429 return -ENOMEM;
edd16368 7430
55c06c71 7431 h->pdev = pdev;
a9a3a273 7432 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 7433 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 7434 spin_lock_init(&h->lock);
9846590e 7435 spin_lock_init(&h->offline_device_lock);
6eaf46fd 7436 spin_lock_init(&h->scan_lock);
34f0c627 7437 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 7438 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da 7439
6636e7f4
DB		 7440 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
7441 if (!h->rescan_ctlr_wq) {
7442 rc = -ENOMEM;
7443 goto clean1;
7444 }
7445
7446 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
080ef1cc 7447 if (!h->resubmit_wq) {
080ef1cc
DB		 7448 rc = -ENOMEM;
7449 goto clean1;
7450 }
6636e7f4 7451
094963da
SC		 7452 /* Allocate and clear per-cpu variable lockup_detected */
7453 h->lockup_detected = alloc_percpu(u32);
2a5ac326
SC		 7454 if (!h->lockup_detected) {
7455 rc = -ENOMEM;
094963da 7456 goto clean1;
2a5ac326 7457 }
094963da
SC		 7458 set_lockup_detected_for_all_cpus(h, 0);
7459
55c06c71 7460 rc = hpsa_pci_init(h);
ecd9aad4 7461 if (rc != 0)
edd16368
SC		 7462 goto clean1;
7463
f79cfec6 7464 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 7465 h->ctlr = number_of_controllers;
7466 number_of_controllers++;
edd16368
SC		 7467
7468 /* configure PCI DMA stuff */
ecd9aad4
SC		 7469 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
7470 if (rc == 0) {
edd16368 7471 dac = 1;
ecd9aad4
SC		 7472 } else {
7473 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7474 if (rc == 0) {
7475 dac = 0;
7476 } else {
7477 dev_err(&pdev->dev, "no suitable DMA available\n");
195f2c65 7478 goto clean2;
ecd9aad4 7479 }
edd16368
SC		 7480 }
7481
7482 /* make sure the board interrupts are off */
7483 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 7484
9ee61794 7485 if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 7486 goto clean2;
303932fd
DB		 7487 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
7488 h->devname, pdev->device,
a9a3a273 7489 h->intr[h->intr_mode], dac ? "" : " not");
d37ffbe4 7490 rc = hpsa_alloc_cmd_pool(h);
8947fd10
RE		 7491 if (rc)
7492 goto clean2_and_free_irqs;
33a2ffce
SC		 7493 if (hpsa_allocate_sg_chain_blocks(h))
7494 goto clean4;
a08a8471 7495 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 7496 init_waitqueue_head(&h->abort_cmd_wait_queue);
a08a8471 7497 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 7498
7499 pci_set_drvdata(pdev, h);
9a41338e 7500 h->ndevices = 0;
316b221a 7501 h->hba_mode_enabled = 0;
9a41338e
SC		 7502 h->scsi_host = NULL;
7503 spin_lock_init(&h->devlock);
64670ac8
SC		 7504 hpsa_put_ctlr_into_performant_mode(h);
7505
7506 /* At this point, the controller is ready to take commands.
7507 * Now, if reset_devices and the hard reset didn't work, try
7508 * the soft reset and see if that works.
7509 */
7510 if (try_soft_reset) {
7511
7512 /* This is kind of gross. We may or may not get a completion
7513 * from the soft reset command, and if we do, then the value
7514 * from the fifo may or may not be valid. So, we wait 10 secs
7515 * after the reset throwing away any completions we get during
7516 * that time. Unregister the interrupt handler and register
7517 * fake ones to scoop up any residual completions.
7518 */
7519 spin_lock_irqsave(&h->lock, flags);
7520 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7521 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 7522 hpsa_free_irqs(h);
9ee61794 7523 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 7524 hpsa_intx_discard_completions);
7525 if (rc) {
9ee61794
RE		 7526 dev_warn(&h->pdev->dev,
7527 "Failed to request_irq after soft reset.\n");
64670ac8
SC		 7528 goto clean4;
7529 }
7530
7531 rc = hpsa_kdump_soft_reset(h);
7532 if (rc)
7533 /* Neither hard nor soft reset worked, we're hosed. */
7534 goto clean4;
7535
7536 dev_info(&h->pdev->dev, "Board READY.\n");
7537 dev_info(&h->pdev->dev,
7538 "Waiting for stale completions to drain.\n");
7539 h->access.set_intr_mask(h, HPSA_INTR_ON);
7540 msleep(10000);
7541 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7542
7543 rc = controller_reset_failed(h->cfgtable);
7544 if (rc)
7545 dev_info(&h->pdev->dev,
7546 "Soft reset appears to have failed.\n");
7547
7548 /* since the controller's reset, we have to go back and re-init
7549 * everything. Easiest to just forget what we've done and do it
7550 * all over again.
7551 */
7552 hpsa_undo_allocations_after_kdump_soft_reset(h);
7553 try_soft_reset = 0;
7554 if (rc)
7555 /* don't go to clean4, we already unallocated */
7556 return -ENODEV;
7557
7558 goto reinit_after_soft_reset;
7559 }
edd16368 7560
316b221a
SC		 7561 /* Enable Accelerated IO path at driver layer */
7562 h->acciopath_status = 1;
da0697bd 7563
e863d68e 7564
edd16368
SC		 7565 /* Turn the interrupts on so we can service requests */
7566 h->access.set_intr_mask(h, HPSA_INTR_ON);
7567
339b2b14 7568 hpsa_hba_inquiry(h);
4a4384ce
SC		 7569 rc = hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
7570 if (rc)
7571 goto clean4;
8a98db73
SC		 7572
7573 /* Monitor the controller for firmware lockups */
7574 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
7575 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
7576 schedule_delayed_work(&h->monitor_ctlr_work,
7577 h->heartbeat_sample_interval);
6636e7f4
DB		 7578 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
7579 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7580 h->heartbeat_sample_interval);
88bf6d62 7581 return 0;
edd16368
SC		 7582
7583clean4:
33a2ffce 7584 hpsa_free_sg_chain_blocks(h);
2e9d1b36 7585 hpsa_free_cmd_pool(h);
1fb7c98a
RE		 7586 hpsa_free_ioaccel1_cmd_and_bft(h);
7587 hpsa_free_ioaccel2_cmd_and_bft(h);
8947fd10 7588clean2_and_free_irqs:
ec501a18 7589 hpsa_free_irqs(h);
edd16368 7590clean2:
195f2c65 7591 hpsa_free_pci_init(h);
edd16368 7592clean1:
080ef1cc
DB		 7593 if (h->resubmit_wq)
7594 destroy_workqueue(h->resubmit_wq);
6636e7f4
DB		 7595 if (h->rescan_ctlr_wq)
7596 destroy_workqueue(h->rescan_ctlr_wq);
094963da
SC		 7597 if (h->lockup_detected)
7598 free_percpu(h->lockup_detected);
edd16368 7599 kfree(h);
ecd9aad4 7600 return rc;
edd16368
SC		 7601}
7602
7603static void hpsa_flush_cache(struct ctlr_info *h)
7604{
7605 char *flush_buf;
7606 struct CommandList *c;
25163bd5 7607 int rc;
702890e3
SC		 7608
7609 /* Don't bother trying to flush the cache if locked up */
25163bd5 7610 /* FIXME not necessary if do_simple_cmd does the check */
094963da 7611 if (unlikely(lockup_detected(h)))
702890e3 7612 return;
edd16368
SC		 7613 flush_buf = kzalloc(4, GFP_KERNEL);
7614 if (!flush_buf)
7615 return;
7616
45fcb86e 7617 c = cmd_alloc(h);
edd16368 7618 if (!c) {
45fcb86e 7619 dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n");
edd16368
SC		 7620 goto out_of_memory;
7621 }
a2dac136
SC		 7622 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
7623 RAID_CTLR_LUNID, TYPE_CMD)) {
7624 goto out;
7625 }
25163bd5
WS		 7626 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
7627 PCI_DMA_TODEVICE, NO_TIMEOUT);
7628 if (rc)
7629 goto out;
edd16368 7630 if (c->err_info->CommandStatus != 0)
a2dac136 7631out:
edd16368
SC		 7632 dev_warn(&h->pdev->dev,
7633 "error flushing cache on controller\n");
45fcb86e 7634 cmd_free(h, c);
edd16368
SC		 7635out_of_memory:
7636 kfree(flush_buf);
7637}
7638
7639static void hpsa_shutdown(struct pci_dev *pdev)
7640{
7641 struct ctlr_info *h;
7642
7643 h = pci_get_drvdata(pdev);
7644 /* Turn board interrupts off and send the flush cache command
7645 * sendcmd will turn off interrupt, and send the flush...
7646 * To write all data in the battery backed cache to disks
7647 */
7648 hpsa_flush_cache(h);
7649 h->access.set_intr_mask(h, HPSA_INTR_OFF);
cc64c817
RE		 7650 hpsa_free_irqs(h);
7651 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 7652}
7653
6f039790 7654static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 7655{
7656 int i;
7657
7658 for (i = 0; i < h->ndevices; i++)
7659 kfree(h->dev[i]);
7660}
7661
6f039790 7662static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 7663{
7664 struct ctlr_info *h;
8a98db73 7665 unsigned long flags;
edd16368
SC		 7666
7667 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 7668 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 7669 return;
7670 }
7671 h = pci_get_drvdata(pdev);
8a98db73
SC		 7672
7673 /* Get rid of any controller monitoring work items */
7674 spin_lock_irqsave(&h->lock, flags);
7675 h->remove_in_progress = 1;
8a98db73 7676 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 7677 cancel_delayed_work_sync(&h->monitor_ctlr_work);
7678 cancel_delayed_work_sync(&h->rescan_ctlr_work);
7679 destroy_workqueue(h->rescan_ctlr_wq);
7680 destroy_workqueue(h->resubmit_wq);
edd16368 7681 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
cc64c817 7682
195f2c65
RE		 7683 /* includes hpsa_free_irqs */
7684 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 7685 hpsa_shutdown(pdev);
cc64c817 7686
55e14e76 7687 hpsa_free_device_info(h);
33a2ffce 7688 hpsa_free_sg_chain_blocks(h);
1fb7c98a
RE		 7689 kfree(h->blockFetchTable); /* perf 2 */
7690 hpsa_free_reply_queues(h); /* perf 1 */
7691 hpsa_free_ioaccel1_cmd_and_bft(h); /* perf 1 */
7692 hpsa_free_ioaccel2_cmd_and_bft(h); /* perf 1 */
7693 hpsa_free_cmd_pool(h); /* init_one 5 */
339b2b14 7694 kfree(h->hba_inquiry_data);
195f2c65
RE		 7695
7696 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
7697 hpsa_free_pci_init(h);
7698
094963da 7699 free_percpu(h->lockup_detected);
edd16368
SC		 7700 kfree(h);
7701}
7702
7703static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
7704 __attribute__((unused)) pm_message_t state)
7705{
7706 return -ENOSYS;
7707}
7708
7709static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
7710{
7711 return -ENOSYS;
7712}
7713
7714static struct pci_driver hpsa_pci_driver = {
f79cfec6 7715 .name = HPSA,
edd16368 7716 .probe = hpsa_init_one,
6f039790 7717 .remove = hpsa_remove_one,
edd16368
SC		 7718 .id_table = hpsa_pci_device_id, /* id_table */
7719 .shutdown = hpsa_shutdown,
7720 .suspend = hpsa_suspend,
7721 .resume = hpsa_resume,
7722};
7723
303932fd
DB		 7724/* Fill in bucket_map[], given nsgs (the max number of
7725 * scatter gather elements supported) and bucket[],
7726 * which is an array of 8 integers. The bucket[] array
7727 * contains 8 different DMA transfer sizes (in 16
7728 * byte increments) which the controller uses to fetch
7729 * commands. This function fills in bucket_map[], which
7730 * maps a given number of scatter gather elements to one of
7731 * the 8 DMA transfer sizes. The point of it is to allow the
7732 * controller to only do as much DMA as needed to fetch the
7733 * command, with the DMA transfer size encoded in the lower
7734 * bits of the command address.
7735 */
7736static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 7737 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 7738{
7739 int i, j, b, size;
7740
303932fd
DB		 7741 /* Note, bucket_map must have nsgs+1 entries. */
7742 for (i = 0; i <= nsgs; i++) {
7743 /* Compute size of a command with i SG entries */
e1f7de0c 7744 size = i + min_blocks;
303932fd
DB		 7745 b = num_buckets; /* Assume the biggest bucket */
7746 /* Find the bucket that is just big enough */
e1f7de0c 7747 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 7748 if (bucket[j] >= size) {
7749 b = j;
7750 break;
7751 }
7752 }
7753 /* for a command with i SG entries, use bucket b. */
7754 bucket_map[i] = b;
7755 }
7756}
7757
c706a795
RE		 7758/* return -ENODEV or other reason on error, 0 on success */
7759static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 7760{
6c311b57
SC		 7761 int i;
7762 unsigned long register_value;
e1f7de0c
MG		 7763 unsigned long transMethod = CFGTBL_Trans_Performant |
7764 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 7765 CFGTBL_Trans_enable_directed_msix |
7766 (trans_support & (CFGTBL_Trans_io_accel1 |
7767 CFGTBL_Trans_io_accel2));
e1f7de0c 7768 struct access_method access = SA5_performant_access;
def342bd
SC		 7769
7770 /* This is a bit complicated. There are 8 registers on
7771 * the controller which we write to to tell it 8 different
7772 * sizes of commands which there may be. It's a way of
7773 * reducing the DMA done to fetch each command. Encoded into
7774 * each command's tag are 3 bits which communicate to the controller
7775 * which of the eight sizes that command fits within. The size of
7776 * each command depends on how many scatter gather entries there are.
7777 * Each SG entry requires 16 bytes. The eight registers are programmed
7778 * with the number of 16-byte blocks a command of that size requires.
7779 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 7780 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 7781 * blocks. Note, this only extends to the SG entries contained
7782 * within the command block, and does not extend to chained blocks
7783 * of SG elements. bft[] contains the eight values we write to
7784 * the registers. They are not evenly distributed, but have more
7785 * sizes for small commands, and fewer sizes for larger commands.
7786 */
d66ae08b 7787 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 7788#define MIN_IOACCEL2_BFT_ENTRY 5
7789#define HPSA_IOACCEL2_HEADER_SZ 4
7790 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
7791 13, 14, 15, 16, 17, 18, 19,
7792 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
7793 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
7794 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
7795 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
7796 16 * MIN_IOACCEL2_BFT_ENTRY);
7797 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 7798 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 7799 /* 5 = 1 s/g entry or 4k
7800 * 6 = 2 s/g entry or 8k
7801 * 8 = 4 s/g entry or 16k
7802 * 10 = 6 s/g entry or 24k
7803 */
303932fd 7804
b3a52e79
SC		 7805 /* If the controller supports either ioaccel method then
7806 * we can also use the RAID stack submit path that does not
7807 * perform the superfluous readl() after each command submission.
7808 */
7809 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
7810 access = SA5_performant_access_no_read;
7811
303932fd 7812 /* Controller spec: zero out this buffer. */
072b0518
SC		 7813 for (i = 0; i < h->nreply_queues; i++)
7814 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 7815
d66ae08b
SC		 7816 bft[7] = SG_ENTRIES_IN_CMD + 4;
7817 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 7818 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 7819 for (i = 0; i < 8; i++)
7820 writel(bft[i], &h->transtable->BlockFetch[i]);
7821
7822 /* size of controller ring buffer */
7823 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 7824 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 7825 writel(0, &h->transtable->RepQCtrAddrLow32);
7826 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 7827
7828 for (i = 0; i < h->nreply_queues; i++) {
7829 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 7830 writel(h->reply_queue[i].busaddr,
254f796b
MG		 7831 &h->transtable->RepQAddr[i].lower);
7832 }
7833
b9af4937 7834 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 7835 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
7836 /*
7837 * enable outbound interrupt coalescing in accelerator mode;
7838 */
7839 if (trans_support & CFGTBL_Trans_io_accel1) {
7840 access = SA5_ioaccel_mode1_access;
7841 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7842 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 7843 } else {
7844 if (trans_support & CFGTBL_Trans_io_accel2) {
7845 access = SA5_ioaccel_mode2_access;
7846 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
7847 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
7848 }
e1f7de0c 7849 }
303932fd 7850 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7851 if (hpsa_wait_for_mode_change_ack(h)) {
7852 dev_err(&h->pdev->dev,
7853 "performant mode problem - doorbell timeout\n");
7854 return -ENODEV;
7855 }
303932fd
DB		 7856 register_value = readl(&(h->cfgtable->TransportActive));
7857 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 7858 dev_err(&h->pdev->dev,
7859 "performant mode problem - transport not active\n");
c706a795 7860 return -ENODEV;
303932fd 7861 }
960a30e7 7862 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 7863 h->access = access;
7864 h->transMethod = transMethod;
7865
b9af4937
SC		 7866 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
7867 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 7868 return 0;
e1f7de0c 7869
b9af4937
SC		 7870 if (trans_support & CFGTBL_Trans_io_accel1) {
7871 /* Set up I/O accelerator mode */
7872 for (i = 0; i < h->nreply_queues; i++) {
7873 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
7874 h->reply_queue[i].current_entry =
7875 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
7876 }
7877 bft[7] = h->ioaccel_maxsg + 8;
7878 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
7879 h->ioaccel1_blockFetchTable);
e1f7de0c 7880
b9af4937 7881 /* initialize all reply queue entries to unused */
072b0518
SC		 7882 for (i = 0; i < h->nreply_queues; i++)
7883 memset(h->reply_queue[i].head,
7884 (u8) IOACCEL_MODE1_REPLY_UNUSED,
7885 h->reply_queue_size);
e1f7de0c 7886
b9af4937
SC		 7887 /* set all the constant fields in the accelerator command
7888 * frames once at init time to save CPU cycles later.
7889 */
7890 for (i = 0; i < h->nr_cmds; i++) {
7891 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
7892
7893 cp->function = IOACCEL1_FUNCTION_SCSIIO;
7894 cp->err_info = (u32) (h->errinfo_pool_dhandle +
7895 (i * sizeof(struct ErrorInfo)));
7896 cp->err_info_len = sizeof(struct ErrorInfo);
7897 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 7898 cp->host_context_flags =
7899 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 7900 cp->timeout_sec = 0;
7901 cp->ReplyQueue = 0;
50a0decf 7902 cp->tag =
f2405db8 7903 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 7904 cp->host_addr =
7905 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 7906 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 7907 }
7908 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7909 u64 cfg_offset, cfg_base_addr_index;
7910 u32 bft2_offset, cfg_base_addr;
7911 int rc;
7912
7913 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7914 &cfg_base_addr_index, &cfg_offset);
7915 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7916 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7917 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7918 4, h->ioaccel2_blockFetchTable);
7919 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7920 BUILD_BUG_ON(offsetof(struct CfgTable,
7921 io_accel_request_size_offset) != 0xb8);
7922 h->ioaccel2_bft2_regs =
7923 remap_pci_mem(pci_resource_start(h->pdev,
7924 cfg_base_addr_index) +
7925 cfg_offset + bft2_offset,
7926 ARRAY_SIZE(bft2) *
7927 sizeof(*h->ioaccel2_bft2_regs));
7928 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7929 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7930 }
b9af4937 7931 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7932 if (hpsa_wait_for_mode_change_ack(h)) {
7933 dev_err(&h->pdev->dev,
7934 "performant mode problem - enabling ioaccel mode\n");
7935 return -ENODEV;
7936 }
7937 return 0;
e1f7de0c
MG		 7938}
7939
1fb7c98a
RE		 7940/* Free ioaccel1 mode command blocks and block fetch table */
7941static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
7942{
7943 if (h->ioaccel_cmd_pool)
7944 pci_free_consistent(h->pdev,
7945 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7946 h->ioaccel_cmd_pool,
7947 h->ioaccel_cmd_pool_dhandle);
7948 kfree(h->ioaccel1_blockFetchTable);
7949}
7950
d37ffbe4
RE		 7951/* Allocate ioaccel1 mode command blocks and block fetch table */
7952static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 7953{
283b4a9b
SC		 7954 h->ioaccel_maxsg =
7955 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7956 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7957 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7958
e1f7de0c
MG		 7959 /* Command structures must be aligned on a 128-byte boundary
7960 * because the 7 lower bits of the address are used by the
7961 * hardware.
7962 */
e1f7de0c
MG		 7963 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7964 IOACCEL1_COMMANDLIST_ALIGNMENT);
7965 h->ioaccel_cmd_pool =
7966 pci_alloc_consistent(h->pdev,
7967 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7968 &(h->ioaccel_cmd_pool_dhandle));
7969
7970 h->ioaccel1_blockFetchTable =
283b4a9b 7971 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7972 sizeof(u32)), GFP_KERNEL);
7973
7974 if ((h->ioaccel_cmd_pool == NULL) ||
7975 (h->ioaccel1_blockFetchTable == NULL))
7976 goto clean_up;
7977
7978 memset(h->ioaccel_cmd_pool, 0,
7979 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7980 return 0;
7981
7982clean_up:
1fb7c98a 7983 hpsa_free_ioaccel1_cmd_and_bft(h);
e1f7de0c 7984 return 1;
6c311b57
SC		 7985}
7986
1fb7c98a
RE		 7987/* Free ioaccel2 mode command blocks and block fetch table */
7988static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
7989{
d9a729f3
WS		 7990 hpsa_free_ioaccel2_sg_chain_blocks(h);
7991
1fb7c98a
RE		 7992 if (h->ioaccel2_cmd_pool)
7993 pci_free_consistent(h->pdev,
7994 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7995 h->ioaccel2_cmd_pool,
7996 h->ioaccel2_cmd_pool_dhandle);
7997 kfree(h->ioaccel2_blockFetchTable);
7998}
7999
d37ffbe4
RE		 8000/* Allocate ioaccel2 mode command blocks and block fetch table */
8001static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8002{
d9a729f3
WS		 8003 int rc;
8004
aca9012a
SC		 8005 /* Allocate ioaccel2 mode command blocks and block fetch table */
8006
8007 h->ioaccel_maxsg =
8008 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8009 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8010 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8011
aca9012a
SC		 8012 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8013 IOACCEL2_COMMANDLIST_ALIGNMENT);
8014 h->ioaccel2_cmd_pool =
8015 pci_alloc_consistent(h->pdev,
8016 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8017 &(h->ioaccel2_cmd_pool_dhandle));
8018
8019 h->ioaccel2_blockFetchTable =
8020 kmalloc(((h->ioaccel_maxsg + 1) *
8021 sizeof(u32)), GFP_KERNEL);
8022
8023 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8024 (h->ioaccel2_blockFetchTable == NULL)) {
8025 rc = -ENOMEM;
8026 goto clean_up;
8027 }
8028
8029 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8030 if (rc)
aca9012a
SC		 8031 goto clean_up;
8032
8033 memset(h->ioaccel2_cmd_pool, 0,
8034 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8035 return 0;
8036
8037clean_up:
1fb7c98a 8038 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8039 return rc;
aca9012a
SC		 8040}
8041
6f039790 8042static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8043{
8044 u32 trans_support;
e1f7de0c
MG		 8045 unsigned long transMethod = CFGTBL_Trans_Performant |
8046 CFGTBL_Trans_use_short_tags;
254f796b 8047 int i;
6c311b57 8048
02ec19c8
SC		 8049 if (hpsa_simple_mode)
8050 return;
8051
67c99a72 8052 trans_support = readl(&(h->cfgtable->TransportSupport));
8053 if (!(trans_support & PERFORMANT_MODE))
8054 return;
8055
e1f7de0c
MG		 8056 /* Check for I/O accelerator mode support */
8057 if (trans_support & CFGTBL_Trans_io_accel1) {
8058 transMethod |= CFGTBL_Trans_io_accel1 |
8059 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 8060 if (hpsa_alloc_ioaccel1_cmd_and_bft(h))
e1f7de0c 8061 goto clean_up;
aca9012a
SC		 8062 } else {
8063 if (trans_support & CFGTBL_Trans_io_accel2) {
8064 transMethod |= CFGTBL_Trans_io_accel2 |
8065 CFGTBL_Trans_enable_directed_msix;
d37ffbe4 8066 if (hpsa_alloc_ioaccel2_cmd_and_bft(h))
aca9012a
SC		 8067 goto clean_up;
8068 }
e1f7de0c
MG		 8069 }
8070
eee0f03a 8071 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8072 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8073 /* Performant mode ring buffer and supporting data structures */
072b0518 8074 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8075
254f796b 8076 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8077 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8078 h->reply_queue_size,
8079 &(h->reply_queue[i].busaddr));
8080 if (!h->reply_queue[i].head)
8081 goto clean_up;
254f796b
MG		 8082 h->reply_queue[i].size = h->max_commands;
8083 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8084 h->reply_queue[i].current_entry = 0;
8085 }
8086
6c311b57 8087 /* Need a block fetch table for performant mode */
d66ae08b 8088 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8089 sizeof(u32)), GFP_KERNEL);
072b0518 8090 if (!h->blockFetchTable)
6c311b57
SC		 8091 goto clean_up;
8092
e1f7de0c 8093 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 8094 return;
8095
8096clean_up:
072b0518 8097 hpsa_free_reply_queues(h);
303932fd
DB		 8098 kfree(h->blockFetchTable);
8099}
8100
23100dd9 8101static int is_accelerated_cmd(struct CommandList *c)
76438d08 8102{
23100dd9
SC		 8103 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8104}
8105
8106static void hpsa_drain_accel_commands(struct ctlr_info *h)
8107{
8108 struct CommandList *c = NULL;
f2405db8 8109 int i, accel_cmds_out;
281a7fd0 8110 int refcount;
76438d08 8111
f2405db8 8112 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8113 accel_cmds_out = 0;
f2405db8 8114 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8115 c = h->cmd_pool + i;
281a7fd0
WS		 8116 refcount = atomic_inc_return(&c->refcount);
8117 if (refcount > 1) /* Command is allocated */
8118 accel_cmds_out += is_accelerated_cmd(c);
8119 cmd_free(h, c);
f2405db8 8120 }
23100dd9 8121 if (accel_cmds_out <= 0)
281a7fd0 8122 break;
76438d08
SC		 8123 msleep(100);
8124 } while (1);
8125}
8126
edd16368
SC		 8127/*
8128 * This is it. Register the PCI driver information for the cards we control
8129 * the OS will call our registered routines when it finds one of our cards.
8130 */
8131static int __init hpsa_init(void)
8132{
31468401 8133 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8134}
8135
8136static void __exit hpsa_cleanup(void)
8137{
8138 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8139}
8140
e1f7de0c
MG		 8141static void __attribute__((unused)) verify_offsets(void)
8142{
dd0e19f3
ST		 8143#define VERIFY_OFFSET(member, offset) \
8144 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8145
8146 VERIFY_OFFSET(structure_size, 0);
8147 VERIFY_OFFSET(volume_blk_size, 4);
8148 VERIFY_OFFSET(volume_blk_cnt, 8);
8149 VERIFY_OFFSET(phys_blk_shift, 16);
8150 VERIFY_OFFSET(parity_rotation_shift, 17);
8151 VERIFY_OFFSET(strip_size, 18);
8152 VERIFY_OFFSET(disk_starting_blk, 20);
8153 VERIFY_OFFSET(disk_blk_cnt, 28);
8154 VERIFY_OFFSET(data_disks_per_row, 36);
8155 VERIFY_OFFSET(metadata_disks_per_row, 38);
8156 VERIFY_OFFSET(row_cnt, 40);
8157 VERIFY_OFFSET(layout_map_count, 42);
8158 VERIFY_OFFSET(flags, 44);
8159 VERIFY_OFFSET(dekindex, 46);
8160 /* VERIFY_OFFSET(reserved, 48 */
8161 VERIFY_OFFSET(data, 64);
8162
8163#undef VERIFY_OFFSET
8164
b66cc250
MM		 8165#define VERIFY_OFFSET(member, offset) \
8166 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8167
8168 VERIFY_OFFSET(IU_type, 0);
8169 VERIFY_OFFSET(direction, 1);
8170 VERIFY_OFFSET(reply_queue, 2);
8171 /* VERIFY_OFFSET(reserved1, 3); */
8172 VERIFY_OFFSET(scsi_nexus, 4);
8173 VERIFY_OFFSET(Tag, 8);
8174 VERIFY_OFFSET(cdb, 16);
8175 VERIFY_OFFSET(cciss_lun, 32);
8176 VERIFY_OFFSET(data_len, 40);
8177 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8178 VERIFY_OFFSET(sg_count, 45);
8179 /* VERIFY_OFFSET(reserved3 */
8180 VERIFY_OFFSET(err_ptr, 48);
8181 VERIFY_OFFSET(err_len, 56);
8182 /* VERIFY_OFFSET(reserved4 */
8183 VERIFY_OFFSET(sg, 64);
8184
8185#undef VERIFY_OFFSET
8186
e1f7de0c
MG		 8187#define VERIFY_OFFSET(member, offset) \
8188 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8189
8190 VERIFY_OFFSET(dev_handle, 0x00);
8191 VERIFY_OFFSET(reserved1, 0x02);
8192 VERIFY_OFFSET(function, 0x03);
8193 VERIFY_OFFSET(reserved2, 0x04);
8194 VERIFY_OFFSET(err_info, 0x0C);
8195 VERIFY_OFFSET(reserved3, 0x10);
8196 VERIFY_OFFSET(err_info_len, 0x12);
8197 VERIFY_OFFSET(reserved4, 0x13);
8198 VERIFY_OFFSET(sgl_offset, 0x14);
8199 VERIFY_OFFSET(reserved5, 0x15);
8200 VERIFY_OFFSET(transfer_len, 0x1C);
8201 VERIFY_OFFSET(reserved6, 0x20);
8202 VERIFY_OFFSET(io_flags, 0x24);
8203 VERIFY_OFFSET(reserved7, 0x26);
8204 VERIFY_OFFSET(LUN, 0x34);
8205 VERIFY_OFFSET(control, 0x3C);
8206 VERIFY_OFFSET(CDB, 0x40);
8207 VERIFY_OFFSET(reserved8, 0x50);
8208 VERIFY_OFFSET(host_context_flags, 0x60);
8209 VERIFY_OFFSET(timeout_sec, 0x62);
8210 VERIFY_OFFSET(ReplyQueue, 0x64);
8211 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8212 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8213 VERIFY_OFFSET(host_addr, 0x70);
8214 VERIFY_OFFSET(CISS_LUN, 0x78);
8215 VERIFY_OFFSET(SG, 0x78 + 8);
8216#undef VERIFY_OFFSET
8217}
8218
edd16368
SC		 8219module_init(hpsa_init);
8220module_exit(hpsa_cleanup);
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