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[SCSI] hpsa: rescan devices on ioaccel2 error
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
76438d08
SC		 223static void hpsa_drain_commands(struct ctlr_info *h);
224static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
227 u8 *scsi3addr);
edd16368 228
edd16368
SC		 229static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
230{
231 unsigned long *priv = shost_priv(sdev->host);
232 return (struct ctlr_info *) *priv;
233}
234
a23513e8
SC		 235static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
236{
237 unsigned long *priv = shost_priv(sh);
238 return (struct ctlr_info *) *priv;
239}
240
edd16368
SC		 241static int check_for_unit_attention(struct ctlr_info *h,
242 struct CommandList *c)
243{
244 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
245 return 0;
246
247 switch (c->err_info->SenseInfo[12]) {
248 case STATE_CHANGED:
f79cfec6 249 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 250 "detected, command retried\n", h->ctlr);
251 break;
252 case LUN_FAILED:
f79cfec6 253 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 254 "detected, action required\n", h->ctlr);
255 break;
256 case REPORT_LUNS_CHANGED:
f79cfec6 257 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 258 "changed, action required\n", h->ctlr);
edd16368 259 /*
4f4eb9f1
ST		 260 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
261 * target (array) devices.
edd16368
SC		 262 */
263 break;
264 case POWER_OR_RESET:
f79cfec6 265 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 266 "or device reset detected\n", h->ctlr);
267 break;
268 case UNIT_ATTENTION_CLEARED:
f79cfec6 269 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 270 "cleared by another initiator\n", h->ctlr);
271 break;
272 default:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 274 "unit attention detected\n", h->ctlr);
275 break;
276 }
277 return 1;
278}
279
852af20a
MB		 280static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
281{
282 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
283 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
284 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
285 return 0;
286 dev_warn(&h->pdev->dev, HPSA "device busy");
287 return 1;
288}
289
da0697bd
ST		 290static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 int status, len;
295 struct ctlr_info *h;
296 struct Scsi_Host *shost = class_to_shost(dev);
297 char tmpbuf[10];
298
299 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
300 return -EACCES;
301 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
302 strncpy(tmpbuf, buf, len);
303 tmpbuf[len] = '\0';
304 if (sscanf(tmpbuf, "%d", &status) != 1)
305 return -EINVAL;
306 h = shost_to_hba(shost);
307 h->acciopath_status = !!status;
308 dev_warn(&h->pdev->dev,
309 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
310 h->acciopath_status ? "enabled" : "disabled");
311 return count;
312}
313
edd16368
SC		 314static ssize_t host_store_rescan(struct device *dev,
315 struct device_attribute *attr,
316 const char *buf, size_t count)
317{
318 struct ctlr_info *h;
319 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 320 h = shost_to_hba(shost);
31468401 321 hpsa_scan_start(h->scsi_host);
edd16368
SC		 322 return count;
323}
324
d28ce020
SC		 325static ssize_t host_show_firmware_revision(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330 unsigned char *fwrev;
331
332 h = shost_to_hba(shost);
333 if (!h->hba_inquiry_data)
334 return 0;
335 fwrev = &h->hba_inquiry_data[32];
336 return snprintf(buf, 20, "%c%c%c%c\n",
337 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
338}
339
94a13649
SC		 340static ssize_t host_show_commands_outstanding(struct device *dev,
341 struct device_attribute *attr, char *buf)
342{
343 struct Scsi_Host *shost = class_to_shost(dev);
344 struct ctlr_info *h = shost_to_hba(shost);
345
346 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
347}
348
745a7a25
SC		 349static ssize_t host_show_transport_mode(struct device *dev,
350 struct device_attribute *attr, char *buf)
351{
352 struct ctlr_info *h;
353 struct Scsi_Host *shost = class_to_shost(dev);
354
355 h = shost_to_hba(shost);
356 return snprintf(buf, 20, "%s\n",
960a30e7 357 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 358 "performant" : "simple");
359}
360
da0697bd
ST		 361static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
362 struct device_attribute *attr, char *buf)
363{
364 struct ctlr_info *h;
365 struct Scsi_Host *shost = class_to_shost(dev);
366
367 h = shost_to_hba(shost);
368 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
369 (h->acciopath_status == 1) ? "enabled" : "disabled");
370}
371
46380786 372/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 373static u32 unresettable_controller[] = {
374 0x324a103C, /* Smart Array P712m */
375 0x324b103C, /* SmartArray P711m */
376 0x3223103C, /* Smart Array P800 */
377 0x3234103C, /* Smart Array P400 */
378 0x3235103C, /* Smart Array P400i */
379 0x3211103C, /* Smart Array E200i */
380 0x3212103C, /* Smart Array E200 */
381 0x3213103C, /* Smart Array E200i */
382 0x3214103C, /* Smart Array E200i */
383 0x3215103C, /* Smart Array E200i */
384 0x3237103C, /* Smart Array E500 */
385 0x323D103C, /* Smart Array P700m */
7af0abbc 386 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 387 0x409C0E11, /* Smart Array 6400 */
388 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 389 0x40700E11, /* Smart Array 5300 */
390 0x40820E11, /* Smart Array 532 */
391 0x40830E11, /* Smart Array 5312 */
392 0x409A0E11, /* Smart Array 641 */
393 0x409B0E11, /* Smart Array 642 */
394 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 395};
396
46380786
SC		 397/* List of controllers which cannot even be soft reset */
398static u32 soft_unresettable_controller[] = {
7af0abbc 399 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 400 0x40700E11, /* Smart Array 5300 */
401 0x40820E11, /* Smart Array 532 */
402 0x40830E11, /* Smart Array 5312 */
403 0x409A0E11, /* Smart Array 641 */
404 0x409B0E11, /* Smart Array 642 */
405 0x40910E11, /* Smart Array 6i */
46380786
SC		 406 /* Exclude 640x boards. These are two pci devices in one slot
407 * which share a battery backed cache module. One controls the
408 * cache, the other accesses the cache through the one that controls
409 * it. If we reset the one controlling the cache, the other will
410 * likely not be happy. Just forbid resetting this conjoined mess.
411 * The 640x isn't really supported by hpsa anyway.
412 */
413 0x409C0E11, /* Smart Array 6400 */
414 0x409D0E11, /* Smart Array 6400 EM */
415};
416
417static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 418{
419 int i;
420
421 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 422 if (unresettable_controller[i] == board_id)
423 return 0;
424 return 1;
425}
426
427static int ctlr_is_soft_resettable(u32 board_id)
428{
429 int i;
430
431 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
432 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 433 return 0;
434 return 1;
435}
436
46380786
SC		 437static int ctlr_is_resettable(u32 board_id)
438{
439 return ctlr_is_hard_resettable(board_id) ||
440 ctlr_is_soft_resettable(board_id);
441}
442
941b1cda
SC		 443static ssize_t host_show_resettable(struct device *dev,
444 struct device_attribute *attr, char *buf)
445{
446 struct ctlr_info *h;
447 struct Scsi_Host *shost = class_to_shost(dev);
448
449 h = shost_to_hba(shost);
46380786 450 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 451}
452
edd16368
SC		 453static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
454{
455 return (scsi3addr[3] & 0xC0) == 0x40;
456}
457
458static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 459 "1(ADM)", "UNKNOWN"
edd16368 460};
6b80b18f
ST		 461#define HPSA_RAID_0 0
462#define HPSA_RAID_4 1
463#define HPSA_RAID_1 2 /* also used for RAID 10 */
464#define HPSA_RAID_5 3 /* also used for RAID 50 */
465#define HPSA_RAID_51 4
466#define HPSA_RAID_6 5 /* also used for RAID 60 */
467#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 468#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
469
470static ssize_t raid_level_show(struct device *dev,
471 struct device_attribute *attr, char *buf)
472{
473 ssize_t l = 0;
82a72c0a 474 unsigned char rlevel;
edd16368
SC		 475 struct ctlr_info *h;
476 struct scsi_device *sdev;
477 struct hpsa_scsi_dev_t *hdev;
478 unsigned long flags;
479
480 sdev = to_scsi_device(dev);
481 h = sdev_to_hba(sdev);
482 spin_lock_irqsave(&h->lock, flags);
483 hdev = sdev->hostdata;
484 if (!hdev) {
485 spin_unlock_irqrestore(&h->lock, flags);
486 return -ENODEV;
487 }
488
489 /* Is this even a logical drive? */
490 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
491 spin_unlock_irqrestore(&h->lock, flags);
492 l = snprintf(buf, PAGE_SIZE, "N/A\n");
493 return l;
494 }
495
496 rlevel = hdev->raid_level;
497 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 498 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 499 rlevel = RAID_UNKNOWN;
500 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
501 return l;
502}
503
504static ssize_t lunid_show(struct device *dev,
505 struct device_attribute *attr, char *buf)
506{
507 struct ctlr_info *h;
508 struct scsi_device *sdev;
509 struct hpsa_scsi_dev_t *hdev;
510 unsigned long flags;
511 unsigned char lunid[8];
512
513 sdev = to_scsi_device(dev);
514 h = sdev_to_hba(sdev);
515 spin_lock_irqsave(&h->lock, flags);
516 hdev = sdev->hostdata;
517 if (!hdev) {
518 spin_unlock_irqrestore(&h->lock, flags);
519 return -ENODEV;
520 }
521 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
522 spin_unlock_irqrestore(&h->lock, flags);
523 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
524 lunid[0], lunid[1], lunid[2], lunid[3],
525 lunid[4], lunid[5], lunid[6], lunid[7]);
526}
527
528static ssize_t unique_id_show(struct device *dev,
529 struct device_attribute *attr, char *buf)
530{
531 struct ctlr_info *h;
532 struct scsi_device *sdev;
533 struct hpsa_scsi_dev_t *hdev;
534 unsigned long flags;
535 unsigned char sn[16];
536
537 sdev = to_scsi_device(dev);
538 h = sdev_to_hba(sdev);
539 spin_lock_irqsave(&h->lock, flags);
540 hdev = sdev->hostdata;
541 if (!hdev) {
542 spin_unlock_irqrestore(&h->lock, flags);
543 return -ENODEV;
544 }
545 memcpy(sn, hdev->device_id, sizeof(sn));
546 spin_unlock_irqrestore(&h->lock, flags);
547 return snprintf(buf, 16 * 2 + 2,
548 "%02X%02X%02X%02X%02X%02X%02X%02X"
549 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
550 sn[0], sn[1], sn[2], sn[3],
551 sn[4], sn[5], sn[6], sn[7],
552 sn[8], sn[9], sn[10], sn[11],
553 sn[12], sn[13], sn[14], sn[15]);
554}
555
c1988684
ST		 556static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
557 struct device_attribute *attr, char *buf)
558{
559 struct ctlr_info *h;
560 struct scsi_device *sdev;
561 struct hpsa_scsi_dev_t *hdev;
562 unsigned long flags;
563 int offload_enabled;
564
565 sdev = to_scsi_device(dev);
566 h = sdev_to_hba(sdev);
567 spin_lock_irqsave(&h->lock, flags);
568 hdev = sdev->hostdata;
569 if (!hdev) {
570 spin_unlock_irqrestore(&h->lock, flags);
571 return -ENODEV;
572 }
573 offload_enabled = hdev->offload_enabled;
574 spin_unlock_irqrestore(&h->lock, flags);
575 return snprintf(buf, 20, "%d\n", offload_enabled);
576}
577
3f5eac3a
SC		 578static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
579static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
580static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
581static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 582static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
583 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 584static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
585 host_show_hp_ssd_smart_path_status,
586 host_store_hp_ssd_smart_path_status);
3f5eac3a
SC		 587static DEVICE_ATTR(firmware_revision, S_IRUGO,
588 host_show_firmware_revision, NULL);
589static DEVICE_ATTR(commands_outstanding, S_IRUGO,
590 host_show_commands_outstanding, NULL);
591static DEVICE_ATTR(transport_mode, S_IRUGO,
592 host_show_transport_mode, NULL);
941b1cda
SC		 593static DEVICE_ATTR(resettable, S_IRUGO,
594 host_show_resettable, NULL);
3f5eac3a
SC		 595
596static struct device_attribute *hpsa_sdev_attrs[] = {
597 &dev_attr_raid_level,
598 &dev_attr_lunid,
599 &dev_attr_unique_id,
c1988684 600 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 601 NULL,
602};
603
604static struct device_attribute *hpsa_shost_attrs[] = {
605 &dev_attr_rescan,
606 &dev_attr_firmware_revision,
607 &dev_attr_commands_outstanding,
608 &dev_attr_transport_mode,
941b1cda 609 &dev_attr_resettable,
da0697bd 610 &dev_attr_hp_ssd_smart_path_status,
3f5eac3a
SC		 611 NULL,
612};
613
614static struct scsi_host_template hpsa_driver_template = {
615 .module = THIS_MODULE,
f79cfec6
SC		 616 .name = HPSA,
617 .proc_name = HPSA,
3f5eac3a
SC		 618 .queuecommand = hpsa_scsi_queue_command,
619 .scan_start = hpsa_scan_start,
620 .scan_finished = hpsa_scan_finished,
621 .change_queue_depth = hpsa_change_queue_depth,
622 .this_id = -1,
623 .use_clustering = ENABLE_CLUSTERING,
75167d2c 624 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 625 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
626 .ioctl = hpsa_ioctl,
627 .slave_alloc = hpsa_slave_alloc,
628 .slave_destroy = hpsa_slave_destroy,
629#ifdef CONFIG_COMPAT
630 .compat_ioctl = hpsa_compat_ioctl,
631#endif
632 .sdev_attrs = hpsa_sdev_attrs,
633 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 634 .max_sectors = 8192,
54b2b50c 635 .no_write_same = 1,
3f5eac3a
SC		 636};
637
638
639/* Enqueuing and dequeuing functions for cmdlists. */
640static inline void addQ(struct list_head *list, struct CommandList *c)
641{
642 list_add_tail(&c->list, list);
643}
644
254f796b 645static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 646{
647 u32 a;
254f796b 648 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 649 unsigned long flags;
3f5eac3a 650
e1f7de0c
MG		 651 if (h->transMethod & CFGTBL_Trans_io_accel1)
652 return h->access.command_completed(h, q);
653
3f5eac3a 654 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 655 return h->access.command_completed(h, q);
3f5eac3a 656
254f796b
MG		 657 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
658 a = rq->head[rq->current_entry];
659 rq->current_entry++;
e16a33ad 660 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 661 h->commands_outstanding--;
e16a33ad 662 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 663 } else {
664 a = FIFO_EMPTY;
665 }
666 /* Check for wraparound */
254f796b
MG		 667 if (rq->current_entry == h->max_commands) {
668 rq->current_entry = 0;
669 rq->wraparound ^= 1;
3f5eac3a
SC		 670 }
671 return a;
672}
673
c349775e
ST		 674/*
675 * There are some special bits in the bus address of the
676 * command that we have to set for the controller to know
677 * how to process the command:
678 *
679 * Normal performant mode:
680 * bit 0: 1 means performant mode, 0 means simple mode.
681 * bits 1-3 = block fetch table entry
682 * bits 4-6 = command type (== 0)
683 *
684 * ioaccel1 mode:
685 * bit 0 = "performant mode" bit.
686 * bits 1-3 = block fetch table entry
687 * bits 4-6 = command type (== 110)
688 * (command type is needed because ioaccel1 mode
689 * commands are submitted through the same register as normal
690 * mode commands, so this is how the controller knows whether
691 * the command is normal mode or ioaccel1 mode.)
692 *
693 * ioaccel2 mode:
694 * bit 0 = "performant mode" bit.
695 * bits 1-4 = block fetch table entry (note extra bit)
696 * bits 4-6 = not needed, because ioaccel2 mode has
697 * a separate special register for submitting commands.
698 */
699
3f5eac3a
SC		 700/* set_performant_mode: Modify the tag for cciss performant
701 * set bit 0 for pull model, bits 3-1 for block fetch
702 * register number
703 */
704static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
705{
254f796b 706 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 707 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 708 if (likely(h->msix_vector > 0))
254f796b 709 c->Header.ReplyQueue =
804a5cb5 710 raw_smp_processor_id() % h->nreply_queues;
254f796b 711 }
3f5eac3a
SC		 712}
713
c349775e
ST		 714static void set_ioaccel1_performant_mode(struct ctlr_info *h,
715 struct CommandList *c)
716{
717 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
718
719 /* Tell the controller to post the reply to the queue for this
720 * processor. This seems to give the best I/O throughput.
721 */
722 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
723 /* Set the bits in the address sent down to include:
724 * - performant mode bit (bit 0)
725 * - pull count (bits 1-3)
726 * - command type (bits 4-6)
727 */
728 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
729 IOACCEL1_BUSADDR_CMDTYPE;
730}
731
732static void set_ioaccel2_performant_mode(struct ctlr_info *h,
733 struct CommandList *c)
734{
735 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
736
737 /* Tell the controller to post the reply to the queue for this
738 * processor. This seems to give the best I/O throughput.
739 */
740 cp->reply_queue = smp_processor_id() % h->nreply_queues;
741 /* Set the bits in the address sent down to include:
742 * - performant mode bit not used in ioaccel mode 2
743 * - pull count (bits 0-3)
744 * - command type isn't needed for ioaccel2
745 */
746 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
747}
748
e85c5974
SC		 749static int is_firmware_flash_cmd(u8 *cdb)
750{
751 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
752}
753
754/*
755 * During firmware flash, the heartbeat register may not update as frequently
756 * as it should. So we dial down lockup detection during firmware flash. and
757 * dial it back up when firmware flash completes.
758 */
759#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
760#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
761static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
762 struct CommandList *c)
763{
764 if (!is_firmware_flash_cmd(c->Request.CDB))
765 return;
766 atomic_inc(&h->firmware_flash_in_progress);
767 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
768}
769
770static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
771 struct CommandList *c)
772{
773 if (is_firmware_flash_cmd(c->Request.CDB) &&
774 atomic_dec_and_test(&h->firmware_flash_in_progress))
775 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
776}
777
3f5eac3a
SC		 778static void enqueue_cmd_and_start_io(struct ctlr_info *h,
779 struct CommandList *c)
780{
781 unsigned long flags;
782
c349775e
ST		 783 switch (c->cmd_type) {
784 case CMD_IOACCEL1:
785 set_ioaccel1_performant_mode(h, c);
786 break;
787 case CMD_IOACCEL2:
788 set_ioaccel2_performant_mode(h, c);
789 break;
790 default:
791 set_performant_mode(h, c);
792 }
e85c5974 793 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 794 spin_lock_irqsave(&h->lock, flags);
795 addQ(&h->reqQ, c);
796 h->Qdepth++;
3f5eac3a 797 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 798 start_io(h);
3f5eac3a
SC		 799}
800
801static inline void removeQ(struct CommandList *c)
802{
803 if (WARN_ON(list_empty(&c->list)))
804 return;
805 list_del_init(&c->list);
806}
807
808static inline int is_hba_lunid(unsigned char scsi3addr[])
809{
810 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
811}
812
813static inline int is_scsi_rev_5(struct ctlr_info *h)
814{
815 if (!h->hba_inquiry_data)
816 return 0;
817 if ((h->hba_inquiry_data[2] & 0x07) == 5)
818 return 1;
819 return 0;
820}
821
edd16368
SC		 822static int hpsa_find_target_lun(struct ctlr_info *h,
823 unsigned char scsi3addr[], int bus, int *target, int *lun)
824{
825 /* finds an unused bus, target, lun for a new physical device
826 * assumes h->devlock is held
827 */
828 int i, found = 0;
cfe5badc 829 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 830
263d9401 831 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 832
833 for (i = 0; i < h->ndevices; i++) {
834 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 835 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 836 }
837
263d9401
AM		 838 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
839 if (i < HPSA_MAX_DEVICES) {
840 /* *bus = 1; */
841 *target = i;
842 *lun = 0;
843 found = 1;
edd16368
SC		 844 }
845 return !found;
846}
847
848/* Add an entry into h->dev[] array. */
849static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
850 struct hpsa_scsi_dev_t *device,
851 struct hpsa_scsi_dev_t *added[], int *nadded)
852{
853 /* assumes h->devlock is held */
854 int n = h->ndevices;
855 int i;
856 unsigned char addr1[8], addr2[8];
857 struct hpsa_scsi_dev_t *sd;
858
cfe5badc 859 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 860 dev_err(&h->pdev->dev, "too many devices, some will be "
861 "inaccessible.\n");
862 return -1;
863 }
864
865 /* physical devices do not have lun or target assigned until now. */
866 if (device->lun != -1)
867 /* Logical device, lun is already assigned. */
868 goto lun_assigned;
869
870 /* If this device a non-zero lun of a multi-lun device
871 * byte 4 of the 8-byte LUN addr will contain the logical
872 * unit no, zero otherise.
873 */
874 if (device->scsi3addr[4] == 0) {
875 /* This is not a non-zero lun of a multi-lun device */
876 if (hpsa_find_target_lun(h, device->scsi3addr,
877 device->bus, &device->target, &device->lun) != 0)
878 return -1;
879 goto lun_assigned;
880 }
881
882 /* This is a non-zero lun of a multi-lun device.
883 * Search through our list and find the device which
884 * has the same 8 byte LUN address, excepting byte 4.
885 * Assign the same bus and target for this new LUN.
886 * Use the logical unit number from the firmware.
887 */
888 memcpy(addr1, device->scsi3addr, 8);
889 addr1[4] = 0;
890 for (i = 0; i < n; i++) {
891 sd = h->dev[i];
892 memcpy(addr2, sd->scsi3addr, 8);
893 addr2[4] = 0;
894 /* differ only in byte 4? */
895 if (memcmp(addr1, addr2, 8) == 0) {
896 device->bus = sd->bus;
897 device->target = sd->target;
898 device->lun = device->scsi3addr[4];
899 break;
900 }
901 }
902 if (device->lun == -1) {
903 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
904 " suspect firmware bug or unsupported hardware "
905 "configuration.\n");
906 return -1;
907 }
908
909lun_assigned:
910
911 h->dev[n] = device;
912 h->ndevices++;
913 added[*nadded] = device;
914 (*nadded)++;
915
916 /* initially, (before registering with scsi layer) we don't
917 * know our hostno and we don't want to print anything first
918 * time anyway (the scsi layer's inquiries will show that info)
919 */
920 /* if (hostno != -1) */
921 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
922 scsi_device_type(device->devtype), hostno,
923 device->bus, device->target, device->lun);
924 return 0;
925}
926
bd9244f7
ST		 927/* Update an entry in h->dev[] array. */
928static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
929 int entry, struct hpsa_scsi_dev_t *new_entry)
930{
931 /* assumes h->devlock is held */
932 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
933
934 /* Raid level changed. */
935 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 936
937 /* Raid offload parameters changed. */
938 h->dev[entry]->offload_config = new_entry->offload_config;
939 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 940 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
941 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
942 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 943
bd9244f7
ST		 944 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
945 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
946 new_entry->target, new_entry->lun);
947}
948
2a8ccf31
SC		 949/* Replace an entry from h->dev[] array. */
950static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
951 int entry, struct hpsa_scsi_dev_t *new_entry,
952 struct hpsa_scsi_dev_t *added[], int *nadded,
953 struct hpsa_scsi_dev_t *removed[], int *nremoved)
954{
955 /* assumes h->devlock is held */
cfe5badc 956 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 957 removed[*nremoved] = h->dev[entry];
958 (*nremoved)++;
01350d05
SC		 959
960 /*
961 * New physical devices won't have target/lun assigned yet
962 * so we need to preserve the values in the slot we are replacing.
963 */
964 if (new_entry->target == -1) {
965 new_entry->target = h->dev[entry]->target;
966 new_entry->lun = h->dev[entry]->lun;
967 }
968
2a8ccf31
SC		 969 h->dev[entry] = new_entry;
970 added[*nadded] = new_entry;
971 (*nadded)++;
972 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
973 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
974 new_entry->target, new_entry->lun);
975}
976
edd16368
SC		 977/* Remove an entry from h->dev[] array. */
978static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
979 struct hpsa_scsi_dev_t *removed[], int *nremoved)
980{
981 /* assumes h->devlock is held */
982 int i;
983 struct hpsa_scsi_dev_t *sd;
984
cfe5badc 985 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 986
987 sd = h->dev[entry];
988 removed[*nremoved] = h->dev[entry];
989 (*nremoved)++;
990
991 for (i = entry; i < h->ndevices-1; i++)
992 h->dev[i] = h->dev[i+1];
993 h->ndevices--;
994 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
995 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
996 sd->lun);
997}
998
999#define SCSI3ADDR_EQ(a, b) ( \
1000 (a)[7] == (b)[7] && \
1001 (a)[6] == (b)[6] && \
1002 (a)[5] == (b)[5] && \
1003 (a)[4] == (b)[4] && \
1004 (a)[3] == (b)[3] && \
1005 (a)[2] == (b)[2] && \
1006 (a)[1] == (b)[1] && \
1007 (a)[0] == (b)[0])
1008
1009static void fixup_botched_add(struct ctlr_info *h,
1010 struct hpsa_scsi_dev_t *added)
1011{
1012 /* called when scsi_add_device fails in order to re-adjust
1013 * h->dev[] to match the mid layer's view.
1014 */
1015 unsigned long flags;
1016 int i, j;
1017
1018 spin_lock_irqsave(&h->lock, flags);
1019 for (i = 0; i < h->ndevices; i++) {
1020 if (h->dev[i] == added) {
1021 for (j = i; j < h->ndevices-1; j++)
1022 h->dev[j] = h->dev[j+1];
1023 h->ndevices--;
1024 break;
1025 }
1026 }
1027 spin_unlock_irqrestore(&h->lock, flags);
1028 kfree(added);
1029}
1030
1031static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1032 struct hpsa_scsi_dev_t *dev2)
1033{
edd16368
SC		 1034 /* we compare everything except lun and target as these
1035 * are not yet assigned. Compare parts likely
1036 * to differ first
1037 */
1038 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1039 sizeof(dev1->scsi3addr)) != 0)
1040 return 0;
1041 if (memcmp(dev1->device_id, dev2->device_id,
1042 sizeof(dev1->device_id)) != 0)
1043 return 0;
1044 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1045 return 0;
1046 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1047 return 0;
edd16368
SC		 1048 if (dev1->devtype != dev2->devtype)
1049 return 0;
edd16368
SC		 1050 if (dev1->bus != dev2->bus)
1051 return 0;
1052 return 1;
1053}
1054
bd9244f7
ST		 1055static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1056 struct hpsa_scsi_dev_t *dev2)
1057{
1058 /* Device attributes that can change, but don't mean
1059 * that the device is a different device, nor that the OS
1060 * needs to be told anything about the change.
1061 */
1062 if (dev1->raid_level != dev2->raid_level)
1063 return 1;
250fb125
SC		 1064 if (dev1->offload_config != dev2->offload_config)
1065 return 1;
1066 if (dev1->offload_enabled != dev2->offload_enabled)
1067 return 1;
bd9244f7
ST		 1068 return 0;
1069}
1070
edd16368
SC		 1071/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1072 * and return needle location in *index. If scsi3addr matches, but not
1073 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1074 * location in *index.
1075 * In the case of a minor device attribute change, such as RAID level, just
1076 * return DEVICE_UPDATED, along with the updated device's location in index.
1077 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1078 */
1079static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1080 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1081 int *index)
1082{
1083 int i;
1084#define DEVICE_NOT_FOUND 0
1085#define DEVICE_CHANGED 1
1086#define DEVICE_SAME 2
bd9244f7 1087#define DEVICE_UPDATED 3
edd16368 1088 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1089 if (haystack[i] == NULL) /* previously removed. */
1090 continue;
edd16368
SC		 1091 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1092 *index = i;
bd9244f7
ST		 1093 if (device_is_the_same(needle, haystack[i])) {
1094 if (device_updated(needle, haystack[i]))
1095 return DEVICE_UPDATED;
edd16368 1096 return DEVICE_SAME;
bd9244f7 1097 } else {
edd16368 1098 return DEVICE_CHANGED;
bd9244f7 1099 }
edd16368
SC		 1100 }
1101 }
1102 *index = -1;
1103 return DEVICE_NOT_FOUND;
1104}
1105
4967bd3e 1106static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1107 struct hpsa_scsi_dev_t *sd[], int nsds)
1108{
1109 /* sd contains scsi3 addresses and devtypes, and inquiry
1110 * data. This function takes what's in sd to be the current
1111 * reality and updates h->dev[] to reflect that reality.
1112 */
1113 int i, entry, device_change, changes = 0;
1114 struct hpsa_scsi_dev_t *csd;
1115 unsigned long flags;
1116 struct hpsa_scsi_dev_t **added, **removed;
1117 int nadded, nremoved;
1118 struct Scsi_Host *sh = NULL;
1119
cfe5badc
ST		 1120 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1121 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1122
1123 if (!added || !removed) {
1124 dev_warn(&h->pdev->dev, "out of memory in "
1125 "adjust_hpsa_scsi_table\n");
1126 goto free_and_out;
1127 }
1128
1129 spin_lock_irqsave(&h->devlock, flags);
1130
1131 /* find any devices in h->dev[] that are not in
1132 * sd[] and remove them from h->dev[], and for any
1133 * devices which have changed, remove the old device
1134 * info and add the new device info.
bd9244f7
ST		 1135 * If minor device attributes change, just update
1136 * the existing device structure.
edd16368
SC		 1137 */
1138 i = 0;
1139 nremoved = 0;
1140 nadded = 0;
1141 while (i < h->ndevices) {
1142 csd = h->dev[i];
1143 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1144 if (device_change == DEVICE_NOT_FOUND) {
1145 changes++;
1146 hpsa_scsi_remove_entry(h, hostno, i,
1147 removed, &nremoved);
1148 continue; /* remove ^^^, hence i not incremented */
1149 } else if (device_change == DEVICE_CHANGED) {
1150 changes++;
2a8ccf31
SC		 1151 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1152 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1153 /* Set it to NULL to prevent it from being freed
1154 * at the bottom of hpsa_update_scsi_devices()
1155 */
1156 sd[entry] = NULL;
bd9244f7
ST		 1157 } else if (device_change == DEVICE_UPDATED) {
1158 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1159 }
1160 i++;
1161 }
1162
1163 /* Now, make sure every device listed in sd[] is also
1164 * listed in h->dev[], adding them if they aren't found
1165 */
1166
1167 for (i = 0; i < nsds; i++) {
1168 if (!sd[i]) /* if already added above. */
1169 continue;
1170 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1171 h->ndevices, &entry);
1172 if (device_change == DEVICE_NOT_FOUND) {
1173 changes++;
1174 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1175 added, &nadded) != 0)
1176 break;
1177 sd[i] = NULL; /* prevent from being freed later. */
1178 } else if (device_change == DEVICE_CHANGED) {
1179 /* should never happen... */
1180 changes++;
1181 dev_warn(&h->pdev->dev,
1182 "device unexpectedly changed.\n");
1183 /* but if it does happen, we just ignore that device */
1184 }
1185 }
1186 spin_unlock_irqrestore(&h->devlock, flags);
1187
1188 /* Don't notify scsi mid layer of any changes the first time through
1189 * (or if there are no changes) scsi_scan_host will do it later the
1190 * first time through.
1191 */
1192 if (hostno == -1 || !changes)
1193 goto free_and_out;
1194
1195 sh = h->scsi_host;
1196 /* Notify scsi mid layer of any removed devices */
1197 for (i = 0; i < nremoved; i++) {
1198 struct scsi_device *sdev =
1199 scsi_device_lookup(sh, removed[i]->bus,
1200 removed[i]->target, removed[i]->lun);
1201 if (sdev != NULL) {
1202 scsi_remove_device(sdev);
1203 scsi_device_put(sdev);
1204 } else {
1205 /* We don't expect to get here.
1206 * future cmds to this device will get selection
1207 * timeout as if the device was gone.
1208 */
1209 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1210 " for removal.", hostno, removed[i]->bus,
1211 removed[i]->target, removed[i]->lun);
1212 }
1213 kfree(removed[i]);
1214 removed[i] = NULL;
1215 }
1216
1217 /* Notify scsi mid layer of any added devices */
1218 for (i = 0; i < nadded; i++) {
1219 if (scsi_add_device(sh, added[i]->bus,
1220 added[i]->target, added[i]->lun) == 0)
1221 continue;
1222 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1223 "device not added.\n", hostno, added[i]->bus,
1224 added[i]->target, added[i]->lun);
1225 /* now we have to remove it from h->dev,
1226 * since it didn't get added to scsi mid layer
1227 */
1228 fixup_botched_add(h, added[i]);
1229 }
1230
1231free_and_out:
1232 kfree(added);
1233 kfree(removed);
edd16368
SC		 1234}
1235
1236/*
9e03aa2f 1237 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1238 * Assume's h->devlock is held.
1239 */
1240static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1241 int bus, int target, int lun)
1242{
1243 int i;
1244 struct hpsa_scsi_dev_t *sd;
1245
1246 for (i = 0; i < h->ndevices; i++) {
1247 sd = h->dev[i];
1248 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1249 return sd;
1250 }
1251 return NULL;
1252}
1253
1254/* link sdev->hostdata to our per-device structure. */
1255static int hpsa_slave_alloc(struct scsi_device *sdev)
1256{
1257 struct hpsa_scsi_dev_t *sd;
1258 unsigned long flags;
1259 struct ctlr_info *h;
1260
1261 h = sdev_to_hba(sdev);
1262 spin_lock_irqsave(&h->devlock, flags);
1263 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1264 sdev_id(sdev), sdev->lun);
1265 if (sd != NULL)
1266 sdev->hostdata = sd;
1267 spin_unlock_irqrestore(&h->devlock, flags);
1268 return 0;
1269}
1270
1271static void hpsa_slave_destroy(struct scsi_device *sdev)
1272{
bcc44255 1273 /* nothing to do. */
edd16368
SC		 1274}
1275
33a2ffce
SC		 1276static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1277{
1278 int i;
1279
1280 if (!h->cmd_sg_list)
1281 return;
1282 for (i = 0; i < h->nr_cmds; i++) {
1283 kfree(h->cmd_sg_list[i]);
1284 h->cmd_sg_list[i] = NULL;
1285 }
1286 kfree(h->cmd_sg_list);
1287 h->cmd_sg_list = NULL;
1288}
1289
1290static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1291{
1292 int i;
1293
1294 if (h->chainsize <= 0)
1295 return 0;
1296
1297 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1298 GFP_KERNEL);
1299 if (!h->cmd_sg_list)
1300 return -ENOMEM;
1301 for (i = 0; i < h->nr_cmds; i++) {
1302 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1303 h->chainsize, GFP_KERNEL);
1304 if (!h->cmd_sg_list[i])
1305 goto clean;
1306 }
1307 return 0;
1308
1309clean:
1310 hpsa_free_sg_chain_blocks(h);
1311 return -ENOMEM;
1312}
1313
e2bea6df 1314static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1315 struct CommandList *c)
1316{
1317 struct SGDescriptor *chain_sg, *chain_block;
1318 u64 temp64;
1319
1320 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1321 chain_block = h->cmd_sg_list[c->cmdindex];
1322 chain_sg->Ext = HPSA_SG_CHAIN;
1323 chain_sg->Len = sizeof(*chain_sg) *
1324 (c->Header.SGTotal - h->max_cmd_sg_entries);
1325 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1326 PCI_DMA_TODEVICE);
e2bea6df
SC		 1327 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1328 /* prevent subsequent unmapping */
1329 chain_sg->Addr.lower = 0;
1330 chain_sg->Addr.upper = 0;
1331 return -1;
1332 }
33a2ffce
SC		 1333 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1334 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1335 return 0;
33a2ffce
SC		 1336}
1337
1338static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1339 struct CommandList *c)
1340{
1341 struct SGDescriptor *chain_sg;
1342 union u64bit temp64;
1343
1344 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1345 return;
1346
1347 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1348 temp64.val32.lower = chain_sg->Addr.lower;
1349 temp64.val32.upper = chain_sg->Addr.upper;
1350 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1351}
1352
c349775e
ST		 1353static void handle_ioaccel_mode2_error(struct ctlr_info *h,
1354 struct CommandList *c,
1355 struct scsi_cmnd *cmd,
1356 struct io_accel2_cmd *c2)
1357{
1358 int data_len;
1359
1360 switch (c2->error_data.serv_response) {
1361 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1362 switch (c2->error_data.status) {
1363 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1364 break;
1365 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1366 dev_warn(&h->pdev->dev,
1367 "%s: task complete with check condition.\n",
1368 "HP SSD Smart Path");
1369 if (c2->error_data.data_present !=
1370 IOACCEL2_SENSE_DATA_PRESENT)
1371 break;
1372 /* copy the sense data */
1373 data_len = c2->error_data.sense_data_len;
1374 if (data_len > SCSI_SENSE_BUFFERSIZE)
1375 data_len = SCSI_SENSE_BUFFERSIZE;
1376 if (data_len > sizeof(c2->error_data.sense_data_buff))
1377 data_len =
1378 sizeof(c2->error_data.sense_data_buff);
1379 memcpy(cmd->sense_buffer,
1380 c2->error_data.sense_data_buff, data_len);
1381 cmd->result |= SAM_STAT_CHECK_CONDITION;
1382 break;
1383 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1384 dev_warn(&h->pdev->dev,
1385 "%s: task complete with BUSY status.\n",
1386 "HP SSD Smart Path");
1387 break;
1388 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1389 dev_warn(&h->pdev->dev,
1390 "%s: task complete with reservation conflict.\n",
1391 "HP SSD Smart Path");
1392 break;
1393 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1394 /* Make scsi midlayer do unlimited retries */
1395 cmd->result = DID_IMM_RETRY << 16;
1396 break;
1397 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1398 dev_warn(&h->pdev->dev,
1399 "%s: task complete with aborted status.\n",
1400 "HP SSD Smart Path");
1401 break;
1402 default:
1403 dev_warn(&h->pdev->dev,
1404 "%s: task complete with unrecognized status: 0x%02x\n",
1405 "HP SSD Smart Path", c2->error_data.status);
1406 break;
1407 }
1408 break;
1409 case IOACCEL2_SERV_RESPONSE_FAILURE:
1410 /* don't expect to get here. */
1411 dev_warn(&h->pdev->dev,
1412 "unexpected delivery or target failure, status = 0x%02x\n",
1413 c2->error_data.status);
1414 break;
1415 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1416 break;
1417 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1418 break;
1419 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1420 dev_warn(&h->pdev->dev, "task management function rejected.\n");
1421 break;
1422 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1423 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1424 break;
1425 default:
1426 dev_warn(&h->pdev->dev,
1427 "%s: Unrecognized server response: 0x%02x\n",
1428 "HP SSD Smart Path", c2->error_data.serv_response);
1429 break;
1430 }
1431}
1432
1433static void process_ioaccel2_completion(struct ctlr_info *h,
1434 struct CommandList *c, struct scsi_cmnd *cmd,
1435 struct hpsa_scsi_dev_t *dev)
1436{
1437 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1438
1439 /* check for good status */
1440 if (likely(c2->error_data.serv_response == 0 &&
1441 c2->error_data.status == 0)) {
1442 cmd_free(h, c);
1443 cmd->scsi_done(cmd);
1444 return;
1445 }
1446
1447 /* Any RAID offload error results in retry which will use
1448 * the normal I/O path so the controller can handle whatever's
1449 * wrong.
1450 */
1451 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1452 c2->error_data.serv_response ==
1453 IOACCEL2_SERV_RESPONSE_FAILURE) {
1454 if (c2->error_data.status !=
1455 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1456 dev_warn(&h->pdev->dev,
1457 "%s: Error 0x%02x, Retrying on standard path.\n",
1458 "HP SSD Smart Path", c2->error_data.status);
1459 dev->offload_enabled = 0;
e863d68e 1460 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1461 cmd->result = DID_SOFT_ERROR << 16;
1462 cmd_free(h, c);
1463 cmd->scsi_done(cmd);
1464 return;
1465 }
1466 handle_ioaccel_mode2_error(h, c, cmd, c2);
1467 cmd_free(h, c);
1468 cmd->scsi_done(cmd);
1469}
1470
1fb011fb 1471static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1472{
1473 struct scsi_cmnd *cmd;
1474 struct ctlr_info *h;
1475 struct ErrorInfo *ei;
283b4a9b 1476 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1477
1478 unsigned char sense_key;
1479 unsigned char asc; /* additional sense code */
1480 unsigned char ascq; /* additional sense code qualifier */
db111e18 1481 unsigned long sense_data_size;
edd16368
SC		 1482
1483 ei = cp->err_info;
1484 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1485 h = cp->h;
283b4a9b 1486 dev = cmd->device->hostdata;
edd16368
SC		 1487
1488 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1489 if ((cp->cmd_type == CMD_SCSI) &&
1490 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1491 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1492
1493 cmd->result = (DID_OK << 16); /* host byte */
1494 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1495
1496 if (cp->cmd_type == CMD_IOACCEL2)
1497 return process_ioaccel2_completion(h, cp, cmd, dev);
1498
5512672f 1499 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1500
1501 /* copy the sense data whether we need to or not. */
db111e18
SC		 1502 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1503 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1504 else
1505 sense_data_size = sizeof(ei->SenseInfo);
1506 if (ei->SenseLen < sense_data_size)
1507 sense_data_size = ei->SenseLen;
1508
1509 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1510 scsi_set_resid(cmd, ei->ResidualCnt);
1511
1512 if (ei->CommandStatus == 0) {
edd16368 1513 cmd_free(h, cp);
2cc5bfaf 1514 cmd->scsi_done(cmd);
edd16368
SC		 1515 return;
1516 }
1517
e1f7de0c
MG		 1518 /* For I/O accelerator commands, copy over some fields to the normal
1519 * CISS header used below for error handling.
1520 */
1521 if (cp->cmd_type == CMD_IOACCEL1) {
1522 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1523 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1524 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1525 cp->Header.Tag.lower = c->Tag.lower;
1526 cp->Header.Tag.upper = c->Tag.upper;
1527 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1528 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1529
1530 /* Any RAID offload error results in retry which will use
1531 * the normal I/O path so the controller can handle whatever's
1532 * wrong.
1533 */
1534 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1535 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1536 dev->offload_enabled = 0;
1537 cmd->result = DID_SOFT_ERROR << 16;
1538 cmd_free(h, cp);
1539 cmd->scsi_done(cmd);
1540 return;
1541 }
e1f7de0c
MG		 1542 }
1543
edd16368
SC		 1544 /* an error has occurred */
1545 switch (ei->CommandStatus) {
1546
1547 case CMD_TARGET_STATUS:
1548 if (ei->ScsiStatus) {
1549 /* Get sense key */
1550 sense_key = 0xf & ei->SenseInfo[2];
1551 /* Get additional sense code */
1552 asc = ei->SenseInfo[12];
1553 /* Get addition sense code qualifier */
1554 ascq = ei->SenseInfo[13];
1555 }
1556
1557 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1558 if (check_for_unit_attention(h, cp))
edd16368 1559 break;
edd16368
SC		 1560 if (sense_key == ILLEGAL_REQUEST) {
1561 /*
1562 * SCSI REPORT_LUNS is commonly unsupported on
1563 * Smart Array. Suppress noisy complaint.
1564 */
1565 if (cp->Request.CDB[0] == REPORT_LUNS)
1566 break;
1567
1568 /* If ASC/ASCQ indicate Logical Unit
1569 * Not Supported condition,
1570 */
1571 if ((asc == 0x25) && (ascq == 0x0)) {
1572 dev_warn(&h->pdev->dev, "cp %p "
1573 "has check condition\n", cp);
1574 break;
1575 }
1576 }
1577
1578 if (sense_key == NOT_READY) {
1579 /* If Sense is Not Ready, Logical Unit
1580 * Not ready, Manual Intervention
1581 * required
1582 */
1583 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1584 dev_warn(&h->pdev->dev, "cp %p "
1585 "has check condition: unit "
1586 "not ready, manual "
1587 "intervention required\n", cp);
1588 break;
1589 }
1590 }
1d3b3609
MG		 1591 if (sense_key == ABORTED_COMMAND) {
1592 /* Aborted command is retryable */
1593 dev_warn(&h->pdev->dev, "cp %p "
1594 "has check condition: aborted command: "
1595 "ASC: 0x%x, ASCQ: 0x%x\n",
1596 cp, asc, ascq);
2e311fba 1597 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1598 break;
1599 }
edd16368 1600 /* Must be some other type of check condition */
21b8e4ef 1601 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1602 "unknown type: "
1603 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1604 "Returning result: 0x%x, "
1605 "cmd=[%02x %02x %02x %02x %02x "
807be732 1606 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1607 "%02x %02x %02x %02x %02x]\n",
1608 cp, sense_key, asc, ascq,
1609 cmd->result,
1610 cmd->cmnd[0], cmd->cmnd[1],
1611 cmd->cmnd[2], cmd->cmnd[3],
1612 cmd->cmnd[4], cmd->cmnd[5],
1613 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1614 cmd->cmnd[8], cmd->cmnd[9],
1615 cmd->cmnd[10], cmd->cmnd[11],
1616 cmd->cmnd[12], cmd->cmnd[13],
1617 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1618 break;
1619 }
1620
1621
1622 /* Problem was not a check condition
1623 * Pass it up to the upper layers...
1624 */
1625 if (ei->ScsiStatus) {
1626 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1627 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1628 "Returning result: 0x%x\n",
1629 cp, ei->ScsiStatus,
1630 sense_key, asc, ascq,
1631 cmd->result);
1632 } else { /* scsi status is zero??? How??? */
1633 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1634 "Returning no connection.\n", cp),
1635
1636 /* Ordinarily, this case should never happen,
1637 * but there is a bug in some released firmware
1638 * revisions that allows it to happen if, for
1639 * example, a 4100 backplane loses power and
1640 * the tape drive is in it. We assume that
1641 * it's a fatal error of some kind because we
1642 * can't show that it wasn't. We will make it
1643 * look like selection timeout since that is
1644 * the most common reason for this to occur,
1645 * and it's severe enough.
1646 */
1647
1648 cmd->result = DID_NO_CONNECT << 16;
1649 }
1650 break;
1651
1652 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1653 break;
1654 case CMD_DATA_OVERRUN:
1655 dev_warn(&h->pdev->dev, "cp %p has"
1656 " completed with data overrun "
1657 "reported\n", cp);
1658 break;
1659 case CMD_INVALID: {
1660 /* print_bytes(cp, sizeof(*cp), 1, 0);
1661 print_cmd(cp); */
1662 /* We get CMD_INVALID if you address a non-existent device
1663 * instead of a selection timeout (no response). You will
1664 * see this if you yank out a drive, then try to access it.
1665 * This is kind of a shame because it means that any other
1666 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1667 * missing target. */
1668 cmd->result = DID_NO_CONNECT << 16;
1669 }
1670 break;
1671 case CMD_PROTOCOL_ERR:
256d0eaa 1672 cmd->result = DID_ERROR << 16;
edd16368 1673 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1674 "protocol error\n", cp);
edd16368
SC		 1675 break;
1676 case CMD_HARDWARE_ERR:
1677 cmd->result = DID_ERROR << 16;
1678 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1679 break;
1680 case CMD_CONNECTION_LOST:
1681 cmd->result = DID_ERROR << 16;
1682 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1683 break;
1684 case CMD_ABORTED:
1685 cmd->result = DID_ABORT << 16;
1686 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1687 cp, ei->ScsiStatus);
1688 break;
1689 case CMD_ABORT_FAILED:
1690 cmd->result = DID_ERROR << 16;
1691 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1692 break;
1693 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1694 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1695 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1696 "abort\n", cp);
1697 break;
1698 case CMD_TIMEOUT:
1699 cmd->result = DID_TIME_OUT << 16;
1700 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1701 break;
1d5e2ed0
SC		 1702 case CMD_UNABORTABLE:
1703 cmd->result = DID_ERROR << 16;
1704 dev_warn(&h->pdev->dev, "Command unabortable\n");
1705 break;
283b4a9b
SC		 1706 case CMD_IOACCEL_DISABLED:
1707 /* This only handles the direct pass-through case since RAID
1708 * offload is handled above. Just attempt a retry.
1709 */
1710 cmd->result = DID_SOFT_ERROR << 16;
1711 dev_warn(&h->pdev->dev,
1712 "cp %p had HP SSD Smart Path error\n", cp);
1713 break;
edd16368
SC		 1714 default:
1715 cmd->result = DID_ERROR << 16;
1716 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1717 cp, ei->CommandStatus);
1718 }
edd16368 1719 cmd_free(h, cp);
2cc5bfaf 1720 cmd->scsi_done(cmd);
edd16368
SC		 1721}
1722
edd16368
SC		 1723static void hpsa_pci_unmap(struct pci_dev *pdev,
1724 struct CommandList *c, int sg_used, int data_direction)
1725{
1726 int i;
1727 union u64bit addr64;
1728
1729 for (i = 0; i < sg_used; i++) {
1730 addr64.val32.lower = c->SG[i].Addr.lower;
1731 addr64.val32.upper = c->SG[i].Addr.upper;
1732 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1733 data_direction);
1734 }
1735}
1736
a2dac136 1737static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1738 struct CommandList *cp,
1739 unsigned char *buf,
1740 size_t buflen,
1741 int data_direction)
1742{
01a02ffc 1743 u64 addr64;
edd16368
SC		 1744
1745 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1746 cp->Header.SGList = 0;
1747 cp->Header.SGTotal = 0;
a2dac136 1748 return 0;
edd16368
SC		 1749 }
1750
01a02ffc 1751 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1752 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1753 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1754 cp->Header.SGList = 0;
1755 cp->Header.SGTotal = 0;
a2dac136 1756 return -1;
eceaae18 1757 }
edd16368 1758 cp->SG[0].Addr.lower =
01a02ffc 1759 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1760 cp->SG[0].Addr.upper =
01a02ffc 1761 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1762 cp->SG[0].Len = buflen;
e1d9cbfa 1763 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1764 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1765 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1766 return 0;
edd16368
SC		 1767}
1768
1769static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1770 struct CommandList *c)
1771{
1772 DECLARE_COMPLETION_ONSTACK(wait);
1773
1774 c->waiting = &wait;
1775 enqueue_cmd_and_start_io(h, c);
1776 wait_for_completion(&wait);
1777}
1778
a0c12413
SC		 1779static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1780 struct CommandList *c)
1781{
1782 unsigned long flags;
1783
1784 /* If controller lockup detected, fake a hardware error. */
1785 spin_lock_irqsave(&h->lock, flags);
1786 if (unlikely(h->lockup_detected)) {
1787 spin_unlock_irqrestore(&h->lock, flags);
1788 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1789 } else {
1790 spin_unlock_irqrestore(&h->lock, flags);
1791 hpsa_scsi_do_simple_cmd_core(h, c);
1792 }
1793}
1794
9c2fc160 1795#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1796static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1797 struct CommandList *c, int data_direction)
1798{
9c2fc160 1799 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1800
1801 do {
7630abd0 1802 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1803 hpsa_scsi_do_simple_cmd_core(h, c);
1804 retry_count++;
9c2fc160
SC		 1805 if (retry_count > 3) {
1806 msleep(backoff_time);
1807 if (backoff_time < 1000)
1808 backoff_time *= 2;
1809 }
852af20a 1810 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1811 check_for_busy(h, c)) &&
1812 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1813 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1814}
1815
1816static void hpsa_scsi_interpret_error(struct CommandList *cp)
1817{
1818 struct ErrorInfo *ei;
1819 struct device *d = &cp->h->pdev->dev;
1820
1821 ei = cp->err_info;
1822 switch (ei->CommandStatus) {
1823 case CMD_TARGET_STATUS:
1824 dev_warn(d, "cmd %p has completed with errors\n", cp);
1825 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1826 ei->ScsiStatus);
1827 if (ei->ScsiStatus == 0)
1828 dev_warn(d, "SCSI status is abnormally zero. "
1829 "(probably indicates selection timeout "
1830 "reported incorrectly due to a known "
1831 "firmware bug, circa July, 2001.)\n");
1832 break;
1833 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1834 dev_info(d, "UNDERRUN\n");
1835 break;
1836 case CMD_DATA_OVERRUN:
1837 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1838 break;
1839 case CMD_INVALID: {
1840 /* controller unfortunately reports SCSI passthru's
1841 * to non-existent targets as invalid commands.
1842 */
1843 dev_warn(d, "cp %p is reported invalid (probably means "
1844 "target device no longer present)\n", cp);
1845 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1846 print_cmd(cp); */
1847 }
1848 break;
1849 case CMD_PROTOCOL_ERR:
1850 dev_warn(d, "cp %p has protocol error \n", cp);
1851 break;
1852 case CMD_HARDWARE_ERR:
1853 /* cmd->result = DID_ERROR << 16; */
1854 dev_warn(d, "cp %p had hardware error\n", cp);
1855 break;
1856 case CMD_CONNECTION_LOST:
1857 dev_warn(d, "cp %p had connection lost\n", cp);
1858 break;
1859 case CMD_ABORTED:
1860 dev_warn(d, "cp %p was aborted\n", cp);
1861 break;
1862 case CMD_ABORT_FAILED:
1863 dev_warn(d, "cp %p reports abort failed\n", cp);
1864 break;
1865 case CMD_UNSOLICITED_ABORT:
1866 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1867 break;
1868 case CMD_TIMEOUT:
1869 dev_warn(d, "cp %p timed out\n", cp);
1870 break;
1d5e2ed0
SC		 1871 case CMD_UNABORTABLE:
1872 dev_warn(d, "Command unabortable\n");
1873 break;
edd16368
SC		 1874 default:
1875 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1876 ei->CommandStatus);
1877 }
1878}
1879
1880static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1881 unsigned char page, unsigned char *buf,
1882 unsigned char bufsize)
1883{
1884 int rc = IO_OK;
1885 struct CommandList *c;
1886 struct ErrorInfo *ei;
1887
1888 c = cmd_special_alloc(h);
1889
1890 if (c == NULL) { /* trouble... */
1891 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1892 return -ENOMEM;
edd16368
SC		 1893 }
1894
a2dac136
SC		 1895 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1896 page, scsi3addr, TYPE_CMD)) {
1897 rc = -1;
1898 goto out;
1899 }
edd16368
SC		 1900 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1901 ei = c->err_info;
1902 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1903 hpsa_scsi_interpret_error(c);
1904 rc = -1;
1905 }
a2dac136 1906out:
edd16368
SC		 1907 cmd_special_free(h, c);
1908 return rc;
1909}
1910
bf711ac6
ST		 1911static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
1912 u8 reset_type)
edd16368
SC		 1913{
1914 int rc = IO_OK;
1915 struct CommandList *c;
1916 struct ErrorInfo *ei;
1917
1918 c = cmd_special_alloc(h);
1919
1920 if (c == NULL) { /* trouble... */
1921 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1922 return -ENOMEM;
edd16368
SC		 1923 }
1924
a2dac136 1925 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 1926 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
1927 scsi3addr, TYPE_MSG);
1928 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 1929 hpsa_scsi_do_simple_cmd_core(h, c);
1930 /* no unmap needed here because no data xfer. */
1931
1932 ei = c->err_info;
1933 if (ei->CommandStatus != 0) {
1934 hpsa_scsi_interpret_error(c);
1935 rc = -1;
1936 }
1937 cmd_special_free(h, c);
1938 return rc;
1939}
1940
1941static void hpsa_get_raid_level(struct ctlr_info *h,
1942 unsigned char *scsi3addr, unsigned char *raid_level)
1943{
1944 int rc;
1945 unsigned char *buf;
1946
1947 *raid_level = RAID_UNKNOWN;
1948 buf = kzalloc(64, GFP_KERNEL);
1949 if (!buf)
1950 return;
1951 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1952 if (rc == 0)
1953 *raid_level = buf[8];
1954 if (*raid_level > RAID_UNKNOWN)
1955 *raid_level = RAID_UNKNOWN;
1956 kfree(buf);
1957 return;
1958}
1959
283b4a9b
SC		 1960#define HPSA_MAP_DEBUG
1961#ifdef HPSA_MAP_DEBUG
1962static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1963 struct raid_map_data *map_buff)
1964{
1965 struct raid_map_disk_data *dd = &map_buff->data[0];
1966 int map, row, col;
1967 u16 map_cnt, row_cnt, disks_per_row;
1968
1969 if (rc != 0)
1970 return;
1971
1972 dev_info(&h->pdev->dev, "structure_size = %u\n",
1973 le32_to_cpu(map_buff->structure_size));
1974 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1975 le32_to_cpu(map_buff->volume_blk_size));
1976 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1977 le64_to_cpu(map_buff->volume_blk_cnt));
1978 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1979 map_buff->phys_blk_shift);
1980 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1981 map_buff->parity_rotation_shift);
1982 dev_info(&h->pdev->dev, "strip_size = %u\n",
1983 le16_to_cpu(map_buff->strip_size));
1984 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1985 le64_to_cpu(map_buff->disk_starting_blk));
1986 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1987 le64_to_cpu(map_buff->disk_blk_cnt));
1988 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1989 le16_to_cpu(map_buff->data_disks_per_row));
1990 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1991 le16_to_cpu(map_buff->metadata_disks_per_row));
1992 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1993 le16_to_cpu(map_buff->row_cnt));
1994 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1995 le16_to_cpu(map_buff->layout_map_count));
1996
1997 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1998 for (map = 0; map < map_cnt; map++) {
1999 dev_info(&h->pdev->dev, "Map%u:\n", map);
2000 row_cnt = le16_to_cpu(map_buff->row_cnt);
2001 for (row = 0; row < row_cnt; row++) {
2002 dev_info(&h->pdev->dev, " Row%u:\n", row);
2003 disks_per_row =
2004 le16_to_cpu(map_buff->data_disks_per_row);
2005 for (col = 0; col < disks_per_row; col++, dd++)
2006 dev_info(&h->pdev->dev,
2007 " D%02u: h=0x%04x xor=%u,%u\n",
2008 col, dd->ioaccel_handle,
2009 dd->xor_mult[0], dd->xor_mult[1]);
2010 disks_per_row =
2011 le16_to_cpu(map_buff->metadata_disks_per_row);
2012 for (col = 0; col < disks_per_row; col++, dd++)
2013 dev_info(&h->pdev->dev,
2014 " M%02u: h=0x%04x xor=%u,%u\n",
2015 col, dd->ioaccel_handle,
2016 dd->xor_mult[0], dd->xor_mult[1]);
2017 }
2018 }
2019}
2020#else
2021static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2022 __attribute__((unused)) int rc,
2023 __attribute__((unused)) struct raid_map_data *map_buff)
2024{
2025}
2026#endif
2027
2028static int hpsa_get_raid_map(struct ctlr_info *h,
2029 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2030{
2031 int rc = 0;
2032 struct CommandList *c;
2033 struct ErrorInfo *ei;
2034
2035 c = cmd_special_alloc(h);
2036 if (c == NULL) {
2037 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2038 return -ENOMEM;
2039 }
2040 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2041 sizeof(this_device->raid_map), 0,
2042 scsi3addr, TYPE_CMD)) {
2043 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2044 cmd_special_free(h, c);
2045 return -ENOMEM;
2046 }
2047 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2048 ei = c->err_info;
2049 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2050 hpsa_scsi_interpret_error(c);
2051 cmd_special_free(h, c);
2052 return -1;
2053 }
2054 cmd_special_free(h, c);
2055
2056 /* @todo in the future, dynamically allocate RAID map memory */
2057 if (le32_to_cpu(this_device->raid_map.structure_size) >
2058 sizeof(this_device->raid_map)) {
2059 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2060 rc = -1;
2061 }
2062 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2063 return rc;
2064}
2065
2066static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2067 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2068{
2069 int rc;
2070 unsigned char *buf;
2071 u8 ioaccel_status;
2072
2073 this_device->offload_config = 0;
2074 this_device->offload_enabled = 0;
2075
2076 buf = kzalloc(64, GFP_KERNEL);
2077 if (!buf)
2078 return;
2079 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2080 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
2081 if (rc != 0)
2082 goto out;
2083
2084#define IOACCEL_STATUS_BYTE 4
2085#define OFFLOAD_CONFIGURED_BIT 0x01
2086#define OFFLOAD_ENABLED_BIT 0x02
2087 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2088 this_device->offload_config =
2089 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2090 if (this_device->offload_config) {
2091 this_device->offload_enabled =
2092 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2093 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2094 this_device->offload_enabled = 0;
2095 }
2096out:
2097 kfree(buf);
2098 return;
2099}
2100
edd16368
SC		 2101/* Get the device id from inquiry page 0x83 */
2102static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2103 unsigned char *device_id, int buflen)
2104{
2105 int rc;
2106 unsigned char *buf;
2107
2108 if (buflen > 16)
2109 buflen = 16;
2110 buf = kzalloc(64, GFP_KERNEL);
2111 if (!buf)
2112 return -1;
2113 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
2114 if (rc == 0)
2115 memcpy(device_id, &buf[8], buflen);
2116 kfree(buf);
2117 return rc != 0;
2118}
2119
2120static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2121 struct ReportLUNdata *buf, int bufsize,
2122 int extended_response)
2123{
2124 int rc = IO_OK;
2125 struct CommandList *c;
2126 unsigned char scsi3addr[8];
2127 struct ErrorInfo *ei;
2128
2129 c = cmd_special_alloc(h);
2130 if (c == NULL) { /* trouble... */
2131 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2132 return -1;
2133 }
e89c0ae7
SC		 2134 /* address the controller */
2135 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2136 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2137 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2138 rc = -1;
2139 goto out;
2140 }
edd16368
SC		 2141 if (extended_response)
2142 c->Request.CDB[1] = extended_response;
2143 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2144 ei = c->err_info;
2145 if (ei->CommandStatus != 0 &&
2146 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2147 hpsa_scsi_interpret_error(c);
2148 rc = -1;
283b4a9b
SC		 2149 } else {
2150 if (buf->extended_response_flag != extended_response) {
2151 dev_err(&h->pdev->dev,
2152 "report luns requested format %u, got %u\n",
2153 extended_response,
2154 buf->extended_response_flag);
2155 rc = -1;
2156 }
edd16368 2157 }
a2dac136 2158out:
edd16368
SC		 2159 cmd_special_free(h, c);
2160 return rc;
2161}
2162
2163static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2164 struct ReportLUNdata *buf,
2165 int bufsize, int extended_response)
2166{
2167 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2168}
2169
2170static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2171 struct ReportLUNdata *buf, int bufsize)
2172{
2173 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2174}
2175
2176static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2177 int bus, int target, int lun)
2178{
2179 device->bus = bus;
2180 device->target = target;
2181 device->lun = lun;
2182}
2183
2184static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2185 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2186 unsigned char *is_OBDR_device)
edd16368 2187{
0b0e1d6c
SC		 2188
2189#define OBDR_SIG_OFFSET 43
2190#define OBDR_TAPE_SIG "$DR-10"
2191#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2192#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2193
ea6d3bc3 2194 unsigned char *inq_buff;
0b0e1d6c 2195 unsigned char *obdr_sig;
edd16368 2196
ea6d3bc3 2197 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2198 if (!inq_buff)
2199 goto bail_out;
2200
edd16368
SC		 2201 /* Do an inquiry to the device to see what it is. */
2202 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2203 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2204 /* Inquiry failed (msg printed already) */
2205 dev_err(&h->pdev->dev,
2206 "hpsa_update_device_info: inquiry failed\n");
2207 goto bail_out;
2208 }
2209
edd16368
SC		 2210 this_device->devtype = (inq_buff[0] & 0x1f);
2211 memcpy(this_device->scsi3addr, scsi3addr, 8);
2212 memcpy(this_device->vendor, &inq_buff[8],
2213 sizeof(this_device->vendor));
2214 memcpy(this_device->model, &inq_buff[16],
2215 sizeof(this_device->model));
edd16368
SC		 2216 memset(this_device->device_id, 0,
2217 sizeof(this_device->device_id));
2218 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2219 sizeof(this_device->device_id));
2220
2221 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2222 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2223 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2224 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2225 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2226 } else {
edd16368 2227 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2228 this_device->offload_config = 0;
2229 this_device->offload_enabled = 0;
2230 }
edd16368 2231
0b0e1d6c
SC		 2232 if (is_OBDR_device) {
2233 /* See if this is a One-Button-Disaster-Recovery device
2234 * by looking for "$DR-10" at offset 43 in inquiry data.
2235 */
2236 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2237 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2238 strncmp(obdr_sig, OBDR_TAPE_SIG,
2239 OBDR_SIG_LEN) == 0);
2240 }
2241
edd16368
SC		 2242 kfree(inq_buff);
2243 return 0;
2244
2245bail_out:
2246 kfree(inq_buff);
2247 return 1;
2248}
2249
4f4eb9f1 2250static unsigned char *ext_target_model[] = {
edd16368
SC		 2251 "MSA2012",
2252 "MSA2024",
2253 "MSA2312",
2254 "MSA2324",
fda38518 2255 "P2000 G3 SAS",
e06c8e5c 2256 "MSA 2040 SAS",
edd16368
SC		 2257 NULL,
2258};
2259
4f4eb9f1 2260static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2261{
2262 int i;
2263
4f4eb9f1
ST		 2264 for (i = 0; ext_target_model[i]; i++)
2265 if (strncmp(device->model, ext_target_model[i],
2266 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2267 return 1;
2268 return 0;
2269}
2270
2271/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2272 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2273 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2274 * Logical drive target and lun are assigned at this time, but
2275 * physical device lun and target assignment are deferred (assigned
2276 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2277 */
2278static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2279 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2280{
1f310bde
SC		 2281 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2282
2283 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2284 /* physical device, target and lun filled in later */
edd16368 2285 if (is_hba_lunid(lunaddrbytes))
1f310bde 2286 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2287 else
1f310bde
SC		 2288 /* defer target, lun assignment for physical devices */
2289 hpsa_set_bus_target_lun(device, 2, -1, -1);
2290 return;
2291 }
2292 /* It's a logical device */
4f4eb9f1
ST		 2293 if (is_ext_target(h, device)) {
2294 /* external target way, put logicals on bus 1
1f310bde
SC		 2295 * and match target/lun numbers box
2296 * reports, other smart array, bus 0, target 0, match lunid
2297 */
2298 hpsa_set_bus_target_lun(device,
2299 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2300 return;
edd16368 2301 }
1f310bde 2302 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2303}
2304
2305/*
2306 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2307 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2308 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2309 * it for some reason. *tmpdevice is the target we're adding,
2310 * this_device is a pointer into the current element of currentsd[]
2311 * that we're building up in update_scsi_devices(), below.
2312 * lunzerobits is a bitmap that tracks which targets already have a
2313 * lun 0 assigned.
2314 * Returns 1 if an enclosure was added, 0 if not.
2315 */
4f4eb9f1 2316static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2317 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2318 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2319 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2320{
2321 unsigned char scsi3addr[8];
2322
1f310bde 2323 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2324 return 0; /* There is already a lun 0 on this target. */
2325
2326 if (!is_logical_dev_addr_mode(lunaddrbytes))
2327 return 0; /* It's the logical targets that may lack lun 0. */
2328
4f4eb9f1
ST		 2329 if (!is_ext_target(h, tmpdevice))
2330 return 0; /* Only external target devices have this problem. */
edd16368 2331
1f310bde 2332 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2333 return 0;
2334
c4f8a299 2335 memset(scsi3addr, 0, 8);
1f310bde 2336 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2337 if (is_hba_lunid(scsi3addr))
2338 return 0; /* Don't add the RAID controller here. */
2339
339b2b14
SC		 2340 if (is_scsi_rev_5(h))
2341 return 0; /* p1210m doesn't need to do this. */
2342
4f4eb9f1 2343 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2344 dev_warn(&h->pdev->dev, "Maximum number of external "
2345 "target devices exceeded. Check your hardware "
edd16368
SC		 2346 "configuration.");
2347 return 0;
2348 }
2349
0b0e1d6c 2350 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2351 return 0;
4f4eb9f1 2352 (*n_ext_target_devs)++;
1f310bde
SC		 2353 hpsa_set_bus_target_lun(this_device,
2354 tmpdevice->bus, tmpdevice->target, 0);
2355 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2356 return 1;
2357}
2358
54b6e9e9
ST		 2359/*
2360 * Get address of physical disk used for an ioaccel2 mode command:
2361 * 1. Extract ioaccel2 handle from the command.
2362 * 2. Find a matching ioaccel2 handle from list of physical disks.
2363 * 3. Return:
2364 * 1 and set scsi3addr to address of matching physical
2365 * 0 if no matching physical disk was found.
2366 */
2367static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2368 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2369{
2370 struct ReportExtendedLUNdata *physicals = NULL;
2371 int responsesize = 24; /* size of physical extended response */
2372 int extended = 2; /* flag forces reporting 'other dev info'. */
2373 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2374 u32 nphysicals = 0; /* number of reported physical devs */
2375 int found = 0; /* found match (1) or not (0) */
2376 u32 find; /* handle we need to match */
2377 int i;
2378 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2379 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2380 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2381 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2382 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2383
2384 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2385 return 0; /* no match */
2386
2387 /* point to the ioaccel2 device handle */
2388 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2389 if (c2a == NULL)
2390 return 0; /* no match */
2391
2392 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2393 if (scmd == NULL)
2394 return 0; /* no match */
2395
2396 d = scmd->device->hostdata;
2397 if (d == NULL)
2398 return 0; /* no match */
2399
2400 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2401 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2402 find = c2a->scsi_nexus;
2403
2404 /* Get the list of physical devices */
2405 physicals = kzalloc(reportsize, GFP_KERNEL);
2406 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2407 reportsize, extended)) {
2408 dev_err(&h->pdev->dev,
2409 "Can't lookup %s device handle: report physical LUNs failed.\n",
2410 "HP SSD Smart Path");
2411 kfree(physicals);
2412 return 0;
2413 }
2414 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2415 responsesize;
2416
2417
2418 /* find ioaccel2 handle in list of physicals: */
2419 for (i = 0; i < nphysicals; i++) {
2420 /* handle is in bytes 28-31 of each lun */
2421 if (memcmp(&((struct ReportExtendedLUNdata *)
2422 physicals)->LUN[i][20], &find, 4) != 0) {
2423 continue; /* didn't match */
2424 }
2425 found = 1;
2426 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2427 physicals)->LUN[i][0], 8);
2428 break; /* found it */
2429 }
2430
2431 kfree(physicals);
2432 if (found)
2433 return 1;
2434 else
2435 return 0;
2436
2437}
edd16368
SC		 2438/*
2439 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2440 * logdev. The number of luns in physdev and logdev are returned in
2441 * *nphysicals and *nlogicals, respectively.
2442 * Returns 0 on success, -1 otherwise.
2443 */
2444static int hpsa_gather_lun_info(struct ctlr_info *h,
2445 int reportlunsize,
283b4a9b 2446 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2447 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2448{
283b4a9b
SC		 2449 int physical_entry_size = 8;
2450
2451 *physical_mode = 0;
2452
2453 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2454 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2455 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2456 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2457 physical_entry_size = 24;
2458 }
a93aa1fe 2459 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2460 *physical_mode)) {
edd16368
SC		 2461 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2462 return -1;
2463 }
283b4a9b
SC		 2464 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2465 physical_entry_size;
edd16368
SC		 2466 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2467 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2468 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2469 *nphysicals - HPSA_MAX_PHYS_LUN);
2470 *nphysicals = HPSA_MAX_PHYS_LUN;
2471 }
2472 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2473 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2474 return -1;
2475 }
6df1e954 2476 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2477 /* Reject Logicals in excess of our max capability. */
2478 if (*nlogicals > HPSA_MAX_LUN) {
2479 dev_warn(&h->pdev->dev,
2480 "maximum logical LUNs (%d) exceeded. "
2481 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2482 *nlogicals - HPSA_MAX_LUN);
2483 *nlogicals = HPSA_MAX_LUN;
2484 }
2485 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2486 dev_warn(&h->pdev->dev,
2487 "maximum logical + physical LUNs (%d) exceeded. "
2488 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2489 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2490 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2491 }
2492 return 0;
2493}
2494
339b2b14 2495u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2496 int nphysicals, int nlogicals,
2497 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2498 struct ReportLUNdata *logdev_list)
2499{
2500 /* Helper function, figure out where the LUN ID info is coming from
2501 * given index i, lists of physical and logical devices, where in
2502 * the list the raid controller is supposed to appear (first or last)
2503 */
2504
2505 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2506 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2507
2508 if (i == raid_ctlr_position)
2509 return RAID_CTLR_LUNID;
2510
2511 if (i < logicals_start)
2512 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2513
2514 if (i < last_device)
2515 return &logdev_list->LUN[i - nphysicals -
2516 (raid_ctlr_position == 0)][0];
2517 BUG();
2518 return NULL;
2519}
2520
edd16368
SC		 2521static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2522{
2523 /* the idea here is we could get notified
2524 * that some devices have changed, so we do a report
2525 * physical luns and report logical luns cmd, and adjust
2526 * our list of devices accordingly.
2527 *
2528 * The scsi3addr's of devices won't change so long as the
2529 * adapter is not reset. That means we can rescan and
2530 * tell which devices we already know about, vs. new
2531 * devices, vs. disappearing devices.
2532 */
a93aa1fe 2533 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2534 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2535 u32 nphysicals = 0;
2536 u32 nlogicals = 0;
283b4a9b 2537 int physical_mode = 0;
01a02ffc 2538 u32 ndev_allocated = 0;
edd16368
SC		 2539 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2540 int ncurrent = 0;
283b4a9b 2541 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2542 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2543 int raid_ctlr_position;
aca4a520 2544 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2545
cfe5badc 2546 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2547 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2548 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2549 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2550
0b0e1d6c 2551 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2552 dev_err(&h->pdev->dev, "out of memory\n");
2553 goto out;
2554 }
2555 memset(lunzerobits, 0, sizeof(lunzerobits));
2556
a93aa1fe
MG		 2557 if (hpsa_gather_lun_info(h, reportlunsize,
2558 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2559 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2560 goto out;
2561
aca4a520
ST		 2562 /* We might see up to the maximum number of logical and physical disks
2563 * plus external target devices, and a device for the local RAID
2564 * controller.
edd16368 2565 */
aca4a520 2566 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2567
2568 /* Allocate the per device structures */
2569 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2570 if (i >= HPSA_MAX_DEVICES) {
2571 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2572 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2573 ndevs_to_allocate - HPSA_MAX_DEVICES);
2574 break;
2575 }
2576
edd16368
SC		 2577 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2578 if (!currentsd[i]) {
2579 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2580 __FILE__, __LINE__);
2581 goto out;
2582 }
2583 ndev_allocated++;
2584 }
2585
339b2b14
SC		 2586 if (unlikely(is_scsi_rev_5(h)))
2587 raid_ctlr_position = 0;
2588 else
2589 raid_ctlr_position = nphysicals + nlogicals;
2590
edd16368 2591 /* adjust our table of devices */
4f4eb9f1 2592 n_ext_target_devs = 0;
edd16368 2593 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2594 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2595
2596 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2597 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2598 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2599 /* skip masked physical devices. */
339b2b14
SC		 2600 if (lunaddrbytes[3] & 0xC0 &&
2601 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2602 continue;
2603
2604 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2605 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2606 &is_OBDR))
edd16368 2607 continue; /* skip it if we can't talk to it. */
1f310bde 2608 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2609 this_device = currentsd[ncurrent];
2610
2611 /*
4f4eb9f1 2612 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2613 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2614 * is nonetheless an enclosure device there. We have to
2615 * present that otherwise linux won't find anything if
2616 * there is no lun 0.
2617 */
4f4eb9f1 2618 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2619 lunaddrbytes, lunzerobits,
4f4eb9f1 2620 &n_ext_target_devs)) {
edd16368
SC		 2621 ncurrent++;
2622 this_device = currentsd[ncurrent];
2623 }
2624
2625 *this_device = *tmpdevice;
edd16368
SC		 2626
2627 switch (this_device->devtype) {
0b0e1d6c 2628 case TYPE_ROM:
edd16368
SC		 2629 /* We don't *really* support actual CD-ROM devices,
2630 * just "One Button Disaster Recovery" tape drive
2631 * which temporarily pretends to be a CD-ROM drive.
2632 * So we check that the device is really an OBDR tape
2633 * device by checking for "$DR-10" in bytes 43-48 of
2634 * the inquiry data.
2635 */
0b0e1d6c
SC		 2636 if (is_OBDR)
2637 ncurrent++;
edd16368
SC		 2638 break;
2639 case TYPE_DISK:
283b4a9b
SC		 2640 if (i >= nphysicals) {
2641 ncurrent++;
edd16368 2642 break;
283b4a9b
SC		 2643 }
2644 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2645 memcpy(&this_device->ioaccel_handle,
2646 &lunaddrbytes[20],
2647 sizeof(this_device->ioaccel_handle));
2648 ncurrent++;
2649 }
edd16368
SC		 2650 break;
2651 case TYPE_TAPE:
2652 case TYPE_MEDIUM_CHANGER:
2653 ncurrent++;
2654 break;
2655 case TYPE_RAID:
2656 /* Only present the Smartarray HBA as a RAID controller.
2657 * If it's a RAID controller other than the HBA itself
2658 * (an external RAID controller, MSA500 or similar)
2659 * don't present it.
2660 */
2661 if (!is_hba_lunid(lunaddrbytes))
2662 break;
2663 ncurrent++;
2664 break;
2665 default:
2666 break;
2667 }
cfe5badc 2668 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2669 break;
2670 }
2671 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2672out:
2673 kfree(tmpdevice);
2674 for (i = 0; i < ndev_allocated; i++)
2675 kfree(currentsd[i]);
2676 kfree(currentsd);
edd16368
SC		 2677 kfree(physdev_list);
2678 kfree(logdev_list);
edd16368
SC		 2679}
2680
2681/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2682 * dma mapping and fills in the scatter gather entries of the
2683 * hpsa command, cp.
2684 */
33a2ffce 2685static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2686 struct CommandList *cp,
2687 struct scsi_cmnd *cmd)
2688{
2689 unsigned int len;
2690 struct scatterlist *sg;
01a02ffc 2691 u64 addr64;
33a2ffce
SC		 2692 int use_sg, i, sg_index, chained;
2693 struct SGDescriptor *curr_sg;
edd16368 2694
33a2ffce 2695 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2696
2697 use_sg = scsi_dma_map(cmd);
2698 if (use_sg < 0)
2699 return use_sg;
2700
2701 if (!use_sg)
2702 goto sglist_finished;
2703
33a2ffce
SC		 2704 curr_sg = cp->SG;
2705 chained = 0;
2706 sg_index = 0;
edd16368 2707 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2708 if (i == h->max_cmd_sg_entries - 1 &&
2709 use_sg > h->max_cmd_sg_entries) {
2710 chained = 1;
2711 curr_sg = h->cmd_sg_list[cp->cmdindex];
2712 sg_index = 0;
2713 }
01a02ffc 2714 addr64 = (u64) sg_dma_address(sg);
edd16368 2715 len = sg_dma_len(sg);
33a2ffce
SC		 2716 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2717 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2718 curr_sg->Len = len;
e1d9cbfa 2719 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2720 curr_sg++;
2721 }
2722
2723 if (use_sg + chained > h->maxSG)
2724 h->maxSG = use_sg + chained;
2725
2726 if (chained) {
2727 cp->Header.SGList = h->max_cmd_sg_entries;
2728 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2729 if (hpsa_map_sg_chain_block(h, cp)) {
2730 scsi_dma_unmap(cmd);
2731 return -1;
2732 }
33a2ffce 2733 return 0;
edd16368
SC		 2734 }
2735
2736sglist_finished:
2737
01a02ffc
SC		 2738 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2739 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2740 return 0;
2741}
2742
283b4a9b
SC		 2743#define IO_ACCEL_INELIGIBLE (1)
2744static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2745{
2746 int is_write = 0;
2747 u32 block;
2748 u32 block_cnt;
2749
2750 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2751 switch (cdb[0]) {
2752 case WRITE_6:
2753 case WRITE_12:
2754 is_write = 1;
2755 case READ_6:
2756 case READ_12:
2757 if (*cdb_len == 6) {
2758 block = (((u32) cdb[2]) << 8) | cdb[3];
2759 block_cnt = cdb[4];
2760 } else {
2761 BUG_ON(*cdb_len != 12);
2762 block = (((u32) cdb[2]) << 24) |
2763 (((u32) cdb[3]) << 16) |
2764 (((u32) cdb[4]) << 8) |
2765 cdb[5];
2766 block_cnt =
2767 (((u32) cdb[6]) << 24) |
2768 (((u32) cdb[7]) << 16) |
2769 (((u32) cdb[8]) << 8) |
2770 cdb[9];
2771 }
2772 if (block_cnt > 0xffff)
2773 return IO_ACCEL_INELIGIBLE;
2774
2775 cdb[0] = is_write ? WRITE_10 : READ_10;
2776 cdb[1] = 0;
2777 cdb[2] = (u8) (block >> 24);
2778 cdb[3] = (u8) (block >> 16);
2779 cdb[4] = (u8) (block >> 8);
2780 cdb[5] = (u8) (block);
2781 cdb[6] = 0;
2782 cdb[7] = (u8) (block_cnt >> 8);
2783 cdb[8] = (u8) (block_cnt);
2784 cdb[9] = 0;
2785 *cdb_len = 10;
2786 break;
2787 }
2788 return 0;
2789}
2790
c349775e 2791static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2792 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2793 u8 *scsi3addr)
e1f7de0c
MG		 2794{
2795 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2796 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2797 unsigned int len;
2798 unsigned int total_len = 0;
2799 struct scatterlist *sg;
2800 u64 addr64;
2801 int use_sg, i;
2802 struct SGDescriptor *curr_sg;
2803 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2804
283b4a9b
SC		 2805 /* TODO: implement chaining support */
2806 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2807 return IO_ACCEL_INELIGIBLE;
2808
e1f7de0c
MG		 2809 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2810
283b4a9b
SC		 2811 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2812 return IO_ACCEL_INELIGIBLE;
2813
e1f7de0c
MG		 2814 c->cmd_type = CMD_IOACCEL1;
2815
2816 /* Adjust the DMA address to point to the accelerated command buffer */
2817 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2818 (c->cmdindex * sizeof(*cp));
2819 BUG_ON(c->busaddr & 0x0000007F);
2820
2821 use_sg = scsi_dma_map(cmd);
2822 if (use_sg < 0)
2823 return use_sg;
2824
2825 if (use_sg) {
2826 curr_sg = cp->SG;
2827 scsi_for_each_sg(cmd, sg, use_sg, i) {
2828 addr64 = (u64) sg_dma_address(sg);
2829 len = sg_dma_len(sg);
2830 total_len += len;
2831 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2832 curr_sg->Addr.upper =
2833 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2834 curr_sg->Len = len;
2835
2836 if (i == (scsi_sg_count(cmd) - 1))
2837 curr_sg->Ext = HPSA_SG_LAST;
2838 else
2839 curr_sg->Ext = 0; /* we are not chaining */
2840 curr_sg++;
2841 }
2842
2843 switch (cmd->sc_data_direction) {
2844 case DMA_TO_DEVICE:
2845 control |= IOACCEL1_CONTROL_DATA_OUT;
2846 break;
2847 case DMA_FROM_DEVICE:
2848 control |= IOACCEL1_CONTROL_DATA_IN;
2849 break;
2850 case DMA_NONE:
2851 control |= IOACCEL1_CONTROL_NODATAXFER;
2852 break;
2853 default:
2854 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2855 cmd->sc_data_direction);
2856 BUG();
2857 break;
2858 }
2859 } else {
2860 control |= IOACCEL1_CONTROL_NODATAXFER;
2861 }
2862
c349775e 2863 c->Header.SGList = use_sg;
e1f7de0c 2864 /* Fill out the command structure to submit */
283b4a9b 2865 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2866 cp->transfer_len = total_len;
2867 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2868 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2869 cp->control = control;
283b4a9b
SC		 2870 memcpy(cp->CDB, cdb, cdb_len);
2871 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2872 /* Tag was already set at init time. */
283b4a9b 2873 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2874 return 0;
2875}
edd16368 2876
283b4a9b
SC		 2877/*
2878 * Queue a command directly to a device behind the controller using the
2879 * I/O accelerator path.
2880 */
2881static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2882 struct CommandList *c)
2883{
2884 struct scsi_cmnd *cmd = c->scsi_cmd;
2885 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2886
2887 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2888 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2889}
2890
c349775e
ST		 2891static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
2892 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2893 u8 *scsi3addr)
2894{
2895 struct scsi_cmnd *cmd = c->scsi_cmd;
2896 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
2897 struct ioaccel2_sg_element *curr_sg;
2898 int use_sg, i;
2899 struct scatterlist *sg;
2900 u64 addr64;
2901 u32 len;
2902 u32 total_len = 0;
2903
2904 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2905 return IO_ACCEL_INELIGIBLE;
2906
2907 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2908 return IO_ACCEL_INELIGIBLE;
2909 c->cmd_type = CMD_IOACCEL2;
2910 /* Adjust the DMA address to point to the accelerated command buffer */
2911 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
2912 (c->cmdindex * sizeof(*cp));
2913 BUG_ON(c->busaddr & 0x0000007F);
2914
2915 memset(cp, 0, sizeof(*cp));
2916 cp->IU_type = IOACCEL2_IU_TYPE;
2917
2918 use_sg = scsi_dma_map(cmd);
2919 if (use_sg < 0)
2920 return use_sg;
2921
2922 if (use_sg) {
2923 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
2924 curr_sg = cp->sg;
2925 scsi_for_each_sg(cmd, sg, use_sg, i) {
2926 addr64 = (u64) sg_dma_address(sg);
2927 len = sg_dma_len(sg);
2928 total_len += len;
2929 curr_sg->address = cpu_to_le64(addr64);
2930 curr_sg->length = cpu_to_le32(len);
2931 curr_sg->reserved[0] = 0;
2932 curr_sg->reserved[1] = 0;
2933 curr_sg->reserved[2] = 0;
2934 curr_sg->chain_indicator = 0;
2935 curr_sg++;
2936 }
2937
2938 switch (cmd->sc_data_direction) {
2939 case DMA_TO_DEVICE:
2940 cp->direction = IOACCEL2_DIR_DATA_OUT;
2941 break;
2942 case DMA_FROM_DEVICE:
2943 cp->direction = IOACCEL2_DIR_DATA_IN;
2944 break;
2945 case DMA_NONE:
2946 cp->direction = IOACCEL2_DIR_NO_DATA;
2947 break;
2948 default:
2949 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2950 cmd->sc_data_direction);
2951 BUG();
2952 break;
2953 }
2954 } else {
2955 cp->direction = IOACCEL2_DIR_NO_DATA;
2956 }
2957 cp->scsi_nexus = ioaccel_handle;
2958 cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
2959 DIRECT_LOOKUP_BIT;
2960 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
2961 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
2962 cp->cmd_priority_task_attr = 0;
2963
2964 /* fill in sg elements */
2965 cp->sg_count = (u8) use_sg;
2966
2967 cp->data_len = cpu_to_le32(total_len);
2968 cp->err_ptr = cpu_to_le64(c->busaddr +
2969 offsetof(struct io_accel2_cmd, error_data));
2970 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
2971
2972 enqueue_cmd_and_start_io(h, c);
2973 return 0;
2974}
2975
2976/*
2977 * Queue a command to the correct I/O accelerator path.
2978 */
2979static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
2980 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2981 u8 *scsi3addr)
2982{
2983 if (h->transMethod & CFGTBL_Trans_io_accel1)
2984 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
2985 cdb, cdb_len, scsi3addr);
2986 else
2987 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
2988 cdb, cdb_len, scsi3addr);
2989}
2990
6b80b18f
ST		 2991static void raid_map_helper(struct raid_map_data *map,
2992 int offload_to_mirror, u32 *map_index, u32 *current_group)
2993{
2994 if (offload_to_mirror == 0) {
2995 /* use physical disk in the first mirrored group. */
2996 *map_index %= map->data_disks_per_row;
2997 return;
2998 }
2999 do {
3000 /* determine mirror group that *map_index indicates */
3001 *current_group = *map_index / map->data_disks_per_row;
3002 if (offload_to_mirror == *current_group)
3003 continue;
3004 if (*current_group < (map->layout_map_count - 1)) {
3005 /* select map index from next group */
3006 *map_index += map->data_disks_per_row;
3007 (*current_group)++;
3008 } else {
3009 /* select map index from first group */
3010 *map_index %= map->data_disks_per_row;
3011 *current_group = 0;
3012 }
3013 } while (offload_to_mirror != *current_group);
3014}
3015
283b4a9b
SC		 3016/*
3017 * Attempt to perform offload RAID mapping for a logical volume I/O.
3018 */
3019static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3020 struct CommandList *c)
3021{
3022 struct scsi_cmnd *cmd = c->scsi_cmd;
3023 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3024 struct raid_map_data *map = &dev->raid_map;
3025 struct raid_map_disk_data *dd = &map->data[0];
3026 int is_write = 0;
3027 u32 map_index;
3028 u64 first_block, last_block;
3029 u32 block_cnt;
3030 u32 blocks_per_row;
3031 u64 first_row, last_row;
3032 u32 first_row_offset, last_row_offset;
3033 u32 first_column, last_column;
6b80b18f
ST		 3034 u64 r0_first_row, r0_last_row;
3035 u32 r5or6_blocks_per_row;
3036 u64 r5or6_first_row, r5or6_last_row;
3037 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3038 u32 r5or6_first_column, r5or6_last_column;
3039 u32 total_disks_per_row;
3040 u32 stripesize;
3041 u32 first_group, last_group, current_group;
283b4a9b
SC		 3042 u32 map_row;
3043 u32 disk_handle;
3044 u64 disk_block;
3045 u32 disk_block_cnt;
3046 u8 cdb[16];
3047 u8 cdb_len;
3048#if BITS_PER_LONG == 32
3049 u64 tmpdiv;
3050#endif
6b80b18f 3051 int offload_to_mirror;
283b4a9b
SC		 3052
3053 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3054
3055 /* check for valid opcode, get LBA and block count */
3056 switch (cmd->cmnd[0]) {
3057 case WRITE_6:
3058 is_write = 1;
3059 case READ_6:
3060 first_block =
3061 (((u64) cmd->cmnd[2]) << 8) |
3062 cmd->cmnd[3];
3063 block_cnt = cmd->cmnd[4];
3064 break;
3065 case WRITE_10:
3066 is_write = 1;
3067 case READ_10:
3068 first_block =
3069 (((u64) cmd->cmnd[2]) << 24) |
3070 (((u64) cmd->cmnd[3]) << 16) |
3071 (((u64) cmd->cmnd[4]) << 8) |
3072 cmd->cmnd[5];
3073 block_cnt =
3074 (((u32) cmd->cmnd[7]) << 8) |
3075 cmd->cmnd[8];
3076 break;
3077 case WRITE_12:
3078 is_write = 1;
3079 case READ_12:
3080 first_block =
3081 (((u64) cmd->cmnd[2]) << 24) |
3082 (((u64) cmd->cmnd[3]) << 16) |
3083 (((u64) cmd->cmnd[4]) << 8) |
3084 cmd->cmnd[5];
3085 block_cnt =
3086 (((u32) cmd->cmnd[6]) << 24) |
3087 (((u32) cmd->cmnd[7]) << 16) |
3088 (((u32) cmd->cmnd[8]) << 8) |
3089 cmd->cmnd[9];
3090 break;
3091 case WRITE_16:
3092 is_write = 1;
3093 case READ_16:
3094 first_block =
3095 (((u64) cmd->cmnd[2]) << 56) |
3096 (((u64) cmd->cmnd[3]) << 48) |
3097 (((u64) cmd->cmnd[4]) << 40) |
3098 (((u64) cmd->cmnd[5]) << 32) |
3099 (((u64) cmd->cmnd[6]) << 24) |
3100 (((u64) cmd->cmnd[7]) << 16) |
3101 (((u64) cmd->cmnd[8]) << 8) |
3102 cmd->cmnd[9];
3103 block_cnt =
3104 (((u32) cmd->cmnd[10]) << 24) |
3105 (((u32) cmd->cmnd[11]) << 16) |
3106 (((u32) cmd->cmnd[12]) << 8) |
3107 cmd->cmnd[13];
3108 break;
3109 default:
3110 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3111 }
3112 BUG_ON(block_cnt == 0);
3113 last_block = first_block + block_cnt - 1;
3114
3115 /* check for write to non-RAID-0 */
3116 if (is_write && dev->raid_level != 0)
3117 return IO_ACCEL_INELIGIBLE;
3118
3119 /* check for invalid block or wraparound */
3120 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3121 return IO_ACCEL_INELIGIBLE;
3122
3123 /* calculate stripe information for the request */
3124 blocks_per_row = map->data_disks_per_row * map->strip_size;
3125#if BITS_PER_LONG == 32
3126 tmpdiv = first_block;
3127 (void) do_div(tmpdiv, blocks_per_row);
3128 first_row = tmpdiv;
3129 tmpdiv = last_block;
3130 (void) do_div(tmpdiv, blocks_per_row);
3131 last_row = tmpdiv;
3132 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3133 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3134 tmpdiv = first_row_offset;
3135 (void) do_div(tmpdiv, map->strip_size);
3136 first_column = tmpdiv;
3137 tmpdiv = last_row_offset;
3138 (void) do_div(tmpdiv, map->strip_size);
3139 last_column = tmpdiv;
3140#else
3141 first_row = first_block / blocks_per_row;
3142 last_row = last_block / blocks_per_row;
3143 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3144 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3145 first_column = first_row_offset / map->strip_size;
3146 last_column = last_row_offset / map->strip_size;
3147#endif
3148
3149 /* if this isn't a single row/column then give to the controller */
3150 if ((first_row != last_row) || (first_column != last_column))
3151 return IO_ACCEL_INELIGIBLE;
3152
3153 /* proceeding with driver mapping */
6b80b18f
ST		 3154 total_disks_per_row = map->data_disks_per_row +
3155 map->metadata_disks_per_row;
283b4a9b
SC		 3156 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3157 map->row_cnt;
6b80b18f
ST		 3158 map_index = (map_row * total_disks_per_row) + first_column;
3159
3160 switch (dev->raid_level) {
3161 case HPSA_RAID_0:
3162 break; /* nothing special to do */
3163 case HPSA_RAID_1:
3164 /* Handles load balance across RAID 1 members.
3165 * (2-drive R1 and R10 with even # of drives.)
3166 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3167 */
6b80b18f 3168 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3169 if (dev->offload_to_mirror)
3170 map_index += map->data_disks_per_row;
3171 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3172 break;
3173 case HPSA_RAID_ADM:
3174 /* Handles N-way mirrors (R1-ADM)
3175 * and R10 with # of drives divisible by 3.)
3176 */
3177 BUG_ON(map->layout_map_count != 3);
3178
3179 offload_to_mirror = dev->offload_to_mirror;
3180 raid_map_helper(map, offload_to_mirror,
3181 &map_index, &current_group);
3182 /* set mirror group to use next time */
3183 offload_to_mirror =
3184 (offload_to_mirror >= map->layout_map_count - 1)
3185 ? 0 : offload_to_mirror + 1;
3186 /* FIXME: remove after debug/dev */
3187 BUG_ON(offload_to_mirror >= map->layout_map_count);
3188 dev_warn(&h->pdev->dev,
3189 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3190 map_index, offload_to_mirror);
3191 dev->offload_to_mirror = offload_to_mirror;
3192 /* Avoid direct use of dev->offload_to_mirror within this
3193 * function since multiple threads might simultaneously
3194 * increment it beyond the range of dev->layout_map_count -1.
3195 */
3196 break;
3197 case HPSA_RAID_5:
3198 case HPSA_RAID_6:
3199 if (map->layout_map_count <= 1)
3200 break;
3201
3202 /* Verify first and last block are in same RAID group */
3203 r5or6_blocks_per_row =
3204 map->strip_size * map->data_disks_per_row;
3205 BUG_ON(r5or6_blocks_per_row == 0);
3206 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3207#if BITS_PER_LONG == 32
3208 tmpdiv = first_block;
3209 first_group = do_div(tmpdiv, stripesize);
3210 tmpdiv = first_group;
3211 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3212 first_group = tmpdiv;
3213 tmpdiv = last_block;
3214 last_group = do_div(tmpdiv, stripesize);
3215 tmpdiv = last_group;
3216 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3217 last_group = tmpdiv;
3218#else
3219 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3220 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3221 if (first_group != last_group)
3222#endif
3223 return IO_ACCEL_INELIGIBLE;
3224
3225 /* Verify request is in a single row of RAID 5/6 */
3226#if BITS_PER_LONG == 32
3227 tmpdiv = first_block;
3228 (void) do_div(tmpdiv, stripesize);
3229 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3230 tmpdiv = last_block;
3231 (void) do_div(tmpdiv, stripesize);
3232 r5or6_last_row = r0_last_row = tmpdiv;
3233#else
3234 first_row = r5or6_first_row = r0_first_row =
3235 first_block / stripesize;
3236 r5or6_last_row = r0_last_row = last_block / stripesize;
3237#endif
3238 if (r5or6_first_row != r5or6_last_row)
3239 return IO_ACCEL_INELIGIBLE;
3240
3241
3242 /* Verify request is in a single column */
3243#if BITS_PER_LONG == 32
3244 tmpdiv = first_block;
3245 first_row_offset = do_div(tmpdiv, stripesize);
3246 tmpdiv = first_row_offset;
3247 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3248 r5or6_first_row_offset = first_row_offset;
3249 tmpdiv = last_block;
3250 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3251 tmpdiv = r5or6_last_row_offset;
3252 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3253 tmpdiv = r5or6_first_row_offset;
3254 (void) do_div(tmpdiv, map->strip_size);
3255 first_column = r5or6_first_column = tmpdiv;
3256 tmpdiv = r5or6_last_row_offset;
3257 (void) do_div(tmpdiv, map->strip_size);
3258 r5or6_last_column = tmpdiv;
3259#else
3260 first_row_offset = r5or6_first_row_offset =
3261 (u32)((first_block % stripesize) %
3262 r5or6_blocks_per_row);
3263
3264 r5or6_last_row_offset =
3265 (u32)((last_block % stripesize) %
3266 r5or6_blocks_per_row);
3267
3268 first_column = r5or6_first_column =
3269 r5or6_first_row_offset / map->strip_size;
3270 r5or6_last_column =
3271 r5or6_last_row_offset / map->strip_size;
3272#endif
3273 if (r5or6_first_column != r5or6_last_column)
3274 return IO_ACCEL_INELIGIBLE;
3275
3276 /* Request is eligible */
3277 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3278 map->row_cnt;
3279
3280 map_index = (first_group *
3281 (map->row_cnt * total_disks_per_row)) +
3282 (map_row * total_disks_per_row) + first_column;
3283 break;
3284 default:
3285 return IO_ACCEL_INELIGIBLE;
283b4a9b 3286 }
6b80b18f 3287
283b4a9b
SC		 3288 disk_handle = dd[map_index].ioaccel_handle;
3289 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3290 (first_row_offset - (first_column * map->strip_size));
3291 disk_block_cnt = block_cnt;
3292
3293 /* handle differing logical/physical block sizes */
3294 if (map->phys_blk_shift) {
3295 disk_block <<= map->phys_blk_shift;
3296 disk_block_cnt <<= map->phys_blk_shift;
3297 }
3298 BUG_ON(disk_block_cnt > 0xffff);
3299
3300 /* build the new CDB for the physical disk I/O */
3301 if (disk_block > 0xffffffff) {
3302 cdb[0] = is_write ? WRITE_16 : READ_16;
3303 cdb[1] = 0;
3304 cdb[2] = (u8) (disk_block >> 56);
3305 cdb[3] = (u8) (disk_block >> 48);
3306 cdb[4] = (u8) (disk_block >> 40);
3307 cdb[5] = (u8) (disk_block >> 32);
3308 cdb[6] = (u8) (disk_block >> 24);
3309 cdb[7] = (u8) (disk_block >> 16);
3310 cdb[8] = (u8) (disk_block >> 8);
3311 cdb[9] = (u8) (disk_block);
3312 cdb[10] = (u8) (disk_block_cnt >> 24);
3313 cdb[11] = (u8) (disk_block_cnt >> 16);
3314 cdb[12] = (u8) (disk_block_cnt >> 8);
3315 cdb[13] = (u8) (disk_block_cnt);
3316 cdb[14] = 0;
3317 cdb[15] = 0;
3318 cdb_len = 16;
3319 } else {
3320 cdb[0] = is_write ? WRITE_10 : READ_10;
3321 cdb[1] = 0;
3322 cdb[2] = (u8) (disk_block >> 24);
3323 cdb[3] = (u8) (disk_block >> 16);
3324 cdb[4] = (u8) (disk_block >> 8);
3325 cdb[5] = (u8) (disk_block);
3326 cdb[6] = 0;
3327 cdb[7] = (u8) (disk_block_cnt >> 8);
3328 cdb[8] = (u8) (disk_block_cnt);
3329 cdb[9] = 0;
3330 cdb_len = 10;
3331 }
3332 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3333 dev->scsi3addr);
3334}
3335
f281233d 3336static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3337 void (*done)(struct scsi_cmnd *))
3338{
3339 struct ctlr_info *h;
3340 struct hpsa_scsi_dev_t *dev;
3341 unsigned char scsi3addr[8];
3342 struct CommandList *c;
3343 unsigned long flags;
283b4a9b 3344 int rc = 0;
edd16368
SC		 3345
3346 /* Get the ptr to our adapter structure out of cmd->host. */
3347 h = sdev_to_hba(cmd->device);
3348 dev = cmd->device->hostdata;
3349 if (!dev) {
3350 cmd->result = DID_NO_CONNECT << 16;
3351 done(cmd);
3352 return 0;
3353 }
3354 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3355
edd16368 3356 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3357 if (unlikely(h->lockup_detected)) {
3358 spin_unlock_irqrestore(&h->lock, flags);
3359 cmd->result = DID_ERROR << 16;
3360 done(cmd);
3361 return 0;
3362 }
edd16368 3363 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3364 c = cmd_alloc(h);
edd16368
SC		 3365 if (c == NULL) { /* trouble... */
3366 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3367 return SCSI_MLQUEUE_HOST_BUSY;
3368 }
3369
3370 /* Fill in the command list header */
3371
3372 cmd->scsi_done = done; /* save this for use by completion code */
3373
3374 /* save c in case we have to abort it */
3375 cmd->host_scribble = (unsigned char *) c;
3376
3377 c->cmd_type = CMD_SCSI;
3378 c->scsi_cmd = cmd;
e1f7de0c 3379
283b4a9b
SC		 3380 /* Call alternate submit routine for I/O accelerated commands.
3381 * Retries always go down the normal I/O path.
3382 */
3383 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3384 cmd->request->cmd_type == REQ_TYPE_FS &&
3385 h->acciopath_status)) {
283b4a9b
SC		 3386 if (dev->offload_enabled) {
3387 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3388 if (rc == 0)
3389 return 0; /* Sent on ioaccel path */
3390 if (rc < 0) { /* scsi_dma_map failed. */
3391 cmd_free(h, c);
3392 return SCSI_MLQUEUE_HOST_BUSY;
3393 }
3394 } else if (dev->ioaccel_handle) {
3395 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3396 if (rc == 0)
3397 return 0; /* Sent on direct map path */
3398 if (rc < 0) { /* scsi_dma_map failed. */
3399 cmd_free(h, c);
3400 return SCSI_MLQUEUE_HOST_BUSY;
3401 }
3402 }
3403 }
e1f7de0c 3404
edd16368
SC		 3405 c->Header.ReplyQueue = 0; /* unused in simple mode */
3406 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3407 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3408 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3409
3410 /* Fill in the request block... */
3411
3412 c->Request.Timeout = 0;
3413 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3414 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3415 c->Request.CDBLen = cmd->cmd_len;
3416 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3417 c->Request.Type.Type = TYPE_CMD;
3418 c->Request.Type.Attribute = ATTR_SIMPLE;
3419 switch (cmd->sc_data_direction) {
3420 case DMA_TO_DEVICE:
3421 c->Request.Type.Direction = XFER_WRITE;
3422 break;
3423 case DMA_FROM_DEVICE:
3424 c->Request.Type.Direction = XFER_READ;
3425 break;
3426 case DMA_NONE:
3427 c->Request.Type.Direction = XFER_NONE;
3428 break;
3429 case DMA_BIDIRECTIONAL:
3430 /* This can happen if a buggy application does a scsi passthru
3431 * and sets both inlen and outlen to non-zero. ( see
3432 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3433 */
3434
3435 c->Request.Type.Direction = XFER_RSVD;
3436 /* This is technically wrong, and hpsa controllers should
3437 * reject it with CMD_INVALID, which is the most correct
3438 * response, but non-fibre backends appear to let it
3439 * slide by, and give the same results as if this field
3440 * were set correctly. Either way is acceptable for
3441 * our purposes here.
3442 */
3443
3444 break;
3445
3446 default:
3447 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3448 cmd->sc_data_direction);
3449 BUG();
3450 break;
3451 }
3452
33a2ffce 3453 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3454 cmd_free(h, c);
3455 return SCSI_MLQUEUE_HOST_BUSY;
3456 }
3457 enqueue_cmd_and_start_io(h, c);
3458 /* the cmd'll come back via intr handler in complete_scsi_command() */
3459 return 0;
3460}
3461
f281233d
JG		 3462static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3463
5f389360
SC		 3464static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3465{
3466 unsigned long flags;
3467
3468 /*
3469 * Don't let rescans be initiated on a controller known
3470 * to be locked up. If the controller locks up *during*
3471 * a rescan, that thread is probably hosed, but at least
3472 * we can prevent new rescan threads from piling up on a
3473 * locked up controller.
3474 */
3475 spin_lock_irqsave(&h->lock, flags);
3476 if (unlikely(h->lockup_detected)) {
3477 spin_unlock_irqrestore(&h->lock, flags);
3478 spin_lock_irqsave(&h->scan_lock, flags);
3479 h->scan_finished = 1;
3480 wake_up_all(&h->scan_wait_queue);
3481 spin_unlock_irqrestore(&h->scan_lock, flags);
3482 return 1;
3483 }
3484 spin_unlock_irqrestore(&h->lock, flags);
3485 return 0;
3486}
3487
a08a8471
SC		 3488static void hpsa_scan_start(struct Scsi_Host *sh)
3489{
3490 struct ctlr_info *h = shost_to_hba(sh);
3491 unsigned long flags;
3492
5f389360
SC		 3493 if (do_not_scan_if_controller_locked_up(h))
3494 return;
3495
a08a8471
SC		 3496 /* wait until any scan already in progress is finished. */
3497 while (1) {
3498 spin_lock_irqsave(&h->scan_lock, flags);
3499 if (h->scan_finished)
3500 break;
3501 spin_unlock_irqrestore(&h->scan_lock, flags);
3502 wait_event(h->scan_wait_queue, h->scan_finished);
3503 /* Note: We don't need to worry about a race between this
3504 * thread and driver unload because the midlayer will
3505 * have incremented the reference count, so unload won't
3506 * happen if we're in here.
3507 */
3508 }
3509 h->scan_finished = 0; /* mark scan as in progress */
3510 spin_unlock_irqrestore(&h->scan_lock, flags);
3511
5f389360
SC		 3512 if (do_not_scan_if_controller_locked_up(h))
3513 return;
3514
a08a8471
SC		 3515 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3516
3517 spin_lock_irqsave(&h->scan_lock, flags);
3518 h->scan_finished = 1; /* mark scan as finished. */
3519 wake_up_all(&h->scan_wait_queue);
3520 spin_unlock_irqrestore(&h->scan_lock, flags);
3521}
3522
3523static int hpsa_scan_finished(struct Scsi_Host *sh,
3524 unsigned long elapsed_time)
3525{
3526 struct ctlr_info *h = shost_to_hba(sh);
3527 unsigned long flags;
3528 int finished;
3529
3530 spin_lock_irqsave(&h->scan_lock, flags);
3531 finished = h->scan_finished;
3532 spin_unlock_irqrestore(&h->scan_lock, flags);
3533 return finished;
3534}
3535
667e23d4
SC		 3536static int hpsa_change_queue_depth(struct scsi_device *sdev,
3537 int qdepth, int reason)
3538{
3539 struct ctlr_info *h = sdev_to_hba(sdev);
3540
3541 if (reason != SCSI_QDEPTH_DEFAULT)
3542 return -ENOTSUPP;
3543
3544 if (qdepth < 1)
3545 qdepth = 1;
3546 else
3547 if (qdepth > h->nr_cmds)
3548 qdepth = h->nr_cmds;
3549 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3550 return sdev->queue_depth;
3551}
3552
edd16368
SC		 3553static void hpsa_unregister_scsi(struct ctlr_info *h)
3554{
3555 /* we are being forcibly unloaded, and may not refuse. */
3556 scsi_remove_host(h->scsi_host);
3557 scsi_host_put(h->scsi_host);
3558 h->scsi_host = NULL;
3559}
3560
3561static int hpsa_register_scsi(struct ctlr_info *h)
3562{
b705690d
SC		 3563 struct Scsi_Host *sh;
3564 int error;
edd16368 3565
b705690d
SC		 3566 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3567 if (sh == NULL)
3568 goto fail;
3569
3570 sh->io_port = 0;
3571 sh->n_io_port = 0;
3572 sh->this_id = -1;
3573 sh->max_channel = 3;
3574 sh->max_cmd_len = MAX_COMMAND_SIZE;
3575 sh->max_lun = HPSA_MAX_LUN;
3576 sh->max_id = HPSA_MAX_LUN;
3577 sh->can_queue = h->nr_cmds;
3578 sh->cmd_per_lun = h->nr_cmds;
3579 sh->sg_tablesize = h->maxsgentries;
3580 h->scsi_host = sh;
3581 sh->hostdata[0] = (unsigned long) h;
3582 sh->irq = h->intr[h->intr_mode];
3583 sh->unique_id = sh->irq;
3584 error = scsi_add_host(sh, &h->pdev->dev);
3585 if (error)
3586 goto fail_host_put;
3587 scsi_scan_host(sh);
3588 return 0;
3589
3590 fail_host_put:
3591 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3592 " failed for controller %d\n", __func__, h->ctlr);
3593 scsi_host_put(sh);
3594 return error;
3595 fail:
3596 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3597 " failed for controller %d\n", __func__, h->ctlr);
3598 return -ENOMEM;
edd16368
SC		 3599}
3600
3601static int wait_for_device_to_become_ready(struct ctlr_info *h,
3602 unsigned char lunaddr[])
3603{
3604 int rc = 0;
3605 int count = 0;
3606 int waittime = 1; /* seconds */
3607 struct CommandList *c;
3608
3609 c = cmd_special_alloc(h);
3610 if (!c) {
3611 dev_warn(&h->pdev->dev, "out of memory in "
3612 "wait_for_device_to_become_ready.\n");
3613 return IO_ERROR;
3614 }
3615
3616 /* Send test unit ready until device ready, or give up. */
3617 while (count < HPSA_TUR_RETRY_LIMIT) {
3618
3619 /* Wait for a bit. do this first, because if we send
3620 * the TUR right away, the reset will just abort it.
3621 */
3622 msleep(1000 * waittime);
3623 count++;
3624
3625 /* Increase wait time with each try, up to a point. */
3626 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3627 waittime = waittime * 2;
3628
a2dac136
SC		 3629 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3630 (void) fill_cmd(c, TEST_UNIT_READY, h,
3631 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3632 hpsa_scsi_do_simple_cmd_core(h, c);
3633 /* no unmap needed here because no data xfer. */
3634
3635 if (c->err_info->CommandStatus == CMD_SUCCESS)
3636 break;
3637
3638 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3639 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3640 (c->err_info->SenseInfo[2] == NO_SENSE ||
3641 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3642 break;
3643
3644 dev_warn(&h->pdev->dev, "waiting %d secs "
3645 "for device to become ready.\n", waittime);
3646 rc = 1; /* device not ready. */
3647 }
3648
3649 if (rc)
3650 dev_warn(&h->pdev->dev, "giving up on device.\n");
3651 else
3652 dev_warn(&h->pdev->dev, "device is ready.\n");
3653
3654 cmd_special_free(h, c);
3655 return rc;
3656}
3657
3658/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3659 * complaining. Doing a host- or bus-reset can't do anything good here.
3660 */
3661static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3662{
3663 int rc;
3664 struct ctlr_info *h;
3665 struct hpsa_scsi_dev_t *dev;
3666
3667 /* find the controller to which the command to be aborted was sent */
3668 h = sdev_to_hba(scsicmd->device);
3669 if (h == NULL) /* paranoia */
3670 return FAILED;
edd16368
SC		 3671 dev = scsicmd->device->hostdata;
3672 if (!dev) {
3673 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3674 "device lookup failed.\n");
3675 return FAILED;
3676 }
d416b0c7
SC		 3677 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3678 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3679 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3680 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3681 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3682 return SUCCESS;
3683
3684 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3685 return FAILED;
3686}
3687
6cba3f19
SC		 3688static void swizzle_abort_tag(u8 *tag)
3689{
3690 u8 original_tag[8];
3691
3692 memcpy(original_tag, tag, 8);
3693 tag[0] = original_tag[3];
3694 tag[1] = original_tag[2];
3695 tag[2] = original_tag[1];
3696 tag[3] = original_tag[0];
3697 tag[4] = original_tag[7];
3698 tag[5] = original_tag[6];
3699 tag[6] = original_tag[5];
3700 tag[7] = original_tag[4];
3701}
3702
17eb87d2
ST		 3703static void hpsa_get_tag(struct ctlr_info *h,
3704 struct CommandList *c, u32 *taglower, u32 *tagupper)
3705{
3706 if (c->cmd_type == CMD_IOACCEL1) {
3707 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3708 &h->ioaccel_cmd_pool[c->cmdindex];
3709 *tagupper = cm1->Tag.upper;
3710 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 3711 return;
3712 }
3713 if (c->cmd_type == CMD_IOACCEL2) {
3714 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
3715 &h->ioaccel2_cmd_pool[c->cmdindex];
3716 *tagupper = cm2->Tag.upper;
3717 *taglower = cm2->Tag.lower;
3718 return;
17eb87d2 3719 }
54b6e9e9
ST		 3720 *tagupper = c->Header.Tag.upper;
3721 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 3722}
3723
54b6e9e9 3724
75167d2c 3725static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3726 struct CommandList *abort, int swizzle)
75167d2c
SC		 3727{
3728 int rc = IO_OK;
3729 struct CommandList *c;
3730 struct ErrorInfo *ei;
17eb87d2 3731 u32 tagupper, taglower;
75167d2c
SC		 3732
3733 c = cmd_special_alloc(h);
3734 if (c == NULL) { /* trouble... */
3735 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3736 return -ENOMEM;
3737 }
3738
a2dac136
SC		 3739 /* fill_cmd can't fail here, no buffer to map */
3740 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3741 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3742 if (swizzle)
3743 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3744 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3745 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3746 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3747 __func__, tagupper, taglower);
75167d2c
SC		 3748 /* no unmap needed here because no data xfer. */
3749
3750 ei = c->err_info;
3751 switch (ei->CommandStatus) {
3752 case CMD_SUCCESS:
3753 break;
3754 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3755 rc = -1;
3756 break;
3757 default:
3758 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3759 __func__, tagupper, taglower);
75167d2c
SC		 3760 hpsa_scsi_interpret_error(c);
3761 rc = -1;
3762 break;
3763 }
3764 cmd_special_free(h, c);
3765 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3766 abort->Header.Tag.upper, abort->Header.Tag.lower);
3767 return rc;
3768}
3769
3770/*
3771 * hpsa_find_cmd_in_queue
3772 *
3773 * Used to determine whether a command (find) is still present
3774 * in queue_head. Optionally excludes the last element of queue_head.
3775 *
3776 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3777 * not yet been submitted, and so can be aborted by the driver without
3778 * sending an abort to the hardware.
3779 *
3780 * Returns pointer to command if found in queue, NULL otherwise.
3781 */
3782static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3783 struct scsi_cmnd *find, struct list_head *queue_head)
3784{
3785 unsigned long flags;
3786 struct CommandList *c = NULL; /* ptr into cmpQ */
3787
3788 if (!find)
3789 return 0;
3790 spin_lock_irqsave(&h->lock, flags);
3791 list_for_each_entry(c, queue_head, list) {
3792 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3793 continue;
3794 if (c->scsi_cmd == find) {
3795 spin_unlock_irqrestore(&h->lock, flags);
3796 return c;
3797 }
3798 }
3799 spin_unlock_irqrestore(&h->lock, flags);
3800 return NULL;
3801}
3802
6cba3f19
SC		 3803static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3804 u8 *tag, struct list_head *queue_head)
3805{
3806 unsigned long flags;
3807 struct CommandList *c;
3808
3809 spin_lock_irqsave(&h->lock, flags);
3810 list_for_each_entry(c, queue_head, list) {
3811 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3812 continue;
3813 spin_unlock_irqrestore(&h->lock, flags);
3814 return c;
3815 }
3816 spin_unlock_irqrestore(&h->lock, flags);
3817 return NULL;
3818}
3819
54b6e9e9
ST		 3820/* ioaccel2 path firmware cannot handle abort task requests.
3821 * Change abort requests to physical target reset, and send to the
3822 * address of the physical disk used for the ioaccel 2 command.
3823 * Return 0 on success (IO_OK)
3824 * -1 on failure
3825 */
3826
3827static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
3828 unsigned char *scsi3addr, struct CommandList *abort)
3829{
3830 int rc = IO_OK;
3831 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
3832 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
3833 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
3834 unsigned char *psa = &phys_scsi3addr[0];
3835
3836 /* Get a pointer to the hpsa logical device. */
3837 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
3838 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
3839 if (dev == NULL) {
3840 dev_warn(&h->pdev->dev,
3841 "Cannot abort: no device pointer for command.\n");
3842 return -1; /* not abortable */
3843 }
3844
3845 if (!dev->offload_enabled) {
3846 dev_warn(&h->pdev->dev,
3847 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
3848 return -1; /* not abortable */
3849 }
3850
3851 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
3852 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
3853 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
3854 return -1; /* not abortable */
3855 }
3856
3857 /* send the reset */
3858 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
3859 if (rc != 0) {
3860 dev_warn(&h->pdev->dev,
3861 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3862 psa[0], psa[1], psa[2], psa[3],
3863 psa[4], psa[5], psa[6], psa[7]);
3864 return rc; /* failed to reset */
3865 }
3866
3867 /* wait for device to recover */
3868 if (wait_for_device_to_become_ready(h, psa) != 0) {
3869 dev_warn(&h->pdev->dev,
3870 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3871 psa[0], psa[1], psa[2], psa[3],
3872 psa[4], psa[5], psa[6], psa[7]);
3873 return -1; /* failed to recover */
3874 }
3875
3876 /* device recovered */
3877 dev_info(&h->pdev->dev,
3878 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3879 psa[0], psa[1], psa[2], psa[3],
3880 psa[4], psa[5], psa[6], psa[7]);
3881
3882 return rc; /* success */
3883}
3884
6cba3f19
SC		 3885/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3886 * tell which kind we're dealing with, so we send the abort both ways. There
3887 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3888 * way we construct our tags but we check anyway in case the assumptions which
3889 * make this true someday become false.
3890 */
3891static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3892 unsigned char *scsi3addr, struct CommandList *abort)
3893{
3894 u8 swizzled_tag[8];
3895 struct CommandList *c;
3896 int rc = 0, rc2 = 0;
3897
54b6e9e9
ST		 3898 /* ioccelerator mode 2 commands should be aborted via the
3899 * accelerated path, since RAID path is unaware of these commands,
3900 * but underlying firmware can't handle abort TMF.
3901 * Change abort to physical device reset.
3902 */
3903 if (abort->cmd_type == CMD_IOACCEL2)
3904 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
3905
6cba3f19
SC		 3906 /* we do not expect to find the swizzled tag in our queue, but
3907 * check anyway just to be sure the assumptions which make this
3908 * the case haven't become wrong.
3909 */
3910 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3911 swizzle_abort_tag(swizzled_tag);
3912 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3913 if (c != NULL) {
3914 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3915 return hpsa_send_abort(h, scsi3addr, abort, 0);
3916 }
3917 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3918
3919 /* if the command is still in our queue, we can't conclude that it was
3920 * aborted (it might have just completed normally) but in any case
3921 * we don't need to try to abort it another way.
3922 */
3923 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3924 if (c)
3925 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3926 return rc && rc2;
3927}
3928
75167d2c
SC		 3929/* Send an abort for the specified command.
3930 * If the device and controller support it,
3931 * send a task abort request.
3932 */
3933static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3934{
3935
3936 int i, rc;
3937 struct ctlr_info *h;
3938 struct hpsa_scsi_dev_t *dev;
3939 struct CommandList *abort; /* pointer to command to be aborted */
3940 struct CommandList *found;
3941 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3942 char msg[256]; /* For debug messaging. */
3943 int ml = 0;
17eb87d2 3944 u32 tagupper, taglower;
75167d2c
SC		 3945
3946 /* Find the controller of the command to be aborted */
3947 h = sdev_to_hba(sc->device);
3948 if (WARN(h == NULL,
3949 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3950 return FAILED;
3951
3952 /* Check that controller supports some kind of task abort */
3953 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3954 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3955 return FAILED;
3956
3957 memset(msg, 0, sizeof(msg));
3958 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3959 h->scsi_host->host_no, sc->device->channel,
3960 sc->device->id, sc->device->lun);
3961
3962 /* Find the device of the command to be aborted */
3963 dev = sc->device->hostdata;
3964 if (!dev) {
3965 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3966 msg);
3967 return FAILED;
3968 }
3969
3970 /* Get SCSI command to be aborted */
3971 abort = (struct CommandList *) sc->host_scribble;
3972 if (abort == NULL) {
3973 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3974 msg);
3975 return FAILED;
3976 }
17eb87d2
ST		 3977 hpsa_get_tag(h, abort, &taglower, &tagupper);
3978 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3979 as = (struct scsi_cmnd *) abort->scsi_cmd;
3980 if (as != NULL)
3981 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3982 as->cmnd[0], as->serial_number);
3983 dev_dbg(&h->pdev->dev, "%s\n", msg);
3984 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3985 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3986
3987 /* Search reqQ to See if command is queued but not submitted,
3988 * if so, complete the command with aborted status and remove
3989 * it from the reqQ.
3990 */
3991 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3992 if (found) {
3993 found->err_info->CommandStatus = CMD_ABORTED;
3994 finish_cmd(found);
3995 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3996 msg);
3997 return SUCCESS;
3998 }
3999
4000 /* not in reqQ, if also not in cmpQ, must have already completed */
4001 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4002 if (!found) {
d6ebd0f7 4003 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4004 msg);
4005 return SUCCESS;
4006 }
4007
4008 /*
4009 * Command is in flight, or possibly already completed
4010 * by the firmware (but not to the scsi mid layer) but we can't
4011 * distinguish which. Send the abort down.
4012 */
6cba3f19 4013 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4014 if (rc != 0) {
4015 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4016 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4017 h->scsi_host->host_no,
4018 dev->bus, dev->target, dev->lun);
4019 return FAILED;
4020 }
4021 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4022
4023 /* If the abort(s) above completed and actually aborted the
4024 * command, then the command to be aborted should already be
4025 * completed. If not, wait around a bit more to see if they
4026 * manage to complete normally.
4027 */
4028#define ABORT_COMPLETE_WAIT_SECS 30
4029 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4030 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4031 if (!found)
4032 return SUCCESS;
4033 msleep(100);
4034 }
4035 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4036 msg, ABORT_COMPLETE_WAIT_SECS);
4037 return FAILED;
4038}
4039
4040
edd16368
SC		 4041/*
4042 * For operations that cannot sleep, a command block is allocated at init,
4043 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4044 * which ones are free or in use. Lock must be held when calling this.
4045 * cmd_free() is the complement.
4046 */
4047static struct CommandList *cmd_alloc(struct ctlr_info *h)
4048{
4049 struct CommandList *c;
4050 int i;
4051 union u64bit temp64;
4052 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4053 unsigned long flags;
edd16368 4054
e16a33ad 4055 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4056 do {
4057 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4058 if (i == h->nr_cmds) {
4059 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4060 return NULL;
e16a33ad 4061 }
edd16368
SC		 4062 } while (test_and_set_bit
4063 (i & (BITS_PER_LONG - 1),
4064 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4065 spin_unlock_irqrestore(&h->lock, flags);
4066
edd16368
SC		 4067 c = h->cmd_pool + i;
4068 memset(c, 0, sizeof(*c));
4069 cmd_dma_handle = h->cmd_pool_dhandle
4070 + i * sizeof(*c);
4071 c->err_info = h->errinfo_pool + i;
4072 memset(c->err_info, 0, sizeof(*c->err_info));
4073 err_dma_handle = h->errinfo_pool_dhandle
4074 + i * sizeof(*c->err_info);
edd16368
SC		 4075
4076 c->cmdindex = i;
4077
9e0fc764 4078 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4079 c->busaddr = (u32) cmd_dma_handle;
4080 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4081 c->ErrDesc.Addr.lower = temp64.val32.lower;
4082 c->ErrDesc.Addr.upper = temp64.val32.upper;
4083 c->ErrDesc.Len = sizeof(*c->err_info);
4084
4085 c->h = h;
4086 return c;
4087}
4088
4089/* For operations that can wait for kmalloc to possibly sleep,
4090 * this routine can be called. Lock need not be held to call
4091 * cmd_special_alloc. cmd_special_free() is the complement.
4092 */
4093static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4094{
4095 struct CommandList *c;
4096 union u64bit temp64;
4097 dma_addr_t cmd_dma_handle, err_dma_handle;
4098
4099 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4100 if (c == NULL)
4101 return NULL;
4102 memset(c, 0, sizeof(*c));
4103
e1f7de0c 4104 c->cmd_type = CMD_SCSI;
edd16368
SC		 4105 c->cmdindex = -1;
4106
4107 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4108 &err_dma_handle);
4109
4110 if (c->err_info == NULL) {
4111 pci_free_consistent(h->pdev,
4112 sizeof(*c), c, cmd_dma_handle);
4113 return NULL;
4114 }
4115 memset(c->err_info, 0, sizeof(*c->err_info));
4116
9e0fc764 4117 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4118 c->busaddr = (u32) cmd_dma_handle;
4119 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4120 c->ErrDesc.Addr.lower = temp64.val32.lower;
4121 c->ErrDesc.Addr.upper = temp64.val32.upper;
4122 c->ErrDesc.Len = sizeof(*c->err_info);
4123
4124 c->h = h;
4125 return c;
4126}
4127
4128static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4129{
4130 int i;
e16a33ad 4131 unsigned long flags;
edd16368
SC		 4132
4133 i = c - h->cmd_pool;
e16a33ad 4134 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4135 clear_bit(i & (BITS_PER_LONG - 1),
4136 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4137 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4138}
4139
4140static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4141{
4142 union u64bit temp64;
4143
4144 temp64.val32.lower = c->ErrDesc.Addr.lower;
4145 temp64.val32.upper = c->ErrDesc.Addr.upper;
4146 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4147 c->err_info, (dma_addr_t) temp64.val);
4148 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4149 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4150}
4151
4152#ifdef CONFIG_COMPAT
4153
edd16368
SC		 4154static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4155{
4156 IOCTL32_Command_struct __user *arg32 =
4157 (IOCTL32_Command_struct __user *) arg;
4158 IOCTL_Command_struct arg64;
4159 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4160 int err;
4161 u32 cp;
4162
938abd84 4163 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4164 err = 0;
4165 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4166 sizeof(arg64.LUN_info));
4167 err |= copy_from_user(&arg64.Request, &arg32->Request,
4168 sizeof(arg64.Request));
4169 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4170 sizeof(arg64.error_info));
4171 err |= get_user(arg64.buf_size, &arg32->buf_size);
4172 err |= get_user(cp, &arg32->buf);
4173 arg64.buf = compat_ptr(cp);
4174 err |= copy_to_user(p, &arg64, sizeof(arg64));
4175
4176 if (err)
4177 return -EFAULT;
4178
e39eeaed 4179 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4180 if (err)
4181 return err;
4182 err |= copy_in_user(&arg32->error_info, &p->error_info,
4183 sizeof(arg32->error_info));
4184 if (err)
4185 return -EFAULT;
4186 return err;
4187}
4188
4189static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4190 int cmd, void *arg)
4191{
4192 BIG_IOCTL32_Command_struct __user *arg32 =
4193 (BIG_IOCTL32_Command_struct __user *) arg;
4194 BIG_IOCTL_Command_struct arg64;
4195 BIG_IOCTL_Command_struct __user *p =
4196 compat_alloc_user_space(sizeof(arg64));
4197 int err;
4198 u32 cp;
4199
938abd84 4200 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4201 err = 0;
4202 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4203 sizeof(arg64.LUN_info));
4204 err |= copy_from_user(&arg64.Request, &arg32->Request,
4205 sizeof(arg64.Request));
4206 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4207 sizeof(arg64.error_info));
4208 err |= get_user(arg64.buf_size, &arg32->buf_size);
4209 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4210 err |= get_user(cp, &arg32->buf);
4211 arg64.buf = compat_ptr(cp);
4212 err |= copy_to_user(p, &arg64, sizeof(arg64));
4213
4214 if (err)
4215 return -EFAULT;
4216
e39eeaed 4217 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4218 if (err)
4219 return err;
4220 err |= copy_in_user(&arg32->error_info, &p->error_info,
4221 sizeof(arg32->error_info));
4222 if (err)
4223 return -EFAULT;
4224 return err;
4225}
71fe75a7
SC		 4226
4227static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4228{
4229 switch (cmd) {
4230 case CCISS_GETPCIINFO:
4231 case CCISS_GETINTINFO:
4232 case CCISS_SETINTINFO:
4233 case CCISS_GETNODENAME:
4234 case CCISS_SETNODENAME:
4235 case CCISS_GETHEARTBEAT:
4236 case CCISS_GETBUSTYPES:
4237 case CCISS_GETFIRMVER:
4238 case CCISS_GETDRIVVER:
4239 case CCISS_REVALIDVOLS:
4240 case CCISS_DEREGDISK:
4241 case CCISS_REGNEWDISK:
4242 case CCISS_REGNEWD:
4243 case CCISS_RESCANDISK:
4244 case CCISS_GETLUNINFO:
4245 return hpsa_ioctl(dev, cmd, arg);
4246
4247 case CCISS_PASSTHRU32:
4248 return hpsa_ioctl32_passthru(dev, cmd, arg);
4249 case CCISS_BIG_PASSTHRU32:
4250 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4251
4252 default:
4253 return -ENOIOCTLCMD;
4254 }
4255}
edd16368
SC		 4256#endif
4257
4258static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4259{
4260 struct hpsa_pci_info pciinfo;
4261
4262 if (!argp)
4263 return -EINVAL;
4264 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4265 pciinfo.bus = h->pdev->bus->number;
4266 pciinfo.dev_fn = h->pdev->devfn;
4267 pciinfo.board_id = h->board_id;
4268 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4269 return -EFAULT;
4270 return 0;
4271}
4272
4273static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4274{
4275 DriverVer_type DriverVer;
4276 unsigned char vmaj, vmin, vsubmin;
4277 int rc;
4278
4279 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4280 &vmaj, &vmin, &vsubmin);
4281 if (rc != 3) {
4282 dev_info(&h->pdev->dev, "driver version string '%s' "
4283 "unrecognized.", HPSA_DRIVER_VERSION);
4284 vmaj = 0;
4285 vmin = 0;
4286 vsubmin = 0;
4287 }
4288 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4289 if (!argp)
4290 return -EINVAL;
4291 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4292 return -EFAULT;
4293 return 0;
4294}
4295
4296static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4297{
4298 IOCTL_Command_struct iocommand;
4299 struct CommandList *c;
4300 char *buff = NULL;
4301 union u64bit temp64;
c1f63c8f 4302 int rc = 0;
edd16368
SC		 4303
4304 if (!argp)
4305 return -EINVAL;
4306 if (!capable(CAP_SYS_RAWIO))
4307 return -EPERM;
4308 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4309 return -EFAULT;
4310 if ((iocommand.buf_size < 1) &&
4311 (iocommand.Request.Type.Direction != XFER_NONE)) {
4312 return -EINVAL;
4313 }
4314 if (iocommand.buf_size > 0) {
4315 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4316 if (buff == NULL)
4317 return -EFAULT;
b03a7771
SC		 4318 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4319 /* Copy the data into the buffer we created */
4320 if (copy_from_user(buff, iocommand.buf,
4321 iocommand.buf_size)) {
c1f63c8f
SC		 4322 rc = -EFAULT;
4323 goto out_kfree;
b03a7771
SC		 4324 }
4325 } else {
4326 memset(buff, 0, iocommand.buf_size);
edd16368 4327 }
b03a7771 4328 }
edd16368
SC		 4329 c = cmd_special_alloc(h);
4330 if (c == NULL) {
c1f63c8f
SC		 4331 rc = -ENOMEM;
4332 goto out_kfree;
edd16368
SC		 4333 }
4334 /* Fill in the command type */
4335 c->cmd_type = CMD_IOCTL_PEND;
4336 /* Fill in Command Header */
4337 c->Header.ReplyQueue = 0; /* unused in simple mode */
4338 if (iocommand.buf_size > 0) { /* buffer to fill */
4339 c->Header.SGList = 1;
4340 c->Header.SGTotal = 1;
4341 } else { /* no buffers to fill */
4342 c->Header.SGList = 0;
4343 c->Header.SGTotal = 0;
4344 }
4345 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4346 /* use the kernel address the cmd block for tag */
4347 c->Header.Tag.lower = c->busaddr;
4348
4349 /* Fill in Request block */
4350 memcpy(&c->Request, &iocommand.Request,
4351 sizeof(c->Request));
4352
4353 /* Fill in the scatter gather information */
4354 if (iocommand.buf_size > 0) {
4355 temp64.val = pci_map_single(h->pdev, buff,
4356 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4357 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4358 c->SG[0].Addr.lower = 0;
4359 c->SG[0].Addr.upper = 0;
4360 c->SG[0].Len = 0;
4361 rc = -ENOMEM;
4362 goto out;
4363 }
edd16368
SC		 4364 c->SG[0].Addr.lower = temp64.val32.lower;
4365 c->SG[0].Addr.upper = temp64.val32.upper;
4366 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4367 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4368 }
a0c12413 4369 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4370 if (iocommand.buf_size > 0)
4371 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4372 check_ioctl_unit_attention(h, c);
4373
4374 /* Copy the error information out */
4375 memcpy(&iocommand.error_info, c->err_info,
4376 sizeof(iocommand.error_info));
4377 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4378 rc = -EFAULT;
4379 goto out;
edd16368 4380 }
b03a7771
SC		 4381 if (iocommand.Request.Type.Direction == XFER_READ &&
4382 iocommand.buf_size > 0) {
edd16368
SC		 4383 /* Copy the data out of the buffer we created */
4384 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4385 rc = -EFAULT;
4386 goto out;
edd16368
SC		 4387 }
4388 }
c1f63c8f 4389out:
edd16368 4390 cmd_special_free(h, c);
c1f63c8f
SC		 4391out_kfree:
4392 kfree(buff);
4393 return rc;
edd16368
SC		 4394}
4395
4396static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4397{
4398 BIG_IOCTL_Command_struct *ioc;
4399 struct CommandList *c;
4400 unsigned char **buff = NULL;
4401 int *buff_size = NULL;
4402 union u64bit temp64;
4403 BYTE sg_used = 0;
4404 int status = 0;
4405 int i;
01a02ffc
SC		 4406 u32 left;
4407 u32 sz;
edd16368
SC		 4408 BYTE __user *data_ptr;
4409
4410 if (!argp)
4411 return -EINVAL;
4412 if (!capable(CAP_SYS_RAWIO))
4413 return -EPERM;
4414 ioc = (BIG_IOCTL_Command_struct *)
4415 kmalloc(sizeof(*ioc), GFP_KERNEL);
4416 if (!ioc) {
4417 status = -ENOMEM;
4418 goto cleanup1;
4419 }
4420 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4421 status = -EFAULT;
4422 goto cleanup1;
4423 }
4424 if ((ioc->buf_size < 1) &&
4425 (ioc->Request.Type.Direction != XFER_NONE)) {
4426 status = -EINVAL;
4427 goto cleanup1;
4428 }
4429 /* Check kmalloc limits using all SGs */
4430 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4431 status = -EINVAL;
4432 goto cleanup1;
4433 }
d66ae08b 4434 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4435 status = -EINVAL;
4436 goto cleanup1;
4437 }
d66ae08b 4438 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4439 if (!buff) {
4440 status = -ENOMEM;
4441 goto cleanup1;
4442 }
d66ae08b 4443 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4444 if (!buff_size) {
4445 status = -ENOMEM;
4446 goto cleanup1;
4447 }
4448 left = ioc->buf_size;
4449 data_ptr = ioc->buf;
4450 while (left) {
4451 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4452 buff_size[sg_used] = sz;
4453 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4454 if (buff[sg_used] == NULL) {
4455 status = -ENOMEM;
4456 goto cleanup1;
4457 }
4458 if (ioc->Request.Type.Direction == XFER_WRITE) {
4459 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4460 status = -ENOMEM;
4461 goto cleanup1;
4462 }
4463 } else
4464 memset(buff[sg_used], 0, sz);
4465 left -= sz;
4466 data_ptr += sz;
4467 sg_used++;
4468 }
4469 c = cmd_special_alloc(h);
4470 if (c == NULL) {
4471 status = -ENOMEM;
4472 goto cleanup1;
4473 }
4474 c->cmd_type = CMD_IOCTL_PEND;
4475 c->Header.ReplyQueue = 0;
b03a7771 4476 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4477 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4478 c->Header.Tag.lower = c->busaddr;
4479 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4480 if (ioc->buf_size > 0) {
4481 int i;
4482 for (i = 0; i < sg_used; i++) {
4483 temp64.val = pci_map_single(h->pdev, buff[i],
4484 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4485 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4486 c->SG[i].Addr.lower = 0;
4487 c->SG[i].Addr.upper = 0;
4488 c->SG[i].Len = 0;
4489 hpsa_pci_unmap(h->pdev, c, i,
4490 PCI_DMA_BIDIRECTIONAL);
4491 status = -ENOMEM;
e2d4a1f6 4492 goto cleanup0;
bcc48ffa 4493 }
edd16368
SC		 4494 c->SG[i].Addr.lower = temp64.val32.lower;
4495 c->SG[i].Addr.upper = temp64.val32.upper;
4496 c->SG[i].Len = buff_size[i];
e1d9cbfa 4497 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4498 }
4499 }
a0c12413 4500 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4501 if (sg_used)
4502 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4503 check_ioctl_unit_attention(h, c);
4504 /* Copy the error information out */
4505 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4506 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4507 status = -EFAULT;
e2d4a1f6 4508 goto cleanup0;
edd16368 4509 }
b03a7771 4510 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4511 /* Copy the data out of the buffer we created */
4512 BYTE __user *ptr = ioc->buf;
4513 for (i = 0; i < sg_used; i++) {
4514 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4515 status = -EFAULT;
e2d4a1f6 4516 goto cleanup0;
edd16368
SC		 4517 }
4518 ptr += buff_size[i];
4519 }
4520 }
edd16368 4521 status = 0;
e2d4a1f6
SC		 4522cleanup0:
4523 cmd_special_free(h, c);
edd16368
SC		 4524cleanup1:
4525 if (buff) {
4526 for (i = 0; i < sg_used; i++)
4527 kfree(buff[i]);
4528 kfree(buff);
4529 }
4530 kfree(buff_size);
4531 kfree(ioc);
4532 return status;
4533}
4534
4535static void check_ioctl_unit_attention(struct ctlr_info *h,
4536 struct CommandList *c)
4537{
4538 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4539 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4540 (void) check_for_unit_attention(h, c);
4541}
0390f0c0
SC		 4542
4543static int increment_passthru_count(struct ctlr_info *h)
4544{
4545 unsigned long flags;
4546
4547 spin_lock_irqsave(&h->passthru_count_lock, flags);
4548 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4549 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4550 return -1;
4551 }
4552 h->passthru_count++;
4553 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4554 return 0;
4555}
4556
4557static void decrement_passthru_count(struct ctlr_info *h)
4558{
4559 unsigned long flags;
4560
4561 spin_lock_irqsave(&h->passthru_count_lock, flags);
4562 if (h->passthru_count <= 0) {
4563 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4564 /* not expecting to get here. */
4565 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4566 return;
4567 }
4568 h->passthru_count--;
4569 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4570}
4571
edd16368
SC		 4572/*
4573 * ioctl
4574 */
4575static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4576{
4577 struct ctlr_info *h;
4578 void __user *argp = (void __user *)arg;
0390f0c0 4579 int rc;
edd16368
SC		 4580
4581 h = sdev_to_hba(dev);
4582
4583 switch (cmd) {
4584 case CCISS_DEREGDISK:
4585 case CCISS_REGNEWDISK:
4586 case CCISS_REGNEWD:
a08a8471 4587 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4588 return 0;
4589 case CCISS_GETPCIINFO:
4590 return hpsa_getpciinfo_ioctl(h, argp);
4591 case CCISS_GETDRIVVER:
4592 return hpsa_getdrivver_ioctl(h, argp);
4593 case CCISS_PASSTHRU:
0390f0c0
SC		 4594 if (increment_passthru_count(h))
4595 return -EAGAIN;
4596 rc = hpsa_passthru_ioctl(h, argp);
4597 decrement_passthru_count(h);
4598 return rc;
edd16368 4599 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4600 if (increment_passthru_count(h))
4601 return -EAGAIN;
4602 rc = hpsa_big_passthru_ioctl(h, argp);
4603 decrement_passthru_count(h);
4604 return rc;
edd16368
SC		 4605 default:
4606 return -ENOTTY;
4607 }
4608}
4609
6f039790
GKH		 4610static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4611 u8 reset_type)
64670ac8
SC		 4612{
4613 struct CommandList *c;
4614
4615 c = cmd_alloc(h);
4616 if (!c)
4617 return -ENOMEM;
a2dac136
SC		 4618 /* fill_cmd can't fail here, no data buffer to map */
4619 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4620 RAID_CTLR_LUNID, TYPE_MSG);
4621 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4622 c->waiting = NULL;
4623 enqueue_cmd_and_start_io(h, c);
4624 /* Don't wait for completion, the reset won't complete. Don't free
4625 * the command either. This is the last command we will send before
4626 * re-initializing everything, so it doesn't matter and won't leak.
4627 */
4628 return 0;
4629}
4630
a2dac136 4631static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 4632 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 4633 int cmd_type)
4634{
4635 int pci_dir = XFER_NONE;
75167d2c 4636 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4637
4638 c->cmd_type = CMD_IOCTL_PEND;
4639 c->Header.ReplyQueue = 0;
4640 if (buff != NULL && size > 0) {
4641 c->Header.SGList = 1;
4642 c->Header.SGTotal = 1;
4643 } else {
4644 c->Header.SGList = 0;
4645 c->Header.SGTotal = 0;
4646 }
4647 c->Header.Tag.lower = c->busaddr;
4648 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4649
4650 c->Request.Type.Type = cmd_type;
4651 if (cmd_type == TYPE_CMD) {
4652 switch (cmd) {
4653 case HPSA_INQUIRY:
4654 /* are we trying to read a vital product page */
4655 if (page_code != 0) {
4656 c->Request.CDB[1] = 0x01;
4657 c->Request.CDB[2] = page_code;
4658 }
4659 c->Request.CDBLen = 6;
4660 c->Request.Type.Attribute = ATTR_SIMPLE;
4661 c->Request.Type.Direction = XFER_READ;
4662 c->Request.Timeout = 0;
4663 c->Request.CDB[0] = HPSA_INQUIRY;
4664 c->Request.CDB[4] = size & 0xFF;
4665 break;
4666 case HPSA_REPORT_LOG:
4667 case HPSA_REPORT_PHYS:
4668 /* Talking to controller so It's a physical command
4669 mode = 00 target = 0. Nothing to write.
4670 */
4671 c->Request.CDBLen = 12;
4672 c->Request.Type.Attribute = ATTR_SIMPLE;
4673 c->Request.Type.Direction = XFER_READ;
4674 c->Request.Timeout = 0;
4675 c->Request.CDB[0] = cmd;
4676 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4677 c->Request.CDB[7] = (size >> 16) & 0xFF;
4678 c->Request.CDB[8] = (size >> 8) & 0xFF;
4679 c->Request.CDB[9] = size & 0xFF;
4680 break;
edd16368
SC		 4681 case HPSA_CACHE_FLUSH:
4682 c->Request.CDBLen = 12;
4683 c->Request.Type.Attribute = ATTR_SIMPLE;
4684 c->Request.Type.Direction = XFER_WRITE;
4685 c->Request.Timeout = 0;
4686 c->Request.CDB[0] = BMIC_WRITE;
4687 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4688 c->Request.CDB[7] = (size >> 8) & 0xFF;
4689 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4690 break;
4691 case TEST_UNIT_READY:
4692 c->Request.CDBLen = 6;
4693 c->Request.Type.Attribute = ATTR_SIMPLE;
4694 c->Request.Type.Direction = XFER_NONE;
4695 c->Request.Timeout = 0;
4696 break;
283b4a9b
SC		 4697 case HPSA_GET_RAID_MAP:
4698 c->Request.CDBLen = 12;
4699 c->Request.Type.Attribute = ATTR_SIMPLE;
4700 c->Request.Type.Direction = XFER_READ;
4701 c->Request.Timeout = 0;
4702 c->Request.CDB[0] = HPSA_CISS_READ;
4703 c->Request.CDB[1] = cmd;
4704 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4705 c->Request.CDB[7] = (size >> 16) & 0xFF;
4706 c->Request.CDB[8] = (size >> 8) & 0xFF;
4707 c->Request.CDB[9] = size & 0xFF;
4708 break;
edd16368
SC		 4709 default:
4710 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4711 BUG();
a2dac136 4712 return -1;
edd16368
SC		 4713 }
4714 } else if (cmd_type == TYPE_MSG) {
4715 switch (cmd) {
4716
4717 case HPSA_DEVICE_RESET_MSG:
4718 c->Request.CDBLen = 16;
4719 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4720 c->Request.Type.Attribute = ATTR_SIMPLE;
4721 c->Request.Type.Direction = XFER_NONE;
4722 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4723 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4724 c->Request.CDB[0] = cmd;
21e89afd 4725 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4726 /* If bytes 4-7 are zero, it means reset the */
4727 /* LunID device */
4728 c->Request.CDB[4] = 0x00;
4729 c->Request.CDB[5] = 0x00;
4730 c->Request.CDB[6] = 0x00;
4731 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4732 break;
4733 case HPSA_ABORT_MSG:
4734 a = buff; /* point to command to be aborted */
4735 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4736 a->Header.Tag.upper, a->Header.Tag.lower,
4737 c->Header.Tag.upper, c->Header.Tag.lower);
4738 c->Request.CDBLen = 16;
4739 c->Request.Type.Type = TYPE_MSG;
4740 c->Request.Type.Attribute = ATTR_SIMPLE;
4741 c->Request.Type.Direction = XFER_WRITE;
4742 c->Request.Timeout = 0; /* Don't time out */
4743 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4744 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4745 c->Request.CDB[2] = 0x00; /* reserved */
4746 c->Request.CDB[3] = 0x00; /* reserved */
4747 /* Tag to abort goes in CDB[4]-CDB[11] */
4748 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4749 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4750 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4751 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4752 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4753 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4754 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4755 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4756 c->Request.CDB[12] = 0x00; /* reserved */
4757 c->Request.CDB[13] = 0x00; /* reserved */
4758 c->Request.CDB[14] = 0x00; /* reserved */
4759 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4760 break;
edd16368
SC		 4761 default:
4762 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4763 cmd);
4764 BUG();
4765 }
4766 } else {
4767 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4768 BUG();
4769 }
4770
4771 switch (c->Request.Type.Direction) {
4772 case XFER_READ:
4773 pci_dir = PCI_DMA_FROMDEVICE;
4774 break;
4775 case XFER_WRITE:
4776 pci_dir = PCI_DMA_TODEVICE;
4777 break;
4778 case XFER_NONE:
4779 pci_dir = PCI_DMA_NONE;
4780 break;
4781 default:
4782 pci_dir = PCI_DMA_BIDIRECTIONAL;
4783 }
a2dac136
SC		 4784 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4785 return -1;
4786 return 0;
edd16368
SC		 4787}
4788
4789/*
4790 * Map (physical) PCI mem into (virtual) kernel space
4791 */
4792static void __iomem *remap_pci_mem(ulong base, ulong size)
4793{
4794 ulong page_base = ((ulong) base) & PAGE_MASK;
4795 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4796 void __iomem *page_remapped = ioremap_nocache(page_base,
4797 page_offs + size);
edd16368
SC		 4798
4799 return page_remapped ? (page_remapped + page_offs) : NULL;
4800}
4801
4802/* Takes cmds off the submission queue and sends them to the hardware,
4803 * then puts them on the queue of cmds waiting for completion.
4804 */
4805static void start_io(struct ctlr_info *h)
4806{
4807 struct CommandList *c;
e16a33ad 4808 unsigned long flags;
edd16368 4809
e16a33ad 4810 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4811 while (!list_empty(&h->reqQ)) {
4812 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4813 /* can't do anything if fifo is full */
4814 if ((h->access.fifo_full(h))) {
396883e2 4815 h->fifo_recently_full = 1;
edd16368
SC		 4816 dev_warn(&h->pdev->dev, "fifo full\n");
4817 break;
4818 }
396883e2 4819 h->fifo_recently_full = 0;
edd16368
SC		 4820
4821 /* Get the first entry from the Request Q */
4822 removeQ(c);
4823 h->Qdepth--;
4824
edd16368
SC		 4825 /* Put job onto the completed Q */
4826 addQ(&h->cmpQ, c);
e16a33ad
MG		 4827
4828 /* Must increment commands_outstanding before unlocking
4829 * and submitting to avoid race checking for fifo full
4830 * condition.
4831 */
4832 h->commands_outstanding++;
4833 if (h->commands_outstanding > h->max_outstanding)
4834 h->max_outstanding = h->commands_outstanding;
4835
4836 /* Tell the controller execute command */
4837 spin_unlock_irqrestore(&h->lock, flags);
4838 h->access.submit_command(h, c);
4839 spin_lock_irqsave(&h->lock, flags);
edd16368 4840 }
e16a33ad 4841 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4842}
4843
254f796b 4844static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4845{
254f796b 4846 return h->access.command_completed(h, q);
edd16368
SC		 4847}
4848
900c5440 4849static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4850{
4851 return h->access.intr_pending(h);
4852}
4853
4854static inline long interrupt_not_for_us(struct ctlr_info *h)
4855{
10f66018
SC		 4856 return (h->access.intr_pending(h) == 0) ||
4857 (h->interrupts_enabled == 0);
edd16368
SC		 4858}
4859
01a02ffc
SC		 4860static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4861 u32 raw_tag)
edd16368
SC		 4862{
4863 if (unlikely(tag_index >= h->nr_cmds)) {
4864 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4865 return 1;
4866 }
4867 return 0;
4868}
4869
5a3d16f5 4870static inline void finish_cmd(struct CommandList *c)
edd16368 4871{
e16a33ad 4872 unsigned long flags;
396883e2
SC		 4873 int io_may_be_stalled = 0;
4874 struct ctlr_info *h = c->h;
e16a33ad 4875
396883e2 4876 spin_lock_irqsave(&h->lock, flags);
edd16368 4877 removeQ(c);
396883e2
SC		 4878
4879 /*
4880 * Check for possibly stalled i/o.
4881 *
4882 * If a fifo_full condition is encountered, requests will back up
4883 * in h->reqQ. This queue is only emptied out by start_io which is
4884 * only called when a new i/o request comes in. If no i/o's are
4885 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4886 * start_io from here if we detect such a danger.
4887 *
4888 * Normally, we shouldn't hit this case, but pounding on the
4889 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4890 * commands_outstanding is low. We want to avoid calling
4891 * start_io from in here as much as possible, and esp. don't
4892 * want to get in a cycle where we call start_io every time
4893 * through here.
4894 */
4895 if (unlikely(h->fifo_recently_full) &&
4896 h->commands_outstanding < 5)
4897 io_may_be_stalled = 1;
4898
4899 spin_unlock_irqrestore(&h->lock, flags);
4900
e85c5974 4901 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 4902 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
4903 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 4904 complete_scsi_command(c);
edd16368
SC		 4905 else if (c->cmd_type == CMD_IOCTL_PEND)
4906 complete(c->waiting);
396883e2
SC		 4907 if (unlikely(io_may_be_stalled))
4908 start_io(h);
edd16368
SC		 4909}
4910
a104c99f
SC		 4911static inline u32 hpsa_tag_contains_index(u32 tag)
4912{
a104c99f
SC		 4913 return tag & DIRECT_LOOKUP_BIT;
4914}
4915
4916static inline u32 hpsa_tag_to_index(u32 tag)
4917{
a104c99f
SC		 4918 return tag >> DIRECT_LOOKUP_SHIFT;
4919}
4920
a9a3a273
SC		 4921
4922static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4923{
a9a3a273
SC		 4924#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4925#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4926 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4927 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4928 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4929}
4930
303932fd 4931/* process completion of an indexed ("direct lookup") command */
1d94f94d 4932static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4933 u32 raw_tag)
4934{
4935 u32 tag_index;
4936 struct CommandList *c;
4937
4938 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4939 if (!bad_tag(h, tag_index, raw_tag)) {
4940 c = h->cmd_pool + tag_index;
4941 finish_cmd(c);
4942 }
303932fd
DB		 4943}
4944
4945/* process completion of a non-indexed command */
1d94f94d 4946static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4947 u32 raw_tag)
4948{
4949 u32 tag;
4950 struct CommandList *c = NULL;
e16a33ad 4951 unsigned long flags;
303932fd 4952
a9a3a273 4953 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4954 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4955 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4956 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4957 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4958 finish_cmd(c);
1d94f94d 4959 return;
303932fd
DB		 4960 }
4961 }
e16a33ad 4962 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4963 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4964}
4965
64670ac8
SC		 4966/* Some controllers, like p400, will give us one interrupt
4967 * after a soft reset, even if we turned interrupts off.
4968 * Only need to check for this in the hpsa_xxx_discard_completions
4969 * functions.
4970 */
4971static int ignore_bogus_interrupt(struct ctlr_info *h)
4972{
4973 if (likely(!reset_devices))
4974 return 0;
4975
4976 if (likely(h->interrupts_enabled))
4977 return 0;
4978
4979 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4980 "(known firmware bug.) Ignoring.\n");
4981
4982 return 1;
4983}
4984
254f796b
MG		 4985/*
4986 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4987 * Relies on (h-q[x] == x) being true for x such that
4988 * 0 <= x < MAX_REPLY_QUEUES.
4989 */
4990static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4991{
254f796b
MG		 4992 return container_of((queue - *queue), struct ctlr_info, q[0]);
4993}
4994
4995static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4996{
4997 struct ctlr_info *h = queue_to_hba(queue);
4998 u8 q = *(u8 *) queue;
64670ac8
SC		 4999 u32 raw_tag;
5000
5001 if (ignore_bogus_interrupt(h))
5002 return IRQ_NONE;
5003
5004 if (interrupt_not_for_us(h))
5005 return IRQ_NONE;
a0c12413 5006 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5007 while (interrupt_pending(h)) {
254f796b 5008 raw_tag = get_next_completion(h, q);
64670ac8 5009 while (raw_tag != FIFO_EMPTY)
254f796b 5010 raw_tag = next_command(h, q);
64670ac8 5011 }
64670ac8
SC		 5012 return IRQ_HANDLED;
5013}
5014
254f796b 5015static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5016{
254f796b 5017 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5018 u32 raw_tag;
254f796b 5019 u8 q = *(u8 *) queue;
64670ac8
SC		 5020
5021 if (ignore_bogus_interrupt(h))
5022 return IRQ_NONE;
5023
a0c12413 5024 h->last_intr_timestamp = get_jiffies_64();
254f796b 5025 raw_tag = get_next_completion(h, q);
64670ac8 5026 while (raw_tag != FIFO_EMPTY)
254f796b 5027 raw_tag = next_command(h, q);
64670ac8
SC		 5028 return IRQ_HANDLED;
5029}
5030
254f796b 5031static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5032{
254f796b 5033 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5034 u32 raw_tag;
254f796b 5035 u8 q = *(u8 *) queue;
edd16368
SC		 5036
5037 if (interrupt_not_for_us(h))
5038 return IRQ_NONE;
a0c12413 5039 h->last_intr_timestamp = get_jiffies_64();
10f66018 5040 while (interrupt_pending(h)) {
254f796b 5041 raw_tag = get_next_completion(h, q);
10f66018 5042 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5043 if (likely(hpsa_tag_contains_index(raw_tag)))
5044 process_indexed_cmd(h, raw_tag);
10f66018 5045 else
1d94f94d 5046 process_nonindexed_cmd(h, raw_tag);
254f796b 5047 raw_tag = next_command(h, q);
10f66018
SC		 5048 }
5049 }
10f66018
SC		 5050 return IRQ_HANDLED;
5051}
5052
254f796b 5053static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5054{
254f796b 5055 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5056 u32 raw_tag;
254f796b 5057 u8 q = *(u8 *) queue;
10f66018 5058
a0c12413 5059 h->last_intr_timestamp = get_jiffies_64();
254f796b 5060 raw_tag = get_next_completion(h, q);
303932fd 5061 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5062 if (likely(hpsa_tag_contains_index(raw_tag)))
5063 process_indexed_cmd(h, raw_tag);
303932fd 5064 else
1d94f94d 5065 process_nonindexed_cmd(h, raw_tag);
254f796b 5066 raw_tag = next_command(h, q);
edd16368 5067 }
edd16368
SC		 5068 return IRQ_HANDLED;
5069}
5070
a9a3a273
SC		 5071/* Send a message CDB to the firmware. Careful, this only works
5072 * in simple mode, not performant mode due to the tag lookup.
5073 * We only ever use this immediately after a controller reset.
5074 */
6f039790
GKH		 5075static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5076 unsigned char type)
edd16368
SC		 5077{
5078 struct Command {
5079 struct CommandListHeader CommandHeader;
5080 struct RequestBlock Request;
5081 struct ErrDescriptor ErrorDescriptor;
5082 };
5083 struct Command *cmd;
5084 static const size_t cmd_sz = sizeof(*cmd) +
5085 sizeof(cmd->ErrorDescriptor);
5086 dma_addr_t paddr64;
5087 uint32_t paddr32, tag;
5088 void __iomem *vaddr;
5089 int i, err;
5090
5091 vaddr = pci_ioremap_bar(pdev, 0);
5092 if (vaddr == NULL)
5093 return -ENOMEM;
5094
5095 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5096 * CCISS commands, so they must be allocated from the lower 4GiB of
5097 * memory.
5098 */
5099 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5100 if (err) {
5101 iounmap(vaddr);
5102 return -ENOMEM;
5103 }
5104
5105 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5106 if (cmd == NULL) {
5107 iounmap(vaddr);
5108 return -ENOMEM;
5109 }
5110
5111 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5112 * although there's no guarantee, we assume that the address is at
5113 * least 4-byte aligned (most likely, it's page-aligned).
5114 */
5115 paddr32 = paddr64;
5116
5117 cmd->CommandHeader.ReplyQueue = 0;
5118 cmd->CommandHeader.SGList = 0;
5119 cmd->CommandHeader.SGTotal = 0;
5120 cmd->CommandHeader.Tag.lower = paddr32;
5121 cmd->CommandHeader.Tag.upper = 0;
5122 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5123
5124 cmd->Request.CDBLen = 16;
5125 cmd->Request.Type.Type = TYPE_MSG;
5126 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5127 cmd->Request.Type.Direction = XFER_NONE;
5128 cmd->Request.Timeout = 0; /* Don't time out */
5129 cmd->Request.CDB[0] = opcode;
5130 cmd->Request.CDB[1] = type;
5131 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5132 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5133 cmd->ErrorDescriptor.Addr.upper = 0;
5134 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5135
5136 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5137
5138 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5139 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5140 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5141 break;
5142 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5143 }
5144
5145 iounmap(vaddr);
5146
5147 /* we leak the DMA buffer here ... no choice since the controller could
5148 * still complete the command.
5149 */
5150 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5151 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5152 opcode, type);
5153 return -ETIMEDOUT;
5154 }
5155
5156 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5157
5158 if (tag & HPSA_ERROR_BIT) {
5159 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5160 opcode, type);
5161 return -EIO;
5162 }
5163
5164 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5165 opcode, type);
5166 return 0;
5167}
5168
edd16368
SC		 5169#define hpsa_noop(p) hpsa_message(p, 3, 0)
5170
1df8552a 5171static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5172 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5173{
5174 u16 pmcsr;
5175 int pos;
5176
5177 if (use_doorbell) {
5178 /* For everything after the P600, the PCI power state method
5179 * of resetting the controller doesn't work, so we have this
5180 * other way using the doorbell register.
5181 */
5182 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5183 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5184
5185 /* PMC hardware guys tell us we need a 5 second delay after
5186 * doorbell reset and before any attempt to talk to the board
5187 * at all to ensure that this actually works and doesn't fall
5188 * over in some weird corner cases.
5189 */
5190 msleep(5000);
1df8552a
SC		 5191 } else { /* Try to do it the PCI power state way */
5192
5193 /* Quoting from the Open CISS Specification: "The Power
5194 * Management Control/Status Register (CSR) controls the power
5195 * state of the device. The normal operating state is D0,
5196 * CSR=00h. The software off state is D3, CSR=03h. To reset
5197 * the controller, place the interface device in D3 then to D0,
5198 * this causes a secondary PCI reset which will reset the
5199 * controller." */
5200
5201 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5202 if (pos == 0) {
5203 dev_err(&pdev->dev,
5204 "hpsa_reset_controller: "
5205 "PCI PM not supported\n");
5206 return -ENODEV;
5207 }
5208 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5209 /* enter the D3hot power management state */
5210 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5211 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5212 pmcsr |= PCI_D3hot;
5213 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5214
5215 msleep(500);
5216
5217 /* enter the D0 power management state */
5218 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5219 pmcsr |= PCI_D0;
5220 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5221
5222 /*
5223 * The P600 requires a small delay when changing states.
5224 * Otherwise we may think the board did not reset and we bail.
5225 * This for kdump only and is particular to the P600.
5226 */
5227 msleep(500);
1df8552a
SC		 5228 }
5229 return 0;
5230}
5231
6f039790 5232static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5233{
5234 memset(driver_version, 0, len);
f79cfec6 5235 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5236}
5237
6f039790 5238static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5239{
5240 char *driver_version;
5241 int i, size = sizeof(cfgtable->driver_version);
5242
5243 driver_version = kmalloc(size, GFP_KERNEL);
5244 if (!driver_version)
5245 return -ENOMEM;
5246
5247 init_driver_version(driver_version, size);
5248 for (i = 0; i < size; i++)
5249 writeb(driver_version[i], &cfgtable->driver_version[i]);
5250 kfree(driver_version);
5251 return 0;
5252}
5253
6f039790
GKH		 5254static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5255 unsigned char *driver_ver)
580ada3c
SC		 5256{
5257 int i;
5258
5259 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5260 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5261}
5262
6f039790 5263static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5264{
5265
5266 char *driver_ver, *old_driver_ver;
5267 int rc, size = sizeof(cfgtable->driver_version);
5268
5269 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5270 if (!old_driver_ver)
5271 return -ENOMEM;
5272 driver_ver = old_driver_ver + size;
5273
5274 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5275 * should have been changed, otherwise we know the reset failed.
5276 */
5277 init_driver_version(old_driver_ver, size);
5278 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5279 rc = !memcmp(driver_ver, old_driver_ver, size);
5280 kfree(old_driver_ver);
5281 return rc;
5282}
edd16368 5283/* This does a hard reset of the controller using PCI power management
1df8552a 5284 * states or the using the doorbell register.
edd16368 5285 */
6f039790 5286static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5287{
1df8552a
SC		 5288 u64 cfg_offset;
5289 u32 cfg_base_addr;
5290 u64 cfg_base_addr_index;
5291 void __iomem *vaddr;
5292 unsigned long paddr;
580ada3c 5293 u32 misc_fw_support;
270d05de 5294 int rc;
1df8552a 5295 struct CfgTable __iomem *cfgtable;
cf0b08d0 5296 u32 use_doorbell;
18867659 5297 u32 board_id;
270d05de 5298 u16 command_register;
edd16368 5299
1df8552a
SC		 5300 /* For controllers as old as the P600, this is very nearly
5301 * the same thing as
edd16368
SC		 5302 *
5303 * pci_save_state(pci_dev);
5304 * pci_set_power_state(pci_dev, PCI_D3hot);
5305 * pci_set_power_state(pci_dev, PCI_D0);
5306 * pci_restore_state(pci_dev);
5307 *
1df8552a
SC		 5308 * For controllers newer than the P600, the pci power state
5309 * method of resetting doesn't work so we have another way
5310 * using the doorbell register.
edd16368 5311 */
18867659 5312
25c1e56a 5313 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5314 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5315 dev_warn(&pdev->dev, "Not resetting device.\n");
5316 return -ENODEV;
5317 }
46380786
SC		 5318
5319 /* if controller is soft- but not hard resettable... */
5320 if (!ctlr_is_hard_resettable(board_id))
5321 return -ENOTSUPP; /* try soft reset later. */
18867659 5322
270d05de
SC		 5323 /* Save the PCI command register */
5324 pci_read_config_word(pdev, 4, &command_register);
5325 /* Turn the board off. This is so that later pci_restore_state()
5326 * won't turn the board on before the rest of config space is ready.
5327 */
5328 pci_disable_device(pdev);
5329 pci_save_state(pdev);
edd16368 5330
1df8552a
SC		 5331 /* find the first memory BAR, so we can find the cfg table */
5332 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5333 if (rc)
5334 return rc;
5335 vaddr = remap_pci_mem(paddr, 0x250);
5336 if (!vaddr)
5337 return -ENOMEM;
edd16368 5338
1df8552a
SC		 5339 /* find cfgtable in order to check if reset via doorbell is supported */
5340 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5341 &cfg_base_addr_index, &cfg_offset);
5342 if (rc)
5343 goto unmap_vaddr;
5344 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5345 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5346 if (!cfgtable) {
5347 rc = -ENOMEM;
5348 goto unmap_vaddr;
5349 }
580ada3c
SC		 5350 rc = write_driver_ver_to_cfgtable(cfgtable);
5351 if (rc)
5352 goto unmap_vaddr;
edd16368 5353
cf0b08d0
SC		 5354 /* If reset via doorbell register is supported, use that.
5355 * There are two such methods. Favor the newest method.
5356 */
1df8552a 5357 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5358 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5359 if (use_doorbell) {
5360 use_doorbell = DOORBELL_CTLR_RESET2;
5361 } else {
5362 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5363 if (use_doorbell) {
fba63097
MM		 5364 dev_warn(&pdev->dev, "Soft reset not supported. "
5365 "Firmware update is required.\n");
64670ac8 5366 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5367 goto unmap_cfgtable;
5368 }
5369 }
edd16368 5370
1df8552a
SC		 5371 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5372 if (rc)
5373 goto unmap_cfgtable;
edd16368 5374
270d05de
SC		 5375 pci_restore_state(pdev);
5376 rc = pci_enable_device(pdev);
5377 if (rc) {
5378 dev_warn(&pdev->dev, "failed to enable device.\n");
5379 goto unmap_cfgtable;
edd16368 5380 }
270d05de 5381 pci_write_config_word(pdev, 4, command_register);
edd16368 5382
1df8552a
SC		 5383 /* Some devices (notably the HP Smart Array 5i Controller)
5384 need a little pause here */
5385 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5386
fe5389c8
SC		 5387 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5388 if (rc) {
5389 dev_warn(&pdev->dev,
64670ac8
SC		 5390 "failed waiting for board to become ready "
5391 "after hard reset\n");
fe5389c8
SC		 5392 goto unmap_cfgtable;
5393 }
fe5389c8 5394
580ada3c
SC		 5395 rc = controller_reset_failed(vaddr);
5396 if (rc < 0)
5397 goto unmap_cfgtable;
5398 if (rc) {
64670ac8
SC		 5399 dev_warn(&pdev->dev, "Unable to successfully reset "
5400 "controller. Will try soft reset.\n");
5401 rc = -ENOTSUPP;
580ada3c 5402 } else {
64670ac8 5403 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5404 }
5405
5406unmap_cfgtable:
5407 iounmap(cfgtable);
5408
5409unmap_vaddr:
5410 iounmap(vaddr);
5411 return rc;
edd16368
SC		 5412}
5413
5414/*
5415 * We cannot read the structure directly, for portability we must use
5416 * the io functions.
5417 * This is for debug only.
5418 */
edd16368
SC		 5419static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5420{
58f8665c 5421#ifdef HPSA_DEBUG
edd16368
SC		 5422 int i;
5423 char temp_name[17];
5424
5425 dev_info(dev, "Controller Configuration information\n");
5426 dev_info(dev, "------------------------------------\n");
5427 for (i = 0; i < 4; i++)
5428 temp_name[i] = readb(&(tb->Signature[i]));
5429 temp_name[4] = '\0';
5430 dev_info(dev, " Signature = %s\n", temp_name);
5431 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5432 dev_info(dev, " Transport methods supported = 0x%x\n",
5433 readl(&(tb->TransportSupport)));
5434 dev_info(dev, " Transport methods active = 0x%x\n",
5435 readl(&(tb->TransportActive)));
5436 dev_info(dev, " Requested transport Method = 0x%x\n",
5437 readl(&(tb->HostWrite.TransportRequest)));
5438 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5439 readl(&(tb->HostWrite.CoalIntDelay)));
5440 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5441 readl(&(tb->HostWrite.CoalIntCount)));
5442 dev_info(dev, " Max outstanding commands = 0x%d\n",
5443 readl(&(tb->CmdsOutMax)));
5444 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5445 for (i = 0; i < 16; i++)
5446 temp_name[i] = readb(&(tb->ServerName[i]));
5447 temp_name[16] = '\0';
5448 dev_info(dev, " Server Name = %s\n", temp_name);
5449 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5450 readl(&(tb->HeartBeat)));
edd16368 5451#endif /* HPSA_DEBUG */
58f8665c 5452}
edd16368
SC		 5453
5454static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5455{
5456 int i, offset, mem_type, bar_type;
5457
5458 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5459 return 0;
5460 offset = 0;
5461 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5462 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5463 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5464 offset += 4;
5465 else {
5466 mem_type = pci_resource_flags(pdev, i) &
5467 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5468 switch (mem_type) {
5469 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5470 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5471 offset += 4; /* 32 bit */
5472 break;
5473 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5474 offset += 8;
5475 break;
5476 default: /* reserved in PCI 2.2 */
5477 dev_warn(&pdev->dev,
5478 "base address is invalid\n");
5479 return -1;
5480 break;
5481 }
5482 }
5483 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5484 return i + 1;
5485 }
5486 return -1;
5487}
5488
5489/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5490 * controllers that are capable. If not, we use IO-APIC mode.
5491 */
5492
6f039790 5493static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5494{
5495#ifdef CONFIG_PCI_MSI
254f796b
MG		 5496 int err, i;
5497 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5498
5499 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5500 hpsa_msix_entries[i].vector = 0;
5501 hpsa_msix_entries[i].entry = i;
5502 }
edd16368
SC		 5503
5504 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5505 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5506 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5507 goto default_int_mode;
55c06c71
SC		 5508 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5509 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5510 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5511 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5512 h->msix_vector);
edd16368 5513 if (err > 0) {
55c06c71 5514 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5515 "available\n", err);
eee0f03a
HR		 5516 h->msix_vector = err;
5517 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5518 h->msix_vector);
5519 }
5520 if (!err) {
5521 for (i = 0; i < h->msix_vector; i++)
5522 h->intr[i] = hpsa_msix_entries[i].vector;
5523 return;
edd16368 5524 } else {
55c06c71 5525 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5526 err);
eee0f03a 5527 h->msix_vector = 0;
edd16368
SC		 5528 goto default_int_mode;
5529 }
5530 }
55c06c71
SC		 5531 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5532 dev_info(&h->pdev->dev, "MSI\n");
5533 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5534 h->msi_vector = 1;
5535 else
55c06c71 5536 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5537 }
5538default_int_mode:
5539#endif /* CONFIG_PCI_MSI */
5540 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5541 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5542}
5543
6f039790 5544static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5545{
5546 int i;
5547 u32 subsystem_vendor_id, subsystem_device_id;
5548
5549 subsystem_vendor_id = pdev->subsystem_vendor;
5550 subsystem_device_id = pdev->subsystem_device;
5551 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5552 subsystem_vendor_id;
5553
5554 for (i = 0; i < ARRAY_SIZE(products); i++)
5555 if (*board_id == products[i].board_id)
5556 return i;
5557
6798cc0a
SC		 5558 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5559 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5560 !hpsa_allow_any) {
e5c880d1
SC		 5561 dev_warn(&pdev->dev, "unrecognized board ID: "
5562 "0x%08x, ignoring.\n", *board_id);
5563 return -ENODEV;
5564 }
5565 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5566}
5567
6f039790
GKH		 5568static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5569 unsigned long *memory_bar)
3a7774ce
SC		 5570{
5571 int i;
5572
5573 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5574 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5575 /* addressing mode bits already removed */
12d2cd47
SC		 5576 *memory_bar = pci_resource_start(pdev, i);
5577 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5578 *memory_bar);
5579 return 0;
5580 }
12d2cd47 5581 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5582 return -ENODEV;
5583}
5584
6f039790
GKH		 5585static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5586 int wait_for_ready)
2c4c8c8b 5587{
fe5389c8 5588 int i, iterations;
2c4c8c8b 5589 u32 scratchpad;
fe5389c8
SC		 5590 if (wait_for_ready)
5591 iterations = HPSA_BOARD_READY_ITERATIONS;
5592 else
5593 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5594
fe5389c8
SC		 5595 for (i = 0; i < iterations; i++) {
5596 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5597 if (wait_for_ready) {
5598 if (scratchpad == HPSA_FIRMWARE_READY)
5599 return 0;
5600 } else {
5601 if (scratchpad != HPSA_FIRMWARE_READY)
5602 return 0;
5603 }
2c4c8c8b
SC		 5604 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5605 }
fe5389c8 5606 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5607 return -ENODEV;
5608}
5609
6f039790
GKH		 5610static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5611 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5612 u64 *cfg_offset)
a51fd47f
SC		 5613{
5614 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5615 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5616 *cfg_base_addr &= (u32) 0x0000ffff;
5617 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5618 if (*cfg_base_addr_index == -1) {
5619 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5620 return -ENODEV;
5621 }
5622 return 0;
5623}
5624
6f039790 5625static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5626{
01a02ffc
SC		 5627 u64 cfg_offset;
5628 u32 cfg_base_addr;
5629 u64 cfg_base_addr_index;
303932fd 5630 u32 trans_offset;
a51fd47f 5631 int rc;
77c4495c 5632
a51fd47f
SC		 5633 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5634 &cfg_base_addr_index, &cfg_offset);
5635 if (rc)
5636 return rc;
77c4495c 5637 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5638 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5639 if (!h->cfgtable)
5640 return -ENOMEM;
580ada3c
SC		 5641 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5642 if (rc)
5643 return rc;
77c4495c 5644 /* Find performant mode table. */
a51fd47f 5645 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5646 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5647 cfg_base_addr_index)+cfg_offset+trans_offset,
5648 sizeof(*h->transtable));
5649 if (!h->transtable)
5650 return -ENOMEM;
5651 return 0;
5652}
5653
6f039790 5654static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5655{
5656 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5657
5658 /* Limit commands in memory limited kdump scenario. */
5659 if (reset_devices && h->max_commands > 32)
5660 h->max_commands = 32;
5661
cba3d38b
SC		 5662 if (h->max_commands < 16) {
5663 dev_warn(&h->pdev->dev, "Controller reports "
5664 "max supported commands of %d, an obvious lie. "
5665 "Using 16. Ensure that firmware is up to date.\n",
5666 h->max_commands);
5667 h->max_commands = 16;
5668 }
5669}
5670
b93d7536
SC		 5671/* Interrogate the hardware for some limits:
5672 * max commands, max SG elements without chaining, and with chaining,
5673 * SG chain block size, etc.
5674 */
6f039790 5675static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5676{
cba3d38b 5677 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5678 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5679 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5680 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5681 /*
5682 * Limit in-command s/g elements to 32 save dma'able memory.
5683 * Howvever spec says if 0, use 31
5684 */
5685 h->max_cmd_sg_entries = 31;
5686 if (h->maxsgentries > 512) {
5687 h->max_cmd_sg_entries = 32;
5688 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5689 h->maxsgentries--; /* save one for chain pointer */
5690 } else {
5691 h->maxsgentries = 31; /* default to traditional values */
5692 h->chainsize = 0;
5693 }
75167d2c
SC		 5694
5695 /* Find out what task management functions are supported and cache */
5696 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5697 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5698 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5699 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5700 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5701}
5702
76c46e49
SC		 5703static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5704{
0fc9fd40 5705 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5706 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5707 return false;
5708 }
5709 return true;
5710}
5711
97a5e98c 5712static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5713{
97a5e98c 5714 u32 driver_support;
f7c39101 5715
28e13446
SC		 5716#ifdef CONFIG_X86
5717 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5718 driver_support = readl(&(h->cfgtable->driver_support));
5719 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5720#endif
28e13446
SC		 5721 driver_support |= ENABLE_UNIT_ATTN;
5722 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5723}
5724
3d0eab67
SC		 5725/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5726 * in a prefetch beyond physical memory.
5727 */
5728static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5729{
5730 u32 dma_prefetch;
5731
5732 if (h->board_id != 0x3225103C)
5733 return;
5734 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5735 dma_prefetch |= 0x8000;
5736 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5737}
5738
76438d08
SC		 5739static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5740{
5741 int i;
5742 u32 doorbell_value;
5743 unsigned long flags;
5744 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5745 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5746 spin_lock_irqsave(&h->lock, flags);
5747 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5748 spin_unlock_irqrestore(&h->lock, flags);
5749 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5750 break;
5751 /* delay and try again */
5752 msleep(20);
5753 }
5754}
5755
6f039790 5756static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5757{
5758 int i;
6eaf46fd
SC		 5759 u32 doorbell_value;
5760 unsigned long flags;
eb6b2ae9
SC		 5761
5762 /* under certain very rare conditions, this can take awhile.
5763 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5764 * as we enter this code.)
5765 */
5766 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5767 spin_lock_irqsave(&h->lock, flags);
5768 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5769 spin_unlock_irqrestore(&h->lock, flags);
382be668 5770 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5771 break;
5772 /* delay and try again */
60d3f5b0 5773 usleep_range(10000, 20000);
eb6b2ae9 5774 }
3f4336f3
SC		 5775}
5776
6f039790 5777static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5778{
5779 u32 trans_support;
5780
5781 trans_support = readl(&(h->cfgtable->TransportSupport));
5782 if (!(trans_support & SIMPLE_MODE))
5783 return -ENOTSUPP;
5784
5785 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5786
3f4336f3
SC		 5787 /* Update the field, and then ring the doorbell */
5788 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 5789 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 5790 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5791 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5792 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5793 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5794 goto error;
960a30e7 5795 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5796 return 0;
283b4a9b
SC		 5797error:
5798 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5799 return -ENODEV;
eb6b2ae9
SC		 5800}
5801
6f039790 5802static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5803{
eb6b2ae9 5804 int prod_index, err;
edd16368 5805
e5c880d1
SC		 5806 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5807 if (prod_index < 0)
5808 return -ENODEV;
5809 h->product_name = products[prod_index].product_name;
5810 h->access = *(products[prod_index].access);
edd16368 5811
e5a44df8
MG		 5812 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5813 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5814
55c06c71 5815 err = pci_enable_device(h->pdev);
edd16368 5816 if (err) {
55c06c71 5817 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5818 return err;
5819 }
5820
5cb460a6
SC		 5821 /* Enable bus mastering (pci_disable_device may disable this) */
5822 pci_set_master(h->pdev);
5823
f79cfec6 5824 err = pci_request_regions(h->pdev, HPSA);
edd16368 5825 if (err) {
55c06c71
SC		 5826 dev_err(&h->pdev->dev,
5827 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5828 return err;
5829 }
6b3f4c52 5830 hpsa_interrupt_mode(h);
12d2cd47 5831 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5832 if (err)
edd16368 5833 goto err_out_free_res;
edd16368 5834 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5835 if (!h->vaddr) {
5836 err = -ENOMEM;
5837 goto err_out_free_res;
5838 }
fe5389c8 5839 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5840 if (err)
edd16368 5841 goto err_out_free_res;
77c4495c
SC		 5842 err = hpsa_find_cfgtables(h);
5843 if (err)
edd16368 5844 goto err_out_free_res;
b93d7536 5845 hpsa_find_board_params(h);
edd16368 5846
76c46e49 5847 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5848 err = -ENODEV;
5849 goto err_out_free_res;
5850 }
97a5e98c 5851 hpsa_set_driver_support_bits(h);
3d0eab67 5852 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5853 err = hpsa_enter_simple_mode(h);
5854 if (err)
edd16368 5855 goto err_out_free_res;
edd16368
SC		 5856 return 0;
5857
5858err_out_free_res:
204892e9
SC		 5859 if (h->transtable)
5860 iounmap(h->transtable);
5861 if (h->cfgtable)
5862 iounmap(h->cfgtable);
5863 if (h->vaddr)
5864 iounmap(h->vaddr);
f0bd0b68 5865 pci_disable_device(h->pdev);
55c06c71 5866 pci_release_regions(h->pdev);
edd16368
SC		 5867 return err;
5868}
5869
6f039790 5870static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5871{
5872 int rc;
5873
5874#define HBA_INQUIRY_BYTE_COUNT 64
5875 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5876 if (!h->hba_inquiry_data)
5877 return;
5878 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5879 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5880 if (rc != 0) {
5881 kfree(h->hba_inquiry_data);
5882 h->hba_inquiry_data = NULL;
5883 }
5884}
5885
6f039790 5886static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5887{
1df8552a 5888 int rc, i;
4c2a8c40
SC		 5889
5890 if (!reset_devices)
5891 return 0;
5892
1df8552a
SC		 5893 /* Reset the controller with a PCI power-cycle or via doorbell */
5894 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5895
1df8552a
SC		 5896 /* -ENOTSUPP here means we cannot reset the controller
5897 * but it's already (and still) up and running in
18867659
SC		 5898 * "performant mode". Or, it might be 640x, which can't reset
5899 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5900 */
5901 if (rc == -ENOTSUPP)
64670ac8 5902 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5903 if (rc)
5904 return -ENODEV;
4c2a8c40
SC		 5905
5906 /* Now try to get the controller to respond to a no-op */
2b870cb3 5907 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5908 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5909 if (hpsa_noop(pdev) == 0)
5910 break;
5911 else
5912 dev_warn(&pdev->dev, "no-op failed%s\n",
5913 (i < 11 ? "; re-trying" : ""));
5914 }
5915 return 0;
5916}
5917
6f039790 5918static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5919{
5920 h->cmd_pool_bits = kzalloc(
5921 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5922 sizeof(unsigned long), GFP_KERNEL);
5923 h->cmd_pool = pci_alloc_consistent(h->pdev,
5924 h->nr_cmds * sizeof(*h->cmd_pool),
5925 &(h->cmd_pool_dhandle));
5926 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5927 h->nr_cmds * sizeof(*h->errinfo_pool),
5928 &(h->errinfo_pool_dhandle));
5929 if ((h->cmd_pool_bits == NULL)
5930 || (h->cmd_pool == NULL)
5931 || (h->errinfo_pool == NULL)) {
5932 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5933 return -ENOMEM;
5934 }
5935 return 0;
5936}
5937
5938static void hpsa_free_cmd_pool(struct ctlr_info *h)
5939{
5940 kfree(h->cmd_pool_bits);
5941 if (h->cmd_pool)
5942 pci_free_consistent(h->pdev,
5943 h->nr_cmds * sizeof(struct CommandList),
5944 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 5945 if (h->ioaccel2_cmd_pool)
5946 pci_free_consistent(h->pdev,
5947 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
5948 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 5949 if (h->errinfo_pool)
5950 pci_free_consistent(h->pdev,
5951 h->nr_cmds * sizeof(struct ErrorInfo),
5952 h->errinfo_pool,
5953 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5954 if (h->ioaccel_cmd_pool)
5955 pci_free_consistent(h->pdev,
5956 h->nr_cmds * sizeof(struct io_accel1_cmd),
5957 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5958}
5959
0ae01a32
SC		 5960static int hpsa_request_irq(struct ctlr_info *h,
5961 irqreturn_t (*msixhandler)(int, void *),
5962 irqreturn_t (*intxhandler)(int, void *))
5963{
254f796b 5964 int rc, i;
0ae01a32 5965
254f796b
MG		 5966 /*
5967 * initialize h->q[x] = x so that interrupt handlers know which
5968 * queue to process.
5969 */
5970 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5971 h->q[i] = (u8) i;
5972
eee0f03a 5973 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5974 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5975 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5976 rc = request_irq(h->intr[i], msixhandler,
5977 0, h->devname,
5978 &h->q[i]);
5979 } else {
5980 /* Use single reply pool */
eee0f03a 5981 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5982 rc = request_irq(h->intr[h->intr_mode],
5983 msixhandler, 0, h->devname,
5984 &h->q[h->intr_mode]);
5985 } else {
5986 rc = request_irq(h->intr[h->intr_mode],
5987 intxhandler, IRQF_SHARED, h->devname,
5988 &h->q[h->intr_mode]);
5989 }
5990 }
0ae01a32
SC		 5991 if (rc) {
5992 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5993 h->intr[h->intr_mode], h->devname);
5994 return -ENODEV;
5995 }
5996 return 0;
5997}
5998
6f039790 5999static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6000{
6001 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6002 HPSA_RESET_TYPE_CONTROLLER)) {
6003 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6004 return -EIO;
6005 }
6006
6007 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6008 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6009 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6010 return -1;
6011 }
6012
6013 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6014 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6015 dev_warn(&h->pdev->dev, "Board failed to become ready "
6016 "after soft reset.\n");
6017 return -1;
6018 }
6019
6020 return 0;
6021}
6022
254f796b
MG		 6023static void free_irqs(struct ctlr_info *h)
6024{
6025 int i;
6026
6027 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6028 /* Single reply queue, only one irq to free */
6029 i = h->intr_mode;
6030 free_irq(h->intr[i], &h->q[i]);
6031 return;
6032 }
6033
eee0f03a 6034 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6035 free_irq(h->intr[i], &h->q[i]);
6036}
6037
0097f0f4 6038static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6039{
254f796b 6040 free_irqs(h);
64670ac8 6041#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6042 if (h->msix_vector) {
6043 if (h->pdev->msix_enabled)
6044 pci_disable_msix(h->pdev);
6045 } else if (h->msi_vector) {
6046 if (h->pdev->msi_enabled)
6047 pci_disable_msi(h->pdev);
6048 }
64670ac8 6049#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6050}
6051
6052static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6053{
6054 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6055 hpsa_free_sg_chain_blocks(h);
6056 hpsa_free_cmd_pool(h);
e1f7de0c 6057 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6058 kfree(h->blockFetchTable);
6059 pci_free_consistent(h->pdev, h->reply_pool_size,
6060 h->reply_pool, h->reply_pool_dhandle);
6061 if (h->vaddr)
6062 iounmap(h->vaddr);
6063 if (h->transtable)
6064 iounmap(h->transtable);
6065 if (h->cfgtable)
6066 iounmap(h->cfgtable);
6067 pci_release_regions(h->pdev);
6068 kfree(h);
6069}
6070
a0c12413
SC		 6071/* Called when controller lockup detected. */
6072static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6073{
6074 struct CommandList *c = NULL;
6075
6076 assert_spin_locked(&h->lock);
6077 /* Mark all outstanding commands as failed and complete them. */
6078 while (!list_empty(list)) {
6079 c = list_entry(list->next, struct CommandList, list);
6080 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6081 finish_cmd(c);
a0c12413
SC		 6082 }
6083}
6084
6085static void controller_lockup_detected(struct ctlr_info *h)
6086{
6087 unsigned long flags;
6088
a0c12413
SC		 6089 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6090 spin_lock_irqsave(&h->lock, flags);
6091 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6092 spin_unlock_irqrestore(&h->lock, flags);
6093 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6094 h->lockup_detected);
6095 pci_disable_device(h->pdev);
6096 spin_lock_irqsave(&h->lock, flags);
6097 fail_all_cmds_on_list(h, &h->cmpQ);
6098 fail_all_cmds_on_list(h, &h->reqQ);
6099 spin_unlock_irqrestore(&h->lock, flags);
6100}
6101
a0c12413
SC		 6102static void detect_controller_lockup(struct ctlr_info *h)
6103{
6104 u64 now;
6105 u32 heartbeat;
6106 unsigned long flags;
6107
a0c12413
SC		 6108 now = get_jiffies_64();
6109 /* If we've received an interrupt recently, we're ok. */
6110 if (time_after64(h->last_intr_timestamp +
e85c5974 6111 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6112 return;
6113
6114 /*
6115 * If we've already checked the heartbeat recently, we're ok.
6116 * This could happen if someone sends us a signal. We
6117 * otherwise don't care about signals in this thread.
6118 */
6119 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6120 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6121 return;
6122
6123 /* If heartbeat has not changed since we last looked, we're not ok. */
6124 spin_lock_irqsave(&h->lock, flags);
6125 heartbeat = readl(&h->cfgtable->HeartBeat);
6126 spin_unlock_irqrestore(&h->lock, flags);
6127 if (h->last_heartbeat == heartbeat) {
6128 controller_lockup_detected(h);
6129 return;
6130 }
6131
6132 /* We're ok. */
6133 h->last_heartbeat = heartbeat;
6134 h->last_heartbeat_timestamp = now;
6135}
6136
76438d08
SC		 6137static int hpsa_kickoff_rescan(struct ctlr_info *h)
6138{
6139 int i;
6140 char *event_type;
6141
e863d68e
ST		 6142 /* Clear the driver-requested rescan flag */
6143 h->drv_req_rescan = 0;
6144
76438d08 6145 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6146 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6147 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6148 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6149 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6150
6151 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6152 event_type = "state change";
6153 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6154 event_type = "configuration change";
6155 /* Stop sending new RAID offload reqs via the IO accelerator */
6156 scsi_block_requests(h->scsi_host);
6157 for (i = 0; i < h->ndevices; i++)
6158 h->dev[i]->offload_enabled = 0;
6159 hpsa_drain_commands(h);
6160 /* Set 'accelerator path config change' bit */
6161 dev_warn(&h->pdev->dev,
6162 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6163 h->events, event_type);
6164 writel(h->events, &(h->cfgtable->clear_event_notify));
6165 /* Set the "clear event notify field update" bit 6 */
6166 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6167 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6168 hpsa_wait_for_clear_event_notify_ack(h);
6169 scsi_unblock_requests(h->scsi_host);
6170 } else {
6171 /* Acknowledge controller notification events. */
6172 writel(h->events, &(h->cfgtable->clear_event_notify));
6173 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6174 hpsa_wait_for_clear_event_notify_ack(h);
6175#if 0
6176 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6177 hpsa_wait_for_mode_change_ack(h);
6178#endif
6179 }
6180
6181 /* Something in the device list may have changed to trigger
6182 * the event, so do a rescan.
6183 */
6184 hpsa_scan_start(h->scsi_host);
6185 /* release reference taken on scsi host in check_controller_events */
6186 scsi_host_put(h->scsi_host);
6187 return 0;
6188}
6189
6190/* Check a register on the controller to see if there are configuration
6191 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6192 * we should rescan the controller for devices.
6193 * Also check flag for driver-initiated rescan.
6194 * If either flag or controller event indicate rescan, add the controller
76438d08
SC		 6195 * to the list of controllers needing to be rescanned, and gets a
6196 * reference to the associated scsi_host.
6197 */
6198static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
6199{
6200 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6201 return;
6202
6203 h->events = readl(&(h->cfgtable->event_notify));
e863d68e 6204 if (!h->events && !h->drv_req_rescan)
76438d08
SC		 6205 return;
6206
6207 /*
6208 * Take a reference on scsi host for the duration of the scan
6209 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
6210 * as only a single thread accesses this list.
6211 */
6212 scsi_host_get(h->scsi_host);
6213 hpsa_kickoff_rescan(h);
6214}
6215
8a98db73 6216static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6217{
6218 unsigned long flags;
8a98db73
SC		 6219 struct ctlr_info *h = container_of(to_delayed_work(work),
6220 struct ctlr_info, monitor_ctlr_work);
6221 detect_controller_lockup(h);
6222 if (h->lockup_detected)
6223 return;
76438d08 6224 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6225 spin_lock_irqsave(&h->lock, flags);
6226 if (h->remove_in_progress) {
6227 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6228 return;
6229 }
8a98db73
SC		 6230 schedule_delayed_work(&h->monitor_ctlr_work,
6231 h->heartbeat_sample_interval);
6232 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6233}
6234
6f039790 6235static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6236{
4c2a8c40 6237 int dac, rc;
edd16368 6238 struct ctlr_info *h;
64670ac8
SC		 6239 int try_soft_reset = 0;
6240 unsigned long flags;
edd16368
SC		 6241
6242 if (number_of_controllers == 0)
6243 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6244
4c2a8c40 6245 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6246 if (rc) {
6247 if (rc != -ENOTSUPP)
6248 return rc;
6249 /* If the reset fails in a particular way (it has no way to do
6250 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6251 * a soft reset once we get the controller configured up to the
6252 * point that it can accept a command.
6253 */
6254 try_soft_reset = 1;
6255 rc = 0;
6256 }
6257
6258reinit_after_soft_reset:
edd16368 6259
303932fd
DB		 6260 /* Command structures must be aligned on a 32-byte boundary because
6261 * the 5 lower bits of the address are used by the hardware. and by
6262 * the driver. See comments in hpsa.h for more info.
6263 */
283b4a9b 6264#define COMMANDLIST_ALIGNMENT 128
303932fd 6265 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6266 h = kzalloc(sizeof(*h), GFP_KERNEL);
6267 if (!h)
ecd9aad4 6268 return -ENOMEM;
edd16368 6269
55c06c71 6270 h->pdev = pdev;
a9a3a273 6271 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6272 INIT_LIST_HEAD(&h->cmpQ);
6273 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6274 spin_lock_init(&h->lock);
6275 spin_lock_init(&h->scan_lock);
0390f0c0 6276 spin_lock_init(&h->passthru_count_lock);
55c06c71 6277 rc = hpsa_pci_init(h);
ecd9aad4 6278 if (rc != 0)
edd16368
SC		 6279 goto clean1;
6280
f79cfec6 6281 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6282 h->ctlr = number_of_controllers;
6283 number_of_controllers++;
edd16368
SC		 6284
6285 /* configure PCI DMA stuff */
ecd9aad4
SC		 6286 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6287 if (rc == 0) {
edd16368 6288 dac = 1;
ecd9aad4
SC		 6289 } else {
6290 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6291 if (rc == 0) {
6292 dac = 0;
6293 } else {
6294 dev_err(&pdev->dev, "no suitable DMA available\n");
6295 goto clean1;
6296 }
edd16368
SC		 6297 }
6298
6299 /* make sure the board interrupts are off */
6300 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6301
0ae01a32 6302 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6303 goto clean2;
303932fd
DB		 6304 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6305 h->devname, pdev->device,
a9a3a273 6306 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6307 if (hpsa_allocate_cmd_pool(h))
edd16368 6308 goto clean4;
33a2ffce
SC		 6309 if (hpsa_allocate_sg_chain_blocks(h))
6310 goto clean4;
a08a8471
SC		 6311 init_waitqueue_head(&h->scan_wait_queue);
6312 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6313
6314 pci_set_drvdata(pdev, h);
9a41338e
SC		 6315 h->ndevices = 0;
6316 h->scsi_host = NULL;
6317 spin_lock_init(&h->devlock);
64670ac8
SC		 6318 hpsa_put_ctlr_into_performant_mode(h);
6319
6320 /* At this point, the controller is ready to take commands.
6321 * Now, if reset_devices and the hard reset didn't work, try
6322 * the soft reset and see if that works.
6323 */
6324 if (try_soft_reset) {
6325
6326 /* This is kind of gross. We may or may not get a completion
6327 * from the soft reset command, and if we do, then the value
6328 * from the fifo may or may not be valid. So, we wait 10 secs
6329 * after the reset throwing away any completions we get during
6330 * that time. Unregister the interrupt handler and register
6331 * fake ones to scoop up any residual completions.
6332 */
6333 spin_lock_irqsave(&h->lock, flags);
6334 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6335 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6336 free_irqs(h);
64670ac8
SC		 6337 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6338 hpsa_intx_discard_completions);
6339 if (rc) {
6340 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6341 "soft reset.\n");
6342 goto clean4;
6343 }
6344
6345 rc = hpsa_kdump_soft_reset(h);
6346 if (rc)
6347 /* Neither hard nor soft reset worked, we're hosed. */
6348 goto clean4;
6349
6350 dev_info(&h->pdev->dev, "Board READY.\n");
6351 dev_info(&h->pdev->dev,
6352 "Waiting for stale completions to drain.\n");
6353 h->access.set_intr_mask(h, HPSA_INTR_ON);
6354 msleep(10000);
6355 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6356
6357 rc = controller_reset_failed(h->cfgtable);
6358 if (rc)
6359 dev_info(&h->pdev->dev,
6360 "Soft reset appears to have failed.\n");
6361
6362 /* since the controller's reset, we have to go back and re-init
6363 * everything. Easiest to just forget what we've done and do it
6364 * all over again.
6365 */
6366 hpsa_undo_allocations_after_kdump_soft_reset(h);
6367 try_soft_reset = 0;
6368 if (rc)
6369 /* don't go to clean4, we already unallocated */
6370 return -ENODEV;
6371
6372 goto reinit_after_soft_reset;
6373 }
edd16368 6374
da0697bd
ST		 6375 /* Enable Accelerated IO path at driver layer */
6376 h->acciopath_status = 1;
6377
e863d68e
ST		 6378 h->drv_req_rescan = 0;
6379
edd16368
SC		 6380 /* Turn the interrupts on so we can service requests */
6381 h->access.set_intr_mask(h, HPSA_INTR_ON);
6382
339b2b14 6383 hpsa_hba_inquiry(h);
edd16368 6384 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6385
6386 /* Monitor the controller for firmware lockups */
6387 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6388 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6389 schedule_delayed_work(&h->monitor_ctlr_work,
6390 h->heartbeat_sample_interval);
88bf6d62 6391 return 0;
edd16368
SC		 6392
6393clean4:
33a2ffce 6394 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6395 hpsa_free_cmd_pool(h);
254f796b 6396 free_irqs(h);
edd16368
SC		 6397clean2:
6398clean1:
edd16368 6399 kfree(h);
ecd9aad4 6400 return rc;
edd16368
SC		 6401}
6402
6403static void hpsa_flush_cache(struct ctlr_info *h)
6404{
6405 char *flush_buf;
6406 struct CommandList *c;
702890e3
SC		 6407 unsigned long flags;
6408
6409 /* Don't bother trying to flush the cache if locked up */
6410 spin_lock_irqsave(&h->lock, flags);
6411 if (unlikely(h->lockup_detected)) {
6412 spin_unlock_irqrestore(&h->lock, flags);
6413 return;
6414 }
6415 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6416
6417 flush_buf = kzalloc(4, GFP_KERNEL);
6418 if (!flush_buf)
6419 return;
6420
6421 c = cmd_special_alloc(h);
6422 if (!c) {
6423 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6424 goto out_of_memory;
6425 }
a2dac136
SC		 6426 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6427 RAID_CTLR_LUNID, TYPE_CMD)) {
6428 goto out;
6429 }
edd16368
SC		 6430 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6431 if (c->err_info->CommandStatus != 0)
a2dac136 6432out:
edd16368
SC		 6433 dev_warn(&h->pdev->dev,
6434 "error flushing cache on controller\n");
6435 cmd_special_free(h, c);
6436out_of_memory:
6437 kfree(flush_buf);
6438}
6439
6440static void hpsa_shutdown(struct pci_dev *pdev)
6441{
6442 struct ctlr_info *h;
6443
6444 h = pci_get_drvdata(pdev);
6445 /* Turn board interrupts off and send the flush cache command
6446 * sendcmd will turn off interrupt, and send the flush...
6447 * To write all data in the battery backed cache to disks
6448 */
6449 hpsa_flush_cache(h);
6450 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6451 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6452}
6453
6f039790 6454static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6455{
6456 int i;
6457
6458 for (i = 0; i < h->ndevices; i++)
6459 kfree(h->dev[i]);
6460}
6461
6f039790 6462static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6463{
6464 struct ctlr_info *h;
8a98db73 6465 unsigned long flags;
edd16368
SC		 6466
6467 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6468 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6469 return;
6470 }
6471 h = pci_get_drvdata(pdev);
8a98db73
SC		 6472
6473 /* Get rid of any controller monitoring work items */
6474 spin_lock_irqsave(&h->lock, flags);
6475 h->remove_in_progress = 1;
6476 cancel_delayed_work(&h->monitor_ctlr_work);
6477 spin_unlock_irqrestore(&h->lock, flags);
6478
edd16368
SC		 6479 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6480 hpsa_shutdown(pdev);
6481 iounmap(h->vaddr);
204892e9
SC		 6482 iounmap(h->transtable);
6483 iounmap(h->cfgtable);
55e14e76 6484 hpsa_free_device_info(h);
33a2ffce 6485 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6486 pci_free_consistent(h->pdev,
6487 h->nr_cmds * sizeof(struct CommandList),
6488 h->cmd_pool, h->cmd_pool_dhandle);
6489 pci_free_consistent(h->pdev,
6490 h->nr_cmds * sizeof(struct ErrorInfo),
6491 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6492 pci_free_consistent(h->pdev, h->reply_pool_size,
6493 h->reply_pool, h->reply_pool_dhandle);
edd16368 6494 kfree(h->cmd_pool_bits);
303932fd 6495 kfree(h->blockFetchTable);
e1f7de0c 6496 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6497 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6498 kfree(h->hba_inquiry_data);
f0bd0b68 6499 pci_disable_device(pdev);
edd16368 6500 pci_release_regions(pdev);
edd16368
SC		 6501 kfree(h);
6502}
6503
6504static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6505 __attribute__((unused)) pm_message_t state)
6506{
6507 return -ENOSYS;
6508}
6509
6510static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6511{
6512 return -ENOSYS;
6513}
6514
6515static struct pci_driver hpsa_pci_driver = {
f79cfec6 6516 .name = HPSA,
edd16368 6517 .probe = hpsa_init_one,
6f039790 6518 .remove = hpsa_remove_one,
edd16368
SC		 6519 .id_table = hpsa_pci_device_id, /* id_table */
6520 .shutdown = hpsa_shutdown,
6521 .suspend = hpsa_suspend,
6522 .resume = hpsa_resume,
6523};
6524
303932fd
DB		 6525/* Fill in bucket_map[], given nsgs (the max number of
6526 * scatter gather elements supported) and bucket[],
6527 * which is an array of 8 integers. The bucket[] array
6528 * contains 8 different DMA transfer sizes (in 16
6529 * byte increments) which the controller uses to fetch
6530 * commands. This function fills in bucket_map[], which
6531 * maps a given number of scatter gather elements to one of
6532 * the 8 DMA transfer sizes. The point of it is to allow the
6533 * controller to only do as much DMA as needed to fetch the
6534 * command, with the DMA transfer size encoded in the lower
6535 * bits of the command address.
6536 */
6537static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6538 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6539{
6540 int i, j, b, size;
6541
303932fd
DB		 6542 /* Note, bucket_map must have nsgs+1 entries. */
6543 for (i = 0; i <= nsgs; i++) {
6544 /* Compute size of a command with i SG entries */
e1f7de0c 6545 size = i + min_blocks;
303932fd
DB		 6546 b = num_buckets; /* Assume the biggest bucket */
6547 /* Find the bucket that is just big enough */
e1f7de0c 6548 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6549 if (bucket[j] >= size) {
6550 b = j;
6551 break;
6552 }
6553 }
6554 /* for a command with i SG entries, use bucket b. */
6555 bucket_map[i] = b;
6556 }
6557}
6558
e1f7de0c 6559static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6560{
6c311b57
SC		 6561 int i;
6562 unsigned long register_value;
e1f7de0c
MG		 6563 unsigned long transMethod = CFGTBL_Trans_Performant |
6564 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6565 CFGTBL_Trans_enable_directed_msix |
6566 (trans_support & (CFGTBL_Trans_io_accel1 |
6567 CFGTBL_Trans_io_accel2));
e1f7de0c 6568 struct access_method access = SA5_performant_access;
def342bd
SC		 6569
6570 /* This is a bit complicated. There are 8 registers on
6571 * the controller which we write to to tell it 8 different
6572 * sizes of commands which there may be. It's a way of
6573 * reducing the DMA done to fetch each command. Encoded into
6574 * each command's tag are 3 bits which communicate to the controller
6575 * which of the eight sizes that command fits within. The size of
6576 * each command depends on how many scatter gather entries there are.
6577 * Each SG entry requires 16 bytes. The eight registers are programmed
6578 * with the number of 16-byte blocks a command of that size requires.
6579 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6580 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6581 * blocks. Note, this only extends to the SG entries contained
6582 * within the command block, and does not extend to chained blocks
6583 * of SG elements. bft[] contains the eight values we write to
6584 * the registers. They are not evenly distributed, but have more
6585 * sizes for small commands, and fewer sizes for larger commands.
6586 */
d66ae08b 6587 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6588#define MIN_IOACCEL2_BFT_ENTRY 5
6589#define HPSA_IOACCEL2_HEADER_SZ 4
6590 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6591 13, 14, 15, 16, 17, 18, 19,
6592 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6593 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6594 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6595 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6596 16 * MIN_IOACCEL2_BFT_ENTRY);
6597 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6598 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6599 /* 5 = 1 s/g entry or 4k
6600 * 6 = 2 s/g entry or 8k
6601 * 8 = 4 s/g entry or 16k
6602 * 10 = 6 s/g entry or 24k
6603 */
303932fd 6604
303932fd
DB		 6605 /* Controller spec: zero out this buffer. */
6606 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6607
d66ae08b
SC		 6608 bft[7] = SG_ENTRIES_IN_CMD + 4;
6609 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6610 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6611 for (i = 0; i < 8; i++)
6612 writel(bft[i], &h->transtable->BlockFetch[i]);
6613
6614 /* size of controller ring buffer */
6615 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6616 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6617 writel(0, &h->transtable->RepQCtrAddrLow32);
6618 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6619
6620 for (i = 0; i < h->nreply_queues; i++) {
6621 writel(0, &h->transtable->RepQAddr[i].upper);
6622 writel(h->reply_pool_dhandle +
6623 (h->max_commands * sizeof(u64) * i),
6624 &h->transtable->RepQAddr[i].lower);
6625 }
6626
b9af4937 6627 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6628 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6629 /*
6630 * enable outbound interrupt coalescing in accelerator mode;
6631 */
6632 if (trans_support & CFGTBL_Trans_io_accel1) {
6633 access = SA5_ioaccel_mode1_access;
6634 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6635 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6636 } else {
6637 if (trans_support & CFGTBL_Trans_io_accel2) {
6638 access = SA5_ioaccel_mode2_access;
6639 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6640 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6641 }
e1f7de0c 6642 }
303932fd 6643 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6644 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6645 register_value = readl(&(h->cfgtable->TransportActive));
6646 if (!(register_value & CFGTBL_Trans_Performant)) {
6647 dev_warn(&h->pdev->dev, "unable to get board into"
6648 " performant mode\n");
6649 return;
6650 }
960a30e7 6651 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6652 h->access = access;
6653 h->transMethod = transMethod;
6654
b9af4937
SC		 6655 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6656 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6657 return;
6658
b9af4937
SC		 6659 if (trans_support & CFGTBL_Trans_io_accel1) {
6660 /* Set up I/O accelerator mode */
6661 for (i = 0; i < h->nreply_queues; i++) {
6662 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6663 h->reply_queue[i].current_entry =
6664 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6665 }
6666 bft[7] = h->ioaccel_maxsg + 8;
6667 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6668 h->ioaccel1_blockFetchTable);
e1f7de0c 6669
b9af4937
SC		 6670 /* initialize all reply queue entries to unused */
6671 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6672 h->reply_pool_size);
e1f7de0c 6673
b9af4937
SC		 6674 /* set all the constant fields in the accelerator command
6675 * frames once at init time to save CPU cycles later.
6676 */
6677 for (i = 0; i < h->nr_cmds; i++) {
6678 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6679
6680 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6681 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6682 (i * sizeof(struct ErrorInfo)));
6683 cp->err_info_len = sizeof(struct ErrorInfo);
6684 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6685 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6686 cp->timeout_sec = 0;
6687 cp->ReplyQueue = 0;
6688 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6689 DIRECT_LOOKUP_BIT;
6690 cp->Tag.upper = 0;
6691 cp->host_addr.lower =
6692 (u32) (h->ioaccel_cmd_pool_dhandle +
6693 (i * sizeof(struct io_accel1_cmd)));
6694 cp->host_addr.upper = 0;
6695 }
6696 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6697 u64 cfg_offset, cfg_base_addr_index;
6698 u32 bft2_offset, cfg_base_addr;
6699 int rc;
6700
6701 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6702 &cfg_base_addr_index, &cfg_offset);
6703 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6704 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6705 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6706 4, h->ioaccel2_blockFetchTable);
6707 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6708 BUILD_BUG_ON(offsetof(struct CfgTable,
6709 io_accel_request_size_offset) != 0xb8);
6710 h->ioaccel2_bft2_regs =
6711 remap_pci_mem(pci_resource_start(h->pdev,
6712 cfg_base_addr_index) +
6713 cfg_offset + bft2_offset,
6714 ARRAY_SIZE(bft2) *
6715 sizeof(*h->ioaccel2_bft2_regs));
6716 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6717 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6718 }
b9af4937
SC		 6719 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6720 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6721}
6722
6723static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6724{
283b4a9b
SC		 6725 h->ioaccel_maxsg =
6726 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6727 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6728 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6729
e1f7de0c
MG		 6730 /* Command structures must be aligned on a 128-byte boundary
6731 * because the 7 lower bits of the address are used by the
6732 * hardware.
6733 */
6734#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6735 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6736 IOACCEL1_COMMANDLIST_ALIGNMENT);
6737 h->ioaccel_cmd_pool =
6738 pci_alloc_consistent(h->pdev,
6739 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6740 &(h->ioaccel_cmd_pool_dhandle));
6741
6742 h->ioaccel1_blockFetchTable =
283b4a9b 6743 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6744 sizeof(u32)), GFP_KERNEL);
6745
6746 if ((h->ioaccel_cmd_pool == NULL) ||
6747 (h->ioaccel1_blockFetchTable == NULL))
6748 goto clean_up;
6749
6750 memset(h->ioaccel_cmd_pool, 0,
6751 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6752 return 0;
6753
6754clean_up:
6755 if (h->ioaccel_cmd_pool)
6756 pci_free_consistent(h->pdev,
6757 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6758 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6759 kfree(h->ioaccel1_blockFetchTable);
6760 return 1;
6c311b57
SC		 6761}
6762
aca9012a
SC		 6763static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6764{
6765 /* Allocate ioaccel2 mode command blocks and block fetch table */
6766
6767 h->ioaccel_maxsg =
6768 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6769 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6770 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6771
6772#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6773 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6774 IOACCEL2_COMMANDLIST_ALIGNMENT);
6775 h->ioaccel2_cmd_pool =
6776 pci_alloc_consistent(h->pdev,
6777 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6778 &(h->ioaccel2_cmd_pool_dhandle));
6779
6780 h->ioaccel2_blockFetchTable =
6781 kmalloc(((h->ioaccel_maxsg + 1) *
6782 sizeof(u32)), GFP_KERNEL);
6783
6784 if ((h->ioaccel2_cmd_pool == NULL) ||
6785 (h->ioaccel2_blockFetchTable == NULL))
6786 goto clean_up;
6787
6788 memset(h->ioaccel2_cmd_pool, 0,
6789 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
6790 return 0;
6791
6792clean_up:
6793 if (h->ioaccel2_cmd_pool)
6794 pci_free_consistent(h->pdev,
6795 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6796 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
6797 kfree(h->ioaccel2_blockFetchTable);
6798 return 1;
6799}
6800
6f039790 6801static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 6802{
6803 u32 trans_support;
e1f7de0c
MG		 6804 unsigned long transMethod = CFGTBL_Trans_Performant |
6805 CFGTBL_Trans_use_short_tags;
254f796b 6806 int i;
6c311b57 6807
02ec19c8
SC		 6808 if (hpsa_simple_mode)
6809 return;
6810
e1f7de0c
MG		 6811 /* Check for I/O accelerator mode support */
6812 if (trans_support & CFGTBL_Trans_io_accel1) {
6813 transMethod |= CFGTBL_Trans_io_accel1 |
6814 CFGTBL_Trans_enable_directed_msix;
6815 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
6816 goto clean_up;
aca9012a
SC		 6817 } else {
6818 if (trans_support & CFGTBL_Trans_io_accel2) {
6819 transMethod |= CFGTBL_Trans_io_accel2 |
6820 CFGTBL_Trans_enable_directed_msix;
6821 if (ioaccel2_alloc_cmds_and_bft(h))
6822 goto clean_up;
6823 }
e1f7de0c
MG		 6824 }
6825
6826 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 6827 trans_support = readl(&(h->cfgtable->TransportSupport));
6828 if (!(trans_support & PERFORMANT_MODE))
6829 return;
6830
eee0f03a 6831 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 6832 hpsa_get_max_perf_mode_cmds(h);
6c311b57 6833 /* Performant mode ring buffer and supporting data structures */
254f796b 6834 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 6835 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
6836 &(h->reply_pool_dhandle));
6837
254f796b
MG		 6838 for (i = 0; i < h->nreply_queues; i++) {
6839 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
6840 h->reply_queue[i].size = h->max_commands;
6841 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
6842 h->reply_queue[i].current_entry = 0;
6843 }
6844
6c311b57 6845 /* Need a block fetch table for performant mode */
d66ae08b 6846 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 6847 sizeof(u32)), GFP_KERNEL);
6848
6849 if ((h->reply_pool == NULL)
6850 || (h->blockFetchTable == NULL))
6851 goto clean_up;
6852
e1f7de0c 6853 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 6854 return;
6855
6856clean_up:
6857 if (h->reply_pool)
6858 pci_free_consistent(h->pdev, h->reply_pool_size,
6859 h->reply_pool, h->reply_pool_dhandle);
6860 kfree(h->blockFetchTable);
6861}
6862
76438d08
SC		 6863static void hpsa_drain_commands(struct ctlr_info *h)
6864{
6865 int cmds_out;
6866 unsigned long flags;
6867
6868 do { /* wait for all outstanding commands to drain out */
6869 spin_lock_irqsave(&h->lock, flags);
6870 cmds_out = h->commands_outstanding;
6871 spin_unlock_irqrestore(&h->lock, flags);
6872 if (cmds_out <= 0)
6873 break;
6874 msleep(100);
6875 } while (1);
6876}
6877
edd16368
SC		 6878/*
6879 * This is it. Register the PCI driver information for the cards we control
6880 * the OS will call our registered routines when it finds one of our cards.
6881 */
6882static int __init hpsa_init(void)
6883{
31468401 6884 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 6885}
6886
6887static void __exit hpsa_cleanup(void)
6888{
6889 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 6890}
6891
e1f7de0c
MG		 6892static void __attribute__((unused)) verify_offsets(void)
6893{
b66cc250
MM		 6894#define VERIFY_OFFSET(member, offset) \
6895 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
6896
6897 VERIFY_OFFSET(IU_type, 0);
6898 VERIFY_OFFSET(direction, 1);
6899 VERIFY_OFFSET(reply_queue, 2);
6900 /* VERIFY_OFFSET(reserved1, 3); */
6901 VERIFY_OFFSET(scsi_nexus, 4);
6902 VERIFY_OFFSET(Tag, 8);
6903 VERIFY_OFFSET(cdb, 16);
6904 VERIFY_OFFSET(cciss_lun, 32);
6905 VERIFY_OFFSET(data_len, 40);
6906 VERIFY_OFFSET(cmd_priority_task_attr, 44);
6907 VERIFY_OFFSET(sg_count, 45);
6908 /* VERIFY_OFFSET(reserved3 */
6909 VERIFY_OFFSET(err_ptr, 48);
6910 VERIFY_OFFSET(err_len, 56);
6911 /* VERIFY_OFFSET(reserved4 */
6912 VERIFY_OFFSET(sg, 64);
6913
6914#undef VERIFY_OFFSET
6915
e1f7de0c
MG		 6916#define VERIFY_OFFSET(member, offset) \
6917 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
6918
6919 VERIFY_OFFSET(dev_handle, 0x00);
6920 VERIFY_OFFSET(reserved1, 0x02);
6921 VERIFY_OFFSET(function, 0x03);
6922 VERIFY_OFFSET(reserved2, 0x04);
6923 VERIFY_OFFSET(err_info, 0x0C);
6924 VERIFY_OFFSET(reserved3, 0x10);
6925 VERIFY_OFFSET(err_info_len, 0x12);
6926 VERIFY_OFFSET(reserved4, 0x13);
6927 VERIFY_OFFSET(sgl_offset, 0x14);
6928 VERIFY_OFFSET(reserved5, 0x15);
6929 VERIFY_OFFSET(transfer_len, 0x1C);
6930 VERIFY_OFFSET(reserved6, 0x20);
6931 VERIFY_OFFSET(io_flags, 0x24);
6932 VERIFY_OFFSET(reserved7, 0x26);
6933 VERIFY_OFFSET(LUN, 0x34);
6934 VERIFY_OFFSET(control, 0x3C);
6935 VERIFY_OFFSET(CDB, 0x40);
6936 VERIFY_OFFSET(reserved8, 0x50);
6937 VERIFY_OFFSET(host_context_flags, 0x60);
6938 VERIFY_OFFSET(timeout_sec, 0x62);
6939 VERIFY_OFFSET(ReplyQueue, 0x64);
6940 VERIFY_OFFSET(reserved9, 0x65);
6941 VERIFY_OFFSET(Tag, 0x68);
6942 VERIFY_OFFSET(host_addr, 0x70);
6943 VERIFY_OFFSET(CISS_LUN, 0x78);
6944 VERIFY_OFFSET(SG, 0x78 + 8);
6945#undef VERIFY_OFFSET
6946}
6947
edd16368
SC		 6948module_init(hpsa_init);
6949module_exit(hpsa_cleanup);
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