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hpsa: add function is_logical_device
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
1358f6dc
DB		 3 * Copyright 2014-2015 PMC-Sierra, Inc.
4 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
13 * NON INFRINGEMENT. See the GNU General Public License for more details.
14 *
1358f6dc 15 * Questions/Comments/Bugfixes to storagedev@pmcs.com
edd16368
SC		 16 *
17 */
18
19#include <linux/module.h>
20#include <linux/interrupt.h>
21#include <linux/types.h>
22#include <linux/pci.h>
e5a44df8 23#include <linux/pci-aspm.h>
edd16368
SC		 24#include <linux/kernel.h>
25#include <linux/slab.h>
26#include <linux/delay.h>
27#include <linux/fs.h>
28#include <linux/timer.h>
edd16368
SC		 29#include <linux/init.h>
30#include <linux/spinlock.h>
edd16368
SC		 31#include <linux/compat.h>
32#include <linux/blktrace_api.h>
33#include <linux/uaccess.h>
34#include <linux/io.h>
35#include <linux/dma-mapping.h>
36#include <linux/completion.h>
37#include <linux/moduleparam.h>
38#include <scsi/scsi.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
667e23d4 42#include <scsi/scsi_tcq.h>
9437ac43 43#include <scsi/scsi_eh.h>
73153fe5 44#include <scsi/scsi_dbg.h>
edd16368
SC		 45#include <linux/cciss_ioctl.h>
46#include <linux/string.h>
47#include <linux/bitmap.h>
60063497 48#include <linux/atomic.h>
a0c12413 49#include <linux/jiffies.h>
42a91641 50#include <linux/percpu-defs.h>
094963da 51#include <linux/percpu.h>
2b08b3e9 52#include <asm/unaligned.h>
283b4a9b 53#include <asm/div64.h>
edd16368
SC		 54#include "hpsa_cmd.h"
55#include "hpsa.h"
56
57/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
f532a3f9 58#define HPSA_DRIVER_VERSION "3.4.10-0"
edd16368 59#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 60#define HPSA "hpsa"
edd16368 61
007e7aa9
RE		 62/* How long to wait for CISS doorbell communication */
63#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
64#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
65#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
66#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 67#define MAX_IOCTL_CONFIG_WAIT 1000
68
69/*define how many times we will try a command because of bus resets */
70#define MAX_CMD_RETRIES 3
71
72/* Embedded module documentation macros - see modules.h */
73MODULE_AUTHOR("Hewlett-Packard Company");
74MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
75 HPSA_DRIVER_VERSION);
76MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
77MODULE_VERSION(HPSA_DRIVER_VERSION);
78MODULE_LICENSE("GPL");
79
80static int hpsa_allow_any;
81module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_allow_any,
83 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 84static int hpsa_simple_mode;
85module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
86MODULE_PARM_DESC(hpsa_simple_mode,
87 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 88
89/* define the PCI info for the cards we can control */
90static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
fe0c9610
MM		 110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 131 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 132 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
133 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
134 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 137 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
138 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
139 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
140 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
141 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 142 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 143 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 144 {0,}
145};
146
147MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
148
149/* board_id = Subsystem Device ID & Vendor ID
150 * product = Marketing Name for the board
151 * access = Address of the struct of function pointers
152 */
153static struct board_type products[] = {
edd16368
SC		 154 {0x3241103C, "Smart Array P212", &SA5_access},
155 {0x3243103C, "Smart Array P410", &SA5_access},
156 {0x3245103C, "Smart Array P410i", &SA5_access},
157 {0x3247103C, "Smart Array P411", &SA5_access},
158 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 159 {0x324A103C, "Smart Array P712m", &SA5_access},
160 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 161 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 162 {0x3350103C, "Smart Array P222", &SA5_access},
163 {0x3351103C, "Smart Array P420", &SA5_access},
164 {0x3352103C, "Smart Array P421", &SA5_access},
165 {0x3353103C, "Smart Array P822", &SA5_access},
166 {0x3354103C, "Smart Array P420i", &SA5_access},
167 {0x3355103C, "Smart Array P220i", &SA5_access},
168 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 169 {0x1921103C, "Smart Array P830i", &SA5_access},
170 {0x1922103C, "Smart Array P430", &SA5_access},
171 {0x1923103C, "Smart Array P431", &SA5_access},
172 {0x1924103C, "Smart Array P830", &SA5_access},
173 {0x1926103C, "Smart Array P731m", &SA5_access},
174 {0x1928103C, "Smart Array P230i", &SA5_access},
175 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 176 {0x21BD103C, "Smart Array P244br", &SA5_access},
177 {0x21BE103C, "Smart Array P741m", &SA5_access},
178 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
179 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 180 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 181 {0x21C2103C, "Smart Array P440", &SA5_access},
182 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 183 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 184 {0x21C5103C, "Smart Array P841", &SA5_access},
185 {0x21C6103C, "Smart HBA H244br", &SA5_access},
186 {0x21C7103C, "Smart HBA H240", &SA5_access},
187 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 188 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 189 {0x21CA103C, "Smart Array P246br", &SA5_access},
190 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 191 {0x21CC103C, "Smart Array", &SA5_access},
192 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 193 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 194 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 195 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
196 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
197 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
198 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
199 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 200 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
201 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
202 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
203 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
204 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 205 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
206};
207
a58e7e53
WS		 208#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
209static const struct scsi_cmnd hpsa_cmd_busy;
210#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
211static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 212static int number_of_controllers;
213
10f66018
SC		 214static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
215static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
42a91641 216static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
edd16368
SC		 217
218#ifdef CONFIG_COMPAT
42a91641
DB		 219static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
220 void __user *arg);
edd16368
SC		 221#endif
222
223static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 224static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 225static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
226static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
227 struct scsi_cmnd *scmd);
a2dac136 228static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 229 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 230 int cmd_type);
2c143342 231static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 232#define VPD_PAGE (1 << 8)
b48d9804 233#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 234
f281233d 235static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 236static void hpsa_scan_start(struct Scsi_Host *);
237static int hpsa_scan_finished(struct Scsi_Host *sh,
238 unsigned long elapsed_time);
7c0a0229 239static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 240
241static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 242static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368 243static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 244static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 245static void hpsa_slave_destroy(struct scsi_device *sdev);
246
8aa60681 247static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 248static int check_for_unit_attention(struct ctlr_info *h,
249 struct CommandList *c);
250static void check_ioctl_unit_attention(struct ctlr_info *h,
251 struct CommandList *c);
303932fd
DB		 252/* performant mode helper functions */
253static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 254 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 255static void hpsa_free_performant_mode(struct ctlr_info *h);
256static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 257static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 258static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
259 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
260 u64 *cfg_offset);
261static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
262 unsigned long *memory_bar);
263static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
264static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
265 int wait_for_ready);
75167d2c 266static inline void finish_cmd(struct CommandList *c);
c706a795 267static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 268#define BOARD_NOT_READY 0
269#define BOARD_READY 1
23100dd9 270static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 271static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 272static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
273 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 274 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 275static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 276static u32 lockup_detected(struct ctlr_info *h);
277static int detect_controller_lockup(struct ctlr_info *h);
8270b862 278static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device);
edd16368 279
edd16368
SC		 280static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
281{
282 unsigned long *priv = shost_priv(sdev->host);
283 return (struct ctlr_info *) *priv;
284}
285
a23513e8
SC		 286static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
287{
288 unsigned long *priv = shost_priv(sh);
289 return (struct ctlr_info *) *priv;
290}
291
a58e7e53
WS		 292static inline bool hpsa_is_cmd_idle(struct CommandList *c)
293{
294 return c->scsi_cmd == SCSI_CMD_IDLE;
295}
296
d604f533
WS		 297static inline bool hpsa_is_pending_event(struct CommandList *c)
298{
299 return c->abort_pending || c->reset_pending;
300}
301
9437ac43
SC		 302/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
303static void decode_sense_data(const u8 *sense_data, int sense_data_len,
304 u8 *sense_key, u8 *asc, u8 *ascq)
305{
306 struct scsi_sense_hdr sshdr;
307 bool rc;
308
309 *sense_key = -1;
310 *asc = -1;
311 *ascq = -1;
312
313 if (sense_data_len < 1)
314 return;
315
316 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
317 if (rc) {
318 *sense_key = sshdr.sense_key;
319 *asc = sshdr.asc;
320 *ascq = sshdr.ascq;
321 }
322}
323
edd16368
SC		 324static int check_for_unit_attention(struct ctlr_info *h,
325 struct CommandList *c)
326{
9437ac43
SC		 327 u8 sense_key, asc, ascq;
328 int sense_len;
329
330 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
331 sense_len = sizeof(c->err_info->SenseInfo);
332 else
333 sense_len = c->err_info->SenseLen;
334
335 decode_sense_data(c->err_info->SenseInfo, sense_len,
336 &sense_key, &asc, &ascq);
81c27557 337 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 338 return 0;
339
9437ac43 340 switch (asc) {
edd16368 341 case STATE_CHANGED:
9437ac43 342 dev_warn(&h->pdev->dev,
2946e82b
RE		 343 "%s: a state change detected, command retried\n",
344 h->devname);
edd16368
SC		 345 break;
346 case LUN_FAILED:
7f73695a 347 dev_warn(&h->pdev->dev,
2946e82b 348 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 349 break;
350 case REPORT_LUNS_CHANGED:
7f73695a 351 dev_warn(&h->pdev->dev,
2946e82b 352 "%s: report LUN data changed\n", h->devname);
edd16368 353 /*
4f4eb9f1
ST		 354 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
355 * target (array) devices.
edd16368
SC		 356 */
357 break;
358 case POWER_OR_RESET:
2946e82b
RE		 359 dev_warn(&h->pdev->dev,
360 "%s: a power on or device reset detected\n",
361 h->devname);
edd16368
SC		 362 break;
363 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 364 dev_warn(&h->pdev->dev,
365 "%s: unit attention cleared by another initiator\n",
366 h->devname);
edd16368
SC		 367 break;
368 default:
2946e82b
RE		 369 dev_warn(&h->pdev->dev,
370 "%s: unknown unit attention detected\n",
371 h->devname);
edd16368
SC		 372 break;
373 }
374 return 1;
375}
376
852af20a
MB		 377static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
378{
379 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
380 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
381 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
382 return 0;
383 dev_warn(&h->pdev->dev, HPSA "device busy");
384 return 1;
385}
386
e985c58f
SC		 387static u32 lockup_detected(struct ctlr_info *h);
388static ssize_t host_show_lockup_detected(struct device *dev,
389 struct device_attribute *attr, char *buf)
390{
391 int ld;
392 struct ctlr_info *h;
393 struct Scsi_Host *shost = class_to_shost(dev);
394
395 h = shost_to_hba(shost);
396 ld = lockup_detected(h);
397
398 return sprintf(buf, "ld=%d\n", ld);
399}
400
da0697bd
ST		 401static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
402 struct device_attribute *attr,
403 const char *buf, size_t count)
404{
405 int status, len;
406 struct ctlr_info *h;
407 struct Scsi_Host *shost = class_to_shost(dev);
408 char tmpbuf[10];
409
410 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
411 return -EACCES;
412 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
413 strncpy(tmpbuf, buf, len);
414 tmpbuf[len] = '\0';
415 if (sscanf(tmpbuf, "%d", &status) != 1)
416 return -EINVAL;
417 h = shost_to_hba(shost);
418 h->acciopath_status = !!status;
419 dev_warn(&h->pdev->dev,
420 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
421 h->acciopath_status ? "enabled" : "disabled");
422 return count;
423}
424
2ba8bfc8
SC		 425static ssize_t host_store_raid_offload_debug(struct device *dev,
426 struct device_attribute *attr,
427 const char *buf, size_t count)
428{
429 int debug_level, len;
430 struct ctlr_info *h;
431 struct Scsi_Host *shost = class_to_shost(dev);
432 char tmpbuf[10];
433
434 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
435 return -EACCES;
436 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
437 strncpy(tmpbuf, buf, len);
438 tmpbuf[len] = '\0';
439 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
440 return -EINVAL;
441 if (debug_level < 0)
442 debug_level = 0;
443 h = shost_to_hba(shost);
444 h->raid_offload_debug = debug_level;
445 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
446 h->raid_offload_debug);
447 return count;
448}
449
edd16368
SC		 450static ssize_t host_store_rescan(struct device *dev,
451 struct device_attribute *attr,
452 const char *buf, size_t count)
453{
454 struct ctlr_info *h;
455 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 456 h = shost_to_hba(shost);
31468401 457 hpsa_scan_start(h->scsi_host);
edd16368
SC		 458 return count;
459}
460
d28ce020
SC		 461static ssize_t host_show_firmware_revision(struct device *dev,
462 struct device_attribute *attr, char *buf)
463{
464 struct ctlr_info *h;
465 struct Scsi_Host *shost = class_to_shost(dev);
466 unsigned char *fwrev;
467
468 h = shost_to_hba(shost);
469 if (!h->hba_inquiry_data)
470 return 0;
471 fwrev = &h->hba_inquiry_data[32];
472 return snprintf(buf, 20, "%c%c%c%c\n",
473 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
474}
475
94a13649
SC		 476static ssize_t host_show_commands_outstanding(struct device *dev,
477 struct device_attribute *attr, char *buf)
478{
479 struct Scsi_Host *shost = class_to_shost(dev);
480 struct ctlr_info *h = shost_to_hba(shost);
481
0cbf768e
SC		 482 return snprintf(buf, 20, "%d\n",
483 atomic_read(&h->commands_outstanding));
94a13649
SC		 484}
485
745a7a25
SC		 486static ssize_t host_show_transport_mode(struct device *dev,
487 struct device_attribute *attr, char *buf)
488{
489 struct ctlr_info *h;
490 struct Scsi_Host *shost = class_to_shost(dev);
491
492 h = shost_to_hba(shost);
493 return snprintf(buf, 20, "%s\n",
960a30e7 494 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 495 "performant" : "simple");
496}
497
da0697bd
ST		 498static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
499 struct device_attribute *attr, char *buf)
500{
501 struct ctlr_info *h;
502 struct Scsi_Host *shost = class_to_shost(dev);
503
504 h = shost_to_hba(shost);
505 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
506 (h->acciopath_status == 1) ? "enabled" : "disabled");
507}
508
46380786 509/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 510static u32 unresettable_controller[] = {
511 0x324a103C, /* Smart Array P712m */
9b5c48c2 512 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 513 0x3223103C, /* Smart Array P800 */
514 0x3234103C, /* Smart Array P400 */
515 0x3235103C, /* Smart Array P400i */
516 0x3211103C, /* Smart Array E200i */
517 0x3212103C, /* Smart Array E200 */
518 0x3213103C, /* Smart Array E200i */
519 0x3214103C, /* Smart Array E200i */
520 0x3215103C, /* Smart Array E200i */
521 0x3237103C, /* Smart Array E500 */
522 0x323D103C, /* Smart Array P700m */
7af0abbc 523 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 524 0x409C0E11, /* Smart Array 6400 */
525 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 526 0x40700E11, /* Smart Array 5300 */
527 0x40820E11, /* Smart Array 532 */
528 0x40830E11, /* Smart Array 5312 */
529 0x409A0E11, /* Smart Array 641 */
530 0x409B0E11, /* Smart Array 642 */
531 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 532};
533
46380786
SC		 534/* List of controllers which cannot even be soft reset */
535static u32 soft_unresettable_controller[] = {
7af0abbc 536 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 537 0x40700E11, /* Smart Array 5300 */
538 0x40820E11, /* Smart Array 532 */
539 0x40830E11, /* Smart Array 5312 */
540 0x409A0E11, /* Smart Array 641 */
541 0x409B0E11, /* Smart Array 642 */
542 0x40910E11, /* Smart Array 6i */
46380786
SC		 543 /* Exclude 640x boards. These are two pci devices in one slot
544 * which share a battery backed cache module. One controls the
545 * cache, the other accesses the cache through the one that controls
546 * it. If we reset the one controlling the cache, the other will
547 * likely not be happy. Just forbid resetting this conjoined mess.
548 * The 640x isn't really supported by hpsa anyway.
549 */
550 0x409C0E11, /* Smart Array 6400 */
551 0x409D0E11, /* Smart Array 6400 EM */
552};
553
9b5c48c2
SC		 554static u32 needs_abort_tags_swizzled[] = {
555 0x323D103C, /* Smart Array P700m */
556 0x324a103C, /* Smart Array P712m */
557 0x324b103C, /* SmartArray P711m */
558};
559
560static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 561{
562 int i;
563
9b5c48c2
SC		 564 for (i = 0; i < nelems; i++)
565 if (a[i] == board_id)
566 return 1;
567 return 0;
46380786
SC		 568}
569
9b5c48c2 570static int ctlr_is_hard_resettable(u32 board_id)
46380786 571{
9b5c48c2
SC		 572 return !board_id_in_array(unresettable_controller,
573 ARRAY_SIZE(unresettable_controller), board_id);
574}
46380786 575
9b5c48c2
SC		 576static int ctlr_is_soft_resettable(u32 board_id)
577{
578 return !board_id_in_array(soft_unresettable_controller,
579 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 580}
581
46380786
SC		 582static int ctlr_is_resettable(u32 board_id)
583{
584 return ctlr_is_hard_resettable(board_id) ||
585 ctlr_is_soft_resettable(board_id);
586}
587
9b5c48c2
SC		 588static int ctlr_needs_abort_tags_swizzled(u32 board_id)
589{
590 return board_id_in_array(needs_abort_tags_swizzled,
591 ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
592}
593
941b1cda
SC		 594static ssize_t host_show_resettable(struct device *dev,
595 struct device_attribute *attr, char *buf)
596{
597 struct ctlr_info *h;
598 struct Scsi_Host *shost = class_to_shost(dev);
599
600 h = shost_to_hba(shost);
46380786 601 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 602}
603
edd16368
SC		 604static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
605{
606 return (scsi3addr[3] & 0xC0) == 0x40;
607}
608
f2ef0ce7
RE		 609static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
610 "1(+0)ADM", "UNKNOWN"
edd16368 611};
6b80b18f
ST		 612#define HPSA_RAID_0 0
613#define HPSA_RAID_4 1
614#define HPSA_RAID_1 2 /* also used for RAID 10 */
615#define HPSA_RAID_5 3 /* also used for RAID 50 */
616#define HPSA_RAID_51 4
617#define HPSA_RAID_6 5 /* also used for RAID 60 */
618#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 619#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
620
f3f01730
KB		 621static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
622{
623 return !device->physical_device;
624}
625
edd16368
SC		 626static ssize_t raid_level_show(struct device *dev,
627 struct device_attribute *attr, char *buf)
628{
629 ssize_t l = 0;
82a72c0a 630 unsigned char rlevel;
edd16368
SC		 631 struct ctlr_info *h;
632 struct scsi_device *sdev;
633 struct hpsa_scsi_dev_t *hdev;
634 unsigned long flags;
635
636 sdev = to_scsi_device(dev);
637 h = sdev_to_hba(sdev);
638 spin_lock_irqsave(&h->lock, flags);
639 hdev = sdev->hostdata;
640 if (!hdev) {
641 spin_unlock_irqrestore(&h->lock, flags);
642 return -ENODEV;
643 }
644
645 /* Is this even a logical drive? */
f3f01730 646 if (!is_logical_device(hdev)) {
edd16368
SC		 647 spin_unlock_irqrestore(&h->lock, flags);
648 l = snprintf(buf, PAGE_SIZE, "N/A\n");
649 return l;
650 }
651
652 rlevel = hdev->raid_level;
653 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 654 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 655 rlevel = RAID_UNKNOWN;
656 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
657 return l;
658}
659
660static ssize_t lunid_show(struct device *dev,
661 struct device_attribute *attr, char *buf)
662{
663 struct ctlr_info *h;
664 struct scsi_device *sdev;
665 struct hpsa_scsi_dev_t *hdev;
666 unsigned long flags;
667 unsigned char lunid[8];
668
669 sdev = to_scsi_device(dev);
670 h = sdev_to_hba(sdev);
671 spin_lock_irqsave(&h->lock, flags);
672 hdev = sdev->hostdata;
673 if (!hdev) {
674 spin_unlock_irqrestore(&h->lock, flags);
675 return -ENODEV;
676 }
677 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
678 spin_unlock_irqrestore(&h->lock, flags);
679 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
680 lunid[0], lunid[1], lunid[2], lunid[3],
681 lunid[4], lunid[5], lunid[6], lunid[7]);
682}
683
684static ssize_t unique_id_show(struct device *dev,
685 struct device_attribute *attr, char *buf)
686{
687 struct ctlr_info *h;
688 struct scsi_device *sdev;
689 struct hpsa_scsi_dev_t *hdev;
690 unsigned long flags;
691 unsigned char sn[16];
692
693 sdev = to_scsi_device(dev);
694 h = sdev_to_hba(sdev);
695 spin_lock_irqsave(&h->lock, flags);
696 hdev = sdev->hostdata;
697 if (!hdev) {
698 spin_unlock_irqrestore(&h->lock, flags);
699 return -ENODEV;
700 }
701 memcpy(sn, hdev->device_id, sizeof(sn));
702 spin_unlock_irqrestore(&h->lock, flags);
703 return snprintf(buf, 16 * 2 + 2,
704 "%02X%02X%02X%02X%02X%02X%02X%02X"
705 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
706 sn[0], sn[1], sn[2], sn[3],
707 sn[4], sn[5], sn[6], sn[7],
708 sn[8], sn[9], sn[10], sn[11],
709 sn[12], sn[13], sn[14], sn[15]);
710}
711
c1988684
ST		 712static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
713 struct device_attribute *attr, char *buf)
714{
715 struct ctlr_info *h;
716 struct scsi_device *sdev;
717 struct hpsa_scsi_dev_t *hdev;
718 unsigned long flags;
719 int offload_enabled;
720
721 sdev = to_scsi_device(dev);
722 h = sdev_to_hba(sdev);
723 spin_lock_irqsave(&h->lock, flags);
724 hdev = sdev->hostdata;
725 if (!hdev) {
726 spin_unlock_irqrestore(&h->lock, flags);
727 return -ENODEV;
728 }
729 offload_enabled = hdev->offload_enabled;
730 spin_unlock_irqrestore(&h->lock, flags);
731 return snprintf(buf, 20, "%d\n", offload_enabled);
732}
733
8270b862
JH		 734#define MAX_PATHS 8
735#define PATH_STRING_LEN 50
736
737static ssize_t path_info_show(struct device *dev,
738 struct device_attribute *attr, char *buf)
739{
740 struct ctlr_info *h;
741 struct scsi_device *sdev;
742 struct hpsa_scsi_dev_t *hdev;
743 unsigned long flags;
744 int i;
745 int output_len = 0;
746 u8 box;
747 u8 bay;
748 u8 path_map_index = 0;
749 char *active;
750 unsigned char phys_connector[2];
751 unsigned char path[MAX_PATHS][PATH_STRING_LEN];
752
753 memset(path, 0, MAX_PATHS * PATH_STRING_LEN);
754 sdev = to_scsi_device(dev);
755 h = sdev_to_hba(sdev);
756 spin_lock_irqsave(&h->devlock, flags);
757 hdev = sdev->hostdata;
758 if (!hdev) {
759 spin_unlock_irqrestore(&h->devlock, flags);
760 return -ENODEV;
761 }
762
763 bay = hdev->bay;
764 for (i = 0; i < MAX_PATHS; i++) {
765 path_map_index = 1<<i;
766 if (i == hdev->active_path_index)
767 active = "Active";
768 else if (hdev->path_map & path_map_index)
769 active = "Inactive";
770 else
771 continue;
772
773 output_len = snprintf(path[i],
774 PATH_STRING_LEN, "[%d:%d:%d:%d] %20.20s ",
775 h->scsi_host->host_no,
776 hdev->bus, hdev->target, hdev->lun,
777 scsi_device_type(hdev->devtype));
778
779 if (is_ext_target(h, hdev) ||
f3f01730
KB		 780 hdev->devtype == TYPE_RAID ||
781 is_logical_device(hdev)) {
8270b862
JH		 782 output_len += snprintf(path[i] + output_len,
783 PATH_STRING_LEN, "%s\n",
784 active);
785 continue;
786 }
787
788 box = hdev->box[i];
789 memcpy(&phys_connector, &hdev->phys_connector[i],
790 sizeof(phys_connector));
791 if (phys_connector[0] < '0')
792 phys_connector[0] = '0';
793 if (phys_connector[1] < '0')
794 phys_connector[1] = '0';
795 if (hdev->phys_connector[i] > 0)
796 output_len += snprintf(path[i] + output_len,
797 PATH_STRING_LEN,
798 "PORT: %.2s ",
799 phys_connector);
2a168208 800 if (hdev->devtype == TYPE_DISK && hdev->expose_device) {
8270b862
JH		 801 if (box == 0 || box == 0xFF) {
802 output_len += snprintf(path[i] + output_len,
803 PATH_STRING_LEN,
804 "BAY: %hhu %s\n",
805 bay, active);
806 } else {
807 output_len += snprintf(path[i] + output_len,
808 PATH_STRING_LEN,
809 "BOX: %hhu BAY: %hhu %s\n",
810 box, bay, active);
811 }
812 } else if (box != 0 && box != 0xFF) {
813 output_len += snprintf(path[i] + output_len,
814 PATH_STRING_LEN, "BOX: %hhu %s\n",
815 box, active);
816 } else
817 output_len += snprintf(path[i] + output_len,
818 PATH_STRING_LEN, "%s\n", active);
819 }
820
821 spin_unlock_irqrestore(&h->devlock, flags);
822 return snprintf(buf, output_len+1, "%s%s%s%s%s%s%s%s",
823 path[0], path[1], path[2], path[3],
824 path[4], path[5], path[6], path[7]);
825}
826
3f5eac3a
SC		 827static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
828static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
829static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
830static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 831static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
832 host_show_hp_ssd_smart_path_enabled, NULL);
8270b862 833static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
da0697bd
ST		 834static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
835 host_show_hp_ssd_smart_path_status,
836 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 837static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
838 host_store_raid_offload_debug);
3f5eac3a
SC		 839static DEVICE_ATTR(firmware_revision, S_IRUGO,
840 host_show_firmware_revision, NULL);
841static DEVICE_ATTR(commands_outstanding, S_IRUGO,
842 host_show_commands_outstanding, NULL);
843static DEVICE_ATTR(transport_mode, S_IRUGO,
844 host_show_transport_mode, NULL);
941b1cda
SC		 845static DEVICE_ATTR(resettable, S_IRUGO,
846 host_show_resettable, NULL);
e985c58f
SC		 847static DEVICE_ATTR(lockup_detected, S_IRUGO,
848 host_show_lockup_detected, NULL);
3f5eac3a
SC		 849
850static struct device_attribute *hpsa_sdev_attrs[] = {
851 &dev_attr_raid_level,
852 &dev_attr_lunid,
853 &dev_attr_unique_id,
c1988684 854 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 855 &dev_attr_path_info,
e985c58f 856 &dev_attr_lockup_detected,
3f5eac3a
SC		 857 NULL,
858};
859
860static struct device_attribute *hpsa_shost_attrs[] = {
861 &dev_attr_rescan,
862 &dev_attr_firmware_revision,
863 &dev_attr_commands_outstanding,
864 &dev_attr_transport_mode,
941b1cda 865 &dev_attr_resettable,
da0697bd 866 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 867 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 868 NULL,
869};
870
41ce4c35
SC		 871#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
872 HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
873
3f5eac3a
SC		 874static struct scsi_host_template hpsa_driver_template = {
875 .module = THIS_MODULE,
f79cfec6
SC		 876 .name = HPSA,
877 .proc_name = HPSA,
3f5eac3a
SC		 878 .queuecommand = hpsa_scsi_queue_command,
879 .scan_start = hpsa_scan_start,
880 .scan_finished = hpsa_scan_finished,
7c0a0229 881 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a
SC		 882 .this_id = -1,
883 .use_clustering = ENABLE_CLUSTERING,
75167d2c 884 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 885 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
886 .ioctl = hpsa_ioctl,
887 .slave_alloc = hpsa_slave_alloc,
41ce4c35 888 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 889 .slave_destroy = hpsa_slave_destroy,
890#ifdef CONFIG_COMPAT
891 .compat_ioctl = hpsa_compat_ioctl,
892#endif
893 .sdev_attrs = hpsa_sdev_attrs,
894 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 895 .max_sectors = 8192,
54b2b50c 896 .no_write_same = 1,
3f5eac3a
SC		 897};
898
254f796b 899static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 900{
901 u32 a;
072b0518 902 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 903
e1f7de0c
MG		 904 if (h->transMethod & CFGTBL_Trans_io_accel1)
905 return h->access.command_completed(h, q);
906
3f5eac3a 907 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 908 return h->access.command_completed(h, q);
3f5eac3a 909
254f796b
MG		 910 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
911 a = rq->head[rq->current_entry];
912 rq->current_entry++;
0cbf768e 913 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 914 } else {
915 a = FIFO_EMPTY;
916 }
917 /* Check for wraparound */
254f796b
MG		 918 if (rq->current_entry == h->max_commands) {
919 rq->current_entry = 0;
920 rq->wraparound ^= 1;
3f5eac3a
SC		 921 }
922 return a;
923}
924
c349775e
ST		 925/*
926 * There are some special bits in the bus address of the
927 * command that we have to set for the controller to know
928 * how to process the command:
929 *
930 * Normal performant mode:
931 * bit 0: 1 means performant mode, 0 means simple mode.
932 * bits 1-3 = block fetch table entry
933 * bits 4-6 = command type (== 0)
934 *
935 * ioaccel1 mode:
936 * bit 0 = "performant mode" bit.
937 * bits 1-3 = block fetch table entry
938 * bits 4-6 = command type (== 110)
939 * (command type is needed because ioaccel1 mode
940 * commands are submitted through the same register as normal
941 * mode commands, so this is how the controller knows whether
942 * the command is normal mode or ioaccel1 mode.)
943 *
944 * ioaccel2 mode:
945 * bit 0 = "performant mode" bit.
946 * bits 1-4 = block fetch table entry (note extra bit)
947 * bits 4-6 = not needed, because ioaccel2 mode has
948 * a separate special register for submitting commands.
949 */
950
25163bd5
WS		 951/*
952 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 953 * set bit 0 for pull model, bits 3-1 for block fetch
954 * register number
955 */
25163bd5
WS		 956#define DEFAULT_REPLY_QUEUE (-1)
957static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
958 int reply_queue)
3f5eac3a 959{
254f796b 960 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 961 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
25163bd5
WS		 962 if (unlikely(!h->msix_vector))
963 return;
964 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
254f796b 965 c->Header.ReplyQueue =
804a5cb5 966 raw_smp_processor_id() % h->nreply_queues;
25163bd5
WS		 967 else
968 c->Header.ReplyQueue = reply_queue % h->nreply_queues;
254f796b 969 }
3f5eac3a
SC		 970}
971
c349775e 972static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 973 struct CommandList *c,
974 int reply_queue)
c349775e
ST		 975{
976 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
977
25163bd5
WS		 978 /*
979 * Tell the controller to post the reply to the queue for this
c349775e
ST		 980 * processor. This seems to give the best I/O throughput.
981 */
25163bd5
WS		 982 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
983 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
984 else
985 cp->ReplyQueue = reply_queue % h->nreply_queues;
986 /*
987 * Set the bits in the address sent down to include:
c349775e
ST		 988 * - performant mode bit (bit 0)
989 * - pull count (bits 1-3)
990 * - command type (bits 4-6)
991 */
992 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
993 IOACCEL1_BUSADDR_CMDTYPE;
994}
995
8be986cc
SC		 996static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
997 struct CommandList *c,
998 int reply_queue)
999{
1000 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1001 &h->ioaccel2_cmd_pool[c->cmdindex];
1002
1003 /* Tell the controller to post the reply to the queue for this
1004 * processor. This seems to give the best I/O throughput.
1005 */
1006 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1007 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1008 else
1009 cp->reply_queue = reply_queue % h->nreply_queues;
1010 /* Set the bits in the address sent down to include:
1011 * - performant mode bit not used in ioaccel mode 2
1012 * - pull count (bits 0-3)
1013 * - command type isn't needed for ioaccel2
1014 */
1015 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1016}
1017
c349775e 1018static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1019 struct CommandList *c,
1020 int reply_queue)
c349775e
ST		 1021{
1022 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1023
25163bd5
WS		 1024 /*
1025 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1026 * processor. This seems to give the best I/O throughput.
1027 */
25163bd5
WS		 1028 if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
1029 cp->reply_queue = smp_processor_id() % h->nreply_queues;
1030 else
1031 cp->reply_queue = reply_queue % h->nreply_queues;
1032 /*
1033 * Set the bits in the address sent down to include:
c349775e
ST		 1034 * - performant mode bit not used in ioaccel mode 2
1035 * - pull count (bits 0-3)
1036 * - command type isn't needed for ioaccel2
1037 */
1038 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1039}
1040
e85c5974
SC		 1041static int is_firmware_flash_cmd(u8 *cdb)
1042{
1043 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1044}
1045
1046/*
1047 * During firmware flash, the heartbeat register may not update as frequently
1048 * as it should. So we dial down lockup detection during firmware flash. and
1049 * dial it back up when firmware flash completes.
1050 */
1051#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1052#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
1053static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1054 struct CommandList *c)
1055{
1056 if (!is_firmware_flash_cmd(c->Request.CDB))
1057 return;
1058 atomic_inc(&h->firmware_flash_in_progress);
1059 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1060}
1061
1062static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1063 struct CommandList *c)
1064{
1065 if (is_firmware_flash_cmd(c->Request.CDB) &&
1066 atomic_dec_and_test(&h->firmware_flash_in_progress))
1067 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1068}
1069
25163bd5
WS		 1070static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1071 struct CommandList *c, int reply_queue)
3f5eac3a 1072{
c05e8866
SC		 1073 dial_down_lockup_detection_during_fw_flash(h, c);
1074 atomic_inc(&h->commands_outstanding);
c349775e
ST		 1075 switch (c->cmd_type) {
1076 case CMD_IOACCEL1:
25163bd5 1077 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1078 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1079 break;
1080 case CMD_IOACCEL2:
25163bd5 1081 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1082 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1083 break;
8be986cc
SC		 1084 case IOACCEL2_TMF:
1085 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1086 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1087 break;
c349775e 1088 default:
25163bd5 1089 set_performant_mode(h, c, reply_queue);
c05e8866 1090 h->access.submit_command(h, c);
c349775e 1091 }
3f5eac3a
SC		 1092}
1093
a58e7e53 1094static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1095{
d604f533 1096 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1097 return finish_cmd(c);
1098
25163bd5
WS		 1099 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1100}
1101
3f5eac3a
SC		 1102static inline int is_hba_lunid(unsigned char scsi3addr[])
1103{
1104 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1105}
1106
1107static inline int is_scsi_rev_5(struct ctlr_info *h)
1108{
1109 if (!h->hba_inquiry_data)
1110 return 0;
1111 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1112 return 1;
1113 return 0;
1114}
1115
edd16368
SC		 1116static int hpsa_find_target_lun(struct ctlr_info *h,
1117 unsigned char scsi3addr[], int bus, int *target, int *lun)
1118{
1119 /* finds an unused bus, target, lun for a new physical device
1120 * assumes h->devlock is held
1121 */
1122 int i, found = 0;
cfe5badc 1123 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1124
263d9401 1125 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1126
1127 for (i = 0; i < h->ndevices; i++) {
1128 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1129 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1130 }
1131
263d9401
AM		 1132 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1133 if (i < HPSA_MAX_DEVICES) {
1134 /* *bus = 1; */
1135 *target = i;
1136 *lun = 0;
1137 found = 1;
edd16368
SC		 1138 }
1139 return !found;
1140}
1141
1d33d85d 1142static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1143 struct hpsa_scsi_dev_t *dev, char *description)
1144{
9975ec9d
DB		 1145 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1146 return;
1147
0d96ef5f
WS		 1148 dev_printk(level, &h->pdev->dev,
1149 "scsi %d:%d:%d:%d: %s %s %.8s %.16s RAID-%s SSDSmartPathCap%c En%c Exp=%d\n",
1150 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1151 description,
1152 scsi_device_type(dev->devtype),
1153 dev->vendor,
1154 dev->model,
1155 dev->raid_level > RAID_UNKNOWN ?
1156 "RAID-?" : raid_label[dev->raid_level],
1157 dev->offload_config ? '+' : '-',
1158 dev->offload_enabled ? '+' : '-',
2a168208 1159 dev->expose_device);
0d96ef5f
WS		 1160}
1161
edd16368 1162/* Add an entry into h->dev[] array. */
8aa60681 1163static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1164 struct hpsa_scsi_dev_t *device,
1165 struct hpsa_scsi_dev_t *added[], int *nadded)
1166{
1167 /* assumes h->devlock is held */
1168 int n = h->ndevices;
1169 int i;
1170 unsigned char addr1[8], addr2[8];
1171 struct hpsa_scsi_dev_t *sd;
1172
cfe5badc 1173 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1174 dev_err(&h->pdev->dev, "too many devices, some will be "
1175 "inaccessible.\n");
1176 return -1;
1177 }
1178
1179 /* physical devices do not have lun or target assigned until now. */
1180 if (device->lun != -1)
1181 /* Logical device, lun is already assigned. */
1182 goto lun_assigned;
1183
1184 /* If this device a non-zero lun of a multi-lun device
1185 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1186 * unit no, zero otherwise.
edd16368
SC		 1187 */
1188 if (device->scsi3addr[4] == 0) {
1189 /* This is not a non-zero lun of a multi-lun device */
1190 if (hpsa_find_target_lun(h, device->scsi3addr,
1191 device->bus, &device->target, &device->lun) != 0)
1192 return -1;
1193 goto lun_assigned;
1194 }
1195
1196 /* This is a non-zero lun of a multi-lun device.
1197 * Search through our list and find the device which
9a4178b7 1198 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1199 * Assign the same bus and target for this new LUN.
1200 * Use the logical unit number from the firmware.
1201 */
1202 memcpy(addr1, device->scsi3addr, 8);
1203 addr1[4] = 0;
9a4178b7 1204 addr1[5] = 0;
edd16368
SC		 1205 for (i = 0; i < n; i++) {
1206 sd = h->dev[i];
1207 memcpy(addr2, sd->scsi3addr, 8);
1208 addr2[4] = 0;
9a4178b7 1209 addr2[5] = 0;
1210 /* differ only in byte 4 and 5? */
edd16368
SC		 1211 if (memcmp(addr1, addr2, 8) == 0) {
1212 device->bus = sd->bus;
1213 device->target = sd->target;
1214 device->lun = device->scsi3addr[4];
1215 break;
1216 }
1217 }
1218 if (device->lun == -1) {
1219 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1220 " suspect firmware bug or unsupported hardware "
1221 "configuration.\n");
1222 return -1;
1223 }
1224
1225lun_assigned:
1226
1227 h->dev[n] = device;
1228 h->ndevices++;
1229 added[*nadded] = device;
1230 (*nadded)++;
0d96ef5f 1231 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1232 device->expose_device ? "added" : "masked");
a473d86c
RE		 1233 device->offload_to_be_enabled = device->offload_enabled;
1234 device->offload_enabled = 0;
edd16368
SC		 1235 return 0;
1236}
1237
bd9244f7 1238/* Update an entry in h->dev[] array. */
8aa60681 1239static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1240 int entry, struct hpsa_scsi_dev_t *new_entry)
1241{
a473d86c 1242 int offload_enabled;
bd9244f7
ST		 1243 /* assumes h->devlock is held */
1244 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1245
1246 /* Raid level changed. */
1247 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1248
03383736
DB		 1249 /* Raid offload parameters changed. Careful about the ordering. */
1250 if (new_entry->offload_config && new_entry->offload_enabled) {
1251 /*
1252 * if drive is newly offload_enabled, we want to copy the
1253 * raid map data first. If previously offload_enabled and
1254 * offload_config were set, raid map data had better be
1255 * the same as it was before. if raid map data is changed
1256 * then it had better be the case that
1257 * h->dev[entry]->offload_enabled is currently 0.
1258 */
1259 h->dev[entry]->raid_map = new_entry->raid_map;
1260 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1261 }
a3144e0b
JH		 1262 if (new_entry->hba_ioaccel_enabled) {
1263 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1264 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1265 }
1266 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1267 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1268 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1269 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1270
41ce4c35
SC		 1271 /*
1272 * We can turn off ioaccel offload now, but need to delay turning
1273 * it on until we can update h->dev[entry]->phys_disk[], but we
1274 * can't do that until all the devices are updated.
1275 */
1276 h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
1277 if (!new_entry->offload_enabled)
1278 h->dev[entry]->offload_enabled = 0;
1279
a473d86c
RE		 1280 offload_enabled = h->dev[entry]->offload_enabled;
1281 h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
0d96ef5f 1282 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
a473d86c 1283 h->dev[entry]->offload_enabled = offload_enabled;
bd9244f7
ST		 1284}
1285
2a8ccf31 1286/* Replace an entry from h->dev[] array. */
8aa60681 1287static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1288 int entry, struct hpsa_scsi_dev_t *new_entry,
1289 struct hpsa_scsi_dev_t *added[], int *nadded,
1290 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1291{
1292 /* assumes h->devlock is held */
cfe5badc 1293 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1294 removed[*nremoved] = h->dev[entry];
1295 (*nremoved)++;
01350d05
SC		 1296
1297 /*
1298 * New physical devices won't have target/lun assigned yet
1299 * so we need to preserve the values in the slot we are replacing.
1300 */
1301 if (new_entry->target == -1) {
1302 new_entry->target = h->dev[entry]->target;
1303 new_entry->lun = h->dev[entry]->lun;
1304 }
1305
2a8ccf31
SC		 1306 h->dev[entry] = new_entry;
1307 added[*nadded] = new_entry;
1308 (*nadded)++;
0d96ef5f 1309 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
a473d86c
RE		 1310 new_entry->offload_to_be_enabled = new_entry->offload_enabled;
1311 new_entry->offload_enabled = 0;
2a8ccf31
SC		 1312}
1313
edd16368 1314/* Remove an entry from h->dev[] array. */
8aa60681 1315static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1316 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1317{
1318 /* assumes h->devlock is held */
1319 int i;
1320 struct hpsa_scsi_dev_t *sd;
1321
cfe5badc 1322 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1323
1324 sd = h->dev[entry];
1325 removed[*nremoved] = h->dev[entry];
1326 (*nremoved)++;
1327
1328 for (i = entry; i < h->ndevices-1; i++)
1329 h->dev[i] = h->dev[i+1];
1330 h->ndevices--;
0d96ef5f 1331 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1332}
1333
1334#define SCSI3ADDR_EQ(a, b) ( \
1335 (a)[7] == (b)[7] && \
1336 (a)[6] == (b)[6] && \
1337 (a)[5] == (b)[5] && \
1338 (a)[4] == (b)[4] && \
1339 (a)[3] == (b)[3] && \
1340 (a)[2] == (b)[2] && \
1341 (a)[1] == (b)[1] && \
1342 (a)[0] == (b)[0])
1343
1344static void fixup_botched_add(struct ctlr_info *h,
1345 struct hpsa_scsi_dev_t *added)
1346{
1347 /* called when scsi_add_device fails in order to re-adjust
1348 * h->dev[] to match the mid layer's view.
1349 */
1350 unsigned long flags;
1351 int i, j;
1352
1353 spin_lock_irqsave(&h->lock, flags);
1354 for (i = 0; i < h->ndevices; i++) {
1355 if (h->dev[i] == added) {
1356 for (j = i; j < h->ndevices-1; j++)
1357 h->dev[j] = h->dev[j+1];
1358 h->ndevices--;
1359 break;
1360 }
1361 }
1362 spin_unlock_irqrestore(&h->lock, flags);
1363 kfree(added);
1364}
1365
1366static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1367 struct hpsa_scsi_dev_t *dev2)
1368{
edd16368
SC		 1369 /* we compare everything except lun and target as these
1370 * are not yet assigned. Compare parts likely
1371 * to differ first
1372 */
1373 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1374 sizeof(dev1->scsi3addr)) != 0)
1375 return 0;
1376 if (memcmp(dev1->device_id, dev2->device_id,
1377 sizeof(dev1->device_id)) != 0)
1378 return 0;
1379 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1380 return 0;
1381 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1382 return 0;
edd16368
SC		 1383 if (dev1->devtype != dev2->devtype)
1384 return 0;
edd16368
SC		 1385 if (dev1->bus != dev2->bus)
1386 return 0;
1387 return 1;
1388}
1389
bd9244f7
ST		 1390static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1391 struct hpsa_scsi_dev_t *dev2)
1392{
1393 /* Device attributes that can change, but don't mean
1394 * that the device is a different device, nor that the OS
1395 * needs to be told anything about the change.
1396 */
1397 if (dev1->raid_level != dev2->raid_level)
1398 return 1;
250fb125
SC		 1399 if (dev1->offload_config != dev2->offload_config)
1400 return 1;
1401 if (dev1->offload_enabled != dev2->offload_enabled)
1402 return 1;
93849508
DB		 1403 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1404 if (dev1->queue_depth != dev2->queue_depth)
1405 return 1;
bd9244f7
ST		 1406 return 0;
1407}
1408
edd16368
SC		 1409/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1410 * and return needle location in *index. If scsi3addr matches, but not
1411 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1412 * location in *index.
1413 * In the case of a minor device attribute change, such as RAID level, just
1414 * return DEVICE_UPDATED, along with the updated device's location in index.
1415 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1416 */
1417static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1418 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1419 int *index)
1420{
1421 int i;
1422#define DEVICE_NOT_FOUND 0
1423#define DEVICE_CHANGED 1
1424#define DEVICE_SAME 2
bd9244f7 1425#define DEVICE_UPDATED 3
1d33d85d
DB		 1426 if (needle == NULL)
1427 return DEVICE_NOT_FOUND;
1428
edd16368 1429 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1430 if (haystack[i] == NULL) /* previously removed. */
1431 continue;
edd16368
SC		 1432 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1433 *index = i;
bd9244f7
ST		 1434 if (device_is_the_same(needle, haystack[i])) {
1435 if (device_updated(needle, haystack[i]))
1436 return DEVICE_UPDATED;
edd16368 1437 return DEVICE_SAME;
bd9244f7 1438 } else {
9846590e
SC		 1439 /* Keep offline devices offline */
1440 if (needle->volume_offline)
1441 return DEVICE_NOT_FOUND;
edd16368 1442 return DEVICE_CHANGED;
bd9244f7 1443 }
edd16368
SC		 1444 }
1445 }
1446 *index = -1;
1447 return DEVICE_NOT_FOUND;
1448}
1449
9846590e
SC		 1450static void hpsa_monitor_offline_device(struct ctlr_info *h,
1451 unsigned char scsi3addr[])
1452{
1453 struct offline_device_entry *device;
1454 unsigned long flags;
1455
1456 /* Check to see if device is already on the list */
1457 spin_lock_irqsave(&h->offline_device_lock, flags);
1458 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1459 if (memcmp(device->scsi3addr, scsi3addr,
1460 sizeof(device->scsi3addr)) == 0) {
1461 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1462 return;
1463 }
1464 }
1465 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1466
1467 /* Device is not on the list, add it. */
1468 device = kmalloc(sizeof(*device), GFP_KERNEL);
1469 if (!device) {
1470 dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
1471 return;
1472 }
1473 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1474 spin_lock_irqsave(&h->offline_device_lock, flags);
1475 list_add_tail(&device->offline_list, &h->offline_device_list);
1476 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1477}
1478
1479/* Print a message explaining various offline volume states */
1480static void hpsa_show_volume_status(struct ctlr_info *h,
1481 struct hpsa_scsi_dev_t *sd)
1482{
1483 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1484 dev_info(&h->pdev->dev,
1485 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1486 h->scsi_host->host_no,
1487 sd->bus, sd->target, sd->lun);
1488 switch (sd->volume_offline) {
1489 case HPSA_LV_OK:
1490 break;
1491 case HPSA_LV_UNDERGOING_ERASE:
1492 dev_info(&h->pdev->dev,
1493 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1494 h->scsi_host->host_no,
1495 sd->bus, sd->target, sd->lun);
1496 break;
5ca01204
SB		 1497 case HPSA_LV_NOT_AVAILABLE:
1498 dev_info(&h->pdev->dev,
1499 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1500 h->scsi_host->host_no,
1501 sd->bus, sd->target, sd->lun);
1502 break;
9846590e
SC		 1503 case HPSA_LV_UNDERGOING_RPI:
1504 dev_info(&h->pdev->dev,
5ca01204 1505 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1506 h->scsi_host->host_no,
1507 sd->bus, sd->target, sd->lun);
1508 break;
1509 case HPSA_LV_PENDING_RPI:
1510 dev_info(&h->pdev->dev,
5ca01204
SB		 1511 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1512 h->scsi_host->host_no,
1513 sd->bus, sd->target, sd->lun);
9846590e
SC		 1514 break;
1515 case HPSA_LV_ENCRYPTED_NO_KEY:
1516 dev_info(&h->pdev->dev,
1517 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1518 h->scsi_host->host_no,
1519 sd->bus, sd->target, sd->lun);
1520 break;
1521 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1522 dev_info(&h->pdev->dev,
1523 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1524 h->scsi_host->host_no,
1525 sd->bus, sd->target, sd->lun);
1526 break;
1527 case HPSA_LV_UNDERGOING_ENCRYPTION:
1528 dev_info(&h->pdev->dev,
1529 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1530 h->scsi_host->host_no,
1531 sd->bus, sd->target, sd->lun);
1532 break;
1533 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1534 dev_info(&h->pdev->dev,
1535 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1536 h->scsi_host->host_no,
1537 sd->bus, sd->target, sd->lun);
1538 break;
1539 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1540 dev_info(&h->pdev->dev,
1541 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1542 h->scsi_host->host_no,
1543 sd->bus, sd->target, sd->lun);
1544 break;
1545 case HPSA_LV_PENDING_ENCRYPTION:
1546 dev_info(&h->pdev->dev,
1547 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1548 h->scsi_host->host_no,
1549 sd->bus, sd->target, sd->lun);
1550 break;
1551 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1552 dev_info(&h->pdev->dev,
1553 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1554 h->scsi_host->host_no,
1555 sd->bus, sd->target, sd->lun);
1556 break;
1557 }
1558}
1559
03383736
DB		 1560/*
1561 * Figure the list of physical drive pointers for a logical drive with
1562 * raid offload configured.
1563 */
1564static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1565 struct hpsa_scsi_dev_t *dev[], int ndevices,
1566 struct hpsa_scsi_dev_t *logical_drive)
1567{
1568 struct raid_map_data *map = &logical_drive->raid_map;
1569 struct raid_map_disk_data *dd = &map->data[0];
1570 int i, j;
1571 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1572 le16_to_cpu(map->metadata_disks_per_row);
1573 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1574 le16_to_cpu(map->layout_map_count) *
1575 total_disks_per_row;
1576 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1577 total_disks_per_row;
1578 int qdepth;
1579
1580 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1581 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1582
d604f533
WS		 1583 logical_drive->nphysical_disks = nraid_map_entries;
1584
03383736
DB		 1585 qdepth = 0;
1586 for (i = 0; i < nraid_map_entries; i++) {
1587 logical_drive->phys_disk[i] = NULL;
1588 if (!logical_drive->offload_config)
1589 continue;
1590 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1591 if (dev[j] == NULL)
1592 continue;
03383736
DB		 1593 if (dev[j]->devtype != TYPE_DISK)
1594 continue;
f3f01730 1595 if (is_logical_device(dev[j]))
03383736
DB		 1596 continue;
1597 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1598 continue;
1599
1600 logical_drive->phys_disk[i] = dev[j];
1601 if (i < nphys_disk)
1602 qdepth = min(h->nr_cmds, qdepth +
1603 logical_drive->phys_disk[i]->queue_depth);
1604 break;
1605 }
1606
1607 /*
1608 * This can happen if a physical drive is removed and
1609 * the logical drive is degraded. In that case, the RAID
1610 * map data will refer to a physical disk which isn't actually
1611 * present. And in that case offload_enabled should already
1612 * be 0, but we'll turn it off here just in case
1613 */
1614 if (!logical_drive->phys_disk[i]) {
1615 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1616 logical_drive->offload_to_be_enabled = 0;
1617 logical_drive->queue_depth = 8;
03383736
DB		 1618 }
1619 }
1620 if (nraid_map_entries)
1621 /*
1622 * This is correct for reads, too high for full stripe writes,
1623 * way too high for partial stripe writes
1624 */
1625 logical_drive->queue_depth = qdepth;
1626 else
1627 logical_drive->queue_depth = h->nr_cmds;
1628}
1629
1630static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1631 struct hpsa_scsi_dev_t *dev[], int ndevices)
1632{
1633 int i;
1634
1635 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1636 if (dev[i] == NULL)
1637 continue;
03383736
DB		 1638 if (dev[i]->devtype != TYPE_DISK)
1639 continue;
f3f01730 1640 if (!is_logical_device(dev[i]))
03383736 1641 continue;
41ce4c35
SC		 1642
1643 /*
1644 * If offload is currently enabled, the RAID map and
1645 * phys_disk[] assignment *better* not be changing
1646 * and since it isn't changing, we do not need to
1647 * update it.
1648 */
1649 if (dev[i]->offload_enabled)
1650 continue;
1651
03383736
DB		 1652 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
1653 }
1654}
1655
8aa60681 1656static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1657 struct hpsa_scsi_dev_t *sd[], int nsds)
1658{
1659 /* sd contains scsi3 addresses and devtypes, and inquiry
1660 * data. This function takes what's in sd to be the current
1661 * reality and updates h->dev[] to reflect that reality.
1662 */
1663 int i, entry, device_change, changes = 0;
1664 struct hpsa_scsi_dev_t *csd;
1665 unsigned long flags;
1666 struct hpsa_scsi_dev_t **added, **removed;
1667 int nadded, nremoved;
1668 struct Scsi_Host *sh = NULL;
1669
da03ded0
DB		 1670 /*
1671 * A reset can cause a device status to change
1672 * re-schedule the scan to see what happened.
1673 */
1674 if (h->reset_in_progress) {
1675 h->drv_req_rescan = 1;
1676 return;
1677 }
1678
cfe5badc
ST		 1679 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1680 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1681
1682 if (!added || !removed) {
1683 dev_warn(&h->pdev->dev, "out of memory in "
1684 "adjust_hpsa_scsi_table\n");
1685 goto free_and_out;
1686 }
1687
1688 spin_lock_irqsave(&h->devlock, flags);
1689
1690 /* find any devices in h->dev[] that are not in
1691 * sd[] and remove them from h->dev[], and for any
1692 * devices which have changed, remove the old device
1693 * info and add the new device info.
bd9244f7
ST		 1694 * If minor device attributes change, just update
1695 * the existing device structure.
edd16368
SC		 1696 */
1697 i = 0;
1698 nremoved = 0;
1699 nadded = 0;
1700 while (i < h->ndevices) {
1701 csd = h->dev[i];
1702 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1703 if (device_change == DEVICE_NOT_FOUND) {
1704 changes++;
8aa60681 1705 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1706 continue; /* remove ^^^, hence i not incremented */
1707 } else if (device_change == DEVICE_CHANGED) {
1708 changes++;
8aa60681 1709 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1710 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1711 /* Set it to NULL to prevent it from being freed
1712 * at the bottom of hpsa_update_scsi_devices()
1713 */
1714 sd[entry] = NULL;
bd9244f7 1715 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1716 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1717 }
1718 i++;
1719 }
1720
1721 /* Now, make sure every device listed in sd[] is also
1722 * listed in h->dev[], adding them if they aren't found
1723 */
1724
1725 for (i = 0; i < nsds; i++) {
1726 if (!sd[i]) /* if already added above. */
1727 continue;
9846590e
SC		 1728
1729 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1730 * as the SCSI mid-layer does not handle such devices well.
1731 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1732 * at 160Hz, and prevents the system from coming up.
1733 */
1734 if (sd[i]->volume_offline) {
1735 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1736 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1737 continue;
1738 }
1739
edd16368
SC		 1740 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1741 h->ndevices, &entry);
1742 if (device_change == DEVICE_NOT_FOUND) {
1743 changes++;
8aa60681 1744 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1745 break;
1746 sd[i] = NULL; /* prevent from being freed later. */
1747 } else if (device_change == DEVICE_CHANGED) {
1748 /* should never happen... */
1749 changes++;
1750 dev_warn(&h->pdev->dev,
1751 "device unexpectedly changed.\n");
1752 /* but if it does happen, we just ignore that device */
1753 }
1754 }
41ce4c35
SC		 1755 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
1756
1757 /* Now that h->dev[]->phys_disk[] is coherent, we can enable
1758 * any logical drives that need it enabled.
1759 */
1d33d85d
DB		 1760 for (i = 0; i < h->ndevices; i++) {
1761 if (h->dev[i] == NULL)
1762 continue;
41ce4c35 1763 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 1764 }
41ce4c35 1765
edd16368
SC		 1766 spin_unlock_irqrestore(&h->devlock, flags);
1767
9846590e
SC		 1768 /* Monitor devices which are in one of several NOT READY states to be
1769 * brought online later. This must be done without holding h->devlock,
1770 * so don't touch h->dev[]
1771 */
1772 for (i = 0; i < nsds; i++) {
1773 if (!sd[i]) /* if already added above. */
1774 continue;
1775 if (sd[i]->volume_offline)
1776 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
1777 }
1778
edd16368
SC		 1779 /* Don't notify scsi mid layer of any changes the first time through
1780 * (or if there are no changes) scsi_scan_host will do it later the
1781 * first time through.
1782 */
8aa60681 1783 if (!changes)
edd16368
SC		 1784 goto free_and_out;
1785
1786 sh = h->scsi_host;
da03ded0
DB		 1787 if (sh == NULL) {
1788 dev_warn(&h->pdev->dev, "%s: scsi_host is null\n", __func__);
1789 goto free_and_out;
1790 }
edd16368
SC		 1791 /* Notify scsi mid layer of any removed devices */
1792 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 1793 if (removed[i] == NULL)
1794 continue;
2a168208 1795 if (removed[i]->expose_device) {
41ce4c35
SC		 1796 struct scsi_device *sdev =
1797 scsi_device_lookup(sh, removed[i]->bus,
1798 removed[i]->target, removed[i]->lun);
1799 if (sdev != NULL) {
1800 scsi_remove_device(sdev);
1801 scsi_device_put(sdev);
1802 } else {
1803 /*
1804 * We don't expect to get here.
1805 * future cmds to this device will get selection
1806 * timeout as if the device was gone.
1807 */
0d96ef5f
WS		 1808 hpsa_show_dev_msg(KERN_WARNING, h, removed[i],
1809 "didn't find device for removal.");
41ce4c35 1810 }
edd16368
SC		 1811 }
1812 kfree(removed[i]);
1813 removed[i] = NULL;
1814 }
1815
1816 /* Notify scsi mid layer of any added devices */
1817 for (i = 0; i < nadded; i++) {
1d33d85d
DB		 1818 if (added[i] == NULL)
1819 continue;
2a168208 1820 if (!(added[i]->expose_device))
41ce4c35 1821 continue;
edd16368
SC		 1822 if (scsi_add_device(sh, added[i]->bus,
1823 added[i]->target, added[i]->lun) == 0)
1824 continue;
1d33d85d 1825 dev_warn(&h->pdev->dev, "addition failed, device not added.");
edd16368
SC		 1826 /* now we have to remove it from h->dev,
1827 * since it didn't get added to scsi mid layer
1828 */
1829 fixup_botched_add(h, added[i]);
853633e8 1830 h->drv_req_rescan = 1;
edd16368
SC		 1831 }
1832
1833free_and_out:
1834 kfree(added);
1835 kfree(removed);
edd16368
SC		 1836}
1837
1838/*
9e03aa2f 1839 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1840 * Assume's h->devlock is held.
1841 */
1842static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1843 int bus, int target, int lun)
1844{
1845 int i;
1846 struct hpsa_scsi_dev_t *sd;
1847
1848 for (i = 0; i < h->ndevices; i++) {
1849 sd = h->dev[i];
1850 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1851 return sd;
1852 }
1853 return NULL;
1854}
1855
edd16368
SC		 1856static int hpsa_slave_alloc(struct scsi_device *sdev)
1857{
1858 struct hpsa_scsi_dev_t *sd;
1859 unsigned long flags;
1860 struct ctlr_info *h;
1861
1862 h = sdev_to_hba(sdev);
1863 spin_lock_irqsave(&h->devlock, flags);
1864 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1865 sdev_id(sdev), sdev->lun);
41ce4c35 1866 if (likely(sd)) {
03383736 1867 atomic_set(&sd->ioaccel_cmds_out, 0);
2a168208 1868 sdev->hostdata = sd->expose_device ? sd : NULL;
41ce4c35
SC		 1869 } else
1870 sdev->hostdata = NULL;
edd16368
SC		 1871 spin_unlock_irqrestore(&h->devlock, flags);
1872 return 0;
1873}
1874
41ce4c35
SC		 1875/* configure scsi device based on internal per-device structure */
1876static int hpsa_slave_configure(struct scsi_device *sdev)
1877{
1878 struct hpsa_scsi_dev_t *sd;
1879 int queue_depth;
1880
1881 sd = sdev->hostdata;
2a168208 1882 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35
SC		 1883
1884 if (sd)
1885 queue_depth = sd->queue_depth != 0 ?
1886 sd->queue_depth : sdev->host->can_queue;
1887 else
1888 queue_depth = sdev->host->can_queue;
1889
1890 scsi_change_queue_depth(sdev, queue_depth);
1891
1892 return 0;
1893}
1894
edd16368
SC		 1895static void hpsa_slave_destroy(struct scsi_device *sdev)
1896{
bcc44255 1897 /* nothing to do. */
edd16368
SC		 1898}
1899
d9a729f3
WS		 1900static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1901{
1902 int i;
1903
1904 if (!h->ioaccel2_cmd_sg_list)
1905 return;
1906 for (i = 0; i < h->nr_cmds; i++) {
1907 kfree(h->ioaccel2_cmd_sg_list[i]);
1908 h->ioaccel2_cmd_sg_list[i] = NULL;
1909 }
1910 kfree(h->ioaccel2_cmd_sg_list);
1911 h->ioaccel2_cmd_sg_list = NULL;
1912}
1913
1914static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
1915{
1916 int i;
1917
1918 if (h->chainsize <= 0)
1919 return 0;
1920
1921 h->ioaccel2_cmd_sg_list =
1922 kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
1923 GFP_KERNEL);
1924 if (!h->ioaccel2_cmd_sg_list)
1925 return -ENOMEM;
1926 for (i = 0; i < h->nr_cmds; i++) {
1927 h->ioaccel2_cmd_sg_list[i] =
1928 kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
1929 h->maxsgentries, GFP_KERNEL);
1930 if (!h->ioaccel2_cmd_sg_list[i])
1931 goto clean;
1932 }
1933 return 0;
1934
1935clean:
1936 hpsa_free_ioaccel2_sg_chain_blocks(h);
1937 return -ENOMEM;
1938}
1939
33a2ffce
SC		 1940static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1941{
1942 int i;
1943
1944 if (!h->cmd_sg_list)
1945 return;
1946 for (i = 0; i < h->nr_cmds; i++) {
1947 kfree(h->cmd_sg_list[i]);
1948 h->cmd_sg_list[i] = NULL;
1949 }
1950 kfree(h->cmd_sg_list);
1951 h->cmd_sg_list = NULL;
1952}
1953
105a3dbc 1954static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 1955{
1956 int i;
1957
1958 if (h->chainsize <= 0)
1959 return 0;
1960
1961 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1962 GFP_KERNEL);
3d4e6af8
RE		 1963 if (!h->cmd_sg_list) {
1964 dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
33a2ffce 1965 return -ENOMEM;
3d4e6af8 1966 }
33a2ffce
SC		 1967 for (i = 0; i < h->nr_cmds; i++) {
1968 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1969 h->chainsize, GFP_KERNEL);
3d4e6af8
RE		 1970 if (!h->cmd_sg_list[i]) {
1971 dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
33a2ffce 1972 goto clean;
3d4e6af8 1973 }
33a2ffce
SC		 1974 }
1975 return 0;
1976
1977clean:
1978 hpsa_free_sg_chain_blocks(h);
1979 return -ENOMEM;
1980}
1981
d9a729f3
WS		 1982static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
1983 struct io_accel2_cmd *cp, struct CommandList *c)
1984{
1985 struct ioaccel2_sg_element *chain_block;
1986 u64 temp64;
1987 u32 chain_size;
1988
1989 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 1990 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 1991 temp64 = pci_map_single(h->pdev, chain_block, chain_size,
1992 PCI_DMA_TODEVICE);
1993 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1994 /* prevent subsequent unmapping */
1995 cp->sg->address = 0;
1996 return -1;
1997 }
1998 cp->sg->address = cpu_to_le64(temp64);
1999 return 0;
2000}
2001
2002static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2003 struct io_accel2_cmd *cp)
2004{
2005 struct ioaccel2_sg_element *chain_sg;
2006 u64 temp64;
2007 u32 chain_size;
2008
2009 chain_sg = cp->sg;
2010 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2011 chain_size = le32_to_cpu(cp->sg[0].length);
d9a729f3
WS		 2012 pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
2013}
2014
e2bea6df 2015static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2016 struct CommandList *c)
2017{
2018 struct SGDescriptor *chain_sg, *chain_block;
2019 u64 temp64;
50a0decf 2020 u32 chain_len;
33a2ffce
SC		 2021
2022 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2023 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2024 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2025 chain_len = sizeof(*chain_sg) *
2b08b3e9 2026 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf
SC		 2027 chain_sg->Len = cpu_to_le32(chain_len);
2028 temp64 = pci_map_single(h->pdev, chain_block, chain_len,
33a2ffce 2029 PCI_DMA_TODEVICE);
e2bea6df
SC		 2030 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2031 /* prevent subsequent unmapping */
50a0decf 2032 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2033 return -1;
2034 }
50a0decf 2035 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2036 return 0;
33a2ffce
SC		 2037}
2038
2039static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2040 struct CommandList *c)
2041{
2042 struct SGDescriptor *chain_sg;
33a2ffce 2043
50a0decf 2044 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2045 return;
2046
2047 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
50a0decf
SC		 2048 pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
2049 le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
33a2ffce
SC		 2050}
2051
a09c1441
ST		 2052
2053/* Decode the various types of errors on ioaccel2 path.
2054 * Return 1 for any error that should generate a RAID path retry.
2055 * Return 0 for errors that don't require a RAID path retry.
2056 */
2057static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2058 struct CommandList *c,
2059 struct scsi_cmnd *cmd,
2060 struct io_accel2_cmd *c2)
2061{
2062 int data_len;
a09c1441 2063 int retry = 0;
c40820d5 2064 u32 ioaccel2_resid = 0;
c349775e
ST		 2065
2066 switch (c2->error_data.serv_response) {
2067 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2068 switch (c2->error_data.status) {
2069 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2070 break;
2071 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2072 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2073 if (c2->error_data.data_present !=
ee6b1889
SC		 2074 IOACCEL2_SENSE_DATA_PRESENT) {
2075 memset(cmd->sense_buffer, 0,
2076 SCSI_SENSE_BUFFERSIZE);
c349775e 2077 break;
ee6b1889 2078 }
c349775e
ST		 2079 /* copy the sense data */
2080 data_len = c2->error_data.sense_data_len;
2081 if (data_len > SCSI_SENSE_BUFFERSIZE)
2082 data_len = SCSI_SENSE_BUFFERSIZE;
2083 if (data_len > sizeof(c2->error_data.sense_data_buff))
2084 data_len =
2085 sizeof(c2->error_data.sense_data_buff);
2086 memcpy(cmd->sense_buffer,
2087 c2->error_data.sense_data_buff, data_len);
a09c1441 2088 retry = 1;
c349775e
ST		 2089 break;
2090 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2091 retry = 1;
c349775e
ST		 2092 break;
2093 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2094 retry = 1;
c349775e
ST		 2095 break;
2096 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2097 retry = 1;
c349775e
ST		 2098 break;
2099 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2100 retry = 1;
c349775e
ST		 2101 break;
2102 default:
a09c1441 2103 retry = 1;
c349775e
ST		 2104 break;
2105 }
2106 break;
2107 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2108 switch (c2->error_data.status) {
2109 case IOACCEL2_STATUS_SR_IO_ERROR:
2110 case IOACCEL2_STATUS_SR_IO_ABORTED:
2111 case IOACCEL2_STATUS_SR_OVERRUN:
2112 retry = 1;
2113 break;
2114 case IOACCEL2_STATUS_SR_UNDERRUN:
2115 cmd->result = (DID_OK << 16); /* host byte */
2116 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2117 ioaccel2_resid = get_unaligned_le32(
2118 &c2->error_data.resid_cnt[0]);
2119 scsi_set_resid(cmd, ioaccel2_resid);
2120 break;
2121 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2122 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2123 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
2124 /* We will get an event from ctlr to trigger rescan */
2125 retry = 1;
2126 break;
2127 default:
2128 retry = 1;
c40820d5 2129 }
c349775e
ST		 2130 break;
2131 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2132 break;
2133 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2134 break;
2135 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2136 retry = 1;
c349775e
ST		 2137 break;
2138 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2139 break;
2140 default:
a09c1441 2141 retry = 1;
c349775e
ST		 2142 break;
2143 }
a09c1441
ST		 2144
2145 return retry; /* retry on raid path? */
c349775e
ST		 2146}
2147
a58e7e53
WS		 2148static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2149 struct CommandList *c)
2150{
d604f533
WS		 2151 bool do_wake = false;
2152
a58e7e53
WS		 2153 /*
2154 * Prevent the following race in the abort handler:
2155 *
2156 * 1. LLD is requested to abort a SCSI command
2157 * 2. The SCSI command completes
2158 * 3. The struct CommandList associated with step 2 is made available
2159 * 4. New I/O request to LLD to another LUN re-uses struct CommandList
2160 * 5. Abort handler follows scsi_cmnd->host_scribble and
2161 * finds struct CommandList and tries to aborts it
2162 * Now we have aborted the wrong command.
2163 *
d604f533
WS		 2164 * Reset c->scsi_cmd here so that the abort or reset handler will know
2165 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2166 * waiting for this command, and, if so, wake it.
2167 */
2168 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2169 mb(); /* Declare command idle before checking for pending events. */
a58e7e53 2170 if (c->abort_pending) {
d604f533 2171 do_wake = true;
a58e7e53 2172 c->abort_pending = false;
a58e7e53 2173 }
d604f533
WS		 2174 if (c->reset_pending) {
2175 unsigned long flags;
2176 struct hpsa_scsi_dev_t *dev;
2177
2178 /*
2179 * There appears to be a reset pending; lock the lock and
2180 * reconfirm. If so, then decrement the count of outstanding
2181 * commands and wake the reset command if this is the last one.
2182 */
2183 spin_lock_irqsave(&h->lock, flags);
2184 dev = c->reset_pending; /* Re-fetch under the lock. */
2185 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2186 do_wake = true;
2187 c->reset_pending = NULL;
2188 spin_unlock_irqrestore(&h->lock, flags);
2189 }
2190
2191 if (do_wake)
2192 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2193}
2194
73153fe5
WS		 2195static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2196 struct CommandList *c)
2197{
2198 hpsa_cmd_resolve_events(h, c);
2199 cmd_tagged_free(h, c);
2200}
2201
8a0ff92c
WS		 2202static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2203 struct CommandList *c, struct scsi_cmnd *cmd)
2204{
73153fe5 2205 hpsa_cmd_resolve_and_free(h, c);
8a0ff92c
WS		 2206 cmd->scsi_done(cmd);
2207}
2208
2209static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2210{
2211 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2212 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2213}
2214
a58e7e53
WS		 2215static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
2216{
2217 cmd->result = DID_ABORT << 16;
2218}
2219
2220static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
2221 struct scsi_cmnd *cmd)
2222{
2223 hpsa_set_scsi_cmd_aborted(cmd);
2224 dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
2225 c->Request.CDB, c->err_info->ScsiStatus);
73153fe5 2226 hpsa_cmd_resolve_and_free(h, c);
a58e7e53
WS		 2227}
2228
c349775e
ST		 2229static void process_ioaccel2_completion(struct ctlr_info *h,
2230 struct CommandList *c, struct scsi_cmnd *cmd,
2231 struct hpsa_scsi_dev_t *dev)
2232{
2233 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2234
2235 /* check for good status */
2236 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2237 c2->error_data.status == 0))
2238 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2239
8a0ff92c
WS		 2240 /*
2241 * Any RAID offload error results in retry which will use
c349775e
ST		 2242 * the normal I/O path so the controller can handle whatever's
2243 * wrong.
2244 */
f3f01730 2245 if (is_logical_device(dev) &&
c349775e
ST		 2246 c2->error_data.serv_response ==
2247 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc
DB		 2248 if (c2->error_data.status ==
2249 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
2250 dev->offload_enabled = 0;
8a0ff92c
WS		 2251
2252 return hpsa_retry_cmd(h, c);
a09c1441 2253 }
080ef1cc
DB		 2254
2255 if (handle_ioaccel_mode2_error(h, c, cmd, c2))
8a0ff92c 2256 return hpsa_retry_cmd(h, c);
080ef1cc 2257
8a0ff92c 2258 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2259}
2260
9437ac43
SC		 2261/* Returns 0 on success, < 0 otherwise. */
2262static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2263 struct CommandList *cp)
2264{
2265 u8 tmf_status = cp->err_info->ScsiStatus;
2266
2267 switch (tmf_status) {
2268 case CISS_TMF_COMPLETE:
2269 /*
2270 * CISS_TMF_COMPLETE never happens, instead,
2271 * ei->CommandStatus == 0 for this case.
2272 */
2273 case CISS_TMF_SUCCESS:
2274 return 0;
2275 case CISS_TMF_INVALID_FRAME:
2276 case CISS_TMF_NOT_SUPPORTED:
2277 case CISS_TMF_FAILED:
2278 case CISS_TMF_WRONG_LUN:
2279 case CISS_TMF_OVERLAPPED_TAG:
2280 break;
2281 default:
2282 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2283 tmf_status);
2284 break;
2285 }
2286 return -tmf_status;
2287}
2288
1fb011fb 2289static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2290{
2291 struct scsi_cmnd *cmd;
2292 struct ctlr_info *h;
2293 struct ErrorInfo *ei;
283b4a9b 2294 struct hpsa_scsi_dev_t *dev;
d9a729f3 2295 struct io_accel2_cmd *c2;
edd16368 2296
9437ac43
SC		 2297 u8 sense_key;
2298 u8 asc; /* additional sense code */
2299 u8 ascq; /* additional sense code qualifier */
db111e18 2300 unsigned long sense_data_size;
edd16368
SC		 2301
2302 ei = cp->err_info;
7fa3030c 2303 cmd = cp->scsi_cmd;
edd16368 2304 h = cp->h;
283b4a9b 2305 dev = cmd->device->hostdata;
d9a729f3 2306 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2307
2308 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2309 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2310 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2311 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2312
d9a729f3
WS		 2313 if ((cp->cmd_type == CMD_IOACCEL2) &&
2314 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2315 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2316
edd16368
SC		 2317 cmd->result = (DID_OK << 16); /* host byte */
2318 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2319
03383736
DB		 2320 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
2321 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2322
25163bd5
WS		 2323 /*
2324 * We check for lockup status here as it may be set for
2325 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2326 * fail_all_oustanding_cmds()
2327 */
2328 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2329 /* DID_NO_CONNECT will prevent a retry */
2330 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2331 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2332 }
2333
d604f533
WS		 2334 if ((unlikely(hpsa_is_pending_event(cp)))) {
2335 if (cp->reset_pending)
2336 return hpsa_cmd_resolve_and_free(h, cp);
2337 if (cp->abort_pending)
2338 return hpsa_cmd_abort_and_free(h, cp, cmd);
2339 }
2340
c349775e
ST		 2341 if (cp->cmd_type == CMD_IOACCEL2)
2342 return process_ioaccel2_completion(h, cp, cmd, dev);
2343
6aa4c361 2344 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2345 if (ei->CommandStatus == 0)
2346 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2347
e1f7de0c
MG		 2348 /* For I/O accelerator commands, copy over some fields to the normal
2349 * CISS header used below for error handling.
2350 */
2351 if (cp->cmd_type == CMD_IOACCEL1) {
2352 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2353 cp->Header.SGList = scsi_sg_count(cmd);
2354 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2355 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2356 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2357 cp->Header.tag = c->tag;
e1f7de0c
MG		 2358 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2359 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2360
2361 /* Any RAID offload error results in retry which will use
2362 * the normal I/O path so the controller can handle whatever's
2363 * wrong.
2364 */
f3f01730 2365 if (is_logical_device(dev)) {
283b4a9b
SC		 2366 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2367 dev->offload_enabled = 0;
d604f533 2368 return hpsa_retry_cmd(h, cp);
283b4a9b 2369 }
e1f7de0c
MG		 2370 }
2371
edd16368
SC		 2372 /* an error has occurred */
2373 switch (ei->CommandStatus) {
2374
2375 case CMD_TARGET_STATUS:
9437ac43
SC		 2376 cmd->result |= ei->ScsiStatus;
2377 /* copy the sense data */
2378 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2379 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2380 else
2381 sense_data_size = sizeof(ei->SenseInfo);
2382 if (ei->SenseLen < sense_data_size)
2383 sense_data_size = ei->SenseLen;
2384 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2385 if (ei->ScsiStatus)
2386 decode_sense_data(ei->SenseInfo, sense_data_size,
2387 &sense_key, &asc, &ascq);
edd16368 2388 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
1d3b3609 2389 if (sense_key == ABORTED_COMMAND) {
2e311fba 2390 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 2391 break;
2392 }
edd16368
SC		 2393 break;
2394 }
edd16368
SC		 2395 /* Problem was not a check condition
2396 * Pass it up to the upper layers...
2397 */
2398 if (ei->ScsiStatus) {
2399 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2400 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2401 "Returning result: 0x%x\n",
2402 cp, ei->ScsiStatus,
2403 sense_key, asc, ascq,
2404 cmd->result);
2405 } else { /* scsi status is zero??? How??? */
2406 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2407 "Returning no connection.\n", cp),
2408
2409 /* Ordinarily, this case should never happen,
2410 * but there is a bug in some released firmware
2411 * revisions that allows it to happen if, for
2412 * example, a 4100 backplane loses power and
2413 * the tape drive is in it. We assume that
2414 * it's a fatal error of some kind because we
2415 * can't show that it wasn't. We will make it
2416 * look like selection timeout since that is
2417 * the most common reason for this to occur,
2418 * and it's severe enough.
2419 */
2420
2421 cmd->result = DID_NO_CONNECT << 16;
2422 }
2423 break;
2424
2425 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2426 break;
2427 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2428 dev_warn(&h->pdev->dev,
2429 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2430 break;
2431 case CMD_INVALID: {
2432 /* print_bytes(cp, sizeof(*cp), 1, 0);
2433 print_cmd(cp); */
2434 /* We get CMD_INVALID if you address a non-existent device
2435 * instead of a selection timeout (no response). You will
2436 * see this if you yank out a drive, then try to access it.
2437 * This is kind of a shame because it means that any other
2438 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2439 * missing target. */
2440 cmd->result = DID_NO_CONNECT << 16;
2441 }
2442 break;
2443 case CMD_PROTOCOL_ERR:
256d0eaa 2444 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2445 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2446 cp->Request.CDB);
edd16368
SC		 2447 break;
2448 case CMD_HARDWARE_ERR:
2449 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2450 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2451 cp->Request.CDB);
edd16368
SC		 2452 break;
2453 case CMD_CONNECTION_LOST:
2454 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2455 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2456 cp->Request.CDB);
edd16368
SC		 2457 break;
2458 case CMD_ABORTED:
a58e7e53
WS		 2459 /* Return now to avoid calling scsi_done(). */
2460 return hpsa_cmd_abort_and_free(h, cp, cmd);
edd16368
SC		 2461 case CMD_ABORT_FAILED:
2462 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2463 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2464 cp->Request.CDB);
edd16368
SC		 2465 break;
2466 case CMD_UNSOLICITED_ABORT:
f6e76055 2467 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2468 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2469 cp->Request.CDB);
edd16368
SC		 2470 break;
2471 case CMD_TIMEOUT:
2472 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2473 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2474 cp->Request.CDB);
edd16368 2475 break;
1d5e2ed0
SC		 2476 case CMD_UNABORTABLE:
2477 cmd->result = DID_ERROR << 16;
2478 dev_warn(&h->pdev->dev, "Command unabortable\n");
2479 break;
9437ac43
SC		 2480 case CMD_TMF_STATUS:
2481 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2482 cmd->result = DID_ERROR << 16;
2483 break;
283b4a9b
SC		 2484 case CMD_IOACCEL_DISABLED:
2485 /* This only handles the direct pass-through case since RAID
2486 * offload is handled above. Just attempt a retry.
2487 */
2488 cmd->result = DID_SOFT_ERROR << 16;
2489 dev_warn(&h->pdev->dev,
2490 "cp %p had HP SSD Smart Path error\n", cp);
2491 break;
edd16368
SC		 2492 default:
2493 cmd->result = DID_ERROR << 16;
2494 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2495 cp, ei->CommandStatus);
2496 }
8a0ff92c
WS		 2497
2498 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2499}
2500
edd16368
SC		 2501static void hpsa_pci_unmap(struct pci_dev *pdev,
2502 struct CommandList *c, int sg_used, int data_direction)
2503{
2504 int i;
edd16368 2505
50a0decf
SC		 2506 for (i = 0; i < sg_used; i++)
2507 pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
2508 le32_to_cpu(c->SG[i].Len),
2509 data_direction);
edd16368
SC		 2510}
2511
a2dac136 2512static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2513 struct CommandList *cp,
2514 unsigned char *buf,
2515 size_t buflen,
2516 int data_direction)
2517{
01a02ffc 2518 u64 addr64;
edd16368
SC		 2519
2520 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
2521 cp->Header.SGList = 0;
50a0decf 2522 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2523 return 0;
edd16368
SC		 2524 }
2525
50a0decf 2526 addr64 = pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 2527 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2528 /* Prevent subsequent unmap of something never mapped */
eceaae18 2529 cp->Header.SGList = 0;
50a0decf 2530 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2531 return -1;
eceaae18 2532 }
50a0decf
SC		 2533 cp->SG[0].Addr = cpu_to_le64(addr64);
2534 cp->SG[0].Len = cpu_to_le32(buflen);
2535 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2536 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2537 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2538 return 0;
edd16368
SC		 2539}
2540
25163bd5
WS		 2541#define NO_TIMEOUT ((unsigned long) -1)
2542#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2543static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2544 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2545{
2546 DECLARE_COMPLETION_ONSTACK(wait);
2547
2548 c->waiting = &wait;
25163bd5
WS		 2549 __enqueue_cmd_and_start_io(h, c, reply_queue);
2550 if (timeout_msecs == NO_TIMEOUT) {
2551 /* TODO: get rid of this no-timeout thing */
2552 wait_for_completion_io(&wait);
2553 return IO_OK;
2554 }
2555 if (!wait_for_completion_io_timeout(&wait,
2556 msecs_to_jiffies(timeout_msecs))) {
2557 dev_warn(&h->pdev->dev, "Command timed out.\n");
2558 return -ETIMEDOUT;
2559 }
2560 return IO_OK;
2561}
2562
2563static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2564 int reply_queue, unsigned long timeout_msecs)
2565{
2566 if (unlikely(lockup_detected(h))) {
2567 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2568 return IO_OK;
2569 }
2570 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2571}
2572
094963da
SC		 2573static u32 lockup_detected(struct ctlr_info *h)
2574{
2575 int cpu;
2576 u32 rc, *lockup_detected;
2577
2578 cpu = get_cpu();
2579 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2580 rc = *lockup_detected;
2581 put_cpu();
2582 return rc;
2583}
2584
9c2fc160 2585#define MAX_DRIVER_CMD_RETRIES 25
25163bd5
WS		 2586static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
2587 struct CommandList *c, int data_direction, unsigned long timeout_msecs)
edd16368 2588{
9c2fc160 2589 int backoff_time = 10, retry_count = 0;
25163bd5 2590 int rc;
edd16368
SC		 2591
2592 do {
7630abd0 2593 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2594 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2595 timeout_msecs);
2596 if (rc)
2597 break;
edd16368 2598 retry_count++;
9c2fc160
SC		 2599 if (retry_count > 3) {
2600 msleep(backoff_time);
2601 if (backoff_time < 1000)
2602 backoff_time *= 2;
2603 }
852af20a 2604 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2605 check_for_busy(h, c)) &&
2606 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2607 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2608 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2609 rc = -EIO;
2610 return rc;
edd16368
SC		 2611}
2612
d1e8beac
SC		 2613static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2614 struct CommandList *c)
edd16368 2615{
d1e8beac
SC		 2616 const u8 *cdb = c->Request.CDB;
2617 const u8 *lun = c->Header.LUN.LunAddrBytes;
2618
2619 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
2620 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2621 txt, lun[0], lun[1], lun[2], lun[3],
2622 lun[4], lun[5], lun[6], lun[7],
2623 cdb[0], cdb[1], cdb[2], cdb[3],
2624 cdb[4], cdb[5], cdb[6], cdb[7],
2625 cdb[8], cdb[9], cdb[10], cdb[11],
2626 cdb[12], cdb[13], cdb[14], cdb[15]);
2627}
2628
2629static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2630 struct CommandList *cp)
2631{
2632 const struct ErrorInfo *ei = cp->err_info;
edd16368 2633 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2634 u8 sense_key, asc, ascq;
2635 int sense_len;
edd16368 2636
edd16368
SC		 2637 switch (ei->CommandStatus) {
2638 case CMD_TARGET_STATUS:
9437ac43
SC		 2639 if (ei->SenseLen > sizeof(ei->SenseInfo))
2640 sense_len = sizeof(ei->SenseInfo);
2641 else
2642 sense_len = ei->SenseLen;
2643 decode_sense_data(ei->SenseInfo, sense_len,
2644 &sense_key, &asc, &ascq);
d1e8beac
SC		 2645 hpsa_print_cmd(h, "SCSI status", cp);
2646 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2647 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2648 sense_key, asc, ascq);
d1e8beac 2649 else
9437ac43 2650 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2651 if (ei->ScsiStatus == 0)
2652 dev_warn(d, "SCSI status is abnormally zero. "
2653 "(probably indicates selection timeout "
2654 "reported incorrectly due to a known "
2655 "firmware bug, circa July, 2001.)\n");
2656 break;
2657 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2658 break;
2659 case CMD_DATA_OVERRUN:
d1e8beac 2660 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2661 break;
2662 case CMD_INVALID: {
2663 /* controller unfortunately reports SCSI passthru's
2664 * to non-existent targets as invalid commands.
2665 */
d1e8beac
SC		 2666 hpsa_print_cmd(h, "invalid command", cp);
2667 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2668 }
2669 break;
2670 case CMD_PROTOCOL_ERR:
d1e8beac 2671 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2672 break;
2673 case CMD_HARDWARE_ERR:
d1e8beac 2674 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2675 break;
2676 case CMD_CONNECTION_LOST:
d1e8beac 2677 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2678 break;
2679 case CMD_ABORTED:
d1e8beac 2680 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2681 break;
2682 case CMD_ABORT_FAILED:
d1e8beac 2683 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2684 break;
2685 case CMD_UNSOLICITED_ABORT:
d1e8beac 2686 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2687 break;
2688 case CMD_TIMEOUT:
d1e8beac 2689 hpsa_print_cmd(h, "timed out", cp);
edd16368 2690 break;
1d5e2ed0 2691 case CMD_UNABORTABLE:
d1e8beac 2692 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2693 break;
25163bd5
WS		 2694 case CMD_CTLR_LOCKUP:
2695 hpsa_print_cmd(h, "controller lockup detected", cp);
2696 break;
edd16368 2697 default:
d1e8beac
SC		 2698 hpsa_print_cmd(h, "unknown status", cp);
2699 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2700 ei->CommandStatus);
2701 }
2702}
2703
2704static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 2705 u16 page, unsigned char *buf,
edd16368
SC		 2706 unsigned char bufsize)
2707{
2708 int rc = IO_OK;
2709 struct CommandList *c;
2710 struct ErrorInfo *ei;
2711
45fcb86e 2712 c = cmd_alloc(h);
edd16368 2713
a2dac136
SC		 2714 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
2715 page, scsi3addr, TYPE_CMD)) {
2716 rc = -1;
2717 goto out;
2718 }
25163bd5
WS		 2719 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2720 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2721 if (rc)
2722 goto out;
edd16368
SC		 2723 ei = c->err_info;
2724 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2725 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2726 rc = -1;
2727 }
a2dac136 2728out:
45fcb86e 2729 cmd_free(h, c);
edd16368
SC		 2730 return rc;
2731}
2732
bf711ac6 2733static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 2734 u8 reset_type, int reply_queue)
edd16368
SC		 2735{
2736 int rc = IO_OK;
2737 struct CommandList *c;
2738 struct ErrorInfo *ei;
2739
45fcb86e 2740 c = cmd_alloc(h);
edd16368 2741
edd16368 2742
a2dac136 2743 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 2744 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 2745 scsi3addr, TYPE_MSG);
25163bd5
WS		 2746 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
2747 if (rc) {
2748 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
2749 goto out;
2750 }
edd16368
SC		 2751 /* no unmap needed here because no data xfer. */
2752
2753 ei = c->err_info;
2754 if (ei->CommandStatus != 0) {
d1e8beac 2755 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2756 rc = -1;
2757 }
25163bd5 2758out:
45fcb86e 2759 cmd_free(h, c);
edd16368
SC		 2760 return rc;
2761}
2762
d604f533
WS		 2763static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
2764 struct hpsa_scsi_dev_t *dev,
2765 unsigned char *scsi3addr)
2766{
2767 int i;
2768 bool match = false;
2769 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2770 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
2771
2772 if (hpsa_is_cmd_idle(c))
2773 return false;
2774
2775 switch (c->cmd_type) {
2776 case CMD_SCSI:
2777 case CMD_IOCTL_PEND:
2778 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
2779 sizeof(c->Header.LUN.LunAddrBytes));
2780 break;
2781
2782 case CMD_IOACCEL1:
2783 case CMD_IOACCEL2:
2784 if (c->phys_disk == dev) {
2785 /* HBA mode match */
2786 match = true;
2787 } else {
2788 /* Possible RAID mode -- check each phys dev. */
2789 /* FIXME: Do we need to take out a lock here? If
2790 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
2791 * instead. */
2792 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2793 /* FIXME: an alternate test might be
2794 *
2795 * match = dev->phys_disk[i]->ioaccel_handle
2796 * == c2->scsi_nexus; */
2797 match = dev->phys_disk[i] == c->phys_disk;
2798 }
2799 }
2800 break;
2801
2802 case IOACCEL2_TMF:
2803 for (i = 0; i < dev->nphysical_disks && !match; i++) {
2804 match = dev->phys_disk[i]->ioaccel_handle ==
2805 le32_to_cpu(ac->it_nexus);
2806 }
2807 break;
2808
2809 case 0: /* The command is in the middle of being initialized. */
2810 match = false;
2811 break;
2812
2813 default:
2814 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
2815 c->cmd_type);
2816 BUG();
2817 }
2818
2819 return match;
2820}
2821
2822static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
2823 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
2824{
2825 int i;
2826 int rc = 0;
2827
2828 /* We can really only handle one reset at a time */
2829 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
2830 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
2831 return -EINTR;
2832 }
2833
2834 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
2835
2836 for (i = 0; i < h->nr_cmds; i++) {
2837 struct CommandList *c = h->cmd_pool + i;
2838 int refcount = atomic_inc_return(&c->refcount);
2839
2840 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
2841 unsigned long flags;
2842
2843 /*
2844 * Mark the target command as having a reset pending,
2845 * then lock a lock so that the command cannot complete
2846 * while we're considering it. If the command is not
2847 * idle then count it; otherwise revoke the event.
2848 */
2849 c->reset_pending = dev;
2850 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
2851 if (!hpsa_is_cmd_idle(c))
2852 atomic_inc(&dev->reset_cmds_out);
2853 else
2854 c->reset_pending = NULL;
2855 spin_unlock_irqrestore(&h->lock, flags);
2856 }
2857
2858 cmd_free(h, c);
2859 }
2860
2861 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
2862 if (!rc)
2863 wait_event(h->event_sync_wait_queue,
2864 atomic_read(&dev->reset_cmds_out) == 0 ||
2865 lockup_detected(h));
2866
2867 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 2868 dev_warn(&h->pdev->dev,
2869 "Controller lockup detected during reset wait\n");
2870 rc = -ENODEV;
2871 }
d604f533
WS		 2872
2873 if (unlikely(rc))
2874 atomic_set(&dev->reset_cmds_out, 0);
2875
2876 mutex_unlock(&h->reset_mutex);
2877 return rc;
2878}
2879
edd16368
SC		 2880static void hpsa_get_raid_level(struct ctlr_info *h,
2881 unsigned char *scsi3addr, unsigned char *raid_level)
2882{
2883 int rc;
2884 unsigned char *buf;
2885
2886 *raid_level = RAID_UNKNOWN;
2887 buf = kzalloc(64, GFP_KERNEL);
2888 if (!buf)
2889 return;
b7bb24eb 2890 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2891 if (rc == 0)
2892 *raid_level = buf[8];
2893 if (*raid_level > RAID_UNKNOWN)
2894 *raid_level = RAID_UNKNOWN;
2895 kfree(buf);
2896 return;
2897}
2898
283b4a9b
SC		 2899#define HPSA_MAP_DEBUG
2900#ifdef HPSA_MAP_DEBUG
2901static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2902 struct raid_map_data *map_buff)
2903{
2904 struct raid_map_disk_data *dd = &map_buff->data[0];
2905 int map, row, col;
2906 u16 map_cnt, row_cnt, disks_per_row;
2907
2908 if (rc != 0)
2909 return;
2910
2ba8bfc8
SC		 2911 /* Show details only if debugging has been activated. */
2912 if (h->raid_offload_debug < 2)
2913 return;
2914
283b4a9b
SC		 2915 dev_info(&h->pdev->dev, "structure_size = %u\n",
2916 le32_to_cpu(map_buff->structure_size));
2917 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2918 le32_to_cpu(map_buff->volume_blk_size));
2919 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2920 le64_to_cpu(map_buff->volume_blk_cnt));
2921 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2922 map_buff->phys_blk_shift);
2923 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2924 map_buff->parity_rotation_shift);
2925 dev_info(&h->pdev->dev, "strip_size = %u\n",
2926 le16_to_cpu(map_buff->strip_size));
2927 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2928 le64_to_cpu(map_buff->disk_starting_blk));
2929 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2930 le64_to_cpu(map_buff->disk_blk_cnt));
2931 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2932 le16_to_cpu(map_buff->data_disks_per_row));
2933 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2934 le16_to_cpu(map_buff->metadata_disks_per_row));
2935 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2936 le16_to_cpu(map_buff->row_cnt));
2937 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2938 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 2939 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 2940 le16_to_cpu(map_buff->flags));
2b08b3e9
DB		 2941 dev_info(&h->pdev->dev, "encrypytion = %s\n",
2942 le16_to_cpu(map_buff->flags) &
2943 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 2944 dev_info(&h->pdev->dev, "dekindex = %u\n",
2945 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2946 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2947 for (map = 0; map < map_cnt; map++) {
2948 dev_info(&h->pdev->dev, "Map%u:\n", map);
2949 row_cnt = le16_to_cpu(map_buff->row_cnt);
2950 for (row = 0; row < row_cnt; row++) {
2951 dev_info(&h->pdev->dev, " Row%u:\n", row);
2952 disks_per_row =
2953 le16_to_cpu(map_buff->data_disks_per_row);
2954 for (col = 0; col < disks_per_row; col++, dd++)
2955 dev_info(&h->pdev->dev,
2956 " D%02u: h=0x%04x xor=%u,%u\n",
2957 col, dd->ioaccel_handle,
2958 dd->xor_mult[0], dd->xor_mult[1]);
2959 disks_per_row =
2960 le16_to_cpu(map_buff->metadata_disks_per_row);
2961 for (col = 0; col < disks_per_row; col++, dd++)
2962 dev_info(&h->pdev->dev,
2963 " M%02u: h=0x%04x xor=%u,%u\n",
2964 col, dd->ioaccel_handle,
2965 dd->xor_mult[0], dd->xor_mult[1]);
2966 }
2967 }
2968}
2969#else
2970static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2971 __attribute__((unused)) int rc,
2972 __attribute__((unused)) struct raid_map_data *map_buff)
2973{
2974}
2975#endif
2976
2977static int hpsa_get_raid_map(struct ctlr_info *h,
2978 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2979{
2980 int rc = 0;
2981 struct CommandList *c;
2982 struct ErrorInfo *ei;
2983
45fcb86e 2984 c = cmd_alloc(h);
bf43caf3 2985
283b4a9b
SC		 2986 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2987 sizeof(this_device->raid_map), 0,
2988 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 2989 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
2990 cmd_free(h, c);
2991 return -1;
283b4a9b 2992 }
25163bd5
WS		 2993 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
2994 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
2995 if (rc)
2996 goto out;
283b4a9b
SC		 2997 ei = c->err_info;
2998 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2999 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3000 rc = -1;
3001 goto out;
283b4a9b 3002 }
45fcb86e 3003 cmd_free(h, c);
283b4a9b
SC		 3004
3005 /* @todo in the future, dynamically allocate RAID map memory */
3006 if (le32_to_cpu(this_device->raid_map.structure_size) >
3007 sizeof(this_device->raid_map)) {
3008 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3009 rc = -1;
3010 }
3011 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3012 return rc;
25163bd5
WS		 3013out:
3014 cmd_free(h, c);
3015 return rc;
283b4a9b
SC		 3016}
3017
03383736
DB		 3018static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3019 unsigned char scsi3addr[], u16 bmic_device_index,
3020 struct bmic_identify_physical_device *buf, size_t bufsize)
3021{
3022 int rc = IO_OK;
3023 struct CommandList *c;
3024 struct ErrorInfo *ei;
3025
3026 c = cmd_alloc(h);
3027 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3028 0, RAID_CTLR_LUNID, TYPE_CMD);
3029 if (rc)
3030 goto out;
3031
3032 c->Request.CDB[2] = bmic_device_index & 0xff;
3033 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3034
25163bd5
WS		 3035 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
3036 NO_TIMEOUT);
03383736
DB		 3037 ei = c->err_info;
3038 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3039 hpsa_scsi_interpret_error(h, c);
3040 rc = -1;
3041 }
3042out:
3043 cmd_free(h, c);
3044 return rc;
3045}
3046
1b70150a
SC		 3047static int hpsa_vpd_page_supported(struct ctlr_info *h,
3048 unsigned char scsi3addr[], u8 page)
3049{
3050 int rc;
3051 int i;
3052 int pages;
3053 unsigned char *buf, bufsize;
3054
3055 buf = kzalloc(256, GFP_KERNEL);
3056 if (!buf)
3057 return 0;
3058
3059 /* Get the size of the page list first */
3060 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3061 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3062 buf, HPSA_VPD_HEADER_SZ);
3063 if (rc != 0)
3064 goto exit_unsupported;
3065 pages = buf[3];
3066 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3067 bufsize = pages + HPSA_VPD_HEADER_SZ;
3068 else
3069 bufsize = 255;
3070
3071 /* Get the whole VPD page list */
3072 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3073 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3074 buf, bufsize);
3075 if (rc != 0)
3076 goto exit_unsupported;
3077
3078 pages = buf[3];
3079 for (i = 1; i <= pages; i++)
3080 if (buf[3 + i] == page)
3081 goto exit_supported;
3082exit_unsupported:
3083 kfree(buf);
3084 return 0;
3085exit_supported:
3086 kfree(buf);
3087 return 1;
3088}
3089
283b4a9b
SC		 3090static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3091 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3092{
3093 int rc;
3094 unsigned char *buf;
3095 u8 ioaccel_status;
3096
3097 this_device->offload_config = 0;
3098 this_device->offload_enabled = 0;
41ce4c35 3099 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3100
3101 buf = kzalloc(64, GFP_KERNEL);
3102 if (!buf)
3103 return;
1b70150a
SC		 3104 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3105 goto out;
283b4a9b 3106 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3107 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3108 if (rc != 0)
3109 goto out;
3110
3111#define IOACCEL_STATUS_BYTE 4
3112#define OFFLOAD_CONFIGURED_BIT 0x01
3113#define OFFLOAD_ENABLED_BIT 0x02
3114 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3115 this_device->offload_config =
3116 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3117 if (this_device->offload_config) {
3118 this_device->offload_enabled =
3119 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3120 if (hpsa_get_raid_map(h, scsi3addr, this_device))
3121 this_device->offload_enabled = 0;
3122 }
41ce4c35 3123 this_device->offload_to_be_enabled = this_device->offload_enabled;
283b4a9b
SC		 3124out:
3125 kfree(buf);
3126 return;
3127}
3128
edd16368
SC		 3129/* Get the device id from inquiry page 0x83 */
3130static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
3131 unsigned char *device_id, int buflen)
3132{
3133 int rc;
3134 unsigned char *buf;
3135
3136 if (buflen > 16)
3137 buflen = 16;
3138 buf = kzalloc(64, GFP_KERNEL);
3139 if (!buf)
a84d794d 3140 return -ENOMEM;
b7bb24eb 3141 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 3142 if (rc == 0)
3143 memcpy(device_id, &buf[8], buflen);
3144 kfree(buf);
3145 return rc != 0;
3146}
3147
3148static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3149 void *buf, int bufsize,
edd16368
SC		 3150 int extended_response)
3151{
3152 int rc = IO_OK;
3153 struct CommandList *c;
3154 unsigned char scsi3addr[8];
3155 struct ErrorInfo *ei;
3156
45fcb86e 3157 c = cmd_alloc(h);
bf43caf3 3158
e89c0ae7
SC		 3159 /* address the controller */
3160 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3161 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3162 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
3163 rc = -1;
3164 goto out;
3165 }
edd16368
SC		 3166 if (extended_response)
3167 c->Request.CDB[1] = extended_response;
25163bd5
WS		 3168 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
3169 PCI_DMA_FROMDEVICE, NO_TIMEOUT);
3170 if (rc)
3171 goto out;
edd16368
SC		 3172 ei = c->err_info;
3173 if (ei->CommandStatus != 0 &&
3174 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3175 hpsa_scsi_interpret_error(h, c);
edd16368 3176 rc = -1;
283b4a9b 3177 } else {
03383736
DB		 3178 struct ReportLUNdata *rld = buf;
3179
3180 if (rld->extended_response_flag != extended_response) {
283b4a9b
SC		 3181 dev_err(&h->pdev->dev,
3182 "report luns requested format %u, got %u\n",
3183 extended_response,
03383736 3184 rld->extended_response_flag);
283b4a9b
SC		 3185 rc = -1;
3186 }
edd16368 3187 }
a2dac136 3188out:
45fcb86e 3189 cmd_free(h, c);
edd16368
SC		 3190 return rc;
3191}
3192
3193static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3194 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3195{
03383736
DB		 3196 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3197 HPSA_REPORT_PHYS_EXTENDED);
edd16368
SC		 3198}
3199
3200static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3201 struct ReportLUNdata *buf, int bufsize)
3202{
3203 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3204}
3205
3206static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3207 int bus, int target, int lun)
3208{
3209 device->bus = bus;
3210 device->target = target;
3211 device->lun = lun;
3212}
3213
9846590e
SC		 3214/* Use VPD inquiry to get details of volume status */
3215static int hpsa_get_volume_status(struct ctlr_info *h,
3216 unsigned char scsi3addr[])
3217{
3218 int rc;
3219 int status;
3220 int size;
3221 unsigned char *buf;
3222
3223 buf = kzalloc(64, GFP_KERNEL);
3224 if (!buf)
3225 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3226
3227 /* Does controller have VPD for logical volume status? */
24a4b078 3228 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3229 goto exit_failed;
9846590e
SC		 3230
3231 /* Get the size of the VPD return buffer */
3232 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3233 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3234 if (rc != 0)
9846590e 3235 goto exit_failed;
9846590e
SC		 3236 size = buf[3];
3237
3238 /* Now get the whole VPD buffer */
3239 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3240 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3241 if (rc != 0)
9846590e 3242 goto exit_failed;
9846590e
SC		 3243 status = buf[4]; /* status byte */
3244
3245 kfree(buf);
3246 return status;
3247exit_failed:
3248 kfree(buf);
3249 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3250}
3251
3252/* Determine offline status of a volume.
3253 * Return either:
3254 * 0 (not offline)
67955ba3 3255 * 0xff (offline for unknown reasons)
9846590e
SC		 3256 * # (integer code indicating one of several NOT READY states
3257 * describing why a volume is to be kept offline)
3258 */
67955ba3 3259static int hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3260 unsigned char scsi3addr[])
3261{
3262 struct CommandList *c;
9437ac43
SC		 3263 unsigned char *sense;
3264 u8 sense_key, asc, ascq;
3265 int sense_len;
25163bd5 3266 int rc, ldstat = 0;
9846590e
SC		 3267 u16 cmd_status;
3268 u8 scsi_status;
3269#define ASC_LUN_NOT_READY 0x04
3270#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3271#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3272
3273 c = cmd_alloc(h);
bf43caf3 3274
9846590e 3275 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
25163bd5
WS		 3276 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3277 if (rc) {
3278 cmd_free(h, c);
3279 return 0;
3280 }
9846590e 3281 sense = c->err_info->SenseInfo;
9437ac43
SC		 3282 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3283 sense_len = sizeof(c->err_info->SenseInfo);
3284 else
3285 sense_len = c->err_info->SenseLen;
3286 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3287 cmd_status = c->err_info->CommandStatus;
3288 scsi_status = c->err_info->ScsiStatus;
3289 cmd_free(h, c);
3290 /* Is the volume 'not ready'? */
3291 if (cmd_status != CMD_TARGET_STATUS ||
3292 scsi_status != SAM_STAT_CHECK_CONDITION ||
3293 sense_key != NOT_READY ||
3294 asc != ASC_LUN_NOT_READY) {
3295 return 0;
3296 }
3297
3298 /* Determine the reason for not ready state */
3299 ldstat = hpsa_get_volume_status(h, scsi3addr);
3300
3301 /* Keep volume offline in certain cases: */
3302 switch (ldstat) {
3303 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3304 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3305 case HPSA_LV_UNDERGOING_RPI:
3306 case HPSA_LV_PENDING_RPI:
3307 case HPSA_LV_ENCRYPTED_NO_KEY:
3308 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3309 case HPSA_LV_UNDERGOING_ENCRYPTION:
3310 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3311 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3312 return ldstat;
3313 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3314 /* If VPD status page isn't available,
3315 * use ASC/ASCQ to determine state
3316 */
3317 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3318 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3319 return ldstat;
3320 break;
3321 default:
3322 break;
3323 }
3324 return 0;
3325}
3326
9b5c48c2
SC		 3327/*
3328 * Find out if a logical device supports aborts by simply trying one.
3329 * Smart Array may claim not to support aborts on logical drives, but
3330 * if a MSA2000 * is connected, the drives on that will be presented
3331 * by the Smart Array as logical drives, and aborts may be sent to
3332 * those devices successfully. So the simplest way to find out is
3333 * to simply try an abort and see how the device responds.
3334 */
3335static int hpsa_device_supports_aborts(struct ctlr_info *h,
3336 unsigned char *scsi3addr)
3337{
3338 struct CommandList *c;
3339 struct ErrorInfo *ei;
3340 int rc = 0;
3341
3342 u64 tag = (u64) -1; /* bogus tag */
3343
3344 /* Assume that physical devices support aborts */
3345 if (!is_logical_dev_addr_mode(scsi3addr))
3346 return 1;
3347
3348 c = cmd_alloc(h);
bf43caf3 3349
9b5c48c2
SC		 3350 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
3351 (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
3352 /* no unmap needed here because no data xfer. */
3353 ei = c->err_info;
3354 switch (ei->CommandStatus) {
3355 case CMD_INVALID:
3356 rc = 0;
3357 break;
3358 case CMD_UNABORTABLE:
3359 case CMD_ABORT_FAILED:
3360 rc = 1;
3361 break;
9437ac43
SC		 3362 case CMD_TMF_STATUS:
3363 rc = hpsa_evaluate_tmf_status(h, c);
3364 break;
9b5c48c2
SC		 3365 default:
3366 rc = 0;
3367 break;
3368 }
3369 cmd_free(h, c);
3370 return rc;
3371}
3372
edd16368 3373static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3374 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3375 unsigned char *is_OBDR_device)
edd16368 3376{
0b0e1d6c
SC		 3377
3378#define OBDR_SIG_OFFSET 43
3379#define OBDR_TAPE_SIG "$DR-10"
3380#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3381#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3382
ea6d3bc3 3383 unsigned char *inq_buff;
0b0e1d6c 3384 unsigned char *obdr_sig;
683fc444 3385 int rc = 0;
edd16368 3386
ea6d3bc3 3387 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3388 if (!inq_buff) {
3389 rc = -ENOMEM;
edd16368 3390 goto bail_out;
683fc444 3391 }
edd16368 3392
edd16368
SC		 3393 /* Do an inquiry to the device to see what it is. */
3394 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3395 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
3396 /* Inquiry failed (msg printed already) */
3397 dev_err(&h->pdev->dev,
3398 "hpsa_update_device_info: inquiry failed\n");
683fc444 3399 rc = -EIO;
edd16368
SC		 3400 goto bail_out;
3401 }
3402
edd16368
SC		 3403 this_device->devtype = (inq_buff[0] & 0x1f);
3404 memcpy(this_device->scsi3addr, scsi3addr, 8);
3405 memcpy(this_device->vendor, &inq_buff[8],
3406 sizeof(this_device->vendor));
3407 memcpy(this_device->model, &inq_buff[16],
3408 sizeof(this_device->model));
edd16368
SC		 3409 memset(this_device->device_id, 0,
3410 sizeof(this_device->device_id));
3411 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
3412 sizeof(this_device->device_id));
3413
3414 if (this_device->devtype == TYPE_DISK &&
283b4a9b 3415 is_logical_dev_addr_mode(scsi3addr)) {
67955ba3
SC		 3416 int volume_offline;
3417
edd16368 3418 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3419 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3420 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3
SC		 3421 volume_offline = hpsa_volume_offline(h, scsi3addr);
3422 if (volume_offline < 0 || volume_offline > 0xff)
3423 volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED;
3424 this_device->volume_offline = volume_offline & 0xff;
283b4a9b 3425 } else {
edd16368 3426 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 3427 this_device->offload_config = 0;
3428 this_device->offload_enabled = 0;
41ce4c35 3429 this_device->offload_to_be_enabled = 0;
a3144e0b 3430 this_device->hba_ioaccel_enabled = 0;
9846590e 3431 this_device->volume_offline = 0;
03383736 3432 this_device->queue_depth = h->nr_cmds;
283b4a9b 3433 }
edd16368 3434
0b0e1d6c
SC		 3435 if (is_OBDR_device) {
3436 /* See if this is a One-Button-Disaster-Recovery device
3437 * by looking for "$DR-10" at offset 43 in inquiry data.
3438 */
3439 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
3440 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
3441 strncmp(obdr_sig, OBDR_TAPE_SIG,
3442 OBDR_SIG_LEN) == 0);
3443 }
edd16368
SC		 3444 kfree(inq_buff);
3445 return 0;
3446
3447bail_out:
3448 kfree(inq_buff);
683fc444 3449 return rc;
edd16368
SC		 3450}
3451
9b5c48c2
SC		 3452static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
3453 struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
3454{
3455 unsigned long flags;
3456 int rc, entry;
3457 /*
3458 * See if this device supports aborts. If we already know
3459 * the device, we already know if it supports aborts, otherwise
3460 * we have to find out if it supports aborts by trying one.
3461 */
3462 spin_lock_irqsave(&h->devlock, flags);
3463 rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
3464 if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
3465 entry >= 0 && entry < h->ndevices) {
3466 dev->supports_aborts = h->dev[entry]->supports_aborts;
3467 spin_unlock_irqrestore(&h->devlock, flags);
3468 } else {
3469 spin_unlock_irqrestore(&h->devlock, flags);
3470 dev->supports_aborts =
3471 hpsa_device_supports_aborts(h, scsi3addr);
3472 if (dev->supports_aborts < 0)
3473 dev->supports_aborts = 0;
3474 }
3475}
3476
4f4eb9f1 3477static unsigned char *ext_target_model[] = {
edd16368
SC		 3478 "MSA2012",
3479 "MSA2024",
3480 "MSA2312",
3481 "MSA2324",
fda38518 3482 "P2000 G3 SAS",
e06c8e5c 3483 "MSA 2040 SAS",
edd16368
SC		 3484 NULL,
3485};
3486
4f4eb9f1 3487static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 3488{
3489 int i;
3490
4f4eb9f1
ST		 3491 for (i = 0; ext_target_model[i]; i++)
3492 if (strncmp(device->model, ext_target_model[i],
3493 strlen(ext_target_model[i])) == 0)
edd16368
SC		 3494 return 1;
3495 return 0;
3496}
3497
3498/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 3499 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 3500 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
3501 * Logical drive target and lun are assigned at this time, but
3502 * physical device lun and target assignment are deferred (assigned
3503 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
3504 */
3505static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 3506 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 3507{
1f310bde
SC		 3508 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
3509
3510 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
3511 /* physical device, target and lun filled in later */
edd16368 3512 if (is_hba_lunid(lunaddrbytes))
1f310bde 3513 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 3514 else
1f310bde
SC		 3515 /* defer target, lun assignment for physical devices */
3516 hpsa_set_bus_target_lun(device, 2, -1, -1);
3517 return;
3518 }
3519 /* It's a logical device */
4f4eb9f1
ST		 3520 if (is_ext_target(h, device)) {
3521 /* external target way, put logicals on bus 1
1f310bde
SC		 3522 * and match target/lun numbers box
3523 * reports, other smart array, bus 0, target 0, match lunid
3524 */
3525 hpsa_set_bus_target_lun(device,
3526 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
3527 return;
edd16368 3528 }
1f310bde 3529 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 3530}
3531
3532/*
3533 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 3534 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 3535 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
3536 * it for some reason. *tmpdevice is the target we're adding,
3537 * this_device is a pointer into the current element of currentsd[]
3538 * that we're building up in update_scsi_devices(), below.
3539 * lunzerobits is a bitmap that tracks which targets already have a
3540 * lun 0 assigned.
3541 * Returns 1 if an enclosure was added, 0 if not.
3542 */
4f4eb9f1 3543static int add_ext_target_dev(struct ctlr_info *h,
edd16368 3544 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 3545 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 3546 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 3547{
3548 unsigned char scsi3addr[8];
3549
1f310bde 3550 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 3551 return 0; /* There is already a lun 0 on this target. */
3552
3553 if (!is_logical_dev_addr_mode(lunaddrbytes))
3554 return 0; /* It's the logical targets that may lack lun 0. */
3555
4f4eb9f1
ST		 3556 if (!is_ext_target(h, tmpdevice))
3557 return 0; /* Only external target devices have this problem. */
edd16368 3558
1f310bde 3559 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 3560 return 0;
3561
c4f8a299 3562 memset(scsi3addr, 0, 8);
1f310bde 3563 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 3564 if (is_hba_lunid(scsi3addr))
3565 return 0; /* Don't add the RAID controller here. */
3566
339b2b14
SC		 3567 if (is_scsi_rev_5(h))
3568 return 0; /* p1210m doesn't need to do this. */
3569
4f4eb9f1 3570 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 3571 dev_warn(&h->pdev->dev, "Maximum number of external "
3572 "target devices exceeded. Check your hardware "
edd16368
SC		 3573 "configuration.");
3574 return 0;
3575 }
3576
0b0e1d6c 3577 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 3578 return 0;
4f4eb9f1 3579 (*n_ext_target_devs)++;
1f310bde
SC		 3580 hpsa_set_bus_target_lun(this_device,
3581 tmpdevice->bus, tmpdevice->target, 0);
9b5c48c2 3582 hpsa_update_device_supports_aborts(h, this_device, scsi3addr);
1f310bde 3583 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 3584 return 1;
3585}
3586
54b6e9e9
ST		 3587/*
3588 * Get address of physical disk used for an ioaccel2 mode command:
3589 * 1. Extract ioaccel2 handle from the command.
3590 * 2. Find a matching ioaccel2 handle from list of physical disks.
3591 * 3. Return:
3592 * 1 and set scsi3addr to address of matching physical
3593 * 0 if no matching physical disk was found.
3594 */
3595static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
3596 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
3597{
41ce4c35
SC		 3598 struct io_accel2_cmd *c2 =
3599 &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
3600 unsigned long flags;
54b6e9e9 3601 int i;
54b6e9e9 3602
41ce4c35
SC		 3603 spin_lock_irqsave(&h->devlock, flags);
3604 for (i = 0; i < h->ndevices; i++)
3605 if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
3606 memcpy(scsi3addr, h->dev[i]->scsi3addr,
3607 sizeof(h->dev[i]->scsi3addr));
3608 spin_unlock_irqrestore(&h->devlock, flags);
3609 return 1;
3610 }
3611 spin_unlock_irqrestore(&h->devlock, flags);
3612 return 0;
54b6e9e9 3613}
41ce4c35 3614
edd16368
SC		 3615/*
3616 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
3617 * logdev. The number of luns in physdev and logdev are returned in
3618 * *nphysicals and *nlogicals, respectively.
3619 * Returns 0 on success, -1 otherwise.
3620 */
3621static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 3622 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 3623 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 3624{
03383736 3625 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 3626 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3627 return -1;
3628 }
03383736 3629 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 3630 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 3631 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
3632 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 3633 *nphysicals = HPSA_MAX_PHYS_LUN;
3634 }
03383736 3635 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 3636 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
3637 return -1;
3638 }
6df1e954 3639 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 3640 /* Reject Logicals in excess of our max capability. */
3641 if (*nlogicals > HPSA_MAX_LUN) {
3642 dev_warn(&h->pdev->dev,
3643 "maximum logical LUNs (%d) exceeded. "
3644 "%d LUNs ignored.\n", HPSA_MAX_LUN,
3645 *nlogicals - HPSA_MAX_LUN);
3646 *nlogicals = HPSA_MAX_LUN;
3647 }
3648 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
3649 dev_warn(&h->pdev->dev,
3650 "maximum logical + physical LUNs (%d) exceeded. "
3651 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
3652 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
3653 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
3654 }
3655 return 0;
3656}
3657
42a91641
DB		 3658static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
3659 int i, int nphysicals, int nlogicals,
a93aa1fe 3660 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 3661 struct ReportLUNdata *logdev_list)
3662{
3663 /* Helper function, figure out where the LUN ID info is coming from
3664 * given index i, lists of physical and logical devices, where in
3665 * the list the raid controller is supposed to appear (first or last)
3666 */
3667
3668 int logicals_start = nphysicals + (raid_ctlr_position == 0);
3669 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
3670
3671 if (i == raid_ctlr_position)
3672 return RAID_CTLR_LUNID;
3673
3674 if (i < logicals_start)
d5b5d964
SC		 3675 return &physdev_list->LUN[i -
3676 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 3677
3678 if (i < last_device)
3679 return &logdev_list->LUN[i - nphysicals -
3680 (raid_ctlr_position == 0)][0];
3681 BUG();
3682 return NULL;
3683}
3684
03383736
DB		 3685/* get physical drive ioaccel handle and queue depth */
3686static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
3687 struct hpsa_scsi_dev_t *dev,
f2039b03 3688 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 3689 struct bmic_identify_physical_device *id_phys)
3690{
3691 int rc;
f2039b03 3692 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
03383736
DB		 3693
3694 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 3695 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 3696 dev->hba_ioaccel_enabled = 1;
03383736 3697 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 3698 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
3699 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 3700 sizeof(*id_phys));
3701 if (!rc)
3702 /* Reserve space for FW operations */
3703#define DRIVE_CMDS_RESERVED_FOR_FW 2
3704#define DRIVE_QUEUE_DEPTH 7
3705 dev->queue_depth =
3706 le16_to_cpu(id_phys->current_queue_depth_limit) -
3707 DRIVE_CMDS_RESERVED_FOR_FW;
3708 else
3709 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 3710}
3711
8270b862 3712static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 3713 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 3714 struct bmic_identify_physical_device *id_phys)
3715{
f2039b03
DB		 3716 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3717
3718 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 3719 this_device->hba_ioaccel_enabled = 1;
3720
3721 memcpy(&this_device->active_path_index,
3722 &id_phys->active_path_number,
3723 sizeof(this_device->active_path_index));
3724 memcpy(&this_device->path_map,
3725 &id_phys->redundant_path_present_map,
3726 sizeof(this_device->path_map));
3727 memcpy(&this_device->box,
3728 &id_phys->alternate_paths_phys_box_on_port,
3729 sizeof(this_device->box));
3730 memcpy(&this_device->phys_connector,
3731 &id_phys->alternate_paths_phys_connector,
3732 sizeof(this_device->phys_connector));
3733 memcpy(&this_device->bay,
3734 &id_phys->phys_bay_in_box,
3735 sizeof(this_device->bay));
3736}
3737
8aa60681 3738static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 3739{
3740 /* the idea here is we could get notified
3741 * that some devices have changed, so we do a report
3742 * physical luns and report logical luns cmd, and adjust
3743 * our list of devices accordingly.
3744 *
3745 * The scsi3addr's of devices won't change so long as the
3746 * adapter is not reset. That means we can rescan and
3747 * tell which devices we already know about, vs. new
3748 * devices, vs. disappearing devices.
3749 */
a93aa1fe 3750 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 3751 struct ReportLUNdata *logdev_list = NULL;
03383736 3752 struct bmic_identify_physical_device *id_phys = NULL;
01a02ffc
SC		 3753 u32 nphysicals = 0;
3754 u32 nlogicals = 0;
3755 u32 ndev_allocated = 0;
edd16368
SC		 3756 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
3757 int ncurrent = 0;
4f4eb9f1 3758 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 3759 int raid_ctlr_position;
04fa2f44 3760 bool physical_device;
aca4a520 3761 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 3762
cfe5badc 3763 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
92084715
SC		 3764 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
3765 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 3766 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 3767 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
edd16368 3768
03383736
DB		 3769 if (!currentsd || !physdev_list || !logdev_list ||
3770 !tmpdevice || !id_phys) {
edd16368
SC		 3771 dev_err(&h->pdev->dev, "out of memory\n");
3772 goto out;
3773 }
3774 memset(lunzerobits, 0, sizeof(lunzerobits));
3775
853633e8
DB		 3776 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
3777
03383736 3778 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 3779 logdev_list, &nlogicals)) {
3780 h->drv_req_rescan = 1;
edd16368 3781 goto out;
853633e8 3782 }
edd16368 3783
aca4a520
ST		 3784 /* We might see up to the maximum number of logical and physical disks
3785 * plus external target devices, and a device for the local RAID
3786 * controller.
edd16368 3787 */
aca4a520 3788 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 3789
3790 /* Allocate the per device structures */
3791 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 3792 if (i >= HPSA_MAX_DEVICES) {
3793 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
3794 " %d devices ignored.\n", HPSA_MAX_DEVICES,
3795 ndevs_to_allocate - HPSA_MAX_DEVICES);
3796 break;
3797 }
3798
edd16368
SC		 3799 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
3800 if (!currentsd[i]) {
3801 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
3802 __FILE__, __LINE__);
853633e8 3803 h->drv_req_rescan = 1;
edd16368
SC		 3804 goto out;
3805 }
3806 ndev_allocated++;
3807 }
3808
8645291b 3809 if (is_scsi_rev_5(h))
339b2b14
SC		 3810 raid_ctlr_position = 0;
3811 else
3812 raid_ctlr_position = nphysicals + nlogicals;
3813
edd16368 3814 /* adjust our table of devices */
4f4eb9f1 3815 n_ext_target_devs = 0;
edd16368 3816 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 3817 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 3818 int rc = 0;
f2039b03 3819 int phys_dev_index = i - (raid_ctlr_position == 0);
edd16368 3820
04fa2f44
KB		 3821 physical_device = i < nphysicals + (raid_ctlr_position == 0);
3822
edd16368 3823 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 3824 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
3825 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35
SC		 3826
3827 /* skip masked non-disk devices */
04fa2f44
KB		 3828 if (MASKED_DEVICE(lunaddrbytes) && physical_device &&
3829 (physdev_list->LUN[phys_dev_index].device_flags & 0x01))
3830 continue;
edd16368
SC		 3831
3832 /* Get device type, vendor, model, device id */
683fc444
DB		 3833 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
3834 &is_OBDR);
3835 if (rc == -ENOMEM) {
3836 dev_warn(&h->pdev->dev,
3837 "Out of memory, rescan deferred.\n");
853633e8 3838 h->drv_req_rescan = 1;
683fc444 3839 goto out;
853633e8 3840 }
683fc444
DB		 3841 if (rc) {
3842 dev_warn(&h->pdev->dev,
3843 "Inquiry failed, skipping device.\n");
3844 continue;
3845 }
3846
1f310bde 3847 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
9b5c48c2 3848 hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
edd16368
SC		 3849 this_device = currentsd[ncurrent];
3850
3851 /*
4f4eb9f1 3852 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 3853 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
3854 * is nonetheless an enclosure device there. We have to
3855 * present that otherwise linux won't find anything if
3856 * there is no lun 0.
3857 */
4f4eb9f1 3858 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 3859 lunaddrbytes, lunzerobits,
4f4eb9f1 3860 &n_ext_target_devs)) {
edd16368
SC		 3861 ncurrent++;
3862 this_device = currentsd[ncurrent];
3863 }
3864
3865 *this_device = *tmpdevice;
04fa2f44 3866 this_device->physical_device = physical_device;
edd16368 3867
04fa2f44
KB		 3868 /*
3869 * Expose all devices except for physical devices that
3870 * are masked.
3871 */
3872 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 3873 this_device->expose_device = 0;
3874 else
3875 this_device->expose_device = 1;
41ce4c35 3876
edd16368 3877 switch (this_device->devtype) {
0b0e1d6c 3878 case TYPE_ROM:
edd16368
SC		 3879 /* We don't *really* support actual CD-ROM devices,
3880 * just "One Button Disaster Recovery" tape drive
3881 * which temporarily pretends to be a CD-ROM drive.
3882 * So we check that the device is really an OBDR tape
3883 * device by checking for "$DR-10" in bytes 43-48 of
3884 * the inquiry data.
3885 */
0b0e1d6c
SC		 3886 if (is_OBDR)
3887 ncurrent++;
edd16368
SC		 3888 break;
3889 case TYPE_DISK:
04fa2f44 3890 if (this_device->physical_device) {
b9092b79
KB		 3891 /* The disk is in HBA mode. */
3892 /* Never use RAID mapper in HBA mode. */
ecf418d1 3893 this_device->offload_enabled = 0;
b9092b79 3894 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 3895 physdev_list, phys_dev_index, id_phys);
3896 hpsa_get_path_info(this_device,
3897 physdev_list, phys_dev_index, id_phys);
b9092b79 3898 }
ecf418d1 3899 ncurrent++;
edd16368
SC		 3900 break;
3901 case TYPE_TAPE:
3902 case TYPE_MEDIUM_CHANGER:
41ce4c35 3903 case TYPE_ENCLOSURE:
b9092b79 3904 ncurrent++;
41ce4c35 3905 break;
edd16368
SC		 3906 case TYPE_RAID:
3907 /* Only present the Smartarray HBA as a RAID controller.
3908 * If it's a RAID controller other than the HBA itself
3909 * (an external RAID controller, MSA500 or similar)
3910 * don't present it.
3911 */
3912 if (!is_hba_lunid(lunaddrbytes))
3913 break;
3914 ncurrent++;
3915 break;
3916 default:
3917 break;
3918 }
cfe5badc 3919 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 3920 break;
3921 }
8aa60681 3922 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 3923out:
3924 kfree(tmpdevice);
3925 for (i = 0; i < ndev_allocated; i++)
3926 kfree(currentsd[i]);
3927 kfree(currentsd);
edd16368
SC		 3928 kfree(physdev_list);
3929 kfree(logdev_list);
03383736 3930 kfree(id_phys);
edd16368
SC		 3931}
3932
ec5cbf04
WS		 3933static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
3934 struct scatterlist *sg)
3935{
3936 u64 addr64 = (u64) sg_dma_address(sg);
3937 unsigned int len = sg_dma_len(sg);
3938
3939 desc->Addr = cpu_to_le64(addr64);
3940 desc->Len = cpu_to_le32(len);
3941 desc->Ext = 0;
3942}
3943
c7ee65b3
WS		 3944/*
3945 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 3946 * dma mapping and fills in the scatter gather entries of the
3947 * hpsa command, cp.
3948 */
33a2ffce 3949static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 3950 struct CommandList *cp,
3951 struct scsi_cmnd *cmd)
3952{
edd16368 3953 struct scatterlist *sg;
b3a7ba7c 3954 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 3955 struct SGDescriptor *curr_sg;
edd16368 3956
33a2ffce 3957 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 3958
3959 use_sg = scsi_dma_map(cmd);
3960 if (use_sg < 0)
3961 return use_sg;
3962
3963 if (!use_sg)
3964 goto sglist_finished;
3965
b3a7ba7c
WS		 3966 /*
3967 * If the number of entries is greater than the max for a single list,
3968 * then we have a chained list; we will set up all but one entry in the
3969 * first list (the last entry is saved for link information);
3970 * otherwise, we don't have a chained list and we'll set up at each of
3971 * the entries in the one list.
3972 */
33a2ffce 3973 curr_sg = cp->SG;
b3a7ba7c
WS		 3974 chained = use_sg > h->max_cmd_sg_entries;
3975 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
3976 last_sg = scsi_sg_count(cmd) - 1;
3977 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 3978 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 3979 curr_sg++;
3980 }
ec5cbf04 3981
b3a7ba7c
WS		 3982 if (chained) {
3983 /*
3984 * Continue with the chained list. Set curr_sg to the chained
3985 * list. Modify the limit to the total count less the entries
3986 * we've already set up. Resume the scan at the list entry
3987 * where the previous loop left off.
3988 */
3989 curr_sg = h->cmd_sg_list[cp->cmdindex];
3990 sg_limit = use_sg - sg_limit;
3991 for_each_sg(sg, sg, sg_limit, i) {
3992 hpsa_set_sg_descriptor(curr_sg, sg);
3993 curr_sg++;
3994 }
3995 }
3996
ec5cbf04 3997 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 3998 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 3999
4000 if (use_sg + chained > h->maxSG)
4001 h->maxSG = use_sg + chained;
4002
4003 if (chained) {
4004 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4005 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4006 if (hpsa_map_sg_chain_block(h, cp)) {
4007 scsi_dma_unmap(cmd);
4008 return -1;
4009 }
33a2ffce 4010 return 0;
edd16368
SC		 4011 }
4012
4013sglist_finished:
4014
01a02ffc 4015 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4016 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4017 return 0;
4018}
4019
283b4a9b
SC		 4020#define IO_ACCEL_INELIGIBLE (1)
4021static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4022{
4023 int is_write = 0;
4024 u32 block;
4025 u32 block_cnt;
4026
4027 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4028 switch (cdb[0]) {
4029 case WRITE_6:
4030 case WRITE_12:
4031 is_write = 1;
4032 case READ_6:
4033 case READ_12:
4034 if (*cdb_len == 6) {
c8a6c9a6 4035 block = get_unaligned_be16(&cdb[2]);
283b4a9b 4036 block_cnt = cdb[4];
c8a6c9a6
DB		 4037 if (block_cnt == 0)
4038 block_cnt = 256;
283b4a9b
SC		 4039 } else {
4040 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4041 block = get_unaligned_be32(&cdb[2]);
4042 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4043 }
4044 if (block_cnt > 0xffff)
4045 return IO_ACCEL_INELIGIBLE;
4046
4047 cdb[0] = is_write ? WRITE_10 : READ_10;
4048 cdb[1] = 0;
4049 cdb[2] = (u8) (block >> 24);
4050 cdb[3] = (u8) (block >> 16);
4051 cdb[4] = (u8) (block >> 8);
4052 cdb[5] = (u8) (block);
4053 cdb[6] = 0;
4054 cdb[7] = (u8) (block_cnt >> 8);
4055 cdb[8] = (u8) (block_cnt);
4056 cdb[9] = 0;
4057 *cdb_len = 10;
4058 break;
4059 }
4060 return 0;
4061}
4062
c349775e 4063static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4064 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4065 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4066{
4067 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4068 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4069 unsigned int len;
4070 unsigned int total_len = 0;
4071 struct scatterlist *sg;
4072 u64 addr64;
4073 int use_sg, i;
4074 struct SGDescriptor *curr_sg;
4075 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4076
283b4a9b 4077 /* TODO: implement chaining support */
03383736
DB		 4078 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4079 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4080 return IO_ACCEL_INELIGIBLE;
03383736 4081 }
283b4a9b 4082
e1f7de0c
MG		 4083 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4084
03383736
DB		 4085 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4086 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4087 return IO_ACCEL_INELIGIBLE;
03383736 4088 }
283b4a9b 4089
e1f7de0c
MG		 4090 c->cmd_type = CMD_IOACCEL1;
4091
4092 /* Adjust the DMA address to point to the accelerated command buffer */
4093 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4094 (c->cmdindex * sizeof(*cp));
4095 BUG_ON(c->busaddr & 0x0000007F);
4096
4097 use_sg = scsi_dma_map(cmd);
03383736
DB		 4098 if (use_sg < 0) {
4099 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4100 return use_sg;
03383736 4101 }
e1f7de0c
MG		 4102
4103 if (use_sg) {
4104 curr_sg = cp->SG;
4105 scsi_for_each_sg(cmd, sg, use_sg, i) {
4106 addr64 = (u64) sg_dma_address(sg);
4107 len = sg_dma_len(sg);
4108 total_len += len;
50a0decf
SC		 4109 curr_sg->Addr = cpu_to_le64(addr64);
4110 curr_sg->Len = cpu_to_le32(len);
4111 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4112 curr_sg++;
4113 }
50a0decf 4114 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4115
4116 switch (cmd->sc_data_direction) {
4117 case DMA_TO_DEVICE:
4118 control |= IOACCEL1_CONTROL_DATA_OUT;
4119 break;
4120 case DMA_FROM_DEVICE:
4121 control |= IOACCEL1_CONTROL_DATA_IN;
4122 break;
4123 case DMA_NONE:
4124 control |= IOACCEL1_CONTROL_NODATAXFER;
4125 break;
4126 default:
4127 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4128 cmd->sc_data_direction);
4129 BUG();
4130 break;
4131 }
4132 } else {
4133 control |= IOACCEL1_CONTROL_NODATAXFER;
4134 }
4135
c349775e 4136 c->Header.SGList = use_sg;
e1f7de0c 4137 /* Fill out the command structure to submit */
2b08b3e9
DB		 4138 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4139 cp->transfer_len = cpu_to_le32(total_len);
4140 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4141 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4142 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4143 memcpy(cp->CDB, cdb, cdb_len);
4144 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4145 /* Tag was already set at init time. */
283b4a9b 4146 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4147 return 0;
4148}
edd16368 4149
283b4a9b
SC		 4150/*
4151 * Queue a command directly to a device behind the controller using the
4152 * I/O accelerator path.
4153 */
4154static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4155 struct CommandList *c)
4156{
4157 struct scsi_cmnd *cmd = c->scsi_cmd;
4158 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4159
03383736
DB		 4160 c->phys_disk = dev;
4161
283b4a9b 4162 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4163 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4164}
4165
dd0e19f3
ST		 4166/*
4167 * Set encryption parameters for the ioaccel2 request
4168 */
4169static void set_encrypt_ioaccel2(struct ctlr_info *h,
4170 struct CommandList *c, struct io_accel2_cmd *cp)
4171{
4172 struct scsi_cmnd *cmd = c->scsi_cmd;
4173 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4174 struct raid_map_data *map = &dev->raid_map;
4175 u64 first_block;
4176
dd0e19f3 4177 /* Are we doing encryption on this device */
2b08b3e9 4178 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4179 return;
4180 /* Set the data encryption key index. */
4181 cp->dekindex = map->dekindex;
4182
4183 /* Set the encryption enable flag, encoded into direction field. */
4184 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4185
4186 /* Set encryption tweak values based on logical block address
4187 * If block size is 512, tweak value is LBA.
4188 * For other block sizes, tweak is (LBA * block size)/ 512)
4189 */
4190 switch (cmd->cmnd[0]) {
4191 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
4192 case WRITE_6:
4193 case READ_6:
2b08b3e9 4194 first_block = get_unaligned_be16(&cmd->cmnd[2]);
dd0e19f3
ST		 4195 break;
4196 case WRITE_10:
4197 case READ_10:
dd0e19f3
ST		 4198 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4199 case WRITE_12:
4200 case READ_12:
2b08b3e9 4201 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4202 break;
4203 case WRITE_16:
4204 case READ_16:
2b08b3e9 4205 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4206 break;
4207 default:
4208 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4209 "ERROR: %s: size (0x%x) not supported for encryption\n",
4210 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4211 BUG();
4212 break;
4213 }
2b08b3e9
DB		 4214
4215 if (le32_to_cpu(map->volume_blk_size) != 512)
4216 first_block = first_block *
4217 le32_to_cpu(map->volume_blk_size)/512;
4218
4219 cp->tweak_lower = cpu_to_le32(first_block);
4220 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4221}
4222
c349775e
ST		 4223static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4224 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4225 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4226{
4227 struct scsi_cmnd *cmd = c->scsi_cmd;
4228 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4229 struct ioaccel2_sg_element *curr_sg;
4230 int use_sg, i;
4231 struct scatterlist *sg;
4232 u64 addr64;
4233 u32 len;
4234 u32 total_len = 0;
4235
d9a729f3 4236 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4237
03383736
DB		 4238 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4239 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4240 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4241 }
4242
c349775e
ST		 4243 c->cmd_type = CMD_IOACCEL2;
4244 /* Adjust the DMA address to point to the accelerated command buffer */
4245 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4246 (c->cmdindex * sizeof(*cp));
4247 BUG_ON(c->busaddr & 0x0000007F);
4248
4249 memset(cp, 0, sizeof(*cp));
4250 cp->IU_type = IOACCEL2_IU_TYPE;
4251
4252 use_sg = scsi_dma_map(cmd);
03383736
DB		 4253 if (use_sg < 0) {
4254 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4255 return use_sg;
03383736 4256 }
c349775e
ST		 4257
4258 if (use_sg) {
c349775e 4259 curr_sg = cp->sg;
d9a729f3
WS		 4260 if (use_sg > h->ioaccel_maxsg) {
4261 addr64 = le64_to_cpu(
4262 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4263 curr_sg->address = cpu_to_le64(addr64);
4264 curr_sg->length = 0;
4265 curr_sg->reserved[0] = 0;
4266 curr_sg->reserved[1] = 0;
4267 curr_sg->reserved[2] = 0;
4268 curr_sg->chain_indicator = 0x80;
4269
4270 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4271 }
c349775e
ST		 4272 scsi_for_each_sg(cmd, sg, use_sg, i) {
4273 addr64 = (u64) sg_dma_address(sg);
4274 len = sg_dma_len(sg);
4275 total_len += len;
4276 curr_sg->address = cpu_to_le64(addr64);
4277 curr_sg->length = cpu_to_le32(len);
4278 curr_sg->reserved[0] = 0;
4279 curr_sg->reserved[1] = 0;
4280 curr_sg->reserved[2] = 0;
4281 curr_sg->chain_indicator = 0;
4282 curr_sg++;
4283 }
4284
4285 switch (cmd->sc_data_direction) {
4286 case DMA_TO_DEVICE:
dd0e19f3
ST		 4287 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4288 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4289 break;
4290 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4291 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4292 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4293 break;
4294 case DMA_NONE:
dd0e19f3
ST		 4295 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4296 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4297 break;
4298 default:
4299 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4300 cmd->sc_data_direction);
4301 BUG();
4302 break;
4303 }
4304 } else {
dd0e19f3
ST		 4305 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4306 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4307 }
dd0e19f3
ST		 4308
4309 /* Set encryption parameters, if necessary */
4310 set_encrypt_ioaccel2(h, c, cp);
4311
2b08b3e9 4312 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4313 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4314 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4315
c349775e
ST		 4316 cp->data_len = cpu_to_le32(total_len);
4317 cp->err_ptr = cpu_to_le64(c->busaddr +
4318 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4319 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4320
d9a729f3
WS		 4321 /* fill in sg elements */
4322 if (use_sg > h->ioaccel_maxsg) {
4323 cp->sg_count = 1;
a736e9b6 4324 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 4325 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
4326 atomic_dec(&phys_disk->ioaccel_cmds_out);
4327 scsi_dma_unmap(cmd);
4328 return -1;
4329 }
4330 } else
4331 cp->sg_count = (u8) use_sg;
4332
c349775e
ST		 4333 enqueue_cmd_and_start_io(h, c);
4334 return 0;
4335}
4336
4337/*
4338 * Queue a command to the correct I/O accelerator path.
4339 */
4340static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
4341 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4342 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 4343{
03383736
DB		 4344 /* Try to honor the device's queue depth */
4345 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
4346 phys_disk->queue_depth) {
4347 atomic_dec(&phys_disk->ioaccel_cmds_out);
4348 return IO_ACCEL_INELIGIBLE;
4349 }
c349775e
ST		 4350 if (h->transMethod & CFGTBL_Trans_io_accel1)
4351 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 4352 cdb, cdb_len, scsi3addr,
4353 phys_disk);
c349775e
ST		 4354 else
4355 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 4356 cdb, cdb_len, scsi3addr,
4357 phys_disk);
c349775e
ST		 4358}
4359
6b80b18f
ST		 4360static void raid_map_helper(struct raid_map_data *map,
4361 int offload_to_mirror, u32 *map_index, u32 *current_group)
4362{
4363 if (offload_to_mirror == 0) {
4364 /* use physical disk in the first mirrored group. */
2b08b3e9 4365 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4366 return;
4367 }
4368 do {
4369 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 4370 *current_group = *map_index /
4371 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4372 if (offload_to_mirror == *current_group)
4373 continue;
2b08b3e9 4374 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 4375 /* select map index from next group */
2b08b3e9 4376 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4377 (*current_group)++;
4378 } else {
4379 /* select map index from first group */
2b08b3e9 4380 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 4381 *current_group = 0;
4382 }
4383 } while (offload_to_mirror != *current_group);
4384}
4385
283b4a9b
SC		 4386/*
4387 * Attempt to perform offload RAID mapping for a logical volume I/O.
4388 */
4389static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
4390 struct CommandList *c)
4391{
4392 struct scsi_cmnd *cmd = c->scsi_cmd;
4393 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4394 struct raid_map_data *map = &dev->raid_map;
4395 struct raid_map_disk_data *dd = &map->data[0];
4396 int is_write = 0;
4397 u32 map_index;
4398 u64 first_block, last_block;
4399 u32 block_cnt;
4400 u32 blocks_per_row;
4401 u64 first_row, last_row;
4402 u32 first_row_offset, last_row_offset;
4403 u32 first_column, last_column;
6b80b18f
ST		 4404 u64 r0_first_row, r0_last_row;
4405 u32 r5or6_blocks_per_row;
4406 u64 r5or6_first_row, r5or6_last_row;
4407 u32 r5or6_first_row_offset, r5or6_last_row_offset;
4408 u32 r5or6_first_column, r5or6_last_column;
4409 u32 total_disks_per_row;
4410 u32 stripesize;
4411 u32 first_group, last_group, current_group;
283b4a9b
SC		 4412 u32 map_row;
4413 u32 disk_handle;
4414 u64 disk_block;
4415 u32 disk_block_cnt;
4416 u8 cdb[16];
4417 u8 cdb_len;
2b08b3e9 4418 u16 strip_size;
283b4a9b
SC		 4419#if BITS_PER_LONG == 32
4420 u64 tmpdiv;
4421#endif
6b80b18f 4422 int offload_to_mirror;
283b4a9b 4423
283b4a9b
SC		 4424 /* check for valid opcode, get LBA and block count */
4425 switch (cmd->cmnd[0]) {
4426 case WRITE_6:
4427 is_write = 1;
4428 case READ_6:
c8a6c9a6 4429 first_block = get_unaligned_be16(&cmd->cmnd[2]);
283b4a9b 4430 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 4431 if (block_cnt == 0)
4432 block_cnt = 256;
283b4a9b
SC		 4433 break;
4434 case WRITE_10:
4435 is_write = 1;
4436 case READ_10:
4437 first_block =
4438 (((u64) cmd->cmnd[2]) << 24) |
4439 (((u64) cmd->cmnd[3]) << 16) |
4440 (((u64) cmd->cmnd[4]) << 8) |
4441 cmd->cmnd[5];
4442 block_cnt =
4443 (((u32) cmd->cmnd[7]) << 8) |
4444 cmd->cmnd[8];
4445 break;
4446 case WRITE_12:
4447 is_write = 1;
4448 case READ_12:
4449 first_block =
4450 (((u64) cmd->cmnd[2]) << 24) |
4451 (((u64) cmd->cmnd[3]) << 16) |
4452 (((u64) cmd->cmnd[4]) << 8) |
4453 cmd->cmnd[5];
4454 block_cnt =
4455 (((u32) cmd->cmnd[6]) << 24) |
4456 (((u32) cmd->cmnd[7]) << 16) |
4457 (((u32) cmd->cmnd[8]) << 8) |
4458 cmd->cmnd[9];
4459 break;
4460 case WRITE_16:
4461 is_write = 1;
4462 case READ_16:
4463 first_block =
4464 (((u64) cmd->cmnd[2]) << 56) |
4465 (((u64) cmd->cmnd[3]) << 48) |
4466 (((u64) cmd->cmnd[4]) << 40) |
4467 (((u64) cmd->cmnd[5]) << 32) |
4468 (((u64) cmd->cmnd[6]) << 24) |
4469 (((u64) cmd->cmnd[7]) << 16) |
4470 (((u64) cmd->cmnd[8]) << 8) |
4471 cmd->cmnd[9];
4472 block_cnt =
4473 (((u32) cmd->cmnd[10]) << 24) |
4474 (((u32) cmd->cmnd[11]) << 16) |
4475 (((u32) cmd->cmnd[12]) << 8) |
4476 cmd->cmnd[13];
4477 break;
4478 default:
4479 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
4480 }
283b4a9b
SC		 4481 last_block = first_block + block_cnt - 1;
4482
4483 /* check for write to non-RAID-0 */
4484 if (is_write && dev->raid_level != 0)
4485 return IO_ACCEL_INELIGIBLE;
4486
4487 /* check for invalid block or wraparound */
2b08b3e9
DB		 4488 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
4489 last_block < first_block)
283b4a9b
SC		 4490 return IO_ACCEL_INELIGIBLE;
4491
4492 /* calculate stripe information for the request */
2b08b3e9
DB		 4493 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
4494 le16_to_cpu(map->strip_size);
4495 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 4496#if BITS_PER_LONG == 32
4497 tmpdiv = first_block;
4498 (void) do_div(tmpdiv, blocks_per_row);
4499 first_row = tmpdiv;
4500 tmpdiv = last_block;
4501 (void) do_div(tmpdiv, blocks_per_row);
4502 last_row = tmpdiv;
4503 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4504 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
4505 tmpdiv = first_row_offset;
2b08b3e9 4506 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4507 first_column = tmpdiv;
4508 tmpdiv = last_row_offset;
2b08b3e9 4509 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 4510 last_column = tmpdiv;
4511#else
4512 first_row = first_block / blocks_per_row;
4513 last_row = last_block / blocks_per_row;
4514 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
4515 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 4516 first_column = first_row_offset / strip_size;
4517 last_column = last_row_offset / strip_size;
283b4a9b
SC		 4518#endif
4519
4520 /* if this isn't a single row/column then give to the controller */
4521 if ((first_row != last_row) || (first_column != last_column))
4522 return IO_ACCEL_INELIGIBLE;
4523
4524 /* proceeding with driver mapping */
2b08b3e9
DB		 4525 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
4526 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 4527 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4528 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4529 map_index = (map_row * total_disks_per_row) + first_column;
4530
4531 switch (dev->raid_level) {
4532 case HPSA_RAID_0:
4533 break; /* nothing special to do */
4534 case HPSA_RAID_1:
4535 /* Handles load balance across RAID 1 members.
4536 * (2-drive R1 and R10 with even # of drives.)
4537 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 4538 */
2b08b3e9 4539 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 4540 if (dev->offload_to_mirror)
2b08b3e9 4541 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 4542 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 4543 break;
4544 case HPSA_RAID_ADM:
4545 /* Handles N-way mirrors (R1-ADM)
4546 * and R10 with # of drives divisible by 3.)
4547 */
2b08b3e9 4548 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 4549
4550 offload_to_mirror = dev->offload_to_mirror;
4551 raid_map_helper(map, offload_to_mirror,
4552 &map_index, &current_group);
4553 /* set mirror group to use next time */
4554 offload_to_mirror =
2b08b3e9
DB		 4555 (offload_to_mirror >=
4556 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 4557 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 4558 dev->offload_to_mirror = offload_to_mirror;
4559 /* Avoid direct use of dev->offload_to_mirror within this
4560 * function since multiple threads might simultaneously
4561 * increment it beyond the range of dev->layout_map_count -1.
4562 */
4563 break;
4564 case HPSA_RAID_5:
4565 case HPSA_RAID_6:
2b08b3e9 4566 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 4567 break;
4568
4569 /* Verify first and last block are in same RAID group */
4570 r5or6_blocks_per_row =
2b08b3e9
DB		 4571 le16_to_cpu(map->strip_size) *
4572 le16_to_cpu(map->data_disks_per_row);
6b80b18f 4573 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 4574 stripesize = r5or6_blocks_per_row *
4575 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 4576#if BITS_PER_LONG == 32
4577 tmpdiv = first_block;
4578 first_group = do_div(tmpdiv, stripesize);
4579 tmpdiv = first_group;
4580 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4581 first_group = tmpdiv;
4582 tmpdiv = last_block;
4583 last_group = do_div(tmpdiv, stripesize);
4584 tmpdiv = last_group;
4585 (void) do_div(tmpdiv, r5or6_blocks_per_row);
4586 last_group = tmpdiv;
4587#else
4588 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
4589 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 4590#endif
000ff7c2 4591 if (first_group != last_group)
6b80b18f
ST		 4592 return IO_ACCEL_INELIGIBLE;
4593
4594 /* Verify request is in a single row of RAID 5/6 */
4595#if BITS_PER_LONG == 32
4596 tmpdiv = first_block;
4597 (void) do_div(tmpdiv, stripesize);
4598 first_row = r5or6_first_row = r0_first_row = tmpdiv;
4599 tmpdiv = last_block;
4600 (void) do_div(tmpdiv, stripesize);
4601 r5or6_last_row = r0_last_row = tmpdiv;
4602#else
4603 first_row = r5or6_first_row = r0_first_row =
4604 first_block / stripesize;
4605 r5or6_last_row = r0_last_row = last_block / stripesize;
4606#endif
4607 if (r5or6_first_row != r5or6_last_row)
4608 return IO_ACCEL_INELIGIBLE;
4609
4610
4611 /* Verify request is in a single column */
4612#if BITS_PER_LONG == 32
4613 tmpdiv = first_block;
4614 first_row_offset = do_div(tmpdiv, stripesize);
4615 tmpdiv = first_row_offset;
4616 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
4617 r5or6_first_row_offset = first_row_offset;
4618 tmpdiv = last_block;
4619 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
4620 tmpdiv = r5or6_last_row_offset;
4621 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
4622 tmpdiv = r5or6_first_row_offset;
4623 (void) do_div(tmpdiv, map->strip_size);
4624 first_column = r5or6_first_column = tmpdiv;
4625 tmpdiv = r5or6_last_row_offset;
4626 (void) do_div(tmpdiv, map->strip_size);
4627 r5or6_last_column = tmpdiv;
4628#else
4629 first_row_offset = r5or6_first_row_offset =
4630 (u32)((first_block % stripesize) %
4631 r5or6_blocks_per_row);
4632
4633 r5or6_last_row_offset =
4634 (u32)((last_block % stripesize) %
4635 r5or6_blocks_per_row);
4636
4637 first_column = r5or6_first_column =
2b08b3e9 4638 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 4639 r5or6_last_column =
2b08b3e9 4640 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 4641#endif
4642 if (r5or6_first_column != r5or6_last_column)
4643 return IO_ACCEL_INELIGIBLE;
4644
4645 /* Request is eligible */
4646 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 4647 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 4648
4649 map_index = (first_group *
2b08b3e9 4650 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 4651 (map_row * total_disks_per_row) + first_column;
4652 break;
4653 default:
4654 return IO_ACCEL_INELIGIBLE;
283b4a9b 4655 }
6b80b18f 4656
07543e0c
SC		 4657 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
4658 return IO_ACCEL_INELIGIBLE;
4659
03383736
DB		 4660 c->phys_disk = dev->phys_disk[map_index];
4661
283b4a9b 4662 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 4663 disk_block = le64_to_cpu(map->disk_starting_blk) +
4664 first_row * le16_to_cpu(map->strip_size) +
4665 (first_row_offset - first_column *
4666 le16_to_cpu(map->strip_size));
283b4a9b
SC		 4667 disk_block_cnt = block_cnt;
4668
4669 /* handle differing logical/physical block sizes */
4670 if (map->phys_blk_shift) {
4671 disk_block <<= map->phys_blk_shift;
4672 disk_block_cnt <<= map->phys_blk_shift;
4673 }
4674 BUG_ON(disk_block_cnt > 0xffff);
4675
4676 /* build the new CDB for the physical disk I/O */
4677 if (disk_block > 0xffffffff) {
4678 cdb[0] = is_write ? WRITE_16 : READ_16;
4679 cdb[1] = 0;
4680 cdb[2] = (u8) (disk_block >> 56);
4681 cdb[3] = (u8) (disk_block >> 48);
4682 cdb[4] = (u8) (disk_block >> 40);
4683 cdb[5] = (u8) (disk_block >> 32);
4684 cdb[6] = (u8) (disk_block >> 24);
4685 cdb[7] = (u8) (disk_block >> 16);
4686 cdb[8] = (u8) (disk_block >> 8);
4687 cdb[9] = (u8) (disk_block);
4688 cdb[10] = (u8) (disk_block_cnt >> 24);
4689 cdb[11] = (u8) (disk_block_cnt >> 16);
4690 cdb[12] = (u8) (disk_block_cnt >> 8);
4691 cdb[13] = (u8) (disk_block_cnt);
4692 cdb[14] = 0;
4693 cdb[15] = 0;
4694 cdb_len = 16;
4695 } else {
4696 cdb[0] = is_write ? WRITE_10 : READ_10;
4697 cdb[1] = 0;
4698 cdb[2] = (u8) (disk_block >> 24);
4699 cdb[3] = (u8) (disk_block >> 16);
4700 cdb[4] = (u8) (disk_block >> 8);
4701 cdb[5] = (u8) (disk_block);
4702 cdb[6] = 0;
4703 cdb[7] = (u8) (disk_block_cnt >> 8);
4704 cdb[8] = (u8) (disk_block_cnt);
4705 cdb[9] = 0;
4706 cdb_len = 10;
4707 }
4708 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 4709 dev->scsi3addr,
4710 dev->phys_disk[map_index]);
283b4a9b
SC		 4711}
4712
25163bd5
WS		 4713/*
4714 * Submit commands down the "normal" RAID stack path
4715 * All callers to hpsa_ciss_submit must check lockup_detected
4716 * beforehand, before (opt.) and after calling cmd_alloc
4717 */
574f05d3
SC		 4718static int hpsa_ciss_submit(struct ctlr_info *h,
4719 struct CommandList *c, struct scsi_cmnd *cmd,
4720 unsigned char scsi3addr[])
edd16368 4721{
edd16368 4722 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 4723 c->cmd_type = CMD_SCSI;
4724 c->scsi_cmd = cmd;
4725 c->Header.ReplyQueue = 0; /* unused in simple mode */
4726 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 4727 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 4728
4729 /* Fill in the request block... */
4730
4731 c->Request.Timeout = 0;
edd16368
SC		 4732 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
4733 c->Request.CDBLen = cmd->cmd_len;
4734 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 4735 switch (cmd->sc_data_direction) {
4736 case DMA_TO_DEVICE:
a505b86f
SC		 4737 c->Request.type_attr_dir =
4738 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 4739 break;
4740 case DMA_FROM_DEVICE:
a505b86f
SC		 4741 c->Request.type_attr_dir =
4742 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 4743 break;
4744 case DMA_NONE:
a505b86f
SC		 4745 c->Request.type_attr_dir =
4746 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 4747 break;
4748 case DMA_BIDIRECTIONAL:
4749 /* This can happen if a buggy application does a scsi passthru
4750 * and sets both inlen and outlen to non-zero. ( see
4751 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
4752 */
4753
a505b86f
SC		 4754 c->Request.type_attr_dir =
4755 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 4756 /* This is technically wrong, and hpsa controllers should
4757 * reject it with CMD_INVALID, which is the most correct
4758 * response, but non-fibre backends appear to let it
4759 * slide by, and give the same results as if this field
4760 * were set correctly. Either way is acceptable for
4761 * our purposes here.
4762 */
4763
4764 break;
4765
4766 default:
4767 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4768 cmd->sc_data_direction);
4769 BUG();
4770 break;
4771 }
4772
33a2ffce 4773 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 4774 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 4775 return SCSI_MLQUEUE_HOST_BUSY;
4776 }
4777 enqueue_cmd_and_start_io(h, c);
4778 /* the cmd'll come back via intr handler in complete_scsi_command() */
4779 return 0;
4780}
4781
360c73bd
SC		 4782static void hpsa_cmd_init(struct ctlr_info *h, int index,
4783 struct CommandList *c)
4784{
4785 dma_addr_t cmd_dma_handle, err_dma_handle;
4786
4787 /* Zero out all of commandlist except the last field, refcount */
4788 memset(c, 0, offsetof(struct CommandList, refcount));
4789 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
4790 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4791 c->err_info = h->errinfo_pool + index;
4792 memset(c->err_info, 0, sizeof(*c->err_info));
4793 err_dma_handle = h->errinfo_pool_dhandle
4794 + index * sizeof(*c->err_info);
4795 c->cmdindex = index;
4796 c->busaddr = (u32) cmd_dma_handle;
4797 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
4798 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
4799 c->h = h;
a58e7e53 4800 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 4801}
4802
4803static void hpsa_preinitialize_commands(struct ctlr_info *h)
4804{
4805 int i;
4806
4807 for (i = 0; i < h->nr_cmds; i++) {
4808 struct CommandList *c = h->cmd_pool + i;
4809
4810 hpsa_cmd_init(h, i, c);
4811 atomic_set(&c->refcount, 0);
4812 }
4813}
4814
4815static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
4816 struct CommandList *c)
4817{
4818 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
4819
73153fe5
WS		 4820 BUG_ON(c->cmdindex != index);
4821
360c73bd
SC		 4822 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
4823 memset(c->err_info, 0, sizeof(*c->err_info));
4824 c->busaddr = (u32) cmd_dma_handle;
4825}
4826
592a0ad5
WS		 4827static int hpsa_ioaccel_submit(struct ctlr_info *h,
4828 struct CommandList *c, struct scsi_cmnd *cmd,
4829 unsigned char *scsi3addr)
4830{
4831 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4832 int rc = IO_ACCEL_INELIGIBLE;
4833
4834 cmd->host_scribble = (unsigned char *) c;
4835
4836 if (dev->offload_enabled) {
4837 hpsa_cmd_init(h, c->cmdindex, c);
4838 c->cmd_type = CMD_SCSI;
4839 c->scsi_cmd = cmd;
4840 rc = hpsa_scsi_ioaccel_raid_map(h, c);
4841 if (rc < 0) /* scsi_dma_map failed. */
4842 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 4843 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 4844 hpsa_cmd_init(h, c->cmdindex, c);
4845 c->cmd_type = CMD_SCSI;
4846 c->scsi_cmd = cmd;
4847 rc = hpsa_scsi_ioaccel_direct_map(h, c);
4848 if (rc < 0) /* scsi_dma_map failed. */
4849 rc = SCSI_MLQUEUE_HOST_BUSY;
4850 }
4851 return rc;
4852}
4853
080ef1cc
DB		 4854static void hpsa_command_resubmit_worker(struct work_struct *work)
4855{
4856 struct scsi_cmnd *cmd;
4857 struct hpsa_scsi_dev_t *dev;
8a0ff92c 4858 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 4859
4860 cmd = c->scsi_cmd;
4861 dev = cmd->device->hostdata;
4862 if (!dev) {
4863 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 4864 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 4865 }
d604f533
WS		 4866 if (c->reset_pending)
4867 return hpsa_cmd_resolve_and_free(c->h, c);
a58e7e53
WS		 4868 if (c->abort_pending)
4869 return hpsa_cmd_abort_and_free(c->h, c, cmd);
592a0ad5
WS		 4870 if (c->cmd_type == CMD_IOACCEL2) {
4871 struct ctlr_info *h = c->h;
4872 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
4873 int rc;
4874
4875 if (c2->error_data.serv_response ==
4876 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
4877 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
4878 if (rc == 0)
4879 return;
4880 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
4881 /*
4882 * If we get here, it means dma mapping failed.
4883 * Try again via scsi mid layer, which will
4884 * then get SCSI_MLQUEUE_HOST_BUSY.
4885 */
4886 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 4887 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 4888 }
4889 /* else, fall thru and resubmit down CISS path */
4890 }
4891 }
360c73bd 4892 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 4893 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
4894 /*
4895 * If we get here, it means dma mapping failed. Try
4896 * again via scsi mid layer, which will then get
4897 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 4898 *
4899 * hpsa_ciss_submit will have already freed c
4900 * if it encountered a dma mapping failure.
080ef1cc
DB		 4901 */
4902 cmd->result = DID_IMM_RETRY << 16;
4903 cmd->scsi_done(cmd);
4904 }
4905}
4906
574f05d3
SC		 4907/* Running in struct Scsi_Host->host_lock less mode */
4908static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
4909{
4910 struct ctlr_info *h;
4911 struct hpsa_scsi_dev_t *dev;
4912 unsigned char scsi3addr[8];
4913 struct CommandList *c;
4914 int rc = 0;
4915
4916 /* Get the ptr to our adapter structure out of cmd->host. */
4917 h = sdev_to_hba(cmd->device);
73153fe5
WS		 4918
4919 BUG_ON(cmd->request->tag < 0);
4920
574f05d3
SC		 4921 dev = cmd->device->hostdata;
4922 if (!dev) {
4923 cmd->result = DID_NO_CONNECT << 16;
4924 cmd->scsi_done(cmd);
4925 return 0;
4926 }
574f05d3 4927
73153fe5 4928 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 4929
407863cb 4930 if (unlikely(lockup_detected(h))) {
25163bd5 4931 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 4932 cmd->scsi_done(cmd);
4933 return 0;
4934 }
73153fe5 4935 c = cmd_tagged_alloc(h, cmd);
574f05d3 4936
407863cb
SC		 4937 /*
4938 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 4939 * Retries always go down the normal I/O path.
4940 */
4941 if (likely(cmd->retries == 0 &&
4942 cmd->request->cmd_type == REQ_TYPE_FS &&
4943 h->acciopath_status)) {
592a0ad5
WS		 4944 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
4945 if (rc == 0)
4946 return 0;
4947 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 4948 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 4949 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 4950 }
4951 }
4952 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
4953}
4954
8ebc9248 4955static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 4956{
4957 unsigned long flags;
4958
8ebc9248
WS		 4959 spin_lock_irqsave(&h->scan_lock, flags);
4960 h->scan_finished = 1;
4961 wake_up_all(&h->scan_wait_queue);
4962 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 4963}
4964
a08a8471
SC		 4965static void hpsa_scan_start(struct Scsi_Host *sh)
4966{
4967 struct ctlr_info *h = shost_to_hba(sh);
4968 unsigned long flags;
4969
8ebc9248
WS		 4970 /*
4971 * Don't let rescans be initiated on a controller known to be locked
4972 * up. If the controller locks up *during* a rescan, that thread is
4973 * probably hosed, but at least we can prevent new rescan threads from
4974 * piling up on a locked up controller.
4975 */
4976 if (unlikely(lockup_detected(h)))
4977 return hpsa_scan_complete(h);
5f389360 4978
a08a8471
SC		 4979 /* wait until any scan already in progress is finished. */
4980 while (1) {
4981 spin_lock_irqsave(&h->scan_lock, flags);
4982 if (h->scan_finished)
4983 break;
4984 spin_unlock_irqrestore(&h->scan_lock, flags);
4985 wait_event(h->scan_wait_queue, h->scan_finished);
4986 /* Note: We don't need to worry about a race between this
4987 * thread and driver unload because the midlayer will
4988 * have incremented the reference count, so unload won't
4989 * happen if we're in here.
4990 */
4991 }
4992 h->scan_finished = 0; /* mark scan as in progress */
4993 spin_unlock_irqrestore(&h->scan_lock, flags);
4994
8ebc9248
WS		 4995 if (unlikely(lockup_detected(h)))
4996 return hpsa_scan_complete(h);
5f389360 4997
8aa60681 4998 hpsa_update_scsi_devices(h);
a08a8471 4999
8ebc9248 5000 hpsa_scan_complete(h);
a08a8471
SC		 5001}
5002
7c0a0229
DB		 5003static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5004{
03383736
DB		 5005 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5006
5007 if (!logical_drive)
5008 return -ENODEV;
7c0a0229
DB		 5009
5010 if (qdepth < 1)
5011 qdepth = 1;
03383736
DB		 5012 else if (qdepth > logical_drive->queue_depth)
5013 qdepth = logical_drive->queue_depth;
5014
5015 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5016}
5017
a08a8471
SC		 5018static int hpsa_scan_finished(struct Scsi_Host *sh,
5019 unsigned long elapsed_time)
5020{
5021 struct ctlr_info *h = shost_to_hba(sh);
5022 unsigned long flags;
5023 int finished;
5024
5025 spin_lock_irqsave(&h->scan_lock, flags);
5026 finished = h->scan_finished;
5027 spin_unlock_irqrestore(&h->scan_lock, flags);
5028 return finished;
5029}
5030
2946e82b 5031static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5032{
b705690d
SC		 5033 struct Scsi_Host *sh;
5034 int error;
edd16368 5035
b705690d 5036 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5037 if (sh == NULL) {
5038 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5039 return -ENOMEM;
5040 }
b705690d
SC		 5041
5042 sh->io_port = 0;
5043 sh->n_io_port = 0;
5044 sh->this_id = -1;
5045 sh->max_channel = 3;
5046 sh->max_cmd_len = MAX_COMMAND_SIZE;
5047 sh->max_lun = HPSA_MAX_LUN;
5048 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5049 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5050 sh->cmd_per_lun = sh->can_queue;
b705690d 5051 sh->sg_tablesize = h->maxsgentries;
b705690d
SC		 5052 sh->hostdata[0] = (unsigned long) h;
5053 sh->irq = h->intr[h->intr_mode];
5054 sh->unique_id = sh->irq;
73153fe5
WS		 5055 error = scsi_init_shared_tag_map(sh, sh->can_queue);
5056 if (error) {
5057 dev_err(&h->pdev->dev,
5058 "%s: scsi_init_shared_tag_map failed for controller %d\n",
5059 __func__, h->ctlr);
2946e82b
RE		 5060 scsi_host_put(sh);
5061 return error;
73153fe5 5062 }
2946e82b 5063 h->scsi_host = sh;
b705690d 5064 return 0;
2946e82b 5065}
b705690d 5066
2946e82b
RE		 5067static int hpsa_scsi_add_host(struct ctlr_info *h)
5068{
5069 int rv;
5070
5071 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5072 if (rv) {
5073 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5074 return rv;
5075 }
5076 scsi_scan_host(h->scsi_host);
5077 return 0;
edd16368
SC		 5078}
5079
73153fe5
WS		 5080/*
5081 * The block layer has already gone to the trouble of picking out a unique,
5082 * small-integer tag for this request. We use an offset from that value as
5083 * an index to select our command block. (The offset allows us to reserve the
5084 * low-numbered entries for our own uses.)
5085 */
5086static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5087{
5088 int idx = scmd->request->tag;
5089
5090 if (idx < 0)
5091 return idx;
5092
5093 /* Offset to leave space for internal cmds. */
5094 return idx += HPSA_NRESERVED_CMDS;
5095}
5096
b69324ff
WS		 5097/*
5098 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5099 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5100 */
5101static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5102 struct CommandList *c, unsigned char lunaddr[],
5103 int reply_queue)
5104{
5105 int rc;
5106
5107 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5108 (void) fill_cmd(c, TEST_UNIT_READY, h,
5109 NULL, 0, 0, lunaddr, TYPE_CMD);
5110 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5111 if (rc)
5112 return rc;
5113 /* no unmap needed here because no data xfer. */
5114
5115 /* Check if the unit is already ready. */
5116 if (c->err_info->CommandStatus == CMD_SUCCESS)
5117 return 0;
5118
5119 /*
5120 * The first command sent after reset will receive "unit attention" to
5121 * indicate that the LUN has been reset...this is actually what we're
5122 * looking for (but, success is good too).
5123 */
5124 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5125 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5126 (c->err_info->SenseInfo[2] == NO_SENSE ||
5127 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5128 return 0;
5129
5130 return 1;
5131}
5132
5133/*
5134 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5135 * returns zero when the unit is ready, and non-zero when giving up.
5136 */
5137static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5138 struct CommandList *c,
5139 unsigned char lunaddr[], int reply_queue)
edd16368 5140{
8919358e 5141 int rc;
edd16368
SC		 5142 int count = 0;
5143 int waittime = 1; /* seconds */
edd16368
SC		 5144
5145 /* Send test unit ready until device ready, or give up. */
b69324ff 5146 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5147
b69324ff
WS		 5148 /*
5149 * Wait for a bit. do this first, because if we send
edd16368
SC		 5150 * the TUR right away, the reset will just abort it.
5151 */
5152 msleep(1000 * waittime);
b69324ff
WS		 5153
5154 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5155 if (!rc)
5156 break;
edd16368
SC		 5157
5158 /* Increase wait time with each try, up to a point. */
5159 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5160 waittime *= 2;
edd16368 5161
b69324ff
WS		 5162 dev_warn(&h->pdev->dev,
5163 "waiting %d secs for device to become ready.\n",
5164 waittime);
5165 }
edd16368 5166
b69324ff
WS		 5167 return rc;
5168}
edd16368 5169
b69324ff
WS		 5170static int wait_for_device_to_become_ready(struct ctlr_info *h,
5171 unsigned char lunaddr[],
5172 int reply_queue)
5173{
5174 int first_queue;
5175 int last_queue;
5176 int rq;
5177 int rc = 0;
5178 struct CommandList *c;
5179
5180 c = cmd_alloc(h);
5181
5182 /*
5183 * If no specific reply queue was requested, then send the TUR
5184 * repeatedly, requesting a reply on each reply queue; otherwise execute
5185 * the loop exactly once using only the specified queue.
5186 */
5187 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5188 first_queue = 0;
5189 last_queue = h->nreply_queues - 1;
5190 } else {
5191 first_queue = reply_queue;
5192 last_queue = reply_queue;
5193 }
5194
5195 for (rq = first_queue; rq <= last_queue; rq++) {
5196 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5197 if (rc)
edd16368 5198 break;
edd16368
SC		 5199 }
5200
5201 if (rc)
5202 dev_warn(&h->pdev->dev, "giving up on device.\n");
5203 else
5204 dev_warn(&h->pdev->dev, "device is ready.\n");
5205
45fcb86e 5206 cmd_free(h, c);
edd16368
SC		 5207 return rc;
5208}
5209
5210/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5211 * complaining. Doing a host- or bus-reset can't do anything good here.
5212 */
5213static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5214{
5215 int rc;
5216 struct ctlr_info *h;
5217 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5218 u8 reset_type;
2dc127bb 5219 char msg[48];
edd16368
SC		 5220
5221 /* find the controller to which the command to be aborted was sent */
5222 h = sdev_to_hba(scsicmd->device);
5223 if (h == NULL) /* paranoia */
5224 return FAILED;
e345893b
DB		 5225
5226 if (lockup_detected(h))
5227 return FAILED;
5228
edd16368
SC		 5229 dev = scsicmd->device->hostdata;
5230 if (!dev) {
d604f533 5231 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
edd16368
SC		 5232 return FAILED;
5233 }
25163bd5
WS		 5234
5235 /* if controller locked up, we can guarantee command won't complete */
5236 if (lockup_detected(h)) {
2dc127bb
DC		 5237 snprintf(msg, sizeof(msg),
5238 "cmd %d RESET FAILED, lockup detected",
5239 hpsa_get_cmd_index(scsicmd));
73153fe5 5240 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5241 return FAILED;
5242 }
5243
5244 /* this reset request might be the result of a lockup; check */
5245 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5246 snprintf(msg, sizeof(msg),
5247 "cmd %d RESET FAILED, new lockup detected",
5248 hpsa_get_cmd_index(scsicmd));
73153fe5 5249 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5
WS		 5250 return FAILED;
5251 }
5252
d604f533
WS		 5253 /* Do not attempt on controller */
5254 if (is_hba_lunid(dev->scsi3addr))
5255 return SUCCESS;
5256
0b9b7b6e
ST		 5257 if (is_logical_dev_addr_mode(dev->scsi3addr))
5258 reset_type = HPSA_DEVICE_RESET_MSG;
5259 else
5260 reset_type = HPSA_PHYS_TARGET_RESET;
5261
5262 sprintf(msg, "resetting %s",
5263 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5264 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5265
da03ded0
DB		 5266 h->reset_in_progress = 1;
5267
edd16368 5268 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 5269 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 5270 DEFAULT_REPLY_QUEUE);
0b9b7b6e
ST		 5271 sprintf(msg, "reset %s %s",
5272 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
5273 rc == 0 ? "completed successfully" : "failed");
d604f533 5274 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
da03ded0 5275 h->reset_in_progress = 0;
d604f533 5276 return rc == 0 ? SUCCESS : FAILED;
edd16368
SC		 5277}
5278
6cba3f19
SC		 5279static void swizzle_abort_tag(u8 *tag)
5280{
5281 u8 original_tag[8];
5282
5283 memcpy(original_tag, tag, 8);
5284 tag[0] = original_tag[3];
5285 tag[1] = original_tag[2];
5286 tag[2] = original_tag[1];
5287 tag[3] = original_tag[0];
5288 tag[4] = original_tag[7];
5289 tag[5] = original_tag[6];
5290 tag[6] = original_tag[5];
5291 tag[7] = original_tag[4];
5292}
5293
17eb87d2 5294static void hpsa_get_tag(struct ctlr_info *h,
2b08b3e9 5295 struct CommandList *c, __le32 *taglower, __le32 *tagupper)
17eb87d2 5296{
2b08b3e9 5297 u64 tag;
17eb87d2
ST		 5298 if (c->cmd_type == CMD_IOACCEL1) {
5299 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
5300 &h->ioaccel_cmd_pool[c->cmdindex];
2b08b3e9
DB		 5301 tag = le64_to_cpu(cm1->tag);
5302 *tagupper = cpu_to_le32(tag >> 32);
5303 *taglower = cpu_to_le32(tag);
54b6e9e9
ST		 5304 return;
5305 }
5306 if (c->cmd_type == CMD_IOACCEL2) {
5307 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
5308 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 5309 /* upper tag not used in ioaccel2 mode */
5310 memset(tagupper, 0, sizeof(*tagupper));
5311 *taglower = cm2->Tag;
54b6e9e9 5312 return;
17eb87d2 5313 }
2b08b3e9
DB		 5314 tag = le64_to_cpu(c->Header.tag);
5315 *tagupper = cpu_to_le32(tag >> 32);
5316 *taglower = cpu_to_le32(tag);
17eb87d2
ST		 5317}
5318
75167d2c 5319static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
9b5c48c2 5320 struct CommandList *abort, int reply_queue)
75167d2c
SC		 5321{
5322 int rc = IO_OK;
5323 struct CommandList *c;
5324 struct ErrorInfo *ei;
2b08b3e9 5325 __le32 tagupper, taglower;
75167d2c 5326
45fcb86e 5327 c = cmd_alloc(h);
75167d2c 5328
a2dac136 5329 /* fill_cmd can't fail here, no buffer to map */
9b5c48c2 5330 (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
a2dac136 5331 0, 0, scsi3addr, TYPE_MSG);
9b5c48c2 5332 if (h->needs_abort_tags_swizzled)
6cba3f19 5333 swizzle_abort_tag(&c->Request.CDB[4]);
25163bd5 5334 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
17eb87d2 5335 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5336 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
17eb87d2 5337 __func__, tagupper, taglower);
75167d2c
SC		 5338 /* no unmap needed here because no data xfer. */
5339
5340 ei = c->err_info;
5341 switch (ei->CommandStatus) {
5342 case CMD_SUCCESS:
5343 break;
9437ac43
SC		 5344 case CMD_TMF_STATUS:
5345 rc = hpsa_evaluate_tmf_status(h, c);
5346 break;
75167d2c
SC		 5347 case CMD_UNABORTABLE: /* Very common, don't make noise. */
5348 rc = -1;
5349 break;
5350 default:
5351 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 5352 __func__, tagupper, taglower);
d1e8beac 5353 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 5354 rc = -1;
5355 break;
5356 }
45fcb86e 5357 cmd_free(h, c);
dd0e19f3
ST		 5358 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
5359 __func__, tagupper, taglower);
75167d2c
SC		 5360 return rc;
5361}
5362
8be986cc
SC		 5363static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
5364 struct CommandList *command_to_abort, int reply_queue)
5365{
5366 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5367 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
5368 struct io_accel2_cmd *c2a =
5369 &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
a58e7e53 5370 struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
8be986cc
SC		 5371 struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
5372
5373 /*
5374 * We're overlaying struct hpsa_tmf_struct on top of something which
5375 * was allocated as a struct io_accel2_cmd, so we better be sure it
5376 * actually fits, and doesn't overrun the error info space.
5377 */
5378 BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
5379 sizeof(struct io_accel2_cmd));
5380 BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
5381 offsetof(struct hpsa_tmf_struct, error_len) +
5382 sizeof(ac->error_len));
5383
5384 c->cmd_type = IOACCEL2_TMF;
a58e7e53
WS		 5385 c->scsi_cmd = SCSI_CMD_BUSY;
5386
8be986cc
SC		 5387 /* Adjust the DMA address to point to the accelerated command buffer */
5388 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
5389 (c->cmdindex * sizeof(struct io_accel2_cmd));
5390 BUG_ON(c->busaddr & 0x0000007F);
5391
5392 memset(ac, 0, sizeof(*c2)); /* yes this is correct */
5393 ac->iu_type = IOACCEL2_IU_TMF_TYPE;
5394 ac->reply_queue = reply_queue;
5395 ac->tmf = IOACCEL2_TMF_ABORT;
5396 ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
5397 memset(ac->lun_id, 0, sizeof(ac->lun_id));
5398 ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
5399 ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
5400 ac->error_ptr = cpu_to_le64(c->busaddr +
5401 offsetof(struct io_accel2_cmd, error_data));
5402 ac->error_len = cpu_to_le32(sizeof(c2->error_data));
5403}
5404
54b6e9e9
ST		 5405/* ioaccel2 path firmware cannot handle abort task requests.
5406 * Change abort requests to physical target reset, and send to the
5407 * address of the physical disk used for the ioaccel 2 command.
5408 * Return 0 on success (IO_OK)
5409 * -1 on failure
5410 */
5411
5412static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
25163bd5 5413 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
54b6e9e9
ST		 5414{
5415 int rc = IO_OK;
5416 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
5417 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
5418 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
5419 unsigned char *psa = &phys_scsi3addr[0];
5420
5421 /* Get a pointer to the hpsa logical device. */
7fa3030c 5422 scmd = abort->scsi_cmd;
54b6e9e9
ST		 5423 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
5424 if (dev == NULL) {
5425 dev_warn(&h->pdev->dev,
5426 "Cannot abort: no device pointer for command.\n");
5427 return -1; /* not abortable */
5428 }
5429
2ba8bfc8
SC		 5430 if (h->raid_offload_debug > 0)
5431 dev_info(&h->pdev->dev,
0d96ef5f 5432 "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2ba8bfc8 5433 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
0d96ef5f 5434 "Reset as abort",
2ba8bfc8
SC		 5435 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
5436 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
5437
54b6e9e9
ST		 5438 if (!dev->offload_enabled) {
5439 dev_warn(&h->pdev->dev,
5440 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
5441 return -1; /* not abortable */
5442 }
5443
5444 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
5445 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
5446 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
5447 return -1; /* not abortable */
5448 }
5449
5450 /* send the reset */
2ba8bfc8
SC		 5451 if (h->raid_offload_debug > 0)
5452 dev_info(&h->pdev->dev,
5453 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5454 psa[0], psa[1], psa[2], psa[3],
5455 psa[4], psa[5], psa[6], psa[7]);
d604f533 5456 rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
54b6e9e9
ST		 5457 if (rc != 0) {
5458 dev_warn(&h->pdev->dev,
5459 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5460 psa[0], psa[1], psa[2], psa[3],
5461 psa[4], psa[5], psa[6], psa[7]);
5462 return rc; /* failed to reset */
5463 }
5464
5465 /* wait for device to recover */
b69324ff 5466 if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
54b6e9e9
ST		 5467 dev_warn(&h->pdev->dev,
5468 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5469 psa[0], psa[1], psa[2], psa[3],
5470 psa[4], psa[5], psa[6], psa[7]);
5471 return -1; /* failed to recover */
5472 }
5473
5474 /* device recovered */
5475 dev_info(&h->pdev->dev,
5476 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
5477 psa[0], psa[1], psa[2], psa[3],
5478 psa[4], psa[5], psa[6], psa[7]);
5479
5480 return rc; /* success */
5481}
5482
8be986cc
SC		 5483static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
5484 struct CommandList *abort, int reply_queue)
5485{
5486 int rc = IO_OK;
5487 struct CommandList *c;
5488 __le32 taglower, tagupper;
5489 struct hpsa_scsi_dev_t *dev;
5490 struct io_accel2_cmd *c2;
5491
5492 dev = abort->scsi_cmd->device->hostdata;
5493 if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
5494 return -1;
5495
5496 c = cmd_alloc(h);
5497 setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
5498 c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5499 (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
5500 hpsa_get_tag(h, abort, &taglower, &tagupper);
5501 dev_dbg(&h->pdev->dev,
5502 "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
5503 __func__, tagupper, taglower);
5504 /* no unmap needed here because no data xfer. */
5505
5506 dev_dbg(&h->pdev->dev,
5507 "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
5508 __func__, tagupper, taglower, c2->error_data.serv_response);
5509 switch (c2->error_data.serv_response) {
5510 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
5511 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
5512 rc = 0;
5513 break;
5514 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
5515 case IOACCEL2_SERV_RESPONSE_FAILURE:
5516 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
5517 rc = -1;
5518 break;
5519 default:
5520 dev_warn(&h->pdev->dev,
5521 "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
5522 __func__, tagupper, taglower,
5523 c2->error_data.serv_response);
5524 rc = -1;
5525 }
5526 cmd_free(h, c);
5527 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
5528 tagupper, taglower);
5529 return rc;
5530}
5531
6cba3f19 5532static int hpsa_send_abort_both_ways(struct ctlr_info *h,
25163bd5 5533 unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
6cba3f19 5534{
8be986cc
SC		 5535 /*
5536 * ioccelerator mode 2 commands should be aborted via the
54b6e9e9 5537 * accelerated path, since RAID path is unaware of these commands,
8be986cc
SC		 5538 * but not all underlying firmware can handle abort TMF.
5539 * Change abort to physical device reset when abort TMF is unsupported.
54b6e9e9 5540 */
8be986cc
SC		 5541 if (abort->cmd_type == CMD_IOACCEL2) {
5542 if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
5543 return hpsa_send_abort_ioaccel2(h, abort,
5544 reply_queue);
5545 else
5546 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
25163bd5 5547 abort, reply_queue);
8be986cc 5548 }
9b5c48c2 5549 return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
25163bd5 5550}
54b6e9e9 5551
25163bd5
WS		 5552/* Find out which reply queue a command was meant to return on */
5553static int hpsa_extract_reply_queue(struct ctlr_info *h,
5554 struct CommandList *c)
5555{
5556 if (c->cmd_type == CMD_IOACCEL2)
5557 return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
5558 return c->Header.ReplyQueue;
6cba3f19
SC		 5559}
5560
9b5c48c2
SC		 5561/*
5562 * Limit concurrency of abort commands to prevent
5563 * over-subscription of commands
5564 */
5565static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
5566{
5567#define ABORT_CMD_WAIT_MSECS 5000
5568 return !wait_event_timeout(h->abort_cmd_wait_queue,
5569 atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
5570 msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
5571}
5572
75167d2c
SC		 5573/* Send an abort for the specified command.
5574 * If the device and controller support it,
5575 * send a task abort request.
5576 */
5577static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
5578{
5579
a58e7e53 5580 int rc;
75167d2c
SC		 5581 struct ctlr_info *h;
5582 struct hpsa_scsi_dev_t *dev;
5583 struct CommandList *abort; /* pointer to command to be aborted */
75167d2c
SC		 5584 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
5585 char msg[256]; /* For debug messaging. */
5586 int ml = 0;
2b08b3e9 5587 __le32 tagupper, taglower;
25163bd5
WS		 5588 int refcount, reply_queue;
5589
5590 if (sc == NULL)
5591 return FAILED;
75167d2c 5592
9b5c48c2
SC		 5593 if (sc->device == NULL)
5594 return FAILED;
5595
75167d2c
SC		 5596 /* Find the controller of the command to be aborted */
5597 h = sdev_to_hba(sc->device);
9b5c48c2 5598 if (h == NULL)
75167d2c
SC		 5599 return FAILED;
5600
25163bd5
WS		 5601 /* Find the device of the command to be aborted */
5602 dev = sc->device->hostdata;
5603 if (!dev) {
5604 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
5605 msg);
e345893b 5606 return FAILED;
25163bd5
WS		 5607 }
5608
5609 /* If controller locked up, we can guarantee command won't complete */
5610 if (lockup_detected(h)) {
5611 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5612 "ABORT FAILED, lockup detected");
5613 return FAILED;
5614 }
5615
5616 /* This is a good time to check if controller lockup has occurred */
5617 if (detect_controller_lockup(h)) {
5618 hpsa_show_dev_msg(KERN_WARNING, h, dev,
5619 "ABORT FAILED, new lockup detected");
5620 return FAILED;
5621 }
e345893b 5622
75167d2c
SC		 5623 /* Check that controller supports some kind of task abort */
5624 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
5625 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5626 return FAILED;
5627
5628 memset(msg, 0, sizeof(msg));
4b761557 5629 ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
75167d2c 5630 h->scsi_host->host_no, sc->device->channel,
0d96ef5f 5631 sc->device->id, sc->device->lun,
4b761557 5632 "Aborting command", sc);
75167d2c 5633
75167d2c
SC		 5634 /* Get SCSI command to be aborted */
5635 abort = (struct CommandList *) sc->host_scribble;
5636 if (abort == NULL) {
281a7fd0
WS		 5637 /* This can happen if the command already completed. */
5638 return SUCCESS;
5639 }
5640 refcount = atomic_inc_return(&abort->refcount);
5641 if (refcount == 1) { /* Command is done already. */
5642 cmd_free(h, abort);
5643 return SUCCESS;
75167d2c 5644 }
9b5c48c2
SC		 5645
5646 /* Don't bother trying the abort if we know it won't work. */
5647 if (abort->cmd_type != CMD_IOACCEL2 &&
5648 abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
5649 cmd_free(h, abort);
5650 return FAILED;
5651 }
5652
a58e7e53
WS		 5653 /*
5654 * Check that we're aborting the right command.
5655 * It's possible the CommandList already completed and got re-used.
5656 */
5657 if (abort->scsi_cmd != sc) {
5658 cmd_free(h, abort);
5659 return SUCCESS;
5660 }
5661
5662 abort->abort_pending = true;
17eb87d2 5663 hpsa_get_tag(h, abort, &taglower, &tagupper);
25163bd5 5664 reply_queue = hpsa_extract_reply_queue(h, abort);
17eb87d2 5665 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
7fa3030c 5666 as = abort->scsi_cmd;
75167d2c 5667 if (as != NULL)
4b761557
RE		 5668 ml += sprintf(msg+ml,
5669 "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
5670 as->cmd_len, as->cmnd[0], as->cmnd[1],
5671 as->serial_number);
5672 dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
0d96ef5f 5673 hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
4b761557 5674
75167d2c
SC		 5675 /*
5676 * Command is in flight, or possibly already completed
5677 * by the firmware (but not to the scsi mid layer) but we can't
5678 * distinguish which. Send the abort down.
5679 */
9b5c48c2
SC		 5680 if (wait_for_available_abort_cmd(h)) {
5681 dev_warn(&h->pdev->dev,
4b761557
RE		 5682 "%s FAILED, timeout waiting for an abort command to become available.\n",
5683 msg);
9b5c48c2
SC		 5684 cmd_free(h, abort);
5685 return FAILED;
5686 }
25163bd5 5687 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
9b5c48c2
SC		 5688 atomic_inc(&h->abort_cmds_available);
5689 wake_up_all(&h->abort_cmd_wait_queue);
75167d2c 5690 if (rc != 0) {
4b761557 5691 dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
0d96ef5f 5692 hpsa_show_dev_msg(KERN_WARNING, h, dev,
4b761557 5693 "FAILED to abort command");
281a7fd0 5694 cmd_free(h, abort);
75167d2c
SC		 5695 return FAILED;
5696 }
4b761557 5697 dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
d604f533 5698 wait_event(h->event_sync_wait_queue,
a58e7e53 5699 abort->scsi_cmd != sc || lockup_detected(h));
281a7fd0 5700 cmd_free(h, abort);
a58e7e53 5701 return !lockup_detected(h) ? SUCCESS : FAILED;
75167d2c
SC		 5702}
5703
73153fe5
WS		 5704/*
5705 * For operations with an associated SCSI command, a command block is allocated
5706 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
5707 * block request tag as an index into a table of entries. cmd_tagged_free() is
5708 * the complement, although cmd_free() may be called instead.
5709 */
5710static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
5711 struct scsi_cmnd *scmd)
5712{
5713 int idx = hpsa_get_cmd_index(scmd);
5714 struct CommandList *c = h->cmd_pool + idx;
5715
5716 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
5717 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
5718 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
5719 /* The index value comes from the block layer, so if it's out of
5720 * bounds, it's probably not our bug.
5721 */
5722 BUG();
5723 }
5724
5725 atomic_inc(&c->refcount);
5726 if (unlikely(!hpsa_is_cmd_idle(c))) {
5727 /*
5728 * We expect that the SCSI layer will hand us a unique tag
5729 * value. Thus, there should never be a collision here between
5730 * two requests...because if the selected command isn't idle
5731 * then someone is going to be very disappointed.
5732 */
5733 dev_err(&h->pdev->dev,
5734 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
5735 idx);
5736 if (c->scsi_cmd != NULL)
5737 scsi_print_command(c->scsi_cmd);
5738 scsi_print_command(scmd);
5739 }
5740
5741 hpsa_cmd_partial_init(h, idx, c);
5742 return c;
5743}
5744
5745static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
5746{
5747 /*
5748 * Release our reference to the block. We don't need to do anything
5749 * else to free it, because it is accessed by index. (There's no point
5750 * in checking the result of the decrement, since we cannot guarantee
5751 * that there isn't a concurrent abort which is also accessing it.)
5752 */
5753 (void)atomic_dec(&c->refcount);
5754}
5755
edd16368
SC		 5756/*
5757 * For operations that cannot sleep, a command block is allocated at init,
5758 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
5759 * which ones are free or in use. Lock must be held when calling this.
5760 * cmd_free() is the complement.
bf43caf3
RE		 5761 * This function never gives up and returns NULL. If it hangs,
5762 * another thread must call cmd_free() to free some tags.
edd16368 5763 */
281a7fd0 5764
edd16368
SC		 5765static struct CommandList *cmd_alloc(struct ctlr_info *h)
5766{
5767 struct CommandList *c;
360c73bd 5768 int refcount, i;
73153fe5 5769 int offset = 0;
4c413128 5770
33811026
RE		 5771 /*
5772 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 5773 * multiple threads could get in here, and one thread could
5774 * be scanning through the list of bits looking for a free
5775 * one, but the free ones are always behind him, and other
5776 * threads sneak in behind him and eat them before he can
5777 * get to them, so that while there is always a free one, a
5778 * very unlucky thread might be starved anyway, never able to
5779 * beat the other threads. In reality, this happens so
5780 * infrequently as to be indistinguishable from never.
73153fe5
WS		 5781 *
5782 * Note that we start allocating commands before the SCSI host structure
5783 * is initialized. Since the search starts at bit zero, this
5784 * all works, since we have at least one command structure available;
5785 * however, it means that the structures with the low indexes have to be
5786 * reserved for driver-initiated requests, while requests from the block
5787 * layer will use the higher indexes.
4c413128 5788 */
edd16368 5789
281a7fd0 5790 for (;;) {
73153fe5
WS		 5791 i = find_next_zero_bit(h->cmd_pool_bits,
5792 HPSA_NRESERVED_CMDS,
5793 offset);
5794 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 5795 offset = 0;
5796 continue;
5797 }
5798 c = h->cmd_pool + i;
5799 refcount = atomic_inc_return(&c->refcount);
5800 if (unlikely(refcount > 1)) {
5801 cmd_free(h, c); /* already in use */
73153fe5 5802 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 5803 continue;
5804 }
5805 set_bit(i & (BITS_PER_LONG - 1),
5806 h->cmd_pool_bits + (i / BITS_PER_LONG));
5807 break; /* it's ours now. */
5808 }
360c73bd 5809 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 5810 return c;
5811}
5812
73153fe5
WS		 5813/*
5814 * This is the complementary operation to cmd_alloc(). Note, however, in some
5815 * corner cases it may also be used to free blocks allocated by
5816 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
5817 * the clear-bit is harmless.
5818 */
edd16368
SC		 5819static void cmd_free(struct ctlr_info *h, struct CommandList *c)
5820{
281a7fd0
WS		 5821 if (atomic_dec_and_test(&c->refcount)) {
5822 int i;
edd16368 5823
281a7fd0
WS		 5824 i = c - h->cmd_pool;
5825 clear_bit(i & (BITS_PER_LONG - 1),
5826 h->cmd_pool_bits + (i / BITS_PER_LONG));
5827 }
edd16368
SC		 5828}
5829
edd16368
SC		 5830#ifdef CONFIG_COMPAT
5831
42a91641
DB		 5832static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
5833 void __user *arg)
edd16368
SC		 5834{
5835 IOCTL32_Command_struct __user *arg32 =
5836 (IOCTL32_Command_struct __user *) arg;
5837 IOCTL_Command_struct arg64;
5838 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
5839 int err;
5840 u32 cp;
5841
938abd84 5842 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5843 err = 0;
5844 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5845 sizeof(arg64.LUN_info));
5846 err |= copy_from_user(&arg64.Request, &arg32->Request,
5847 sizeof(arg64.Request));
5848 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5849 sizeof(arg64.error_info));
5850 err |= get_user(arg64.buf_size, &arg32->buf_size);
5851 err |= get_user(cp, &arg32->buf);
5852 arg64.buf = compat_ptr(cp);
5853 err |= copy_to_user(p, &arg64, sizeof(arg64));
5854
5855 if (err)
5856 return -EFAULT;
5857
42a91641 5858 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 5859 if (err)
5860 return err;
5861 err |= copy_in_user(&arg32->error_info, &p->error_info,
5862 sizeof(arg32->error_info));
5863 if (err)
5864 return -EFAULT;
5865 return err;
5866}
5867
5868static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
42a91641 5869 int cmd, void __user *arg)
edd16368
SC		 5870{
5871 BIG_IOCTL32_Command_struct __user *arg32 =
5872 (BIG_IOCTL32_Command_struct __user *) arg;
5873 BIG_IOCTL_Command_struct arg64;
5874 BIG_IOCTL_Command_struct __user *p =
5875 compat_alloc_user_space(sizeof(arg64));
5876 int err;
5877 u32 cp;
5878
938abd84 5879 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 5880 err = 0;
5881 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
5882 sizeof(arg64.LUN_info));
5883 err |= copy_from_user(&arg64.Request, &arg32->Request,
5884 sizeof(arg64.Request));
5885 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
5886 sizeof(arg64.error_info));
5887 err |= get_user(arg64.buf_size, &arg32->buf_size);
5888 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
5889 err |= get_user(cp, &arg32->buf);
5890 arg64.buf = compat_ptr(cp);
5891 err |= copy_to_user(p, &arg64, sizeof(arg64));
5892
5893 if (err)
5894 return -EFAULT;
5895
42a91641 5896 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 5897 if (err)
5898 return err;
5899 err |= copy_in_user(&arg32->error_info, &p->error_info,
5900 sizeof(arg32->error_info));
5901 if (err)
5902 return -EFAULT;
5903 return err;
5904}
71fe75a7 5905
42a91641 5906static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
71fe75a7
SC		 5907{
5908 switch (cmd) {
5909 case CCISS_GETPCIINFO:
5910 case CCISS_GETINTINFO:
5911 case CCISS_SETINTINFO:
5912 case CCISS_GETNODENAME:
5913 case CCISS_SETNODENAME:
5914 case CCISS_GETHEARTBEAT:
5915 case CCISS_GETBUSTYPES:
5916 case CCISS_GETFIRMVER:
5917 case CCISS_GETDRIVVER:
5918 case CCISS_REVALIDVOLS:
5919 case CCISS_DEREGDISK:
5920 case CCISS_REGNEWDISK:
5921 case CCISS_REGNEWD:
5922 case CCISS_RESCANDISK:
5923 case CCISS_GETLUNINFO:
5924 return hpsa_ioctl(dev, cmd, arg);
5925
5926 case CCISS_PASSTHRU32:
5927 return hpsa_ioctl32_passthru(dev, cmd, arg);
5928 case CCISS_BIG_PASSTHRU32:
5929 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
5930
5931 default:
5932 return -ENOIOCTLCMD;
5933 }
5934}
edd16368
SC		 5935#endif
5936
5937static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
5938{
5939 struct hpsa_pci_info pciinfo;
5940
5941 if (!argp)
5942 return -EINVAL;
5943 pciinfo.domain = pci_domain_nr(h->pdev->bus);
5944 pciinfo.bus = h->pdev->bus->number;
5945 pciinfo.dev_fn = h->pdev->devfn;
5946 pciinfo.board_id = h->board_id;
5947 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
5948 return -EFAULT;
5949 return 0;
5950}
5951
5952static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
5953{
5954 DriverVer_type DriverVer;
5955 unsigned char vmaj, vmin, vsubmin;
5956 int rc;
5957
5958 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
5959 &vmaj, &vmin, &vsubmin);
5960 if (rc != 3) {
5961 dev_info(&h->pdev->dev, "driver version string '%s' "
5962 "unrecognized.", HPSA_DRIVER_VERSION);
5963 vmaj = 0;
5964 vmin = 0;
5965 vsubmin = 0;
5966 }
5967 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
5968 if (!argp)
5969 return -EINVAL;
5970 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
5971 return -EFAULT;
5972 return 0;
5973}
5974
5975static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
5976{
5977 IOCTL_Command_struct iocommand;
5978 struct CommandList *c;
5979 char *buff = NULL;
50a0decf 5980 u64 temp64;
c1f63c8f 5981 int rc = 0;
edd16368
SC		 5982
5983 if (!argp)
5984 return -EINVAL;
5985 if (!capable(CAP_SYS_RAWIO))
5986 return -EPERM;
5987 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
5988 return -EFAULT;
5989 if ((iocommand.buf_size < 1) &&
5990 (iocommand.Request.Type.Direction != XFER_NONE)) {
5991 return -EINVAL;
5992 }
5993 if (iocommand.buf_size > 0) {
5994 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
5995 if (buff == NULL)
2dd02d74 5996 return -ENOMEM;
9233fb10 5997 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 5998 /* Copy the data into the buffer we created */
5999 if (copy_from_user(buff, iocommand.buf,
6000 iocommand.buf_size)) {
c1f63c8f
SC		 6001 rc = -EFAULT;
6002 goto out_kfree;
b03a7771
SC		 6003 }
6004 } else {
6005 memset(buff, 0, iocommand.buf_size);
edd16368 6006 }
b03a7771 6007 }
45fcb86e 6008 c = cmd_alloc(h);
bf43caf3 6009
edd16368
SC		 6010 /* Fill in the command type */
6011 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6012 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6013 /* Fill in Command Header */
6014 c->Header.ReplyQueue = 0; /* unused in simple mode */
6015 if (iocommand.buf_size > 0) { /* buffer to fill */
6016 c->Header.SGList = 1;
50a0decf 6017 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6018 } else { /* no buffers to fill */
6019 c->Header.SGList = 0;
50a0decf 6020 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6021 }
6022 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6023
6024 /* Fill in Request block */
6025 memcpy(&c->Request, &iocommand.Request,
6026 sizeof(c->Request));
6027
6028 /* Fill in the scatter gather information */
6029 if (iocommand.buf_size > 0) {
50a0decf 6030 temp64 = pci_map_single(h->pdev, buff,
edd16368 6031 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6032 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6033 c->SG[0].Addr = cpu_to_le64(0);
6034 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6035 rc = -ENOMEM;
6036 goto out;
6037 }
50a0decf
SC		 6038 c->SG[0].Addr = cpu_to_le64(temp64);
6039 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6040 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6041 }
25163bd5 6042 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
c2dd32e0
SC		 6043 if (iocommand.buf_size > 0)
6044 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368 6045 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6046 if (rc) {
6047 rc = -EIO;
6048 goto out;
6049 }
edd16368
SC		 6050
6051 /* Copy the error information out */
6052 memcpy(&iocommand.error_info, c->err_info,
6053 sizeof(iocommand.error_info));
6054 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6055 rc = -EFAULT;
6056 goto out;
edd16368 6057 }
9233fb10 6058 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6059 iocommand.buf_size > 0) {
edd16368
SC		 6060 /* Copy the data out of the buffer we created */
6061 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6062 rc = -EFAULT;
6063 goto out;
edd16368
SC		 6064 }
6065 }
c1f63c8f 6066out:
45fcb86e 6067 cmd_free(h, c);
c1f63c8f
SC		 6068out_kfree:
6069 kfree(buff);
6070 return rc;
edd16368
SC		 6071}
6072
6073static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6074{
6075 BIG_IOCTL_Command_struct *ioc;
6076 struct CommandList *c;
6077 unsigned char **buff = NULL;
6078 int *buff_size = NULL;
50a0decf 6079 u64 temp64;
edd16368
SC		 6080 BYTE sg_used = 0;
6081 int status = 0;
01a02ffc
SC		 6082 u32 left;
6083 u32 sz;
edd16368
SC		 6084 BYTE __user *data_ptr;
6085
6086 if (!argp)
6087 return -EINVAL;
6088 if (!capable(CAP_SYS_RAWIO))
6089 return -EPERM;
6090 ioc = (BIG_IOCTL_Command_struct *)
6091 kmalloc(sizeof(*ioc), GFP_KERNEL);
6092 if (!ioc) {
6093 status = -ENOMEM;
6094 goto cleanup1;
6095 }
6096 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
6097 status = -EFAULT;
6098 goto cleanup1;
6099 }
6100 if ((ioc->buf_size < 1) &&
6101 (ioc->Request.Type.Direction != XFER_NONE)) {
6102 status = -EINVAL;
6103 goto cleanup1;
6104 }
6105 /* Check kmalloc limits using all SGs */
6106 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6107 status = -EINVAL;
6108 goto cleanup1;
6109 }
d66ae08b 6110 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6111 status = -EINVAL;
6112 goto cleanup1;
6113 }
d66ae08b 6114 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 6115 if (!buff) {
6116 status = -ENOMEM;
6117 goto cleanup1;
6118 }
d66ae08b 6119 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 6120 if (!buff_size) {
6121 status = -ENOMEM;
6122 goto cleanup1;
6123 }
6124 left = ioc->buf_size;
6125 data_ptr = ioc->buf;
6126 while (left) {
6127 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6128 buff_size[sg_used] = sz;
6129 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6130 if (buff[sg_used] == NULL) {
6131 status = -ENOMEM;
6132 goto cleanup1;
6133 }
9233fb10 6134 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6135 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6136 status = -EFAULT;
edd16368
SC		 6137 goto cleanup1;
6138 }
6139 } else
6140 memset(buff[sg_used], 0, sz);
6141 left -= sz;
6142 data_ptr += sz;
6143 sg_used++;
6144 }
45fcb86e 6145 c = cmd_alloc(h);
bf43caf3 6146
edd16368 6147 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6148 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6149 c->Header.ReplyQueue = 0;
50a0decf
SC		 6150 c->Header.SGList = (u8) sg_used;
6151 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6152 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6153 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6154 if (ioc->buf_size > 0) {
6155 int i;
6156 for (i = 0; i < sg_used; i++) {
50a0decf 6157 temp64 = pci_map_single(h->pdev, buff[i],
edd16368 6158 buff_size[i], PCI_DMA_BIDIRECTIONAL);
50a0decf
SC		 6159 if (dma_mapping_error(&h->pdev->dev,
6160 (dma_addr_t) temp64)) {
6161 c->SG[i].Addr = cpu_to_le64(0);
6162 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa
SC		 6163 hpsa_pci_unmap(h->pdev, c, i,
6164 PCI_DMA_BIDIRECTIONAL);
6165 status = -ENOMEM;
e2d4a1f6 6166 goto cleanup0;
bcc48ffa 6167 }
50a0decf
SC		 6168 c->SG[i].Addr = cpu_to_le64(temp64);
6169 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6170 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6171 }
50a0decf 6172 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6173 }
25163bd5 6174 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
b03a7771
SC		 6175 if (sg_used)
6176 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368 6177 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6178 if (status) {
6179 status = -EIO;
6180 goto cleanup0;
6181 }
6182
edd16368
SC		 6183 /* Copy the error information out */
6184 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6185 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6186 status = -EFAULT;
e2d4a1f6 6187 goto cleanup0;
edd16368 6188 }
9233fb10 6189 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6190 int i;
6191
edd16368
SC		 6192 /* Copy the data out of the buffer we created */
6193 BYTE __user *ptr = ioc->buf;
6194 for (i = 0; i < sg_used; i++) {
6195 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6196 status = -EFAULT;
e2d4a1f6 6197 goto cleanup0;
edd16368
SC		 6198 }
6199 ptr += buff_size[i];
6200 }
6201 }
edd16368 6202 status = 0;
e2d4a1f6 6203cleanup0:
45fcb86e 6204 cmd_free(h, c);
edd16368
SC		 6205cleanup1:
6206 if (buff) {
2b08b3e9
DB		 6207 int i;
6208
edd16368
SC		 6209 for (i = 0; i < sg_used; i++)
6210 kfree(buff[i]);
6211 kfree(buff);
6212 }
6213 kfree(buff_size);
6214 kfree(ioc);
6215 return status;
6216}
6217
6218static void check_ioctl_unit_attention(struct ctlr_info *h,
6219 struct CommandList *c)
6220{
6221 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6222 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6223 (void) check_for_unit_attention(h, c);
6224}
0390f0c0 6225
edd16368
SC		 6226/*
6227 * ioctl
6228 */
42a91641 6229static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
edd16368
SC		 6230{
6231 struct ctlr_info *h;
6232 void __user *argp = (void __user *)arg;
0390f0c0 6233 int rc;
edd16368
SC		 6234
6235 h = sdev_to_hba(dev);
6236
6237 switch (cmd) {
6238 case CCISS_DEREGDISK:
6239 case CCISS_REGNEWDISK:
6240 case CCISS_REGNEWD:
a08a8471 6241 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6242 return 0;
6243 case CCISS_GETPCIINFO:
6244 return hpsa_getpciinfo_ioctl(h, argp);
6245 case CCISS_GETDRIVVER:
6246 return hpsa_getdrivver_ioctl(h, argp);
6247 case CCISS_PASSTHRU:
34f0c627 6248 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6249 return -EAGAIN;
6250 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6251 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6252 return rc;
edd16368 6253 case CCISS_BIG_PASSTHRU:
34f0c627 6254 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6255 return -EAGAIN;
6256 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6257 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6258 return rc;
edd16368
SC		 6259 default:
6260 return -ENOTTY;
6261 }
6262}
6263
bf43caf3 6264static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6265 u8 reset_type)
64670ac8
SC		 6266{
6267 struct CommandList *c;
6268
6269 c = cmd_alloc(h);
bf43caf3 6270
a2dac136
SC		 6271 /* fill_cmd can't fail here, no data buffer to map */
6272 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6273 RAID_CTLR_LUNID, TYPE_MSG);
6274 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6275 c->waiting = NULL;
6276 enqueue_cmd_and_start_io(h, c);
6277 /* Don't wait for completion, the reset won't complete. Don't free
6278 * the command either. This is the last command we will send before
6279 * re-initializing everything, so it doesn't matter and won't leak.
6280 */
bf43caf3 6281 return;
64670ac8
SC		 6282}
6283
a2dac136 6284static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6285 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6286 int cmd_type)
6287{
6288 int pci_dir = XFER_NONE;
9b5c48c2 6289 u64 tag; /* for commands to be aborted */
edd16368
SC		 6290
6291 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6292 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6293 c->Header.ReplyQueue = 0;
6294 if (buff != NULL && size > 0) {
6295 c->Header.SGList = 1;
50a0decf 6296 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6297 } else {
6298 c->Header.SGList = 0;
50a0decf 6299 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6300 }
edd16368
SC		 6301 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6302
edd16368
SC		 6303 if (cmd_type == TYPE_CMD) {
6304 switch (cmd) {
6305 case HPSA_INQUIRY:
6306 /* are we trying to read a vital product page */
b7bb24eb 6307 if (page_code & VPD_PAGE) {
edd16368 6308 c->Request.CDB[1] = 0x01;
b7bb24eb 6309 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6310 }
6311 c->Request.CDBLen = 6;
a505b86f
SC		 6312 c->Request.type_attr_dir =
6313 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6314 c->Request.Timeout = 0;
6315 c->Request.CDB[0] = HPSA_INQUIRY;
6316 c->Request.CDB[4] = size & 0xFF;
6317 break;
6318 case HPSA_REPORT_LOG:
6319 case HPSA_REPORT_PHYS:
6320 /* Talking to controller so It's a physical command
6321 mode = 00 target = 0. Nothing to write.
6322 */
6323 c->Request.CDBLen = 12;
a505b86f
SC		 6324 c->Request.type_attr_dir =
6325 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6326 c->Request.Timeout = 0;
6327 c->Request.CDB[0] = cmd;
6328 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6329 c->Request.CDB[7] = (size >> 16) & 0xFF;
6330 c->Request.CDB[8] = (size >> 8) & 0xFF;
6331 c->Request.CDB[9] = size & 0xFF;
6332 break;
edd16368
SC		 6333 case HPSA_CACHE_FLUSH:
6334 c->Request.CDBLen = 12;
a505b86f
SC		 6335 c->Request.type_attr_dir =
6336 TYPE_ATTR_DIR(cmd_type,
6337 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6338 c->Request.Timeout = 0;
6339 c->Request.CDB[0] = BMIC_WRITE;
6340 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6341 c->Request.CDB[7] = (size >> 8) & 0xFF;
6342 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6343 break;
6344 case TEST_UNIT_READY:
6345 c->Request.CDBLen = 6;
a505b86f
SC		 6346 c->Request.type_attr_dir =
6347 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6348 c->Request.Timeout = 0;
6349 break;
283b4a9b
SC		 6350 case HPSA_GET_RAID_MAP:
6351 c->Request.CDBLen = 12;
a505b86f
SC		 6352 c->Request.type_attr_dir =
6353 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6354 c->Request.Timeout = 0;
6355 c->Request.CDB[0] = HPSA_CISS_READ;
6356 c->Request.CDB[1] = cmd;
6357 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6358 c->Request.CDB[7] = (size >> 16) & 0xFF;
6359 c->Request.CDB[8] = (size >> 8) & 0xFF;
6360 c->Request.CDB[9] = size & 0xFF;
6361 break;
316b221a
SC		 6362 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6363 c->Request.CDBLen = 10;
a505b86f
SC		 6364 c->Request.type_attr_dir =
6365 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6366 c->Request.Timeout = 0;
6367 c->Request.CDB[0] = BMIC_READ;
6368 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6369 c->Request.CDB[7] = (size >> 16) & 0xFF;
6370 c->Request.CDB[8] = (size >> 8) & 0xFF;
6371 break;
03383736
DB		 6372 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6373 c->Request.CDBLen = 10;
6374 c->Request.type_attr_dir =
6375 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6376 c->Request.Timeout = 0;
6377 c->Request.CDB[0] = BMIC_READ;
6378 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6379 c->Request.CDB[7] = (size >> 16) & 0xFF;
6380 c->Request.CDB[8] = (size >> 8) & 0XFF;
6381 break;
edd16368
SC		 6382 default:
6383 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6384 BUG();
a2dac136 6385 return -1;
edd16368
SC		 6386 }
6387 } else if (cmd_type == TYPE_MSG) {
6388 switch (cmd) {
6389
0b9b7b6e
ST		 6390 case HPSA_PHYS_TARGET_RESET:
6391 c->Request.CDBLen = 16;
6392 c->Request.type_attr_dir =
6393 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6394 c->Request.Timeout = 0; /* Don't time out */
6395 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6396 c->Request.CDB[0] = HPSA_RESET;
6397 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6398 /* Physical target reset needs no control bytes 4-7*/
6399 c->Request.CDB[4] = 0x00;
6400 c->Request.CDB[5] = 0x00;
6401 c->Request.CDB[6] = 0x00;
6402 c->Request.CDB[7] = 0x00;
6403 break;
edd16368
SC		 6404 case HPSA_DEVICE_RESET_MSG:
6405 c->Request.CDBLen = 16;
a505b86f
SC		 6406 c->Request.type_attr_dir =
6407 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6408 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6409 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6410 c->Request.CDB[0] = cmd;
21e89afd 6411 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6412 /* If bytes 4-7 are zero, it means reset the */
6413 /* LunID device */
6414 c->Request.CDB[4] = 0x00;
6415 c->Request.CDB[5] = 0x00;
6416 c->Request.CDB[6] = 0x00;
6417 c->Request.CDB[7] = 0x00;
75167d2c
SC		 6418 break;
6419 case HPSA_ABORT_MSG:
9b5c48c2 6420 memcpy(&tag, buff, sizeof(tag));
2b08b3e9 6421 dev_dbg(&h->pdev->dev,
9b5c48c2
SC		 6422 "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
6423 tag, c->Header.tag);
75167d2c 6424 c->Request.CDBLen = 16;
a505b86f
SC		 6425 c->Request.type_attr_dir =
6426 TYPE_ATTR_DIR(cmd_type,
6427 ATTR_SIMPLE, XFER_WRITE);
75167d2c
SC		 6428 c->Request.Timeout = 0; /* Don't time out */
6429 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
6430 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
6431 c->Request.CDB[2] = 0x00; /* reserved */
6432 c->Request.CDB[3] = 0x00; /* reserved */
6433 /* Tag to abort goes in CDB[4]-CDB[11] */
9b5c48c2 6434 memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
75167d2c
SC		 6435 c->Request.CDB[12] = 0x00; /* reserved */
6436 c->Request.CDB[13] = 0x00; /* reserved */
6437 c->Request.CDB[14] = 0x00; /* reserved */
6438 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 6439 break;
edd16368
SC		 6440 default:
6441 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6442 cmd);
6443 BUG();
6444 }
6445 } else {
6446 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6447 BUG();
6448 }
6449
a505b86f 6450 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368
SC		 6451 case XFER_READ:
6452 pci_dir = PCI_DMA_FROMDEVICE;
6453 break;
6454 case XFER_WRITE:
6455 pci_dir = PCI_DMA_TODEVICE;
6456 break;
6457 case XFER_NONE:
6458 pci_dir = PCI_DMA_NONE;
6459 break;
6460 default:
6461 pci_dir = PCI_DMA_BIDIRECTIONAL;
6462 }
a2dac136
SC		 6463 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
6464 return -1;
6465 return 0;
edd16368
SC		 6466}
6467
6468/*
6469 * Map (physical) PCI mem into (virtual) kernel space
6470 */
6471static void __iomem *remap_pci_mem(ulong base, ulong size)
6472{
6473 ulong page_base = ((ulong) base) & PAGE_MASK;
6474 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6475 void __iomem *page_remapped = ioremap_nocache(page_base,
6476 page_offs + size);
edd16368
SC		 6477
6478 return page_remapped ? (page_remapped + page_offs) : NULL;
6479}
6480
254f796b 6481static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6482{
254f796b 6483 return h->access.command_completed(h, q);
edd16368
SC		 6484}
6485
900c5440 6486static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6487{
6488 return h->access.intr_pending(h);
6489}
6490
6491static inline long interrupt_not_for_us(struct ctlr_info *h)
6492{
10f66018
SC		 6493 return (h->access.intr_pending(h) == 0) ||
6494 (h->interrupts_enabled == 0);
edd16368
SC		 6495}
6496
01a02ffc
SC		 6497static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6498 u32 raw_tag)
edd16368
SC		 6499{
6500 if (unlikely(tag_index >= h->nr_cmds)) {
6501 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6502 return 1;
6503 }
6504 return 0;
6505}
6506
5a3d16f5 6507static inline void finish_cmd(struct CommandList *c)
edd16368 6508{
e85c5974 6509 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6510 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6511 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6512 complete_scsi_command(c);
8be986cc 6513 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6514 complete(c->waiting);
a104c99f
SC		 6515}
6516
303932fd 6517/* process completion of an indexed ("direct lookup") command */
1d94f94d 6518static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6519 u32 raw_tag)
6520{
6521 u32 tag_index;
6522 struct CommandList *c;
6523
f2405db8 6524 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6525 if (!bad_tag(h, tag_index, raw_tag)) {
6526 c = h->cmd_pool + tag_index;
6527 finish_cmd(c);
6528 }
303932fd
DB		 6529}
6530
64670ac8
SC		 6531/* Some controllers, like p400, will give us one interrupt
6532 * after a soft reset, even if we turned interrupts off.
6533 * Only need to check for this in the hpsa_xxx_discard_completions
6534 * functions.
6535 */
6536static int ignore_bogus_interrupt(struct ctlr_info *h)
6537{
6538 if (likely(!reset_devices))
6539 return 0;
6540
6541 if (likely(h->interrupts_enabled))
6542 return 0;
6543
6544 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6545 "(known firmware bug.) Ignoring.\n");
6546
6547 return 1;
6548}
6549
254f796b
MG		 6550/*
6551 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6552 * Relies on (h-q[x] == x) being true for x such that
6553 * 0 <= x < MAX_REPLY_QUEUES.
6554 */
6555static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6556{
254f796b
MG		 6557 return container_of((queue - *queue), struct ctlr_info, q[0]);
6558}
6559
6560static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6561{
6562 struct ctlr_info *h = queue_to_hba(queue);
6563 u8 q = *(u8 *) queue;
64670ac8
SC		 6564 u32 raw_tag;
6565
6566 if (ignore_bogus_interrupt(h))
6567 return IRQ_NONE;
6568
6569 if (interrupt_not_for_us(h))
6570 return IRQ_NONE;
a0c12413 6571 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6572 while (interrupt_pending(h)) {
254f796b 6573 raw_tag = get_next_completion(h, q);
64670ac8 6574 while (raw_tag != FIFO_EMPTY)
254f796b 6575 raw_tag = next_command(h, q);
64670ac8 6576 }
64670ac8
SC		 6577 return IRQ_HANDLED;
6578}
6579
254f796b 6580static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6581{
254f796b 6582 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6583 u32 raw_tag;
254f796b 6584 u8 q = *(u8 *) queue;
64670ac8
SC		 6585
6586 if (ignore_bogus_interrupt(h))
6587 return IRQ_NONE;
6588
a0c12413 6589 h->last_intr_timestamp = get_jiffies_64();
254f796b 6590 raw_tag = get_next_completion(h, q);
64670ac8 6591 while (raw_tag != FIFO_EMPTY)
254f796b 6592 raw_tag = next_command(h, q);
64670ac8
SC		 6593 return IRQ_HANDLED;
6594}
6595
254f796b 6596static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6597{
254f796b 6598 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6599 u32 raw_tag;
254f796b 6600 u8 q = *(u8 *) queue;
edd16368
SC		 6601
6602 if (interrupt_not_for_us(h))
6603 return IRQ_NONE;
a0c12413 6604 h->last_intr_timestamp = get_jiffies_64();
10f66018 6605 while (interrupt_pending(h)) {
254f796b 6606 raw_tag = get_next_completion(h, q);
10f66018 6607 while (raw_tag != FIFO_EMPTY) {
f2405db8 6608 process_indexed_cmd(h, raw_tag);
254f796b 6609 raw_tag = next_command(h, q);
10f66018
SC		 6610 }
6611 }
10f66018
SC		 6612 return IRQ_HANDLED;
6613}
6614
254f796b 6615static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6616{
254f796b 6617 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6618 u32 raw_tag;
254f796b 6619 u8 q = *(u8 *) queue;
10f66018 6620
a0c12413 6621 h->last_intr_timestamp = get_jiffies_64();
254f796b 6622 raw_tag = get_next_completion(h, q);
303932fd 6623 while (raw_tag != FIFO_EMPTY) {
f2405db8 6624 process_indexed_cmd(h, raw_tag);
254f796b 6625 raw_tag = next_command(h, q);
edd16368 6626 }
edd16368
SC		 6627 return IRQ_HANDLED;
6628}
6629
a9a3a273
SC		 6630/* Send a message CDB to the firmware. Careful, this only works
6631 * in simple mode, not performant mode due to the tag lookup.
6632 * We only ever use this immediately after a controller reset.
6633 */
6f039790
GKH		 6634static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6635 unsigned char type)
edd16368
SC		 6636{
6637 struct Command {
6638 struct CommandListHeader CommandHeader;
6639 struct RequestBlock Request;
6640 struct ErrDescriptor ErrorDescriptor;
6641 };
6642 struct Command *cmd;
6643 static const size_t cmd_sz = sizeof(*cmd) +
6644 sizeof(cmd->ErrorDescriptor);
6645 dma_addr_t paddr64;
2b08b3e9
DB		 6646 __le32 paddr32;
6647 u32 tag;
edd16368
SC		 6648 void __iomem *vaddr;
6649 int i, err;
6650
6651 vaddr = pci_ioremap_bar(pdev, 0);
6652 if (vaddr == NULL)
6653 return -ENOMEM;
6654
6655 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
6656 * CCISS commands, so they must be allocated from the lower 4GiB of
6657 * memory.
6658 */
6659 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
6660 if (err) {
6661 iounmap(vaddr);
1eaec8f3 6662 return err;
edd16368
SC		 6663 }
6664
6665 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
6666 if (cmd == NULL) {
6667 iounmap(vaddr);
6668 return -ENOMEM;
6669 }
6670
6671 /* This must fit, because of the 32-bit consistent DMA mask. Also,
6672 * although there's no guarantee, we assume that the address is at
6673 * least 4-byte aligned (most likely, it's page-aligned).
6674 */
2b08b3e9 6675 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 6676
6677 cmd->CommandHeader.ReplyQueue = 0;
6678 cmd->CommandHeader.SGList = 0;
50a0decf 6679 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 6680 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 6681 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
6682
6683 cmd->Request.CDBLen = 16;
a505b86f
SC		 6684 cmd->Request.type_attr_dir =
6685 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 6686 cmd->Request.Timeout = 0; /* Don't time out */
6687 cmd->Request.CDB[0] = opcode;
6688 cmd->Request.CDB[1] = type;
6689 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 6690 cmd->ErrorDescriptor.Addr =
2b08b3e9 6691 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 6692 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 6693
2b08b3e9 6694 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 6695
6696 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
6697 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 6698 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 6699 break;
6700 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
6701 }
6702
6703 iounmap(vaddr);
6704
6705 /* we leak the DMA buffer here ... no choice since the controller could
6706 * still complete the command.
6707 */
6708 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
6709 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
6710 opcode, type);
6711 return -ETIMEDOUT;
6712 }
6713
6714 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
6715
6716 if (tag & HPSA_ERROR_BIT) {
6717 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
6718 opcode, type);
6719 return -EIO;
6720 }
6721
6722 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
6723 opcode, type);
6724 return 0;
6725}
6726
edd16368
SC		 6727#define hpsa_noop(p) hpsa_message(p, 3, 0)
6728
1df8552a 6729static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 6730 void __iomem *vaddr, u32 use_doorbell)
1df8552a 6731{
1df8552a
SC		 6732
6733 if (use_doorbell) {
6734 /* For everything after the P600, the PCI power state method
6735 * of resetting the controller doesn't work, so we have this
6736 * other way using the doorbell register.
6737 */
6738 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 6739 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 6740
00701a96 6741 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 6742 * doorbell reset and before any attempt to talk to the board
6743 * at all to ensure that this actually works and doesn't fall
6744 * over in some weird corner cases.
6745 */
00701a96 6746 msleep(10000);
1df8552a
SC		 6747 } else { /* Try to do it the PCI power state way */
6748
6749 /* Quoting from the Open CISS Specification: "The Power
6750 * Management Control/Status Register (CSR) controls the power
6751 * state of the device. The normal operating state is D0,
6752 * CSR=00h. The software off state is D3, CSR=03h. To reset
6753 * the controller, place the interface device in D3 then to D0,
6754 * this causes a secondary PCI reset which will reset the
6755 * controller." */
2662cab8
DB		 6756
6757 int rc = 0;
6758
1df8552a 6759 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 6760
1df8552a 6761 /* enter the D3hot power management state */
2662cab8
DB		 6762 rc = pci_set_power_state(pdev, PCI_D3hot);
6763 if (rc)
6764 return rc;
1df8552a
SC		 6765
6766 msleep(500);
6767
6768 /* enter the D0 power management state */
2662cab8
DB		 6769 rc = pci_set_power_state(pdev, PCI_D0);
6770 if (rc)
6771 return rc;
c4853efe
MM		 6772
6773 /*
6774 * The P600 requires a small delay when changing states.
6775 * Otherwise we may think the board did not reset and we bail.
6776 * This for kdump only and is particular to the P600.
6777 */
6778 msleep(500);
1df8552a
SC		 6779 }
6780 return 0;
6781}
6782
6f039790 6783static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 6784{
6785 memset(driver_version, 0, len);
f79cfec6 6786 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 6787}
6788
6f039790 6789static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6790{
6791 char *driver_version;
6792 int i, size = sizeof(cfgtable->driver_version);
6793
6794 driver_version = kmalloc(size, GFP_KERNEL);
6795 if (!driver_version)
6796 return -ENOMEM;
6797
6798 init_driver_version(driver_version, size);
6799 for (i = 0; i < size; i++)
6800 writeb(driver_version[i], &cfgtable->driver_version[i]);
6801 kfree(driver_version);
6802 return 0;
6803}
6804
6f039790
GKH		 6805static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
6806 unsigned char *driver_ver)
580ada3c
SC		 6807{
6808 int i;
6809
6810 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
6811 driver_ver[i] = readb(&cfgtable->driver_version[i]);
6812}
6813
6f039790 6814static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 6815{
6816
6817 char *driver_ver, *old_driver_ver;
6818 int rc, size = sizeof(cfgtable->driver_version);
6819
6820 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
6821 if (!old_driver_ver)
6822 return -ENOMEM;
6823 driver_ver = old_driver_ver + size;
6824
6825 /* After a reset, the 32 bytes of "driver version" in the cfgtable
6826 * should have been changed, otherwise we know the reset failed.
6827 */
6828 init_driver_version(old_driver_ver, size);
6829 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
6830 rc = !memcmp(driver_ver, old_driver_ver, size);
6831 kfree(old_driver_ver);
6832 return rc;
6833}
edd16368 6834/* This does a hard reset of the controller using PCI power management
1df8552a 6835 * states or the using the doorbell register.
edd16368 6836 */
6b6c1cd7 6837static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 6838{
1df8552a
SC		 6839 u64 cfg_offset;
6840 u32 cfg_base_addr;
6841 u64 cfg_base_addr_index;
6842 void __iomem *vaddr;
6843 unsigned long paddr;
580ada3c 6844 u32 misc_fw_support;
270d05de 6845 int rc;
1df8552a 6846 struct CfgTable __iomem *cfgtable;
cf0b08d0 6847 u32 use_doorbell;
270d05de 6848 u16 command_register;
edd16368 6849
1df8552a
SC		 6850 /* For controllers as old as the P600, this is very nearly
6851 * the same thing as
edd16368
SC		 6852 *
6853 * pci_save_state(pci_dev);
6854 * pci_set_power_state(pci_dev, PCI_D3hot);
6855 * pci_set_power_state(pci_dev, PCI_D0);
6856 * pci_restore_state(pci_dev);
6857 *
1df8552a
SC		 6858 * For controllers newer than the P600, the pci power state
6859 * method of resetting doesn't work so we have another way
6860 * using the doorbell register.
edd16368 6861 */
18867659 6862
60f923b9
RE		 6863 if (!ctlr_is_resettable(board_id)) {
6864 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 6865 return -ENODEV;
6866 }
46380786
SC		 6867
6868 /* if controller is soft- but not hard resettable... */
6869 if (!ctlr_is_hard_resettable(board_id))
6870 return -ENOTSUPP; /* try soft reset later. */
18867659 6871
270d05de
SC		 6872 /* Save the PCI command register */
6873 pci_read_config_word(pdev, 4, &command_register);
270d05de 6874 pci_save_state(pdev);
edd16368 6875
1df8552a
SC		 6876 /* find the first memory BAR, so we can find the cfg table */
6877 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
6878 if (rc)
6879 return rc;
6880 vaddr = remap_pci_mem(paddr, 0x250);
6881 if (!vaddr)
6882 return -ENOMEM;
edd16368 6883
1df8552a
SC		 6884 /* find cfgtable in order to check if reset via doorbell is supported */
6885 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
6886 &cfg_base_addr_index, &cfg_offset);
6887 if (rc)
6888 goto unmap_vaddr;
6889 cfgtable = remap_pci_mem(pci_resource_start(pdev,
6890 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
6891 if (!cfgtable) {
6892 rc = -ENOMEM;
6893 goto unmap_vaddr;
6894 }
580ada3c
SC		 6895 rc = write_driver_ver_to_cfgtable(cfgtable);
6896 if (rc)
03741d95 6897 goto unmap_cfgtable;
edd16368 6898
cf0b08d0
SC		 6899 /* If reset via doorbell register is supported, use that.
6900 * There are two such methods. Favor the newest method.
6901 */
1df8552a 6902 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 6903 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
6904 if (use_doorbell) {
6905 use_doorbell = DOORBELL_CTLR_RESET2;
6906 } else {
6907 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
6908 if (use_doorbell) {
050f7147
SC		 6909 dev_warn(&pdev->dev,
6910 "Soft reset not supported. Firmware update is required.\n");
64670ac8 6911 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 6912 goto unmap_cfgtable;
6913 }
6914 }
edd16368 6915
1df8552a
SC		 6916 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
6917 if (rc)
6918 goto unmap_cfgtable;
edd16368 6919
270d05de 6920 pci_restore_state(pdev);
270d05de 6921 pci_write_config_word(pdev, 4, command_register);
edd16368 6922
1df8552a
SC		 6923 /* Some devices (notably the HP Smart Array 5i Controller)
6924 need a little pause here */
6925 msleep(HPSA_POST_RESET_PAUSE_MSECS);
6926
fe5389c8
SC		 6927 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
6928 if (rc) {
6929 dev_warn(&pdev->dev,
050f7147 6930 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 6931 goto unmap_cfgtable;
6932 }
fe5389c8 6933
580ada3c
SC		 6934 rc = controller_reset_failed(vaddr);
6935 if (rc < 0)
6936 goto unmap_cfgtable;
6937 if (rc) {
64670ac8
SC		 6938 dev_warn(&pdev->dev, "Unable to successfully reset "
6939 "controller. Will try soft reset.\n");
6940 rc = -ENOTSUPP;
580ada3c 6941 } else {
64670ac8 6942 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 6943 }
6944
6945unmap_cfgtable:
6946 iounmap(cfgtable);
6947
6948unmap_vaddr:
6949 iounmap(vaddr);
6950 return rc;
edd16368
SC		 6951}
6952
6953/*
6954 * We cannot read the structure directly, for portability we must use
6955 * the io functions.
6956 * This is for debug only.
6957 */
42a91641 6958static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 6959{
58f8665c 6960#ifdef HPSA_DEBUG
edd16368
SC		 6961 int i;
6962 char temp_name[17];
6963
6964 dev_info(dev, "Controller Configuration information\n");
6965 dev_info(dev, "------------------------------------\n");
6966 for (i = 0; i < 4; i++)
6967 temp_name[i] = readb(&(tb->Signature[i]));
6968 temp_name[4] = '\0';
6969 dev_info(dev, " Signature = %s\n", temp_name);
6970 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
6971 dev_info(dev, " Transport methods supported = 0x%x\n",
6972 readl(&(tb->TransportSupport)));
6973 dev_info(dev, " Transport methods active = 0x%x\n",
6974 readl(&(tb->TransportActive)));
6975 dev_info(dev, " Requested transport Method = 0x%x\n",
6976 readl(&(tb->HostWrite.TransportRequest)));
6977 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
6978 readl(&(tb->HostWrite.CoalIntDelay)));
6979 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
6980 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 6981 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 6982 readl(&(tb->CmdsOutMax)));
6983 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
6984 for (i = 0; i < 16; i++)
6985 temp_name[i] = readb(&(tb->ServerName[i]));
6986 temp_name[16] = '\0';
6987 dev_info(dev, " Server Name = %s\n", temp_name);
6988 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
6989 readl(&(tb->HeartBeat)));
edd16368 6990#endif /* HPSA_DEBUG */
58f8665c 6991}
edd16368
SC		 6992
6993static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
6994{
6995 int i, offset, mem_type, bar_type;
6996
6997 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
6998 return 0;
6999 offset = 0;
7000 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7001 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7002 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7003 offset += 4;
7004 else {
7005 mem_type = pci_resource_flags(pdev, i) &
7006 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7007 switch (mem_type) {
7008 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7009 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7010 offset += 4; /* 32 bit */
7011 break;
7012 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7013 offset += 8;
7014 break;
7015 default: /* reserved in PCI 2.2 */
7016 dev_warn(&pdev->dev,
7017 "base address is invalid\n");
7018 return -1;
7019 break;
7020 }
7021 }
7022 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7023 return i + 1;
7024 }
7025 return -1;
7026}
7027
cc64c817
RE		 7028static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7029{
7030 if (h->msix_vector) {
7031 if (h->pdev->msix_enabled)
7032 pci_disable_msix(h->pdev);
105a3dbc 7033 h->msix_vector = 0;
cc64c817
RE		 7034 } else if (h->msi_vector) {
7035 if (h->pdev->msi_enabled)
7036 pci_disable_msi(h->pdev);
105a3dbc 7037 h->msi_vector = 0;
cc64c817
RE		 7038 }
7039}
7040
edd16368 7041/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7042 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7043 */
6f039790 7044static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 7045{
7046#ifdef CONFIG_PCI_MSI
254f796b
MG		 7047 int err, i;
7048 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
7049
7050 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
7051 hpsa_msix_entries[i].vector = 0;
7052 hpsa_msix_entries[i].entry = i;
7053 }
edd16368
SC		 7054
7055 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 7056 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
7057 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 7058 goto default_int_mode;
55c06c71 7059 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
050f7147 7060 dev_info(&h->pdev->dev, "MSI-X capable controller\n");
eee0f03a 7061 h->msix_vector = MAX_REPLY_QUEUES;
f89439bc
SC		 7062 if (h->msix_vector > num_online_cpus())
7063 h->msix_vector = num_online_cpus();
18fce3c4
AG		 7064 err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
7065 1, h->msix_vector);
7066 if (err < 0) {
7067 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
7068 h->msix_vector = 0;
7069 goto single_msi_mode;
7070 } else if (err < h->msix_vector) {
55c06c71 7071 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 7072 "available\n", err);
edd16368 7073 }
18fce3c4
AG		 7074 h->msix_vector = err;
7075 for (i = 0; i < h->msix_vector; i++)
7076 h->intr[i] = hpsa_msix_entries[i].vector;
7077 return;
edd16368 7078 }
18fce3c4 7079single_msi_mode:
55c06c71 7080 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
050f7147 7081 dev_info(&h->pdev->dev, "MSI capable controller\n");
55c06c71 7082 if (!pci_enable_msi(h->pdev))
edd16368
SC		 7083 h->msi_vector = 1;
7084 else
55c06c71 7085 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 7086 }
7087default_int_mode:
7088#endif /* CONFIG_PCI_MSI */
7089 /* if we get here we're going to use the default interrupt mode */
a9a3a273 7090 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 7091}
7092
6f039790 7093static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 7094{
7095 int i;
7096 u32 subsystem_vendor_id, subsystem_device_id;
7097
7098 subsystem_vendor_id = pdev->subsystem_vendor;
7099 subsystem_device_id = pdev->subsystem_device;
7100 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7101 subsystem_vendor_id;
7102
7103 for (i = 0; i < ARRAY_SIZE(products); i++)
7104 if (*board_id == products[i].board_id)
7105 return i;
7106
6798cc0a
SC		 7107 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
7108 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
7109 !hpsa_allow_any) {
e5c880d1
SC		 7110 dev_warn(&pdev->dev, "unrecognized board ID: "
7111 "0x%08x, ignoring.\n", *board_id);
7112 return -ENODEV;
7113 }
7114 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7115}
7116
6f039790
GKH		 7117static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7118 unsigned long *memory_bar)
3a7774ce
SC		 7119{
7120 int i;
7121
7122 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7123 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7124 /* addressing mode bits already removed */
12d2cd47
SC		 7125 *memory_bar = pci_resource_start(pdev, i);
7126 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7127 *memory_bar);
7128 return 0;
7129 }
12d2cd47 7130 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7131 return -ENODEV;
7132}
7133
6f039790
GKH		 7134static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7135 int wait_for_ready)
2c4c8c8b 7136{
fe5389c8 7137 int i, iterations;
2c4c8c8b 7138 u32 scratchpad;
fe5389c8
SC		 7139 if (wait_for_ready)
7140 iterations = HPSA_BOARD_READY_ITERATIONS;
7141 else
7142 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7143
fe5389c8
SC		 7144 for (i = 0; i < iterations; i++) {
7145 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7146 if (wait_for_ready) {
7147 if (scratchpad == HPSA_FIRMWARE_READY)
7148 return 0;
7149 } else {
7150 if (scratchpad != HPSA_FIRMWARE_READY)
7151 return 0;
7152 }
2c4c8c8b
SC		 7153 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7154 }
fe5389c8 7155 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7156 return -ENODEV;
7157}
7158
6f039790
GKH		 7159static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7160 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7161 u64 *cfg_offset)
a51fd47f
SC		 7162{
7163 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7164 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7165 *cfg_base_addr &= (u32) 0x0000ffff;
7166 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7167 if (*cfg_base_addr_index == -1) {
7168 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7169 return -ENODEV;
7170 }
7171 return 0;
7172}
7173
195f2c65
RE		 7174static void hpsa_free_cfgtables(struct ctlr_info *h)
7175{
105a3dbc 7176 if (h->transtable) {
195f2c65 7177 iounmap(h->transtable);
105a3dbc
RE		 7178 h->transtable = NULL;
7179 }
7180 if (h->cfgtable) {
195f2c65 7181 iounmap(h->cfgtable);
105a3dbc
RE		 7182 h->cfgtable = NULL;
7183 }
195f2c65
RE		 7184}
7185
7186/* Find and map CISS config table and transfer table
7187+ * several items must be unmapped (freed) later
7188+ * */
6f039790 7189static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7190{
01a02ffc
SC		 7191 u64 cfg_offset;
7192 u32 cfg_base_addr;
7193 u64 cfg_base_addr_index;
303932fd 7194 u32 trans_offset;
a51fd47f 7195 int rc;
77c4495c 7196
a51fd47f
SC		 7197 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7198 &cfg_base_addr_index, &cfg_offset);
7199 if (rc)
7200 return rc;
77c4495c 7201 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7202 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7203 if (!h->cfgtable) {
7204 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7205 return -ENOMEM;
cd3c81c4 7206 }
580ada3c
SC		 7207 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7208 if (rc)
7209 return rc;
77c4495c 7210 /* Find performant mode table. */
a51fd47f 7211 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7212 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7213 cfg_base_addr_index)+cfg_offset+trans_offset,
7214 sizeof(*h->transtable));
195f2c65
RE		 7215 if (!h->transtable) {
7216 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7217 hpsa_free_cfgtables(h);
77c4495c 7218 return -ENOMEM;
195f2c65 7219 }
77c4495c
SC		 7220 return 0;
7221}
7222
6f039790 7223static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7224{
41ce4c35
SC		 7225#define MIN_MAX_COMMANDS 16
7226 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7227
7228 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7229
7230 /* Limit commands in memory limited kdump scenario. */
7231 if (reset_devices && h->max_commands > 32)
7232 h->max_commands = 32;
7233
41ce4c35
SC		 7234 if (h->max_commands < MIN_MAX_COMMANDS) {
7235 dev_warn(&h->pdev->dev,
7236 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7237 h->max_commands,
7238 MIN_MAX_COMMANDS);
7239 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7240 }
7241}
7242
c7ee65b3
WS		 7243/* If the controller reports that the total max sg entries is greater than 512,
7244 * then we know that chained SG blocks work. (Original smart arrays did not
7245 * support chained SG blocks and would return zero for max sg entries.)
7246 */
7247static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7248{
7249 return h->maxsgentries > 512;
7250}
7251
b93d7536
SC		 7252/* Interrogate the hardware for some limits:
7253 * max commands, max SG elements without chaining, and with chaining,
7254 * SG chain block size, etc.
7255 */
6f039790 7256static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7257{
cba3d38b 7258 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7259 h->nr_cmds = h->max_commands;
b93d7536 7260 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7261 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7262 if (hpsa_supports_chained_sg_blocks(h)) {
7263 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7264 h->max_cmd_sg_entries = 32;
1a63ea6f 7265 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7266 h->maxsgentries--; /* save one for chain pointer */
7267 } else {
c7ee65b3
WS		 7268 /*
7269 * Original smart arrays supported at most 31 s/g entries
7270 * embedded inline in the command (trying to use more
7271 * would lock up the controller)
7272 */
7273 h->max_cmd_sg_entries = 31;
1a63ea6f 7274 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7275 h->chainsize = 0;
b93d7536 7276 }
75167d2c
SC		 7277
7278 /* Find out what task management functions are supported and cache */
7279 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7280 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7281 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7282 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7283 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7284 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7285 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7286}
7287
76c46e49
SC		 7288static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7289{
0fc9fd40 7290 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7291 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7292 return false;
7293 }
7294 return true;
7295}
7296
97a5e98c 7297static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7298{
97a5e98c 7299 u32 driver_support;
f7c39101 7300
97a5e98c 7301 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7302 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7303#ifdef CONFIG_X86
97a5e98c 7304 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7305#endif
28e13446
SC		 7306 driver_support |= ENABLE_UNIT_ATTN;
7307 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7308}
7309
3d0eab67
SC		 7310/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7311 * in a prefetch beyond physical memory.
7312 */
7313static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7314{
7315 u32 dma_prefetch;
7316
7317 if (h->board_id != 0x3225103C)
7318 return;
7319 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7320 dma_prefetch |= 0x8000;
7321 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7322}
7323
c706a795 7324static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7325{
7326 int i;
7327 u32 doorbell_value;
7328 unsigned long flags;
7329 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7330 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7331 spin_lock_irqsave(&h->lock, flags);
7332 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7333 spin_unlock_irqrestore(&h->lock, flags);
7334 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7335 goto done;
76438d08 7336 /* delay and try again */
007e7aa9 7337 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7338 }
c706a795
RE		 7339 return -ENODEV;
7340done:
7341 return 0;
76438d08
SC		 7342}
7343
c706a795 7344static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7345{
7346 int i;
6eaf46fd
SC		 7347 u32 doorbell_value;
7348 unsigned long flags;
eb6b2ae9
SC		 7349
7350 /* under certain very rare conditions, this can take awhile.
7351 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7352 * as we enter this code.)
7353 */
007e7aa9 7354 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7355 if (h->remove_in_progress)
7356 goto done;
6eaf46fd
SC		 7357 spin_lock_irqsave(&h->lock, flags);
7358 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7359 spin_unlock_irqrestore(&h->lock, flags);
382be668 7360 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7361 goto done;
eb6b2ae9 7362 /* delay and try again */
007e7aa9 7363 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7364 }
c706a795
RE		 7365 return -ENODEV;
7366done:
7367 return 0;
3f4336f3
SC		 7368}
7369
c706a795 7370/* return -ENODEV or other reason on error, 0 on success */
6f039790 7371static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7372{
7373 u32 trans_support;
7374
7375 trans_support = readl(&(h->cfgtable->TransportSupport));
7376 if (!(trans_support & SIMPLE_MODE))
7377 return -ENOTSUPP;
7378
7379 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7380
3f4336f3
SC		 7381 /* Update the field, and then ring the doorbell */
7382 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7383 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7384 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7385 if (hpsa_wait_for_mode_change_ack(h))
7386 goto error;
eb6b2ae9 7387 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7388 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7389 goto error;
960a30e7 7390 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7391 return 0;
283b4a9b 7392error:
050f7147 7393 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7394 return -ENODEV;
eb6b2ae9
SC		 7395}
7396
195f2c65
RE		 7397/* free items allocated or mapped by hpsa_pci_init */
7398static void hpsa_free_pci_init(struct ctlr_info *h)
7399{
7400 hpsa_free_cfgtables(h); /* pci_init 4 */
7401 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7402 h->vaddr = NULL;
195f2c65 7403 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7404 /*
7405 * call pci_disable_device before pci_release_regions per
7406 * Documentation/PCI/pci.txt
7407 */
195f2c65 7408 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7409 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7410}
7411
7412/* several items must be freed later */
6f039790 7413static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7414{
eb6b2ae9 7415 int prod_index, err;
edd16368 7416
e5c880d1
SC		 7417 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
7418 if (prod_index < 0)
60f923b9 7419 return prod_index;
e5c880d1
SC		 7420 h->product_name = products[prod_index].product_name;
7421 h->access = *(products[prod_index].access);
edd16368 7422
9b5c48c2
SC		 7423 h->needs_abort_tags_swizzled =
7424 ctlr_needs_abort_tags_swizzled(h->board_id);
7425
e5a44df8
MG		 7426 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7427 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7428
55c06c71 7429 err = pci_enable_device(h->pdev);
edd16368 7430 if (err) {
195f2c65 7431 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7432 pci_disable_device(h->pdev);
edd16368
SC		 7433 return err;
7434 }
7435
f79cfec6 7436 err = pci_request_regions(h->pdev, HPSA);
edd16368 7437 if (err) {
55c06c71 7438 dev_err(&h->pdev->dev,
195f2c65 7439 "failed to obtain PCI resources\n");
943a7021
RE		 7440 pci_disable_device(h->pdev);
7441 return err;
edd16368 7442 }
4fa604e1
RE		 7443
7444 pci_set_master(h->pdev);
7445
6b3f4c52 7446 hpsa_interrupt_mode(h);
12d2cd47 7447 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7448 if (err)
195f2c65 7449 goto clean2; /* intmode+region, pci */
edd16368 7450 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7451 if (!h->vaddr) {
195f2c65 7452 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7453 err = -ENOMEM;
195f2c65 7454 goto clean2; /* intmode+region, pci */
204892e9 7455 }
fe5389c8 7456 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7457 if (err)
195f2c65 7458 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7459 err = hpsa_find_cfgtables(h);
7460 if (err)
195f2c65 7461 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7462 hpsa_find_board_params(h);
edd16368 7463
76c46e49 7464 if (!hpsa_CISS_signature_present(h)) {
edd16368 7465 err = -ENODEV;
195f2c65 7466 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7467 }
97a5e98c 7468 hpsa_set_driver_support_bits(h);
3d0eab67 7469 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7470 err = hpsa_enter_simple_mode(h);
7471 if (err)
195f2c65 7472 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7473 return 0;
7474
195f2c65
RE		 7475clean4: /* cfgtables, vaddr, intmode+region, pci */
7476 hpsa_free_cfgtables(h);
7477clean3: /* vaddr, intmode+region, pci */
7478 iounmap(h->vaddr);
105a3dbc 7479 h->vaddr = NULL;
195f2c65
RE		 7480clean2: /* intmode+region, pci */
7481 hpsa_disable_interrupt_mode(h);
943a7021
RE		 7482 /*
7483 * call pci_disable_device before pci_release_regions per
7484 * Documentation/PCI/pci.txt
7485 */
195f2c65 7486 pci_disable_device(h->pdev);
943a7021 7487 pci_release_regions(h->pdev);
edd16368
SC		 7488 return err;
7489}
7490
6f039790 7491static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7492{
7493 int rc;
7494
7495#define HBA_INQUIRY_BYTE_COUNT 64
7496 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7497 if (!h->hba_inquiry_data)
7498 return;
7499 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7500 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7501 if (rc != 0) {
7502 kfree(h->hba_inquiry_data);
7503 h->hba_inquiry_data = NULL;
7504 }
7505}
7506
6b6c1cd7 7507static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7508{
1df8552a 7509 int rc, i;
3b747298 7510 void __iomem *vaddr;
4c2a8c40
SC		 7511
7512 if (!reset_devices)
7513 return 0;
7514
132aa220
TH		 7515 /* kdump kernel is loading, we don't know in which state is
7516 * the pci interface. The dev->enable_cnt is equal zero
7517 * so we call enable+disable, wait a while and switch it on.
7518 */
7519 rc = pci_enable_device(pdev);
7520 if (rc) {
7521 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7522 return -ENODEV;
7523 }
7524 pci_disable_device(pdev);
7525 msleep(260); /* a randomly chosen number */
7526 rc = pci_enable_device(pdev);
7527 if (rc) {
7528 dev_warn(&pdev->dev, "failed to enable device.\n");
7529 return -ENODEV;
7530 }
4fa604e1 7531
859c75ab 7532 pci_set_master(pdev);
4fa604e1 7533
3b747298
TH		 7534 vaddr = pci_ioremap_bar(pdev, 0);
7535 if (vaddr == NULL) {
7536 rc = -ENOMEM;
7537 goto out_disable;
7538 }
7539 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7540 iounmap(vaddr);
7541
1df8552a 7542 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7543 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7544
1df8552a
SC		 7545 /* -ENOTSUPP here means we cannot reset the controller
7546 * but it's already (and still) up and running in
18867659
SC		 7547 * "performant mode". Or, it might be 640x, which can't reset
7548 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7549 */
adf1b3a3 7550 if (rc)
132aa220 7551 goto out_disable;
4c2a8c40
SC		 7552
7553 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7554 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7555 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7556 if (hpsa_noop(pdev) == 0)
7557 break;
7558 else
7559 dev_warn(&pdev->dev, "no-op failed%s\n",
7560 (i < 11 ? "; re-trying" : ""));
7561 }
132aa220
TH		 7562
7563out_disable:
7564
7565 pci_disable_device(pdev);
7566 return rc;
4c2a8c40
SC		 7567}
7568
1fb7c98a
RE		 7569static void hpsa_free_cmd_pool(struct ctlr_info *h)
7570{
7571 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7572 h->cmd_pool_bits = NULL;
7573 if (h->cmd_pool) {
1fb7c98a
RE		 7574 pci_free_consistent(h->pdev,
7575 h->nr_cmds * sizeof(struct CommandList),
7576 h->cmd_pool,
7577 h->cmd_pool_dhandle);
105a3dbc
RE		 7578 h->cmd_pool = NULL;
7579 h->cmd_pool_dhandle = 0;
7580 }
7581 if (h->errinfo_pool) {
1fb7c98a
RE		 7582 pci_free_consistent(h->pdev,
7583 h->nr_cmds * sizeof(struct ErrorInfo),
7584 h->errinfo_pool,
7585 h->errinfo_pool_dhandle);
105a3dbc
RE		 7586 h->errinfo_pool = NULL;
7587 h->errinfo_pool_dhandle = 0;
7588 }
1fb7c98a
RE		 7589}
7590
d37ffbe4 7591static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 7592{
7593 h->cmd_pool_bits = kzalloc(
7594 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
7595 sizeof(unsigned long), GFP_KERNEL);
7596 h->cmd_pool = pci_alloc_consistent(h->pdev,
7597 h->nr_cmds * sizeof(*h->cmd_pool),
7598 &(h->cmd_pool_dhandle));
7599 h->errinfo_pool = pci_alloc_consistent(h->pdev,
7600 h->nr_cmds * sizeof(*h->errinfo_pool),
7601 &(h->errinfo_pool_dhandle));
7602 if ((h->cmd_pool_bits == NULL)
7603 || (h->cmd_pool == NULL)
7604 || (h->errinfo_pool == NULL)) {
7605 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7606 goto clean_up;
2e9d1b36 7607 }
360c73bd 7608 hpsa_preinitialize_commands(h);
2e9d1b36 7609 return 0;
2c143342
RE		 7610clean_up:
7611 hpsa_free_cmd_pool(h);
7612 return -ENOMEM;
2e9d1b36
SC		 7613}
7614
41b3cf08
SC		 7615static void hpsa_irq_affinity_hints(struct ctlr_info *h)
7616{
ec429952 7617 int i, cpu;
41b3cf08
SC		 7618
7619 cpu = cpumask_first(cpu_online_mask);
7620 for (i = 0; i < h->msix_vector; i++) {
ec429952 7621 irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
41b3cf08
SC		 7622 cpu = cpumask_next(cpu, cpu_online_mask);
7623 }
7624}
7625
ec501a18
RE		 7626/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7627static void hpsa_free_irqs(struct ctlr_info *h)
7628{
7629 int i;
7630
7631 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
7632 /* Single reply queue, only one irq to free */
7633 i = h->intr_mode;
7634 irq_set_affinity_hint(h->intr[i], NULL);
7635 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7636 h->q[i] = 0;
ec501a18
RE		 7637 return;
7638 }
7639
7640 for (i = 0; i < h->msix_vector; i++) {
7641 irq_set_affinity_hint(h->intr[i], NULL);
7642 free_irq(h->intr[i], &h->q[i]);
105a3dbc 7643 h->q[i] = 0;
ec501a18 7644 }
a4e17fc1
RE		 7645 for (; i < MAX_REPLY_QUEUES; i++)
7646 h->q[i] = 0;
ec501a18
RE		 7647}
7648
9ee61794
RE		 7649/* returns 0 on success; cleans up and returns -Enn on error */
7650static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7651 irqreturn_t (*msixhandler)(int, void *),
7652 irqreturn_t (*intxhandler)(int, void *))
7653{
254f796b 7654 int rc, i;
0ae01a32 7655
254f796b
MG		 7656 /*
7657 * initialize h->q[x] = x so that interrupt handlers know which
7658 * queue to process.
7659 */
7660 for (i = 0; i < MAX_REPLY_QUEUES; i++)
7661 h->q[i] = (u8) i;
7662
eee0f03a 7663 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 7664 /* If performant mode and MSI-X, use multiple reply queues */
a4e17fc1 7665 for (i = 0; i < h->msix_vector; i++) {
8b47004a 7666 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
254f796b 7667 rc = request_irq(h->intr[i], msixhandler,
8b47004a 7668 0, h->intrname[i],
254f796b 7669 &h->q[i]);
a4e17fc1
RE		 7670 if (rc) {
7671 int j;
7672
7673 dev_err(&h->pdev->dev,
7674 "failed to get irq %d for %s\n",
7675 h->intr[i], h->devname);
7676 for (j = 0; j < i; j++) {
7677 free_irq(h->intr[j], &h->q[j]);
7678 h->q[j] = 0;
7679 }
7680 for (; j < MAX_REPLY_QUEUES; j++)
7681 h->q[j] = 0;
7682 return rc;
7683 }
7684 }
41b3cf08 7685 hpsa_irq_affinity_hints(h);
254f796b
MG		 7686 } else {
7687 /* Use single reply pool */
eee0f03a 7688 if (h->msix_vector > 0 || h->msi_vector) {
8b47004a
RE		 7689 if (h->msix_vector)
7690 sprintf(h->intrname[h->intr_mode],
7691 "%s-msix", h->devname);
7692 else
7693 sprintf(h->intrname[h->intr_mode],
7694 "%s-msi", h->devname);
254f796b 7695 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7696 msixhandler, 0,
7697 h->intrname[h->intr_mode],
254f796b
MG		 7698 &h->q[h->intr_mode]);
7699 } else {
8b47004a
RE		 7700 sprintf(h->intrname[h->intr_mode],
7701 "%s-intx", h->devname);
254f796b 7702 rc = request_irq(h->intr[h->intr_mode],
8b47004a
RE		 7703 intxhandler, IRQF_SHARED,
7704 h->intrname[h->intr_mode],
254f796b
MG		 7705 &h->q[h->intr_mode]);
7706 }
105a3dbc 7707 irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
254f796b 7708 }
0ae01a32 7709 if (rc) {
195f2c65 7710 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
0ae01a32 7711 h->intr[h->intr_mode], h->devname);
195f2c65 7712 hpsa_free_irqs(h);
0ae01a32
SC		 7713 return -ENODEV;
7714 }
7715 return 0;
7716}
7717
6f039790 7718static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 7719{
39c53f55 7720 int rc;
bf43caf3 7721 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 7722
7723 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 7724 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
7725 if (rc) {
64670ac8 7726 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 7727 return rc;
64670ac8
SC		 7728 }
7729
7730 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 7731 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
7732 if (rc) {
64670ac8
SC		 7733 dev_warn(&h->pdev->dev, "Board failed to become ready "
7734 "after soft reset.\n");
39c53f55 7735 return rc;
64670ac8
SC		 7736 }
7737
7738 return 0;
7739}
7740
072b0518
SC		 7741static void hpsa_free_reply_queues(struct ctlr_info *h)
7742{
7743 int i;
7744
7745 for (i = 0; i < h->nreply_queues; i++) {
7746 if (!h->reply_queue[i].head)
7747 continue;
1fb7c98a
RE		 7748 pci_free_consistent(h->pdev,
7749 h->reply_queue_size,
7750 h->reply_queue[i].head,
7751 h->reply_queue[i].busaddr);
072b0518
SC		 7752 h->reply_queue[i].head = NULL;
7753 h->reply_queue[i].busaddr = 0;
7754 }
105a3dbc 7755 h->reply_queue_size = 0;
072b0518
SC		 7756}
7757
0097f0f4
SC		 7758static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
7759{
105a3dbc
RE		 7760 hpsa_free_performant_mode(h); /* init_one 7 */
7761 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
7762 hpsa_free_cmd_pool(h); /* init_one 5 */
7763 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 7764 scsi_host_put(h->scsi_host); /* init_one 3 */
7765 h->scsi_host = NULL; /* init_one 3 */
7766 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 7767 free_percpu(h->lockup_detected); /* init_one 2 */
7768 h->lockup_detected = NULL; /* init_one 2 */
7769 if (h->resubmit_wq) {
7770 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
7771 h->resubmit_wq = NULL;
7772 }
7773 if (h->rescan_ctlr_wq) {
7774 destroy_workqueue(h->rescan_ctlr_wq);
7775 h->rescan_ctlr_wq = NULL;
7776 }
105a3dbc 7777 kfree(h); /* init_one 1 */
64670ac8
SC		 7778}
7779
a0c12413 7780/* Called when controller lockup detected. */
f2405db8 7781static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 7782{
281a7fd0
WS		 7783 int i, refcount;
7784 struct CommandList *c;
25163bd5 7785 int failcount = 0;
a0c12413 7786
080ef1cc 7787 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 7788 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 7789 c = h->cmd_pool + i;
281a7fd0
WS		 7790 refcount = atomic_inc_return(&c->refcount);
7791 if (refcount > 1) {
25163bd5 7792 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 7793 finish_cmd(c);
433b5f4d 7794 atomic_dec(&h->commands_outstanding);
25163bd5 7795 failcount++;
281a7fd0
WS		 7796 }
7797 cmd_free(h, c);
a0c12413 7798 }
25163bd5
WS		 7799 dev_warn(&h->pdev->dev,
7800 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 7801}
7802
094963da
SC		 7803static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
7804{
c8ed0010 7805 int cpu;
094963da 7806
c8ed0010 7807 for_each_online_cpu(cpu) {
094963da
SC		 7808 u32 *lockup_detected;
7809 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
7810 *lockup_detected = value;
094963da
SC		 7811 }
7812 wmb(); /* be sure the per-cpu variables are out to memory */
7813}
7814
a0c12413
SC		 7815static void controller_lockup_detected(struct ctlr_info *h)
7816{
7817 unsigned long flags;
094963da 7818 u32 lockup_detected;
a0c12413 7819
a0c12413
SC		 7820 h->access.set_intr_mask(h, HPSA_INTR_OFF);
7821 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 7822 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
7823 if (!lockup_detected) {
7824 /* no heartbeat, but controller gave us a zero. */
7825 dev_warn(&h->pdev->dev,
25163bd5
WS		 7826 "lockup detected after %d but scratchpad register is zero\n",
7827 h->heartbeat_sample_interval / HZ);
094963da
SC		 7828 lockup_detected = 0xffffffff;
7829 }
7830 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 7831 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 7832 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
7833 lockup_detected, h->heartbeat_sample_interval / HZ);
a0c12413 7834 pci_disable_device(h->pdev);
f2405db8 7835 fail_all_outstanding_cmds(h);
a0c12413
SC		 7836}
7837
25163bd5 7838static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 7839{
7840 u64 now;
7841 u32 heartbeat;
7842 unsigned long flags;
7843
a0c12413
SC		 7844 now = get_jiffies_64();
7845 /* If we've received an interrupt recently, we're ok. */
7846 if (time_after64(h->last_intr_timestamp +
e85c5974 7847 (h->heartbeat_sample_interval), now))
25163bd5 7848 return false;
a0c12413
SC		 7849
7850 /*
7851 * If we've already checked the heartbeat recently, we're ok.
7852 * This could happen if someone sends us a signal. We
7853 * otherwise don't care about signals in this thread.
7854 */
7855 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 7856 (h->heartbeat_sample_interval), now))
25163bd5 7857 return false;
a0c12413
SC		 7858
7859 /* If heartbeat has not changed since we last looked, we're not ok. */
7860 spin_lock_irqsave(&h->lock, flags);
7861 heartbeat = readl(&h->cfgtable->HeartBeat);
7862 spin_unlock_irqrestore(&h->lock, flags);
7863 if (h->last_heartbeat == heartbeat) {
7864 controller_lockup_detected(h);
25163bd5 7865 return true;
a0c12413
SC		 7866 }
7867
7868 /* We're ok. */
7869 h->last_heartbeat = heartbeat;
7870 h->last_heartbeat_timestamp = now;
25163bd5 7871 return false;
a0c12413
SC		 7872}
7873
9846590e 7874static void hpsa_ack_ctlr_events(struct ctlr_info *h)
76438d08
SC		 7875{
7876 int i;
7877 char *event_type;
7878
e4aa3e6a
SC		 7879 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
7880 return;
7881
76438d08 7882 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 7883 if ((h->transMethod & (CFGTBL_Trans_io_accel1
7884 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 7885 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
7886 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
7887
7888 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
7889 event_type = "state change";
7890 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
7891 event_type = "configuration change";
7892 /* Stop sending new RAID offload reqs via the IO accelerator */
7893 scsi_block_requests(h->scsi_host);
7894 for (i = 0; i < h->ndevices; i++)
7895 h->dev[i]->offload_enabled = 0;
23100dd9 7896 hpsa_drain_accel_commands(h);
76438d08
SC		 7897 /* Set 'accelerator path config change' bit */
7898 dev_warn(&h->pdev->dev,
7899 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
7900 h->events, event_type);
7901 writel(h->events, &(h->cfgtable->clear_event_notify));
7902 /* Set the "clear event notify field update" bit 6 */
7903 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7904 /* Wait until ctlr clears 'clear event notify field', bit 6 */
7905 hpsa_wait_for_clear_event_notify_ack(h);
7906 scsi_unblock_requests(h->scsi_host);
7907 } else {
7908 /* Acknowledge controller notification events. */
7909 writel(h->events, &(h->cfgtable->clear_event_notify));
7910 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
7911 hpsa_wait_for_clear_event_notify_ack(h);
7912#if 0
7913 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7914 hpsa_wait_for_mode_change_ack(h);
7915#endif
7916 }
9846590e 7917 return;
76438d08
SC		 7918}
7919
7920/* Check a register on the controller to see if there are configuration
7921 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 7922 * we should rescan the controller for devices.
7923 * Also check flag for driver-initiated rescan.
76438d08 7924 */
9846590e 7925static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 7926{
853633e8
DB		 7927 if (h->drv_req_rescan) {
7928 h->drv_req_rescan = 0;
7929 return 1;
7930 }
7931
76438d08 7932 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 7933 return 0;
76438d08
SC		 7934
7935 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 7936 return h->events & RESCAN_REQUIRED_EVENT_BITS;
7937}
76438d08 7938
9846590e
SC		 7939/*
7940 * Check if any of the offline devices have become ready
7941 */
7942static int hpsa_offline_devices_ready(struct ctlr_info *h)
7943{
7944 unsigned long flags;
7945 struct offline_device_entry *d;
7946 struct list_head *this, *tmp;
7947
7948 spin_lock_irqsave(&h->offline_device_lock, flags);
7949 list_for_each_safe(this, tmp, &h->offline_device_list) {
7950 d = list_entry(this, struct offline_device_entry,
7951 offline_list);
7952 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 7953 if (!hpsa_volume_offline(h, d->scsi3addr)) {
7954 spin_lock_irqsave(&h->offline_device_lock, flags);
7955 list_del(&d->offline_list);
7956 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 7957 return 1;
d1fea47c 7958 }
9846590e
SC		 7959 spin_lock_irqsave(&h->offline_device_lock, flags);
7960 }
7961 spin_unlock_irqrestore(&h->offline_device_lock, flags);
7962 return 0;
76438d08
SC		 7963}
7964
6636e7f4 7965static void hpsa_rescan_ctlr_worker(struct work_struct *work)
a0c12413
SC		 7966{
7967 unsigned long flags;
8a98db73 7968 struct ctlr_info *h = container_of(to_delayed_work(work),
6636e7f4
DB		 7969 struct ctlr_info, rescan_ctlr_work);
7970
7971
7972 if (h->remove_in_progress)
8a98db73 7973 return;
9846590e
SC		 7974
7975 if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
7976 scsi_host_get(h->scsi_host);
9846590e
SC		 7977 hpsa_ack_ctlr_events(h);
7978 hpsa_scan_start(h->scsi_host);
7979 scsi_host_put(h->scsi_host);
7980 }
8a98db73 7981 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 7982 if (!h->remove_in_progress)
7983 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
7984 h->heartbeat_sample_interval);
7985 spin_unlock_irqrestore(&h->lock, flags);
7986}
7987
7988static void hpsa_monitor_ctlr_worker(struct work_struct *work)
7989{
7990 unsigned long flags;
7991 struct ctlr_info *h = container_of(to_delayed_work(work),
7992 struct ctlr_info, monitor_ctlr_work);
7993
7994 detect_controller_lockup(h);
7995 if (lockup_detected(h))
a0c12413 7996 return;
6636e7f4
DB		 7997
7998 spin_lock_irqsave(&h->lock, flags);
7999 if (!h->remove_in_progress)
8000 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8001 h->heartbeat_sample_interval);
8002 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8003}
8004
6636e7f4
DB		 8005static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8006 char *name)
8007{
8008 struct workqueue_struct *wq = NULL;
6636e7f4 8009
397ea9cb 8010 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8011 if (!wq)
8012 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8013
8014 return wq;
8015}
8016
6f039790 8017static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8018{
4c2a8c40 8019 int dac, rc;
edd16368 8020 struct ctlr_info *h;
64670ac8
SC		 8021 int try_soft_reset = 0;
8022 unsigned long flags;
6b6c1cd7 8023 u32 board_id;
edd16368
SC		 8024
8025 if (number_of_controllers == 0)
8026 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8027
6b6c1cd7
TH		 8028 rc = hpsa_lookup_board_id(pdev, &board_id);
8029 if (rc < 0) {
8030 dev_warn(&pdev->dev, "Board ID not found\n");
8031 return rc;
8032 }
8033
8034 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8035 if (rc) {
8036 if (rc != -ENOTSUPP)
8037 return rc;
8038 /* If the reset fails in a particular way (it has no way to do
8039 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8040 * a soft reset once we get the controller configured up to the
8041 * point that it can accept a command.
8042 */
8043 try_soft_reset = 1;
8044 rc = 0;
8045 }
8046
8047reinit_after_soft_reset:
edd16368 8048
303932fd
DB		 8049 /* Command structures must be aligned on a 32-byte boundary because
8050 * the 5 lower bits of the address are used by the hardware. and by
8051 * the driver. See comments in hpsa.h for more info.
8052 */
303932fd 8053 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368 8054 h = kzalloc(sizeof(*h), GFP_KERNEL);
105a3dbc
RE		 8055 if (!h) {
8056 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8057 return -ENOMEM;
105a3dbc 8058 }
edd16368 8059
55c06c71 8060 h->pdev = pdev;
105a3dbc 8061
a9a3a273 8062 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8063 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8064 spin_lock_init(&h->lock);
9846590e 8065 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8066 spin_lock_init(&h->scan_lock);
34f0c627 8067 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
9b5c48c2 8068 atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
094963da
SC		 8069
8070 /* Allocate and clear per-cpu variable lockup_detected */
8071 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8072 if (!h->lockup_detected) {
105a3dbc 8073 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8074 rc = -ENOMEM;
2efa5929 8075 goto clean1; /* aer/h */
2a5ac326 8076 }
094963da
SC		 8077 set_lockup_detected_for_all_cpus(h, 0);
8078
55c06c71 8079 rc = hpsa_pci_init(h);
105a3dbc 8080 if (rc)
2946e82b
RE		 8081 goto clean2; /* lu, aer/h */
8082
8083 /* relies on h-> settings made by hpsa_pci_init, including
8084 * interrupt_mode h->intr */
8085 rc = hpsa_scsi_host_alloc(h);
8086 if (rc)
8087 goto clean2_5; /* pci, lu, aer/h */
edd16368 8088
2946e82b 8089 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8090 h->ctlr = number_of_controllers;
8091 number_of_controllers++;
edd16368
SC		 8092
8093 /* configure PCI DMA stuff */
ecd9aad4
SC		 8094 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
8095 if (rc == 0) {
edd16368 8096 dac = 1;
ecd9aad4
SC		 8097 } else {
8098 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
8099 if (rc == 0) {
8100 dac = 0;
8101 } else {
8102 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8103 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8104 }
edd16368
SC		 8105 }
8106
8107 /* make sure the board interrupts are off */
8108 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8109
105a3dbc
RE		 8110 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8111 if (rc)
2946e82b 8112 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8113 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8114 if (rc)
2946e82b 8115 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8116 rc = hpsa_alloc_sg_chain_blocks(h);
8117 if (rc)
2946e82b 8118 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8119 init_waitqueue_head(&h->scan_wait_queue);
9b5c48c2 8120 init_waitqueue_head(&h->abort_cmd_wait_queue);
d604f533
WS		 8121 init_waitqueue_head(&h->event_sync_wait_queue);
8122 mutex_init(&h->reset_mutex);
a08a8471 8123 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 8124
8125 pci_set_drvdata(pdev, h);
9a41338e 8126 h->ndevices = 0;
2946e82b 8127
9a41338e 8128 spin_lock_init(&h->devlock);
105a3dbc
RE		 8129 rc = hpsa_put_ctlr_into_performant_mode(h);
8130 if (rc)
2946e82b
RE		 8131 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8132
8133 /* hook into SCSI subsystem */
8134 rc = hpsa_scsi_add_host(h);
8135 if (rc)
8136 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
2efa5929
RE		 8137
8138 /* create the resubmit workqueue */
8139 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8140 if (!h->rescan_ctlr_wq) {
8141 rc = -ENOMEM;
8142 goto clean7;
8143 }
8144
8145 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8146 if (!h->resubmit_wq) {
8147 rc = -ENOMEM;
8148 goto clean7; /* aer/h */
8149 }
64670ac8 8150
105a3dbc
RE		 8151 /*
8152 * At this point, the controller is ready to take commands.
64670ac8
SC		 8153 * Now, if reset_devices and the hard reset didn't work, try
8154 * the soft reset and see if that works.
8155 */
8156 if (try_soft_reset) {
8157
8158 /* This is kind of gross. We may or may not get a completion
8159 * from the soft reset command, and if we do, then the value
8160 * from the fifo may or may not be valid. So, we wait 10 secs
8161 * after the reset throwing away any completions we get during
8162 * that time. Unregister the interrupt handler and register
8163 * fake ones to scoop up any residual completions.
8164 */
8165 spin_lock_irqsave(&h->lock, flags);
8166 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8167 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8168 hpsa_free_irqs(h);
9ee61794 8169 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8170 hpsa_intx_discard_completions);
8171 if (rc) {
9ee61794
RE		 8172 dev_warn(&h->pdev->dev,
8173 "Failed to request_irq after soft reset.\n");
d498757c 8174 /*
b2ef480c
RE		 8175 * cannot goto clean7 or free_irqs will be called
8176 * again. Instead, do its work
8177 */
8178 hpsa_free_performant_mode(h); /* clean7 */
8179 hpsa_free_sg_chain_blocks(h); /* clean6 */
8180 hpsa_free_cmd_pool(h); /* clean5 */
8181 /*
8182 * skip hpsa_free_irqs(h) clean4 since that
8183 * was just called before request_irqs failed
d498757c
RE		 8184 */
8185 goto clean3;
64670ac8
SC		 8186 }
8187
8188 rc = hpsa_kdump_soft_reset(h);
8189 if (rc)
8190 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8191 goto clean7;
64670ac8
SC		 8192
8193 dev_info(&h->pdev->dev, "Board READY.\n");
8194 dev_info(&h->pdev->dev,
8195 "Waiting for stale completions to drain.\n");
8196 h->access.set_intr_mask(h, HPSA_INTR_ON);
8197 msleep(10000);
8198 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8199
8200 rc = controller_reset_failed(h->cfgtable);
8201 if (rc)
8202 dev_info(&h->pdev->dev,
8203 "Soft reset appears to have failed.\n");
8204
8205 /* since the controller's reset, we have to go back and re-init
8206 * everything. Easiest to just forget what we've done and do it
8207 * all over again.
8208 */
8209 hpsa_undo_allocations_after_kdump_soft_reset(h);
8210 try_soft_reset = 0;
8211 if (rc)
b2ef480c 8212 /* don't goto clean, we already unallocated */
64670ac8
SC		 8213 return -ENODEV;
8214
8215 goto reinit_after_soft_reset;
8216 }
edd16368 8217
105a3dbc
RE		 8218 /* Enable Accelerated IO path at driver layer */
8219 h->acciopath_status = 1;
da0697bd 8220
e863d68e 8221
edd16368
SC		 8222 /* Turn the interrupts on so we can service requests */
8223 h->access.set_intr_mask(h, HPSA_INTR_ON);
8224
339b2b14 8225 hpsa_hba_inquiry(h);
8a98db73
SC		 8226
8227 /* Monitor the controller for firmware lockups */
8228 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8229 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8230 schedule_delayed_work(&h->monitor_ctlr_work,
8231 h->heartbeat_sample_interval);
6636e7f4
DB		 8232 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8233 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8234 h->heartbeat_sample_interval);
88bf6d62 8235 return 0;
edd16368 8236
2946e82b 8237clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8238 hpsa_free_performant_mode(h);
8239 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8240clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8241 hpsa_free_sg_chain_blocks(h);
2946e82b 8242clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8243 hpsa_free_cmd_pool(h);
2946e82b 8244clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8245 hpsa_free_irqs(h);
2946e82b
RE		 8246clean3: /* shost, pci, lu, aer/h */
8247 scsi_host_put(h->scsi_host);
8248 h->scsi_host = NULL;
8249clean2_5: /* pci, lu, aer/h */
195f2c65 8250 hpsa_free_pci_init(h);
2946e82b 8251clean2: /* lu, aer/h */
105a3dbc
RE		 8252 if (h->lockup_detected) {
8253 free_percpu(h->lockup_detected);
8254 h->lockup_detected = NULL;
8255 }
8256clean1: /* wq/aer/h */
8257 if (h->resubmit_wq) {
080ef1cc 8258 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8259 h->resubmit_wq = NULL;
8260 }
8261 if (h->rescan_ctlr_wq) {
6636e7f4 8262 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8263 h->rescan_ctlr_wq = NULL;
8264 }
edd16368 8265 kfree(h);
ecd9aad4 8266 return rc;
edd16368
SC		 8267}
8268
8269static void hpsa_flush_cache(struct ctlr_info *h)
8270{
8271 char *flush_buf;
8272 struct CommandList *c;
25163bd5 8273 int rc;
702890e3 8274
094963da 8275 if (unlikely(lockup_detected(h)))
702890e3 8276 return;
edd16368
SC		 8277 flush_buf = kzalloc(4, GFP_KERNEL);
8278 if (!flush_buf)
8279 return;
8280
45fcb86e 8281 c = cmd_alloc(h);
bf43caf3 8282
a2dac136
SC		 8283 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8284 RAID_CTLR_LUNID, TYPE_CMD)) {
8285 goto out;
8286 }
25163bd5
WS		 8287 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
8288 PCI_DMA_TODEVICE, NO_TIMEOUT);
8289 if (rc)
8290 goto out;
edd16368 8291 if (c->err_info->CommandStatus != 0)
a2dac136 8292out:
edd16368
SC		 8293 dev_warn(&h->pdev->dev,
8294 "error flushing cache on controller\n");
45fcb86e 8295 cmd_free(h, c);
edd16368
SC		 8296 kfree(flush_buf);
8297}
8298
8299static void hpsa_shutdown(struct pci_dev *pdev)
8300{
8301 struct ctlr_info *h;
8302
8303 h = pci_get_drvdata(pdev);
8304 /* Turn board interrupts off and send the flush cache command
8305 * sendcmd will turn off interrupt, and send the flush...
8306 * To write all data in the battery backed cache to disks
8307 */
8308 hpsa_flush_cache(h);
8309 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8310 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8311 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8312}
8313
6f039790 8314static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8315{
8316 int i;
8317
105a3dbc 8318 for (i = 0; i < h->ndevices; i++) {
55e14e76 8319 kfree(h->dev[i]);
105a3dbc
RE		 8320 h->dev[i] = NULL;
8321 }
55e14e76
SC		 8322}
8323
6f039790 8324static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8325{
8326 struct ctlr_info *h;
8a98db73 8327 unsigned long flags;
edd16368
SC		 8328
8329 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8330 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8331 return;
8332 }
8333 h = pci_get_drvdata(pdev);
8a98db73
SC		 8334
8335 /* Get rid of any controller monitoring work items */
8336 spin_lock_irqsave(&h->lock, flags);
8337 h->remove_in_progress = 1;
8a98db73 8338 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8339 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8340 cancel_delayed_work_sync(&h->rescan_ctlr_work);
8341 destroy_workqueue(h->rescan_ctlr_wq);
8342 destroy_workqueue(h->resubmit_wq);
cc64c817 8343
2d041306
DB		 8344 /*
8345 * Call before disabling interrupts.
8346 * scsi_remove_host can trigger I/O operations especially
8347 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8348 * operations which cannot complete and will hang the system.
8349 */
8350 if (h->scsi_host)
8351 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8352 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8353 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
edd16368 8354 hpsa_shutdown(pdev);
cc64c817 8355
105a3dbc
RE		 8356 hpsa_free_device_info(h); /* scan */
8357
2946e82b
RE		 8358 kfree(h->hba_inquiry_data); /* init_one 10 */
8359 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8360 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8361 hpsa_free_performant_mode(h); /* init_one 7 */
8362 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8363 hpsa_free_cmd_pool(h); /* init_one 5 */
8364
8365 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8366
2946e82b
RE		 8367 scsi_host_put(h->scsi_host); /* init_one 3 */
8368 h->scsi_host = NULL; /* init_one 3 */
8369
195f2c65 8370 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8371 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8372
105a3dbc
RE		 8373 free_percpu(h->lockup_detected); /* init_one 2 */
8374 h->lockup_detected = NULL; /* init_one 2 */
8375 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
8376 kfree(h); /* init_one 1 */
edd16368
SC		 8377}
8378
8379static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8380 __attribute__((unused)) pm_message_t state)
8381{
8382 return -ENOSYS;
8383}
8384
8385static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8386{
8387 return -ENOSYS;
8388}
8389
8390static struct pci_driver hpsa_pci_driver = {
f79cfec6 8391 .name = HPSA,
edd16368 8392 .probe = hpsa_init_one,
6f039790 8393 .remove = hpsa_remove_one,
edd16368
SC		 8394 .id_table = hpsa_pci_device_id, /* id_table */
8395 .shutdown = hpsa_shutdown,
8396 .suspend = hpsa_suspend,
8397 .resume = hpsa_resume,
8398};
8399
303932fd
DB		 8400/* Fill in bucket_map[], given nsgs (the max number of
8401 * scatter gather elements supported) and bucket[],
8402 * which is an array of 8 integers. The bucket[] array
8403 * contains 8 different DMA transfer sizes (in 16
8404 * byte increments) which the controller uses to fetch
8405 * commands. This function fills in bucket_map[], which
8406 * maps a given number of scatter gather elements to one of
8407 * the 8 DMA transfer sizes. The point of it is to allow the
8408 * controller to only do as much DMA as needed to fetch the
8409 * command, with the DMA transfer size encoded in the lower
8410 * bits of the command address.
8411 */
8412static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 8413 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 8414{
8415 int i, j, b, size;
8416
303932fd
DB		 8417 /* Note, bucket_map must have nsgs+1 entries. */
8418 for (i = 0; i <= nsgs; i++) {
8419 /* Compute size of a command with i SG entries */
e1f7de0c 8420 size = i + min_blocks;
303932fd
DB		 8421 b = num_buckets; /* Assume the biggest bucket */
8422 /* Find the bucket that is just big enough */
e1f7de0c 8423 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 8424 if (bucket[j] >= size) {
8425 b = j;
8426 break;
8427 }
8428 }
8429 /* for a command with i SG entries, use bucket b. */
8430 bucket_map[i] = b;
8431 }
8432}
8433
105a3dbc
RE		 8434/*
8435 * return -ENODEV on err, 0 on success (or no action)
8436 * allocates numerous items that must be freed later
8437 */
c706a795 8438static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 8439{
6c311b57
SC		 8440 int i;
8441 unsigned long register_value;
e1f7de0c
MG		 8442 unsigned long transMethod = CFGTBL_Trans_Performant |
8443 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 8444 CFGTBL_Trans_enable_directed_msix |
8445 (trans_support & (CFGTBL_Trans_io_accel1 |
8446 CFGTBL_Trans_io_accel2));
e1f7de0c 8447 struct access_method access = SA5_performant_access;
def342bd
SC		 8448
8449 /* This is a bit complicated. There are 8 registers on
8450 * the controller which we write to to tell it 8 different
8451 * sizes of commands which there may be. It's a way of
8452 * reducing the DMA done to fetch each command. Encoded into
8453 * each command's tag are 3 bits which communicate to the controller
8454 * which of the eight sizes that command fits within. The size of
8455 * each command depends on how many scatter gather entries there are.
8456 * Each SG entry requires 16 bytes. The eight registers are programmed
8457 * with the number of 16-byte blocks a command of that size requires.
8458 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 8459 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 8460 * blocks. Note, this only extends to the SG entries contained
8461 * within the command block, and does not extend to chained blocks
8462 * of SG elements. bft[] contains the eight values we write to
8463 * the registers. They are not evenly distributed, but have more
8464 * sizes for small commands, and fewer sizes for larger commands.
8465 */
d66ae08b 8466 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 8467#define MIN_IOACCEL2_BFT_ENTRY 5
8468#define HPSA_IOACCEL2_HEADER_SZ 4
8469 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
8470 13, 14, 15, 16, 17, 18, 19,
8471 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
8472 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
8473 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
8474 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
8475 16 * MIN_IOACCEL2_BFT_ENTRY);
8476 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 8477 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 8478 /* 5 = 1 s/g entry or 4k
8479 * 6 = 2 s/g entry or 8k
8480 * 8 = 4 s/g entry or 16k
8481 * 10 = 6 s/g entry or 24k
8482 */
303932fd 8483
b3a52e79
SC		 8484 /* If the controller supports either ioaccel method then
8485 * we can also use the RAID stack submit path that does not
8486 * perform the superfluous readl() after each command submission.
8487 */
8488 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
8489 access = SA5_performant_access_no_read;
8490
303932fd 8491 /* Controller spec: zero out this buffer. */
072b0518
SC		 8492 for (i = 0; i < h->nreply_queues; i++)
8493 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 8494
d66ae08b
SC		 8495 bft[7] = SG_ENTRIES_IN_CMD + 4;
8496 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 8497 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 8498 for (i = 0; i < 8; i++)
8499 writel(bft[i], &h->transtable->BlockFetch[i]);
8500
8501 /* size of controller ring buffer */
8502 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 8503 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 8504 writel(0, &h->transtable->RepQCtrAddrLow32);
8505 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 8506
8507 for (i = 0; i < h->nreply_queues; i++) {
8508 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 8509 writel(h->reply_queue[i].busaddr,
254f796b
MG		 8510 &h->transtable->RepQAddr[i].lower);
8511 }
8512
b9af4937 8513 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 8514 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
8515 /*
8516 * enable outbound interrupt coalescing in accelerator mode;
8517 */
8518 if (trans_support & CFGTBL_Trans_io_accel1) {
8519 access = SA5_ioaccel_mode1_access;
8520 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8521 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 8522 } else {
8523 if (trans_support & CFGTBL_Trans_io_accel2) {
8524 access = SA5_ioaccel_mode2_access;
8525 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
8526 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
8527 }
e1f7de0c 8528 }
303932fd 8529 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8530 if (hpsa_wait_for_mode_change_ack(h)) {
8531 dev_err(&h->pdev->dev,
8532 "performant mode problem - doorbell timeout\n");
8533 return -ENODEV;
8534 }
303932fd
DB		 8535 register_value = readl(&(h->cfgtable->TransportActive));
8536 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 8537 dev_err(&h->pdev->dev,
8538 "performant mode problem - transport not active\n");
c706a795 8539 return -ENODEV;
303932fd 8540 }
960a30e7 8541 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 8542 h->access = access;
8543 h->transMethod = transMethod;
8544
b9af4937
SC		 8545 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
8546 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 8547 return 0;
e1f7de0c 8548
b9af4937
SC		 8549 if (trans_support & CFGTBL_Trans_io_accel1) {
8550 /* Set up I/O accelerator mode */
8551 for (i = 0; i < h->nreply_queues; i++) {
8552 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
8553 h->reply_queue[i].current_entry =
8554 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
8555 }
8556 bft[7] = h->ioaccel_maxsg + 8;
8557 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
8558 h->ioaccel1_blockFetchTable);
e1f7de0c 8559
b9af4937 8560 /* initialize all reply queue entries to unused */
072b0518
SC		 8561 for (i = 0; i < h->nreply_queues; i++)
8562 memset(h->reply_queue[i].head,
8563 (u8) IOACCEL_MODE1_REPLY_UNUSED,
8564 h->reply_queue_size);
e1f7de0c 8565
b9af4937
SC		 8566 /* set all the constant fields in the accelerator command
8567 * frames once at init time to save CPU cycles later.
8568 */
8569 for (i = 0; i < h->nr_cmds; i++) {
8570 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
8571
8572 cp->function = IOACCEL1_FUNCTION_SCSIIO;
8573 cp->err_info = (u32) (h->errinfo_pool_dhandle +
8574 (i * sizeof(struct ErrorInfo)));
8575 cp->err_info_len = sizeof(struct ErrorInfo);
8576 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 8577 cp->host_context_flags =
8578 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 8579 cp->timeout_sec = 0;
8580 cp->ReplyQueue = 0;
50a0decf 8581 cp->tag =
f2405db8 8582 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 8583 cp->host_addr =
8584 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 8585 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 8586 }
8587 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8588 u64 cfg_offset, cfg_base_addr_index;
8589 u32 bft2_offset, cfg_base_addr;
8590 int rc;
8591
8592 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
8593 &cfg_base_addr_index, &cfg_offset);
8594 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
8595 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
8596 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
8597 4, h->ioaccel2_blockFetchTable);
8598 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
8599 BUILD_BUG_ON(offsetof(struct CfgTable,
8600 io_accel_request_size_offset) != 0xb8);
8601 h->ioaccel2_bft2_regs =
8602 remap_pci_mem(pci_resource_start(h->pdev,
8603 cfg_base_addr_index) +
8604 cfg_offset + bft2_offset,
8605 ARRAY_SIZE(bft2) *
8606 sizeof(*h->ioaccel2_bft2_regs));
8607 for (i = 0; i < ARRAY_SIZE(bft2); i++)
8608 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 8609 }
b9af4937 8610 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 8611 if (hpsa_wait_for_mode_change_ack(h)) {
8612 dev_err(&h->pdev->dev,
8613 "performant mode problem - enabling ioaccel mode\n");
8614 return -ENODEV;
8615 }
8616 return 0;
e1f7de0c
MG		 8617}
8618
1fb7c98a
RE		 8619/* Free ioaccel1 mode command blocks and block fetch table */
8620static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
8621{
105a3dbc 8622 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 8623 pci_free_consistent(h->pdev,
8624 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8625 h->ioaccel_cmd_pool,
8626 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 8627 h->ioaccel_cmd_pool = NULL;
8628 h->ioaccel_cmd_pool_dhandle = 0;
8629 }
1fb7c98a 8630 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 8631 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 8632}
8633
d37ffbe4
RE		 8634/* Allocate ioaccel1 mode command blocks and block fetch table */
8635static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 8636{
283b4a9b
SC		 8637 h->ioaccel_maxsg =
8638 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8639 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
8640 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
8641
e1f7de0c
MG		 8642 /* Command structures must be aligned on a 128-byte boundary
8643 * because the 7 lower bits of the address are used by the
8644 * hardware.
8645 */
e1f7de0c
MG		 8646 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
8647 IOACCEL1_COMMANDLIST_ALIGNMENT);
8648 h->ioaccel_cmd_pool =
8649 pci_alloc_consistent(h->pdev,
8650 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8651 &(h->ioaccel_cmd_pool_dhandle));
8652
8653 h->ioaccel1_blockFetchTable =
283b4a9b 8654 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 8655 sizeof(u32)), GFP_KERNEL);
8656
8657 if ((h->ioaccel_cmd_pool == NULL) ||
8658 (h->ioaccel1_blockFetchTable == NULL))
8659 goto clean_up;
8660
8661 memset(h->ioaccel_cmd_pool, 0,
8662 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
8663 return 0;
8664
8665clean_up:
1fb7c98a 8666 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 8667 return -ENOMEM;
6c311b57
SC		 8668}
8669
1fb7c98a
RE		 8670/* Free ioaccel2 mode command blocks and block fetch table */
8671static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
8672{
d9a729f3
WS		 8673 hpsa_free_ioaccel2_sg_chain_blocks(h);
8674
105a3dbc 8675 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 8676 pci_free_consistent(h->pdev,
8677 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8678 h->ioaccel2_cmd_pool,
8679 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 8680 h->ioaccel2_cmd_pool = NULL;
8681 h->ioaccel2_cmd_pool_dhandle = 0;
8682 }
1fb7c98a 8683 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 8684 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 8685}
8686
d37ffbe4
RE		 8687/* Allocate ioaccel2 mode command blocks and block fetch table */
8688static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 8689{
d9a729f3
WS		 8690 int rc;
8691
aca9012a
SC		 8692 /* Allocate ioaccel2 mode command blocks and block fetch table */
8693
8694 h->ioaccel_maxsg =
8695 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
8696 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
8697 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
8698
aca9012a
SC		 8699 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
8700 IOACCEL2_COMMANDLIST_ALIGNMENT);
8701 h->ioaccel2_cmd_pool =
8702 pci_alloc_consistent(h->pdev,
8703 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8704 &(h->ioaccel2_cmd_pool_dhandle));
8705
8706 h->ioaccel2_blockFetchTable =
8707 kmalloc(((h->ioaccel_maxsg + 1) *
8708 sizeof(u32)), GFP_KERNEL);
8709
8710 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 8711 (h->ioaccel2_blockFetchTable == NULL)) {
8712 rc = -ENOMEM;
8713 goto clean_up;
8714 }
8715
8716 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
8717 if (rc)
aca9012a
SC		 8718 goto clean_up;
8719
8720 memset(h->ioaccel2_cmd_pool, 0,
8721 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
8722 return 0;
8723
8724clean_up:
1fb7c98a 8725 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 8726 return rc;
aca9012a
SC		 8727}
8728
105a3dbc
RE		 8729/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
8730static void hpsa_free_performant_mode(struct ctlr_info *h)
8731{
8732 kfree(h->blockFetchTable);
8733 h->blockFetchTable = NULL;
8734 hpsa_free_reply_queues(h);
8735 hpsa_free_ioaccel1_cmd_and_bft(h);
8736 hpsa_free_ioaccel2_cmd_and_bft(h);
8737}
8738
8739/* return -ENODEV on error, 0 on success (or no action)
8740 * allocates numerous items that must be freed later
8741 */
8742static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 8743{
8744 u32 trans_support;
e1f7de0c
MG		 8745 unsigned long transMethod = CFGTBL_Trans_Performant |
8746 CFGTBL_Trans_use_short_tags;
105a3dbc 8747 int i, rc;
6c311b57 8748
02ec19c8 8749 if (hpsa_simple_mode)
105a3dbc 8750 return 0;
02ec19c8 8751
67c99a72 8752 trans_support = readl(&(h->cfgtable->TransportSupport));
8753 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 8754 return 0;
67c99a72 8755
e1f7de0c
MG		 8756 /* Check for I/O accelerator mode support */
8757 if (trans_support & CFGTBL_Trans_io_accel1) {
8758 transMethod |= CFGTBL_Trans_io_accel1 |
8759 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8760 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
8761 if (rc)
8762 return rc;
8763 } else if (trans_support & CFGTBL_Trans_io_accel2) {
8764 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 8765 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 8766 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
8767 if (rc)
8768 return rc;
e1f7de0c
MG		 8769 }
8770
eee0f03a 8771 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 8772 hpsa_get_max_perf_mode_cmds(h);
6c311b57 8773 /* Performant mode ring buffer and supporting data structures */
072b0518 8774 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 8775
254f796b 8776 for (i = 0; i < h->nreply_queues; i++) {
072b0518
SC		 8777 h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
8778 h->reply_queue_size,
8779 &(h->reply_queue[i].busaddr));
105a3dbc
RE		 8780 if (!h->reply_queue[i].head) {
8781 rc = -ENOMEM;
8782 goto clean1; /* rq, ioaccel */
8783 }
254f796b
MG		 8784 h->reply_queue[i].size = h->max_commands;
8785 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
8786 h->reply_queue[i].current_entry = 0;
8787 }
8788
6c311b57 8789 /* Need a block fetch table for performant mode */
d66ae08b 8790 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 8791 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 8792 if (!h->blockFetchTable) {
8793 rc = -ENOMEM;
8794 goto clean1; /* rq, ioaccel */
8795 }
6c311b57 8796
105a3dbc
RE		 8797 rc = hpsa_enter_performant_mode(h, trans_support);
8798 if (rc)
8799 goto clean2; /* bft, rq, ioaccel */
8800 return 0;
303932fd 8801
105a3dbc 8802clean2: /* bft, rq, ioaccel */
303932fd 8803 kfree(h->blockFetchTable);
105a3dbc
RE		 8804 h->blockFetchTable = NULL;
8805clean1: /* rq, ioaccel */
8806 hpsa_free_reply_queues(h);
8807 hpsa_free_ioaccel1_cmd_and_bft(h);
8808 hpsa_free_ioaccel2_cmd_and_bft(h);
8809 return rc;
303932fd
DB		 8810}
8811
23100dd9 8812static int is_accelerated_cmd(struct CommandList *c)
76438d08 8813{
23100dd9
SC		 8814 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
8815}
8816
8817static void hpsa_drain_accel_commands(struct ctlr_info *h)
8818{
8819 struct CommandList *c = NULL;
f2405db8 8820 int i, accel_cmds_out;
281a7fd0 8821 int refcount;
76438d08 8822
f2405db8 8823 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 8824 accel_cmds_out = 0;
f2405db8 8825 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8826 c = h->cmd_pool + i;
281a7fd0
WS		 8827 refcount = atomic_inc_return(&c->refcount);
8828 if (refcount > 1) /* Command is allocated */
8829 accel_cmds_out += is_accelerated_cmd(c);
8830 cmd_free(h, c);
f2405db8 8831 }
23100dd9 8832 if (accel_cmds_out <= 0)
281a7fd0 8833 break;
76438d08
SC		 8834 msleep(100);
8835 } while (1);
8836}
8837
edd16368
SC		 8838/*
8839 * This is it. Register the PCI driver information for the cards we control
8840 * the OS will call our registered routines when it finds one of our cards.
8841 */
8842static int __init hpsa_init(void)
8843{
31468401 8844 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 8845}
8846
8847static void __exit hpsa_cleanup(void)
8848{
8849 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 8850}
8851
e1f7de0c
MG		 8852static void __attribute__((unused)) verify_offsets(void)
8853{
dd0e19f3
ST		 8854#define VERIFY_OFFSET(member, offset) \
8855 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
8856
8857 VERIFY_OFFSET(structure_size, 0);
8858 VERIFY_OFFSET(volume_blk_size, 4);
8859 VERIFY_OFFSET(volume_blk_cnt, 8);
8860 VERIFY_OFFSET(phys_blk_shift, 16);
8861 VERIFY_OFFSET(parity_rotation_shift, 17);
8862 VERIFY_OFFSET(strip_size, 18);
8863 VERIFY_OFFSET(disk_starting_blk, 20);
8864 VERIFY_OFFSET(disk_blk_cnt, 28);
8865 VERIFY_OFFSET(data_disks_per_row, 36);
8866 VERIFY_OFFSET(metadata_disks_per_row, 38);
8867 VERIFY_OFFSET(row_cnt, 40);
8868 VERIFY_OFFSET(layout_map_count, 42);
8869 VERIFY_OFFSET(flags, 44);
8870 VERIFY_OFFSET(dekindex, 46);
8871 /* VERIFY_OFFSET(reserved, 48 */
8872 VERIFY_OFFSET(data, 64);
8873
8874#undef VERIFY_OFFSET
8875
b66cc250
MM		 8876#define VERIFY_OFFSET(member, offset) \
8877 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
8878
8879 VERIFY_OFFSET(IU_type, 0);
8880 VERIFY_OFFSET(direction, 1);
8881 VERIFY_OFFSET(reply_queue, 2);
8882 /* VERIFY_OFFSET(reserved1, 3); */
8883 VERIFY_OFFSET(scsi_nexus, 4);
8884 VERIFY_OFFSET(Tag, 8);
8885 VERIFY_OFFSET(cdb, 16);
8886 VERIFY_OFFSET(cciss_lun, 32);
8887 VERIFY_OFFSET(data_len, 40);
8888 VERIFY_OFFSET(cmd_priority_task_attr, 44);
8889 VERIFY_OFFSET(sg_count, 45);
8890 /* VERIFY_OFFSET(reserved3 */
8891 VERIFY_OFFSET(err_ptr, 48);
8892 VERIFY_OFFSET(err_len, 56);
8893 /* VERIFY_OFFSET(reserved4 */
8894 VERIFY_OFFSET(sg, 64);
8895
8896#undef VERIFY_OFFSET
8897
e1f7de0c
MG		 8898#define VERIFY_OFFSET(member, offset) \
8899 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
8900
8901 VERIFY_OFFSET(dev_handle, 0x00);
8902 VERIFY_OFFSET(reserved1, 0x02);
8903 VERIFY_OFFSET(function, 0x03);
8904 VERIFY_OFFSET(reserved2, 0x04);
8905 VERIFY_OFFSET(err_info, 0x0C);
8906 VERIFY_OFFSET(reserved3, 0x10);
8907 VERIFY_OFFSET(err_info_len, 0x12);
8908 VERIFY_OFFSET(reserved4, 0x13);
8909 VERIFY_OFFSET(sgl_offset, 0x14);
8910 VERIFY_OFFSET(reserved5, 0x15);
8911 VERIFY_OFFSET(transfer_len, 0x1C);
8912 VERIFY_OFFSET(reserved6, 0x20);
8913 VERIFY_OFFSET(io_flags, 0x24);
8914 VERIFY_OFFSET(reserved7, 0x26);
8915 VERIFY_OFFSET(LUN, 0x34);
8916 VERIFY_OFFSET(control, 0x3C);
8917 VERIFY_OFFSET(CDB, 0x40);
8918 VERIFY_OFFSET(reserved8, 0x50);
8919 VERIFY_OFFSET(host_context_flags, 0x60);
8920 VERIFY_OFFSET(timeout_sec, 0x62);
8921 VERIFY_OFFSET(ReplyQueue, 0x64);
8922 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 8923 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 8924 VERIFY_OFFSET(host_addr, 0x70);
8925 VERIFY_OFFSET(CISS_LUN, 0x78);
8926 VERIFY_OFFSET(SG, 0x78 + 8);
8927#undef VERIFY_OFFSET
8928}
8929
edd16368
SC		 8930module_init(hpsa_init);
8931module_exit(hpsa_cleanup);
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