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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
94c7bc31 | 3 | * Copyright 2016 Microsemi Corporation |
1358f6dc DB |
4 | * Copyright 2014-2015 PMC-Sierra, Inc. |
5 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
14 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
15 | * | |
94c7bc31 | 16 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
edd16368 SC |
17 | * |
18 | */ | |
19 | ||
20 | #include <linux/module.h> | |
21 | #include <linux/interrupt.h> | |
22 | #include <linux/types.h> | |
23 | #include <linux/pci.h> | |
e5a44df8 | 24 | #include <linux/pci-aspm.h> |
edd16368 SC |
25 | #include <linux/kernel.h> |
26 | #include <linux/slab.h> | |
27 | #include <linux/delay.h> | |
28 | #include <linux/fs.h> | |
29 | #include <linux/timer.h> | |
edd16368 SC |
30 | #include <linux/init.h> |
31 | #include <linux/spinlock.h> | |
edd16368 SC |
32 | #include <linux/compat.h> |
33 | #include <linux/blktrace_api.h> | |
34 | #include <linux/uaccess.h> | |
35 | #include <linux/io.h> | |
36 | #include <linux/dma-mapping.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/moduleparam.h> | |
39 | #include <scsi/scsi.h> | |
40 | #include <scsi/scsi_cmnd.h> | |
41 | #include <scsi/scsi_device.h> | |
42 | #include <scsi/scsi_host.h> | |
667e23d4 | 43 | #include <scsi/scsi_tcq.h> |
9437ac43 | 44 | #include <scsi/scsi_eh.h> |
d04e62b9 | 45 | #include <scsi/scsi_transport_sas.h> |
73153fe5 | 46 | #include <scsi/scsi_dbg.h> |
edd16368 SC |
47 | #include <linux/cciss_ioctl.h> |
48 | #include <linux/string.h> | |
49 | #include <linux/bitmap.h> | |
60063497 | 50 | #include <linux/atomic.h> |
a0c12413 | 51 | #include <linux/jiffies.h> |
42a91641 | 52 | #include <linux/percpu-defs.h> |
094963da | 53 | #include <linux/percpu.h> |
2b08b3e9 | 54 | #include <asm/unaligned.h> |
283b4a9b | 55 | #include <asm/div64.h> |
edd16368 SC |
56 | #include "hpsa_cmd.h" |
57 | #include "hpsa.h" | |
58 | ||
ec2c3aa9 DB |
59 | /* |
60 | * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' | |
61 | * with an optional trailing '-' followed by a byte value (0-255). | |
62 | */ | |
9a14f9b1 | 63 | #define HPSA_DRIVER_VERSION "3.4.20-170" |
edd16368 | 64 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 65 | #define HPSA "hpsa" |
edd16368 | 66 | |
007e7aa9 RE |
67 | /* How long to wait for CISS doorbell communication */ |
68 | #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */ | |
69 | #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */ | |
70 | #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */ | |
71 | #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */ | |
edd16368 SC |
72 | #define MAX_IOCTL_CONFIG_WAIT 1000 |
73 | ||
74 | /*define how many times we will try a command because of bus resets */ | |
75 | #define MAX_CMD_RETRIES 3 | |
b443d3ea DB |
76 | /* How long to wait before giving up on a command */ |
77 | #define HPSA_EH_PTRAID_TIMEOUT (240 * HZ) | |
edd16368 SC |
78 | |
79 | /* Embedded module documentation macros - see modules.h */ | |
80 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
81 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
82 | HPSA_DRIVER_VERSION); | |
83 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
84 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
85 | MODULE_LICENSE("GPL"); | |
253d2464 | 86 | MODULE_ALIAS("cciss"); |
edd16368 | 87 | |
02ec19c8 SC |
88 | static int hpsa_simple_mode; |
89 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
90 | MODULE_PARM_DESC(hpsa_simple_mode, | |
91 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
92 | |
93 | /* define the PCI info for the cards we can control */ | |
94 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
95 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
7f1974a7 | 110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920}, |
fe0c9610 MM |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
7f1974a7 | 115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925}, |
fe0c9610 MM |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
121 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
122 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
123 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
124 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
125 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
126 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
127 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
3b7a45e5 | 128 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, |
97b9f53d MM |
129 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, |
130 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
131 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
3b7a45e5 JH |
132 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, |
133 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, | |
134 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, | |
135 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, | |
136 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, | |
fdfa4b6d | 137 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580}, |
cbb47dcb DB |
138 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581}, |
139 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582}, | |
140 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583}, | |
141 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584}, | |
142 | {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585}, | |
8e616a5e SC |
143 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, |
144 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, | |
145 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, | |
146 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, | |
147 | {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, | |
7c03b870 | 148 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 149 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
135ae6ed HR |
150 | {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
151 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, | |
edd16368 SC |
152 | {0,} |
153 | }; | |
154 | ||
155 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
156 | ||
157 | /* board_id = Subsystem Device ID & Vendor ID | |
158 | * product = Marketing Name for the board | |
159 | * access = Address of the struct of function pointers | |
160 | */ | |
161 | static struct board_type products[] = { | |
135ae6ed HR |
162 | {0x40700E11, "Smart Array 5300", &SA5A_access}, |
163 | {0x40800E11, "Smart Array 5i", &SA5B_access}, | |
164 | {0x40820E11, "Smart Array 532", &SA5B_access}, | |
165 | {0x40830E11, "Smart Array 5312", &SA5B_access}, | |
166 | {0x409A0E11, "Smart Array 641", &SA5A_access}, | |
167 | {0x409B0E11, "Smart Array 642", &SA5A_access}, | |
168 | {0x409C0E11, "Smart Array 6400", &SA5A_access}, | |
169 | {0x409D0E11, "Smart Array 6400 EM", &SA5A_access}, | |
170 | {0x40910E11, "Smart Array 6i", &SA5A_access}, | |
171 | {0x3225103C, "Smart Array P600", &SA5A_access}, | |
172 | {0x3223103C, "Smart Array P800", &SA5A_access}, | |
173 | {0x3234103C, "Smart Array P400", &SA5A_access}, | |
174 | {0x3235103C, "Smart Array P400i", &SA5A_access}, | |
175 | {0x3211103C, "Smart Array E200i", &SA5A_access}, | |
176 | {0x3212103C, "Smart Array E200", &SA5A_access}, | |
177 | {0x3213103C, "Smart Array E200i", &SA5A_access}, | |
178 | {0x3214103C, "Smart Array E200i", &SA5A_access}, | |
179 | {0x3215103C, "Smart Array E200i", &SA5A_access}, | |
180 | {0x3237103C, "Smart Array E500", &SA5A_access}, | |
181 | {0x323D103C, "Smart Array P700m", &SA5A_access}, | |
edd16368 SC |
182 | {0x3241103C, "Smart Array P212", &SA5_access}, |
183 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
184 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
185 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
186 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
187 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
188 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
7d2cce58 | 189 | {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ |
fe0c9610 MM |
190 | {0x3350103C, "Smart Array P222", &SA5_access}, |
191 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
192 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
193 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
194 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
195 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
196 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
7f1974a7 | 197 | {0x1920103C, "Smart Array P430i", &SA5_access}, |
1fd6c8e3 MM |
198 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
199 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
200 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
201 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
7f1974a7 | 202 | {0x1925103C, "Smart Array P831", &SA5_access}, |
1fd6c8e3 MM |
203 | {0x1926103C, "Smart Array P731m", &SA5_access}, |
204 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
205 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
27fb8137 DB |
206 | {0x21BD103C, "Smart Array P244br", &SA5_access}, |
207 | {0x21BE103C, "Smart Array P741m", &SA5_access}, | |
208 | {0x21BF103C, "Smart HBA H240ar", &SA5_access}, | |
209 | {0x21C0103C, "Smart Array P440ar", &SA5_access}, | |
c8ae0ab1 | 210 | {0x21C1103C, "Smart Array P840ar", &SA5_access}, |
27fb8137 DB |
211 | {0x21C2103C, "Smart Array P440", &SA5_access}, |
212 | {0x21C3103C, "Smart Array P441", &SA5_access}, | |
97b9f53d | 213 | {0x21C4103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
214 | {0x21C5103C, "Smart Array P841", &SA5_access}, |
215 | {0x21C6103C, "Smart HBA H244br", &SA5_access}, | |
216 | {0x21C7103C, "Smart HBA H240", &SA5_access}, | |
217 | {0x21C8103C, "Smart HBA H241", &SA5_access}, | |
97b9f53d | 218 | {0x21C9103C, "Smart Array", &SA5_access}, |
27fb8137 DB |
219 | {0x21CA103C, "Smart Array P246br", &SA5_access}, |
220 | {0x21CB103C, "Smart Array P840", &SA5_access}, | |
3b7a45e5 JH |
221 | {0x21CC103C, "Smart Array", &SA5_access}, |
222 | {0x21CD103C, "Smart Array", &SA5_access}, | |
27fb8137 | 223 | {0x21CE103C, "Smart HBA", &SA5_access}, |
fdfa4b6d | 224 | {0x05809005, "SmartHBA-SA", &SA5_access}, |
cbb47dcb DB |
225 | {0x05819005, "SmartHBA-SA 8i", &SA5_access}, |
226 | {0x05829005, "SmartHBA-SA 8i8e", &SA5_access}, | |
227 | {0x05839005, "SmartHBA-SA 8e", &SA5_access}, | |
228 | {0x05849005, "SmartHBA-SA 16i", &SA5_access}, | |
229 | {0x05859005, "SmartHBA-SA 4i4e", &SA5_access}, | |
8e616a5e SC |
230 | {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, |
231 | {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, | |
232 | {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, | |
233 | {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, | |
234 | {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, | |
edd16368 SC |
235 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
236 | }; | |
237 | ||
d04e62b9 KB |
238 | static struct scsi_transport_template *hpsa_sas_transport_template; |
239 | static int hpsa_add_sas_host(struct ctlr_info *h); | |
240 | static void hpsa_delete_sas_host(struct ctlr_info *h); | |
241 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
242 | struct hpsa_scsi_dev_t *device); | |
243 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device); | |
244 | static struct hpsa_scsi_dev_t | |
245 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
246 | struct sas_rphy *rphy); | |
247 | ||
a58e7e53 WS |
248 | #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy) |
249 | static const struct scsi_cmnd hpsa_cmd_busy; | |
250 | #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle) | |
251 | static const struct scsi_cmnd hpsa_cmd_idle; | |
edd16368 SC |
252 | static int number_of_controllers; |
253 | ||
10f66018 SC |
254 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
255 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
6f4e626f NC |
256 | static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd, |
257 | void __user *arg); | |
edd16368 SC |
258 | |
259 | #ifdef CONFIG_COMPAT | |
6f4e626f | 260 | static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd, |
42a91641 | 261 | void __user *arg); |
edd16368 SC |
262 | #endif |
263 | ||
264 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
edd16368 | 265 | static struct CommandList *cmd_alloc(struct ctlr_info *h); |
73153fe5 WS |
266 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c); |
267 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
268 | struct scsi_cmnd *scmd); | |
a2dac136 | 269 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 270 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 | 271 | int cmd_type); |
2c143342 | 272 | static void hpsa_free_cmd_pool(struct ctlr_info *h); |
b7bb24eb | 273 | #define VPD_PAGE (1 << 8) |
b48d9804 | 274 | #define HPSA_SIMPLE_ERROR_BITS 0x03 |
edd16368 | 275 | |
f281233d | 276 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
277 | static void hpsa_scan_start(struct Scsi_Host *); |
278 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
279 | unsigned long elapsed_time); | |
7c0a0229 | 280 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); |
edd16368 SC |
281 | |
282 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
283 | static int hpsa_slave_alloc(struct scsi_device *sdev); | |
41ce4c35 | 284 | static int hpsa_slave_configure(struct scsi_device *sdev); |
edd16368 SC |
285 | static void hpsa_slave_destroy(struct scsi_device *sdev); |
286 | ||
8aa60681 | 287 | static void hpsa_update_scsi_devices(struct ctlr_info *h); |
edd16368 SC |
288 | static int check_for_unit_attention(struct ctlr_info *h, |
289 | struct CommandList *c); | |
290 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
291 | struct CommandList *c); | |
303932fd DB |
292 | /* performant mode helper functions */ |
293 | static void calc_bucket_map(int *bucket, int num_buckets, | |
2b08b3e9 | 294 | int nsgs, int min_blocks, u32 *bucket_map); |
105a3dbc RE |
295 | static void hpsa_free_performant_mode(struct ctlr_info *h); |
296 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); | |
254f796b | 297 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
298 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
299 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
300 | u64 *cfg_offset); | |
301 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
302 | unsigned long *memory_bar); | |
135ae6ed HR |
303 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, |
304 | bool *legacy_board); | |
bfd7546c DB |
305 | static int wait_for_device_to_become_ready(struct ctlr_info *h, |
306 | unsigned char lunaddr[], | |
307 | int reply_queue); | |
6f039790 GKH |
308 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
309 | int wait_for_ready); | |
75167d2c | 310 | static inline void finish_cmd(struct CommandList *c); |
c706a795 | 311 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h); |
fe5389c8 SC |
312 | #define BOARD_NOT_READY 0 |
313 | #define BOARD_READY 1 | |
23100dd9 | 314 | static void hpsa_drain_accel_commands(struct ctlr_info *h); |
76438d08 | 315 | static void hpsa_flush_cache(struct ctlr_info *h); |
c349775e ST |
316 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, |
317 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 318 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); |
080ef1cc | 319 | static void hpsa_command_resubmit_worker(struct work_struct *work); |
25163bd5 WS |
320 | static u32 lockup_detected(struct ctlr_info *h); |
321 | static int detect_controller_lockup(struct ctlr_info *h); | |
c2adae44 | 322 | static void hpsa_disable_rld_caching(struct ctlr_info *h); |
d04e62b9 KB |
323 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, |
324 | struct ReportExtendedLUNdata *buf, int bufsize); | |
8383278d ST |
325 | static bool hpsa_vpd_page_supported(struct ctlr_info *h, |
326 | unsigned char scsi3addr[], u8 page); | |
34592254 | 327 | static int hpsa_luns_changed(struct ctlr_info *h); |
ba74fdc4 DB |
328 | static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, |
329 | struct hpsa_scsi_dev_t *dev, | |
330 | unsigned char *scsi3addr); | |
edd16368 | 331 | |
edd16368 SC |
332 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
333 | { | |
334 | unsigned long *priv = shost_priv(sdev->host); | |
335 | return (struct ctlr_info *) *priv; | |
336 | } | |
337 | ||
a23513e8 SC |
338 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
339 | { | |
340 | unsigned long *priv = shost_priv(sh); | |
341 | return (struct ctlr_info *) *priv; | |
342 | } | |
343 | ||
a58e7e53 WS |
344 | static inline bool hpsa_is_cmd_idle(struct CommandList *c) |
345 | { | |
346 | return c->scsi_cmd == SCSI_CMD_IDLE; | |
347 | } | |
348 | ||
9437ac43 SC |
349 | /* extract sense key, asc, and ascq from sense data. -1 means invalid. */ |
350 | static void decode_sense_data(const u8 *sense_data, int sense_data_len, | |
351 | u8 *sense_key, u8 *asc, u8 *ascq) | |
352 | { | |
353 | struct scsi_sense_hdr sshdr; | |
354 | bool rc; | |
355 | ||
356 | *sense_key = -1; | |
357 | *asc = -1; | |
358 | *ascq = -1; | |
359 | ||
360 | if (sense_data_len < 1) | |
361 | return; | |
362 | ||
363 | rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr); | |
364 | if (rc) { | |
365 | *sense_key = sshdr.sense_key; | |
366 | *asc = sshdr.asc; | |
367 | *ascq = sshdr.ascq; | |
368 | } | |
369 | } | |
370 | ||
edd16368 SC |
371 | static int check_for_unit_attention(struct ctlr_info *h, |
372 | struct CommandList *c) | |
373 | { | |
9437ac43 SC |
374 | u8 sense_key, asc, ascq; |
375 | int sense_len; | |
376 | ||
377 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) | |
378 | sense_len = sizeof(c->err_info->SenseInfo); | |
379 | else | |
380 | sense_len = c->err_info->SenseLen; | |
381 | ||
382 | decode_sense_data(c->err_info->SenseInfo, sense_len, | |
383 | &sense_key, &asc, &ascq); | |
81c27557 | 384 | if (sense_key != UNIT_ATTENTION || asc == 0xff) |
edd16368 SC |
385 | return 0; |
386 | ||
9437ac43 | 387 | switch (asc) { |
edd16368 | 388 | case STATE_CHANGED: |
9437ac43 | 389 | dev_warn(&h->pdev->dev, |
2946e82b RE |
390 | "%s: a state change detected, command retried\n", |
391 | h->devname); | |
edd16368 SC |
392 | break; |
393 | case LUN_FAILED: | |
7f73695a | 394 | dev_warn(&h->pdev->dev, |
2946e82b | 395 | "%s: LUN failure detected\n", h->devname); |
edd16368 SC |
396 | break; |
397 | case REPORT_LUNS_CHANGED: | |
7f73695a | 398 | dev_warn(&h->pdev->dev, |
2946e82b | 399 | "%s: report LUN data changed\n", h->devname); |
edd16368 | 400 | /* |
4f4eb9f1 ST |
401 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
402 | * target (array) devices. | |
edd16368 SC |
403 | */ |
404 | break; | |
405 | case POWER_OR_RESET: | |
2946e82b RE |
406 | dev_warn(&h->pdev->dev, |
407 | "%s: a power on or device reset detected\n", | |
408 | h->devname); | |
edd16368 SC |
409 | break; |
410 | case UNIT_ATTENTION_CLEARED: | |
2946e82b RE |
411 | dev_warn(&h->pdev->dev, |
412 | "%s: unit attention cleared by another initiator\n", | |
413 | h->devname); | |
edd16368 SC |
414 | break; |
415 | default: | |
2946e82b RE |
416 | dev_warn(&h->pdev->dev, |
417 | "%s: unknown unit attention detected\n", | |
418 | h->devname); | |
edd16368 SC |
419 | break; |
420 | } | |
421 | return 1; | |
422 | } | |
423 | ||
852af20a MB |
424 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
425 | { | |
426 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
427 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
428 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
429 | return 0; | |
430 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
431 | return 1; | |
432 | } | |
433 | ||
e985c58f SC |
434 | static u32 lockup_detected(struct ctlr_info *h); |
435 | static ssize_t host_show_lockup_detected(struct device *dev, | |
436 | struct device_attribute *attr, char *buf) | |
437 | { | |
438 | int ld; | |
439 | struct ctlr_info *h; | |
440 | struct Scsi_Host *shost = class_to_shost(dev); | |
441 | ||
442 | h = shost_to_hba(shost); | |
443 | ld = lockup_detected(h); | |
444 | ||
445 | return sprintf(buf, "ld=%d\n", ld); | |
446 | } | |
447 | ||
da0697bd ST |
448 | static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, |
449 | struct device_attribute *attr, | |
450 | const char *buf, size_t count) | |
451 | { | |
452 | int status, len; | |
453 | struct ctlr_info *h; | |
454 | struct Scsi_Host *shost = class_to_shost(dev); | |
455 | char tmpbuf[10]; | |
456 | ||
457 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
458 | return -EACCES; | |
459 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
460 | strncpy(tmpbuf, buf, len); | |
461 | tmpbuf[len] = '\0'; | |
462 | if (sscanf(tmpbuf, "%d", &status) != 1) | |
463 | return -EINVAL; | |
464 | h = shost_to_hba(shost); | |
465 | h->acciopath_status = !!status; | |
466 | dev_warn(&h->pdev->dev, | |
467 | "hpsa: HP SSD Smart Path %s via sysfs update.\n", | |
468 | h->acciopath_status ? "enabled" : "disabled"); | |
469 | return count; | |
470 | } | |
471 | ||
2ba8bfc8 SC |
472 | static ssize_t host_store_raid_offload_debug(struct device *dev, |
473 | struct device_attribute *attr, | |
474 | const char *buf, size_t count) | |
475 | { | |
476 | int debug_level, len; | |
477 | struct ctlr_info *h; | |
478 | struct Scsi_Host *shost = class_to_shost(dev); | |
479 | char tmpbuf[10]; | |
480 | ||
481 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
482 | return -EACCES; | |
483 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
484 | strncpy(tmpbuf, buf, len); | |
485 | tmpbuf[len] = '\0'; | |
486 | if (sscanf(tmpbuf, "%d", &debug_level) != 1) | |
487 | return -EINVAL; | |
488 | if (debug_level < 0) | |
489 | debug_level = 0; | |
490 | h = shost_to_hba(shost); | |
491 | h->raid_offload_debug = debug_level; | |
492 | dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", | |
493 | h->raid_offload_debug); | |
494 | return count; | |
495 | } | |
496 | ||
edd16368 SC |
497 | static ssize_t host_store_rescan(struct device *dev, |
498 | struct device_attribute *attr, | |
499 | const char *buf, size_t count) | |
500 | { | |
501 | struct ctlr_info *h; | |
502 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 503 | h = shost_to_hba(shost); |
31468401 | 504 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
505 | return count; |
506 | } | |
507 | ||
d28ce020 SC |
508 | static ssize_t host_show_firmware_revision(struct device *dev, |
509 | struct device_attribute *attr, char *buf) | |
510 | { | |
511 | struct ctlr_info *h; | |
512 | struct Scsi_Host *shost = class_to_shost(dev); | |
513 | unsigned char *fwrev; | |
514 | ||
515 | h = shost_to_hba(shost); | |
516 | if (!h->hba_inquiry_data) | |
517 | return 0; | |
518 | fwrev = &h->hba_inquiry_data[32]; | |
519 | return snprintf(buf, 20, "%c%c%c%c\n", | |
520 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
521 | } | |
522 | ||
94a13649 SC |
523 | static ssize_t host_show_commands_outstanding(struct device *dev, |
524 | struct device_attribute *attr, char *buf) | |
525 | { | |
526 | struct Scsi_Host *shost = class_to_shost(dev); | |
527 | struct ctlr_info *h = shost_to_hba(shost); | |
528 | ||
0cbf768e SC |
529 | return snprintf(buf, 20, "%d\n", |
530 | atomic_read(&h->commands_outstanding)); | |
94a13649 SC |
531 | } |
532 | ||
745a7a25 SC |
533 | static ssize_t host_show_transport_mode(struct device *dev, |
534 | struct device_attribute *attr, char *buf) | |
535 | { | |
536 | struct ctlr_info *h; | |
537 | struct Scsi_Host *shost = class_to_shost(dev); | |
538 | ||
539 | h = shost_to_hba(shost); | |
540 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 541 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
542 | "performant" : "simple"); |
543 | } | |
544 | ||
da0697bd ST |
545 | static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, |
546 | struct device_attribute *attr, char *buf) | |
547 | { | |
548 | struct ctlr_info *h; | |
549 | struct Scsi_Host *shost = class_to_shost(dev); | |
550 | ||
551 | h = shost_to_hba(shost); | |
552 | return snprintf(buf, 30, "HP SSD Smart Path %s\n", | |
553 | (h->acciopath_status == 1) ? "enabled" : "disabled"); | |
554 | } | |
555 | ||
46380786 | 556 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
557 | static u32 unresettable_controller[] = { |
558 | 0x324a103C, /* Smart Array P712m */ | |
9b5c48c2 | 559 | 0x324b103C, /* Smart Array P711m */ |
941b1cda SC |
560 | 0x3223103C, /* Smart Array P800 */ |
561 | 0x3234103C, /* Smart Array P400 */ | |
562 | 0x3235103C, /* Smart Array P400i */ | |
563 | 0x3211103C, /* Smart Array E200i */ | |
564 | 0x3212103C, /* Smart Array E200 */ | |
565 | 0x3213103C, /* Smart Array E200i */ | |
566 | 0x3214103C, /* Smart Array E200i */ | |
567 | 0x3215103C, /* Smart Array E200i */ | |
568 | 0x3237103C, /* Smart Array E500 */ | |
569 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 570 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
571 | 0x409C0E11, /* Smart Array 6400 */ |
572 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
573 | 0x40700E11, /* Smart Array 5300 */ |
574 | 0x40820E11, /* Smart Array 532 */ | |
575 | 0x40830E11, /* Smart Array 5312 */ | |
576 | 0x409A0E11, /* Smart Array 641 */ | |
577 | 0x409B0E11, /* Smart Array 642 */ | |
578 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
579 | }; |
580 | ||
46380786 SC |
581 | /* List of controllers which cannot even be soft reset */ |
582 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 583 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
584 | 0x40700E11, /* Smart Array 5300 */ |
585 | 0x40820E11, /* Smart Array 532 */ | |
586 | 0x40830E11, /* Smart Array 5312 */ | |
587 | 0x409A0E11, /* Smart Array 641 */ | |
588 | 0x409B0E11, /* Smart Array 642 */ | |
589 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
590 | /* Exclude 640x boards. These are two pci devices in one slot |
591 | * which share a battery backed cache module. One controls the | |
592 | * cache, the other accesses the cache through the one that controls | |
593 | * it. If we reset the one controlling the cache, the other will | |
594 | * likely not be happy. Just forbid resetting this conjoined mess. | |
595 | * The 640x isn't really supported by hpsa anyway. | |
596 | */ | |
597 | 0x409C0E11, /* Smart Array 6400 */ | |
598 | 0x409D0E11, /* Smart Array 6400 EM */ | |
599 | }; | |
600 | ||
9b5c48c2 | 601 | static int board_id_in_array(u32 a[], int nelems, u32 board_id) |
941b1cda SC |
602 | { |
603 | int i; | |
604 | ||
9b5c48c2 SC |
605 | for (i = 0; i < nelems; i++) |
606 | if (a[i] == board_id) | |
607 | return 1; | |
608 | return 0; | |
46380786 SC |
609 | } |
610 | ||
9b5c48c2 | 611 | static int ctlr_is_hard_resettable(u32 board_id) |
46380786 | 612 | { |
9b5c48c2 SC |
613 | return !board_id_in_array(unresettable_controller, |
614 | ARRAY_SIZE(unresettable_controller), board_id); | |
615 | } | |
46380786 | 616 | |
9b5c48c2 SC |
617 | static int ctlr_is_soft_resettable(u32 board_id) |
618 | { | |
619 | return !board_id_in_array(soft_unresettable_controller, | |
620 | ARRAY_SIZE(soft_unresettable_controller), board_id); | |
941b1cda SC |
621 | } |
622 | ||
46380786 SC |
623 | static int ctlr_is_resettable(u32 board_id) |
624 | { | |
625 | return ctlr_is_hard_resettable(board_id) || | |
626 | ctlr_is_soft_resettable(board_id); | |
627 | } | |
628 | ||
941b1cda SC |
629 | static ssize_t host_show_resettable(struct device *dev, |
630 | struct device_attribute *attr, char *buf) | |
631 | { | |
632 | struct ctlr_info *h; | |
633 | struct Scsi_Host *shost = class_to_shost(dev); | |
634 | ||
635 | h = shost_to_hba(shost); | |
46380786 | 636 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
637 | } |
638 | ||
edd16368 SC |
639 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
640 | { | |
641 | return (scsi3addr[3] & 0xC0) == 0x40; | |
642 | } | |
643 | ||
f2ef0ce7 | 644 | static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", |
7c59a0d4 | 645 | "1(+0)ADM", "UNKNOWN", "PHYS DRV" |
edd16368 | 646 | }; |
6b80b18f ST |
647 | #define HPSA_RAID_0 0 |
648 | #define HPSA_RAID_4 1 | |
649 | #define HPSA_RAID_1 2 /* also used for RAID 10 */ | |
650 | #define HPSA_RAID_5 3 /* also used for RAID 50 */ | |
651 | #define HPSA_RAID_51 4 | |
652 | #define HPSA_RAID_6 5 /* also used for RAID 60 */ | |
653 | #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ | |
7c59a0d4 DB |
654 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2) |
655 | #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1) | |
edd16368 | 656 | |
f3f01730 KB |
657 | static inline bool is_logical_device(struct hpsa_scsi_dev_t *device) |
658 | { | |
659 | return !device->physical_device; | |
660 | } | |
edd16368 SC |
661 | |
662 | static ssize_t raid_level_show(struct device *dev, | |
663 | struct device_attribute *attr, char *buf) | |
664 | { | |
665 | ssize_t l = 0; | |
82a72c0a | 666 | unsigned char rlevel; |
edd16368 SC |
667 | struct ctlr_info *h; |
668 | struct scsi_device *sdev; | |
669 | struct hpsa_scsi_dev_t *hdev; | |
670 | unsigned long flags; | |
671 | ||
672 | sdev = to_scsi_device(dev); | |
673 | h = sdev_to_hba(sdev); | |
674 | spin_lock_irqsave(&h->lock, flags); | |
675 | hdev = sdev->hostdata; | |
676 | if (!hdev) { | |
677 | spin_unlock_irqrestore(&h->lock, flags); | |
678 | return -ENODEV; | |
679 | } | |
680 | ||
681 | /* Is this even a logical drive? */ | |
f3f01730 | 682 | if (!is_logical_device(hdev)) { |
edd16368 SC |
683 | spin_unlock_irqrestore(&h->lock, flags); |
684 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
685 | return l; | |
686 | } | |
687 | ||
688 | rlevel = hdev->raid_level; | |
689 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 690 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
691 | rlevel = RAID_UNKNOWN; |
692 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
693 | return l; | |
694 | } | |
695 | ||
696 | static ssize_t lunid_show(struct device *dev, | |
697 | struct device_attribute *attr, char *buf) | |
698 | { | |
699 | struct ctlr_info *h; | |
700 | struct scsi_device *sdev; | |
701 | struct hpsa_scsi_dev_t *hdev; | |
702 | unsigned long flags; | |
703 | unsigned char lunid[8]; | |
704 | ||
705 | sdev = to_scsi_device(dev); | |
706 | h = sdev_to_hba(sdev); | |
707 | spin_lock_irqsave(&h->lock, flags); | |
708 | hdev = sdev->hostdata; | |
709 | if (!hdev) { | |
710 | spin_unlock_irqrestore(&h->lock, flags); | |
711 | return -ENODEV; | |
712 | } | |
713 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
714 | spin_unlock_irqrestore(&h->lock, flags); | |
609a70df | 715 | return snprintf(buf, 20, "0x%8phN\n", lunid); |
edd16368 SC |
716 | } |
717 | ||
718 | static ssize_t unique_id_show(struct device *dev, | |
719 | struct device_attribute *attr, char *buf) | |
720 | { | |
721 | struct ctlr_info *h; | |
722 | struct scsi_device *sdev; | |
723 | struct hpsa_scsi_dev_t *hdev; | |
724 | unsigned long flags; | |
725 | unsigned char sn[16]; | |
726 | ||
727 | sdev = to_scsi_device(dev); | |
728 | h = sdev_to_hba(sdev); | |
729 | spin_lock_irqsave(&h->lock, flags); | |
730 | hdev = sdev->hostdata; | |
731 | if (!hdev) { | |
732 | spin_unlock_irqrestore(&h->lock, flags); | |
733 | return -ENODEV; | |
734 | } | |
735 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
736 | spin_unlock_irqrestore(&h->lock, flags); | |
737 | return snprintf(buf, 16 * 2 + 2, | |
738 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
739 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
740 | sn[0], sn[1], sn[2], sn[3], | |
741 | sn[4], sn[5], sn[6], sn[7], | |
742 | sn[8], sn[9], sn[10], sn[11], | |
743 | sn[12], sn[13], sn[14], sn[15]); | |
744 | } | |
745 | ||
ded1be4a JH |
746 | static ssize_t sas_address_show(struct device *dev, |
747 | struct device_attribute *attr, char *buf) | |
748 | { | |
749 | struct ctlr_info *h; | |
750 | struct scsi_device *sdev; | |
751 | struct hpsa_scsi_dev_t *hdev; | |
752 | unsigned long flags; | |
753 | u64 sas_address; | |
754 | ||
755 | sdev = to_scsi_device(dev); | |
756 | h = sdev_to_hba(sdev); | |
757 | spin_lock_irqsave(&h->lock, flags); | |
758 | hdev = sdev->hostdata; | |
759 | if (!hdev || is_logical_device(hdev) || !hdev->expose_device) { | |
760 | spin_unlock_irqrestore(&h->lock, flags); | |
761 | return -ENODEV; | |
762 | } | |
763 | sas_address = hdev->sas_address; | |
764 | spin_unlock_irqrestore(&h->lock, flags); | |
765 | ||
766 | return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address); | |
767 | } | |
768 | ||
c1988684 ST |
769 | static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, |
770 | struct device_attribute *attr, char *buf) | |
771 | { | |
772 | struct ctlr_info *h; | |
773 | struct scsi_device *sdev; | |
774 | struct hpsa_scsi_dev_t *hdev; | |
775 | unsigned long flags; | |
776 | int offload_enabled; | |
777 | ||
778 | sdev = to_scsi_device(dev); | |
779 | h = sdev_to_hba(sdev); | |
780 | spin_lock_irqsave(&h->lock, flags); | |
781 | hdev = sdev->hostdata; | |
782 | if (!hdev) { | |
783 | spin_unlock_irqrestore(&h->lock, flags); | |
784 | return -ENODEV; | |
785 | } | |
786 | offload_enabled = hdev->offload_enabled; | |
787 | spin_unlock_irqrestore(&h->lock, flags); | |
b2582a65 DB |
788 | |
789 | if (hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) | |
790 | return snprintf(buf, 20, "%d\n", offload_enabled); | |
791 | else | |
792 | return snprintf(buf, 40, "%s\n", | |
793 | "Not applicable for a controller"); | |
c1988684 ST |
794 | } |
795 | ||
8270b862 | 796 | #define MAX_PATHS 8 |
8270b862 JH |
797 | static ssize_t path_info_show(struct device *dev, |
798 | struct device_attribute *attr, char *buf) | |
799 | { | |
800 | struct ctlr_info *h; | |
801 | struct scsi_device *sdev; | |
802 | struct hpsa_scsi_dev_t *hdev; | |
803 | unsigned long flags; | |
804 | int i; | |
805 | int output_len = 0; | |
806 | u8 box; | |
807 | u8 bay; | |
808 | u8 path_map_index = 0; | |
809 | char *active; | |
810 | unsigned char phys_connector[2]; | |
8270b862 | 811 | |
8270b862 JH |
812 | sdev = to_scsi_device(dev); |
813 | h = sdev_to_hba(sdev); | |
814 | spin_lock_irqsave(&h->devlock, flags); | |
815 | hdev = sdev->hostdata; | |
816 | if (!hdev) { | |
817 | spin_unlock_irqrestore(&h->devlock, flags); | |
818 | return -ENODEV; | |
819 | } | |
820 | ||
821 | bay = hdev->bay; | |
822 | for (i = 0; i < MAX_PATHS; i++) { | |
823 | path_map_index = 1<<i; | |
824 | if (i == hdev->active_path_index) | |
825 | active = "Active"; | |
826 | else if (hdev->path_map & path_map_index) | |
827 | active = "Inactive"; | |
828 | else | |
829 | continue; | |
830 | ||
1faf072c RV |
831 | output_len += scnprintf(buf + output_len, |
832 | PAGE_SIZE - output_len, | |
833 | "[%d:%d:%d:%d] %20.20s ", | |
8270b862 JH |
834 | h->scsi_host->host_no, |
835 | hdev->bus, hdev->target, hdev->lun, | |
836 | scsi_device_type(hdev->devtype)); | |
837 | ||
cca8f13b | 838 | if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) { |
2708f295 | 839 | output_len += scnprintf(buf + output_len, |
1faf072c RV |
840 | PAGE_SIZE - output_len, |
841 | "%s\n", active); | |
8270b862 JH |
842 | continue; |
843 | } | |
844 | ||
845 | box = hdev->box[i]; | |
846 | memcpy(&phys_connector, &hdev->phys_connector[i], | |
847 | sizeof(phys_connector)); | |
848 | if (phys_connector[0] < '0') | |
849 | phys_connector[0] = '0'; | |
850 | if (phys_connector[1] < '0') | |
851 | phys_connector[1] = '0'; | |
cca8f13b | 852 | output_len += scnprintf(buf + output_len, |
1faf072c | 853 | PAGE_SIZE - output_len, |
8270b862 JH |
854 | "PORT: %.2s ", |
855 | phys_connector); | |
af15ed36 DB |
856 | if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) && |
857 | hdev->expose_device) { | |
8270b862 | 858 | if (box == 0 || box == 0xFF) { |
2708f295 | 859 | output_len += scnprintf(buf + output_len, |
1faf072c | 860 | PAGE_SIZE - output_len, |
8270b862 JH |
861 | "BAY: %hhu %s\n", |
862 | bay, active); | |
863 | } else { | |
2708f295 | 864 | output_len += scnprintf(buf + output_len, |
1faf072c | 865 | PAGE_SIZE - output_len, |
8270b862 JH |
866 | "BOX: %hhu BAY: %hhu %s\n", |
867 | box, bay, active); | |
868 | } | |
869 | } else if (box != 0 && box != 0xFF) { | |
2708f295 | 870 | output_len += scnprintf(buf + output_len, |
1faf072c | 871 | PAGE_SIZE - output_len, "BOX: %hhu %s\n", |
8270b862 JH |
872 | box, active); |
873 | } else | |
2708f295 | 874 | output_len += scnprintf(buf + output_len, |
1faf072c | 875 | PAGE_SIZE - output_len, "%s\n", active); |
8270b862 JH |
876 | } |
877 | ||
878 | spin_unlock_irqrestore(&h->devlock, flags); | |
1faf072c | 879 | return output_len; |
8270b862 JH |
880 | } |
881 | ||
16961204 HR |
882 | static ssize_t host_show_ctlr_num(struct device *dev, |
883 | struct device_attribute *attr, char *buf) | |
884 | { | |
885 | struct ctlr_info *h; | |
886 | struct Scsi_Host *shost = class_to_shost(dev); | |
887 | ||
888 | h = shost_to_hba(shost); | |
889 | return snprintf(buf, 20, "%d\n", h->ctlr); | |
890 | } | |
891 | ||
135ae6ed HR |
892 | static ssize_t host_show_legacy_board(struct device *dev, |
893 | struct device_attribute *attr, char *buf) | |
894 | { | |
895 | struct ctlr_info *h; | |
896 | struct Scsi_Host *shost = class_to_shost(dev); | |
897 | ||
898 | h = shost_to_hba(shost); | |
899 | return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0); | |
900 | } | |
901 | ||
c828a892 JP |
902 | static DEVICE_ATTR_RO(raid_level); |
903 | static DEVICE_ATTR_RO(lunid); | |
904 | static DEVICE_ATTR_RO(unique_id); | |
3f5eac3a | 905 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); |
c828a892 | 906 | static DEVICE_ATTR_RO(sas_address); |
c1988684 ST |
907 | static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, |
908 | host_show_hp_ssd_smart_path_enabled, NULL); | |
c828a892 | 909 | static DEVICE_ATTR_RO(path_info); |
da0697bd ST |
910 | static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, |
911 | host_show_hp_ssd_smart_path_status, | |
912 | host_store_hp_ssd_smart_path_status); | |
2ba8bfc8 SC |
913 | static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, |
914 | host_store_raid_offload_debug); | |
3f5eac3a SC |
915 | static DEVICE_ATTR(firmware_revision, S_IRUGO, |
916 | host_show_firmware_revision, NULL); | |
917 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
918 | host_show_commands_outstanding, NULL); | |
919 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
920 | host_show_transport_mode, NULL); | |
941b1cda SC |
921 | static DEVICE_ATTR(resettable, S_IRUGO, |
922 | host_show_resettable, NULL); | |
e985c58f SC |
923 | static DEVICE_ATTR(lockup_detected, S_IRUGO, |
924 | host_show_lockup_detected, NULL); | |
16961204 HR |
925 | static DEVICE_ATTR(ctlr_num, S_IRUGO, |
926 | host_show_ctlr_num, NULL); | |
135ae6ed HR |
927 | static DEVICE_ATTR(legacy_board, S_IRUGO, |
928 | host_show_legacy_board, NULL); | |
3f5eac3a SC |
929 | |
930 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
931 | &dev_attr_raid_level, | |
932 | &dev_attr_lunid, | |
933 | &dev_attr_unique_id, | |
c1988684 | 934 | &dev_attr_hp_ssd_smart_path_enabled, |
8270b862 | 935 | &dev_attr_path_info, |
ded1be4a | 936 | &dev_attr_sas_address, |
3f5eac3a SC |
937 | NULL, |
938 | }; | |
939 | ||
940 | static struct device_attribute *hpsa_shost_attrs[] = { | |
941 | &dev_attr_rescan, | |
942 | &dev_attr_firmware_revision, | |
943 | &dev_attr_commands_outstanding, | |
944 | &dev_attr_transport_mode, | |
941b1cda | 945 | &dev_attr_resettable, |
da0697bd | 946 | &dev_attr_hp_ssd_smart_path_status, |
2ba8bfc8 | 947 | &dev_attr_raid_offload_debug, |
fb53c439 | 948 | &dev_attr_lockup_detected, |
16961204 | 949 | &dev_attr_ctlr_num, |
135ae6ed | 950 | &dev_attr_legacy_board, |
3f5eac3a SC |
951 | NULL, |
952 | }; | |
953 | ||
08ec46f6 DB |
954 | #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\ |
955 | HPSA_MAX_CONCURRENT_PASSTHRUS) | |
41ce4c35 | 956 | |
3f5eac3a SC |
957 | static struct scsi_host_template hpsa_driver_template = { |
958 | .module = THIS_MODULE, | |
f79cfec6 SC |
959 | .name = HPSA, |
960 | .proc_name = HPSA, | |
3f5eac3a SC |
961 | .queuecommand = hpsa_scsi_queue_command, |
962 | .scan_start = hpsa_scan_start, | |
963 | .scan_finished = hpsa_scan_finished, | |
7c0a0229 | 964 | .change_queue_depth = hpsa_change_queue_depth, |
3f5eac3a | 965 | .this_id = -1, |
3f5eac3a SC |
966 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
967 | .ioctl = hpsa_ioctl, | |
968 | .slave_alloc = hpsa_slave_alloc, | |
41ce4c35 | 969 | .slave_configure = hpsa_slave_configure, |
3f5eac3a SC |
970 | .slave_destroy = hpsa_slave_destroy, |
971 | #ifdef CONFIG_COMPAT | |
972 | .compat_ioctl = hpsa_compat_ioctl, | |
973 | #endif | |
974 | .sdev_attrs = hpsa_sdev_attrs, | |
975 | .shost_attrs = hpsa_shost_attrs, | |
eb53a3ea | 976 | .max_sectors = 2048, |
54b2b50c | 977 | .no_write_same = 1, |
3f5eac3a SC |
978 | }; |
979 | ||
254f796b | 980 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
981 | { |
982 | u32 a; | |
072b0518 | 983 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
3f5eac3a | 984 | |
e1f7de0c MG |
985 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
986 | return h->access.command_completed(h, q); | |
987 | ||
3f5eac3a | 988 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 989 | return h->access.command_completed(h, q); |
3f5eac3a | 990 | |
254f796b MG |
991 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
992 | a = rq->head[rq->current_entry]; | |
993 | rq->current_entry++; | |
0cbf768e | 994 | atomic_dec(&h->commands_outstanding); |
3f5eac3a SC |
995 | } else { |
996 | a = FIFO_EMPTY; | |
997 | } | |
998 | /* Check for wraparound */ | |
254f796b MG |
999 | if (rq->current_entry == h->max_commands) { |
1000 | rq->current_entry = 0; | |
1001 | rq->wraparound ^= 1; | |
3f5eac3a SC |
1002 | } |
1003 | return a; | |
1004 | } | |
1005 | ||
c349775e ST |
1006 | /* |
1007 | * There are some special bits in the bus address of the | |
1008 | * command that we have to set for the controller to know | |
1009 | * how to process the command: | |
1010 | * | |
1011 | * Normal performant mode: | |
1012 | * bit 0: 1 means performant mode, 0 means simple mode. | |
1013 | * bits 1-3 = block fetch table entry | |
1014 | * bits 4-6 = command type (== 0) | |
1015 | * | |
1016 | * ioaccel1 mode: | |
1017 | * bit 0 = "performant mode" bit. | |
1018 | * bits 1-3 = block fetch table entry | |
1019 | * bits 4-6 = command type (== 110) | |
1020 | * (command type is needed because ioaccel1 mode | |
1021 | * commands are submitted through the same register as normal | |
1022 | * mode commands, so this is how the controller knows whether | |
1023 | * the command is normal mode or ioaccel1 mode.) | |
1024 | * | |
1025 | * ioaccel2 mode: | |
1026 | * bit 0 = "performant mode" bit. | |
1027 | * bits 1-4 = block fetch table entry (note extra bit) | |
1028 | * bits 4-6 = not needed, because ioaccel2 mode has | |
1029 | * a separate special register for submitting commands. | |
1030 | */ | |
1031 | ||
25163bd5 WS |
1032 | /* |
1033 | * set_performant_mode: Modify the tag for cciss performant | |
3f5eac3a SC |
1034 | * set bit 0 for pull model, bits 3-1 for block fetch |
1035 | * register number | |
1036 | */ | |
25163bd5 WS |
1037 | #define DEFAULT_REPLY_QUEUE (-1) |
1038 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c, | |
1039 | int reply_queue) | |
3f5eac3a | 1040 | { |
254f796b | 1041 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 1042 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
bc2bb154 | 1043 | if (unlikely(!h->msix_vectors)) |
25163bd5 | 1044 | return; |
8b834bff | 1045 | c->Header.ReplyQueue = reply_queue; |
254f796b | 1046 | } |
3f5eac3a SC |
1047 | } |
1048 | ||
c349775e | 1049 | static void set_ioaccel1_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
1050 | struct CommandList *c, |
1051 | int reply_queue) | |
c349775e ST |
1052 | { |
1053 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
1054 | ||
25163bd5 WS |
1055 | /* |
1056 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
1057 | * processor. This seems to give the best I/O throughput. |
1058 | */ | |
8b834bff | 1059 | cp->ReplyQueue = reply_queue; |
25163bd5 WS |
1060 | /* |
1061 | * Set the bits in the address sent down to include: | |
c349775e ST |
1062 | * - performant mode bit (bit 0) |
1063 | * - pull count (bits 1-3) | |
1064 | * - command type (bits 4-6) | |
1065 | */ | |
1066 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | | |
1067 | IOACCEL1_BUSADDR_CMDTYPE; | |
1068 | } | |
1069 | ||
8be986cc SC |
1070 | static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h, |
1071 | struct CommandList *c, | |
1072 | int reply_queue) | |
1073 | { | |
1074 | struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *) | |
1075 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1076 | ||
1077 | /* Tell the controller to post the reply to the queue for this | |
1078 | * processor. This seems to give the best I/O throughput. | |
1079 | */ | |
8b834bff | 1080 | cp->reply_queue = reply_queue; |
8be986cc SC |
1081 | /* Set the bits in the address sent down to include: |
1082 | * - performant mode bit not used in ioaccel mode 2 | |
1083 | * - pull count (bits 0-3) | |
1084 | * - command type isn't needed for ioaccel2 | |
1085 | */ | |
1086 | c->busaddr |= h->ioaccel2_blockFetchTable[0]; | |
1087 | } | |
1088 | ||
c349775e | 1089 | static void set_ioaccel2_performant_mode(struct ctlr_info *h, |
25163bd5 WS |
1090 | struct CommandList *c, |
1091 | int reply_queue) | |
c349775e ST |
1092 | { |
1093 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1094 | ||
25163bd5 WS |
1095 | /* |
1096 | * Tell the controller to post the reply to the queue for this | |
c349775e ST |
1097 | * processor. This seems to give the best I/O throughput. |
1098 | */ | |
8b834bff | 1099 | cp->reply_queue = reply_queue; |
25163bd5 WS |
1100 | /* |
1101 | * Set the bits in the address sent down to include: | |
c349775e ST |
1102 | * - performant mode bit not used in ioaccel mode 2 |
1103 | * - pull count (bits 0-3) | |
1104 | * - command type isn't needed for ioaccel2 | |
1105 | */ | |
1106 | c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); | |
1107 | } | |
1108 | ||
e85c5974 SC |
1109 | static int is_firmware_flash_cmd(u8 *cdb) |
1110 | { | |
1111 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
1112 | } | |
1113 | ||
1114 | /* | |
1115 | * During firmware flash, the heartbeat register may not update as frequently | |
1116 | * as it should. So we dial down lockup detection during firmware flash. and | |
1117 | * dial it back up when firmware flash completes. | |
1118 | */ | |
1119 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
1120 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
3d38f00c | 1121 | #define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ) |
e85c5974 SC |
1122 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, |
1123 | struct CommandList *c) | |
1124 | { | |
1125 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
1126 | return; | |
1127 | atomic_inc(&h->firmware_flash_in_progress); | |
1128 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
1129 | } | |
1130 | ||
1131 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
1132 | struct CommandList *c) | |
1133 | { | |
1134 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
1135 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
1136 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
1137 | } | |
1138 | ||
25163bd5 WS |
1139 | static void __enqueue_cmd_and_start_io(struct ctlr_info *h, |
1140 | struct CommandList *c, int reply_queue) | |
3f5eac3a | 1141 | { |
c05e8866 SC |
1142 | dial_down_lockup_detection_during_fw_flash(h, c); |
1143 | atomic_inc(&h->commands_outstanding); | |
c5dfd106 DB |
1144 | if (c->device) |
1145 | atomic_inc(&c->device->commands_outstanding); | |
8b834bff ML |
1146 | |
1147 | reply_queue = h->reply_map[raw_smp_processor_id()]; | |
c349775e ST |
1148 | switch (c->cmd_type) { |
1149 | case CMD_IOACCEL1: | |
25163bd5 | 1150 | set_ioaccel1_performant_mode(h, c, reply_queue); |
c05e8866 | 1151 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
1152 | break; |
1153 | case CMD_IOACCEL2: | |
25163bd5 | 1154 | set_ioaccel2_performant_mode(h, c, reply_queue); |
c05e8866 | 1155 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); |
c349775e | 1156 | break; |
8be986cc SC |
1157 | case IOACCEL2_TMF: |
1158 | set_ioaccel2_tmf_performant_mode(h, c, reply_queue); | |
1159 | writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32); | |
1160 | break; | |
c349775e | 1161 | default: |
25163bd5 | 1162 | set_performant_mode(h, c, reply_queue); |
c05e8866 | 1163 | h->access.submit_command(h, c); |
c349775e | 1164 | } |
3f5eac3a SC |
1165 | } |
1166 | ||
a58e7e53 | 1167 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c) |
25163bd5 WS |
1168 | { |
1169 | __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE); | |
1170 | } | |
1171 | ||
3f5eac3a SC |
1172 | static inline int is_hba_lunid(unsigned char scsi3addr[]) |
1173 | { | |
1174 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
1175 | } | |
1176 | ||
1177 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
1178 | { | |
1179 | if (!h->hba_inquiry_data) | |
1180 | return 0; | |
1181 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
1182 | return 1; | |
1183 | return 0; | |
1184 | } | |
1185 | ||
edd16368 SC |
1186 | static int hpsa_find_target_lun(struct ctlr_info *h, |
1187 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
1188 | { | |
1189 | /* finds an unused bus, target, lun for a new physical device | |
1190 | * assumes h->devlock is held | |
1191 | */ | |
1192 | int i, found = 0; | |
cfe5badc | 1193 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 1194 | |
263d9401 | 1195 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
1196 | |
1197 | for (i = 0; i < h->ndevices; i++) { | |
1198 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 1199 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
1200 | } |
1201 | ||
263d9401 AM |
1202 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
1203 | if (i < HPSA_MAX_DEVICES) { | |
1204 | /* *bus = 1; */ | |
1205 | *target = i; | |
1206 | *lun = 0; | |
1207 | found = 1; | |
edd16368 SC |
1208 | } |
1209 | return !found; | |
1210 | } | |
1211 | ||
1d33d85d | 1212 | static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h, |
0d96ef5f WS |
1213 | struct hpsa_scsi_dev_t *dev, char *description) |
1214 | { | |
7c59a0d4 DB |
1215 | #define LABEL_SIZE 25 |
1216 | char label[LABEL_SIZE]; | |
1217 | ||
9975ec9d DB |
1218 | if (h == NULL || h->pdev == NULL || h->scsi_host == NULL) |
1219 | return; | |
1220 | ||
7c59a0d4 DB |
1221 | switch (dev->devtype) { |
1222 | case TYPE_RAID: | |
1223 | snprintf(label, LABEL_SIZE, "controller"); | |
1224 | break; | |
1225 | case TYPE_ENCLOSURE: | |
1226 | snprintf(label, LABEL_SIZE, "enclosure"); | |
1227 | break; | |
1228 | case TYPE_DISK: | |
af15ed36 | 1229 | case TYPE_ZBC: |
7c59a0d4 DB |
1230 | if (dev->external) |
1231 | snprintf(label, LABEL_SIZE, "external"); | |
1232 | else if (!is_logical_dev_addr_mode(dev->scsi3addr)) | |
1233 | snprintf(label, LABEL_SIZE, "%s", | |
1234 | raid_label[PHYSICAL_DRIVE]); | |
1235 | else | |
1236 | snprintf(label, LABEL_SIZE, "RAID-%s", | |
1237 | dev->raid_level > RAID_UNKNOWN ? "?" : | |
1238 | raid_label[dev->raid_level]); | |
1239 | break; | |
1240 | case TYPE_ROM: | |
1241 | snprintf(label, LABEL_SIZE, "rom"); | |
1242 | break; | |
1243 | case TYPE_TAPE: | |
1244 | snprintf(label, LABEL_SIZE, "tape"); | |
1245 | break; | |
1246 | case TYPE_MEDIUM_CHANGER: | |
1247 | snprintf(label, LABEL_SIZE, "changer"); | |
1248 | break; | |
1249 | default: | |
1250 | snprintf(label, LABEL_SIZE, "UNKNOWN"); | |
1251 | break; | |
1252 | } | |
1253 | ||
0d96ef5f | 1254 | dev_printk(level, &h->pdev->dev, |
7c59a0d4 | 1255 | "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n", |
0d96ef5f WS |
1256 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, |
1257 | description, | |
1258 | scsi_device_type(dev->devtype), | |
1259 | dev->vendor, | |
1260 | dev->model, | |
7c59a0d4 | 1261 | label, |
0d96ef5f | 1262 | dev->offload_config ? '+' : '-', |
b2582a65 | 1263 | dev->offload_to_be_enabled ? '+' : '-', |
2a168208 | 1264 | dev->expose_device); |
0d96ef5f WS |
1265 | } |
1266 | ||
edd16368 | 1267 | /* Add an entry into h->dev[] array. */ |
8aa60681 | 1268 | static int hpsa_scsi_add_entry(struct ctlr_info *h, |
edd16368 SC |
1269 | struct hpsa_scsi_dev_t *device, |
1270 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
1271 | { | |
1272 | /* assumes h->devlock is held */ | |
1273 | int n = h->ndevices; | |
1274 | int i; | |
1275 | unsigned char addr1[8], addr2[8]; | |
1276 | struct hpsa_scsi_dev_t *sd; | |
1277 | ||
cfe5badc | 1278 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
1279 | dev_err(&h->pdev->dev, "too many devices, some will be " |
1280 | "inaccessible.\n"); | |
1281 | return -1; | |
1282 | } | |
1283 | ||
1284 | /* physical devices do not have lun or target assigned until now. */ | |
1285 | if (device->lun != -1) | |
1286 | /* Logical device, lun is already assigned. */ | |
1287 | goto lun_assigned; | |
1288 | ||
1289 | /* If this device a non-zero lun of a multi-lun device | |
1290 | * byte 4 of the 8-byte LUN addr will contain the logical | |
2b08b3e9 | 1291 | * unit no, zero otherwise. |
edd16368 SC |
1292 | */ |
1293 | if (device->scsi3addr[4] == 0) { | |
1294 | /* This is not a non-zero lun of a multi-lun device */ | |
1295 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
1296 | device->bus, &device->target, &device->lun) != 0) | |
1297 | return -1; | |
1298 | goto lun_assigned; | |
1299 | } | |
1300 | ||
1301 | /* This is a non-zero lun of a multi-lun device. | |
1302 | * Search through our list and find the device which | |
9a4178b7 | 1303 | * has the same 8 byte LUN address, excepting byte 4 and 5. |
edd16368 SC |
1304 | * Assign the same bus and target for this new LUN. |
1305 | * Use the logical unit number from the firmware. | |
1306 | */ | |
1307 | memcpy(addr1, device->scsi3addr, 8); | |
1308 | addr1[4] = 0; | |
9a4178b7 | 1309 | addr1[5] = 0; |
edd16368 SC |
1310 | for (i = 0; i < n; i++) { |
1311 | sd = h->dev[i]; | |
1312 | memcpy(addr2, sd->scsi3addr, 8); | |
1313 | addr2[4] = 0; | |
9a4178b7 | 1314 | addr2[5] = 0; |
1315 | /* differ only in byte 4 and 5? */ | |
edd16368 SC |
1316 | if (memcmp(addr1, addr2, 8) == 0) { |
1317 | device->bus = sd->bus; | |
1318 | device->target = sd->target; | |
1319 | device->lun = device->scsi3addr[4]; | |
1320 | break; | |
1321 | } | |
1322 | } | |
1323 | if (device->lun == -1) { | |
1324 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
1325 | " suspect firmware bug or unsupported hardware " | |
1326 | "configuration.\n"); | |
b64ae4ab | 1327 | return -1; |
edd16368 SC |
1328 | } |
1329 | ||
1330 | lun_assigned: | |
1331 | ||
1332 | h->dev[n] = device; | |
1333 | h->ndevices++; | |
1334 | added[*nadded] = device; | |
1335 | (*nadded)++; | |
0d96ef5f | 1336 | hpsa_show_dev_msg(KERN_INFO, h, device, |
2a168208 | 1337 | device->expose_device ? "added" : "masked"); |
edd16368 SC |
1338 | return 0; |
1339 | } | |
1340 | ||
b2582a65 DB |
1341 | /* |
1342 | * Called during a scan operation. | |
1343 | * | |
1344 | * Update an entry in h->dev[] array. | |
1345 | */ | |
8aa60681 | 1346 | static void hpsa_scsi_update_entry(struct ctlr_info *h, |
bd9244f7 ST |
1347 | int entry, struct hpsa_scsi_dev_t *new_entry) |
1348 | { | |
1349 | /* assumes h->devlock is held */ | |
1350 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
1351 | ||
1352 | /* Raid level changed. */ | |
1353 | h->dev[entry]->raid_level = new_entry->raid_level; | |
250fb125 | 1354 | |
b2582a65 DB |
1355 | /* |
1356 | * ioacccel_handle may have changed for a dual domain disk | |
1357 | */ | |
1358 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
1359 | ||
03383736 | 1360 | /* Raid offload parameters changed. Careful about the ordering. */ |
b2582a65 | 1361 | if (new_entry->offload_config && new_entry->offload_to_be_enabled) { |
03383736 DB |
1362 | /* |
1363 | * if drive is newly offload_enabled, we want to copy the | |
1364 | * raid map data first. If previously offload_enabled and | |
1365 | * offload_config were set, raid map data had better be | |
b2582a65 | 1366 | * the same as it was before. If raid map data has changed |
03383736 DB |
1367 | * then it had better be the case that |
1368 | * h->dev[entry]->offload_enabled is currently 0. | |
1369 | */ | |
1370 | h->dev[entry]->raid_map = new_entry->raid_map; | |
1371 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
03383736 | 1372 | } |
b2582a65 | 1373 | if (new_entry->offload_to_be_enabled) { |
a3144e0b JH |
1374 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; |
1375 | wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */ | |
1376 | } | |
1377 | h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled; | |
250fb125 | 1378 | h->dev[entry]->offload_config = new_entry->offload_config; |
9fb0de2d | 1379 | h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; |
03383736 | 1380 | h->dev[entry]->queue_depth = new_entry->queue_depth; |
250fb125 | 1381 | |
41ce4c35 SC |
1382 | /* |
1383 | * We can turn off ioaccel offload now, but need to delay turning | |
b2582a65 | 1384 | * ioaccel on until we can update h->dev[entry]->phys_disk[], but we |
41ce4c35 SC |
1385 | * can't do that until all the devices are updated. |
1386 | */ | |
b2582a65 DB |
1387 | h->dev[entry]->offload_to_be_enabled = new_entry->offload_to_be_enabled; |
1388 | ||
1389 | /* | |
1390 | * turn ioaccel off immediately if told to do so. | |
1391 | */ | |
1392 | if (!new_entry->offload_to_be_enabled) | |
41ce4c35 SC |
1393 | h->dev[entry]->offload_enabled = 0; |
1394 | ||
0d96ef5f | 1395 | hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated"); |
bd9244f7 ST |
1396 | } |
1397 | ||
2a8ccf31 | 1398 | /* Replace an entry from h->dev[] array. */ |
8aa60681 | 1399 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, |
2a8ccf31 SC |
1400 | int entry, struct hpsa_scsi_dev_t *new_entry, |
1401 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
1402 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
1403 | { | |
1404 | /* assumes h->devlock is held */ | |
cfe5badc | 1405 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
1406 | removed[*nremoved] = h->dev[entry]; |
1407 | (*nremoved)++; | |
01350d05 SC |
1408 | |
1409 | /* | |
1410 | * New physical devices won't have target/lun assigned yet | |
1411 | * so we need to preserve the values in the slot we are replacing. | |
1412 | */ | |
1413 | if (new_entry->target == -1) { | |
1414 | new_entry->target = h->dev[entry]->target; | |
1415 | new_entry->lun = h->dev[entry]->lun; | |
1416 | } | |
1417 | ||
2a8ccf31 SC |
1418 | h->dev[entry] = new_entry; |
1419 | added[*nadded] = new_entry; | |
1420 | (*nadded)++; | |
b2582a65 | 1421 | |
0d96ef5f | 1422 | hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced"); |
2a8ccf31 SC |
1423 | } |
1424 | ||
edd16368 | 1425 | /* Remove an entry from h->dev[] array. */ |
8aa60681 | 1426 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry, |
edd16368 SC |
1427 | struct hpsa_scsi_dev_t *removed[], int *nremoved) |
1428 | { | |
1429 | /* assumes h->devlock is held */ | |
1430 | int i; | |
1431 | struct hpsa_scsi_dev_t *sd; | |
1432 | ||
cfe5badc | 1433 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
1434 | |
1435 | sd = h->dev[entry]; | |
1436 | removed[*nremoved] = h->dev[entry]; | |
1437 | (*nremoved)++; | |
1438 | ||
1439 | for (i = entry; i < h->ndevices-1; i++) | |
1440 | h->dev[i] = h->dev[i+1]; | |
1441 | h->ndevices--; | |
0d96ef5f | 1442 | hpsa_show_dev_msg(KERN_INFO, h, sd, "removed"); |
edd16368 SC |
1443 | } |
1444 | ||
1445 | #define SCSI3ADDR_EQ(a, b) ( \ | |
1446 | (a)[7] == (b)[7] && \ | |
1447 | (a)[6] == (b)[6] && \ | |
1448 | (a)[5] == (b)[5] && \ | |
1449 | (a)[4] == (b)[4] && \ | |
1450 | (a)[3] == (b)[3] && \ | |
1451 | (a)[2] == (b)[2] && \ | |
1452 | (a)[1] == (b)[1] && \ | |
1453 | (a)[0] == (b)[0]) | |
1454 | ||
1455 | static void fixup_botched_add(struct ctlr_info *h, | |
1456 | struct hpsa_scsi_dev_t *added) | |
1457 | { | |
1458 | /* called when scsi_add_device fails in order to re-adjust | |
1459 | * h->dev[] to match the mid layer's view. | |
1460 | */ | |
1461 | unsigned long flags; | |
1462 | int i, j; | |
1463 | ||
1464 | spin_lock_irqsave(&h->lock, flags); | |
1465 | for (i = 0; i < h->ndevices; i++) { | |
1466 | if (h->dev[i] == added) { | |
1467 | for (j = i; j < h->ndevices-1; j++) | |
1468 | h->dev[j] = h->dev[j+1]; | |
1469 | h->ndevices--; | |
1470 | break; | |
1471 | } | |
1472 | } | |
1473 | spin_unlock_irqrestore(&h->lock, flags); | |
1474 | kfree(added); | |
1475 | } | |
1476 | ||
1477 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
1478 | struct hpsa_scsi_dev_t *dev2) | |
1479 | { | |
edd16368 SC |
1480 | /* we compare everything except lun and target as these |
1481 | * are not yet assigned. Compare parts likely | |
1482 | * to differ first | |
1483 | */ | |
1484 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
1485 | sizeof(dev1->scsi3addr)) != 0) | |
1486 | return 0; | |
1487 | if (memcmp(dev1->device_id, dev2->device_id, | |
1488 | sizeof(dev1->device_id)) != 0) | |
1489 | return 0; | |
1490 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
1491 | return 0; | |
1492 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
1493 | return 0; | |
edd16368 SC |
1494 | if (dev1->devtype != dev2->devtype) |
1495 | return 0; | |
edd16368 SC |
1496 | if (dev1->bus != dev2->bus) |
1497 | return 0; | |
1498 | return 1; | |
1499 | } | |
1500 | ||
bd9244f7 ST |
1501 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
1502 | struct hpsa_scsi_dev_t *dev2) | |
1503 | { | |
1504 | /* Device attributes that can change, but don't mean | |
1505 | * that the device is a different device, nor that the OS | |
1506 | * needs to be told anything about the change. | |
1507 | */ | |
1508 | if (dev1->raid_level != dev2->raid_level) | |
1509 | return 1; | |
250fb125 SC |
1510 | if (dev1->offload_config != dev2->offload_config) |
1511 | return 1; | |
b2582a65 | 1512 | if (dev1->offload_to_be_enabled != dev2->offload_to_be_enabled) |
250fb125 | 1513 | return 1; |
93849508 DB |
1514 | if (!is_logical_dev_addr_mode(dev1->scsi3addr)) |
1515 | if (dev1->queue_depth != dev2->queue_depth) | |
1516 | return 1; | |
b2582a65 DB |
1517 | /* |
1518 | * This can happen for dual domain devices. An active | |
1519 | * path change causes the ioaccel handle to change | |
1520 | * | |
1521 | * for example note the handle differences between p0 and p1 | |
1522 | * Device WWN ,WWN hash,Handle | |
1523 | * D016 p0|0x3 [02]P2E:01:01,0x5000C5005FC4DACA,0x9B5616,0x01030003 | |
1524 | * p1 0x5000C5005FC4DAC9,0x6798C0,0x00040004 | |
1525 | */ | |
1526 | if (dev1->ioaccel_handle != dev2->ioaccel_handle) | |
1527 | return 1; | |
bd9244f7 ST |
1528 | return 0; |
1529 | } | |
1530 | ||
edd16368 SC |
1531 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
1532 | * and return needle location in *index. If scsi3addr matches, but not | |
1533 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
1534 | * location in *index. |
1535 | * In the case of a minor device attribute change, such as RAID level, just | |
1536 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
1537 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
1538 | */ |
1539 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
1540 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
1541 | int *index) | |
1542 | { | |
1543 | int i; | |
1544 | #define DEVICE_NOT_FOUND 0 | |
1545 | #define DEVICE_CHANGED 1 | |
1546 | #define DEVICE_SAME 2 | |
bd9244f7 | 1547 | #define DEVICE_UPDATED 3 |
1d33d85d DB |
1548 | if (needle == NULL) |
1549 | return DEVICE_NOT_FOUND; | |
1550 | ||
edd16368 | 1551 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
1552 | if (haystack[i] == NULL) /* previously removed. */ |
1553 | continue; | |
edd16368 SC |
1554 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
1555 | *index = i; | |
bd9244f7 ST |
1556 | if (device_is_the_same(needle, haystack[i])) { |
1557 | if (device_updated(needle, haystack[i])) | |
1558 | return DEVICE_UPDATED; | |
edd16368 | 1559 | return DEVICE_SAME; |
bd9244f7 | 1560 | } else { |
9846590e SC |
1561 | /* Keep offline devices offline */ |
1562 | if (needle->volume_offline) | |
1563 | return DEVICE_NOT_FOUND; | |
edd16368 | 1564 | return DEVICE_CHANGED; |
bd9244f7 | 1565 | } |
edd16368 SC |
1566 | } |
1567 | } | |
1568 | *index = -1; | |
1569 | return DEVICE_NOT_FOUND; | |
1570 | } | |
1571 | ||
9846590e SC |
1572 | static void hpsa_monitor_offline_device(struct ctlr_info *h, |
1573 | unsigned char scsi3addr[]) | |
1574 | { | |
1575 | struct offline_device_entry *device; | |
1576 | unsigned long flags; | |
1577 | ||
1578 | /* Check to see if device is already on the list */ | |
1579 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1580 | list_for_each_entry(device, &h->offline_device_list, offline_list) { | |
1581 | if (memcmp(device->scsi3addr, scsi3addr, | |
1582 | sizeof(device->scsi3addr)) == 0) { | |
1583 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1584 | return; | |
1585 | } | |
1586 | } | |
1587 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1588 | ||
1589 | /* Device is not on the list, add it. */ | |
1590 | device = kmalloc(sizeof(*device), GFP_KERNEL); | |
7e8a9486 | 1591 | if (!device) |
9846590e | 1592 | return; |
7e8a9486 | 1593 | |
9846590e SC |
1594 | memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); |
1595 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1596 | list_add_tail(&device->offline_list, &h->offline_device_list); | |
1597 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1598 | } | |
1599 | ||
1600 | /* Print a message explaining various offline volume states */ | |
1601 | static void hpsa_show_volume_status(struct ctlr_info *h, | |
1602 | struct hpsa_scsi_dev_t *sd) | |
1603 | { | |
1604 | if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) | |
1605 | dev_info(&h->pdev->dev, | |
1606 | "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", | |
1607 | h->scsi_host->host_no, | |
1608 | sd->bus, sd->target, sd->lun); | |
1609 | switch (sd->volume_offline) { | |
1610 | case HPSA_LV_OK: | |
1611 | break; | |
1612 | case HPSA_LV_UNDERGOING_ERASE: | |
1613 | dev_info(&h->pdev->dev, | |
1614 | "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", | |
1615 | h->scsi_host->host_no, | |
1616 | sd->bus, sd->target, sd->lun); | |
1617 | break; | |
5ca01204 SB |
1618 | case HPSA_LV_NOT_AVAILABLE: |
1619 | dev_info(&h->pdev->dev, | |
1620 | "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n", | |
1621 | h->scsi_host->host_no, | |
1622 | sd->bus, sd->target, sd->lun); | |
1623 | break; | |
9846590e SC |
1624 | case HPSA_LV_UNDERGOING_RPI: |
1625 | dev_info(&h->pdev->dev, | |
5ca01204 | 1626 | "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n", |
9846590e SC |
1627 | h->scsi_host->host_no, |
1628 | sd->bus, sd->target, sd->lun); | |
1629 | break; | |
1630 | case HPSA_LV_PENDING_RPI: | |
1631 | dev_info(&h->pdev->dev, | |
5ca01204 SB |
1632 | "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", |
1633 | h->scsi_host->host_no, | |
1634 | sd->bus, sd->target, sd->lun); | |
9846590e SC |
1635 | break; |
1636 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
1637 | dev_info(&h->pdev->dev, | |
1638 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", | |
1639 | h->scsi_host->host_no, | |
1640 | sd->bus, sd->target, sd->lun); | |
1641 | break; | |
1642 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
1643 | dev_info(&h->pdev->dev, | |
1644 | "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", | |
1645 | h->scsi_host->host_no, | |
1646 | sd->bus, sd->target, sd->lun); | |
1647 | break; | |
1648 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
1649 | dev_info(&h->pdev->dev, | |
1650 | "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", | |
1651 | h->scsi_host->host_no, | |
1652 | sd->bus, sd->target, sd->lun); | |
1653 | break; | |
1654 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
1655 | dev_info(&h->pdev->dev, | |
1656 | "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", | |
1657 | h->scsi_host->host_no, | |
1658 | sd->bus, sd->target, sd->lun); | |
1659 | break; | |
1660 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
1661 | dev_info(&h->pdev->dev, | |
1662 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", | |
1663 | h->scsi_host->host_no, | |
1664 | sd->bus, sd->target, sd->lun); | |
1665 | break; | |
1666 | case HPSA_LV_PENDING_ENCRYPTION: | |
1667 | dev_info(&h->pdev->dev, | |
1668 | "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", | |
1669 | h->scsi_host->host_no, | |
1670 | sd->bus, sd->target, sd->lun); | |
1671 | break; | |
1672 | case HPSA_LV_PENDING_ENCRYPTION_REKEYING: | |
1673 | dev_info(&h->pdev->dev, | |
1674 | "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", | |
1675 | h->scsi_host->host_no, | |
1676 | sd->bus, sd->target, sd->lun); | |
1677 | break; | |
1678 | } | |
1679 | } | |
1680 | ||
03383736 DB |
1681 | /* |
1682 | * Figure the list of physical drive pointers for a logical drive with | |
1683 | * raid offload configured. | |
1684 | */ | |
1685 | static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, | |
1686 | struct hpsa_scsi_dev_t *dev[], int ndevices, | |
1687 | struct hpsa_scsi_dev_t *logical_drive) | |
1688 | { | |
1689 | struct raid_map_data *map = &logical_drive->raid_map; | |
1690 | struct raid_map_disk_data *dd = &map->data[0]; | |
1691 | int i, j; | |
1692 | int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + | |
1693 | le16_to_cpu(map->metadata_disks_per_row); | |
1694 | int nraid_map_entries = le16_to_cpu(map->row_cnt) * | |
1695 | le16_to_cpu(map->layout_map_count) * | |
1696 | total_disks_per_row; | |
1697 | int nphys_disk = le16_to_cpu(map->layout_map_count) * | |
1698 | total_disks_per_row; | |
1699 | int qdepth; | |
1700 | ||
1701 | if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) | |
1702 | nraid_map_entries = RAID_MAP_MAX_ENTRIES; | |
1703 | ||
d604f533 WS |
1704 | logical_drive->nphysical_disks = nraid_map_entries; |
1705 | ||
03383736 DB |
1706 | qdepth = 0; |
1707 | for (i = 0; i < nraid_map_entries; i++) { | |
1708 | logical_drive->phys_disk[i] = NULL; | |
1709 | if (!logical_drive->offload_config) | |
1710 | continue; | |
1711 | for (j = 0; j < ndevices; j++) { | |
1d33d85d DB |
1712 | if (dev[j] == NULL) |
1713 | continue; | |
ff615f06 PK |
1714 | if (dev[j]->devtype != TYPE_DISK && |
1715 | dev[j]->devtype != TYPE_ZBC) | |
af15ed36 | 1716 | continue; |
f3f01730 | 1717 | if (is_logical_device(dev[j])) |
03383736 DB |
1718 | continue; |
1719 | if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) | |
1720 | continue; | |
1721 | ||
1722 | logical_drive->phys_disk[i] = dev[j]; | |
1723 | if (i < nphys_disk) | |
1724 | qdepth = min(h->nr_cmds, qdepth + | |
1725 | logical_drive->phys_disk[i]->queue_depth); | |
1726 | break; | |
1727 | } | |
1728 | ||
1729 | /* | |
1730 | * This can happen if a physical drive is removed and | |
1731 | * the logical drive is degraded. In that case, the RAID | |
1732 | * map data will refer to a physical disk which isn't actually | |
1733 | * present. And in that case offload_enabled should already | |
1734 | * be 0, but we'll turn it off here just in case | |
1735 | */ | |
1736 | if (!logical_drive->phys_disk[i]) { | |
b2582a65 DB |
1737 | dev_warn(&h->pdev->dev, |
1738 | "%s: [%d:%d:%d:%d] A phys disk component of LV is missing, turning off offload_enabled for LV.\n", | |
1739 | __func__, | |
1740 | h->scsi_host->host_no, logical_drive->bus, | |
1741 | logical_drive->target, logical_drive->lun); | |
03383736 | 1742 | logical_drive->offload_enabled = 0; |
41ce4c35 SC |
1743 | logical_drive->offload_to_be_enabled = 0; |
1744 | logical_drive->queue_depth = 8; | |
03383736 DB |
1745 | } |
1746 | } | |
1747 | if (nraid_map_entries) | |
1748 | /* | |
1749 | * This is correct for reads, too high for full stripe writes, | |
1750 | * way too high for partial stripe writes | |
1751 | */ | |
1752 | logical_drive->queue_depth = qdepth; | |
2c5fc363 DB |
1753 | else { |
1754 | if (logical_drive->external) | |
1755 | logical_drive->queue_depth = EXTERNAL_QD; | |
1756 | else | |
1757 | logical_drive->queue_depth = h->nr_cmds; | |
1758 | } | |
03383736 DB |
1759 | } |
1760 | ||
1761 | static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, | |
1762 | struct hpsa_scsi_dev_t *dev[], int ndevices) | |
1763 | { | |
1764 | int i; | |
1765 | ||
1766 | for (i = 0; i < ndevices; i++) { | |
1d33d85d DB |
1767 | if (dev[i] == NULL) |
1768 | continue; | |
ff615f06 PK |
1769 | if (dev[i]->devtype != TYPE_DISK && |
1770 | dev[i]->devtype != TYPE_ZBC) | |
af15ed36 | 1771 | continue; |
f3f01730 | 1772 | if (!is_logical_device(dev[i])) |
03383736 | 1773 | continue; |
41ce4c35 SC |
1774 | |
1775 | /* | |
1776 | * If offload is currently enabled, the RAID map and | |
1777 | * phys_disk[] assignment *better* not be changing | |
b2582a65 DB |
1778 | * because we would be changing ioaccel phsy_disk[] pointers |
1779 | * on a ioaccel volume processing I/O requests. | |
1780 | * | |
1781 | * If an ioaccel volume status changed, initially because it was | |
1782 | * re-configured and thus underwent a transformation, or | |
1783 | * a drive failed, we would have received a state change | |
1784 | * request and ioaccel should have been turned off. When the | |
1785 | * transformation completes, we get another state change | |
1786 | * request to turn ioaccel back on. In this case, we need | |
1787 | * to update the ioaccel information. | |
1788 | * | |
1789 | * Thus: If it is not currently enabled, but will be after | |
1790 | * the scan completes, make sure the ioaccel pointers | |
1791 | * are up to date. | |
41ce4c35 | 1792 | */ |
41ce4c35 | 1793 | |
b2582a65 DB |
1794 | if (!dev[i]->offload_enabled && dev[i]->offload_to_be_enabled) |
1795 | hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); | |
03383736 DB |
1796 | } |
1797 | } | |
1798 | ||
096ccff4 KB |
1799 | static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
1800 | { | |
1801 | int rc = 0; | |
1802 | ||
1803 | if (!h->scsi_host) | |
1804 | return 1; | |
1805 | ||
d04e62b9 KB |
1806 | if (is_logical_device(device)) /* RAID */ |
1807 | rc = scsi_add_device(h->scsi_host, device->bus, | |
096ccff4 | 1808 | device->target, device->lun); |
d04e62b9 KB |
1809 | else /* HBA */ |
1810 | rc = hpsa_add_sas_device(h->sas_host, device); | |
1811 | ||
096ccff4 KB |
1812 | return rc; |
1813 | } | |
1814 | ||
ba74fdc4 DB |
1815 | static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h, |
1816 | struct hpsa_scsi_dev_t *dev) | |
1817 | { | |
1818 | int i; | |
1819 | int count = 0; | |
1820 | ||
1821 | for (i = 0; i < h->nr_cmds; i++) { | |
1822 | struct CommandList *c = h->cmd_pool + i; | |
1823 | int refcount = atomic_inc_return(&c->refcount); | |
1824 | ||
1825 | if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, | |
1826 | dev->scsi3addr)) { | |
1827 | unsigned long flags; | |
1828 | ||
1829 | spin_lock_irqsave(&h->lock, flags); /* Implied MB */ | |
1830 | if (!hpsa_is_cmd_idle(c)) | |
1831 | ++count; | |
1832 | spin_unlock_irqrestore(&h->lock, flags); | |
1833 | } | |
1834 | ||
1835 | cmd_free(h, c); | |
1836 | } | |
1837 | ||
1838 | return count; | |
1839 | } | |
1840 | ||
b443d3ea | 1841 | #define NUM_WAIT 20 |
ba74fdc4 DB |
1842 | static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h, |
1843 | struct hpsa_scsi_dev_t *device) | |
1844 | { | |
1845 | int cmds = 0; | |
1846 | int waits = 0; | |
b443d3ea DB |
1847 | int num_wait = NUM_WAIT; |
1848 | ||
1849 | if (device->external) | |
1850 | num_wait = HPSA_EH_PTRAID_TIMEOUT; | |
ba74fdc4 DB |
1851 | |
1852 | while (1) { | |
1853 | cmds = hpsa_find_outstanding_commands_for_dev(h, device); | |
1854 | if (cmds == 0) | |
1855 | break; | |
b443d3ea | 1856 | if (++waits > num_wait) |
ba74fdc4 | 1857 | break; |
9211a07f DB |
1858 | msleep(1000); |
1859 | } | |
1860 | ||
b443d3ea | 1861 | if (waits > num_wait) { |
ba74fdc4 | 1862 | dev_warn(&h->pdev->dev, |
b443d3ea DB |
1863 | "%s: removing device [%d:%d:%d:%d] with %d outstanding commands!\n", |
1864 | __func__, | |
1865 | h->scsi_host->host_no, | |
1866 | device->bus, device->target, device->lun, cmds); | |
1867 | } | |
ba74fdc4 DB |
1868 | } |
1869 | ||
096ccff4 KB |
1870 | static void hpsa_remove_device(struct ctlr_info *h, |
1871 | struct hpsa_scsi_dev_t *device) | |
1872 | { | |
1873 | struct scsi_device *sdev = NULL; | |
1874 | ||
1875 | if (!h->scsi_host) | |
1876 | return; | |
1877 | ||
0ff365f5 DB |
1878 | /* |
1879 | * Allow for commands to drain | |
1880 | */ | |
1881 | device->removed = 1; | |
1882 | hpsa_wait_for_outstanding_commands_for_dev(h, device); | |
1883 | ||
d04e62b9 KB |
1884 | if (is_logical_device(device)) { /* RAID */ |
1885 | sdev = scsi_device_lookup(h->scsi_host, device->bus, | |
096ccff4 | 1886 | device->target, device->lun); |
d04e62b9 KB |
1887 | if (sdev) { |
1888 | scsi_remove_device(sdev); | |
1889 | scsi_device_put(sdev); | |
1890 | } else { | |
1891 | /* | |
1892 | * We don't expect to get here. Future commands | |
1893 | * to this device will get a selection timeout as | |
1894 | * if the device were gone. | |
1895 | */ | |
1896 | hpsa_show_dev_msg(KERN_WARNING, h, device, | |
096ccff4 | 1897 | "didn't find device for removal."); |
d04e62b9 | 1898 | } |
ba74fdc4 DB |
1899 | } else { /* HBA */ |
1900 | ||
d04e62b9 | 1901 | hpsa_remove_sas_device(device); |
ba74fdc4 | 1902 | } |
096ccff4 KB |
1903 | } |
1904 | ||
8aa60681 | 1905 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, |
edd16368 SC |
1906 | struct hpsa_scsi_dev_t *sd[], int nsds) |
1907 | { | |
1908 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
1909 | * data. This function takes what's in sd to be the current | |
1910 | * reality and updates h->dev[] to reflect that reality. | |
1911 | */ | |
1912 | int i, entry, device_change, changes = 0; | |
1913 | struct hpsa_scsi_dev_t *csd; | |
1914 | unsigned long flags; | |
1915 | struct hpsa_scsi_dev_t **added, **removed; | |
1916 | int nadded, nremoved; | |
edd16368 | 1917 | |
da03ded0 DB |
1918 | /* |
1919 | * A reset can cause a device status to change | |
1920 | * re-schedule the scan to see what happened. | |
1921 | */ | |
c59d04f3 | 1922 | spin_lock_irqsave(&h->reset_lock, flags); |
da03ded0 DB |
1923 | if (h->reset_in_progress) { |
1924 | h->drv_req_rescan = 1; | |
c59d04f3 | 1925 | spin_unlock_irqrestore(&h->reset_lock, flags); |
da03ded0 DB |
1926 | return; |
1927 | } | |
c59d04f3 | 1928 | spin_unlock_irqrestore(&h->reset_lock, flags); |
edd16368 | 1929 | |
6396bb22 KC |
1930 | added = kcalloc(HPSA_MAX_DEVICES, sizeof(*added), GFP_KERNEL); |
1931 | removed = kcalloc(HPSA_MAX_DEVICES, sizeof(*removed), GFP_KERNEL); | |
edd16368 SC |
1932 | |
1933 | if (!added || !removed) { | |
1934 | dev_warn(&h->pdev->dev, "out of memory in " | |
1935 | "adjust_hpsa_scsi_table\n"); | |
1936 | goto free_and_out; | |
1937 | } | |
1938 | ||
1939 | spin_lock_irqsave(&h->devlock, flags); | |
1940 | ||
1941 | /* find any devices in h->dev[] that are not in | |
1942 | * sd[] and remove them from h->dev[], and for any | |
1943 | * devices which have changed, remove the old device | |
1944 | * info and add the new device info. | |
bd9244f7 ST |
1945 | * If minor device attributes change, just update |
1946 | * the existing device structure. | |
edd16368 SC |
1947 | */ |
1948 | i = 0; | |
1949 | nremoved = 0; | |
1950 | nadded = 0; | |
1951 | while (i < h->ndevices) { | |
1952 | csd = h->dev[i]; | |
1953 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
1954 | if (device_change == DEVICE_NOT_FOUND) { | |
1955 | changes++; | |
8aa60681 | 1956 | hpsa_scsi_remove_entry(h, i, removed, &nremoved); |
edd16368 SC |
1957 | continue; /* remove ^^^, hence i not incremented */ |
1958 | } else if (device_change == DEVICE_CHANGED) { | |
1959 | changes++; | |
8aa60681 | 1960 | hpsa_scsi_replace_entry(h, i, sd[entry], |
2a8ccf31 | 1961 | added, &nadded, removed, &nremoved); |
c7f172dc SC |
1962 | /* Set it to NULL to prevent it from being freed |
1963 | * at the bottom of hpsa_update_scsi_devices() | |
1964 | */ | |
1965 | sd[entry] = NULL; | |
bd9244f7 | 1966 | } else if (device_change == DEVICE_UPDATED) { |
8aa60681 | 1967 | hpsa_scsi_update_entry(h, i, sd[entry]); |
edd16368 SC |
1968 | } |
1969 | i++; | |
1970 | } | |
1971 | ||
1972 | /* Now, make sure every device listed in sd[] is also | |
1973 | * listed in h->dev[], adding them if they aren't found | |
1974 | */ | |
1975 | ||
1976 | for (i = 0; i < nsds; i++) { | |
1977 | if (!sd[i]) /* if already added above. */ | |
1978 | continue; | |
9846590e SC |
1979 | |
1980 | /* Don't add devices which are NOT READY, FORMAT IN PROGRESS | |
1981 | * as the SCSI mid-layer does not handle such devices well. | |
1982 | * It relentlessly loops sending TUR at 3Hz, then READ(10) | |
1983 | * at 160Hz, and prevents the system from coming up. | |
1984 | */ | |
1985 | if (sd[i]->volume_offline) { | |
1986 | hpsa_show_volume_status(h, sd[i]); | |
0d96ef5f | 1987 | hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline"); |
9846590e SC |
1988 | continue; |
1989 | } | |
1990 | ||
edd16368 SC |
1991 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, |
1992 | h->ndevices, &entry); | |
1993 | if (device_change == DEVICE_NOT_FOUND) { | |
1994 | changes++; | |
8aa60681 | 1995 | if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0) |
edd16368 SC |
1996 | break; |
1997 | sd[i] = NULL; /* prevent from being freed later. */ | |
1998 | } else if (device_change == DEVICE_CHANGED) { | |
1999 | /* should never happen... */ | |
2000 | changes++; | |
2001 | dev_warn(&h->pdev->dev, | |
2002 | "device unexpectedly changed.\n"); | |
2003 | /* but if it does happen, we just ignore that device */ | |
2004 | } | |
2005 | } | |
41ce4c35 SC |
2006 | hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices); |
2007 | ||
b2582a65 DB |
2008 | /* |
2009 | * Now that h->dev[]->phys_disk[] is coherent, we can enable | |
41ce4c35 | 2010 | * any logical drives that need it enabled. |
b2582a65 DB |
2011 | * |
2012 | * The raid map should be current by now. | |
2013 | * | |
2014 | * We are updating the device list used for I/O requests. | |
41ce4c35 | 2015 | */ |
1d33d85d DB |
2016 | for (i = 0; i < h->ndevices; i++) { |
2017 | if (h->dev[i] == NULL) | |
2018 | continue; | |
41ce4c35 | 2019 | h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled; |
1d33d85d | 2020 | } |
41ce4c35 | 2021 | |
edd16368 SC |
2022 | spin_unlock_irqrestore(&h->devlock, flags); |
2023 | ||
9846590e SC |
2024 | /* Monitor devices which are in one of several NOT READY states to be |
2025 | * brought online later. This must be done without holding h->devlock, | |
2026 | * so don't touch h->dev[] | |
2027 | */ | |
2028 | for (i = 0; i < nsds; i++) { | |
2029 | if (!sd[i]) /* if already added above. */ | |
2030 | continue; | |
2031 | if (sd[i]->volume_offline) | |
2032 | hpsa_monitor_offline_device(h, sd[i]->scsi3addr); | |
2033 | } | |
2034 | ||
edd16368 SC |
2035 | /* Don't notify scsi mid layer of any changes the first time through |
2036 | * (or if there are no changes) scsi_scan_host will do it later the | |
2037 | * first time through. | |
2038 | */ | |
8aa60681 | 2039 | if (!changes) |
edd16368 SC |
2040 | goto free_and_out; |
2041 | ||
edd16368 SC |
2042 | /* Notify scsi mid layer of any removed devices */ |
2043 | for (i = 0; i < nremoved; i++) { | |
1d33d85d DB |
2044 | if (removed[i] == NULL) |
2045 | continue; | |
096ccff4 KB |
2046 | if (removed[i]->expose_device) |
2047 | hpsa_remove_device(h, removed[i]); | |
edd16368 SC |
2048 | kfree(removed[i]); |
2049 | removed[i] = NULL; | |
2050 | } | |
2051 | ||
2052 | /* Notify scsi mid layer of any added devices */ | |
2053 | for (i = 0; i < nadded; i++) { | |
096ccff4 KB |
2054 | int rc = 0; |
2055 | ||
1d33d85d DB |
2056 | if (added[i] == NULL) |
2057 | continue; | |
2a168208 | 2058 | if (!(added[i]->expose_device)) |
41ce4c35 | 2059 | continue; |
096ccff4 KB |
2060 | rc = hpsa_add_device(h, added[i]); |
2061 | if (!rc) | |
edd16368 | 2062 | continue; |
096ccff4 KB |
2063 | dev_warn(&h->pdev->dev, |
2064 | "addition failed %d, device not added.", rc); | |
edd16368 SC |
2065 | /* now we have to remove it from h->dev, |
2066 | * since it didn't get added to scsi mid layer | |
2067 | */ | |
2068 | fixup_botched_add(h, added[i]); | |
853633e8 | 2069 | h->drv_req_rescan = 1; |
edd16368 SC |
2070 | } |
2071 | ||
2072 | free_and_out: | |
2073 | kfree(added); | |
2074 | kfree(removed); | |
edd16368 SC |
2075 | } |
2076 | ||
2077 | /* | |
9e03aa2f | 2078 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
2079 | * Assume's h->devlock is held. |
2080 | */ | |
2081 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
2082 | int bus, int target, int lun) | |
2083 | { | |
2084 | int i; | |
2085 | struct hpsa_scsi_dev_t *sd; | |
2086 | ||
2087 | for (i = 0; i < h->ndevices; i++) { | |
2088 | sd = h->dev[i]; | |
2089 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
2090 | return sd; | |
2091 | } | |
2092 | return NULL; | |
2093 | } | |
2094 | ||
edd16368 SC |
2095 | static int hpsa_slave_alloc(struct scsi_device *sdev) |
2096 | { | |
7630b3a5 | 2097 | struct hpsa_scsi_dev_t *sd = NULL; |
edd16368 SC |
2098 | unsigned long flags; |
2099 | struct ctlr_info *h; | |
2100 | ||
2101 | h = sdev_to_hba(sdev); | |
2102 | spin_lock_irqsave(&h->devlock, flags); | |
d04e62b9 KB |
2103 | if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) { |
2104 | struct scsi_target *starget; | |
2105 | struct sas_rphy *rphy; | |
2106 | ||
2107 | starget = scsi_target(sdev); | |
2108 | rphy = target_to_rphy(starget); | |
2109 | sd = hpsa_find_device_by_sas_rphy(h, rphy); | |
2110 | if (sd) { | |
2111 | sd->target = sdev_id(sdev); | |
2112 | sd->lun = sdev->lun; | |
2113 | } | |
7630b3a5 HR |
2114 | } |
2115 | if (!sd) | |
d04e62b9 KB |
2116 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), |
2117 | sdev_id(sdev), sdev->lun); | |
2118 | ||
2119 | if (sd && sd->expose_device) { | |
03383736 | 2120 | atomic_set(&sd->ioaccel_cmds_out, 0); |
d04e62b9 | 2121 | sdev->hostdata = sd; |
41ce4c35 SC |
2122 | } else |
2123 | sdev->hostdata = NULL; | |
edd16368 SC |
2124 | spin_unlock_irqrestore(&h->devlock, flags); |
2125 | return 0; | |
2126 | } | |
2127 | ||
41ce4c35 SC |
2128 | /* configure scsi device based on internal per-device structure */ |
2129 | static int hpsa_slave_configure(struct scsi_device *sdev) | |
2130 | { | |
2131 | struct hpsa_scsi_dev_t *sd; | |
2132 | int queue_depth; | |
2133 | ||
2134 | sd = sdev->hostdata; | |
2a168208 | 2135 | sdev->no_uld_attach = !sd || !sd->expose_device; |
41ce4c35 | 2136 | |
5086435e | 2137 | if (sd) { |
9e33f0d5 | 2138 | sd->was_removed = 0; |
b443d3ea | 2139 | if (sd->external) { |
5086435e | 2140 | queue_depth = EXTERNAL_QD; |
b443d3ea DB |
2141 | sdev->eh_timeout = HPSA_EH_PTRAID_TIMEOUT; |
2142 | blk_queue_rq_timeout(sdev->request_queue, | |
2143 | HPSA_EH_PTRAID_TIMEOUT); | |
2144 | } else { | |
5086435e DB |
2145 | queue_depth = sd->queue_depth != 0 ? |
2146 | sd->queue_depth : sdev->host->can_queue; | |
b443d3ea | 2147 | } |
5086435e | 2148 | } else |
41ce4c35 SC |
2149 | queue_depth = sdev->host->can_queue; |
2150 | ||
2151 | scsi_change_queue_depth(sdev, queue_depth); | |
2152 | ||
2153 | return 0; | |
2154 | } | |
2155 | ||
edd16368 SC |
2156 | static void hpsa_slave_destroy(struct scsi_device *sdev) |
2157 | { | |
9e33f0d5 DB |
2158 | struct hpsa_scsi_dev_t *hdev = NULL; |
2159 | ||
2160 | hdev = sdev->hostdata; | |
2161 | ||
2162 | if (hdev) | |
2163 | hdev->was_removed = 1; | |
edd16368 SC |
2164 | } |
2165 | ||
d9a729f3 WS |
2166 | static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h) |
2167 | { | |
2168 | int i; | |
2169 | ||
2170 | if (!h->ioaccel2_cmd_sg_list) | |
2171 | return; | |
2172 | for (i = 0; i < h->nr_cmds; i++) { | |
2173 | kfree(h->ioaccel2_cmd_sg_list[i]); | |
2174 | h->ioaccel2_cmd_sg_list[i] = NULL; | |
2175 | } | |
2176 | kfree(h->ioaccel2_cmd_sg_list); | |
2177 | h->ioaccel2_cmd_sg_list = NULL; | |
2178 | } | |
2179 | ||
2180 | static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h) | |
2181 | { | |
2182 | int i; | |
2183 | ||
2184 | if (h->chainsize <= 0) | |
2185 | return 0; | |
2186 | ||
2187 | h->ioaccel2_cmd_sg_list = | |
6396bb22 | 2188 | kcalloc(h->nr_cmds, sizeof(*h->ioaccel2_cmd_sg_list), |
d9a729f3 WS |
2189 | GFP_KERNEL); |
2190 | if (!h->ioaccel2_cmd_sg_list) | |
2191 | return -ENOMEM; | |
2192 | for (i = 0; i < h->nr_cmds; i++) { | |
2193 | h->ioaccel2_cmd_sg_list[i] = | |
6da2ec56 KC |
2194 | kmalloc_array(h->maxsgentries, |
2195 | sizeof(*h->ioaccel2_cmd_sg_list[i]), | |
2196 | GFP_KERNEL); | |
d9a729f3 WS |
2197 | if (!h->ioaccel2_cmd_sg_list[i]) |
2198 | goto clean; | |
2199 | } | |
2200 | return 0; | |
2201 | ||
2202 | clean: | |
2203 | hpsa_free_ioaccel2_sg_chain_blocks(h); | |
2204 | return -ENOMEM; | |
2205 | } | |
2206 | ||
33a2ffce SC |
2207 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
2208 | { | |
2209 | int i; | |
2210 | ||
2211 | if (!h->cmd_sg_list) | |
2212 | return; | |
2213 | for (i = 0; i < h->nr_cmds; i++) { | |
2214 | kfree(h->cmd_sg_list[i]); | |
2215 | h->cmd_sg_list[i] = NULL; | |
2216 | } | |
2217 | kfree(h->cmd_sg_list); | |
2218 | h->cmd_sg_list = NULL; | |
2219 | } | |
2220 | ||
105a3dbc | 2221 | static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h) |
33a2ffce SC |
2222 | { |
2223 | int i; | |
2224 | ||
2225 | if (h->chainsize <= 0) | |
2226 | return 0; | |
2227 | ||
6396bb22 KC |
2228 | h->cmd_sg_list = kcalloc(h->nr_cmds, sizeof(*h->cmd_sg_list), |
2229 | GFP_KERNEL); | |
7e8a9486 | 2230 | if (!h->cmd_sg_list) |
33a2ffce | 2231 | return -ENOMEM; |
7e8a9486 | 2232 | |
33a2ffce | 2233 | for (i = 0; i < h->nr_cmds; i++) { |
6da2ec56 KC |
2234 | h->cmd_sg_list[i] = kmalloc_array(h->chainsize, |
2235 | sizeof(*h->cmd_sg_list[i]), | |
2236 | GFP_KERNEL); | |
7e8a9486 | 2237 | if (!h->cmd_sg_list[i]) |
33a2ffce | 2238 | goto clean; |
7e8a9486 | 2239 | |
33a2ffce SC |
2240 | } |
2241 | return 0; | |
2242 | ||
2243 | clean: | |
2244 | hpsa_free_sg_chain_blocks(h); | |
2245 | return -ENOMEM; | |
2246 | } | |
2247 | ||
d9a729f3 WS |
2248 | static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h, |
2249 | struct io_accel2_cmd *cp, struct CommandList *c) | |
2250 | { | |
2251 | struct ioaccel2_sg_element *chain_block; | |
2252 | u64 temp64; | |
2253 | u32 chain_size; | |
2254 | ||
2255 | chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
a736e9b6 | 2256 | chain_size = le32_to_cpu(cp->sg[0].length); |
8bc8f47e CH |
2257 | temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_size, |
2258 | DMA_TO_DEVICE); | |
d9a729f3 WS |
2259 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
2260 | /* prevent subsequent unmapping */ | |
2261 | cp->sg->address = 0; | |
2262 | return -1; | |
2263 | } | |
2264 | cp->sg->address = cpu_to_le64(temp64); | |
2265 | return 0; | |
2266 | } | |
2267 | ||
2268 | static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h, | |
2269 | struct io_accel2_cmd *cp) | |
2270 | { | |
2271 | struct ioaccel2_sg_element *chain_sg; | |
2272 | u64 temp64; | |
2273 | u32 chain_size; | |
2274 | ||
2275 | chain_sg = cp->sg; | |
2276 | temp64 = le64_to_cpu(chain_sg->address); | |
a736e9b6 | 2277 | chain_size = le32_to_cpu(cp->sg[0].length); |
8bc8f47e | 2278 | dma_unmap_single(&h->pdev->dev, temp64, chain_size, DMA_TO_DEVICE); |
d9a729f3 WS |
2279 | } |
2280 | ||
e2bea6df | 2281 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
2282 | struct CommandList *c) |
2283 | { | |
2284 | struct SGDescriptor *chain_sg, *chain_block; | |
2285 | u64 temp64; | |
50a0decf | 2286 | u32 chain_len; |
33a2ffce SC |
2287 | |
2288 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
2289 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
50a0decf SC |
2290 | chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); |
2291 | chain_len = sizeof(*chain_sg) * | |
2b08b3e9 | 2292 | (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); |
50a0decf | 2293 | chain_sg->Len = cpu_to_le32(chain_len); |
8bc8f47e CH |
2294 | temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_len, |
2295 | DMA_TO_DEVICE); | |
e2bea6df SC |
2296 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
2297 | /* prevent subsequent unmapping */ | |
50a0decf | 2298 | chain_sg->Addr = cpu_to_le64(0); |
e2bea6df SC |
2299 | return -1; |
2300 | } | |
50a0decf | 2301 | chain_sg->Addr = cpu_to_le64(temp64); |
e2bea6df | 2302 | return 0; |
33a2ffce SC |
2303 | } |
2304 | ||
2305 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
2306 | struct CommandList *c) | |
2307 | { | |
2308 | struct SGDescriptor *chain_sg; | |
33a2ffce | 2309 | |
50a0decf | 2310 | if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) |
33a2ffce SC |
2311 | return; |
2312 | ||
2313 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
8bc8f47e CH |
2314 | dma_unmap_single(&h->pdev->dev, le64_to_cpu(chain_sg->Addr), |
2315 | le32_to_cpu(chain_sg->Len), DMA_TO_DEVICE); | |
33a2ffce SC |
2316 | } |
2317 | ||
a09c1441 ST |
2318 | |
2319 | /* Decode the various types of errors on ioaccel2 path. | |
2320 | * Return 1 for any error that should generate a RAID path retry. | |
2321 | * Return 0 for errors that don't require a RAID path retry. | |
2322 | */ | |
2323 | static int handle_ioaccel_mode2_error(struct ctlr_info *h, | |
c349775e ST |
2324 | struct CommandList *c, |
2325 | struct scsi_cmnd *cmd, | |
ba74fdc4 DB |
2326 | struct io_accel2_cmd *c2, |
2327 | struct hpsa_scsi_dev_t *dev) | |
c349775e ST |
2328 | { |
2329 | int data_len; | |
a09c1441 | 2330 | int retry = 0; |
c40820d5 | 2331 | u32 ioaccel2_resid = 0; |
c349775e ST |
2332 | |
2333 | switch (c2->error_data.serv_response) { | |
2334 | case IOACCEL2_SERV_RESPONSE_COMPLETE: | |
2335 | switch (c2->error_data.status) { | |
2336 | case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: | |
eeebce18 DB |
2337 | if (cmd) |
2338 | cmd->result = 0; | |
c349775e ST |
2339 | break; |
2340 | case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: | |
ee6b1889 | 2341 | cmd->result |= SAM_STAT_CHECK_CONDITION; |
c349775e | 2342 | if (c2->error_data.data_present != |
ee6b1889 SC |
2343 | IOACCEL2_SENSE_DATA_PRESENT) { |
2344 | memset(cmd->sense_buffer, 0, | |
2345 | SCSI_SENSE_BUFFERSIZE); | |
c349775e | 2346 | break; |
ee6b1889 | 2347 | } |
c349775e ST |
2348 | /* copy the sense data */ |
2349 | data_len = c2->error_data.sense_data_len; | |
2350 | if (data_len > SCSI_SENSE_BUFFERSIZE) | |
2351 | data_len = SCSI_SENSE_BUFFERSIZE; | |
2352 | if (data_len > sizeof(c2->error_data.sense_data_buff)) | |
2353 | data_len = | |
2354 | sizeof(c2->error_data.sense_data_buff); | |
2355 | memcpy(cmd->sense_buffer, | |
2356 | c2->error_data.sense_data_buff, data_len); | |
a09c1441 | 2357 | retry = 1; |
c349775e ST |
2358 | break; |
2359 | case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: | |
a09c1441 | 2360 | retry = 1; |
c349775e ST |
2361 | break; |
2362 | case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: | |
a09c1441 | 2363 | retry = 1; |
c349775e ST |
2364 | break; |
2365 | case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: | |
4a8da22b | 2366 | retry = 1; |
c349775e ST |
2367 | break; |
2368 | case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: | |
a09c1441 | 2369 | retry = 1; |
c349775e ST |
2370 | break; |
2371 | default: | |
a09c1441 | 2372 | retry = 1; |
c349775e ST |
2373 | break; |
2374 | } | |
2375 | break; | |
2376 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
c40820d5 JH |
2377 | switch (c2->error_data.status) { |
2378 | case IOACCEL2_STATUS_SR_IO_ERROR: | |
2379 | case IOACCEL2_STATUS_SR_IO_ABORTED: | |
2380 | case IOACCEL2_STATUS_SR_OVERRUN: | |
2381 | retry = 1; | |
2382 | break; | |
2383 | case IOACCEL2_STATUS_SR_UNDERRUN: | |
2384 | cmd->result = (DID_OK << 16); /* host byte */ | |
2385 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
2386 | ioaccel2_resid = get_unaligned_le32( | |
2387 | &c2->error_data.resid_cnt[0]); | |
2388 | scsi_set_resid(cmd, ioaccel2_resid); | |
2389 | break; | |
2390 | case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE: | |
2391 | case IOACCEL2_STATUS_SR_INVALID_DEVICE: | |
2392 | case IOACCEL2_STATUS_SR_IOACCEL_DISABLED: | |
ba74fdc4 DB |
2393 | /* |
2394 | * Did an HBA disk disappear? We will eventually | |
2395 | * get a state change event from the controller but | |
2396 | * in the meantime, we need to tell the OS that the | |
2397 | * HBA disk is no longer there and stop I/O | |
2398 | * from going down. This allows the potential re-insert | |
2399 | * of the disk to get the same device node. | |
2400 | */ | |
2401 | if (dev->physical_device && dev->expose_device) { | |
2402 | cmd->result = DID_NO_CONNECT << 16; | |
2403 | dev->removed = 1; | |
2404 | h->drv_req_rescan = 1; | |
2405 | dev_warn(&h->pdev->dev, | |
2406 | "%s: device is gone!\n", __func__); | |
2407 | } else | |
2408 | /* | |
2409 | * Retry by sending down the RAID path. | |
2410 | * We will get an event from ctlr to | |
2411 | * trigger rescan regardless. | |
2412 | */ | |
2413 | retry = 1; | |
c40820d5 JH |
2414 | break; |
2415 | default: | |
2416 | retry = 1; | |
c40820d5 | 2417 | } |
c349775e ST |
2418 | break; |
2419 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
2420 | break; | |
2421 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
2422 | break; | |
2423 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
a09c1441 | 2424 | retry = 1; |
c349775e ST |
2425 | break; |
2426 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
c349775e ST |
2427 | break; |
2428 | default: | |
a09c1441 | 2429 | retry = 1; |
c349775e ST |
2430 | break; |
2431 | } | |
a09c1441 | 2432 | |
c5dfd106 DB |
2433 | if (dev->in_reset) |
2434 | retry = 0; | |
2435 | ||
a09c1441 | 2436 | return retry; /* retry on raid path? */ |
c349775e ST |
2437 | } |
2438 | ||
a58e7e53 WS |
2439 | static void hpsa_cmd_resolve_events(struct ctlr_info *h, |
2440 | struct CommandList *c) | |
2441 | { | |
c5dfd106 | 2442 | struct hpsa_scsi_dev_t *dev = c->device; |
d604f533 | 2443 | |
a58e7e53 | 2444 | /* |
08ec46f6 | 2445 | * Reset c->scsi_cmd here so that the reset handler will know |
d604f533 | 2446 | * this command has completed. Then, check to see if the handler is |
a58e7e53 WS |
2447 | * waiting for this command, and, if so, wake it. |
2448 | */ | |
2449 | c->scsi_cmd = SCSI_CMD_IDLE; | |
d604f533 | 2450 | mb(); /* Declare command idle before checking for pending events. */ |
c5dfd106 DB |
2451 | if (dev) { |
2452 | atomic_dec(&dev->commands_outstanding); | |
2453 | if (dev->in_reset && | |
2454 | atomic_read(&dev->commands_outstanding) <= 0) | |
2455 | wake_up_all(&h->event_sync_wait_queue); | |
d604f533 | 2456 | } |
a58e7e53 WS |
2457 | } |
2458 | ||
73153fe5 WS |
2459 | static void hpsa_cmd_resolve_and_free(struct ctlr_info *h, |
2460 | struct CommandList *c) | |
2461 | { | |
2462 | hpsa_cmd_resolve_events(h, c); | |
2463 | cmd_tagged_free(h, c); | |
2464 | } | |
2465 | ||
8a0ff92c WS |
2466 | static void hpsa_cmd_free_and_done(struct ctlr_info *h, |
2467 | struct CommandList *c, struct scsi_cmnd *cmd) | |
2468 | { | |
73153fe5 | 2469 | hpsa_cmd_resolve_and_free(h, c); |
d49c2077 DB |
2470 | if (cmd && cmd->scsi_done) |
2471 | cmd->scsi_done(cmd); | |
8a0ff92c WS |
2472 | } |
2473 | ||
2474 | static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c) | |
2475 | { | |
2476 | INIT_WORK(&c->work, hpsa_command_resubmit_worker); | |
2477 | queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); | |
2478 | } | |
2479 | ||
c349775e ST |
2480 | static void process_ioaccel2_completion(struct ctlr_info *h, |
2481 | struct CommandList *c, struct scsi_cmnd *cmd, | |
2482 | struct hpsa_scsi_dev_t *dev) | |
2483 | { | |
2484 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
2485 | ||
2486 | /* check for good status */ | |
2487 | if (likely(c2->error_data.serv_response == 0 && | |
eeebce18 DB |
2488 | c2->error_data.status == 0)) { |
2489 | cmd->result = 0; | |
8a0ff92c | 2490 | return hpsa_cmd_free_and_done(h, c, cmd); |
eeebce18 | 2491 | } |
c349775e | 2492 | |
8a0ff92c WS |
2493 | /* |
2494 | * Any RAID offload error results in retry which will use | |
b2582a65 | 2495 | * the normal I/O path so the controller can handle whatever is |
c349775e ST |
2496 | * wrong. |
2497 | */ | |
f3f01730 | 2498 | if (is_logical_device(dev) && |
c349775e ST |
2499 | c2->error_data.serv_response == |
2500 | IOACCEL2_SERV_RESPONSE_FAILURE) { | |
080ef1cc | 2501 | if (c2->error_data.status == |
064d1b1d | 2502 | IOACCEL2_STATUS_SR_IOACCEL_DISABLED) { |
080ef1cc | 2503 | dev->offload_enabled = 0; |
064d1b1d DB |
2504 | dev->offload_to_be_enabled = 0; |
2505 | } | |
8a0ff92c | 2506 | |
c5dfd106 DB |
2507 | if (dev->in_reset) { |
2508 | cmd->result = DID_RESET << 16; | |
2509 | return hpsa_cmd_free_and_done(h, c, cmd); | |
2510 | } | |
2511 | ||
8a0ff92c | 2512 | return hpsa_retry_cmd(h, c); |
a09c1441 | 2513 | } |
080ef1cc | 2514 | |
ba74fdc4 | 2515 | if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev)) |
8a0ff92c | 2516 | return hpsa_retry_cmd(h, c); |
080ef1cc | 2517 | |
8a0ff92c | 2518 | return hpsa_cmd_free_and_done(h, c, cmd); |
c349775e ST |
2519 | } |
2520 | ||
9437ac43 SC |
2521 | /* Returns 0 on success, < 0 otherwise. */ |
2522 | static int hpsa_evaluate_tmf_status(struct ctlr_info *h, | |
2523 | struct CommandList *cp) | |
2524 | { | |
2525 | u8 tmf_status = cp->err_info->ScsiStatus; | |
2526 | ||
2527 | switch (tmf_status) { | |
2528 | case CISS_TMF_COMPLETE: | |
2529 | /* | |
2530 | * CISS_TMF_COMPLETE never happens, instead, | |
2531 | * ei->CommandStatus == 0 for this case. | |
2532 | */ | |
2533 | case CISS_TMF_SUCCESS: | |
2534 | return 0; | |
2535 | case CISS_TMF_INVALID_FRAME: | |
2536 | case CISS_TMF_NOT_SUPPORTED: | |
2537 | case CISS_TMF_FAILED: | |
2538 | case CISS_TMF_WRONG_LUN: | |
2539 | case CISS_TMF_OVERLAPPED_TAG: | |
2540 | break; | |
2541 | default: | |
2542 | dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n", | |
2543 | tmf_status); | |
2544 | break; | |
2545 | } | |
2546 | return -tmf_status; | |
2547 | } | |
2548 | ||
1fb011fb | 2549 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
2550 | { |
2551 | struct scsi_cmnd *cmd; | |
2552 | struct ctlr_info *h; | |
2553 | struct ErrorInfo *ei; | |
283b4a9b | 2554 | struct hpsa_scsi_dev_t *dev; |
d9a729f3 | 2555 | struct io_accel2_cmd *c2; |
edd16368 | 2556 | |
9437ac43 SC |
2557 | u8 sense_key; |
2558 | u8 asc; /* additional sense code */ | |
2559 | u8 ascq; /* additional sense code qualifier */ | |
db111e18 | 2560 | unsigned long sense_data_size; |
edd16368 SC |
2561 | |
2562 | ei = cp->err_info; | |
7fa3030c | 2563 | cmd = cp->scsi_cmd; |
edd16368 | 2564 | h = cp->h; |
d49c2077 DB |
2565 | |
2566 | if (!cmd->device) { | |
2567 | cmd->result = DID_NO_CONNECT << 16; | |
2568 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
2569 | } | |
2570 | ||
283b4a9b | 2571 | dev = cmd->device->hostdata; |
45e596cd DB |
2572 | if (!dev) { |
2573 | cmd->result = DID_NO_CONNECT << 16; | |
2574 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
2575 | } | |
d9a729f3 | 2576 | c2 = &h->ioaccel2_cmd_pool[cp->cmdindex]; |
edd16368 SC |
2577 | |
2578 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c | 2579 | if ((cp->cmd_type == CMD_SCSI) && |
2b08b3e9 | 2580 | (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) |
33a2ffce | 2581 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 | 2582 | |
d9a729f3 WS |
2583 | if ((cp->cmd_type == CMD_IOACCEL2) && |
2584 | (c2->sg[0].chain_indicator == IOACCEL2_CHAIN)) | |
2585 | hpsa_unmap_ioaccel2_sg_chain_block(h, c2); | |
2586 | ||
edd16368 SC |
2587 | cmd->result = (DID_OK << 16); /* host byte */ |
2588 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
c349775e | 2589 | |
9e33f0d5 DB |
2590 | /* SCSI command has already been cleaned up in SML */ |
2591 | if (dev->was_removed) { | |
2592 | hpsa_cmd_resolve_and_free(h, cp); | |
2593 | return; | |
2594 | } | |
2595 | ||
d49c2077 DB |
2596 | if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) { |
2597 | if (dev->physical_device && dev->expose_device && | |
2598 | dev->removed) { | |
2599 | cmd->result = DID_NO_CONNECT << 16; | |
2600 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
2601 | } | |
2602 | if (likely(cp->phys_disk != NULL)) | |
2603 | atomic_dec(&cp->phys_disk->ioaccel_cmds_out); | |
2604 | } | |
03383736 | 2605 | |
25163bd5 WS |
2606 | /* |
2607 | * We check for lockup status here as it may be set for | |
2608 | * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by | |
2609 | * fail_all_oustanding_cmds() | |
2610 | */ | |
2611 | if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) { | |
2612 | /* DID_NO_CONNECT will prevent a retry */ | |
2613 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 2614 | return hpsa_cmd_free_and_done(h, cp, cmd); |
25163bd5 WS |
2615 | } |
2616 | ||
c349775e ST |
2617 | if (cp->cmd_type == CMD_IOACCEL2) |
2618 | return process_ioaccel2_completion(h, cp, cmd, dev); | |
2619 | ||
6aa4c361 | 2620 | scsi_set_resid(cmd, ei->ResidualCnt); |
8a0ff92c WS |
2621 | if (ei->CommandStatus == 0) |
2622 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
6aa4c361 | 2623 | |
e1f7de0c MG |
2624 | /* For I/O accelerator commands, copy over some fields to the normal |
2625 | * CISS header used below for error handling. | |
2626 | */ | |
2627 | if (cp->cmd_type == CMD_IOACCEL1) { | |
2628 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
2b08b3e9 DB |
2629 | cp->Header.SGList = scsi_sg_count(cmd); |
2630 | cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); | |
2631 | cp->Request.CDBLen = le16_to_cpu(c->io_flags) & | |
2632 | IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
50a0decf | 2633 | cp->Header.tag = c->tag; |
e1f7de0c MG |
2634 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); |
2635 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
283b4a9b SC |
2636 | |
2637 | /* Any RAID offload error results in retry which will use | |
2638 | * the normal I/O path so the controller can handle whatever's | |
2639 | * wrong. | |
2640 | */ | |
f3f01730 | 2641 | if (is_logical_device(dev)) { |
283b4a9b SC |
2642 | if (ei->CommandStatus == CMD_IOACCEL_DISABLED) |
2643 | dev->offload_enabled = 0; | |
d604f533 | 2644 | return hpsa_retry_cmd(h, cp); |
283b4a9b | 2645 | } |
e1f7de0c MG |
2646 | } |
2647 | ||
edd16368 SC |
2648 | /* an error has occurred */ |
2649 | switch (ei->CommandStatus) { | |
2650 | ||
2651 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2652 | cmd->result |= ei->ScsiStatus; |
2653 | /* copy the sense data */ | |
2654 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) | |
2655 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
2656 | else | |
2657 | sense_data_size = sizeof(ei->SenseInfo); | |
2658 | if (ei->SenseLen < sense_data_size) | |
2659 | sense_data_size = ei->SenseLen; | |
2660 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
2661 | if (ei->ScsiStatus) | |
2662 | decode_sense_data(ei->SenseInfo, sense_data_size, | |
2663 | &sense_key, &asc, &ascq); | |
edd16368 | 2664 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { |
49ea45cb DB |
2665 | switch (sense_key) { |
2666 | case ABORTED_COMMAND: | |
2e311fba | 2667 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 | 2668 | break; |
49ea45cb DB |
2669 | case UNIT_ATTENTION: |
2670 | if (asc == 0x3F && ascq == 0x0E) | |
2671 | h->drv_req_rescan = 1; | |
2672 | break; | |
2673 | case ILLEGAL_REQUEST: | |
2674 | if (asc == 0x25 && ascq == 0x00) { | |
2675 | dev->removed = 1; | |
2676 | cmd->result = DID_NO_CONNECT << 16; | |
2677 | } | |
2678 | break; | |
1d3b3609 | 2679 | } |
edd16368 SC |
2680 | break; |
2681 | } | |
edd16368 SC |
2682 | /* Problem was not a check condition |
2683 | * Pass it up to the upper layers... | |
2684 | */ | |
2685 | if (ei->ScsiStatus) { | |
2686 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
2687 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
2688 | "Returning result: 0x%x\n", | |
2689 | cp, ei->ScsiStatus, | |
2690 | sense_key, asc, ascq, | |
2691 | cmd->result); | |
2692 | } else { /* scsi status is zero??? How??? */ | |
2693 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
2694 | "Returning no connection.\n", cp), | |
2695 | ||
2696 | /* Ordinarily, this case should never happen, | |
2697 | * but there is a bug in some released firmware | |
2698 | * revisions that allows it to happen if, for | |
2699 | * example, a 4100 backplane loses power and | |
2700 | * the tape drive is in it. We assume that | |
2701 | * it's a fatal error of some kind because we | |
2702 | * can't show that it wasn't. We will make it | |
2703 | * look like selection timeout since that is | |
2704 | * the most common reason for this to occur, | |
2705 | * and it's severe enough. | |
2706 | */ | |
2707 | ||
2708 | cmd->result = DID_NO_CONNECT << 16; | |
2709 | } | |
2710 | break; | |
2711 | ||
2712 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
2713 | break; | |
2714 | case CMD_DATA_OVERRUN: | |
f42e81e1 SC |
2715 | dev_warn(&h->pdev->dev, |
2716 | "CDB %16phN data overrun\n", cp->Request.CDB); | |
edd16368 SC |
2717 | break; |
2718 | case CMD_INVALID: { | |
2719 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
2720 | print_cmd(cp); */ | |
2721 | /* We get CMD_INVALID if you address a non-existent device | |
2722 | * instead of a selection timeout (no response). You will | |
2723 | * see this if you yank out a drive, then try to access it. | |
2724 | * This is kind of a shame because it means that any other | |
2725 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
2726 | * missing target. */ | |
2727 | cmd->result = DID_NO_CONNECT << 16; | |
2728 | } | |
2729 | break; | |
2730 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 2731 | cmd->result = DID_ERROR << 16; |
f42e81e1 SC |
2732 | dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n", |
2733 | cp->Request.CDB); | |
edd16368 SC |
2734 | break; |
2735 | case CMD_HARDWARE_ERR: | |
2736 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2737 | dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n", |
2738 | cp->Request.CDB); | |
edd16368 SC |
2739 | break; |
2740 | case CMD_CONNECTION_LOST: | |
2741 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2742 | dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n", |
2743 | cp->Request.CDB); | |
edd16368 SC |
2744 | break; |
2745 | case CMD_ABORTED: | |
08ec46f6 DB |
2746 | cmd->result = DID_ABORT << 16; |
2747 | break; | |
edd16368 SC |
2748 | case CMD_ABORT_FAILED: |
2749 | cmd->result = DID_ERROR << 16; | |
f42e81e1 SC |
2750 | dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n", |
2751 | cp->Request.CDB); | |
edd16368 SC |
2752 | break; |
2753 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 | 2754 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
f42e81e1 SC |
2755 | dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n", |
2756 | cp->Request.CDB); | |
edd16368 SC |
2757 | break; |
2758 | case CMD_TIMEOUT: | |
2759 | cmd->result = DID_TIME_OUT << 16; | |
f42e81e1 SC |
2760 | dev_warn(&h->pdev->dev, "CDB %16phN timed out\n", |
2761 | cp->Request.CDB); | |
edd16368 | 2762 | break; |
1d5e2ed0 SC |
2763 | case CMD_UNABORTABLE: |
2764 | cmd->result = DID_ERROR << 16; | |
2765 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
2766 | break; | |
9437ac43 SC |
2767 | case CMD_TMF_STATUS: |
2768 | if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */ | |
2769 | cmd->result = DID_ERROR << 16; | |
2770 | break; | |
283b4a9b SC |
2771 | case CMD_IOACCEL_DISABLED: |
2772 | /* This only handles the direct pass-through case since RAID | |
2773 | * offload is handled above. Just attempt a retry. | |
2774 | */ | |
2775 | cmd->result = DID_SOFT_ERROR << 16; | |
2776 | dev_warn(&h->pdev->dev, | |
2777 | "cp %p had HP SSD Smart Path error\n", cp); | |
2778 | break; | |
edd16368 SC |
2779 | default: |
2780 | cmd->result = DID_ERROR << 16; | |
2781 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
2782 | cp, ei->CommandStatus); | |
2783 | } | |
8a0ff92c WS |
2784 | |
2785 | return hpsa_cmd_free_and_done(h, cp, cmd); | |
edd16368 SC |
2786 | } |
2787 | ||
8bc8f47e CH |
2788 | static void hpsa_pci_unmap(struct pci_dev *pdev, struct CommandList *c, |
2789 | int sg_used, enum dma_data_direction data_direction) | |
edd16368 SC |
2790 | { |
2791 | int i; | |
edd16368 | 2792 | |
50a0decf | 2793 | for (i = 0; i < sg_used; i++) |
8bc8f47e | 2794 | dma_unmap_single(&pdev->dev, le64_to_cpu(c->SG[i].Addr), |
50a0decf SC |
2795 | le32_to_cpu(c->SG[i].Len), |
2796 | data_direction); | |
edd16368 SC |
2797 | } |
2798 | ||
a2dac136 | 2799 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
2800 | struct CommandList *cp, |
2801 | unsigned char *buf, | |
2802 | size_t buflen, | |
8bc8f47e | 2803 | enum dma_data_direction data_direction) |
edd16368 | 2804 | { |
01a02ffc | 2805 | u64 addr64; |
edd16368 | 2806 | |
8bc8f47e | 2807 | if (buflen == 0 || data_direction == DMA_NONE) { |
edd16368 | 2808 | cp->Header.SGList = 0; |
50a0decf | 2809 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2810 | return 0; |
edd16368 SC |
2811 | } |
2812 | ||
8bc8f47e | 2813 | addr64 = dma_map_single(&pdev->dev, buf, buflen, data_direction); |
eceaae18 | 2814 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 2815 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 | 2816 | cp->Header.SGList = 0; |
50a0decf | 2817 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 2818 | return -1; |
eceaae18 | 2819 | } |
50a0decf SC |
2820 | cp->SG[0].Addr = cpu_to_le64(addr64); |
2821 | cp->SG[0].Len = cpu_to_le32(buflen); | |
2822 | cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ | |
2823 | cp->Header.SGList = 1; /* no. SGs contig in this cmd */ | |
2824 | cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ | |
a2dac136 | 2825 | return 0; |
edd16368 SC |
2826 | } |
2827 | ||
25163bd5 WS |
2828 | #define NO_TIMEOUT ((unsigned long) -1) |
2829 | #define DEFAULT_TIMEOUT 30000 /* milliseconds */ | |
2830 | static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
2831 | struct CommandList *c, int reply_queue, unsigned long timeout_msecs) | |
edd16368 SC |
2832 | { |
2833 | DECLARE_COMPLETION_ONSTACK(wait); | |
2834 | ||
2835 | c->waiting = &wait; | |
25163bd5 WS |
2836 | __enqueue_cmd_and_start_io(h, c, reply_queue); |
2837 | if (timeout_msecs == NO_TIMEOUT) { | |
2838 | /* TODO: get rid of this no-timeout thing */ | |
2839 | wait_for_completion_io(&wait); | |
2840 | return IO_OK; | |
2841 | } | |
2842 | if (!wait_for_completion_io_timeout(&wait, | |
2843 | msecs_to_jiffies(timeout_msecs))) { | |
2844 | dev_warn(&h->pdev->dev, "Command timed out.\n"); | |
2845 | return -ETIMEDOUT; | |
2846 | } | |
2847 | return IO_OK; | |
2848 | } | |
2849 | ||
2850 | static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c, | |
2851 | int reply_queue, unsigned long timeout_msecs) | |
2852 | { | |
2853 | if (unlikely(lockup_detected(h))) { | |
2854 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; | |
2855 | return IO_OK; | |
2856 | } | |
2857 | return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs); | |
edd16368 SC |
2858 | } |
2859 | ||
094963da SC |
2860 | static u32 lockup_detected(struct ctlr_info *h) |
2861 | { | |
2862 | int cpu; | |
2863 | u32 rc, *lockup_detected; | |
2864 | ||
2865 | cpu = get_cpu(); | |
2866 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
2867 | rc = *lockup_detected; | |
2868 | put_cpu(); | |
2869 | return rc; | |
2870 | } | |
2871 | ||
9c2fc160 | 2872 | #define MAX_DRIVER_CMD_RETRIES 25 |
25163bd5 | 2873 | static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
8bc8f47e CH |
2874 | struct CommandList *c, enum dma_data_direction data_direction, |
2875 | unsigned long timeout_msecs) | |
edd16368 | 2876 | { |
9c2fc160 | 2877 | int backoff_time = 10, retry_count = 0; |
25163bd5 | 2878 | int rc; |
edd16368 SC |
2879 | |
2880 | do { | |
7630abd0 | 2881 | memset(c->err_info, 0, sizeof(*c->err_info)); |
25163bd5 WS |
2882 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
2883 | timeout_msecs); | |
2884 | if (rc) | |
2885 | break; | |
edd16368 | 2886 | retry_count++; |
9c2fc160 SC |
2887 | if (retry_count > 3) { |
2888 | msleep(backoff_time); | |
2889 | if (backoff_time < 1000) | |
2890 | backoff_time *= 2; | |
2891 | } | |
852af20a | 2892 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
2893 | check_for_busy(h, c)) && |
2894 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 | 2895 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
25163bd5 WS |
2896 | if (retry_count > MAX_DRIVER_CMD_RETRIES) |
2897 | rc = -EIO; | |
2898 | return rc; | |
edd16368 SC |
2899 | } |
2900 | ||
d1e8beac SC |
2901 | static void hpsa_print_cmd(struct ctlr_info *h, char *txt, |
2902 | struct CommandList *c) | |
edd16368 | 2903 | { |
d1e8beac SC |
2904 | const u8 *cdb = c->Request.CDB; |
2905 | const u8 *lun = c->Header.LUN.LunAddrBytes; | |
2906 | ||
609a70df RV |
2907 | dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n", |
2908 | txt, lun, cdb); | |
d1e8beac SC |
2909 | } |
2910 | ||
2911 | static void hpsa_scsi_interpret_error(struct ctlr_info *h, | |
2912 | struct CommandList *cp) | |
2913 | { | |
2914 | const struct ErrorInfo *ei = cp->err_info; | |
edd16368 | 2915 | struct device *d = &cp->h->pdev->dev; |
9437ac43 SC |
2916 | u8 sense_key, asc, ascq; |
2917 | int sense_len; | |
edd16368 | 2918 | |
edd16368 SC |
2919 | switch (ei->CommandStatus) { |
2920 | case CMD_TARGET_STATUS: | |
9437ac43 SC |
2921 | if (ei->SenseLen > sizeof(ei->SenseInfo)) |
2922 | sense_len = sizeof(ei->SenseInfo); | |
2923 | else | |
2924 | sense_len = ei->SenseLen; | |
2925 | decode_sense_data(ei->SenseInfo, sense_len, | |
2926 | &sense_key, &asc, &ascq); | |
d1e8beac SC |
2927 | hpsa_print_cmd(h, "SCSI status", cp); |
2928 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) | |
9437ac43 SC |
2929 | dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n", |
2930 | sense_key, asc, ascq); | |
d1e8beac | 2931 | else |
9437ac43 | 2932 | dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus); |
edd16368 SC |
2933 | if (ei->ScsiStatus == 0) |
2934 | dev_warn(d, "SCSI status is abnormally zero. " | |
2935 | "(probably indicates selection timeout " | |
2936 | "reported incorrectly due to a known " | |
2937 | "firmware bug, circa July, 2001.)\n"); | |
2938 | break; | |
2939 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
edd16368 SC |
2940 | break; |
2941 | case CMD_DATA_OVERRUN: | |
d1e8beac | 2942 | hpsa_print_cmd(h, "overrun condition", cp); |
edd16368 SC |
2943 | break; |
2944 | case CMD_INVALID: { | |
2945 | /* controller unfortunately reports SCSI passthru's | |
2946 | * to non-existent targets as invalid commands. | |
2947 | */ | |
d1e8beac SC |
2948 | hpsa_print_cmd(h, "invalid command", cp); |
2949 | dev_warn(d, "probably means device no longer present\n"); | |
edd16368 SC |
2950 | } |
2951 | break; | |
2952 | case CMD_PROTOCOL_ERR: | |
d1e8beac | 2953 | hpsa_print_cmd(h, "protocol error", cp); |
edd16368 SC |
2954 | break; |
2955 | case CMD_HARDWARE_ERR: | |
d1e8beac | 2956 | hpsa_print_cmd(h, "hardware error", cp); |
edd16368 SC |
2957 | break; |
2958 | case CMD_CONNECTION_LOST: | |
d1e8beac | 2959 | hpsa_print_cmd(h, "connection lost", cp); |
edd16368 SC |
2960 | break; |
2961 | case CMD_ABORTED: | |
d1e8beac | 2962 | hpsa_print_cmd(h, "aborted", cp); |
edd16368 SC |
2963 | break; |
2964 | case CMD_ABORT_FAILED: | |
d1e8beac | 2965 | hpsa_print_cmd(h, "abort failed", cp); |
edd16368 SC |
2966 | break; |
2967 | case CMD_UNSOLICITED_ABORT: | |
d1e8beac | 2968 | hpsa_print_cmd(h, "unsolicited abort", cp); |
edd16368 SC |
2969 | break; |
2970 | case CMD_TIMEOUT: | |
d1e8beac | 2971 | hpsa_print_cmd(h, "timed out", cp); |
edd16368 | 2972 | break; |
1d5e2ed0 | 2973 | case CMD_UNABORTABLE: |
d1e8beac | 2974 | hpsa_print_cmd(h, "unabortable", cp); |
1d5e2ed0 | 2975 | break; |
25163bd5 WS |
2976 | case CMD_CTLR_LOCKUP: |
2977 | hpsa_print_cmd(h, "controller lockup detected", cp); | |
2978 | break; | |
edd16368 | 2979 | default: |
d1e8beac SC |
2980 | hpsa_print_cmd(h, "unknown status", cp); |
2981 | dev_warn(d, "Unknown command status %x\n", | |
edd16368 SC |
2982 | ei->CommandStatus); |
2983 | } | |
2984 | } | |
2985 | ||
0a7c3bb8 DB |
2986 | static int hpsa_do_receive_diagnostic(struct ctlr_info *h, u8 *scsi3addr, |
2987 | u8 page, u8 *buf, size_t bufsize) | |
2988 | { | |
2989 | int rc = IO_OK; | |
2990 | struct CommandList *c; | |
2991 | struct ErrorInfo *ei; | |
2992 | ||
2993 | c = cmd_alloc(h); | |
2994 | if (fill_cmd(c, RECEIVE_DIAGNOSTIC, h, buf, bufsize, | |
2995 | page, scsi3addr, TYPE_CMD)) { | |
2996 | rc = -1; | |
2997 | goto out; | |
2998 | } | |
8bc8f47e CH |
2999 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3000 | NO_TIMEOUT); | |
0a7c3bb8 DB |
3001 | if (rc) |
3002 | goto out; | |
3003 | ei = c->err_info; | |
3004 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3005 | hpsa_scsi_interpret_error(h, c); | |
3006 | rc = -1; | |
3007 | } | |
3008 | out: | |
3009 | cmd_free(h, c); | |
3010 | return rc; | |
3011 | } | |
3012 | ||
3013 | static u64 hpsa_get_enclosure_logical_identifier(struct ctlr_info *h, | |
3014 | u8 *scsi3addr) | |
3015 | { | |
3016 | u8 *buf; | |
3017 | u64 sa = 0; | |
3018 | int rc = 0; | |
3019 | ||
3020 | buf = kzalloc(1024, GFP_KERNEL); | |
3021 | if (!buf) | |
3022 | return 0; | |
3023 | ||
3024 | rc = hpsa_do_receive_diagnostic(h, scsi3addr, RECEIVE_DIAGNOSTIC, | |
3025 | buf, 1024); | |
3026 | ||
3027 | if (rc) | |
3028 | goto out; | |
3029 | ||
3030 | sa = get_unaligned_be64(buf+12); | |
3031 | ||
3032 | out: | |
3033 | kfree(buf); | |
3034 | return sa; | |
3035 | } | |
3036 | ||
edd16368 | 3037 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, |
b7bb24eb | 3038 | u16 page, unsigned char *buf, |
edd16368 SC |
3039 | unsigned char bufsize) |
3040 | { | |
3041 | int rc = IO_OK; | |
3042 | struct CommandList *c; | |
3043 | struct ErrorInfo *ei; | |
3044 | ||
45fcb86e | 3045 | c = cmd_alloc(h); |
edd16368 | 3046 | |
a2dac136 SC |
3047 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
3048 | page, scsi3addr, TYPE_CMD)) { | |
3049 | rc = -1; | |
3050 | goto out; | |
3051 | } | |
8bc8f47e CH |
3052 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3053 | NO_TIMEOUT); | |
25163bd5 WS |
3054 | if (rc) |
3055 | goto out; | |
edd16368 SC |
3056 | ei = c->err_info; |
3057 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3058 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
3059 | rc = -1; |
3060 | } | |
a2dac136 | 3061 | out: |
45fcb86e | 3062 | cmd_free(h, c); |
edd16368 SC |
3063 | return rc; |
3064 | } | |
3065 | ||
c5dfd106 | 3066 | static int hpsa_send_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, |
25163bd5 | 3067 | u8 reset_type, int reply_queue) |
edd16368 SC |
3068 | { |
3069 | int rc = IO_OK; | |
3070 | struct CommandList *c; | |
3071 | struct ErrorInfo *ei; | |
3072 | ||
45fcb86e | 3073 | c = cmd_alloc(h); |
c5dfd106 | 3074 | c->device = dev; |
edd16368 | 3075 | |
a2dac136 | 3076 | /* fill_cmd can't fail here, no data buffer to map. */ |
c5dfd106 | 3077 | (void) fill_cmd(c, reset_type, h, NULL, 0, 0, dev->scsi3addr, TYPE_MSG); |
2ef28849 | 3078 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); |
25163bd5 WS |
3079 | if (rc) { |
3080 | dev_warn(&h->pdev->dev, "Failed to send reset command\n"); | |
3081 | goto out; | |
3082 | } | |
edd16368 SC |
3083 | /* no unmap needed here because no data xfer. */ |
3084 | ||
3085 | ei = c->err_info; | |
3086 | if (ei->CommandStatus != 0) { | |
d1e8beac | 3087 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
3088 | rc = -1; |
3089 | } | |
25163bd5 | 3090 | out: |
45fcb86e | 3091 | cmd_free(h, c); |
edd16368 SC |
3092 | return rc; |
3093 | } | |
3094 | ||
d604f533 WS |
3095 | static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c, |
3096 | struct hpsa_scsi_dev_t *dev, | |
3097 | unsigned char *scsi3addr) | |
3098 | { | |
3099 | int i; | |
3100 | bool match = false; | |
3101 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
3102 | struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2; | |
3103 | ||
3104 | if (hpsa_is_cmd_idle(c)) | |
3105 | return false; | |
3106 | ||
3107 | switch (c->cmd_type) { | |
3108 | case CMD_SCSI: | |
3109 | case CMD_IOCTL_PEND: | |
3110 | match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes, | |
3111 | sizeof(c->Header.LUN.LunAddrBytes)); | |
3112 | break; | |
3113 | ||
3114 | case CMD_IOACCEL1: | |
3115 | case CMD_IOACCEL2: | |
3116 | if (c->phys_disk == dev) { | |
3117 | /* HBA mode match */ | |
3118 | match = true; | |
3119 | } else { | |
3120 | /* Possible RAID mode -- check each phys dev. */ | |
3121 | /* FIXME: Do we need to take out a lock here? If | |
3122 | * so, we could just call hpsa_get_pdisk_of_ioaccel2() | |
3123 | * instead. */ | |
3124 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
3125 | /* FIXME: an alternate test might be | |
3126 | * | |
3127 | * match = dev->phys_disk[i]->ioaccel_handle | |
3128 | * == c2->scsi_nexus; */ | |
3129 | match = dev->phys_disk[i] == c->phys_disk; | |
3130 | } | |
3131 | } | |
3132 | break; | |
3133 | ||
3134 | case IOACCEL2_TMF: | |
3135 | for (i = 0; i < dev->nphysical_disks && !match; i++) { | |
3136 | match = dev->phys_disk[i]->ioaccel_handle == | |
3137 | le32_to_cpu(ac->it_nexus); | |
3138 | } | |
3139 | break; | |
3140 | ||
3141 | case 0: /* The command is in the middle of being initialized. */ | |
3142 | match = false; | |
3143 | break; | |
3144 | ||
3145 | default: | |
3146 | dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n", | |
3147 | c->cmd_type); | |
3148 | BUG(); | |
3149 | } | |
3150 | ||
3151 | return match; | |
3152 | } | |
3153 | ||
3154 | static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev, | |
c5dfd106 | 3155 | u8 reset_type, int reply_queue) |
d604f533 | 3156 | { |
d604f533 WS |
3157 | int rc = 0; |
3158 | ||
3159 | /* We can really only handle one reset at a time */ | |
3160 | if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) { | |
3161 | dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n"); | |
3162 | return -EINTR; | |
3163 | } | |
3164 | ||
c5dfd106 DB |
3165 | rc = hpsa_send_reset(h, dev, reset_type, reply_queue); |
3166 | if (!rc) { | |
3167 | /* incremented by sending the reset request */ | |
3168 | atomic_dec(&dev->commands_outstanding); | |
d604f533 | 3169 | wait_event(h->event_sync_wait_queue, |
c5dfd106 | 3170 | atomic_read(&dev->commands_outstanding) <= 0 || |
d604f533 | 3171 | lockup_detected(h)); |
c5dfd106 | 3172 | } |
d604f533 WS |
3173 | |
3174 | if (unlikely(lockup_detected(h))) { | |
77678d3a DB |
3175 | dev_warn(&h->pdev->dev, |
3176 | "Controller lockup detected during reset wait\n"); | |
3177 | rc = -ENODEV; | |
3178 | } | |
d604f533 | 3179 | |
c5dfd106 DB |
3180 | if (!rc) |
3181 | rc = wait_for_device_to_become_ready(h, dev->scsi3addr, 0); | |
d604f533 WS |
3182 | |
3183 | mutex_unlock(&h->reset_mutex); | |
3184 | return rc; | |
3185 | } | |
3186 | ||
edd16368 SC |
3187 | static void hpsa_get_raid_level(struct ctlr_info *h, |
3188 | unsigned char *scsi3addr, unsigned char *raid_level) | |
3189 | { | |
3190 | int rc; | |
3191 | unsigned char *buf; | |
3192 | ||
3193 | *raid_level = RAID_UNKNOWN; | |
3194 | buf = kzalloc(64, GFP_KERNEL); | |
3195 | if (!buf) | |
3196 | return; | |
8383278d ST |
3197 | |
3198 | if (!hpsa_vpd_page_supported(h, scsi3addr, | |
3199 | HPSA_VPD_LV_DEVICE_GEOMETRY)) | |
3200 | goto exit; | |
3201 | ||
3202 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | | |
3203 | HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64); | |
3204 | ||
edd16368 SC |
3205 | if (rc == 0) |
3206 | *raid_level = buf[8]; | |
3207 | if (*raid_level > RAID_UNKNOWN) | |
3208 | *raid_level = RAID_UNKNOWN; | |
8383278d | 3209 | exit: |
edd16368 SC |
3210 | kfree(buf); |
3211 | return; | |
3212 | } | |
3213 | ||
283b4a9b SC |
3214 | #define HPSA_MAP_DEBUG |
3215 | #ifdef HPSA_MAP_DEBUG | |
3216 | static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, | |
3217 | struct raid_map_data *map_buff) | |
3218 | { | |
3219 | struct raid_map_disk_data *dd = &map_buff->data[0]; | |
3220 | int map, row, col; | |
3221 | u16 map_cnt, row_cnt, disks_per_row; | |
3222 | ||
3223 | if (rc != 0) | |
3224 | return; | |
3225 | ||
2ba8bfc8 SC |
3226 | /* Show details only if debugging has been activated. */ |
3227 | if (h->raid_offload_debug < 2) | |
3228 | return; | |
3229 | ||
283b4a9b SC |
3230 | dev_info(&h->pdev->dev, "structure_size = %u\n", |
3231 | le32_to_cpu(map_buff->structure_size)); | |
3232 | dev_info(&h->pdev->dev, "volume_blk_size = %u\n", | |
3233 | le32_to_cpu(map_buff->volume_blk_size)); | |
3234 | dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", | |
3235 | le64_to_cpu(map_buff->volume_blk_cnt)); | |
3236 | dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", | |
3237 | map_buff->phys_blk_shift); | |
3238 | dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", | |
3239 | map_buff->parity_rotation_shift); | |
3240 | dev_info(&h->pdev->dev, "strip_size = %u\n", | |
3241 | le16_to_cpu(map_buff->strip_size)); | |
3242 | dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", | |
3243 | le64_to_cpu(map_buff->disk_starting_blk)); | |
3244 | dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", | |
3245 | le64_to_cpu(map_buff->disk_blk_cnt)); | |
3246 | dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", | |
3247 | le16_to_cpu(map_buff->data_disks_per_row)); | |
3248 | dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", | |
3249 | le16_to_cpu(map_buff->metadata_disks_per_row)); | |
3250 | dev_info(&h->pdev->dev, "row_cnt = %u\n", | |
3251 | le16_to_cpu(map_buff->row_cnt)); | |
3252 | dev_info(&h->pdev->dev, "layout_map_count = %u\n", | |
3253 | le16_to_cpu(map_buff->layout_map_count)); | |
2b08b3e9 | 3254 | dev_info(&h->pdev->dev, "flags = 0x%x\n", |
dd0e19f3 | 3255 | le16_to_cpu(map_buff->flags)); |
ba82d91b | 3256 | dev_info(&h->pdev->dev, "encryption = %s\n", |
2b08b3e9 DB |
3257 | le16_to_cpu(map_buff->flags) & |
3258 | RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); | |
dd0e19f3 ST |
3259 | dev_info(&h->pdev->dev, "dekindex = %u\n", |
3260 | le16_to_cpu(map_buff->dekindex)); | |
283b4a9b SC |
3261 | map_cnt = le16_to_cpu(map_buff->layout_map_count); |
3262 | for (map = 0; map < map_cnt; map++) { | |
3263 | dev_info(&h->pdev->dev, "Map%u:\n", map); | |
3264 | row_cnt = le16_to_cpu(map_buff->row_cnt); | |
3265 | for (row = 0; row < row_cnt; row++) { | |
3266 | dev_info(&h->pdev->dev, " Row%u:\n", row); | |
3267 | disks_per_row = | |
3268 | le16_to_cpu(map_buff->data_disks_per_row); | |
3269 | for (col = 0; col < disks_per_row; col++, dd++) | |
3270 | dev_info(&h->pdev->dev, | |
3271 | " D%02u: h=0x%04x xor=%u,%u\n", | |
3272 | col, dd->ioaccel_handle, | |
3273 | dd->xor_mult[0], dd->xor_mult[1]); | |
3274 | disks_per_row = | |
3275 | le16_to_cpu(map_buff->metadata_disks_per_row); | |
3276 | for (col = 0; col < disks_per_row; col++, dd++) | |
3277 | dev_info(&h->pdev->dev, | |
3278 | " M%02u: h=0x%04x xor=%u,%u\n", | |
3279 | col, dd->ioaccel_handle, | |
3280 | dd->xor_mult[0], dd->xor_mult[1]); | |
3281 | } | |
3282 | } | |
3283 | } | |
3284 | #else | |
3285 | static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, | |
3286 | __attribute__((unused)) int rc, | |
3287 | __attribute__((unused)) struct raid_map_data *map_buff) | |
3288 | { | |
3289 | } | |
3290 | #endif | |
3291 | ||
3292 | static int hpsa_get_raid_map(struct ctlr_info *h, | |
3293 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3294 | { | |
3295 | int rc = 0; | |
3296 | struct CommandList *c; | |
3297 | struct ErrorInfo *ei; | |
3298 | ||
45fcb86e | 3299 | c = cmd_alloc(h); |
bf43caf3 | 3300 | |
283b4a9b SC |
3301 | if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, |
3302 | sizeof(this_device->raid_map), 0, | |
3303 | scsi3addr, TYPE_CMD)) { | |
2dd02d74 RE |
3304 | dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n"); |
3305 | cmd_free(h, c); | |
3306 | return -1; | |
283b4a9b | 3307 | } |
8bc8f47e CH |
3308 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3309 | NO_TIMEOUT); | |
25163bd5 WS |
3310 | if (rc) |
3311 | goto out; | |
283b4a9b SC |
3312 | ei = c->err_info; |
3313 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3314 | hpsa_scsi_interpret_error(h, c); |
25163bd5 WS |
3315 | rc = -1; |
3316 | goto out; | |
283b4a9b | 3317 | } |
45fcb86e | 3318 | cmd_free(h, c); |
283b4a9b SC |
3319 | |
3320 | /* @todo in the future, dynamically allocate RAID map memory */ | |
3321 | if (le32_to_cpu(this_device->raid_map.structure_size) > | |
3322 | sizeof(this_device->raid_map)) { | |
3323 | dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); | |
3324 | rc = -1; | |
3325 | } | |
3326 | hpsa_debug_map_buff(h, rc, &this_device->raid_map); | |
3327 | return rc; | |
25163bd5 WS |
3328 | out: |
3329 | cmd_free(h, c); | |
3330 | return rc; | |
283b4a9b SC |
3331 | } |
3332 | ||
d04e62b9 KB |
3333 | static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h, |
3334 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3335 | struct bmic_sense_subsystem_info *buf, size_t bufsize) | |
3336 | { | |
3337 | int rc = IO_OK; | |
3338 | struct CommandList *c; | |
3339 | struct ErrorInfo *ei; | |
3340 | ||
3341 | c = cmd_alloc(h); | |
3342 | ||
3343 | rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize, | |
3344 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3345 | if (rc) | |
3346 | goto out; | |
3347 | ||
3348 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3349 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3350 | ||
8bc8f47e CH |
3351 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3352 | NO_TIMEOUT); | |
d04e62b9 KB |
3353 | if (rc) |
3354 | goto out; | |
3355 | ei = c->err_info; | |
3356 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3357 | hpsa_scsi_interpret_error(h, c); | |
3358 | rc = -1; | |
3359 | } | |
3360 | out: | |
3361 | cmd_free(h, c); | |
3362 | return rc; | |
3363 | } | |
3364 | ||
66749d0d ST |
3365 | static int hpsa_bmic_id_controller(struct ctlr_info *h, |
3366 | struct bmic_identify_controller *buf, size_t bufsize) | |
3367 | { | |
3368 | int rc = IO_OK; | |
3369 | struct CommandList *c; | |
3370 | struct ErrorInfo *ei; | |
3371 | ||
3372 | c = cmd_alloc(h); | |
3373 | ||
3374 | rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize, | |
3375 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3376 | if (rc) | |
3377 | goto out; | |
3378 | ||
8bc8f47e CH |
3379 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3380 | NO_TIMEOUT); | |
66749d0d ST |
3381 | if (rc) |
3382 | goto out; | |
3383 | ei = c->err_info; | |
3384 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3385 | hpsa_scsi_interpret_error(h, c); | |
3386 | rc = -1; | |
3387 | } | |
3388 | out: | |
3389 | cmd_free(h, c); | |
3390 | return rc; | |
3391 | } | |
3392 | ||
03383736 DB |
3393 | static int hpsa_bmic_id_physical_device(struct ctlr_info *h, |
3394 | unsigned char scsi3addr[], u16 bmic_device_index, | |
3395 | struct bmic_identify_physical_device *buf, size_t bufsize) | |
3396 | { | |
3397 | int rc = IO_OK; | |
3398 | struct CommandList *c; | |
3399 | struct ErrorInfo *ei; | |
3400 | ||
3401 | c = cmd_alloc(h); | |
3402 | rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, | |
3403 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3404 | if (rc) | |
3405 | goto out; | |
3406 | ||
3407 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
3408 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
3409 | ||
8bc8f47e | 3410 | hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3026ff9b | 3411 | NO_TIMEOUT); |
03383736 DB |
3412 | ei = c->err_info; |
3413 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3414 | hpsa_scsi_interpret_error(h, c); | |
3415 | rc = -1; | |
3416 | } | |
3417 | out: | |
3418 | cmd_free(h, c); | |
d04e62b9 | 3419 | |
03383736 DB |
3420 | return rc; |
3421 | } | |
3422 | ||
cca8f13b DB |
3423 | /* |
3424 | * get enclosure information | |
3425 | * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number | |
3426 | * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure | |
3427 | * Uses id_physical_device to determine the box_index. | |
3428 | */ | |
3429 | static void hpsa_get_enclosure_info(struct ctlr_info *h, | |
3430 | unsigned char *scsi3addr, | |
3431 | struct ReportExtendedLUNdata *rlep, int rle_index, | |
3432 | struct hpsa_scsi_dev_t *encl_dev) | |
3433 | { | |
3434 | int rc = -1; | |
3435 | struct CommandList *c = NULL; | |
3436 | struct ErrorInfo *ei = NULL; | |
3437 | struct bmic_sense_storage_box_params *bssbp = NULL; | |
3438 | struct bmic_identify_physical_device *id_phys = NULL; | |
3439 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; | |
3440 | u16 bmic_device_index = 0; | |
3441 | ||
01d0e789 | 3442 | encl_dev->eli = |
0a7c3bb8 DB |
3443 | hpsa_get_enclosure_logical_identifier(h, scsi3addr); |
3444 | ||
01d0e789 DB |
3445 | bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]); |
3446 | ||
5ac517b8 DB |
3447 | if (encl_dev->target == -1 || encl_dev->lun == -1) { |
3448 | rc = IO_OK; | |
3449 | goto out; | |
3450 | } | |
3451 | ||
17a9e54a DB |
3452 | if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) { |
3453 | rc = IO_OK; | |
cca8f13b | 3454 | goto out; |
17a9e54a | 3455 | } |
cca8f13b DB |
3456 | |
3457 | bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL); | |
3458 | if (!bssbp) | |
3459 | goto out; | |
3460 | ||
3461 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); | |
3462 | if (!id_phys) | |
3463 | goto out; | |
3464 | ||
3465 | rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index, | |
3466 | id_phys, sizeof(*id_phys)); | |
3467 | if (rc) { | |
3468 | dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n", | |
3469 | __func__, encl_dev->external, bmic_device_index); | |
3470 | goto out; | |
3471 | } | |
3472 | ||
3473 | c = cmd_alloc(h); | |
3474 | ||
3475 | rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp, | |
3476 | sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD); | |
3477 | ||
3478 | if (rc) | |
3479 | goto out; | |
3480 | ||
3481 | if (id_phys->phys_connector[1] == 'E') | |
3482 | c->Request.CDB[5] = id_phys->box_index; | |
3483 | else | |
3484 | c->Request.CDB[5] = 0; | |
3485 | ||
8bc8f47e | 3486 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3026ff9b | 3487 | NO_TIMEOUT); |
cca8f13b DB |
3488 | if (rc) |
3489 | goto out; | |
3490 | ||
3491 | ei = c->err_info; | |
3492 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
3493 | rc = -1; | |
3494 | goto out; | |
3495 | } | |
3496 | ||
3497 | encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port; | |
3498 | memcpy(&encl_dev->phys_connector[id_phys->active_path_number], | |
3499 | bssbp->phys_connector, sizeof(bssbp->phys_connector)); | |
3500 | ||
3501 | rc = IO_OK; | |
3502 | out: | |
3503 | kfree(bssbp); | |
3504 | kfree(id_phys); | |
3505 | ||
3506 | if (c) | |
3507 | cmd_free(h, c); | |
3508 | ||
3509 | if (rc != IO_OK) | |
3510 | hpsa_show_dev_msg(KERN_INFO, h, encl_dev, | |
b4e9ce1c | 3511 | "Error, could not get enclosure information"); |
cca8f13b DB |
3512 | } |
3513 | ||
d04e62b9 KB |
3514 | static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h, |
3515 | unsigned char *scsi3addr) | |
3516 | { | |
3517 | struct ReportExtendedLUNdata *physdev; | |
3518 | u32 nphysicals; | |
3519 | u64 sa = 0; | |
3520 | int i; | |
3521 | ||
3522 | physdev = kzalloc(sizeof(*physdev), GFP_KERNEL); | |
3523 | if (!physdev) | |
3524 | return 0; | |
3525 | ||
3526 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { | |
3527 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); | |
3528 | kfree(physdev); | |
3529 | return 0; | |
3530 | } | |
3531 | nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24; | |
3532 | ||
3533 | for (i = 0; i < nphysicals; i++) | |
3534 | if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) { | |
3535 | sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]); | |
3536 | break; | |
3537 | } | |
3538 | ||
3539 | kfree(physdev); | |
3540 | ||
3541 | return sa; | |
3542 | } | |
3543 | ||
3544 | static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr, | |
3545 | struct hpsa_scsi_dev_t *dev) | |
3546 | { | |
3547 | int rc; | |
3548 | u64 sa = 0; | |
3549 | ||
3550 | if (is_hba_lunid(scsi3addr)) { | |
3551 | struct bmic_sense_subsystem_info *ssi; | |
3552 | ||
3553 | ssi = kzalloc(sizeof(*ssi), GFP_KERNEL); | |
7e8a9486 | 3554 | if (!ssi) |
d04e62b9 | 3555 | return; |
d04e62b9 KB |
3556 | |
3557 | rc = hpsa_bmic_sense_subsystem_information(h, | |
3558 | scsi3addr, 0, ssi, sizeof(*ssi)); | |
3559 | if (rc == 0) { | |
3560 | sa = get_unaligned_be64(ssi->primary_world_wide_id); | |
3561 | h->sas_address = sa; | |
3562 | } | |
3563 | ||
3564 | kfree(ssi); | |
3565 | } else | |
3566 | sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr); | |
3567 | ||
3568 | dev->sas_address = sa; | |
3569 | } | |
3570 | ||
4e188184 BAS |
3571 | static void hpsa_ext_ctrl_present(struct ctlr_info *h, |
3572 | struct ReportExtendedLUNdata *physdev) | |
3573 | { | |
3574 | u32 nphysicals; | |
3575 | int i; | |
3576 | ||
3577 | if (h->discovery_polling) | |
3578 | return; | |
3579 | ||
3580 | nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1; | |
3581 | ||
3582 | for (i = 0; i < nphysicals; i++) { | |
3583 | if (physdev->LUN[i].device_type == | |
3584 | BMIC_DEVICE_TYPE_CONTROLLER | |
3585 | && !is_hba_lunid(physdev->LUN[i].lunid)) { | |
3586 | dev_info(&h->pdev->dev, | |
3587 | "External controller present, activate discovery polling and disable rld caching\n"); | |
3588 | hpsa_disable_rld_caching(h); | |
3589 | h->discovery_polling = 1; | |
3590 | break; | |
3591 | } | |
3592 | } | |
3593 | } | |
3594 | ||
d04e62b9 | 3595 | /* Get a device id from inquiry page 0x83 */ |
8383278d | 3596 | static bool hpsa_vpd_page_supported(struct ctlr_info *h, |
1b70150a SC |
3597 | unsigned char scsi3addr[], u8 page) |
3598 | { | |
3599 | int rc; | |
3600 | int i; | |
3601 | int pages; | |
3602 | unsigned char *buf, bufsize; | |
3603 | ||
3604 | buf = kzalloc(256, GFP_KERNEL); | |
3605 | if (!buf) | |
8383278d | 3606 | return false; |
1b70150a SC |
3607 | |
3608 | /* Get the size of the page list first */ | |
3609 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3610 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3611 | buf, HPSA_VPD_HEADER_SZ); | |
3612 | if (rc != 0) | |
3613 | goto exit_unsupported; | |
3614 | pages = buf[3]; | |
3615 | if ((pages + HPSA_VPD_HEADER_SZ) <= 255) | |
3616 | bufsize = pages + HPSA_VPD_HEADER_SZ; | |
3617 | else | |
3618 | bufsize = 255; | |
3619 | ||
3620 | /* Get the whole VPD page list */ | |
3621 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
3622 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
3623 | buf, bufsize); | |
3624 | if (rc != 0) | |
3625 | goto exit_unsupported; | |
3626 | ||
3627 | pages = buf[3]; | |
3628 | for (i = 1; i <= pages; i++) | |
3629 | if (buf[3 + i] == page) | |
3630 | goto exit_supported; | |
3631 | exit_unsupported: | |
3632 | kfree(buf); | |
8383278d | 3633 | return false; |
1b70150a SC |
3634 | exit_supported: |
3635 | kfree(buf); | |
8383278d | 3636 | return true; |
1b70150a SC |
3637 | } |
3638 | ||
b2582a65 DB |
3639 | /* |
3640 | * Called during a scan operation. | |
3641 | * Sets ioaccel status on the new device list, not the existing device list | |
3642 | * | |
3643 | * The device list used during I/O will be updated later in | |
3644 | * adjust_hpsa_scsi_table. | |
3645 | */ | |
283b4a9b SC |
3646 | static void hpsa_get_ioaccel_status(struct ctlr_info *h, |
3647 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
3648 | { | |
3649 | int rc; | |
3650 | unsigned char *buf; | |
3651 | u8 ioaccel_status; | |
3652 | ||
3653 | this_device->offload_config = 0; | |
3654 | this_device->offload_enabled = 0; | |
41ce4c35 | 3655 | this_device->offload_to_be_enabled = 0; |
283b4a9b SC |
3656 | |
3657 | buf = kzalloc(64, GFP_KERNEL); | |
3658 | if (!buf) | |
3659 | return; | |
1b70150a SC |
3660 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) |
3661 | goto out; | |
283b4a9b | 3662 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, |
b7bb24eb | 3663 | VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); |
283b4a9b SC |
3664 | if (rc != 0) |
3665 | goto out; | |
3666 | ||
3667 | #define IOACCEL_STATUS_BYTE 4 | |
3668 | #define OFFLOAD_CONFIGURED_BIT 0x01 | |
3669 | #define OFFLOAD_ENABLED_BIT 0x02 | |
3670 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
3671 | this_device->offload_config = | |
3672 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
3673 | if (this_device->offload_config) { | |
b2582a65 | 3674 | this_device->offload_to_be_enabled = |
283b4a9b SC |
3675 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); |
3676 | if (hpsa_get_raid_map(h, scsi3addr, this_device)) | |
b2582a65 | 3677 | this_device->offload_to_be_enabled = 0; |
283b4a9b | 3678 | } |
b2582a65 | 3679 | |
283b4a9b SC |
3680 | out: |
3681 | kfree(buf); | |
3682 | return; | |
3683 | } | |
3684 | ||
edd16368 SC |
3685 | /* Get the device id from inquiry page 0x83 */ |
3686 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
75d23d89 | 3687 | unsigned char *device_id, int index, int buflen) |
edd16368 SC |
3688 | { |
3689 | int rc; | |
3690 | unsigned char *buf; | |
3691 | ||
8383278d ST |
3692 | /* Does controller have VPD for device id? */ |
3693 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID)) | |
3694 | return 1; /* not supported */ | |
3695 | ||
edd16368 SC |
3696 | buf = kzalloc(64, GFP_KERNEL); |
3697 | if (!buf) | |
a84d794d | 3698 | return -ENOMEM; |
8383278d ST |
3699 | |
3700 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | | |
3701 | HPSA_VPD_LV_DEVICE_ID, buf, 64); | |
3702 | if (rc == 0) { | |
3703 | if (buflen > 16) | |
3704 | buflen = 16; | |
3705 | memcpy(device_id, &buf[8], buflen); | |
3706 | } | |
75d23d89 | 3707 | |
edd16368 | 3708 | kfree(buf); |
75d23d89 | 3709 | |
8383278d | 3710 | return rc; /*0 - got id, otherwise, didn't */ |
edd16368 SC |
3711 | } |
3712 | ||
3713 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
03383736 | 3714 | void *buf, int bufsize, |
edd16368 SC |
3715 | int extended_response) |
3716 | { | |
3717 | int rc = IO_OK; | |
3718 | struct CommandList *c; | |
3719 | unsigned char scsi3addr[8]; | |
3720 | struct ErrorInfo *ei; | |
3721 | ||
45fcb86e | 3722 | c = cmd_alloc(h); |
bf43caf3 | 3723 | |
e89c0ae7 SC |
3724 | /* address the controller */ |
3725 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
3726 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
3727 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
45f769b2 | 3728 | rc = -EAGAIN; |
a2dac136 SC |
3729 | goto out; |
3730 | } | |
edd16368 SC |
3731 | if (extended_response) |
3732 | c->Request.CDB[1] = extended_response; | |
8bc8f47e CH |
3733 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
3734 | NO_TIMEOUT); | |
25163bd5 WS |
3735 | if (rc) |
3736 | goto out; | |
edd16368 SC |
3737 | ei = c->err_info; |
3738 | if (ei->CommandStatus != 0 && | |
3739 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 3740 | hpsa_scsi_interpret_error(h, c); |
45f769b2 | 3741 | rc = -EIO; |
283b4a9b | 3742 | } else { |
03383736 DB |
3743 | struct ReportLUNdata *rld = buf; |
3744 | ||
3745 | if (rld->extended_response_flag != extended_response) { | |
45f769b2 HR |
3746 | if (!h->legacy_board) { |
3747 | dev_err(&h->pdev->dev, | |
3748 | "report luns requested format %u, got %u\n", | |
3749 | extended_response, | |
3750 | rld->extended_response_flag); | |
3751 | rc = -EINVAL; | |
3752 | } else | |
3753 | rc = -EOPNOTSUPP; | |
283b4a9b | 3754 | } |
edd16368 | 3755 | } |
a2dac136 | 3756 | out: |
45fcb86e | 3757 | cmd_free(h, c); |
edd16368 SC |
3758 | return rc; |
3759 | } | |
3760 | ||
3761 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
03383736 | 3762 | struct ReportExtendedLUNdata *buf, int bufsize) |
edd16368 | 3763 | { |
2a80d545 HR |
3764 | int rc; |
3765 | struct ReportLUNdata *lbuf; | |
3766 | ||
3767 | rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize, | |
3768 | HPSA_REPORT_PHYS_EXTENDED); | |
45f769b2 | 3769 | if (!rc || rc != -EOPNOTSUPP) |
2a80d545 HR |
3770 | return rc; |
3771 | ||
3772 | /* REPORT PHYS EXTENDED is not supported */ | |
3773 | lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL); | |
3774 | if (!lbuf) | |
3775 | return -ENOMEM; | |
3776 | ||
3777 | rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0); | |
3778 | if (!rc) { | |
3779 | int i; | |
3780 | u32 nphys; | |
3781 | ||
3782 | /* Copy ReportLUNdata header */ | |
3783 | memcpy(buf, lbuf, 8); | |
3784 | nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8; | |
3785 | for (i = 0; i < nphys; i++) | |
3786 | memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8); | |
3787 | } | |
3788 | kfree(lbuf); | |
3789 | return rc; | |
edd16368 SC |
3790 | } |
3791 | ||
3792 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
3793 | struct ReportLUNdata *buf, int bufsize) | |
3794 | { | |
3795 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
3796 | } | |
3797 | ||
3798 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
3799 | int bus, int target, int lun) | |
3800 | { | |
3801 | device->bus = bus; | |
3802 | device->target = target; | |
3803 | device->lun = lun; | |
3804 | } | |
3805 | ||
9846590e SC |
3806 | /* Use VPD inquiry to get details of volume status */ |
3807 | static int hpsa_get_volume_status(struct ctlr_info *h, | |
3808 | unsigned char scsi3addr[]) | |
3809 | { | |
3810 | int rc; | |
3811 | int status; | |
3812 | int size; | |
3813 | unsigned char *buf; | |
3814 | ||
3815 | buf = kzalloc(64, GFP_KERNEL); | |
3816 | if (!buf) | |
3817 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3818 | ||
3819 | /* Does controller have VPD for logical volume status? */ | |
24a4b078 | 3820 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) |
9846590e | 3821 | goto exit_failed; |
9846590e SC |
3822 | |
3823 | /* Get the size of the VPD return buffer */ | |
3824 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3825 | buf, HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3826 | if (rc != 0) |
9846590e | 3827 | goto exit_failed; |
9846590e SC |
3828 | size = buf[3]; |
3829 | ||
3830 | /* Now get the whole VPD buffer */ | |
3831 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
3832 | buf, size + HPSA_VPD_HEADER_SZ); | |
24a4b078 | 3833 | if (rc != 0) |
9846590e | 3834 | goto exit_failed; |
9846590e SC |
3835 | status = buf[4]; /* status byte */ |
3836 | ||
3837 | kfree(buf); | |
3838 | return status; | |
3839 | exit_failed: | |
3840 | kfree(buf); | |
3841 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
3842 | } | |
3843 | ||
3844 | /* Determine offline status of a volume. | |
3845 | * Return either: | |
3846 | * 0 (not offline) | |
67955ba3 | 3847 | * 0xff (offline for unknown reasons) |
9846590e SC |
3848 | * # (integer code indicating one of several NOT READY states |
3849 | * describing why a volume is to be kept offline) | |
3850 | */ | |
85b29008 | 3851 | static unsigned char hpsa_volume_offline(struct ctlr_info *h, |
9846590e SC |
3852 | unsigned char scsi3addr[]) |
3853 | { | |
3854 | struct CommandList *c; | |
9437ac43 SC |
3855 | unsigned char *sense; |
3856 | u8 sense_key, asc, ascq; | |
3857 | int sense_len; | |
25163bd5 | 3858 | int rc, ldstat = 0; |
9846590e SC |
3859 | u16 cmd_status; |
3860 | u8 scsi_status; | |
3861 | #define ASC_LUN_NOT_READY 0x04 | |
3862 | #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 | |
3863 | #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 | |
3864 | ||
3865 | c = cmd_alloc(h); | |
bf43caf3 | 3866 | |
9846590e | 3867 | (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); |
c448ecfa | 3868 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
3026ff9b | 3869 | NO_TIMEOUT); |
25163bd5 WS |
3870 | if (rc) { |
3871 | cmd_free(h, c); | |
85b29008 | 3872 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; |
25163bd5 | 3873 | } |
9846590e | 3874 | sense = c->err_info->SenseInfo; |
9437ac43 SC |
3875 | if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo)) |
3876 | sense_len = sizeof(c->err_info->SenseInfo); | |
3877 | else | |
3878 | sense_len = c->err_info->SenseLen; | |
3879 | decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq); | |
9846590e SC |
3880 | cmd_status = c->err_info->CommandStatus; |
3881 | scsi_status = c->err_info->ScsiStatus; | |
3882 | cmd_free(h, c); | |
9846590e SC |
3883 | |
3884 | /* Determine the reason for not ready state */ | |
3885 | ldstat = hpsa_get_volume_status(h, scsi3addr); | |
3886 | ||
3887 | /* Keep volume offline in certain cases: */ | |
3888 | switch (ldstat) { | |
85b29008 | 3889 | case HPSA_LV_FAILED: |
9846590e | 3890 | case HPSA_LV_UNDERGOING_ERASE: |
5ca01204 | 3891 | case HPSA_LV_NOT_AVAILABLE: |
9846590e SC |
3892 | case HPSA_LV_UNDERGOING_RPI: |
3893 | case HPSA_LV_PENDING_RPI: | |
3894 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
3895 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
3896 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
3897 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
3898 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
3899 | return ldstat; | |
3900 | case HPSA_VPD_LV_STATUS_UNSUPPORTED: | |
3901 | /* If VPD status page isn't available, | |
3902 | * use ASC/ASCQ to determine state | |
3903 | */ | |
3904 | if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || | |
3905 | (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) | |
3906 | return ldstat; | |
3907 | break; | |
3908 | default: | |
3909 | break; | |
3910 | } | |
85b29008 | 3911 | return HPSA_LV_OK; |
9846590e SC |
3912 | } |
3913 | ||
edd16368 | 3914 | static int hpsa_update_device_info(struct ctlr_info *h, |
0b0e1d6c SC |
3915 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
3916 | unsigned char *is_OBDR_device) | |
edd16368 | 3917 | { |
0b0e1d6c SC |
3918 | |
3919 | #define OBDR_SIG_OFFSET 43 | |
3920 | #define OBDR_TAPE_SIG "$DR-10" | |
3921 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
3922 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
3923 | ||
ea6d3bc3 | 3924 | unsigned char *inq_buff; |
0b0e1d6c | 3925 | unsigned char *obdr_sig; |
683fc444 | 3926 | int rc = 0; |
edd16368 | 3927 | |
ea6d3bc3 | 3928 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
683fc444 DB |
3929 | if (!inq_buff) { |
3930 | rc = -ENOMEM; | |
edd16368 | 3931 | goto bail_out; |
683fc444 | 3932 | } |
edd16368 | 3933 | |
edd16368 SC |
3934 | /* Do an inquiry to the device to see what it is. */ |
3935 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
3936 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
edd16368 | 3937 | dev_err(&h->pdev->dev, |
85b29008 DB |
3938 | "%s: inquiry failed, device will be skipped.\n", |
3939 | __func__); | |
3940 | rc = HPSA_INQUIRY_FAILED; | |
edd16368 SC |
3941 | goto bail_out; |
3942 | } | |
3943 | ||
4af61e4f DB |
3944 | scsi_sanitize_inquiry_string(&inq_buff[8], 8); |
3945 | scsi_sanitize_inquiry_string(&inq_buff[16], 16); | |
75d23d89 | 3946 | |
edd16368 SC |
3947 | this_device->devtype = (inq_buff[0] & 0x1f); |
3948 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
3949 | memcpy(this_device->vendor, &inq_buff[8], | |
3950 | sizeof(this_device->vendor)); | |
3951 | memcpy(this_device->model, &inq_buff[16], | |
3952 | sizeof(this_device->model)); | |
7630b3a5 | 3953 | this_device->rev = inq_buff[2]; |
edd16368 SC |
3954 | memset(this_device->device_id, 0, |
3955 | sizeof(this_device->device_id)); | |
8383278d | 3956 | if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8, |
a45bcc4e | 3957 | sizeof(this_device->device_id)) < 0) { |
8383278d | 3958 | dev_err(&h->pdev->dev, |
a45bcc4e | 3959 | "hpsa%d: %s: can't get device id for [%d:%d:%d:%d]\t%s\t%.16s\n", |
8383278d ST |
3960 | h->ctlr, __func__, |
3961 | h->scsi_host->host_no, | |
a45bcc4e DB |
3962 | this_device->bus, this_device->target, |
3963 | this_device->lun, | |
8383278d ST |
3964 | scsi_device_type(this_device->devtype), |
3965 | this_device->model); | |
a45bcc4e DB |
3966 | rc = HPSA_LV_FAILED; |
3967 | goto bail_out; | |
3968 | } | |
edd16368 | 3969 | |
af15ed36 DB |
3970 | if ((this_device->devtype == TYPE_DISK || |
3971 | this_device->devtype == TYPE_ZBC) && | |
283b4a9b | 3972 | is_logical_dev_addr_mode(scsi3addr)) { |
85b29008 | 3973 | unsigned char volume_offline; |
67955ba3 | 3974 | |
edd16368 | 3975 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); |
283b4a9b SC |
3976 | if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) |
3977 | hpsa_get_ioaccel_status(h, scsi3addr, this_device); | |
67955ba3 | 3978 | volume_offline = hpsa_volume_offline(h, scsi3addr); |
4d17944a HR |
3979 | if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED && |
3980 | h->legacy_board) { | |
3981 | /* | |
3982 | * Legacy boards might not support volume status | |
3983 | */ | |
3984 | dev_info(&h->pdev->dev, | |
3985 | "C0:T%d:L%d Volume status not available, assuming online.\n", | |
3986 | this_device->target, this_device->lun); | |
3987 | volume_offline = 0; | |
3988 | } | |
eb94588d | 3989 | this_device->volume_offline = volume_offline; |
85b29008 DB |
3990 | if (volume_offline == HPSA_LV_FAILED) { |
3991 | rc = HPSA_LV_FAILED; | |
3992 | dev_err(&h->pdev->dev, | |
3993 | "%s: LV failed, device will be skipped.\n", | |
3994 | __func__); | |
3995 | goto bail_out; | |
3996 | } | |
283b4a9b | 3997 | } else { |
edd16368 | 3998 | this_device->raid_level = RAID_UNKNOWN; |
283b4a9b SC |
3999 | this_device->offload_config = 0; |
4000 | this_device->offload_enabled = 0; | |
41ce4c35 | 4001 | this_device->offload_to_be_enabled = 0; |
a3144e0b | 4002 | this_device->hba_ioaccel_enabled = 0; |
9846590e | 4003 | this_device->volume_offline = 0; |
03383736 | 4004 | this_device->queue_depth = h->nr_cmds; |
283b4a9b | 4005 | } |
edd16368 | 4006 | |
5086435e DB |
4007 | if (this_device->external) |
4008 | this_device->queue_depth = EXTERNAL_QD; | |
4009 | ||
0b0e1d6c SC |
4010 | if (is_OBDR_device) { |
4011 | /* See if this is a One-Button-Disaster-Recovery device | |
4012 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
4013 | */ | |
4014 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
4015 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
4016 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
4017 | OBDR_SIG_LEN) == 0); | |
4018 | } | |
edd16368 SC |
4019 | kfree(inq_buff); |
4020 | return 0; | |
4021 | ||
4022 | bail_out: | |
4023 | kfree(inq_buff); | |
683fc444 | 4024 | return rc; |
edd16368 SC |
4025 | } |
4026 | ||
c795505a KB |
4027 | /* |
4028 | * Helper function to assign bus, target, lun mapping of devices. | |
edd16368 SC |
4029 | * Logical drive target and lun are assigned at this time, but |
4030 | * physical device lun and target assignment are deferred (assigned | |
4031 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
c795505a | 4032 | */ |
edd16368 | 4033 | static void figure_bus_target_lun(struct ctlr_info *h, |
1f310bde | 4034 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 4035 | { |
c795505a | 4036 | u32 lunid = get_unaligned_le32(lunaddrbytes); |
1f310bde SC |
4037 | |
4038 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
4039 | /* physical device, target and lun filled in later */ | |
7630b3a5 HR |
4040 | if (is_hba_lunid(lunaddrbytes)) { |
4041 | int bus = HPSA_HBA_BUS; | |
4042 | ||
4043 | if (!device->rev) | |
4044 | bus = HPSA_LEGACY_HBA_BUS; | |
c795505a | 4045 | hpsa_set_bus_target_lun(device, |
7630b3a5 HR |
4046 | bus, 0, lunid & 0x3fff); |
4047 | } else | |
1f310bde | 4048 | /* defer target, lun assignment for physical devices */ |
c795505a KB |
4049 | hpsa_set_bus_target_lun(device, |
4050 | HPSA_PHYSICAL_DEVICE_BUS, -1, -1); | |
1f310bde SC |
4051 | return; |
4052 | } | |
4053 | /* It's a logical device */ | |
66749d0d | 4054 | if (device->external) { |
1f310bde | 4055 | hpsa_set_bus_target_lun(device, |
c795505a KB |
4056 | HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff, |
4057 | lunid & 0x00ff); | |
1f310bde | 4058 | return; |
edd16368 | 4059 | } |
c795505a KB |
4060 | hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS, |
4061 | 0, lunid & 0x3fff); | |
edd16368 SC |
4062 | } |
4063 | ||
66749d0d ST |
4064 | static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position, |
4065 | int i, int nphysicals, int nlocal_logicals) | |
4066 | { | |
4067 | /* In report logicals, local logicals are listed first, | |
4068 | * then any externals. | |
4069 | */ | |
4070 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
4071 | ||
4072 | if (i == raid_ctlr_position) | |
4073 | return 0; | |
4074 | ||
4075 | if (i < logicals_start) | |
4076 | return 0; | |
4077 | ||
4078 | /* i is in logicals range, but still within local logicals */ | |
4079 | if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals) | |
4080 | return 0; | |
4081 | ||
4082 | return 1; /* it's an external lun */ | |
4083 | } | |
4084 | ||
edd16368 SC |
4085 | /* |
4086 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
4087 | * logdev. The number of luns in physdev and logdev are returned in | |
4088 | * *nphysicals and *nlogicals, respectively. | |
4089 | * Returns 0 on success, -1 otherwise. | |
4090 | */ | |
4091 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
03383736 | 4092 | struct ReportExtendedLUNdata *physdev, u32 *nphysicals, |
01a02ffc | 4093 | struct ReportLUNdata *logdev, u32 *nlogicals) |
edd16368 | 4094 | { |
03383736 | 4095 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { |
edd16368 SC |
4096 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
4097 | return -1; | |
4098 | } | |
03383736 | 4099 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; |
edd16368 | 4100 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
03383736 DB |
4101 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", |
4102 | HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); | |
edd16368 SC |
4103 | *nphysicals = HPSA_MAX_PHYS_LUN; |
4104 | } | |
03383736 | 4105 | if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { |
edd16368 SC |
4106 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); |
4107 | return -1; | |
4108 | } | |
6df1e954 | 4109 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
4110 | /* Reject Logicals in excess of our max capability. */ |
4111 | if (*nlogicals > HPSA_MAX_LUN) { | |
4112 | dev_warn(&h->pdev->dev, | |
4113 | "maximum logical LUNs (%d) exceeded. " | |
4114 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
4115 | *nlogicals - HPSA_MAX_LUN); | |
b64ae4ab | 4116 | *nlogicals = HPSA_MAX_LUN; |
edd16368 SC |
4117 | } |
4118 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
4119 | dev_warn(&h->pdev->dev, | |
4120 | "maximum logical + physical LUNs (%d) exceeded. " | |
4121 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
4122 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
4123 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
4124 | } | |
4125 | return 0; | |
4126 | } | |
4127 | ||
42a91641 DB |
4128 | static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, |
4129 | int i, int nphysicals, int nlogicals, | |
a93aa1fe | 4130 | struct ReportExtendedLUNdata *physdev_list, |
339b2b14 SC |
4131 | struct ReportLUNdata *logdev_list) |
4132 | { | |
4133 | /* Helper function, figure out where the LUN ID info is coming from | |
4134 | * given index i, lists of physical and logical devices, where in | |
4135 | * the list the raid controller is supposed to appear (first or last) | |
4136 | */ | |
4137 | ||
4138 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
4139 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
4140 | ||
4141 | if (i == raid_ctlr_position) | |
4142 | return RAID_CTLR_LUNID; | |
4143 | ||
4144 | if (i < logicals_start) | |
d5b5d964 SC |
4145 | return &physdev_list->LUN[i - |
4146 | (raid_ctlr_position == 0)].lunid[0]; | |
339b2b14 SC |
4147 | |
4148 | if (i < last_device) | |
4149 | return &logdev_list->LUN[i - nphysicals - | |
4150 | (raid_ctlr_position == 0)][0]; | |
4151 | BUG(); | |
4152 | return NULL; | |
4153 | } | |
4154 | ||
03383736 DB |
4155 | /* get physical drive ioaccel handle and queue depth */ |
4156 | static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, | |
4157 | struct hpsa_scsi_dev_t *dev, | |
f2039b03 | 4158 | struct ReportExtendedLUNdata *rlep, int rle_index, |
03383736 DB |
4159 | struct bmic_identify_physical_device *id_phys) |
4160 | { | |
4161 | int rc; | |
4b6e5597 ST |
4162 | struct ext_report_lun_entry *rle; |
4163 | ||
4b6e5597 | 4164 | rle = &rlep->LUN[rle_index]; |
03383736 DB |
4165 | |
4166 | dev->ioaccel_handle = rle->ioaccel_handle; | |
f2039b03 | 4167 | if ((rle->device_flags & 0x08) && dev->ioaccel_handle) |
a3144e0b | 4168 | dev->hba_ioaccel_enabled = 1; |
03383736 | 4169 | memset(id_phys, 0, sizeof(*id_phys)); |
f2039b03 DB |
4170 | rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0], |
4171 | GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys, | |
03383736 DB |
4172 | sizeof(*id_phys)); |
4173 | if (!rc) | |
4174 | /* Reserve space for FW operations */ | |
4175 | #define DRIVE_CMDS_RESERVED_FOR_FW 2 | |
4176 | #define DRIVE_QUEUE_DEPTH 7 | |
4177 | dev->queue_depth = | |
4178 | le16_to_cpu(id_phys->current_queue_depth_limit) - | |
4179 | DRIVE_CMDS_RESERVED_FOR_FW; | |
4180 | else | |
4181 | dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ | |
03383736 DB |
4182 | } |
4183 | ||
8270b862 | 4184 | static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device, |
f2039b03 | 4185 | struct ReportExtendedLUNdata *rlep, int rle_index, |
8270b862 JH |
4186 | struct bmic_identify_physical_device *id_phys) |
4187 | { | |
f2039b03 DB |
4188 | struct ext_report_lun_entry *rle = &rlep->LUN[rle_index]; |
4189 | ||
4190 | if ((rle->device_flags & 0x08) && this_device->ioaccel_handle) | |
8270b862 JH |
4191 | this_device->hba_ioaccel_enabled = 1; |
4192 | ||
4193 | memcpy(&this_device->active_path_index, | |
4194 | &id_phys->active_path_number, | |
4195 | sizeof(this_device->active_path_index)); | |
4196 | memcpy(&this_device->path_map, | |
4197 | &id_phys->redundant_path_present_map, | |
4198 | sizeof(this_device->path_map)); | |
4199 | memcpy(&this_device->box, | |
4200 | &id_phys->alternate_paths_phys_box_on_port, | |
4201 | sizeof(this_device->box)); | |
4202 | memcpy(&this_device->phys_connector, | |
4203 | &id_phys->alternate_paths_phys_connector, | |
4204 | sizeof(this_device->phys_connector)); | |
4205 | memcpy(&this_device->bay, | |
4206 | &id_phys->phys_bay_in_box, | |
4207 | sizeof(this_device->bay)); | |
4208 | } | |
4209 | ||
66749d0d ST |
4210 | /* get number of local logical disks. */ |
4211 | static int hpsa_set_local_logical_count(struct ctlr_info *h, | |
4212 | struct bmic_identify_controller *id_ctlr, | |
4213 | u32 *nlocals) | |
4214 | { | |
4215 | int rc; | |
4216 | ||
4217 | if (!id_ctlr) { | |
4218 | dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n", | |
4219 | __func__); | |
4220 | return -ENOMEM; | |
4221 | } | |
4222 | memset(id_ctlr, 0, sizeof(*id_ctlr)); | |
4223 | rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr)); | |
4224 | if (!rc) | |
c99dfd20 | 4225 | if (id_ctlr->configured_logical_drive_count < 255) |
66749d0d ST |
4226 | *nlocals = id_ctlr->configured_logical_drive_count; |
4227 | else | |
4228 | *nlocals = le16_to_cpu( | |
4229 | id_ctlr->extended_logical_unit_count); | |
4230 | else | |
4231 | *nlocals = -1; | |
4232 | return rc; | |
4233 | } | |
4234 | ||
64ce60ca DB |
4235 | static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes) |
4236 | { | |
4237 | struct bmic_identify_physical_device *id_phys; | |
4238 | bool is_spare = false; | |
4239 | int rc; | |
4240 | ||
4241 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); | |
4242 | if (!id_phys) | |
4243 | return false; | |
4244 | ||
4245 | rc = hpsa_bmic_id_physical_device(h, | |
4246 | lunaddrbytes, | |
4247 | GET_BMIC_DRIVE_NUMBER(lunaddrbytes), | |
4248 | id_phys, sizeof(*id_phys)); | |
4249 | if (rc == 0) | |
4250 | is_spare = (id_phys->more_flags >> 6) & 0x01; | |
4251 | ||
4252 | kfree(id_phys); | |
4253 | return is_spare; | |
4254 | } | |
4255 | ||
4256 | #define RPL_DEV_FLAG_NON_DISK 0x1 | |
4257 | #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2 | |
4258 | #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4 | |
4259 | ||
4260 | #define BMIC_DEVICE_TYPE_ENCLOSURE 6 | |
4261 | ||
4262 | static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes, | |
4263 | struct ext_report_lun_entry *rle) | |
4264 | { | |
4265 | u8 device_flags; | |
4266 | u8 device_type; | |
4267 | ||
4268 | if (!MASKED_DEVICE(lunaddrbytes)) | |
4269 | return false; | |
4270 | ||
4271 | device_flags = rle->device_flags; | |
4272 | device_type = rle->device_type; | |
4273 | ||
4274 | if (device_flags & RPL_DEV_FLAG_NON_DISK) { | |
4275 | if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE) | |
4276 | return false; | |
4277 | return true; | |
4278 | } | |
4279 | ||
4280 | if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED)) | |
4281 | return false; | |
4282 | ||
4283 | if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK) | |
4284 | return false; | |
4285 | ||
4286 | /* | |
4287 | * Spares may be spun down, we do not want to | |
4288 | * do an Inquiry to a RAID set spare drive as | |
4289 | * that would have them spun up, that is a | |
4290 | * performance hit because I/O to the RAID device | |
4291 | * stops while the spin up occurs which can take | |
4292 | * over 50 seconds. | |
4293 | */ | |
4294 | if (hpsa_is_disk_spare(h, lunaddrbytes)) | |
4295 | return true; | |
4296 | ||
4297 | return false; | |
4298 | } | |
66749d0d | 4299 | |
8aa60681 | 4300 | static void hpsa_update_scsi_devices(struct ctlr_info *h) |
edd16368 SC |
4301 | { |
4302 | /* the idea here is we could get notified | |
4303 | * that some devices have changed, so we do a report | |
4304 | * physical luns and report logical luns cmd, and adjust | |
4305 | * our list of devices accordingly. | |
4306 | * | |
4307 | * The scsi3addr's of devices won't change so long as the | |
4308 | * adapter is not reset. That means we can rescan and | |
4309 | * tell which devices we already know about, vs. new | |
4310 | * devices, vs. disappearing devices. | |
4311 | */ | |
a93aa1fe | 4312 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 4313 | struct ReportLUNdata *logdev_list = NULL; |
03383736 | 4314 | struct bmic_identify_physical_device *id_phys = NULL; |
66749d0d | 4315 | struct bmic_identify_controller *id_ctlr = NULL; |
01a02ffc SC |
4316 | u32 nphysicals = 0; |
4317 | u32 nlogicals = 0; | |
66749d0d | 4318 | u32 nlocal_logicals = 0; |
01a02ffc | 4319 | u32 ndev_allocated = 0; |
edd16368 SC |
4320 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
4321 | int ncurrent = 0; | |
4f4eb9f1 | 4322 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 4323 | int raid_ctlr_position; |
04fa2f44 | 4324 | bool physical_device; |
aca4a520 | 4325 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 4326 | |
6396bb22 | 4327 | currentsd = kcalloc(HPSA_MAX_DEVICES, sizeof(*currentsd), GFP_KERNEL); |
92084715 SC |
4328 | physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); |
4329 | logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); | |
edd16368 | 4330 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
03383736 | 4331 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); |
66749d0d | 4332 | id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL); |
edd16368 | 4333 | |
03383736 | 4334 | if (!currentsd || !physdev_list || !logdev_list || |
66749d0d | 4335 | !tmpdevice || !id_phys || !id_ctlr) { |
edd16368 SC |
4336 | dev_err(&h->pdev->dev, "out of memory\n"); |
4337 | goto out; | |
4338 | } | |
4339 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
4340 | ||
853633e8 DB |
4341 | h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */ |
4342 | ||
03383736 | 4343 | if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, |
853633e8 DB |
4344 | logdev_list, &nlogicals)) { |
4345 | h->drv_req_rescan = 1; | |
edd16368 | 4346 | goto out; |
853633e8 | 4347 | } |
edd16368 | 4348 | |
66749d0d ST |
4349 | /* Set number of local logicals (non PTRAID) */ |
4350 | if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) { | |
4351 | dev_warn(&h->pdev->dev, | |
4352 | "%s: Can't determine number of local logical devices.\n", | |
4353 | __func__); | |
4354 | } | |
edd16368 | 4355 | |
aca4a520 ST |
4356 | /* We might see up to the maximum number of logical and physical disks |
4357 | * plus external target devices, and a device for the local RAID | |
4358 | * controller. | |
edd16368 | 4359 | */ |
aca4a520 | 4360 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 | 4361 | |
4e188184 BAS |
4362 | hpsa_ext_ctrl_present(h, physdev_list); |
4363 | ||
edd16368 SC |
4364 | /* Allocate the per device structures */ |
4365 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
4366 | if (i >= HPSA_MAX_DEVICES) { |
4367 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
4368 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
4369 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
4370 | break; | |
4371 | } | |
4372 | ||
edd16368 SC |
4373 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
4374 | if (!currentsd[i]) { | |
853633e8 | 4375 | h->drv_req_rescan = 1; |
edd16368 SC |
4376 | goto out; |
4377 | } | |
4378 | ndev_allocated++; | |
4379 | } | |
4380 | ||
8645291b | 4381 | if (is_scsi_rev_5(h)) |
339b2b14 SC |
4382 | raid_ctlr_position = 0; |
4383 | else | |
4384 | raid_ctlr_position = nphysicals + nlogicals; | |
4385 | ||
edd16368 | 4386 | /* adjust our table of devices */ |
4f4eb9f1 | 4387 | n_ext_target_devs = 0; |
edd16368 | 4388 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 4389 | u8 *lunaddrbytes, is_OBDR = 0; |
683fc444 | 4390 | int rc = 0; |
f2039b03 | 4391 | int phys_dev_index = i - (raid_ctlr_position == 0); |
64ce60ca | 4392 | bool skip_device = false; |
edd16368 | 4393 | |
421bf80c ST |
4394 | memset(tmpdevice, 0, sizeof(*tmpdevice)); |
4395 | ||
04fa2f44 | 4396 | physical_device = i < nphysicals + (raid_ctlr_position == 0); |
edd16368 SC |
4397 | |
4398 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
4399 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
4400 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
41ce4c35 | 4401 | |
86cf7130 DB |
4402 | /* Determine if this is a lun from an external target array */ |
4403 | tmpdevice->external = | |
4404 | figure_external_status(h, raid_ctlr_position, i, | |
4405 | nphysicals, nlocal_logicals); | |
4406 | ||
64ce60ca DB |
4407 | /* |
4408 | * Skip over some devices such as a spare. | |
4409 | */ | |
4410 | if (!tmpdevice->external && physical_device) { | |
4411 | skip_device = hpsa_skip_device(h, lunaddrbytes, | |
4412 | &physdev_list->LUN[phys_dev_index]); | |
4413 | if (skip_device) | |
4414 | continue; | |
4415 | } | |
edd16368 | 4416 | |
b2582a65 | 4417 | /* Get device type, vendor, model, device id, raid_map */ |
683fc444 DB |
4418 | rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
4419 | &is_OBDR); | |
4420 | if (rc == -ENOMEM) { | |
4421 | dev_warn(&h->pdev->dev, | |
4422 | "Out of memory, rescan deferred.\n"); | |
853633e8 | 4423 | h->drv_req_rescan = 1; |
683fc444 | 4424 | goto out; |
853633e8 | 4425 | } |
683fc444 | 4426 | if (rc) { |
85b29008 | 4427 | h->drv_req_rescan = 1; |
683fc444 DB |
4428 | continue; |
4429 | } | |
4430 | ||
1f310bde | 4431 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
edd16368 SC |
4432 | this_device = currentsd[ncurrent]; |
4433 | ||
edd16368 | 4434 | *this_device = *tmpdevice; |
04fa2f44 | 4435 | this_device->physical_device = physical_device; |
edd16368 | 4436 | |
04fa2f44 KB |
4437 | /* |
4438 | * Expose all devices except for physical devices that | |
4439 | * are masked. | |
4440 | */ | |
4441 | if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device) | |
2a168208 KB |
4442 | this_device->expose_device = 0; |
4443 | else | |
4444 | this_device->expose_device = 1; | |
41ce4c35 | 4445 | |
d04e62b9 KB |
4446 | |
4447 | /* | |
4448 | * Get the SAS address for physical devices that are exposed. | |
4449 | */ | |
4450 | if (this_device->physical_device && this_device->expose_device) | |
4451 | hpsa_get_sas_address(h, lunaddrbytes, this_device); | |
41ce4c35 | 4452 | |
edd16368 | 4453 | switch (this_device->devtype) { |
0b0e1d6c | 4454 | case TYPE_ROM: |
edd16368 SC |
4455 | /* We don't *really* support actual CD-ROM devices, |
4456 | * just "One Button Disaster Recovery" tape drive | |
4457 | * which temporarily pretends to be a CD-ROM drive. | |
4458 | * So we check that the device is really an OBDR tape | |
4459 | * device by checking for "$DR-10" in bytes 43-48 of | |
4460 | * the inquiry data. | |
4461 | */ | |
0b0e1d6c SC |
4462 | if (is_OBDR) |
4463 | ncurrent++; | |
edd16368 SC |
4464 | break; |
4465 | case TYPE_DISK: | |
af15ed36 | 4466 | case TYPE_ZBC: |
04fa2f44 | 4467 | if (this_device->physical_device) { |
b9092b79 KB |
4468 | /* The disk is in HBA mode. */ |
4469 | /* Never use RAID mapper in HBA mode. */ | |
ecf418d1 | 4470 | this_device->offload_enabled = 0; |
b9092b79 | 4471 | hpsa_get_ioaccel_drive_info(h, this_device, |
f2039b03 DB |
4472 | physdev_list, phys_dev_index, id_phys); |
4473 | hpsa_get_path_info(this_device, | |
4474 | physdev_list, phys_dev_index, id_phys); | |
b9092b79 | 4475 | } |
ecf418d1 | 4476 | ncurrent++; |
edd16368 SC |
4477 | break; |
4478 | case TYPE_TAPE: | |
4479 | case TYPE_MEDIUM_CHANGER: | |
cca8f13b DB |
4480 | ncurrent++; |
4481 | break; | |
41ce4c35 | 4482 | case TYPE_ENCLOSURE: |
17a9e54a DB |
4483 | if (!this_device->external) |
4484 | hpsa_get_enclosure_info(h, lunaddrbytes, | |
cca8f13b DB |
4485 | physdev_list, phys_dev_index, |
4486 | this_device); | |
b9092b79 | 4487 | ncurrent++; |
41ce4c35 | 4488 | break; |
edd16368 SC |
4489 | case TYPE_RAID: |
4490 | /* Only present the Smartarray HBA as a RAID controller. | |
4491 | * If it's a RAID controller other than the HBA itself | |
4492 | * (an external RAID controller, MSA500 or similar) | |
4493 | * don't present it. | |
4494 | */ | |
4495 | if (!is_hba_lunid(lunaddrbytes)) | |
4496 | break; | |
4497 | ncurrent++; | |
4498 | break; | |
4499 | default: | |
4500 | break; | |
4501 | } | |
cfe5badc | 4502 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
4503 | break; |
4504 | } | |
d04e62b9 KB |
4505 | |
4506 | if (h->sas_host == NULL) { | |
4507 | int rc = 0; | |
4508 | ||
4509 | rc = hpsa_add_sas_host(h); | |
4510 | if (rc) { | |
4511 | dev_warn(&h->pdev->dev, | |
4512 | "Could not add sas host %d\n", rc); | |
4513 | goto out; | |
4514 | } | |
4515 | } | |
4516 | ||
8aa60681 | 4517 | adjust_hpsa_scsi_table(h, currentsd, ncurrent); |
edd16368 SC |
4518 | out: |
4519 | kfree(tmpdevice); | |
4520 | for (i = 0; i < ndev_allocated; i++) | |
4521 | kfree(currentsd[i]); | |
4522 | kfree(currentsd); | |
edd16368 SC |
4523 | kfree(physdev_list); |
4524 | kfree(logdev_list); | |
66749d0d | 4525 | kfree(id_ctlr); |
03383736 | 4526 | kfree(id_phys); |
edd16368 SC |
4527 | } |
4528 | ||
ec5cbf04 WS |
4529 | static void hpsa_set_sg_descriptor(struct SGDescriptor *desc, |
4530 | struct scatterlist *sg) | |
4531 | { | |
4532 | u64 addr64 = (u64) sg_dma_address(sg); | |
4533 | unsigned int len = sg_dma_len(sg); | |
4534 | ||
4535 | desc->Addr = cpu_to_le64(addr64); | |
4536 | desc->Len = cpu_to_le32(len); | |
4537 | desc->Ext = 0; | |
4538 | } | |
4539 | ||
c7ee65b3 WS |
4540 | /* |
4541 | * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
edd16368 SC |
4542 | * dma mapping and fills in the scatter gather entries of the |
4543 | * hpsa command, cp. | |
4544 | */ | |
33a2ffce | 4545 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
4546 | struct CommandList *cp, |
4547 | struct scsi_cmnd *cmd) | |
4548 | { | |
edd16368 | 4549 | struct scatterlist *sg; |
b3a7ba7c | 4550 | int use_sg, i, sg_limit, chained, last_sg; |
33a2ffce | 4551 | struct SGDescriptor *curr_sg; |
edd16368 | 4552 | |
33a2ffce | 4553 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
4554 | |
4555 | use_sg = scsi_dma_map(cmd); | |
4556 | if (use_sg < 0) | |
4557 | return use_sg; | |
4558 | ||
4559 | if (!use_sg) | |
4560 | goto sglist_finished; | |
4561 | ||
b3a7ba7c WS |
4562 | /* |
4563 | * If the number of entries is greater than the max for a single list, | |
4564 | * then we have a chained list; we will set up all but one entry in the | |
4565 | * first list (the last entry is saved for link information); | |
4566 | * otherwise, we don't have a chained list and we'll set up at each of | |
4567 | * the entries in the one list. | |
4568 | */ | |
33a2ffce | 4569 | curr_sg = cp->SG; |
b3a7ba7c WS |
4570 | chained = use_sg > h->max_cmd_sg_entries; |
4571 | sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg; | |
4572 | last_sg = scsi_sg_count(cmd) - 1; | |
4573 | scsi_for_each_sg(cmd, sg, sg_limit, i) { | |
ec5cbf04 | 4574 | hpsa_set_sg_descriptor(curr_sg, sg); |
33a2ffce SC |
4575 | curr_sg++; |
4576 | } | |
ec5cbf04 | 4577 | |
b3a7ba7c WS |
4578 | if (chained) { |
4579 | /* | |
4580 | * Continue with the chained list. Set curr_sg to the chained | |
4581 | * list. Modify the limit to the total count less the entries | |
4582 | * we've already set up. Resume the scan at the list entry | |
4583 | * where the previous loop left off. | |
4584 | */ | |
4585 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
4586 | sg_limit = use_sg - sg_limit; | |
4587 | for_each_sg(sg, sg, sg_limit, i) { | |
4588 | hpsa_set_sg_descriptor(curr_sg, sg); | |
4589 | curr_sg++; | |
4590 | } | |
4591 | } | |
4592 | ||
ec5cbf04 | 4593 | /* Back the pointer up to the last entry and mark it as "last". */ |
b3a7ba7c | 4594 | (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST); |
33a2ffce SC |
4595 | |
4596 | if (use_sg + chained > h->maxSG) | |
4597 | h->maxSG = use_sg + chained; | |
4598 | ||
4599 | if (chained) { | |
4600 | cp->Header.SGList = h->max_cmd_sg_entries; | |
50a0decf | 4601 | cp->Header.SGTotal = cpu_to_le16(use_sg + 1); |
e2bea6df SC |
4602 | if (hpsa_map_sg_chain_block(h, cp)) { |
4603 | scsi_dma_unmap(cmd); | |
4604 | return -1; | |
4605 | } | |
33a2ffce | 4606 | return 0; |
edd16368 SC |
4607 | } |
4608 | ||
4609 | sglist_finished: | |
4610 | ||
01a02ffc | 4611 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
c7ee65b3 | 4612 | cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ |
edd16368 SC |
4613 | return 0; |
4614 | } | |
4615 | ||
b63c64ac DB |
4616 | static inline void warn_zero_length_transfer(struct ctlr_info *h, |
4617 | u8 *cdb, int cdb_len, | |
4618 | const char *func) | |
4619 | { | |
f4d0ad1f AS |
4620 | dev_warn(&h->pdev->dev, |
4621 | "%s: Blocking zero-length request: CDB:%*phN\n", | |
4622 | func, cdb_len, cdb); | |
b63c64ac DB |
4623 | } |
4624 | ||
4625 | #define IO_ACCEL_INELIGIBLE 1 | |
4626 | /* zero-length transfers trigger hardware errors. */ | |
4627 | static bool is_zero_length_transfer(u8 *cdb) | |
4628 | { | |
4629 | u32 block_cnt; | |
4630 | ||
4631 | /* Block zero-length transfer sizes on certain commands. */ | |
4632 | switch (cdb[0]) { | |
4633 | case READ_10: | |
4634 | case WRITE_10: | |
4635 | case VERIFY: /* 0x2F */ | |
4636 | case WRITE_VERIFY: /* 0x2E */ | |
4637 | block_cnt = get_unaligned_be16(&cdb[7]); | |
4638 | break; | |
4639 | case READ_12: | |
4640 | case WRITE_12: | |
4641 | case VERIFY_12: /* 0xAF */ | |
4642 | case WRITE_VERIFY_12: /* 0xAE */ | |
4643 | block_cnt = get_unaligned_be32(&cdb[6]); | |
4644 | break; | |
4645 | case READ_16: | |
4646 | case WRITE_16: | |
4647 | case VERIFY_16: /* 0x8F */ | |
4648 | block_cnt = get_unaligned_be32(&cdb[10]); | |
4649 | break; | |
4650 | default: | |
4651 | return false; | |
4652 | } | |
4653 | ||
4654 | return block_cnt == 0; | |
4655 | } | |
4656 | ||
283b4a9b SC |
4657 | static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) |
4658 | { | |
4659 | int is_write = 0; | |
4660 | u32 block; | |
4661 | u32 block_cnt; | |
4662 | ||
4663 | /* Perform some CDB fixups if needed using 10 byte reads/writes only */ | |
4664 | switch (cdb[0]) { | |
4665 | case WRITE_6: | |
4666 | case WRITE_12: | |
4667 | is_write = 1; | |
5dfdb089 | 4668 | /* fall through */ |
283b4a9b SC |
4669 | case READ_6: |
4670 | case READ_12: | |
4671 | if (*cdb_len == 6) { | |
abbada71 MR |
4672 | block = (((cdb[1] & 0x1F) << 16) | |
4673 | (cdb[2] << 8) | | |
4674 | cdb[3]); | |
283b4a9b | 4675 | block_cnt = cdb[4]; |
c8a6c9a6 DB |
4676 | if (block_cnt == 0) |
4677 | block_cnt = 256; | |
283b4a9b SC |
4678 | } else { |
4679 | BUG_ON(*cdb_len != 12); | |
c8a6c9a6 DB |
4680 | block = get_unaligned_be32(&cdb[2]); |
4681 | block_cnt = get_unaligned_be32(&cdb[6]); | |
283b4a9b SC |
4682 | } |
4683 | if (block_cnt > 0xffff) | |
4684 | return IO_ACCEL_INELIGIBLE; | |
4685 | ||
4686 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
4687 | cdb[1] = 0; | |
4688 | cdb[2] = (u8) (block >> 24); | |
4689 | cdb[3] = (u8) (block >> 16); | |
4690 | cdb[4] = (u8) (block >> 8); | |
4691 | cdb[5] = (u8) (block); | |
4692 | cdb[6] = 0; | |
4693 | cdb[7] = (u8) (block_cnt >> 8); | |
4694 | cdb[8] = (u8) (block_cnt); | |
4695 | cdb[9] = 0; | |
4696 | *cdb_len = 10; | |
4697 | break; | |
4698 | } | |
4699 | return 0; | |
4700 | } | |
4701 | ||
c349775e | 4702 | static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, |
283b4a9b | 4703 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, |
03383736 | 4704 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
e1f7de0c MG |
4705 | { |
4706 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
e1f7de0c MG |
4707 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; |
4708 | unsigned int len; | |
4709 | unsigned int total_len = 0; | |
4710 | struct scatterlist *sg; | |
4711 | u64 addr64; | |
4712 | int use_sg, i; | |
4713 | struct SGDescriptor *curr_sg; | |
4714 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
4715 | ||
283b4a9b | 4716 | /* TODO: implement chaining support */ |
03383736 DB |
4717 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { |
4718 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4719 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4720 | } |
283b4a9b | 4721 | |
e1f7de0c MG |
4722 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); |
4723 | ||
b63c64ac DB |
4724 | if (is_zero_length_transfer(cdb)) { |
4725 | warn_zero_length_transfer(h, cdb, cdb_len, __func__); | |
4726 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4727 | return IO_ACCEL_INELIGIBLE; | |
4728 | } | |
4729 | ||
03383736 DB |
4730 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4731 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 4732 | return IO_ACCEL_INELIGIBLE; |
03383736 | 4733 | } |
283b4a9b | 4734 | |
e1f7de0c MG |
4735 | c->cmd_type = CMD_IOACCEL1; |
4736 | ||
4737 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4738 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
4739 | (c->cmdindex * sizeof(*cp)); | |
4740 | BUG_ON(c->busaddr & 0x0000007F); | |
4741 | ||
4742 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4743 | if (use_sg < 0) { |
4744 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
e1f7de0c | 4745 | return use_sg; |
03383736 | 4746 | } |
e1f7de0c MG |
4747 | |
4748 | if (use_sg) { | |
4749 | curr_sg = cp->SG; | |
4750 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
4751 | addr64 = (u64) sg_dma_address(sg); | |
4752 | len = sg_dma_len(sg); | |
4753 | total_len += len; | |
50a0decf SC |
4754 | curr_sg->Addr = cpu_to_le64(addr64); |
4755 | curr_sg->Len = cpu_to_le32(len); | |
4756 | curr_sg->Ext = cpu_to_le32(0); | |
e1f7de0c MG |
4757 | curr_sg++; |
4758 | } | |
50a0decf | 4759 | (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); |
e1f7de0c MG |
4760 | |
4761 | switch (cmd->sc_data_direction) { | |
4762 | case DMA_TO_DEVICE: | |
4763 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
4764 | break; | |
4765 | case DMA_FROM_DEVICE: | |
4766 | control |= IOACCEL1_CONTROL_DATA_IN; | |
4767 | break; | |
4768 | case DMA_NONE: | |
4769 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4770 | break; | |
4771 | default: | |
4772 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4773 | cmd->sc_data_direction); | |
4774 | BUG(); | |
4775 | break; | |
4776 | } | |
4777 | } else { | |
4778 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
4779 | } | |
4780 | ||
c349775e | 4781 | c->Header.SGList = use_sg; |
e1f7de0c | 4782 | /* Fill out the command structure to submit */ |
2b08b3e9 DB |
4783 | cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); |
4784 | cp->transfer_len = cpu_to_le32(total_len); | |
4785 | cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | | |
4786 | (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); | |
4787 | cp->control = cpu_to_le32(control); | |
283b4a9b SC |
4788 | memcpy(cp->CDB, cdb, cdb_len); |
4789 | memcpy(cp->CISS_LUN, scsi3addr, 8); | |
c349775e | 4790 | /* Tag was already set at init time. */ |
283b4a9b | 4791 | enqueue_cmd_and_start_io(h, c); |
e1f7de0c MG |
4792 | return 0; |
4793 | } | |
edd16368 | 4794 | |
283b4a9b SC |
4795 | /* |
4796 | * Queue a command directly to a device behind the controller using the | |
4797 | * I/O accelerator path. | |
4798 | */ | |
4799 | static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, | |
4800 | struct CommandList *c) | |
4801 | { | |
4802 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4803 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4804 | ||
45e596cd DB |
4805 | if (!dev) |
4806 | return -1; | |
4807 | ||
03383736 DB |
4808 | c->phys_disk = dev; |
4809 | ||
c5dfd106 DB |
4810 | if (dev->in_reset) |
4811 | return -1; | |
4812 | ||
283b4a9b | 4813 | return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, |
03383736 | 4814 | cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); |
283b4a9b SC |
4815 | } |
4816 | ||
dd0e19f3 ST |
4817 | /* |
4818 | * Set encryption parameters for the ioaccel2 request | |
4819 | */ | |
4820 | static void set_encrypt_ioaccel2(struct ctlr_info *h, | |
4821 | struct CommandList *c, struct io_accel2_cmd *cp) | |
4822 | { | |
4823 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4824 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
4825 | struct raid_map_data *map = &dev->raid_map; | |
4826 | u64 first_block; | |
4827 | ||
dd0e19f3 | 4828 | /* Are we doing encryption on this device */ |
2b08b3e9 | 4829 | if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) |
dd0e19f3 ST |
4830 | return; |
4831 | /* Set the data encryption key index. */ | |
4832 | cp->dekindex = map->dekindex; | |
4833 | ||
4834 | /* Set the encryption enable flag, encoded into direction field. */ | |
4835 | cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; | |
4836 | ||
4837 | /* Set encryption tweak values based on logical block address | |
4838 | * If block size is 512, tweak value is LBA. | |
4839 | * For other block sizes, tweak is (LBA * block size)/ 512) | |
4840 | */ | |
4841 | switch (cmd->cmnd[0]) { | |
4842 | /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ | |
dd0e19f3 | 4843 | case READ_6: |
abbada71 MR |
4844 | case WRITE_6: |
4845 | first_block = (((cmd->cmnd[1] & 0x1F) << 16) | | |
4846 | (cmd->cmnd[2] << 8) | | |
4847 | cmd->cmnd[3]); | |
dd0e19f3 ST |
4848 | break; |
4849 | case WRITE_10: | |
4850 | case READ_10: | |
dd0e19f3 ST |
4851 | /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ |
4852 | case WRITE_12: | |
4853 | case READ_12: | |
2b08b3e9 | 4854 | first_block = get_unaligned_be32(&cmd->cmnd[2]); |
dd0e19f3 ST |
4855 | break; |
4856 | case WRITE_16: | |
4857 | case READ_16: | |
2b08b3e9 | 4858 | first_block = get_unaligned_be64(&cmd->cmnd[2]); |
dd0e19f3 ST |
4859 | break; |
4860 | default: | |
4861 | dev_err(&h->pdev->dev, | |
2b08b3e9 DB |
4862 | "ERROR: %s: size (0x%x) not supported for encryption\n", |
4863 | __func__, cmd->cmnd[0]); | |
dd0e19f3 ST |
4864 | BUG(); |
4865 | break; | |
4866 | } | |
2b08b3e9 DB |
4867 | |
4868 | if (le32_to_cpu(map->volume_blk_size) != 512) | |
4869 | first_block = first_block * | |
4870 | le32_to_cpu(map->volume_blk_size)/512; | |
4871 | ||
4872 | cp->tweak_lower = cpu_to_le32(first_block); | |
4873 | cp->tweak_upper = cpu_to_le32(first_block >> 32); | |
dd0e19f3 ST |
4874 | } |
4875 | ||
c349775e ST |
4876 | static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, |
4877 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 4878 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e ST |
4879 | { |
4880 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
4881 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
4882 | struct ioaccel2_sg_element *curr_sg; | |
4883 | int use_sg, i; | |
4884 | struct scatterlist *sg; | |
4885 | u64 addr64; | |
4886 | u32 len; | |
4887 | u32 total_len = 0; | |
4888 | ||
45e596cd DB |
4889 | if (!cmd->device) |
4890 | return -1; | |
4891 | ||
4892 | if (!cmd->device->hostdata) | |
4893 | return -1; | |
4894 | ||
d9a729f3 | 4895 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
c349775e | 4896 | |
b63c64ac DB |
4897 | if (is_zero_length_transfer(cdb)) { |
4898 | warn_zero_length_transfer(h, cdb, cdb_len, __func__); | |
4899 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4900 | return IO_ACCEL_INELIGIBLE; | |
4901 | } | |
4902 | ||
03383736 DB |
4903 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
4904 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4905 | return IO_ACCEL_INELIGIBLE; |
03383736 DB |
4906 | } |
4907 | ||
c349775e ST |
4908 | c->cmd_type = CMD_IOACCEL2; |
4909 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
4910 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
4911 | (c->cmdindex * sizeof(*cp)); | |
4912 | BUG_ON(c->busaddr & 0x0000007F); | |
4913 | ||
4914 | memset(cp, 0, sizeof(*cp)); | |
4915 | cp->IU_type = IOACCEL2_IU_TYPE; | |
4916 | ||
4917 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
4918 | if (use_sg < 0) { |
4919 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 4920 | return use_sg; |
03383736 | 4921 | } |
c349775e ST |
4922 | |
4923 | if (use_sg) { | |
c349775e | 4924 | curr_sg = cp->sg; |
d9a729f3 WS |
4925 | if (use_sg > h->ioaccel_maxsg) { |
4926 | addr64 = le64_to_cpu( | |
4927 | h->ioaccel2_cmd_sg_list[c->cmdindex]->address); | |
4928 | curr_sg->address = cpu_to_le64(addr64); | |
4929 | curr_sg->length = 0; | |
4930 | curr_sg->reserved[0] = 0; | |
4931 | curr_sg->reserved[1] = 0; | |
4932 | curr_sg->reserved[2] = 0; | |
625d7d35 | 4933 | curr_sg->chain_indicator = IOACCEL2_CHAIN; |
d9a729f3 WS |
4934 | |
4935 | curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex]; | |
4936 | } | |
c349775e ST |
4937 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
4938 | addr64 = (u64) sg_dma_address(sg); | |
4939 | len = sg_dma_len(sg); | |
4940 | total_len += len; | |
4941 | curr_sg->address = cpu_to_le64(addr64); | |
4942 | curr_sg->length = cpu_to_le32(len); | |
4943 | curr_sg->reserved[0] = 0; | |
4944 | curr_sg->reserved[1] = 0; | |
4945 | curr_sg->reserved[2] = 0; | |
4946 | curr_sg->chain_indicator = 0; | |
4947 | curr_sg++; | |
4948 | } | |
4949 | ||
625d7d35 DB |
4950 | /* |
4951 | * Set the last s/g element bit | |
4952 | */ | |
4953 | (curr_sg - 1)->chain_indicator = IOACCEL2_LAST_SG; | |
4954 | ||
c349775e ST |
4955 | switch (cmd->sc_data_direction) { |
4956 | case DMA_TO_DEVICE: | |
dd0e19f3 ST |
4957 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4958 | cp->direction |= IOACCEL2_DIR_DATA_OUT; | |
c349775e ST |
4959 | break; |
4960 | case DMA_FROM_DEVICE: | |
dd0e19f3 ST |
4961 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4962 | cp->direction |= IOACCEL2_DIR_DATA_IN; | |
c349775e ST |
4963 | break; |
4964 | case DMA_NONE: | |
dd0e19f3 ST |
4965 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4966 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e ST |
4967 | break; |
4968 | default: | |
4969 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4970 | cmd->sc_data_direction); | |
4971 | BUG(); | |
4972 | break; | |
4973 | } | |
4974 | } else { | |
dd0e19f3 ST |
4975 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
4976 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e | 4977 | } |
dd0e19f3 ST |
4978 | |
4979 | /* Set encryption parameters, if necessary */ | |
4980 | set_encrypt_ioaccel2(h, c, cp); | |
4981 | ||
2b08b3e9 | 4982 | cp->scsi_nexus = cpu_to_le32(ioaccel_handle); |
f2405db8 | 4983 | cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); |
c349775e | 4984 | memcpy(cp->cdb, cdb, sizeof(cp->cdb)); |
c349775e | 4985 | |
c349775e ST |
4986 | cp->data_len = cpu_to_le32(total_len); |
4987 | cp->err_ptr = cpu_to_le64(c->busaddr + | |
4988 | offsetof(struct io_accel2_cmd, error_data)); | |
50a0decf | 4989 | cp->err_len = cpu_to_le32(sizeof(cp->error_data)); |
c349775e | 4990 | |
d9a729f3 WS |
4991 | /* fill in sg elements */ |
4992 | if (use_sg > h->ioaccel_maxsg) { | |
4993 | cp->sg_count = 1; | |
a736e9b6 | 4994 | cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0])); |
d9a729f3 WS |
4995 | if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) { |
4996 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
4997 | scsi_dma_unmap(cmd); | |
4998 | return -1; | |
4999 | } | |
5000 | } else | |
5001 | cp->sg_count = (u8) use_sg; | |
5002 | ||
c5dfd106 DB |
5003 | if (phys_disk->in_reset) { |
5004 | cmd->result = DID_RESET << 16; | |
5005 | return -1; | |
5006 | } | |
5007 | ||
c349775e ST |
5008 | enqueue_cmd_and_start_io(h, c); |
5009 | return 0; | |
5010 | } | |
5011 | ||
5012 | /* | |
5013 | * Queue a command to the correct I/O accelerator path. | |
5014 | */ | |
5015 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
5016 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 5017 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e | 5018 | { |
45e596cd DB |
5019 | if (!c->scsi_cmd->device) |
5020 | return -1; | |
5021 | ||
5022 | if (!c->scsi_cmd->device->hostdata) | |
5023 | return -1; | |
5024 | ||
c5dfd106 DB |
5025 | if (phys_disk->in_reset) |
5026 | return -1; | |
5027 | ||
03383736 DB |
5028 | /* Try to honor the device's queue depth */ |
5029 | if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > | |
5030 | phys_disk->queue_depth) { | |
5031 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
5032 | return IO_ACCEL_INELIGIBLE; | |
5033 | } | |
c349775e ST |
5034 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
5035 | return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
5036 | cdb, cdb_len, scsi3addr, |
5037 | phys_disk); | |
c349775e ST |
5038 | else |
5039 | return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
5040 | cdb, cdb_len, scsi3addr, |
5041 | phys_disk); | |
c349775e ST |
5042 | } |
5043 | ||
6b80b18f ST |
5044 | static void raid_map_helper(struct raid_map_data *map, |
5045 | int offload_to_mirror, u32 *map_index, u32 *current_group) | |
5046 | { | |
5047 | if (offload_to_mirror == 0) { | |
5048 | /* use physical disk in the first mirrored group. */ | |
2b08b3e9 | 5049 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
5050 | return; |
5051 | } | |
5052 | do { | |
5053 | /* determine mirror group that *map_index indicates */ | |
2b08b3e9 DB |
5054 | *current_group = *map_index / |
5055 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f ST |
5056 | if (offload_to_mirror == *current_group) |
5057 | continue; | |
2b08b3e9 | 5058 | if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { |
6b80b18f | 5059 | /* select map index from next group */ |
2b08b3e9 | 5060 | *map_index += le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
5061 | (*current_group)++; |
5062 | } else { | |
5063 | /* select map index from first group */ | |
2b08b3e9 | 5064 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
5065 | *current_group = 0; |
5066 | } | |
5067 | } while (offload_to_mirror != *current_group); | |
5068 | } | |
5069 | ||
283b4a9b SC |
5070 | /* |
5071 | * Attempt to perform offload RAID mapping for a logical volume I/O. | |
5072 | */ | |
5073 | static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, | |
5074 | struct CommandList *c) | |
5075 | { | |
5076 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
5077 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
5078 | struct raid_map_data *map = &dev->raid_map; | |
5079 | struct raid_map_disk_data *dd = &map->data[0]; | |
5080 | int is_write = 0; | |
5081 | u32 map_index; | |
5082 | u64 first_block, last_block; | |
5083 | u32 block_cnt; | |
5084 | u32 blocks_per_row; | |
5085 | u64 first_row, last_row; | |
5086 | u32 first_row_offset, last_row_offset; | |
5087 | u32 first_column, last_column; | |
6b80b18f ST |
5088 | u64 r0_first_row, r0_last_row; |
5089 | u32 r5or6_blocks_per_row; | |
5090 | u64 r5or6_first_row, r5or6_last_row; | |
5091 | u32 r5or6_first_row_offset, r5or6_last_row_offset; | |
5092 | u32 r5or6_first_column, r5or6_last_column; | |
5093 | u32 total_disks_per_row; | |
5094 | u32 stripesize; | |
5095 | u32 first_group, last_group, current_group; | |
283b4a9b SC |
5096 | u32 map_row; |
5097 | u32 disk_handle; | |
5098 | u64 disk_block; | |
5099 | u32 disk_block_cnt; | |
5100 | u8 cdb[16]; | |
5101 | u8 cdb_len; | |
2b08b3e9 | 5102 | u16 strip_size; |
283b4a9b SC |
5103 | #if BITS_PER_LONG == 32 |
5104 | u64 tmpdiv; | |
5105 | #endif | |
6b80b18f | 5106 | int offload_to_mirror; |
283b4a9b | 5107 | |
45e596cd DB |
5108 | if (!dev) |
5109 | return -1; | |
5110 | ||
c5dfd106 DB |
5111 | if (dev->in_reset) |
5112 | return -1; | |
5113 | ||
283b4a9b SC |
5114 | /* check for valid opcode, get LBA and block count */ |
5115 | switch (cmd->cmnd[0]) { | |
5116 | case WRITE_6: | |
5117 | is_write = 1; | |
5dfdb089 | 5118 | /* fall through */ |
283b4a9b | 5119 | case READ_6: |
abbada71 MR |
5120 | first_block = (((cmd->cmnd[1] & 0x1F) << 16) | |
5121 | (cmd->cmnd[2] << 8) | | |
5122 | cmd->cmnd[3]); | |
283b4a9b | 5123 | block_cnt = cmd->cmnd[4]; |
3fa89a04 SC |
5124 | if (block_cnt == 0) |
5125 | block_cnt = 256; | |
283b4a9b SC |
5126 | break; |
5127 | case WRITE_10: | |
5128 | is_write = 1; | |
5dfdb089 | 5129 | /* fall through */ |
283b4a9b SC |
5130 | case READ_10: |
5131 | first_block = | |
5132 | (((u64) cmd->cmnd[2]) << 24) | | |
5133 | (((u64) cmd->cmnd[3]) << 16) | | |
5134 | (((u64) cmd->cmnd[4]) << 8) | | |
5135 | cmd->cmnd[5]; | |
5136 | block_cnt = | |
5137 | (((u32) cmd->cmnd[7]) << 8) | | |
5138 | cmd->cmnd[8]; | |
5139 | break; | |
5140 | case WRITE_12: | |
5141 | is_write = 1; | |
5dfdb089 | 5142 | /* fall through */ |
283b4a9b SC |
5143 | case READ_12: |
5144 | first_block = | |
5145 | (((u64) cmd->cmnd[2]) << 24) | | |
5146 | (((u64) cmd->cmnd[3]) << 16) | | |
5147 | (((u64) cmd->cmnd[4]) << 8) | | |
5148 | cmd->cmnd[5]; | |
5149 | block_cnt = | |
5150 | (((u32) cmd->cmnd[6]) << 24) | | |
5151 | (((u32) cmd->cmnd[7]) << 16) | | |
5152 | (((u32) cmd->cmnd[8]) << 8) | | |
5153 | cmd->cmnd[9]; | |
5154 | break; | |
5155 | case WRITE_16: | |
5156 | is_write = 1; | |
5dfdb089 | 5157 | /* fall through */ |
283b4a9b SC |
5158 | case READ_16: |
5159 | first_block = | |
5160 | (((u64) cmd->cmnd[2]) << 56) | | |
5161 | (((u64) cmd->cmnd[3]) << 48) | | |
5162 | (((u64) cmd->cmnd[4]) << 40) | | |
5163 | (((u64) cmd->cmnd[5]) << 32) | | |
5164 | (((u64) cmd->cmnd[6]) << 24) | | |
5165 | (((u64) cmd->cmnd[7]) << 16) | | |
5166 | (((u64) cmd->cmnd[8]) << 8) | | |
5167 | cmd->cmnd[9]; | |
5168 | block_cnt = | |
5169 | (((u32) cmd->cmnd[10]) << 24) | | |
5170 | (((u32) cmd->cmnd[11]) << 16) | | |
5171 | (((u32) cmd->cmnd[12]) << 8) | | |
5172 | cmd->cmnd[13]; | |
5173 | break; | |
5174 | default: | |
5175 | return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ | |
5176 | } | |
283b4a9b SC |
5177 | last_block = first_block + block_cnt - 1; |
5178 | ||
5179 | /* check for write to non-RAID-0 */ | |
5180 | if (is_write && dev->raid_level != 0) | |
5181 | return IO_ACCEL_INELIGIBLE; | |
5182 | ||
5183 | /* check for invalid block or wraparound */ | |
2b08b3e9 DB |
5184 | if (last_block >= le64_to_cpu(map->volume_blk_cnt) || |
5185 | last_block < first_block) | |
283b4a9b SC |
5186 | return IO_ACCEL_INELIGIBLE; |
5187 | ||
5188 | /* calculate stripe information for the request */ | |
2b08b3e9 DB |
5189 | blocks_per_row = le16_to_cpu(map->data_disks_per_row) * |
5190 | le16_to_cpu(map->strip_size); | |
5191 | strip_size = le16_to_cpu(map->strip_size); | |
283b4a9b SC |
5192 | #if BITS_PER_LONG == 32 |
5193 | tmpdiv = first_block; | |
5194 | (void) do_div(tmpdiv, blocks_per_row); | |
5195 | first_row = tmpdiv; | |
5196 | tmpdiv = last_block; | |
5197 | (void) do_div(tmpdiv, blocks_per_row); | |
5198 | last_row = tmpdiv; | |
5199 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
5200 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
5201 | tmpdiv = first_row_offset; | |
2b08b3e9 | 5202 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
5203 | first_column = tmpdiv; |
5204 | tmpdiv = last_row_offset; | |
2b08b3e9 | 5205 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
5206 | last_column = tmpdiv; |
5207 | #else | |
5208 | first_row = first_block / blocks_per_row; | |
5209 | last_row = last_block / blocks_per_row; | |
5210 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
5211 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2b08b3e9 DB |
5212 | first_column = first_row_offset / strip_size; |
5213 | last_column = last_row_offset / strip_size; | |
283b4a9b SC |
5214 | #endif |
5215 | ||
5216 | /* if this isn't a single row/column then give to the controller */ | |
5217 | if ((first_row != last_row) || (first_column != last_column)) | |
5218 | return IO_ACCEL_INELIGIBLE; | |
5219 | ||
5220 | /* proceeding with driver mapping */ | |
2b08b3e9 DB |
5221 | total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + |
5222 | le16_to_cpu(map->metadata_disks_per_row); | |
283b4a9b | 5223 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % |
2b08b3e9 | 5224 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
5225 | map_index = (map_row * total_disks_per_row) + first_column; |
5226 | ||
5227 | switch (dev->raid_level) { | |
5228 | case HPSA_RAID_0: | |
5229 | break; /* nothing special to do */ | |
5230 | case HPSA_RAID_1: | |
5231 | /* Handles load balance across RAID 1 members. | |
5232 | * (2-drive R1 and R10 with even # of drives.) | |
5233 | * Appropriate for SSDs, not optimal for HDDs | |
283b4a9b | 5234 | */ |
2b08b3e9 | 5235 | BUG_ON(le16_to_cpu(map->layout_map_count) != 2); |
283b4a9b | 5236 | if (dev->offload_to_mirror) |
2b08b3e9 | 5237 | map_index += le16_to_cpu(map->data_disks_per_row); |
283b4a9b | 5238 | dev->offload_to_mirror = !dev->offload_to_mirror; |
6b80b18f ST |
5239 | break; |
5240 | case HPSA_RAID_ADM: | |
5241 | /* Handles N-way mirrors (R1-ADM) | |
5242 | * and R10 with # of drives divisible by 3.) | |
5243 | */ | |
2b08b3e9 | 5244 | BUG_ON(le16_to_cpu(map->layout_map_count) != 3); |
6b80b18f ST |
5245 | |
5246 | offload_to_mirror = dev->offload_to_mirror; | |
5247 | raid_map_helper(map, offload_to_mirror, | |
5248 | &map_index, ¤t_group); | |
5249 | /* set mirror group to use next time */ | |
5250 | offload_to_mirror = | |
2b08b3e9 DB |
5251 | (offload_to_mirror >= |
5252 | le16_to_cpu(map->layout_map_count) - 1) | |
6b80b18f | 5253 | ? 0 : offload_to_mirror + 1; |
6b80b18f ST |
5254 | dev->offload_to_mirror = offload_to_mirror; |
5255 | /* Avoid direct use of dev->offload_to_mirror within this | |
5256 | * function since multiple threads might simultaneously | |
5257 | * increment it beyond the range of dev->layout_map_count -1. | |
5258 | */ | |
5259 | break; | |
5260 | case HPSA_RAID_5: | |
5261 | case HPSA_RAID_6: | |
2b08b3e9 | 5262 | if (le16_to_cpu(map->layout_map_count) <= 1) |
6b80b18f ST |
5263 | break; |
5264 | ||
5265 | /* Verify first and last block are in same RAID group */ | |
5266 | r5or6_blocks_per_row = | |
2b08b3e9 DB |
5267 | le16_to_cpu(map->strip_size) * |
5268 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f | 5269 | BUG_ON(r5or6_blocks_per_row == 0); |
2b08b3e9 DB |
5270 | stripesize = r5or6_blocks_per_row * |
5271 | le16_to_cpu(map->layout_map_count); | |
6b80b18f ST |
5272 | #if BITS_PER_LONG == 32 |
5273 | tmpdiv = first_block; | |
5274 | first_group = do_div(tmpdiv, stripesize); | |
5275 | tmpdiv = first_group; | |
5276 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
5277 | first_group = tmpdiv; | |
5278 | tmpdiv = last_block; | |
5279 | last_group = do_div(tmpdiv, stripesize); | |
5280 | tmpdiv = last_group; | |
5281 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
5282 | last_group = tmpdiv; | |
5283 | #else | |
5284 | first_group = (first_block % stripesize) / r5or6_blocks_per_row; | |
5285 | last_group = (last_block % stripesize) / r5or6_blocks_per_row; | |
6b80b18f | 5286 | #endif |
000ff7c2 | 5287 | if (first_group != last_group) |
6b80b18f ST |
5288 | return IO_ACCEL_INELIGIBLE; |
5289 | ||
5290 | /* Verify request is in a single row of RAID 5/6 */ | |
5291 | #if BITS_PER_LONG == 32 | |
5292 | tmpdiv = first_block; | |
5293 | (void) do_div(tmpdiv, stripesize); | |
5294 | first_row = r5or6_first_row = r0_first_row = tmpdiv; | |
5295 | tmpdiv = last_block; | |
5296 | (void) do_div(tmpdiv, stripesize); | |
5297 | r5or6_last_row = r0_last_row = tmpdiv; | |
5298 | #else | |
5299 | first_row = r5or6_first_row = r0_first_row = | |
5300 | first_block / stripesize; | |
5301 | r5or6_last_row = r0_last_row = last_block / stripesize; | |
5302 | #endif | |
5303 | if (r5or6_first_row != r5or6_last_row) | |
5304 | return IO_ACCEL_INELIGIBLE; | |
5305 | ||
5306 | ||
5307 | /* Verify request is in a single column */ | |
5308 | #if BITS_PER_LONG == 32 | |
5309 | tmpdiv = first_block; | |
5310 | first_row_offset = do_div(tmpdiv, stripesize); | |
5311 | tmpdiv = first_row_offset; | |
5312 | first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); | |
5313 | r5or6_first_row_offset = first_row_offset; | |
5314 | tmpdiv = last_block; | |
5315 | r5or6_last_row_offset = do_div(tmpdiv, stripesize); | |
5316 | tmpdiv = r5or6_last_row_offset; | |
5317 | r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); | |
5318 | tmpdiv = r5or6_first_row_offset; | |
5319 | (void) do_div(tmpdiv, map->strip_size); | |
5320 | first_column = r5or6_first_column = tmpdiv; | |
5321 | tmpdiv = r5or6_last_row_offset; | |
5322 | (void) do_div(tmpdiv, map->strip_size); | |
5323 | r5or6_last_column = tmpdiv; | |
5324 | #else | |
5325 | first_row_offset = r5or6_first_row_offset = | |
5326 | (u32)((first_block % stripesize) % | |
5327 | r5or6_blocks_per_row); | |
5328 | ||
5329 | r5or6_last_row_offset = | |
5330 | (u32)((last_block % stripesize) % | |
5331 | r5or6_blocks_per_row); | |
5332 | ||
5333 | first_column = r5or6_first_column = | |
2b08b3e9 | 5334 | r5or6_first_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f | 5335 | r5or6_last_column = |
2b08b3e9 | 5336 | r5or6_last_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f ST |
5337 | #endif |
5338 | if (r5or6_first_column != r5or6_last_column) | |
5339 | return IO_ACCEL_INELIGIBLE; | |
5340 | ||
5341 | /* Request is eligible */ | |
5342 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % | |
2b08b3e9 | 5343 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
5344 | |
5345 | map_index = (first_group * | |
2b08b3e9 | 5346 | (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + |
6b80b18f ST |
5347 | (map_row * total_disks_per_row) + first_column; |
5348 | break; | |
5349 | default: | |
5350 | return IO_ACCEL_INELIGIBLE; | |
283b4a9b | 5351 | } |
6b80b18f | 5352 | |
07543e0c SC |
5353 | if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) |
5354 | return IO_ACCEL_INELIGIBLE; | |
5355 | ||
03383736 | 5356 | c->phys_disk = dev->phys_disk[map_index]; |
c3390df4 DB |
5357 | if (!c->phys_disk) |
5358 | return IO_ACCEL_INELIGIBLE; | |
03383736 | 5359 | |
283b4a9b | 5360 | disk_handle = dd[map_index].ioaccel_handle; |
2b08b3e9 DB |
5361 | disk_block = le64_to_cpu(map->disk_starting_blk) + |
5362 | first_row * le16_to_cpu(map->strip_size) + | |
5363 | (first_row_offset - first_column * | |
5364 | le16_to_cpu(map->strip_size)); | |
283b4a9b SC |
5365 | disk_block_cnt = block_cnt; |
5366 | ||
5367 | /* handle differing logical/physical block sizes */ | |
5368 | if (map->phys_blk_shift) { | |
5369 | disk_block <<= map->phys_blk_shift; | |
5370 | disk_block_cnt <<= map->phys_blk_shift; | |
5371 | } | |
5372 | BUG_ON(disk_block_cnt > 0xffff); | |
5373 | ||
5374 | /* build the new CDB for the physical disk I/O */ | |
5375 | if (disk_block > 0xffffffff) { | |
5376 | cdb[0] = is_write ? WRITE_16 : READ_16; | |
5377 | cdb[1] = 0; | |
5378 | cdb[2] = (u8) (disk_block >> 56); | |
5379 | cdb[3] = (u8) (disk_block >> 48); | |
5380 | cdb[4] = (u8) (disk_block >> 40); | |
5381 | cdb[5] = (u8) (disk_block >> 32); | |
5382 | cdb[6] = (u8) (disk_block >> 24); | |
5383 | cdb[7] = (u8) (disk_block >> 16); | |
5384 | cdb[8] = (u8) (disk_block >> 8); | |
5385 | cdb[9] = (u8) (disk_block); | |
5386 | cdb[10] = (u8) (disk_block_cnt >> 24); | |
5387 | cdb[11] = (u8) (disk_block_cnt >> 16); | |
5388 | cdb[12] = (u8) (disk_block_cnt >> 8); | |
5389 | cdb[13] = (u8) (disk_block_cnt); | |
5390 | cdb[14] = 0; | |
5391 | cdb[15] = 0; | |
5392 | cdb_len = 16; | |
5393 | } else { | |
5394 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
5395 | cdb[1] = 0; | |
5396 | cdb[2] = (u8) (disk_block >> 24); | |
5397 | cdb[3] = (u8) (disk_block >> 16); | |
5398 | cdb[4] = (u8) (disk_block >> 8); | |
5399 | cdb[5] = (u8) (disk_block); | |
5400 | cdb[6] = 0; | |
5401 | cdb[7] = (u8) (disk_block_cnt >> 8); | |
5402 | cdb[8] = (u8) (disk_block_cnt); | |
5403 | cdb[9] = 0; | |
5404 | cdb_len = 10; | |
5405 | } | |
5406 | return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, | |
03383736 DB |
5407 | dev->scsi3addr, |
5408 | dev->phys_disk[map_index]); | |
283b4a9b SC |
5409 | } |
5410 | ||
25163bd5 WS |
5411 | /* |
5412 | * Submit commands down the "normal" RAID stack path | |
5413 | * All callers to hpsa_ciss_submit must check lockup_detected | |
5414 | * beforehand, before (opt.) and after calling cmd_alloc | |
5415 | */ | |
574f05d3 SC |
5416 | static int hpsa_ciss_submit(struct ctlr_info *h, |
5417 | struct CommandList *c, struct scsi_cmnd *cmd, | |
c5dfd106 | 5418 | struct hpsa_scsi_dev_t *dev) |
edd16368 | 5419 | { |
edd16368 | 5420 | cmd->host_scribble = (unsigned char *) c; |
edd16368 SC |
5421 | c->cmd_type = CMD_SCSI; |
5422 | c->scsi_cmd = cmd; | |
5423 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
c5dfd106 | 5424 | memcpy(&c->Header.LUN.LunAddrBytes[0], &dev->scsi3addr[0], 8); |
f2405db8 | 5425 | c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); |
edd16368 SC |
5426 | |
5427 | /* Fill in the request block... */ | |
5428 | ||
5429 | c->Request.Timeout = 0; | |
edd16368 SC |
5430 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); |
5431 | c->Request.CDBLen = cmd->cmd_len; | |
5432 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
edd16368 SC |
5433 | switch (cmd->sc_data_direction) { |
5434 | case DMA_TO_DEVICE: | |
a505b86f SC |
5435 | c->Request.type_attr_dir = |
5436 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
5437 | break; |
5438 | case DMA_FROM_DEVICE: | |
a505b86f SC |
5439 | c->Request.type_attr_dir = |
5440 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
5441 | break; |
5442 | case DMA_NONE: | |
a505b86f SC |
5443 | c->Request.type_attr_dir = |
5444 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
5445 | break; |
5446 | case DMA_BIDIRECTIONAL: | |
5447 | /* This can happen if a buggy application does a scsi passthru | |
5448 | * and sets both inlen and outlen to non-zero. ( see | |
5449 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
5450 | */ | |
5451 | ||
a505b86f SC |
5452 | c->Request.type_attr_dir = |
5453 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); | |
edd16368 SC |
5454 | /* This is technically wrong, and hpsa controllers should |
5455 | * reject it with CMD_INVALID, which is the most correct | |
5456 | * response, but non-fibre backends appear to let it | |
5457 | * slide by, and give the same results as if this field | |
5458 | * were set correctly. Either way is acceptable for | |
5459 | * our purposes here. | |
5460 | */ | |
5461 | ||
5462 | break; | |
5463 | ||
5464 | default: | |
5465 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
5466 | cmd->sc_data_direction); | |
5467 | BUG(); | |
5468 | break; | |
5469 | } | |
5470 | ||
33a2ffce | 5471 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
73153fe5 | 5472 | hpsa_cmd_resolve_and_free(h, c); |
edd16368 SC |
5473 | return SCSI_MLQUEUE_HOST_BUSY; |
5474 | } | |
c5dfd106 DB |
5475 | |
5476 | if (dev->in_reset) { | |
5477 | hpsa_cmd_resolve_and_free(h, c); | |
5478 | return SCSI_MLQUEUE_HOST_BUSY; | |
5479 | } | |
5480 | ||
ab76212e DB |
5481 | c->device = dev; |
5482 | ||
edd16368 SC |
5483 | enqueue_cmd_and_start_io(h, c); |
5484 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
5485 | return 0; | |
5486 | } | |
5487 | ||
360c73bd SC |
5488 | static void hpsa_cmd_init(struct ctlr_info *h, int index, |
5489 | struct CommandList *c) | |
5490 | { | |
5491 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
5492 | ||
5493 | /* Zero out all of commandlist except the last field, refcount */ | |
5494 | memset(c, 0, offsetof(struct CommandList, refcount)); | |
5495 | c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT)); | |
5496 | cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5497 | c->err_info = h->errinfo_pool + index; | |
5498 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5499 | err_dma_handle = h->errinfo_pool_dhandle | |
5500 | + index * sizeof(*c->err_info); | |
5501 | c->cmdindex = index; | |
5502 | c->busaddr = (u32) cmd_dma_handle; | |
5503 | c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); | |
5504 | c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); | |
5505 | c->h = h; | |
a58e7e53 | 5506 | c->scsi_cmd = SCSI_CMD_IDLE; |
360c73bd SC |
5507 | } |
5508 | ||
5509 | static void hpsa_preinitialize_commands(struct ctlr_info *h) | |
5510 | { | |
5511 | int i; | |
5512 | ||
5513 | for (i = 0; i < h->nr_cmds; i++) { | |
5514 | struct CommandList *c = h->cmd_pool + i; | |
5515 | ||
5516 | hpsa_cmd_init(h, i, c); | |
5517 | atomic_set(&c->refcount, 0); | |
5518 | } | |
5519 | } | |
5520 | ||
5521 | static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index, | |
5522 | struct CommandList *c) | |
5523 | { | |
5524 | dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c); | |
5525 | ||
73153fe5 WS |
5526 | BUG_ON(c->cmdindex != index); |
5527 | ||
360c73bd SC |
5528 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); |
5529 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
5530 | c->busaddr = (u32) cmd_dma_handle; | |
5531 | } | |
5532 | ||
592a0ad5 | 5533 | static int hpsa_ioaccel_submit(struct ctlr_info *h, |
c5dfd106 | 5534 | struct CommandList *c, struct scsi_cmnd *cmd) |
592a0ad5 WS |
5535 | { |
5536 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
5537 | int rc = IO_ACCEL_INELIGIBLE; | |
5538 | ||
45e596cd DB |
5539 | if (!dev) |
5540 | return SCSI_MLQUEUE_HOST_BUSY; | |
5541 | ||
c5dfd106 DB |
5542 | if (dev->in_reset) |
5543 | return SCSI_MLQUEUE_HOST_BUSY; | |
5544 | ||
a68fdb3a DB |
5545 | if (hpsa_simple_mode) |
5546 | return IO_ACCEL_INELIGIBLE; | |
5547 | ||
592a0ad5 WS |
5548 | cmd->host_scribble = (unsigned char *) c; |
5549 | ||
5550 | if (dev->offload_enabled) { | |
5551 | hpsa_cmd_init(h, c->cmdindex, c); | |
5552 | c->cmd_type = CMD_SCSI; | |
5553 | c->scsi_cmd = cmd; | |
ab76212e | 5554 | c->device = dev; |
592a0ad5 WS |
5555 | rc = hpsa_scsi_ioaccel_raid_map(h, c); |
5556 | if (rc < 0) /* scsi_dma_map failed. */ | |
5557 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
a3144e0b | 5558 | } else if (dev->hba_ioaccel_enabled) { |
592a0ad5 WS |
5559 | hpsa_cmd_init(h, c->cmdindex, c); |
5560 | c->cmd_type = CMD_SCSI; | |
5561 | c->scsi_cmd = cmd; | |
ab76212e | 5562 | c->device = dev; |
592a0ad5 WS |
5563 | rc = hpsa_scsi_ioaccel_direct_map(h, c); |
5564 | if (rc < 0) /* scsi_dma_map failed. */ | |
5565 | rc = SCSI_MLQUEUE_HOST_BUSY; | |
5566 | } | |
5567 | return rc; | |
5568 | } | |
5569 | ||
080ef1cc DB |
5570 | static void hpsa_command_resubmit_worker(struct work_struct *work) |
5571 | { | |
5572 | struct scsi_cmnd *cmd; | |
5573 | struct hpsa_scsi_dev_t *dev; | |
8a0ff92c | 5574 | struct CommandList *c = container_of(work, struct CommandList, work); |
080ef1cc DB |
5575 | |
5576 | cmd = c->scsi_cmd; | |
5577 | dev = cmd->device->hostdata; | |
5578 | if (!dev) { | |
5579 | cmd->result = DID_NO_CONNECT << 16; | |
8a0ff92c | 5580 | return hpsa_cmd_free_and_done(c->h, c, cmd); |
080ef1cc | 5581 | } |
c5dfd106 DB |
5582 | |
5583 | if (dev->in_reset) { | |
5584 | cmd->result = DID_RESET << 16; | |
d2315ce6 | 5585 | return hpsa_cmd_free_and_done(c->h, c, cmd); |
c5dfd106 DB |
5586 | } |
5587 | ||
592a0ad5 WS |
5588 | if (c->cmd_type == CMD_IOACCEL2) { |
5589 | struct ctlr_info *h = c->h; | |
5590 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
5591 | int rc; | |
5592 | ||
5593 | if (c2->error_data.serv_response == | |
5594 | IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) { | |
c5dfd106 | 5595 | rc = hpsa_ioaccel_submit(h, c, cmd); |
592a0ad5 WS |
5596 | if (rc == 0) |
5597 | return; | |
5598 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
5599 | /* | |
5600 | * If we get here, it means dma mapping failed. | |
5601 | * Try again via scsi mid layer, which will | |
5602 | * then get SCSI_MLQUEUE_HOST_BUSY. | |
5603 | */ | |
5604 | cmd->result = DID_IMM_RETRY << 16; | |
8a0ff92c | 5605 | return hpsa_cmd_free_and_done(h, c, cmd); |
592a0ad5 WS |
5606 | } |
5607 | /* else, fall thru and resubmit down CISS path */ | |
5608 | } | |
5609 | } | |
360c73bd | 5610 | hpsa_cmd_partial_init(c->h, c->cmdindex, c); |
c5dfd106 | 5611 | if (hpsa_ciss_submit(c->h, c, cmd, dev)) { |
080ef1cc DB |
5612 | /* |
5613 | * If we get here, it means dma mapping failed. Try | |
5614 | * again via scsi mid layer, which will then get | |
5615 | * SCSI_MLQUEUE_HOST_BUSY. | |
592a0ad5 WS |
5616 | * |
5617 | * hpsa_ciss_submit will have already freed c | |
5618 | * if it encountered a dma mapping failure. | |
080ef1cc DB |
5619 | */ |
5620 | cmd->result = DID_IMM_RETRY << 16; | |
5621 | cmd->scsi_done(cmd); | |
5622 | } | |
5623 | } | |
5624 | ||
574f05d3 SC |
5625 | /* Running in struct Scsi_Host->host_lock less mode */ |
5626 | static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) | |
5627 | { | |
5628 | struct ctlr_info *h; | |
5629 | struct hpsa_scsi_dev_t *dev; | |
574f05d3 SC |
5630 | struct CommandList *c; |
5631 | int rc = 0; | |
5632 | ||
5633 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
5634 | h = sdev_to_hba(cmd->device); | |
73153fe5 WS |
5635 | |
5636 | BUG_ON(cmd->request->tag < 0); | |
5637 | ||
574f05d3 SC |
5638 | dev = cmd->device->hostdata; |
5639 | if (!dev) { | |
1ccde700 | 5640 | cmd->result = DID_NO_CONNECT << 16; |
ba74fdc4 DB |
5641 | cmd->scsi_done(cmd); |
5642 | return 0; | |
5643 | } | |
5644 | ||
5645 | if (dev->removed) { | |
574f05d3 SC |
5646 | cmd->result = DID_NO_CONNECT << 16; |
5647 | cmd->scsi_done(cmd); | |
5648 | return 0; | |
5649 | } | |
574f05d3 | 5650 | |
407863cb | 5651 | if (unlikely(lockup_detected(h))) { |
25163bd5 | 5652 | cmd->result = DID_NO_CONNECT << 16; |
407863cb SC |
5653 | cmd->scsi_done(cmd); |
5654 | return 0; | |
5655 | } | |
c5dfd106 DB |
5656 | |
5657 | if (dev->in_reset) | |
5658 | return SCSI_MLQUEUE_DEVICE_BUSY; | |
5659 | ||
73153fe5 | 5660 | c = cmd_tagged_alloc(h, cmd); |
4770e68d DB |
5661 | if (c == NULL) |
5662 | return SCSI_MLQUEUE_DEVICE_BUSY; | |
574f05d3 | 5663 | |
eeebce18 DB |
5664 | /* |
5665 | * This is necessary because the SML doesn't zero out this field during | |
5666 | * error recovery. | |
5667 | */ | |
5668 | cmd->result = 0; | |
5669 | ||
407863cb SC |
5670 | /* |
5671 | * Call alternate submit routine for I/O accelerated commands. | |
574f05d3 SC |
5672 | * Retries always go down the normal I/O path. |
5673 | */ | |
5674 | if (likely(cmd->retries == 0 && | |
57292b58 CH |
5675 | !blk_rq_is_passthrough(cmd->request) && |
5676 | h->acciopath_status)) { | |
c5dfd106 | 5677 | rc = hpsa_ioaccel_submit(h, c, cmd); |
592a0ad5 WS |
5678 | if (rc == 0) |
5679 | return 0; | |
5680 | if (rc == SCSI_MLQUEUE_HOST_BUSY) { | |
73153fe5 | 5681 | hpsa_cmd_resolve_and_free(h, c); |
592a0ad5 | 5682 | return SCSI_MLQUEUE_HOST_BUSY; |
574f05d3 SC |
5683 | } |
5684 | } | |
c5dfd106 | 5685 | return hpsa_ciss_submit(h, c, cmd, dev); |
574f05d3 SC |
5686 | } |
5687 | ||
8ebc9248 | 5688 | static void hpsa_scan_complete(struct ctlr_info *h) |
5f389360 SC |
5689 | { |
5690 | unsigned long flags; | |
5691 | ||
8ebc9248 WS |
5692 | spin_lock_irqsave(&h->scan_lock, flags); |
5693 | h->scan_finished = 1; | |
87b9e6aa | 5694 | wake_up(&h->scan_wait_queue); |
8ebc9248 | 5695 | spin_unlock_irqrestore(&h->scan_lock, flags); |
5f389360 SC |
5696 | } |
5697 | ||
a08a8471 SC |
5698 | static void hpsa_scan_start(struct Scsi_Host *sh) |
5699 | { | |
5700 | struct ctlr_info *h = shost_to_hba(sh); | |
5701 | unsigned long flags; | |
5702 | ||
8ebc9248 WS |
5703 | /* |
5704 | * Don't let rescans be initiated on a controller known to be locked | |
5705 | * up. If the controller locks up *during* a rescan, that thread is | |
5706 | * probably hosed, but at least we can prevent new rescan threads from | |
5707 | * piling up on a locked up controller. | |
5708 | */ | |
5709 | if (unlikely(lockup_detected(h))) | |
5710 | return hpsa_scan_complete(h); | |
5f389360 | 5711 | |
87b9e6aa DB |
5712 | /* |
5713 | * If a scan is already waiting to run, no need to add another | |
5714 | */ | |
5715 | spin_lock_irqsave(&h->scan_lock, flags); | |
5716 | if (h->scan_waiting) { | |
5717 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5718 | return; | |
5719 | } | |
5720 | ||
5721 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5722 | ||
a08a8471 SC |
5723 | /* wait until any scan already in progress is finished. */ |
5724 | while (1) { | |
5725 | spin_lock_irqsave(&h->scan_lock, flags); | |
5726 | if (h->scan_finished) | |
5727 | break; | |
87b9e6aa | 5728 | h->scan_waiting = 1; |
a08a8471 SC |
5729 | spin_unlock_irqrestore(&h->scan_lock, flags); |
5730 | wait_event(h->scan_wait_queue, h->scan_finished); | |
5731 | /* Note: We don't need to worry about a race between this | |
5732 | * thread and driver unload because the midlayer will | |
5733 | * have incremented the reference count, so unload won't | |
5734 | * happen if we're in here. | |
5735 | */ | |
5736 | } | |
5737 | h->scan_finished = 0; /* mark scan as in progress */ | |
87b9e6aa | 5738 | h->scan_waiting = 0; |
a08a8471 SC |
5739 | spin_unlock_irqrestore(&h->scan_lock, flags); |
5740 | ||
8ebc9248 WS |
5741 | if (unlikely(lockup_detected(h))) |
5742 | return hpsa_scan_complete(h); | |
5f389360 | 5743 | |
bfd7546c DB |
5744 | /* |
5745 | * Do the scan after a reset completion | |
5746 | */ | |
c59d04f3 | 5747 | spin_lock_irqsave(&h->reset_lock, flags); |
bfd7546c DB |
5748 | if (h->reset_in_progress) { |
5749 | h->drv_req_rescan = 1; | |
c59d04f3 | 5750 | spin_unlock_irqrestore(&h->reset_lock, flags); |
3b476aa2 | 5751 | hpsa_scan_complete(h); |
bfd7546c DB |
5752 | return; |
5753 | } | |
c59d04f3 | 5754 | spin_unlock_irqrestore(&h->reset_lock, flags); |
bfd7546c | 5755 | |
8aa60681 | 5756 | hpsa_update_scsi_devices(h); |
a08a8471 | 5757 | |
8ebc9248 | 5758 | hpsa_scan_complete(h); |
a08a8471 SC |
5759 | } |
5760 | ||
7c0a0229 DB |
5761 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) |
5762 | { | |
03383736 DB |
5763 | struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; |
5764 | ||
5765 | if (!logical_drive) | |
5766 | return -ENODEV; | |
7c0a0229 DB |
5767 | |
5768 | if (qdepth < 1) | |
5769 | qdepth = 1; | |
03383736 DB |
5770 | else if (qdepth > logical_drive->queue_depth) |
5771 | qdepth = logical_drive->queue_depth; | |
5772 | ||
5773 | return scsi_change_queue_depth(sdev, qdepth); | |
7c0a0229 DB |
5774 | } |
5775 | ||
a08a8471 SC |
5776 | static int hpsa_scan_finished(struct Scsi_Host *sh, |
5777 | unsigned long elapsed_time) | |
5778 | { | |
5779 | struct ctlr_info *h = shost_to_hba(sh); | |
5780 | unsigned long flags; | |
5781 | int finished; | |
5782 | ||
5783 | spin_lock_irqsave(&h->scan_lock, flags); | |
5784 | finished = h->scan_finished; | |
5785 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
5786 | return finished; | |
5787 | } | |
5788 | ||
2946e82b | 5789 | static int hpsa_scsi_host_alloc(struct ctlr_info *h) |
edd16368 | 5790 | { |
b705690d | 5791 | struct Scsi_Host *sh; |
edd16368 | 5792 | |
b705690d | 5793 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
2946e82b RE |
5794 | if (sh == NULL) { |
5795 | dev_err(&h->pdev->dev, "scsi_host_alloc failed\n"); | |
5796 | return -ENOMEM; | |
5797 | } | |
b705690d SC |
5798 | |
5799 | sh->io_port = 0; | |
5800 | sh->n_io_port = 0; | |
5801 | sh->this_id = -1; | |
5802 | sh->max_channel = 3; | |
5803 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
5804 | sh->max_lun = HPSA_MAX_LUN; | |
5805 | sh->max_id = HPSA_MAX_LUN; | |
41ce4c35 | 5806 | sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS; |
03383736 | 5807 | sh->cmd_per_lun = sh->can_queue; |
b705690d | 5808 | sh->sg_tablesize = h->maxsgentries; |
d04e62b9 | 5809 | sh->transportt = hpsa_sas_transport_template; |
b705690d | 5810 | sh->hostdata[0] = (unsigned long) h; |
bc2bb154 | 5811 | sh->irq = pci_irq_vector(h->pdev, 0); |
b705690d | 5812 | sh->unique_id = sh->irq; |
64d513ac | 5813 | |
2946e82b | 5814 | h->scsi_host = sh; |
b705690d | 5815 | return 0; |
2946e82b | 5816 | } |
b705690d | 5817 | |
2946e82b RE |
5818 | static int hpsa_scsi_add_host(struct ctlr_info *h) |
5819 | { | |
5820 | int rv; | |
5821 | ||
5822 | rv = scsi_add_host(h->scsi_host, &h->pdev->dev); | |
5823 | if (rv) { | |
5824 | dev_err(&h->pdev->dev, "scsi_add_host failed\n"); | |
5825 | return rv; | |
5826 | } | |
5827 | scsi_scan_host(h->scsi_host); | |
5828 | return 0; | |
edd16368 SC |
5829 | } |
5830 | ||
73153fe5 WS |
5831 | /* |
5832 | * The block layer has already gone to the trouble of picking out a unique, | |
5833 | * small-integer tag for this request. We use an offset from that value as | |
5834 | * an index to select our command block. (The offset allows us to reserve the | |
5835 | * low-numbered entries for our own uses.) | |
5836 | */ | |
5837 | static int hpsa_get_cmd_index(struct scsi_cmnd *scmd) | |
5838 | { | |
5839 | int idx = scmd->request->tag; | |
5840 | ||
5841 | if (idx < 0) | |
5842 | return idx; | |
5843 | ||
5844 | /* Offset to leave space for internal cmds. */ | |
5845 | return idx += HPSA_NRESERVED_CMDS; | |
5846 | } | |
5847 | ||
b69324ff WS |
5848 | /* |
5849 | * Send a TEST_UNIT_READY command to the specified LUN using the specified | |
5850 | * reply queue; returns zero if the unit is ready, and non-zero otherwise. | |
5851 | */ | |
5852 | static int hpsa_send_test_unit_ready(struct ctlr_info *h, | |
5853 | struct CommandList *c, unsigned char lunaddr[], | |
5854 | int reply_queue) | |
5855 | { | |
5856 | int rc; | |
5857 | ||
5858 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ | |
5859 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
5860 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
1edb6934 | 5861 | rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT); |
b69324ff WS |
5862 | if (rc) |
5863 | return rc; | |
5864 | /* no unmap needed here because no data xfer. */ | |
5865 | ||
5866 | /* Check if the unit is already ready. */ | |
5867 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
5868 | return 0; | |
5869 | ||
5870 | /* | |
5871 | * The first command sent after reset will receive "unit attention" to | |
5872 | * indicate that the LUN has been reset...this is actually what we're | |
5873 | * looking for (but, success is good too). | |
5874 | */ | |
5875 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
5876 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
5877 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
5878 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
5879 | return 0; | |
5880 | ||
5881 | return 1; | |
5882 | } | |
5883 | ||
5884 | /* | |
5885 | * Wait for a TEST_UNIT_READY command to complete, retrying as necessary; | |
5886 | * returns zero when the unit is ready, and non-zero when giving up. | |
5887 | */ | |
5888 | static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h, | |
5889 | struct CommandList *c, | |
5890 | unsigned char lunaddr[], int reply_queue) | |
edd16368 | 5891 | { |
8919358e | 5892 | int rc; |
edd16368 SC |
5893 | int count = 0; |
5894 | int waittime = 1; /* seconds */ | |
edd16368 SC |
5895 | |
5896 | /* Send test unit ready until device ready, or give up. */ | |
b69324ff | 5897 | for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) { |
edd16368 | 5898 | |
b69324ff WS |
5899 | /* |
5900 | * Wait for a bit. do this first, because if we send | |
edd16368 SC |
5901 | * the TUR right away, the reset will just abort it. |
5902 | */ | |
5903 | msleep(1000 * waittime); | |
b69324ff WS |
5904 | |
5905 | rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue); | |
5906 | if (!rc) | |
5907 | break; | |
edd16368 SC |
5908 | |
5909 | /* Increase wait time with each try, up to a point. */ | |
5910 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
b69324ff | 5911 | waittime *= 2; |
edd16368 | 5912 | |
b69324ff WS |
5913 | dev_warn(&h->pdev->dev, |
5914 | "waiting %d secs for device to become ready.\n", | |
5915 | waittime); | |
5916 | } | |
edd16368 | 5917 | |
b69324ff WS |
5918 | return rc; |
5919 | } | |
edd16368 | 5920 | |
b69324ff WS |
5921 | static int wait_for_device_to_become_ready(struct ctlr_info *h, |
5922 | unsigned char lunaddr[], | |
5923 | int reply_queue) | |
5924 | { | |
5925 | int first_queue; | |
5926 | int last_queue; | |
5927 | int rq; | |
5928 | int rc = 0; | |
5929 | struct CommandList *c; | |
5930 | ||
5931 | c = cmd_alloc(h); | |
5932 | ||
5933 | /* | |
5934 | * If no specific reply queue was requested, then send the TUR | |
5935 | * repeatedly, requesting a reply on each reply queue; otherwise execute | |
5936 | * the loop exactly once using only the specified queue. | |
5937 | */ | |
5938 | if (reply_queue == DEFAULT_REPLY_QUEUE) { | |
5939 | first_queue = 0; | |
5940 | last_queue = h->nreply_queues - 1; | |
5941 | } else { | |
5942 | first_queue = reply_queue; | |
5943 | last_queue = reply_queue; | |
5944 | } | |
5945 | ||
5946 | for (rq = first_queue; rq <= last_queue; rq++) { | |
5947 | rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq); | |
5948 | if (rc) | |
edd16368 | 5949 | break; |
edd16368 SC |
5950 | } |
5951 | ||
5952 | if (rc) | |
5953 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
5954 | else | |
5955 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
5956 | ||
45fcb86e | 5957 | cmd_free(h, c); |
edd16368 SC |
5958 | return rc; |
5959 | } | |
5960 | ||
5961 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
5962 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
5963 | */ | |
5964 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
5965 | { | |
c59d04f3 | 5966 | int rc = SUCCESS; |
c5dfd106 | 5967 | int i; |
edd16368 | 5968 | struct ctlr_info *h; |
36631157 | 5969 | struct hpsa_scsi_dev_t *dev = NULL; |
0b9b7b6e | 5970 | u8 reset_type; |
2dc127bb | 5971 | char msg[48]; |
c59d04f3 | 5972 | unsigned long flags; |
edd16368 SC |
5973 | |
5974 | /* find the controller to which the command to be aborted was sent */ | |
5975 | h = sdev_to_hba(scsicmd->device); | |
5976 | if (h == NULL) /* paranoia */ | |
5977 | return FAILED; | |
e345893b | 5978 | |
c59d04f3 DB |
5979 | spin_lock_irqsave(&h->reset_lock, flags); |
5980 | h->reset_in_progress = 1; | |
5981 | spin_unlock_irqrestore(&h->reset_lock, flags); | |
5982 | ||
5983 | if (lockup_detected(h)) { | |
5984 | rc = FAILED; | |
5985 | goto return_reset_status; | |
5986 | } | |
e345893b | 5987 | |
edd16368 SC |
5988 | dev = scsicmd->device->hostdata; |
5989 | if (!dev) { | |
d604f533 | 5990 | dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__); |
c59d04f3 DB |
5991 | rc = FAILED; |
5992 | goto return_reset_status; | |
edd16368 | 5993 | } |
25163bd5 | 5994 | |
c59d04f3 DB |
5995 | if (dev->devtype == TYPE_ENCLOSURE) { |
5996 | rc = SUCCESS; | |
5997 | goto return_reset_status; | |
5998 | } | |
ef8a5203 | 5999 | |
25163bd5 WS |
6000 | /* if controller locked up, we can guarantee command won't complete */ |
6001 | if (lockup_detected(h)) { | |
2dc127bb DC |
6002 | snprintf(msg, sizeof(msg), |
6003 | "cmd %d RESET FAILED, lockup detected", | |
6004 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 6005 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
c59d04f3 DB |
6006 | rc = FAILED; |
6007 | goto return_reset_status; | |
25163bd5 WS |
6008 | } |
6009 | ||
6010 | /* this reset request might be the result of a lockup; check */ | |
6011 | if (detect_controller_lockup(h)) { | |
2dc127bb DC |
6012 | snprintf(msg, sizeof(msg), |
6013 | "cmd %d RESET FAILED, new lockup detected", | |
6014 | hpsa_get_cmd_index(scsicmd)); | |
73153fe5 | 6015 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
c59d04f3 DB |
6016 | rc = FAILED; |
6017 | goto return_reset_status; | |
25163bd5 WS |
6018 | } |
6019 | ||
d604f533 | 6020 | /* Do not attempt on controller */ |
c59d04f3 DB |
6021 | if (is_hba_lunid(dev->scsi3addr)) { |
6022 | rc = SUCCESS; | |
6023 | goto return_reset_status; | |
6024 | } | |
d604f533 | 6025 | |
0b9b7b6e ST |
6026 | if (is_logical_dev_addr_mode(dev->scsi3addr)) |
6027 | reset_type = HPSA_DEVICE_RESET_MSG; | |
6028 | else | |
6029 | reset_type = HPSA_PHYS_TARGET_RESET; | |
6030 | ||
6031 | sprintf(msg, "resetting %s", | |
6032 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical "); | |
6033 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); | |
25163bd5 | 6034 | |
c5dfd106 DB |
6035 | /* |
6036 | * wait to see if any commands will complete before sending reset | |
6037 | */ | |
6038 | dev->in_reset = true; /* block any new cmds from OS for this device */ | |
6039 | for (i = 0; i < 10; i++) { | |
6040 | if (atomic_read(&dev->commands_outstanding) > 0) | |
6041 | msleep(1000); | |
6042 | else | |
6043 | break; | |
6044 | } | |
6045 | ||
edd16368 | 6046 | /* send a reset to the SCSI LUN which the command was sent to */ |
c5dfd106 | 6047 | rc = hpsa_do_reset(h, dev, reset_type, DEFAULT_REPLY_QUEUE); |
c59d04f3 DB |
6048 | if (rc == 0) |
6049 | rc = SUCCESS; | |
6050 | else | |
6051 | rc = FAILED; | |
6052 | ||
0b9b7b6e ST |
6053 | sprintf(msg, "reset %s %s", |
6054 | reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ", | |
c59d04f3 | 6055 | rc == SUCCESS ? "completed successfully" : "failed"); |
d604f533 | 6056 | hpsa_show_dev_msg(KERN_WARNING, h, dev, msg); |
c59d04f3 DB |
6057 | |
6058 | return_reset_status: | |
6059 | spin_lock_irqsave(&h->reset_lock, flags); | |
da03ded0 | 6060 | h->reset_in_progress = 0; |
c5dfd106 DB |
6061 | if (dev) |
6062 | dev->in_reset = false; | |
c59d04f3 DB |
6063 | spin_unlock_irqrestore(&h->reset_lock, flags); |
6064 | return rc; | |
edd16368 SC |
6065 | } |
6066 | ||
73153fe5 WS |
6067 | /* |
6068 | * For operations with an associated SCSI command, a command block is allocated | |
6069 | * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the | |
6070 | * block request tag as an index into a table of entries. cmd_tagged_free() is | |
6071 | * the complement, although cmd_free() may be called instead. | |
6072 | */ | |
6073 | static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h, | |
6074 | struct scsi_cmnd *scmd) | |
6075 | { | |
6076 | int idx = hpsa_get_cmd_index(scmd); | |
6077 | struct CommandList *c = h->cmd_pool + idx; | |
6078 | ||
6079 | if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) { | |
6080 | dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n", | |
6081 | idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1); | |
6082 | /* The index value comes from the block layer, so if it's out of | |
6083 | * bounds, it's probably not our bug. | |
6084 | */ | |
6085 | BUG(); | |
6086 | } | |
6087 | ||
73153fe5 WS |
6088 | if (unlikely(!hpsa_is_cmd_idle(c))) { |
6089 | /* | |
6090 | * We expect that the SCSI layer will hand us a unique tag | |
6091 | * value. Thus, there should never be a collision here between | |
6092 | * two requests...because if the selected command isn't idle | |
6093 | * then someone is going to be very disappointed. | |
6094 | */ | |
4770e68d DB |
6095 | if (idx != h->last_collision_tag) { /* Print once per tag */ |
6096 | dev_warn(&h->pdev->dev, | |
6097 | "%s: tag collision (tag=%d)\n", __func__, idx); | |
4770e68d DB |
6098 | if (scmd) |
6099 | scsi_print_command(scmd); | |
6100 | h->last_collision_tag = idx; | |
6101 | } | |
6102 | return NULL; | |
73153fe5 WS |
6103 | } |
6104 | ||
4770e68d DB |
6105 | atomic_inc(&c->refcount); |
6106 | ||
73153fe5 WS |
6107 | hpsa_cmd_partial_init(h, idx, c); |
6108 | return c; | |
6109 | } | |
6110 | ||
6111 | static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c) | |
6112 | { | |
6113 | /* | |
6114 | * Release our reference to the block. We don't need to do anything | |
08ec46f6 | 6115 | * else to free it, because it is accessed by index. |
73153fe5 WS |
6116 | */ |
6117 | (void)atomic_dec(&c->refcount); | |
6118 | } | |
6119 | ||
edd16368 SC |
6120 | /* |
6121 | * For operations that cannot sleep, a command block is allocated at init, | |
6122 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
6123 | * which ones are free or in use. Lock must be held when calling this. | |
6124 | * cmd_free() is the complement. | |
bf43caf3 RE |
6125 | * This function never gives up and returns NULL. If it hangs, |
6126 | * another thread must call cmd_free() to free some tags. | |
edd16368 | 6127 | */ |
281a7fd0 | 6128 | |
edd16368 SC |
6129 | static struct CommandList *cmd_alloc(struct ctlr_info *h) |
6130 | { | |
6131 | struct CommandList *c; | |
360c73bd | 6132 | int refcount, i; |
73153fe5 | 6133 | int offset = 0; |
4c413128 | 6134 | |
33811026 RE |
6135 | /* |
6136 | * There is some *extremely* small but non-zero chance that that | |
4c413128 SC |
6137 | * multiple threads could get in here, and one thread could |
6138 | * be scanning through the list of bits looking for a free | |
6139 | * one, but the free ones are always behind him, and other | |
6140 | * threads sneak in behind him and eat them before he can | |
6141 | * get to them, so that while there is always a free one, a | |
6142 | * very unlucky thread might be starved anyway, never able to | |
6143 | * beat the other threads. In reality, this happens so | |
6144 | * infrequently as to be indistinguishable from never. | |
73153fe5 WS |
6145 | * |
6146 | * Note that we start allocating commands before the SCSI host structure | |
6147 | * is initialized. Since the search starts at bit zero, this | |
6148 | * all works, since we have at least one command structure available; | |
6149 | * however, it means that the structures with the low indexes have to be | |
6150 | * reserved for driver-initiated requests, while requests from the block | |
6151 | * layer will use the higher indexes. | |
4c413128 | 6152 | */ |
edd16368 | 6153 | |
281a7fd0 | 6154 | for (;;) { |
73153fe5 WS |
6155 | i = find_next_zero_bit(h->cmd_pool_bits, |
6156 | HPSA_NRESERVED_CMDS, | |
6157 | offset); | |
6158 | if (unlikely(i >= HPSA_NRESERVED_CMDS)) { | |
281a7fd0 WS |
6159 | offset = 0; |
6160 | continue; | |
6161 | } | |
6162 | c = h->cmd_pool + i; | |
6163 | refcount = atomic_inc_return(&c->refcount); | |
6164 | if (unlikely(refcount > 1)) { | |
6165 | cmd_free(h, c); /* already in use */ | |
73153fe5 | 6166 | offset = (i + 1) % HPSA_NRESERVED_CMDS; |
281a7fd0 WS |
6167 | continue; |
6168 | } | |
6169 | set_bit(i & (BITS_PER_LONG - 1), | |
6170 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6171 | break; /* it's ours now. */ | |
6172 | } | |
360c73bd | 6173 | hpsa_cmd_partial_init(h, i, c); |
c5dfd106 | 6174 | c->device = NULL; |
edd16368 SC |
6175 | return c; |
6176 | } | |
6177 | ||
73153fe5 WS |
6178 | /* |
6179 | * This is the complementary operation to cmd_alloc(). Note, however, in some | |
6180 | * corner cases it may also be used to free blocks allocated by | |
6181 | * cmd_tagged_alloc() in which case the ref-count decrement does the trick and | |
6182 | * the clear-bit is harmless. | |
6183 | */ | |
edd16368 SC |
6184 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) |
6185 | { | |
281a7fd0 WS |
6186 | if (atomic_dec_and_test(&c->refcount)) { |
6187 | int i; | |
edd16368 | 6188 | |
281a7fd0 WS |
6189 | i = c - h->cmd_pool; |
6190 | clear_bit(i & (BITS_PER_LONG - 1), | |
6191 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
6192 | } | |
edd16368 SC |
6193 | } |
6194 | ||
edd16368 SC |
6195 | #ifdef CONFIG_COMPAT |
6196 | ||
6f4e626f | 6197 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, unsigned int cmd, |
42a91641 | 6198 | void __user *arg) |
edd16368 SC |
6199 | { |
6200 | IOCTL32_Command_struct __user *arg32 = | |
6201 | (IOCTL32_Command_struct __user *) arg; | |
6202 | IOCTL_Command_struct arg64; | |
6203 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
6204 | int err; | |
6205 | u32 cp; | |
6206 | ||
938abd84 | 6207 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6208 | err = 0; |
6209 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6210 | sizeof(arg64.LUN_info)); | |
6211 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6212 | sizeof(arg64.Request)); | |
6213 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6214 | sizeof(arg64.error_info)); | |
6215 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6216 | err |= get_user(cp, &arg32->buf); | |
6217 | arg64.buf = compat_ptr(cp); | |
6218 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6219 | ||
6220 | if (err) | |
6221 | return -EFAULT; | |
6222 | ||
42a91641 | 6223 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); |
edd16368 SC |
6224 | if (err) |
6225 | return err; | |
6226 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6227 | sizeof(arg32->error_info)); | |
6228 | if (err) | |
6229 | return -EFAULT; | |
6230 | return err; | |
6231 | } | |
6232 | ||
6233 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
6f4e626f | 6234 | unsigned int cmd, void __user *arg) |
edd16368 SC |
6235 | { |
6236 | BIG_IOCTL32_Command_struct __user *arg32 = | |
6237 | (BIG_IOCTL32_Command_struct __user *) arg; | |
6238 | BIG_IOCTL_Command_struct arg64; | |
6239 | BIG_IOCTL_Command_struct __user *p = | |
6240 | compat_alloc_user_space(sizeof(arg64)); | |
6241 | int err; | |
6242 | u32 cp; | |
6243 | ||
938abd84 | 6244 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
6245 | err = 0; |
6246 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
6247 | sizeof(arg64.LUN_info)); | |
6248 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
6249 | sizeof(arg64.Request)); | |
6250 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
6251 | sizeof(arg64.error_info)); | |
6252 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
6253 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
6254 | err |= get_user(cp, &arg32->buf); | |
6255 | arg64.buf = compat_ptr(cp); | |
6256 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
6257 | ||
6258 | if (err) | |
6259 | return -EFAULT; | |
6260 | ||
42a91641 | 6261 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); |
edd16368 SC |
6262 | if (err) |
6263 | return err; | |
6264 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
6265 | sizeof(arg32->error_info)); | |
6266 | if (err) | |
6267 | return -EFAULT; | |
6268 | return err; | |
6269 | } | |
71fe75a7 | 6270 | |
6f4e626f NC |
6271 | static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd, |
6272 | void __user *arg) | |
71fe75a7 SC |
6273 | { |
6274 | switch (cmd) { | |
6275 | case CCISS_GETPCIINFO: | |
6276 | case CCISS_GETINTINFO: | |
6277 | case CCISS_SETINTINFO: | |
6278 | case CCISS_GETNODENAME: | |
6279 | case CCISS_SETNODENAME: | |
6280 | case CCISS_GETHEARTBEAT: | |
6281 | case CCISS_GETBUSTYPES: | |
6282 | case CCISS_GETFIRMVER: | |
6283 | case CCISS_GETDRIVVER: | |
6284 | case CCISS_REVALIDVOLS: | |
6285 | case CCISS_DEREGDISK: | |
6286 | case CCISS_REGNEWDISK: | |
6287 | case CCISS_REGNEWD: | |
6288 | case CCISS_RESCANDISK: | |
6289 | case CCISS_GETLUNINFO: | |
6290 | return hpsa_ioctl(dev, cmd, arg); | |
6291 | ||
6292 | case CCISS_PASSTHRU32: | |
6293 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
6294 | case CCISS_BIG_PASSTHRU32: | |
6295 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
6296 | ||
6297 | default: | |
6298 | return -ENOIOCTLCMD; | |
6299 | } | |
6300 | } | |
edd16368 SC |
6301 | #endif |
6302 | ||
6303 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
6304 | { | |
6305 | struct hpsa_pci_info pciinfo; | |
6306 | ||
6307 | if (!argp) | |
6308 | return -EINVAL; | |
6309 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
6310 | pciinfo.bus = h->pdev->bus->number; | |
6311 | pciinfo.dev_fn = h->pdev->devfn; | |
6312 | pciinfo.board_id = h->board_id; | |
6313 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
6314 | return -EFAULT; | |
6315 | return 0; | |
6316 | } | |
6317 | ||
6318 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
6319 | { | |
6320 | DriverVer_type DriverVer; | |
6321 | unsigned char vmaj, vmin, vsubmin; | |
6322 | int rc; | |
6323 | ||
6324 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
6325 | &vmaj, &vmin, &vsubmin); | |
6326 | if (rc != 3) { | |
6327 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
6328 | "unrecognized.", HPSA_DRIVER_VERSION); | |
6329 | vmaj = 0; | |
6330 | vmin = 0; | |
6331 | vsubmin = 0; | |
6332 | } | |
6333 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
6334 | if (!argp) | |
6335 | return -EINVAL; | |
6336 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
6337 | return -EFAULT; | |
6338 | return 0; | |
6339 | } | |
6340 | ||
6341 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6342 | { | |
6343 | IOCTL_Command_struct iocommand; | |
6344 | struct CommandList *c; | |
6345 | char *buff = NULL; | |
50a0decf | 6346 | u64 temp64; |
c1f63c8f | 6347 | int rc = 0; |
edd16368 SC |
6348 | |
6349 | if (!argp) | |
6350 | return -EINVAL; | |
6351 | if (!capable(CAP_SYS_RAWIO)) | |
6352 | return -EPERM; | |
6353 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
6354 | return -EFAULT; | |
6355 | if ((iocommand.buf_size < 1) && | |
6356 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
6357 | return -EINVAL; | |
6358 | } | |
6359 | if (iocommand.buf_size > 0) { | |
6360 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
6361 | if (buff == NULL) | |
2dd02d74 | 6362 | return -ENOMEM; |
9233fb10 | 6363 | if (iocommand.Request.Type.Direction & XFER_WRITE) { |
b03a7771 SC |
6364 | /* Copy the data into the buffer we created */ |
6365 | if (copy_from_user(buff, iocommand.buf, | |
6366 | iocommand.buf_size)) { | |
c1f63c8f SC |
6367 | rc = -EFAULT; |
6368 | goto out_kfree; | |
b03a7771 SC |
6369 | } |
6370 | } else { | |
6371 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 6372 | } |
b03a7771 | 6373 | } |
45fcb86e | 6374 | c = cmd_alloc(h); |
bf43caf3 | 6375 | |
edd16368 SC |
6376 | /* Fill in the command type */ |
6377 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6378 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6379 | /* Fill in Command Header */ |
6380 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
6381 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
6382 | c->Header.SGList = 1; | |
50a0decf | 6383 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6384 | } else { /* no buffers to fill */ |
6385 | c->Header.SGList = 0; | |
50a0decf | 6386 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 SC |
6387 | } |
6388 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
edd16368 SC |
6389 | |
6390 | /* Fill in Request block */ | |
6391 | memcpy(&c->Request, &iocommand.Request, | |
6392 | sizeof(c->Request)); | |
6393 | ||
6394 | /* Fill in the scatter gather information */ | |
6395 | if (iocommand.buf_size > 0) { | |
8bc8f47e CH |
6396 | temp64 = dma_map_single(&h->pdev->dev, buff, |
6397 | iocommand.buf_size, DMA_BIDIRECTIONAL); | |
50a0decf SC |
6398 | if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { |
6399 | c->SG[0].Addr = cpu_to_le64(0); | |
6400 | c->SG[0].Len = cpu_to_le32(0); | |
bcc48ffa SC |
6401 | rc = -ENOMEM; |
6402 | goto out; | |
6403 | } | |
50a0decf SC |
6404 | c->SG[0].Addr = cpu_to_le64(temp64); |
6405 | c->SG[0].Len = cpu_to_le32(iocommand.buf_size); | |
6406 | c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ | |
edd16368 | 6407 | } |
c448ecfa | 6408 | rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
3fb134cb | 6409 | NO_TIMEOUT); |
c2dd32e0 | 6410 | if (iocommand.buf_size > 0) |
8bc8f47e | 6411 | hpsa_pci_unmap(h->pdev, c, 1, DMA_BIDIRECTIONAL); |
edd16368 | 6412 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6413 | if (rc) { |
6414 | rc = -EIO; | |
6415 | goto out; | |
6416 | } | |
edd16368 SC |
6417 | |
6418 | /* Copy the error information out */ | |
6419 | memcpy(&iocommand.error_info, c->err_info, | |
6420 | sizeof(iocommand.error_info)); | |
6421 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
6422 | rc = -EFAULT; |
6423 | goto out; | |
edd16368 | 6424 | } |
9233fb10 | 6425 | if ((iocommand.Request.Type.Direction & XFER_READ) && |
b03a7771 | 6426 | iocommand.buf_size > 0) { |
edd16368 SC |
6427 | /* Copy the data out of the buffer we created */ |
6428 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
6429 | rc = -EFAULT; |
6430 | goto out; | |
edd16368 SC |
6431 | } |
6432 | } | |
c1f63c8f | 6433 | out: |
45fcb86e | 6434 | cmd_free(h, c); |
c1f63c8f SC |
6435 | out_kfree: |
6436 | kfree(buff); | |
6437 | return rc; | |
edd16368 SC |
6438 | } |
6439 | ||
6440 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
6441 | { | |
6442 | BIG_IOCTL_Command_struct *ioc; | |
6443 | struct CommandList *c; | |
6444 | unsigned char **buff = NULL; | |
6445 | int *buff_size = NULL; | |
50a0decf | 6446 | u64 temp64; |
edd16368 SC |
6447 | BYTE sg_used = 0; |
6448 | int status = 0; | |
01a02ffc SC |
6449 | u32 left; |
6450 | u32 sz; | |
edd16368 SC |
6451 | BYTE __user *data_ptr; |
6452 | ||
6453 | if (!argp) | |
6454 | return -EINVAL; | |
6455 | if (!capable(CAP_SYS_RAWIO)) | |
6456 | return -EPERM; | |
048a864e | 6457 | ioc = vmemdup_user(argp, sizeof(*ioc)); |
6458 | if (IS_ERR(ioc)) { | |
6459 | status = PTR_ERR(ioc); | |
edd16368 SC |
6460 | goto cleanup1; |
6461 | } | |
6462 | if ((ioc->buf_size < 1) && | |
6463 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
6464 | status = -EINVAL; | |
6465 | goto cleanup1; | |
6466 | } | |
6467 | /* Check kmalloc limits using all SGs */ | |
6468 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
6469 | status = -EINVAL; | |
6470 | goto cleanup1; | |
6471 | } | |
d66ae08b | 6472 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
6473 | status = -EINVAL; |
6474 | goto cleanup1; | |
6475 | } | |
6396bb22 | 6476 | buff = kcalloc(SG_ENTRIES_IN_CMD, sizeof(char *), GFP_KERNEL); |
edd16368 SC |
6477 | if (!buff) { |
6478 | status = -ENOMEM; | |
6479 | goto cleanup1; | |
6480 | } | |
6da2ec56 | 6481 | buff_size = kmalloc_array(SG_ENTRIES_IN_CMD, sizeof(int), GFP_KERNEL); |
edd16368 SC |
6482 | if (!buff_size) { |
6483 | status = -ENOMEM; | |
6484 | goto cleanup1; | |
6485 | } | |
6486 | left = ioc->buf_size; | |
6487 | data_ptr = ioc->buf; | |
6488 | while (left) { | |
6489 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
6490 | buff_size[sg_used] = sz; | |
6491 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
6492 | if (buff[sg_used] == NULL) { | |
6493 | status = -ENOMEM; | |
6494 | goto cleanup1; | |
6495 | } | |
9233fb10 | 6496 | if (ioc->Request.Type.Direction & XFER_WRITE) { |
edd16368 | 6497 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { |
0758f4f7 | 6498 | status = -EFAULT; |
edd16368 SC |
6499 | goto cleanup1; |
6500 | } | |
6501 | } else | |
6502 | memset(buff[sg_used], 0, sz); | |
6503 | left -= sz; | |
6504 | data_ptr += sz; | |
6505 | sg_used++; | |
6506 | } | |
45fcb86e | 6507 | c = cmd_alloc(h); |
bf43caf3 | 6508 | |
edd16368 | 6509 | c->cmd_type = CMD_IOCTL_PEND; |
a58e7e53 | 6510 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 | 6511 | c->Header.ReplyQueue = 0; |
50a0decf SC |
6512 | c->Header.SGList = (u8) sg_used; |
6513 | c->Header.SGTotal = cpu_to_le16(sg_used); | |
edd16368 | 6514 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
edd16368 SC |
6515 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); |
6516 | if (ioc->buf_size > 0) { | |
6517 | int i; | |
6518 | for (i = 0; i < sg_used; i++) { | |
8bc8f47e CH |
6519 | temp64 = dma_map_single(&h->pdev->dev, buff[i], |
6520 | buff_size[i], DMA_BIDIRECTIONAL); | |
50a0decf SC |
6521 | if (dma_mapping_error(&h->pdev->dev, |
6522 | (dma_addr_t) temp64)) { | |
6523 | c->SG[i].Addr = cpu_to_le64(0); | |
6524 | c->SG[i].Len = cpu_to_le32(0); | |
bcc48ffa | 6525 | hpsa_pci_unmap(h->pdev, c, i, |
8bc8f47e | 6526 | DMA_BIDIRECTIONAL); |
bcc48ffa | 6527 | status = -ENOMEM; |
e2d4a1f6 | 6528 | goto cleanup0; |
bcc48ffa | 6529 | } |
50a0decf SC |
6530 | c->SG[i].Addr = cpu_to_le64(temp64); |
6531 | c->SG[i].Len = cpu_to_le32(buff_size[i]); | |
6532 | c->SG[i].Ext = cpu_to_le32(0); | |
edd16368 | 6533 | } |
50a0decf | 6534 | c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); |
edd16368 | 6535 | } |
c448ecfa | 6536 | status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, |
3fb134cb | 6537 | NO_TIMEOUT); |
b03a7771 | 6538 | if (sg_used) |
8bc8f47e | 6539 | hpsa_pci_unmap(h->pdev, c, sg_used, DMA_BIDIRECTIONAL); |
edd16368 | 6540 | check_ioctl_unit_attention(h, c); |
25163bd5 WS |
6541 | if (status) { |
6542 | status = -EIO; | |
6543 | goto cleanup0; | |
6544 | } | |
6545 | ||
edd16368 SC |
6546 | /* Copy the error information out */ |
6547 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
6548 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 6549 | status = -EFAULT; |
e2d4a1f6 | 6550 | goto cleanup0; |
edd16368 | 6551 | } |
9233fb10 | 6552 | if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { |
2b08b3e9 DB |
6553 | int i; |
6554 | ||
edd16368 SC |
6555 | /* Copy the data out of the buffer we created */ |
6556 | BYTE __user *ptr = ioc->buf; | |
6557 | for (i = 0; i < sg_used; i++) { | |
6558 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 6559 | status = -EFAULT; |
e2d4a1f6 | 6560 | goto cleanup0; |
edd16368 SC |
6561 | } |
6562 | ptr += buff_size[i]; | |
6563 | } | |
6564 | } | |
edd16368 | 6565 | status = 0; |
e2d4a1f6 | 6566 | cleanup0: |
45fcb86e | 6567 | cmd_free(h, c); |
edd16368 SC |
6568 | cleanup1: |
6569 | if (buff) { | |
2b08b3e9 DB |
6570 | int i; |
6571 | ||
edd16368 SC |
6572 | for (i = 0; i < sg_used; i++) |
6573 | kfree(buff[i]); | |
6574 | kfree(buff); | |
6575 | } | |
6576 | kfree(buff_size); | |
048a864e | 6577 | kvfree(ioc); |
edd16368 SC |
6578 | return status; |
6579 | } | |
6580 | ||
6581 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
6582 | struct CommandList *c) | |
6583 | { | |
6584 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
6585 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
6586 | (void) check_for_unit_attention(h, c); | |
6587 | } | |
0390f0c0 | 6588 | |
edd16368 SC |
6589 | /* |
6590 | * ioctl | |
6591 | */ | |
6f4e626f NC |
6592 | static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd, |
6593 | void __user *arg) | |
edd16368 SC |
6594 | { |
6595 | struct ctlr_info *h; | |
6596 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 6597 | int rc; |
edd16368 SC |
6598 | |
6599 | h = sdev_to_hba(dev); | |
6600 | ||
6601 | switch (cmd) { | |
6602 | case CCISS_DEREGDISK: | |
6603 | case CCISS_REGNEWDISK: | |
6604 | case CCISS_REGNEWD: | |
a08a8471 | 6605 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
6606 | return 0; |
6607 | case CCISS_GETPCIINFO: | |
6608 | return hpsa_getpciinfo_ioctl(h, argp); | |
6609 | case CCISS_GETDRIVVER: | |
6610 | return hpsa_getdrivver_ioctl(h, argp); | |
6611 | case CCISS_PASSTHRU: | |
34f0c627 | 6612 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6613 | return -EAGAIN; |
6614 | rc = hpsa_passthru_ioctl(h, argp); | |
34f0c627 | 6615 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6616 | return rc; |
edd16368 | 6617 | case CCISS_BIG_PASSTHRU: |
34f0c627 | 6618 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
6619 | return -EAGAIN; |
6620 | rc = hpsa_big_passthru_ioctl(h, argp); | |
34f0c627 | 6621 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 6622 | return rc; |
edd16368 SC |
6623 | default: |
6624 | return -ENOTTY; | |
6625 | } | |
6626 | } | |
6627 | ||
c5dfd106 | 6628 | static void hpsa_send_host_reset(struct ctlr_info *h, u8 reset_type) |
64670ac8 SC |
6629 | { |
6630 | struct CommandList *c; | |
6631 | ||
6632 | c = cmd_alloc(h); | |
bf43caf3 | 6633 | |
a2dac136 SC |
6634 | /* fill_cmd can't fail here, no data buffer to map */ |
6635 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
6636 | RAID_CTLR_LUNID, TYPE_MSG); |
6637 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
6638 | c->waiting = NULL; | |
6639 | enqueue_cmd_and_start_io(h, c); | |
6640 | /* Don't wait for completion, the reset won't complete. Don't free | |
6641 | * the command either. This is the last command we will send before | |
6642 | * re-initializing everything, so it doesn't matter and won't leak. | |
6643 | */ | |
bf43caf3 | 6644 | return; |
64670ac8 SC |
6645 | } |
6646 | ||
a2dac136 | 6647 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 6648 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 SC |
6649 | int cmd_type) |
6650 | { | |
8bc8f47e | 6651 | enum dma_data_direction dir = DMA_NONE; |
edd16368 SC |
6652 | |
6653 | c->cmd_type = CMD_IOCTL_PEND; | |
a58e7e53 | 6654 | c->scsi_cmd = SCSI_CMD_BUSY; |
edd16368 SC |
6655 | c->Header.ReplyQueue = 0; |
6656 | if (buff != NULL && size > 0) { | |
6657 | c->Header.SGList = 1; | |
50a0decf | 6658 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
6659 | } else { |
6660 | c->Header.SGList = 0; | |
50a0decf | 6661 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 | 6662 | } |
edd16368 SC |
6663 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); |
6664 | ||
edd16368 SC |
6665 | if (cmd_type == TYPE_CMD) { |
6666 | switch (cmd) { | |
6667 | case HPSA_INQUIRY: | |
6668 | /* are we trying to read a vital product page */ | |
b7bb24eb | 6669 | if (page_code & VPD_PAGE) { |
edd16368 | 6670 | c->Request.CDB[1] = 0x01; |
b7bb24eb | 6671 | c->Request.CDB[2] = (page_code & 0xff); |
edd16368 SC |
6672 | } |
6673 | c->Request.CDBLen = 6; | |
a505b86f SC |
6674 | c->Request.type_attr_dir = |
6675 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6676 | c->Request.Timeout = 0; |
6677 | c->Request.CDB[0] = HPSA_INQUIRY; | |
6678 | c->Request.CDB[4] = size & 0xFF; | |
6679 | break; | |
0a7c3bb8 DB |
6680 | case RECEIVE_DIAGNOSTIC: |
6681 | c->Request.CDBLen = 6; | |
6682 | c->Request.type_attr_dir = | |
6683 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6684 | c->Request.Timeout = 0; | |
6685 | c->Request.CDB[0] = cmd; | |
6686 | c->Request.CDB[1] = 1; | |
6687 | c->Request.CDB[2] = 1; | |
6688 | c->Request.CDB[3] = (size >> 8) & 0xFF; | |
6689 | c->Request.CDB[4] = size & 0xFF; | |
6690 | break; | |
edd16368 SC |
6691 | case HPSA_REPORT_LOG: |
6692 | case HPSA_REPORT_PHYS: | |
6693 | /* Talking to controller so It's a physical command | |
6694 | mode = 00 target = 0. Nothing to write. | |
6695 | */ | |
6696 | c->Request.CDBLen = 12; | |
a505b86f SC |
6697 | c->Request.type_attr_dir = |
6698 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
6699 | c->Request.Timeout = 0; |
6700 | c->Request.CDB[0] = cmd; | |
6701 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6702 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6703 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6704 | c->Request.CDB[9] = size & 0xFF; | |
6705 | break; | |
c2adae44 ST |
6706 | case BMIC_SENSE_DIAG_OPTIONS: |
6707 | c->Request.CDBLen = 16; | |
6708 | c->Request.type_attr_dir = | |
6709 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6710 | c->Request.Timeout = 0; | |
6711 | /* Spec says this should be BMIC_WRITE */ | |
6712 | c->Request.CDB[0] = BMIC_READ; | |
6713 | c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS; | |
6714 | break; | |
6715 | case BMIC_SET_DIAG_OPTIONS: | |
6716 | c->Request.CDBLen = 16; | |
6717 | c->Request.type_attr_dir = | |
6718 | TYPE_ATTR_DIR(cmd_type, | |
6719 | ATTR_SIMPLE, XFER_WRITE); | |
6720 | c->Request.Timeout = 0; | |
6721 | c->Request.CDB[0] = BMIC_WRITE; | |
6722 | c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS; | |
6723 | break; | |
edd16368 SC |
6724 | case HPSA_CACHE_FLUSH: |
6725 | c->Request.CDBLen = 12; | |
a505b86f SC |
6726 | c->Request.type_attr_dir = |
6727 | TYPE_ATTR_DIR(cmd_type, | |
6728 | ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
6729 | c->Request.Timeout = 0; |
6730 | c->Request.CDB[0] = BMIC_WRITE; | |
6731 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
6732 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
6733 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
6734 | break; |
6735 | case TEST_UNIT_READY: | |
6736 | c->Request.CDBLen = 6; | |
a505b86f SC |
6737 | c->Request.type_attr_dir = |
6738 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
6739 | c->Request.Timeout = 0; |
6740 | break; | |
283b4a9b SC |
6741 | case HPSA_GET_RAID_MAP: |
6742 | c->Request.CDBLen = 12; | |
a505b86f SC |
6743 | c->Request.type_attr_dir = |
6744 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
283b4a9b SC |
6745 | c->Request.Timeout = 0; |
6746 | c->Request.CDB[0] = HPSA_CISS_READ; | |
6747 | c->Request.CDB[1] = cmd; | |
6748 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
6749 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6750 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6751 | c->Request.CDB[9] = size & 0xFF; | |
6752 | break; | |
316b221a SC |
6753 | case BMIC_SENSE_CONTROLLER_PARAMETERS: |
6754 | c->Request.CDBLen = 10; | |
a505b86f SC |
6755 | c->Request.type_attr_dir = |
6756 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
316b221a SC |
6757 | c->Request.Timeout = 0; |
6758 | c->Request.CDB[0] = BMIC_READ; | |
6759 | c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; | |
6760 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6761 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
6762 | break; | |
03383736 DB |
6763 | case BMIC_IDENTIFY_PHYSICAL_DEVICE: |
6764 | c->Request.CDBLen = 10; | |
6765 | c->Request.type_attr_dir = | |
6766 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6767 | c->Request.Timeout = 0; | |
6768 | c->Request.CDB[0] = BMIC_READ; | |
6769 | c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; | |
6770 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6771 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6772 | break; | |
d04e62b9 KB |
6773 | case BMIC_SENSE_SUBSYSTEM_INFORMATION: |
6774 | c->Request.CDBLen = 10; | |
6775 | c->Request.type_attr_dir = | |
6776 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6777 | c->Request.Timeout = 0; | |
6778 | c->Request.CDB[0] = BMIC_READ; | |
6779 | c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION; | |
6780 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6781 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6782 | break; | |
cca8f13b DB |
6783 | case BMIC_SENSE_STORAGE_BOX_PARAMS: |
6784 | c->Request.CDBLen = 10; | |
6785 | c->Request.type_attr_dir = | |
6786 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6787 | c->Request.Timeout = 0; | |
6788 | c->Request.CDB[0] = BMIC_READ; | |
6789 | c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS; | |
6790 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6791 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6792 | break; | |
66749d0d ST |
6793 | case BMIC_IDENTIFY_CONTROLLER: |
6794 | c->Request.CDBLen = 10; | |
6795 | c->Request.type_attr_dir = | |
6796 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
6797 | c->Request.Timeout = 0; | |
6798 | c->Request.CDB[0] = BMIC_READ; | |
6799 | c->Request.CDB[1] = 0; | |
6800 | c->Request.CDB[2] = 0; | |
6801 | c->Request.CDB[3] = 0; | |
6802 | c->Request.CDB[4] = 0; | |
6803 | c->Request.CDB[5] = 0; | |
6804 | c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER; | |
6805 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
6806 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
6807 | c->Request.CDB[9] = 0; | |
6808 | break; | |
edd16368 SC |
6809 | default: |
6810 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
6811 | BUG(); | |
edd16368 SC |
6812 | } |
6813 | } else if (cmd_type == TYPE_MSG) { | |
6814 | switch (cmd) { | |
6815 | ||
0b9b7b6e ST |
6816 | case HPSA_PHYS_TARGET_RESET: |
6817 | c->Request.CDBLen = 16; | |
6818 | c->Request.type_attr_dir = | |
6819 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
6820 | c->Request.Timeout = 0; /* Don't time out */ | |
6821 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); | |
6822 | c->Request.CDB[0] = HPSA_RESET; | |
6823 | c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE; | |
6824 | /* Physical target reset needs no control bytes 4-7*/ | |
6825 | c->Request.CDB[4] = 0x00; | |
6826 | c->Request.CDB[5] = 0x00; | |
6827 | c->Request.CDB[6] = 0x00; | |
6828 | c->Request.CDB[7] = 0x00; | |
6829 | break; | |
edd16368 SC |
6830 | case HPSA_DEVICE_RESET_MSG: |
6831 | c->Request.CDBLen = 16; | |
a505b86f SC |
6832 | c->Request.type_attr_dir = |
6833 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 | 6834 | c->Request.Timeout = 0; /* Don't time out */ |
64670ac8 SC |
6835 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
6836 | c->Request.CDB[0] = cmd; | |
21e89afd | 6837 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
6838 | /* If bytes 4-7 are zero, it means reset the */ |
6839 | /* LunID device */ | |
6840 | c->Request.CDB[4] = 0x00; | |
6841 | c->Request.CDB[5] = 0x00; | |
6842 | c->Request.CDB[6] = 0x00; | |
6843 | c->Request.CDB[7] = 0x00; | |
75167d2c | 6844 | break; |
edd16368 SC |
6845 | default: |
6846 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
6847 | cmd); | |
6848 | BUG(); | |
6849 | } | |
6850 | } else { | |
6851 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
6852 | BUG(); | |
6853 | } | |
6854 | ||
a505b86f | 6855 | switch (GET_DIR(c->Request.type_attr_dir)) { |
edd16368 | 6856 | case XFER_READ: |
8bc8f47e | 6857 | dir = DMA_FROM_DEVICE; |
edd16368 SC |
6858 | break; |
6859 | case XFER_WRITE: | |
8bc8f47e | 6860 | dir = DMA_TO_DEVICE; |
edd16368 SC |
6861 | break; |
6862 | case XFER_NONE: | |
8bc8f47e | 6863 | dir = DMA_NONE; |
edd16368 SC |
6864 | break; |
6865 | default: | |
8bc8f47e | 6866 | dir = DMA_BIDIRECTIONAL; |
edd16368 | 6867 | } |
8bc8f47e | 6868 | if (hpsa_map_one(h->pdev, c, buff, size, dir)) |
a2dac136 SC |
6869 | return -1; |
6870 | return 0; | |
edd16368 SC |
6871 | } |
6872 | ||
6873 | /* | |
6874 | * Map (physical) PCI mem into (virtual) kernel space | |
6875 | */ | |
6876 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
6877 | { | |
6878 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
6879 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
6880 | void __iomem *page_remapped = ioremap_nocache(page_base, |
6881 | page_offs + size); | |
edd16368 SC |
6882 | |
6883 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
6884 | } | |
6885 | ||
254f796b | 6886 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 6887 | { |
254f796b | 6888 | return h->access.command_completed(h, q); |
edd16368 SC |
6889 | } |
6890 | ||
900c5440 | 6891 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
6892 | { |
6893 | return h->access.intr_pending(h); | |
6894 | } | |
6895 | ||
6896 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
6897 | { | |
10f66018 SC |
6898 | return (h->access.intr_pending(h) == 0) || |
6899 | (h->interrupts_enabled == 0); | |
edd16368 SC |
6900 | } |
6901 | ||
01a02ffc SC |
6902 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
6903 | u32 raw_tag) | |
edd16368 SC |
6904 | { |
6905 | if (unlikely(tag_index >= h->nr_cmds)) { | |
6906 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
6907 | return 1; | |
6908 | } | |
6909 | return 0; | |
6910 | } | |
6911 | ||
5a3d16f5 | 6912 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 6913 | { |
e85c5974 | 6914 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
c349775e ST |
6915 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI |
6916 | || c->cmd_type == CMD_IOACCEL2)) | |
1fb011fb | 6917 | complete_scsi_command(c); |
8be986cc | 6918 | else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF) |
edd16368 | 6919 | complete(c->waiting); |
a104c99f SC |
6920 | } |
6921 | ||
303932fd | 6922 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 6923 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
6924 | u32 raw_tag) |
6925 | { | |
6926 | u32 tag_index; | |
6927 | struct CommandList *c; | |
6928 | ||
f2405db8 | 6929 | tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; |
1d94f94d SC |
6930 | if (!bad_tag(h, tag_index, raw_tag)) { |
6931 | c = h->cmd_pool + tag_index; | |
6932 | finish_cmd(c); | |
6933 | } | |
303932fd DB |
6934 | } |
6935 | ||
64670ac8 SC |
6936 | /* Some controllers, like p400, will give us one interrupt |
6937 | * after a soft reset, even if we turned interrupts off. | |
6938 | * Only need to check for this in the hpsa_xxx_discard_completions | |
6939 | * functions. | |
6940 | */ | |
6941 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
6942 | { | |
6943 | if (likely(!reset_devices)) | |
6944 | return 0; | |
6945 | ||
6946 | if (likely(h->interrupts_enabled)) | |
6947 | return 0; | |
6948 | ||
6949 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
6950 | "(known firmware bug.) Ignoring.\n"); | |
6951 | ||
6952 | return 1; | |
6953 | } | |
6954 | ||
254f796b MG |
6955 | /* |
6956 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
6957 | * Relies on (h-q[x] == x) being true for x such that | |
6958 | * 0 <= x < MAX_REPLY_QUEUES. | |
6959 | */ | |
6960 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 6961 | { |
254f796b MG |
6962 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
6963 | } | |
6964 | ||
6965 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
6966 | { | |
6967 | struct ctlr_info *h = queue_to_hba(queue); | |
6968 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
6969 | u32 raw_tag; |
6970 | ||
6971 | if (ignore_bogus_interrupt(h)) | |
6972 | return IRQ_NONE; | |
6973 | ||
6974 | if (interrupt_not_for_us(h)) | |
6975 | return IRQ_NONE; | |
a0c12413 | 6976 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 6977 | while (interrupt_pending(h)) { |
254f796b | 6978 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6979 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6980 | raw_tag = next_command(h, q); |
64670ac8 | 6981 | } |
64670ac8 SC |
6982 | return IRQ_HANDLED; |
6983 | } | |
6984 | ||
254f796b | 6985 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 6986 | { |
254f796b | 6987 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 6988 | u32 raw_tag; |
254f796b | 6989 | u8 q = *(u8 *) queue; |
64670ac8 SC |
6990 | |
6991 | if (ignore_bogus_interrupt(h)) | |
6992 | return IRQ_NONE; | |
6993 | ||
a0c12413 | 6994 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 6995 | raw_tag = get_next_completion(h, q); |
64670ac8 | 6996 | while (raw_tag != FIFO_EMPTY) |
254f796b | 6997 | raw_tag = next_command(h, q); |
64670ac8 SC |
6998 | return IRQ_HANDLED; |
6999 | } | |
7000 | ||
254f796b | 7001 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 7002 | { |
254f796b | 7003 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 7004 | u32 raw_tag; |
254f796b | 7005 | u8 q = *(u8 *) queue; |
edd16368 SC |
7006 | |
7007 | if (interrupt_not_for_us(h)) | |
7008 | return IRQ_NONE; | |
a0c12413 | 7009 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 7010 | while (interrupt_pending(h)) { |
254f796b | 7011 | raw_tag = get_next_completion(h, q); |
10f66018 | 7012 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 7013 | process_indexed_cmd(h, raw_tag); |
254f796b | 7014 | raw_tag = next_command(h, q); |
10f66018 SC |
7015 | } |
7016 | } | |
10f66018 SC |
7017 | return IRQ_HANDLED; |
7018 | } | |
7019 | ||
254f796b | 7020 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 7021 | { |
254f796b | 7022 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 7023 | u32 raw_tag; |
254f796b | 7024 | u8 q = *(u8 *) queue; |
10f66018 | 7025 | |
a0c12413 | 7026 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 7027 | raw_tag = get_next_completion(h, q); |
303932fd | 7028 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 7029 | process_indexed_cmd(h, raw_tag); |
254f796b | 7030 | raw_tag = next_command(h, q); |
edd16368 | 7031 | } |
edd16368 SC |
7032 | return IRQ_HANDLED; |
7033 | } | |
7034 | ||
a9a3a273 SC |
7035 | /* Send a message CDB to the firmware. Careful, this only works |
7036 | * in simple mode, not performant mode due to the tag lookup. | |
7037 | * We only ever use this immediately after a controller reset. | |
7038 | */ | |
6f039790 GKH |
7039 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
7040 | unsigned char type) | |
edd16368 SC |
7041 | { |
7042 | struct Command { | |
7043 | struct CommandListHeader CommandHeader; | |
7044 | struct RequestBlock Request; | |
7045 | struct ErrDescriptor ErrorDescriptor; | |
7046 | }; | |
7047 | struct Command *cmd; | |
7048 | static const size_t cmd_sz = sizeof(*cmd) + | |
7049 | sizeof(cmd->ErrorDescriptor); | |
7050 | dma_addr_t paddr64; | |
2b08b3e9 DB |
7051 | __le32 paddr32; |
7052 | u32 tag; | |
edd16368 SC |
7053 | void __iomem *vaddr; |
7054 | int i, err; | |
7055 | ||
7056 | vaddr = pci_ioremap_bar(pdev, 0); | |
7057 | if (vaddr == NULL) | |
7058 | return -ENOMEM; | |
7059 | ||
7060 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
7061 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
7062 | * memory. | |
7063 | */ | |
8bc8f47e | 7064 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
edd16368 SC |
7065 | if (err) { |
7066 | iounmap(vaddr); | |
1eaec8f3 | 7067 | return err; |
edd16368 SC |
7068 | } |
7069 | ||
8bc8f47e | 7070 | cmd = dma_alloc_coherent(&pdev->dev, cmd_sz, &paddr64, GFP_KERNEL); |
edd16368 SC |
7071 | if (cmd == NULL) { |
7072 | iounmap(vaddr); | |
7073 | return -ENOMEM; | |
7074 | } | |
7075 | ||
7076 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
7077 | * although there's no guarantee, we assume that the address is at | |
7078 | * least 4-byte aligned (most likely, it's page-aligned). | |
7079 | */ | |
2b08b3e9 | 7080 | paddr32 = cpu_to_le32(paddr64); |
edd16368 SC |
7081 | |
7082 | cmd->CommandHeader.ReplyQueue = 0; | |
7083 | cmd->CommandHeader.SGList = 0; | |
50a0decf | 7084 | cmd->CommandHeader.SGTotal = cpu_to_le16(0); |
2b08b3e9 | 7085 | cmd->CommandHeader.tag = cpu_to_le64(paddr64); |
edd16368 SC |
7086 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); |
7087 | ||
7088 | cmd->Request.CDBLen = 16; | |
a505b86f SC |
7089 | cmd->Request.type_attr_dir = |
7090 | TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); | |
edd16368 SC |
7091 | cmd->Request.Timeout = 0; /* Don't time out */ |
7092 | cmd->Request.CDB[0] = opcode; | |
7093 | cmd->Request.CDB[1] = type; | |
7094 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
50a0decf | 7095 | cmd->ErrorDescriptor.Addr = |
2b08b3e9 | 7096 | cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); |
50a0decf | 7097 | cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); |
edd16368 | 7098 | |
2b08b3e9 | 7099 | writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); |
edd16368 SC |
7100 | |
7101 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
7102 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
2b08b3e9 | 7103 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) |
edd16368 SC |
7104 | break; |
7105 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
7106 | } | |
7107 | ||
7108 | iounmap(vaddr); | |
7109 | ||
7110 | /* we leak the DMA buffer here ... no choice since the controller could | |
7111 | * still complete the command. | |
7112 | */ | |
7113 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
7114 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
7115 | opcode, type); | |
7116 | return -ETIMEDOUT; | |
7117 | } | |
7118 | ||
8bc8f47e | 7119 | dma_free_coherent(&pdev->dev, cmd_sz, cmd, paddr64); |
edd16368 SC |
7120 | |
7121 | if (tag & HPSA_ERROR_BIT) { | |
7122 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
7123 | opcode, type); | |
7124 | return -EIO; | |
7125 | } | |
7126 | ||
7127 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
7128 | opcode, type); | |
7129 | return 0; | |
7130 | } | |
7131 | ||
edd16368 SC |
7132 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
7133 | ||
1df8552a | 7134 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
42a91641 | 7135 | void __iomem *vaddr, u32 use_doorbell) |
1df8552a | 7136 | { |
1df8552a SC |
7137 | |
7138 | if (use_doorbell) { | |
7139 | /* For everything after the P600, the PCI power state method | |
7140 | * of resetting the controller doesn't work, so we have this | |
7141 | * other way using the doorbell register. | |
7142 | */ | |
7143 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 7144 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 | 7145 | |
00701a96 | 7146 | /* PMC hardware guys tell us we need a 10 second delay after |
85009239 SC |
7147 | * doorbell reset and before any attempt to talk to the board |
7148 | * at all to ensure that this actually works and doesn't fall | |
7149 | * over in some weird corner cases. | |
7150 | */ | |
00701a96 | 7151 | msleep(10000); |
1df8552a SC |
7152 | } else { /* Try to do it the PCI power state way */ |
7153 | ||
7154 | /* Quoting from the Open CISS Specification: "The Power | |
7155 | * Management Control/Status Register (CSR) controls the power | |
7156 | * state of the device. The normal operating state is D0, | |
7157 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
7158 | * the controller, place the interface device in D3 then to D0, | |
7159 | * this causes a secondary PCI reset which will reset the | |
7160 | * controller." */ | |
2662cab8 DB |
7161 | |
7162 | int rc = 0; | |
7163 | ||
1df8552a | 7164 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); |
2662cab8 | 7165 | |
1df8552a | 7166 | /* enter the D3hot power management state */ |
2662cab8 DB |
7167 | rc = pci_set_power_state(pdev, PCI_D3hot); |
7168 | if (rc) | |
7169 | return rc; | |
1df8552a SC |
7170 | |
7171 | msleep(500); | |
7172 | ||
7173 | /* enter the D0 power management state */ | |
2662cab8 DB |
7174 | rc = pci_set_power_state(pdev, PCI_D0); |
7175 | if (rc) | |
7176 | return rc; | |
c4853efe MM |
7177 | |
7178 | /* | |
7179 | * The P600 requires a small delay when changing states. | |
7180 | * Otherwise we may think the board did not reset and we bail. | |
7181 | * This for kdump only and is particular to the P600. | |
7182 | */ | |
7183 | msleep(500); | |
1df8552a SC |
7184 | } |
7185 | return 0; | |
7186 | } | |
7187 | ||
6f039790 | 7188 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
7189 | { |
7190 | memset(driver_version, 0, len); | |
f79cfec6 | 7191 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
7192 | } |
7193 | ||
6f039790 | 7194 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7195 | { |
7196 | char *driver_version; | |
7197 | int i, size = sizeof(cfgtable->driver_version); | |
7198 | ||
7199 | driver_version = kmalloc(size, GFP_KERNEL); | |
7200 | if (!driver_version) | |
7201 | return -ENOMEM; | |
7202 | ||
7203 | init_driver_version(driver_version, size); | |
7204 | for (i = 0; i < size; i++) | |
7205 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
7206 | kfree(driver_version); | |
7207 | return 0; | |
7208 | } | |
7209 | ||
6f039790 GKH |
7210 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
7211 | unsigned char *driver_ver) | |
580ada3c SC |
7212 | { |
7213 | int i; | |
7214 | ||
7215 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
7216 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
7217 | } | |
7218 | ||
6f039790 | 7219 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
7220 | { |
7221 | ||
7222 | char *driver_ver, *old_driver_ver; | |
7223 | int rc, size = sizeof(cfgtable->driver_version); | |
7224 | ||
6da2ec56 | 7225 | old_driver_ver = kmalloc_array(2, size, GFP_KERNEL); |
580ada3c SC |
7226 | if (!old_driver_ver) |
7227 | return -ENOMEM; | |
7228 | driver_ver = old_driver_ver + size; | |
7229 | ||
7230 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
7231 | * should have been changed, otherwise we know the reset failed. | |
7232 | */ | |
7233 | init_driver_version(old_driver_ver, size); | |
7234 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
7235 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
7236 | kfree(old_driver_ver); | |
7237 | return rc; | |
7238 | } | |
edd16368 | 7239 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 7240 | * states or the using the doorbell register. |
edd16368 | 7241 | */ |
6b6c1cd7 | 7242 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id) |
edd16368 | 7243 | { |
1df8552a SC |
7244 | u64 cfg_offset; |
7245 | u32 cfg_base_addr; | |
7246 | u64 cfg_base_addr_index; | |
7247 | void __iomem *vaddr; | |
7248 | unsigned long paddr; | |
580ada3c | 7249 | u32 misc_fw_support; |
270d05de | 7250 | int rc; |
1df8552a | 7251 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 7252 | u32 use_doorbell; |
270d05de | 7253 | u16 command_register; |
edd16368 | 7254 | |
1df8552a SC |
7255 | /* For controllers as old as the P600, this is very nearly |
7256 | * the same thing as | |
edd16368 SC |
7257 | * |
7258 | * pci_save_state(pci_dev); | |
7259 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
7260 | * pci_set_power_state(pci_dev, PCI_D0); | |
7261 | * pci_restore_state(pci_dev); | |
7262 | * | |
1df8552a SC |
7263 | * For controllers newer than the P600, the pci power state |
7264 | * method of resetting doesn't work so we have another way | |
7265 | * using the doorbell register. | |
edd16368 | 7266 | */ |
18867659 | 7267 | |
60f923b9 RE |
7268 | if (!ctlr_is_resettable(board_id)) { |
7269 | dev_warn(&pdev->dev, "Controller not resettable\n"); | |
25c1e56a SC |
7270 | return -ENODEV; |
7271 | } | |
46380786 SC |
7272 | |
7273 | /* if controller is soft- but not hard resettable... */ | |
7274 | if (!ctlr_is_hard_resettable(board_id)) | |
7275 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 7276 | |
270d05de SC |
7277 | /* Save the PCI command register */ |
7278 | pci_read_config_word(pdev, 4, &command_register); | |
270d05de | 7279 | pci_save_state(pdev); |
edd16368 | 7280 | |
1df8552a SC |
7281 | /* find the first memory BAR, so we can find the cfg table */ |
7282 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
7283 | if (rc) | |
7284 | return rc; | |
7285 | vaddr = remap_pci_mem(paddr, 0x250); | |
7286 | if (!vaddr) | |
7287 | return -ENOMEM; | |
edd16368 | 7288 | |
1df8552a SC |
7289 | /* find cfgtable in order to check if reset via doorbell is supported */ |
7290 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
7291 | &cfg_base_addr_index, &cfg_offset); | |
7292 | if (rc) | |
7293 | goto unmap_vaddr; | |
7294 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
7295 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
7296 | if (!cfgtable) { | |
7297 | rc = -ENOMEM; | |
7298 | goto unmap_vaddr; | |
7299 | } | |
580ada3c SC |
7300 | rc = write_driver_ver_to_cfgtable(cfgtable); |
7301 | if (rc) | |
03741d95 | 7302 | goto unmap_cfgtable; |
edd16368 | 7303 | |
cf0b08d0 SC |
7304 | /* If reset via doorbell register is supported, use that. |
7305 | * There are two such methods. Favor the newest method. | |
7306 | */ | |
1df8552a | 7307 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
7308 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
7309 | if (use_doorbell) { | |
7310 | use_doorbell = DOORBELL_CTLR_RESET2; | |
7311 | } else { | |
7312 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
7313 | if (use_doorbell) { | |
050f7147 SC |
7314 | dev_warn(&pdev->dev, |
7315 | "Soft reset not supported. Firmware update is required.\n"); | |
64670ac8 | 7316 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
7317 | goto unmap_cfgtable; |
7318 | } | |
7319 | } | |
edd16368 | 7320 | |
1df8552a SC |
7321 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
7322 | if (rc) | |
7323 | goto unmap_cfgtable; | |
edd16368 | 7324 | |
270d05de | 7325 | pci_restore_state(pdev); |
270d05de | 7326 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 7327 | |
1df8552a SC |
7328 | /* Some devices (notably the HP Smart Array 5i Controller) |
7329 | need a little pause here */ | |
7330 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
7331 | ||
fe5389c8 SC |
7332 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
7333 | if (rc) { | |
7334 | dev_warn(&pdev->dev, | |
050f7147 | 7335 | "Failed waiting for board to become ready after hard reset\n"); |
fe5389c8 SC |
7336 | goto unmap_cfgtable; |
7337 | } | |
fe5389c8 | 7338 | |
580ada3c SC |
7339 | rc = controller_reset_failed(vaddr); |
7340 | if (rc < 0) | |
7341 | goto unmap_cfgtable; | |
7342 | if (rc) { | |
64670ac8 SC |
7343 | dev_warn(&pdev->dev, "Unable to successfully reset " |
7344 | "controller. Will try soft reset.\n"); | |
7345 | rc = -ENOTSUPP; | |
580ada3c | 7346 | } else { |
64670ac8 | 7347 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
7348 | } |
7349 | ||
7350 | unmap_cfgtable: | |
7351 | iounmap(cfgtable); | |
7352 | ||
7353 | unmap_vaddr: | |
7354 | iounmap(vaddr); | |
7355 | return rc; | |
edd16368 SC |
7356 | } |
7357 | ||
7358 | /* | |
7359 | * We cannot read the structure directly, for portability we must use | |
7360 | * the io functions. | |
7361 | * This is for debug only. | |
7362 | */ | |
42a91641 | 7363 | static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) |
edd16368 | 7364 | { |
58f8665c | 7365 | #ifdef HPSA_DEBUG |
edd16368 SC |
7366 | int i; |
7367 | char temp_name[17]; | |
7368 | ||
7369 | dev_info(dev, "Controller Configuration information\n"); | |
7370 | dev_info(dev, "------------------------------------\n"); | |
7371 | for (i = 0; i < 4; i++) | |
7372 | temp_name[i] = readb(&(tb->Signature[i])); | |
7373 | temp_name[4] = '\0'; | |
7374 | dev_info(dev, " Signature = %s\n", temp_name); | |
7375 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
7376 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
7377 | readl(&(tb->TransportSupport))); | |
7378 | dev_info(dev, " Transport methods active = 0x%x\n", | |
7379 | readl(&(tb->TransportActive))); | |
7380 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
7381 | readl(&(tb->HostWrite.TransportRequest))); | |
7382 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
7383 | readl(&(tb->HostWrite.CoalIntDelay))); | |
7384 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
7385 | readl(&(tb->HostWrite.CoalIntCount))); | |
69d6e33d | 7386 | dev_info(dev, " Max outstanding commands = %d\n", |
edd16368 SC |
7387 | readl(&(tb->CmdsOutMax))); |
7388 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
7389 | for (i = 0; i < 16; i++) | |
7390 | temp_name[i] = readb(&(tb->ServerName[i])); | |
7391 | temp_name[16] = '\0'; | |
7392 | dev_info(dev, " Server Name = %s\n", temp_name); | |
7393 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
7394 | readl(&(tb->HeartBeat))); | |
edd16368 | 7395 | #endif /* HPSA_DEBUG */ |
58f8665c | 7396 | } |
edd16368 SC |
7397 | |
7398 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
7399 | { | |
7400 | int i, offset, mem_type, bar_type; | |
7401 | ||
7402 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
7403 | return 0; | |
7404 | offset = 0; | |
7405 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
7406 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
7407 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
7408 | offset += 4; | |
7409 | else { | |
7410 | mem_type = pci_resource_flags(pdev, i) & | |
7411 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
7412 | switch (mem_type) { | |
7413 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
7414 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
7415 | offset += 4; /* 32 bit */ | |
7416 | break; | |
7417 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
7418 | offset += 8; | |
7419 | break; | |
7420 | default: /* reserved in PCI 2.2 */ | |
7421 | dev_warn(&pdev->dev, | |
7422 | "base address is invalid\n"); | |
7423 | return -1; | |
7424 | break; | |
7425 | } | |
7426 | } | |
7427 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
7428 | return i + 1; | |
7429 | } | |
7430 | return -1; | |
7431 | } | |
7432 | ||
cc64c817 RE |
7433 | static void hpsa_disable_interrupt_mode(struct ctlr_info *h) |
7434 | { | |
bc2bb154 CH |
7435 | pci_free_irq_vectors(h->pdev); |
7436 | h->msix_vectors = 0; | |
cc64c817 RE |
7437 | } |
7438 | ||
8b834bff ML |
7439 | static void hpsa_setup_reply_map(struct ctlr_info *h) |
7440 | { | |
7441 | const struct cpumask *mask; | |
7442 | unsigned int queue, cpu; | |
7443 | ||
7444 | for (queue = 0; queue < h->msix_vectors; queue++) { | |
7445 | mask = pci_irq_get_affinity(h->pdev, queue); | |
7446 | if (!mask) | |
7447 | goto fallback; | |
7448 | ||
7449 | for_each_cpu(cpu, mask) | |
7450 | h->reply_map[cpu] = queue; | |
7451 | } | |
7452 | return; | |
7453 | ||
7454 | fallback: | |
7455 | for_each_possible_cpu(cpu) | |
7456 | h->reply_map[cpu] = 0; | |
7457 | } | |
7458 | ||
edd16368 | 7459 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on |
050f7147 | 7460 | * controllers that are capable. If not, we use legacy INTx mode. |
edd16368 | 7461 | */ |
bc2bb154 | 7462 | static int hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 | 7463 | { |
bc2bb154 CH |
7464 | unsigned int flags = PCI_IRQ_LEGACY; |
7465 | int ret; | |
edd16368 SC |
7466 | |
7467 | /* Some boards advertise MSI but don't really support it */ | |
bc2bb154 CH |
7468 | switch (h->board_id) { |
7469 | case 0x40700E11: | |
7470 | case 0x40800E11: | |
7471 | case 0x40820E11: | |
7472 | case 0x40830E11: | |
7473 | break; | |
7474 | default: | |
7475 | ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES, | |
7476 | PCI_IRQ_MSIX | PCI_IRQ_AFFINITY); | |
7477 | if (ret > 0) { | |
7478 | h->msix_vectors = ret; | |
7479 | return 0; | |
edd16368 | 7480 | } |
bc2bb154 CH |
7481 | |
7482 | flags |= PCI_IRQ_MSI; | |
7483 | break; | |
edd16368 | 7484 | } |
bc2bb154 CH |
7485 | |
7486 | ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags); | |
7487 | if (ret < 0) | |
7488 | return ret; | |
7489 | return 0; | |
edd16368 SC |
7490 | } |
7491 | ||
135ae6ed HR |
7492 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id, |
7493 | bool *legacy_board) | |
e5c880d1 SC |
7494 | { |
7495 | int i; | |
7496 | u32 subsystem_vendor_id, subsystem_device_id; | |
7497 | ||
7498 | subsystem_vendor_id = pdev->subsystem_vendor; | |
7499 | subsystem_device_id = pdev->subsystem_device; | |
7500 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
7501 | subsystem_vendor_id; | |
7502 | ||
135ae6ed HR |
7503 | if (legacy_board) |
7504 | *legacy_board = false; | |
e5c880d1 | 7505 | for (i = 0; i < ARRAY_SIZE(products); i++) |
135ae6ed HR |
7506 | if (*board_id == products[i].board_id) { |
7507 | if (products[i].access != &SA5A_access && | |
7508 | products[i].access != &SA5B_access) | |
7509 | return i; | |
c8cd71f1 HR |
7510 | dev_warn(&pdev->dev, |
7511 | "legacy board ID: 0x%08x\n", | |
7512 | *board_id); | |
7513 | if (legacy_board) | |
7514 | *legacy_board = true; | |
7515 | return i; | |
135ae6ed | 7516 | } |
e5c880d1 | 7517 | |
c8cd71f1 | 7518 | dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id); |
135ae6ed HR |
7519 | if (legacy_board) |
7520 | *legacy_board = true; | |
e5c880d1 SC |
7521 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ |
7522 | } | |
7523 | ||
6f039790 GKH |
7524 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
7525 | unsigned long *memory_bar) | |
3a7774ce SC |
7526 | { |
7527 | int i; | |
7528 | ||
7529 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 7530 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 7531 | /* addressing mode bits already removed */ |
12d2cd47 SC |
7532 | *memory_bar = pci_resource_start(pdev, i); |
7533 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
7534 | *memory_bar); |
7535 | return 0; | |
7536 | } | |
12d2cd47 | 7537 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
7538 | return -ENODEV; |
7539 | } | |
7540 | ||
6f039790 GKH |
7541 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
7542 | int wait_for_ready) | |
2c4c8c8b | 7543 | { |
fe5389c8 | 7544 | int i, iterations; |
2c4c8c8b | 7545 | u32 scratchpad; |
fe5389c8 SC |
7546 | if (wait_for_ready) |
7547 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
7548 | else | |
7549 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 7550 | |
fe5389c8 SC |
7551 | for (i = 0; i < iterations; i++) { |
7552 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
7553 | if (wait_for_ready) { | |
7554 | if (scratchpad == HPSA_FIRMWARE_READY) | |
7555 | return 0; | |
7556 | } else { | |
7557 | if (scratchpad != HPSA_FIRMWARE_READY) | |
7558 | return 0; | |
7559 | } | |
2c4c8c8b SC |
7560 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
7561 | } | |
fe5389c8 | 7562 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
7563 | return -ENODEV; |
7564 | } | |
7565 | ||
6f039790 GKH |
7566 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
7567 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
7568 | u64 *cfg_offset) | |
a51fd47f SC |
7569 | { |
7570 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
7571 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
7572 | *cfg_base_addr &= (u32) 0x0000ffff; | |
7573 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
7574 | if (*cfg_base_addr_index == -1) { | |
7575 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
7576 | return -ENODEV; | |
7577 | } | |
7578 | return 0; | |
7579 | } | |
7580 | ||
195f2c65 RE |
7581 | static void hpsa_free_cfgtables(struct ctlr_info *h) |
7582 | { | |
105a3dbc | 7583 | if (h->transtable) { |
195f2c65 | 7584 | iounmap(h->transtable); |
105a3dbc RE |
7585 | h->transtable = NULL; |
7586 | } | |
7587 | if (h->cfgtable) { | |
195f2c65 | 7588 | iounmap(h->cfgtable); |
105a3dbc RE |
7589 | h->cfgtable = NULL; |
7590 | } | |
195f2c65 RE |
7591 | } |
7592 | ||
7593 | /* Find and map CISS config table and transfer table | |
7594 | + * several items must be unmapped (freed) later | |
7595 | + * */ | |
6f039790 | 7596 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 7597 | { |
01a02ffc SC |
7598 | u64 cfg_offset; |
7599 | u32 cfg_base_addr; | |
7600 | u64 cfg_base_addr_index; | |
303932fd | 7601 | u32 trans_offset; |
a51fd47f | 7602 | int rc; |
77c4495c | 7603 | |
a51fd47f SC |
7604 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
7605 | &cfg_base_addr_index, &cfg_offset); | |
7606 | if (rc) | |
7607 | return rc; | |
77c4495c | 7608 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 7609 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
cd3c81c4 RE |
7610 | if (!h->cfgtable) { |
7611 | dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); | |
77c4495c | 7612 | return -ENOMEM; |
cd3c81c4 | 7613 | } |
580ada3c SC |
7614 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
7615 | if (rc) | |
7616 | return rc; | |
77c4495c | 7617 | /* Find performant mode table. */ |
a51fd47f | 7618 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
7619 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
7620 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
7621 | sizeof(*h->transtable)); | |
195f2c65 RE |
7622 | if (!h->transtable) { |
7623 | dev_err(&h->pdev->dev, "Failed mapping transfer table\n"); | |
7624 | hpsa_free_cfgtables(h); | |
77c4495c | 7625 | return -ENOMEM; |
195f2c65 | 7626 | } |
77c4495c SC |
7627 | return 0; |
7628 | } | |
7629 | ||
6f039790 | 7630 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b | 7631 | { |
41ce4c35 SC |
7632 | #define MIN_MAX_COMMANDS 16 |
7633 | BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS); | |
7634 | ||
7635 | h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands); | |
72ceeaec SC |
7636 | |
7637 | /* Limit commands in memory limited kdump scenario. */ | |
7638 | if (reset_devices && h->max_commands > 32) | |
7639 | h->max_commands = 32; | |
7640 | ||
41ce4c35 SC |
7641 | if (h->max_commands < MIN_MAX_COMMANDS) { |
7642 | dev_warn(&h->pdev->dev, | |
7643 | "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n", | |
7644 | h->max_commands, | |
7645 | MIN_MAX_COMMANDS); | |
7646 | h->max_commands = MIN_MAX_COMMANDS; | |
cba3d38b SC |
7647 | } |
7648 | } | |
7649 | ||
c7ee65b3 WS |
7650 | /* If the controller reports that the total max sg entries is greater than 512, |
7651 | * then we know that chained SG blocks work. (Original smart arrays did not | |
7652 | * support chained SG blocks and would return zero for max sg entries.) | |
7653 | */ | |
7654 | static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) | |
7655 | { | |
7656 | return h->maxsgentries > 512; | |
7657 | } | |
7658 | ||
b93d7536 SC |
7659 | /* Interrogate the hardware for some limits: |
7660 | * max commands, max SG elements without chaining, and with chaining, | |
7661 | * SG chain block size, etc. | |
7662 | */ | |
6f039790 | 7663 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 7664 | { |
cba3d38b | 7665 | hpsa_get_max_perf_mode_cmds(h); |
45fcb86e | 7666 | h->nr_cmds = h->max_commands; |
b93d7536 | 7667 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); |
283b4a9b | 7668 | h->fw_support = readl(&(h->cfgtable->misc_fw_support)); |
c7ee65b3 WS |
7669 | if (hpsa_supports_chained_sg_blocks(h)) { |
7670 | /* Limit in-command s/g elements to 32 save dma'able memory. */ | |
b93d7536 | 7671 | h->max_cmd_sg_entries = 32; |
1a63ea6f | 7672 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; |
b93d7536 SC |
7673 | h->maxsgentries--; /* save one for chain pointer */ |
7674 | } else { | |
c7ee65b3 WS |
7675 | /* |
7676 | * Original smart arrays supported at most 31 s/g entries | |
7677 | * embedded inline in the command (trying to use more | |
7678 | * would lock up the controller) | |
7679 | */ | |
7680 | h->max_cmd_sg_entries = 31; | |
1a63ea6f | 7681 | h->maxsgentries = 31; /* default to traditional values */ |
c7ee65b3 | 7682 | h->chainsize = 0; |
b93d7536 | 7683 | } |
75167d2c SC |
7684 | |
7685 | /* Find out what task management functions are supported and cache */ | |
7686 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
0e7a7fce ST |
7687 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) |
7688 | dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); | |
7689 | if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
7690 | dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); | |
8be986cc SC |
7691 | if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)) |
7692 | dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n"); | |
b93d7536 SC |
7693 | } |
7694 | ||
76c46e49 SC |
7695 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
7696 | { | |
0fc9fd40 | 7697 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
050f7147 | 7698 | dev_err(&h->pdev->dev, "not a valid CISS config table\n"); |
76c46e49 SC |
7699 | return false; |
7700 | } | |
7701 | return true; | |
7702 | } | |
7703 | ||
97a5e98c | 7704 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 7705 | { |
97a5e98c | 7706 | u32 driver_support; |
f7c39101 | 7707 | |
97a5e98c | 7708 | driver_support = readl(&(h->cfgtable->driver_support)); |
0b9e7b74 AB |
7709 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ |
7710 | #ifdef CONFIG_X86 | |
97a5e98c | 7711 | driver_support |= ENABLE_SCSI_PREFETCH; |
f7c39101 | 7712 | #endif |
28e13446 SC |
7713 | driver_support |= ENABLE_UNIT_ATTN; |
7714 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
7715 | } |
7716 | ||
3d0eab67 SC |
7717 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
7718 | * in a prefetch beyond physical memory. | |
7719 | */ | |
7720 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
7721 | { | |
7722 | u32 dma_prefetch; | |
7723 | ||
7724 | if (h->board_id != 0x3225103C) | |
7725 | return; | |
7726 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
7727 | dma_prefetch |= 0x8000; | |
7728 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
7729 | } | |
7730 | ||
c706a795 | 7731 | static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) |
76438d08 SC |
7732 | { |
7733 | int i; | |
7734 | u32 doorbell_value; | |
7735 | unsigned long flags; | |
7736 | /* wait until the clear_event_notify bit 6 is cleared by controller. */ | |
007e7aa9 | 7737 | for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) { |
76438d08 SC |
7738 | spin_lock_irqsave(&h->lock, flags); |
7739 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7740 | spin_unlock_irqrestore(&h->lock, flags); | |
7741 | if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) | |
c706a795 | 7742 | goto done; |
76438d08 | 7743 | /* delay and try again */ |
007e7aa9 | 7744 | msleep(CLEAR_EVENT_WAIT_INTERVAL); |
76438d08 | 7745 | } |
c706a795 RE |
7746 | return -ENODEV; |
7747 | done: | |
7748 | return 0; | |
76438d08 SC |
7749 | } |
7750 | ||
c706a795 | 7751 | static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
7752 | { |
7753 | int i; | |
6eaf46fd SC |
7754 | u32 doorbell_value; |
7755 | unsigned long flags; | |
eb6b2ae9 SC |
7756 | |
7757 | /* under certain very rare conditions, this can take awhile. | |
7758 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
7759 | * as we enter this code.) | |
7760 | */ | |
007e7aa9 | 7761 | for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) { |
25163bd5 WS |
7762 | if (h->remove_in_progress) |
7763 | goto done; | |
6eaf46fd SC |
7764 | spin_lock_irqsave(&h->lock, flags); |
7765 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
7766 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 7767 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
c706a795 | 7768 | goto done; |
eb6b2ae9 | 7769 | /* delay and try again */ |
007e7aa9 | 7770 | msleep(MODE_CHANGE_WAIT_INTERVAL); |
eb6b2ae9 | 7771 | } |
c706a795 RE |
7772 | return -ENODEV; |
7773 | done: | |
7774 | return 0; | |
3f4336f3 SC |
7775 | } |
7776 | ||
c706a795 | 7777 | /* return -ENODEV or other reason on error, 0 on success */ |
6f039790 | 7778 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
7779 | { |
7780 | u32 trans_support; | |
7781 | ||
7782 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
7783 | if (!(trans_support & SIMPLE_MODE)) | |
7784 | return -ENOTSUPP; | |
7785 | ||
7786 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
283b4a9b | 7787 | |
3f4336f3 SC |
7788 | /* Update the field, and then ring the doorbell */ |
7789 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
b9af4937 | 7790 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
3f4336f3 | 7791 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
7792 | if (hpsa_wait_for_mode_change_ack(h)) |
7793 | goto error; | |
eb6b2ae9 | 7794 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
283b4a9b SC |
7795 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) |
7796 | goto error; | |
960a30e7 | 7797 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 | 7798 | return 0; |
283b4a9b | 7799 | error: |
050f7147 | 7800 | dev_err(&h->pdev->dev, "failed to enter simple mode\n"); |
283b4a9b | 7801 | return -ENODEV; |
eb6b2ae9 SC |
7802 | } |
7803 | ||
195f2c65 RE |
7804 | /* free items allocated or mapped by hpsa_pci_init */ |
7805 | static void hpsa_free_pci_init(struct ctlr_info *h) | |
7806 | { | |
7807 | hpsa_free_cfgtables(h); /* pci_init 4 */ | |
7808 | iounmap(h->vaddr); /* pci_init 3 */ | |
105a3dbc | 7809 | h->vaddr = NULL; |
195f2c65 | 7810 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
943a7021 RE |
7811 | /* |
7812 | * call pci_disable_device before pci_release_regions per | |
bff9e34c | 7813 | * Documentation/driver-api/pci/pci.rst |
943a7021 | 7814 | */ |
195f2c65 | 7815 | pci_disable_device(h->pdev); /* pci_init 1 */ |
943a7021 | 7816 | pci_release_regions(h->pdev); /* pci_init 2 */ |
195f2c65 RE |
7817 | } |
7818 | ||
7819 | /* several items must be freed later */ | |
6f039790 | 7820 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 7821 | { |
eb6b2ae9 | 7822 | int prod_index, err; |
135ae6ed | 7823 | bool legacy_board; |
edd16368 | 7824 | |
135ae6ed | 7825 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board); |
e5c880d1 | 7826 | if (prod_index < 0) |
60f923b9 | 7827 | return prod_index; |
e5c880d1 SC |
7828 | h->product_name = products[prod_index].product_name; |
7829 | h->access = *(products[prod_index].access); | |
135ae6ed | 7830 | h->legacy_board = legacy_board; |
e5a44df8 MG |
7831 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
7832 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
7833 | ||
55c06c71 | 7834 | err = pci_enable_device(h->pdev); |
edd16368 | 7835 | if (err) { |
195f2c65 | 7836 | dev_err(&h->pdev->dev, "failed to enable PCI device\n"); |
943a7021 | 7837 | pci_disable_device(h->pdev); |
edd16368 SC |
7838 | return err; |
7839 | } | |
7840 | ||
f79cfec6 | 7841 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 7842 | if (err) { |
55c06c71 | 7843 | dev_err(&h->pdev->dev, |
195f2c65 | 7844 | "failed to obtain PCI resources\n"); |
943a7021 RE |
7845 | pci_disable_device(h->pdev); |
7846 | return err; | |
edd16368 | 7847 | } |
4fa604e1 RE |
7848 | |
7849 | pci_set_master(h->pdev); | |
7850 | ||
bc2bb154 CH |
7851 | err = hpsa_interrupt_mode(h); |
7852 | if (err) | |
7853 | goto clean1; | |
8b834bff ML |
7854 | |
7855 | /* setup mapping between CPU and reply queue */ | |
7856 | hpsa_setup_reply_map(h); | |
7857 | ||
12d2cd47 | 7858 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 7859 | if (err) |
195f2c65 | 7860 | goto clean2; /* intmode+region, pci */ |
edd16368 | 7861 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 | 7862 | if (!h->vaddr) { |
195f2c65 | 7863 | dev_err(&h->pdev->dev, "failed to remap PCI mem\n"); |
204892e9 | 7864 | err = -ENOMEM; |
195f2c65 | 7865 | goto clean2; /* intmode+region, pci */ |
204892e9 | 7866 | } |
fe5389c8 | 7867 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 7868 | if (err) |
195f2c65 | 7869 | goto clean3; /* vaddr, intmode+region, pci */ |
77c4495c SC |
7870 | err = hpsa_find_cfgtables(h); |
7871 | if (err) | |
195f2c65 | 7872 | goto clean3; /* vaddr, intmode+region, pci */ |
b93d7536 | 7873 | hpsa_find_board_params(h); |
edd16368 | 7874 | |
76c46e49 | 7875 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 | 7876 | err = -ENODEV; |
195f2c65 | 7877 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 | 7878 | } |
97a5e98c | 7879 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 7880 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
7881 | err = hpsa_enter_simple_mode(h); |
7882 | if (err) | |
195f2c65 | 7883 | goto clean4; /* cfgtables, vaddr, intmode+region, pci */ |
edd16368 SC |
7884 | return 0; |
7885 | ||
195f2c65 RE |
7886 | clean4: /* cfgtables, vaddr, intmode+region, pci */ |
7887 | hpsa_free_cfgtables(h); | |
7888 | clean3: /* vaddr, intmode+region, pci */ | |
7889 | iounmap(h->vaddr); | |
105a3dbc | 7890 | h->vaddr = NULL; |
195f2c65 RE |
7891 | clean2: /* intmode+region, pci */ |
7892 | hpsa_disable_interrupt_mode(h); | |
bc2bb154 | 7893 | clean1: |
943a7021 RE |
7894 | /* |
7895 | * call pci_disable_device before pci_release_regions per | |
bff9e34c | 7896 | * Documentation/driver-api/pci/pci.rst |
943a7021 | 7897 | */ |
195f2c65 | 7898 | pci_disable_device(h->pdev); |
943a7021 | 7899 | pci_release_regions(h->pdev); |
edd16368 SC |
7900 | return err; |
7901 | } | |
7902 | ||
6f039790 | 7903 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
7904 | { |
7905 | int rc; | |
7906 | ||
7907 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
7908 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
7909 | if (!h->hba_inquiry_data) | |
7910 | return; | |
7911 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
7912 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
7913 | if (rc != 0) { | |
7914 | kfree(h->hba_inquiry_data); | |
7915 | h->hba_inquiry_data = NULL; | |
7916 | } | |
7917 | } | |
7918 | ||
6b6c1cd7 | 7919 | static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id) |
4c2a8c40 | 7920 | { |
1df8552a | 7921 | int rc, i; |
3b747298 | 7922 | void __iomem *vaddr; |
4c2a8c40 SC |
7923 | |
7924 | if (!reset_devices) | |
7925 | return 0; | |
7926 | ||
132aa220 TH |
7927 | /* kdump kernel is loading, we don't know in which state is |
7928 | * the pci interface. The dev->enable_cnt is equal zero | |
7929 | * so we call enable+disable, wait a while and switch it on. | |
7930 | */ | |
7931 | rc = pci_enable_device(pdev); | |
7932 | if (rc) { | |
7933 | dev_warn(&pdev->dev, "Failed to enable PCI device\n"); | |
7934 | return -ENODEV; | |
7935 | } | |
7936 | pci_disable_device(pdev); | |
7937 | msleep(260); /* a randomly chosen number */ | |
7938 | rc = pci_enable_device(pdev); | |
7939 | if (rc) { | |
7940 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
7941 | return -ENODEV; | |
7942 | } | |
4fa604e1 | 7943 | |
859c75ab | 7944 | pci_set_master(pdev); |
4fa604e1 | 7945 | |
3b747298 TH |
7946 | vaddr = pci_ioremap_bar(pdev, 0); |
7947 | if (vaddr == NULL) { | |
7948 | rc = -ENOMEM; | |
7949 | goto out_disable; | |
7950 | } | |
7951 | writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
7952 | iounmap(vaddr); | |
7953 | ||
1df8552a | 7954 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
6b6c1cd7 | 7955 | rc = hpsa_kdump_hard_reset_controller(pdev, board_id); |
4c2a8c40 | 7956 | |
1df8552a SC |
7957 | /* -ENOTSUPP here means we cannot reset the controller |
7958 | * but it's already (and still) up and running in | |
18867659 SC |
7959 | * "performant mode". Or, it might be 640x, which can't reset |
7960 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a | 7961 | */ |
adf1b3a3 | 7962 | if (rc) |
132aa220 | 7963 | goto out_disable; |
4c2a8c40 SC |
7964 | |
7965 | /* Now try to get the controller to respond to a no-op */ | |
1ba66c9c | 7966 | dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
7967 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
7968 | if (hpsa_noop(pdev) == 0) | |
7969 | break; | |
7970 | else | |
7971 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
7972 | (i < 11 ? "; re-trying" : "")); | |
7973 | } | |
132aa220 TH |
7974 | |
7975 | out_disable: | |
7976 | ||
7977 | pci_disable_device(pdev); | |
7978 | return rc; | |
4c2a8c40 SC |
7979 | } |
7980 | ||
1fb7c98a RE |
7981 | static void hpsa_free_cmd_pool(struct ctlr_info *h) |
7982 | { | |
7983 | kfree(h->cmd_pool_bits); | |
105a3dbc RE |
7984 | h->cmd_pool_bits = NULL; |
7985 | if (h->cmd_pool) { | |
8bc8f47e | 7986 | dma_free_coherent(&h->pdev->dev, |
1fb7c98a RE |
7987 | h->nr_cmds * sizeof(struct CommandList), |
7988 | h->cmd_pool, | |
7989 | h->cmd_pool_dhandle); | |
105a3dbc RE |
7990 | h->cmd_pool = NULL; |
7991 | h->cmd_pool_dhandle = 0; | |
7992 | } | |
7993 | if (h->errinfo_pool) { | |
8bc8f47e | 7994 | dma_free_coherent(&h->pdev->dev, |
1fb7c98a RE |
7995 | h->nr_cmds * sizeof(struct ErrorInfo), |
7996 | h->errinfo_pool, | |
7997 | h->errinfo_pool_dhandle); | |
105a3dbc RE |
7998 | h->errinfo_pool = NULL; |
7999 | h->errinfo_pool_dhandle = 0; | |
8000 | } | |
1fb7c98a RE |
8001 | } |
8002 | ||
d37ffbe4 | 8003 | static int hpsa_alloc_cmd_pool(struct ctlr_info *h) |
2e9d1b36 | 8004 | { |
6396bb22 KC |
8005 | h->cmd_pool_bits = kcalloc(DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG), |
8006 | sizeof(unsigned long), | |
8007 | GFP_KERNEL); | |
8bc8f47e | 8008 | h->cmd_pool = dma_alloc_coherent(&h->pdev->dev, |
2e9d1b36 | 8009 | h->nr_cmds * sizeof(*h->cmd_pool), |
8bc8f47e CH |
8010 | &h->cmd_pool_dhandle, GFP_KERNEL); |
8011 | h->errinfo_pool = dma_alloc_coherent(&h->pdev->dev, | |
2e9d1b36 | 8012 | h->nr_cmds * sizeof(*h->errinfo_pool), |
8bc8f47e | 8013 | &h->errinfo_pool_dhandle, GFP_KERNEL); |
2e9d1b36 SC |
8014 | if ((h->cmd_pool_bits == NULL) |
8015 | || (h->cmd_pool == NULL) | |
8016 | || (h->errinfo_pool == NULL)) { | |
8017 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
2c143342 | 8018 | goto clean_up; |
2e9d1b36 | 8019 | } |
360c73bd | 8020 | hpsa_preinitialize_commands(h); |
2e9d1b36 | 8021 | return 0; |
2c143342 RE |
8022 | clean_up: |
8023 | hpsa_free_cmd_pool(h); | |
8024 | return -ENOMEM; | |
2e9d1b36 SC |
8025 | } |
8026 | ||
ec501a18 RE |
8027 | /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ |
8028 | static void hpsa_free_irqs(struct ctlr_info *h) | |
8029 | { | |
8030 | int i; | |
a68fdb3a DB |
8031 | int irq_vector = 0; |
8032 | ||
8033 | if (hpsa_simple_mode) | |
8034 | irq_vector = h->intr_mode; | |
ec501a18 | 8035 | |
bc2bb154 | 8036 | if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) { |
ec501a18 | 8037 | /* Single reply queue, only one irq to free */ |
a68fdb3a DB |
8038 | free_irq(pci_irq_vector(h->pdev, irq_vector), |
8039 | &h->q[h->intr_mode]); | |
bc2bb154 | 8040 | h->q[h->intr_mode] = 0; |
ec501a18 RE |
8041 | return; |
8042 | } | |
8043 | ||
bc2bb154 CH |
8044 | for (i = 0; i < h->msix_vectors; i++) { |
8045 | free_irq(pci_irq_vector(h->pdev, i), &h->q[i]); | |
105a3dbc | 8046 | h->q[i] = 0; |
ec501a18 | 8047 | } |
a4e17fc1 RE |
8048 | for (; i < MAX_REPLY_QUEUES; i++) |
8049 | h->q[i] = 0; | |
ec501a18 RE |
8050 | } |
8051 | ||
9ee61794 RE |
8052 | /* returns 0 on success; cleans up and returns -Enn on error */ |
8053 | static int hpsa_request_irqs(struct ctlr_info *h, | |
0ae01a32 SC |
8054 | irqreturn_t (*msixhandler)(int, void *), |
8055 | irqreturn_t (*intxhandler)(int, void *)) | |
8056 | { | |
254f796b | 8057 | int rc, i; |
a68fdb3a DB |
8058 | int irq_vector = 0; |
8059 | ||
8060 | if (hpsa_simple_mode) | |
8061 | irq_vector = h->intr_mode; | |
0ae01a32 | 8062 | |
254f796b MG |
8063 | /* |
8064 | * initialize h->q[x] = x so that interrupt handlers know which | |
8065 | * queue to process. | |
8066 | */ | |
8067 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
8068 | h->q[i] = (u8) i; | |
8069 | ||
bc2bb154 | 8070 | if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) { |
254f796b | 8071 | /* If performant mode and MSI-X, use multiple reply queues */ |
bc2bb154 | 8072 | for (i = 0; i < h->msix_vectors; i++) { |
8b47004a | 8073 | sprintf(h->intrname[i], "%s-msix%d", h->devname, i); |
bc2bb154 | 8074 | rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler, |
8b47004a | 8075 | 0, h->intrname[i], |
254f796b | 8076 | &h->q[i]); |
a4e17fc1 RE |
8077 | if (rc) { |
8078 | int j; | |
8079 | ||
8080 | dev_err(&h->pdev->dev, | |
8081 | "failed to get irq %d for %s\n", | |
bc2bb154 | 8082 | pci_irq_vector(h->pdev, i), h->devname); |
a4e17fc1 | 8083 | for (j = 0; j < i; j++) { |
bc2bb154 | 8084 | free_irq(pci_irq_vector(h->pdev, j), &h->q[j]); |
a4e17fc1 RE |
8085 | h->q[j] = 0; |
8086 | } | |
8087 | for (; j < MAX_REPLY_QUEUES; j++) | |
8088 | h->q[j] = 0; | |
8089 | return rc; | |
8090 | } | |
8091 | } | |
254f796b MG |
8092 | } else { |
8093 | /* Use single reply pool */ | |
bc2bb154 CH |
8094 | if (h->msix_vectors > 0 || h->pdev->msi_enabled) { |
8095 | sprintf(h->intrname[0], "%s-msi%s", h->devname, | |
8096 | h->msix_vectors ? "x" : ""); | |
a68fdb3a | 8097 | rc = request_irq(pci_irq_vector(h->pdev, irq_vector), |
8b47004a | 8098 | msixhandler, 0, |
bc2bb154 | 8099 | h->intrname[0], |
254f796b MG |
8100 | &h->q[h->intr_mode]); |
8101 | } else { | |
8b47004a RE |
8102 | sprintf(h->intrname[h->intr_mode], |
8103 | "%s-intx", h->devname); | |
a68fdb3a | 8104 | rc = request_irq(pci_irq_vector(h->pdev, irq_vector), |
8b47004a | 8105 | intxhandler, IRQF_SHARED, |
bc2bb154 | 8106 | h->intrname[0], |
254f796b MG |
8107 | &h->q[h->intr_mode]); |
8108 | } | |
8109 | } | |
0ae01a32 | 8110 | if (rc) { |
195f2c65 | 8111 | dev_err(&h->pdev->dev, "failed to get irq %d for %s\n", |
a68fdb3a | 8112 | pci_irq_vector(h->pdev, irq_vector), h->devname); |
195f2c65 | 8113 | hpsa_free_irqs(h); |
0ae01a32 SC |
8114 | return -ENODEV; |
8115 | } | |
8116 | return 0; | |
8117 | } | |
8118 | ||
6f039790 | 8119 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 | 8120 | { |
39c53f55 | 8121 | int rc; |
c5dfd106 | 8122 | hpsa_send_host_reset(h, HPSA_RESET_TYPE_CONTROLLER); |
64670ac8 SC |
8123 | |
8124 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
39c53f55 RE |
8125 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY); |
8126 | if (rc) { | |
64670ac8 | 8127 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); |
39c53f55 | 8128 | return rc; |
64670ac8 SC |
8129 | } |
8130 | ||
8131 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
39c53f55 RE |
8132 | rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
8133 | if (rc) { | |
64670ac8 SC |
8134 | dev_warn(&h->pdev->dev, "Board failed to become ready " |
8135 | "after soft reset.\n"); | |
39c53f55 | 8136 | return rc; |
64670ac8 SC |
8137 | } |
8138 | ||
8139 | return 0; | |
8140 | } | |
8141 | ||
072b0518 SC |
8142 | static void hpsa_free_reply_queues(struct ctlr_info *h) |
8143 | { | |
8144 | int i; | |
8145 | ||
8146 | for (i = 0; i < h->nreply_queues; i++) { | |
8147 | if (!h->reply_queue[i].head) | |
8148 | continue; | |
8bc8f47e | 8149 | dma_free_coherent(&h->pdev->dev, |
1fb7c98a RE |
8150 | h->reply_queue_size, |
8151 | h->reply_queue[i].head, | |
8152 | h->reply_queue[i].busaddr); | |
072b0518 SC |
8153 | h->reply_queue[i].head = NULL; |
8154 | h->reply_queue[i].busaddr = 0; | |
8155 | } | |
105a3dbc | 8156 | h->reply_queue_size = 0; |
072b0518 SC |
8157 | } |
8158 | ||
0097f0f4 SC |
8159 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) |
8160 | { | |
105a3dbc RE |
8161 | hpsa_free_performant_mode(h); /* init_one 7 */ |
8162 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
8163 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
8164 | hpsa_free_irqs(h); /* init_one 4 */ | |
2946e82b RE |
8165 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
8166 | h->scsi_host = NULL; /* init_one 3 */ | |
8167 | hpsa_free_pci_init(h); /* init_one 2_5 */ | |
9ecd953a RE |
8168 | free_percpu(h->lockup_detected); /* init_one 2 */ |
8169 | h->lockup_detected = NULL; /* init_one 2 */ | |
8170 | if (h->resubmit_wq) { | |
8171 | destroy_workqueue(h->resubmit_wq); /* init_one 1 */ | |
8172 | h->resubmit_wq = NULL; | |
8173 | } | |
8174 | if (h->rescan_ctlr_wq) { | |
8175 | destroy_workqueue(h->rescan_ctlr_wq); | |
8176 | h->rescan_ctlr_wq = NULL; | |
8177 | } | |
01192088 DB |
8178 | if (h->monitor_ctlr_wq) { |
8179 | destroy_workqueue(h->monitor_ctlr_wq); | |
8180 | h->monitor_ctlr_wq = NULL; | |
8181 | } | |
8182 | ||
105a3dbc | 8183 | kfree(h); /* init_one 1 */ |
64670ac8 SC |
8184 | } |
8185 | ||
a0c12413 | 8186 | /* Called when controller lockup detected. */ |
f2405db8 | 8187 | static void fail_all_outstanding_cmds(struct ctlr_info *h) |
a0c12413 | 8188 | { |
281a7fd0 WS |
8189 | int i, refcount; |
8190 | struct CommandList *c; | |
25163bd5 | 8191 | int failcount = 0; |
a0c12413 | 8192 | |
080ef1cc | 8193 | flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ |
f2405db8 | 8194 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 8195 | c = h->cmd_pool + i; |
281a7fd0 WS |
8196 | refcount = atomic_inc_return(&c->refcount); |
8197 | if (refcount > 1) { | |
25163bd5 | 8198 | c->err_info->CommandStatus = CMD_CTLR_LOCKUP; |
281a7fd0 | 8199 | finish_cmd(c); |
433b5f4d | 8200 | atomic_dec(&h->commands_outstanding); |
25163bd5 | 8201 | failcount++; |
281a7fd0 WS |
8202 | } |
8203 | cmd_free(h, c); | |
a0c12413 | 8204 | } |
25163bd5 WS |
8205 | dev_warn(&h->pdev->dev, |
8206 | "failed %d commands in fail_all\n", failcount); | |
a0c12413 SC |
8207 | } |
8208 | ||
094963da SC |
8209 | static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) |
8210 | { | |
c8ed0010 | 8211 | int cpu; |
094963da | 8212 | |
c8ed0010 | 8213 | for_each_online_cpu(cpu) { |
094963da SC |
8214 | u32 *lockup_detected; |
8215 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
8216 | *lockup_detected = value; | |
094963da SC |
8217 | } |
8218 | wmb(); /* be sure the per-cpu variables are out to memory */ | |
8219 | } | |
8220 | ||
a0c12413 SC |
8221 | static void controller_lockup_detected(struct ctlr_info *h) |
8222 | { | |
8223 | unsigned long flags; | |
094963da | 8224 | u32 lockup_detected; |
a0c12413 | 8225 | |
a0c12413 SC |
8226 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
8227 | spin_lock_irqsave(&h->lock, flags); | |
094963da SC |
8228 | lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
8229 | if (!lockup_detected) { | |
8230 | /* no heartbeat, but controller gave us a zero. */ | |
8231 | dev_warn(&h->pdev->dev, | |
25163bd5 WS |
8232 | "lockup detected after %d but scratchpad register is zero\n", |
8233 | h->heartbeat_sample_interval / HZ); | |
094963da SC |
8234 | lockup_detected = 0xffffffff; |
8235 | } | |
8236 | set_lockup_detected_for_all_cpus(h, lockup_detected); | |
a0c12413 | 8237 | spin_unlock_irqrestore(&h->lock, flags); |
25163bd5 WS |
8238 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n", |
8239 | lockup_detected, h->heartbeat_sample_interval / HZ); | |
b9b08cad DB |
8240 | if (lockup_detected == 0xffff0000) { |
8241 | dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n"); | |
8242 | writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL); | |
8243 | } | |
a0c12413 | 8244 | pci_disable_device(h->pdev); |
f2405db8 | 8245 | fail_all_outstanding_cmds(h); |
a0c12413 SC |
8246 | } |
8247 | ||
25163bd5 | 8248 | static int detect_controller_lockup(struct ctlr_info *h) |
a0c12413 SC |
8249 | { |
8250 | u64 now; | |
8251 | u32 heartbeat; | |
8252 | unsigned long flags; | |
8253 | ||
a0c12413 SC |
8254 | now = get_jiffies_64(); |
8255 | /* If we've received an interrupt recently, we're ok. */ | |
8256 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 8257 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8258 | return false; |
a0c12413 SC |
8259 | |
8260 | /* | |
8261 | * If we've already checked the heartbeat recently, we're ok. | |
8262 | * This could happen if someone sends us a signal. We | |
8263 | * otherwise don't care about signals in this thread. | |
8264 | */ | |
8265 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 8266 | (h->heartbeat_sample_interval), now)) |
25163bd5 | 8267 | return false; |
a0c12413 SC |
8268 | |
8269 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
8270 | spin_lock_irqsave(&h->lock, flags); | |
8271 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
8272 | spin_unlock_irqrestore(&h->lock, flags); | |
8273 | if (h->last_heartbeat == heartbeat) { | |
8274 | controller_lockup_detected(h); | |
25163bd5 | 8275 | return true; |
a0c12413 SC |
8276 | } |
8277 | ||
8278 | /* We're ok. */ | |
8279 | h->last_heartbeat = heartbeat; | |
8280 | h->last_heartbeat_timestamp = now; | |
25163bd5 | 8281 | return false; |
a0c12413 SC |
8282 | } |
8283 | ||
b2582a65 DB |
8284 | /* |
8285 | * Set ioaccel status for all ioaccel volumes. | |
8286 | * | |
8287 | * Called from monitor controller worker (hpsa_event_monitor_worker) | |
8288 | * | |
8289 | * A Volume (or Volumes that comprise an Array set may be undergoing a | |
8290 | * transformation, so we will be turning off ioaccel for all volumes that | |
8291 | * make up the Array. | |
8292 | */ | |
8293 | static void hpsa_set_ioaccel_status(struct ctlr_info *h) | |
76438d08 | 8294 | { |
b2582a65 | 8295 | int rc; |
76438d08 | 8296 | int i; |
b2582a65 DB |
8297 | u8 ioaccel_status; |
8298 | unsigned char *buf; | |
8299 | struct hpsa_scsi_dev_t *device; | |
8300 | ||
8301 | if (!h) | |
8302 | return; | |
8303 | ||
8304 | buf = kmalloc(64, GFP_KERNEL); | |
8305 | if (!buf) | |
8306 | return; | |
8307 | ||
8308 | /* | |
8309 | * Run through current device list used during I/O requests. | |
8310 | */ | |
8311 | for (i = 0; i < h->ndevices; i++) { | |
8312 | device = h->dev[i]; | |
8313 | ||
8314 | if (!device) | |
8315 | continue; | |
b2582a65 DB |
8316 | if (!hpsa_vpd_page_supported(h, device->scsi3addr, |
8317 | HPSA_VPD_LV_IOACCEL_STATUS)) | |
8318 | continue; | |
8319 | ||
8320 | memset(buf, 0, 64); | |
8321 | ||
8322 | rc = hpsa_scsi_do_inquiry(h, device->scsi3addr, | |
8323 | VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, | |
8324 | buf, 64); | |
8325 | if (rc != 0) | |
8326 | continue; | |
8327 | ||
8328 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
8329 | device->offload_config = | |
8330 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
8331 | if (device->offload_config) | |
8332 | device->offload_to_be_enabled = | |
8333 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); | |
8334 | ||
8335 | /* | |
8336 | * Immediately turn off ioaccel for any volume the | |
8337 | * controller tells us to. Some of the reasons could be: | |
8338 | * transformation - change to the LVs of an Array. | |
8339 | * degraded volume - component failure | |
8340 | * | |
8341 | * If ioaccel is to be re-enabled, re-enable later during the | |
8342 | * scan operation so the driver can get a fresh raidmap | |
8343 | * before turning ioaccel back on. | |
8344 | * | |
8345 | */ | |
8346 | if (!device->offload_to_be_enabled) | |
8347 | device->offload_enabled = 0; | |
8348 | } | |
8349 | ||
8350 | kfree(buf); | |
8351 | } | |
8352 | ||
8353 | static void hpsa_ack_ctlr_events(struct ctlr_info *h) | |
8354 | { | |
76438d08 SC |
8355 | char *event_type; |
8356 | ||
e4aa3e6a SC |
8357 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
8358 | return; | |
8359 | ||
76438d08 | 8360 | /* Ask the controller to clear the events we're handling. */ |
1f7cee8c SC |
8361 | if ((h->transMethod & (CFGTBL_Trans_io_accel1 |
8362 | | CFGTBL_Trans_io_accel2)) && | |
76438d08 SC |
8363 | (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || |
8364 | h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { | |
8365 | ||
8366 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) | |
8367 | event_type = "state change"; | |
8368 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) | |
8369 | event_type = "configuration change"; | |
8370 | /* Stop sending new RAID offload reqs via the IO accelerator */ | |
8371 | scsi_block_requests(h->scsi_host); | |
b2582a65 | 8372 | hpsa_set_ioaccel_status(h); |
23100dd9 | 8373 | hpsa_drain_accel_commands(h); |
76438d08 SC |
8374 | /* Set 'accelerator path config change' bit */ |
8375 | dev_warn(&h->pdev->dev, | |
8376 | "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", | |
8377 | h->events, event_type); | |
8378 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8379 | /* Set the "clear event notify field update" bit 6 */ | |
8380 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8381 | /* Wait until ctlr clears 'clear event notify field', bit 6 */ | |
8382 | hpsa_wait_for_clear_event_notify_ack(h); | |
8383 | scsi_unblock_requests(h->scsi_host); | |
8384 | } else { | |
8385 | /* Acknowledge controller notification events. */ | |
8386 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
8387 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
8388 | hpsa_wait_for_clear_event_notify_ack(h); | |
76438d08 | 8389 | } |
9846590e | 8390 | return; |
76438d08 SC |
8391 | } |
8392 | ||
8393 | /* Check a register on the controller to see if there are configuration | |
8394 | * changes (added/changed/removed logical drives, etc.) which mean that | |
e863d68e ST |
8395 | * we should rescan the controller for devices. |
8396 | * Also check flag for driver-initiated rescan. | |
76438d08 | 8397 | */ |
9846590e | 8398 | static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) |
76438d08 | 8399 | { |
853633e8 DB |
8400 | if (h->drv_req_rescan) { |
8401 | h->drv_req_rescan = 0; | |
8402 | return 1; | |
8403 | } | |
8404 | ||
76438d08 | 8405 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
9846590e | 8406 | return 0; |
76438d08 SC |
8407 | |
8408 | h->events = readl(&(h->cfgtable->event_notify)); | |
9846590e SC |
8409 | return h->events & RESCAN_REQUIRED_EVENT_BITS; |
8410 | } | |
76438d08 | 8411 | |
9846590e SC |
8412 | /* |
8413 | * Check if any of the offline devices have become ready | |
8414 | */ | |
8415 | static int hpsa_offline_devices_ready(struct ctlr_info *h) | |
8416 | { | |
8417 | unsigned long flags; | |
8418 | struct offline_device_entry *d; | |
8419 | struct list_head *this, *tmp; | |
8420 | ||
8421 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8422 | list_for_each_safe(this, tmp, &h->offline_device_list) { | |
8423 | d = list_entry(this, struct offline_device_entry, | |
8424 | offline_list); | |
8425 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
d1fea47c SC |
8426 | if (!hpsa_volume_offline(h, d->scsi3addr)) { |
8427 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
8428 | list_del(&d->offline_list); | |
8429 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
9846590e | 8430 | return 1; |
d1fea47c | 8431 | } |
9846590e SC |
8432 | spin_lock_irqsave(&h->offline_device_lock, flags); |
8433 | } | |
8434 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
8435 | return 0; | |
76438d08 SC |
8436 | } |
8437 | ||
34592254 ST |
8438 | static int hpsa_luns_changed(struct ctlr_info *h) |
8439 | { | |
8440 | int rc = 1; /* assume there are changes */ | |
8441 | struct ReportLUNdata *logdev = NULL; | |
8442 | ||
8443 | /* if we can't find out if lun data has changed, | |
8444 | * assume that it has. | |
8445 | */ | |
8446 | ||
8447 | if (!h->lastlogicals) | |
7e8a9486 | 8448 | return rc; |
34592254 ST |
8449 | |
8450 | logdev = kzalloc(sizeof(*logdev), GFP_KERNEL); | |
7e8a9486 AK |
8451 | if (!logdev) |
8452 | return rc; | |
8453 | ||
34592254 ST |
8454 | if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) { |
8455 | dev_warn(&h->pdev->dev, | |
8456 | "report luns failed, can't track lun changes.\n"); | |
8457 | goto out; | |
8458 | } | |
8459 | if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) { | |
8460 | dev_info(&h->pdev->dev, | |
8461 | "Lun changes detected.\n"); | |
8462 | memcpy(h->lastlogicals, logdev, sizeof(*logdev)); | |
8463 | goto out; | |
8464 | } else | |
8465 | rc = 0; /* no changes detected. */ | |
8466 | out: | |
8467 | kfree(logdev); | |
8468 | return rc; | |
8469 | } | |
8470 | ||
3d38f00c | 8471 | static void hpsa_perform_rescan(struct ctlr_info *h) |
a0c12413 | 8472 | { |
3d38f00c | 8473 | struct Scsi_Host *sh = NULL; |
a0c12413 | 8474 | unsigned long flags; |
9846590e | 8475 | |
bfd7546c DB |
8476 | /* |
8477 | * Do the scan after the reset | |
8478 | */ | |
c59d04f3 | 8479 | spin_lock_irqsave(&h->reset_lock, flags); |
bfd7546c DB |
8480 | if (h->reset_in_progress) { |
8481 | h->drv_req_rescan = 1; | |
c59d04f3 | 8482 | spin_unlock_irqrestore(&h->reset_lock, flags); |
bfd7546c DB |
8483 | return; |
8484 | } | |
c59d04f3 | 8485 | spin_unlock_irqrestore(&h->reset_lock, flags); |
bfd7546c | 8486 | |
3d38f00c ST |
8487 | sh = scsi_host_get(h->scsi_host); |
8488 | if (sh != NULL) { | |
8489 | hpsa_scan_start(sh); | |
8490 | scsi_host_put(sh); | |
8491 | h->drv_req_rescan = 0; | |
8492 | } | |
8493 | } | |
8494 | ||
8495 | /* | |
8496 | * watch for controller events | |
8497 | */ | |
8498 | static void hpsa_event_monitor_worker(struct work_struct *work) | |
8499 | { | |
8500 | struct ctlr_info *h = container_of(to_delayed_work(work), | |
8501 | struct ctlr_info, event_monitor_work); | |
8502 | unsigned long flags; | |
8503 | ||
8504 | spin_lock_irqsave(&h->lock, flags); | |
8505 | if (h->remove_in_progress) { | |
8506 | spin_unlock_irqrestore(&h->lock, flags); | |
8507 | return; | |
8508 | } | |
8509 | spin_unlock_irqrestore(&h->lock, flags); | |
8510 | ||
8511 | if (hpsa_ctlr_needs_rescan(h)) { | |
9846590e | 8512 | hpsa_ack_ctlr_events(h); |
3d38f00c ST |
8513 | hpsa_perform_rescan(h); |
8514 | } | |
8515 | ||
8516 | spin_lock_irqsave(&h->lock, flags); | |
8517 | if (!h->remove_in_progress) | |
01192088 DB |
8518 | queue_delayed_work(h->monitor_ctlr_wq, &h->event_monitor_work, |
8519 | HPSA_EVENT_MONITOR_INTERVAL); | |
3d38f00c ST |
8520 | spin_unlock_irqrestore(&h->lock, flags); |
8521 | } | |
8522 | ||
8523 | static void hpsa_rescan_ctlr_worker(struct work_struct *work) | |
8524 | { | |
8525 | unsigned long flags; | |
8526 | struct ctlr_info *h = container_of(to_delayed_work(work), | |
8527 | struct ctlr_info, rescan_ctlr_work); | |
8528 | ||
8529 | spin_lock_irqsave(&h->lock, flags); | |
8530 | if (h->remove_in_progress) { | |
8531 | spin_unlock_irqrestore(&h->lock, flags); | |
8532 | return; | |
8533 | } | |
8534 | spin_unlock_irqrestore(&h->lock, flags); | |
8535 | ||
8536 | if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) { | |
8537 | hpsa_perform_rescan(h); | |
34592254 ST |
8538 | } else if (h->discovery_polling) { |
8539 | if (hpsa_luns_changed(h)) { | |
34592254 ST |
8540 | dev_info(&h->pdev->dev, |
8541 | "driver discovery polling rescan.\n"); | |
3d38f00c | 8542 | hpsa_perform_rescan(h); |
34592254 | 8543 | } |
9846590e | 8544 | } |
8a98db73 | 8545 | spin_lock_irqsave(&h->lock, flags); |
6636e7f4 DB |
8546 | if (!h->remove_in_progress) |
8547 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8548 | h->heartbeat_sample_interval); | |
8549 | spin_unlock_irqrestore(&h->lock, flags); | |
8550 | } | |
8551 | ||
8552 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) | |
8553 | { | |
8554 | unsigned long flags; | |
8555 | struct ctlr_info *h = container_of(to_delayed_work(work), | |
8556 | struct ctlr_info, monitor_ctlr_work); | |
8557 | ||
8558 | detect_controller_lockup(h); | |
8559 | if (lockup_detected(h)) | |
a0c12413 | 8560 | return; |
6636e7f4 DB |
8561 | |
8562 | spin_lock_irqsave(&h->lock, flags); | |
8563 | if (!h->remove_in_progress) | |
01192088 | 8564 | queue_delayed_work(h->monitor_ctlr_wq, &h->monitor_ctlr_work, |
8a98db73 SC |
8565 | h->heartbeat_sample_interval); |
8566 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
8567 | } |
8568 | ||
6636e7f4 DB |
8569 | static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h, |
8570 | char *name) | |
8571 | { | |
8572 | struct workqueue_struct *wq = NULL; | |
6636e7f4 | 8573 | |
397ea9cb | 8574 | wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr); |
6636e7f4 DB |
8575 | if (!wq) |
8576 | dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name); | |
8577 | ||
8578 | return wq; | |
8579 | } | |
8580 | ||
8b834bff ML |
8581 | static void hpda_free_ctlr_info(struct ctlr_info *h) |
8582 | { | |
8583 | kfree(h->reply_map); | |
8584 | kfree(h); | |
8585 | } | |
8586 | ||
8587 | static struct ctlr_info *hpda_alloc_ctlr_info(void) | |
8588 | { | |
8589 | struct ctlr_info *h; | |
8590 | ||
8591 | h = kzalloc(sizeof(*h), GFP_KERNEL); | |
8592 | if (!h) | |
8593 | return NULL; | |
8594 | ||
6396bb22 | 8595 | h->reply_map = kcalloc(nr_cpu_ids, sizeof(*h->reply_map), GFP_KERNEL); |
8b834bff ML |
8596 | if (!h->reply_map) { |
8597 | kfree(h); | |
8598 | return NULL; | |
8599 | } | |
8600 | return h; | |
8601 | } | |
8602 | ||
6f039790 | 8603 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 8604 | { |
4c2a8c40 | 8605 | int dac, rc; |
edd16368 | 8606 | struct ctlr_info *h; |
64670ac8 SC |
8607 | int try_soft_reset = 0; |
8608 | unsigned long flags; | |
6b6c1cd7 | 8609 | u32 board_id; |
edd16368 SC |
8610 | |
8611 | if (number_of_controllers == 0) | |
8612 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 8613 | |
135ae6ed | 8614 | rc = hpsa_lookup_board_id(pdev, &board_id, NULL); |
6b6c1cd7 TH |
8615 | if (rc < 0) { |
8616 | dev_warn(&pdev->dev, "Board ID not found\n"); | |
8617 | return rc; | |
8618 | } | |
8619 | ||
8620 | rc = hpsa_init_reset_devices(pdev, board_id); | |
64670ac8 SC |
8621 | if (rc) { |
8622 | if (rc != -ENOTSUPP) | |
8623 | return rc; | |
8624 | /* If the reset fails in a particular way (it has no way to do | |
8625 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
8626 | * a soft reset once we get the controller configured up to the | |
8627 | * point that it can accept a command. | |
8628 | */ | |
8629 | try_soft_reset = 1; | |
8630 | rc = 0; | |
8631 | } | |
8632 | ||
8633 | reinit_after_soft_reset: | |
edd16368 | 8634 | |
303932fd DB |
8635 | /* Command structures must be aligned on a 32-byte boundary because |
8636 | * the 5 lower bits of the address are used by the hardware. and by | |
8637 | * the driver. See comments in hpsa.h for more info. | |
8638 | */ | |
303932fd | 8639 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); |
8b834bff | 8640 | h = hpda_alloc_ctlr_info(); |
105a3dbc RE |
8641 | if (!h) { |
8642 | dev_err(&pdev->dev, "Failed to allocate controller head\n"); | |
ecd9aad4 | 8643 | return -ENOMEM; |
105a3dbc | 8644 | } |
edd16368 | 8645 | |
55c06c71 | 8646 | h->pdev = pdev; |
105a3dbc | 8647 | |
a9a3a273 | 8648 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9846590e | 8649 | INIT_LIST_HEAD(&h->offline_device_list); |
6eaf46fd | 8650 | spin_lock_init(&h->lock); |
9846590e | 8651 | spin_lock_init(&h->offline_device_lock); |
6eaf46fd | 8652 | spin_lock_init(&h->scan_lock); |
c59d04f3 | 8653 | spin_lock_init(&h->reset_lock); |
34f0c627 | 8654 | atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); |
094963da SC |
8655 | |
8656 | /* Allocate and clear per-cpu variable lockup_detected */ | |
8657 | h->lockup_detected = alloc_percpu(u32); | |
2a5ac326 | 8658 | if (!h->lockup_detected) { |
105a3dbc | 8659 | dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n"); |
2a5ac326 | 8660 | rc = -ENOMEM; |
2efa5929 | 8661 | goto clean1; /* aer/h */ |
2a5ac326 | 8662 | } |
094963da SC |
8663 | set_lockup_detected_for_all_cpus(h, 0); |
8664 | ||
55c06c71 | 8665 | rc = hpsa_pci_init(h); |
105a3dbc | 8666 | if (rc) |
2946e82b RE |
8667 | goto clean2; /* lu, aer/h */ |
8668 | ||
8669 | /* relies on h-> settings made by hpsa_pci_init, including | |
8670 | * interrupt_mode h->intr */ | |
8671 | rc = hpsa_scsi_host_alloc(h); | |
8672 | if (rc) | |
8673 | goto clean2_5; /* pci, lu, aer/h */ | |
edd16368 | 8674 | |
2946e82b | 8675 | sprintf(h->devname, HPSA "%d", h->scsi_host->host_no); |
edd16368 SC |
8676 | h->ctlr = number_of_controllers; |
8677 | number_of_controllers++; | |
edd16368 SC |
8678 | |
8679 | /* configure PCI DMA stuff */ | |
8bc8f47e | 8680 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)); |
ecd9aad4 | 8681 | if (rc == 0) { |
edd16368 | 8682 | dac = 1; |
ecd9aad4 | 8683 | } else { |
8bc8f47e | 8684 | rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
ecd9aad4 SC |
8685 | if (rc == 0) { |
8686 | dac = 0; | |
8687 | } else { | |
8688 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
2946e82b | 8689 | goto clean3; /* shost, pci, lu, aer/h */ |
ecd9aad4 | 8690 | } |
edd16368 SC |
8691 | } |
8692 | ||
8693 | /* make sure the board interrupts are off */ | |
8694 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 8695 | |
105a3dbc RE |
8696 | rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx); |
8697 | if (rc) | |
2946e82b | 8698 | goto clean3; /* shost, pci, lu, aer/h */ |
d37ffbe4 | 8699 | rc = hpsa_alloc_cmd_pool(h); |
8947fd10 | 8700 | if (rc) |
2946e82b | 8701 | goto clean4; /* irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8702 | rc = hpsa_alloc_sg_chain_blocks(h); |
8703 | if (rc) | |
2946e82b | 8704 | goto clean5; /* cmd, irq, shost, pci, lu, aer/h */ |
a08a8471 | 8705 | init_waitqueue_head(&h->scan_wait_queue); |
d604f533 WS |
8706 | init_waitqueue_head(&h->event_sync_wait_queue); |
8707 | mutex_init(&h->reset_mutex); | |
a08a8471 | 8708 | h->scan_finished = 1; /* no scan currently in progress */ |
87b9e6aa | 8709 | h->scan_waiting = 0; |
edd16368 SC |
8710 | |
8711 | pci_set_drvdata(pdev, h); | |
9a41338e | 8712 | h->ndevices = 0; |
2946e82b | 8713 | |
9a41338e | 8714 | spin_lock_init(&h->devlock); |
105a3dbc RE |
8715 | rc = hpsa_put_ctlr_into_performant_mode(h); |
8716 | if (rc) | |
2946e82b RE |
8717 | goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */ |
8718 | ||
2efa5929 RE |
8719 | /* create the resubmit workqueue */ |
8720 | h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan"); | |
8721 | if (!h->rescan_ctlr_wq) { | |
8722 | rc = -ENOMEM; | |
8723 | goto clean7; | |
8724 | } | |
8725 | ||
8726 | h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit"); | |
8727 | if (!h->resubmit_wq) { | |
8728 | rc = -ENOMEM; | |
8729 | goto clean7; /* aer/h */ | |
8730 | } | |
64670ac8 | 8731 | |
01192088 DB |
8732 | h->monitor_ctlr_wq = hpsa_create_controller_wq(h, "monitor"); |
8733 | if (!h->monitor_ctlr_wq) { | |
8734 | rc = -ENOMEM; | |
8735 | goto clean7; | |
8736 | } | |
8737 | ||
105a3dbc RE |
8738 | /* |
8739 | * At this point, the controller is ready to take commands. | |
64670ac8 SC |
8740 | * Now, if reset_devices and the hard reset didn't work, try |
8741 | * the soft reset and see if that works. | |
8742 | */ | |
8743 | if (try_soft_reset) { | |
8744 | ||
8745 | /* This is kind of gross. We may or may not get a completion | |
8746 | * from the soft reset command, and if we do, then the value | |
8747 | * from the fifo may or may not be valid. So, we wait 10 secs | |
8748 | * after the reset throwing away any completions we get during | |
8749 | * that time. Unregister the interrupt handler and register | |
8750 | * fake ones to scoop up any residual completions. | |
8751 | */ | |
8752 | spin_lock_irqsave(&h->lock, flags); | |
8753 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8754 | spin_unlock_irqrestore(&h->lock, flags); | |
ec501a18 | 8755 | hpsa_free_irqs(h); |
9ee61794 | 8756 | rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, |
64670ac8 SC |
8757 | hpsa_intx_discard_completions); |
8758 | if (rc) { | |
9ee61794 RE |
8759 | dev_warn(&h->pdev->dev, |
8760 | "Failed to request_irq after soft reset.\n"); | |
d498757c | 8761 | /* |
b2ef480c RE |
8762 | * cannot goto clean7 or free_irqs will be called |
8763 | * again. Instead, do its work | |
8764 | */ | |
8765 | hpsa_free_performant_mode(h); /* clean7 */ | |
8766 | hpsa_free_sg_chain_blocks(h); /* clean6 */ | |
8767 | hpsa_free_cmd_pool(h); /* clean5 */ | |
8768 | /* | |
8769 | * skip hpsa_free_irqs(h) clean4 since that | |
8770 | * was just called before request_irqs failed | |
d498757c RE |
8771 | */ |
8772 | goto clean3; | |
64670ac8 SC |
8773 | } |
8774 | ||
8775 | rc = hpsa_kdump_soft_reset(h); | |
8776 | if (rc) | |
8777 | /* Neither hard nor soft reset worked, we're hosed. */ | |
7ef7323f | 8778 | goto clean7; |
64670ac8 SC |
8779 | |
8780 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
8781 | dev_info(&h->pdev->dev, | |
8782 | "Waiting for stale completions to drain.\n"); | |
8783 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8784 | msleep(10000); | |
8785 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8786 | ||
8787 | rc = controller_reset_failed(h->cfgtable); | |
8788 | if (rc) | |
8789 | dev_info(&h->pdev->dev, | |
8790 | "Soft reset appears to have failed.\n"); | |
8791 | ||
8792 | /* since the controller's reset, we have to go back and re-init | |
8793 | * everything. Easiest to just forget what we've done and do it | |
8794 | * all over again. | |
8795 | */ | |
8796 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
8797 | try_soft_reset = 0; | |
8798 | if (rc) | |
b2ef480c | 8799 | /* don't goto clean, we already unallocated */ |
64670ac8 SC |
8800 | return -ENODEV; |
8801 | ||
8802 | goto reinit_after_soft_reset; | |
8803 | } | |
edd16368 | 8804 | |
105a3dbc RE |
8805 | /* Enable Accelerated IO path at driver layer */ |
8806 | h->acciopath_status = 1; | |
34592254 ST |
8807 | /* Disable discovery polling.*/ |
8808 | h->discovery_polling = 0; | |
da0697bd | 8809 | |
e863d68e | 8810 | |
edd16368 SC |
8811 | /* Turn the interrupts on so we can service requests */ |
8812 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
8813 | ||
339b2b14 | 8814 | hpsa_hba_inquiry(h); |
8a98db73 | 8815 | |
34592254 ST |
8816 | h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL); |
8817 | if (!h->lastlogicals) | |
8818 | dev_info(&h->pdev->dev, | |
8819 | "Can't track change to report lun data\n"); | |
8820 | ||
cf477237 DB |
8821 | /* hook into SCSI subsystem */ |
8822 | rc = hpsa_scsi_add_host(h); | |
8823 | if (rc) | |
8824 | goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ | |
8825 | ||
8a98db73 SC |
8826 | /* Monitor the controller for firmware lockups */ |
8827 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
8828 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
8829 | schedule_delayed_work(&h->monitor_ctlr_work, | |
8830 | h->heartbeat_sample_interval); | |
6636e7f4 DB |
8831 | INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker); |
8832 | queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work, | |
8833 | h->heartbeat_sample_interval); | |
3d38f00c ST |
8834 | INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker); |
8835 | schedule_delayed_work(&h->event_monitor_work, | |
8836 | HPSA_EVENT_MONITOR_INTERVAL); | |
88bf6d62 | 8837 | return 0; |
edd16368 | 8838 | |
2946e82b | 8839 | clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */ |
105a3dbc RE |
8840 | hpsa_free_performant_mode(h); |
8841 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
8842 | clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */ | |
33a2ffce | 8843 | hpsa_free_sg_chain_blocks(h); |
2946e82b | 8844 | clean5: /* cmd, irq, shost, pci, lu, aer/h */ |
2e9d1b36 | 8845 | hpsa_free_cmd_pool(h); |
2946e82b | 8846 | clean4: /* irq, shost, pci, lu, aer/h */ |
ec501a18 | 8847 | hpsa_free_irqs(h); |
2946e82b RE |
8848 | clean3: /* shost, pci, lu, aer/h */ |
8849 | scsi_host_put(h->scsi_host); | |
8850 | h->scsi_host = NULL; | |
8851 | clean2_5: /* pci, lu, aer/h */ | |
195f2c65 | 8852 | hpsa_free_pci_init(h); |
2946e82b | 8853 | clean2: /* lu, aer/h */ |
105a3dbc RE |
8854 | if (h->lockup_detected) { |
8855 | free_percpu(h->lockup_detected); | |
8856 | h->lockup_detected = NULL; | |
8857 | } | |
8858 | clean1: /* wq/aer/h */ | |
8859 | if (h->resubmit_wq) { | |
080ef1cc | 8860 | destroy_workqueue(h->resubmit_wq); |
105a3dbc RE |
8861 | h->resubmit_wq = NULL; |
8862 | } | |
8863 | if (h->rescan_ctlr_wq) { | |
6636e7f4 | 8864 | destroy_workqueue(h->rescan_ctlr_wq); |
105a3dbc RE |
8865 | h->rescan_ctlr_wq = NULL; |
8866 | } | |
01192088 DB |
8867 | if (h->monitor_ctlr_wq) { |
8868 | destroy_workqueue(h->monitor_ctlr_wq); | |
8869 | h->monitor_ctlr_wq = NULL; | |
8870 | } | |
edd16368 | 8871 | kfree(h); |
ecd9aad4 | 8872 | return rc; |
edd16368 SC |
8873 | } |
8874 | ||
8875 | static void hpsa_flush_cache(struct ctlr_info *h) | |
8876 | { | |
8877 | char *flush_buf; | |
8878 | struct CommandList *c; | |
25163bd5 | 8879 | int rc; |
702890e3 | 8880 | |
094963da | 8881 | if (unlikely(lockup_detected(h))) |
702890e3 | 8882 | return; |
edd16368 SC |
8883 | flush_buf = kzalloc(4, GFP_KERNEL); |
8884 | if (!flush_buf) | |
8885 | return; | |
8886 | ||
45fcb86e | 8887 | c = cmd_alloc(h); |
bf43caf3 | 8888 | |
a2dac136 SC |
8889 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
8890 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
8891 | goto out; | |
8892 | } | |
8bc8f47e CH |
8893 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE, |
8894 | DEFAULT_TIMEOUT); | |
25163bd5 WS |
8895 | if (rc) |
8896 | goto out; | |
edd16368 | 8897 | if (c->err_info->CommandStatus != 0) |
a2dac136 | 8898 | out: |
edd16368 SC |
8899 | dev_warn(&h->pdev->dev, |
8900 | "error flushing cache on controller\n"); | |
45fcb86e | 8901 | cmd_free(h, c); |
edd16368 SC |
8902 | kfree(flush_buf); |
8903 | } | |
8904 | ||
c2adae44 ST |
8905 | /* Make controller gather fresh report lun data each time we |
8906 | * send down a report luns request | |
8907 | */ | |
8908 | static void hpsa_disable_rld_caching(struct ctlr_info *h) | |
8909 | { | |
8910 | u32 *options; | |
8911 | struct CommandList *c; | |
8912 | int rc; | |
8913 | ||
8914 | /* Don't bother trying to set diag options if locked up */ | |
8915 | if (unlikely(h->lockup_detected)) | |
8916 | return; | |
8917 | ||
8918 | options = kzalloc(sizeof(*options), GFP_KERNEL); | |
7e8a9486 | 8919 | if (!options) |
c2adae44 | 8920 | return; |
c2adae44 ST |
8921 | |
8922 | c = cmd_alloc(h); | |
8923 | ||
8924 | /* first, get the current diag options settings */ | |
8925 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8926 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8927 | goto errout; | |
8928 | ||
8bc8f47e CH |
8929 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
8930 | NO_TIMEOUT); | |
c2adae44 ST |
8931 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8932 | goto errout; | |
8933 | ||
8934 | /* Now, set the bit for disabling the RLD caching */ | |
8935 | *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING; | |
8936 | ||
8937 | if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0, | |
8938 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8939 | goto errout; | |
8940 | ||
8bc8f47e CH |
8941 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE, |
8942 | NO_TIMEOUT); | |
c2adae44 ST |
8943 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8944 | goto errout; | |
8945 | ||
8946 | /* Now verify that it got set: */ | |
8947 | if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0, | |
8948 | RAID_CTLR_LUNID, TYPE_CMD)) | |
8949 | goto errout; | |
8950 | ||
8bc8f47e CH |
8951 | rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE, |
8952 | NO_TIMEOUT); | |
c2adae44 ST |
8953 | if ((rc != 0) || (c->err_info->CommandStatus != 0)) |
8954 | goto errout; | |
8955 | ||
d8a080c3 | 8956 | if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING) |
c2adae44 ST |
8957 | goto out; |
8958 | ||
8959 | errout: | |
8960 | dev_err(&h->pdev->dev, | |
8961 | "Error: failed to disable report lun data caching.\n"); | |
8962 | out: | |
8963 | cmd_free(h, c); | |
8964 | kfree(options); | |
8965 | } | |
8966 | ||
0d98ba8d | 8967 | static void __hpsa_shutdown(struct pci_dev *pdev) |
edd16368 SC |
8968 | { |
8969 | struct ctlr_info *h; | |
8970 | ||
8971 | h = pci_get_drvdata(pdev); | |
8972 | /* Turn board interrupts off and send the flush cache command | |
8973 | * sendcmd will turn off interrupt, and send the flush... | |
8974 | * To write all data in the battery backed cache to disks | |
8975 | */ | |
8976 | hpsa_flush_cache(h); | |
8977 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
105a3dbc | 8978 | hpsa_free_irqs(h); /* init_one 4 */ |
cc64c817 | 8979 | hpsa_disable_interrupt_mode(h); /* pci_init 2 */ |
edd16368 SC |
8980 | } |
8981 | ||
0d98ba8d SK |
8982 | static void hpsa_shutdown(struct pci_dev *pdev) |
8983 | { | |
8984 | __hpsa_shutdown(pdev); | |
8985 | pci_disable_device(pdev); | |
8986 | } | |
8987 | ||
6f039790 | 8988 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
8989 | { |
8990 | int i; | |
8991 | ||
105a3dbc | 8992 | for (i = 0; i < h->ndevices; i++) { |
55e14e76 | 8993 | kfree(h->dev[i]); |
105a3dbc RE |
8994 | h->dev[i] = NULL; |
8995 | } | |
55e14e76 SC |
8996 | } |
8997 | ||
6f039790 | 8998 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
8999 | { |
9000 | struct ctlr_info *h; | |
8a98db73 | 9001 | unsigned long flags; |
edd16368 SC |
9002 | |
9003 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 9004 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
9005 | return; |
9006 | } | |
9007 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
9008 | |
9009 | /* Get rid of any controller monitoring work items */ | |
9010 | spin_lock_irqsave(&h->lock, flags); | |
9011 | h->remove_in_progress = 1; | |
8a98db73 | 9012 | spin_unlock_irqrestore(&h->lock, flags); |
6636e7f4 DB |
9013 | cancel_delayed_work_sync(&h->monitor_ctlr_work); |
9014 | cancel_delayed_work_sync(&h->rescan_ctlr_work); | |
3d38f00c | 9015 | cancel_delayed_work_sync(&h->event_monitor_work); |
6636e7f4 DB |
9016 | destroy_workqueue(h->rescan_ctlr_wq); |
9017 | destroy_workqueue(h->resubmit_wq); | |
01192088 | 9018 | destroy_workqueue(h->monitor_ctlr_wq); |
cc64c817 | 9019 | |
dfb2e6f4 MW |
9020 | hpsa_delete_sas_host(h); |
9021 | ||
2d041306 DB |
9022 | /* |
9023 | * Call before disabling interrupts. | |
9024 | * scsi_remove_host can trigger I/O operations especially | |
9025 | * when multipath is enabled. There can be SYNCHRONIZE CACHE | |
9026 | * operations which cannot complete and will hang the system. | |
9027 | */ | |
9028 | if (h->scsi_host) | |
9029 | scsi_remove_host(h->scsi_host); /* init_one 8 */ | |
105a3dbc | 9030 | /* includes hpsa_free_irqs - init_one 4 */ |
195f2c65 | 9031 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
0d98ba8d | 9032 | __hpsa_shutdown(pdev); |
cc64c817 | 9033 | |
105a3dbc RE |
9034 | hpsa_free_device_info(h); /* scan */ |
9035 | ||
2946e82b RE |
9036 | kfree(h->hba_inquiry_data); /* init_one 10 */ |
9037 | h->hba_inquiry_data = NULL; /* init_one 10 */ | |
2946e82b | 9038 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
105a3dbc RE |
9039 | hpsa_free_performant_mode(h); /* init_one 7 */ |
9040 | hpsa_free_sg_chain_blocks(h); /* init_one 6 */ | |
9041 | hpsa_free_cmd_pool(h); /* init_one 5 */ | |
34592254 | 9042 | kfree(h->lastlogicals); |
105a3dbc RE |
9043 | |
9044 | /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */ | |
195f2c65 | 9045 | |
2946e82b RE |
9046 | scsi_host_put(h->scsi_host); /* init_one 3 */ |
9047 | h->scsi_host = NULL; /* init_one 3 */ | |
9048 | ||
195f2c65 | 9049 | /* includes hpsa_disable_interrupt_mode - pci_init 2 */ |
2946e82b | 9050 | hpsa_free_pci_init(h); /* init_one 2.5 */ |
195f2c65 | 9051 | |
105a3dbc RE |
9052 | free_percpu(h->lockup_detected); /* init_one 2 */ |
9053 | h->lockup_detected = NULL; /* init_one 2 */ | |
9054 | /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */ | |
d04e62b9 | 9055 | |
8b834bff | 9056 | hpda_free_ctlr_info(h); /* init_one 1 */ |
edd16368 SC |
9057 | } |
9058 | ||
9059 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
9060 | __attribute__((unused)) pm_message_t state) | |
9061 | { | |
9062 | return -ENOSYS; | |
9063 | } | |
9064 | ||
9065 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
9066 | { | |
9067 | return -ENOSYS; | |
9068 | } | |
9069 | ||
9070 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 9071 | .name = HPSA, |
edd16368 | 9072 | .probe = hpsa_init_one, |
6f039790 | 9073 | .remove = hpsa_remove_one, |
edd16368 SC |
9074 | .id_table = hpsa_pci_device_id, /* id_table */ |
9075 | .shutdown = hpsa_shutdown, | |
9076 | .suspend = hpsa_suspend, | |
9077 | .resume = hpsa_resume, | |
9078 | }; | |
9079 | ||
303932fd DB |
9080 | /* Fill in bucket_map[], given nsgs (the max number of |
9081 | * scatter gather elements supported) and bucket[], | |
9082 | * which is an array of 8 integers. The bucket[] array | |
9083 | * contains 8 different DMA transfer sizes (in 16 | |
9084 | * byte increments) which the controller uses to fetch | |
9085 | * commands. This function fills in bucket_map[], which | |
9086 | * maps a given number of scatter gather elements to one of | |
9087 | * the 8 DMA transfer sizes. The point of it is to allow the | |
9088 | * controller to only do as much DMA as needed to fetch the | |
9089 | * command, with the DMA transfer size encoded in the lower | |
9090 | * bits of the command address. | |
9091 | */ | |
9092 | static void calc_bucket_map(int bucket[], int num_buckets, | |
2b08b3e9 | 9093 | int nsgs, int min_blocks, u32 *bucket_map) |
303932fd DB |
9094 | { |
9095 | int i, j, b, size; | |
9096 | ||
303932fd DB |
9097 | /* Note, bucket_map must have nsgs+1 entries. */ |
9098 | for (i = 0; i <= nsgs; i++) { | |
9099 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 9100 | size = i + min_blocks; |
303932fd DB |
9101 | b = num_buckets; /* Assume the biggest bucket */ |
9102 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 9103 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
9104 | if (bucket[j] >= size) { |
9105 | b = j; | |
9106 | break; | |
9107 | } | |
9108 | } | |
9109 | /* for a command with i SG entries, use bucket b. */ | |
9110 | bucket_map[i] = b; | |
9111 | } | |
9112 | } | |
9113 | ||
105a3dbc RE |
9114 | /* |
9115 | * return -ENODEV on err, 0 on success (or no action) | |
9116 | * allocates numerous items that must be freed later | |
9117 | */ | |
c706a795 | 9118 | static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 9119 | { |
6c311b57 SC |
9120 | int i; |
9121 | unsigned long register_value; | |
e1f7de0c MG |
9122 | unsigned long transMethod = CFGTBL_Trans_Performant | |
9123 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
b9af4937 SC |
9124 | CFGTBL_Trans_enable_directed_msix | |
9125 | (trans_support & (CFGTBL_Trans_io_accel1 | | |
9126 | CFGTBL_Trans_io_accel2)); | |
e1f7de0c | 9127 | struct access_method access = SA5_performant_access; |
def342bd SC |
9128 | |
9129 | /* This is a bit complicated. There are 8 registers on | |
9130 | * the controller which we write to to tell it 8 different | |
9131 | * sizes of commands which there may be. It's a way of | |
9132 | * reducing the DMA done to fetch each command. Encoded into | |
9133 | * each command's tag are 3 bits which communicate to the controller | |
9134 | * which of the eight sizes that command fits within. The size of | |
9135 | * each command depends on how many scatter gather entries there are. | |
9136 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
9137 | * with the number of 16-byte blocks a command of that size requires. | |
9138 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 9139 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
9140 | * blocks. Note, this only extends to the SG entries contained |
9141 | * within the command block, and does not extend to chained blocks | |
9142 | * of SG elements. bft[] contains the eight values we write to | |
9143 | * the registers. They are not evenly distributed, but have more | |
9144 | * sizes for small commands, and fewer sizes for larger commands. | |
9145 | */ | |
d66ae08b | 9146 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
b9af4937 SC |
9147 | #define MIN_IOACCEL2_BFT_ENTRY 5 |
9148 | #define HPSA_IOACCEL2_HEADER_SZ 4 | |
9149 | int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, | |
9150 | 13, 14, 15, 16, 17, 18, 19, | |
9151 | HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; | |
9152 | BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); | |
9153 | BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); | |
9154 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > | |
9155 | 16 * MIN_IOACCEL2_BFT_ENTRY); | |
9156 | BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); | |
d66ae08b | 9157 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); |
303932fd DB |
9158 | /* 5 = 1 s/g entry or 4k |
9159 | * 6 = 2 s/g entry or 8k | |
9160 | * 8 = 4 s/g entry or 16k | |
9161 | * 10 = 6 s/g entry or 24k | |
9162 | */ | |
303932fd | 9163 | |
b3a52e79 SC |
9164 | /* If the controller supports either ioaccel method then |
9165 | * we can also use the RAID stack submit path that does not | |
9166 | * perform the superfluous readl() after each command submission. | |
9167 | */ | |
9168 | if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) | |
9169 | access = SA5_performant_access_no_read; | |
9170 | ||
303932fd | 9171 | /* Controller spec: zero out this buffer. */ |
072b0518 SC |
9172 | for (i = 0; i < h->nreply_queues; i++) |
9173 | memset(h->reply_queue[i].head, 0, h->reply_queue_size); | |
303932fd | 9174 | |
d66ae08b SC |
9175 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
9176 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 9177 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
9178 | for (i = 0; i < 8; i++) |
9179 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
9180 | ||
9181 | /* size of controller ring buffer */ | |
9182 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 9183 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
9184 | writel(0, &h->transtable->RepQCtrAddrLow32); |
9185 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
9186 | |
9187 | for (i = 0; i < h->nreply_queues; i++) { | |
9188 | writel(0, &h->transtable->RepQAddr[i].upper); | |
072b0518 | 9189 | writel(h->reply_queue[i].busaddr, |
254f796b MG |
9190 | &h->transtable->RepQAddr[i].lower); |
9191 | } | |
9192 | ||
b9af4937 | 9193 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
e1f7de0c MG |
9194 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
9195 | /* | |
9196 | * enable outbound interrupt coalescing in accelerator mode; | |
9197 | */ | |
9198 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
9199 | access = SA5_ioaccel_mode1_access; | |
9200 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
9201 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
96b6ce4e DB |
9202 | } else |
9203 | if (trans_support & CFGTBL_Trans_io_accel2) | |
c349775e | 9204 | access = SA5_ioaccel_mode2_access; |
303932fd | 9205 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
9206 | if (hpsa_wait_for_mode_change_ack(h)) { |
9207 | dev_err(&h->pdev->dev, | |
9208 | "performant mode problem - doorbell timeout\n"); | |
9209 | return -ENODEV; | |
9210 | } | |
303932fd DB |
9211 | register_value = readl(&(h->cfgtable->TransportActive)); |
9212 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
050f7147 SC |
9213 | dev_err(&h->pdev->dev, |
9214 | "performant mode problem - transport not active\n"); | |
c706a795 | 9215 | return -ENODEV; |
303932fd | 9216 | } |
960a30e7 | 9217 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
9218 | h->access = access; |
9219 | h->transMethod = transMethod; | |
9220 | ||
b9af4937 SC |
9221 | if (!((trans_support & CFGTBL_Trans_io_accel1) || |
9222 | (trans_support & CFGTBL_Trans_io_accel2))) | |
c706a795 | 9223 | return 0; |
e1f7de0c | 9224 | |
b9af4937 SC |
9225 | if (trans_support & CFGTBL_Trans_io_accel1) { |
9226 | /* Set up I/O accelerator mode */ | |
9227 | for (i = 0; i < h->nreply_queues; i++) { | |
9228 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
9229 | h->reply_queue[i].current_entry = | |
9230 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
9231 | } | |
9232 | bft[7] = h->ioaccel_maxsg + 8; | |
9233 | calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, | |
9234 | h->ioaccel1_blockFetchTable); | |
e1f7de0c | 9235 | |
b9af4937 | 9236 | /* initialize all reply queue entries to unused */ |
072b0518 SC |
9237 | for (i = 0; i < h->nreply_queues; i++) |
9238 | memset(h->reply_queue[i].head, | |
9239 | (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
9240 | h->reply_queue_size); | |
e1f7de0c | 9241 | |
b9af4937 SC |
9242 | /* set all the constant fields in the accelerator command |
9243 | * frames once at init time to save CPU cycles later. | |
9244 | */ | |
9245 | for (i = 0; i < h->nr_cmds; i++) { | |
9246 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
9247 | ||
9248 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
9249 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
9250 | (i * sizeof(struct ErrorInfo))); | |
9251 | cp->err_info_len = sizeof(struct ErrorInfo); | |
9252 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
2b08b3e9 DB |
9253 | cp->host_context_flags = |
9254 | cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); | |
b9af4937 SC |
9255 | cp->timeout_sec = 0; |
9256 | cp->ReplyQueue = 0; | |
50a0decf | 9257 | cp->tag = |
f2405db8 | 9258 | cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); |
50a0decf SC |
9259 | cp->host_addr = |
9260 | cpu_to_le64(h->ioaccel_cmd_pool_dhandle + | |
b9af4937 | 9261 | (i * sizeof(struct io_accel1_cmd))); |
b9af4937 SC |
9262 | } |
9263 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
9264 | u64 cfg_offset, cfg_base_addr_index; | |
9265 | u32 bft2_offset, cfg_base_addr; | |
9266 | int rc; | |
9267 | ||
9268 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, | |
9269 | &cfg_base_addr_index, &cfg_offset); | |
9270 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); | |
9271 | bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; | |
9272 | calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, | |
9273 | 4, h->ioaccel2_blockFetchTable); | |
9274 | bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); | |
9275 | BUILD_BUG_ON(offsetof(struct CfgTable, | |
9276 | io_accel_request_size_offset) != 0xb8); | |
9277 | h->ioaccel2_bft2_regs = | |
9278 | remap_pci_mem(pci_resource_start(h->pdev, | |
9279 | cfg_base_addr_index) + | |
9280 | cfg_offset + bft2_offset, | |
9281 | ARRAY_SIZE(bft2) * | |
9282 | sizeof(*h->ioaccel2_bft2_regs)); | |
9283 | for (i = 0; i < ARRAY_SIZE(bft2); i++) | |
9284 | writel(bft2[i], &h->ioaccel2_bft2_regs[i]); | |
e1f7de0c | 9285 | } |
b9af4937 | 9286 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
c706a795 RE |
9287 | if (hpsa_wait_for_mode_change_ack(h)) { |
9288 | dev_err(&h->pdev->dev, | |
9289 | "performant mode problem - enabling ioaccel mode\n"); | |
9290 | return -ENODEV; | |
9291 | } | |
9292 | return 0; | |
e1f7de0c MG |
9293 | } |
9294 | ||
1fb7c98a RE |
9295 | /* Free ioaccel1 mode command blocks and block fetch table */ |
9296 | static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
9297 | { | |
105a3dbc | 9298 | if (h->ioaccel_cmd_pool) { |
1fb7c98a RE |
9299 | pci_free_consistent(h->pdev, |
9300 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
9301 | h->ioaccel_cmd_pool, | |
9302 | h->ioaccel_cmd_pool_dhandle); | |
105a3dbc RE |
9303 | h->ioaccel_cmd_pool = NULL; |
9304 | h->ioaccel_cmd_pool_dhandle = 0; | |
9305 | } | |
1fb7c98a | 9306 | kfree(h->ioaccel1_blockFetchTable); |
105a3dbc | 9307 | h->ioaccel1_blockFetchTable = NULL; |
1fb7c98a RE |
9308 | } |
9309 | ||
d37ffbe4 RE |
9310 | /* Allocate ioaccel1 mode command blocks and block fetch table */ |
9311 | static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h) | |
e1f7de0c | 9312 | { |
283b4a9b SC |
9313 | h->ioaccel_maxsg = |
9314 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9315 | if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) | |
9316 | h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; | |
9317 | ||
e1f7de0c MG |
9318 | /* Command structures must be aligned on a 128-byte boundary |
9319 | * because the 7 lower bits of the address are used by the | |
9320 | * hardware. | |
9321 | */ | |
e1f7de0c MG |
9322 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % |
9323 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
9324 | h->ioaccel_cmd_pool = | |
8bc8f47e | 9325 | dma_alloc_coherent(&h->pdev->dev, |
e1f7de0c | 9326 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), |
8bc8f47e | 9327 | &h->ioaccel_cmd_pool_dhandle, GFP_KERNEL); |
e1f7de0c MG |
9328 | |
9329 | h->ioaccel1_blockFetchTable = | |
283b4a9b | 9330 | kmalloc(((h->ioaccel_maxsg + 1) * |
e1f7de0c MG |
9331 | sizeof(u32)), GFP_KERNEL); |
9332 | ||
9333 | if ((h->ioaccel_cmd_pool == NULL) || | |
9334 | (h->ioaccel1_blockFetchTable == NULL)) | |
9335 | goto clean_up; | |
9336 | ||
9337 | memset(h->ioaccel_cmd_pool, 0, | |
9338 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
9339 | return 0; | |
9340 | ||
9341 | clean_up: | |
1fb7c98a | 9342 | hpsa_free_ioaccel1_cmd_and_bft(h); |
2dd02d74 | 9343 | return -ENOMEM; |
6c311b57 SC |
9344 | } |
9345 | ||
1fb7c98a RE |
9346 | /* Free ioaccel2 mode command blocks and block fetch table */ |
9347 | static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
9348 | { | |
d9a729f3 WS |
9349 | hpsa_free_ioaccel2_sg_chain_blocks(h); |
9350 | ||
105a3dbc | 9351 | if (h->ioaccel2_cmd_pool) { |
1fb7c98a RE |
9352 | pci_free_consistent(h->pdev, |
9353 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
9354 | h->ioaccel2_cmd_pool, | |
9355 | h->ioaccel2_cmd_pool_dhandle); | |
105a3dbc RE |
9356 | h->ioaccel2_cmd_pool = NULL; |
9357 | h->ioaccel2_cmd_pool_dhandle = 0; | |
9358 | } | |
1fb7c98a | 9359 | kfree(h->ioaccel2_blockFetchTable); |
105a3dbc | 9360 | h->ioaccel2_blockFetchTable = NULL; |
1fb7c98a RE |
9361 | } |
9362 | ||
d37ffbe4 RE |
9363 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9364 | static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h) | |
aca9012a | 9365 | { |
d9a729f3 WS |
9366 | int rc; |
9367 | ||
aca9012a SC |
9368 | /* Allocate ioaccel2 mode command blocks and block fetch table */ |
9369 | ||
9370 | h->ioaccel_maxsg = | |
9371 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
9372 | if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) | |
9373 | h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; | |
9374 | ||
aca9012a SC |
9375 | BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % |
9376 | IOACCEL2_COMMANDLIST_ALIGNMENT); | |
9377 | h->ioaccel2_cmd_pool = | |
8bc8f47e | 9378 | dma_alloc_coherent(&h->pdev->dev, |
aca9012a | 9379 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), |
8bc8f47e | 9380 | &h->ioaccel2_cmd_pool_dhandle, GFP_KERNEL); |
aca9012a SC |
9381 | |
9382 | h->ioaccel2_blockFetchTable = | |
9383 | kmalloc(((h->ioaccel_maxsg + 1) * | |
9384 | sizeof(u32)), GFP_KERNEL); | |
9385 | ||
9386 | if ((h->ioaccel2_cmd_pool == NULL) || | |
d9a729f3 WS |
9387 | (h->ioaccel2_blockFetchTable == NULL)) { |
9388 | rc = -ENOMEM; | |
9389 | goto clean_up; | |
9390 | } | |
9391 | ||
9392 | rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h); | |
9393 | if (rc) | |
aca9012a SC |
9394 | goto clean_up; |
9395 | ||
9396 | memset(h->ioaccel2_cmd_pool, 0, | |
9397 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); | |
9398 | return 0; | |
9399 | ||
9400 | clean_up: | |
1fb7c98a | 9401 | hpsa_free_ioaccel2_cmd_and_bft(h); |
d9a729f3 | 9402 | return rc; |
aca9012a SC |
9403 | } |
9404 | ||
105a3dbc RE |
9405 | /* Free items allocated by hpsa_put_ctlr_into_performant_mode */ |
9406 | static void hpsa_free_performant_mode(struct ctlr_info *h) | |
9407 | { | |
9408 | kfree(h->blockFetchTable); | |
9409 | h->blockFetchTable = NULL; | |
9410 | hpsa_free_reply_queues(h); | |
9411 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9412 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9413 | } | |
9414 | ||
9415 | /* return -ENODEV on error, 0 on success (or no action) | |
9416 | * allocates numerous items that must be freed later | |
9417 | */ | |
9418 | static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) | |
6c311b57 SC |
9419 | { |
9420 | u32 trans_support; | |
e1f7de0c MG |
9421 | unsigned long transMethod = CFGTBL_Trans_Performant | |
9422 | CFGTBL_Trans_use_short_tags; | |
105a3dbc | 9423 | int i, rc; |
6c311b57 | 9424 | |
02ec19c8 | 9425 | if (hpsa_simple_mode) |
105a3dbc | 9426 | return 0; |
02ec19c8 | 9427 | |
67c99a72 | 9428 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
9429 | if (!(trans_support & PERFORMANT_MODE)) | |
105a3dbc | 9430 | return 0; |
67c99a72 | 9431 | |
e1f7de0c MG |
9432 | /* Check for I/O accelerator mode support */ |
9433 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
9434 | transMethod |= CFGTBL_Trans_io_accel1 | | |
9435 | CFGTBL_Trans_enable_directed_msix; | |
105a3dbc RE |
9436 | rc = hpsa_alloc_ioaccel1_cmd_and_bft(h); |
9437 | if (rc) | |
9438 | return rc; | |
9439 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
9440 | transMethod |= CFGTBL_Trans_io_accel2 | | |
aca9012a | 9441 | CFGTBL_Trans_enable_directed_msix; |
105a3dbc RE |
9442 | rc = hpsa_alloc_ioaccel2_cmd_and_bft(h); |
9443 | if (rc) | |
9444 | return rc; | |
e1f7de0c MG |
9445 | } |
9446 | ||
bc2bb154 | 9447 | h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1; |
cba3d38b | 9448 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 9449 | /* Performant mode ring buffer and supporting data structures */ |
072b0518 | 9450 | h->reply_queue_size = h->max_commands * sizeof(u64); |
6c311b57 | 9451 | |
254f796b | 9452 | for (i = 0; i < h->nreply_queues; i++) { |
8bc8f47e | 9453 | h->reply_queue[i].head = dma_alloc_coherent(&h->pdev->dev, |
072b0518 | 9454 | h->reply_queue_size, |
8bc8f47e CH |
9455 | &h->reply_queue[i].busaddr, |
9456 | GFP_KERNEL); | |
105a3dbc RE |
9457 | if (!h->reply_queue[i].head) { |
9458 | rc = -ENOMEM; | |
9459 | goto clean1; /* rq, ioaccel */ | |
9460 | } | |
254f796b MG |
9461 | h->reply_queue[i].size = h->max_commands; |
9462 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
9463 | h->reply_queue[i].current_entry = 0; | |
9464 | } | |
9465 | ||
6c311b57 | 9466 | /* Need a block fetch table for performant mode */ |
d66ae08b | 9467 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 | 9468 | sizeof(u32)), GFP_KERNEL); |
105a3dbc RE |
9469 | if (!h->blockFetchTable) { |
9470 | rc = -ENOMEM; | |
9471 | goto clean1; /* rq, ioaccel */ | |
9472 | } | |
6c311b57 | 9473 | |
105a3dbc RE |
9474 | rc = hpsa_enter_performant_mode(h, trans_support); |
9475 | if (rc) | |
9476 | goto clean2; /* bft, rq, ioaccel */ | |
9477 | return 0; | |
303932fd | 9478 | |
105a3dbc | 9479 | clean2: /* bft, rq, ioaccel */ |
303932fd | 9480 | kfree(h->blockFetchTable); |
105a3dbc RE |
9481 | h->blockFetchTable = NULL; |
9482 | clean1: /* rq, ioaccel */ | |
9483 | hpsa_free_reply_queues(h); | |
9484 | hpsa_free_ioaccel1_cmd_and_bft(h); | |
9485 | hpsa_free_ioaccel2_cmd_and_bft(h); | |
9486 | return rc; | |
303932fd DB |
9487 | } |
9488 | ||
23100dd9 | 9489 | static int is_accelerated_cmd(struct CommandList *c) |
76438d08 | 9490 | { |
23100dd9 SC |
9491 | return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; |
9492 | } | |
9493 | ||
9494 | static void hpsa_drain_accel_commands(struct ctlr_info *h) | |
9495 | { | |
9496 | struct CommandList *c = NULL; | |
f2405db8 | 9497 | int i, accel_cmds_out; |
281a7fd0 | 9498 | int refcount; |
76438d08 | 9499 | |
f2405db8 | 9500 | do { /* wait for all outstanding ioaccel commands to drain out */ |
23100dd9 | 9501 | accel_cmds_out = 0; |
f2405db8 | 9502 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 9503 | c = h->cmd_pool + i; |
281a7fd0 WS |
9504 | refcount = atomic_inc_return(&c->refcount); |
9505 | if (refcount > 1) /* Command is allocated */ | |
9506 | accel_cmds_out += is_accelerated_cmd(c); | |
9507 | cmd_free(h, c); | |
f2405db8 | 9508 | } |
23100dd9 | 9509 | if (accel_cmds_out <= 0) |
281a7fd0 | 9510 | break; |
76438d08 SC |
9511 | msleep(100); |
9512 | } while (1); | |
9513 | } | |
9514 | ||
d04e62b9 KB |
9515 | static struct hpsa_sas_phy *hpsa_alloc_sas_phy( |
9516 | struct hpsa_sas_port *hpsa_sas_port) | |
9517 | { | |
9518 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9519 | struct sas_phy *phy; | |
9520 | ||
9521 | hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL); | |
9522 | if (!hpsa_sas_phy) | |
9523 | return NULL; | |
9524 | ||
9525 | phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev, | |
9526 | hpsa_sas_port->next_phy_index); | |
9527 | if (!phy) { | |
9528 | kfree(hpsa_sas_phy); | |
9529 | return NULL; | |
9530 | } | |
9531 | ||
9532 | hpsa_sas_port->next_phy_index++; | |
9533 | hpsa_sas_phy->phy = phy; | |
9534 | hpsa_sas_phy->parent_port = hpsa_sas_port; | |
9535 | ||
9536 | return hpsa_sas_phy; | |
9537 | } | |
9538 | ||
9539 | static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9540 | { | |
9541 | struct sas_phy *phy = hpsa_sas_phy->phy; | |
9542 | ||
9543 | sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy); | |
d04e62b9 KB |
9544 | if (hpsa_sas_phy->added_to_port) |
9545 | list_del(&hpsa_sas_phy->phy_list_entry); | |
55ca38b4 | 9546 | sas_phy_delete(phy); |
d04e62b9 KB |
9547 | kfree(hpsa_sas_phy); |
9548 | } | |
9549 | ||
9550 | static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy) | |
9551 | { | |
9552 | int rc; | |
9553 | struct hpsa_sas_port *hpsa_sas_port; | |
9554 | struct sas_phy *phy; | |
9555 | struct sas_identify *identify; | |
9556 | ||
9557 | hpsa_sas_port = hpsa_sas_phy->parent_port; | |
9558 | phy = hpsa_sas_phy->phy; | |
9559 | ||
9560 | identify = &phy->identify; | |
9561 | memset(identify, 0, sizeof(*identify)); | |
9562 | identify->sas_address = hpsa_sas_port->sas_address; | |
9563 | identify->device_type = SAS_END_DEVICE; | |
9564 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9565 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9566 | phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9567 | phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN; | |
9568 | phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9569 | phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9570 | phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN; | |
9571 | ||
9572 | rc = sas_phy_add(hpsa_sas_phy->phy); | |
9573 | if (rc) | |
9574 | return rc; | |
9575 | ||
9576 | sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy); | |
9577 | list_add_tail(&hpsa_sas_phy->phy_list_entry, | |
9578 | &hpsa_sas_port->phy_list_head); | |
9579 | hpsa_sas_phy->added_to_port = true; | |
9580 | ||
9581 | return 0; | |
9582 | } | |
9583 | ||
9584 | static int | |
9585 | hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port, | |
9586 | struct sas_rphy *rphy) | |
9587 | { | |
9588 | struct sas_identify *identify; | |
9589 | ||
9590 | identify = &rphy->identify; | |
9591 | identify->sas_address = hpsa_sas_port->sas_address; | |
9592 | identify->initiator_port_protocols = SAS_PROTOCOL_STP; | |
9593 | identify->target_port_protocols = SAS_PROTOCOL_STP; | |
9594 | ||
9595 | return sas_rphy_add(rphy); | |
9596 | } | |
9597 | ||
9598 | static struct hpsa_sas_port | |
9599 | *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node, | |
9600 | u64 sas_address) | |
9601 | { | |
9602 | int rc; | |
9603 | struct hpsa_sas_port *hpsa_sas_port; | |
9604 | struct sas_port *port; | |
9605 | ||
9606 | hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL); | |
9607 | if (!hpsa_sas_port) | |
9608 | return NULL; | |
9609 | ||
9610 | INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head); | |
9611 | hpsa_sas_port->parent_node = hpsa_sas_node; | |
9612 | ||
9613 | port = sas_port_alloc_num(hpsa_sas_node->parent_dev); | |
9614 | if (!port) | |
9615 | goto free_hpsa_port; | |
9616 | ||
9617 | rc = sas_port_add(port); | |
9618 | if (rc) | |
9619 | goto free_sas_port; | |
9620 | ||
9621 | hpsa_sas_port->port = port; | |
9622 | hpsa_sas_port->sas_address = sas_address; | |
9623 | list_add_tail(&hpsa_sas_port->port_list_entry, | |
9624 | &hpsa_sas_node->port_list_head); | |
9625 | ||
9626 | return hpsa_sas_port; | |
9627 | ||
9628 | free_sas_port: | |
9629 | sas_port_free(port); | |
9630 | free_hpsa_port: | |
9631 | kfree(hpsa_sas_port); | |
9632 | ||
9633 | return NULL; | |
9634 | } | |
9635 | ||
9636 | static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port) | |
9637 | { | |
9638 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9639 | struct hpsa_sas_phy *next; | |
9640 | ||
9641 | list_for_each_entry_safe(hpsa_sas_phy, next, | |
9642 | &hpsa_sas_port->phy_list_head, phy_list_entry) | |
9643 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9644 | ||
9645 | sas_port_delete(hpsa_sas_port->port); | |
9646 | list_del(&hpsa_sas_port->port_list_entry); | |
9647 | kfree(hpsa_sas_port); | |
9648 | } | |
9649 | ||
9650 | static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev) | |
9651 | { | |
9652 | struct hpsa_sas_node *hpsa_sas_node; | |
9653 | ||
9654 | hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL); | |
9655 | if (hpsa_sas_node) { | |
9656 | hpsa_sas_node->parent_dev = parent_dev; | |
9657 | INIT_LIST_HEAD(&hpsa_sas_node->port_list_head); | |
9658 | } | |
9659 | ||
9660 | return hpsa_sas_node; | |
9661 | } | |
9662 | ||
9663 | static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node) | |
9664 | { | |
9665 | struct hpsa_sas_port *hpsa_sas_port; | |
9666 | struct hpsa_sas_port *next; | |
9667 | ||
9668 | if (!hpsa_sas_node) | |
9669 | return; | |
9670 | ||
9671 | list_for_each_entry_safe(hpsa_sas_port, next, | |
9672 | &hpsa_sas_node->port_list_head, port_list_entry) | |
9673 | hpsa_free_sas_port(hpsa_sas_port); | |
9674 | ||
9675 | kfree(hpsa_sas_node); | |
9676 | } | |
9677 | ||
9678 | static struct hpsa_scsi_dev_t | |
9679 | *hpsa_find_device_by_sas_rphy(struct ctlr_info *h, | |
9680 | struct sas_rphy *rphy) | |
9681 | { | |
9682 | int i; | |
9683 | struct hpsa_scsi_dev_t *device; | |
9684 | ||
9685 | for (i = 0; i < h->ndevices; i++) { | |
9686 | device = h->dev[i]; | |
9687 | if (!device->sas_port) | |
9688 | continue; | |
9689 | if (device->sas_port->rphy == rphy) | |
9690 | return device; | |
9691 | } | |
9692 | ||
9693 | return NULL; | |
9694 | } | |
9695 | ||
9696 | static int hpsa_add_sas_host(struct ctlr_info *h) | |
9697 | { | |
9698 | int rc; | |
9699 | struct device *parent_dev; | |
9700 | struct hpsa_sas_node *hpsa_sas_node; | |
9701 | struct hpsa_sas_port *hpsa_sas_port; | |
9702 | struct hpsa_sas_phy *hpsa_sas_phy; | |
9703 | ||
0a7c3bb8 | 9704 | parent_dev = &h->scsi_host->shost_dev; |
d04e62b9 KB |
9705 | |
9706 | hpsa_sas_node = hpsa_alloc_sas_node(parent_dev); | |
9707 | if (!hpsa_sas_node) | |
9708 | return -ENOMEM; | |
9709 | ||
9710 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address); | |
9711 | if (!hpsa_sas_port) { | |
9712 | rc = -ENODEV; | |
9713 | goto free_sas_node; | |
9714 | } | |
9715 | ||
9716 | hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port); | |
9717 | if (!hpsa_sas_phy) { | |
9718 | rc = -ENODEV; | |
9719 | goto free_sas_port; | |
9720 | } | |
9721 | ||
9722 | rc = hpsa_sas_port_add_phy(hpsa_sas_phy); | |
9723 | if (rc) | |
9724 | goto free_sas_phy; | |
9725 | ||
9726 | h->sas_host = hpsa_sas_node; | |
9727 | ||
9728 | return 0; | |
9729 | ||
9730 | free_sas_phy: | |
9731 | hpsa_free_sas_phy(hpsa_sas_phy); | |
9732 | free_sas_port: | |
9733 | hpsa_free_sas_port(hpsa_sas_port); | |
9734 | free_sas_node: | |
9735 | hpsa_free_sas_node(hpsa_sas_node); | |
9736 | ||
9737 | return rc; | |
9738 | } | |
9739 | ||
9740 | static void hpsa_delete_sas_host(struct ctlr_info *h) | |
9741 | { | |
9742 | hpsa_free_sas_node(h->sas_host); | |
9743 | } | |
9744 | ||
9745 | static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node, | |
9746 | struct hpsa_scsi_dev_t *device) | |
9747 | { | |
9748 | int rc; | |
9749 | struct hpsa_sas_port *hpsa_sas_port; | |
9750 | struct sas_rphy *rphy; | |
9751 | ||
9752 | hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address); | |
9753 | if (!hpsa_sas_port) | |
9754 | return -ENOMEM; | |
9755 | ||
9756 | rphy = sas_end_device_alloc(hpsa_sas_port->port); | |
9757 | if (!rphy) { | |
9758 | rc = -ENODEV; | |
9759 | goto free_sas_port; | |
9760 | } | |
9761 | ||
9762 | hpsa_sas_port->rphy = rphy; | |
9763 | device->sas_port = hpsa_sas_port; | |
9764 | ||
9765 | rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy); | |
9766 | if (rc) | |
9767 | goto free_sas_port; | |
9768 | ||
9769 | return 0; | |
9770 | ||
9771 | free_sas_port: | |
9772 | hpsa_free_sas_port(hpsa_sas_port); | |
9773 | device->sas_port = NULL; | |
9774 | ||
9775 | return rc; | |
9776 | } | |
9777 | ||
9778 | static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device) | |
9779 | { | |
9780 | if (device->sas_port) { | |
9781 | hpsa_free_sas_port(device->sas_port); | |
9782 | device->sas_port = NULL; | |
9783 | } | |
9784 | } | |
9785 | ||
9786 | static int | |
9787 | hpsa_sas_get_linkerrors(struct sas_phy *phy) | |
9788 | { | |
9789 | return 0; | |
9790 | } | |
9791 | ||
9792 | static int | |
9793 | hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier) | |
9794 | { | |
01d0e789 DB |
9795 | struct Scsi_Host *shost = phy_to_shost(rphy); |
9796 | struct ctlr_info *h; | |
9797 | struct hpsa_scsi_dev_t *sd; | |
9798 | ||
9799 | if (!shost) | |
9800 | return -ENXIO; | |
9801 | ||
9802 | h = shost_to_hba(shost); | |
9803 | ||
9804 | if (!h) | |
9805 | return -ENXIO; | |
9806 | ||
9807 | sd = hpsa_find_device_by_sas_rphy(h, rphy); | |
9808 | if (!sd) | |
9809 | return -ENXIO; | |
9810 | ||
9811 | *identifier = sd->eli; | |
9812 | ||
d04e62b9 KB |
9813 | return 0; |
9814 | } | |
9815 | ||
9816 | static int | |
9817 | hpsa_sas_get_bay_identifier(struct sas_rphy *rphy) | |
9818 | { | |
9819 | return -ENXIO; | |
9820 | } | |
9821 | ||
9822 | static int | |
9823 | hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset) | |
9824 | { | |
9825 | return 0; | |
9826 | } | |
9827 | ||
9828 | static int | |
9829 | hpsa_sas_phy_enable(struct sas_phy *phy, int enable) | |
9830 | { | |
9831 | return 0; | |
9832 | } | |
9833 | ||
9834 | static int | |
9835 | hpsa_sas_phy_setup(struct sas_phy *phy) | |
9836 | { | |
9837 | return 0; | |
9838 | } | |
9839 | ||
9840 | static void | |
9841 | hpsa_sas_phy_release(struct sas_phy *phy) | |
9842 | { | |
9843 | } | |
9844 | ||
9845 | static int | |
9846 | hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates) | |
9847 | { | |
9848 | return -EINVAL; | |
9849 | } | |
9850 | ||
d04e62b9 KB |
9851 | static struct sas_function_template hpsa_sas_transport_functions = { |
9852 | .get_linkerrors = hpsa_sas_get_linkerrors, | |
9853 | .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier, | |
9854 | .get_bay_identifier = hpsa_sas_get_bay_identifier, | |
9855 | .phy_reset = hpsa_sas_phy_reset, | |
9856 | .phy_enable = hpsa_sas_phy_enable, | |
9857 | .phy_setup = hpsa_sas_phy_setup, | |
9858 | .phy_release = hpsa_sas_phy_release, | |
9859 | .set_phy_speed = hpsa_sas_phy_speed, | |
d04e62b9 KB |
9860 | }; |
9861 | ||
edd16368 SC |
9862 | /* |
9863 | * This is it. Register the PCI driver information for the cards we control | |
9864 | * the OS will call our registered routines when it finds one of our cards. | |
9865 | */ | |
9866 | static int __init hpsa_init(void) | |
9867 | { | |
d04e62b9 KB |
9868 | int rc; |
9869 | ||
9870 | hpsa_sas_transport_template = | |
9871 | sas_attach_transport(&hpsa_sas_transport_functions); | |
9872 | if (!hpsa_sas_transport_template) | |
9873 | return -ENODEV; | |
9874 | ||
9875 | rc = pci_register_driver(&hpsa_pci_driver); | |
9876 | ||
9877 | if (rc) | |
9878 | sas_release_transport(hpsa_sas_transport_template); | |
9879 | ||
9880 | return rc; | |
edd16368 SC |
9881 | } |
9882 | ||
9883 | static void __exit hpsa_cleanup(void) | |
9884 | { | |
9885 | pci_unregister_driver(&hpsa_pci_driver); | |
d04e62b9 | 9886 | sas_release_transport(hpsa_sas_transport_template); |
edd16368 SC |
9887 | } |
9888 | ||
e1f7de0c MG |
9889 | static void __attribute__((unused)) verify_offsets(void) |
9890 | { | |
dd0e19f3 ST |
9891 | #define VERIFY_OFFSET(member, offset) \ |
9892 | BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) | |
9893 | ||
9894 | VERIFY_OFFSET(structure_size, 0); | |
9895 | VERIFY_OFFSET(volume_blk_size, 4); | |
9896 | VERIFY_OFFSET(volume_blk_cnt, 8); | |
9897 | VERIFY_OFFSET(phys_blk_shift, 16); | |
9898 | VERIFY_OFFSET(parity_rotation_shift, 17); | |
9899 | VERIFY_OFFSET(strip_size, 18); | |
9900 | VERIFY_OFFSET(disk_starting_blk, 20); | |
9901 | VERIFY_OFFSET(disk_blk_cnt, 28); | |
9902 | VERIFY_OFFSET(data_disks_per_row, 36); | |
9903 | VERIFY_OFFSET(metadata_disks_per_row, 38); | |
9904 | VERIFY_OFFSET(row_cnt, 40); | |
9905 | VERIFY_OFFSET(layout_map_count, 42); | |
9906 | VERIFY_OFFSET(flags, 44); | |
9907 | VERIFY_OFFSET(dekindex, 46); | |
9908 | /* VERIFY_OFFSET(reserved, 48 */ | |
9909 | VERIFY_OFFSET(data, 64); | |
9910 | ||
9911 | #undef VERIFY_OFFSET | |
9912 | ||
b66cc250 MM |
9913 | #define VERIFY_OFFSET(member, offset) \ |
9914 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) | |
9915 | ||
9916 | VERIFY_OFFSET(IU_type, 0); | |
9917 | VERIFY_OFFSET(direction, 1); | |
9918 | VERIFY_OFFSET(reply_queue, 2); | |
9919 | /* VERIFY_OFFSET(reserved1, 3); */ | |
9920 | VERIFY_OFFSET(scsi_nexus, 4); | |
9921 | VERIFY_OFFSET(Tag, 8); | |
9922 | VERIFY_OFFSET(cdb, 16); | |
9923 | VERIFY_OFFSET(cciss_lun, 32); | |
9924 | VERIFY_OFFSET(data_len, 40); | |
9925 | VERIFY_OFFSET(cmd_priority_task_attr, 44); | |
9926 | VERIFY_OFFSET(sg_count, 45); | |
9927 | /* VERIFY_OFFSET(reserved3 */ | |
9928 | VERIFY_OFFSET(err_ptr, 48); | |
9929 | VERIFY_OFFSET(err_len, 56); | |
9930 | /* VERIFY_OFFSET(reserved4 */ | |
9931 | VERIFY_OFFSET(sg, 64); | |
9932 | ||
9933 | #undef VERIFY_OFFSET | |
9934 | ||
e1f7de0c MG |
9935 | #define VERIFY_OFFSET(member, offset) \ |
9936 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
9937 | ||
9938 | VERIFY_OFFSET(dev_handle, 0x00); | |
9939 | VERIFY_OFFSET(reserved1, 0x02); | |
9940 | VERIFY_OFFSET(function, 0x03); | |
9941 | VERIFY_OFFSET(reserved2, 0x04); | |
9942 | VERIFY_OFFSET(err_info, 0x0C); | |
9943 | VERIFY_OFFSET(reserved3, 0x10); | |
9944 | VERIFY_OFFSET(err_info_len, 0x12); | |
9945 | VERIFY_OFFSET(reserved4, 0x13); | |
9946 | VERIFY_OFFSET(sgl_offset, 0x14); | |
9947 | VERIFY_OFFSET(reserved5, 0x15); | |
9948 | VERIFY_OFFSET(transfer_len, 0x1C); | |
9949 | VERIFY_OFFSET(reserved6, 0x20); | |
9950 | VERIFY_OFFSET(io_flags, 0x24); | |
9951 | VERIFY_OFFSET(reserved7, 0x26); | |
9952 | VERIFY_OFFSET(LUN, 0x34); | |
9953 | VERIFY_OFFSET(control, 0x3C); | |
9954 | VERIFY_OFFSET(CDB, 0x40); | |
9955 | VERIFY_OFFSET(reserved8, 0x50); | |
9956 | VERIFY_OFFSET(host_context_flags, 0x60); | |
9957 | VERIFY_OFFSET(timeout_sec, 0x62); | |
9958 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
9959 | VERIFY_OFFSET(reserved9, 0x65); | |
50a0decf | 9960 | VERIFY_OFFSET(tag, 0x68); |
e1f7de0c MG |
9961 | VERIFY_OFFSET(host_addr, 0x70); |
9962 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
9963 | VERIFY_OFFSET(SG, 0x78 + 8); | |
9964 | #undef VERIFY_OFFSET | |
9965 | } | |
9966 | ||
edd16368 SC |
9967 | module_init(hpsa_init); |
9968 | module_exit(hpsa_cleanup); |