[mirror_ubuntu-focal-kernel.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
	unsigned char volume_offline;	/* discovered via TUR or VPD */
	u16 queue_depth;		/* max queue_depth for this device */
	atomic_t ioaccel_cmds_out;	/* Only used for physical devices
					 * counts commands sent to physical
					 * device via "ioaccel" path.
					 */
	u32 ioaccel_handle;
	int offload_config;		/* I/O accel RAID offload configured */
	int offload_enabled;		/* I/O accel RAID offload enabled */
	int offload_to_be_enabled;
	int offload_to_mirror;		/* Send next I/O accelerator RAID
					 * offload request to mirror drive
					 */
	struct raid_map_data raid_map;	/* I/O accelerator RAID map */

	/*
	 * Pointers from logical drive map indices to the phys drives that
	 * make those logical drives.  Note, multiple logical drives may
	 * share physical drives.  You can have for instance 5 physical
	 * drives with 3 logical drives each using those same 5 physical
	 * disks. We need these pointers for counting i/o's out to physical
	 * devices in order to honor physical device queue depth limits.
	 */
	struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
#define HPSA_DO_NOT_EXPOSE	0x0
#define HPSA_SG_ATTACH		0x1
#define HPSA_ULD_ATTACH		0x2
#define HPSA_SCSI_ADD		(HPSA_SG_ATTACH | HPSA_ULD_ATTACH)
	u8 expose_state;
};

struct reply_queue_buffer {
	u64 *head;
	size_t size;
	u8 wraparound;
	u32 current_entry;
	dma_addr_t busaddr;
};

#pragma pack(1)
struct bmic_controller_parameters {
	u8   led_flags;
	u8   enable_command_list_verification;
	u8   backed_out_write_drives;
	u16  stripes_for_parity;
	u8   parity_distribution_mode_flags;
	u16  max_driver_requests;
	u16  elevator_trend_count;
	u8   disable_elevator;
	u8   force_scan_complete;
	u8   scsi_transfer_mode;
	u8   force_narrow;
	u8   rebuild_priority;
	u8   expand_priority;
	u8   host_sdb_asic_fix;
	u8   pdpi_burst_from_host_disabled;
	char software_name[64];
	char hardware_name[32];
	u8   bridge_revision;
	u8   snapshot_priority;
	u32  os_specific;
	u8   post_prompt_timeout;
	u8   automatic_drive_slamming;
	u8   reserved1;
	u8   nvram_flags;
#define HBA_MODE_ENABLED_FLAG (1 << 3)
	u8   cache_nvram_flags;
	u8   drive_config_flags;
	u16  reserved2;
	u8   temp_warning_level;
	u8   temp_shutdown_level;
	u8   temp_condition_reset;
	u8   max_coalesce_commands;
	u32  max_coalesce_delay;
	u8   orca_password[4];
	u8   access_id[16];
	u8   reserved[356];
};
#pragma pack()

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int 	max_commands;
	int last_allocation;
	atomic_t commands_outstanding;
#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[MAX_REPLY_QUEUES];
	unsigned int msix_vector;
	unsigned int msi_vector;
	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
	struct access_method access;
	char hba_mode_enabled;

	/* queue and queue Info */
	unsigned int Qdepth;
	unsigned int maxSG;
	spinlock_t lock;
	int maxsgentries;
	u8 max_cmd_sg_entries;
	int chainsize;
	struct SGDescriptor **cmd_sg_list;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct io_accel1_cmd	*ioaccel_cmd_pool;
	dma_addr_t		ioaccel_cmd_pool_dhandle;
	struct io_accel2_cmd	*ioaccel2_cmd_pool;
	dma_addr_t		ioaccel2_cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			scan_finished;
	spinlock_t		scan_lock;
	wait_queue_head_t	scan_wait_queue;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct __iomem *transtable;
	unsigned long transMethod;

	/* cap concurrent passthrus at some reasonable maximum */
#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
	atomic_t passthru_cmds_avail;

	/*
	 * Performant mode completion buffers
	 */
	size_t reply_queue_size;
	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
	u8 nreply_queues;
	u32 *blockFetchTable;
	u32 *ioaccel1_blockFetchTable;
	u32 *ioaccel2_blockFetchTable;
	u32 __iomem *ioaccel2_bft2_regs;
	unsigned char *hba_inquiry_data;
	u32 driver_support;
	u32 fw_support;
	int ioaccel_support;
	int ioaccel_maxsg;
	u64 last_intr_timestamp;
	u32 last_heartbeat;
	u64 last_heartbeat_timestamp;
	u32 heartbeat_sample_interval;
	atomic_t firmware_flash_in_progress;
	u32 __percpu *lockup_detected;
	struct delayed_work monitor_ctlr_work;
	struct delayed_work rescan_ctlr_work;
	int remove_in_progress;
	/* Address of h->q[x] is passed to intr handler to know which queue */
	u8 q[MAX_REPLY_QUEUES];
	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
#define HPSATMF_BITS_SUPPORTED  (1 << 0)
#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
#define HPSATMF_MASK_SUPPORTED  (1 << 16)
#define HPSATMF_LOG_LUN_RESET   (1 << 17)
#define HPSATMF_LOG_NEX_RESET   (1 << 18)
#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
#define HPSATMF_LOG_QRY_TASK    (1 << 23)
#define HPSATMF_LOG_QRY_TSET    (1 << 24)
#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
	u32 events;
#define CTLR_STATE_CHANGE_EVENT				(1 << 0)
#define CTLR_ENCLOSURE_HOT_PLUG_EVENT			(1 << 1)
#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV		(1 << 4)
#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV		(1 << 5)
#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL		(1 << 6)
#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED	(1 << 30)
#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE	(1 << 31)

#define RESCAN_REQUIRED_EVENT_BITS \
		(CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
		CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
		CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
	spinlock_t offline_device_lock;
	struct list_head offline_device_list;
	int	acciopath_status;
	int	raid_offload_debug;
	struct workqueue_struct *resubmit_wq;
	struct workqueue_struct *rescan_ctlr_wq;
};

struct offline_device_entry {
	unsigned char scsi3addr[8];
	struct list_head offline_list;
};

#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_RESET_TYPE_CONTROLLER 0x00
#define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_BOARD_NOT_READY_ITERATIONS \
	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
#define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

/* Performant mode flags */
#define SA5_PERF_INTR_PENDING   0x04
#define SA5_PERF_INTR_OFF       0x05
#define SA5_OUTDB_STATUS_PERF_BIT       0x01
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0

/*
 * Inbound Post Queue offsets for IO Accelerator Mode 2
 */
#define IOACCEL2_INBOUND_POSTQ_32	0x48
#define IOACCEL2_INBOUND_POSTQ_64_LOW	0xd0
#define IOACCEL2_INBOUND_POSTQ_64_HI	0xd4

/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

static void SA5_submit_command_no_read(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
{
	struct reply_queue_buffer *rq = &h->reply_queue[q];
	unsigned long register_value = FIFO_EMPTY;

	/* msi auto clears the interrupt pending bit. */
	if (unlikely(!(h->msi_vector || h->msix_vector))) {
		/* flush the controller write of the reply queue by reading
		 * outbound doorbell status register.
		 */
		(void) readl(h->vaddr + SA5_OUTDB_STATUS);
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		(void) readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
		register_value = rq->head[rq->current_entry];
		rq->current_entry++;
		atomic_dec(&h->commands_outstanding);
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (rq->current_entry == h->max_commands) {
		rq->current_entry = 0;
		rq->wraparound ^= 1;
	}
	return register_value;
}

/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h,
	__attribute__((unused)) u8 q)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);

	if (register_value != FIFO_EMPTY)
		atomic_dec(&h->commands_outstanding);

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	return register_value & SA5_INTR_PENDING;
}

static bool SA5_performant_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT    0x100

static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
		true : false;
}

#define IOACCEL_MODE1_REPLY_QUEUE_INDEX  0x1A0
#define IOACCEL_MODE1_PRODUCER_INDEX     0x1B8
#define IOACCEL_MODE1_CONSUMER_INDEX     0x1BC
#define IOACCEL_MODE1_REPLY_UNUSED       0xFFFFFFFFFFFFFFFFULL

static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
{
	u64 register_value;
	struct reply_queue_buffer *rq = &h->reply_queue[q];

	BUG_ON(q >= h->nreply_queues);

	register_value = rq->head[rq->current_entry];
	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
		rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
		if (++rq->current_entry == rq->size)
			rq->current_entry = 0;
		/*
		 * @todo
		 *
		 * Don't really need to write the new index after each command,
		 * but with current driver design this is easiest.
		 */
		wmb();
		writel((q << 24) | rq->current_entry, h->vaddr +
				IOACCEL_MODE1_CONSUMER_INDEX);
		atomic_dec(&h->commands_outstanding);
	}
	return (unsigned long) register_value;
}

static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_intr_pending,
	SA5_completed,
};

static struct access_method SA5_ioaccel_mode1_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_ioaccel_mode1_intr_pending,
	SA5_ioaccel_mode1_completed,
};

static struct access_method SA5_ioaccel_mode2_access = {
	SA5_submit_command_ioaccel2,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access_no_read = {
	SA5_submit_command_no_read,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
edd16368 SC	2	* Disk Array driver for HP Smart Array SAS controllers
51c35139	3	* Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368 SC	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
900c5440	35	bool (intr_pending)(struct ctlr_info h);
254f796b	36	unsigned long (command_completed)(struct ctlr_info h, u8 q);
edd16368 SC	37	};
	38
	39	struct hpsa_scsi_dev_t {
	40	int devtype;
	41	int bus, target, lun; /* as presented to the OS */
	42	unsigned char scsi3addr[8]; /* as presented to the HW */
	43	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	44	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	45	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	46	unsigned char model[16]; /* bytes 16-31 of inquiry data */
edd16368	47	unsigned char raid_level; /* from inquiry page 0xC1 */
9846590e	48	unsigned char volume_offline; /* discovered via TUR or VPD */
03383736 DB	49	u16 queue_depth; /* max queue_depth for this device */
	50	atomic_t ioaccel_cmds_out; /* Only used for physical devices
	51	* counts commands sent to physical
	52	* device via "ioaccel" path.
	53	*/
e1f7de0c	54	u32 ioaccel_handle;
283b4a9b SC	55	int offload_config; /* I/O accel RAID offload configured */
283b4a9b SC	56	int offload_enabled; /* I/O accel RAID offload enabled */
41ce4c35	57	int offload_to_be_enabled;
283b4a9b SC	58	int offload_to_mirror; /* Send next I/O accelerator RAID
	59	* offload request to mirror drive
	60	*/
	61	struct raid_map_data raid_map; /* I/O accelerator RAID map */
	62
03383736 DB	63	/*
	64	* Pointers from logical drive map indices to the phys drives that
	65	* make those logical drives. Note, multiple logical drives may
	66	* share physical drives. You can have for instance 5 physical
	67	* drives with 3 logical drives each using those same 5 physical
	68	* disks. We need these pointers for counting i/o's out to physical
	69	* devices in order to honor physical device queue depth limits.
	70	*/
	71	struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES];
41ce4c35 SC	72	#define HPSA_DO_NOT_EXPOSE 0x0
	73	#define HPSA_SG_ATTACH 0x1
	74	#define HPSA_ULD_ATTACH 0x2
	75	#define HPSA_SCSI_ADD (HPSA_SG_ATTACH \| HPSA_ULD_ATTACH)
	76	u8 expose_state;
edd16368 SC	77	};
edd16368 SC	78
072b0518	79	struct reply_queue_buffer {
254f796b MG	80	u64 *head;
	81	size_t size;
	82	u8 wraparound;
	83	u32 current_entry;
072b0518	84	dma_addr_t busaddr;
254f796b MG	85	};
254f796b MG	86
316b221a SC	87	#pragma pack(1)
	88	struct bmic_controller_parameters {
	89	u8 led_flags;
	90	u8 enable_command_list_verification;
	91	u8 backed_out_write_drives;
	92	u16 stripes_for_parity;
	93	u8 parity_distribution_mode_flags;
	94	u16 max_driver_requests;
	95	u16 elevator_trend_count;
	96	u8 disable_elevator;
	97	u8 force_scan_complete;
	98	u8 scsi_transfer_mode;
	99	u8 force_narrow;
	100	u8 rebuild_priority;
	101	u8 expand_priority;
	102	u8 host_sdb_asic_fix;
	103	u8 pdpi_burst_from_host_disabled;
	104	char software_name[64];
	105	char hardware_name[32];
	106	u8 bridge_revision;
	107	u8 snapshot_priority;
	108	u32 os_specific;
	109	u8 post_prompt_timeout;
	110	u8 automatic_drive_slamming;
	111	u8 reserved1;
	112	u8 nvram_flags;
6e8e8088	113	#define HBA_MODE_ENABLED_FLAG (1 << 3)
316b221a SC	114	u8 cache_nvram_flags;
	115	u8 drive_config_flags;
	116	u16 reserved2;
	117	u8 temp_warning_level;
	118	u8 temp_shutdown_level;
	119	u8 temp_condition_reset;
	120	u8 max_coalesce_commands;
	121	u32 max_coalesce_delay;
	122	u8 orca_password[4];
	123	u8 access_id[16];
	124	u8 reserved[356];
	125	};
	126	#pragma pack()
	127
edd16368 SC	128	struct ctlr_info {
	129	int ctlr;
	130	char devname[8];
	131	char *product_name;
edd16368	132	struct pci_dev *pdev;
01a02ffc	133	u32 board_id;
edd16368 SC	134	void __iomem *vaddr;
	135	unsigned long paddr;
	136	int nr_cmds; /* Number of commands allowed on this controller */
d54c5c24 SC	137	#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
d54c5c24 SC	138	#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
edd16368 SC	139	struct CfgTable __iomem *cfgtable;
edd16368 SC	140	int interrupts_enabled;
edd16368	141	int max_commands;
33811026	142	int last_allocation;
0cbf768e	143	atomic_t commands_outstanding;
303932fd DB	144	# define PERF_MODE_INT 0
303932fd DB	145	# define DOORBELL_INT 1
edd16368 SC	146	# define SIMPLE_MODE_INT 2
edd16368 SC	147	# define MEMQ_MODE_INT 3
254f796b	148	unsigned int intr[MAX_REPLY_QUEUES];
edd16368 SC	149	unsigned int msix_vector;
edd16368 SC	150	unsigned int msi_vector;
a9a3a273	151	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
edd16368	152	struct access_method access;
316b221a	153	char hba_mode_enabled;
edd16368 SC	154
edd16368 SC	155	/* queue and queue Info */
edd16368	156	unsigned int Qdepth;
edd16368 SC	157	unsigned int maxSG;
edd16368 SC	158	spinlock_t lock;
33a2ffce SC	159	int maxsgentries;
	160	u8 max_cmd_sg_entries;
	161	int chainsize;
	162	struct SGDescriptor **cmd_sg_list;
edd16368 SC	163
	164	/* pointers to command and error info pool */
	165	struct CommandList *cmd_pool;
	166	dma_addr_t cmd_pool_dhandle;
e1f7de0c MG	167	struct io_accel1_cmd *ioaccel_cmd_pool;
e1f7de0c MG	168	dma_addr_t ioaccel_cmd_pool_dhandle;
aca9012a SC	169	struct io_accel2_cmd *ioaccel2_cmd_pool;
aca9012a SC	170	dma_addr_t ioaccel2_cmd_pool_dhandle;
edd16368 SC	171	struct ErrorInfo *errinfo_pool;
	172	dma_addr_t errinfo_pool_dhandle;
	173	unsigned long *cmd_pool_bits;
a08a8471 SC	174	int scan_finished;
	175	spinlock_t scan_lock;
	176	wait_queue_head_t scan_wait_queue;
edd16368 SC	177
	178	struct Scsi_Host *scsi_host;
	179	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	180	int ndevices; /* number of used elements in .dev[] array. */
cfe5badc	181	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
303932fd DB	182	/*
	183	* Performant mode tables.
	184	*/
	185	u32 trans_support;
	186	u32 trans_offset;
42a91641	187	struct TransTable_struct __iomem *transtable;
303932fd DB	188	unsigned long transMethod;
303932fd DB	189
0390f0c0	190	/* cap concurrent passthrus at some reasonable maximum */
45fcb86e	191	#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
34f0c627	192	atomic_t passthru_cmds_avail;
0390f0c0	193
303932fd	194	/*
254f796b	195	* Performant mode completion buffers
303932fd	196	*/
072b0518 SC	197	size_t reply_queue_size;
072b0518 SC	198	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
254f796b	199	u8 nreply_queues;
303932fd	200	u32 *blockFetchTable;
e1f7de0c	201	u32 *ioaccel1_blockFetchTable;
aca9012a	202	u32 *ioaccel2_blockFetchTable;
42a91641	203	u32 __iomem *ioaccel2_bft2_regs;
339b2b14	204	unsigned char *hba_inquiry_data;
283b4a9b SC	205	u32 driver_support;
	206	u32 fw_support;
	207	int ioaccel_support;
	208	int ioaccel_maxsg;
a0c12413 SC	209	u64 last_intr_timestamp;
	210	u32 last_heartbeat;
	211	u64 last_heartbeat_timestamp;
e85c5974 SC	212	u32 heartbeat_sample_interval;
e85c5974 SC	213	atomic_t firmware_flash_in_progress;
42a91641	214	u32 __percpu *lockup_detected;
8a98db73	215	struct delayed_work monitor_ctlr_work;
6636e7f4	216	struct delayed_work rescan_ctlr_work;
8a98db73	217	int remove_in_progress;
254f796b MG	218	/* Address of h->q[x] is passed to intr handler to know which queue */
254f796b MG	219	u8 q[MAX_REPLY_QUEUES];
75167d2c SC	220	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
	221	#define HPSATMF_BITS_SUPPORTED (1 << 0)
	222	#define HPSATMF_PHYS_LUN_RESET (1 << 1)
	223	#define HPSATMF_PHYS_NEX_RESET (1 << 2)
	224	#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
	225	#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
	226	#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
	227	#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
	228	#define HPSATMF_PHYS_QRY_TASK (1 << 7)
	229	#define HPSATMF_PHYS_QRY_TSET (1 << 8)
	230	#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
	231	#define HPSATMF_MASK_SUPPORTED (1 << 16)
	232	#define HPSATMF_LOG_LUN_RESET (1 << 17)
	233	#define HPSATMF_LOG_NEX_RESET (1 << 18)
	234	#define HPSATMF_LOG_TASK_ABORT (1 << 19)
	235	#define HPSATMF_LOG_TSET_ABORT (1 << 20)
	236	#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
	237	#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
	238	#define HPSATMF_LOG_QRY_TASK (1 << 23)
	239	#define HPSATMF_LOG_QRY_TSET (1 << 24)
	240	#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
76438d08	241	u32 events;
faff6ee0 SC	242	#define CTLR_STATE_CHANGE_EVENT (1 << 0)
	243	#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
	244	#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
	245	#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
	246	#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
	247	#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
	248	#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
	249
	250	#define RESCAN_REQUIRED_EVENT_BITS \
7b2c46ee	251	(CTLR_ENCLOSURE_HOT_PLUG_EVENT \| \
faff6ee0 SC	252	CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV \| \
faff6ee0 SC	253	CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV \| \
faff6ee0 SC	254	CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED \| \
faff6ee0 SC	255	CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
9846590e SC	256	spinlock_t offline_device_lock;
9846590e SC	257	struct list_head offline_device_list;
da0697bd	258	int acciopath_status;
2ba8bfc8	259	int raid_offload_debug;
080ef1cc	260	struct workqueue_struct *resubmit_wq;
6636e7f4	261	struct workqueue_struct *rescan_ctlr_wq;
edd16368	262	};
9846590e SC	263
	264	struct offline_device_entry {
	265	unsigned char scsi3addr[8];
	266	struct list_head offline_list;
	267	};
	268
edd16368 SC	269	#define HPSA_ABORT_MSG 0
edd16368 SC	270	#define HPSA_DEVICE_RESET_MSG 1
64670ac8 SC	271	#define HPSA_RESET_TYPE_CONTROLLER 0x00
	272	#define HPSA_RESET_TYPE_BUS 0x01
	273	#define HPSA_RESET_TYPE_TARGET 0x03
	274	#define HPSA_RESET_TYPE_LUN 0x04
edd16368	275	#define HPSA_MSG_SEND_RETRY_LIMIT 10
516fda49	276	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
edd16368 SC	277
	278	/* Maximum time in seconds driver will wait for command completions
	279	* when polling before giving up.
	280	*/
	281	#define HPSA_MAX_POLL_TIME_SECS (20)
	282
	283	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	284	* how many times to retry TEST UNIT READY on a device
	285	* while waiting for it to become ready before giving up.
	286	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	287	* between sending TURs while waiting for a device
	288	* to become ready.
	289	*/
	290	#define HPSA_TUR_RETRY_LIMIT (20)
	291	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
	292
	293	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
	294	* to become ready, in seconds, before giving up on it.
	295	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	296	* between polling the board to see if it is ready, in
	297	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
	298	* HPSA_BOARD_READY_ITERATIONS are derived from those.
	299	*/
	300	#define HPSA_BOARD_READY_WAIT_SECS (120)
2ed7127b	301	#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
edd16368 SC	302	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
	303	#define HPSA_BOARD_READY_POLL_INTERVAL \
	304	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
	305	#define HPSA_BOARD_READY_ITERATIONS \
	306	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
	307	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
fe5389c8 SC	308	#define HPSA_BOARD_NOT_READY_ITERATIONS \
	309	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	310	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
edd16368 SC	311	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
	312	#define HPSA_POST_RESET_NOOP_RETRIES (12)
	313
	314	/* Defining the diffent access_menthods */
	315	/*
	316	* Memory mapped FIFO interface (SMART 53xx cards)
	317	*/
	318	#define SA5_DOORBELL 0x20
	319	#define SA5_REQUEST_PORT_OFFSET 0x40
281a7fd0 WS	320	#define SA5_REQUEST_PORT64_LO_OFFSET 0xC0
281a7fd0 WS	321	#define SA5_REQUEST_PORT64_HI_OFFSET 0xC4
edd16368 SC	322	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	323	#define SA5_REPLY_PORT_OFFSET 0x44
	324	#define SA5_INTR_STATUS 0x30
	325	#define SA5_SCRATCHPAD_OFFSET 0xB0
	326
	327	#define SA5_CTCFG_OFFSET 0xB4
	328	#define SA5_CTMEM_OFFSET 0xB8
	329
	330	#define SA5_INTR_OFF 0x08
	331	#define SA5B_INTR_OFF 0x04
	332	#define SA5_INTR_PENDING 0x08
	333	#define SA5B_INTR_PENDING 0x04
	334	#define FIFO_EMPTY 0xffffffff
	335	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
	336
	337	#define HPSA_ERROR_BIT 0x02
edd16368	338
303932fd DB	339	/* Performant mode flags */
	340	#define SA5_PERF_INTR_PENDING 0x04
	341	#define SA5_PERF_INTR_OFF 0x05
	342	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	343	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	344	#define SA5_OUTDB_CLEAR 0xA0
	345	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	346	#define SA5_OUTDB_STATUS 0x9C
	347
	348
edd16368 SC	349	#define HPSA_INTR_ON 1
edd16368 SC	350	#define HPSA_INTR_OFF 0
b66cc250 MM	351
	352	/*
	353	* Inbound Post Queue offsets for IO Accelerator Mode 2
	354	*/
	355	#define IOACCEL2_INBOUND_POSTQ_32 0x48
	356	#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
	357	#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
	358
edd16368 SC	359	/*
	360	Send the command to the hardware
	361	*/
	362	static void SA5_submit_command(struct ctlr_info *h,
	363	struct CommandList *c)
	364	{
edd16368	365	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
fec62c36	366	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
edd16368 SC	367	}
edd16368 SC	368
b3a52e79 SC	369	static void SA5_submit_command_no_read(struct ctlr_info *h,
	370	struct CommandList *c)
	371	{
	372	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	373	}
	374
c349775e ST	375	static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	376	struct CommandList *c)
	377	{
c05e8866	378	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e ST	379	}
c349775e ST	380
edd16368 SC	381	/*
	382	* This card is the opposite of the other cards.
	383	* 0 turns interrupts on...
	384	* 0x08 turns them off...
	385	*/
	386	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	387	{
	388	if (val) { /* Turn interrupts on */
	389	h->interrupts_enabled = 1;
	390	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	391	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	392	} else { /* Turn them off */
	393	h->interrupts_enabled = 0;
	394	writel(SA5_INTR_OFF,
	395	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	396	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	397	}
edd16368 SC	398	}
303932fd DB	399
	400	static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
	401	{
	402	if (val) { /* turn on interrupts */
	403	h->interrupts_enabled = 1;
	404	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	405	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	406	} else {
	407	h->interrupts_enabled = 0;
	408	writel(SA5_PERF_INTR_OFF,
	409	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	410	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	411	}
	412	}
	413
254f796b	414	static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
303932fd	415	{
072b0518	416	struct reply_queue_buffer *rq = &h->reply_queue[q];
0cbf768e	417	unsigned long register_value = FIFO_EMPTY;
303932fd	418
303932fd	419	/* msi auto clears the interrupt pending bit. */
bee266a6	420	if (unlikely(!(h->msi_vector \|\| h->msix_vector))) {
2c17d2da SC	421	/* flush the controller write of the reply queue by reading
	422	* outbound doorbell status register.
	423	*/
bee266a6	424	(void) readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	425	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	426	/* Do a read in order to flush the write to the controller
	427	* (as per spec.)
	428	*/
bee266a6	429	(void) readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	430	}
303932fd DB	431
bee266a6	432	if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) {
254f796b MG	433	register_value = rq->head[rq->current_entry];
254f796b MG	434	rq->current_entry++;
0cbf768e	435	atomic_dec(&h->commands_outstanding);
303932fd DB	436	} else {
	437	register_value = FIFO_EMPTY;
	438	}
	439	/* Check for wraparound */
254f796b MG	440	if (rq->current_entry == h->max_commands) {
	441	rq->current_entry = 0;
	442	rq->wraparound ^= 1;
303932fd	443	}
303932fd DB	444	return register_value;
	445	}
	446
edd16368 SC	447	/*
	448	* returns value read from hardware.
	449	* returns FIFO_EMPTY if there is nothing to read
	450	*/
254f796b MG	451	static unsigned long SA5_completed(struct ctlr_info *h,
254f796b MG	452	__attribute__((unused)) u8 q)
edd16368 SC	453	{
	454	unsigned long register_value
	455	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	456
0cbf768e SC	457	if (register_value != FIFO_EMPTY)
0cbf768e SC	458	atomic_dec(&h->commands_outstanding);
edd16368 SC	459
	460	#ifdef HPSA_DEBUG
	461	if (register_value != FIFO_EMPTY)
84ca0be2	462	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	463	register_value);
edd16368 SC	464	else
f79cfec6	465	dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
edd16368 SC	466	#endif
	467
	468	return register_value;
	469	}
	470	/*
	471	* Returns true if an interrupt is pending..
	472	*/
900c5440	473	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	474	{
	475	unsigned long register_value =
	476	readl(h->vaddr + SA5_INTR_STATUS);
900c5440	477	return register_value & SA5_INTR_PENDING;
edd16368 SC	478	}
edd16368 SC	479
303932fd DB	480	static bool SA5_performant_intr_pending(struct ctlr_info *h)
	481	{
	482	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	483
	484	if (!register_value)
	485	return false;
	486
303932fd DB	487	/* Read outbound doorbell to flush */
	488	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	489	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	490	}
edd16368	491
e1f7de0c MG	492	#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
	493
	494	static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
	495	{
	496	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	497
	498	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
	499	true : false;
	500	}
	501
	502	#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
	503	#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
	504	#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
	505	#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
	506
283b4a9b	507	static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
e1f7de0c MG	508	{
e1f7de0c MG	509	u64 register_value;
072b0518	510	struct reply_queue_buffer *rq = &h->reply_queue[q];
e1f7de0c MG	511
	512	BUG_ON(q >= h->nreply_queues);
	513
	514	register_value = rq->head[rq->current_entry];
	515	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
	516	rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
	517	if (++rq->current_entry == rq->size)
	518	rq->current_entry = 0;
283b4a9b SC	519	/*
	520	* @todo
	521	*
	522	* Don't really need to write the new index after each command,
	523	* but with current driver design this is easiest.
	524	*/
	525	wmb();
	526	writel((q << 24) \| rq->current_entry, h->vaddr +
	527	IOACCEL_MODE1_CONSUMER_INDEX);
0cbf768e	528	atomic_dec(&h->commands_outstanding);
e1f7de0c MG	529	}
	530	return (unsigned long) register_value;
	531	}
	532
edd16368 SC	533	static struct access_method SA5_access = {
	534	SA5_submit_command,
	535	SA5_intr_mask,
edd16368 SC	536	SA5_intr_pending,
	537	SA5_completed,
	538	};
	539
e1f7de0c MG	540	static struct access_method SA5_ioaccel_mode1_access = {
	541	SA5_submit_command,
	542	SA5_performant_intr_mask,
e1f7de0c MG	543	SA5_ioaccel_mode1_intr_pending,
	544	SA5_ioaccel_mode1_completed,
	545	};
	546
c349775e ST	547	static struct access_method SA5_ioaccel_mode2_access = {
	548	SA5_submit_command_ioaccel2,
	549	SA5_performant_intr_mask,
c349775e ST	550	SA5_performant_intr_pending,
	551	SA5_performant_completed,
	552	};
	553
303932fd DB	554	static struct access_method SA5_performant_access = {
	555	SA5_submit_command,
	556	SA5_performant_intr_mask,
303932fd DB	557	SA5_performant_intr_pending,
	558	SA5_performant_completed,
	559	};
	560
b3a52e79 SC	561	static struct access_method SA5_performant_access_no_read = {
	562	SA5_submit_command_no_read,
	563	SA5_performant_intr_mask,
b3a52e79 SC	564	SA5_performant_intr_pending,
	565	SA5_performant_completed,
	566	};
	567
edd16368	568	struct board_type {
01a02ffc	569	u32 board_id;
edd16368 SC	570	char *product_name;
	571	struct access_method *access;
	572	};
	573
edd16368 SC	574	#endif /* HPSA_H */
edd16368 SC	575