[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
	unsigned char volume_offline;	/* discovered via TUR or VPD */
	u32 ioaccel_handle;
	int offload_config;		/* I/O accel RAID offload configured */
	int offload_enabled;		/* I/O accel RAID offload enabled */
	int offload_to_mirror;		/* Send next I/O accelerator RAID
					 * offload request to mirror drive
					 */
	struct raid_map_data raid_map;	/* I/O accelerator RAID map */

};

struct reply_queue_buffer {
	u64 *head;
	size_t size;
	u8 wraparound;
	u32 current_entry;
	dma_addr_t busaddr;
};

#pragma pack(1)
struct bmic_controller_parameters {
	u8   led_flags;
	u8   enable_command_list_verification;
	u8   backed_out_write_drives;
	u16  stripes_for_parity;
	u8   parity_distribution_mode_flags;
	u16  max_driver_requests;
	u16  elevator_trend_count;
	u8   disable_elevator;
	u8   force_scan_complete;
	u8   scsi_transfer_mode;
	u8   force_narrow;
	u8   rebuild_priority;
	u8   expand_priority;
	u8   host_sdb_asic_fix;
	u8   pdpi_burst_from_host_disabled;
	char software_name[64];
	char hardware_name[32];
	u8   bridge_revision;
	u8   snapshot_priority;
	u32  os_specific;
	u8   post_prompt_timeout;
	u8   automatic_drive_slamming;
	u8   reserved1;
	u8   nvram_flags;
#define HBA_MODE_ENABLED_FLAG (1 << 3)
	u8   cache_nvram_flags;
	u8   drive_config_flags;
	u16  reserved2;
	u8   temp_warning_level;
	u8   temp_shutdown_level;
	u8   temp_condition_reset;
	u8   max_coalesce_commands;
	u32  max_coalesce_delay;
	u8   orca_password[4];
	u8   access_id[16];
	u8   reserved[356];
};
#pragma pack()

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int 	max_commands;
	atomic_t commands_outstanding;
#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[MAX_REPLY_QUEUES];
	unsigned int msix_vector;
	unsigned int msi_vector;
	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
	struct access_method access;
	char hba_mode_enabled;

	/* queue and queue Info */
	unsigned int Qdepth;
	unsigned int maxSG;
	spinlock_t lock;
	int maxsgentries;
	u8 max_cmd_sg_entries;
	int chainsize;
	struct SGDescriptor **cmd_sg_list;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct io_accel1_cmd	*ioaccel_cmd_pool;
	dma_addr_t		ioaccel_cmd_pool_dhandle;
	struct io_accel2_cmd	*ioaccel2_cmd_pool;
	dma_addr_t		ioaccel2_cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			scan_finished;
	spinlock_t		scan_lock;
	wait_queue_head_t	scan_wait_queue;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct __iomem *transtable;
	unsigned long transMethod;

	/* cap concurrent passthrus at some reasonable maximum */
#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
	spinlock_t passthru_count_lock; /* protects passthru_count */
	int passthru_count;

	/*
	 * Performant mode completion buffers
	 */
	size_t reply_queue_size;
	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
	u8 nreply_queues;
	u32 *blockFetchTable;
	u32 *ioaccel1_blockFetchTable;
	u32 *ioaccel2_blockFetchTable;
	u32 __iomem *ioaccel2_bft2_regs;
	unsigned char *hba_inquiry_data;
	u32 driver_support;
	u32 fw_support;
	int ioaccel_support;
	int ioaccel_maxsg;
	u64 last_intr_timestamp;
	u32 last_heartbeat;
	u64 last_heartbeat_timestamp;
	u32 heartbeat_sample_interval;
	atomic_t firmware_flash_in_progress;
	u32 __percpu *lockup_detected;
	struct delayed_work monitor_ctlr_work;
	int remove_in_progress;
	/* Address of h->q[x] is passed to intr handler to know which queue */
	u8 q[MAX_REPLY_QUEUES];
	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
#define HPSATMF_BITS_SUPPORTED  (1 << 0)
#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
#define HPSATMF_MASK_SUPPORTED  (1 << 16)
#define HPSATMF_LOG_LUN_RESET   (1 << 17)
#define HPSATMF_LOG_NEX_RESET   (1 << 18)
#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
#define HPSATMF_LOG_QRY_TASK    (1 << 23)
#define HPSATMF_LOG_QRY_TSET    (1 << 24)
#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
	u32 events;
#define CTLR_STATE_CHANGE_EVENT				(1 << 0)
#define CTLR_ENCLOSURE_HOT_PLUG_EVENT			(1 << 1)
#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV		(1 << 4)
#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV		(1 << 5)
#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL		(1 << 6)
#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED	(1 << 30)
#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE	(1 << 31)

#define RESCAN_REQUIRED_EVENT_BITS \
		(CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
		CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
		CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
	spinlock_t offline_device_lock;
	struct list_head offline_device_list;
	int	acciopath_status;
	int	raid_offload_debug;
};

struct offline_device_entry {
	unsigned char scsi3addr[8];
	struct list_head offline_list;
};

#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_RESET_TYPE_CONTROLLER 0x00
#define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_BOARD_NOT_READY_ITERATIONS \
	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

/* Performant mode flags */
#define SA5_PERF_INTR_PENDING   0x04
#define SA5_PERF_INTR_OFF       0x05
#define SA5_OUTDB_STATUS_PERF_BIT       0x01
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0

/*
 * Inbound Post Queue offsets for IO Accelerator Mode 2
 */
#define IOACCEL2_INBOUND_POSTQ_32	0x48
#define IOACCEL2_INBOUND_POSTQ_64_LOW	0xd0
#define IOACCEL2_INBOUND_POSTQ_64_HI	0xd4

/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

static void SA5_submit_command_no_read(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	struct CommandList *c)
{
	if (c->cmd_type == CMD_IOACCEL2)
		writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	else
		writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
{
	struct reply_queue_buffer *rq = &h->reply_queue[q];
	unsigned long register_value = FIFO_EMPTY;

	/* msi auto clears the interrupt pending bit. */
	if (!(h->msi_vector || h->msix_vector)) {
		/* flush the controller write of the reply queue by reading
		 * outbound doorbell status register.
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
		register_value = rq->head[rq->current_entry];
		rq->current_entry++;
		atomic_dec(&h->commands_outstanding);
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (rq->current_entry == h->max_commands) {
		rq->current_entry = 0;
		rq->wraparound ^= 1;
	}
	return register_value;
}

/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h,
	__attribute__((unused)) u8 q)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);

	if (register_value != FIFO_EMPTY)
		atomic_dec(&h->commands_outstanding);

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	return register_value & SA5_INTR_PENDING;
}

static bool SA5_performant_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	if (h->msi_vector || h->msix_vector)
		return true;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT    0x100

static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
		true : false;
}

#define IOACCEL_MODE1_REPLY_QUEUE_INDEX  0x1A0
#define IOACCEL_MODE1_PRODUCER_INDEX     0x1B8
#define IOACCEL_MODE1_CONSUMER_INDEX     0x1BC
#define IOACCEL_MODE1_REPLY_UNUSED       0xFFFFFFFFFFFFFFFFULL

static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
{
	u64 register_value;
	struct reply_queue_buffer *rq = &h->reply_queue[q];

	BUG_ON(q >= h->nreply_queues);

	register_value = rq->head[rq->current_entry];
	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
		rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
		if (++rq->current_entry == rq->size)
			rq->current_entry = 0;
		/*
		 * @todo
		 *
		 * Don't really need to write the new index after each command,
		 * but with current driver design this is easiest.
		 */
		wmb();
		writel((q << 24) | rq->current_entry, h->vaddr +
				IOACCEL_MODE1_CONSUMER_INDEX);
		atomic_dec(&h->commands_outstanding);
	}
	return (unsigned long) register_value;
}

static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_intr_pending,
	SA5_completed,
};

static struct access_method SA5_ioaccel_mode1_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_ioaccel_mode1_intr_pending,
	SA5_ioaccel_mode1_completed,
};

static struct access_method SA5_ioaccel_mode2_access = {
	SA5_submit_command_ioaccel2,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access_no_read = {
	SA5_submit_command_no_read,
	SA5_performant_intr_mask,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
edd16368 SC	2	* Disk Array driver for HP Smart Array SAS controllers
51c35139	3	* Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368 SC	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
900c5440	35	bool (intr_pending)(struct ctlr_info h);
254f796b	36	unsigned long (command_completed)(struct ctlr_info h, u8 q);
edd16368 SC	37	};
	38
	39	struct hpsa_scsi_dev_t {
	40	int devtype;
	41	int bus, target, lun; /* as presented to the OS */
	42	unsigned char scsi3addr[8]; /* as presented to the HW */
	43	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	44	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	45	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	46	unsigned char model[16]; /* bytes 16-31 of inquiry data */
edd16368	47	unsigned char raid_level; /* from inquiry page 0xC1 */
9846590e	48	unsigned char volume_offline; /* discovered via TUR or VPD */
e1f7de0c	49	u32 ioaccel_handle;
283b4a9b SC	50	int offload_config; /* I/O accel RAID offload configured */
	51	int offload_enabled; /* I/O accel RAID offload enabled */
	52	int offload_to_mirror; /* Send next I/O accelerator RAID
	53	* offload request to mirror drive
	54	*/
	55	struct raid_map_data raid_map; /* I/O accelerator RAID map */
	56
edd16368 SC	57	};
edd16368 SC	58
072b0518	59	struct reply_queue_buffer {
254f796b MG	60	u64 *head;
	61	size_t size;
	62	u8 wraparound;
	63	u32 current_entry;
072b0518	64	dma_addr_t busaddr;
254f796b MG	65	};
254f796b MG	66
316b221a SC	67	#pragma pack(1)
	68	struct bmic_controller_parameters {
	69	u8 led_flags;
	70	u8 enable_command_list_verification;
	71	u8 backed_out_write_drives;
	72	u16 stripes_for_parity;
	73	u8 parity_distribution_mode_flags;
	74	u16 max_driver_requests;
	75	u16 elevator_trend_count;
	76	u8 disable_elevator;
	77	u8 force_scan_complete;
	78	u8 scsi_transfer_mode;
	79	u8 force_narrow;
	80	u8 rebuild_priority;
	81	u8 expand_priority;
	82	u8 host_sdb_asic_fix;
	83	u8 pdpi_burst_from_host_disabled;
	84	char software_name[64];
	85	char hardware_name[32];
	86	u8 bridge_revision;
	87	u8 snapshot_priority;
	88	u32 os_specific;
	89	u8 post_prompt_timeout;
	90	u8 automatic_drive_slamming;
	91	u8 reserved1;
	92	u8 nvram_flags;
6e8e8088	93	#define HBA_MODE_ENABLED_FLAG (1 << 3)
316b221a SC	94	u8 cache_nvram_flags;
	95	u8 drive_config_flags;
	96	u16 reserved2;
	97	u8 temp_warning_level;
	98	u8 temp_shutdown_level;
	99	u8 temp_condition_reset;
	100	u8 max_coalesce_commands;
	101	u32 max_coalesce_delay;
	102	u8 orca_password[4];
	103	u8 access_id[16];
	104	u8 reserved[356];
	105	};
	106	#pragma pack()
	107
edd16368 SC	108	struct ctlr_info {
	109	int ctlr;
	110	char devname[8];
	111	char *product_name;
edd16368	112	struct pci_dev *pdev;
01a02ffc	113	u32 board_id;
edd16368 SC	114	void __iomem *vaddr;
	115	unsigned long paddr;
	116	int nr_cmds; /* Number of commands allowed on this controller */
d54c5c24 SC	117	#define HPSA_CMDS_RESERVED_FOR_ABORTS 2
d54c5c24 SC	118	#define HPSA_CMDS_RESERVED_FOR_DRIVER 1
edd16368 SC	119	struct CfgTable __iomem *cfgtable;
edd16368 SC	120	int interrupts_enabled;
edd16368	121	int max_commands;
0cbf768e	122	atomic_t commands_outstanding;
303932fd DB	123	# define PERF_MODE_INT 0
303932fd DB	124	# define DOORBELL_INT 1
edd16368 SC	125	# define SIMPLE_MODE_INT 2
edd16368 SC	126	# define MEMQ_MODE_INT 3
254f796b	127	unsigned int intr[MAX_REPLY_QUEUES];
edd16368 SC	128	unsigned int msix_vector;
edd16368 SC	129	unsigned int msi_vector;
a9a3a273	130	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
edd16368	131	struct access_method access;
316b221a	132	char hba_mode_enabled;
edd16368 SC	133
edd16368 SC	134	/* queue and queue Info */
edd16368	135	unsigned int Qdepth;
edd16368 SC	136	unsigned int maxSG;
edd16368 SC	137	spinlock_t lock;
33a2ffce SC	138	int maxsgentries;
	139	u8 max_cmd_sg_entries;
	140	int chainsize;
	141	struct SGDescriptor **cmd_sg_list;
edd16368 SC	142
	143	/* pointers to command and error info pool */
	144	struct CommandList *cmd_pool;
	145	dma_addr_t cmd_pool_dhandle;
e1f7de0c MG	146	struct io_accel1_cmd *ioaccel_cmd_pool;
e1f7de0c MG	147	dma_addr_t ioaccel_cmd_pool_dhandle;
aca9012a SC	148	struct io_accel2_cmd *ioaccel2_cmd_pool;
aca9012a SC	149	dma_addr_t ioaccel2_cmd_pool_dhandle;
edd16368 SC	150	struct ErrorInfo *errinfo_pool;
	151	dma_addr_t errinfo_pool_dhandle;
	152	unsigned long *cmd_pool_bits;
a08a8471 SC	153	int scan_finished;
	154	spinlock_t scan_lock;
	155	wait_queue_head_t scan_wait_queue;
edd16368 SC	156
	157	struct Scsi_Host *scsi_host;
	158	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	159	int ndevices; /* number of used elements in .dev[] array. */
cfe5badc	160	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
303932fd DB	161	/*
	162	* Performant mode tables.
	163	*/
	164	u32 trans_support;
	165	u32 trans_offset;
42a91641	166	struct TransTable_struct __iomem *transtable;
303932fd DB	167	unsigned long transMethod;
303932fd DB	168
0390f0c0	169	/* cap concurrent passthrus at some reasonable maximum */
45fcb86e	170	#define HPSA_MAX_CONCURRENT_PASSTHRUS (10)
0390f0c0 SC	171	spinlock_t passthru_count_lock; /* protects passthru_count */
	172	int passthru_count;
	173
303932fd	174	/*
254f796b	175	* Performant mode completion buffers
303932fd	176	*/
072b0518 SC	177	size_t reply_queue_size;
072b0518 SC	178	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
254f796b	179	u8 nreply_queues;
303932fd	180	u32 *blockFetchTable;
e1f7de0c	181	u32 *ioaccel1_blockFetchTable;
aca9012a	182	u32 *ioaccel2_blockFetchTable;
42a91641	183	u32 __iomem *ioaccel2_bft2_regs;
339b2b14	184	unsigned char *hba_inquiry_data;
283b4a9b SC	185	u32 driver_support;
	186	u32 fw_support;
	187	int ioaccel_support;
	188	int ioaccel_maxsg;
a0c12413 SC	189	u64 last_intr_timestamp;
	190	u32 last_heartbeat;
	191	u64 last_heartbeat_timestamp;
e85c5974 SC	192	u32 heartbeat_sample_interval;
e85c5974 SC	193	atomic_t firmware_flash_in_progress;
42a91641	194	u32 __percpu *lockup_detected;
8a98db73 SC	195	struct delayed_work monitor_ctlr_work;
8a98db73 SC	196	int remove_in_progress;
254f796b MG	197	/* Address of h->q[x] is passed to intr handler to know which queue */
254f796b MG	198	u8 q[MAX_REPLY_QUEUES];
75167d2c SC	199	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
	200	#define HPSATMF_BITS_SUPPORTED (1 << 0)
	201	#define HPSATMF_PHYS_LUN_RESET (1 << 1)
	202	#define HPSATMF_PHYS_NEX_RESET (1 << 2)
	203	#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
	204	#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
	205	#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
	206	#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
	207	#define HPSATMF_PHYS_QRY_TASK (1 << 7)
	208	#define HPSATMF_PHYS_QRY_TSET (1 << 8)
	209	#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
	210	#define HPSATMF_MASK_SUPPORTED (1 << 16)
	211	#define HPSATMF_LOG_LUN_RESET (1 << 17)
	212	#define HPSATMF_LOG_NEX_RESET (1 << 18)
	213	#define HPSATMF_LOG_TASK_ABORT (1 << 19)
	214	#define HPSATMF_LOG_TSET_ABORT (1 << 20)
	215	#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
	216	#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
	217	#define HPSATMF_LOG_QRY_TASK (1 << 23)
	218	#define HPSATMF_LOG_QRY_TSET (1 << 24)
	219	#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
76438d08	220	u32 events;
faff6ee0 SC	221	#define CTLR_STATE_CHANGE_EVENT (1 << 0)
	222	#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
	223	#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
	224	#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
	225	#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
	226	#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
	227	#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
	228
	229	#define RESCAN_REQUIRED_EVENT_BITS \
7b2c46ee	230	(CTLR_ENCLOSURE_HOT_PLUG_EVENT \| \
faff6ee0 SC	231	CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV \| \
faff6ee0 SC	232	CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV \| \
faff6ee0 SC	233	CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED \| \
faff6ee0 SC	234	CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
9846590e SC	235	spinlock_t offline_device_lock;
9846590e SC	236	struct list_head offline_device_list;
da0697bd	237	int acciopath_status;
2ba8bfc8	238	int raid_offload_debug;
edd16368	239	};
9846590e SC	240
	241	struct offline_device_entry {
	242	unsigned char scsi3addr[8];
	243	struct list_head offline_list;
	244	};
	245
edd16368 SC	246	#define HPSA_ABORT_MSG 0
edd16368 SC	247	#define HPSA_DEVICE_RESET_MSG 1
64670ac8 SC	248	#define HPSA_RESET_TYPE_CONTROLLER 0x00
	249	#define HPSA_RESET_TYPE_BUS 0x01
	250	#define HPSA_RESET_TYPE_TARGET 0x03
	251	#define HPSA_RESET_TYPE_LUN 0x04
edd16368	252	#define HPSA_MSG_SEND_RETRY_LIMIT 10
516fda49	253	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
edd16368 SC	254
	255	/* Maximum time in seconds driver will wait for command completions
	256	* when polling before giving up.
	257	*/
	258	#define HPSA_MAX_POLL_TIME_SECS (20)
	259
	260	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	261	* how many times to retry TEST UNIT READY on a device
	262	* while waiting for it to become ready before giving up.
	263	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	264	* between sending TURs while waiting for a device
	265	* to become ready.
	266	*/
	267	#define HPSA_TUR_RETRY_LIMIT (20)
	268	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
	269
	270	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
	271	* to become ready, in seconds, before giving up on it.
	272	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	273	* between polling the board to see if it is ready, in
	274	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
	275	* HPSA_BOARD_READY_ITERATIONS are derived from those.
	276	*/
	277	#define HPSA_BOARD_READY_WAIT_SECS (120)
2ed7127b	278	#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
edd16368 SC	279	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
	280	#define HPSA_BOARD_READY_POLL_INTERVAL \
	281	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
	282	#define HPSA_BOARD_READY_ITERATIONS \
	283	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
	284	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
fe5389c8 SC	285	#define HPSA_BOARD_NOT_READY_ITERATIONS \
	286	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	287	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
edd16368 SC	288	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
	289	#define HPSA_POST_RESET_NOOP_RETRIES (12)
	290
	291	/* Defining the diffent access_menthods */
	292	/*
	293	* Memory mapped FIFO interface (SMART 53xx cards)
	294	*/
	295	#define SA5_DOORBELL 0x20
	296	#define SA5_REQUEST_PORT_OFFSET 0x40
	297	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	298	#define SA5_REPLY_PORT_OFFSET 0x44
	299	#define SA5_INTR_STATUS 0x30
	300	#define SA5_SCRATCHPAD_OFFSET 0xB0
	301
	302	#define SA5_CTCFG_OFFSET 0xB4
	303	#define SA5_CTMEM_OFFSET 0xB8
	304
	305	#define SA5_INTR_OFF 0x08
	306	#define SA5B_INTR_OFF 0x04
	307	#define SA5_INTR_PENDING 0x08
	308	#define SA5B_INTR_PENDING 0x04
	309	#define FIFO_EMPTY 0xffffffff
	310	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
	311
	312	#define HPSA_ERROR_BIT 0x02
edd16368	313
303932fd DB	314	/* Performant mode flags */
	315	#define SA5_PERF_INTR_PENDING 0x04
	316	#define SA5_PERF_INTR_OFF 0x05
	317	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	318	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	319	#define SA5_OUTDB_CLEAR 0xA0
	320	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	321	#define SA5_OUTDB_STATUS 0x9C
	322
	323
edd16368 SC	324	#define HPSA_INTR_ON 1
edd16368 SC	325	#define HPSA_INTR_OFF 0
b66cc250 MM	326
	327	/*
	328	* Inbound Post Queue offsets for IO Accelerator Mode 2
	329	*/
	330	#define IOACCEL2_INBOUND_POSTQ_32 0x48
	331	#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
	332	#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
	333
edd16368 SC	334	/*
	335	Send the command to the hardware
	336	*/
	337	static void SA5_submit_command(struct ctlr_info *h,
	338	struct CommandList *c)
	339	{
edd16368	340	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
fec62c36	341	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
edd16368 SC	342	}
edd16368 SC	343
b3a52e79 SC	344	static void SA5_submit_command_no_read(struct ctlr_info *h,
	345	struct CommandList *c)
	346	{
	347	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	348	}
	349
c349775e ST	350	static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	351	struct CommandList *c)
	352	{
c349775e ST	353	if (c->cmd_type == CMD_IOACCEL2)
	354	writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	355	else
	356	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e ST	357	}
c349775e ST	358
edd16368 SC	359	/*
	360	* This card is the opposite of the other cards.
	361	* 0 turns interrupts on...
	362	* 0x08 turns them off...
	363	*/
	364	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	365	{
	366	if (val) { /* Turn interrupts on */
	367	h->interrupts_enabled = 1;
	368	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	369	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	370	} else { /* Turn them off */
	371	h->interrupts_enabled = 0;
	372	writel(SA5_INTR_OFF,
	373	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	374	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	375	}
edd16368 SC	376	}
303932fd DB	377
	378	static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
	379	{
	380	if (val) { /* turn on interrupts */
	381	h->interrupts_enabled = 1;
	382	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	383	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	384	} else {
	385	h->interrupts_enabled = 0;
	386	writel(SA5_PERF_INTR_OFF,
	387	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	388	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	389	}
	390	}
	391
254f796b	392	static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
303932fd	393	{
072b0518	394	struct reply_queue_buffer *rq = &h->reply_queue[q];
0cbf768e	395	unsigned long register_value = FIFO_EMPTY;
303932fd	396
303932fd DB	397	/* msi auto clears the interrupt pending bit. */
303932fd DB	398	if (!(h->msi_vector \|\| h->msix_vector)) {
2c17d2da SC	399	/* flush the controller write of the reply queue by reading
	400	* outbound doorbell status register.
	401	*/
	402	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	403	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	404	/* Do a read in order to flush the write to the controller
	405	* (as per spec.)
	406	*/
	407	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	408	}
	409
254f796b MG	410	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
	411	register_value = rq->head[rq->current_entry];
	412	rq->current_entry++;
0cbf768e	413	atomic_dec(&h->commands_outstanding);
303932fd DB	414	} else {
	415	register_value = FIFO_EMPTY;
	416	}
	417	/* Check for wraparound */
254f796b MG	418	if (rq->current_entry == h->max_commands) {
	419	rq->current_entry = 0;
	420	rq->wraparound ^= 1;
303932fd	421	}
303932fd DB	422	return register_value;
	423	}
	424
edd16368 SC	425	/*
	426	* returns value read from hardware.
	427	* returns FIFO_EMPTY if there is nothing to read
	428	*/
254f796b MG	429	static unsigned long SA5_completed(struct ctlr_info *h,
254f796b MG	430	__attribute__((unused)) u8 q)
edd16368 SC	431	{
	432	unsigned long register_value
	433	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	434
0cbf768e SC	435	if (register_value != FIFO_EMPTY)
0cbf768e SC	436	atomic_dec(&h->commands_outstanding);
edd16368 SC	437
	438	#ifdef HPSA_DEBUG
	439	if (register_value != FIFO_EMPTY)
84ca0be2	440	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	441	register_value);
edd16368 SC	442	else
f79cfec6	443	dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
edd16368 SC	444	#endif
	445
	446	return register_value;
	447	}
	448	/*
	449	* Returns true if an interrupt is pending..
	450	*/
900c5440	451	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	452	{
	453	unsigned long register_value =
	454	readl(h->vaddr + SA5_INTR_STATUS);
900c5440	455	return register_value & SA5_INTR_PENDING;
edd16368 SC	456	}
edd16368 SC	457
303932fd DB	458	static bool SA5_performant_intr_pending(struct ctlr_info *h)
	459	{
	460	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	461
	462	if (!register_value)
	463	return false;
	464
	465	if (h->msi_vector \|\| h->msix_vector)
	466	return true;
	467
	468	/* Read outbound doorbell to flush */
	469	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	470	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	471	}
edd16368	472
e1f7de0c MG	473	#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
	474
	475	static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
	476	{
	477	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	478
	479	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
	480	true : false;
	481	}
	482
	483	#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
	484	#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
	485	#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
	486	#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
	487
283b4a9b	488	static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
e1f7de0c MG	489	{
e1f7de0c MG	490	u64 register_value;
072b0518	491	struct reply_queue_buffer *rq = &h->reply_queue[q];
e1f7de0c MG	492
	493	BUG_ON(q >= h->nreply_queues);
	494
	495	register_value = rq->head[rq->current_entry];
	496	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
	497	rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
	498	if (++rq->current_entry == rq->size)
	499	rq->current_entry = 0;
283b4a9b SC	500	/*
	501	* @todo
	502	*
	503	* Don't really need to write the new index after each command,
	504	* but with current driver design this is easiest.
	505	*/
	506	wmb();
	507	writel((q << 24) \| rq->current_entry, h->vaddr +
	508	IOACCEL_MODE1_CONSUMER_INDEX);
0cbf768e	509	atomic_dec(&h->commands_outstanding);
e1f7de0c MG	510	}
	511	return (unsigned long) register_value;
	512	}
	513
edd16368 SC	514	static struct access_method SA5_access = {
	515	SA5_submit_command,
	516	SA5_intr_mask,
edd16368 SC	517	SA5_intr_pending,
	518	SA5_completed,
	519	};
	520
e1f7de0c MG	521	static struct access_method SA5_ioaccel_mode1_access = {
	522	SA5_submit_command,
	523	SA5_performant_intr_mask,
e1f7de0c MG	524	SA5_ioaccel_mode1_intr_pending,
	525	SA5_ioaccel_mode1_completed,
	526	};
	527
c349775e ST	528	static struct access_method SA5_ioaccel_mode2_access = {
	529	SA5_submit_command_ioaccel2,
	530	SA5_performant_intr_mask,
c349775e ST	531	SA5_performant_intr_pending,
	532	SA5_performant_completed,
	533	};
	534
303932fd DB	535	static struct access_method SA5_performant_access = {
	536	SA5_submit_command,
	537	SA5_performant_intr_mask,
303932fd DB	538	SA5_performant_intr_pending,
	539	SA5_performant_completed,
	540	};
	541
b3a52e79 SC	542	static struct access_method SA5_performant_access_no_read = {
	543	SA5_submit_command_no_read,
	544	SA5_performant_intr_mask,
b3a52e79 SC	545	SA5_performant_intr_pending,
	546	SA5_performant_completed,
	547	};
	548
edd16368	549	struct board_type {
01a02ffc	550	u32 board_id;
edd16368 SC	551	char *product_name;
	552	struct access_method *access;
	553	};
	554
edd16368 SC	555	#endif /* HPSA_H */
edd16368 SC	556