[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	unsigned long (*fifo_full)(struct ctlr_info *h);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
	unsigned char volume_offline;	/* discovered via TUR or VPD */
	u32 ioaccel_handle;
	int offload_config;		/* I/O accel RAID offload configured */
	int offload_enabled;		/* I/O accel RAID offload enabled */
	int offload_to_mirror;		/* Send next I/O accelerator RAID
					 * offload request to mirror drive
					 */
	struct raid_map_data raid_map;	/* I/O accelerator RAID map */

};

struct reply_queue_buffer {
	u64 *head;
	size_t size;
	u8 wraparound;
	u32 current_entry;
	dma_addr_t busaddr;
};

#pragma pack(1)
struct bmic_controller_parameters {
	u8   led_flags;
	u8   enable_command_list_verification;
	u8   backed_out_write_drives;
	u16  stripes_for_parity;
	u8   parity_distribution_mode_flags;
	u16  max_driver_requests;
	u16  elevator_trend_count;
	u8   disable_elevator;
	u8   force_scan_complete;
	u8   scsi_transfer_mode;
	u8   force_narrow;
	u8   rebuild_priority;
	u8   expand_priority;
	u8   host_sdb_asic_fix;
	u8   pdpi_burst_from_host_disabled;
	char software_name[64];
	char hardware_name[32];
	u8   bridge_revision;
	u8   snapshot_priority;
	u32  os_specific;
	u8   post_prompt_timeout;
	u8   automatic_drive_slamming;
	u8   reserved1;
	u8   nvram_flags;
#define HBA_MODE_ENABLED_FLAG (1 << 3)
	u8   cache_nvram_flags;
	u8   drive_config_flags;
	u16  reserved2;
	u8   temp_warning_level;
	u8   temp_shutdown_level;
	u8   temp_condition_reset;
	u8   max_coalesce_commands;
	u32  max_coalesce_delay;
	u8   orca_password[4];
	u8   access_id[16];
	u8   reserved[356];
};
#pragma pack()

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int 	max_commands;
	atomic_t commands_outstanding;
#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[MAX_REPLY_QUEUES];
	unsigned int msix_vector;
	unsigned int msi_vector;
	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
	struct access_method access;
	char hba_mode_enabled;

	/* queue and queue Info */
	struct list_head reqQ;
	struct list_head cmpQ;
	unsigned int Qdepth;
	unsigned int maxSG;
	spinlock_t lock;
	int maxsgentries;
	u8 max_cmd_sg_entries;
	int chainsize;
	struct SGDescriptor **cmd_sg_list;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct io_accel1_cmd	*ioaccel_cmd_pool;
	dma_addr_t		ioaccel_cmd_pool_dhandle;
	struct io_accel2_cmd	*ioaccel2_cmd_pool;
	dma_addr_t		ioaccel2_cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			scan_finished;
	spinlock_t		scan_lock;
	wait_queue_head_t	scan_wait_queue;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct __iomem *transtable;
	unsigned long transMethod;

	/* cap concurrent passthrus at some reasonable maximum */
#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	spinlock_t passthru_count_lock; /* protects passthru_count */
	int passthru_count;

	/*
	 * Performant mode completion buffers
	 */
	size_t reply_queue_size;
	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
	u8 nreply_queues;
	u32 *blockFetchTable;
	u32 *ioaccel1_blockFetchTable;
	u32 *ioaccel2_blockFetchTable;
	u32 __iomem *ioaccel2_bft2_regs;
	unsigned char *hba_inquiry_data;
	u32 driver_support;
	u32 fw_support;
	int ioaccel_support;
	int ioaccel_maxsg;
	u64 last_intr_timestamp;
	u32 last_heartbeat;
	u64 last_heartbeat_timestamp;
	u32 heartbeat_sample_interval;
	atomic_t firmware_flash_in_progress;
	u32 __percpu *lockup_detected;
	struct delayed_work monitor_ctlr_work;
	int remove_in_progress;
	u32 fifo_recently_full;
	/* Address of h->q[x] is passed to intr handler to know which queue */
	u8 q[MAX_REPLY_QUEUES];
	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
#define HPSATMF_BITS_SUPPORTED  (1 << 0)
#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
#define HPSATMF_MASK_SUPPORTED  (1 << 16)
#define HPSATMF_LOG_LUN_RESET   (1 << 17)
#define HPSATMF_LOG_NEX_RESET   (1 << 18)
#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
#define HPSATMF_LOG_QRY_TASK    (1 << 23)
#define HPSATMF_LOG_QRY_TSET    (1 << 24)
#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
	u32 events;
#define CTLR_STATE_CHANGE_EVENT				(1 << 0)
#define CTLR_ENCLOSURE_HOT_PLUG_EVENT			(1 << 1)
#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV		(1 << 4)
#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV		(1 << 5)
#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL		(1 << 6)
#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED	(1 << 30)
#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE	(1 << 31)

#define RESCAN_REQUIRED_EVENT_BITS \
		(CTLR_ENCLOSURE_HOT_PLUG_EVENT | \
		CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \
		CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \
		CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
	spinlock_t offline_device_lock;
	struct list_head offline_device_list;
	int	acciopath_status;
	int	drv_req_rescan;	/* flag for driver to request rescan event */
	int	raid_offload_debug;
};

struct offline_device_entry {
	unsigned char scsi3addr[8];
	struct list_head offline_list;
};

#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_RESET_TYPE_CONTROLLER 0x00
#define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_BOARD_NOT_READY_ITERATIONS \
	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

/* Performant mode flags */
#define SA5_PERF_INTR_PENDING   0x04
#define SA5_PERF_INTR_OFF       0x05
#define SA5_OUTDB_STATUS_PERF_BIT       0x01
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0

/*
 * Inbound Post Queue offsets for IO Accelerator Mode 2
 */
#define IOACCEL2_INBOUND_POSTQ_32	0x48
#define IOACCEL2_INBOUND_POSTQ_64_LOW	0xd0
#define IOACCEL2_INBOUND_POSTQ_64_HI	0xd4

/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

static void SA5_submit_command_no_read(struct ctlr_info *h,
	struct CommandList *c)
{
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	struct CommandList *c)
{
	if (c->cmd_type == CMD_IOACCEL2)
		writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	else
		writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
{
	struct reply_queue_buffer *rq = &h->reply_queue[q];
	unsigned long register_value = FIFO_EMPTY;

	/* msi auto clears the interrupt pending bit. */
	if (!(h->msi_vector || h->msix_vector)) {
		/* flush the controller write of the reply queue by reading
		 * outbound doorbell status register.
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
		register_value = rq->head[rq->current_entry];
		rq->current_entry++;
		atomic_dec(&h->commands_outstanding);
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (rq->current_entry == h->max_commands) {
		rq->current_entry = 0;
		rq->wraparound ^= 1;
	}
	return register_value;
}

/*
 *  Returns true if fifo is full.
 *
 */
static unsigned long SA5_fifo_full(struct ctlr_info *h)
{
	return atomic_read(&h->commands_outstanding) >= h->max_commands;
}
/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h,
	__attribute__((unused)) u8 q)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);

	if (register_value != FIFO_EMPTY)
		atomic_dec(&h->commands_outstanding);

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	return register_value & SA5_INTR_PENDING;
}

static bool SA5_performant_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	if (h->msi_vector || h->msix_vector)
		return true;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT    0x100

static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
		true : false;
}

#define IOACCEL_MODE1_REPLY_QUEUE_INDEX  0x1A0
#define IOACCEL_MODE1_PRODUCER_INDEX     0x1B8
#define IOACCEL_MODE1_CONSUMER_INDEX     0x1BC
#define IOACCEL_MODE1_REPLY_UNUSED       0xFFFFFFFFFFFFFFFFULL

static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
{
	u64 register_value;
	struct reply_queue_buffer *rq = &h->reply_queue[q];

	BUG_ON(q >= h->nreply_queues);

	register_value = rq->head[rq->current_entry];
	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
		rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
		if (++rq->current_entry == rq->size)
			rq->current_entry = 0;
		/*
		 * @todo
		 *
		 * Don't really need to write the new index after each command,
		 * but with current driver design this is easiest.
		 */
		wmb();
		writel((q << 24) | rq->current_entry, h->vaddr +
				IOACCEL_MODE1_CONSUMER_INDEX);
		atomic_dec(&h->commands_outstanding);
	}
	return (unsigned long) register_value;
}

static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_fifo_full,
	SA5_intr_pending,
	SA5_completed,
};

static struct access_method SA5_ioaccel_mode1_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_ioaccel_mode1_intr_pending,
	SA5_ioaccel_mode1_completed,
};

static struct access_method SA5_ioaccel_mode2_access = {
	SA5_submit_command_ioaccel2,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access_no_read = {
	SA5_submit_command_no_read,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
edd16368 SC	2	* Disk Array driver for HP Smart Array SAS controllers
51c35139	3	* Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368 SC	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
	35	unsigned long (fifo_full)(struct ctlr_info h);
900c5440	36	bool (intr_pending)(struct ctlr_info h);
254f796b	37	unsigned long (command_completed)(struct ctlr_info h, u8 q);
edd16368 SC	38	};
	39
	40	struct hpsa_scsi_dev_t {
	41	int devtype;
	42	int bus, target, lun; /* as presented to the OS */
	43	unsigned char scsi3addr[8]; /* as presented to the HW */
	44	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	45	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	46	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	47	unsigned char model[16]; /* bytes 16-31 of inquiry data */
edd16368	48	unsigned char raid_level; /* from inquiry page 0xC1 */
9846590e	49	unsigned char volume_offline; /* discovered via TUR or VPD */
e1f7de0c	50	u32 ioaccel_handle;
283b4a9b SC	51	int offload_config; /* I/O accel RAID offload configured */
	52	int offload_enabled; /* I/O accel RAID offload enabled */
	53	int offload_to_mirror; /* Send next I/O accelerator RAID
	54	* offload request to mirror drive
	55	*/
	56	struct raid_map_data raid_map; /* I/O accelerator RAID map */
	57
edd16368 SC	58	};
edd16368 SC	59
072b0518	60	struct reply_queue_buffer {
254f796b MG	61	u64 *head;
	62	size_t size;
	63	u8 wraparound;
	64	u32 current_entry;
072b0518	65	dma_addr_t busaddr;
254f796b MG	66	};
254f796b MG	67
316b221a SC	68	#pragma pack(1)
	69	struct bmic_controller_parameters {
	70	u8 led_flags;
	71	u8 enable_command_list_verification;
	72	u8 backed_out_write_drives;
	73	u16 stripes_for_parity;
	74	u8 parity_distribution_mode_flags;
	75	u16 max_driver_requests;
	76	u16 elevator_trend_count;
	77	u8 disable_elevator;
	78	u8 force_scan_complete;
	79	u8 scsi_transfer_mode;
	80	u8 force_narrow;
	81	u8 rebuild_priority;
	82	u8 expand_priority;
	83	u8 host_sdb_asic_fix;
	84	u8 pdpi_burst_from_host_disabled;
	85	char software_name[64];
	86	char hardware_name[32];
	87	u8 bridge_revision;
	88	u8 snapshot_priority;
	89	u32 os_specific;
	90	u8 post_prompt_timeout;
	91	u8 automatic_drive_slamming;
	92	u8 reserved1;
	93	u8 nvram_flags;
6e8e8088	94	#define HBA_MODE_ENABLED_FLAG (1 << 3)
316b221a SC	95	u8 cache_nvram_flags;
	96	u8 drive_config_flags;
	97	u16 reserved2;
	98	u8 temp_warning_level;
	99	u8 temp_shutdown_level;
	100	u8 temp_condition_reset;
	101	u8 max_coalesce_commands;
	102	u32 max_coalesce_delay;
	103	u8 orca_password[4];
	104	u8 access_id[16];
	105	u8 reserved[356];
	106	};
	107	#pragma pack()
	108
edd16368 SC	109	struct ctlr_info {
	110	int ctlr;
	111	char devname[8];
	112	char *product_name;
edd16368	113	struct pci_dev *pdev;
01a02ffc	114	u32 board_id;
edd16368 SC	115	void __iomem *vaddr;
	116	unsigned long paddr;
	117	int nr_cmds; /* Number of commands allowed on this controller */
	118	struct CfgTable __iomem *cfgtable;
	119	int interrupts_enabled;
edd16368	120	int max_commands;
0cbf768e	121	atomic_t commands_outstanding;
303932fd DB	122	# define PERF_MODE_INT 0
303932fd DB	123	# define DOORBELL_INT 1
edd16368 SC	124	# define SIMPLE_MODE_INT 2
edd16368 SC	125	# define MEMQ_MODE_INT 3
254f796b	126	unsigned int intr[MAX_REPLY_QUEUES];
edd16368 SC	127	unsigned int msix_vector;
edd16368 SC	128	unsigned int msi_vector;
a9a3a273	129	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
edd16368	130	struct access_method access;
316b221a	131	char hba_mode_enabled;
edd16368 SC	132
edd16368 SC	133	/* queue and queue Info */
9e0fc764 SC	134	struct list_head reqQ;
9e0fc764 SC	135	struct list_head cmpQ;
edd16368	136	unsigned int Qdepth;
edd16368 SC	137	unsigned int maxSG;
edd16368 SC	138	spinlock_t lock;
33a2ffce SC	139	int maxsgentries;
	140	u8 max_cmd_sg_entries;
	141	int chainsize;
	142	struct SGDescriptor **cmd_sg_list;
edd16368 SC	143
	144	/* pointers to command and error info pool */
	145	struct CommandList *cmd_pool;
	146	dma_addr_t cmd_pool_dhandle;
e1f7de0c MG	147	struct io_accel1_cmd *ioaccel_cmd_pool;
e1f7de0c MG	148	dma_addr_t ioaccel_cmd_pool_dhandle;
aca9012a SC	149	struct io_accel2_cmd *ioaccel2_cmd_pool;
aca9012a SC	150	dma_addr_t ioaccel2_cmd_pool_dhandle;
edd16368 SC	151	struct ErrorInfo *errinfo_pool;
	152	dma_addr_t errinfo_pool_dhandle;
	153	unsigned long *cmd_pool_bits;
a08a8471 SC	154	int scan_finished;
	155	spinlock_t scan_lock;
	156	wait_queue_head_t scan_wait_queue;
edd16368 SC	157
	158	struct Scsi_Host *scsi_host;
	159	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	160	int ndevices; /* number of used elements in .dev[] array. */
cfe5badc	161	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
303932fd DB	162	/*
	163	* Performant mode tables.
	164	*/
	165	u32 trans_support;
	166	u32 trans_offset;
42a91641	167	struct TransTable_struct __iomem *transtable;
303932fd DB	168	unsigned long transMethod;
303932fd DB	169
0390f0c0 SC	170	/* cap concurrent passthrus at some reasonable maximum */
	171	#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	172	spinlock_t passthru_count_lock; /* protects passthru_count */
	173	int passthru_count;
	174
303932fd	175	/*
254f796b	176	* Performant mode completion buffers
303932fd	177	*/
072b0518 SC	178	size_t reply_queue_size;
072b0518 SC	179	struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES];
254f796b	180	u8 nreply_queues;
303932fd	181	u32 *blockFetchTable;
e1f7de0c	182	u32 *ioaccel1_blockFetchTable;
aca9012a	183	u32 *ioaccel2_blockFetchTable;
42a91641	184	u32 __iomem *ioaccel2_bft2_regs;
339b2b14	185	unsigned char *hba_inquiry_data;
283b4a9b SC	186	u32 driver_support;
	187	u32 fw_support;
	188	int ioaccel_support;
	189	int ioaccel_maxsg;
a0c12413 SC	190	u64 last_intr_timestamp;
	191	u32 last_heartbeat;
	192	u64 last_heartbeat_timestamp;
e85c5974 SC	193	u32 heartbeat_sample_interval;
e85c5974 SC	194	atomic_t firmware_flash_in_progress;
42a91641	195	u32 __percpu *lockup_detected;
8a98db73 SC	196	struct delayed_work monitor_ctlr_work;
8a98db73 SC	197	int remove_in_progress;
396883e2	198	u32 fifo_recently_full;
254f796b MG	199	/* Address of h->q[x] is passed to intr handler to know which queue */
254f796b MG	200	u8 q[MAX_REPLY_QUEUES];
75167d2c SC	201	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
	202	#define HPSATMF_BITS_SUPPORTED (1 << 0)
	203	#define HPSATMF_PHYS_LUN_RESET (1 << 1)
	204	#define HPSATMF_PHYS_NEX_RESET (1 << 2)
	205	#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
	206	#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
	207	#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
	208	#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
	209	#define HPSATMF_PHYS_QRY_TASK (1 << 7)
	210	#define HPSATMF_PHYS_QRY_TSET (1 << 8)
	211	#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
	212	#define HPSATMF_MASK_SUPPORTED (1 << 16)
	213	#define HPSATMF_LOG_LUN_RESET (1 << 17)
	214	#define HPSATMF_LOG_NEX_RESET (1 << 18)
	215	#define HPSATMF_LOG_TASK_ABORT (1 << 19)
	216	#define HPSATMF_LOG_TSET_ABORT (1 << 20)
	217	#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
	218	#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
	219	#define HPSATMF_LOG_QRY_TASK (1 << 23)
	220	#define HPSATMF_LOG_QRY_TSET (1 << 24)
	221	#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
76438d08	222	u32 events;
faff6ee0 SC	223	#define CTLR_STATE_CHANGE_EVENT (1 << 0)
	224	#define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1)
	225	#define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4)
	226	#define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5)
	227	#define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6)
	228	#define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30)
	229	#define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31)
	230
	231	#define RESCAN_REQUIRED_EVENT_BITS \
7b2c46ee	232	(CTLR_ENCLOSURE_HOT_PLUG_EVENT \| \
faff6ee0 SC	233	CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV \| \
faff6ee0 SC	234	CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV \| \
faff6ee0 SC	235	CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED \| \
faff6ee0 SC	236	CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE)
9846590e SC	237	spinlock_t offline_device_lock;
9846590e SC	238	struct list_head offline_device_list;
da0697bd	239	int acciopath_status;
e863d68e	240	int drv_req_rescan; /* flag for driver to request rescan event */
2ba8bfc8	241	int raid_offload_debug;
edd16368	242	};
9846590e SC	243
	244	struct offline_device_entry {
	245	unsigned char scsi3addr[8];
	246	struct list_head offline_list;
	247	};
	248
edd16368 SC	249	#define HPSA_ABORT_MSG 0
edd16368 SC	250	#define HPSA_DEVICE_RESET_MSG 1
64670ac8 SC	251	#define HPSA_RESET_TYPE_CONTROLLER 0x00
	252	#define HPSA_RESET_TYPE_BUS 0x01
	253	#define HPSA_RESET_TYPE_TARGET 0x03
	254	#define HPSA_RESET_TYPE_LUN 0x04
edd16368	255	#define HPSA_MSG_SEND_RETRY_LIMIT 10
516fda49	256	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
edd16368 SC	257
	258	/* Maximum time in seconds driver will wait for command completions
	259	* when polling before giving up.
	260	*/
	261	#define HPSA_MAX_POLL_TIME_SECS (20)
	262
	263	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	264	* how many times to retry TEST UNIT READY on a device
	265	* while waiting for it to become ready before giving up.
	266	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	267	* between sending TURs while waiting for a device
	268	* to become ready.
	269	*/
	270	#define HPSA_TUR_RETRY_LIMIT (20)
	271	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
	272
	273	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
	274	* to become ready, in seconds, before giving up on it.
	275	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	276	* between polling the board to see if it is ready, in
	277	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
	278	* HPSA_BOARD_READY_ITERATIONS are derived from those.
	279	*/
	280	#define HPSA_BOARD_READY_WAIT_SECS (120)
2ed7127b	281	#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
edd16368 SC	282	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
	283	#define HPSA_BOARD_READY_POLL_INTERVAL \
	284	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
	285	#define HPSA_BOARD_READY_ITERATIONS \
	286	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
	287	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
fe5389c8 SC	288	#define HPSA_BOARD_NOT_READY_ITERATIONS \
	289	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	290	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
edd16368 SC	291	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
	292	#define HPSA_POST_RESET_NOOP_RETRIES (12)
	293
	294	/* Defining the diffent access_menthods */
	295	/*
	296	* Memory mapped FIFO interface (SMART 53xx cards)
	297	*/
	298	#define SA5_DOORBELL 0x20
	299	#define SA5_REQUEST_PORT_OFFSET 0x40
	300	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	301	#define SA5_REPLY_PORT_OFFSET 0x44
	302	#define SA5_INTR_STATUS 0x30
	303	#define SA5_SCRATCHPAD_OFFSET 0xB0
	304
	305	#define SA5_CTCFG_OFFSET 0xB4
	306	#define SA5_CTMEM_OFFSET 0xB8
	307
	308	#define SA5_INTR_OFF 0x08
	309	#define SA5B_INTR_OFF 0x04
	310	#define SA5_INTR_PENDING 0x08
	311	#define SA5B_INTR_PENDING 0x04
	312	#define FIFO_EMPTY 0xffffffff
	313	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
	314
	315	#define HPSA_ERROR_BIT 0x02
edd16368	316
303932fd DB	317	/* Performant mode flags */
	318	#define SA5_PERF_INTR_PENDING 0x04
	319	#define SA5_PERF_INTR_OFF 0x05
	320	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	321	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	322	#define SA5_OUTDB_CLEAR 0xA0
	323	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	324	#define SA5_OUTDB_STATUS 0x9C
	325
	326
edd16368 SC	327	#define HPSA_INTR_ON 1
edd16368 SC	328	#define HPSA_INTR_OFF 0
b66cc250 MM	329
	330	/*
	331	* Inbound Post Queue offsets for IO Accelerator Mode 2
	332	*/
	333	#define IOACCEL2_INBOUND_POSTQ_32 0x48
	334	#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
	335	#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
	336
edd16368 SC	337	/*
	338	Send the command to the hardware
	339	*/
	340	static void SA5_submit_command(struct ctlr_info *h,
	341	struct CommandList *c)
	342	{
edd16368	343	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
fec62c36	344	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
edd16368 SC	345	}
edd16368 SC	346
b3a52e79 SC	347	static void SA5_submit_command_no_read(struct ctlr_info *h,
	348	struct CommandList *c)
	349	{
	350	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	351	}
	352
c349775e ST	353	static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	354	struct CommandList *c)
	355	{
c349775e ST	356	if (c->cmd_type == CMD_IOACCEL2)
	357	writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	358	else
	359	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e ST	360	}
c349775e ST	361
edd16368 SC	362	/*
	363	* This card is the opposite of the other cards.
	364	* 0 turns interrupts on...
	365	* 0x08 turns them off...
	366	*/
	367	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	368	{
	369	if (val) { /* Turn interrupts on */
	370	h->interrupts_enabled = 1;
	371	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	372	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	373	} else { /* Turn them off */
	374	h->interrupts_enabled = 0;
	375	writel(SA5_INTR_OFF,
	376	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	377	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	378	}
edd16368 SC	379	}
303932fd DB	380
	381	static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
	382	{
	383	if (val) { /* turn on interrupts */
	384	h->interrupts_enabled = 1;
	385	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	386	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	387	} else {
	388	h->interrupts_enabled = 0;
	389	writel(SA5_PERF_INTR_OFF,
	390	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	391	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	392	}
	393	}
	394
254f796b	395	static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
303932fd	396	{
072b0518	397	struct reply_queue_buffer *rq = &h->reply_queue[q];
0cbf768e	398	unsigned long register_value = FIFO_EMPTY;
303932fd	399
303932fd DB	400	/* msi auto clears the interrupt pending bit. */
303932fd DB	401	if (!(h->msi_vector \|\| h->msix_vector)) {
2c17d2da SC	402	/* flush the controller write of the reply queue by reading
	403	* outbound doorbell status register.
	404	*/
	405	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	406	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	407	/* Do a read in order to flush the write to the controller
	408	* (as per spec.)
	409	*/
	410	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	411	}
	412
254f796b MG	413	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
	414	register_value = rq->head[rq->current_entry];
	415	rq->current_entry++;
0cbf768e	416	atomic_dec(&h->commands_outstanding);
303932fd DB	417	} else {
	418	register_value = FIFO_EMPTY;
	419	}
	420	/* Check for wraparound */
254f796b MG	421	if (rq->current_entry == h->max_commands) {
	422	rq->current_entry = 0;
	423	rq->wraparound ^= 1;
303932fd	424	}
303932fd DB	425	return register_value;
	426	}
	427
edd16368 SC	428	/*
	429	* Returns true if fifo is full.
	430	*
	431	*/
	432	static unsigned long SA5_fifo_full(struct ctlr_info *h)
	433	{
0cbf768e	434	return atomic_read(&h->commands_outstanding) >= h->max_commands;
edd16368 SC	435	}
	436	/*
	437	* returns value read from hardware.
	438	* returns FIFO_EMPTY if there is nothing to read
	439	*/
254f796b MG	440	static unsigned long SA5_completed(struct ctlr_info *h,
254f796b MG	441	__attribute__((unused)) u8 q)
edd16368 SC	442	{
	443	unsigned long register_value
	444	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	445
0cbf768e SC	446	if (register_value != FIFO_EMPTY)
0cbf768e SC	447	atomic_dec(&h->commands_outstanding);
edd16368 SC	448
	449	#ifdef HPSA_DEBUG
	450	if (register_value != FIFO_EMPTY)
84ca0be2	451	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	452	register_value);
edd16368 SC	453	else
f79cfec6	454	dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
edd16368 SC	455	#endif
	456
	457	return register_value;
	458	}
	459	/*
	460	* Returns true if an interrupt is pending..
	461	*/
900c5440	462	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	463	{
	464	unsigned long register_value =
	465	readl(h->vaddr + SA5_INTR_STATUS);
900c5440	466	return register_value & SA5_INTR_PENDING;
edd16368 SC	467	}
edd16368 SC	468
303932fd DB	469	static bool SA5_performant_intr_pending(struct ctlr_info *h)
	470	{
	471	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	472
	473	if (!register_value)
	474	return false;
	475
	476	if (h->msi_vector \|\| h->msix_vector)
	477	return true;
	478
	479	/* Read outbound doorbell to flush */
	480	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	481	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	482	}
edd16368	483
e1f7de0c MG	484	#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
	485
	486	static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
	487	{
	488	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	489
	490	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
	491	true : false;
	492	}
	493
	494	#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
	495	#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
	496	#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
	497	#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
	498
283b4a9b	499	static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
e1f7de0c MG	500	{
e1f7de0c MG	501	u64 register_value;
072b0518	502	struct reply_queue_buffer *rq = &h->reply_queue[q];
e1f7de0c MG	503
	504	BUG_ON(q >= h->nreply_queues);
	505
	506	register_value = rq->head[rq->current_entry];
	507	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
	508	rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
	509	if (++rq->current_entry == rq->size)
	510	rq->current_entry = 0;
283b4a9b SC	511	/*
	512	* @todo
	513	*
	514	* Don't really need to write the new index after each command,
	515	* but with current driver design this is easiest.
	516	*/
	517	wmb();
	518	writel((q << 24) \| rq->current_entry, h->vaddr +
	519	IOACCEL_MODE1_CONSUMER_INDEX);
0cbf768e	520	atomic_dec(&h->commands_outstanding);
e1f7de0c MG	521	}
	522	return (unsigned long) register_value;
	523	}
	524
edd16368 SC	525	static struct access_method SA5_access = {
	526	SA5_submit_command,
	527	SA5_intr_mask,
	528	SA5_fifo_full,
	529	SA5_intr_pending,
	530	SA5_completed,
	531	};
	532
e1f7de0c MG	533	static struct access_method SA5_ioaccel_mode1_access = {
	534	SA5_submit_command,
	535	SA5_performant_intr_mask,
	536	SA5_fifo_full,
	537	SA5_ioaccel_mode1_intr_pending,
	538	SA5_ioaccel_mode1_completed,
	539	};
	540
c349775e ST	541	static struct access_method SA5_ioaccel_mode2_access = {
	542	SA5_submit_command_ioaccel2,
	543	SA5_performant_intr_mask,
	544	SA5_fifo_full,
	545	SA5_performant_intr_pending,
	546	SA5_performant_completed,
	547	};
	548
303932fd DB	549	static struct access_method SA5_performant_access = {
	550	SA5_submit_command,
	551	SA5_performant_intr_mask,
	552	SA5_fifo_full,
	553	SA5_performant_intr_pending,
	554	SA5_performant_completed,
	555	};
	556
b3a52e79 SC	557	static struct access_method SA5_performant_access_no_read = {
	558	SA5_submit_command_no_read,
	559	SA5_performant_intr_mask,
	560	SA5_fifo_full,
	561	SA5_performant_intr_pending,
	562	SA5_performant_completed,
	563	};
	564
edd16368	565	struct board_type {
01a02ffc	566	u32 board_id;
edd16368 SC	567	char *product_name;
	568	struct access_method *access;
	569	};
	570
edd16368 SC	571	#endif /* HPSA_H */
edd16368 SC	572