[mirror_ubuntu-artful-kernel.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	unsigned long (*fifo_full)(struct ctlr_info *h);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char revision[4];      /* bytes 32-35 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
};

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	char	firm_ver[4]; /* Firmware version */
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int	major;
	int 	max_commands;
	int	commands_outstanding;
	int 	max_outstanding; /* Debug */
	int	usage_count;  /* number of opens all all minor devices */
#	define DOORBELL_INT	0
#	define PERF_MODE_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[4];
	unsigned int msix_vector;
	unsigned int msi_vector;
	struct access_method access;

	/* queue and queue Info */
	struct hlist_head reqQ;
	struct hlist_head cmpQ;
	unsigned int Qdepth;
	unsigned int maxQsinceinit;
	unsigned int maxSG;
	spinlock_t lock;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			nr_allocs;
	int			nr_frees;
	int			busy_initializing;
	int			busy_scanning;
	struct mutex		busy_shutting_down;
	struct list_head	scan_list;
	struct completion	scan_wait;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
};
#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_BUS_RESET_MSG 2
#define HPSA_HOST_RESET_MSG 3
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0
/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	dev_dbg(&h->pdev->dev, "Sending %x\n", c->busaddr);
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	h->commands_outstanding++;
	if (h->commands_outstanding > h->max_outstanding)
		h->max_outstanding = h->commands_outstanding;
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}
/*
 *  Returns true if fifo is full.
 *
 */
static unsigned long SA5_fifo_full(struct ctlr_info *h)
{
	if (h->commands_outstanding >= h->max_commands)
		return 1;
	else
		return 0;

}
/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);

	if (register_value != FIFO_EMPTY)
		h->commands_outstanding--;

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
	return register_value & SA5_INTR_PENDING;
}


static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_fifo_full,
	SA5_intr_pending,
	SA5_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};


/* end of old hpsa_scsi.h file */

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
	35	unsigned long (fifo_full)(struct ctlr_info h);
900c5440	36	bool (intr_pending)(struct ctlr_info h);
edd16368 SC	37	unsigned long (command_completed)(struct ctlr_info h);
	38	};
	39
	40	struct hpsa_scsi_dev_t {
	41	int devtype;
	42	int bus, target, lun; /* as presented to the OS */
	43	unsigned char scsi3addr[8]; /* as presented to the HW */
	44	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	45	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	46	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	47	unsigned char model[16]; /* bytes 16-31 of inquiry data */
	48	unsigned char revision[4]; /* bytes 32-35 of inquiry data */
	49	unsigned char raid_level; /* from inquiry page 0xC1 */
	50	};
	51
	52	struct ctlr_info {
	53	int ctlr;
	54	char devname[8];
	55	char *product_name;
	56	char firm_ver[4]; /* Firmware version */
	57	struct pci_dev *pdev;
01a02ffc	58	u32 board_id;
edd16368 SC	59	void __iomem *vaddr;
	60	unsigned long paddr;
	61	int nr_cmds; /* Number of commands allowed on this controller */
	62	struct CfgTable __iomem *cfgtable;
	63	int interrupts_enabled;
	64	int major;
	65	int max_commands;
	66	int commands_outstanding;
	67	int max_outstanding; /* Debug */
	68	int usage_count; /* number of opens all all minor devices */
	69	# define DOORBELL_INT 0
	70	# define PERF_MODE_INT 1
	71	# define SIMPLE_MODE_INT 2
	72	# define MEMQ_MODE_INT 3
	73	unsigned int intr[4];
	74	unsigned int msix_vector;
	75	unsigned int msi_vector;
	76	struct access_method access;
	77
	78	/* queue and queue Info */
	79	struct hlist_head reqQ;
	80	struct hlist_head cmpQ;
	81	unsigned int Qdepth;
	82	unsigned int maxQsinceinit;
	83	unsigned int maxSG;
	84	spinlock_t lock;
	85
	86	/* pointers to command and error info pool */
	87	struct CommandList *cmd_pool;
	88	dma_addr_t cmd_pool_dhandle;
	89	struct ErrorInfo *errinfo_pool;
	90	dma_addr_t errinfo_pool_dhandle;
	91	unsigned long *cmd_pool_bits;
	92	int nr_allocs;
	93	int nr_frees;
	94	int busy_initializing;
	95	int busy_scanning;
	96	struct mutex busy_shutting_down;
	97	struct list_head scan_list;
	98	struct completion scan_wait;
	99
	100	struct Scsi_Host *scsi_host;
	101	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	102	int ndevices; /* number of used elements in .dev[] array. */
	103	#define HPSA_MAX_SCSI_DEVS_PER_HBA 256
	104	struct hpsa_scsi_dev_t *dev[HPSA_MAX_SCSI_DEVS_PER_HBA];
	105	};
	106	#define HPSA_ABORT_MSG 0
	107	#define HPSA_DEVICE_RESET_MSG 1
	108	#define HPSA_BUS_RESET_MSG 2
	109	#define HPSA_HOST_RESET_MSG 3
	110	#define HPSA_MSG_SEND_RETRY_LIMIT 10
	111	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS 1000
	112
	113	/* Maximum time in seconds driver will wait for command completions
	114	* when polling before giving up.
	115	*/
	116	#define HPSA_MAX_POLL_TIME_SECS (20)
	117
	118	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	119	* how many times to retry TEST UNIT READY on a device
	120	* while waiting for it to become ready before giving up.
	121	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	122	* between sending TURs while waiting for a device
123	* to become ready.
124	*/
125	#define HPSA_TUR_RETRY_LIMIT (20)
126	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
127
128	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
129	* to become ready, in seconds, before giving up on it.
130	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
131	* between polling the board to see if it is ready, in
132	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
133	* HPSA_BOARD_READY_ITERATIONS are derived from those.
134	*/
135	#define HPSA_BOARD_READY_WAIT_SECS (120)
136	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
137	#define HPSA_BOARD_READY_POLL_INTERVAL \
138	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
139	#define HPSA_BOARD_READY_ITERATIONS \
140	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
141	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
142	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
143	#define HPSA_POST_RESET_NOOP_RETRIES (12)
144
145	/* Defining the diffent access_menthods */
146	/*
147	* Memory mapped FIFO interface (SMART 53xx cards)
148	*/
149	#define SA5_DOORBELL 0x20
150	#define SA5_REQUEST_PORT_OFFSET 0x40
151	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
152	#define SA5_REPLY_PORT_OFFSET 0x44
153	#define SA5_INTR_STATUS 0x30
154	#define SA5_SCRATCHPAD_OFFSET 0xB0
155
156	#define SA5_CTCFG_OFFSET 0xB4
157	#define SA5_CTMEM_OFFSET 0xB8
158
159	#define SA5_INTR_OFF 0x08
160	#define SA5B_INTR_OFF 0x04
161	#define SA5_INTR_PENDING 0x08
162	#define SA5B_INTR_PENDING 0x04
163	#define FIFO_EMPTY 0xffffffff
164	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
165
166	#define HPSA_ERROR_BIT 0x02
edd16368 SC	167
	168	#define HPSA_INTR_ON 1
	169	#define HPSA_INTR_OFF 0
	170	/*
	171	Send the command to the hardware
	172	*/
	173	static void SA5_submit_command(struct ctlr_info *h,
	174	struct CommandList *c)
	175	{
84ca0be2	176	dev_dbg(&h->pdev->dev, "Sending %x\n", c->busaddr);
edd16368 SC	177	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	178	h->commands_outstanding++;
	179	if (h->commands_outstanding > h->max_outstanding)
	180	h->max_outstanding = h->commands_outstanding;
	181	}
	182
	183	/*
	184	* This card is the opposite of the other cards.
	185	* 0 turns interrupts on...
	186	* 0x08 turns them off...
	187	*/
	188	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	189	{
	190	if (val) { /* Turn interrupts on */
	191	h->interrupts_enabled = 1;
	192	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	193	} else { /* Turn them off */
	194	h->interrupts_enabled = 0;
	195	writel(SA5_INTR_OFF,
	196	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	197	}
	198	}
	199	/*
	200	* Returns true if fifo is full.
	201	*
	202	*/
	203	static unsigned long SA5_fifo_full(struct ctlr_info *h)
	204	{
	205	if (h->commands_outstanding >= h->max_commands)
	206	return 1;
	207	else
	208	return 0;
	209
	210	}
	211	/*
	212	* returns value read from hardware.
	213	* returns FIFO_EMPTY if there is nothing to read
	214	*/
	215	static unsigned long SA5_completed(struct ctlr_info *h)
	216	{
	217	unsigned long register_value
	218	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	219
	220	if (register_value != FIFO_EMPTY)
	221	h->commands_outstanding--;
	222
	223	#ifdef HPSA_DEBUG
	224	if (register_value != FIFO_EMPTY)
84ca0be2	225	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	226	register_value);
edd16368 SC	227	else
84ca0be2	228	dev_dbg(&h->pdev->dev, "hpsa: FIFO Empty read\n");
edd16368 SC	229	#endif
	230
	231	return register_value;
	232	}
	233	/*
	234	* Returns true if an interrupt is pending..
	235	*/
900c5440	236	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	237	{
	238	unsigned long register_value =
	239	readl(h->vaddr + SA5_INTR_STATUS);
84ca0be2	240	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
900c5440	241	return register_value & SA5_INTR_PENDING;
edd16368 SC	242	}
	243
	244
	245	static struct access_method SA5_access = {
	246	SA5_submit_command,
	247	SA5_intr_mask,
	248	SA5_fifo_full,
	249	SA5_intr_pending,
	250	SA5_completed,
	251	};
	252
	253	struct board_type {
01a02ffc	254	u32 board_id;
edd16368 SC	255	char *product_name;
	256	struct access_method *access;
	257	};
	258
	259
	260	/* end of old hpsa_scsi.h file */
	261
	262	#endif /* HPSA_H */
	263