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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
94c7bc31 | 3 | * Copyright 2016 Microsemi Corporation |
1358f6dc DB |
4 | * Copyright 2014-2015 PMC-Sierra, Inc. |
5 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
14 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
15 | * | |
94c7bc31 | 16 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
edd16368 SC |
17 | * |
18 | */ | |
19 | #ifndef HPSA_CMD_H | |
20 | #define HPSA_CMD_H | |
21 | ||
22 | /* general boundary defintions */ | |
23 | #define SENSEINFOBYTES 32 /* may vary between hbas */ | |
d66ae08b | 24 | #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ |
33a2ffce | 25 | #define HPSA_SG_CHAIN 0x80000000 |
e1d9cbfa | 26 | #define HPSA_SG_LAST 0x40000000 |
edd16368 SC |
27 | #define MAXREPLYQS 256 |
28 | ||
29 | /* Command Status value */ | |
30 | #define CMD_SUCCESS 0x0000 | |
31 | #define CMD_TARGET_STATUS 0x0001 | |
32 | #define CMD_DATA_UNDERRUN 0x0002 | |
33 | #define CMD_DATA_OVERRUN 0x0003 | |
34 | #define CMD_INVALID 0x0004 | |
35 | #define CMD_PROTOCOL_ERR 0x0005 | |
36 | #define CMD_HARDWARE_ERR 0x0006 | |
37 | #define CMD_CONNECTION_LOST 0x0007 | |
38 | #define CMD_ABORTED 0x0008 | |
39 | #define CMD_ABORT_FAILED 0x0009 | |
40 | #define CMD_UNSOLICITED_ABORT 0x000A | |
41 | #define CMD_TIMEOUT 0x000B | |
42 | #define CMD_UNABORTABLE 0x000C | |
9437ac43 | 43 | #define CMD_TMF_STATUS 0x000D |
283b4a9b | 44 | #define CMD_IOACCEL_DISABLED 0x000E |
25163bd5 WS |
45 | #define CMD_CTLR_LOCKUP 0xffff |
46 | /* Note: CMD_CTLR_LOCKUP is not a value defined by the CISS spec | |
47 | * it is a value defined by the driver that commands can be marked | |
48 | * with when a controller lockup has been detected by the driver | |
49 | */ | |
283b4a9b | 50 | |
9437ac43 SC |
51 | /* TMF function status values */ |
52 | #define CISS_TMF_COMPLETE 0x00 | |
53 | #define CISS_TMF_INVALID_FRAME 0x02 | |
54 | #define CISS_TMF_NOT_SUPPORTED 0x04 | |
55 | #define CISS_TMF_FAILED 0x05 | |
56 | #define CISS_TMF_SUCCESS 0x08 | |
57 | #define CISS_TMF_WRONG_LUN 0x09 | |
58 | #define CISS_TMF_OVERLAPPED_TAG 0x0a | |
edd16368 SC |
59 | |
60 | /* Unit Attentions ASC's as defined for the MSA2012sa */ | |
61 | #define POWER_OR_RESET 0x29 | |
62 | #define STATE_CHANGED 0x2a | |
63 | #define UNIT_ATTENTION_CLEARED 0x2f | |
64 | #define LUN_FAILED 0x3e | |
65 | #define REPORT_LUNS_CHANGED 0x3f | |
66 | ||
67 | /* Unit Attentions ASCQ's as defined for the MSA2012sa */ | |
68 | ||
69 | /* These ASCQ's defined for ASC = POWER_OR_RESET */ | |
70 | #define POWER_ON_RESET 0x00 | |
71 | #define POWER_ON_REBOOT 0x01 | |
72 | #define SCSI_BUS_RESET 0x02 | |
73 | #define MSA_TARGET_RESET 0x03 | |
74 | #define CONTROLLER_FAILOVER 0x04 | |
75 | #define TRANSCEIVER_SE 0x05 | |
76 | #define TRANSCEIVER_LVD 0x06 | |
77 | ||
78 | /* These ASCQ's defined for ASC = STATE_CHANGED */ | |
79 | #define RESERVATION_PREEMPTED 0x03 | |
80 | #define ASYM_ACCESS_CHANGED 0x06 | |
81 | #define LUN_CAPACITY_CHANGED 0x09 | |
82 | ||
83 | /* transfer direction */ | |
84 | #define XFER_NONE 0x00 | |
85 | #define XFER_WRITE 0x01 | |
86 | #define XFER_READ 0x02 | |
87 | #define XFER_RSVD 0x03 | |
88 | ||
89 | /* task attribute */ | |
90 | #define ATTR_UNTAGGED 0x00 | |
91 | #define ATTR_SIMPLE 0x04 | |
92 | #define ATTR_HEADOFQUEUE 0x05 | |
93 | #define ATTR_ORDERED 0x06 | |
94 | #define ATTR_ACA 0x07 | |
95 | ||
96 | /* cdb type */ | |
54b6e9e9 ST |
97 | #define TYPE_CMD 0x00 |
98 | #define TYPE_MSG 0x01 | |
99 | #define TYPE_IOACCEL2_CMD 0x81 /* 0x81 is not used by hardware */ | |
edd16368 | 100 | |
75167d2c SC |
101 | /* Message Types */ |
102 | #define HPSA_TASK_MANAGEMENT 0x00 | |
103 | #define HPSA_RESET 0x01 | |
104 | #define HPSA_SCAN 0x02 | |
105 | #define HPSA_NOOP 0x03 | |
106 | ||
107 | #define HPSA_CTLR_RESET_TYPE 0x00 | |
108 | #define HPSA_BUS_RESET_TYPE 0x01 | |
109 | #define HPSA_TARGET_RESET_TYPE 0x03 | |
110 | #define HPSA_LUN_RESET_TYPE 0x04 | |
111 | #define HPSA_NEXUS_RESET_TYPE 0x05 | |
112 | ||
113 | /* Task Management Functions */ | |
114 | #define HPSA_TMF_ABORT_TASK 0x00 | |
115 | #define HPSA_TMF_ABORT_TASK_SET 0x01 | |
116 | #define HPSA_TMF_CLEAR_ACA 0x02 | |
117 | #define HPSA_TMF_CLEAR_TASK_SET 0x03 | |
118 | #define HPSA_TMF_QUERY_TASK 0x04 | |
119 | #define HPSA_TMF_QUERY_TASK_SET 0x05 | |
120 | #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 | |
121 | ||
122 | ||
123 | ||
edd16368 SC |
124 | /* config space register offsets */ |
125 | #define CFG_VENDORID 0x00 | |
126 | #define CFG_DEVICEID 0x02 | |
127 | #define CFG_I2OBAR 0x10 | |
128 | #define CFG_MEM1BAR 0x14 | |
129 | ||
130 | /* i2o space register offsets */ | |
131 | #define I2O_IBDB_SET 0x20 | |
132 | #define I2O_IBDB_CLEAR 0x70 | |
133 | #define I2O_INT_STATUS 0x30 | |
134 | #define I2O_INT_MASK 0x34 | |
135 | #define I2O_IBPOST_Q 0x40 | |
136 | #define I2O_OBPOST_Q 0x44 | |
137 | #define I2O_DMA1_CFG 0x214 | |
138 | ||
139 | /* Configuration Table */ | |
140 | #define CFGTBL_ChangeReq 0x00000001l | |
141 | #define CFGTBL_AccCmds 0x00000001l | |
1df8552a | 142 | #define DOORBELL_CTLR_RESET 0x00000004l |
cf0b08d0 | 143 | #define DOORBELL_CTLR_RESET2 0x00000020l |
76438d08 | 144 | #define DOORBELL_CLEAR_EVENTS 0x00000040l |
b9b08cad | 145 | #define DOORBELL_GENERATE_CHKPT 0x00000080l |
edd16368 SC |
146 | |
147 | #define CFGTBL_Trans_Simple 0x00000002l | |
303932fd | 148 | #define CFGTBL_Trans_Performant 0x00000004l |
e1f7de0c | 149 | #define CFGTBL_Trans_io_accel1 0x00000080l |
1f7cee8c | 150 | #define CFGTBL_Trans_io_accel2 0x00000100l |
960a30e7 | 151 | #define CFGTBL_Trans_use_short_tags 0x20000000l |
254f796b | 152 | #define CFGTBL_Trans_enable_directed_msix (1 << 30) |
edd16368 SC |
153 | |
154 | #define CFGTBL_BusType_Ultra2 0x00000001l | |
155 | #define CFGTBL_BusType_Ultra3 0x00000002l | |
156 | #define CFGTBL_BusType_Fibre1G 0x00000100l | |
157 | #define CFGTBL_BusType_Fibre2G 0x00000200l | |
283b4a9b SC |
158 | |
159 | /* VPD Inquiry types */ | |
85b29008 | 160 | #define HPSA_INQUIRY_FAILED 0x02 |
1b70150a | 161 | #define HPSA_VPD_SUPPORTED_PAGES 0x00 |
8383278d | 162 | #define HPSA_VPD_LV_DEVICE_ID 0x83 |
283b4a9b SC |
163 | #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 |
164 | #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 | |
9846590e | 165 | #define HPSA_VPD_LV_STATUS 0xC3 |
1b70150a | 166 | #define HPSA_VPD_HEADER_SZ 4 |
283b4a9b | 167 | |
9846590e | 168 | /* Logical volume states */ |
67955ba3 | 169 | #define HPSA_VPD_LV_STATUS_UNSUPPORTED 0xff |
9846590e | 170 | #define HPSA_LV_OK 0x0 |
85b29008 | 171 | #define HPSA_LV_FAILED 0x01 |
5ca01204 | 172 | #define HPSA_LV_NOT_AVAILABLE 0x0b |
9846590e SC |
173 | #define HPSA_LV_UNDERGOING_ERASE 0x0F |
174 | #define HPSA_LV_UNDERGOING_RPI 0x12 | |
175 | #define HPSA_LV_PENDING_RPI 0x13 | |
176 | #define HPSA_LV_ENCRYPTED_NO_KEY 0x14 | |
177 | #define HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER 0x15 | |
178 | #define HPSA_LV_UNDERGOING_ENCRYPTION 0x16 | |
179 | #define HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING 0x17 | |
180 | #define HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER 0x18 | |
181 | #define HPSA_LV_PENDING_ENCRYPTION 0x19 | |
182 | #define HPSA_LV_PENDING_ENCRYPTION_REKEYING 0x1A | |
183 | ||
edd16368 | 184 | struct vals32 { |
01a02ffc SC |
185 | u32 lower; |
186 | u32 upper; | |
edd16368 SC |
187 | }; |
188 | ||
189 | union u64bit { | |
190 | struct vals32 val32; | |
01a02ffc | 191 | u64 val; |
edd16368 SC |
192 | }; |
193 | ||
194 | /* FIXME this is a per controller value (barf!) */ | |
b7ec021f | 195 | #define HPSA_MAX_LUN 1024 |
edd16368 | 196 | #define HPSA_MAX_PHYS_LUN 1024 |
aca4a520 | 197 | #define MAX_EXT_TARGETS 32 |
b7ec021f | 198 | #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ |
aca4a520 | 199 | MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ |
edd16368 SC |
200 | |
201 | /* SCSI-3 Commands */ | |
202 | #pragma pack(1) | |
203 | ||
204 | #define HPSA_INQUIRY 0x12 | |
205 | struct InquiryData { | |
01a02ffc | 206 | u8 data_byte[36]; |
edd16368 SC |
207 | }; |
208 | ||
209 | #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ | |
210 | #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ | |
a93aa1fe | 211 | #define HPSA_REPORT_PHYS_EXTENDED 0x02 |
283b4a9b SC |
212 | #define HPSA_CISS_READ 0xc0 /* CISS Read */ |
213 | #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ | |
214 | ||
215 | #define RAID_MAP_MAX_ENTRIES 256 | |
216 | ||
217 | struct raid_map_disk_data { | |
218 | u32 ioaccel_handle; /**< Handle to access this disk via the | |
219 | * I/O accelerator */ | |
220 | u8 xor_mult[2]; /**< XOR multipliers for this position, | |
221 | * valid for data disks only */ | |
222 | u8 reserved[2]; | |
223 | }; | |
224 | ||
225 | struct raid_map_data { | |
2b08b3e9 DB |
226 | __le32 structure_size; /* Size of entire structure in bytes */ |
227 | __le32 volume_blk_size; /* bytes / block in the volume */ | |
228 | __le64 volume_blk_cnt; /* logical blocks on the volume */ | |
283b4a9b SC |
229 | u8 phys_blk_shift; /* Shift factor to convert between |
230 | * units of logical blocks and physical | |
231 | * disk blocks */ | |
232 | u8 parity_rotation_shift; /* Shift factor to convert between units | |
233 | * of logical stripes and physical | |
234 | * stripes */ | |
2b08b3e9 DB |
235 | __le16 strip_size; /* blocks used on each disk / stripe */ |
236 | __le64 disk_starting_blk; /* First disk block used in volume */ | |
237 | __le64 disk_blk_cnt; /* disk blocks used by volume / disk */ | |
238 | __le16 data_disks_per_row; /* data disk entries / row in the map */ | |
239 | __le16 metadata_disks_per_row;/* mirror/parity disk entries / row | |
283b4a9b | 240 | * in the map */ |
2b08b3e9 DB |
241 | __le16 row_cnt; /* rows in each layout map */ |
242 | __le16 layout_map_count; /* layout maps (1 map per mirror/parity | |
283b4a9b | 243 | * group) */ |
2b08b3e9 | 244 | __le16 flags; /* Bit 0 set if encryption enabled */ |
dd0e19f3 | 245 | #define RAID_MAP_FLAG_ENCRYPT_ON 0x01 |
2b08b3e9 | 246 | __le16 dekindex; /* Data encryption key index. */ |
dd0e19f3 | 247 | u8 reserved[16]; |
283b4a9b SC |
248 | struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; |
249 | }; | |
250 | ||
edd16368 | 251 | struct ReportLUNdata { |
01a02ffc | 252 | u8 LUNListLength[4]; |
283b4a9b SC |
253 | u8 extended_response_flag; |
254 | u8 reserved[3]; | |
01a02ffc | 255 | u8 LUN[HPSA_MAX_LUN][8]; |
edd16368 SC |
256 | }; |
257 | ||
d5b5d964 SC |
258 | struct ext_report_lun_entry { |
259 | u8 lunid[8]; | |
41ce4c35 | 260 | #define MASKED_DEVICE(x) ((x)[3] & 0xC0) |
03383736 DB |
261 | #define GET_BMIC_BUS(lunid) ((lunid)[7] & 0x3F) |
262 | #define GET_BMIC_LEVEL_TWO_TARGET(lunid) ((lunid)[6]) | |
263 | #define GET_BMIC_DRIVE_NUMBER(lunid) (((GET_BMIC_BUS((lunid)) - 1) << 8) + \ | |
264 | GET_BMIC_LEVEL_TWO_TARGET((lunid))) | |
d5b5d964 SC |
265 | u8 wwid[8]; |
266 | u8 device_type; | |
267 | u8 device_flags; | |
268 | u8 lun_count; /* multi-lun device, how many luns */ | |
269 | u8 redundant_paths; | |
270 | u32 ioaccel_handle; /* ioaccel1 only uses lower 16 bits */ | |
271 | }; | |
272 | ||
edd16368 | 273 | struct ReportExtendedLUNdata { |
01a02ffc SC |
274 | u8 LUNListLength[4]; |
275 | u8 extended_response_flag; | |
276 | u8 reserved[3]; | |
92084715 | 277 | struct ext_report_lun_entry LUN[HPSA_MAX_PHYS_LUN]; |
edd16368 SC |
278 | }; |
279 | ||
280 | struct SenseSubsystem_info { | |
01a02ffc SC |
281 | u8 reserved[36]; |
282 | u8 portname[8]; | |
283 | u8 reserved1[1108]; | |
edd16368 SC |
284 | }; |
285 | ||
edd16368 SC |
286 | /* BMIC commands */ |
287 | #define BMIC_READ 0x26 | |
288 | #define BMIC_WRITE 0x27 | |
289 | #define BMIC_CACHE_FLUSH 0xc2 | |
290 | #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ | |
e85c5974 | 291 | #define BMIC_FLASH_FIRMWARE 0xF7 |
316b221a | 292 | #define BMIC_SENSE_CONTROLLER_PARAMETERS 0x64 |
03383736 | 293 | #define BMIC_IDENTIFY_PHYSICAL_DEVICE 0x15 |
66749d0d | 294 | #define BMIC_IDENTIFY_CONTROLLER 0x11 |
c2adae44 ST |
295 | #define BMIC_SET_DIAG_OPTIONS 0xF4 |
296 | #define BMIC_SENSE_DIAG_OPTIONS 0xF5 | |
d9e52fb1 | 297 | #define HPSA_DIAG_OPTS_DISABLE_RLD_CACHING 0x80000000 |
d04e62b9 | 298 | #define BMIC_SENSE_SUBSYSTEM_INFORMATION 0x66 |
cca8f13b | 299 | #define BMIC_SENSE_STORAGE_BOX_PARAMS 0x65 |
edd16368 SC |
300 | |
301 | /* Command List Structure */ | |
302 | union SCSI3Addr { | |
303 | struct { | |
01a02ffc SC |
304 | u8 Dev; |
305 | u8 Bus:6; | |
306 | u8 Mode:2; /* b00 */ | |
edd16368 SC |
307 | } PeripDev; |
308 | struct { | |
01a02ffc SC |
309 | u8 DevLSB; |
310 | u8 DevMSB:6; | |
311 | u8 Mode:2; /* b01 */ | |
edd16368 SC |
312 | } LogDev; |
313 | struct { | |
01a02ffc SC |
314 | u8 Dev:5; |
315 | u8 Bus:3; | |
316 | u8 Targ:6; | |
317 | u8 Mode:2; /* b10 */ | |
edd16368 SC |
318 | } LogUnit; |
319 | }; | |
320 | ||
321 | struct PhysDevAddr { | |
01a02ffc SC |
322 | u32 TargetId:24; |
323 | u32 Bus:6; | |
324 | u32 Mode:2; | |
edd16368 SC |
325 | /* 2 level target device addr */ |
326 | union SCSI3Addr Target[2]; | |
327 | }; | |
328 | ||
329 | struct LogDevAddr { | |
01a02ffc SC |
330 | u32 VolId:30; |
331 | u32 Mode:2; | |
332 | u8 reserved[4]; | |
edd16368 SC |
333 | }; |
334 | ||
335 | union LUNAddr { | |
01a02ffc | 336 | u8 LunAddrBytes[8]; |
edd16368 SC |
337 | union SCSI3Addr SCSI3Lun[4]; |
338 | struct PhysDevAddr PhysDev; | |
339 | struct LogDevAddr LogDev; | |
340 | }; | |
341 | ||
342 | struct CommandListHeader { | |
01a02ffc SC |
343 | u8 ReplyQueue; |
344 | u8 SGList; | |
2b08b3e9 DB |
345 | __le16 SGTotal; |
346 | __le64 tag; | |
edd16368 SC |
347 | union LUNAddr LUN; |
348 | }; | |
349 | ||
350 | struct RequestBlock { | |
01a02ffc | 351 | u8 CDBLen; |
a505b86f SC |
352 | /* |
353 | * type_attr_dir: | |
354 | * type: low 3 bits | |
355 | * attr: middle 3 bits | |
356 | * dir: high 2 bits | |
357 | */ | |
358 | u8 type_attr_dir; | |
359 | #define TYPE_ATTR_DIR(t, a, d) ((((d) & 0x03) << 6) |\ | |
360 | (((a) & 0x07) << 3) |\ | |
361 | ((t) & 0x07)) | |
362 | #define GET_TYPE(tad) ((tad) & 0x07) | |
363 | #define GET_ATTR(tad) (((tad) >> 3) & 0x07) | |
364 | #define GET_DIR(tad) (((tad) >> 6) & 0x03) | |
01a02ffc SC |
365 | u16 Timeout; |
366 | u8 CDB[16]; | |
edd16368 SC |
367 | }; |
368 | ||
369 | struct ErrDescriptor { | |
2b08b3e9 DB |
370 | __le64 Addr; |
371 | __le32 Len; | |
edd16368 SC |
372 | }; |
373 | ||
374 | struct SGDescriptor { | |
2b08b3e9 DB |
375 | __le64 Addr; |
376 | __le32 Len; | |
377 | __le32 Ext; | |
edd16368 SC |
378 | }; |
379 | ||
380 | union MoreErrInfo { | |
381 | struct { | |
01a02ffc SC |
382 | u8 Reserved[3]; |
383 | u8 Type; | |
384 | u32 ErrorInfo; | |
edd16368 SC |
385 | } Common_Info; |
386 | struct { | |
01a02ffc SC |
387 | u8 Reserved[2]; |
388 | u8 offense_size; /* size of offending entry */ | |
389 | u8 offense_num; /* byte # of offense 0-base */ | |
390 | u32 offense_value; | |
edd16368 SC |
391 | } Invalid_Cmd; |
392 | }; | |
393 | struct ErrorInfo { | |
01a02ffc SC |
394 | u8 ScsiStatus; |
395 | u8 SenseLen; | |
396 | u16 CommandStatus; | |
397 | u32 ResidualCnt; | |
edd16368 | 398 | union MoreErrInfo MoreErrInfo; |
01a02ffc | 399 | u8 SenseInfo[SENSEINFOBYTES]; |
edd16368 SC |
400 | }; |
401 | /* Command types */ | |
402 | #define CMD_IOCTL_PEND 0x01 | |
403 | #define CMD_SCSI 0x03 | |
e1f7de0c | 404 | #define CMD_IOACCEL1 0x04 |
b66cc250 | 405 | #define CMD_IOACCEL2 0x05 |
8be986cc | 406 | #define IOACCEL2_TMF 0x06 |
edd16368 | 407 | |
f2405db8 | 408 | #define DIRECT_LOOKUP_SHIFT 4 |
d896f3f3 | 409 | #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) |
303932fd DB |
410 | |
411 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 412 | struct ctlr_info; /* defined in hpsa.h */ |
f2405db8 DB |
413 | /* The size of this structure needs to be divisible by 128 |
414 | * on all architectures. The low 4 bits of the addresses | |
303932fd DB |
415 | * are used as follows: |
416 | * | |
417 | * bit 0: to device, used to indicate "performant mode" command | |
418 | * from device, indidcates error status. | |
419 | * bit 1-3: to device, indicates block fetch table entry for | |
420 | * reducing DMA in fetching commands from host memory. | |
edd16368 | 421 | */ |
303932fd | 422 | |
35d697c4 | 423 | #define COMMANDLIST_ALIGNMENT 128 |
edd16368 SC |
424 | struct CommandList { |
425 | struct CommandListHeader Header; | |
426 | struct RequestBlock Request; | |
427 | struct ErrDescriptor ErrDesc; | |
d66ae08b | 428 | struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; |
edd16368 | 429 | /* information associated with the command */ |
01a02ffc | 430 | u32 busaddr; /* physical addr of this record */ |
edd16368 SC |
431 | struct ErrorInfo *err_info; /* pointer to the allocated mem */ |
432 | struct ctlr_info *h; | |
433 | int cmd_type; | |
434 | long cmdindex; | |
edd16368 | 435 | struct completion *waiting; |
7fa3030c | 436 | struct scsi_cmnd *scsi_cmd; |
080ef1cc | 437 | struct work_struct work; |
03383736 DB |
438 | |
439 | /* | |
440 | * For commands using either of the two "ioaccel" paths to | |
441 | * bypass the RAID stack and go directly to the physical disk | |
442 | * phys_disk is a pointer to the hpsa_scsi_dev_t to which the | |
443 | * i/o is destined. We need to store that here because the command | |
444 | * may potentially encounter TASK SET FULL and need to be resubmitted | |
445 | * For "normal" i/o's not using the "ioaccel" paths, phys_disk is | |
446 | * not used. | |
447 | */ | |
448 | struct hpsa_scsi_dev_t *phys_disk; | |
a58e7e53 WS |
449 | |
450 | int abort_pending; | |
c5dfd106 | 451 | struct hpsa_scsi_dev_t *device; |
360c73bd | 452 | atomic_t refcount; /* Must be last to avoid memset in hpsa_cmd_init() */ |
35d697c4 | 453 | } __aligned(COMMANDLIST_ALIGNMENT); |
edd16368 | 454 | |
e1f7de0c MG |
455 | /* Max S/G elements in I/O accelerator command */ |
456 | #define IOACCEL1_MAXSGENTRIES 24 | |
b66cc250 | 457 | #define IOACCEL2_MAXSGENTRIES 28 |
e1f7de0c MG |
458 | |
459 | /* | |
460 | * Structure for I/O accelerator (mode 1) commands. | |
461 | * Note that this structure must be 128-byte aligned in size. | |
462 | */ | |
35d697c4 | 463 | #define IOACCEL1_COMMANDLIST_ALIGNMENT 128 |
e1f7de0c | 464 | struct io_accel1_cmd { |
2b08b3e9 | 465 | __le16 dev_handle; /* 0x00 - 0x01 */ |
e1f7de0c MG |
466 | u8 reserved1; /* 0x02 */ |
467 | u8 function; /* 0x03 */ | |
468 | u8 reserved2[8]; /* 0x04 - 0x0B */ | |
469 | u32 err_info; /* 0x0C - 0x0F */ | |
470 | u8 reserved3[2]; /* 0x10 - 0x11 */ | |
471 | u8 err_info_len; /* 0x12 */ | |
472 | u8 reserved4; /* 0x13 */ | |
473 | u8 sgl_offset; /* 0x14 */ | |
474 | u8 reserved5[7]; /* 0x15 - 0x1B */ | |
2b08b3e9 | 475 | __le32 transfer_len; /* 0x1C - 0x1F */ |
e1f7de0c | 476 | u8 reserved6[4]; /* 0x20 - 0x23 */ |
2b08b3e9 | 477 | __le16 io_flags; /* 0x24 - 0x25 */ |
e1f7de0c MG |
478 | u8 reserved7[14]; /* 0x26 - 0x33 */ |
479 | u8 LUN[8]; /* 0x34 - 0x3B */ | |
2b08b3e9 | 480 | __le32 control; /* 0x3C - 0x3F */ |
e1f7de0c MG |
481 | u8 CDB[16]; /* 0x40 - 0x4F */ |
482 | u8 reserved8[16]; /* 0x50 - 0x5F */ | |
2b08b3e9 DB |
483 | __le16 host_context_flags; /* 0x60 - 0x61 */ |
484 | __le16 timeout_sec; /* 0x62 - 0x63 */ | |
e1f7de0c MG |
485 | u8 ReplyQueue; /* 0x64 */ |
486 | u8 reserved9[3]; /* 0x65 - 0x67 */ | |
2b08b3e9 DB |
487 | __le64 tag; /* 0x68 - 0x6F */ |
488 | __le64 host_addr; /* 0x70 - 0x77 */ | |
e1f7de0c MG |
489 | u8 CISS_LUN[8]; /* 0x78 - 0x7F */ |
490 | struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; | |
35d697c4 | 491 | } __aligned(IOACCEL1_COMMANDLIST_ALIGNMENT); |
e1f7de0c MG |
492 | |
493 | #define IOACCEL1_FUNCTION_SCSIIO 0x00 | |
494 | #define IOACCEL1_SGLOFFSET 32 | |
495 | ||
496 | #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 | |
497 | #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F | |
498 | #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 | |
499 | ||
500 | #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 | |
501 | #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 | |
502 | #define IOACCEL1_CONTROL_DATA_IN 0x02000000 | |
503 | #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 | |
504 | #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 | |
505 | #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 | |
506 | #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 | |
507 | #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 | |
508 | #define IOACCEL1_CONTROL_ACA 0x00000400 | |
509 | ||
510 | #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 | |
511 | ||
512 | #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 | |
513 | ||
b66cc250 | 514 | struct ioaccel2_sg_element { |
2b08b3e9 DB |
515 | __le64 address; |
516 | __le32 length; | |
b66cc250 MM |
517 | u8 reserved[3]; |
518 | u8 chain_indicator; | |
519 | #define IOACCEL2_CHAIN 0x80 | |
625d7d35 | 520 | #define IOACCEL2_LAST_SG 0x40 |
b66cc250 MM |
521 | }; |
522 | ||
523 | /* | |
524 | * SCSI Response Format structure for IO Accelerator Mode 2 | |
525 | */ | |
526 | struct io_accel2_scsi_response { | |
527 | u8 IU_type; | |
528 | #define IOACCEL2_IU_TYPE_SRF 0x60 | |
529 | u8 reserved1[3]; | |
530 | u8 req_id[4]; /* request identifier */ | |
531 | u8 reserved2[4]; | |
532 | u8 serv_response; /* service response */ | |
533 | #define IOACCEL2_SERV_RESPONSE_COMPLETE 0x000 | |
534 | #define IOACCEL2_SERV_RESPONSE_FAILURE 0x001 | |
535 | #define IOACCEL2_SERV_RESPONSE_TMF_COMPLETE 0x002 | |
536 | #define IOACCEL2_SERV_RESPONSE_TMF_SUCCESS 0x003 | |
537 | #define IOACCEL2_SERV_RESPONSE_TMF_REJECTED 0x004 | |
538 | #define IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN 0x005 | |
539 | u8 status; /* status */ | |
540 | #define IOACCEL2_STATUS_SR_TASK_COMP_GOOD 0x00 | |
541 | #define IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND 0x02 | |
542 | #define IOACCEL2_STATUS_SR_TASK_COMP_BUSY 0x08 | |
543 | #define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18 | |
544 | #define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28 | |
545 | #define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40 | |
c349775e | 546 | #define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E |
c40820d5 JH |
547 | #define IOACCEL2_STATUS_SR_IO_ERROR 0x01 |
548 | #define IOACCEL2_STATUS_SR_IO_ABORTED 0x02 | |
549 | #define IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE 0x03 | |
550 | #define IOACCEL2_STATUS_SR_INVALID_DEVICE 0x04 | |
551 | #define IOACCEL2_STATUS_SR_UNDERRUN 0x51 | |
552 | #define IOACCEL2_STATUS_SR_OVERRUN 0x75 | |
b66cc250 MM |
553 | u8 data_present; /* low 2 bits */ |
554 | #define IOACCEL2_NO_DATAPRESENT 0x000 | |
555 | #define IOACCEL2_RESPONSE_DATAPRESENT 0x001 | |
556 | #define IOACCEL2_SENSE_DATA_PRESENT 0x002 | |
557 | #define IOACCEL2_RESERVED 0x003 | |
558 | u8 sense_data_len; /* sense/response data length */ | |
559 | u8 resid_cnt[4]; /* residual count */ | |
560 | u8 sense_data_buff[32]; /* sense/response data buffer */ | |
561 | }; | |
562 | ||
b66cc250 MM |
563 | /* |
564 | * Structure for I/O accelerator (mode 2 or m2) commands. | |
565 | * Note that this structure must be 128-byte aligned in size. | |
566 | */ | |
35d697c4 | 567 | #define IOACCEL2_COMMANDLIST_ALIGNMENT 128 |
b66cc250 MM |
568 | struct io_accel2_cmd { |
569 | u8 IU_type; /* IU Type */ | |
dd0e19f3 ST |
570 | u8 direction; /* direction, memtype, and encryption */ |
571 | #define IOACCEL2_DIRECTION_MASK 0x03 /* bits 0,1: direction */ | |
572 | #define IOACCEL2_DIRECTION_MEMTYPE_MASK 0x04 /* bit 2: memtype source/dest */ | |
573 | /* 0b=PCIe, 1b=DDR */ | |
574 | #define IOACCEL2_DIRECTION_ENCRYPT_MASK 0x08 /* bit 3: encryption flag */ | |
575 | /* 0=off, 1=on */ | |
b66cc250 MM |
576 | u8 reply_queue; /* Reply Queue ID */ |
577 | u8 reserved1; /* Reserved */ | |
2b08b3e9 DB |
578 | __le32 scsi_nexus; /* Device Handle */ |
579 | __le32 Tag; /* cciss tag, lower 4 bytes only */ | |
580 | __le32 tweak_lower; /* Encryption tweak, lower 4 bytes */ | |
b66cc250 MM |
581 | u8 cdb[16]; /* SCSI Command Descriptor Block */ |
582 | u8 cciss_lun[8]; /* 8 byte SCSI address */ | |
2b08b3e9 | 583 | __le32 data_len; /* Total bytes to transfer */ |
b66cc250 MM |
584 | u8 cmd_priority_task_attr; /* priority and task attrs */ |
585 | #define IOACCEL2_PRIORITY_MASK 0x78 | |
586 | #define IOACCEL2_ATTR_MASK 0x07 | |
587 | u8 sg_count; /* Number of sg elements */ | |
2b08b3e9 DB |
588 | __le16 dekindex; /* Data encryption key index */ |
589 | __le64 err_ptr; /* Error Pointer */ | |
590 | __le32 err_len; /* Error Length*/ | |
591 | __le32 tweak_upper; /* Encryption tweak, upper 4 bytes */ | |
b66cc250 MM |
592 | struct ioaccel2_sg_element sg[IOACCEL2_MAXSGENTRIES]; |
593 | struct io_accel2_scsi_response error_data; | |
35d697c4 | 594 | } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); |
b66cc250 MM |
595 | |
596 | /* | |
597 | * defines for Mode 2 command struct | |
598 | * FIXME: this can't be all I need mfm | |
599 | */ | |
600 | #define IOACCEL2_IU_TYPE 0x40 | |
54b6e9e9 | 601 | #define IOACCEL2_IU_TMF_TYPE 0x41 |
b66cc250 MM |
602 | #define IOACCEL2_DIR_NO_DATA 0x00 |
603 | #define IOACCEL2_DIR_DATA_IN 0x01 | |
604 | #define IOACCEL2_DIR_DATA_OUT 0x02 | |
8be986cc | 605 | #define IOACCEL2_TMF_ABORT 0x01 |
b66cc250 MM |
606 | /* |
607 | * SCSI Task Management Request format for Accelerator Mode 2 | |
608 | */ | |
609 | struct hpsa_tmf_struct { | |
610 | u8 iu_type; /* Information Unit Type */ | |
611 | u8 reply_queue; /* Reply Queue ID */ | |
612 | u8 tmf; /* Task Management Function */ | |
613 | u8 reserved1; /* byte 3 Reserved */ | |
8be986cc | 614 | __le32 it_nexus; /* SCSI I-T Nexus */ |
b66cc250 | 615 | u8 lun_id[8]; /* LUN ID for TMF request */ |
2b08b3e9 DB |
616 | __le64 tag; /* cciss tag associated w/ request */ |
617 | __le64 abort_tag; /* cciss tag of SCSI cmd or TMF to abort */ | |
618 | __le64 error_ptr; /* Error Pointer */ | |
619 | __le32 error_len; /* Error Length */ | |
8be986cc | 620 | } __aligned(IOACCEL2_COMMANDLIST_ALIGNMENT); |
b66cc250 | 621 | |
edd16368 SC |
622 | /* Configuration Table Structure */ |
623 | struct HostWrite { | |
2b08b3e9 DB |
624 | __le32 TransportRequest; |
625 | __le32 command_pool_addr_hi; | |
626 | __le32 CoalIntDelay; | |
627 | __le32 CoalIntCount; | |
edd16368 SC |
628 | }; |
629 | ||
303932fd DB |
630 | #define SIMPLE_MODE 0x02 |
631 | #define PERFORMANT_MODE 0x04 | |
632 | #define MEMQ_MODE 0x08 | |
e1f7de0c | 633 | #define IOACCEL_MODE_1 0x80 |
303932fd | 634 | |
283b4a9b SC |
635 | #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 |
636 | ||
edd16368 | 637 | struct CfgTable { |
2b08b3e9 DB |
638 | u8 Signature[4]; |
639 | __le32 SpecValence; | |
640 | __le32 TransportSupport; | |
641 | __le32 TransportActive; | |
642 | struct HostWrite HostWrite; | |
643 | __le32 CmdsOutMax; | |
644 | __le32 BusTypes; | |
645 | __le32 TransMethodOffset; | |
646 | u8 ServerName[16]; | |
647 | __le32 HeartBeat; | |
648 | __le32 driver_support; | |
649 | #define ENABLE_SCSI_PREFETCH 0x100 | |
650 | #define ENABLE_UNIT_ATTN 0x01 | |
651 | __le32 MaxScatterGatherElements; | |
652 | __le32 MaxLogicalUnits; | |
653 | __le32 MaxPhysicalDevices; | |
654 | __le32 MaxPhysicalDrivesPerLogicalUnit; | |
655 | __le32 MaxPerformantModeCommands; | |
656 | __le32 MaxBlockFetch; | |
657 | __le32 PowerConservationSupport; | |
658 | __le32 PowerConservationEnable; | |
659 | __le32 TMFSupportFlags; | |
75167d2c SC |
660 | u8 TMFTagMask[8]; |
661 | u8 reserved[0x78 - 0x70]; | |
2b08b3e9 DB |
662 | __le32 misc_fw_support; /* offset 0x78 */ |
663 | #define MISC_FW_DOORBELL_RESET 0x02 | |
664 | #define MISC_FW_DOORBELL_RESET2 0x010 | |
665 | #define MISC_FW_RAID_OFFLOAD_BASIC 0x020 | |
666 | #define MISC_FW_EVENT_NOTIFY 0x080 | |
580ada3c | 667 | u8 driver_version[32]; |
2b08b3e9 DB |
668 | __le32 max_cached_write_size; |
669 | u8 driver_scratchpad[16]; | |
670 | __le32 max_error_info_length; | |
671 | __le32 io_accel_max_embedded_sg_count; | |
672 | __le32 io_accel_request_size_offset; | |
673 | __le32 event_notify; | |
674 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE (1 << 30) | |
675 | #define HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE (1 << 31) | |
676 | __le32 clear_event_notify; | |
303932fd DB |
677 | }; |
678 | ||
679 | #define NUM_BLOCKFETCH_ENTRIES 8 | |
680 | struct TransTable_struct { | |
2b08b3e9 DB |
681 | __le32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; |
682 | __le32 RepQSize; | |
683 | __le32 RepQCount; | |
684 | __le32 RepQCtrAddrLow32; | |
685 | __le32 RepQCtrAddrHigh32; | |
f89439bc | 686 | #define MAX_REPLY_QUEUES 64 |
254f796b | 687 | struct vals32 RepQAddr[MAX_REPLY_QUEUES]; |
edd16368 SC |
688 | }; |
689 | ||
690 | struct hpsa_pci_info { | |
691 | unsigned char bus; | |
692 | unsigned char dev_fn; | |
693 | unsigned short domain; | |
01a02ffc | 694 | u32 board_id; |
edd16368 SC |
695 | }; |
696 | ||
66749d0d ST |
697 | struct bmic_identify_controller { |
698 | u8 configured_logical_drive_count; /* offset 0 */ | |
699 | u8 pad1[153]; | |
700 | __le16 extended_logical_unit_count; /* offset 154 */ | |
701 | u8 pad2[136]; | |
702 | u8 controller_mode; /* offset 292 */ | |
703 | u8 pad3[32]; | |
704 | }; | |
705 | ||
706 | ||
03383736 DB |
707 | struct bmic_identify_physical_device { |
708 | u8 scsi_bus; /* SCSI Bus number on controller */ | |
709 | u8 scsi_id; /* SCSI ID on this bus */ | |
710 | __le16 block_size; /* sector size in bytes */ | |
711 | __le32 total_blocks; /* number for sectors on drive */ | |
712 | __le32 reserved_blocks; /* controller reserved (RIS) */ | |
713 | u8 model[40]; /* Physical Drive Model */ | |
714 | u8 serial_number[40]; /* Drive Serial Number */ | |
715 | u8 firmware_revision[8]; /* drive firmware revision */ | |
716 | u8 scsi_inquiry_bits; /* inquiry byte 7 bits */ | |
717 | u8 compaq_drive_stamp; /* 0 means drive not stamped */ | |
718 | u8 last_failure_reason; | |
719 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_LOAD_CONFIG 0x01 | |
720 | #define BMIC_LAST_FAILURE_ERROR_ERASING_RIS 0x02 | |
721 | #define BMIC_LAST_FAILURE_ERROR_SAVING_RIS 0x03 | |
722 | #define BMIC_LAST_FAILURE_FAIL_DRIVE_COMMAND 0x04 | |
723 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED 0x05 | |
724 | #define BMIC_LAST_FAILURE_MARK_BAD_FAILED_IN_FINISH_REMAP 0x06 | |
725 | #define BMIC_LAST_FAILURE_TIMEOUT 0x07 | |
726 | #define BMIC_LAST_FAILURE_AUTOSENSE_FAILED 0x08 | |
727 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_1 0x09 | |
728 | #define BMIC_LAST_FAILURE_MEDIUM_ERROR_2 0x0a | |
729 | #define BMIC_LAST_FAILURE_NOT_READY_BAD_SENSE 0x0b | |
730 | #define BMIC_LAST_FAILURE_NOT_READY 0x0c | |
731 | #define BMIC_LAST_FAILURE_HARDWARE_ERROR 0x0d | |
732 | #define BMIC_LAST_FAILURE_ABORTED_COMMAND 0x0e | |
733 | #define BMIC_LAST_FAILURE_WRITE_PROTECTED 0x0f | |
734 | #define BMIC_LAST_FAILURE_SPIN_UP_FAILURE_IN_RECOVER 0x10 | |
735 | #define BMIC_LAST_FAILURE_REBUILD_WRITE_ERROR 0x11 | |
736 | #define BMIC_LAST_FAILURE_TOO_SMALL_IN_HOT_PLUG 0x12 | |
737 | #define BMIC_LAST_FAILURE_BUS_RESET_RECOVERY_ABORTED 0x13 | |
738 | #define BMIC_LAST_FAILURE_REMOVED_IN_HOT_PLUG 0x14 | |
739 | #define BMIC_LAST_FAILURE_INIT_REQUEST_SENSE_FAILED 0x15 | |
740 | #define BMIC_LAST_FAILURE_INIT_START_UNIT_FAILED 0x16 | |
741 | #define BMIC_LAST_FAILURE_INQUIRY_FAILED 0x17 | |
742 | #define BMIC_LAST_FAILURE_NON_DISK_DEVICE 0x18 | |
743 | #define BMIC_LAST_FAILURE_READ_CAPACITY_FAILED 0x19 | |
744 | #define BMIC_LAST_FAILURE_INVALID_BLOCK_SIZE 0x1a | |
745 | #define BMIC_LAST_FAILURE_HOT_PLUG_REQUEST_SENSE_FAILED 0x1b | |
746 | #define BMIC_LAST_FAILURE_HOT_PLUG_START_UNIT_FAILED 0x1c | |
747 | #define BMIC_LAST_FAILURE_WRITE_ERROR_AFTER_REMAP 0x1d | |
748 | #define BMIC_LAST_FAILURE_INIT_RESET_RECOVERY_ABORTED 0x1e | |
749 | #define BMIC_LAST_FAILURE_DEFERRED_WRITE_ERROR 0x1f | |
750 | #define BMIC_LAST_FAILURE_MISSING_IN_SAVE_RIS 0x20 | |
751 | #define BMIC_LAST_FAILURE_WRONG_REPLACE 0x21 | |
752 | #define BMIC_LAST_FAILURE_GDP_VPD_INQUIRY_FAILED 0x22 | |
753 | #define BMIC_LAST_FAILURE_GDP_MODE_SENSE_FAILED 0x23 | |
754 | #define BMIC_LAST_FAILURE_DRIVE_NOT_IN_48BIT_MODE 0x24 | |
755 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_HOT_PLUG 0x25 | |
756 | #define BMIC_LAST_FAILURE_DRIVE_TYPE_MIX_IN_LOAD_CFG 0x26 | |
757 | #define BMIC_LAST_FAILURE_PROTOCOL_ADAPTER_FAILED 0x27 | |
758 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_EMPTY 0x28 | |
759 | #define BMIC_LAST_FAILURE_FAULTY_ID_BAY_OCCUPIED 0x29 | |
760 | #define BMIC_LAST_FAILURE_FAULTY_ID_INVALID_BAY 0x2a | |
761 | #define BMIC_LAST_FAILURE_WRITE_RETRIES_FAILED 0x2b | |
762 | ||
763 | #define BMIC_LAST_FAILURE_SMART_ERROR_REPORTED 0x37 | |
764 | #define BMIC_LAST_FAILURE_PHY_RESET_FAILED 0x38 | |
765 | #define BMIC_LAST_FAILURE_ONLY_ONE_CTLR_CAN_SEE_DRIVE 0x40 | |
766 | #define BMIC_LAST_FAILURE_KC_VOLUME_FAILED 0x41 | |
767 | #define BMIC_LAST_FAILURE_UNEXPECTED_REPLACEMENT 0x42 | |
768 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE 0x80 | |
769 | #define BMIC_LAST_FAILURE_OFFLINE_TOO_SMALL 0x81 | |
770 | #define BMIC_LAST_FAILURE_OFFLINE_DRIVE_TYPE_MIX 0x82 | |
771 | #define BMIC_LAST_FAILURE_OFFLINE_ERASE_COMPLETE 0x83 | |
772 | ||
773 | u8 flags; | |
774 | u8 more_flags; | |
775 | u8 scsi_lun; /* SCSI LUN for phys drive */ | |
776 | u8 yet_more_flags; | |
777 | u8 even_more_flags; | |
778 | __le32 spi_speed_rules;/* SPI Speed data:Ultra disable diagnose */ | |
779 | u8 phys_connector[2]; /* connector number on controller */ | |
780 | u8 phys_box_on_bus; /* phys enclosure this drive resides */ | |
781 | u8 phys_bay_in_box; /* phys drv bay this drive resides */ | |
782 | __le32 rpm; /* Drive rotational speed in rpm */ | |
783 | u8 device_type; /* type of drive */ | |
4e188184 BAS |
784 | #define BMIC_DEVICE_TYPE_CONTROLLER 0x07 |
785 | ||
03383736 DB |
786 | u8 sata_version; /* only valid when drive_type is SATA */ |
787 | __le64 big_total_block_count; | |
788 | __le64 ris_starting_lba; | |
789 | __le32 ris_size; | |
790 | u8 wwid[20]; | |
791 | u8 controller_phy_map[32]; | |
792 | __le16 phy_count; | |
793 | u8 phy_connected_dev_type[256]; | |
794 | u8 phy_to_drive_bay_num[256]; | |
795 | __le16 phy_to_attached_dev_index[256]; | |
796 | u8 box_index; | |
797 | u8 reserved; | |
798 | __le16 extra_physical_drive_flags; | |
799 | #define BMIC_PHYS_DRIVE_SUPPORTS_GAS_GAUGE(idphydrv) \ | |
800 | (idphydrv->extra_physical_drive_flags & (1 << 10)) | |
801 | u8 negotiated_link_rate[256]; | |
802 | u8 phy_to_phy_map[256]; | |
803 | u8 redundant_path_present_map; | |
804 | u8 redundant_path_failure_map; | |
805 | u8 active_path_number; | |
806 | __le16 alternate_paths_phys_connector[8]; | |
807 | u8 alternate_paths_phys_box_on_port[8]; | |
808 | u8 multi_lun_device_lun_count; | |
809 | u8 minimum_good_fw_revision[8]; | |
810 | u8 unique_inquiry_bytes[20]; | |
811 | u8 current_temperature_degreesC; | |
812 | u8 temperature_threshold_degreesC; | |
813 | u8 max_temperature_degreesC; | |
814 | u8 logical_blocks_per_phys_block_exp; /* phyblocksize = 512*2^exp */ | |
815 | __le16 current_queue_depth_limit; | |
046b263f | 816 | u8 reserved_switch_stuff[60]; |
03383736 DB |
817 | __le16 power_on_hours; /* valid only if gas gauge supported */ |
818 | __le16 percent_endurance_used; /* valid only if gas gauge supported. */ | |
819 | #define BMIC_PHYS_DRIVE_SSD_WEAROUT(idphydrv) \ | |
820 | ((idphydrv->percent_endurance_used & 0x80) || \ | |
821 | (idphydrv->percent_endurance_used > 10000)) | |
822 | u8 drive_authentication; | |
823 | #define BMIC_PHYS_DRIVE_AUTHENTICATED(idphydrv) \ | |
824 | (idphydrv->drive_authentication == 0x80) | |
825 | u8 smart_carrier_authentication; | |
826 | #define BMIC_SMART_CARRIER_AUTHENTICATION_SUPPORTED(idphydrv) \ | |
827 | (idphydrv->smart_carrier_authentication != 0x0) | |
828 | #define BMIC_SMART_CARRIER_AUTHENTICATED(idphydrv) \ | |
829 | (idphydrv->smart_carrier_authentication == 0x01) | |
830 | u8 smart_carrier_app_fw_version; | |
831 | u8 smart_carrier_bootloader_fw_version; | |
046b263f DB |
832 | u8 sanitize_support_flags; |
833 | u8 drive_key_flags; | |
03383736 DB |
834 | u8 encryption_key_name[64]; |
835 | __le32 misc_drive_flags; | |
836 | __le16 dek_index; | |
046b263f DB |
837 | __le16 hba_drive_encryption_flags; |
838 | __le16 max_overwrite_time; | |
839 | __le16 max_block_erase_time; | |
840 | __le16 max_crypto_erase_time; | |
841 | u8 device_connector_info[5]; | |
842 | u8 connector_name[8][8]; | |
843 | u8 page_83_id[16]; | |
844 | u8 max_link_rate[256]; | |
845 | u8 neg_phys_link_rate[256]; | |
846 | u8 box_conn_name[8]; | |
847 | } __attribute((aligned(512))); | |
03383736 | 848 | |
d04e62b9 KB |
849 | struct bmic_sense_subsystem_info { |
850 | u8 primary_slot_number; | |
851 | u8 reserved[3]; | |
852 | u8 chasis_serial_number[32]; | |
853 | u8 primary_world_wide_id[8]; | |
854 | u8 primary_array_serial_number[32]; /* NULL terminated */ | |
855 | u8 primary_cache_serial_number[32]; /* NULL terminated */ | |
856 | u8 reserved_2[8]; | |
857 | u8 secondary_array_serial_number[32]; | |
858 | u8 secondary_cache_serial_number[32]; | |
859 | u8 pad[332]; | |
860 | }; | |
861 | ||
cca8f13b DB |
862 | struct bmic_sense_storage_box_params { |
863 | u8 reserved[36]; | |
864 | u8 inquiry_valid; | |
865 | u8 reserved_1[68]; | |
866 | u8 phys_box_on_port; | |
867 | u8 reserved_2[22]; | |
868 | u16 connection_info; | |
869 | u8 reserver_3[84]; | |
870 | u8 phys_connector[2]; | |
871 | u8 reserved_4[296]; | |
872 | }; | |
873 | ||
edd16368 SC |
874 | #pragma pack() |
875 | #endif /* HPSA_CMD_H */ |