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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
3 | * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | #ifndef HPSA_CMD_H | |
22 | #define HPSA_CMD_H | |
23 | ||
24 | /* general boundary defintions */ | |
25 | #define SENSEINFOBYTES 32 /* may vary between hbas */ | |
d66ae08b | 26 | #define SG_ENTRIES_IN_CMD 32 /* Max SG entries excluding chain blocks */ |
33a2ffce | 27 | #define HPSA_SG_CHAIN 0x80000000 |
e1d9cbfa | 28 | #define HPSA_SG_LAST 0x40000000 |
edd16368 SC |
29 | #define MAXREPLYQS 256 |
30 | ||
31 | /* Command Status value */ | |
32 | #define CMD_SUCCESS 0x0000 | |
33 | #define CMD_TARGET_STATUS 0x0001 | |
34 | #define CMD_DATA_UNDERRUN 0x0002 | |
35 | #define CMD_DATA_OVERRUN 0x0003 | |
36 | #define CMD_INVALID 0x0004 | |
37 | #define CMD_PROTOCOL_ERR 0x0005 | |
38 | #define CMD_HARDWARE_ERR 0x0006 | |
39 | #define CMD_CONNECTION_LOST 0x0007 | |
40 | #define CMD_ABORTED 0x0008 | |
41 | #define CMD_ABORT_FAILED 0x0009 | |
42 | #define CMD_UNSOLICITED_ABORT 0x000A | |
43 | #define CMD_TIMEOUT 0x000B | |
44 | #define CMD_UNABORTABLE 0x000C | |
283b4a9b SC |
45 | #define CMD_IOACCEL_DISABLED 0x000E |
46 | ||
edd16368 SC |
47 | |
48 | /* Unit Attentions ASC's as defined for the MSA2012sa */ | |
49 | #define POWER_OR_RESET 0x29 | |
50 | #define STATE_CHANGED 0x2a | |
51 | #define UNIT_ATTENTION_CLEARED 0x2f | |
52 | #define LUN_FAILED 0x3e | |
53 | #define REPORT_LUNS_CHANGED 0x3f | |
54 | ||
55 | /* Unit Attentions ASCQ's as defined for the MSA2012sa */ | |
56 | ||
57 | /* These ASCQ's defined for ASC = POWER_OR_RESET */ | |
58 | #define POWER_ON_RESET 0x00 | |
59 | #define POWER_ON_REBOOT 0x01 | |
60 | #define SCSI_BUS_RESET 0x02 | |
61 | #define MSA_TARGET_RESET 0x03 | |
62 | #define CONTROLLER_FAILOVER 0x04 | |
63 | #define TRANSCEIVER_SE 0x05 | |
64 | #define TRANSCEIVER_LVD 0x06 | |
65 | ||
66 | /* These ASCQ's defined for ASC = STATE_CHANGED */ | |
67 | #define RESERVATION_PREEMPTED 0x03 | |
68 | #define ASYM_ACCESS_CHANGED 0x06 | |
69 | #define LUN_CAPACITY_CHANGED 0x09 | |
70 | ||
71 | /* transfer direction */ | |
72 | #define XFER_NONE 0x00 | |
73 | #define XFER_WRITE 0x01 | |
74 | #define XFER_READ 0x02 | |
75 | #define XFER_RSVD 0x03 | |
76 | ||
77 | /* task attribute */ | |
78 | #define ATTR_UNTAGGED 0x00 | |
79 | #define ATTR_SIMPLE 0x04 | |
80 | #define ATTR_HEADOFQUEUE 0x05 | |
81 | #define ATTR_ORDERED 0x06 | |
82 | #define ATTR_ACA 0x07 | |
83 | ||
84 | /* cdb type */ | |
85 | #define TYPE_CMD 0x00 | |
86 | #define TYPE_MSG 0x01 | |
87 | ||
75167d2c SC |
88 | /* Message Types */ |
89 | #define HPSA_TASK_MANAGEMENT 0x00 | |
90 | #define HPSA_RESET 0x01 | |
91 | #define HPSA_SCAN 0x02 | |
92 | #define HPSA_NOOP 0x03 | |
93 | ||
94 | #define HPSA_CTLR_RESET_TYPE 0x00 | |
95 | #define HPSA_BUS_RESET_TYPE 0x01 | |
96 | #define HPSA_TARGET_RESET_TYPE 0x03 | |
97 | #define HPSA_LUN_RESET_TYPE 0x04 | |
98 | #define HPSA_NEXUS_RESET_TYPE 0x05 | |
99 | ||
100 | /* Task Management Functions */ | |
101 | #define HPSA_TMF_ABORT_TASK 0x00 | |
102 | #define HPSA_TMF_ABORT_TASK_SET 0x01 | |
103 | #define HPSA_TMF_CLEAR_ACA 0x02 | |
104 | #define HPSA_TMF_CLEAR_TASK_SET 0x03 | |
105 | #define HPSA_TMF_QUERY_TASK 0x04 | |
106 | #define HPSA_TMF_QUERY_TASK_SET 0x05 | |
107 | #define HPSA_TMF_QUERY_ASYNCEVENT 0x06 | |
108 | ||
109 | ||
110 | ||
edd16368 SC |
111 | /* config space register offsets */ |
112 | #define CFG_VENDORID 0x00 | |
113 | #define CFG_DEVICEID 0x02 | |
114 | #define CFG_I2OBAR 0x10 | |
115 | #define CFG_MEM1BAR 0x14 | |
116 | ||
117 | /* i2o space register offsets */ | |
118 | #define I2O_IBDB_SET 0x20 | |
119 | #define I2O_IBDB_CLEAR 0x70 | |
120 | #define I2O_INT_STATUS 0x30 | |
121 | #define I2O_INT_MASK 0x34 | |
122 | #define I2O_IBPOST_Q 0x40 | |
123 | #define I2O_OBPOST_Q 0x44 | |
124 | #define I2O_DMA1_CFG 0x214 | |
125 | ||
126 | /* Configuration Table */ | |
127 | #define CFGTBL_ChangeReq 0x00000001l | |
128 | #define CFGTBL_AccCmds 0x00000001l | |
1df8552a | 129 | #define DOORBELL_CTLR_RESET 0x00000004l |
cf0b08d0 | 130 | #define DOORBELL_CTLR_RESET2 0x00000020l |
edd16368 SC |
131 | |
132 | #define CFGTBL_Trans_Simple 0x00000002l | |
303932fd | 133 | #define CFGTBL_Trans_Performant 0x00000004l |
e1f7de0c | 134 | #define CFGTBL_Trans_io_accel1 0x00000080l |
960a30e7 | 135 | #define CFGTBL_Trans_use_short_tags 0x20000000l |
254f796b | 136 | #define CFGTBL_Trans_enable_directed_msix (1 << 30) |
edd16368 SC |
137 | |
138 | #define CFGTBL_BusType_Ultra2 0x00000001l | |
139 | #define CFGTBL_BusType_Ultra3 0x00000002l | |
140 | #define CFGTBL_BusType_Fibre1G 0x00000100l | |
141 | #define CFGTBL_BusType_Fibre2G 0x00000200l | |
283b4a9b SC |
142 | |
143 | /* VPD Inquiry types */ | |
144 | #define HPSA_VPD_LV_DEVICE_GEOMETRY 0xC1 | |
145 | #define HPSA_VPD_LV_IOACCEL_STATUS 0xC2 | |
146 | ||
edd16368 | 147 | struct vals32 { |
01a02ffc SC |
148 | u32 lower; |
149 | u32 upper; | |
edd16368 SC |
150 | }; |
151 | ||
152 | union u64bit { | |
153 | struct vals32 val32; | |
01a02ffc | 154 | u64 val; |
edd16368 SC |
155 | }; |
156 | ||
157 | /* FIXME this is a per controller value (barf!) */ | |
b7ec021f | 158 | #define HPSA_MAX_LUN 1024 |
edd16368 | 159 | #define HPSA_MAX_PHYS_LUN 1024 |
aca4a520 | 160 | #define MAX_EXT_TARGETS 32 |
b7ec021f | 161 | #define HPSA_MAX_DEVICES (HPSA_MAX_PHYS_LUN + HPSA_MAX_LUN + \ |
aca4a520 | 162 | MAX_EXT_TARGETS + 1) /* + 1 is for the controller itself */ |
edd16368 SC |
163 | |
164 | /* SCSI-3 Commands */ | |
165 | #pragma pack(1) | |
166 | ||
167 | #define HPSA_INQUIRY 0x12 | |
168 | struct InquiryData { | |
01a02ffc | 169 | u8 data_byte[36]; |
edd16368 SC |
170 | }; |
171 | ||
172 | #define HPSA_REPORT_LOG 0xc2 /* Report Logical LUNs */ | |
173 | #define HPSA_REPORT_PHYS 0xc3 /* Report Physical LUNs */ | |
a93aa1fe | 174 | #define HPSA_REPORT_PHYS_EXTENDED 0x02 |
283b4a9b SC |
175 | #define HPSA_CISS_READ 0xc0 /* CISS Read */ |
176 | #define HPSA_GET_RAID_MAP 0xc8 /* CISS Get RAID Layout Map */ | |
177 | ||
178 | #define RAID_MAP_MAX_ENTRIES 256 | |
179 | ||
180 | struct raid_map_disk_data { | |
181 | u32 ioaccel_handle; /**< Handle to access this disk via the | |
182 | * I/O accelerator */ | |
183 | u8 xor_mult[2]; /**< XOR multipliers for this position, | |
184 | * valid for data disks only */ | |
185 | u8 reserved[2]; | |
186 | }; | |
187 | ||
188 | struct raid_map_data { | |
189 | u32 structure_size; /* Size of entire structure in bytes */ | |
190 | u32 volume_blk_size; /* bytes / block in the volume */ | |
191 | u64 volume_blk_cnt; /* logical blocks on the volume */ | |
192 | u8 phys_blk_shift; /* Shift factor to convert between | |
193 | * units of logical blocks and physical | |
194 | * disk blocks */ | |
195 | u8 parity_rotation_shift; /* Shift factor to convert between units | |
196 | * of logical stripes and physical | |
197 | * stripes */ | |
198 | u16 strip_size; /* blocks used on each disk / stripe */ | |
199 | u64 disk_starting_blk; /* First disk block used in volume */ | |
200 | u64 disk_blk_cnt; /* disk blocks used by volume / disk */ | |
201 | u16 data_disks_per_row; /* data disk entries / row in the map */ | |
202 | u16 metadata_disks_per_row; /* mirror/parity disk entries / row | |
203 | * in the map */ | |
204 | u16 row_cnt; /* rows in each layout map */ | |
205 | u16 layout_map_count; /* layout maps (1 map per mirror/parity | |
206 | * group) */ | |
207 | u8 reserved[20]; | |
208 | struct raid_map_disk_data data[RAID_MAP_MAX_ENTRIES]; | |
209 | }; | |
210 | ||
edd16368 | 211 | struct ReportLUNdata { |
01a02ffc | 212 | u8 LUNListLength[4]; |
283b4a9b SC |
213 | u8 extended_response_flag; |
214 | u8 reserved[3]; | |
01a02ffc | 215 | u8 LUN[HPSA_MAX_LUN][8]; |
edd16368 SC |
216 | }; |
217 | ||
218 | struct ReportExtendedLUNdata { | |
01a02ffc SC |
219 | u8 LUNListLength[4]; |
220 | u8 extended_response_flag; | |
221 | u8 reserved[3]; | |
222 | u8 LUN[HPSA_MAX_LUN][24]; | |
edd16368 SC |
223 | }; |
224 | ||
225 | struct SenseSubsystem_info { | |
01a02ffc SC |
226 | u8 reserved[36]; |
227 | u8 portname[8]; | |
228 | u8 reserved1[1108]; | |
edd16368 SC |
229 | }; |
230 | ||
edd16368 SC |
231 | /* BMIC commands */ |
232 | #define BMIC_READ 0x26 | |
233 | #define BMIC_WRITE 0x27 | |
234 | #define BMIC_CACHE_FLUSH 0xc2 | |
235 | #define HPSA_CACHE_FLUSH 0x01 /* C2 was already being used by HPSA */ | |
e85c5974 | 236 | #define BMIC_FLASH_FIRMWARE 0xF7 |
edd16368 SC |
237 | |
238 | /* Command List Structure */ | |
239 | union SCSI3Addr { | |
240 | struct { | |
01a02ffc SC |
241 | u8 Dev; |
242 | u8 Bus:6; | |
243 | u8 Mode:2; /* b00 */ | |
edd16368 SC |
244 | } PeripDev; |
245 | struct { | |
01a02ffc SC |
246 | u8 DevLSB; |
247 | u8 DevMSB:6; | |
248 | u8 Mode:2; /* b01 */ | |
edd16368 SC |
249 | } LogDev; |
250 | struct { | |
01a02ffc SC |
251 | u8 Dev:5; |
252 | u8 Bus:3; | |
253 | u8 Targ:6; | |
254 | u8 Mode:2; /* b10 */ | |
edd16368 SC |
255 | } LogUnit; |
256 | }; | |
257 | ||
258 | struct PhysDevAddr { | |
01a02ffc SC |
259 | u32 TargetId:24; |
260 | u32 Bus:6; | |
261 | u32 Mode:2; | |
edd16368 SC |
262 | /* 2 level target device addr */ |
263 | union SCSI3Addr Target[2]; | |
264 | }; | |
265 | ||
266 | struct LogDevAddr { | |
01a02ffc SC |
267 | u32 VolId:30; |
268 | u32 Mode:2; | |
269 | u8 reserved[4]; | |
edd16368 SC |
270 | }; |
271 | ||
272 | union LUNAddr { | |
01a02ffc | 273 | u8 LunAddrBytes[8]; |
edd16368 SC |
274 | union SCSI3Addr SCSI3Lun[4]; |
275 | struct PhysDevAddr PhysDev; | |
276 | struct LogDevAddr LogDev; | |
277 | }; | |
278 | ||
279 | struct CommandListHeader { | |
01a02ffc SC |
280 | u8 ReplyQueue; |
281 | u8 SGList; | |
282 | u16 SGTotal; | |
edd16368 SC |
283 | struct vals32 Tag; |
284 | union LUNAddr LUN; | |
285 | }; | |
286 | ||
287 | struct RequestBlock { | |
01a02ffc | 288 | u8 CDBLen; |
edd16368 | 289 | struct { |
01a02ffc SC |
290 | u8 Type:3; |
291 | u8 Attribute:3; | |
292 | u8 Direction:2; | |
edd16368 | 293 | } Type; |
01a02ffc SC |
294 | u16 Timeout; |
295 | u8 CDB[16]; | |
edd16368 SC |
296 | }; |
297 | ||
298 | struct ErrDescriptor { | |
299 | struct vals32 Addr; | |
01a02ffc | 300 | u32 Len; |
edd16368 SC |
301 | }; |
302 | ||
303 | struct SGDescriptor { | |
304 | struct vals32 Addr; | |
01a02ffc SC |
305 | u32 Len; |
306 | u32 Ext; | |
edd16368 SC |
307 | }; |
308 | ||
309 | union MoreErrInfo { | |
310 | struct { | |
01a02ffc SC |
311 | u8 Reserved[3]; |
312 | u8 Type; | |
313 | u32 ErrorInfo; | |
edd16368 SC |
314 | } Common_Info; |
315 | struct { | |
01a02ffc SC |
316 | u8 Reserved[2]; |
317 | u8 offense_size; /* size of offending entry */ | |
318 | u8 offense_num; /* byte # of offense 0-base */ | |
319 | u32 offense_value; | |
edd16368 SC |
320 | } Invalid_Cmd; |
321 | }; | |
322 | struct ErrorInfo { | |
01a02ffc SC |
323 | u8 ScsiStatus; |
324 | u8 SenseLen; | |
325 | u16 CommandStatus; | |
326 | u32 ResidualCnt; | |
edd16368 | 327 | union MoreErrInfo MoreErrInfo; |
01a02ffc | 328 | u8 SenseInfo[SENSEINFOBYTES]; |
edd16368 SC |
329 | }; |
330 | /* Command types */ | |
331 | #define CMD_IOCTL_PEND 0x01 | |
332 | #define CMD_SCSI 0x03 | |
e1f7de0c | 333 | #define CMD_IOACCEL1 0x04 |
edd16368 | 334 | |
303932fd DB |
335 | #define DIRECT_LOOKUP_SHIFT 5 |
336 | #define DIRECT_LOOKUP_BIT 0x10 | |
d896f3f3 | 337 | #define DIRECT_LOOKUP_MASK (~((1 << DIRECT_LOOKUP_SHIFT) - 1)) |
303932fd DB |
338 | |
339 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 340 | struct ctlr_info; /* defined in hpsa.h */ |
303932fd DB |
341 | /* The size of this structure needs to be divisible by 32 |
342 | * on all architectures because low 5 bits of the addresses | |
343 | * are used as follows: | |
344 | * | |
345 | * bit 0: to device, used to indicate "performant mode" command | |
346 | * from device, indidcates error status. | |
347 | * bit 1-3: to device, indicates block fetch table entry for | |
348 | * reducing DMA in fetching commands from host memory. | |
349 | * bit 4: used to indicate whether tag is "direct lookup" (index), | |
350 | * or a bus address. | |
edd16368 | 351 | */ |
303932fd | 352 | |
edd16368 SC |
353 | struct CommandList { |
354 | struct CommandListHeader Header; | |
355 | struct RequestBlock Request; | |
356 | struct ErrDescriptor ErrDesc; | |
d66ae08b | 357 | struct SGDescriptor SG[SG_ENTRIES_IN_CMD]; |
edd16368 | 358 | /* information associated with the command */ |
01a02ffc | 359 | u32 busaddr; /* physical addr of this record */ |
edd16368 SC |
360 | struct ErrorInfo *err_info; /* pointer to the allocated mem */ |
361 | struct ctlr_info *h; | |
362 | int cmd_type; | |
363 | long cmdindex; | |
9e0fc764 | 364 | struct list_head list; |
edd16368 SC |
365 | struct request *rq; |
366 | struct completion *waiting; | |
edd16368 | 367 | void *scsi_cmd; |
303932fd DB |
368 | |
369 | /* on 64 bit architectures, to get this to be 32-byte-aligned | |
db61bfcf SC |
370 | * it so happens we need PAD_64 bytes of padding, on 32 bit systems, |
371 | * we need PAD_32 bytes of padding (see below). This does that. | |
372 | * If it happens that 64 bit and 32 bit systems need different | |
373 | * padding, PAD_32 and PAD_64 can be set independently, and. | |
374 | * the code below will do the right thing. | |
303932fd | 375 | */ |
db61bfcf SC |
376 | #define IS_32_BIT ((8 - sizeof(long))/4) |
377 | #define IS_64_BIT (!IS_32_BIT) | |
283b4a9b | 378 | #define PAD_32 (36) |
43aebfa1 | 379 | #define PAD_64 (4) |
db61bfcf | 380 | #define COMMANDLIST_PAD (IS_32_BIT * PAD_32 + IS_64_BIT * PAD_64) |
303932fd | 381 | u8 pad[COMMANDLIST_PAD]; |
edd16368 SC |
382 | }; |
383 | ||
e1f7de0c MG |
384 | /* Max S/G elements in I/O accelerator command */ |
385 | #define IOACCEL1_MAXSGENTRIES 24 | |
386 | ||
387 | /* | |
388 | * Structure for I/O accelerator (mode 1) commands. | |
389 | * Note that this structure must be 128-byte aligned in size. | |
390 | */ | |
391 | struct io_accel1_cmd { | |
392 | u16 dev_handle; /* 0x00 - 0x01 */ | |
393 | u8 reserved1; /* 0x02 */ | |
394 | u8 function; /* 0x03 */ | |
395 | u8 reserved2[8]; /* 0x04 - 0x0B */ | |
396 | u32 err_info; /* 0x0C - 0x0F */ | |
397 | u8 reserved3[2]; /* 0x10 - 0x11 */ | |
398 | u8 err_info_len; /* 0x12 */ | |
399 | u8 reserved4; /* 0x13 */ | |
400 | u8 sgl_offset; /* 0x14 */ | |
401 | u8 reserved5[7]; /* 0x15 - 0x1B */ | |
402 | u32 transfer_len; /* 0x1C - 0x1F */ | |
403 | u8 reserved6[4]; /* 0x20 - 0x23 */ | |
404 | u16 io_flags; /* 0x24 - 0x25 */ | |
405 | u8 reserved7[14]; /* 0x26 - 0x33 */ | |
406 | u8 LUN[8]; /* 0x34 - 0x3B */ | |
407 | u32 control; /* 0x3C - 0x3F */ | |
408 | u8 CDB[16]; /* 0x40 - 0x4F */ | |
409 | u8 reserved8[16]; /* 0x50 - 0x5F */ | |
410 | u16 host_context_flags; /* 0x60 - 0x61 */ | |
411 | u16 timeout_sec; /* 0x62 - 0x63 */ | |
412 | u8 ReplyQueue; /* 0x64 */ | |
413 | u8 reserved9[3]; /* 0x65 - 0x67 */ | |
414 | struct vals32 Tag; /* 0x68 - 0x6F */ | |
415 | struct vals32 host_addr; /* 0x70 - 0x77 */ | |
416 | u8 CISS_LUN[8]; /* 0x78 - 0x7F */ | |
417 | struct SGDescriptor SG[IOACCEL1_MAXSGENTRIES]; | |
283b4a9b SC |
418 | #define IOACCEL1_PAD_64 0 |
419 | #define IOACCEL1_PAD_32 0 | |
420 | #define IOACCEL1_PAD (IS_32_BIT * IOACCEL1_PAD_32 + \ | |
421 | IS_64_BIT * IOACCEL1_PAD_64) | |
422 | u8 pad[IOACCEL1_PAD]; | |
e1f7de0c MG |
423 | }; |
424 | ||
425 | #define IOACCEL1_FUNCTION_SCSIIO 0x00 | |
426 | #define IOACCEL1_SGLOFFSET 32 | |
427 | ||
428 | #define IOACCEL1_IOFLAGS_IO_REQ 0x4000 | |
429 | #define IOACCEL1_IOFLAGS_CDBLEN_MASK 0x001F | |
430 | #define IOACCEL1_IOFLAGS_CDBLEN_MAX 16 | |
431 | ||
432 | #define IOACCEL1_CONTROL_NODATAXFER 0x00000000 | |
433 | #define IOACCEL1_CONTROL_DATA_OUT 0x01000000 | |
434 | #define IOACCEL1_CONTROL_DATA_IN 0x02000000 | |
435 | #define IOACCEL1_CONTROL_TASKPRIO_MASK 0x00007800 | |
436 | #define IOACCEL1_CONTROL_TASKPRIO_SHIFT 11 | |
437 | #define IOACCEL1_CONTROL_SIMPLEQUEUE 0x00000000 | |
438 | #define IOACCEL1_CONTROL_HEADOFQUEUE 0x00000100 | |
439 | #define IOACCEL1_CONTROL_ORDEREDQUEUE 0x00000200 | |
440 | #define IOACCEL1_CONTROL_ACA 0x00000400 | |
441 | ||
442 | #define IOACCEL1_HCFLAGS_CISS_FORMAT 0x0013 | |
443 | ||
444 | #define IOACCEL1_BUSADDR_CMDTYPE 0x00000060 | |
445 | ||
edd16368 SC |
446 | /* Configuration Table Structure */ |
447 | struct HostWrite { | |
01a02ffc SC |
448 | u32 TransportRequest; |
449 | u32 Reserved; | |
450 | u32 CoalIntDelay; | |
451 | u32 CoalIntCount; | |
edd16368 SC |
452 | }; |
453 | ||
303932fd DB |
454 | #define SIMPLE_MODE 0x02 |
455 | #define PERFORMANT_MODE 0x04 | |
456 | #define MEMQ_MODE 0x08 | |
e1f7de0c | 457 | #define IOACCEL_MODE_1 0x80 |
303932fd | 458 | |
283b4a9b SC |
459 | #define DRIVER_SUPPORT_UA_ENABLE 0x00000001 |
460 | ||
edd16368 | 461 | struct CfgTable { |
303932fd DB |
462 | u8 Signature[4]; |
463 | u32 SpecValence; | |
464 | u32 TransportSupport; | |
465 | u32 TransportActive; | |
466 | struct HostWrite HostWrite; | |
467 | u32 CmdsOutMax; | |
468 | u32 BusTypes; | |
469 | u32 TransMethodOffset; | |
470 | u8 ServerName[16]; | |
471 | u32 HeartBeat; | |
97a5e98c SC |
472 | u32 driver_support; |
473 | #define ENABLE_SCSI_PREFETCH 0x100 | |
28e13446 | 474 | #define ENABLE_UNIT_ATTN 0x01 |
303932fd DB |
475 | u32 MaxScatterGatherElements; |
476 | u32 MaxLogicalUnits; | |
477 | u32 MaxPhysicalDevices; | |
478 | u32 MaxPhysicalDrivesPerLogicalUnit; | |
479 | u32 MaxPerformantModeCommands; | |
75167d2c SC |
480 | u32 MaxBlockFetch; |
481 | u32 PowerConservationSupport; | |
482 | u32 PowerConservationEnable; | |
483 | u32 TMFSupportFlags; | |
484 | u8 TMFTagMask[8]; | |
485 | u8 reserved[0x78 - 0x70]; | |
1df8552a SC |
486 | u32 misc_fw_support; /* offset 0x78 */ |
487 | #define MISC_FW_DOORBELL_RESET (0x02) | |
cf0b08d0 | 488 | #define MISC_FW_DOORBELL_RESET2 (0x010) |
283b4a9b SC |
489 | #define MISC_FW_RAID_OFFLOAD_BASIC (0x020) |
490 | #define MISC_FW_EVENT_NOTIFY (0x080) | |
580ada3c | 491 | u8 driver_version[32]; |
283b4a9b SC |
492 | u32 max_cached_write_size; |
493 | u8 driver_scratchpad[16]; | |
494 | u32 max_error_info_length; | |
495 | u32 io_accel_max_embedded_sg_count; | |
496 | u32 io_accel_request_size_offset; | |
497 | u32 event_notify; | |
498 | u32 clear_event_notify; | |
303932fd DB |
499 | }; |
500 | ||
501 | #define NUM_BLOCKFETCH_ENTRIES 8 | |
502 | struct TransTable_struct { | |
503 | u32 BlockFetch[NUM_BLOCKFETCH_ENTRIES]; | |
504 | u32 RepQSize; | |
505 | u32 RepQCount; | |
506 | u32 RepQCtrAddrLow32; | |
507 | u32 RepQCtrAddrHigh32; | |
254f796b MG |
508 | #define MAX_REPLY_QUEUES 8 |
509 | struct vals32 RepQAddr[MAX_REPLY_QUEUES]; | |
edd16368 SC |
510 | }; |
511 | ||
512 | struct hpsa_pci_info { | |
513 | unsigned char bus; | |
514 | unsigned char dev_fn; | |
515 | unsigned short domain; | |
01a02ffc | 516 | u32 board_id; |
edd16368 SC |
517 | }; |
518 | ||
519 | #pragma pack() | |
520 | #endif /* HPSA_CMD_H */ |