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1 | /* |
2 | * HighPoint RR3xxx controller driver for Linux | |
3 | * Copyright (C) 2006 HighPoint Technologies, Inc. All Rights Reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * Please report bugs/comments/suggestions to linux@highpoint-tech.com | |
15 | * | |
16 | * For more information, visit http://www.highpoint-tech.com | |
17 | */ | |
18 | #ifndef _HPTIOP_H_ | |
19 | #define _HPTIOP_H_ | |
20 | ||
21 | /* | |
22 | * logical device type. | |
23 | * Identify array (logical device) and physical device. | |
24 | */ | |
25 | #define LDT_ARRAY 1 | |
26 | #define LDT_DEVICE 2 | |
27 | ||
28 | /* | |
29 | * Array types | |
30 | */ | |
31 | #define AT_UNKNOWN 0 | |
32 | #define AT_RAID0 1 | |
33 | #define AT_RAID1 2 | |
34 | #define AT_RAID5 3 | |
35 | #define AT_RAID6 4 | |
36 | #define AT_JBOD 7 | |
37 | ||
38 | #define MAX_NAME_LENGTH 36 | |
39 | #define MAX_ARRAYNAME_LEN 16 | |
40 | ||
41 | #define MAX_ARRAY_MEMBERS_V1 8 | |
42 | #define MAX_ARRAY_MEMBERS_V2 16 | |
43 | ||
44 | /* keep definition for source code compatiblity */ | |
45 | #define MAX_ARRAY_MEMBERS MAX_ARRAY_MEMBERS_V1 | |
46 | ||
47 | /* | |
48 | * array flags | |
49 | */ | |
50 | #define ARRAY_FLAG_DISABLED 0x00000001 /* The array is disabled */ | |
51 | #define ARRAY_FLAG_NEEDBUILDING 0x00000002 /* need to be rebuilt */ | |
52 | #define ARRAY_FLAG_REBUILDING 0x00000004 /* in rebuilding process */ | |
53 | #define ARRAY_FLAG_BROKEN 0x00000008 /* broken but still working */ | |
54 | #define ARRAY_FLAG_BOOTDISK 0x00000010 /* has a active partition */ | |
55 | #define ARRAY_FLAG_BOOTMARK 0x00000040 /* array has boot mark set */ | |
56 | #define ARRAY_FLAG_NEED_AUTOREBUILD 0x00000080 /* auto-rebuild should start */ | |
57 | #define ARRAY_FLAG_VERIFYING 0x00000100 /* is being verified */ | |
58 | #define ARRAY_FLAG_INITIALIZING 0x00000200 /* is being initialized */ | |
59 | #define ARRAY_FLAG_TRANSFORMING 0x00000400 /* tranform in progress */ | |
60 | #define ARRAY_FLAG_NEEDTRANSFORM 0x00000800 /* array need tranform */ | |
61 | #define ARRAY_FLAG_NEEDINITIALIZING 0x00001000 /* initialization not done */ | |
62 | #define ARRAY_FLAG_BROKEN_REDUNDANT 0x00002000 /* broken but redundant */ | |
63 | ||
64 | /* | |
65 | * device flags | |
66 | */ | |
67 | #define DEVICE_FLAG_DISABLED 0x00000001 /* device is disabled */ | |
68 | #define DEVICE_FLAG_UNINITIALIZED 0x00010000 /* device is not initialized */ | |
69 | #define DEVICE_FLAG_LEGACY 0x00020000 /* lagacy drive */ | |
70 | #define DEVICE_FLAG_IS_SPARE 0x80000000 /* is a spare disk */ | |
71 | ||
72 | /* | |
73 | * ioctl codes | |
74 | */ | |
75 | #define HPT_CTL_CODE(x) (x+0xFF00) | |
76 | #define HPT_CTL_CODE_LINUX_TO_IOP(x) ((x)-0xff00) | |
77 | ||
78 | #define HPT_IOCTL_GET_CONTROLLER_INFO HPT_CTL_CODE(2) | |
79 | #define HPT_IOCTL_GET_CHANNEL_INFO HPT_CTL_CODE(3) | |
80 | #define HPT_IOCTL_GET_LOGICAL_DEVICES HPT_CTL_CODE(4) | |
81 | #define HPT_IOCTL_GET_DRIVER_CAPABILITIES HPT_CTL_CODE(19) | |
82 | #define HPT_IOCTL_GET_DEVICE_INFO_V3 HPT_CTL_CODE(46) | |
83 | #define HPT_IOCTL_GET_CONTROLLER_INFO_V2 HPT_CTL_CODE(47) | |
84 | ||
85 | /* | |
86 | * Controller information. | |
87 | */ | |
88 | struct hpt_controller_info { | |
89 | u8 chip_type; /* chip type */ | |
90 | u8 interrupt_level; /* IRQ level */ | |
91 | u8 num_buses; /* bus count */ | |
92 | u8 chip_flags; | |
93 | ||
94 | u8 product_id[MAX_NAME_LENGTH];/* product name */ | |
95 | u8 vendor_id[MAX_NAME_LENGTH]; /* vendor name */ | |
96 | } | |
97 | __attribute__((packed)); | |
98 | ||
99 | /* | |
100 | * Channel information. | |
101 | */ | |
102 | struct hpt_channel_info { | |
103 | __le32 io_port; /* IDE Base Port Address */ | |
104 | __le32 control_port; /* IDE Control Port Address */ | |
105 | __le32 devices[2]; /* device connected to this channel */ | |
106 | } | |
107 | __attribute__((packed)); | |
108 | ||
109 | /* | |
110 | * Array information. | |
111 | */ | |
112 | struct hpt_array_info_v3 { | |
113 | u8 name[MAX_ARRAYNAME_LEN]; /* array name */ | |
114 | u8 description[64]; /* array description */ | |
115 | u8 create_manager[16]; /* who created it */ | |
116 | __le32 create_time; /* when created it */ | |
117 | ||
118 | u8 array_type; /* array type */ | |
119 | u8 block_size_shift; /* stripe size */ | |
120 | u8 ndisk; /* Number of ID in Members[] */ | |
121 | u8 reserved; | |
122 | ||
123 | __le32 flags; /* working flags, see ARRAY_FLAG_XXX */ | |
124 | __le32 members[MAX_ARRAY_MEMBERS_V2]; /* member array/disks */ | |
125 | ||
126 | __le32 rebuilding_progress; | |
127 | __le64 rebuilt_sectors; /* rebuilding point (LBA) for single member */ | |
128 | ||
129 | __le32 transform_source; | |
130 | __le32 transform_target; /* destination device ID */ | |
131 | __le32 transforming_progress; | |
132 | __le32 signature; /* persistent identification*/ | |
133 | __le16 critical_members; /* bit mask of critical members */ | |
134 | __le16 reserve2; | |
135 | __le32 reserve; | |
136 | } | |
137 | __attribute__((packed)); | |
138 | ||
139 | /* | |
140 | * physical device information. | |
141 | */ | |
142 | #define MAX_PARENTS_PER_DISK 8 | |
143 | ||
144 | struct hpt_device_info_v2 { | |
145 | u8 ctlr_id; /* controller id */ | |
146 | u8 path_id; /* bus */ | |
147 | u8 target_id; /* id */ | |
148 | u8 device_mode_setting; /* Current Data Transfer mode: 0-4 PIO0-4 */ | |
149 | /* 5-7 MW DMA0-2, 8-13 UDMA0-5 */ | |
150 | u8 device_type; /* device type */ | |
151 | u8 usable_mode; /* highest usable mode */ | |
152 | ||
153 | #ifdef __BIG_ENDIAN_BITFIELD | |
154 | u8 NCQ_enabled: 1; | |
155 | u8 NCQ_supported: 1; | |
156 | u8 TCQ_enabled: 1; | |
157 | u8 TCQ_supported: 1; | |
158 | u8 write_cache_enabled: 1; | |
159 | u8 write_cache_supported: 1; | |
160 | u8 read_ahead_enabled: 1; | |
161 | u8 read_ahead_supported: 1; | |
162 | u8 reserved6: 6; | |
163 | u8 spin_up_mode: 2; | |
164 | #else | |
165 | u8 read_ahead_supported: 1; | |
166 | u8 read_ahead_enabled: 1; | |
167 | u8 write_cache_supported: 1; | |
168 | u8 write_cache_enabled: 1; | |
169 | u8 TCQ_supported: 1; | |
170 | u8 TCQ_enabled: 1; | |
171 | u8 NCQ_supported: 1; | |
172 | u8 NCQ_enabled: 1; | |
173 | u8 spin_up_mode: 2; | |
174 | u8 reserved6: 6; | |
175 | #endif | |
176 | ||
177 | __le32 flags; /* working flags, see DEVICE_FLAG_XXX */ | |
178 | u8 ident[150]; /* (partitial) Identify Data of this device */ | |
179 | ||
180 | __le64 total_free; | |
181 | __le64 max_free; | |
182 | __le64 bad_sectors; | |
183 | __le32 parent_arrays[MAX_PARENTS_PER_DISK]; | |
184 | } | |
185 | __attribute__((packed)); | |
186 | ||
187 | /* | |
188 | * Logical device information. | |
189 | */ | |
190 | #define INVALID_TARGET_ID 0xFF | |
191 | #define INVALID_BUS_ID 0xFF | |
192 | ||
193 | struct hpt_logical_device_info_v3 { | |
194 | u8 type; /* LDT_ARRAY or LDT_DEVICE */ | |
195 | u8 cache_policy; /* refer to CACHE_POLICY_xxx */ | |
196 | u8 vbus_id; /* vbus sequence in vbus_list */ | |
197 | u8 target_id; /* OS target id. 0xFF is invalid */ | |
198 | /* OS name: DISK $VBusId_$TargetId */ | |
199 | __le64 capacity; /* array capacity */ | |
200 | __le32 parent_array; /* don't use this field for physical | |
201 | device. use ParentArrays field in | |
202 | hpt_device_info_v2 */ | |
203 | /* reserved statistic fields */ | |
204 | __le32 stat1; | |
205 | __le32 stat2; | |
206 | __le32 stat3; | |
207 | __le32 stat4; | |
208 | ||
209 | union { | |
210 | struct hpt_array_info_v3 array; | |
211 | struct hpt_device_info_v2 device; | |
212 | } __attribute__((packed)) u; | |
213 | ||
214 | } | |
215 | __attribute__((packed)); | |
216 | ||
217 | /* | |
218 | * ioctl structure | |
219 | */ | |
220 | #define HPT_IOCTL_MAGIC 0xA1B2C3D4 | |
221 | ||
222 | struct hpt_ioctl_u { | |
223 | u32 magic; /* used to check if it's a valid ioctl packet */ | |
224 | u32 ioctl_code; /* operation control code */ | |
225 | void __user *inbuf; /* input data buffer */ | |
226 | u32 inbuf_size; /* size of input data buffer */ | |
227 | void __user *outbuf; /* output data buffer */ | |
228 | u32 outbuf_size; /* size of output data buffer */ | |
229 | void __user *bytes_returned; /* count of bytes returned */ | |
230 | } | |
231 | __attribute__((packed)); | |
232 | ||
233 | ||
234 | struct hpt_iopmu | |
235 | { | |
236 | __le32 resrved0[4]; | |
237 | __le32 inbound_msgaddr0; | |
238 | __le32 inbound_msgaddr1; | |
239 | __le32 outbound_msgaddr0; | |
240 | __le32 outbound_msgaddr1; | |
241 | __le32 inbound_doorbell; | |
242 | __le32 inbound_intstatus; | |
243 | __le32 inbound_intmask; | |
244 | __le32 outbound_doorbell; | |
245 | __le32 outbound_intstatus; | |
246 | __le32 outbound_intmask; | |
247 | __le32 reserved1[2]; | |
248 | __le32 inbound_queue; | |
249 | __le32 outbound_queue; | |
250 | }; | |
251 | ||
252 | #define IOPMU_QUEUE_EMPTY 0xffffffff | |
253 | #define IOPMU_QUEUE_MASK_HOST_BITS 0xf0000000 | |
254 | #define IOPMU_QUEUE_ADDR_HOST_BIT 0x80000000 | |
255 | ||
256 | #define IOPMU_OUTBOUND_INT_MSG0 1 | |
257 | #define IOPMU_OUTBOUND_INT_MSG1 2 | |
258 | #define IOPMU_OUTBOUND_INT_DOORBELL 4 | |
259 | #define IOPMU_OUTBOUND_INT_POSTQUEUE 8 | |
260 | #define IOPMU_OUTBOUND_INT_PCI 0x10 | |
261 | ||
262 | #define IOPMU_INBOUND_INT_MSG0 1 | |
263 | #define IOPMU_INBOUND_INT_MSG1 2 | |
264 | #define IOPMU_INBOUND_INT_DOORBELL 4 | |
265 | #define IOPMU_INBOUND_INT_ERROR 8 | |
266 | #define IOPMU_INBOUND_INT_POSTQUEUE 0x10 | |
267 | ||
268 | enum hpt_iopmu_message { | |
269 | /* host-to-iop messages */ | |
270 | IOPMU_INBOUND_MSG0_NOP = 0, | |
271 | IOPMU_INBOUND_MSG0_RESET, | |
272 | IOPMU_INBOUND_MSG0_FLUSH, | |
273 | IOPMU_INBOUND_MSG0_SHUTDOWN, | |
274 | IOPMU_INBOUND_MSG0_STOP_BACKGROUND_TASK, | |
275 | IOPMU_INBOUND_MSG0_START_BACKGROUND_TASK, | |
276 | IOPMU_INBOUND_MSG0_MAX = 0xff, | |
277 | /* iop-to-host messages */ | |
278 | IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_0 = 0x100, | |
279 | IOPMU_OUTBOUND_MSG0_REGISTER_DEVICE_MAX = 0x1ff, | |
280 | IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_0 = 0x200, | |
281 | IOPMU_OUTBOUND_MSG0_UNREGISTER_DEVICE_MAX = 0x2ff, | |
282 | IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_0 = 0x300, | |
283 | IOPMU_OUTBOUND_MSG0_REVALIDATE_DEVICE_MAX = 0x3ff, | |
284 | }; | |
285 | ||
286 | struct hpt_iop_request_header | |
287 | { | |
288 | __le32 size; | |
289 | __le32 type; | |
290 | __le32 flags; | |
291 | __le32 result; | |
292 | __le32 context; /* host context */ | |
293 | __le32 context_hi32; | |
294 | }; | |
295 | ||
296 | #define IOP_REQUEST_FLAG_SYNC_REQUEST 1 | |
297 | #define IOP_REQUEST_FLAG_BIST_REQUEST 2 | |
298 | #define IOP_REQUEST_FLAG_REMAPPED 4 | |
299 | #define IOP_REQUEST_FLAG_OUTPUT_CONTEXT 8 | |
300 | ||
301 | enum hpt_iop_request_type { | |
302 | IOP_REQUEST_TYPE_GET_CONFIG = 0, | |
303 | IOP_REQUEST_TYPE_SET_CONFIG, | |
304 | IOP_REQUEST_TYPE_BLOCK_COMMAND, | |
305 | IOP_REQUEST_TYPE_SCSI_COMMAND, | |
306 | IOP_REQUEST_TYPE_IOCTL_COMMAND, | |
307 | IOP_REQUEST_TYPE_MAX | |
308 | }; | |
309 | ||
310 | enum hpt_iop_result_type { | |
311 | IOP_RESULT_PENDING = 0, | |
312 | IOP_RESULT_SUCCESS, | |
313 | IOP_RESULT_FAIL, | |
314 | IOP_RESULT_BUSY, | |
315 | IOP_RESULT_RESET, | |
316 | IOP_RESULT_INVALID_REQUEST, | |
317 | IOP_RESULT_BAD_TARGET, | |
318 | IOP_RESULT_MODE_SENSE_CHECK_CONDITION, | |
319 | }; | |
320 | ||
321 | struct hpt_iop_request_get_config | |
322 | { | |
323 | struct hpt_iop_request_header header; | |
324 | __le32 interface_version; | |
325 | __le32 firmware_version; | |
326 | __le32 max_requests; | |
327 | __le32 request_size; | |
328 | __le32 max_sg_count; | |
329 | __le32 data_transfer_length; | |
330 | __le32 alignment_mask; | |
331 | __le32 max_devices; | |
332 | __le32 sdram_size; | |
333 | }; | |
334 | ||
335 | struct hpt_iop_request_set_config | |
336 | { | |
337 | struct hpt_iop_request_header header; | |
338 | __le32 iop_id; | |
339 | __le32 vbus_id; | |
340 | __le32 reserve[6]; | |
341 | }; | |
342 | ||
343 | struct hpt_iopsg | |
344 | { | |
345 | __le32 size; | |
346 | __le32 eot; /* non-zero: end of table */ | |
347 | __le64 pci_address; | |
348 | }; | |
349 | ||
350 | struct hpt_iop_request_block_command | |
351 | { | |
352 | struct hpt_iop_request_header header; | |
353 | u8 channel; | |
354 | u8 target; | |
355 | u8 lun; | |
356 | u8 pad1; | |
357 | __le16 command; /* IOP_BLOCK_COMMAND_{READ,WRITE} */ | |
358 | __le16 sectors; | |
359 | __le64 lba; | |
360 | struct hpt_iopsg sg_list[1]; | |
361 | }; | |
362 | ||
363 | #define IOP_BLOCK_COMMAND_READ 1 | |
364 | #define IOP_BLOCK_COMMAND_WRITE 2 | |
365 | #define IOP_BLOCK_COMMAND_VERIFY 3 | |
366 | #define IOP_BLOCK_COMMAND_FLUSH 4 | |
367 | #define IOP_BLOCK_COMMAND_SHUTDOWN 5 | |
368 | ||
369 | struct hpt_iop_request_scsi_command | |
370 | { | |
371 | struct hpt_iop_request_header header; | |
372 | u8 channel; | |
373 | u8 target; | |
374 | u8 lun; | |
375 | u8 pad1; | |
376 | u8 cdb[16]; | |
377 | __le32 dataxfer_length; | |
378 | struct hpt_iopsg sg_list[1]; | |
379 | }; | |
380 | ||
381 | struct hpt_iop_request_ioctl_command | |
382 | { | |
383 | struct hpt_iop_request_header header; | |
384 | __le32 ioctl_code; | |
385 | __le32 inbuf_size; | |
386 | __le32 outbuf_size; | |
387 | __le32 bytes_returned; | |
388 | u8 buf[1]; | |
389 | /* out data should be put at buf[(inbuf_size+3)&~3] */ | |
390 | }; | |
391 | ||
392 | #define HPTIOP_MAX_REQUESTS 256u | |
393 | ||
394 | struct hptiop_request { | |
395 | struct hptiop_request * next; | |
396 | void * req_virt; | |
397 | u32 req_shifted_phy; | |
398 | struct scsi_cmnd * scp; | |
399 | int index; | |
400 | }; | |
401 | ||
402 | struct hpt_scsi_pointer { | |
403 | int mapped; | |
404 | int sgcnt; | |
405 | dma_addr_t dma_handle; | |
406 | }; | |
407 | ||
408 | #define HPT_SCP(scp) ((struct hpt_scsi_pointer *)&(scp)->SCp) | |
409 | ||
410 | struct hptiop_hba { | |
411 | struct hpt_iopmu __iomem * iop; | |
412 | struct Scsi_Host * host; | |
413 | struct pci_dev * pcidev; | |
414 | ||
415 | struct list_head link; | |
416 | ||
417 | /* IOP config info */ | |
418 | u32 firmware_version; | |
419 | u32 sdram_size; | |
420 | u32 max_devices; | |
421 | u32 max_requests; | |
422 | u32 max_request_size; | |
423 | u32 max_sg_descriptors; | |
424 | ||
425 | u32 req_size; /* host-allocated request buffer size */ | |
426 | int initialized; | |
427 | int msg_done; | |
428 | ||
429 | struct hptiop_request * req_list; | |
430 | struct hptiop_request reqs[HPTIOP_MAX_REQUESTS]; | |
431 | ||
432 | /* used to free allocated dma area */ | |
433 | void * dma_coherent; | |
434 | dma_addr_t dma_coherent_handle; | |
435 | ||
436 | atomic_t reset_count; | |
437 | atomic_t resetting; | |
438 | ||
439 | wait_queue_head_t reset_wq; | |
440 | wait_queue_head_t ioctl_wq; | |
441 | }; | |
442 | ||
443 | struct hpt_ioctl_k | |
444 | { | |
445 | struct hptiop_hba * hba; | |
446 | u32 ioctl_code; | |
447 | u32 inbuf_size; | |
448 | u32 outbuf_size; | |
449 | void * inbuf; | |
450 | void * outbuf; | |
451 | u32 * bytes_returned; | |
452 | void (*done)(struct hpt_ioctl_k *); | |
453 | int result; /* HPT_IOCTL_RESULT_ */ | |
454 | }; | |
455 | ||
456 | #define HPT_IOCTL_RESULT_OK 0 | |
457 | #define HPT_IOCTL_RESULT_FAILED (-1) | |
458 | ||
459 | #if 0 | |
460 | #define dprintk(fmt, args...) do { printk(fmt, ##args); } while(0) | |
461 | #else | |
462 | #define dprintk(fmt, args...) | |
463 | #endif | |
464 | ||
465 | #endif |