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[SCSI] ipr: add error handling updates for the next generation chip
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
95fecd90
WB		 40#define IPR_DRIVER_VERSION "2.4.3"
41#define IPR_DRIVER_DATE "(June 10, 2009)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 115#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 116
ac719aba 117#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 118#define IPR_NUM_LOG_HCAMS 2
119#define IPR_NUM_CFG_CHG_HCAMS 2
120#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 121
122#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
123#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
124
d71a8b0c 125#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 126#define IPR_MAX_NUM_LUNS_PER_TARGET 256
127#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
128#define IPR_VSET_BUS 0xff
129#define IPR_IOA_BUS 0xff
130#define IPR_IOA_TARGET 0xff
131#define IPR_IOA_LUN 0xff
b5145d25 132#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 133#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
134
135#define IPR_NUM_RESET_RELOAD_RETRIES 3
136
137/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
138#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
139 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
140
141#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
142#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
143 IPR_NUM_INTERNAL_CMD_BLKS)
144
145#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 146#define IPR_DEFAULT_SIS64_DEVS 1024
147#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 148
149#define IPR_MAX_SGLIST 64
150#define IPR_IOA_MAX_SECTORS 32767
151#define IPR_VSET_MAX_SECTORS 512
152#define IPR_MAX_CDB_LEN 16
3feeb89d 153#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 154
155#define IPR_DEFAULT_BUS_WIDTH 16
156#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
157#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
158#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
159#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
160
161#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 162#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 163#define IPR_IOA_RES_ADDR 0x00ffffff
164
165/*
166 * Adapter Commands
167 */
168#define IPR_QUERY_RSRC_STATE 0xC2
169#define IPR_RESET_DEVICE 0xC3
170#define IPR_RESET_TYPE_SELECT 0x80
171#define IPR_LUN_RESET 0x40
172#define IPR_TARGET_RESET 0x20
173#define IPR_BUS_RESET 0x10
b5145d25 174#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 175#define IPR_ID_HOST_RR_Q 0xC4
176#define IPR_QUERY_IOA_CONFIG 0xC5
177#define IPR_CANCEL_ALL_REQUESTS 0xCE
178#define IPR_HOST_CONTROLLED_ASYNC 0xCF
179#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
180#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
181#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 182#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 183#define IPR_IOA_SHUTDOWN 0xF7
184#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
185
186/*
187 * Timeouts
188 */
189#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
190#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
191#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 192#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 193#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
194#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
195#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
196#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
197#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
198#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
199#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
200#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 201#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 202#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
203#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
204#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 205#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 206#define IPR_DUMP_TIMEOUT (15 * HZ)
207
208/*
209 * SCSI Literals
210 */
211#define IPR_VENDOR_ID_LEN 8
212#define IPR_PROD_ID_LEN 16
213#define IPR_SERIAL_NUM_LEN 8
214
215/*
216 * Hardware literals
217 */
218#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
219#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
220#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
221#define IPR_GET_FMT2_BAR_SEL(mbx) \
222(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
223#define IPR_SDT_FMT2_BAR0_SEL 0x0
224#define IPR_SDT_FMT2_BAR1_SEL 0x1
225#define IPR_SDT_FMT2_BAR2_SEL 0x2
226#define IPR_SDT_FMT2_BAR3_SEL 0x3
227#define IPR_SDT_FMT2_BAR4_SEL 0x4
228#define IPR_SDT_FMT2_BAR5_SEL 0x5
229#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
230#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
231#define IPR_DOORBELL 0x82800000
3d1d0da6 232#define IPR_RUNTIME_RESET 0x40000000
1da177e4
LT		 233
234#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
235#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
236#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
237#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
238#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
239#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
240#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
241#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
242#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
243#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
244#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
245
246#define IPR_PCII_ERROR_INTERRUPTS \
247(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
248IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
249
250#define IPR_PCII_OPER_INTERRUPTS \
251(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
252
253#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
254#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
255
256#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
257#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
258
259/*
260 * Dump literals
261 */
262#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
263#define IPR_NUM_SDT_ENTRIES 511
264#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
265
266/*
267 * Misc literals
268 */
269#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
270
271/*
272 * Adapter interface types
273 */
274
275struct ipr_res_addr {
276 u8 reserved;
277 u8 bus;
278 u8 target;
279 u8 lun;
280#define IPR_GET_PHYS_LOC(res_addr) \
281 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
282}__attribute__((packed, aligned (4)));
283
284struct ipr_std_inq_vpids {
285 u8 vendor_id[IPR_VENDOR_ID_LEN];
286 u8 product_id[IPR_PROD_ID_LEN];
287}__attribute__((packed));
288
cfc32139
BK		 289struct ipr_vpd {
290 struct ipr_std_inq_vpids vpids;
291 u8 sn[IPR_SERIAL_NUM_LEN];
292}__attribute__((packed));
293
ee0f05b8
BK		 294struct ipr_ext_vpd {
295 struct ipr_vpd vpd;
296 __be32 wwid[2];
297}__attribute__((packed));
298
1da177e4
LT		 299struct ipr_std_inq_data {
300 u8 peri_qual_dev_type;
301#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
302#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
303
304 u8 removeable_medium_rsvd;
305#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
306
307#define IPR_IS_DASD_DEVICE(std_inq) \
308((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
309!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
310
311#define IPR_IS_SES_DEVICE(std_inq) \
312(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
313
314 u8 version;
315 u8 aen_naca_fmt;
316 u8 additional_len;
317 u8 sccs_rsvd;
318 u8 bq_enc_multi;
319 u8 sync_cmdq_flags;
320
321 struct ipr_std_inq_vpids vpids;
322
323 u8 ros_rsvd_ram_rsvd[4];
324
325 u8 serial_num[IPR_SERIAL_NUM_LEN];
326}__attribute__ ((packed));
327
3e7ebdfa
WB		 328#define IPR_RES_TYPE_AF_DASD 0x00
329#define IPR_RES_TYPE_GENERIC_SCSI 0x01
330#define IPR_RES_TYPE_VOLUME_SET 0x02
331#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
332#define IPR_RES_TYPE_GENERIC_ATA 0x04
333#define IPR_RES_TYPE_ARRAY 0x05
334#define IPR_RES_TYPE_IOAFP 0xff
335
1da177e4 336struct ipr_config_table_entry {
b5145d25
BK		 337 u8 proto;
338#define IPR_PROTO_SATA 0x02
339#define IPR_PROTO_SATA_ATAPI 0x03
340#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 341#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 342 u8 array_id;
343 u8 flags;
3e7ebdfa 344#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 345 u8 rsvd_subtype;
3e7ebdfa
WB		 346
347#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
348#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK		 349#define IPR_QUEUE_NACA_MODEL 1
350
1da177e4
LT		 351 struct ipr_res_addr res_addr;
352 __be32 res_handle;
353 __be32 reserved4[2];
354 struct ipr_std_inq_data std_inq_data;
355}__attribute__ ((packed, aligned (4)));
356
3e7ebdfa
WB		 357struct ipr_config_table_entry64 {
358 u8 res_type;
359 u8 proto;
360 u8 vset_num;
361 u8 array_id;
362 __be16 flags;
363 __be16 res_flags;
364#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
365 __be32 res_handle;
366 u8 dev_id_type;
367 u8 reserved[3];
368 __be64 dev_id;
369 __be64 lun;
370 __be64 lun_wwn[2];
371#define IPR_MAX_RES_PATH_LENGTH 24
372 __be64 res_path;
373 struct ipr_std_inq_data std_inq_data;
374 u8 reserved2[4];
375 __be64 reserved3[2]; // description text
376 u8 reserved4[8];
377}__attribute__ ((packed, aligned (8)));
378
1da177e4
LT		 379struct ipr_config_table_hdr {
380 u8 num_entries;
381 u8 flags;
382#define IPR_UCODE_DOWNLOAD_REQ 0x10
383 __be16 reserved;
384}__attribute__((packed, aligned (4)));
385
3e7ebdfa
WB		 386struct ipr_config_table_hdr64 {
387 __be16 num_entries;
388 __be16 reserved;
389 u8 flags;
390 u8 reserved2[11];
391}__attribute__((packed, aligned (4)));
392
1da177e4
LT		 393struct ipr_config_table {
394 struct ipr_config_table_hdr hdr;
3e7ebdfa 395 struct ipr_config_table_entry dev[0];
1da177e4
LT		 396}__attribute__((packed, aligned (4)));
397
3e7ebdfa
WB		 398struct ipr_config_table64 {
399 struct ipr_config_table_hdr64 hdr64;
400 struct ipr_config_table_entry64 dev[0];
401}__attribute__((packed, aligned (8)));
402
403struct ipr_config_table_entry_wrapper {
404 union {
405 struct ipr_config_table_entry *cfgte;
406 struct ipr_config_table_entry64 *cfgte64;
407 } u;
408};
409
1da177e4 410struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 411 union {
412 struct ipr_config_table_entry cfgte;
413 struct ipr_config_table_entry64 cfgte64;
414 } u;
1da177e4
LT		 415 u8 reserved[936];
416}__attribute__((packed, aligned (4)));
417
418struct ipr_supported_device {
419 __be16 data_length;
420 u8 reserved;
421 u8 num_records;
422 struct ipr_std_inq_vpids vpids;
423 u8 reserved2[16];
424}__attribute__((packed, aligned (4)));
425
426/* Command packet structure */
427struct ipr_cmd_pkt {
428 __be16 reserved; /* Reserved by IOA */
429 u8 request_type;
430#define IPR_RQTYPE_SCSICDB 0x00
431#define IPR_RQTYPE_IOACMD 0x01
432#define IPR_RQTYPE_HCAM 0x02
b5145d25 433#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 434
a32c055f 435 u8 reserved2;
1da177e4
LT		 436
437 u8 flags_hi;
438#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
439#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
440#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
441#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
442#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
443
444 u8 flags_lo;
445#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
446#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
447#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
448#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
449#define IPR_FLAGS_LO_ORDERED_TASK 0x04
450#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
451#define IPR_FLAGS_LO_ACA_TASK 0x08
452
453 u8 cdb[16];
454 __be16 timeout;
455}__attribute__ ((packed, aligned(4)));
456
a32c055f 457struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 458 u8 flags;
459#define IPR_ATA_FLAG_PACKET_CMD 0x80
460#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
461#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
462 u8 reserved[3];
463
464 __be16 data;
465 u8 feature;
466 u8 nsect;
467 u8 lbal;
468 u8 lbam;
469 u8 lbah;
470 u8 device;
471 u8 command;
472 u8 reserved2[3];
473 u8 hob_feature;
474 u8 hob_nsect;
475 u8 hob_lbal;
476 u8 hob_lbam;
477 u8 hob_lbah;
478 u8 ctl;
479}__attribute__ ((packed, aligned(4)));
480
51b1c7e1
BK		 481struct ipr_ioadl_desc {
482 __be32 flags_and_data_len;
483#define IPR_IOADL_FLAGS_MASK 0xff000000
484#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
485#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
486#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
487#define IPR_IOADL_FLAGS_READ 0x48000000
488#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
489#define IPR_IOADL_FLAGS_WRITE 0x68000000
490#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
491#define IPR_IOADL_FLAGS_LAST 0x01000000
492
493 __be32 address;
494}__attribute__((packed, aligned (8)));
495
a32c055f
WB		 496struct ipr_ioadl64_desc {
497 __be32 flags;
498 __be32 data_len;
499 __be64 address;
500}__attribute__((packed, aligned (16)));
501
502struct ipr_ata64_ioadl {
503 struct ipr_ioarcb_ata_regs regs;
504 u16 reserved[5];
505 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
506}__attribute__((packed, aligned (16)));
507
b5145d25
BK		 508struct ipr_ioarcb_add_data {
509 union {
510 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 511 struct ipr_ioadl_desc ioadl[5];
b5145d25 512 __be32 add_cmd_parms[10];
a32c055f
WB		 513 } u;
514}__attribute__ ((packed, aligned (4)));
515
516struct ipr_ioarcb_sis64_add_addr_ecb {
517 __be64 ioasa_host_pci_addr;
518 __be64 data_ioadl_addr;
519 __be64 reserved;
520 __be32 ext_control_buf[4];
521}__attribute__((packed, aligned (8)));
b5145d25 522
1da177e4
LT		 523/* IOA Request Control Block 128 bytes */
524struct ipr_ioarcb {
a32c055f
WB		 525 union {
526 __be32 ioarcb_host_pci_addr;
527 __be64 ioarcb_host_pci_addr64;
528 } a;
1da177e4
LT		 529 __be32 res_handle;
530 __be32 host_response_handle;
531 __be32 reserved1;
532 __be32 reserved2;
533 __be32 reserved3;
534
a32c055f 535 __be32 data_transfer_length;
1da177e4
LT		 536 __be32 read_data_transfer_length;
537 __be32 write_ioadl_addr;
a32c055f 538 __be32 ioadl_len;
1da177e4
LT		 539 __be32 read_ioadl_addr;
540 __be32 read_ioadl_len;
541
542 __be32 ioasa_host_pci_addr;
543 __be16 ioasa_len;
544 __be16 reserved4;
545
546 struct ipr_cmd_pkt cmd_pkt;
547
a32c055f
WB		 548 __be16 add_cmd_parms_offset;
549 __be16 add_cmd_parms_len;
550
551 union {
552 struct ipr_ioarcb_add_data add_data;
553 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
554 } u;
555
1da177e4
LT		 556}__attribute__((packed, aligned (4)));
557
1da177e4
LT		 558struct ipr_ioasa_vset {
559 __be32 failing_lba_hi;
560 __be32 failing_lba_lo;
c8f74892 561 __be32 reserved;
1da177e4
LT		 562}__attribute__((packed, aligned (4)));
563
564struct ipr_ioasa_af_dasd {
565 __be32 failing_lba;
c8f74892 566 __be32 reserved[2];
1da177e4
LT		 567}__attribute__((packed, aligned (4)));
568
569struct ipr_ioasa_gpdd {
570 u8 end_state;
571 u8 bus_phase;
572 __be16 reserved;
c8f74892 573 __be32 ioa_data[2];
1da177e4
LT		 574}__attribute__((packed, aligned (4)));
575
b5145d25
BK		 576struct ipr_ioasa_gata {
577 u8 error;
578 u8 nsect; /* Interrupt reason */
579 u8 lbal;
580 u8 lbam;
581 u8 lbah;
582 u8 device;
583 u8 status;
584 u8 alt_status; /* ATA CTL */
585 u8 hob_nsect;
586 u8 hob_lbal;
587 u8 hob_lbam;
588 u8 hob_lbah;
589}__attribute__((packed, aligned (4)));
590
c8f74892
BK		 591struct ipr_auto_sense {
592 __be16 auto_sense_len;
593 __be16 ioa_data_len;
594 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
595};
1da177e4
LT		 596
597struct ipr_ioasa {
598 __be32 ioasc;
599#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
600#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
601#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
602#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
603
604 __be16 ret_stat_len; /* Length of the returned IOASA */
605
606 __be16 avail_stat_len; /* Total Length of status available. */
607
608 __be32 residual_data_len; /* number of bytes in the host data */
609 /* buffers that were not used by the IOARCB command. */
610
611 __be32 ilid;
612#define IPR_NO_ILID 0
613#define IPR_DRIVER_ILID 0xffffffff
614
615 __be32 fd_ioasc;
616
617 __be32 fd_phys_locator;
618
619 __be32 fd_res_handle;
620
621 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 622#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
623#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 624#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 625#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
626#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
627#define IPR_FIELD_POINTER_MASK 0x0000ffff
628
629 union {
630 struct ipr_ioasa_vset vset;
631 struct ipr_ioasa_af_dasd dasd;
632 struct ipr_ioasa_gpdd gpdd;
b5145d25 633 struct ipr_ioasa_gata gata;
1da177e4 634 } u;
c8f74892
BK		 635
636 struct ipr_auto_sense auto_sense;
1da177e4
LT		 637}__attribute__((packed, aligned (4)));
638
639struct ipr_mode_parm_hdr {
640 u8 length;
641 u8 medium_type;
642 u8 device_spec_parms;
643 u8 block_desc_len;
644}__attribute__((packed));
645
646struct ipr_mode_pages {
647 struct ipr_mode_parm_hdr hdr;
648 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
649}__attribute__((packed));
650
651struct ipr_mode_page_hdr {
652 u8 ps_page_code;
653#define IPR_MODE_PAGE_PS 0x80
654#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
655 u8 page_length;
656}__attribute__ ((packed));
657
658struct ipr_dev_bus_entry {
659 struct ipr_res_addr res_addr;
660 u8 flags;
661#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
662#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
663#define IPR_SCSI_ATTR_QAS_MASK 0xC0
664#define IPR_SCSI_ATTR_ENABLE_TM 0x20
665#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
666#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
667#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
668
669 u8 scsi_id;
670 u8 bus_width;
671 u8 extended_reset_delay;
672#define IPR_EXTENDED_RESET_DELAY 7
673
674 __be32 max_xfer_rate;
675
676 u8 spinup_delay;
677 u8 reserved3;
678 __be16 reserved4;
679}__attribute__((packed, aligned (4)));
680
681struct ipr_mode_page28 {
682 struct ipr_mode_page_hdr hdr;
683 u8 num_entries;
684 u8 entry_length;
685 struct ipr_dev_bus_entry bus[0];
686}__attribute__((packed));
687
ac09c349
BK		 688struct ipr_mode_page24 {
689 struct ipr_mode_page_hdr hdr;
690 u8 flags;
691#define IPR_ENABLE_DUAL_IOA_AF 0x80
692}__attribute__((packed));
693
1da177e4
LT		 694struct ipr_ioa_vpd {
695 struct ipr_std_inq_data std_inq_data;
696 u8 ascii_part_num[12];
697 u8 reserved[40];
698 u8 ascii_plant_code[4];
699}__attribute__((packed));
700
701struct ipr_inquiry_page3 {
702 u8 peri_qual_dev_type;
703 u8 page_code;
704 u8 reserved1;
705 u8 page_length;
706 u8 ascii_len;
707 u8 reserved2[3];
708 u8 load_id[4];
709 u8 major_release;
710 u8 card_type;
711 u8 minor_release[2];
712 u8 ptf_number[4];
713 u8 patch_number[4];
714}__attribute__((packed));
715
ac09c349
BK		 716struct ipr_inquiry_cap {
717 u8 peri_qual_dev_type;
718 u8 page_code;
719 u8 reserved1;
720 u8 page_length;
721 u8 ascii_len;
722 u8 reserved2;
723 u8 sis_version[2];
724 u8 cap;
725#define IPR_CAP_DUAL_IOA_RAID 0x80
726 u8 reserved3[15];
727}__attribute__((packed));
728
62275040
BK		 729#define IPR_INQUIRY_PAGE0_ENTRIES 20
730struct ipr_inquiry_page0 {
731 u8 peri_qual_dev_type;
732 u8 page_code;
733 u8 reserved1;
734 u8 len;
735 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
736}__attribute__((packed));
737
1da177e4 738struct ipr_hostrcb_device_data_entry {
cfc32139 739 struct ipr_vpd vpd;
1da177e4 740 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 741 struct ipr_vpd new_vpd;
742 struct ipr_vpd ioa_last_with_dev_vpd;
743 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 744 __be32 ioa_data[5];
745}__attribute__((packed, aligned (4)));
746
ee0f05b8
BK		 747struct ipr_hostrcb_device_data_entry_enhanced {
748 struct ipr_ext_vpd vpd;
749 u8 ccin[4];
750 struct ipr_res_addr dev_res_addr;
751 struct ipr_ext_vpd new_vpd;
752 u8 new_ccin[4];
753 struct ipr_ext_vpd ioa_last_with_dev_vpd;
754 struct ipr_ext_vpd cfc_last_with_dev_vpd;
755}__attribute__((packed, aligned (4)));
756
4565e370
WB		 757struct ipr_hostrcb64_device_data_entry_enhanced {
758 struct ipr_ext_vpd vpd;
759 u8 ccin[4];
760 u8 res_path[8];
761 struct ipr_ext_vpd new_vpd;
762 u8 new_ccin[4];
763 struct ipr_ext_vpd ioa_last_with_dev_vpd;
764 struct ipr_ext_vpd cfc_last_with_dev_vpd;
765}__attribute__((packed, aligned (4)));
766
1da177e4 767struct ipr_hostrcb_array_data_entry {
cfc32139 768 struct ipr_vpd vpd;
1da177e4
LT		 769 struct ipr_res_addr expected_dev_res_addr;
770 struct ipr_res_addr dev_res_addr;
771}__attribute__((packed, aligned (4)));
772
4565e370
WB		 773struct ipr_hostrcb64_array_data_entry {
774 struct ipr_ext_vpd vpd;
775 u8 ccin[4];
776 u8 expected_res_path[8];
777 u8 res_path[8];
778}__attribute__((packed, aligned (4)));
779
ee0f05b8
BK		 780struct ipr_hostrcb_array_data_entry_enhanced {
781 struct ipr_ext_vpd vpd;
782 u8 ccin[4];
783 struct ipr_res_addr expected_dev_res_addr;
784 struct ipr_res_addr dev_res_addr;
785}__attribute__((packed, aligned (4)));
786
1da177e4 787struct ipr_hostrcb_type_ff_error {
ee0f05b8 788 __be32 ioa_data[502];
1da177e4
LT		 789}__attribute__((packed, aligned (4)));
790
791struct ipr_hostrcb_type_01_error {
792 __be32 seek_counter;
793 __be32 read_counter;
794 u8 sense_data[32];
795 __be32 ioa_data[236];
796}__attribute__((packed, aligned (4)));
797
798struct ipr_hostrcb_type_02_error {
cfc32139
BK		 799 struct ipr_vpd ioa_vpd;
800 struct ipr_vpd cfc_vpd;
801 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
802 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 803 __be32 ioa_data[3];
1da177e4
LT		 804}__attribute__((packed, aligned (4)));
805
ee0f05b8
BK		 806struct ipr_hostrcb_type_12_error {
807 struct ipr_ext_vpd ioa_vpd;
808 struct ipr_ext_vpd cfc_vpd;
809 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
810 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
811 __be32 ioa_data[3];
812}__attribute__((packed, aligned (4)));
813
1da177e4 814struct ipr_hostrcb_type_03_error {
cfc32139
BK		 815 struct ipr_vpd ioa_vpd;
816 struct ipr_vpd cfc_vpd;
1da177e4
LT		 817 __be32 errors_detected;
818 __be32 errors_logged;
819 u8 ioa_data[12];
cfc32139 820 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 821}__attribute__((packed, aligned (4)));
822
ee0f05b8
BK		 823struct ipr_hostrcb_type_13_error {
824 struct ipr_ext_vpd ioa_vpd;
825 struct ipr_ext_vpd cfc_vpd;
826 __be32 errors_detected;
827 __be32 errors_logged;
828 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
829}__attribute__((packed, aligned (4)));
830
4565e370
WB		 831struct ipr_hostrcb_type_23_error {
832 struct ipr_ext_vpd ioa_vpd;
833 struct ipr_ext_vpd cfc_vpd;
834 __be32 errors_detected;
835 __be32 errors_logged;
836 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
837}__attribute__((packed, aligned (4)));
838
1da177e4 839struct ipr_hostrcb_type_04_error {
cfc32139
BK		 840 struct ipr_vpd ioa_vpd;
841 struct ipr_vpd cfc_vpd;
1da177e4
LT		 842 u8 ioa_data[12];
843 struct ipr_hostrcb_array_data_entry array_member[10];
844 __be32 exposed_mode_adn;
845 __be32 array_id;
cfc32139 846 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 847 __be32 ioa_data2;
848 struct ipr_hostrcb_array_data_entry array_member2[8];
849 struct ipr_res_addr last_func_vset_res_addr;
850 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
851 u8 protection_level[8];
1da177e4
LT		 852}__attribute__((packed, aligned (4)));
853
ee0f05b8
BK		 854struct ipr_hostrcb_type_14_error {
855 struct ipr_ext_vpd ioa_vpd;
856 struct ipr_ext_vpd cfc_vpd;
857 __be32 exposed_mode_adn;
858 __be32 array_id;
859 struct ipr_res_addr last_func_vset_res_addr;
860 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
861 u8 protection_level[8];
862 __be32 num_entries;
863 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
864}__attribute__((packed, aligned (4)));
865
4565e370
WB		 866struct ipr_hostrcb_type_24_error {
867 struct ipr_ext_vpd ioa_vpd;
868 struct ipr_ext_vpd cfc_vpd;
869 u8 reserved[2];
870 u8 exposed_mode_adn;
871#define IPR_INVALID_ARRAY_DEV_NUM 0xff
872 u8 array_id;
873 u8 last_res_path[8];
874 u8 protection_level[8];
875 struct ipr_ext_vpd array_vpd;
876 u8 description[16];
877 u8 reserved2[3];
878 u8 num_entries;
879 struct ipr_hostrcb64_array_data_entry array_member[32];
880}__attribute__((packed, aligned (4)));
881
b0df54bb
BK		 882struct ipr_hostrcb_type_07_error {
883 u8 failure_reason[64];
884 struct ipr_vpd vpd;
885 u32 data[222];
886}__attribute__((packed, aligned (4)));
887
ee0f05b8
BK		 888struct ipr_hostrcb_type_17_error {
889 u8 failure_reason[64];
890 struct ipr_ext_vpd vpd;
891 u32 data[476];
892}__attribute__((packed, aligned (4)));
893
49dc6a18
BK		 894struct ipr_hostrcb_config_element {
895 u8 type_status;
896#define IPR_PATH_CFG_TYPE_MASK 0xF0
897#define IPR_PATH_CFG_NOT_EXIST 0x00
898#define IPR_PATH_CFG_IOA_PORT 0x10
899#define IPR_PATH_CFG_EXP_PORT 0x20
900#define IPR_PATH_CFG_DEVICE_PORT 0x30
901#define IPR_PATH_CFG_DEVICE_LUN 0x40
902
903#define IPR_PATH_CFG_STATUS_MASK 0x0F
904#define IPR_PATH_CFG_NO_PROB 0x00
905#define IPR_PATH_CFG_DEGRADED 0x01
906#define IPR_PATH_CFG_FAILED 0x02
907#define IPR_PATH_CFG_SUSPECT 0x03
908#define IPR_PATH_NOT_DETECTED 0x04
909#define IPR_PATH_INCORRECT_CONN 0x05
910
911 u8 cascaded_expander;
912 u8 phy;
913 u8 link_rate;
914#define IPR_PHY_LINK_RATE_MASK 0x0F
915
916 __be32 wwid[2];
917}__attribute__((packed, aligned (4)));
918
4565e370
WB		 919struct ipr_hostrcb64_config_element {
920 __be16 length;
921 u8 descriptor_id;
922#define IPR_DESCRIPTOR_MASK 0xC0
923#define IPR_DESCRIPTOR_SIS64 0x00
924
925 u8 reserved;
926 u8 type_status;
927
928 u8 reserved2[2];
929 u8 link_rate;
930
931 u8 res_path[8];
932 __be32 wwid[2];
933}__attribute__((packed, aligned (8)));
934
49dc6a18
BK		 935struct ipr_hostrcb_fabric_desc {
936 __be16 length;
937 u8 ioa_port;
938 u8 cascaded_expander;
939 u8 phy;
940 u8 path_state;
941#define IPR_PATH_ACTIVE_MASK 0xC0
942#define IPR_PATH_NO_INFO 0x00
943#define IPR_PATH_ACTIVE 0x40
944#define IPR_PATH_NOT_ACTIVE 0x80
945
946#define IPR_PATH_STATE_MASK 0x0F
947#define IPR_PATH_STATE_NO_INFO 0x00
948#define IPR_PATH_HEALTHY 0x01
949#define IPR_PATH_DEGRADED 0x02
950#define IPR_PATH_FAILED 0x03
951
952 __be16 num_entries;
953 struct ipr_hostrcb_config_element elem[1];
954}__attribute__((packed, aligned (4)));
955
4565e370
WB		 956struct ipr_hostrcb64_fabric_desc {
957 __be16 length;
958 u8 descriptor_id;
959
960 u8 reserved;
961 u8 path_state;
962
963 u8 reserved2[2];
964 u8 res_path[8];
965 u8 reserved3[6];
966 __be16 num_entries;
967 struct ipr_hostrcb64_config_element elem[1];
968}__attribute__((packed, aligned (8)));
969
49dc6a18
BK		 970#define for_each_fabric_cfg(fabric, cfg) \
971 for (cfg = (fabric)->elem; \
972 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
973 cfg++)
974
975struct ipr_hostrcb_type_20_error {
976 u8 failure_reason[64];
977 u8 reserved[3];
978 u8 num_entries;
979 struct ipr_hostrcb_fabric_desc desc[1];
980}__attribute__((packed, aligned (4)));
981
4565e370
WB		 982struct ipr_hostrcb_type_30_error {
983 u8 failure_reason[64];
984 u8 reserved[3];
985 u8 num_entries;
986 struct ipr_hostrcb64_fabric_desc desc[1];
987}__attribute__((packed, aligned (4)));
988
1da177e4 989struct ipr_hostrcb_error {
4565e370
WB		 990 __be32 fd_ioasc;
991 struct ipr_res_addr fd_res_addr;
992 __be32 fd_res_handle;
1da177e4
LT		 993 __be32 prc;
994 union {
995 struct ipr_hostrcb_type_ff_error type_ff_error;
996 struct ipr_hostrcb_type_01_error type_01_error;
997 struct ipr_hostrcb_type_02_error type_02_error;
998 struct ipr_hostrcb_type_03_error type_03_error;
999 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1000 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 1001 struct ipr_hostrcb_type_12_error type_12_error;
1002 struct ipr_hostrcb_type_13_error type_13_error;
1003 struct ipr_hostrcb_type_14_error type_14_error;
1004 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1005 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1006 } u;
1007}__attribute__((packed, aligned (4)));
1008
4565e370
WB		 1009struct ipr_hostrcb64_error {
1010 __be32 fd_ioasc;
1011 __be32 ioa_fw_level;
1012 __be32 fd_res_handle;
1013 __be32 prc;
1014 __be64 fd_dev_id;
1015 __be64 fd_lun;
1016 u8 fd_res_path[8];
1017 __be64 time_stamp;
1018 u8 reserved[2];
1019 union {
1020 struct ipr_hostrcb_type_ff_error type_ff_error;
1021 struct ipr_hostrcb_type_12_error type_12_error;
1022 struct ipr_hostrcb_type_17_error type_17_error;
1023 struct ipr_hostrcb_type_23_error type_23_error;
1024 struct ipr_hostrcb_type_24_error type_24_error;
1025 struct ipr_hostrcb_type_30_error type_30_error;
1026 } u;
1027}__attribute__((packed, aligned (8)));
1028
1da177e4
LT		 1029struct ipr_hostrcb_raw {
1030 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1031}__attribute__((packed, aligned (4)));
1032
1033struct ipr_hcam {
1034 u8 op_code;
1035#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1036#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1037
1038 u8 notify_type;
1039#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1040#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1041#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1042#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1043#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1044
1045 u8 notifications_lost;
1046#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1047#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1048
1049 u8 flags;
1050#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1051#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1052
1053 u8 overlay_id;
1054#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1055#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1056#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1057#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1058#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1059#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 1060#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1061#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1062#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1063#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1064#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1065#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1066#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1067#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1068#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1069#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1070#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1071
1072 u8 reserved1[3];
1073 __be32 ilid;
1074 __be32 time_since_last_ioa_reset;
1075 __be32 reserved2;
1076 __be32 length;
1077
1078 union {
1079 struct ipr_hostrcb_error error;
4565e370 1080 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1081 struct ipr_hostrcb_cfg_ch_not ccn;
1082 struct ipr_hostrcb_raw raw;
1083 } u;
1084}__attribute__((packed, aligned (4)));
1085
1086struct ipr_hostrcb {
1087 struct ipr_hcam hcam;
1088 dma_addr_t hostrcb_dma;
1089 struct list_head queue;
49dc6a18 1090 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1091 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1092};
1093
1094/* IPR smart dump table structures */
1095struct ipr_sdt_entry {
1096 __be32 bar_str_offset;
1097 __be32 end_offset;
1098 u8 entry_byte;
1099 u8 reserved[3];
1100
1101 u8 flags;
1102#define IPR_SDT_ENDIAN 0x80
1103#define IPR_SDT_VALID_ENTRY 0x20
1104
1105 u8 resv;
1106 __be16 priority;
1107}__attribute__((packed, aligned (4)));
1108
1109struct ipr_sdt_header {
1110 __be32 state;
1111 __be32 num_entries;
1112 __be32 num_entries_used;
1113 __be32 dump_size;
1114}__attribute__((packed, aligned (4)));
1115
1116struct ipr_sdt {
1117 struct ipr_sdt_header hdr;
1118 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1119}__attribute__((packed, aligned (4)));
1120
1121struct ipr_uc_sdt {
1122 struct ipr_sdt_header hdr;
1123 struct ipr_sdt_entry entry[1];
1124}__attribute__((packed, aligned (4)));
1125
1126/*
1127 * Driver types
1128 */
1129struct ipr_bus_attributes {
1130 u8 bus;
1131 u8 qas_enabled;
1132 u8 bus_width;
1133 u8 reserved;
1134 u32 max_xfer_rate;
1135};
1136
35a39691
BK		 1137struct ipr_sata_port {
1138 struct ipr_ioa_cfg *ioa_cfg;
1139 struct ata_port *ap;
1140 struct ipr_resource_entry *res;
1141 struct ipr_ioasa_gata ioasa;
1142};
1143
1da177e4 1144struct ipr_resource_entry {
1da177e4
LT		 1145 u8 needs_sync_complete:1;
1146 u8 in_erp:1;
1147 u8 add_to_ml:1;
1148 u8 del_from_ml:1;
1149 u8 resetting_device:1;
1150
3e7ebdfa
WB		 1151 u32 bus; /* AKA channel */
1152 u32 target; /* AKA id */
1153 u32 lun;
1154#define IPR_ARRAY_VIRTUAL_BUS 0x1
1155#define IPR_VSET_VIRTUAL_BUS 0x2
1156#define IPR_IOAFP_VIRTUAL_BUS 0x3
1157
1158#define IPR_GET_RES_PHYS_LOC(res) \
1159 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1160
1161 u8 ata_class;
1162
1163 u8 flags;
1164 __be16 res_flags;
1165
1166 __be32 type;
1167
1168 u8 qmodel;
1169 struct ipr_std_inq_data std_inq_data;
1170
1171 __be32 res_handle;
1172 __be64 dev_id;
1173 struct scsi_lun dev_lun;
1174 u8 res_path[8];
1175
1176 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1177 struct scsi_device *sdev;
35a39691 1178 struct ipr_sata_port *sata_port;
1da177e4 1179 struct list_head queue;
3e7ebdfa 1180}; /* struct ipr_resource_entry */
1da177e4
LT		 1181
1182struct ipr_resource_hdr {
1183 u16 num_entries;
1184 u16 reserved;
1185};
1186
1da177e4
LT		 1187struct ipr_misc_cbs {
1188 struct ipr_ioa_vpd ioa_vpd;
62275040 1189 struct ipr_inquiry_page0 page0_data;
1da177e4 1190 struct ipr_inquiry_page3 page3_data;
ac09c349 1191 struct ipr_inquiry_cap cap;
1da177e4
LT		 1192 struct ipr_mode_pages mode_pages;
1193 struct ipr_supported_device supp_dev;
1194};
1195
1196struct ipr_interrupt_offsets {
1197 unsigned long set_interrupt_mask_reg;
1198 unsigned long clr_interrupt_mask_reg;
1199 unsigned long sense_interrupt_mask_reg;
1200 unsigned long clr_interrupt_reg;
1201
1202 unsigned long sense_interrupt_reg;
1203 unsigned long ioarrin_reg;
1204 unsigned long sense_uproc_interrupt_reg;
1205 unsigned long set_uproc_interrupt_reg;
1206 unsigned long clr_uproc_interrupt_reg;
1207};
1208
1209struct ipr_interrupts {
1210 void __iomem *set_interrupt_mask_reg;
1211 void __iomem *clr_interrupt_mask_reg;
1212 void __iomem *sense_interrupt_mask_reg;
1213 void __iomem *clr_interrupt_reg;
1214
1215 void __iomem *sense_interrupt_reg;
1216 void __iomem *ioarrin_reg;
1217 void __iomem *sense_uproc_interrupt_reg;
1218 void __iomem *set_uproc_interrupt_reg;
1219 void __iomem *clr_uproc_interrupt_reg;
1220};
1221
1222struct ipr_chip_cfg_t {
1223 u32 mailbox;
1224 u8 cache_line_size;
1225 struct ipr_interrupt_offsets regs;
1226};
1227
1228struct ipr_chip_t {
1229 u16 vendor;
1230 u16 device;
1be7bd82
WB		 1231 u16 intr_type;
1232#define IPR_USE_LSI 0x00
1233#define IPR_USE_MSI 0x01
a32c055f
WB		 1234 u16 sis_type;
1235#define IPR_SIS32 0x00
1236#define IPR_SIS64 0x01
1da177e4
LT		 1237 const struct ipr_chip_cfg_t *cfg;
1238};
1239
1240enum ipr_shutdown_type {
1241 IPR_SHUTDOWN_NORMAL = 0x00,
1242 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1243 IPR_SHUTDOWN_ABBREV = 0x80,
1244 IPR_SHUTDOWN_NONE = 0x100
1245};
1246
1247struct ipr_trace_entry {
1248 u32 time;
1249
1250 u8 op_code;
35a39691 1251 u8 ata_op_code;
1da177e4
LT		 1252 u8 type;
1253#define IPR_TRACE_START 0x00
1254#define IPR_TRACE_FINISH 0xff
35a39691 1255 u8 cmd_index;
1da177e4
LT		 1256
1257 __be32 res_handle;
1258 union {
1259 u32 ioasc;
1260 u32 add_data;
1261 u32 res_addr;
1262 } u;
1263};
1264
1265struct ipr_sglist {
1266 u32 order;
1267 u32 num_sg;
12baa420 1268 u32 num_dma_sg;
1da177e4
LT		 1269 u32 buffer_len;
1270 struct scatterlist scatterlist[1];
1271};
1272
1273enum ipr_sdt_state {
1274 INACTIVE,
1275 WAIT_FOR_DUMP,
1276 GET_DUMP,
1277 ABORT_DUMP,
1278 DUMP_OBTAINED
1279};
1280
62275040
BK		 1281enum ipr_cache_state {
1282 CACHE_NONE,
1283 CACHE_DISABLED,
1284 CACHE_ENABLED,
1285 CACHE_INVALID
1286};
1287
1da177e4
LT		 1288/* Per-controller data */
1289struct ipr_ioa_cfg {
1290 char eye_catcher[8];
1291#define IPR_EYECATCHER "iprcfg"
1292
1293 struct list_head queue;
1294
1295 u8 allow_interrupts:1;
1296 u8 in_reset_reload:1;
1297 u8 in_ioa_bringdown:1;
1298 u8 ioa_unit_checked:1;
1299 u8 ioa_is_dead:1;
1300 u8 dump_taken:1;
1301 u8 allow_cmds:1;
1302 u8 allow_ml_add_del:1;
ce155cce 1303 u8 needs_hard_reset:1;
ac09c349 1304 u8 dual_raid:1;
463fc696 1305 u8 needs_warm_reset:1;
95fecd90 1306 u8 msi_received:1;
a32c055f 1307 u8 sis64:1;
463fc696
BK		 1308
1309 u8 revid;
1da177e4 1310
3e7ebdfa
WB		 1311 /*
1312 * Bitmaps for SIS64 generated target values
1313 */
1314 unsigned long *target_ids;
1315 unsigned long *array_ids;
1316 unsigned long *vset_ids;
1317
62275040 1318 enum ipr_cache_state cache_state;
1da177e4
LT		 1319 u16 type; /* CCIN of the card */
1320
1321 u8 log_level;
1322#define IPR_MAX_LOG_LEVEL 4
1323#define IPR_DEFAULT_LOG_LEVEL 2
1324
1325#define IPR_NUM_TRACE_INDEX_BITS 8
1326#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1327#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1328 char trace_start[8];
1329#define IPR_TRACE_START_LABEL "trace"
1330 struct ipr_trace_entry *trace;
1331 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1332
1333 /*
1334 * Queue for free command blocks
1335 */
1336 char ipr_free_label[8];
1337#define IPR_FREEQ_LABEL "free-q"
1338 struct list_head free_q;
1339
1340 /*
1341 * Queue for command blocks outstanding to the adapter
1342 */
1343 char ipr_pending_label[8];
1344#define IPR_PENDQ_LABEL "pend-q"
1345 struct list_head pending_q;
1346
1347 char cfg_table_start[8];
1348#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1349 union {
1350 struct ipr_config_table *cfg_table;
1351 struct ipr_config_table64 *cfg_table64;
1352 } u;
1da177e4 1353 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1354 u32 cfg_table_size;
1355 u32 max_devs_supported;
1da177e4
LT		 1356
1357 char resource_table_label[8];
1358#define IPR_RES_TABLE_LABEL "res_tbl"
1359 struct ipr_resource_entry *res_entries;
1360 struct list_head free_res_q;
1361 struct list_head used_res_q;
1362
1363 char ipr_hcam_label[8];
1364#define IPR_HCAM_LABEL "hcams"
1365 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1366 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1367 struct list_head hostrcb_free_q;
1368 struct list_head hostrcb_pending_q;
1369
1370 __be32 *host_rrq;
1371 dma_addr_t host_rrq_dma;
1372#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1373#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1374#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1375#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1376 volatile __be32 *hrrq_start;
1377 volatile __be32 *hrrq_end;
1378 volatile __be32 *hrrq_curr;
1379 volatile u32 toggle_bit;
1380
1381 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1382
5469cb5b 1383 unsigned int transop_timeout;
1da177e4 1384 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1385 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1386
1387 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1388 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1389 void __iomem *ioa_mailbox;
1390 struct ipr_interrupts regs;
1391
1392 u16 saved_pcix_cmd_reg;
1393 u16 reset_retries;
1394
1395 u32 errors_logged;
3d1d0da6 1396 u32 doorbell;
1da177e4
LT		 1397
1398 struct Scsi_Host *host;
1399 struct pci_dev *pdev;
1400 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1401 u8 saved_mode_page_len;
1402
1403 struct work_struct work_q;
1404
1405 wait_queue_head_t reset_wait_q;
95fecd90 1406 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1407
1408 struct ipr_dump *dump;
1409 enum ipr_sdt_state sdt_state;
1410
1411 struct ipr_misc_cbs *vpd_cbs;
1412 dma_addr_t vpd_cbs_dma;
1413
1414 struct pci_pool *ipr_cmd_pool;
1415
1416 struct ipr_cmnd *reset_cmd;
463fc696 1417 int (*reset) (struct ipr_cmnd *);
1da177e4 1418
35a39691 1419 struct ata_host ata_host;
1da177e4 1420 char ipr_cmd_label[8];
0124ca9d 1421#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1422 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1423 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1424}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1425
1426struct ipr_cmnd {
1427 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1428 union {
1429 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1430 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1431 struct ipr_ata64_ioadl ata_ioadl;
1432 } i;
1da177e4 1433 struct ipr_ioasa ioasa;
1da177e4
LT		 1434 struct list_head queue;
1435 struct scsi_cmnd *scsi_cmd;
35a39691 1436 struct ata_queued_cmd *qc;
1da177e4
LT		 1437 struct completion completion;
1438 struct timer_list timer;
1439 void (*done) (struct ipr_cmnd *);
1440 int (*job_step) (struct ipr_cmnd *);
dfed823e 1441 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1442 u16 cmd_index;
1443 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1444 dma_addr_t sense_buffer_dma;
1445 unsigned short dma_use_sg;
a32c055f 1446 dma_addr_t dma_addr;
1da177e4
LT		 1447 struct ipr_cmnd *sibling;
1448 union {
1449 enum ipr_shutdown_type shutdown_type;
1450 struct ipr_hostrcb *hostrcb;
1451 unsigned long time_left;
1452 unsigned long scratch;
1453 struct ipr_resource_entry *res;
1454 struct scsi_device *sdev;
1455 } u;
1456
1457 struct ipr_ioa_cfg *ioa_cfg;
1458};
1459
1460struct ipr_ses_table_entry {
1461 char product_id[17];
1462 char compare_product_id_byte[17];
1463 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1464};
1465
1466struct ipr_dump_header {
1467 u32 eye_catcher;
1468#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1469 u32 len;
1470 u32 num_entries;
1471 u32 first_entry_offset;
1472 u32 status;
1473#define IPR_DUMP_STATUS_SUCCESS 0
1474#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1475#define IPR_DUMP_STATUS_FAILED 0xffffffff
1476 u32 os;
1477#define IPR_DUMP_OS_LINUX 0x4C4E5558
1478 u32 driver_name;
1479#define IPR_DUMP_DRIVER_NAME 0x49505232
1480}__attribute__((packed, aligned (4)));
1481
1482struct ipr_dump_entry_header {
1483 u32 eye_catcher;
1484#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1485 u32 len;
1486 u32 num_elems;
1487 u32 offset;
1488 u32 data_type;
1489#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1490#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1491 u32 id;
1492#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1493#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1494#define IPR_DUMP_TRACE_ID 0x54524143
1495#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1496#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1497#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1498#define IPR_DUMP_PEND_OPS 0x414F5053
1499 u32 status;
1500}__attribute__((packed, aligned (4)));
1501
1502struct ipr_dump_location_entry {
1503 struct ipr_dump_entry_header hdr;
71610f55 1504 u8 location[20];
1da177e4
LT		 1505}__attribute__((packed));
1506
1507struct ipr_dump_trace_entry {
1508 struct ipr_dump_entry_header hdr;
1509 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1510}__attribute__((packed, aligned (4)));
1511
1512struct ipr_dump_version_entry {
1513 struct ipr_dump_entry_header hdr;
1514 u8 version[sizeof(IPR_DRIVER_VERSION)];
1515};
1516
1517struct ipr_dump_ioa_type_entry {
1518 struct ipr_dump_entry_header hdr;
1519 u32 type;
1520 u32 fw_version;
1521};
1522
1523struct ipr_driver_dump {
1524 struct ipr_dump_header hdr;
1525 struct ipr_dump_version_entry version_entry;
1526 struct ipr_dump_location_entry location_entry;
1527 struct ipr_dump_ioa_type_entry ioa_type_entry;
1528 struct ipr_dump_trace_entry trace_entry;
1529}__attribute__((packed));
1530
1531struct ipr_ioa_dump {
1532 struct ipr_dump_entry_header hdr;
1533 struct ipr_sdt sdt;
1534 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1535 u32 reserved;
1536 u32 next_page_index;
1537 u32 page_offset;
1538 u32 format;
1539#define IPR_SDT_FMT2 2
1540#define IPR_SDT_UNKNOWN 3
1541}__attribute__((packed, aligned (4)));
1542
1543struct ipr_dump {
1544 struct kref kref;
1545 struct ipr_ioa_cfg *ioa_cfg;
1546 struct ipr_driver_dump driver_dump;
1547 struct ipr_ioa_dump ioa_dump;
1548};
1549
1550struct ipr_error_table_t {
1551 u32 ioasc;
1552 int log_ioasa;
1553 int log_hcam;
1554 char *error;
1555};
1556
1557struct ipr_software_inq_lid_info {
1558 __be32 load_id;
1559 __be32 timestamp[3];
1560}__attribute__((packed, aligned (4)));
1561
1562struct ipr_ucode_image_header {
1563 __be32 header_length;
1564 __be32 lid_table_offset;
1565 u8 major_release;
1566 u8 card_type;
1567 u8 minor_release[2];
1568 u8 reserved[20];
1569 char eyecatcher[16];
1570 __be32 num_lids;
1571 struct ipr_software_inq_lid_info lid[1];
1572}__attribute__((packed, aligned (4)));
1573
1574/*
1575 * Macros
1576 */
d3c74871 1577#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1578
1579#ifdef CONFIG_SCSI_IPR_TRACE
1580#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1581#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1582#else
1583#define ipr_create_trace_file(kobj, attr) 0
1584#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1585#endif
1586
1587#ifdef CONFIG_SCSI_IPR_DUMP
1588#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1589#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1590#else
1591#define ipr_create_dump_file(kobj, attr) 0
1592#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1593#endif
1594
1595/*
1596 * Error logging macros
1597 */
1598#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1599#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1600#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1601
3e7ebdfa
WB		 1602#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1603 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1604 bus, target, lun, ##__VA_ARGS__)
1605
1606#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1607 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1608
fb3ed3cb
BK		 1609#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1610 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1611 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1612
fb3ed3cb
BK		 1613#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1614 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1615
fa15b1f6
BK		 1616#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1617{ \
1618 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1619 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1620 } else { \
1621 ipr_err(fmt": %d:%d:%d:%d\n", \
1622 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1623 (res).bus, (res).target, (res).lun); \
1624 } \
1625}
1626
49dc6a18 1627#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1628{ \
1629 if (ipr_is_device(hostrcb)) { \
1630 if ((hostrcb)->ioa_cfg->sis64) { \
1631 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1632 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1633 &hostrcb->rp_buffer[0]), \
1634 __VA_ARGS__); \
1635 } else { \
1636 ipr_ra_err((hostrcb)->ioa_cfg, \
1637 (hostrcb)->hcam.u.error.fd_res_addr, \
1638 fmt, __VA_ARGS__); \
1639 } \
1640 } else { \
1641 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1642 } \
49dc6a18
BK		 1643}
1644
1da177e4 1645#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1646 __FILE__, __func__, __LINE__)
1da177e4 1647
cadbd4a5
HH		 1648#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1649#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1650
1651#define ipr_err_separator \
1652ipr_err("----------------------------------------------------------\n")
1653
1654
1655/*
1656 * Inlines
1657 */
1658
1659/**
1660 * ipr_is_ioa_resource - Determine if a resource is the IOA
1661 * @res: resource entry struct
1662 *
1663 * Return value:
1664 * 1 if IOA / 0 if not IOA
1665 **/
1666static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1667{
3e7ebdfa 1668 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1669}
1670
1671/**
1672 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1673 * @res: resource entry struct
1674 *
1675 * Return value:
1676 * 1 if AF DASD / 0 if not AF DASD
1677 **/
1678static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1679{
3e7ebdfa
WB		 1680 return res->type == IPR_RES_TYPE_AF_DASD ||
1681 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1682}
1683
1684/**
1685 * ipr_is_vset_device - Determine if a resource is a VSET
1686 * @res: resource entry struct
1687 *
1688 * Return value:
1689 * 1 if VSET / 0 if not VSET
1690 **/
1691static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1692{
3e7ebdfa 1693 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1694}
1695
1696/**
1697 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1698 * @res: resource entry struct
1699 *
1700 * Return value:
1701 * 1 if GSCSI / 0 if not GSCSI
1702 **/
1703static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1704{
3e7ebdfa 1705 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1706}
1707
e4fbf44e
BK		 1708/**
1709 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1710 * @res: resource entry struct
1711 *
1712 * Return value:
1713 * 1 if SCSI disk / 0 if not SCSI disk
1714 **/
1715static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1716{
1717 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1718 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1719 return 1;
1720 else
1721 return 0;
1722}
1723
b5145d25
BK		 1724/**
1725 * ipr_is_gata - Determine if a resource is a generic ATA resource
1726 * @res: resource entry struct
1727 *
1728 * Return value:
1729 * 1 if GATA / 0 if not GATA
1730 **/
1731static inline int ipr_is_gata(struct ipr_resource_entry *res)
1732{
3e7ebdfa 1733 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1734}
1735
ee0a90fa
BK		 1736/**
1737 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1738 * @res: resource entry struct
1739 *
1740 * Return value:
1741 * 1 if NACA queueing model / 0 if not NACA queueing model
1742 **/
1743static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1744{
3e7ebdfa 1745 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK		 1746 return 1;
1747 return 0;
1748}
1749
1da177e4 1750/**
4565e370
WB		 1751 * ipr_is_device - Determine if the hostrcb structure is related to a device
1752 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1753 *
1754 * Return value:
1755 * 1 if AF / 0 if not AF
1756 **/
4565e370 1757static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1758{
4565e370
WB		 1759 struct ipr_res_addr *res_addr;
1760 u8 *res_path;
1761
1762 if (hostrcb->ioa_cfg->sis64) {
1763 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1764 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1765 res_path[0] == 0x81) && res_path[2] != 0xFF)
1766 return 1;
1767 } else {
1768 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1769
1770 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1771 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1772 return 1;
1773 }
1da177e4
LT		 1774 return 0;
1775}
1776
1777/**
1778 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1779 * @sdt_word: SDT address
1780 *
1781 * Return value:
1782 * 1 if format 2 / 0 if not
1783 **/
1784static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1785{
1786 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1787
1788 switch (bar_sel) {
1789 case IPR_SDT_FMT2_BAR0_SEL:
1790 case IPR_SDT_FMT2_BAR1_SEL:
1791 case IPR_SDT_FMT2_BAR2_SEL:
1792 case IPR_SDT_FMT2_BAR3_SEL:
1793 case IPR_SDT_FMT2_BAR4_SEL:
1794 case IPR_SDT_FMT2_BAR5_SEL:
1795 case IPR_SDT_FMT2_EXP_ROM_SEL:
1796 return 1;
1797 };
1798
1799 return 0;
1800}
1801
1802#endif
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