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[SCSI] ipr: add support for new IOASCs
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
95fecd90
WB		 40#define IPR_DRIVER_VERSION "2.4.3"
41#define IPR_DRIVER_DATE "(June 10, 2009)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 115#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 116
ac719aba 117#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 118#define IPR_NUM_LOG_HCAMS 2
119#define IPR_NUM_CFG_CHG_HCAMS 2
120#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 121
122#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
123#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
124
d71a8b0c 125#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 126#define IPR_MAX_NUM_LUNS_PER_TARGET 256
127#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
128#define IPR_VSET_BUS 0xff
129#define IPR_IOA_BUS 0xff
130#define IPR_IOA_TARGET 0xff
131#define IPR_IOA_LUN 0xff
b5145d25 132#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 133#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
134
135#define IPR_NUM_RESET_RELOAD_RETRIES 3
136
137/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
138#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 139 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4
LT		 140
141#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
142#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
143 IPR_NUM_INTERNAL_CMD_BLKS)
144
145#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 146#define IPR_DEFAULT_SIS64_DEVS 1024
147#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 148
149#define IPR_MAX_SGLIST 64
150#define IPR_IOA_MAX_SECTORS 32767
151#define IPR_VSET_MAX_SECTORS 512
152#define IPR_MAX_CDB_LEN 16
3feeb89d 153#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 154
155#define IPR_DEFAULT_BUS_WIDTH 16
156#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
157#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
158#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
159#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
160
161#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 162#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 163#define IPR_IOA_RES_ADDR 0x00ffffff
164
165/*
166 * Adapter Commands
167 */
168#define IPR_QUERY_RSRC_STATE 0xC2
169#define IPR_RESET_DEVICE 0xC3
170#define IPR_RESET_TYPE_SELECT 0x80
171#define IPR_LUN_RESET 0x40
172#define IPR_TARGET_RESET 0x20
173#define IPR_BUS_RESET 0x10
b5145d25 174#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 175#define IPR_ID_HOST_RR_Q 0xC4
176#define IPR_QUERY_IOA_CONFIG 0xC5
177#define IPR_CANCEL_ALL_REQUESTS 0xCE
178#define IPR_HOST_CONTROLLED_ASYNC 0xCF
179#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
180#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
181#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 182#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 183#define IPR_IOA_SHUTDOWN 0xF7
184#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
185
186/*
187 * Timeouts
188 */
189#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
190#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
191#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 192#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 193#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
194#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
195#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
196#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
197#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
198#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
199#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
200#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 201#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 202#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
203#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
204#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 205#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 206#define IPR_DUMP_TIMEOUT (15 * HZ)
207
208/*
209 * SCSI Literals
210 */
211#define IPR_VENDOR_ID_LEN 8
212#define IPR_PROD_ID_LEN 16
213#define IPR_SERIAL_NUM_LEN 8
214
215/*
216 * Hardware literals
217 */
218#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
219#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
220#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
221#define IPR_GET_FMT2_BAR_SEL(mbx) \
222(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
223#define IPR_SDT_FMT2_BAR0_SEL 0x0
224#define IPR_SDT_FMT2_BAR1_SEL 0x1
225#define IPR_SDT_FMT2_BAR2_SEL 0x2
226#define IPR_SDT_FMT2_BAR3_SEL 0x3
227#define IPR_SDT_FMT2_BAR4_SEL 0x4
228#define IPR_SDT_FMT2_BAR5_SEL 0x5
229#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
230#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 231#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 232#define IPR_DOORBELL 0x82800000
3d1d0da6 233#define IPR_RUNTIME_RESET 0x40000000
1da177e4 234
214777ba
WB		 235#define IPR_IPL_INIT_MIN_STAGE_TIME 5
236#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
237#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
238#define IPR_IPL_INIT_STAGE_MASK 0xff000000
239#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
240#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
241
1da177e4
LT		 242#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
243#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
244#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
245#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
246#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
247#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
248#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
249#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
250#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
251#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
252#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
253
254#define IPR_PCII_ERROR_INTERRUPTS \
255(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
256IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
257
258#define IPR_PCII_OPER_INTERRUPTS \
259(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
260
261#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
262#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
263
264#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
265#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
266
267/*
268 * Dump literals
269 */
270#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
271#define IPR_NUM_SDT_ENTRIES 511
272#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
273
274/*
275 * Misc literals
276 */
277#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
278
279/*
280 * Adapter interface types
281 */
282
283struct ipr_res_addr {
284 u8 reserved;
285 u8 bus;
286 u8 target;
287 u8 lun;
288#define IPR_GET_PHYS_LOC(res_addr) \
289 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
290}__attribute__((packed, aligned (4)));
291
292struct ipr_std_inq_vpids {
293 u8 vendor_id[IPR_VENDOR_ID_LEN];
294 u8 product_id[IPR_PROD_ID_LEN];
295}__attribute__((packed));
296
cfc32139
BK		 297struct ipr_vpd {
298 struct ipr_std_inq_vpids vpids;
299 u8 sn[IPR_SERIAL_NUM_LEN];
300}__attribute__((packed));
301
ee0f05b8
BK		 302struct ipr_ext_vpd {
303 struct ipr_vpd vpd;
304 __be32 wwid[2];
305}__attribute__((packed));
306
1da177e4
LT		 307struct ipr_std_inq_data {
308 u8 peri_qual_dev_type;
309#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
310#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
311
312 u8 removeable_medium_rsvd;
313#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
314
315#define IPR_IS_DASD_DEVICE(std_inq) \
316((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
317!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
318
319#define IPR_IS_SES_DEVICE(std_inq) \
320(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
321
322 u8 version;
323 u8 aen_naca_fmt;
324 u8 additional_len;
325 u8 sccs_rsvd;
326 u8 bq_enc_multi;
327 u8 sync_cmdq_flags;
328
329 struct ipr_std_inq_vpids vpids;
330
331 u8 ros_rsvd_ram_rsvd[4];
332
333 u8 serial_num[IPR_SERIAL_NUM_LEN];
334}__attribute__ ((packed));
335
3e7ebdfa
WB		 336#define IPR_RES_TYPE_AF_DASD 0x00
337#define IPR_RES_TYPE_GENERIC_SCSI 0x01
338#define IPR_RES_TYPE_VOLUME_SET 0x02
339#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
340#define IPR_RES_TYPE_GENERIC_ATA 0x04
341#define IPR_RES_TYPE_ARRAY 0x05
342#define IPR_RES_TYPE_IOAFP 0xff
343
1da177e4 344struct ipr_config_table_entry {
b5145d25
BK		 345 u8 proto;
346#define IPR_PROTO_SATA 0x02
347#define IPR_PROTO_SATA_ATAPI 0x03
348#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 349#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 350 u8 array_id;
351 u8 flags;
3e7ebdfa 352#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 353 u8 rsvd_subtype;
3e7ebdfa
WB		 354
355#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
356#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK		 357#define IPR_QUEUE_NACA_MODEL 1
358
1da177e4
LT		 359 struct ipr_res_addr res_addr;
360 __be32 res_handle;
361 __be32 reserved4[2];
362 struct ipr_std_inq_data std_inq_data;
363}__attribute__ ((packed, aligned (4)));
364
3e7ebdfa
WB		 365struct ipr_config_table_entry64 {
366 u8 res_type;
367 u8 proto;
368 u8 vset_num;
369 u8 array_id;
370 __be16 flags;
371 __be16 res_flags;
372#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
373 __be32 res_handle;
374 u8 dev_id_type;
375 u8 reserved[3];
376 __be64 dev_id;
377 __be64 lun;
378 __be64 lun_wwn[2];
379#define IPR_MAX_RES_PATH_LENGTH 24
380 __be64 res_path;
381 struct ipr_std_inq_data std_inq_data;
382 u8 reserved2[4];
383 __be64 reserved3[2]; // description text
384 u8 reserved4[8];
385}__attribute__ ((packed, aligned (8)));
386
1da177e4
LT		 387struct ipr_config_table_hdr {
388 u8 num_entries;
389 u8 flags;
390#define IPR_UCODE_DOWNLOAD_REQ 0x10
391 __be16 reserved;
392}__attribute__((packed, aligned (4)));
393
3e7ebdfa
WB		 394struct ipr_config_table_hdr64 {
395 __be16 num_entries;
396 __be16 reserved;
397 u8 flags;
398 u8 reserved2[11];
399}__attribute__((packed, aligned (4)));
400
1da177e4
LT		 401struct ipr_config_table {
402 struct ipr_config_table_hdr hdr;
3e7ebdfa 403 struct ipr_config_table_entry dev[0];
1da177e4
LT		 404}__attribute__((packed, aligned (4)));
405
3e7ebdfa
WB		 406struct ipr_config_table64 {
407 struct ipr_config_table_hdr64 hdr64;
408 struct ipr_config_table_entry64 dev[0];
409}__attribute__((packed, aligned (8)));
410
411struct ipr_config_table_entry_wrapper {
412 union {
413 struct ipr_config_table_entry *cfgte;
414 struct ipr_config_table_entry64 *cfgte64;
415 } u;
416};
417
1da177e4 418struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 419 union {
420 struct ipr_config_table_entry cfgte;
421 struct ipr_config_table_entry64 cfgte64;
422 } u;
1da177e4
LT		 423 u8 reserved[936];
424}__attribute__((packed, aligned (4)));
425
426struct ipr_supported_device {
427 __be16 data_length;
428 u8 reserved;
429 u8 num_records;
430 struct ipr_std_inq_vpids vpids;
431 u8 reserved2[16];
432}__attribute__((packed, aligned (4)));
433
434/* Command packet structure */
435struct ipr_cmd_pkt {
436 __be16 reserved; /* Reserved by IOA */
437 u8 request_type;
438#define IPR_RQTYPE_SCSICDB 0x00
439#define IPR_RQTYPE_IOACMD 0x01
440#define IPR_RQTYPE_HCAM 0x02
b5145d25 441#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 442
a32c055f 443 u8 reserved2;
1da177e4
LT		 444
445 u8 flags_hi;
446#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
447#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
448#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
449#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
450#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
451
452 u8 flags_lo;
453#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
454#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
455#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
456#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
457#define IPR_FLAGS_LO_ORDERED_TASK 0x04
458#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
459#define IPR_FLAGS_LO_ACA_TASK 0x08
460
461 u8 cdb[16];
462 __be16 timeout;
463}__attribute__ ((packed, aligned(4)));
464
a32c055f 465struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 466 u8 flags;
467#define IPR_ATA_FLAG_PACKET_CMD 0x80
468#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
469#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
470 u8 reserved[3];
471
472 __be16 data;
473 u8 feature;
474 u8 nsect;
475 u8 lbal;
476 u8 lbam;
477 u8 lbah;
478 u8 device;
479 u8 command;
480 u8 reserved2[3];
481 u8 hob_feature;
482 u8 hob_nsect;
483 u8 hob_lbal;
484 u8 hob_lbam;
485 u8 hob_lbah;
486 u8 ctl;
487}__attribute__ ((packed, aligned(4)));
488
51b1c7e1
BK		 489struct ipr_ioadl_desc {
490 __be32 flags_and_data_len;
491#define IPR_IOADL_FLAGS_MASK 0xff000000
492#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
493#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
494#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
495#define IPR_IOADL_FLAGS_READ 0x48000000
496#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
497#define IPR_IOADL_FLAGS_WRITE 0x68000000
498#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
499#define IPR_IOADL_FLAGS_LAST 0x01000000
500
501 __be32 address;
502}__attribute__((packed, aligned (8)));
503
a32c055f
WB		 504struct ipr_ioadl64_desc {
505 __be32 flags;
506 __be32 data_len;
507 __be64 address;
508}__attribute__((packed, aligned (16)));
509
510struct ipr_ata64_ioadl {
511 struct ipr_ioarcb_ata_regs regs;
512 u16 reserved[5];
513 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
514}__attribute__((packed, aligned (16)));
515
b5145d25
BK		 516struct ipr_ioarcb_add_data {
517 union {
518 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 519 struct ipr_ioadl_desc ioadl[5];
b5145d25 520 __be32 add_cmd_parms[10];
a32c055f
WB		 521 } u;
522}__attribute__ ((packed, aligned (4)));
523
524struct ipr_ioarcb_sis64_add_addr_ecb {
525 __be64 ioasa_host_pci_addr;
526 __be64 data_ioadl_addr;
527 __be64 reserved;
528 __be32 ext_control_buf[4];
529}__attribute__((packed, aligned (8)));
b5145d25 530
1da177e4
LT		 531/* IOA Request Control Block 128 bytes */
532struct ipr_ioarcb {
a32c055f
WB		 533 union {
534 __be32 ioarcb_host_pci_addr;
535 __be64 ioarcb_host_pci_addr64;
536 } a;
1da177e4
LT		 537 __be32 res_handle;
538 __be32 host_response_handle;
539 __be32 reserved1;
540 __be32 reserved2;
541 __be32 reserved3;
542
a32c055f 543 __be32 data_transfer_length;
1da177e4
LT		 544 __be32 read_data_transfer_length;
545 __be32 write_ioadl_addr;
a32c055f 546 __be32 ioadl_len;
1da177e4
LT		 547 __be32 read_ioadl_addr;
548 __be32 read_ioadl_len;
549
550 __be32 ioasa_host_pci_addr;
551 __be16 ioasa_len;
552 __be16 reserved4;
553
554 struct ipr_cmd_pkt cmd_pkt;
555
a32c055f
WB		 556 __be16 add_cmd_parms_offset;
557 __be16 add_cmd_parms_len;
558
559 union {
560 struct ipr_ioarcb_add_data add_data;
561 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
562 } u;
563
1da177e4
LT		 564}__attribute__((packed, aligned (4)));
565
1da177e4
LT		 566struct ipr_ioasa_vset {
567 __be32 failing_lba_hi;
568 __be32 failing_lba_lo;
c8f74892 569 __be32 reserved;
1da177e4
LT		 570}__attribute__((packed, aligned (4)));
571
572struct ipr_ioasa_af_dasd {
573 __be32 failing_lba;
c8f74892 574 __be32 reserved[2];
1da177e4
LT		 575}__attribute__((packed, aligned (4)));
576
577struct ipr_ioasa_gpdd {
578 u8 end_state;
579 u8 bus_phase;
580 __be16 reserved;
c8f74892 581 __be32 ioa_data[2];
1da177e4
LT		 582}__attribute__((packed, aligned (4)));
583
b5145d25
BK		 584struct ipr_ioasa_gata {
585 u8 error;
586 u8 nsect; /* Interrupt reason */
587 u8 lbal;
588 u8 lbam;
589 u8 lbah;
590 u8 device;
591 u8 status;
592 u8 alt_status; /* ATA CTL */
593 u8 hob_nsect;
594 u8 hob_lbal;
595 u8 hob_lbam;
596 u8 hob_lbah;
597}__attribute__((packed, aligned (4)));
598
c8f74892
BK		 599struct ipr_auto_sense {
600 __be16 auto_sense_len;
601 __be16 ioa_data_len;
602 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
603};
1da177e4
LT		 604
605struct ipr_ioasa {
606 __be32 ioasc;
607#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
608#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
609#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
610#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
611
612 __be16 ret_stat_len; /* Length of the returned IOASA */
613
614 __be16 avail_stat_len; /* Total Length of status available. */
615
616 __be32 residual_data_len; /* number of bytes in the host data */
617 /* buffers that were not used by the IOARCB command. */
618
619 __be32 ilid;
620#define IPR_NO_ILID 0
621#define IPR_DRIVER_ILID 0xffffffff
622
623 __be32 fd_ioasc;
624
625 __be32 fd_phys_locator;
626
627 __be32 fd_res_handle;
628
629 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 630#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
631#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 632#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 633#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
634#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
635#define IPR_FIELD_POINTER_MASK 0x0000ffff
636
637 union {
638 struct ipr_ioasa_vset vset;
639 struct ipr_ioasa_af_dasd dasd;
640 struct ipr_ioasa_gpdd gpdd;
b5145d25 641 struct ipr_ioasa_gata gata;
1da177e4 642 } u;
c8f74892
BK		 643
644 struct ipr_auto_sense auto_sense;
1da177e4
LT		 645}__attribute__((packed, aligned (4)));
646
647struct ipr_mode_parm_hdr {
648 u8 length;
649 u8 medium_type;
650 u8 device_spec_parms;
651 u8 block_desc_len;
652}__attribute__((packed));
653
654struct ipr_mode_pages {
655 struct ipr_mode_parm_hdr hdr;
656 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
657}__attribute__((packed));
658
659struct ipr_mode_page_hdr {
660 u8 ps_page_code;
661#define IPR_MODE_PAGE_PS 0x80
662#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
663 u8 page_length;
664}__attribute__ ((packed));
665
666struct ipr_dev_bus_entry {
667 struct ipr_res_addr res_addr;
668 u8 flags;
669#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
670#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
671#define IPR_SCSI_ATTR_QAS_MASK 0xC0
672#define IPR_SCSI_ATTR_ENABLE_TM 0x20
673#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
674#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
675#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
676
677 u8 scsi_id;
678 u8 bus_width;
679 u8 extended_reset_delay;
680#define IPR_EXTENDED_RESET_DELAY 7
681
682 __be32 max_xfer_rate;
683
684 u8 spinup_delay;
685 u8 reserved3;
686 __be16 reserved4;
687}__attribute__((packed, aligned (4)));
688
689struct ipr_mode_page28 {
690 struct ipr_mode_page_hdr hdr;
691 u8 num_entries;
692 u8 entry_length;
693 struct ipr_dev_bus_entry bus[0];
694}__attribute__((packed));
695
ac09c349
BK		 696struct ipr_mode_page24 {
697 struct ipr_mode_page_hdr hdr;
698 u8 flags;
699#define IPR_ENABLE_DUAL_IOA_AF 0x80
700}__attribute__((packed));
701
1da177e4
LT		 702struct ipr_ioa_vpd {
703 struct ipr_std_inq_data std_inq_data;
704 u8 ascii_part_num[12];
705 u8 reserved[40];
706 u8 ascii_plant_code[4];
707}__attribute__((packed));
708
709struct ipr_inquiry_page3 {
710 u8 peri_qual_dev_type;
711 u8 page_code;
712 u8 reserved1;
713 u8 page_length;
714 u8 ascii_len;
715 u8 reserved2[3];
716 u8 load_id[4];
717 u8 major_release;
718 u8 card_type;
719 u8 minor_release[2];
720 u8 ptf_number[4];
721 u8 patch_number[4];
722}__attribute__((packed));
723
ac09c349
BK		 724struct ipr_inquiry_cap {
725 u8 peri_qual_dev_type;
726 u8 page_code;
727 u8 reserved1;
728 u8 page_length;
729 u8 ascii_len;
730 u8 reserved2;
731 u8 sis_version[2];
732 u8 cap;
733#define IPR_CAP_DUAL_IOA_RAID 0x80
734 u8 reserved3[15];
735}__attribute__((packed));
736
62275040
BK		 737#define IPR_INQUIRY_PAGE0_ENTRIES 20
738struct ipr_inquiry_page0 {
739 u8 peri_qual_dev_type;
740 u8 page_code;
741 u8 reserved1;
742 u8 len;
743 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
744}__attribute__((packed));
745
1da177e4 746struct ipr_hostrcb_device_data_entry {
cfc32139 747 struct ipr_vpd vpd;
1da177e4 748 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 749 struct ipr_vpd new_vpd;
750 struct ipr_vpd ioa_last_with_dev_vpd;
751 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 752 __be32 ioa_data[5];
753}__attribute__((packed, aligned (4)));
754
ee0f05b8
BK		 755struct ipr_hostrcb_device_data_entry_enhanced {
756 struct ipr_ext_vpd vpd;
757 u8 ccin[4];
758 struct ipr_res_addr dev_res_addr;
759 struct ipr_ext_vpd new_vpd;
760 u8 new_ccin[4];
761 struct ipr_ext_vpd ioa_last_with_dev_vpd;
762 struct ipr_ext_vpd cfc_last_with_dev_vpd;
763}__attribute__((packed, aligned (4)));
764
4565e370
WB		 765struct ipr_hostrcb64_device_data_entry_enhanced {
766 struct ipr_ext_vpd vpd;
767 u8 ccin[4];
768 u8 res_path[8];
769 struct ipr_ext_vpd new_vpd;
770 u8 new_ccin[4];
771 struct ipr_ext_vpd ioa_last_with_dev_vpd;
772 struct ipr_ext_vpd cfc_last_with_dev_vpd;
773}__attribute__((packed, aligned (4)));
774
1da177e4 775struct ipr_hostrcb_array_data_entry {
cfc32139 776 struct ipr_vpd vpd;
1da177e4
LT		 777 struct ipr_res_addr expected_dev_res_addr;
778 struct ipr_res_addr dev_res_addr;
779}__attribute__((packed, aligned (4)));
780
4565e370
WB		 781struct ipr_hostrcb64_array_data_entry {
782 struct ipr_ext_vpd vpd;
783 u8 ccin[4];
784 u8 expected_res_path[8];
785 u8 res_path[8];
786}__attribute__((packed, aligned (4)));
787
ee0f05b8
BK		 788struct ipr_hostrcb_array_data_entry_enhanced {
789 struct ipr_ext_vpd vpd;
790 u8 ccin[4];
791 struct ipr_res_addr expected_dev_res_addr;
792 struct ipr_res_addr dev_res_addr;
793}__attribute__((packed, aligned (4)));
794
1da177e4 795struct ipr_hostrcb_type_ff_error {
ee0f05b8 796 __be32 ioa_data[502];
1da177e4
LT		 797}__attribute__((packed, aligned (4)));
798
799struct ipr_hostrcb_type_01_error {
800 __be32 seek_counter;
801 __be32 read_counter;
802 u8 sense_data[32];
803 __be32 ioa_data[236];
804}__attribute__((packed, aligned (4)));
805
806struct ipr_hostrcb_type_02_error {
cfc32139
BK		 807 struct ipr_vpd ioa_vpd;
808 struct ipr_vpd cfc_vpd;
809 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
810 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 811 __be32 ioa_data[3];
1da177e4
LT		 812}__attribute__((packed, aligned (4)));
813
ee0f05b8
BK		 814struct ipr_hostrcb_type_12_error {
815 struct ipr_ext_vpd ioa_vpd;
816 struct ipr_ext_vpd cfc_vpd;
817 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
818 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
819 __be32 ioa_data[3];
820}__attribute__((packed, aligned (4)));
821
1da177e4 822struct ipr_hostrcb_type_03_error {
cfc32139
BK		 823 struct ipr_vpd ioa_vpd;
824 struct ipr_vpd cfc_vpd;
1da177e4
LT		 825 __be32 errors_detected;
826 __be32 errors_logged;
827 u8 ioa_data[12];
cfc32139 828 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 829}__attribute__((packed, aligned (4)));
830
ee0f05b8
BK		 831struct ipr_hostrcb_type_13_error {
832 struct ipr_ext_vpd ioa_vpd;
833 struct ipr_ext_vpd cfc_vpd;
834 __be32 errors_detected;
835 __be32 errors_logged;
836 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
837}__attribute__((packed, aligned (4)));
838
4565e370
WB		 839struct ipr_hostrcb_type_23_error {
840 struct ipr_ext_vpd ioa_vpd;
841 struct ipr_ext_vpd cfc_vpd;
842 __be32 errors_detected;
843 __be32 errors_logged;
844 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
845}__attribute__((packed, aligned (4)));
846
1da177e4 847struct ipr_hostrcb_type_04_error {
cfc32139
BK		 848 struct ipr_vpd ioa_vpd;
849 struct ipr_vpd cfc_vpd;
1da177e4
LT		 850 u8 ioa_data[12];
851 struct ipr_hostrcb_array_data_entry array_member[10];
852 __be32 exposed_mode_adn;
853 __be32 array_id;
cfc32139 854 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 855 __be32 ioa_data2;
856 struct ipr_hostrcb_array_data_entry array_member2[8];
857 struct ipr_res_addr last_func_vset_res_addr;
858 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
859 u8 protection_level[8];
1da177e4
LT		 860}__attribute__((packed, aligned (4)));
861
ee0f05b8
BK		 862struct ipr_hostrcb_type_14_error {
863 struct ipr_ext_vpd ioa_vpd;
864 struct ipr_ext_vpd cfc_vpd;
865 __be32 exposed_mode_adn;
866 __be32 array_id;
867 struct ipr_res_addr last_func_vset_res_addr;
868 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
869 u8 protection_level[8];
870 __be32 num_entries;
871 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
872}__attribute__((packed, aligned (4)));
873
4565e370
WB		 874struct ipr_hostrcb_type_24_error {
875 struct ipr_ext_vpd ioa_vpd;
876 struct ipr_ext_vpd cfc_vpd;
877 u8 reserved[2];
878 u8 exposed_mode_adn;
879#define IPR_INVALID_ARRAY_DEV_NUM 0xff
880 u8 array_id;
881 u8 last_res_path[8];
882 u8 protection_level[8];
883 struct ipr_ext_vpd array_vpd;
884 u8 description[16];
885 u8 reserved2[3];
886 u8 num_entries;
887 struct ipr_hostrcb64_array_data_entry array_member[32];
888}__attribute__((packed, aligned (4)));
889
b0df54bb
BK		 890struct ipr_hostrcb_type_07_error {
891 u8 failure_reason[64];
892 struct ipr_vpd vpd;
893 u32 data[222];
894}__attribute__((packed, aligned (4)));
895
ee0f05b8
BK		 896struct ipr_hostrcb_type_17_error {
897 u8 failure_reason[64];
898 struct ipr_ext_vpd vpd;
899 u32 data[476];
900}__attribute__((packed, aligned (4)));
901
49dc6a18
BK		 902struct ipr_hostrcb_config_element {
903 u8 type_status;
904#define IPR_PATH_CFG_TYPE_MASK 0xF0
905#define IPR_PATH_CFG_NOT_EXIST 0x00
906#define IPR_PATH_CFG_IOA_PORT 0x10
907#define IPR_PATH_CFG_EXP_PORT 0x20
908#define IPR_PATH_CFG_DEVICE_PORT 0x30
909#define IPR_PATH_CFG_DEVICE_LUN 0x40
910
911#define IPR_PATH_CFG_STATUS_MASK 0x0F
912#define IPR_PATH_CFG_NO_PROB 0x00
913#define IPR_PATH_CFG_DEGRADED 0x01
914#define IPR_PATH_CFG_FAILED 0x02
915#define IPR_PATH_CFG_SUSPECT 0x03
916#define IPR_PATH_NOT_DETECTED 0x04
917#define IPR_PATH_INCORRECT_CONN 0x05
918
919 u8 cascaded_expander;
920 u8 phy;
921 u8 link_rate;
922#define IPR_PHY_LINK_RATE_MASK 0x0F
923
924 __be32 wwid[2];
925}__attribute__((packed, aligned (4)));
926
4565e370
WB		 927struct ipr_hostrcb64_config_element {
928 __be16 length;
929 u8 descriptor_id;
930#define IPR_DESCRIPTOR_MASK 0xC0
931#define IPR_DESCRIPTOR_SIS64 0x00
932
933 u8 reserved;
934 u8 type_status;
935
936 u8 reserved2[2];
937 u8 link_rate;
938
939 u8 res_path[8];
940 __be32 wwid[2];
941}__attribute__((packed, aligned (8)));
942
49dc6a18
BK		 943struct ipr_hostrcb_fabric_desc {
944 __be16 length;
945 u8 ioa_port;
946 u8 cascaded_expander;
947 u8 phy;
948 u8 path_state;
949#define IPR_PATH_ACTIVE_MASK 0xC0
950#define IPR_PATH_NO_INFO 0x00
951#define IPR_PATH_ACTIVE 0x40
952#define IPR_PATH_NOT_ACTIVE 0x80
953
954#define IPR_PATH_STATE_MASK 0x0F
955#define IPR_PATH_STATE_NO_INFO 0x00
956#define IPR_PATH_HEALTHY 0x01
957#define IPR_PATH_DEGRADED 0x02
958#define IPR_PATH_FAILED 0x03
959
960 __be16 num_entries;
961 struct ipr_hostrcb_config_element elem[1];
962}__attribute__((packed, aligned (4)));
963
4565e370
WB		 964struct ipr_hostrcb64_fabric_desc {
965 __be16 length;
966 u8 descriptor_id;
967
968 u8 reserved;
969 u8 path_state;
970
971 u8 reserved2[2];
972 u8 res_path[8];
973 u8 reserved3[6];
974 __be16 num_entries;
975 struct ipr_hostrcb64_config_element elem[1];
976}__attribute__((packed, aligned (8)));
977
49dc6a18
BK		 978#define for_each_fabric_cfg(fabric, cfg) \
979 for (cfg = (fabric)->elem; \
980 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
981 cfg++)
982
983struct ipr_hostrcb_type_20_error {
984 u8 failure_reason[64];
985 u8 reserved[3];
986 u8 num_entries;
987 struct ipr_hostrcb_fabric_desc desc[1];
988}__attribute__((packed, aligned (4)));
989
4565e370
WB		 990struct ipr_hostrcb_type_30_error {
991 u8 failure_reason[64];
992 u8 reserved[3];
993 u8 num_entries;
994 struct ipr_hostrcb64_fabric_desc desc[1];
995}__attribute__((packed, aligned (4)));
996
1da177e4 997struct ipr_hostrcb_error {
4565e370
WB		 998 __be32 fd_ioasc;
999 struct ipr_res_addr fd_res_addr;
1000 __be32 fd_res_handle;
1da177e4
LT		 1001 __be32 prc;
1002 union {
1003 struct ipr_hostrcb_type_ff_error type_ff_error;
1004 struct ipr_hostrcb_type_01_error type_01_error;
1005 struct ipr_hostrcb_type_02_error type_02_error;
1006 struct ipr_hostrcb_type_03_error type_03_error;
1007 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1008 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 1009 struct ipr_hostrcb_type_12_error type_12_error;
1010 struct ipr_hostrcb_type_13_error type_13_error;
1011 struct ipr_hostrcb_type_14_error type_14_error;
1012 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1013 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1014 } u;
1015}__attribute__((packed, aligned (4)));
1016
4565e370
WB		 1017struct ipr_hostrcb64_error {
1018 __be32 fd_ioasc;
1019 __be32 ioa_fw_level;
1020 __be32 fd_res_handle;
1021 __be32 prc;
1022 __be64 fd_dev_id;
1023 __be64 fd_lun;
1024 u8 fd_res_path[8];
1025 __be64 time_stamp;
1026 u8 reserved[2];
1027 union {
1028 struct ipr_hostrcb_type_ff_error type_ff_error;
1029 struct ipr_hostrcb_type_12_error type_12_error;
1030 struct ipr_hostrcb_type_17_error type_17_error;
1031 struct ipr_hostrcb_type_23_error type_23_error;
1032 struct ipr_hostrcb_type_24_error type_24_error;
1033 struct ipr_hostrcb_type_30_error type_30_error;
1034 } u;
1035}__attribute__((packed, aligned (8)));
1036
1da177e4
LT		 1037struct ipr_hostrcb_raw {
1038 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1039}__attribute__((packed, aligned (4)));
1040
1041struct ipr_hcam {
1042 u8 op_code;
1043#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1044#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1045
1046 u8 notify_type;
1047#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1048#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1049#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1050#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1051#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1052
1053 u8 notifications_lost;
1054#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1055#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1056
1057 u8 flags;
1058#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1059#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1060
1061 u8 overlay_id;
1062#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1063#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1064#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1065#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1066#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1067#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 1068#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1069#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1070#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1071#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1072#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1073#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1074#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1075#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1076#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1077#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1078#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1079
1080 u8 reserved1[3];
1081 __be32 ilid;
1082 __be32 time_since_last_ioa_reset;
1083 __be32 reserved2;
1084 __be32 length;
1085
1086 union {
1087 struct ipr_hostrcb_error error;
4565e370 1088 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1089 struct ipr_hostrcb_cfg_ch_not ccn;
1090 struct ipr_hostrcb_raw raw;
1091 } u;
1092}__attribute__((packed, aligned (4)));
1093
1094struct ipr_hostrcb {
1095 struct ipr_hcam hcam;
1096 dma_addr_t hostrcb_dma;
1097 struct list_head queue;
49dc6a18 1098 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1099 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1100};
1101
1102/* IPR smart dump table structures */
1103struct ipr_sdt_entry {
dcbad00e
WB		 1104 __be32 start_token;
1105 __be32 end_token;
1106 u8 reserved[4];
1da177e4
LT		 1107
1108 u8 flags;
1109#define IPR_SDT_ENDIAN 0x80
1110#define IPR_SDT_VALID_ENTRY 0x20
1111
1112 u8 resv;
1113 __be16 priority;
1114}__attribute__((packed, aligned (4)));
1115
1116struct ipr_sdt_header {
1117 __be32 state;
1118 __be32 num_entries;
1119 __be32 num_entries_used;
1120 __be32 dump_size;
1121}__attribute__((packed, aligned (4)));
1122
1123struct ipr_sdt {
1124 struct ipr_sdt_header hdr;
1125 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1126}__attribute__((packed, aligned (4)));
1127
1128struct ipr_uc_sdt {
1129 struct ipr_sdt_header hdr;
1130 struct ipr_sdt_entry entry[1];
1131}__attribute__((packed, aligned (4)));
1132
1133/*
1134 * Driver types
1135 */
1136struct ipr_bus_attributes {
1137 u8 bus;
1138 u8 qas_enabled;
1139 u8 bus_width;
1140 u8 reserved;
1141 u32 max_xfer_rate;
1142};
1143
35a39691
BK		 1144struct ipr_sata_port {
1145 struct ipr_ioa_cfg *ioa_cfg;
1146 struct ata_port *ap;
1147 struct ipr_resource_entry *res;
1148 struct ipr_ioasa_gata ioasa;
1149};
1150
1da177e4 1151struct ipr_resource_entry {
1da177e4
LT		 1152 u8 needs_sync_complete:1;
1153 u8 in_erp:1;
1154 u8 add_to_ml:1;
1155 u8 del_from_ml:1;
1156 u8 resetting_device:1;
1157
3e7ebdfa
WB		 1158 u32 bus; /* AKA channel */
1159 u32 target; /* AKA id */
1160 u32 lun;
1161#define IPR_ARRAY_VIRTUAL_BUS 0x1
1162#define IPR_VSET_VIRTUAL_BUS 0x2
1163#define IPR_IOAFP_VIRTUAL_BUS 0x3
1164
1165#define IPR_GET_RES_PHYS_LOC(res) \
1166 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1167
1168 u8 ata_class;
1169
1170 u8 flags;
1171 __be16 res_flags;
1172
1173 __be32 type;
1174
1175 u8 qmodel;
1176 struct ipr_std_inq_data std_inq_data;
1177
1178 __be32 res_handle;
1179 __be64 dev_id;
1180 struct scsi_lun dev_lun;
1181 u8 res_path[8];
1182
1183 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1184 struct scsi_device *sdev;
35a39691 1185 struct ipr_sata_port *sata_port;
1da177e4 1186 struct list_head queue;
3e7ebdfa 1187}; /* struct ipr_resource_entry */
1da177e4
LT		 1188
1189struct ipr_resource_hdr {
1190 u16 num_entries;
1191 u16 reserved;
1192};
1193
1da177e4
LT		 1194struct ipr_misc_cbs {
1195 struct ipr_ioa_vpd ioa_vpd;
62275040 1196 struct ipr_inquiry_page0 page0_data;
1da177e4 1197 struct ipr_inquiry_page3 page3_data;
ac09c349 1198 struct ipr_inquiry_cap cap;
1da177e4
LT		 1199 struct ipr_mode_pages mode_pages;
1200 struct ipr_supported_device supp_dev;
1201};
1202
1203struct ipr_interrupt_offsets {
1204 unsigned long set_interrupt_mask_reg;
1205 unsigned long clr_interrupt_mask_reg;
214777ba 1206 unsigned long clr_interrupt_mask_reg32;
1da177e4 1207 unsigned long sense_interrupt_mask_reg;
214777ba 1208 unsigned long sense_interrupt_mask_reg32;
1da177e4 1209 unsigned long clr_interrupt_reg;
214777ba 1210 unsigned long clr_interrupt_reg32;
1da177e4
LT		 1211
1212 unsigned long sense_interrupt_reg;
214777ba 1213 unsigned long sense_interrupt_reg32;
1da177e4
LT		 1214 unsigned long ioarrin_reg;
1215 unsigned long sense_uproc_interrupt_reg;
214777ba 1216 unsigned long sense_uproc_interrupt_reg32;
1da177e4 1217 unsigned long set_uproc_interrupt_reg;
214777ba 1218 unsigned long set_uproc_interrupt_reg32;
1da177e4 1219 unsigned long clr_uproc_interrupt_reg;
214777ba
WB		 1220 unsigned long clr_uproc_interrupt_reg32;
1221
1222 unsigned long init_feedback_reg;
dcbad00e
WB		 1223
1224 unsigned long dump_addr_reg;
1225 unsigned long dump_data_reg;
1da177e4
LT		 1226};
1227
1228struct ipr_interrupts {
1229 void __iomem *set_interrupt_mask_reg;
1230 void __iomem *clr_interrupt_mask_reg;
214777ba 1231 void __iomem *clr_interrupt_mask_reg32;
1da177e4 1232 void __iomem *sense_interrupt_mask_reg;
214777ba 1233 void __iomem *sense_interrupt_mask_reg32;
1da177e4 1234 void __iomem *clr_interrupt_reg;
214777ba 1235 void __iomem *clr_interrupt_reg32;
1da177e4
LT		 1236
1237 void __iomem *sense_interrupt_reg;
214777ba 1238 void __iomem *sense_interrupt_reg32;
1da177e4
LT		 1239 void __iomem *ioarrin_reg;
1240 void __iomem *sense_uproc_interrupt_reg;
214777ba 1241 void __iomem *sense_uproc_interrupt_reg32;
1da177e4 1242 void __iomem *set_uproc_interrupt_reg;
214777ba 1243 void __iomem *set_uproc_interrupt_reg32;
1da177e4 1244 void __iomem *clr_uproc_interrupt_reg;
214777ba
WB		 1245 void __iomem *clr_uproc_interrupt_reg32;
1246
1247 void __iomem *init_feedback_reg;
dcbad00e
WB		 1248
1249 void __iomem *dump_addr_reg;
1250 void __iomem *dump_data_reg;
1da177e4
LT		 1251};
1252
1253struct ipr_chip_cfg_t {
1254 u32 mailbox;
1255 u8 cache_line_size;
1256 struct ipr_interrupt_offsets regs;
1257};
1258
1259struct ipr_chip_t {
1260 u16 vendor;
1261 u16 device;
1be7bd82
WB		 1262 u16 intr_type;
1263#define IPR_USE_LSI 0x00
1264#define IPR_USE_MSI 0x01
a32c055f
WB		 1265 u16 sis_type;
1266#define IPR_SIS32 0x00
1267#define IPR_SIS64 0x01
1da177e4
LT		 1268 const struct ipr_chip_cfg_t *cfg;
1269};
1270
1271enum ipr_shutdown_type {
1272 IPR_SHUTDOWN_NORMAL = 0x00,
1273 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1274 IPR_SHUTDOWN_ABBREV = 0x80,
1275 IPR_SHUTDOWN_NONE = 0x100
1276};
1277
1278struct ipr_trace_entry {
1279 u32 time;
1280
1281 u8 op_code;
35a39691 1282 u8 ata_op_code;
1da177e4
LT		 1283 u8 type;
1284#define IPR_TRACE_START 0x00
1285#define IPR_TRACE_FINISH 0xff
35a39691 1286 u8 cmd_index;
1da177e4
LT		 1287
1288 __be32 res_handle;
1289 union {
1290 u32 ioasc;
1291 u32 add_data;
1292 u32 res_addr;
1293 } u;
1294};
1295
1296struct ipr_sglist {
1297 u32 order;
1298 u32 num_sg;
12baa420 1299 u32 num_dma_sg;
1da177e4
LT		 1300 u32 buffer_len;
1301 struct scatterlist scatterlist[1];
1302};
1303
1304enum ipr_sdt_state {
1305 INACTIVE,
1306 WAIT_FOR_DUMP,
1307 GET_DUMP,
1308 ABORT_DUMP,
1309 DUMP_OBTAINED
1310};
1311
1312/* Per-controller data */
1313struct ipr_ioa_cfg {
1314 char eye_catcher[8];
1315#define IPR_EYECATCHER "iprcfg"
1316
1317 struct list_head queue;
1318
1319 u8 allow_interrupts:1;
1320 u8 in_reset_reload:1;
1321 u8 in_ioa_bringdown:1;
1322 u8 ioa_unit_checked:1;
1323 u8 ioa_is_dead:1;
1324 u8 dump_taken:1;
1325 u8 allow_cmds:1;
1326 u8 allow_ml_add_del:1;
ce155cce 1327 u8 needs_hard_reset:1;
ac09c349 1328 u8 dual_raid:1;
463fc696 1329 u8 needs_warm_reset:1;
95fecd90 1330 u8 msi_received:1;
a32c055f 1331 u8 sis64:1;
463fc696
BK		 1332
1333 u8 revid;
1da177e4 1334
3e7ebdfa
WB		 1335 /*
1336 * Bitmaps for SIS64 generated target values
1337 */
1338 unsigned long *target_ids;
1339 unsigned long *array_ids;
1340 unsigned long *vset_ids;
1341
1da177e4
LT		 1342 u16 type; /* CCIN of the card */
1343
1344 u8 log_level;
1345#define IPR_MAX_LOG_LEVEL 4
1346#define IPR_DEFAULT_LOG_LEVEL 2
1347
1348#define IPR_NUM_TRACE_INDEX_BITS 8
1349#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1350#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1351 char trace_start[8];
1352#define IPR_TRACE_START_LABEL "trace"
1353 struct ipr_trace_entry *trace;
1354 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1355
1356 /*
1357 * Queue for free command blocks
1358 */
1359 char ipr_free_label[8];
1360#define IPR_FREEQ_LABEL "free-q"
1361 struct list_head free_q;
1362
1363 /*
1364 * Queue for command blocks outstanding to the adapter
1365 */
1366 char ipr_pending_label[8];
1367#define IPR_PENDQ_LABEL "pend-q"
1368 struct list_head pending_q;
1369
1370 char cfg_table_start[8];
1371#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1372 union {
1373 struct ipr_config_table *cfg_table;
1374 struct ipr_config_table64 *cfg_table64;
1375 } u;
1da177e4 1376 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1377 u32 cfg_table_size;
1378 u32 max_devs_supported;
1da177e4
LT		 1379
1380 char resource_table_label[8];
1381#define IPR_RES_TABLE_LABEL "res_tbl"
1382 struct ipr_resource_entry *res_entries;
1383 struct list_head free_res_q;
1384 struct list_head used_res_q;
1385
1386 char ipr_hcam_label[8];
1387#define IPR_HCAM_LABEL "hcams"
1388 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1389 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1390 struct list_head hostrcb_free_q;
1391 struct list_head hostrcb_pending_q;
1392
1393 __be32 *host_rrq;
1394 dma_addr_t host_rrq_dma;
1395#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1396#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1397#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1398#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1399 volatile __be32 *hrrq_start;
1400 volatile __be32 *hrrq_end;
1401 volatile __be32 *hrrq_curr;
1402 volatile u32 toggle_bit;
1403
1404 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1405
5469cb5b 1406 unsigned int transop_timeout;
1da177e4 1407 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1408 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1409
1410 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1411 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1412 void __iomem *ioa_mailbox;
1413 struct ipr_interrupts regs;
1414
1415 u16 saved_pcix_cmd_reg;
1416 u16 reset_retries;
1417
1418 u32 errors_logged;
3d1d0da6 1419 u32 doorbell;
1da177e4
LT		 1420
1421 struct Scsi_Host *host;
1422 struct pci_dev *pdev;
1423 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1424 u8 saved_mode_page_len;
1425
1426 struct work_struct work_q;
1427
1428 wait_queue_head_t reset_wait_q;
95fecd90 1429 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1430
1431 struct ipr_dump *dump;
1432 enum ipr_sdt_state sdt_state;
1433
1434 struct ipr_misc_cbs *vpd_cbs;
1435 dma_addr_t vpd_cbs_dma;
1436
1437 struct pci_pool *ipr_cmd_pool;
1438
1439 struct ipr_cmnd *reset_cmd;
463fc696 1440 int (*reset) (struct ipr_cmnd *);
1da177e4 1441
35a39691 1442 struct ata_host ata_host;
1da177e4 1443 char ipr_cmd_label[8];
0124ca9d 1444#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1445 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1446 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1447}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1448
1449struct ipr_cmnd {
1450 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1451 union {
1452 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1453 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1454 struct ipr_ata64_ioadl ata_ioadl;
1455 } i;
1da177e4 1456 struct ipr_ioasa ioasa;
1da177e4
LT		 1457 struct list_head queue;
1458 struct scsi_cmnd *scsi_cmd;
35a39691 1459 struct ata_queued_cmd *qc;
1da177e4
LT		 1460 struct completion completion;
1461 struct timer_list timer;
1462 void (*done) (struct ipr_cmnd *);
1463 int (*job_step) (struct ipr_cmnd *);
dfed823e 1464 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1465 u16 cmd_index;
1466 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1467 dma_addr_t sense_buffer_dma;
1468 unsigned short dma_use_sg;
a32c055f 1469 dma_addr_t dma_addr;
1da177e4
LT		 1470 struct ipr_cmnd *sibling;
1471 union {
1472 enum ipr_shutdown_type shutdown_type;
1473 struct ipr_hostrcb *hostrcb;
1474 unsigned long time_left;
1475 unsigned long scratch;
1476 struct ipr_resource_entry *res;
1477 struct scsi_device *sdev;
1478 } u;
1479
1480 struct ipr_ioa_cfg *ioa_cfg;
1481};
1482
1483struct ipr_ses_table_entry {
1484 char product_id[17];
1485 char compare_product_id_byte[17];
1486 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1487};
1488
1489struct ipr_dump_header {
1490 u32 eye_catcher;
1491#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1492 u32 len;
1493 u32 num_entries;
1494 u32 first_entry_offset;
1495 u32 status;
1496#define IPR_DUMP_STATUS_SUCCESS 0
1497#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1498#define IPR_DUMP_STATUS_FAILED 0xffffffff
1499 u32 os;
1500#define IPR_DUMP_OS_LINUX 0x4C4E5558
1501 u32 driver_name;
1502#define IPR_DUMP_DRIVER_NAME 0x49505232
1503}__attribute__((packed, aligned (4)));
1504
1505struct ipr_dump_entry_header {
1506 u32 eye_catcher;
1507#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1508 u32 len;
1509 u32 num_elems;
1510 u32 offset;
1511 u32 data_type;
1512#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1513#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1514 u32 id;
1515#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1516#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1517#define IPR_DUMP_TRACE_ID 0x54524143
1518#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1519#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1520#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1521#define IPR_DUMP_PEND_OPS 0x414F5053
1522 u32 status;
1523}__attribute__((packed, aligned (4)));
1524
1525struct ipr_dump_location_entry {
1526 struct ipr_dump_entry_header hdr;
71610f55 1527 u8 location[20];
1da177e4
LT		 1528}__attribute__((packed));
1529
1530struct ipr_dump_trace_entry {
1531 struct ipr_dump_entry_header hdr;
1532 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1533}__attribute__((packed, aligned (4)));
1534
1535struct ipr_dump_version_entry {
1536 struct ipr_dump_entry_header hdr;
1537 u8 version[sizeof(IPR_DRIVER_VERSION)];
1538};
1539
1540struct ipr_dump_ioa_type_entry {
1541 struct ipr_dump_entry_header hdr;
1542 u32 type;
1543 u32 fw_version;
1544};
1545
1546struct ipr_driver_dump {
1547 struct ipr_dump_header hdr;
1548 struct ipr_dump_version_entry version_entry;
1549 struct ipr_dump_location_entry location_entry;
1550 struct ipr_dump_ioa_type_entry ioa_type_entry;
1551 struct ipr_dump_trace_entry trace_entry;
1552}__attribute__((packed));
1553
1554struct ipr_ioa_dump {
1555 struct ipr_dump_entry_header hdr;
1556 struct ipr_sdt sdt;
1557 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1558 u32 reserved;
1559 u32 next_page_index;
1560 u32 page_offset;
1561 u32 format;
1da177e4
LT		 1562}__attribute__((packed, aligned (4)));
1563
1564struct ipr_dump {
1565 struct kref kref;
1566 struct ipr_ioa_cfg *ioa_cfg;
1567 struct ipr_driver_dump driver_dump;
1568 struct ipr_ioa_dump ioa_dump;
1569};
1570
1571struct ipr_error_table_t {
1572 u32 ioasc;
1573 int log_ioasa;
1574 int log_hcam;
1575 char *error;
1576};
1577
1578struct ipr_software_inq_lid_info {
1579 __be32 load_id;
1580 __be32 timestamp[3];
1581}__attribute__((packed, aligned (4)));
1582
1583struct ipr_ucode_image_header {
1584 __be32 header_length;
1585 __be32 lid_table_offset;
1586 u8 major_release;
1587 u8 card_type;
1588 u8 minor_release[2];
1589 u8 reserved[20];
1590 char eyecatcher[16];
1591 __be32 num_lids;
1592 struct ipr_software_inq_lid_info lid[1];
1593}__attribute__((packed, aligned (4)));
1594
1595/*
1596 * Macros
1597 */
d3c74871 1598#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1599
1600#ifdef CONFIG_SCSI_IPR_TRACE
1601#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1602#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1603#else
1604#define ipr_create_trace_file(kobj, attr) 0
1605#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1606#endif
1607
1608#ifdef CONFIG_SCSI_IPR_DUMP
1609#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1610#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1611#else
1612#define ipr_create_dump_file(kobj, attr) 0
1613#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1614#endif
1615
1616/*
1617 * Error logging macros
1618 */
1619#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1620#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1621#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1622
3e7ebdfa
WB		 1623#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1624 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1625 bus, target, lun, ##__VA_ARGS__)
1626
1627#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1628 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1629
fb3ed3cb
BK		 1630#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1631 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1632 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1633
fb3ed3cb
BK		 1634#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1635 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1636
fa15b1f6
BK		 1637#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1638{ \
1639 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1640 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1641 } else { \
1642 ipr_err(fmt": %d:%d:%d:%d\n", \
1643 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1644 (res).bus, (res).target, (res).lun); \
1645 } \
1646}
1647
49dc6a18 1648#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1649{ \
1650 if (ipr_is_device(hostrcb)) { \
1651 if ((hostrcb)->ioa_cfg->sis64) { \
1652 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1653 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1654 &hostrcb->rp_buffer[0]), \
1655 __VA_ARGS__); \
1656 } else { \
1657 ipr_ra_err((hostrcb)->ioa_cfg, \
1658 (hostrcb)->hcam.u.error.fd_res_addr, \
1659 fmt, __VA_ARGS__); \
1660 } \
1661 } else { \
1662 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1663 } \
49dc6a18
BK		 1664}
1665
1da177e4 1666#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1667 __FILE__, __func__, __LINE__)
1da177e4 1668
cadbd4a5
HH		 1669#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1670#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1671
1672#define ipr_err_separator \
1673ipr_err("----------------------------------------------------------\n")
1674
1675
1676/*
1677 * Inlines
1678 */
1679
1680/**
1681 * ipr_is_ioa_resource - Determine if a resource is the IOA
1682 * @res: resource entry struct
1683 *
1684 * Return value:
1685 * 1 if IOA / 0 if not IOA
1686 **/
1687static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1688{
3e7ebdfa 1689 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1690}
1691
1692/**
1693 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1694 * @res: resource entry struct
1695 *
1696 * Return value:
1697 * 1 if AF DASD / 0 if not AF DASD
1698 **/
1699static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1700{
3e7ebdfa
WB		 1701 return res->type == IPR_RES_TYPE_AF_DASD ||
1702 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1703}
1704
1705/**
1706 * ipr_is_vset_device - Determine if a resource is a VSET
1707 * @res: resource entry struct
1708 *
1709 * Return value:
1710 * 1 if VSET / 0 if not VSET
1711 **/
1712static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1713{
3e7ebdfa 1714 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1715}
1716
1717/**
1718 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1719 * @res: resource entry struct
1720 *
1721 * Return value:
1722 * 1 if GSCSI / 0 if not GSCSI
1723 **/
1724static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1725{
3e7ebdfa 1726 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1727}
1728
e4fbf44e
BK		 1729/**
1730 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1731 * @res: resource entry struct
1732 *
1733 * Return value:
1734 * 1 if SCSI disk / 0 if not SCSI disk
1735 **/
1736static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1737{
1738 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1739 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1740 return 1;
1741 else
1742 return 0;
1743}
1744
b5145d25
BK		 1745/**
1746 * ipr_is_gata - Determine if a resource is a generic ATA resource
1747 * @res: resource entry struct
1748 *
1749 * Return value:
1750 * 1 if GATA / 0 if not GATA
1751 **/
1752static inline int ipr_is_gata(struct ipr_resource_entry *res)
1753{
3e7ebdfa 1754 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1755}
1756
ee0a90fa
BK		 1757/**
1758 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1759 * @res: resource entry struct
1760 *
1761 * Return value:
1762 * 1 if NACA queueing model / 0 if not NACA queueing model
1763 **/
1764static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1765{
3e7ebdfa 1766 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK		 1767 return 1;
1768 return 0;
1769}
1770
1da177e4 1771/**
4565e370
WB		 1772 * ipr_is_device - Determine if the hostrcb structure is related to a device
1773 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1774 *
1775 * Return value:
1776 * 1 if AF / 0 if not AF
1777 **/
4565e370 1778static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1779{
4565e370
WB		 1780 struct ipr_res_addr *res_addr;
1781 u8 *res_path;
1782
1783 if (hostrcb->ioa_cfg->sis64) {
1784 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1785 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1786 res_path[0] == 0x81) && res_path[2] != 0xFF)
1787 return 1;
1788 } else {
1789 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1790
1791 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1792 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1793 return 1;
1794 }
1da177e4
LT		 1795 return 0;
1796}
1797
1798/**
1799 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1800 * @sdt_word: SDT address
1801 *
1802 * Return value:
1803 * 1 if format 2 / 0 if not
1804 **/
1805static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1806{
1807 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1808
1809 switch (bar_sel) {
1810 case IPR_SDT_FMT2_BAR0_SEL:
1811 case IPR_SDT_FMT2_BAR1_SEL:
1812 case IPR_SDT_FMT2_BAR2_SEL:
1813 case IPR_SDT_FMT2_BAR3_SEL:
1814 case IPR_SDT_FMT2_BAR4_SEL:
1815 case IPR_SDT_FMT2_BAR5_SEL:
1816 case IPR_SDT_FMT2_EXP_ROM_SEL:
1817 return 1;
1818 };
1819
1820 return 0;
1821}
1822
1823#endif
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