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[SCSI] ipr: implement shutdown changes and remove obsolete write cache parameter
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT		 1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
fa195afe 22 * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors
1da177e4
LT		 23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
35a39691 31#include <linux/libata.h>
1da177e4
LT		 32#include <linux/list.h>
33#include <linux/kref.h>
34#include <scsi/scsi.h>
35#include <scsi/scsi_cmnd.h>
36
37/*
38 * Literals
39 */
95fecd90
WB		 40#define IPR_DRIVER_VERSION "2.4.3"
41#define IPR_DRIVER_DATE "(June 10, 2009)"
1da177e4 42
1da177e4
LT		 43/*
44 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
45 * ops per device for devices not running tagged command queuing.
46 * This can be adjusted at runtime through sysfs device attributes.
47 */
48#define IPR_MAX_CMD_PER_LUN 6
b5145d25 49#define IPR_MAX_CMD_PER_ATA_LUN 1
1da177e4
LT		 50
51/*
52 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
53 * ops the mid-layer can send to the adapter.
54 */
55#define IPR_NUM_BASE_CMD_BLKS 100
56
60e7486b 57#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
185eb31c 58#define PCI_DEVICE_ID_IBM_SCAMP_E 0x034A
60e7486b 59
1da177e4
LT		 60#define IPR_SUBS_DEV_ID_2780 0x0264
61#define IPR_SUBS_DEV_ID_5702 0x0266
62#define IPR_SUBS_DEV_ID_5703 0x0278
63#define IPR_SUBS_DEV_ID_572E 0x028D
64#define IPR_SUBS_DEV_ID_573E 0x02D3
65#define IPR_SUBS_DEV_ID_573D 0x02D4
66#define IPR_SUBS_DEV_ID_571A 0x02C0
67#define IPR_SUBS_DEV_ID_571B 0x02BE
68#define IPR_SUBS_DEV_ID_571E 0x02BF
86f51436
BK		 69#define IPR_SUBS_DEV_ID_571F 0x02D5
70#define IPR_SUBS_DEV_ID_572A 0x02C1
71#define IPR_SUBS_DEV_ID_572B 0x02C2
60e7486b 72#define IPR_SUBS_DEV_ID_572F 0x02C3
185eb31c
BK		 73#define IPR_SUBS_DEV_ID_574D 0x030B
74#define IPR_SUBS_DEV_ID_574E 0x030A
86f51436 75#define IPR_SUBS_DEV_ID_575B 0x030D
60e7486b 76#define IPR_SUBS_DEV_ID_575C 0x0338
185eb31c
BK		 77#define IPR_SUBS_DEV_ID_575D 0x033E
78#define IPR_SUBS_DEV_ID_57B3 0x033A
60e7486b
BK		 79#define IPR_SUBS_DEV_ID_57B7 0x0360
80#define IPR_SUBS_DEV_ID_57B8 0x02C2
1da177e4
LT		 81
82#define IPR_NAME "ipr"
83
84/*
85 * Return codes
86 */
87#define IPR_RC_JOB_CONTINUE 1
88#define IPR_RC_JOB_RETURN 2
89
90/*
91 * IOASCs
92 */
93#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
65f56475 94#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
1da177e4
LT		 95#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
96#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
97#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
98#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
99#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
100#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
dfed823e 101#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
1da177e4 102#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
b0df54bb
BK		 103#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
104#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
1da177e4
LT		 105#define IPR_IOASC_BUS_WAS_RESET 0x06290000
106#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
107#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
108
109#define IPR_FIRST_DRIVER_IOASC 0x10000000
110#define IPR_IOASC_IOA_WAS_RESET 0x10000001
111#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
112
5469cb5b
BK		 113/* Driver data flags */
114#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
463fc696 115#define IPR_USE_PCI_WARM_RESET 0x00000002
5469cb5b 116
ac719aba 117#define IPR_DEFAULT_MAX_ERROR_DUMP 984
1da177e4
LT		 118#define IPR_NUM_LOG_HCAMS 2
119#define IPR_NUM_CFG_CHG_HCAMS 2
120#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
3e7ebdfa
WB		 121
122#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
123#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
124
d71a8b0c 125#define IPR_MAX_NUM_TARGETS_PER_BUS 256
1da177e4
LT		 126#define IPR_MAX_NUM_LUNS_PER_TARGET 256
127#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
128#define IPR_VSET_BUS 0xff
129#define IPR_IOA_BUS 0xff
130#define IPR_IOA_TARGET 0xff
131#define IPR_IOA_LUN 0xff
b5145d25 132#define IPR_MAX_NUM_BUSES 16
1da177e4
LT		 133#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
134
135#define IPR_NUM_RESET_RELOAD_RETRIES 3
136
137/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
138#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
f72919ec 139 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
1da177e4
LT		 140
141#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
142#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
143 IPR_NUM_INTERNAL_CMD_BLKS)
144
145#define IPR_MAX_PHYSICAL_DEVS 192
3e7ebdfa
WB		 146#define IPR_DEFAULT_SIS64_DEVS 1024
147#define IPR_MAX_SIS64_DEVS 4096
1da177e4
LT		 148
149#define IPR_MAX_SGLIST 64
150#define IPR_IOA_MAX_SECTORS 32767
151#define IPR_VSET_MAX_SECTORS 512
152#define IPR_MAX_CDB_LEN 16
3feeb89d 153#define IPR_MAX_HRRQ_RETRIES 3
1da177e4
LT		 154
155#define IPR_DEFAULT_BUS_WIDTH 16
156#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
157#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
158#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
159#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
160
161#define IPR_IOA_RES_HANDLE 0xffffffff
1121b794 162#define IPR_INVALID_RES_HANDLE 0
1da177e4
LT		 163#define IPR_IOA_RES_ADDR 0x00ffffff
164
165/*
166 * Adapter Commands
167 */
168#define IPR_QUERY_RSRC_STATE 0xC2
169#define IPR_RESET_DEVICE 0xC3
170#define IPR_RESET_TYPE_SELECT 0x80
171#define IPR_LUN_RESET 0x40
172#define IPR_TARGET_RESET 0x20
173#define IPR_BUS_RESET 0x10
b5145d25 174#define IPR_ATA_PHY_RESET 0x80
1da177e4
LT		 175#define IPR_ID_HOST_RR_Q 0xC4
176#define IPR_QUERY_IOA_CONFIG 0xC5
177#define IPR_CANCEL_ALL_REQUESTS 0xCE
178#define IPR_HOST_CONTROLLED_ASYNC 0xCF
179#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
180#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
181#define IPR_SET_SUPPORTED_DEVICES 0xFB
3e7ebdfa 182#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
1da177e4
LT		 183#define IPR_IOA_SHUTDOWN 0xF7
184#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
185
186/*
187 * Timeouts
188 */
189#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
190#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
191#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
ac09c349 192#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
1da177e4
LT		 193#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
194#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
195#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
196#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
197#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
198#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
199#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
200#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
5469cb5b 201#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
1da177e4
LT		 202#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
203#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
204#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
463fc696 205#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
1da177e4
LT		 206#define IPR_DUMP_TIMEOUT (15 * HZ)
207
208/*
209 * SCSI Literals
210 */
211#define IPR_VENDOR_ID_LEN 8
212#define IPR_PROD_ID_LEN 16
213#define IPR_SERIAL_NUM_LEN 8
214
215/*
216 * Hardware literals
217 */
218#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
219#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
220#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
221#define IPR_GET_FMT2_BAR_SEL(mbx) \
222(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
223#define IPR_SDT_FMT2_BAR0_SEL 0x0
224#define IPR_SDT_FMT2_BAR1_SEL 0x1
225#define IPR_SDT_FMT2_BAR2_SEL 0x2
226#define IPR_SDT_FMT2_BAR3_SEL 0x3
227#define IPR_SDT_FMT2_BAR4_SEL 0x4
228#define IPR_SDT_FMT2_BAR5_SEL 0x5
229#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
230#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
dcbad00e 231#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
1da177e4 232#define IPR_DOORBELL 0x82800000
3d1d0da6 233#define IPR_RUNTIME_RESET 0x40000000
1da177e4
LT		 234
235#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
236#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
237#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
238#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
239#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
240#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
241#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
242#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
243#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
244#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
245#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
246
247#define IPR_PCII_ERROR_INTERRUPTS \
248(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
249IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
250
251#define IPR_PCII_OPER_INTERRUPTS \
252(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
253
254#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
255#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
256
257#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
258#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
259
260/*
261 * Dump literals
262 */
263#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
264#define IPR_NUM_SDT_ENTRIES 511
265#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
266
267/*
268 * Misc literals
269 */
270#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
271
272/*
273 * Adapter interface types
274 */
275
276struct ipr_res_addr {
277 u8 reserved;
278 u8 bus;
279 u8 target;
280 u8 lun;
281#define IPR_GET_PHYS_LOC(res_addr) \
282 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
283}__attribute__((packed, aligned (4)));
284
285struct ipr_std_inq_vpids {
286 u8 vendor_id[IPR_VENDOR_ID_LEN];
287 u8 product_id[IPR_PROD_ID_LEN];
288}__attribute__((packed));
289
cfc32139
BK		 290struct ipr_vpd {
291 struct ipr_std_inq_vpids vpids;
292 u8 sn[IPR_SERIAL_NUM_LEN];
293}__attribute__((packed));
294
ee0f05b8
BK		 295struct ipr_ext_vpd {
296 struct ipr_vpd vpd;
297 __be32 wwid[2];
298}__attribute__((packed));
299
1da177e4
LT		 300struct ipr_std_inq_data {
301 u8 peri_qual_dev_type;
302#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
303#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
304
305 u8 removeable_medium_rsvd;
306#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
307
308#define IPR_IS_DASD_DEVICE(std_inq) \
309((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
310!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
311
312#define IPR_IS_SES_DEVICE(std_inq) \
313(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
314
315 u8 version;
316 u8 aen_naca_fmt;
317 u8 additional_len;
318 u8 sccs_rsvd;
319 u8 bq_enc_multi;
320 u8 sync_cmdq_flags;
321
322 struct ipr_std_inq_vpids vpids;
323
324 u8 ros_rsvd_ram_rsvd[4];
325
326 u8 serial_num[IPR_SERIAL_NUM_LEN];
327}__attribute__ ((packed));
328
3e7ebdfa
WB		 329#define IPR_RES_TYPE_AF_DASD 0x00
330#define IPR_RES_TYPE_GENERIC_SCSI 0x01
331#define IPR_RES_TYPE_VOLUME_SET 0x02
332#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
333#define IPR_RES_TYPE_GENERIC_ATA 0x04
334#define IPR_RES_TYPE_ARRAY 0x05
335#define IPR_RES_TYPE_IOAFP 0xff
336
1da177e4 337struct ipr_config_table_entry {
b5145d25
BK		 338 u8 proto;
339#define IPR_PROTO_SATA 0x02
340#define IPR_PROTO_SATA_ATAPI 0x03
341#define IPR_PROTO_SAS_STP 0x06
3e7ebdfa 342#define IPR_PROTO_SAS_STP_ATAPI 0x07
1da177e4
LT		 343 u8 array_id;
344 u8 flags;
3e7ebdfa 345#define IPR_IS_IOA_RESOURCE 0x80
1da177e4 346 u8 rsvd_subtype;
3e7ebdfa
WB		 347
348#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
349#define IPR_QUEUE_FROZEN_MODEL 0
ee0a90fa
BK		 350#define IPR_QUEUE_NACA_MODEL 1
351
1da177e4
LT		 352 struct ipr_res_addr res_addr;
353 __be32 res_handle;
354 __be32 reserved4[2];
355 struct ipr_std_inq_data std_inq_data;
356}__attribute__ ((packed, aligned (4)));
357
3e7ebdfa
WB		 358struct ipr_config_table_entry64 {
359 u8 res_type;
360 u8 proto;
361 u8 vset_num;
362 u8 array_id;
363 __be16 flags;
364 __be16 res_flags;
365#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
366 __be32 res_handle;
367 u8 dev_id_type;
368 u8 reserved[3];
369 __be64 dev_id;
370 __be64 lun;
371 __be64 lun_wwn[2];
372#define IPR_MAX_RES_PATH_LENGTH 24
373 __be64 res_path;
374 struct ipr_std_inq_data std_inq_data;
375 u8 reserved2[4];
376 __be64 reserved3[2]; // description text
377 u8 reserved4[8];
378}__attribute__ ((packed, aligned (8)));
379
1da177e4
LT		 380struct ipr_config_table_hdr {
381 u8 num_entries;
382 u8 flags;
383#define IPR_UCODE_DOWNLOAD_REQ 0x10
384 __be16 reserved;
385}__attribute__((packed, aligned (4)));
386
3e7ebdfa
WB		 387struct ipr_config_table_hdr64 {
388 __be16 num_entries;
389 __be16 reserved;
390 u8 flags;
391 u8 reserved2[11];
392}__attribute__((packed, aligned (4)));
393
1da177e4
LT		 394struct ipr_config_table {
395 struct ipr_config_table_hdr hdr;
3e7ebdfa 396 struct ipr_config_table_entry dev[0];
1da177e4
LT		 397}__attribute__((packed, aligned (4)));
398
3e7ebdfa
WB		 399struct ipr_config_table64 {
400 struct ipr_config_table_hdr64 hdr64;
401 struct ipr_config_table_entry64 dev[0];
402}__attribute__((packed, aligned (8)));
403
404struct ipr_config_table_entry_wrapper {
405 union {
406 struct ipr_config_table_entry *cfgte;
407 struct ipr_config_table_entry64 *cfgte64;
408 } u;
409};
410
1da177e4 411struct ipr_hostrcb_cfg_ch_not {
3e7ebdfa
WB		 412 union {
413 struct ipr_config_table_entry cfgte;
414 struct ipr_config_table_entry64 cfgte64;
415 } u;
1da177e4
LT		 416 u8 reserved[936];
417}__attribute__((packed, aligned (4)));
418
419struct ipr_supported_device {
420 __be16 data_length;
421 u8 reserved;
422 u8 num_records;
423 struct ipr_std_inq_vpids vpids;
424 u8 reserved2[16];
425}__attribute__((packed, aligned (4)));
426
427/* Command packet structure */
428struct ipr_cmd_pkt {
429 __be16 reserved; /* Reserved by IOA */
430 u8 request_type;
431#define IPR_RQTYPE_SCSICDB 0x00
432#define IPR_RQTYPE_IOACMD 0x01
433#define IPR_RQTYPE_HCAM 0x02
b5145d25 434#define IPR_RQTYPE_ATA_PASSTHRU 0x04
1da177e4 435
a32c055f 436 u8 reserved2;
1da177e4
LT		 437
438 u8 flags_hi;
439#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
440#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
441#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
442#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
443#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
444
445 u8 flags_lo;
446#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
447#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
448#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
449#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
450#define IPR_FLAGS_LO_ORDERED_TASK 0x04
451#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
452#define IPR_FLAGS_LO_ACA_TASK 0x08
453
454 u8 cdb[16];
455 __be16 timeout;
456}__attribute__ ((packed, aligned(4)));
457
a32c055f 458struct ipr_ioarcb_ata_regs { /* 22 bytes */
b5145d25
BK		 459 u8 flags;
460#define IPR_ATA_FLAG_PACKET_CMD 0x80
461#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
462#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
463 u8 reserved[3];
464
465 __be16 data;
466 u8 feature;
467 u8 nsect;
468 u8 lbal;
469 u8 lbam;
470 u8 lbah;
471 u8 device;
472 u8 command;
473 u8 reserved2[3];
474 u8 hob_feature;
475 u8 hob_nsect;
476 u8 hob_lbal;
477 u8 hob_lbam;
478 u8 hob_lbah;
479 u8 ctl;
480}__attribute__ ((packed, aligned(4)));
481
51b1c7e1
BK		 482struct ipr_ioadl_desc {
483 __be32 flags_and_data_len;
484#define IPR_IOADL_FLAGS_MASK 0xff000000
485#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
486#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
487#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
488#define IPR_IOADL_FLAGS_READ 0x48000000
489#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
490#define IPR_IOADL_FLAGS_WRITE 0x68000000
491#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
492#define IPR_IOADL_FLAGS_LAST 0x01000000
493
494 __be32 address;
495}__attribute__((packed, aligned (8)));
496
a32c055f
WB		 497struct ipr_ioadl64_desc {
498 __be32 flags;
499 __be32 data_len;
500 __be64 address;
501}__attribute__((packed, aligned (16)));
502
503struct ipr_ata64_ioadl {
504 struct ipr_ioarcb_ata_regs regs;
505 u16 reserved[5];
506 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
507}__attribute__((packed, aligned (16)));
508
b5145d25
BK		 509struct ipr_ioarcb_add_data {
510 union {
511 struct ipr_ioarcb_ata_regs regs;
51b1c7e1 512 struct ipr_ioadl_desc ioadl[5];
b5145d25 513 __be32 add_cmd_parms[10];
a32c055f
WB		 514 } u;
515}__attribute__ ((packed, aligned (4)));
516
517struct ipr_ioarcb_sis64_add_addr_ecb {
518 __be64 ioasa_host_pci_addr;
519 __be64 data_ioadl_addr;
520 __be64 reserved;
521 __be32 ext_control_buf[4];
522}__attribute__((packed, aligned (8)));
b5145d25 523
1da177e4
LT		 524/* IOA Request Control Block 128 bytes */
525struct ipr_ioarcb {
a32c055f
WB		 526 union {
527 __be32 ioarcb_host_pci_addr;
528 __be64 ioarcb_host_pci_addr64;
529 } a;
1da177e4
LT		 530 __be32 res_handle;
531 __be32 host_response_handle;
532 __be32 reserved1;
533 __be32 reserved2;
534 __be32 reserved3;
535
a32c055f 536 __be32 data_transfer_length;
1da177e4
LT		 537 __be32 read_data_transfer_length;
538 __be32 write_ioadl_addr;
a32c055f 539 __be32 ioadl_len;
1da177e4
LT		 540 __be32 read_ioadl_addr;
541 __be32 read_ioadl_len;
542
543 __be32 ioasa_host_pci_addr;
544 __be16 ioasa_len;
545 __be16 reserved4;
546
547 struct ipr_cmd_pkt cmd_pkt;
548
a32c055f
WB		 549 __be16 add_cmd_parms_offset;
550 __be16 add_cmd_parms_len;
551
552 union {
553 struct ipr_ioarcb_add_data add_data;
554 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
555 } u;
556
1da177e4
LT		 557}__attribute__((packed, aligned (4)));
558
1da177e4
LT		 559struct ipr_ioasa_vset {
560 __be32 failing_lba_hi;
561 __be32 failing_lba_lo;
c8f74892 562 __be32 reserved;
1da177e4
LT		 563}__attribute__((packed, aligned (4)));
564
565struct ipr_ioasa_af_dasd {
566 __be32 failing_lba;
c8f74892 567 __be32 reserved[2];
1da177e4
LT		 568}__attribute__((packed, aligned (4)));
569
570struct ipr_ioasa_gpdd {
571 u8 end_state;
572 u8 bus_phase;
573 __be16 reserved;
c8f74892 574 __be32 ioa_data[2];
1da177e4
LT		 575}__attribute__((packed, aligned (4)));
576
b5145d25
BK		 577struct ipr_ioasa_gata {
578 u8 error;
579 u8 nsect; /* Interrupt reason */
580 u8 lbal;
581 u8 lbam;
582 u8 lbah;
583 u8 device;
584 u8 status;
585 u8 alt_status; /* ATA CTL */
586 u8 hob_nsect;
587 u8 hob_lbal;
588 u8 hob_lbam;
589 u8 hob_lbah;
590}__attribute__((packed, aligned (4)));
591
c8f74892
BK		 592struct ipr_auto_sense {
593 __be16 auto_sense_len;
594 __be16 ioa_data_len;
595 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
596};
1da177e4
LT		 597
598struct ipr_ioasa {
599 __be32 ioasc;
600#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
601#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
602#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
603#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
604
605 __be16 ret_stat_len; /* Length of the returned IOASA */
606
607 __be16 avail_stat_len; /* Total Length of status available. */
608
609 __be32 residual_data_len; /* number of bytes in the host data */
610 /* buffers that were not used by the IOARCB command. */
611
612 __be32 ilid;
613#define IPR_NO_ILID 0
614#define IPR_DRIVER_ILID 0xffffffff
615
616 __be32 fd_ioasc;
617
618 __be32 fd_phys_locator;
619
620 __be32 fd_res_handle;
621
622 __be32 ioasc_specific; /* status code specific field */
c8f74892
BK		 623#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
624#define IPR_AUTOSENSE_VALID 0x40000000
b5145d25 625#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
1da177e4
LT		 626#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
627#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
628#define IPR_FIELD_POINTER_MASK 0x0000ffff
629
630 union {
631 struct ipr_ioasa_vset vset;
632 struct ipr_ioasa_af_dasd dasd;
633 struct ipr_ioasa_gpdd gpdd;
b5145d25 634 struct ipr_ioasa_gata gata;
1da177e4 635 } u;
c8f74892
BK		 636
637 struct ipr_auto_sense auto_sense;
1da177e4
LT		 638}__attribute__((packed, aligned (4)));
639
640struct ipr_mode_parm_hdr {
641 u8 length;
642 u8 medium_type;
643 u8 device_spec_parms;
644 u8 block_desc_len;
645}__attribute__((packed));
646
647struct ipr_mode_pages {
648 struct ipr_mode_parm_hdr hdr;
649 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
650}__attribute__((packed));
651
652struct ipr_mode_page_hdr {
653 u8 ps_page_code;
654#define IPR_MODE_PAGE_PS 0x80
655#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
656 u8 page_length;
657}__attribute__ ((packed));
658
659struct ipr_dev_bus_entry {
660 struct ipr_res_addr res_addr;
661 u8 flags;
662#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
663#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
664#define IPR_SCSI_ATTR_QAS_MASK 0xC0
665#define IPR_SCSI_ATTR_ENABLE_TM 0x20
666#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
667#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
668#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
669
670 u8 scsi_id;
671 u8 bus_width;
672 u8 extended_reset_delay;
673#define IPR_EXTENDED_RESET_DELAY 7
674
675 __be32 max_xfer_rate;
676
677 u8 spinup_delay;
678 u8 reserved3;
679 __be16 reserved4;
680}__attribute__((packed, aligned (4)));
681
682struct ipr_mode_page28 {
683 struct ipr_mode_page_hdr hdr;
684 u8 num_entries;
685 u8 entry_length;
686 struct ipr_dev_bus_entry bus[0];
687}__attribute__((packed));
688
ac09c349
BK		 689struct ipr_mode_page24 {
690 struct ipr_mode_page_hdr hdr;
691 u8 flags;
692#define IPR_ENABLE_DUAL_IOA_AF 0x80
693}__attribute__((packed));
694
1da177e4
LT		 695struct ipr_ioa_vpd {
696 struct ipr_std_inq_data std_inq_data;
697 u8 ascii_part_num[12];
698 u8 reserved[40];
699 u8 ascii_plant_code[4];
700}__attribute__((packed));
701
702struct ipr_inquiry_page3 {
703 u8 peri_qual_dev_type;
704 u8 page_code;
705 u8 reserved1;
706 u8 page_length;
707 u8 ascii_len;
708 u8 reserved2[3];
709 u8 load_id[4];
710 u8 major_release;
711 u8 card_type;
712 u8 minor_release[2];
713 u8 ptf_number[4];
714 u8 patch_number[4];
715}__attribute__((packed));
716
ac09c349
BK		 717struct ipr_inquiry_cap {
718 u8 peri_qual_dev_type;
719 u8 page_code;
720 u8 reserved1;
721 u8 page_length;
722 u8 ascii_len;
723 u8 reserved2;
724 u8 sis_version[2];
725 u8 cap;
726#define IPR_CAP_DUAL_IOA_RAID 0x80
727 u8 reserved3[15];
728}__attribute__((packed));
729
62275040
BK		 730#define IPR_INQUIRY_PAGE0_ENTRIES 20
731struct ipr_inquiry_page0 {
732 u8 peri_qual_dev_type;
733 u8 page_code;
734 u8 reserved1;
735 u8 len;
736 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
737}__attribute__((packed));
738
1da177e4 739struct ipr_hostrcb_device_data_entry {
cfc32139 740 struct ipr_vpd vpd;
1da177e4 741 struct ipr_res_addr dev_res_addr;
cfc32139
BK		 742 struct ipr_vpd new_vpd;
743 struct ipr_vpd ioa_last_with_dev_vpd;
744 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT		 745 __be32 ioa_data[5];
746}__attribute__((packed, aligned (4)));
747
ee0f05b8
BK		 748struct ipr_hostrcb_device_data_entry_enhanced {
749 struct ipr_ext_vpd vpd;
750 u8 ccin[4];
751 struct ipr_res_addr dev_res_addr;
752 struct ipr_ext_vpd new_vpd;
753 u8 new_ccin[4];
754 struct ipr_ext_vpd ioa_last_with_dev_vpd;
755 struct ipr_ext_vpd cfc_last_with_dev_vpd;
756}__attribute__((packed, aligned (4)));
757
4565e370
WB		 758struct ipr_hostrcb64_device_data_entry_enhanced {
759 struct ipr_ext_vpd vpd;
760 u8 ccin[4];
761 u8 res_path[8];
762 struct ipr_ext_vpd new_vpd;
763 u8 new_ccin[4];
764 struct ipr_ext_vpd ioa_last_with_dev_vpd;
765 struct ipr_ext_vpd cfc_last_with_dev_vpd;
766}__attribute__((packed, aligned (4)));
767
1da177e4 768struct ipr_hostrcb_array_data_entry {
cfc32139 769 struct ipr_vpd vpd;
1da177e4
LT		 770 struct ipr_res_addr expected_dev_res_addr;
771 struct ipr_res_addr dev_res_addr;
772}__attribute__((packed, aligned (4)));
773
4565e370
WB		 774struct ipr_hostrcb64_array_data_entry {
775 struct ipr_ext_vpd vpd;
776 u8 ccin[4];
777 u8 expected_res_path[8];
778 u8 res_path[8];
779}__attribute__((packed, aligned (4)));
780
ee0f05b8
BK		 781struct ipr_hostrcb_array_data_entry_enhanced {
782 struct ipr_ext_vpd vpd;
783 u8 ccin[4];
784 struct ipr_res_addr expected_dev_res_addr;
785 struct ipr_res_addr dev_res_addr;
786}__attribute__((packed, aligned (4)));
787
1da177e4 788struct ipr_hostrcb_type_ff_error {
ee0f05b8 789 __be32 ioa_data[502];
1da177e4
LT		 790}__attribute__((packed, aligned (4)));
791
792struct ipr_hostrcb_type_01_error {
793 __be32 seek_counter;
794 __be32 read_counter;
795 u8 sense_data[32];
796 __be32 ioa_data[236];
797}__attribute__((packed, aligned (4)));
798
799struct ipr_hostrcb_type_02_error {
cfc32139
BK		 800 struct ipr_vpd ioa_vpd;
801 struct ipr_vpd cfc_vpd;
802 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
803 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 804 __be32 ioa_data[3];
1da177e4
LT		 805}__attribute__((packed, aligned (4)));
806
ee0f05b8
BK		 807struct ipr_hostrcb_type_12_error {
808 struct ipr_ext_vpd ioa_vpd;
809 struct ipr_ext_vpd cfc_vpd;
810 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
811 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
812 __be32 ioa_data[3];
813}__attribute__((packed, aligned (4)));
814
1da177e4 815struct ipr_hostrcb_type_03_error {
cfc32139
BK		 816 struct ipr_vpd ioa_vpd;
817 struct ipr_vpd cfc_vpd;
1da177e4
LT		 818 __be32 errors_detected;
819 __be32 errors_logged;
820 u8 ioa_data[12];
cfc32139 821 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT		 822}__attribute__((packed, aligned (4)));
823
ee0f05b8
BK		 824struct ipr_hostrcb_type_13_error {
825 struct ipr_ext_vpd ioa_vpd;
826 struct ipr_ext_vpd cfc_vpd;
827 __be32 errors_detected;
828 __be32 errors_logged;
829 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
830}__attribute__((packed, aligned (4)));
831
4565e370
WB		 832struct ipr_hostrcb_type_23_error {
833 struct ipr_ext_vpd ioa_vpd;
834 struct ipr_ext_vpd cfc_vpd;
835 __be32 errors_detected;
836 __be32 errors_logged;
837 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
838}__attribute__((packed, aligned (4)));
839
1da177e4 840struct ipr_hostrcb_type_04_error {
cfc32139
BK		 841 struct ipr_vpd ioa_vpd;
842 struct ipr_vpd cfc_vpd;
1da177e4
LT		 843 u8 ioa_data[12];
844 struct ipr_hostrcb_array_data_entry array_member[10];
845 __be32 exposed_mode_adn;
846 __be32 array_id;
cfc32139 847 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT		 848 __be32 ioa_data2;
849 struct ipr_hostrcb_array_data_entry array_member2[8];
850 struct ipr_res_addr last_func_vset_res_addr;
851 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
852 u8 protection_level[8];
1da177e4
LT		 853}__attribute__((packed, aligned (4)));
854
ee0f05b8
BK		 855struct ipr_hostrcb_type_14_error {
856 struct ipr_ext_vpd ioa_vpd;
857 struct ipr_ext_vpd cfc_vpd;
858 __be32 exposed_mode_adn;
859 __be32 array_id;
860 struct ipr_res_addr last_func_vset_res_addr;
861 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
862 u8 protection_level[8];
863 __be32 num_entries;
864 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
865}__attribute__((packed, aligned (4)));
866
4565e370
WB		 867struct ipr_hostrcb_type_24_error {
868 struct ipr_ext_vpd ioa_vpd;
869 struct ipr_ext_vpd cfc_vpd;
870 u8 reserved[2];
871 u8 exposed_mode_adn;
872#define IPR_INVALID_ARRAY_DEV_NUM 0xff
873 u8 array_id;
874 u8 last_res_path[8];
875 u8 protection_level[8];
876 struct ipr_ext_vpd array_vpd;
877 u8 description[16];
878 u8 reserved2[3];
879 u8 num_entries;
880 struct ipr_hostrcb64_array_data_entry array_member[32];
881}__attribute__((packed, aligned (4)));
882
b0df54bb
BK		 883struct ipr_hostrcb_type_07_error {
884 u8 failure_reason[64];
885 struct ipr_vpd vpd;
886 u32 data[222];
887}__attribute__((packed, aligned (4)));
888
ee0f05b8
BK		 889struct ipr_hostrcb_type_17_error {
890 u8 failure_reason[64];
891 struct ipr_ext_vpd vpd;
892 u32 data[476];
893}__attribute__((packed, aligned (4)));
894
49dc6a18
BK		 895struct ipr_hostrcb_config_element {
896 u8 type_status;
897#define IPR_PATH_CFG_TYPE_MASK 0xF0
898#define IPR_PATH_CFG_NOT_EXIST 0x00
899#define IPR_PATH_CFG_IOA_PORT 0x10
900#define IPR_PATH_CFG_EXP_PORT 0x20
901#define IPR_PATH_CFG_DEVICE_PORT 0x30
902#define IPR_PATH_CFG_DEVICE_LUN 0x40
903
904#define IPR_PATH_CFG_STATUS_MASK 0x0F
905#define IPR_PATH_CFG_NO_PROB 0x00
906#define IPR_PATH_CFG_DEGRADED 0x01
907#define IPR_PATH_CFG_FAILED 0x02
908#define IPR_PATH_CFG_SUSPECT 0x03
909#define IPR_PATH_NOT_DETECTED 0x04
910#define IPR_PATH_INCORRECT_CONN 0x05
911
912 u8 cascaded_expander;
913 u8 phy;
914 u8 link_rate;
915#define IPR_PHY_LINK_RATE_MASK 0x0F
916
917 __be32 wwid[2];
918}__attribute__((packed, aligned (4)));
919
4565e370
WB		 920struct ipr_hostrcb64_config_element {
921 __be16 length;
922 u8 descriptor_id;
923#define IPR_DESCRIPTOR_MASK 0xC0
924#define IPR_DESCRIPTOR_SIS64 0x00
925
926 u8 reserved;
927 u8 type_status;
928
929 u8 reserved2[2];
930 u8 link_rate;
931
932 u8 res_path[8];
933 __be32 wwid[2];
934}__attribute__((packed, aligned (8)));
935
49dc6a18
BK		 936struct ipr_hostrcb_fabric_desc {
937 __be16 length;
938 u8 ioa_port;
939 u8 cascaded_expander;
940 u8 phy;
941 u8 path_state;
942#define IPR_PATH_ACTIVE_MASK 0xC0
943#define IPR_PATH_NO_INFO 0x00
944#define IPR_PATH_ACTIVE 0x40
945#define IPR_PATH_NOT_ACTIVE 0x80
946
947#define IPR_PATH_STATE_MASK 0x0F
948#define IPR_PATH_STATE_NO_INFO 0x00
949#define IPR_PATH_HEALTHY 0x01
950#define IPR_PATH_DEGRADED 0x02
951#define IPR_PATH_FAILED 0x03
952
953 __be16 num_entries;
954 struct ipr_hostrcb_config_element elem[1];
955}__attribute__((packed, aligned (4)));
956
4565e370
WB		 957struct ipr_hostrcb64_fabric_desc {
958 __be16 length;
959 u8 descriptor_id;
960
961 u8 reserved;
962 u8 path_state;
963
964 u8 reserved2[2];
965 u8 res_path[8];
966 u8 reserved3[6];
967 __be16 num_entries;
968 struct ipr_hostrcb64_config_element elem[1];
969}__attribute__((packed, aligned (8)));
970
49dc6a18
BK		 971#define for_each_fabric_cfg(fabric, cfg) \
972 for (cfg = (fabric)->elem; \
973 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
974 cfg++)
975
976struct ipr_hostrcb_type_20_error {
977 u8 failure_reason[64];
978 u8 reserved[3];
979 u8 num_entries;
980 struct ipr_hostrcb_fabric_desc desc[1];
981}__attribute__((packed, aligned (4)));
982
4565e370
WB		 983struct ipr_hostrcb_type_30_error {
984 u8 failure_reason[64];
985 u8 reserved[3];
986 u8 num_entries;
987 struct ipr_hostrcb64_fabric_desc desc[1];
988}__attribute__((packed, aligned (4)));
989
1da177e4 990struct ipr_hostrcb_error {
4565e370
WB		 991 __be32 fd_ioasc;
992 struct ipr_res_addr fd_res_addr;
993 __be32 fd_res_handle;
1da177e4
LT		 994 __be32 prc;
995 union {
996 struct ipr_hostrcb_type_ff_error type_ff_error;
997 struct ipr_hostrcb_type_01_error type_01_error;
998 struct ipr_hostrcb_type_02_error type_02_error;
999 struct ipr_hostrcb_type_03_error type_03_error;
1000 struct ipr_hostrcb_type_04_error type_04_error;
b0df54bb 1001 struct ipr_hostrcb_type_07_error type_07_error;
ee0f05b8
BK		 1002 struct ipr_hostrcb_type_12_error type_12_error;
1003 struct ipr_hostrcb_type_13_error type_13_error;
1004 struct ipr_hostrcb_type_14_error type_14_error;
1005 struct ipr_hostrcb_type_17_error type_17_error;
49dc6a18 1006 struct ipr_hostrcb_type_20_error type_20_error;
1da177e4
LT		 1007 } u;
1008}__attribute__((packed, aligned (4)));
1009
4565e370
WB		 1010struct ipr_hostrcb64_error {
1011 __be32 fd_ioasc;
1012 __be32 ioa_fw_level;
1013 __be32 fd_res_handle;
1014 __be32 prc;
1015 __be64 fd_dev_id;
1016 __be64 fd_lun;
1017 u8 fd_res_path[8];
1018 __be64 time_stamp;
1019 u8 reserved[2];
1020 union {
1021 struct ipr_hostrcb_type_ff_error type_ff_error;
1022 struct ipr_hostrcb_type_12_error type_12_error;
1023 struct ipr_hostrcb_type_17_error type_17_error;
1024 struct ipr_hostrcb_type_23_error type_23_error;
1025 struct ipr_hostrcb_type_24_error type_24_error;
1026 struct ipr_hostrcb_type_30_error type_30_error;
1027 } u;
1028}__attribute__((packed, aligned (8)));
1029
1da177e4
LT		 1030struct ipr_hostrcb_raw {
1031 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1032}__attribute__((packed, aligned (4)));
1033
1034struct ipr_hcam {
1035 u8 op_code;
1036#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1037#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1038
1039 u8 notify_type;
1040#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1041#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1042#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1043#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1044#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1045
1046 u8 notifications_lost;
1047#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1048#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1049
1050 u8 flags;
1051#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1052#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1053
1054 u8 overlay_id;
1055#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1056#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1057#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1058#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1059#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
b0df54bb 1060#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
ee0f05b8
BK		 1061#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1062#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1063#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1064#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1065#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
49dc6a18 1066#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
4565e370
WB		 1067#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1068#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1069#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1070#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1071#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1da177e4
LT		 1072
1073 u8 reserved1[3];
1074 __be32 ilid;
1075 __be32 time_since_last_ioa_reset;
1076 __be32 reserved2;
1077 __be32 length;
1078
1079 union {
1080 struct ipr_hostrcb_error error;
4565e370 1081 struct ipr_hostrcb64_error error64;
1da177e4
LT		 1082 struct ipr_hostrcb_cfg_ch_not ccn;
1083 struct ipr_hostrcb_raw raw;
1084 } u;
1085}__attribute__((packed, aligned (4)));
1086
1087struct ipr_hostrcb {
1088 struct ipr_hcam hcam;
1089 dma_addr_t hostrcb_dma;
1090 struct list_head queue;
49dc6a18 1091 struct ipr_ioa_cfg *ioa_cfg;
4565e370 1092 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1da177e4
LT		 1093};
1094
1095/* IPR smart dump table structures */
1096struct ipr_sdt_entry {
dcbad00e
WB		 1097 __be32 start_token;
1098 __be32 end_token;
1099 u8 reserved[4];
1da177e4
LT		 1100
1101 u8 flags;
1102#define IPR_SDT_ENDIAN 0x80
1103#define IPR_SDT_VALID_ENTRY 0x20
1104
1105 u8 resv;
1106 __be16 priority;
1107}__attribute__((packed, aligned (4)));
1108
1109struct ipr_sdt_header {
1110 __be32 state;
1111 __be32 num_entries;
1112 __be32 num_entries_used;
1113 __be32 dump_size;
1114}__attribute__((packed, aligned (4)));
1115
1116struct ipr_sdt {
1117 struct ipr_sdt_header hdr;
1118 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
1119}__attribute__((packed, aligned (4)));
1120
1121struct ipr_uc_sdt {
1122 struct ipr_sdt_header hdr;
1123 struct ipr_sdt_entry entry[1];
1124}__attribute__((packed, aligned (4)));
1125
1126/*
1127 * Driver types
1128 */
1129struct ipr_bus_attributes {
1130 u8 bus;
1131 u8 qas_enabled;
1132 u8 bus_width;
1133 u8 reserved;
1134 u32 max_xfer_rate;
1135};
1136
35a39691
BK		 1137struct ipr_sata_port {
1138 struct ipr_ioa_cfg *ioa_cfg;
1139 struct ata_port *ap;
1140 struct ipr_resource_entry *res;
1141 struct ipr_ioasa_gata ioasa;
1142};
1143
1da177e4 1144struct ipr_resource_entry {
1da177e4
LT		 1145 u8 needs_sync_complete:1;
1146 u8 in_erp:1;
1147 u8 add_to_ml:1;
1148 u8 del_from_ml:1;
1149 u8 resetting_device:1;
1150
3e7ebdfa
WB		 1151 u32 bus; /* AKA channel */
1152 u32 target; /* AKA id */
1153 u32 lun;
1154#define IPR_ARRAY_VIRTUAL_BUS 0x1
1155#define IPR_VSET_VIRTUAL_BUS 0x2
1156#define IPR_IOAFP_VIRTUAL_BUS 0x3
1157
1158#define IPR_GET_RES_PHYS_LOC(res) \
1159 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1160
1161 u8 ata_class;
1162
1163 u8 flags;
1164 __be16 res_flags;
1165
1166 __be32 type;
1167
1168 u8 qmodel;
1169 struct ipr_std_inq_data std_inq_data;
1170
1171 __be32 res_handle;
1172 __be64 dev_id;
1173 struct scsi_lun dev_lun;
1174 u8 res_path[8];
1175
1176 struct ipr_ioa_cfg *ioa_cfg;
1da177e4 1177 struct scsi_device *sdev;
35a39691 1178 struct ipr_sata_port *sata_port;
1da177e4 1179 struct list_head queue;
3e7ebdfa 1180}; /* struct ipr_resource_entry */
1da177e4
LT		 1181
1182struct ipr_resource_hdr {
1183 u16 num_entries;
1184 u16 reserved;
1185};
1186
1da177e4
LT		 1187struct ipr_misc_cbs {
1188 struct ipr_ioa_vpd ioa_vpd;
62275040 1189 struct ipr_inquiry_page0 page0_data;
1da177e4 1190 struct ipr_inquiry_page3 page3_data;
ac09c349 1191 struct ipr_inquiry_cap cap;
1da177e4
LT		 1192 struct ipr_mode_pages mode_pages;
1193 struct ipr_supported_device supp_dev;
1194};
1195
1196struct ipr_interrupt_offsets {
1197 unsigned long set_interrupt_mask_reg;
1198 unsigned long clr_interrupt_mask_reg;
1199 unsigned long sense_interrupt_mask_reg;
1200 unsigned long clr_interrupt_reg;
1201
1202 unsigned long sense_interrupt_reg;
1203 unsigned long ioarrin_reg;
1204 unsigned long sense_uproc_interrupt_reg;
1205 unsigned long set_uproc_interrupt_reg;
1206 unsigned long clr_uproc_interrupt_reg;
dcbad00e
WB		 1207
1208 unsigned long dump_addr_reg;
1209 unsigned long dump_data_reg;
1da177e4
LT		 1210};
1211
1212struct ipr_interrupts {
1213 void __iomem *set_interrupt_mask_reg;
1214 void __iomem *clr_interrupt_mask_reg;
1215 void __iomem *sense_interrupt_mask_reg;
1216 void __iomem *clr_interrupt_reg;
1217
1218 void __iomem *sense_interrupt_reg;
1219 void __iomem *ioarrin_reg;
1220 void __iomem *sense_uproc_interrupt_reg;
1221 void __iomem *set_uproc_interrupt_reg;
1222 void __iomem *clr_uproc_interrupt_reg;
dcbad00e
WB		 1223
1224 void __iomem *dump_addr_reg;
1225 void __iomem *dump_data_reg;
1da177e4
LT		 1226};
1227
1228struct ipr_chip_cfg_t {
1229 u32 mailbox;
1230 u8 cache_line_size;
1231 struct ipr_interrupt_offsets regs;
1232};
1233
1234struct ipr_chip_t {
1235 u16 vendor;
1236 u16 device;
1be7bd82
WB		 1237 u16 intr_type;
1238#define IPR_USE_LSI 0x00
1239#define IPR_USE_MSI 0x01
a32c055f
WB		 1240 u16 sis_type;
1241#define IPR_SIS32 0x00
1242#define IPR_SIS64 0x01
1da177e4
LT		 1243 const struct ipr_chip_cfg_t *cfg;
1244};
1245
1246enum ipr_shutdown_type {
1247 IPR_SHUTDOWN_NORMAL = 0x00,
1248 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1249 IPR_SHUTDOWN_ABBREV = 0x80,
1250 IPR_SHUTDOWN_NONE = 0x100
1251};
1252
1253struct ipr_trace_entry {
1254 u32 time;
1255
1256 u8 op_code;
35a39691 1257 u8 ata_op_code;
1da177e4
LT		 1258 u8 type;
1259#define IPR_TRACE_START 0x00
1260#define IPR_TRACE_FINISH 0xff
35a39691 1261 u8 cmd_index;
1da177e4
LT		 1262
1263 __be32 res_handle;
1264 union {
1265 u32 ioasc;
1266 u32 add_data;
1267 u32 res_addr;
1268 } u;
1269};
1270
1271struct ipr_sglist {
1272 u32 order;
1273 u32 num_sg;
12baa420 1274 u32 num_dma_sg;
1da177e4
LT		 1275 u32 buffer_len;
1276 struct scatterlist scatterlist[1];
1277};
1278
1279enum ipr_sdt_state {
1280 INACTIVE,
1281 WAIT_FOR_DUMP,
1282 GET_DUMP,
1283 ABORT_DUMP,
1284 DUMP_OBTAINED
1285};
1286
1287/* Per-controller data */
1288struct ipr_ioa_cfg {
1289 char eye_catcher[8];
1290#define IPR_EYECATCHER "iprcfg"
1291
1292 struct list_head queue;
1293
1294 u8 allow_interrupts:1;
1295 u8 in_reset_reload:1;
1296 u8 in_ioa_bringdown:1;
1297 u8 ioa_unit_checked:1;
1298 u8 ioa_is_dead:1;
1299 u8 dump_taken:1;
1300 u8 allow_cmds:1;
1301 u8 allow_ml_add_del:1;
ce155cce 1302 u8 needs_hard_reset:1;
ac09c349 1303 u8 dual_raid:1;
463fc696 1304 u8 needs_warm_reset:1;
95fecd90 1305 u8 msi_received:1;
a32c055f 1306 u8 sis64:1;
463fc696
BK		 1307
1308 u8 revid;
1da177e4 1309
3e7ebdfa
WB		 1310 /*
1311 * Bitmaps for SIS64 generated target values
1312 */
1313 unsigned long *target_ids;
1314 unsigned long *array_ids;
1315 unsigned long *vset_ids;
1316
1da177e4
LT		 1317 u16 type; /* CCIN of the card */
1318
1319 u8 log_level;
1320#define IPR_MAX_LOG_LEVEL 4
1321#define IPR_DEFAULT_LOG_LEVEL 2
1322
1323#define IPR_NUM_TRACE_INDEX_BITS 8
1324#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1325#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1326 char trace_start[8];
1327#define IPR_TRACE_START_LABEL "trace"
1328 struct ipr_trace_entry *trace;
1329 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
1330
1331 /*
1332 * Queue for free command blocks
1333 */
1334 char ipr_free_label[8];
1335#define IPR_FREEQ_LABEL "free-q"
1336 struct list_head free_q;
1337
1338 /*
1339 * Queue for command blocks outstanding to the adapter
1340 */
1341 char ipr_pending_label[8];
1342#define IPR_PENDQ_LABEL "pend-q"
1343 struct list_head pending_q;
1344
1345 char cfg_table_start[8];
1346#define IPR_CFG_TBL_START "cfg"
3e7ebdfa
WB		 1347 union {
1348 struct ipr_config_table *cfg_table;
1349 struct ipr_config_table64 *cfg_table64;
1350 } u;
1da177e4 1351 dma_addr_t cfg_table_dma;
3e7ebdfa
WB		 1352 u32 cfg_table_size;
1353 u32 max_devs_supported;
1da177e4
LT		 1354
1355 char resource_table_label[8];
1356#define IPR_RES_TABLE_LABEL "res_tbl"
1357 struct ipr_resource_entry *res_entries;
1358 struct list_head free_res_q;
1359 struct list_head used_res_q;
1360
1361 char ipr_hcam_label[8];
1362#define IPR_HCAM_LABEL "hcams"
1363 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1364 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1365 struct list_head hostrcb_free_q;
1366 struct list_head hostrcb_pending_q;
1367
1368 __be32 *host_rrq;
1369 dma_addr_t host_rrq_dma;
1370#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
1371#define IPR_HRRQ_RESP_BIT_SET 0x00000002
1372#define IPR_HRRQ_TOGGLE_BIT 0x00000001
1373#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
1374 volatile __be32 *hrrq_start;
1375 volatile __be32 *hrrq_end;
1376 volatile __be32 *hrrq_curr;
1377 volatile u32 toggle_bit;
1378
1379 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1380
5469cb5b 1381 unsigned int transop_timeout;
1da177e4 1382 const struct ipr_chip_cfg_t *chip_cfg;
1be7bd82 1383 const struct ipr_chip_t *ipr_chip;
1da177e4
LT		 1384
1385 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
1386 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
1387 void __iomem *ioa_mailbox;
1388 struct ipr_interrupts regs;
1389
1390 u16 saved_pcix_cmd_reg;
1391 u16 reset_retries;
1392
1393 u32 errors_logged;
3d1d0da6 1394 u32 doorbell;
1da177e4
LT		 1395
1396 struct Scsi_Host *host;
1397 struct pci_dev *pdev;
1398 struct ipr_sglist *ucode_sglist;
1da177e4
LT		 1399 u8 saved_mode_page_len;
1400
1401 struct work_struct work_q;
1402
1403 wait_queue_head_t reset_wait_q;
95fecd90 1404 wait_queue_head_t msi_wait_q;
1da177e4
LT		 1405
1406 struct ipr_dump *dump;
1407 enum ipr_sdt_state sdt_state;
1408
1409 struct ipr_misc_cbs *vpd_cbs;
1410 dma_addr_t vpd_cbs_dma;
1411
1412 struct pci_pool *ipr_cmd_pool;
1413
1414 struct ipr_cmnd *reset_cmd;
463fc696 1415 int (*reset) (struct ipr_cmnd *);
1da177e4 1416
35a39691 1417 struct ata_host ata_host;
1da177e4 1418 char ipr_cmd_label[8];
0124ca9d 1419#define IPR_CMD_LABEL "ipr_cmd"
1da177e4 1420 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
a32c055f 1421 dma_addr_t ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
3e7ebdfa 1422}; /* struct ipr_ioa_cfg */
1da177e4
LT		 1423
1424struct ipr_cmnd {
1425 struct ipr_ioarcb ioarcb;
a32c055f
WB		 1426 union {
1427 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1428 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1429 struct ipr_ata64_ioadl ata_ioadl;
1430 } i;
1da177e4 1431 struct ipr_ioasa ioasa;
1da177e4
LT		 1432 struct list_head queue;
1433 struct scsi_cmnd *scsi_cmd;
35a39691 1434 struct ata_queued_cmd *qc;
1da177e4
LT		 1435 struct completion completion;
1436 struct timer_list timer;
1437 void (*done) (struct ipr_cmnd *);
1438 int (*job_step) (struct ipr_cmnd *);
dfed823e 1439 int (*job_step_failed) (struct ipr_cmnd *);
1da177e4
LT		 1440 u16 cmd_index;
1441 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1442 dma_addr_t sense_buffer_dma;
1443 unsigned short dma_use_sg;
a32c055f 1444 dma_addr_t dma_addr;
1da177e4
LT		 1445 struct ipr_cmnd *sibling;
1446 union {
1447 enum ipr_shutdown_type shutdown_type;
1448 struct ipr_hostrcb *hostrcb;
1449 unsigned long time_left;
1450 unsigned long scratch;
1451 struct ipr_resource_entry *res;
1452 struct scsi_device *sdev;
1453 } u;
1454
1455 struct ipr_ioa_cfg *ioa_cfg;
1456};
1457
1458struct ipr_ses_table_entry {
1459 char product_id[17];
1460 char compare_product_id_byte[17];
1461 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1462};
1463
1464struct ipr_dump_header {
1465 u32 eye_catcher;
1466#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1467 u32 len;
1468 u32 num_entries;
1469 u32 first_entry_offset;
1470 u32 status;
1471#define IPR_DUMP_STATUS_SUCCESS 0
1472#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1473#define IPR_DUMP_STATUS_FAILED 0xffffffff
1474 u32 os;
1475#define IPR_DUMP_OS_LINUX 0x4C4E5558
1476 u32 driver_name;
1477#define IPR_DUMP_DRIVER_NAME 0x49505232
1478}__attribute__((packed, aligned (4)));
1479
1480struct ipr_dump_entry_header {
1481 u32 eye_catcher;
1482#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1483 u32 len;
1484 u32 num_elems;
1485 u32 offset;
1486 u32 data_type;
1487#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1488#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1489 u32 id;
1490#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1491#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1492#define IPR_DUMP_TRACE_ID 0x54524143
1493#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1494#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1495#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1496#define IPR_DUMP_PEND_OPS 0x414F5053
1497 u32 status;
1498}__attribute__((packed, aligned (4)));
1499
1500struct ipr_dump_location_entry {
1501 struct ipr_dump_entry_header hdr;
71610f55 1502 u8 location[20];
1da177e4
LT		 1503}__attribute__((packed));
1504
1505struct ipr_dump_trace_entry {
1506 struct ipr_dump_entry_header hdr;
1507 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1508}__attribute__((packed, aligned (4)));
1509
1510struct ipr_dump_version_entry {
1511 struct ipr_dump_entry_header hdr;
1512 u8 version[sizeof(IPR_DRIVER_VERSION)];
1513};
1514
1515struct ipr_dump_ioa_type_entry {
1516 struct ipr_dump_entry_header hdr;
1517 u32 type;
1518 u32 fw_version;
1519};
1520
1521struct ipr_driver_dump {
1522 struct ipr_dump_header hdr;
1523 struct ipr_dump_version_entry version_entry;
1524 struct ipr_dump_location_entry location_entry;
1525 struct ipr_dump_ioa_type_entry ioa_type_entry;
1526 struct ipr_dump_trace_entry trace_entry;
1527}__attribute__((packed));
1528
1529struct ipr_ioa_dump {
1530 struct ipr_dump_entry_header hdr;
1531 struct ipr_sdt sdt;
1532 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1533 u32 reserved;
1534 u32 next_page_index;
1535 u32 page_offset;
1536 u32 format;
1da177e4
LT		 1537}__attribute__((packed, aligned (4)));
1538
1539struct ipr_dump {
1540 struct kref kref;
1541 struct ipr_ioa_cfg *ioa_cfg;
1542 struct ipr_driver_dump driver_dump;
1543 struct ipr_ioa_dump ioa_dump;
1544};
1545
1546struct ipr_error_table_t {
1547 u32 ioasc;
1548 int log_ioasa;
1549 int log_hcam;
1550 char *error;
1551};
1552
1553struct ipr_software_inq_lid_info {
1554 __be32 load_id;
1555 __be32 timestamp[3];
1556}__attribute__((packed, aligned (4)));
1557
1558struct ipr_ucode_image_header {
1559 __be32 header_length;
1560 __be32 lid_table_offset;
1561 u8 major_release;
1562 u8 card_type;
1563 u8 minor_release[2];
1564 u8 reserved[20];
1565 char eyecatcher[16];
1566 __be32 num_lids;
1567 struct ipr_software_inq_lid_info lid[1];
1568}__attribute__((packed, aligned (4)));
1569
1570/*
1571 * Macros
1572 */
d3c74871 1573#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1da177e4
LT		 1574
1575#ifdef CONFIG_SCSI_IPR_TRACE
1576#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1577#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1578#else
1579#define ipr_create_trace_file(kobj, attr) 0
1580#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1581#endif
1582
1583#ifdef CONFIG_SCSI_IPR_DUMP
1584#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1585#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1586#else
1587#define ipr_create_dump_file(kobj, attr) 0
1588#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1589#endif
1590
1591/*
1592 * Error logging macros
1593 */
1594#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1595#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1da177e4
LT		 1596#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1597
3e7ebdfa
WB		 1598#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1599 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1600 bus, target, lun, ##__VA_ARGS__)
1601
1602#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1603 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1604
fb3ed3cb
BK		 1605#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1606 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1607 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1da177e4 1608
fb3ed3cb
BK		 1609#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1610 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1da177e4 1611
fa15b1f6
BK		 1612#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1613{ \
1614 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1615 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1616 } else { \
1617 ipr_err(fmt": %d:%d:%d:%d\n", \
1618 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1619 (res).bus, (res).target, (res).lun); \
1620 } \
1621}
1622
49dc6a18 1623#define ipr_hcam_err(hostrcb, fmt, ...) \
4565e370
WB		 1624{ \
1625 if (ipr_is_device(hostrcb)) { \
1626 if ((hostrcb)->ioa_cfg->sis64) { \
1627 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1628 ipr_format_resource_path(&hostrcb->hcam.u.error64.fd_res_path[0], \
1629 &hostrcb->rp_buffer[0]), \
1630 __VA_ARGS__); \
1631 } else { \
1632 ipr_ra_err((hostrcb)->ioa_cfg, \
1633 (hostrcb)->hcam.u.error.fd_res_addr, \
1634 fmt, __VA_ARGS__); \
1635 } \
1636 } else { \
1637 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1638 } \
49dc6a18
BK		 1639}
1640
1da177e4 1641#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
cadbd4a5 1642 __FILE__, __func__, __LINE__)
1da177e4 1643
cadbd4a5
HH		 1644#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1645#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1da177e4
LT		 1646
1647#define ipr_err_separator \
1648ipr_err("----------------------------------------------------------\n")
1649
1650
1651/*
1652 * Inlines
1653 */
1654
1655/**
1656 * ipr_is_ioa_resource - Determine if a resource is the IOA
1657 * @res: resource entry struct
1658 *
1659 * Return value:
1660 * 1 if IOA / 0 if not IOA
1661 **/
1662static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1663{
3e7ebdfa 1664 return res->type == IPR_RES_TYPE_IOAFP;
1da177e4
LT		 1665}
1666
1667/**
1668 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1669 * @res: resource entry struct
1670 *
1671 * Return value:
1672 * 1 if AF DASD / 0 if not AF DASD
1673 **/
1674static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1675{
3e7ebdfa
WB		 1676 return res->type == IPR_RES_TYPE_AF_DASD ||
1677 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1da177e4
LT		 1678}
1679
1680/**
1681 * ipr_is_vset_device - Determine if a resource is a VSET
1682 * @res: resource entry struct
1683 *
1684 * Return value:
1685 * 1 if VSET / 0 if not VSET
1686 **/
1687static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1688{
3e7ebdfa 1689 return res->type == IPR_RES_TYPE_VOLUME_SET;
1da177e4
LT		 1690}
1691
1692/**
1693 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1694 * @res: resource entry struct
1695 *
1696 * Return value:
1697 * 1 if GSCSI / 0 if not GSCSI
1698 **/
1699static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1700{
3e7ebdfa 1701 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1da177e4
LT		 1702}
1703
e4fbf44e
BK		 1704/**
1705 * ipr_is_scsi_disk - Determine if a resource is a SCSI disk
1706 * @res: resource entry struct
1707 *
1708 * Return value:
1709 * 1 if SCSI disk / 0 if not SCSI disk
1710 **/
1711static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1712{
1713 if (ipr_is_af_dasd_device(res) ||
3e7ebdfa 1714 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
e4fbf44e
BK		 1715 return 1;
1716 else
1717 return 0;
1718}
1719
b5145d25
BK		 1720/**
1721 * ipr_is_gata - Determine if a resource is a generic ATA resource
1722 * @res: resource entry struct
1723 *
1724 * Return value:
1725 * 1 if GATA / 0 if not GATA
1726 **/
1727static inline int ipr_is_gata(struct ipr_resource_entry *res)
1728{
3e7ebdfa 1729 return res->type == IPR_RES_TYPE_GENERIC_ATA;
b5145d25
BK		 1730}
1731
ee0a90fa
BK		 1732/**
1733 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1734 * @res: resource entry struct
1735 *
1736 * Return value:
1737 * 1 if NACA queueing model / 0 if not NACA queueing model
1738 **/
1739static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1740{
3e7ebdfa 1741 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
ee0a90fa
BK		 1742 return 1;
1743 return 0;
1744}
1745
1da177e4 1746/**
4565e370
WB		 1747 * ipr_is_device - Determine if the hostrcb structure is related to a device
1748 * @hostrcb: host resource control blocks struct
1da177e4
LT		 1749 *
1750 * Return value:
1751 * 1 if AF / 0 if not AF
1752 **/
4565e370 1753static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1da177e4 1754{
4565e370
WB		 1755 struct ipr_res_addr *res_addr;
1756 u8 *res_path;
1757
1758 if (hostrcb->ioa_cfg->sis64) {
1759 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1760 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1761 res_path[0] == 0x81) && res_path[2] != 0xFF)
1762 return 1;
1763 } else {
1764 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1765
1766 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1767 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1768 return 1;
1769 }
1da177e4
LT		 1770 return 0;
1771}
1772
1773/**
1774 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1775 * @sdt_word: SDT address
1776 *
1777 * Return value:
1778 * 1 if format 2 / 0 if not
1779 **/
1780static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1781{
1782 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1783
1784 switch (bar_sel) {
1785 case IPR_SDT_FMT2_BAR0_SEL:
1786 case IPR_SDT_FMT2_BAR1_SEL:
1787 case IPR_SDT_FMT2_BAR2_SEL:
1788 case IPR_SDT_FMT2_BAR3_SEL:
1789 case IPR_SDT_FMT2_BAR4_SEL:
1790 case IPR_SDT_FMT2_BAR5_SEL:
1791 case IPR_SDT_FMT2_EXP_ROM_SEL:
1792 return 1;
1793 };
1794
1795 return 0;
1796}
1797
1798#endif
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