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Commit | Line | Data |
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1da177e4 LT |
1 | /* |
2 | * ipr.h -- driver for IBM Power Linux RAID adapters | |
3 | * | |
4 | * Written By: Brian King <brking@us.ibm.com>, IBM Corporation | |
5 | * | |
6 | * Copyright (C) 2003, 2004 IBM Corporation | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
fa195afe | 22 | * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors |
1da177e4 LT |
23 | * that broke 64bit platforms. |
24 | */ | |
25 | ||
26 | #ifndef _IPR_H | |
27 | #define _IPR_H | |
28 | ||
46d74563 | 29 | #include <asm/unaligned.h> |
1da177e4 LT |
30 | #include <linux/types.h> |
31 | #include <linux/completion.h> | |
35a39691 | 32 | #include <linux/libata.h> |
1da177e4 LT |
33 | #include <linux/list.h> |
34 | #include <linux/kref.h> | |
b53d124a | 35 | #include <linux/blk-iopoll.h> |
1da177e4 LT |
36 | #include <scsi/scsi.h> |
37 | #include <scsi/scsi_cmnd.h> | |
38 | ||
39 | /* | |
40 | * Literals | |
41 | */ | |
4415e445 | 42 | #define IPR_DRIVER_VERSION "2.6.0" |
43 | #define IPR_DRIVER_DATE "(November 16, 2012)" | |
1da177e4 | 44 | |
1da177e4 LT |
45 | /* |
46 | * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding | |
47 | * ops per device for devices not running tagged command queuing. | |
48 | * This can be adjusted at runtime through sysfs device attributes. | |
49 | */ | |
50 | #define IPR_MAX_CMD_PER_LUN 6 | |
b5145d25 | 51 | #define IPR_MAX_CMD_PER_ATA_LUN 1 |
1da177e4 LT |
52 | |
53 | /* | |
54 | * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of | |
55 | * ops the mid-layer can send to the adapter. | |
56 | */ | |
89aad428 | 57 | #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) |
1da177e4 | 58 | |
60e7486b | 59 | #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 |
d7b4627f WB |
60 | |
61 | #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D | |
cd9b3d04 | 62 | #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A |
60e7486b | 63 | |
1da177e4 LT |
64 | #define IPR_SUBS_DEV_ID_2780 0x0264 |
65 | #define IPR_SUBS_DEV_ID_5702 0x0266 | |
66 | #define IPR_SUBS_DEV_ID_5703 0x0278 | |
b0f56d3d WB |
67 | #define IPR_SUBS_DEV_ID_572E 0x028D |
68 | #define IPR_SUBS_DEV_ID_573E 0x02D3 | |
69 | #define IPR_SUBS_DEV_ID_573D 0x02D4 | |
1da177e4 LT |
70 | #define IPR_SUBS_DEV_ID_571A 0x02C0 |
71 | #define IPR_SUBS_DEV_ID_571B 0x02BE | |
b0f56d3d | 72 | #define IPR_SUBS_DEV_ID_571E 0x02BF |
86f51436 BK |
73 | #define IPR_SUBS_DEV_ID_571F 0x02D5 |
74 | #define IPR_SUBS_DEV_ID_572A 0x02C1 | |
75 | #define IPR_SUBS_DEV_ID_572B 0x02C2 | |
60e7486b | 76 | #define IPR_SUBS_DEV_ID_572F 0x02C3 |
185eb31c | 77 | #define IPR_SUBS_DEV_ID_574E 0x030A |
86f51436 | 78 | #define IPR_SUBS_DEV_ID_575B 0x030D |
60e7486b | 79 | #define IPR_SUBS_DEV_ID_575C 0x0338 |
185eb31c | 80 | #define IPR_SUBS_DEV_ID_57B3 0x033A |
60e7486b BK |
81 | #define IPR_SUBS_DEV_ID_57B7 0x0360 |
82 | #define IPR_SUBS_DEV_ID_57B8 0x02C2 | |
1da177e4 | 83 | |
d7b4627f WB |
84 | #define IPR_SUBS_DEV_ID_57B4 0x033B |
85 | #define IPR_SUBS_DEV_ID_57B2 0x035F | |
b8d5d568 | 86 | #define IPR_SUBS_DEV_ID_57C0 0x0352 |
5a918353 | 87 | #define IPR_SUBS_DEV_ID_57C3 0x0353 |
32622bde | 88 | #define IPR_SUBS_DEV_ID_57C4 0x0354 |
d7b4627f | 89 | #define IPR_SUBS_DEV_ID_57C6 0x0357 |
b0f56d3d | 90 | #define IPR_SUBS_DEV_ID_57CC 0x035C |
d7b4627f WB |
91 | |
92 | #define IPR_SUBS_DEV_ID_57B5 0x033C | |
93 | #define IPR_SUBS_DEV_ID_57CE 0x035E | |
94 | #define IPR_SUBS_DEV_ID_57B1 0x0355 | |
95 | ||
96 | #define IPR_SUBS_DEV_ID_574D 0x0356 | |
cd9b3d04 | 97 | #define IPR_SUBS_DEV_ID_57C8 0x035D |
d7b4627f | 98 | |
b8d5d568 | 99 | #define IPR_SUBS_DEV_ID_57D5 0x03FB |
100 | #define IPR_SUBS_DEV_ID_57D6 0x03FC | |
101 | #define IPR_SUBS_DEV_ID_57D7 0x03FF | |
102 | #define IPR_SUBS_DEV_ID_57D8 0x03FE | |
43c5fdaf | 103 | #define IPR_SUBS_DEV_ID_57D9 0x046D |
f94d9964 | 104 | #define IPR_SUBS_DEV_ID_57DA 0x04CA |
43c5fdaf | 105 | #define IPR_SUBS_DEV_ID_57EB 0x0474 |
106 | #define IPR_SUBS_DEV_ID_57EC 0x0475 | |
107 | #define IPR_SUBS_DEV_ID_57ED 0x0499 | |
108 | #define IPR_SUBS_DEV_ID_57EE 0x049A | |
109 | #define IPR_SUBS_DEV_ID_57EF 0x049B | |
110 | #define IPR_SUBS_DEV_ID_57F0 0x049C | |
5eeac3e9 WX |
111 | #define IPR_SUBS_DEV_ID_2CCA 0x04C7 |
112 | #define IPR_SUBS_DEV_ID_2CD2 0x04C8 | |
113 | #define IPR_SUBS_DEV_ID_2CCD 0x04C9 | |
1da177e4 LT |
114 | #define IPR_NAME "ipr" |
115 | ||
116 | /* | |
117 | * Return codes | |
118 | */ | |
119 | #define IPR_RC_JOB_CONTINUE 1 | |
120 | #define IPR_RC_JOB_RETURN 2 | |
121 | ||
122 | /* | |
123 | * IOASCs | |
124 | */ | |
125 | #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 | |
65f56475 | 126 | #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 |
1da177e4 LT |
127 | #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 |
128 | #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 | |
129 | #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 | |
130 | #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 | |
131 | #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 | |
132 | #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF | |
d247a70a | 133 | #define IPR_IOASC_HW_CMD_FAILED 0x046E0000 |
dfed823e | 134 | #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 |
1da177e4 | 135 | #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 |
b0df54bb BK |
136 | #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 |
137 | #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 | |
1da177e4 LT |
138 | #define IPR_IOASC_BUS_WAS_RESET 0x06290000 |
139 | #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 | |
140 | #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 | |
f8ee25d7 | 141 | #define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200 |
1da177e4 LT |
142 | |
143 | #define IPR_FIRST_DRIVER_IOASC 0x10000000 | |
144 | #define IPR_IOASC_IOA_WAS_RESET 0x10000001 | |
145 | #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 | |
146 | ||
5469cb5b BK |
147 | /* Driver data flags */ |
148 | #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 | |
463fc696 | 149 | #define IPR_USE_PCI_WARM_RESET 0x00000002 |
5469cb5b | 150 | |
ac719aba | 151 | #define IPR_DEFAULT_MAX_ERROR_DUMP 984 |
1da177e4 LT |
152 | #define IPR_NUM_LOG_HCAMS 2 |
153 | #define IPR_NUM_CFG_CHG_HCAMS 2 | |
154 | #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) | |
3e7ebdfa WB |
155 | |
156 | #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 | |
157 | #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff | |
158 | ||
d71a8b0c | 159 | #define IPR_MAX_NUM_TARGETS_PER_BUS 256 |
1da177e4 | 160 | #define IPR_MAX_NUM_LUNS_PER_TARGET 256 |
1da177e4 LT |
161 | #define IPR_VSET_BUS 0xff |
162 | #define IPR_IOA_BUS 0xff | |
163 | #define IPR_IOA_TARGET 0xff | |
164 | #define IPR_IOA_LUN 0xff | |
b5145d25 | 165 | #define IPR_MAX_NUM_BUSES 16 |
1da177e4 LT |
166 | |
167 | #define IPR_NUM_RESET_RELOAD_RETRIES 3 | |
168 | ||
169 | /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ | |
170 | #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ | |
f72919ec | 171 | ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) |
1da177e4 | 172 | |
89aad428 | 173 | #define IPR_MAX_COMMANDS 100 |
1da177e4 LT |
174 | #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ |
175 | IPR_NUM_INTERNAL_CMD_BLKS) | |
176 | ||
177 | #define IPR_MAX_PHYSICAL_DEVS 192 | |
3e7ebdfa WB |
178 | #define IPR_DEFAULT_SIS64_DEVS 1024 |
179 | #define IPR_MAX_SIS64_DEVS 4096 | |
1da177e4 LT |
180 | |
181 | #define IPR_MAX_SGLIST 64 | |
182 | #define IPR_IOA_MAX_SECTORS 32767 | |
183 | #define IPR_VSET_MAX_SECTORS 512 | |
184 | #define IPR_MAX_CDB_LEN 16 | |
3feeb89d | 185 | #define IPR_MAX_HRRQ_RETRIES 3 |
1da177e4 LT |
186 | |
187 | #define IPR_DEFAULT_BUS_WIDTH 16 | |
188 | #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
189 | #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
190 | #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
191 | #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) | |
192 | ||
193 | #define IPR_IOA_RES_HANDLE 0xffffffff | |
1121b794 | 194 | #define IPR_INVALID_RES_HANDLE 0 |
1da177e4 LT |
195 | #define IPR_IOA_RES_ADDR 0x00ffffff |
196 | ||
197 | /* | |
198 | * Adapter Commands | |
199 | */ | |
4fdd7c7a BK |
200 | #define IPR_CANCEL_REQUEST 0xC0 |
201 | #define IPR_CANCEL_64BIT_IOARCB 0x01 | |
1da177e4 LT |
202 | #define IPR_QUERY_RSRC_STATE 0xC2 |
203 | #define IPR_RESET_DEVICE 0xC3 | |
204 | #define IPR_RESET_TYPE_SELECT 0x80 | |
205 | #define IPR_LUN_RESET 0x40 | |
206 | #define IPR_TARGET_RESET 0x20 | |
207 | #define IPR_BUS_RESET 0x10 | |
b5145d25 | 208 | #define IPR_ATA_PHY_RESET 0x80 |
1da177e4 LT |
209 | #define IPR_ID_HOST_RR_Q 0xC4 |
210 | #define IPR_QUERY_IOA_CONFIG 0xC5 | |
211 | #define IPR_CANCEL_ALL_REQUESTS 0xCE | |
212 | #define IPR_HOST_CONTROLLED_ASYNC 0xCF | |
213 | #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 | |
214 | #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 | |
215 | #define IPR_SET_SUPPORTED_DEVICES 0xFB | |
3e7ebdfa | 216 | #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 |
1da177e4 LT |
217 | #define IPR_IOA_SHUTDOWN 0xF7 |
218 | #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 | |
219 | ||
220 | /* | |
221 | * Timeouts | |
222 | */ | |
223 | #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) | |
224 | #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) | |
225 | #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) | |
ac09c349 | 226 | #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) |
1da177e4 | 227 | #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
4fdd7c7a | 228 | #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
1da177e4 LT |
229 | #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
230 | #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
231 | #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
14ed9cc7 | 232 | #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) |
1da177e4 LT |
233 | #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) |
234 | #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) | |
235 | #define IPR_OPERATIONAL_TIMEOUT (5 * 60) | |
5469cb5b | 236 | #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) |
1da177e4 LT |
237 | #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) |
238 | #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) | |
239 | #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) | |
6270e593 | 240 | #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) |
463fc696 | 241 | #define IPR_PCI_RESET_TIMEOUT (HZ / 2) |
4d4dd706 KSS |
242 | #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ) |
243 | #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ) | |
110def85 WB |
244 | #define IPR_DUMP_DELAY_SECONDS 4 |
245 | #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ) | |
1da177e4 LT |
246 | |
247 | /* | |
248 | * SCSI Literals | |
249 | */ | |
250 | #define IPR_VENDOR_ID_LEN 8 | |
251 | #define IPR_PROD_ID_LEN 16 | |
252 | #define IPR_SERIAL_NUM_LEN 8 | |
253 | ||
254 | /* | |
255 | * Hardware literals | |
256 | */ | |
257 | #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff | |
258 | #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 | |
259 | #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 | |
260 | #define IPR_GET_FMT2_BAR_SEL(mbx) \ | |
261 | (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) | |
262 | #define IPR_SDT_FMT2_BAR0_SEL 0x0 | |
263 | #define IPR_SDT_FMT2_BAR1_SEL 0x1 | |
264 | #define IPR_SDT_FMT2_BAR2_SEL 0x2 | |
265 | #define IPR_SDT_FMT2_BAR3_SEL 0x3 | |
266 | #define IPR_SDT_FMT2_BAR4_SEL 0x4 | |
267 | #define IPR_SDT_FMT2_BAR5_SEL 0x5 | |
268 | #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 | |
269 | #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 | |
dcbad00e | 270 | #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 |
1da177e4 | 271 | #define IPR_DOORBELL 0x82800000 |
3d1d0da6 | 272 | #define IPR_RUNTIME_RESET 0x40000000 |
1da177e4 | 273 | |
214777ba | 274 | #define IPR_IPL_INIT_MIN_STAGE_TIME 5 |
438b0331 | 275 | #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15 |
214777ba WB |
276 | #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 |
277 | #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 | |
278 | #define IPR_IPL_INIT_STAGE_MASK 0xff000000 | |
279 | #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff | |
280 | #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) | |
281 | ||
1da177e4 LT |
282 | #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) |
283 | #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) | |
284 | #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) | |
285 | #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) | |
286 | #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) | |
287 | #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) | |
288 | #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) | |
289 | #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) | |
290 | #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) | |
291 | #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) | |
292 | #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) | |
293 | ||
294 | #define IPR_PCII_ERROR_INTERRUPTS \ | |
295 | (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ | |
296 | IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) | |
297 | ||
298 | #define IPR_PCII_OPER_INTERRUPTS \ | |
299 | (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) | |
300 | ||
301 | #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) | |
302 | #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) | |
cb237ef7 | 303 | #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23) |
1da177e4 LT |
304 | |
305 | #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
306 | #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
307 | ||
308 | /* | |
309 | * Dump literals | |
310 | */ | |
4d4dd706 | 311 | #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) |
95d8a25b | 312 | #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024) |
4d4dd706 KSS |
313 | #define IPR_FMT2_NUM_SDT_ENTRIES 511 |
314 | #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF | |
315 | #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
316 | #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
1da177e4 LT |
317 | |
318 | /* | |
319 | * Misc literals | |
320 | */ | |
321 | #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST | |
6634ff7c | 322 | #define IPR_MAX_MSIX_VECTORS 0x10 |
05a6538a | 323 | #define IPR_MAX_HRRQ_NUM 0x10 |
324 | #define IPR_INIT_HRRQ 0x0 | |
1da177e4 LT |
325 | |
326 | /* | |
327 | * Adapter interface types | |
328 | */ | |
329 | ||
330 | struct ipr_res_addr { | |
331 | u8 reserved; | |
332 | u8 bus; | |
333 | u8 target; | |
334 | u8 lun; | |
335 | #define IPR_GET_PHYS_LOC(res_addr) \ | |
336 | (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) | |
337 | }__attribute__((packed, aligned (4))); | |
338 | ||
339 | struct ipr_std_inq_vpids { | |
340 | u8 vendor_id[IPR_VENDOR_ID_LEN]; | |
341 | u8 product_id[IPR_PROD_ID_LEN]; | |
342 | }__attribute__((packed)); | |
343 | ||
cfc32139 BK |
344 | struct ipr_vpd { |
345 | struct ipr_std_inq_vpids vpids; | |
346 | u8 sn[IPR_SERIAL_NUM_LEN]; | |
347 | }__attribute__((packed)); | |
348 | ||
ee0f05b8 BK |
349 | struct ipr_ext_vpd { |
350 | struct ipr_vpd vpd; | |
351 | __be32 wwid[2]; | |
352 | }__attribute__((packed)); | |
353 | ||
7262026f WB |
354 | struct ipr_ext_vpd64 { |
355 | struct ipr_vpd vpd; | |
356 | __be32 wwid[4]; | |
357 | }__attribute__((packed)); | |
358 | ||
1da177e4 LT |
359 | struct ipr_std_inq_data { |
360 | u8 peri_qual_dev_type; | |
361 | #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) | |
362 | #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) | |
363 | ||
364 | u8 removeable_medium_rsvd; | |
365 | #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 | |
366 | ||
367 | #define IPR_IS_DASD_DEVICE(std_inq) \ | |
368 | ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ | |
369 | !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) | |
370 | ||
371 | #define IPR_IS_SES_DEVICE(std_inq) \ | |
372 | (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) | |
373 | ||
374 | u8 version; | |
375 | u8 aen_naca_fmt; | |
376 | u8 additional_len; | |
377 | u8 sccs_rsvd; | |
378 | u8 bq_enc_multi; | |
379 | u8 sync_cmdq_flags; | |
380 | ||
381 | struct ipr_std_inq_vpids vpids; | |
382 | ||
383 | u8 ros_rsvd_ram_rsvd[4]; | |
384 | ||
385 | u8 serial_num[IPR_SERIAL_NUM_LEN]; | |
386 | }__attribute__ ((packed)); | |
387 | ||
3e7ebdfa WB |
388 | #define IPR_RES_TYPE_AF_DASD 0x00 |
389 | #define IPR_RES_TYPE_GENERIC_SCSI 0x01 | |
390 | #define IPR_RES_TYPE_VOLUME_SET 0x02 | |
391 | #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 | |
392 | #define IPR_RES_TYPE_GENERIC_ATA 0x04 | |
393 | #define IPR_RES_TYPE_ARRAY 0x05 | |
394 | #define IPR_RES_TYPE_IOAFP 0xff | |
395 | ||
1da177e4 | 396 | struct ipr_config_table_entry { |
b5145d25 BK |
397 | u8 proto; |
398 | #define IPR_PROTO_SATA 0x02 | |
399 | #define IPR_PROTO_SATA_ATAPI 0x03 | |
400 | #define IPR_PROTO_SAS_STP 0x06 | |
3e7ebdfa | 401 | #define IPR_PROTO_SAS_STP_ATAPI 0x07 |
1da177e4 LT |
402 | u8 array_id; |
403 | u8 flags; | |
3e7ebdfa | 404 | #define IPR_IS_IOA_RESOURCE 0x80 |
1da177e4 | 405 | u8 rsvd_subtype; |
3e7ebdfa WB |
406 | |
407 | #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) | |
408 | #define IPR_QUEUE_FROZEN_MODEL 0 | |
ee0a90fa BK |
409 | #define IPR_QUEUE_NACA_MODEL 1 |
410 | ||
1da177e4 LT |
411 | struct ipr_res_addr res_addr; |
412 | __be32 res_handle; | |
46d74563 | 413 | __be32 lun_wwn[2]; |
1da177e4 LT |
414 | struct ipr_std_inq_data std_inq_data; |
415 | }__attribute__ ((packed, aligned (4))); | |
416 | ||
3e7ebdfa WB |
417 | struct ipr_config_table_entry64 { |
418 | u8 res_type; | |
419 | u8 proto; | |
420 | u8 vset_num; | |
421 | u8 array_id; | |
422 | __be16 flags; | |
423 | __be16 res_flags; | |
424 | #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) | |
425 | __be32 res_handle; | |
426 | u8 dev_id_type; | |
427 | u8 reserved[3]; | |
428 | __be64 dev_id; | |
429 | __be64 lun; | |
430 | __be64 lun_wwn[2]; | |
b3b3b407 | 431 | #define IPR_MAX_RES_PATH_LENGTH 48 |
3e7ebdfa WB |
432 | __be64 res_path; |
433 | struct ipr_std_inq_data std_inq_data; | |
434 | u8 reserved2[4]; | |
7262026f | 435 | __be64 reserved3[2]; |
3e7ebdfa WB |
436 | u8 reserved4[8]; |
437 | }__attribute__ ((packed, aligned (8))); | |
438 | ||
1da177e4 LT |
439 | struct ipr_config_table_hdr { |
440 | u8 num_entries; | |
441 | u8 flags; | |
442 | #define IPR_UCODE_DOWNLOAD_REQ 0x10 | |
443 | __be16 reserved; | |
444 | }__attribute__((packed, aligned (4))); | |
445 | ||
3e7ebdfa WB |
446 | struct ipr_config_table_hdr64 { |
447 | __be16 num_entries; | |
448 | __be16 reserved; | |
449 | u8 flags; | |
450 | u8 reserved2[11]; | |
451 | }__attribute__((packed, aligned (4))); | |
452 | ||
1da177e4 LT |
453 | struct ipr_config_table { |
454 | struct ipr_config_table_hdr hdr; | |
3e7ebdfa | 455 | struct ipr_config_table_entry dev[0]; |
1da177e4 LT |
456 | }__attribute__((packed, aligned (4))); |
457 | ||
3e7ebdfa WB |
458 | struct ipr_config_table64 { |
459 | struct ipr_config_table_hdr64 hdr64; | |
460 | struct ipr_config_table_entry64 dev[0]; | |
461 | }__attribute__((packed, aligned (8))); | |
462 | ||
463 | struct ipr_config_table_entry_wrapper { | |
464 | union { | |
465 | struct ipr_config_table_entry *cfgte; | |
466 | struct ipr_config_table_entry64 *cfgte64; | |
467 | } u; | |
468 | }; | |
469 | ||
1da177e4 | 470 | struct ipr_hostrcb_cfg_ch_not { |
3e7ebdfa WB |
471 | union { |
472 | struct ipr_config_table_entry cfgte; | |
473 | struct ipr_config_table_entry64 cfgte64; | |
474 | } u; | |
1da177e4 LT |
475 | u8 reserved[936]; |
476 | }__attribute__((packed, aligned (4))); | |
477 | ||
478 | struct ipr_supported_device { | |
479 | __be16 data_length; | |
480 | u8 reserved; | |
481 | u8 num_records; | |
482 | struct ipr_std_inq_vpids vpids; | |
483 | u8 reserved2[16]; | |
484 | }__attribute__((packed, aligned (4))); | |
485 | ||
05a6538a | 486 | struct ipr_hrr_queue { |
487 | struct ipr_ioa_cfg *ioa_cfg; | |
488 | __be32 *host_rrq; | |
489 | dma_addr_t host_rrq_dma; | |
490 | #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc | |
491 | #define IPR_HRRQ_RESP_BIT_SET 0x00000002 | |
492 | #define IPR_HRRQ_TOGGLE_BIT 0x00000001 | |
493 | #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 | |
494 | #define IPR_ID_HRRQ_SELE_ENABLE 0x02 | |
495 | volatile __be32 *hrrq_start; | |
496 | volatile __be32 *hrrq_end; | |
497 | volatile __be32 *hrrq_curr; | |
498 | ||
499 | struct list_head hrrq_free_q; | |
500 | struct list_head hrrq_pending_q; | |
56d6aa33 | 501 | spinlock_t _lock; |
502 | spinlock_t *lock; | |
05a6538a | 503 | |
504 | volatile u32 toggle_bit; | |
505 | u32 size; | |
506 | u32 min_cmd_id; | |
507 | u32 max_cmd_id; | |
56d6aa33 | 508 | u8 allow_interrupts:1; |
509 | u8 ioa_is_dead:1; | |
510 | u8 allow_cmds:1; | |
bfae7820 | 511 | u8 removing_ioa:1; |
b53d124a | 512 | |
513 | struct blk_iopoll iopoll; | |
05a6538a | 514 | }; |
515 | ||
1da177e4 LT |
516 | /* Command packet structure */ |
517 | struct ipr_cmd_pkt { | |
05a6538a | 518 | u8 reserved; /* Reserved by IOA */ |
519 | u8 hrrq_id; | |
1da177e4 LT |
520 | u8 request_type; |
521 | #define IPR_RQTYPE_SCSICDB 0x00 | |
522 | #define IPR_RQTYPE_IOACMD 0x01 | |
523 | #define IPR_RQTYPE_HCAM 0x02 | |
b5145d25 | 524 | #define IPR_RQTYPE_ATA_PASSTHRU 0x04 |
f8ee25d7 | 525 | #define IPR_RQTYPE_PIPE 0x05 |
1da177e4 | 526 | |
a32c055f | 527 | u8 reserved2; |
1da177e4 LT |
528 | |
529 | u8 flags_hi; | |
530 | #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 | |
531 | #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 | |
532 | #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 | |
533 | #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 | |
534 | #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 | |
535 | ||
536 | u8 flags_lo; | |
537 | #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 | |
ab6c10b1 | 538 | #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 |
1da177e4 LT |
539 | #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 |
540 | #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 | |
541 | #define IPR_FLAGS_LO_ORDERED_TASK 0x04 | |
542 | #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 | |
543 | #define IPR_FLAGS_LO_ACA_TASK 0x08 | |
544 | ||
545 | u8 cdb[16]; | |
546 | __be16 timeout; | |
547 | }__attribute__ ((packed, aligned(4))); | |
548 | ||
a32c055f | 549 | struct ipr_ioarcb_ata_regs { /* 22 bytes */ |
b5145d25 BK |
550 | u8 flags; |
551 | #define IPR_ATA_FLAG_PACKET_CMD 0x80 | |
552 | #define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40 | |
553 | #define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20 | |
554 | u8 reserved[3]; | |
555 | ||
556 | __be16 data; | |
557 | u8 feature; | |
558 | u8 nsect; | |
559 | u8 lbal; | |
560 | u8 lbam; | |
561 | u8 lbah; | |
562 | u8 device; | |
563 | u8 command; | |
564 | u8 reserved2[3]; | |
565 | u8 hob_feature; | |
566 | u8 hob_nsect; | |
567 | u8 hob_lbal; | |
568 | u8 hob_lbam; | |
569 | u8 hob_lbah; | |
570 | u8 ctl; | |
1ac7c26d | 571 | }__attribute__ ((packed, aligned(2))); |
b5145d25 | 572 | |
51b1c7e1 BK |
573 | struct ipr_ioadl_desc { |
574 | __be32 flags_and_data_len; | |
575 | #define IPR_IOADL_FLAGS_MASK 0xff000000 | |
576 | #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) | |
577 | #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff | |
578 | #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) | |
579 | #define IPR_IOADL_FLAGS_READ 0x48000000 | |
580 | #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 | |
581 | #define IPR_IOADL_FLAGS_WRITE 0x68000000 | |
582 | #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 | |
583 | #define IPR_IOADL_FLAGS_LAST 0x01000000 | |
584 | ||
585 | __be32 address; | |
586 | }__attribute__((packed, aligned (8))); | |
587 | ||
a32c055f WB |
588 | struct ipr_ioadl64_desc { |
589 | __be32 flags; | |
590 | __be32 data_len; | |
591 | __be64 address; | |
592 | }__attribute__((packed, aligned (16))); | |
593 | ||
594 | struct ipr_ata64_ioadl { | |
595 | struct ipr_ioarcb_ata_regs regs; | |
596 | u16 reserved[5]; | |
597 | struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; | |
598 | }__attribute__((packed, aligned (16))); | |
599 | ||
b5145d25 BK |
600 | struct ipr_ioarcb_add_data { |
601 | union { | |
602 | struct ipr_ioarcb_ata_regs regs; | |
51b1c7e1 | 603 | struct ipr_ioadl_desc ioadl[5]; |
b5145d25 | 604 | __be32 add_cmd_parms[10]; |
a32c055f WB |
605 | } u; |
606 | }__attribute__ ((packed, aligned (4))); | |
607 | ||
608 | struct ipr_ioarcb_sis64_add_addr_ecb { | |
609 | __be64 ioasa_host_pci_addr; | |
610 | __be64 data_ioadl_addr; | |
611 | __be64 reserved; | |
612 | __be32 ext_control_buf[4]; | |
613 | }__attribute__((packed, aligned (8))); | |
b5145d25 | 614 | |
1da177e4 LT |
615 | /* IOA Request Control Block 128 bytes */ |
616 | struct ipr_ioarcb { | |
a32c055f WB |
617 | union { |
618 | __be32 ioarcb_host_pci_addr; | |
619 | __be64 ioarcb_host_pci_addr64; | |
620 | } a; | |
1da177e4 LT |
621 | __be32 res_handle; |
622 | __be32 host_response_handle; | |
623 | __be32 reserved1; | |
624 | __be32 reserved2; | |
625 | __be32 reserved3; | |
626 | ||
a32c055f | 627 | __be32 data_transfer_length; |
1da177e4 LT |
628 | __be32 read_data_transfer_length; |
629 | __be32 write_ioadl_addr; | |
a32c055f | 630 | __be32 ioadl_len; |
1da177e4 LT |
631 | __be32 read_ioadl_addr; |
632 | __be32 read_ioadl_len; | |
633 | ||
634 | __be32 ioasa_host_pci_addr; | |
635 | __be16 ioasa_len; | |
636 | __be16 reserved4; | |
637 | ||
638 | struct ipr_cmd_pkt cmd_pkt; | |
639 | ||
a32c055f WB |
640 | __be16 add_cmd_parms_offset; |
641 | __be16 add_cmd_parms_len; | |
642 | ||
643 | union { | |
644 | struct ipr_ioarcb_add_data add_data; | |
645 | struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; | |
646 | } u; | |
647 | ||
1da177e4 LT |
648 | }__attribute__((packed, aligned (4))); |
649 | ||
1da177e4 LT |
650 | struct ipr_ioasa_vset { |
651 | __be32 failing_lba_hi; | |
652 | __be32 failing_lba_lo; | |
c8f74892 | 653 | __be32 reserved; |
1da177e4 LT |
654 | }__attribute__((packed, aligned (4))); |
655 | ||
656 | struct ipr_ioasa_af_dasd { | |
657 | __be32 failing_lba; | |
c8f74892 | 658 | __be32 reserved[2]; |
1da177e4 LT |
659 | }__attribute__((packed, aligned (4))); |
660 | ||
661 | struct ipr_ioasa_gpdd { | |
662 | u8 end_state; | |
663 | u8 bus_phase; | |
664 | __be16 reserved; | |
c8f74892 | 665 | __be32 ioa_data[2]; |
1da177e4 LT |
666 | }__attribute__((packed, aligned (4))); |
667 | ||
b5145d25 BK |
668 | struct ipr_ioasa_gata { |
669 | u8 error; | |
670 | u8 nsect; /* Interrupt reason */ | |
671 | u8 lbal; | |
672 | u8 lbam; | |
673 | u8 lbah; | |
674 | u8 device; | |
675 | u8 status; | |
676 | u8 alt_status; /* ATA CTL */ | |
677 | u8 hob_nsect; | |
678 | u8 hob_lbal; | |
679 | u8 hob_lbam; | |
680 | u8 hob_lbah; | |
681 | }__attribute__((packed, aligned (4))); | |
682 | ||
c8f74892 BK |
683 | struct ipr_auto_sense { |
684 | __be16 auto_sense_len; | |
685 | __be16 ioa_data_len; | |
686 | __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; | |
687 | }; | |
1da177e4 | 688 | |
96d21f00 | 689 | struct ipr_ioasa_hdr { |
1da177e4 LT |
690 | __be32 ioasc; |
691 | #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) | |
692 | #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) | |
693 | #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) | |
694 | #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) | |
695 | ||
696 | __be16 ret_stat_len; /* Length of the returned IOASA */ | |
697 | ||
698 | __be16 avail_stat_len; /* Total Length of status available. */ | |
699 | ||
700 | __be32 residual_data_len; /* number of bytes in the host data */ | |
701 | /* buffers that were not used by the IOARCB command. */ | |
702 | ||
703 | __be32 ilid; | |
704 | #define IPR_NO_ILID 0 | |
705 | #define IPR_DRIVER_ILID 0xffffffff | |
706 | ||
707 | __be32 fd_ioasc; | |
708 | ||
709 | __be32 fd_phys_locator; | |
710 | ||
711 | __be32 fd_res_handle; | |
712 | ||
713 | __be32 ioasc_specific; /* status code specific field */ | |
c8f74892 BK |
714 | #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 |
715 | #define IPR_AUTOSENSE_VALID 0x40000000 | |
b5145d25 | 716 | #define IPR_ATA_DEVICE_WAS_RESET 0x20000000 |
1da177e4 LT |
717 | #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff |
718 | #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) | |
719 | #define IPR_FIELD_POINTER_MASK 0x0000ffff | |
720 | ||
96d21f00 WB |
721 | }__attribute__((packed, aligned (4))); |
722 | ||
723 | struct ipr_ioasa { | |
724 | struct ipr_ioasa_hdr hdr; | |
725 | ||
726 | union { | |
727 | struct ipr_ioasa_vset vset; | |
728 | struct ipr_ioasa_af_dasd dasd; | |
729 | struct ipr_ioasa_gpdd gpdd; | |
730 | struct ipr_ioasa_gata gata; | |
731 | } u; | |
732 | ||
733 | struct ipr_auto_sense auto_sense; | |
734 | }__attribute__((packed, aligned (4))); | |
735 | ||
736 | struct ipr_ioasa64 { | |
737 | struct ipr_ioasa_hdr hdr; | |
738 | u8 fd_res_path[8]; | |
739 | ||
1da177e4 LT |
740 | union { |
741 | struct ipr_ioasa_vset vset; | |
742 | struct ipr_ioasa_af_dasd dasd; | |
743 | struct ipr_ioasa_gpdd gpdd; | |
b5145d25 | 744 | struct ipr_ioasa_gata gata; |
1da177e4 | 745 | } u; |
c8f74892 BK |
746 | |
747 | struct ipr_auto_sense auto_sense; | |
1da177e4 LT |
748 | }__attribute__((packed, aligned (4))); |
749 | ||
750 | struct ipr_mode_parm_hdr { | |
751 | u8 length; | |
752 | u8 medium_type; | |
753 | u8 device_spec_parms; | |
754 | u8 block_desc_len; | |
755 | }__attribute__((packed)); | |
756 | ||
757 | struct ipr_mode_pages { | |
758 | struct ipr_mode_parm_hdr hdr; | |
759 | u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; | |
760 | }__attribute__((packed)); | |
761 | ||
762 | struct ipr_mode_page_hdr { | |
763 | u8 ps_page_code; | |
764 | #define IPR_MODE_PAGE_PS 0x80 | |
765 | #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) | |
766 | u8 page_length; | |
767 | }__attribute__ ((packed)); | |
768 | ||
769 | struct ipr_dev_bus_entry { | |
770 | struct ipr_res_addr res_addr; | |
771 | u8 flags; | |
772 | #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 | |
773 | #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 | |
774 | #define IPR_SCSI_ATTR_QAS_MASK 0xC0 | |
775 | #define IPR_SCSI_ATTR_ENABLE_TM 0x20 | |
776 | #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 | |
777 | #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 | |
778 | #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 | |
779 | ||
780 | u8 scsi_id; | |
781 | u8 bus_width; | |
782 | u8 extended_reset_delay; | |
783 | #define IPR_EXTENDED_RESET_DELAY 7 | |
784 | ||
785 | __be32 max_xfer_rate; | |
786 | ||
787 | u8 spinup_delay; | |
788 | u8 reserved3; | |
789 | __be16 reserved4; | |
790 | }__attribute__((packed, aligned (4))); | |
791 | ||
792 | struct ipr_mode_page28 { | |
793 | struct ipr_mode_page_hdr hdr; | |
794 | u8 num_entries; | |
795 | u8 entry_length; | |
796 | struct ipr_dev_bus_entry bus[0]; | |
797 | }__attribute__((packed)); | |
798 | ||
ac09c349 BK |
799 | struct ipr_mode_page24 { |
800 | struct ipr_mode_page_hdr hdr; | |
801 | u8 flags; | |
802 | #define IPR_ENABLE_DUAL_IOA_AF 0x80 | |
803 | }__attribute__((packed)); | |
804 | ||
1da177e4 LT |
805 | struct ipr_ioa_vpd { |
806 | struct ipr_std_inq_data std_inq_data; | |
807 | u8 ascii_part_num[12]; | |
808 | u8 reserved[40]; | |
809 | u8 ascii_plant_code[4]; | |
810 | }__attribute__((packed)); | |
811 | ||
812 | struct ipr_inquiry_page3 { | |
813 | u8 peri_qual_dev_type; | |
814 | u8 page_code; | |
815 | u8 reserved1; | |
816 | u8 page_length; | |
817 | u8 ascii_len; | |
818 | u8 reserved2[3]; | |
819 | u8 load_id[4]; | |
820 | u8 major_release; | |
821 | u8 card_type; | |
822 | u8 minor_release[2]; | |
823 | u8 ptf_number[4]; | |
824 | u8 patch_number[4]; | |
825 | }__attribute__((packed)); | |
826 | ||
ac09c349 BK |
827 | struct ipr_inquiry_cap { |
828 | u8 peri_qual_dev_type; | |
829 | u8 page_code; | |
830 | u8 reserved1; | |
831 | u8 page_length; | |
832 | u8 ascii_len; | |
833 | u8 reserved2; | |
834 | u8 sis_version[2]; | |
835 | u8 cap; | |
836 | #define IPR_CAP_DUAL_IOA_RAID 0x80 | |
837 | u8 reserved3[15]; | |
838 | }__attribute__((packed)); | |
839 | ||
62275040 BK |
840 | #define IPR_INQUIRY_PAGE0_ENTRIES 20 |
841 | struct ipr_inquiry_page0 { | |
842 | u8 peri_qual_dev_type; | |
843 | u8 page_code; | |
844 | u8 reserved1; | |
845 | u8 len; | |
846 | u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; | |
847 | }__attribute__((packed)); | |
848 | ||
1da177e4 | 849 | struct ipr_hostrcb_device_data_entry { |
cfc32139 | 850 | struct ipr_vpd vpd; |
1da177e4 | 851 | struct ipr_res_addr dev_res_addr; |
cfc32139 BK |
852 | struct ipr_vpd new_vpd; |
853 | struct ipr_vpd ioa_last_with_dev_vpd; | |
854 | struct ipr_vpd cfc_last_with_dev_vpd; | |
1da177e4 LT |
855 | __be32 ioa_data[5]; |
856 | }__attribute__((packed, aligned (4))); | |
857 | ||
ee0f05b8 BK |
858 | struct ipr_hostrcb_device_data_entry_enhanced { |
859 | struct ipr_ext_vpd vpd; | |
860 | u8 ccin[4]; | |
861 | struct ipr_res_addr dev_res_addr; | |
862 | struct ipr_ext_vpd new_vpd; | |
863 | u8 new_ccin[4]; | |
864 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
865 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
866 | }__attribute__((packed, aligned (4))); | |
867 | ||
4565e370 WB |
868 | struct ipr_hostrcb64_device_data_entry_enhanced { |
869 | struct ipr_ext_vpd vpd; | |
870 | u8 ccin[4]; | |
871 | u8 res_path[8]; | |
872 | struct ipr_ext_vpd new_vpd; | |
873 | u8 new_ccin[4]; | |
874 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
875 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
876 | }__attribute__((packed, aligned (4))); | |
877 | ||
1da177e4 | 878 | struct ipr_hostrcb_array_data_entry { |
cfc32139 | 879 | struct ipr_vpd vpd; |
1da177e4 LT |
880 | struct ipr_res_addr expected_dev_res_addr; |
881 | struct ipr_res_addr dev_res_addr; | |
882 | }__attribute__((packed, aligned (4))); | |
883 | ||
4565e370 WB |
884 | struct ipr_hostrcb64_array_data_entry { |
885 | struct ipr_ext_vpd vpd; | |
886 | u8 ccin[4]; | |
887 | u8 expected_res_path[8]; | |
888 | u8 res_path[8]; | |
889 | }__attribute__((packed, aligned (4))); | |
890 | ||
ee0f05b8 BK |
891 | struct ipr_hostrcb_array_data_entry_enhanced { |
892 | struct ipr_ext_vpd vpd; | |
893 | u8 ccin[4]; | |
894 | struct ipr_res_addr expected_dev_res_addr; | |
895 | struct ipr_res_addr dev_res_addr; | |
896 | }__attribute__((packed, aligned (4))); | |
897 | ||
1da177e4 | 898 | struct ipr_hostrcb_type_ff_error { |
438b0331 | 899 | __be32 ioa_data[758]; |
1da177e4 LT |
900 | }__attribute__((packed, aligned (4))); |
901 | ||
902 | struct ipr_hostrcb_type_01_error { | |
903 | __be32 seek_counter; | |
904 | __be32 read_counter; | |
905 | u8 sense_data[32]; | |
906 | __be32 ioa_data[236]; | |
907 | }__attribute__((packed, aligned (4))); | |
908 | ||
169b9ec8 WX |
909 | struct ipr_hostrcb_type_21_error { |
910 | __be32 wwn[4]; | |
911 | u8 res_path[8]; | |
912 | u8 primary_problem_desc[32]; | |
913 | u8 second_problem_desc[32]; | |
914 | __be32 sense_data[8]; | |
915 | __be32 cdb[4]; | |
916 | __be32 residual_trans_length; | |
917 | __be32 length_of_error; | |
918 | __be32 ioa_data[236]; | |
919 | }__attribute__((packed, aligned (4))); | |
920 | ||
1da177e4 | 921 | struct ipr_hostrcb_type_02_error { |
cfc32139 BK |
922 | struct ipr_vpd ioa_vpd; |
923 | struct ipr_vpd cfc_vpd; | |
924 | struct ipr_vpd ioa_last_attached_to_cfc_vpd; | |
925 | struct ipr_vpd cfc_last_attached_to_ioa_vpd; | |
1da177e4 | 926 | __be32 ioa_data[3]; |
1da177e4 LT |
927 | }__attribute__((packed, aligned (4))); |
928 | ||
ee0f05b8 BK |
929 | struct ipr_hostrcb_type_12_error { |
930 | struct ipr_ext_vpd ioa_vpd; | |
931 | struct ipr_ext_vpd cfc_vpd; | |
932 | struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; | |
933 | struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; | |
934 | __be32 ioa_data[3]; | |
935 | }__attribute__((packed, aligned (4))); | |
936 | ||
1da177e4 | 937 | struct ipr_hostrcb_type_03_error { |
cfc32139 BK |
938 | struct ipr_vpd ioa_vpd; |
939 | struct ipr_vpd cfc_vpd; | |
1da177e4 LT |
940 | __be32 errors_detected; |
941 | __be32 errors_logged; | |
942 | u8 ioa_data[12]; | |
cfc32139 | 943 | struct ipr_hostrcb_device_data_entry dev[3]; |
1da177e4 LT |
944 | }__attribute__((packed, aligned (4))); |
945 | ||
ee0f05b8 BK |
946 | struct ipr_hostrcb_type_13_error { |
947 | struct ipr_ext_vpd ioa_vpd; | |
948 | struct ipr_ext_vpd cfc_vpd; | |
949 | __be32 errors_detected; | |
950 | __be32 errors_logged; | |
951 | struct ipr_hostrcb_device_data_entry_enhanced dev[3]; | |
952 | }__attribute__((packed, aligned (4))); | |
953 | ||
4565e370 WB |
954 | struct ipr_hostrcb_type_23_error { |
955 | struct ipr_ext_vpd ioa_vpd; | |
956 | struct ipr_ext_vpd cfc_vpd; | |
957 | __be32 errors_detected; | |
958 | __be32 errors_logged; | |
959 | struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; | |
960 | }__attribute__((packed, aligned (4))); | |
961 | ||
1da177e4 | 962 | struct ipr_hostrcb_type_04_error { |
cfc32139 BK |
963 | struct ipr_vpd ioa_vpd; |
964 | struct ipr_vpd cfc_vpd; | |
1da177e4 LT |
965 | u8 ioa_data[12]; |
966 | struct ipr_hostrcb_array_data_entry array_member[10]; | |
967 | __be32 exposed_mode_adn; | |
968 | __be32 array_id; | |
cfc32139 | 969 | struct ipr_vpd incomp_dev_vpd; |
1da177e4 LT |
970 | __be32 ioa_data2; |
971 | struct ipr_hostrcb_array_data_entry array_member2[8]; | |
972 | struct ipr_res_addr last_func_vset_res_addr; | |
973 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
974 | u8 protection_level[8]; | |
1da177e4 LT |
975 | }__attribute__((packed, aligned (4))); |
976 | ||
ee0f05b8 BK |
977 | struct ipr_hostrcb_type_14_error { |
978 | struct ipr_ext_vpd ioa_vpd; | |
979 | struct ipr_ext_vpd cfc_vpd; | |
980 | __be32 exposed_mode_adn; | |
981 | __be32 array_id; | |
982 | struct ipr_res_addr last_func_vset_res_addr; | |
983 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
984 | u8 protection_level[8]; | |
985 | __be32 num_entries; | |
986 | struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; | |
987 | }__attribute__((packed, aligned (4))); | |
988 | ||
4565e370 WB |
989 | struct ipr_hostrcb_type_24_error { |
990 | struct ipr_ext_vpd ioa_vpd; | |
991 | struct ipr_ext_vpd cfc_vpd; | |
992 | u8 reserved[2]; | |
993 | u8 exposed_mode_adn; | |
994 | #define IPR_INVALID_ARRAY_DEV_NUM 0xff | |
995 | u8 array_id; | |
996 | u8 last_res_path[8]; | |
997 | u8 protection_level[8]; | |
7262026f | 998 | struct ipr_ext_vpd64 array_vpd; |
4565e370 WB |
999 | u8 description[16]; |
1000 | u8 reserved2[3]; | |
1001 | u8 num_entries; | |
1002 | struct ipr_hostrcb64_array_data_entry array_member[32]; | |
1003 | }__attribute__((packed, aligned (4))); | |
1004 | ||
b0df54bb BK |
1005 | struct ipr_hostrcb_type_07_error { |
1006 | u8 failure_reason[64]; | |
1007 | struct ipr_vpd vpd; | |
1008 | u32 data[222]; | |
1009 | }__attribute__((packed, aligned (4))); | |
1010 | ||
ee0f05b8 BK |
1011 | struct ipr_hostrcb_type_17_error { |
1012 | u8 failure_reason[64]; | |
1013 | struct ipr_ext_vpd vpd; | |
1014 | u32 data[476]; | |
1015 | }__attribute__((packed, aligned (4))); | |
1016 | ||
49dc6a18 BK |
1017 | struct ipr_hostrcb_config_element { |
1018 | u8 type_status; | |
1019 | #define IPR_PATH_CFG_TYPE_MASK 0xF0 | |
1020 | #define IPR_PATH_CFG_NOT_EXIST 0x00 | |
1021 | #define IPR_PATH_CFG_IOA_PORT 0x10 | |
1022 | #define IPR_PATH_CFG_EXP_PORT 0x20 | |
1023 | #define IPR_PATH_CFG_DEVICE_PORT 0x30 | |
1024 | #define IPR_PATH_CFG_DEVICE_LUN 0x40 | |
1025 | ||
1026 | #define IPR_PATH_CFG_STATUS_MASK 0x0F | |
1027 | #define IPR_PATH_CFG_NO_PROB 0x00 | |
1028 | #define IPR_PATH_CFG_DEGRADED 0x01 | |
1029 | #define IPR_PATH_CFG_FAILED 0x02 | |
1030 | #define IPR_PATH_CFG_SUSPECT 0x03 | |
1031 | #define IPR_PATH_NOT_DETECTED 0x04 | |
1032 | #define IPR_PATH_INCORRECT_CONN 0x05 | |
1033 | ||
1034 | u8 cascaded_expander; | |
1035 | u8 phy; | |
1036 | u8 link_rate; | |
1037 | #define IPR_PHY_LINK_RATE_MASK 0x0F | |
1038 | ||
1039 | __be32 wwid[2]; | |
1040 | }__attribute__((packed, aligned (4))); | |
1041 | ||
4565e370 WB |
1042 | struct ipr_hostrcb64_config_element { |
1043 | __be16 length; | |
1044 | u8 descriptor_id; | |
1045 | #define IPR_DESCRIPTOR_MASK 0xC0 | |
1046 | #define IPR_DESCRIPTOR_SIS64 0x00 | |
1047 | ||
1048 | u8 reserved; | |
1049 | u8 type_status; | |
1050 | ||
1051 | u8 reserved2[2]; | |
1052 | u8 link_rate; | |
1053 | ||
1054 | u8 res_path[8]; | |
1055 | __be32 wwid[2]; | |
1056 | }__attribute__((packed, aligned (8))); | |
1057 | ||
49dc6a18 BK |
1058 | struct ipr_hostrcb_fabric_desc { |
1059 | __be16 length; | |
1060 | u8 ioa_port; | |
1061 | u8 cascaded_expander; | |
1062 | u8 phy; | |
1063 | u8 path_state; | |
1064 | #define IPR_PATH_ACTIVE_MASK 0xC0 | |
1065 | #define IPR_PATH_NO_INFO 0x00 | |
1066 | #define IPR_PATH_ACTIVE 0x40 | |
1067 | #define IPR_PATH_NOT_ACTIVE 0x80 | |
1068 | ||
1069 | #define IPR_PATH_STATE_MASK 0x0F | |
1070 | #define IPR_PATH_STATE_NO_INFO 0x00 | |
1071 | #define IPR_PATH_HEALTHY 0x01 | |
1072 | #define IPR_PATH_DEGRADED 0x02 | |
1073 | #define IPR_PATH_FAILED 0x03 | |
1074 | ||
1075 | __be16 num_entries; | |
1076 | struct ipr_hostrcb_config_element elem[1]; | |
1077 | }__attribute__((packed, aligned (4))); | |
1078 | ||
4565e370 WB |
1079 | struct ipr_hostrcb64_fabric_desc { |
1080 | __be16 length; | |
1081 | u8 descriptor_id; | |
1082 | ||
8701f185 | 1083 | u8 reserved[2]; |
4565e370 WB |
1084 | u8 path_state; |
1085 | ||
1086 | u8 reserved2[2]; | |
1087 | u8 res_path[8]; | |
1088 | u8 reserved3[6]; | |
1089 | __be16 num_entries; | |
1090 | struct ipr_hostrcb64_config_element elem[1]; | |
1091 | }__attribute__((packed, aligned (8))); | |
1092 | ||
56d6aa33 | 1093 | #define for_each_hrrq(hrrq, ioa_cfg) \ |
1094 | for (hrrq = (ioa_cfg)->hrrq; \ | |
1095 | hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++) | |
1096 | ||
49dc6a18 BK |
1097 | #define for_each_fabric_cfg(fabric, cfg) \ |
1098 | for (cfg = (fabric)->elem; \ | |
1099 | cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ | |
1100 | cfg++) | |
1101 | ||
1102 | struct ipr_hostrcb_type_20_error { | |
1103 | u8 failure_reason[64]; | |
1104 | u8 reserved[3]; | |
1105 | u8 num_entries; | |
1106 | struct ipr_hostrcb_fabric_desc desc[1]; | |
1107 | }__attribute__((packed, aligned (4))); | |
1108 | ||
4565e370 WB |
1109 | struct ipr_hostrcb_type_30_error { |
1110 | u8 failure_reason[64]; | |
1111 | u8 reserved[3]; | |
1112 | u8 num_entries; | |
1113 | struct ipr_hostrcb64_fabric_desc desc[1]; | |
1114 | }__attribute__((packed, aligned (4))); | |
1115 | ||
1da177e4 | 1116 | struct ipr_hostrcb_error { |
4565e370 WB |
1117 | __be32 fd_ioasc; |
1118 | struct ipr_res_addr fd_res_addr; | |
1119 | __be32 fd_res_handle; | |
1da177e4 LT |
1120 | __be32 prc; |
1121 | union { | |
1122 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1123 | struct ipr_hostrcb_type_01_error type_01_error; | |
1124 | struct ipr_hostrcb_type_02_error type_02_error; | |
1125 | struct ipr_hostrcb_type_03_error type_03_error; | |
1126 | struct ipr_hostrcb_type_04_error type_04_error; | |
b0df54bb | 1127 | struct ipr_hostrcb_type_07_error type_07_error; |
ee0f05b8 BK |
1128 | struct ipr_hostrcb_type_12_error type_12_error; |
1129 | struct ipr_hostrcb_type_13_error type_13_error; | |
1130 | struct ipr_hostrcb_type_14_error type_14_error; | |
1131 | struct ipr_hostrcb_type_17_error type_17_error; | |
49dc6a18 | 1132 | struct ipr_hostrcb_type_20_error type_20_error; |
1da177e4 LT |
1133 | } u; |
1134 | }__attribute__((packed, aligned (4))); | |
1135 | ||
4565e370 WB |
1136 | struct ipr_hostrcb64_error { |
1137 | __be32 fd_ioasc; | |
1138 | __be32 ioa_fw_level; | |
1139 | __be32 fd_res_handle; | |
1140 | __be32 prc; | |
1141 | __be64 fd_dev_id; | |
1142 | __be64 fd_lun; | |
1143 | u8 fd_res_path[8]; | |
1144 | __be64 time_stamp; | |
8701f185 | 1145 | u8 reserved[16]; |
4565e370 WB |
1146 | union { |
1147 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1148 | struct ipr_hostrcb_type_12_error type_12_error; | |
1149 | struct ipr_hostrcb_type_17_error type_17_error; | |
169b9ec8 | 1150 | struct ipr_hostrcb_type_21_error type_21_error; |
4565e370 WB |
1151 | struct ipr_hostrcb_type_23_error type_23_error; |
1152 | struct ipr_hostrcb_type_24_error type_24_error; | |
1153 | struct ipr_hostrcb_type_30_error type_30_error; | |
1154 | } u; | |
1155 | }__attribute__((packed, aligned (8))); | |
1156 | ||
1da177e4 LT |
1157 | struct ipr_hostrcb_raw { |
1158 | __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; | |
1159 | }__attribute__((packed, aligned (4))); | |
1160 | ||
1161 | struct ipr_hcam { | |
1162 | u8 op_code; | |
1163 | #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 | |
1164 | #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 | |
1165 | ||
1166 | u8 notify_type; | |
1167 | #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 | |
1168 | #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 | |
1169 | #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 | |
1170 | #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 | |
1171 | #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 | |
1172 | ||
1173 | u8 notifications_lost; | |
1174 | #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 | |
1175 | #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 | |
1176 | ||
1177 | u8 flags; | |
1178 | #define IPR_HOSTRCB_INTERNAL_OPER 0x80 | |
1179 | #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 | |
1180 | ||
1181 | u8 overlay_id; | |
1182 | #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 | |
1183 | #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 | |
1184 | #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 | |
1185 | #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 | |
1186 | #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 | |
b0df54bb | 1187 | #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 |
ee0f05b8 BK |
1188 | #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 |
1189 | #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 | |
1190 | #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 | |
1191 | #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 | |
1192 | #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 | |
49dc6a18 | 1193 | #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 |
169b9ec8 | 1194 | #define IPR_HOST_RCB_OVERLAY_ID_21 0x21 |
4565e370 WB |
1195 | #define IPR_HOST_RCB_OVERLAY_ID_23 0x23 |
1196 | #define IPR_HOST_RCB_OVERLAY_ID_24 0x24 | |
1197 | #define IPR_HOST_RCB_OVERLAY_ID_26 0x26 | |
1198 | #define IPR_HOST_RCB_OVERLAY_ID_30 0x30 | |
1199 | #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF | |
1da177e4 LT |
1200 | |
1201 | u8 reserved1[3]; | |
1202 | __be32 ilid; | |
1203 | __be32 time_since_last_ioa_reset; | |
1204 | __be32 reserved2; | |
1205 | __be32 length; | |
1206 | ||
1207 | union { | |
1208 | struct ipr_hostrcb_error error; | |
4565e370 | 1209 | struct ipr_hostrcb64_error error64; |
1da177e4 LT |
1210 | struct ipr_hostrcb_cfg_ch_not ccn; |
1211 | struct ipr_hostrcb_raw raw; | |
1212 | } u; | |
1213 | }__attribute__((packed, aligned (4))); | |
1214 | ||
1215 | struct ipr_hostrcb { | |
1216 | struct ipr_hcam hcam; | |
1217 | dma_addr_t hostrcb_dma; | |
1218 | struct list_head queue; | |
49dc6a18 | 1219 | struct ipr_ioa_cfg *ioa_cfg; |
4565e370 | 1220 | char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; |
1da177e4 LT |
1221 | }; |
1222 | ||
1223 | /* IPR smart dump table structures */ | |
1224 | struct ipr_sdt_entry { | |
dcbad00e WB |
1225 | __be32 start_token; |
1226 | __be32 end_token; | |
1227 | u8 reserved[4]; | |
1da177e4 LT |
1228 | |
1229 | u8 flags; | |
1230 | #define IPR_SDT_ENDIAN 0x80 | |
1231 | #define IPR_SDT_VALID_ENTRY 0x20 | |
1232 | ||
1233 | u8 resv; | |
1234 | __be16 priority; | |
1235 | }__attribute__((packed, aligned (4))); | |
1236 | ||
1237 | struct ipr_sdt_header { | |
1238 | __be32 state; | |
1239 | __be32 num_entries; | |
1240 | __be32 num_entries_used; | |
1241 | __be32 dump_size; | |
1242 | }__attribute__((packed, aligned (4))); | |
1243 | ||
1244 | struct ipr_sdt { | |
1245 | struct ipr_sdt_header hdr; | |
4d4dd706 | 1246 | struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES]; |
1da177e4 LT |
1247 | }__attribute__((packed, aligned (4))); |
1248 | ||
1249 | struct ipr_uc_sdt { | |
1250 | struct ipr_sdt_header hdr; | |
1251 | struct ipr_sdt_entry entry[1]; | |
1252 | }__attribute__((packed, aligned (4))); | |
1253 | ||
1254 | /* | |
1255 | * Driver types | |
1256 | */ | |
1257 | struct ipr_bus_attributes { | |
1258 | u8 bus; | |
1259 | u8 qas_enabled; | |
1260 | u8 bus_width; | |
1261 | u8 reserved; | |
1262 | u32 max_xfer_rate; | |
1263 | }; | |
1264 | ||
35a39691 BK |
1265 | struct ipr_sata_port { |
1266 | struct ipr_ioa_cfg *ioa_cfg; | |
1267 | struct ata_port *ap; | |
1268 | struct ipr_resource_entry *res; | |
1269 | struct ipr_ioasa_gata ioasa; | |
1270 | }; | |
1271 | ||
1da177e4 | 1272 | struct ipr_resource_entry { |
1da177e4 LT |
1273 | u8 needs_sync_complete:1; |
1274 | u8 in_erp:1; | |
1275 | u8 add_to_ml:1; | |
1276 | u8 del_from_ml:1; | |
1277 | u8 resetting_device:1; | |
0b1f8d44 | 1278 | u8 reset_occurred:1; |
f8ee25d7 | 1279 | u8 raw_mode:1; |
1da177e4 | 1280 | |
3e7ebdfa WB |
1281 | u32 bus; /* AKA channel */ |
1282 | u32 target; /* AKA id */ | |
1283 | u32 lun; | |
1284 | #define IPR_ARRAY_VIRTUAL_BUS 0x1 | |
1285 | #define IPR_VSET_VIRTUAL_BUS 0x2 | |
1286 | #define IPR_IOAFP_VIRTUAL_BUS 0x3 | |
1287 | ||
1288 | #define IPR_GET_RES_PHYS_LOC(res) \ | |
1289 | (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) | |
1290 | ||
1291 | u8 ata_class; | |
1292 | ||
1293 | u8 flags; | |
1294 | __be16 res_flags; | |
1295 | ||
7be96900 | 1296 | u8 type; |
3e7ebdfa WB |
1297 | |
1298 | u8 qmodel; | |
1299 | struct ipr_std_inq_data std_inq_data; | |
1300 | ||
1301 | __be32 res_handle; | |
1302 | __be64 dev_id; | |
46d74563 | 1303 | __be64 lun_wwn; |
3e7ebdfa WB |
1304 | struct scsi_lun dev_lun; |
1305 | u8 res_path[8]; | |
1306 | ||
1307 | struct ipr_ioa_cfg *ioa_cfg; | |
1da177e4 | 1308 | struct scsi_device *sdev; |
35a39691 | 1309 | struct ipr_sata_port *sata_port; |
1da177e4 | 1310 | struct list_head queue; |
3e7ebdfa | 1311 | }; /* struct ipr_resource_entry */ |
1da177e4 LT |
1312 | |
1313 | struct ipr_resource_hdr { | |
1314 | u16 num_entries; | |
1315 | u16 reserved; | |
1316 | }; | |
1317 | ||
1da177e4 LT |
1318 | struct ipr_misc_cbs { |
1319 | struct ipr_ioa_vpd ioa_vpd; | |
62275040 | 1320 | struct ipr_inquiry_page0 page0_data; |
1da177e4 | 1321 | struct ipr_inquiry_page3 page3_data; |
ac09c349 | 1322 | struct ipr_inquiry_cap cap; |
1da177e4 LT |
1323 | struct ipr_mode_pages mode_pages; |
1324 | struct ipr_supported_device supp_dev; | |
1325 | }; | |
1326 | ||
1327 | struct ipr_interrupt_offsets { | |
1328 | unsigned long set_interrupt_mask_reg; | |
1329 | unsigned long clr_interrupt_mask_reg; | |
214777ba | 1330 | unsigned long clr_interrupt_mask_reg32; |
1da177e4 | 1331 | unsigned long sense_interrupt_mask_reg; |
214777ba | 1332 | unsigned long sense_interrupt_mask_reg32; |
1da177e4 | 1333 | unsigned long clr_interrupt_reg; |
214777ba | 1334 | unsigned long clr_interrupt_reg32; |
1da177e4 LT |
1335 | |
1336 | unsigned long sense_interrupt_reg; | |
214777ba | 1337 | unsigned long sense_interrupt_reg32; |
1da177e4 LT |
1338 | unsigned long ioarrin_reg; |
1339 | unsigned long sense_uproc_interrupt_reg; | |
214777ba | 1340 | unsigned long sense_uproc_interrupt_reg32; |
1da177e4 | 1341 | unsigned long set_uproc_interrupt_reg; |
214777ba | 1342 | unsigned long set_uproc_interrupt_reg32; |
1da177e4 | 1343 | unsigned long clr_uproc_interrupt_reg; |
214777ba WB |
1344 | unsigned long clr_uproc_interrupt_reg32; |
1345 | ||
1346 | unsigned long init_feedback_reg; | |
dcbad00e WB |
1347 | |
1348 | unsigned long dump_addr_reg; | |
1349 | unsigned long dump_data_reg; | |
8701f185 | 1350 | |
4289a086 | 1351 | #define IPR_ENDIAN_SWAP_KEY 0x00080800 |
8701f185 | 1352 | unsigned long endian_swap_reg; |
1da177e4 LT |
1353 | }; |
1354 | ||
1355 | struct ipr_interrupts { | |
1356 | void __iomem *set_interrupt_mask_reg; | |
1357 | void __iomem *clr_interrupt_mask_reg; | |
214777ba | 1358 | void __iomem *clr_interrupt_mask_reg32; |
1da177e4 | 1359 | void __iomem *sense_interrupt_mask_reg; |
214777ba | 1360 | void __iomem *sense_interrupt_mask_reg32; |
1da177e4 | 1361 | void __iomem *clr_interrupt_reg; |
214777ba | 1362 | void __iomem *clr_interrupt_reg32; |
1da177e4 LT |
1363 | |
1364 | void __iomem *sense_interrupt_reg; | |
214777ba | 1365 | void __iomem *sense_interrupt_reg32; |
1da177e4 LT |
1366 | void __iomem *ioarrin_reg; |
1367 | void __iomem *sense_uproc_interrupt_reg; | |
214777ba | 1368 | void __iomem *sense_uproc_interrupt_reg32; |
1da177e4 | 1369 | void __iomem *set_uproc_interrupt_reg; |
214777ba | 1370 | void __iomem *set_uproc_interrupt_reg32; |
1da177e4 | 1371 | void __iomem *clr_uproc_interrupt_reg; |
214777ba WB |
1372 | void __iomem *clr_uproc_interrupt_reg32; |
1373 | ||
1374 | void __iomem *init_feedback_reg; | |
dcbad00e WB |
1375 | |
1376 | void __iomem *dump_addr_reg; | |
1377 | void __iomem *dump_data_reg; | |
8701f185 WB |
1378 | |
1379 | void __iomem *endian_swap_reg; | |
1da177e4 LT |
1380 | }; |
1381 | ||
1382 | struct ipr_chip_cfg_t { | |
1383 | u32 mailbox; | |
89aad428 | 1384 | u16 max_cmds; |
1da177e4 | 1385 | u8 cache_line_size; |
7dd21308 | 1386 | u8 clear_isr; |
b53d124a | 1387 | u32 iopoll_weight; |
1da177e4 LT |
1388 | struct ipr_interrupt_offsets regs; |
1389 | }; | |
1390 | ||
1391 | struct ipr_chip_t { | |
1392 | u16 vendor; | |
1393 | u16 device; | |
1be7bd82 WB |
1394 | u16 intr_type; |
1395 | #define IPR_USE_LSI 0x00 | |
1396 | #define IPR_USE_MSI 0x01 | |
05a6538a | 1397 | #define IPR_USE_MSIX 0x02 |
a32c055f WB |
1398 | u16 sis_type; |
1399 | #define IPR_SIS32 0x00 | |
1400 | #define IPR_SIS64 0x01 | |
cb237ef7 WB |
1401 | u16 bist_method; |
1402 | #define IPR_PCI_CFG 0x00 | |
1403 | #define IPR_MMIO 0x01 | |
1da177e4 LT |
1404 | const struct ipr_chip_cfg_t *cfg; |
1405 | }; | |
1406 | ||
1407 | enum ipr_shutdown_type { | |
1408 | IPR_SHUTDOWN_NORMAL = 0x00, | |
1409 | IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, | |
1410 | IPR_SHUTDOWN_ABBREV = 0x80, | |
4fdd7c7a BK |
1411 | IPR_SHUTDOWN_NONE = 0x100, |
1412 | IPR_SHUTDOWN_QUIESCE = 0x101, | |
1da177e4 LT |
1413 | }; |
1414 | ||
1415 | struct ipr_trace_entry { | |
1416 | u32 time; | |
1417 | ||
1418 | u8 op_code; | |
35a39691 | 1419 | u8 ata_op_code; |
1da177e4 LT |
1420 | u8 type; |
1421 | #define IPR_TRACE_START 0x00 | |
1422 | #define IPR_TRACE_FINISH 0xff | |
35a39691 | 1423 | u8 cmd_index; |
1da177e4 LT |
1424 | |
1425 | __be32 res_handle; | |
1426 | union { | |
1427 | u32 ioasc; | |
1428 | u32 add_data; | |
1429 | u32 res_addr; | |
1430 | } u; | |
1431 | }; | |
1432 | ||
1433 | struct ipr_sglist { | |
1434 | u32 order; | |
1435 | u32 num_sg; | |
12baa420 | 1436 | u32 num_dma_sg; |
1da177e4 LT |
1437 | u32 buffer_len; |
1438 | struct scatterlist scatterlist[1]; | |
1439 | }; | |
1440 | ||
1441 | enum ipr_sdt_state { | |
1442 | INACTIVE, | |
1443 | WAIT_FOR_DUMP, | |
1444 | GET_DUMP, | |
41e9a696 | 1445 | READ_DUMP, |
1da177e4 LT |
1446 | ABORT_DUMP, |
1447 | DUMP_OBTAINED | |
1448 | }; | |
1449 | ||
1450 | /* Per-controller data */ | |
1451 | struct ipr_ioa_cfg { | |
1452 | char eye_catcher[8]; | |
1453 | #define IPR_EYECATCHER "iprcfg" | |
1454 | ||
1455 | struct list_head queue; | |
1456 | ||
1da177e4 LT |
1457 | u8 in_reset_reload:1; |
1458 | u8 in_ioa_bringdown:1; | |
1459 | u8 ioa_unit_checked:1; | |
1da177e4 | 1460 | u8 dump_taken:1; |
f688f96d | 1461 | u8 scan_done:1; |
ce155cce | 1462 | u8 needs_hard_reset:1; |
ac09c349 | 1463 | u8 dual_raid:1; |
463fc696 | 1464 | u8 needs_warm_reset:1; |
95fecd90 | 1465 | u8 msi_received:1; |
a32c055f | 1466 | u8 sis64:1; |
4c647e90 | 1467 | u8 dump_timeout:1; |
fb51ccbf | 1468 | u8 cfg_locked:1; |
7dd21308 | 1469 | u8 clear_isr:1; |
6270e593 | 1470 | u8 probe_done:1; |
463fc696 BK |
1471 | |
1472 | u8 revid; | |
1da177e4 | 1473 | |
3e7ebdfa WB |
1474 | /* |
1475 | * Bitmaps for SIS64 generated target values | |
1476 | */ | |
222ab594 | 1477 | unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; |
1478 | unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
1479 | unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
3e7ebdfa | 1480 | |
1da177e4 LT |
1481 | u16 type; /* CCIN of the card */ |
1482 | ||
1483 | u8 log_level; | |
1484 | #define IPR_MAX_LOG_LEVEL 4 | |
1485 | #define IPR_DEFAULT_LOG_LEVEL 2 | |
1486 | ||
1487 | #define IPR_NUM_TRACE_INDEX_BITS 8 | |
1488 | #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) | |
1489 | #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) | |
1490 | char trace_start[8]; | |
1491 | #define IPR_TRACE_START_LABEL "trace" | |
1492 | struct ipr_trace_entry *trace; | |
56d6aa33 | 1493 | atomic_t trace_index; |
1da177e4 | 1494 | |
1da177e4 LT |
1495 | char cfg_table_start[8]; |
1496 | #define IPR_CFG_TBL_START "cfg" | |
3e7ebdfa WB |
1497 | union { |
1498 | struct ipr_config_table *cfg_table; | |
1499 | struct ipr_config_table64 *cfg_table64; | |
1500 | } u; | |
1da177e4 | 1501 | dma_addr_t cfg_table_dma; |
3e7ebdfa WB |
1502 | u32 cfg_table_size; |
1503 | u32 max_devs_supported; | |
1da177e4 LT |
1504 | |
1505 | char resource_table_label[8]; | |
1506 | #define IPR_RES_TABLE_LABEL "res_tbl" | |
1507 | struct ipr_resource_entry *res_entries; | |
1508 | struct list_head free_res_q; | |
1509 | struct list_head used_res_q; | |
1510 | ||
1511 | char ipr_hcam_label[8]; | |
1512 | #define IPR_HCAM_LABEL "hcams" | |
1513 | struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS]; | |
1514 | dma_addr_t hostrcb_dma[IPR_NUM_HCAMS]; | |
1515 | struct list_head hostrcb_free_q; | |
1516 | struct list_head hostrcb_pending_q; | |
1517 | ||
05a6538a | 1518 | struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM]; |
1519 | u32 hrrq_num; | |
56d6aa33 | 1520 | atomic_t hrrq_index; |
1521 | u16 identify_hrrq_index; | |
1da177e4 LT |
1522 | |
1523 | struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; | |
1524 | ||
5469cb5b | 1525 | unsigned int transop_timeout; |
1da177e4 | 1526 | const struct ipr_chip_cfg_t *chip_cfg; |
1be7bd82 | 1527 | const struct ipr_chip_t *ipr_chip; |
1da177e4 LT |
1528 | |
1529 | void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ | |
1530 | unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ | |
1531 | void __iomem *ioa_mailbox; | |
1532 | struct ipr_interrupts regs; | |
1533 | ||
1534 | u16 saved_pcix_cmd_reg; | |
1535 | u16 reset_retries; | |
1536 | ||
1537 | u32 errors_logged; | |
3d1d0da6 | 1538 | u32 doorbell; |
1da177e4 LT |
1539 | |
1540 | struct Scsi_Host *host; | |
1541 | struct pci_dev *pdev; | |
1542 | struct ipr_sglist *ucode_sglist; | |
1da177e4 LT |
1543 | u8 saved_mode_page_len; |
1544 | ||
1545 | struct work_struct work_q; | |
2796ca5e | 1546 | struct workqueue_struct *reset_work_q; |
1da177e4 LT |
1547 | |
1548 | wait_queue_head_t reset_wait_q; | |
95fecd90 | 1549 | wait_queue_head_t msi_wait_q; |
6270e593 | 1550 | wait_queue_head_t eeh_wait_q; |
1da177e4 LT |
1551 | |
1552 | struct ipr_dump *dump; | |
1553 | enum ipr_sdt_state sdt_state; | |
1554 | ||
1555 | struct ipr_misc_cbs *vpd_cbs; | |
1556 | dma_addr_t vpd_cbs_dma; | |
1557 | ||
d73341bf | 1558 | struct dma_pool *ipr_cmd_pool; |
1da177e4 LT |
1559 | |
1560 | struct ipr_cmnd *reset_cmd; | |
463fc696 | 1561 | int (*reset) (struct ipr_cmnd *); |
1da177e4 | 1562 | |
35a39691 | 1563 | struct ata_host ata_host; |
1da177e4 | 1564 | char ipr_cmd_label[8]; |
0124ca9d | 1565 | #define IPR_CMD_LABEL "ipr_cmd" |
89aad428 BK |
1566 | u32 max_cmds; |
1567 | struct ipr_cmnd **ipr_cmnd_list; | |
1568 | dma_addr_t *ipr_cmnd_list_dma; | |
05a6538a | 1569 | |
1570 | u16 intr_flag; | |
1571 | unsigned int nvectors; | |
1572 | ||
1573 | struct { | |
1574 | unsigned short vec; | |
1575 | char desc[22]; | |
1576 | } vectors_info[IPR_MAX_MSIX_VECTORS]; | |
1577 | ||
b53d124a | 1578 | u32 iopoll_weight; |
1579 | ||
3e7ebdfa | 1580 | }; /* struct ipr_ioa_cfg */ |
1da177e4 LT |
1581 | |
1582 | struct ipr_cmnd { | |
1583 | struct ipr_ioarcb ioarcb; | |
a32c055f WB |
1584 | union { |
1585 | struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; | |
1586 | struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; | |
1587 | struct ipr_ata64_ioadl ata_ioadl; | |
1588 | } i; | |
96d21f00 WB |
1589 | union { |
1590 | struct ipr_ioasa ioasa; | |
1591 | struct ipr_ioasa64 ioasa64; | |
1592 | } s; | |
1da177e4 LT |
1593 | struct list_head queue; |
1594 | struct scsi_cmnd *scsi_cmd; | |
35a39691 | 1595 | struct ata_queued_cmd *qc; |
1da177e4 LT |
1596 | struct completion completion; |
1597 | struct timer_list timer; | |
2796ca5e | 1598 | struct work_struct work; |
172cd6e1 | 1599 | void (*fast_done) (struct ipr_cmnd *); |
1da177e4 LT |
1600 | void (*done) (struct ipr_cmnd *); |
1601 | int (*job_step) (struct ipr_cmnd *); | |
dfed823e | 1602 | int (*job_step_failed) (struct ipr_cmnd *); |
1da177e4 LT |
1603 | u16 cmd_index; |
1604 | u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; | |
1605 | dma_addr_t sense_buffer_dma; | |
1606 | unsigned short dma_use_sg; | |
a32c055f | 1607 | dma_addr_t dma_addr; |
1da177e4 LT |
1608 | struct ipr_cmnd *sibling; |
1609 | union { | |
1610 | enum ipr_shutdown_type shutdown_type; | |
1611 | struct ipr_hostrcb *hostrcb; | |
1612 | unsigned long time_left; | |
1613 | unsigned long scratch; | |
1614 | struct ipr_resource_entry *res; | |
1615 | struct scsi_device *sdev; | |
1616 | } u; | |
1617 | ||
6cdb0817 | 1618 | struct completion *eh_comp; |
05a6538a | 1619 | struct ipr_hrr_queue *hrrq; |
1da177e4 LT |
1620 | struct ipr_ioa_cfg *ioa_cfg; |
1621 | }; | |
1622 | ||
1623 | struct ipr_ses_table_entry { | |
1624 | char product_id[17]; | |
1625 | char compare_product_id_byte[17]; | |
1626 | u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ | |
1627 | }; | |
1628 | ||
1629 | struct ipr_dump_header { | |
1630 | u32 eye_catcher; | |
1631 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1632 | u32 len; | |
1633 | u32 num_entries; | |
1634 | u32 first_entry_offset; | |
1635 | u32 status; | |
1636 | #define IPR_DUMP_STATUS_SUCCESS 0 | |
1637 | #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 | |
1638 | #define IPR_DUMP_STATUS_FAILED 0xffffffff | |
1639 | u32 os; | |
1640 | #define IPR_DUMP_OS_LINUX 0x4C4E5558 | |
1641 | u32 driver_name; | |
1642 | #define IPR_DUMP_DRIVER_NAME 0x49505232 | |
1643 | }__attribute__((packed, aligned (4))); | |
1644 | ||
1645 | struct ipr_dump_entry_header { | |
1646 | u32 eye_catcher; | |
1647 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1648 | u32 len; | |
1649 | u32 num_elems; | |
1650 | u32 offset; | |
1651 | u32 data_type; | |
1652 | #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 | |
1653 | #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 | |
1654 | u32 id; | |
1655 | #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 | |
1656 | #define IPR_DUMP_LOCATION_ID 0x4C4F4341 | |
1657 | #define IPR_DUMP_TRACE_ID 0x54524143 | |
1658 | #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 | |
1659 | #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 | |
1660 | #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 | |
1661 | #define IPR_DUMP_PEND_OPS 0x414F5053 | |
1662 | u32 status; | |
1663 | }__attribute__((packed, aligned (4))); | |
1664 | ||
1665 | struct ipr_dump_location_entry { | |
1666 | struct ipr_dump_entry_header hdr; | |
71610f55 | 1667 | u8 location[20]; |
1da177e4 LT |
1668 | }__attribute__((packed)); |
1669 | ||
1670 | struct ipr_dump_trace_entry { | |
1671 | struct ipr_dump_entry_header hdr; | |
1672 | u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; | |
1673 | }__attribute__((packed, aligned (4))); | |
1674 | ||
1675 | struct ipr_dump_version_entry { | |
1676 | struct ipr_dump_entry_header hdr; | |
1677 | u8 version[sizeof(IPR_DRIVER_VERSION)]; | |
1678 | }; | |
1679 | ||
1680 | struct ipr_dump_ioa_type_entry { | |
1681 | struct ipr_dump_entry_header hdr; | |
1682 | u32 type; | |
1683 | u32 fw_version; | |
1684 | }; | |
1685 | ||
1686 | struct ipr_driver_dump { | |
1687 | struct ipr_dump_header hdr; | |
1688 | struct ipr_dump_version_entry version_entry; | |
1689 | struct ipr_dump_location_entry location_entry; | |
1690 | struct ipr_dump_ioa_type_entry ioa_type_entry; | |
1691 | struct ipr_dump_trace_entry trace_entry; | |
1692 | }__attribute__((packed)); | |
1693 | ||
1694 | struct ipr_ioa_dump { | |
1695 | struct ipr_dump_entry_header hdr; | |
1696 | struct ipr_sdt sdt; | |
4d4dd706 | 1697 | __be32 **ioa_data; |
1da177e4 LT |
1698 | u32 reserved; |
1699 | u32 next_page_index; | |
1700 | u32 page_offset; | |
1701 | u32 format; | |
1da177e4 LT |
1702 | }__attribute__((packed, aligned (4))); |
1703 | ||
1704 | struct ipr_dump { | |
1705 | struct kref kref; | |
1706 | struct ipr_ioa_cfg *ioa_cfg; | |
1707 | struct ipr_driver_dump driver_dump; | |
1708 | struct ipr_ioa_dump ioa_dump; | |
1709 | }; | |
1710 | ||
1711 | struct ipr_error_table_t { | |
1712 | u32 ioasc; | |
1713 | int log_ioasa; | |
1714 | int log_hcam; | |
1715 | char *error; | |
1716 | }; | |
1717 | ||
1718 | struct ipr_software_inq_lid_info { | |
1719 | __be32 load_id; | |
1720 | __be32 timestamp[3]; | |
1721 | }__attribute__((packed, aligned (4))); | |
1722 | ||
1723 | struct ipr_ucode_image_header { | |
1724 | __be32 header_length; | |
1725 | __be32 lid_table_offset; | |
1726 | u8 major_release; | |
1727 | u8 card_type; | |
1728 | u8 minor_release[2]; | |
1729 | u8 reserved[20]; | |
1730 | char eyecatcher[16]; | |
1731 | __be32 num_lids; | |
1732 | struct ipr_software_inq_lid_info lid[1]; | |
1733 | }__attribute__((packed, aligned (4))); | |
1734 | ||
1735 | /* | |
1736 | * Macros | |
1737 | */ | |
d3c74871 | 1738 | #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } |
1da177e4 LT |
1739 | |
1740 | #ifdef CONFIG_SCSI_IPR_TRACE | |
1741 | #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1742 | #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1743 | #else | |
1744 | #define ipr_create_trace_file(kobj, attr) 0 | |
1745 | #define ipr_remove_trace_file(kobj, attr) do { } while(0) | |
1746 | #endif | |
1747 | ||
1748 | #ifdef CONFIG_SCSI_IPR_DUMP | |
1749 | #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1750 | #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1751 | #else | |
1752 | #define ipr_create_dump_file(kobj, attr) 0 | |
1753 | #define ipr_remove_dump_file(kobj, attr) do { } while(0) | |
1754 | #endif | |
1755 | ||
1756 | /* | |
1757 | * Error logging macros | |
1758 | */ | |
1759 | #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) | |
1760 | #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) | |
1da177e4 LT |
1761 | #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) |
1762 | ||
3e7ebdfa WB |
1763 | #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ |
1764 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1765 | bus, target, lun, ##__VA_ARGS__) | |
1766 | ||
1767 | #define ipr_res_err(ioa_cfg, res, fmt, ...) \ | |
1768 | ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) | |
1769 | ||
fb3ed3cb BK |
1770 | #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ |
1771 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1772 | (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) | |
1da177e4 | 1773 | |
fb3ed3cb BK |
1774 | #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ |
1775 | ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) | |
1da177e4 | 1776 | |
fa15b1f6 BK |
1777 | #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ |
1778 | { \ | |
1779 | if ((res).bus >= IPR_MAX_NUM_BUSES) { \ | |
1780 | ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ | |
1781 | } else { \ | |
1782 | ipr_err(fmt": %d:%d:%d:%d\n", \ | |
1783 | ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ | |
1784 | (res).bus, (res).target, (res).lun); \ | |
1785 | } \ | |
1786 | } | |
1787 | ||
49dc6a18 | 1788 | #define ipr_hcam_err(hostrcb, fmt, ...) \ |
4565e370 WB |
1789 | { \ |
1790 | if (ipr_is_device(hostrcb)) { \ | |
1791 | if ((hostrcb)->ioa_cfg->sis64) { \ | |
1792 | printk(KERN_ERR IPR_NAME ": %s: " fmt, \ | |
b3b3b407 BK |
1793 | ipr_format_res_path(hostrcb->ioa_cfg, \ |
1794 | hostrcb->hcam.u.error64.fd_res_path, \ | |
5adcbeb3 WB |
1795 | hostrcb->rp_buffer, \ |
1796 | sizeof(hostrcb->rp_buffer)), \ | |
4565e370 WB |
1797 | __VA_ARGS__); \ |
1798 | } else { \ | |
1799 | ipr_ra_err((hostrcb)->ioa_cfg, \ | |
1800 | (hostrcb)->hcam.u.error.fd_res_addr, \ | |
1801 | fmt, __VA_ARGS__); \ | |
1802 | } \ | |
1803 | } else { \ | |
1804 | dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ | |
1805 | } \ | |
49dc6a18 BK |
1806 | } |
1807 | ||
1da177e4 | 1808 | #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ |
cadbd4a5 | 1809 | __FILE__, __func__, __LINE__) |
1da177e4 | 1810 | |
cadbd4a5 HH |
1811 | #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) |
1812 | #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) | |
1da177e4 LT |
1813 | |
1814 | #define ipr_err_separator \ | |
1815 | ipr_err("----------------------------------------------------------\n") | |
1816 | ||
1817 | ||
1818 | /* | |
1819 | * Inlines | |
1820 | */ | |
1821 | ||
1822 | /** | |
1823 | * ipr_is_ioa_resource - Determine if a resource is the IOA | |
1824 | * @res: resource entry struct | |
1825 | * | |
1826 | * Return value: | |
1827 | * 1 if IOA / 0 if not IOA | |
1828 | **/ | |
1829 | static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) | |
1830 | { | |
3e7ebdfa | 1831 | return res->type == IPR_RES_TYPE_IOAFP; |
1da177e4 LT |
1832 | } |
1833 | ||
1834 | /** | |
1835 | * ipr_is_af_dasd_device - Determine if a resource is an AF DASD | |
1836 | * @res: resource entry struct | |
1837 | * | |
1838 | * Return value: | |
1839 | * 1 if AF DASD / 0 if not AF DASD | |
1840 | **/ | |
1841 | static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) | |
1842 | { | |
3e7ebdfa WB |
1843 | return res->type == IPR_RES_TYPE_AF_DASD || |
1844 | res->type == IPR_RES_TYPE_REMOTE_AF_DASD; | |
1da177e4 LT |
1845 | } |
1846 | ||
1847 | /** | |
1848 | * ipr_is_vset_device - Determine if a resource is a VSET | |
1849 | * @res: resource entry struct | |
1850 | * | |
1851 | * Return value: | |
1852 | * 1 if VSET / 0 if not VSET | |
1853 | **/ | |
1854 | static inline int ipr_is_vset_device(struct ipr_resource_entry *res) | |
1855 | { | |
3e7ebdfa | 1856 | return res->type == IPR_RES_TYPE_VOLUME_SET; |
1da177e4 LT |
1857 | } |
1858 | ||
1859 | /** | |
1860 | * ipr_is_gscsi - Determine if a resource is a generic scsi resource | |
1861 | * @res: resource entry struct | |
1862 | * | |
1863 | * Return value: | |
1864 | * 1 if GSCSI / 0 if not GSCSI | |
1865 | **/ | |
1866 | static inline int ipr_is_gscsi(struct ipr_resource_entry *res) | |
1867 | { | |
3e7ebdfa | 1868 | return res->type == IPR_RES_TYPE_GENERIC_SCSI; |
1da177e4 LT |
1869 | } |
1870 | ||
e4fbf44e BK |
1871 | /** |
1872 | * ipr_is_scsi_disk - Determine if a resource is a SCSI disk | |
1873 | * @res: resource entry struct | |
1874 | * | |
1875 | * Return value: | |
1876 | * 1 if SCSI disk / 0 if not SCSI disk | |
1877 | **/ | |
1878 | static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) | |
1879 | { | |
1880 | if (ipr_is_af_dasd_device(res) || | |
3e7ebdfa | 1881 | (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) |
e4fbf44e BK |
1882 | return 1; |
1883 | else | |
1884 | return 0; | |
1885 | } | |
1886 | ||
b5145d25 BK |
1887 | /** |
1888 | * ipr_is_gata - Determine if a resource is a generic ATA resource | |
1889 | * @res: resource entry struct | |
1890 | * | |
1891 | * Return value: | |
1892 | * 1 if GATA / 0 if not GATA | |
1893 | **/ | |
1894 | static inline int ipr_is_gata(struct ipr_resource_entry *res) | |
1895 | { | |
3e7ebdfa | 1896 | return res->type == IPR_RES_TYPE_GENERIC_ATA; |
b5145d25 BK |
1897 | } |
1898 | ||
ee0a90fa BK |
1899 | /** |
1900 | * ipr_is_naca_model - Determine if a resource is using NACA queueing model | |
1901 | * @res: resource entry struct | |
1902 | * | |
1903 | * Return value: | |
1904 | * 1 if NACA queueing model / 0 if not NACA queueing model | |
1905 | **/ | |
1906 | static inline int ipr_is_naca_model(struct ipr_resource_entry *res) | |
1907 | { | |
3e7ebdfa | 1908 | if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) |
ee0a90fa BK |
1909 | return 1; |
1910 | return 0; | |
1911 | } | |
1912 | ||
1da177e4 | 1913 | /** |
4565e370 WB |
1914 | * ipr_is_device - Determine if the hostrcb structure is related to a device |
1915 | * @hostrcb: host resource control blocks struct | |
1da177e4 LT |
1916 | * |
1917 | * Return value: | |
1918 | * 1 if AF / 0 if not AF | |
1919 | **/ | |
4565e370 | 1920 | static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) |
1da177e4 | 1921 | { |
4565e370 WB |
1922 | struct ipr_res_addr *res_addr; |
1923 | u8 *res_path; | |
1924 | ||
1925 | if (hostrcb->ioa_cfg->sis64) { | |
1926 | res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; | |
1927 | if ((res_path[0] == 0x00 || res_path[0] == 0x80 || | |
1928 | res_path[0] == 0x81) && res_path[2] != 0xFF) | |
1929 | return 1; | |
1930 | } else { | |
1931 | res_addr = &hostrcb->hcam.u.error.fd_res_addr; | |
1932 | ||
1933 | if ((res_addr->bus < IPR_MAX_NUM_BUSES) && | |
1934 | (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) | |
1935 | return 1; | |
1936 | } | |
1da177e4 LT |
1937 | return 0; |
1938 | } | |
1939 | ||
1940 | /** | |
1941 | * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 | |
1942 | * @sdt_word: SDT address | |
1943 | * | |
1944 | * Return value: | |
1945 | * 1 if format 2 / 0 if not | |
1946 | **/ | |
1947 | static inline int ipr_sdt_is_fmt2(u32 sdt_word) | |
1948 | { | |
1949 | u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); | |
1950 | ||
1951 | switch (bar_sel) { | |
1952 | case IPR_SDT_FMT2_BAR0_SEL: | |
1953 | case IPR_SDT_FMT2_BAR1_SEL: | |
1954 | case IPR_SDT_FMT2_BAR2_SEL: | |
1955 | case IPR_SDT_FMT2_BAR3_SEL: | |
1956 | case IPR_SDT_FMT2_BAR4_SEL: | |
1957 | case IPR_SDT_FMT2_BAR5_SEL: | |
1958 | case IPR_SDT_FMT2_EXP_ROM_SEL: | |
1959 | return 1; | |
1960 | }; | |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
c5f10187 WB |
1965 | #ifndef writeq |
1966 | static inline void writeq(u64 val, void __iomem *addr) | |
1967 | { | |
1968 | writel(((u32) (val >> 32)), addr); | |
1969 | writel(((u32) (val)), (addr + 4)); | |
1970 | } | |
1da177e4 | 1971 | #endif |
c5f10187 WB |
1972 | |
1973 | #endif /* _IPR_H */ |