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[SCSI] allow sleeping in ->eh_bus_reset_handler()
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / ips.c
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1da177e4
LT		 1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.xx - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/*****************************************************************************/
141
142/*
143 * Conditional Compilation directives for this driver:
144 *
145 * IPS_DEBUG - Turn on debugging info
146 *
147 * Parameters:
148 *
149 * debug:<number> - Set debug level to <number>
150 * NOTE: only works when IPS_DEBUG compile directive is used.
151 * 1 - Normal debug messages
152 * 2 - Verbose debug messages
153 * 11 - Method trace (non interrupt)
154 * 12 - Method trace (includes interrupt)
155 *
156 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
157 * nommap - Don't use memory mapped I/O
158 * ioctlsize - Initial size of the IOCTL buffer
159 */
160
161#include <asm/io.h>
162#include <asm/byteorder.h>
163#include <asm/page.h>
164#include <linux/stddef.h>
165#include <linux/version.h>
166#include <linux/string.h>
167#include <linux/errno.h>
168#include <linux/kernel.h>
169#include <linux/ioport.h>
170#include <linux/slab.h>
171#include <linux/delay.h>
172#include <linux/pci.h>
173#include <linux/proc_fs.h>
174#include <linux/reboot.h>
175#include <linux/interrupt.h>
176
177#include <linux/blkdev.h>
178#include <linux/types.h>
179
180#include <scsi/sg.h>
181
182#include "scsi.h"
183
184#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
185#include "hosts.h"
186#else
187#include <scsi/scsi_host.h>
188#endif
189
190#include "ips.h"
191
192#include <linux/module.h>
193
194#include <linux/stat.h>
195#include <linux/config.h>
196
197#include <linux/spinlock.h>
198#include <linux/init.h>
199
200#include <linux/smp.h>
201
202#ifdef MODULE
203static char *ips = NULL;
204module_param(ips, charp, 0);
205#endif
206
207/*
208 * DRIVER_VER
209 */
210#define IPS_VERSION_HIGH "7.10"
211#define IPS_VERSION_LOW ".18 "
212
213#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
214#warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
215#endif
216
217#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
218#include <linux/blk.h>
219#include "sd.h"
220#define IPS_SG_ADDRESS(sg) ((sg)->address)
221#define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
222#define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
223#ifndef __devexit_p
224#define __devexit_p(x) x
225#endif
226#else
227#define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
228 page_address((sg)->page)+(sg)->offset : NULL)
229#define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
230#define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
231#endif
232
233#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
be7db055 234 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
1da177e4 235 PCI_DMA_BIDIRECTIONAL : \
be7db055 236 scb->scsi_cmd->sc_data_direction)
1da177e4
LT		 237
238#ifdef IPS_DEBUG
239#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
240#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
241#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
242#else
243#define METHOD_TRACE(s, i)
244#define DEBUG(i, s)
245#define DEBUG_VAR(i, s, v...)
246#endif
247
248/*
249 * Function prototypes
250 */
251static int ips_detect(Scsi_Host_Template *);
252static int ips_release(struct Scsi_Host *);
253static int ips_eh_abort(Scsi_Cmnd *);
254static int ips_eh_reset(Scsi_Cmnd *);
255static int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
256static const char *ips_info(struct Scsi_Host *);
257static irqreturn_t do_ipsintr(int, void *, struct pt_regs *);
258static int ips_hainit(ips_ha_t *);
259static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
260static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
261static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
262static int ips_online(ips_ha_t *, ips_scb_t *);
263static int ips_inquiry(ips_ha_t *, ips_scb_t *);
264static int ips_rdcap(ips_ha_t *, ips_scb_t *);
265static int ips_msense(ips_ha_t *, ips_scb_t *);
266static int ips_reqsen(ips_ha_t *, ips_scb_t *);
267static int ips_deallocatescbs(ips_ha_t *, int);
268static int ips_allocatescbs(ips_ha_t *);
269static int ips_reset_copperhead(ips_ha_t *);
270static int ips_reset_copperhead_memio(ips_ha_t *);
271static int ips_reset_morpheus(ips_ha_t *);
272static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
273static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
274static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
275static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
276static int ips_isintr_copperhead(ips_ha_t *);
277static int ips_isintr_copperhead_memio(ips_ha_t *);
278static int ips_isintr_morpheus(ips_ha_t *);
279static int ips_wait(ips_ha_t *, int, int);
280static int ips_write_driver_status(ips_ha_t *, int);
281static int ips_read_adapter_status(ips_ha_t *, int);
282static int ips_read_subsystem_parameters(ips_ha_t *, int);
283static int ips_read_config(ips_ha_t *, int);
284static int ips_clear_adapter(ips_ha_t *, int);
285static int ips_readwrite_page5(ips_ha_t *, int, int);
286static int ips_init_copperhead(ips_ha_t *);
287static int ips_init_copperhead_memio(ips_ha_t *);
288static int ips_init_morpheus(ips_ha_t *);
289static int ips_isinit_copperhead(ips_ha_t *);
290static int ips_isinit_copperhead_memio(ips_ha_t *);
291static int ips_isinit_morpheus(ips_ha_t *);
292static int ips_erase_bios(ips_ha_t *);
293static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
294static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
295static int ips_erase_bios_memio(ips_ha_t *);
296static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
297static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
298static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
299static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
300static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
301static void ips_free_flash_copperhead(ips_ha_t * ha);
302static void ips_get_bios_version(ips_ha_t *, int);
303static void ips_identify_controller(ips_ha_t *);
304static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
305static void ips_enable_int_copperhead(ips_ha_t *);
306static void ips_enable_int_copperhead_memio(ips_ha_t *);
307static void ips_enable_int_morpheus(ips_ha_t *);
308static int ips_intr_copperhead(ips_ha_t *);
309static int ips_intr_morpheus(ips_ha_t *);
310static void ips_next(ips_ha_t *, int);
311static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
312static void ipsintr_done(ips_ha_t *, struct ips_scb *);
313static void ips_done(ips_ha_t *, ips_scb_t *);
314static void ips_free(ips_ha_t *);
315static void ips_init_scb(ips_ha_t *, ips_scb_t *);
316static void ips_freescb(ips_ha_t *, ips_scb_t *);
317static void ips_setup_funclist(ips_ha_t *);
318static void ips_statinit(ips_ha_t *);
319static void ips_statinit_memio(ips_ha_t *);
320static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
321static void ips_ffdc_reset(ips_ha_t *, int);
322static void ips_ffdc_time(ips_ha_t *);
323static uint32_t ips_statupd_copperhead(ips_ha_t *);
324static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
325static uint32_t ips_statupd_morpheus(ips_ha_t *);
326static ips_scb_t *ips_getscb(ips_ha_t *);
327static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
328static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
329static void ips_putq_copp_tail(ips_copp_queue_t *,
330 ips_copp_wait_item_t *);
331static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
332static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
333static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
334static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
335static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
336 ips_copp_wait_item_t *);
337static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
338
339static int ips_is_passthru(Scsi_Cmnd *);
340static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
341static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
342static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
343static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
344 unsigned int count);
345static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
346
347static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
348static int ips_host_info(ips_ha_t *, char *, off_t, int);
349static void copy_mem_info(IPS_INFOSTR *, char *, int);
350static int copy_info(IPS_INFOSTR *, char *, ...);
351static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
352static void ips_version_check(ips_ha_t * ha, int intr);
353static int ips_abort_init(ips_ha_t * ha, int index);
354static int ips_init_phase2(int index);
355
356static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
357static int ips_register_scsi(int index);
358
359/*
360 * global variables
361 */
362static const char ips_name[] = "ips";
363static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
364static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
365static unsigned int ips_next_controller;
366static unsigned int ips_num_controllers;
367static unsigned int ips_released_controllers;
368static int ips_hotplug;
369static int ips_cmd_timeout = 60;
370static int ips_reset_timeout = 60 * 5;
371static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
372static int ips_force_i2o = 1; /* Always use I2O command delivery */
373static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
374static int ips_cd_boot; /* Booting from Manager CD */
375static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
376static dma_addr_t ips_flashbusaddr;
377static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
378static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
379static Scsi_Host_Template ips_driver_template = {
380 .detect = ips_detect,
381 .release = ips_release,
382 .info = ips_info,
383 .queuecommand = ips_queue,
384 .eh_abort_handler = ips_eh_abort,
385 .eh_host_reset_handler = ips_eh_reset,
386 .proc_name = "ips",
387#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
388 .proc_info = ips_proc_info,
389 .slave_configure = ips_slave_configure,
390#else
391 .proc_info = ips_proc24_info,
392 .select_queue_depths = ips_select_queue_depth,
393#endif
394 .bios_param = ips_biosparam,
395 .this_id = -1,
396 .sg_tablesize = IPS_MAX_SG,
397 .cmd_per_lun = 3,
398 .use_clustering = ENABLE_CLUSTERING,
399#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
400 .use_new_eh_code = 1,
401#endif
402#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
403 .highmem_io = 1,
404#endif
405};
406
407static IPS_DEFINE_COMPAT_TABLE( Compatable ); /* Version Compatability Table */
408
409
410/* This table describes all ServeRAID Adapters */
411static struct pci_device_id ips_pci_table[] = {
412 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
413 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
414 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
415 { 0, }
416};
417
418MODULE_DEVICE_TABLE( pci, ips_pci_table );
419
420static char ips_hot_plug_name[] = "ips";
421
422static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
423static void __devexit ips_remove_device(struct pci_dev *pci_dev);
424
425static struct pci_driver ips_pci_driver = {
426 .name = ips_hot_plug_name,
427 .id_table = ips_pci_table,
428 .probe = ips_insert_device,
429 .remove = __devexit_p(ips_remove_device),
430};
431
432
433/*
434 * Necessary forward function protoypes
435 */
436static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
437
438#define MAX_ADAPTER_NAME 15
439
440static char ips_adapter_name[][30] = {
441 "ServeRAID",
442 "ServeRAID II",
443 "ServeRAID on motherboard",
444 "ServeRAID on motherboard",
445 "ServeRAID 3H",
446 "ServeRAID 3L",
447 "ServeRAID 4H",
448 "ServeRAID 4M",
449 "ServeRAID 4L",
450 "ServeRAID 4Mx",
451 "ServeRAID 4Lx",
452 "ServeRAID 5i",
453 "ServeRAID 5i",
454 "ServeRAID 6M",
455 "ServeRAID 6i",
456 "ServeRAID 7t",
457 "ServeRAID 7k",
458 "ServeRAID 7M"
459};
460
461static struct notifier_block ips_notifier = {
462 ips_halt, NULL, 0
463};
464
465/*
466 * Direction table
467 */
468static char ips_command_direction[] = {
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
470 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
473 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
474 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
475 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
478 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
479 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
480 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
481 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
482 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
483 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
484 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
491 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
492 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
493 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
494 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
495 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
496 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
497 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
498 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
499 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
500 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
501 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
502 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
503 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
504 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
505 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
506 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
507 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
508 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
509 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
510 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
511 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
512 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
513 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
514 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
515 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
516 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
517 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
518 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
519 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
520};
521
522
523/****************************************************************************/
524/* */
525/* Routine Name: ips_setup */
526/* */
527/* Routine Description: */
528/* */
529/* setup parameters to the driver */
530/* */
531/****************************************************************************/
532static int
533ips_setup(char *ips_str)
534{
535
536 int i;
537 char *key;
538 char *value;
539 IPS_OPTION options[] = {
540 {"noi2o", &ips_force_i2o, 0},
541 {"nommap", &ips_force_memio, 0},
542 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
543 {"cdboot", &ips_cd_boot, 0},
544 {"maxcmds", &MaxLiteCmds, 32},
545 };
546
547 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
548 /* Search for value */
549 while ((key = strsep(&ips_str, ",."))) {
550 if (!*key)
551 continue;
552 value = strchr(key, ':');
553 if (value)
554 *value++ = '\0';
555 /*
556 * We now have key/value pairs.
557 * Update the variables
558 */
559 for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
560 if (strnicmp
561 (key, options[i].option_name,
562 strlen(options[i].option_name)) == 0) {
563 if (value)
564 *options[i].option_flag =
565 simple_strtoul(value, NULL, 0);
566 else
567 *options[i].option_flag =
568 options[i].option_value;
569 break;
570 }
571 }
572 }
573
574 return (1);
575}
576
577__setup("ips=", ips_setup);
578
579/****************************************************************************/
580/* */
581/* Routine Name: ips_detect */
582/* */
583/* Routine Description: */
584/* */
585/* Detect and initialize the driver */
586/* */
587/* NOTE: this routine is called under the io_request_lock spinlock */
588/* */
589/****************************************************************************/
590static int
591ips_detect(Scsi_Host_Template * SHT)
592{
593 int i;
594
595 METHOD_TRACE("ips_detect", 1);
596
597#ifdef MODULE
598 if (ips)
599 ips_setup(ips);
600#endif
601
602 for (i = 0; i < ips_num_controllers; i++) {
603 if (ips_register_scsi(i))
604 ips_free(ips_ha[i]);
605 ips_released_controllers++;
606 }
607 ips_hotplug = 1;
608 return (ips_num_controllers);
609}
610
611/****************************************************************************/
612/* configure the function pointers to use the functions that will work */
613/* with the found version of the adapter */
614/****************************************************************************/
615static void
616ips_setup_funclist(ips_ha_t * ha)
617{
618
619 /*
620 * Setup Functions
621 */
622 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
623 /* morpheus / marco / sebring */
624 ha->func.isintr = ips_isintr_morpheus;
625 ha->func.isinit = ips_isinit_morpheus;
626 ha->func.issue = ips_issue_i2o_memio;
627 ha->func.init = ips_init_morpheus;
628 ha->func.statupd = ips_statupd_morpheus;
629 ha->func.reset = ips_reset_morpheus;
630 ha->func.intr = ips_intr_morpheus;
631 ha->func.enableint = ips_enable_int_morpheus;
632 } else if (IPS_USE_MEMIO(ha)) {
633 /* copperhead w/MEMIO */
634 ha->func.isintr = ips_isintr_copperhead_memio;
635 ha->func.isinit = ips_isinit_copperhead_memio;
636 ha->func.init = ips_init_copperhead_memio;
637 ha->func.statupd = ips_statupd_copperhead_memio;
638 ha->func.statinit = ips_statinit_memio;
639 ha->func.reset = ips_reset_copperhead_memio;
640 ha->func.intr = ips_intr_copperhead;
641 ha->func.erasebios = ips_erase_bios_memio;
642 ha->func.programbios = ips_program_bios_memio;
643 ha->func.verifybios = ips_verify_bios_memio;
644 ha->func.enableint = ips_enable_int_copperhead_memio;
645 if (IPS_USE_I2O_DELIVER(ha))
646 ha->func.issue = ips_issue_i2o_memio;
647 else
648 ha->func.issue = ips_issue_copperhead_memio;
649 } else {
650 /* copperhead */
651 ha->func.isintr = ips_isintr_copperhead;
652 ha->func.isinit = ips_isinit_copperhead;
653 ha->func.init = ips_init_copperhead;
654 ha->func.statupd = ips_statupd_copperhead;
655 ha->func.statinit = ips_statinit;
656 ha->func.reset = ips_reset_copperhead;
657 ha->func.intr = ips_intr_copperhead;
658 ha->func.erasebios = ips_erase_bios;
659 ha->func.programbios = ips_program_bios;
660 ha->func.verifybios = ips_verify_bios;
661 ha->func.enableint = ips_enable_int_copperhead;
662
663 if (IPS_USE_I2O_DELIVER(ha))
664 ha->func.issue = ips_issue_i2o;
665 else
666 ha->func.issue = ips_issue_copperhead;
667 }
668}
669
670/****************************************************************************/
671/* */
672/* Routine Name: ips_release */
673/* */
674/* Routine Description: */
675/* */
676/* Remove a driver */
677/* */
678/****************************************************************************/
679static int
680ips_release(struct Scsi_Host *sh)
681{
682 ips_scb_t *scb;
683 ips_ha_t *ha;
684 int i;
685
686 METHOD_TRACE("ips_release", 1);
687
688 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
689
690 if (i == IPS_MAX_ADAPTERS) {
691 printk(KERN_WARNING
692 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
693 BUG();
694 return (FALSE);
695 }
696
697 ha = IPS_HA(sh);
698
699 if (!ha)
700 return (FALSE);
701
702 /* flush the cache on the controller */
703 scb = &ha->scbs[ha->max_cmds - 1];
704
705 ips_init_scb(ha, scb);
706
707 scb->timeout = ips_cmd_timeout;
708 scb->cdb[0] = IPS_CMD_FLUSH;
709
710 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
711 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
712 scb->cmd.flush_cache.state = IPS_NORM_STATE;
713 scb->cmd.flush_cache.reserved = 0;
714 scb->cmd.flush_cache.reserved2 = 0;
715 scb->cmd.flush_cache.reserved3 = 0;
716 scb->cmd.flush_cache.reserved4 = 0;
717
718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
719
720 /* send command */
721 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
722 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
723
724 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
725
726 ips_sh[i] = NULL;
727 ips_ha[i] = NULL;
728
729 /* free extra memory */
730 ips_free(ha);
731
732 /* Free I/O Region */
733 if (ha->io_addr)
734 release_region(ha->io_addr, ha->io_len);
735
736 /* free IRQ */
737 free_irq(ha->irq, ha);
738
739 IPS_REMOVE_HOST(sh);
740 scsi_host_put(sh);
741
742 ips_released_controllers++;
743
744 return (FALSE);
745}
746
747/****************************************************************************/
748/* */
749/* Routine Name: ips_halt */
750/* */
751/* Routine Description: */
752/* */
753/* Perform cleanup when the system reboots */
754/* */
755/****************************************************************************/
756static int
757ips_halt(struct notifier_block *nb, ulong event, void *buf)
758{
759 ips_scb_t *scb;
760 ips_ha_t *ha;
761 int i;
762
763 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
764 (event != SYS_POWER_OFF))
765 return (NOTIFY_DONE);
766
767 for (i = 0; i < ips_next_controller; i++) {
768 ha = (ips_ha_t *) ips_ha[i];
769
770 if (!ha)
771 continue;
772
773 if (!ha->active)
774 continue;
775
776 /* flush the cache on the controller */
777 scb = &ha->scbs[ha->max_cmds - 1];
778
779 ips_init_scb(ha, scb);
780
781 scb->timeout = ips_cmd_timeout;
782 scb->cdb[0] = IPS_CMD_FLUSH;
783
784 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
785 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
786 scb->cmd.flush_cache.state = IPS_NORM_STATE;
787 scb->cmd.flush_cache.reserved = 0;
788 scb->cmd.flush_cache.reserved2 = 0;
789 scb->cmd.flush_cache.reserved3 = 0;
790 scb->cmd.flush_cache.reserved4 = 0;
791
792 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
793
794 /* send command */
795 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
796 IPS_FAILURE)
797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
798 "Incomplete Flush.\n");
799 else
800 IPS_PRINTK(KERN_WARNING, ha->pcidev,
801 "Flushing Complete.\n");
802 }
803
804 return (NOTIFY_OK);
805}
806
807/****************************************************************************/
808/* */
809/* Routine Name: ips_eh_abort */
810/* */
811/* Routine Description: */
812/* */
813/* Abort a command (using the new error code stuff) */
814/* Note: this routine is called under the io_request_lock */
815/****************************************************************************/
816int
817ips_eh_abort(Scsi_Cmnd * SC)
818{
819 ips_ha_t *ha;
820 ips_copp_wait_item_t *item;
821 int ret;
8fa728a2
JG		 822 unsigned long cpu_flags;
823 struct Scsi_Host *host;
1da177e4
LT		 824
825 METHOD_TRACE("ips_eh_abort", 1);
826
827 if (!SC)
828 return (FAILED);
829
8fa728a2 830 host = SC->device->host;
1da177e4
LT		 831 ha = (ips_ha_t *) SC->device->host->hostdata;
832
833 if (!ha)
834 return (FAILED);
835
836 if (!ha->active)
837 return (FAILED);
838
8fa728a2
JG		 839 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
840
1da177e4
LT		 841 /* See if the command is on the copp queue */
842 item = ha->copp_waitlist.head;
843 while ((item) && (item->scsi_cmd != SC))
844 item = item->next;
845
846 if (item) {
847 /* Found it */
848 ips_removeq_copp(&ha->copp_waitlist, item);
849 ret = (SUCCESS);
850
851 /* See if the command is on the wait queue */
852 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
853 /* command not sent yet */
854 ret = (SUCCESS);
855 } else {
856 /* command must have already been sent */
857 ret = (FAILED);
858 }
8fa728a2
JG		 859
860 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1da177e4
LT		 861 return ret;
862}
863
864/****************************************************************************/
865/* */
866/* Routine Name: ips_eh_reset */
867/* */
868/* Routine Description: */
869/* */
870/* Reset the controller (with new eh error code) */
871/* */
872/* NOTE: this routine is called under the io_request_lock spinlock */
873/* */
874/****************************************************************************/
875static int
876ips_eh_reset(Scsi_Cmnd * SC)
877{
878 int ret;
879 int i;
880 ips_ha_t *ha;
881 ips_scb_t *scb;
882 ips_copp_wait_item_t *item;
883
884 METHOD_TRACE("ips_eh_reset", 1);
885
886#ifdef NO_IPS_RESET
887 return (FAILED);
888#else
889
890 if (!SC) {
891 DEBUG(1, "Reset called with NULL scsi command");
892
893 return (FAILED);
894 }
895
896 ha = (ips_ha_t *) SC->device->host->hostdata;
897
898 if (!ha) {
899 DEBUG(1, "Reset called with NULL ha struct");
900
901 return (FAILED);
902 }
903
904 if (!ha->active)
905 return (FAILED);
906
907 /* See if the command is on the copp queue */
908 item = ha->copp_waitlist.head;
909 while ((item) && (item->scsi_cmd != SC))
910 item = item->next;
911
912 if (item) {
913 /* Found it */
914 ips_removeq_copp(&ha->copp_waitlist, item);
915 return (SUCCESS);
916 }
917
918 /* See if the command is on the wait queue */
919 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
920 /* command not sent yet */
921 return (SUCCESS);
922 }
923
924 /* An explanation for the casual observer: */
925 /* Part of the function of a RAID controller is automatic error */
926 /* detection and recovery. As such, the only problem that physically */
927 /* resetting an adapter will ever fix is when, for some reason, */
928 /* the driver is not successfully communicating with the adapter. */
929 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
930 /* then there's no real purpose in a physical reset. This will complete */
931 /* much faster and avoids any problems that might be caused by a */
932 /* physical reset ( such as having to fail all the outstanding I/O's ). */
933
934 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
935 scb = &ha->scbs[ha->max_cmds - 1];
936
937 ips_init_scb(ha, scb);
938
939 scb->timeout = ips_cmd_timeout;
940 scb->cdb[0] = IPS_CMD_FLUSH;
941
942 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
943 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
944 scb->cmd.flush_cache.state = IPS_NORM_STATE;
945 scb->cmd.flush_cache.reserved = 0;
946 scb->cmd.flush_cache.reserved2 = 0;
947 scb->cmd.flush_cache.reserved3 = 0;
948 scb->cmd.flush_cache.reserved4 = 0;
949
950 /* Attempt the flush command */
951 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
952 if (ret == IPS_SUCCESS) {
953 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
954 "Reset Request - Flushed Cache\n");
955 return (SUCCESS);
956 }
957 }
958
959 /* Either we can't communicate with the adapter or it's an IOCTL request */
960 /* from a utility. A physical reset is needed at this point. */
961
962 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
963
964 /*
965 * command must have already been sent
966 * reset the controller
967 */
968 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
969 ret = (*ha->func.reset) (ha);
970
971 if (!ret) {
972 Scsi_Cmnd *scsi_cmd;
973
974 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
975 "Controller reset failed - controller now offline.\n");
976
977 /* Now fail all of the active commands */
978 DEBUG_VAR(1, "(%s%d) Failing active commands",
979 ips_name, ha->host_num);
980
981 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
982 scb->scsi_cmd->result = DID_ERROR << 16;
983 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
984 ips_freescb(ha, scb);
985 }
986
987 /* Now fail all of the pending commands */
988 DEBUG_VAR(1, "(%s%d) Failing pending commands",
989 ips_name, ha->host_num);
990
991 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
992 scsi_cmd->result = DID_ERROR;
993 scsi_cmd->scsi_done(scsi_cmd);
994 }
995
996 ha->active = FALSE;
997 return (FAILED);
998 }
999
1000 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
1001 Scsi_Cmnd *scsi_cmd;
1002
1003 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
1004 "Controller reset failed - controller now offline.\n");
1005
1006 /* Now fail all of the active commands */
1007 DEBUG_VAR(1, "(%s%d) Failing active commands",
1008 ips_name, ha->host_num);
1009
1010 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1011 scb->scsi_cmd->result = DID_ERROR << 16;
1012 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1013 ips_freescb(ha, scb);
1014 }
1015
1016 /* Now fail all of the pending commands */
1017 DEBUG_VAR(1, "(%s%d) Failing pending commands",
1018 ips_name, ha->host_num);
1019
1020 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1021 scsi_cmd->result = DID_ERROR << 16;
1022 scsi_cmd->scsi_done(scsi_cmd);
1023 }
1024
1025 ha->active = FALSE;
1026 return (FAILED);
1027 }
1028
1029 /* FFDC */
1030 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1031 struct timeval tv;
1032
1033 do_gettimeofday(&tv);
1034 ha->last_ffdc = tv.tv_sec;
1035 ha->reset_count++;
1036 ips_ffdc_reset(ha, IPS_INTR_IORL);
1037 }
1038
1039 /* Now fail all of the active commands */
1040 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1041
1042 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1043 scb->scsi_cmd->result =
1044 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1045 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1046 ips_freescb(ha, scb);
1047 }
1048
1049 /* Reset DCDB active command bits */
1050 for (i = 1; i < ha->nbus; i++)
1051 ha->dcdb_active[i - 1] = 0;
1052
1053 /* Reset the number of active IOCTLs */
1054 ha->num_ioctl = 0;
1055
1056 ips_next(ha, IPS_INTR_IORL);
1057
1058 return (SUCCESS);
1059#endif /* NO_IPS_RESET */
1060
1061}
1062
1063/****************************************************************************/
1064/* */
1065/* Routine Name: ips_queue */
1066/* */
1067/* Routine Description: */
1068/* */
1069/* Send a command to the controller */
1070/* */
1071/* NOTE: */
1072/* Linux obtains io_request_lock before calling this function */
1073/* */
1074/****************************************************************************/
1075static int
1076ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
1077{
1078 ips_ha_t *ha;
1079 ips_passthru_t *pt;
1080
1081 METHOD_TRACE("ips_queue", 1);
1082
1083 ha = (ips_ha_t *) SC->device->host->hostdata;
1084
1085 if (!ha)
1086 return (1);
1087
1088 if (!ha->active)
1089 return (DID_ERROR);
1090
1091 if (ips_is_passthru(SC)) {
1092 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1093 SC->result = DID_BUS_BUSY << 16;
1094 done(SC);
1095
1096 return (0);
1097 }
1098 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1099 SC->result = DID_BUS_BUSY << 16;
1100 done(SC);
1101
1102 return (0);
1103 }
1104
1105 SC->scsi_done = done;
1106
1107 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1108 ips_name,
1109 ha->host_num,
1110 SC->cmnd[0],
1111 SC->device->channel, SC->device->id, SC->device->lun);
1112
1113 /* Check for command to initiator IDs */
1114 if ((SC->device->channel > 0)
1115 && (SC->device->id == ha->ha_id[SC->device->channel])) {
1116 SC->result = DID_NO_CONNECT << 16;
1117 done(SC);
1118
1119 return (0);
1120 }
1121
1122 if (ips_is_passthru(SC)) {
1123
1124 ips_copp_wait_item_t *scratch;
1125
1126 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1127 /* There can never be any system activity ( network or disk ), but check */
1128 /* anyway just as a good practice. */
1129 pt = (ips_passthru_t *) SC->request_buffer;
1130 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1131 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1132 if (ha->scb_activelist.count != 0) {
1133 SC->result = DID_BUS_BUSY << 16;
1134 done(SC);
1135 return (0);
1136 }
1137 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1138 ips_eh_reset(SC);
1139 SC->result = DID_OK << 16;
1140 SC->scsi_done(SC);
1141 return (0);
1142 }
1143
1144 /* allocate space for the scribble */
1145 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1146
1147 if (!scratch) {
1148 SC->result = DID_ERROR << 16;
1149 done(SC);
1150
1151 return (0);
1152 }
1153
1154 scratch->scsi_cmd = SC;
1155 scratch->next = NULL;
1156
1157 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1158 } else {
1159 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1160 }
1161
1162 ips_next(ha, IPS_INTR_IORL);
1163
1164 return (0);
1165}
1166
1167/****************************************************************************/
1168/* */
1169/* Routine Name: ips_biosparam */
1170/* */
1171/* Routine Description: */
1172/* */
1173/* Set bios geometry for the controller */
1174/* */
1175/****************************************************************************/
1176static int
1177#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1178ips_biosparam(Disk * disk, kdev_t dev, int geom[])
1179{
1180 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1181 unsigned long capacity = disk->capacity;
1182#else
1183ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1184 sector_t capacity, int geom[])
1185{
1186 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1187#endif
1188 int heads;
1189 int sectors;
1190 int cylinders;
1191
1192 METHOD_TRACE("ips_biosparam", 1);
1193
1194 if (!ha)
1195 /* ?!?! host adater info invalid */
1196 return (0);
1197
1198 if (!ha->active)
1199 return (0);
1200
1201 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1202 /* ?!?! Enquiry command failed */
1203 return (0);
1204
1205 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1206 heads = IPS_NORM_HEADS;
1207 sectors = IPS_NORM_SECTORS;
1208 } else {
1209 heads = IPS_COMP_HEADS;
1210 sectors = IPS_COMP_SECTORS;
1211 }
1212
1213 cylinders = (unsigned long) capacity / (heads * sectors);
1214
1215 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1216 heads, sectors, cylinders);
1217
1218 geom[0] = heads;
1219 geom[1] = sectors;
1220 geom[2] = cylinders;
1221
1222 return (0);
1223}
1224
1225#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1226
1227/* ips_proc24_info is a wrapper around ips_proc_info *
1228 * for compatibility with the 2.4 scsi parameters */
1229static int
1230ips_proc24_info(char *buffer, char **start, off_t offset, int length,
1231 int hostno, int func)
1232{
1233 int i;
1234
1235 for (i = 0; i < ips_next_controller; i++) {
1236 if (ips_sh[i] && ips_sh[i]->host_no == hostno) {
1237 return ips_proc_info(ips_sh[i], buffer, start,
1238 offset, length, func);
1239 }
1240 }
1241 return -EINVAL;
1242}
1243
1244/****************************************************************************/
1245/* */
1246/* Routine Name: ips_select_queue_depth */
1247/* */
1248/* Routine Description: */
1249/* */
1250/* Select queue depths for the devices on the contoller */
1251/* */
1252/****************************************************************************/
1253static void
1254ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
1255{
1256 Scsi_Device *device;
1257 ips_ha_t *ha;
1258 int count = 0;
1259 int min;
1260
1261 ha = IPS_HA(host);
1262 min = ha->max_cmds / 4;
1263
1264 for (device = scsi_devs; device; device = device->next) {
1265 if (device->host == host) {
1266 if ((device->channel == 0) && (device->type == 0))
1267 count++;
1268 }
1269 }
1270
1271 for (device = scsi_devs; device; device = device->next) {
1272 if (device->host == host) {
1273 if ((device->channel == 0) && (device->type == 0)) {
1274 device->queue_depth =
1275 (ha->max_cmds - 1) / count;
1276 if (device->queue_depth < min)
1277 device->queue_depth = min;
1278 } else {
1279 device->queue_depth = 2;
1280 }
1281
1282 if (device->queue_depth < 2)
1283 device->queue_depth = 2;
1284 }
1285 }
1286}
1287
1288#else
1289/****************************************************************************/
1290/* */
1291/* Routine Name: ips_slave_configure */
1292/* */
1293/* Routine Description: */
1294/* */
1295/* Set queue depths on devices once scan is complete */
1296/* */
1297/****************************************************************************/
1298static int
1299ips_slave_configure(Scsi_Device * SDptr)
1300{
1301 ips_ha_t *ha;
1302 int min;
1303
1304 ha = IPS_HA(SDptr->host);
1305 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1306 min = ha->max_cmds / 2;
1307 if (ha->enq->ucLogDriveCount <= 2)
1308 min = ha->max_cmds - 1;
1309 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1310 }
1311 return 0;
1312}
1313#endif
1314
1315/****************************************************************************/
1316/* */
1317/* Routine Name: do_ipsintr */
1318/* */
1319/* Routine Description: */
1320/* */
1321/* Wrapper for the interrupt handler */
1322/* */
1323/****************************************************************************/
1324static irqreturn_t
1325do_ipsintr(int irq, void *dev_id, struct pt_regs * regs)
1326{
1327 ips_ha_t *ha;
1328 unsigned long cpu_flags;
1329 struct Scsi_Host *host;
1330 int irqstatus;
1331
1332 METHOD_TRACE("do_ipsintr", 2);
1333
1334 ha = (ips_ha_t *) dev_id;
1335 if (!ha)
1336 return IRQ_NONE;
1337 host = ips_sh[ha->host_num];
1338 /* interrupt during initialization */
1339 if (!host) {
1340 (*ha->func.intr) (ha);
1341 return IRQ_HANDLED;
1342 }
1343
1344 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
1345
1346 if (!ha->active) {
1347 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1348 return IRQ_HANDLED;
1349 }
1350
1351 irqstatus = (*ha->func.intr) (ha);
1352
1353 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1354
1355 /* start the next command */
1356 ips_next(ha, IPS_INTR_ON);
1357 return IRQ_RETVAL(irqstatus);
1358}
1359
1360/****************************************************************************/
1361/* */
1362/* Routine Name: ips_intr_copperhead */
1363/* */
1364/* Routine Description: */
1365/* */
1366/* Polling interrupt handler */
1367/* */
1368/* ASSUMES interrupts are disabled */
1369/* */
1370/****************************************************************************/
1371int
1372ips_intr_copperhead(ips_ha_t * ha)
1373{
1374 ips_stat_t *sp;
1375 ips_scb_t *scb;
1376 IPS_STATUS cstatus;
1377 int intrstatus;
1378
1379 METHOD_TRACE("ips_intr", 2);
1380
1381 if (!ha)
1382 return 0;
1383
1384 if (!ha->active)
1385 return 0;
1386
1387 intrstatus = (*ha->func.isintr) (ha);
1388
1389 if (!intrstatus) {
1390 /*
1391 * Unexpected/Shared interrupt
1392 */
1393
1394 return 0;
1395 }
1396
1397 while (TRUE) {
1398 sp = &ha->sp;
1399
1400 intrstatus = (*ha->func.isintr) (ha);
1401
1402 if (!intrstatus)
1403 break;
1404 else
1405 cstatus.value = (*ha->func.statupd) (ha);
1406
1407 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1408 /* Spurious Interupt ? */
1409 continue;
1410 }
1411
1412 ips_chkstatus(ha, &cstatus);
1413 scb = (ips_scb_t *) sp->scb_addr;
1414
1415 /*
1416 * use the callback function to finish things up
1417 * NOTE: interrupts are OFF for this
1418 */
1419 (*scb->callback) (ha, scb);
1420 } /* end while */
1421 return 1;
1422}
1423
1424/****************************************************************************/
1425/* */
1426/* Routine Name: ips_intr_morpheus */
1427/* */
1428/* Routine Description: */
1429/* */
1430/* Polling interrupt handler */
1431/* */
1432/* ASSUMES interrupts are disabled */
1433/* */
1434/****************************************************************************/
1435int
1436ips_intr_morpheus(ips_ha_t * ha)
1437{
1438 ips_stat_t *sp;
1439 ips_scb_t *scb;
1440 IPS_STATUS cstatus;
1441 int intrstatus;
1442
1443 METHOD_TRACE("ips_intr_morpheus", 2);
1444
1445 if (!ha)
1446 return 0;
1447
1448 if (!ha->active)
1449 return 0;
1450
1451 intrstatus = (*ha->func.isintr) (ha);
1452
1453 if (!intrstatus) {
1454 /*
1455 * Unexpected/Shared interrupt
1456 */
1457
1458 return 0;
1459 }
1460
1461 while (TRUE) {
1462 sp = &ha->sp;
1463
1464 intrstatus = (*ha->func.isintr) (ha);
1465
1466 if (!intrstatus)
1467 break;
1468 else
1469 cstatus.value = (*ha->func.statupd) (ha);
1470
1471 if (cstatus.value == 0xffffffff)
1472 /* No more to process */
1473 break;
1474
1475 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1476 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1477 "Spurious interrupt; no ccb.\n");
1478
1479 continue;
1480 }
1481
1482 ips_chkstatus(ha, &cstatus);
1483 scb = (ips_scb_t *) sp->scb_addr;
1484
1485 /*
1486 * use the callback function to finish things up
1487 * NOTE: interrupts are OFF for this
1488 */
1489 (*scb->callback) (ha, scb);
1490 } /* end while */
1491 return 1;
1492}
1493
1494/****************************************************************************/
1495/* */
1496/* Routine Name: ips_info */
1497/* */
1498/* Routine Description: */
1499/* */
1500/* Return info about the driver */
1501/* */
1502/****************************************************************************/
1503static const char *
1504ips_info(struct Scsi_Host *SH)
1505{
1506 static char buffer[256];
1507 char *bp;
1508 ips_ha_t *ha;
1509
1510 METHOD_TRACE("ips_info", 1);
1511
1512 ha = IPS_HA(SH);
1513
1514 if (!ha)
1515 return (NULL);
1516
1517 bp = &buffer[0];
1518 memset(bp, 0, sizeof (buffer));
1519
1520 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1521 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1522
1523 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1524 strcat(bp, " <");
1525 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1526 strcat(bp, ">");
1527 }
1528
1529 return (bp);
1530}
1531
1532/****************************************************************************/
1533/* */
1534/* Routine Name: ips_proc_info */
1535/* */
1536/* Routine Description: */
1537/* */
1538/* The passthru interface for the driver */
1539/* */
1540/****************************************************************************/
1541static int
1542ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1543 int length, int func)
1544{
1545 int i;
1546 int ret;
1547 ips_ha_t *ha = NULL;
1548
1549 METHOD_TRACE("ips_proc_info", 1);
1550
1551 /* Find our host structure */
1552 for (i = 0; i < ips_next_controller; i++) {
1553 if (ips_sh[i]) {
1554 if (ips_sh[i] == host) {
1555 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1556 break;
1557 }
1558 }
1559 }
1560
1561 if (!ha)
1562 return (-EINVAL);
1563
1564 if (func) {
1565 /* write */
1566 return (0);
1567 } else {
1568 /* read */
1569 if (start)
1570 *start = buffer;
1571
1572 ret = ips_host_info(ha, buffer, offset, length);
1573
1574 return (ret);
1575 }
1576}
1577
1578/*--------------------------------------------------------------------------*/
1579/* Helper Functions */
1580/*--------------------------------------------------------------------------*/
1581
1582/****************************************************************************/
1583/* */
1584/* Routine Name: ips_is_passthru */
1585/* */
1586/* Routine Description: */
1587/* */
1588/* Determine if the specified SCSI command is really a passthru command */
1589/* */
1590/****************************************************************************/
1591static int
1592ips_is_passthru(Scsi_Cmnd * SC)
1593{
1594 METHOD_TRACE("ips_is_passthru", 1);
1595
1596 if (!SC)
1597 return (0);
1598
1599 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1600 (SC->device->channel == 0) &&
1601 (SC->device->id == IPS_ADAPTER_ID) &&
1602 (SC->device->lun == 0) && SC->request_buffer) {
1603 if ((!SC->use_sg) && SC->request_bufflen &&
1604 (((char *) SC->request_buffer)[0] == 'C') &&
1605 (((char *) SC->request_buffer)[1] == 'O') &&
1606 (((char *) SC->request_buffer)[2] == 'P') &&
1607 (((char *) SC->request_buffer)[3] == 'P'))
1608 return 1;
1609 else if (SC->use_sg) {
1610 struct scatterlist *sg = SC->request_buffer;
1611 char *buffer = IPS_SG_ADDRESS(sg);
1612 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1613 buffer[2] == 'P' && buffer[3] == 'P')
1614 return 1;
1615 }
1616 }
1617 return 0;
1618}
1619
1620/****************************************************************************/
1621/* */
1622/* Routine Name: ips_alloc_passthru_buffer */
1623/* */
1624/* Routine Description: */
1625/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1626/* is too small or doesn't exist */
1627/****************************************************************************/
1628static int
1629ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1630{
1631 void *bigger_buf;
1632 dma_addr_t dma_busaddr;
1633
1634 if (ha->ioctl_data && length <= ha->ioctl_len)
1635 return 0;
1636 /* there is no buffer or it's not big enough, allocate a new one */
1637 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1638 if (bigger_buf) {
1639 /* free the old memory */
1640 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1641 ha->ioctl_busaddr);
1642 /* use the new memory */
1643 ha->ioctl_data = (char *) bigger_buf;
1644 ha->ioctl_len = length;
1645 ha->ioctl_busaddr = dma_busaddr;
1646 } else {
1647 return -1;
1648 }
1649 return 0;
1650}
1651
1652/****************************************************************************/
1653/* */
1654/* Routine Name: ips_make_passthru */
1655/* */
1656/* Routine Description: */
1657/* */
1658/* Make a passthru command out of the info in the Scsi block */
1659/* */
1660/****************************************************************************/
1661static int
1662ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
1663{
1664 ips_passthru_t *pt;
1665 int length = 0;
1666 int ret;
1667
1668 METHOD_TRACE("ips_make_passthru", 1);
1669
1670 if (!SC->use_sg) {
1671 length = SC->request_bufflen;
1672 } else {
1673 struct scatterlist *sg = SC->request_buffer;
1674 int i;
1675 for (i = 0; i < SC->use_sg; i++)
1676 length += sg[i].length;
1677 }
1678 if (length < sizeof (ips_passthru_t)) {
1679 /* wrong size */
1680 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1681 ips_name, ha->host_num);
1682 return (IPS_FAILURE);
1683 }
1684 if (ips_alloc_passthru_buffer(ha, length)) {
1685 /* allocation failure! If ha->ioctl_data exists, use it to return
1686 some error codes. Return a failed command to the scsi layer. */
1687 if (ha->ioctl_data) {
1688 pt = (ips_passthru_t *) ha->ioctl_data;
1689 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1690 pt->BasicStatus = 0x0B;
1691 pt->ExtendedStatus = 0x00;
1692 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1693 }
1694 return IPS_FAILURE;
1695 }
1696 ha->ioctl_datasize = length;
1697
1698 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1699 pt = (ips_passthru_t *) ha->ioctl_data;
1700
1701 /*
1702 * Some notes about the passthru interface used
1703 *
1704 * IF the scsi op_code == 0x0d then we assume
1705 * that the data came along with/goes with the
1706 * packet we received from the sg driver. In this
1707 * case the CmdBSize field of the pt structure is
1708 * used for the size of the buffer.
1709 */
1710
1711 switch (pt->CoppCmd) {
1712 case IPS_NUMCTRLS:
1713 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1714 &ips_num_controllers, sizeof (int));
1715 ips_scmd_buf_write(SC, ha->ioctl_data,
1716 sizeof (ips_passthru_t) + sizeof (int));
1717 SC->result = DID_OK << 16;
1718
1719 return (IPS_SUCCESS_IMM);
1720
1721 case IPS_COPPUSRCMD:
1722 case IPS_COPPIOCCMD:
1723 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1724 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1725 /* wrong size */
1726 DEBUG_VAR(1,
1727 "(%s%d) Passthru structure wrong size",
1728 ips_name, ha->host_num);
1729
1730 return (IPS_FAILURE);
1731 }
1732
1733 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1734 pt->CoppCP.cmd.flashfw.op_code ==
1735 IPS_CMD_RW_BIOSFW) {
1736 ret = ips_flash_copperhead(ha, pt, scb);
1737 ips_scmd_buf_write(SC, ha->ioctl_data,
1738 sizeof (ips_passthru_t));
1739 return ret;
1740 }
1741 if (ips_usrcmd(ha, pt, scb))
1742 return (IPS_SUCCESS);
1743 else
1744 return (IPS_FAILURE);
1745 }
1746
1747 break;
1748
1749 } /* end switch */
1750
1751 return (IPS_FAILURE);
1752}
1753
1754/****************************************************************************/
1755/* Routine Name: ips_flash_copperhead */
1756/* Routine Description: */
1757/* Flash the BIOS/FW on a Copperhead style controller */
1758/****************************************************************************/
1759static int
1760ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1761{
1762 int datasize;
1763
1764 /* Trombone is the only copperhead that can do packet flash, but only
1765 * for firmware. No one said it had to make sence. */
1766 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1767 if (ips_usrcmd(ha, pt, scb))
1768 return IPS_SUCCESS;
1769 else
1770 return IPS_FAILURE;
1771 }
1772 pt->BasicStatus = 0x0B;
1773 pt->ExtendedStatus = 0;
1774 scb->scsi_cmd->result = DID_OK << 16;
1775 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1776 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1777 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1778 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1779 pt->BasicStatus = 0;
1780 return ips_flash_bios(ha, pt, scb);
1781 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1782 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1783 ha->flash_data = ips_FlashData;
1784 ha->flash_busaddr = ips_flashbusaddr;
1785 ha->flash_len = PAGE_SIZE << 7;
1786 ha->flash_datasize = 0;
1787 } else if (!ha->flash_data) {
1788 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1789 pt->CoppCP.cmd.flashfw.count;
1790 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1791 datasize,
1792 &ha->flash_busaddr);
1793 if (!ha->flash_data){
1794 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1795 return IPS_FAILURE;
1796 }
1797 ha->flash_datasize = 0;
1798 ha->flash_len = datasize;
1799 } else
1800 return IPS_FAILURE;
1801 } else {
1802 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1803 ha->flash_len) {
1804 ips_free_flash_copperhead(ha);
1805 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1806 "failed size sanity check\n");
1807 return IPS_FAILURE;
1808 }
1809 }
1810 if (!ha->flash_data)
1811 return IPS_FAILURE;
1812 pt->BasicStatus = 0;
1813 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1814 pt->CoppCP.cmd.flashfw.count);
1815 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1816 if (pt->CoppCP.cmd.flashfw.packet_num ==
1817 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1818 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1819 return ips_flash_bios(ha, pt, scb);
1820 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1821 return ips_flash_firmware(ha, pt, scb);
1822 }
1823 return IPS_SUCCESS_IMM;
1824}
1825
1826/****************************************************************************/
1827/* Routine Name: ips_flash_bios */
1828/* Routine Description: */
1829/* flashes the bios of a copperhead adapter */
1830/****************************************************************************/
1831static int
1832ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1833{
1834
1835 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1836 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1837 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1838 (!ha->func.verifybios))
1839 goto error;
1840 if ((*ha->func.erasebios) (ha)) {
1841 DEBUG_VAR(1,
1842 "(%s%d) flash bios failed - unable to erase flash",
1843 ips_name, ha->host_num);
1844 goto error;
1845 } else
1846 if ((*ha->func.programbios) (ha,
1847 ha->flash_data +
1848 IPS_BIOS_HEADER,
1849 ha->flash_datasize -
1850 IPS_BIOS_HEADER, 0)) {
1851 DEBUG_VAR(1,
1852 "(%s%d) flash bios failed - unable to flash",
1853 ips_name, ha->host_num);
1854 goto error;
1855 } else
1856 if ((*ha->func.verifybios) (ha,
1857 ha->flash_data +
1858 IPS_BIOS_HEADER,
1859 ha->flash_datasize -
1860 IPS_BIOS_HEADER, 0)) {
1861 DEBUG_VAR(1,
1862 "(%s%d) flash bios failed - unable to verify flash",
1863 ips_name, ha->host_num);
1864 goto error;
1865 }
1866 ips_free_flash_copperhead(ha);
1867 return IPS_SUCCESS_IMM;
1868 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1869 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1870 if (!ha->func.erasebios)
1871 goto error;
1872 if ((*ha->func.erasebios) (ha)) {
1873 DEBUG_VAR(1,
1874 "(%s%d) flash bios failed - unable to erase flash",
1875 ips_name, ha->host_num);
1876 goto error;
1877 }
1878 return IPS_SUCCESS_IMM;
1879 }
1880 error:
1881 pt->BasicStatus = 0x0B;
1882 pt->ExtendedStatus = 0x00;
1883 ips_free_flash_copperhead(ha);
1884 return IPS_FAILURE;
1885}
1886
1887/****************************************************************************/
1888/* */
1889/* Routine Name: ips_fill_scb_sg_single */
1890/* */
1891/* Routine Description: */
1892/* Fill in a single scb sg_list element from an address */
1893/* return a -1 if a breakup occurred */
1894/****************************************************************************/
1895static int
1896ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1897 ips_scb_t * scb, int indx, unsigned int e_len)
1898{
1899
1900 int ret_val = 0;
1901
1902 if ((scb->data_len + e_len) > ha->max_xfer) {
1903 e_len = ha->max_xfer - scb->data_len;
1904 scb->breakup = indx;
1905 ++scb->sg_break;
1906 ret_val = -1;
1907 } else {
1908 scb->breakup = 0;
1909 scb->sg_break = 0;
1910 }
1911 if (IPS_USE_ENH_SGLIST(ha)) {
1912 scb->sg_list.enh_list[indx].address_lo =
1913 cpu_to_le32(pci_dma_lo32(busaddr));
1914 scb->sg_list.enh_list[indx].address_hi =
1915 cpu_to_le32(pci_dma_hi32(busaddr));
1916 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1917 } else {
1918 scb->sg_list.std_list[indx].address =
1919 cpu_to_le32(pci_dma_lo32(busaddr));
1920 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1921 }
1922
1923 ++scb->sg_len;
1924 scb->data_len += e_len;
1925 return ret_val;
1926}
1927
1928/****************************************************************************/
1929/* Routine Name: ips_flash_firmware */
1930/* Routine Description: */
1931/* flashes the firmware of a copperhead adapter */
1932/****************************************************************************/
1933static int
1934ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1935{
1936 IPS_SG_LIST sg_list;
1937 uint32_t cmd_busaddr;
1938
1939 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1940 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1941 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1942 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1943 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1944 } else {
1945 pt->BasicStatus = 0x0B;
1946 pt->ExtendedStatus = 0x00;
1947 ips_free_flash_copperhead(ha);
1948 return IPS_FAILURE;
1949 }
1950 /* Save the S/G list pointer so it doesn't get clobbered */
1951 sg_list.list = scb->sg_list.list;
1952 cmd_busaddr = scb->scb_busaddr;
1953 /* copy in the CP */
1954 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1955 /* FIX stuff that might be wrong */
1956 scb->sg_list.list = sg_list.list;
1957 scb->scb_busaddr = cmd_busaddr;
1958 scb->bus = scb->scsi_cmd->device->channel;
1959 scb->target_id = scb->scsi_cmd->device->id;
1960 scb->lun = scb->scsi_cmd->device->lun;
1961 scb->sg_len = 0;
1962 scb->data_len = 0;
1963 scb->flags = 0;
1964 scb->op_code = 0;
1965 scb->callback = ipsintr_done;
1966 scb->timeout = ips_cmd_timeout;
1967
1968 scb->data_len = ha->flash_datasize;
1969 scb->data_busaddr =
1970 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1971 IPS_DMA_DIR(scb));
1972 scb->flags |= IPS_SCB_MAP_SINGLE;
1973 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1974 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1975 if (pt->TimeOut)
1976 scb->timeout = pt->TimeOut;
1977 scb->scsi_cmd->result = DID_OK << 16;
1978 return IPS_SUCCESS;
1979}
1980
1981/****************************************************************************/
1982/* Routine Name: ips_free_flash_copperhead */
1983/* Routine Description: */
1984/* release the memory resources used to hold the flash image */
1985/****************************************************************************/
1986static void
1987ips_free_flash_copperhead(ips_ha_t * ha)
1988{
1989 if (ha->flash_data == ips_FlashData)
1990 test_and_clear_bit(0, &ips_FlashDataInUse);
1991 else if (ha->flash_data)
1992 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1993 ha->flash_busaddr);
1994 ha->flash_data = NULL;
1995}
1996
1997/****************************************************************************/
1998/* */
1999/* Routine Name: ips_usrcmd */
2000/* */
2001/* Routine Description: */
2002/* */
2003/* Process a user command and make it ready to send */
2004/* */
2005/****************************************************************************/
2006static int
2007ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2008{
2009 IPS_SG_LIST sg_list;
2010 uint32_t cmd_busaddr;
2011
2012 METHOD_TRACE("ips_usrcmd", 1);
2013
2014 if ((!scb) || (!pt) || (!ha))
2015 return (0);
2016
2017 /* Save the S/G list pointer so it doesn't get clobbered */
2018 sg_list.list = scb->sg_list.list;
2019 cmd_busaddr = scb->scb_busaddr;
2020 /* copy in the CP */
2021 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
2022 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
2023
2024 /* FIX stuff that might be wrong */
2025 scb->sg_list.list = sg_list.list;
2026 scb->scb_busaddr = cmd_busaddr;
2027 scb->bus = scb->scsi_cmd->device->channel;
2028 scb->target_id = scb->scsi_cmd->device->id;
2029 scb->lun = scb->scsi_cmd->device->lun;
2030 scb->sg_len = 0;
2031 scb->data_len = 0;
2032 scb->flags = 0;
2033 scb->op_code = 0;
2034 scb->callback = ipsintr_done;
2035 scb->timeout = ips_cmd_timeout;
2036 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2037
2038 /* we don't support DCDB/READ/WRITE Scatter Gather */
2039 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
2040 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
2041 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
2042 return (0);
2043
2044 if (pt->CmdBSize) {
2045 scb->data_len = pt->CmdBSize;
2046 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2047 } else {
2048 scb->data_busaddr = 0L;
2049 }
2050
2051 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2052 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
2053 (unsigned long) &scb->
2054 dcdb -
2055 (unsigned long) scb);
2056
2057 if (pt->CmdBSize) {
2058 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2059 scb->dcdb.buffer_pointer =
2060 cpu_to_le32(scb->data_busaddr);
2061 else
2062 scb->cmd.basic_io.sg_addr =
2063 cpu_to_le32(scb->data_busaddr);
2064 }
2065
2066 /* set timeouts */
2067 if (pt->TimeOut) {
2068 scb->timeout = pt->TimeOut;
2069
2070 if (pt->TimeOut <= 10)
2071 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
2072 else if (pt->TimeOut <= 60)
2073 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
2074 else
2075 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
2076 }
2077
2078 /* assume success */
2079 scb->scsi_cmd->result = DID_OK << 16;
2080
2081 /* success */
2082 return (1);
2083}
2084
2085/****************************************************************************/
2086/* */
2087/* Routine Name: ips_cleanup_passthru */
2088/* */
2089/* Routine Description: */
2090/* */
2091/* Cleanup after a passthru command */
2092/* */
2093/****************************************************************************/
2094static void
2095ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2096{
2097 ips_passthru_t *pt;
2098
2099 METHOD_TRACE("ips_cleanup_passthru", 1);
2100
2101 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
2102 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2103 ips_name, ha->host_num);
2104
2105 return;
2106 }
2107 pt = (ips_passthru_t *) ha->ioctl_data;
2108
2109 /* Copy data back to the user */
2110 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2111 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2112
2113 pt->BasicStatus = scb->basic_status;
2114 pt->ExtendedStatus = scb->extended_status;
2115 pt->AdapterType = ha->ad_type;
2116
2117 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2118 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2119 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2120 ips_free_flash_copperhead(ha);
2121
2122 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2123}
2124
2125/****************************************************************************/
2126/* */
2127/* Routine Name: ips_host_info */
2128/* */
2129/* Routine Description: */
2130/* */
2131/* The passthru interface for the driver */
2132/* */
2133/****************************************************************************/
2134static int
2135ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2136{
2137 IPS_INFOSTR info;
2138
2139 METHOD_TRACE("ips_host_info", 1);
2140
2141 info.buffer = ptr;
2142 info.length = len;
2143 info.offset = offset;
2144 info.pos = 0;
2145 info.localpos = 0;
2146
2147 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2148
2149 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2150 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2151 copy_info(&info, "\tController Type : %s\n",
2152 ips_adapter_name[ha->ad_type - 1]);
2153 else
2154 copy_info(&info,
2155 "\tController Type : Unknown\n");
2156
2157 if (ha->io_addr)
2158 copy_info(&info,
2159 "\tIO region : 0x%lx (%d bytes)\n",
2160 ha->io_addr, ha->io_len);
2161
2162 if (ha->mem_addr) {
2163 copy_info(&info,
2164 "\tMemory region : 0x%lx (%d bytes)\n",
2165 ha->mem_addr, ha->mem_len);
2166 copy_info(&info,
2167 "\tShared memory address : 0x%lx\n",
2168 ha->mem_ptr);
2169 }
2170
2171 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2172
2173 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2174 /* That keeps everything happy for "text" operations on the proc file. */
2175
2176 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2177 if (ha->nvram->bios_low[3] == 0) {
2178 copy_info(&info,
2179 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2180 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2181 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2182 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2183 ha->nvram->bios_low[2]);
2184
2185 } else {
2186 copy_info(&info,
2187 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2188 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2189 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2190 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2191 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2192 }
2193
2194 }
2195
2196 if (ha->enq->CodeBlkVersion[7] == 0) {
2197 copy_info(&info,
2198 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2199 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2200 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2201 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2202 ha->enq->CodeBlkVersion[6]);
2203 } else {
2204 copy_info(&info,
2205 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2206 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2207 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2208 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2209 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2210 }
2211
2212 if (ha->enq->BootBlkVersion[7] == 0) {
2213 copy_info(&info,
2214 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2215 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2216 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2217 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2218 ha->enq->BootBlkVersion[6]);
2219 } else {
2220 copy_info(&info,
2221 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2222 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2223 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2224 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2225 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2226 }
2227
2228 copy_info(&info, "\tDriver Version : %s%s\n",
2229 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2230
2231 copy_info(&info, "\tDriver Build : %d\n",
2232 IPS_BUILD_IDENT);
2233
2234 copy_info(&info, "\tMax Physical Devices : %d\n",
2235 ha->enq->ucMaxPhysicalDevices);
2236 copy_info(&info, "\tMax Active Commands : %d\n",
2237 ha->max_cmds);
2238 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2239 ha->scb_waitlist.count);
2240 copy_info(&info, "\tCurrent Active Commands : %d\n",
2241 ha->scb_activelist.count - ha->num_ioctl);
2242 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2243 ha->copp_waitlist.count);
2244 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2245 ha->num_ioctl);
2246
2247 copy_info(&info, "\n");
2248
2249 return (info.localpos);
2250}
2251
2252/****************************************************************************/
2253/* */
2254/* Routine Name: copy_mem_info */
2255/* */
2256/* Routine Description: */
2257/* */
2258/* Copy data into an IPS_INFOSTR structure */
2259/* */
2260/****************************************************************************/
2261static void
2262copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2263{
2264 METHOD_TRACE("copy_mem_info", 1);
2265
2266 if (info->pos + len < info->offset) {
2267 info->pos += len;
2268 return;
2269 }
2270
2271 if (info->pos < info->offset) {
2272 data += (info->offset - info->pos);
2273 len -= (info->offset - info->pos);
2274 info->pos += (info->offset - info->pos);
2275 }
2276
2277 if (info->localpos + len > info->length)
2278 len = info->length - info->localpos;
2279
2280 if (len > 0) {
2281 memcpy(info->buffer + info->localpos, data, len);
2282 info->pos += len;
2283 info->localpos += len;
2284 }
2285}
2286
2287/****************************************************************************/
2288/* */
2289/* Routine Name: copy_info */
2290/* */
2291/* Routine Description: */
2292/* */
2293/* printf style wrapper for an info structure */
2294/* */
2295/****************************************************************************/
2296static int
2297copy_info(IPS_INFOSTR * info, char *fmt, ...)
2298{
2299 va_list args;
2300 char buf[128];
2301 int len;
2302
2303 METHOD_TRACE("copy_info", 1);
2304
2305 va_start(args, fmt);
2306 len = vsprintf(buf, fmt, args);
2307 va_end(args);
2308
2309 copy_mem_info(info, buf, len);
2310
2311 return (len);
2312}
2313
2314/****************************************************************************/
2315/* */
2316/* Routine Name: ips_identify_controller */
2317/* */
2318/* Routine Description: */
2319/* */
2320/* Identify this controller */
2321/* */
2322/****************************************************************************/
2323static void
2324ips_identify_controller(ips_ha_t * ha)
2325{
2326 METHOD_TRACE("ips_identify_controller", 1);
2327
2328 switch (ha->device_id) {
2329 case IPS_DEVICEID_COPPERHEAD:
2330 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2331 ha->ad_type = IPS_ADTYPE_SERVERAID;
2332 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2333 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2334 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2335 ha->ad_type = IPS_ADTYPE_NAVAJO;
2336 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2337 && (ha->slot_num == 0)) {
2338 ha->ad_type = IPS_ADTYPE_KIOWA;
2339 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2340 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2341 if (ha->enq->ucMaxPhysicalDevices == 15)
2342 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2343 else
2344 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2345 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2346 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2347 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2348 }
2349 break;
2350
2351 case IPS_DEVICEID_MORPHEUS:
2352 switch (ha->subdevice_id) {
2353 case IPS_SUBDEVICEID_4L:
2354 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2355 break;
2356
2357 case IPS_SUBDEVICEID_4M:
2358 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2359 break;
2360
2361 case IPS_SUBDEVICEID_4MX:
2362 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2363 break;
2364
2365 case IPS_SUBDEVICEID_4LX:
2366 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2367 break;
2368
2369 case IPS_SUBDEVICEID_5I2:
2370 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2371 break;
2372
2373 case IPS_SUBDEVICEID_5I1:
2374 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2375 break;
2376 }
2377
2378 break;
2379
2380 case IPS_DEVICEID_MARCO:
2381 switch (ha->subdevice_id) {
2382 case IPS_SUBDEVICEID_6M:
2383 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2384 break;
2385 case IPS_SUBDEVICEID_6I:
2386 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2387 break;
2388 case IPS_SUBDEVICEID_7k:
2389 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2390 break;
2391 case IPS_SUBDEVICEID_7M:
2392 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2393 break;
2394 }
2395 break;
2396 }
2397}
2398
2399/****************************************************************************/
2400/* */
2401/* Routine Name: ips_get_bios_version */
2402/* */
2403/* Routine Description: */
2404/* */
2405/* Get the BIOS revision number */
2406/* */
2407/****************************************************************************/
2408static void
2409ips_get_bios_version(ips_ha_t * ha, int intr)
2410{
2411 ips_scb_t *scb;
2412 int ret;
2413 uint8_t major;
2414 uint8_t minor;
2415 uint8_t subminor;
2416 uint8_t *buffer;
2417 char hexDigits[] =
2418 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2419 'D', 'E', 'F' };
2420
2421 METHOD_TRACE("ips_get_bios_version", 1);
2422
2423 major = 0;
2424 minor = 0;
2425
2426 strncpy(ha->bios_version, " ?", 8);
2427
2428 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2429 if (IPS_USE_MEMIO(ha)) {
2430 /* Memory Mapped I/O */
2431
2432 /* test 1st byte */
2433 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2434 if (ha->revision_id == IPS_REVID_TROMBONE64)
2435 udelay(25); /* 25 us */
2436
2437 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2438 return;
2439
2440 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2441 if (ha->revision_id == IPS_REVID_TROMBONE64)
2442 udelay(25); /* 25 us */
2443
2444 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2445 return;
2446
2447 /* Get Major version */
2448 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2449 if (ha->revision_id == IPS_REVID_TROMBONE64)
2450 udelay(25); /* 25 us */
2451
2452 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2453
2454 /* Get Minor version */
2455 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2456 if (ha->revision_id == IPS_REVID_TROMBONE64)
2457 udelay(25); /* 25 us */
2458 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2459
2460 /* Get SubMinor version */
2461 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2462 if (ha->revision_id == IPS_REVID_TROMBONE64)
2463 udelay(25); /* 25 us */
2464 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2465
2466 } else {
2467 /* Programmed I/O */
2468
2469 /* test 1st byte */
2470 outl(0, ha->io_addr + IPS_REG_FLAP);
2471 if (ha->revision_id == IPS_REVID_TROMBONE64)
2472 udelay(25); /* 25 us */
2473
2474 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2475 return;
2476
2477 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2478 if (ha->revision_id == IPS_REVID_TROMBONE64)
2479 udelay(25); /* 25 us */
2480
2481 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2482 return;
2483
2484 /* Get Major version */
2485 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2486 if (ha->revision_id == IPS_REVID_TROMBONE64)
2487 udelay(25); /* 25 us */
2488
2489 major = inb(ha->io_addr + IPS_REG_FLDP);
2490
2491 /* Get Minor version */
2492 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2493 if (ha->revision_id == IPS_REVID_TROMBONE64)
2494 udelay(25); /* 25 us */
2495
2496 minor = inb(ha->io_addr + IPS_REG_FLDP);
2497
2498 /* Get SubMinor version */
2499 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2500 if (ha->revision_id == IPS_REVID_TROMBONE64)
2501 udelay(25); /* 25 us */
2502
2503 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2504
2505 }
2506 } else {
2507 /* Morpheus Family - Send Command to the card */
2508
2509 buffer = ha->ioctl_data;
2510
2511 memset(buffer, 0, 0x1000);
2512
2513 scb = &ha->scbs[ha->max_cmds - 1];
2514
2515 ips_init_scb(ha, scb);
2516
2517 scb->timeout = ips_cmd_timeout;
2518 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2519
2520 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2521 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2522 scb->cmd.flashfw.type = 1;
2523 scb->cmd.flashfw.direction = 0;
2524 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2525 scb->cmd.flashfw.total_packets = 1;
2526 scb->cmd.flashfw.packet_num = 0;
2527 scb->data_len = 0x1000;
2528 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2529
2530 /* issue the command */
2531 if (((ret =
2532 ips_send_wait(ha, scb, ips_cmd_timeout,
2533 intr)) == IPS_FAILURE)
2534 || (ret == IPS_SUCCESS_IMM)
2535 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2536 /* Error occurred */
2537
2538 return;
2539 }
2540
2541 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2542 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2543 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2544 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2545 } else {
2546 return;
2547 }
2548 }
2549
2550 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2551 ha->bios_version[1] = '.';
2552 ha->bios_version[2] = hexDigits[major & 0x0F];
2553 ha->bios_version[3] = hexDigits[subminor];
2554 ha->bios_version[4] = '.';
2555 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2556 ha->bios_version[6] = hexDigits[minor & 0x0F];
2557 ha->bios_version[7] = 0;
2558}
2559
2560/****************************************************************************/
2561/* */
2562/* Routine Name: ips_hainit */
2563/* */
2564/* Routine Description: */
2565/* */
2566/* Initialize the controller */
2567/* */
2568/* NOTE: Assumes to be called from with a lock */
2569/* */
2570/****************************************************************************/
2571static int
2572ips_hainit(ips_ha_t * ha)
2573{
2574 int i;
2575 struct timeval tv;
2576
2577 METHOD_TRACE("ips_hainit", 1);
2578
2579 if (!ha)
2580 return (0);
2581
2582 if (ha->func.statinit)
2583 (*ha->func.statinit) (ha);
2584
2585 if (ha->func.enableint)
2586 (*ha->func.enableint) (ha);
2587
2588 /* Send FFDC */
2589 ha->reset_count = 1;
2590 do_gettimeofday(&tv);
2591 ha->last_ffdc = tv.tv_sec;
2592 ips_ffdc_reset(ha, IPS_INTR_IORL);
2593
2594 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2595 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2596 "unable to read config from controller.\n");
2597
2598 return (0);
2599 }
2600 /* end if */
2601 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2602 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2603 "unable to read controller status.\n");
2604
2605 return (0);
2606 }
2607
2608 /* Identify this controller */
2609 ips_identify_controller(ha);
2610
2611 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2612 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2613 "unable to read subsystem parameters.\n");
2614
2615 return (0);
2616 }
2617
2618 /* write nvram user page 5 */
2619 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2620 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2621 "unable to write driver info to controller.\n");
2622
2623 return (0);
2624 }
2625
2626 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2627 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2628 ips_clear_adapter(ha, IPS_INTR_IORL);
2629
2630 /* set limits on SID, LUN, BUS */
2631 ha->ntargets = IPS_MAX_TARGETS + 1;
2632 ha->nlun = 1;
2633 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2634
2635 switch (ha->conf->logical_drive[0].ucStripeSize) {
2636 case 4:
2637 ha->max_xfer = 0x10000;
2638 break;
2639
2640 case 5:
2641 ha->max_xfer = 0x20000;
2642 break;
2643
2644 case 6:
2645 ha->max_xfer = 0x40000;
2646 break;
2647
2648 case 7:
2649 default:
2650 ha->max_xfer = 0x80000;
2651 break;
2652 }
2653
2654 /* setup max concurrent commands */
2655 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2656 /* Use the new method */
2657 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2658 } else {
2659 /* use the old method */
2660 switch (ha->conf->logical_drive[0].ucStripeSize) {
2661 case 4:
2662 ha->max_cmds = 32;
2663 break;
2664
2665 case 5:
2666 ha->max_cmds = 16;
2667 break;
2668
2669 case 6:
2670 ha->max_cmds = 8;
2671 break;
2672
2673 case 7:
2674 default:
2675 ha->max_cmds = 4;
2676 break;
2677 }
2678 }
2679
2680 /* Limit the Active Commands on a Lite Adapter */
2681 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2682 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2683 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2684 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2685 ha->max_cmds = MaxLiteCmds;
2686 }
2687
2688 /* set controller IDs */
2689 ha->ha_id[0] = IPS_ADAPTER_ID;
2690 for (i = 1; i < ha->nbus; i++) {
2691 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2692 ha->dcdb_active[i - 1] = 0;
2693 }
2694
2695 return (1);
2696}
2697
2698/****************************************************************************/
2699/* */
2700/* Routine Name: ips_next */
2701/* */
2702/* Routine Description: */
2703/* */
2704/* Take the next command off the queue and send it to the controller */
2705/* */
2706/****************************************************************************/
2707static void
2708ips_next(ips_ha_t * ha, int intr)
2709{
2710 ips_scb_t *scb;
2711 Scsi_Cmnd *SC;
2712 Scsi_Cmnd *p;
2713 Scsi_Cmnd *q;
2714 ips_copp_wait_item_t *item;
2715 int ret;
2716 unsigned long cpu_flags = 0;
2717 struct Scsi_Host *host;
2718 METHOD_TRACE("ips_next", 1);
2719
2720 if (!ha)
2721 return;
2722 host = ips_sh[ha->host_num];
2723 /*
2724 * Block access to the queue function so
2725 * this command won't time out
2726 */
2727 if (intr == IPS_INTR_ON)
2728 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2729
2730 if ((ha->subsys->param[3] & 0x300000)
2731 && (ha->scb_activelist.count == 0)) {
2732 struct timeval tv;
2733
2734 do_gettimeofday(&tv);
2735
2736 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2737 ha->last_ffdc = tv.tv_sec;
2738 ips_ffdc_time(ha);
2739 }
2740 }
2741
2742 /*
2743 * Send passthru commands
2744 * These have priority over normal I/O
2745 * but shouldn't affect performance too much
2746 * since we limit the number that can be active
2747 * on the card at any one time
2748 */
2749 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2750 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2751
2752 item = ips_removeq_copp_head(&ha->copp_waitlist);
2753 ha->num_ioctl++;
2754 if (intr == IPS_INTR_ON)
2755 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2756 scb->scsi_cmd = item->scsi_cmd;
2757 kfree(item);
2758
2759 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2760
2761 if (intr == IPS_INTR_ON)
2762 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2763 switch (ret) {
2764 case IPS_FAILURE:
2765 if (scb->scsi_cmd) {
2766 scb->scsi_cmd->result = DID_ERROR << 16;
2767 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2768 }
2769
2770 ips_freescb(ha, scb);
2771 break;
2772 case IPS_SUCCESS_IMM:
2773 if (scb->scsi_cmd) {
2774 scb->scsi_cmd->result = DID_OK << 16;
2775 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2776 }
2777
2778 ips_freescb(ha, scb);
2779 break;
2780 default:
2781 break;
2782 } /* end case */
2783
2784 if (ret != IPS_SUCCESS) {
2785 ha->num_ioctl--;
2786 continue;
2787 }
2788
2789 ret = ips_send_cmd(ha, scb);
2790
2791 if (ret == IPS_SUCCESS)
2792 ips_putq_scb_head(&ha->scb_activelist, scb);
2793 else
2794 ha->num_ioctl--;
2795
2796 switch (ret) {
2797 case IPS_FAILURE:
2798 if (scb->scsi_cmd) {
2799 scb->scsi_cmd->result = DID_ERROR << 16;
2800 }
2801
2802 ips_freescb(ha, scb);
2803 break;
2804 case IPS_SUCCESS_IMM:
2805 ips_freescb(ha, scb);
2806 break;
2807 default:
2808 break;
2809 } /* end case */
2810
2811 }
2812
2813 /*
2814 * Send "Normal" I/O commands
2815 */
2816
2817 p = ha->scb_waitlist.head;
2818 while ((p) && (scb = ips_getscb(ha))) {
2819 if ((p->device->channel > 0)
2820 && (ha->
2821 dcdb_active[p->device->channel -
2822 1] & (1 << p->device->id))) {
2823 ips_freescb(ha, scb);
2824 p = (Scsi_Cmnd *) p->host_scribble;
2825 continue;
2826 }
2827
2828 q = p;
2829 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2830
2831 if (intr == IPS_INTR_ON)
2832 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
2833
2834 SC->result = DID_OK;
2835 SC->host_scribble = NULL;
2836
2837 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2838
2839 scb->target_id = SC->device->id;
2840 scb->lun = SC->device->lun;
2841 scb->bus = SC->device->channel;
2842 scb->scsi_cmd = SC;
2843 scb->breakup = 0;
2844 scb->data_len = 0;
2845 scb->callback = ipsintr_done;
2846 scb->timeout = ips_cmd_timeout;
2847 memset(&scb->cmd, 0, 16);
2848
2849 /* copy in the CDB */
2850 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2851
2852 /* Now handle the data buffer */
2853 if (SC->use_sg) {
2854 struct scatterlist *sg;
2855 int i;
2856
2857 sg = SC->request_buffer;
2858 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
be7db055 2859 SC->sc_data_direction);
1da177e4
LT		 2860 scb->flags |= IPS_SCB_MAP_SG;
2861 for (i = 0; i < scb->sg_count; i++) {
2862 if (ips_fill_scb_sg_single
2863 (ha, sg_dma_address(&sg[i]), scb, i,
2864 sg_dma_len(&sg[i])) < 0)
2865 break;
2866 }
2867 scb->dcdb.transfer_length = scb->data_len;
2868 } else {
2869 if (SC->request_bufflen) {
2870 scb->data_busaddr =
2871 pci_map_single(ha->pcidev,
2872 SC->request_buffer,
2873 SC->request_bufflen,
be7db055 2874 SC->sc_data_direction);
1da177e4
LT		 2875 scb->flags |= IPS_SCB_MAP_SINGLE;
2876 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2877 scb, 0,
2878 SC->request_bufflen);
2879 scb->dcdb.transfer_length = scb->data_len;
2880 } else {
2881 scb->data_busaddr = 0L;
2882 scb->sg_len = 0;
2883 scb->data_len = 0;
2884 scb->dcdb.transfer_length = 0;
2885 }
2886
2887 }
2888
2889 scb->dcdb.cmd_attribute =
2890 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2891
2892 /* Allow a WRITE BUFFER Command to Have no Data */
2893 /* This is Used by Tape Flash Utilites */
2894 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
2895 scb->dcdb.cmd_attribute = 0;
2896
2897 if (!(scb->dcdb.cmd_attribute & 0x3))
2898 scb->dcdb.transfer_length = 0;
2899
2900 if (scb->data_len >= IPS_MAX_XFER) {
2901 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2902 scb->dcdb.transfer_length = 0;
2903 }
2904 if (intr == IPS_INTR_ON)
2905 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2906
2907 ret = ips_send_cmd(ha, scb);
2908
2909 switch (ret) {
2910 case IPS_SUCCESS:
2911 ips_putq_scb_head(&ha->scb_activelist, scb);
2912 break;
2913 case IPS_FAILURE:
2914 if (scb->scsi_cmd) {
2915 scb->scsi_cmd->result = DID_ERROR << 16;
2916 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2917 }
2918
2919 if (scb->bus)
2920 ha->dcdb_active[scb->bus - 1] &=
2921 ~(1 << scb->target_id);
2922
2923 ips_freescb(ha, scb);
2924 break;
2925 case IPS_SUCCESS_IMM:
2926 if (scb->scsi_cmd)
2927 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2928
2929 if (scb->bus)
2930 ha->dcdb_active[scb->bus - 1] &=
2931 ~(1 << scb->target_id);
2932
2933 ips_freescb(ha, scb);
2934 break;
2935 default:
2936 break;
2937 } /* end case */
2938
2939 p = (Scsi_Cmnd *) p->host_scribble;
2940
2941 } /* end while */
2942
2943 if (intr == IPS_INTR_ON)
2944 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2945}
2946
2947/****************************************************************************/
2948/* */
2949/* Routine Name: ips_putq_scb_head */
2950/* */
2951/* Routine Description: */
2952/* */
2953/* Add an item to the head of the queue */
2954/* */
2955/* ASSUMED to be called from within the HA lock */
2956/* */
2957/****************************************************************************/
2958static void
2959ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2960{
2961 METHOD_TRACE("ips_putq_scb_head", 1);
2962
2963 if (!item)
2964 return;
2965
2966 item->q_next = queue->head;
2967 queue->head = item;
2968
2969 if (!queue->tail)
2970 queue->tail = item;
2971
2972 queue->count++;
2973}
2974
2975/****************************************************************************/
2976/* */
2977/* Routine Name: ips_removeq_scb_head */
2978/* */
2979/* Routine Description: */
2980/* */
2981/* Remove the head of the queue */
2982/* */
2983/* ASSUMED to be called from within the HA lock */
2984/* */
2985/****************************************************************************/
2986static ips_scb_t *
2987ips_removeq_scb_head(ips_scb_queue_t * queue)
2988{
2989 ips_scb_t *item;
2990
2991 METHOD_TRACE("ips_removeq_scb_head", 1);
2992
2993 item = queue->head;
2994
2995 if (!item) {
2996 return (NULL);
2997 }
2998
2999 queue->head = item->q_next;
3000 item->q_next = NULL;
3001
3002 if (queue->tail == item)
3003 queue->tail = NULL;
3004
3005 queue->count--;
3006
3007 return (item);
3008}
3009
3010/****************************************************************************/
3011/* */
3012/* Routine Name: ips_removeq_scb */
3013/* */
3014/* Routine Description: */
3015/* */
3016/* Remove an item from a queue */
3017/* */
3018/* ASSUMED to be called from within the HA lock */
3019/* */
3020/****************************************************************************/
3021static ips_scb_t *
3022ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
3023{
3024 ips_scb_t *p;
3025
3026 METHOD_TRACE("ips_removeq_scb", 1);
3027
3028 if (!item)
3029 return (NULL);
3030
3031 if (item == queue->head) {
3032 return (ips_removeq_scb_head(queue));
3033 }
3034
3035 p = queue->head;
3036
3037 while ((p) && (item != p->q_next))
3038 p = p->q_next;
3039
3040 if (p) {
3041 /* found a match */
3042 p->q_next = item->q_next;
3043
3044 if (!item->q_next)
3045 queue->tail = p;
3046
3047 item->q_next = NULL;
3048 queue->count--;
3049
3050 return (item);
3051 }
3052
3053 return (NULL);
3054}
3055
3056/****************************************************************************/
3057/* */
3058/* Routine Name: ips_putq_wait_tail */
3059/* */
3060/* Routine Description: */
3061/* */
3062/* Add an item to the tail of the queue */
3063/* */
3064/* ASSUMED to be called from within the HA lock */
3065/* */
3066/****************************************************************************/
3067static void
3068ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3069{
3070 METHOD_TRACE("ips_putq_wait_tail", 1);
3071
3072 if (!item)
3073 return;
3074
3075 item->host_scribble = NULL;
3076
3077 if (queue->tail)
3078 queue->tail->host_scribble = (char *) item;
3079
3080 queue->tail = item;
3081
3082 if (!queue->head)
3083 queue->head = item;
3084
3085 queue->count++;
3086}
3087
3088/****************************************************************************/
3089/* */
3090/* Routine Name: ips_removeq_wait_head */
3091/* */
3092/* Routine Description: */
3093/* */
3094/* Remove the head of the queue */
3095/* */
3096/* ASSUMED to be called from within the HA lock */
3097/* */
3098/****************************************************************************/
3099static Scsi_Cmnd *
3100ips_removeq_wait_head(ips_wait_queue_t * queue)
3101{
3102 Scsi_Cmnd *item;
3103
3104 METHOD_TRACE("ips_removeq_wait_head", 1);
3105
3106 item = queue->head;
3107
3108 if (!item) {
3109 return (NULL);
3110 }
3111
3112 queue->head = (Scsi_Cmnd *) item->host_scribble;
3113 item->host_scribble = NULL;
3114
3115 if (queue->tail == item)
3116 queue->tail = NULL;
3117
3118 queue->count--;
3119
3120 return (item);
3121}
3122
3123/****************************************************************************/
3124/* */
3125/* Routine Name: ips_removeq_wait */
3126/* */
3127/* Routine Description: */
3128/* */
3129/* Remove an item from a queue */
3130/* */
3131/* ASSUMED to be called from within the HA lock */
3132/* */
3133/****************************************************************************/
3134static Scsi_Cmnd *
3135ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3136{
3137 Scsi_Cmnd *p;
3138
3139 METHOD_TRACE("ips_removeq_wait", 1);
3140
3141 if (!item)
3142 return (NULL);
3143
3144 if (item == queue->head) {
3145 return (ips_removeq_wait_head(queue));
3146 }
3147
3148 p = queue->head;
3149
3150 while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
3151 p = (Scsi_Cmnd *) p->host_scribble;
3152
3153 if (p) {
3154 /* found a match */
3155 p->host_scribble = item->host_scribble;
3156
3157 if (!item->host_scribble)
3158 queue->tail = p;
3159
3160 item->host_scribble = NULL;
3161 queue->count--;
3162
3163 return (item);
3164 }
3165
3166 return (NULL);
3167}
3168
3169/****************************************************************************/
3170/* */
3171/* Routine Name: ips_putq_copp_tail */
3172/* */
3173/* Routine Description: */
3174/* */
3175/* Add an item to the tail of the queue */
3176/* */
3177/* ASSUMED to be called from within the HA lock */
3178/* */
3179/****************************************************************************/
3180static void
3181ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3182{
3183 METHOD_TRACE("ips_putq_copp_tail", 1);
3184
3185 if (!item)
3186 return;
3187
3188 item->next = NULL;
3189
3190 if (queue->tail)
3191 queue->tail->next = item;
3192
3193 queue->tail = item;
3194
3195 if (!queue->head)
3196 queue->head = item;
3197
3198 queue->count++;
3199}
3200
3201/****************************************************************************/
3202/* */
3203/* Routine Name: ips_removeq_copp_head */
3204/* */
3205/* Routine Description: */
3206/* */
3207/* Remove the head of the queue */
3208/* */
3209/* ASSUMED to be called from within the HA lock */
3210/* */
3211/****************************************************************************/
3212static ips_copp_wait_item_t *
3213ips_removeq_copp_head(ips_copp_queue_t * queue)
3214{
3215 ips_copp_wait_item_t *item;
3216
3217 METHOD_TRACE("ips_removeq_copp_head", 1);
3218
3219 item = queue->head;
3220
3221 if (!item) {
3222 return (NULL);
3223 }
3224
3225 queue->head = item->next;
3226 item->next = NULL;
3227
3228 if (queue->tail == item)
3229 queue->tail = NULL;
3230
3231 queue->count--;
3232
3233 return (item);
3234}
3235
3236/****************************************************************************/
3237/* */
3238/* Routine Name: ips_removeq_copp */
3239/* */
3240/* Routine Description: */
3241/* */
3242/* Remove an item from a queue */
3243/* */
3244/* ASSUMED to be called from within the HA lock */
3245/* */
3246/****************************************************************************/
3247static ips_copp_wait_item_t *
3248ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3249{
3250 ips_copp_wait_item_t *p;
3251
3252 METHOD_TRACE("ips_removeq_copp", 1);
3253
3254 if (!item)
3255 return (NULL);
3256
3257 if (item == queue->head) {
3258 return (ips_removeq_copp_head(queue));
3259 }
3260
3261 p = queue->head;
3262
3263 while ((p) && (item != p->next))
3264 p = p->next;
3265
3266 if (p) {
3267 /* found a match */
3268 p->next = item->next;
3269
3270 if (!item->next)
3271 queue->tail = p;
3272
3273 item->next = NULL;
3274 queue->count--;
3275
3276 return (item);
3277 }
3278
3279 return (NULL);
3280}
3281
3282/****************************************************************************/
3283/* */
3284/* Routine Name: ipsintr_blocking */
3285/* */
3286/* Routine Description: */
3287/* */
3288/* Finalize an interrupt for internal commands */
3289/* */
3290/****************************************************************************/
3291static void
3292ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3293{
3294 METHOD_TRACE("ipsintr_blocking", 2);
3295
3296 ips_freescb(ha, scb);
3297 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3298 ha->waitflag = FALSE;
3299
3300 return;
3301 }
3302}
3303
3304/****************************************************************************/
3305/* */
3306/* Routine Name: ipsintr_done */
3307/* */
3308/* Routine Description: */
3309/* */
3310/* Finalize an interrupt for non-internal commands */
3311/* */
3312/****************************************************************************/
3313static void
3314ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3315{
3316 METHOD_TRACE("ipsintr_done", 2);
3317
3318 if (!scb) {
3319 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3320 "Spurious interrupt; scb NULL.\n");
3321
3322 return;
3323 }
3324
3325 if (scb->scsi_cmd == NULL) {
3326 /* unexpected interrupt */
3327 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3328 "Spurious interrupt; scsi_cmd not set.\n");
3329
3330 return;
3331 }
3332
3333 ips_done(ha, scb);
3334}
3335
3336/****************************************************************************/
3337/* */
3338/* Routine Name: ips_done */
3339/* */
3340/* Routine Description: */
3341/* */
3342/* Do housekeeping on completed commands */
3343/* ASSUMED to be called form within the request lock */
3344/****************************************************************************/
3345static void
3346ips_done(ips_ha_t * ha, ips_scb_t * scb)
3347{
3348 int ret;
3349
3350 METHOD_TRACE("ips_done", 1);
3351
3352 if (!scb)
3353 return;
3354
3355 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3356 ips_cleanup_passthru(ha, scb);
3357 ha->num_ioctl--;
3358 } else {
3359 /*
3360 * Check to see if this command had too much
3361 * data and had to be broke up. If so, queue
3362 * the rest of the data and continue.
3363 */
3364 if ((scb->breakup) || (scb->sg_break)) {
3365 /* we had a data breakup */
3366 scb->data_len = 0;
3367
3368 if (scb->sg_count) {
3369 /* S/G request */
3370 struct scatterlist *sg;
3371 int ips_sg_index = 0;
3372 int sg_dma_index;
3373
3374 sg = scb->scsi_cmd->request_buffer;
3375
3376 /* Spin forward to last dma chunk */
3377 sg_dma_index = scb->breakup;
3378
3379 /* Take care of possible partial on last chunk */
3380 ips_fill_scb_sg_single(ha,
3381 sg_dma_address(&sg
3382 [sg_dma_index]),
3383 scb, ips_sg_index++,
3384 sg_dma_len(&sg
3385 [sg_dma_index]));
3386
3387 for (; sg_dma_index < scb->sg_count;
3388 sg_dma_index++) {
3389 if (ips_fill_scb_sg_single
3390 (ha,
3391 sg_dma_address(&sg[sg_dma_index]),
3392 scb, ips_sg_index++,
3393 sg_dma_len(&sg[sg_dma_index])) < 0)
3394 break;
3395
3396 }
3397
3398 } else {
3399 /* Non S/G Request */
3400 (void) ips_fill_scb_sg_single(ha,
3401 scb->
3402 data_busaddr +
3403 (scb->sg_break *
3404 ha->max_xfer),
3405 scb, 0,
3406 scb->scsi_cmd->
3407 request_bufflen -
3408 (scb->sg_break *
3409 ha->max_xfer));
3410 }
3411
3412 scb->dcdb.transfer_length = scb->data_len;
3413 scb->dcdb.cmd_attribute |=
3414 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3415
3416 if (!(scb->dcdb.cmd_attribute & 0x3))
3417 scb->dcdb.transfer_length = 0;
3418
3419 if (scb->data_len >= IPS_MAX_XFER) {
3420 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3421 scb->dcdb.transfer_length = 0;
3422 }
3423
3424 ret = ips_send_cmd(ha, scb);
3425
3426 switch (ret) {
3427 case IPS_FAILURE:
3428 if (scb->scsi_cmd) {
3429 scb->scsi_cmd->result = DID_ERROR << 16;
3430 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3431 }
3432
3433 ips_freescb(ha, scb);
3434 break;
3435 case IPS_SUCCESS_IMM:
3436 if (scb->scsi_cmd) {
3437 scb->scsi_cmd->result = DID_ERROR << 16;
3438 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3439 }
3440
3441 ips_freescb(ha, scb);
3442 break;
3443 default:
3444 break;
3445 } /* end case */
3446
3447 return;
3448 }
3449 } /* end if passthru */
3450
3451 if (scb->bus) {
3452 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3453 }
3454
3455 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3456
3457 ips_freescb(ha, scb);
3458}
3459
3460/****************************************************************************/
3461/* */
3462/* Routine Name: ips_map_status */
3463/* */
3464/* Routine Description: */
3465/* */
3466/* Map Controller Error codes to Linux Error Codes */
3467/* */
3468/****************************************************************************/
3469static int
3470ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3471{
3472 int errcode;
3473 int device_error;
3474 uint32_t transfer_len;
3475 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3476
3477 METHOD_TRACE("ips_map_status", 1);
3478
3479 if (scb->bus) {
3480 DEBUG_VAR(2,
3481 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3482 ips_name, ha->host_num,
3483 scb->scsi_cmd->device->channel,
3484 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3485 scb->basic_status, scb->extended_status,
3486 scb->extended_status ==
3487 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3488 scb->extended_status ==
3489 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3490 scb->extended_status ==
3491 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3492 }
3493
3494 /* default driver error */
3495 errcode = DID_ERROR;
3496 device_error = 0;
3497
3498 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3499 case IPS_CMD_TIMEOUT:
3500 errcode = DID_TIME_OUT;
3501 break;
3502
3503 case IPS_INVAL_OPCO:
3504 case IPS_INVAL_CMD_BLK:
3505 case IPS_INVAL_PARM_BLK:
3506 case IPS_LD_ERROR:
3507 case IPS_CMD_CMPLT_WERROR:
3508 break;
3509
3510 case IPS_PHYS_DRV_ERROR:
3511 switch (scb->extended_status) {
3512 case IPS_ERR_SEL_TO:
3513 if (scb->bus)
3514 errcode = DID_NO_CONNECT;
3515
3516 break;
3517
3518 case IPS_ERR_OU_RUN:
3519 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3520 (scb->cmd.dcdb.op_code ==
3521 IPS_CMD_EXTENDED_DCDB_SG)) {
3522 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3523 transfer_len = tapeDCDB->transfer_length;
3524 } else {
3525 transfer_len =
3526 (uint32_t) scb->dcdb.transfer_length;
3527 }
3528
3529 if ((scb->bus) && (transfer_len < scb->data_len)) {
3530 /* Underrun - set default to no error */
3531 errcode = DID_OK;
3532
3533 /* Restrict access to physical DASD */
3534 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
3535 ((((char *) scb->scsi_cmd->
3536 buffer)[0] & 0x1f) == TYPE_DISK)) {
3537 /* underflow -- no error */
3538 /* restrict access to physical DASD */
3539 errcode = DID_TIME_OUT;
3540 break;
3541 }
3542 } else
3543 errcode = DID_ERROR;
3544
3545 break;
3546
3547 case IPS_ERR_RECOVERY:
3548 /* don't fail recovered errors */
3549 if (scb->bus)
3550 errcode = DID_OK;
3551
3552 break;
3553
3554 case IPS_ERR_HOST_RESET:
3555 case IPS_ERR_DEV_RESET:
3556 errcode = DID_RESET;
3557 break;
3558
3559 case IPS_ERR_CKCOND:
3560 if (scb->bus) {
3561 if ((scb->cmd.dcdb.op_code ==
3562 IPS_CMD_EXTENDED_DCDB)
3563 || (scb->cmd.dcdb.op_code ==
3564 IPS_CMD_EXTENDED_DCDB_SG)) {
3565 tapeDCDB =
3566 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3567 memcpy(scb->scsi_cmd->sense_buffer,
3568 tapeDCDB->sense_info,
3569 sizeof (scb->scsi_cmd->
3570 sense_buffer));
3571 } else {
3572 memcpy(scb->scsi_cmd->sense_buffer,
3573 scb->dcdb.sense_info,
3574 sizeof (scb->scsi_cmd->
3575 sense_buffer));
3576 }
3577 device_error = 2; /* check condition */
3578 }
3579
3580 errcode = DID_OK;
3581
3582 break;
3583
3584 default:
3585 errcode = DID_ERROR;
3586 break;
3587
3588 } /* end switch */
3589 } /* end switch */
3590
3591 scb->scsi_cmd->result = device_error | (errcode << 16);
3592
3593 return (1);
3594}
3595
3596/****************************************************************************/
3597/* */
3598/* Routine Name: ips_send_wait */
3599/* */
3600/* Routine Description: */
3601/* */
3602/* Send a command to the controller and wait for it to return */
3603/* */
3604/* The FFDC Time Stamp use this function for the callback, but doesn't */
3605/* actually need to wait. */
3606/****************************************************************************/
3607static int
3608ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3609{
3610 int ret;
3611
3612 METHOD_TRACE("ips_send_wait", 1);
3613
3614 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3615 ha->waitflag = TRUE;
3616 ha->cmd_in_progress = scb->cdb[0];
3617 }
3618 scb->callback = ipsintr_blocking;
3619 ret = ips_send_cmd(ha, scb);
3620
3621 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3622 return (ret);
3623
3624 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3625 ret = ips_wait(ha, timeout, intr);
3626
3627 return (ret);
3628}
3629
3630/****************************************************************************/
3631/* */
3632/* Routine Name: ips_scmd_buf_write */
3633/* */
3634/* Routine Description: */
3635/* Write data to Scsi_Cmnd request_buffer at proper offsets */
3636/****************************************************************************/
3637static void
3638ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
3639 int count)
3640{
3641 if (scmd->use_sg) {
3642 int i;
3643 unsigned int min_cnt, xfer_cnt;
3644 char *cdata = (char *) data;
3645 struct scatterlist *sg = scmd->request_buffer;
3646 for (i = 0, xfer_cnt = 0;
3647 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3648 if (!IPS_SG_ADDRESS(&sg[i]))
3649 return;
3650 min_cnt = min(count - xfer_cnt, sg[i].length);
3651 memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
3652 min_cnt);
3653 xfer_cnt += min_cnt;
3654 }
3655
3656 } else {
3657 unsigned int min_cnt = min(count, scmd->request_bufflen);
3658 memcpy(scmd->request_buffer, data, min_cnt);
3659 }
3660}
3661
3662/****************************************************************************/
3663/* */
3664/* Routine Name: ips_scmd_buf_read */
3665/* */
3666/* Routine Description: */
3667/* Copy data from a Scsi_Cmnd to a new, linear buffer */
3668/****************************************************************************/
3669static void
3670ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
3671 int count)
3672{
3673 if (scmd->use_sg) {
3674 int i;
3675 unsigned int min_cnt, xfer_cnt;
3676 char *cdata = (char *) data;
3677 struct scatterlist *sg = scmd->request_buffer;
3678 for (i = 0, xfer_cnt = 0;
3679 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3680 if (!IPS_SG_ADDRESS(&sg[i]))
3681 return;
3682 min_cnt = min(count - xfer_cnt, sg[i].length);
3683 memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
3684 min_cnt);
3685 xfer_cnt += min_cnt;
3686 }
3687
3688 } else {
3689 unsigned int min_cnt = min(count, scmd->request_bufflen);
3690 memcpy(data, scmd->request_buffer, min_cnt);
3691 }
3692}
3693
3694/****************************************************************************/
3695/* */
3696/* Routine Name: ips_send_cmd */
3697/* */
3698/* Routine Description: */
3699/* */
3700/* Map SCSI commands to ServeRAID commands for logical drives */
3701/* */
3702/****************************************************************************/
3703static int
3704ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3705{
3706 int ret;
3707 char *sp;
3708 int device_error;
3709 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3710 int TimeOut;
3711
3712 METHOD_TRACE("ips_send_cmd", 1);
3713
3714 ret = IPS_SUCCESS;
3715
3716 if (!scb->scsi_cmd) {
3717 /* internal command */
3718
3719 if (scb->bus > 0) {
3720 /* Controller commands can't be issued */
3721 /* to real devices -- fail them */
3722 if ((ha->waitflag == TRUE) &&
3723 (ha->cmd_in_progress == scb->cdb[0])) {
3724 ha->waitflag = FALSE;
3725 }
3726
3727 return (1);
3728 }
3729 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3730 /* command to logical bus -- interpret */
3731 ret = IPS_SUCCESS_IMM;
3732
3733 switch (scb->scsi_cmd->cmnd[0]) {
3734 case ALLOW_MEDIUM_REMOVAL:
3735 case REZERO_UNIT:
3736 case ERASE:
3737 case WRITE_FILEMARKS:
3738 case SPACE:
3739 scb->scsi_cmd->result = DID_ERROR << 16;
3740 break;
3741
3742 case START_STOP:
3743 scb->scsi_cmd->result = DID_OK << 16;
3744
3745 case TEST_UNIT_READY:
3746 case INQUIRY:
3747 if (scb->target_id == IPS_ADAPTER_ID) {
3748 /*
3749 * Either we have a TUR
3750 * or we have a SCSI inquiry
3751 */
3752 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3753 scb->scsi_cmd->result = DID_OK << 16;
3754
3755 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3756 IPS_SCSI_INQ_DATA inquiry;
3757
3758 memset(&inquiry, 0,
3759 sizeof (IPS_SCSI_INQ_DATA));
3760
3761 inquiry.DeviceType =
3762 IPS_SCSI_INQ_TYPE_PROCESSOR;
3763 inquiry.DeviceTypeQualifier =
3764 IPS_SCSI_INQ_LU_CONNECTED;
3765 inquiry.Version = IPS_SCSI_INQ_REV2;
3766 inquiry.ResponseDataFormat =
3767 IPS_SCSI_INQ_RD_REV2;
3768 inquiry.AdditionalLength = 31;
3769 inquiry.Flags[0] =
3770 IPS_SCSI_INQ_Address16;
3771 inquiry.Flags[1] =
3772 IPS_SCSI_INQ_WBus16 |
3773 IPS_SCSI_INQ_Sync;
3774 strncpy(inquiry.VendorId, "IBM ",
3775 8);
3776 strncpy(inquiry.ProductId,
3777 "SERVERAID ", 16);
3778 strncpy(inquiry.ProductRevisionLevel,
3779 "1.00", 4);
3780
3781 ips_scmd_buf_write(scb->scsi_cmd,
3782 &inquiry,
3783 sizeof (inquiry));
3784
3785 scb->scsi_cmd->result = DID_OK << 16;
3786 }
3787 } else {
3788 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3789 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3790 scb->cmd.logical_info.reserved = 0;
3791 scb->cmd.logical_info.reserved2 = 0;
3792 scb->data_len = sizeof (IPS_LD_INFO);
3793 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3794 scb->flags = 0;
3795 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3796 ret = IPS_SUCCESS;
3797 }
3798
3799 break;
3800
3801 case REQUEST_SENSE:
3802 ips_reqsen(ha, scb);
3803 scb->scsi_cmd->result = DID_OK << 16;
3804 break;
3805
3806 case READ_6:
3807 case WRITE_6:
3808 if (!scb->sg_len) {
3809 scb->cmd.basic_io.op_code =
3810 (scb->scsi_cmd->cmnd[0] ==
3811 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3812 scb->cmd.basic_io.enhanced_sg = 0;
3813 scb->cmd.basic_io.sg_addr =
3814 cpu_to_le32(scb->data_busaddr);
3815 } else {
3816 scb->cmd.basic_io.op_code =
3817 (scb->scsi_cmd->cmnd[0] ==
3818 READ_6) ? IPS_CMD_READ_SG :
3819 IPS_CMD_WRITE_SG;
3820 scb->cmd.basic_io.enhanced_sg =
3821 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3822 scb->cmd.basic_io.sg_addr =
3823 cpu_to_le32(scb->sg_busaddr);
3824 }
3825
3826 scb->cmd.basic_io.segment_4G = 0;
3827 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3828 scb->cmd.basic_io.log_drv = scb->target_id;
3829 scb->cmd.basic_io.sg_count = scb->sg_len;
3830
3831 if (scb->cmd.basic_io.lba)
3832 scb->cmd.basic_io.lba =
3833 cpu_to_le32(le32_to_cpu
3834 (scb->cmd.basic_io.lba) +
3835 le16_to_cpu(scb->cmd.basic_io.
3836 sector_count));
3837 else
3838 scb->cmd.basic_io.lba =
3839 (((scb->scsi_cmd->
3840 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3841 cmnd[2] << 8) |
3842 (scb->scsi_cmd->cmnd[3]));
3843
3844 scb->cmd.basic_io.sector_count =
3845 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3846
3847 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3848 scb->cmd.basic_io.sector_count =
3849 cpu_to_le16(256);
3850
3851 ret = IPS_SUCCESS;
3852 break;
3853
3854 case READ_10:
3855 case WRITE_10:
3856 if (!scb->sg_len) {
3857 scb->cmd.basic_io.op_code =
3858 (scb->scsi_cmd->cmnd[0] ==
3859 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3860 scb->cmd.basic_io.enhanced_sg = 0;
3861 scb->cmd.basic_io.sg_addr =
3862 cpu_to_le32(scb->data_busaddr);
3863 } else {
3864 scb->cmd.basic_io.op_code =
3865 (scb->scsi_cmd->cmnd[0] ==
3866 READ_10) ? IPS_CMD_READ_SG :
3867 IPS_CMD_WRITE_SG;
3868 scb->cmd.basic_io.enhanced_sg =
3869 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3870 scb->cmd.basic_io.sg_addr =
3871 cpu_to_le32(scb->sg_busaddr);
3872 }
3873
3874 scb->cmd.basic_io.segment_4G = 0;
3875 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3876 scb->cmd.basic_io.log_drv = scb->target_id;
3877 scb->cmd.basic_io.sg_count = scb->sg_len;
3878
3879 if (scb->cmd.basic_io.lba)
3880 scb->cmd.basic_io.lba =
3881 cpu_to_le32(le32_to_cpu
3882 (scb->cmd.basic_io.lba) +
3883 le16_to_cpu(scb->cmd.basic_io.
3884 sector_count));
3885 else
3886 scb->cmd.basic_io.lba =
3887 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3888 scsi_cmd->
3889 cmnd[3]
3890 << 16) |
3891 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3892 scsi_cmd->cmnd[5]);
3893
3894 scb->cmd.basic_io.sector_count =
3895 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3896
3897 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3898 /*
3899 * This is a null condition
3900 * we don't have to do anything
3901 * so just return
3902 */
3903 scb->scsi_cmd->result = DID_OK << 16;
3904 } else
3905 ret = IPS_SUCCESS;
3906
3907 break;
3908
3909 case RESERVE:
3910 case RELEASE:
3911 scb->scsi_cmd->result = DID_OK << 16;
3912 break;
3913
3914 case MODE_SENSE:
3915 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3916 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3917 scb->cmd.basic_io.segment_4G = 0;
3918 scb->cmd.basic_io.enhanced_sg = 0;
3919 scb->data_len = sizeof (*ha->enq);
3920 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3921 ret = IPS_SUCCESS;
3922 break;
3923
3924 case READ_CAPACITY:
3925 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3926 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3927 scb->cmd.logical_info.reserved = 0;
3928 scb->cmd.logical_info.reserved2 = 0;
3929 scb->cmd.logical_info.reserved3 = 0;
3930 scb->data_len = sizeof (IPS_LD_INFO);
3931 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3932 scb->flags = 0;
3933 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3934 ret = IPS_SUCCESS;
3935 break;
3936
3937 case SEND_DIAGNOSTIC:
3938 case REASSIGN_BLOCKS:
3939 case FORMAT_UNIT:
3940 case SEEK_10:
3941 case VERIFY:
3942 case READ_DEFECT_DATA:
3943 case READ_BUFFER:
3944 case WRITE_BUFFER:
3945 scb->scsi_cmd->result = DID_OK << 16;
3946 break;
3947
3948 default:
3949 /* Set the Return Info to appear like the Command was */
3950 /* attempted, a Check Condition occurred, and Sense */
3951 /* Data indicating an Invalid CDB OpCode is returned. */
3952 sp = (char *) scb->scsi_cmd->sense_buffer;
3953 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3954
3955 sp[0] = 0x70; /* Error Code */
3956 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3957 sp[7] = 0x0A; /* Additional Sense Length */
3958 sp[12] = 0x20; /* ASC = Invalid OpCode */
3959 sp[13] = 0x00; /* ASCQ */
3960
3961 device_error = 2; /* Indicate Check Condition */
3962 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3963 break;
3964 } /* end switch */
3965 }
3966 /* end if */
3967 if (ret == IPS_SUCCESS_IMM)
3968 return (ret);
3969
3970 /* setup DCDB */
3971 if (scb->bus > 0) {
3972
3973 /* If we already know the Device is Not there, no need to attempt a Command */
3974 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3975 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3976 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3977 return (IPS_SUCCESS_IMM);
3978 }
3979
3980 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3981 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3982 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3983 (unsigned long) &scb->
3984 dcdb -
3985 (unsigned long) scb);
3986 scb->cmd.dcdb.reserved = 0;
3987 scb->cmd.dcdb.reserved2 = 0;
3988 scb->cmd.dcdb.reserved3 = 0;
3989 scb->cmd.dcdb.segment_4G = 0;
3990 scb->cmd.dcdb.enhanced_sg = 0;
3991
3992 TimeOut = scb->scsi_cmd->timeout_per_command;
3993
3994 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3995 if (!scb->sg_len) {
3996 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3997 } else {
3998 scb->cmd.dcdb.op_code =
3999 IPS_CMD_EXTENDED_DCDB_SG;
4000 scb->cmd.dcdb.enhanced_sg =
4001 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4002 }
4003
4004 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
4005 tapeDCDB->device_address =
4006 ((scb->bus - 1) << 4) | scb->target_id;
4007 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4008 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
4009
4010 if (TimeOut) {
4011 if (TimeOut < (10 * HZ))
4012 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4013 else if (TimeOut < (60 * HZ))
4014 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4015 else if (TimeOut < (1200 * HZ))
4016 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4017 }
4018
4019 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
4020 tapeDCDB->reserved_for_LUN = 0;
4021 tapeDCDB->transfer_length = scb->data_len;
4022 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
4023 tapeDCDB->buffer_pointer =
4024 cpu_to_le32(scb->sg_busaddr);
4025 else
4026 tapeDCDB->buffer_pointer =
4027 cpu_to_le32(scb->data_busaddr);
4028 tapeDCDB->sg_count = scb->sg_len;
4029 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
4030 tapeDCDB->scsi_status = 0;
4031 tapeDCDB->reserved = 0;
4032 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
4033 scb->scsi_cmd->cmd_len);
4034 } else {
4035 if (!scb->sg_len) {
4036 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
4037 } else {
4038 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
4039 scb->cmd.dcdb.enhanced_sg =
4040 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4041 }
4042
4043 scb->dcdb.device_address =
4044 ((scb->bus - 1) << 4) | scb->target_id;
4045 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4046
4047 if (TimeOut) {
4048 if (TimeOut < (10 * HZ))
4049 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4050 else if (TimeOut < (60 * HZ))
4051 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4052 else if (TimeOut < (1200 * HZ))
4053 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4054 }
4055
4056 scb->dcdb.transfer_length = scb->data_len;
4057 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
4058 scb->dcdb.transfer_length = 0;
4059 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
4060 scb->dcdb.buffer_pointer =
4061 cpu_to_le32(scb->sg_busaddr);
4062 else
4063 scb->dcdb.buffer_pointer =
4064 cpu_to_le32(scb->data_busaddr);
4065 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
4066 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
4067 scb->dcdb.sg_count = scb->sg_len;
4068 scb->dcdb.reserved = 0;
4069 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
4070 scb->scsi_cmd->cmd_len);
4071 scb->dcdb.scsi_status = 0;
4072 scb->dcdb.reserved2[0] = 0;
4073 scb->dcdb.reserved2[1] = 0;
4074 scb->dcdb.reserved2[2] = 0;
4075 }
4076 }
4077
4078 return ((*ha->func.issue) (ha, scb));
4079}
4080
4081/****************************************************************************/
4082/* */
4083/* Routine Name: ips_chk_status */
4084/* */
4085/* Routine Description: */
4086/* */
4087/* Check the status of commands to logical drives */
4088/* Assumed to be called with the HA lock */
4089/****************************************************************************/
4090static void
4091ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4092{
4093 ips_scb_t *scb;
4094 ips_stat_t *sp;
4095 uint8_t basic_status;
4096 uint8_t ext_status;
4097 int errcode;
4098
4099 METHOD_TRACE("ips_chkstatus", 1);
4100
4101 scb = &ha->scbs[pstatus->fields.command_id];
4102 scb->basic_status = basic_status =
4103 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
4104 scb->extended_status = ext_status = pstatus->fields.extended_status;
4105
4106 sp = &ha->sp;
4107 sp->residue_len = 0;
4108 sp->scb_addr = (void *) scb;
4109
4110 /* Remove the item from the active queue */
4111 ips_removeq_scb(&ha->scb_activelist, scb);
4112
4113 if (!scb->scsi_cmd)
4114 /* internal commands are handled in do_ipsintr */
4115 return;
4116
4117 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
4118 ips_name,
4119 ha->host_num,
4120 scb->cdb[0],
4121 scb->cmd.basic_io.command_id,
4122 scb->bus, scb->target_id, scb->lun);
4123
4124 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
4125 /* passthru - just returns the raw result */
4126 return;
4127
4128 errcode = DID_OK;
4129
4130 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4131 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4132
4133 if (scb->bus == 0) {
4134 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4135 IPS_CMD_RECOVERED_ERROR) {
4136 DEBUG_VAR(1,
4137 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4138 ips_name, ha->host_num,
4139 scb->cmd.basic_io.op_code,
4140 basic_status, ext_status);
4141 }
4142
4143 switch (scb->scsi_cmd->cmnd[0]) {
4144 case ALLOW_MEDIUM_REMOVAL:
4145 case REZERO_UNIT:
4146 case ERASE:
4147 case WRITE_FILEMARKS:
4148 case SPACE:
4149 errcode = DID_ERROR;
4150 break;
4151
4152 case START_STOP:
4153 break;
4154
4155 case TEST_UNIT_READY:
4156 if (!ips_online(ha, scb)) {
4157 errcode = DID_TIME_OUT;
4158 }
4159 break;
4160
4161 case INQUIRY:
4162 if (ips_online(ha, scb)) {
4163 ips_inquiry(ha, scb);
4164 } else {
4165 errcode = DID_TIME_OUT;
4166 }
4167 break;
4168
4169 case REQUEST_SENSE:
4170 ips_reqsen(ha, scb);
4171 break;
4172
4173 case READ_6:
4174 case WRITE_6:
4175 case READ_10:
4176 case WRITE_10:
4177 case RESERVE:
4178 case RELEASE:
4179 break;
4180
4181 case MODE_SENSE:
4182 if (!ips_online(ha, scb)
4183 || !ips_msense(ha, scb)) {
4184 errcode = DID_ERROR;
4185 }
4186 break;
4187
4188 case READ_CAPACITY:
4189 if (ips_online(ha, scb))
4190 ips_rdcap(ha, scb);
4191 else {
4192 errcode = DID_TIME_OUT;
4193 }
4194 break;
4195
4196 case SEND_DIAGNOSTIC:
4197 case REASSIGN_BLOCKS:
4198 break;
4199
4200 case FORMAT_UNIT:
4201 errcode = DID_ERROR;
4202 break;
4203
4204 case SEEK_10:
4205 case VERIFY:
4206 case READ_DEFECT_DATA:
4207 case READ_BUFFER:
4208 case WRITE_BUFFER:
4209 break;
4210
4211 default:
4212 errcode = DID_ERROR;
4213 } /* end switch */
4214
4215 scb->scsi_cmd->result = errcode << 16;
4216 } else { /* bus == 0 */
4217 /* restrict access to physical drives */
4218 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
4219 ((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
4220 TYPE_DISK)) {
4221
4222 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4223 }
4224 } /* else */
4225 } else { /* recovered error / success */
4226 if (scb->bus == 0) {
4227 DEBUG_VAR(1,
4228 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4229 ips_name, ha->host_num,
4230 scb->cmd.basic_io.op_code, basic_status,
4231 ext_status);
4232 }
4233
4234 ips_map_status(ha, scb, sp);
4235 } /* else */
4236}
4237
4238/****************************************************************************/
4239/* */
4240/* Routine Name: ips_online */
4241/* */
4242/* Routine Description: */
4243/* */
4244/* Determine if a logical drive is online */
4245/* */
4246/****************************************************************************/
4247static int
4248ips_online(ips_ha_t * ha, ips_scb_t * scb)
4249{
4250 METHOD_TRACE("ips_online", 1);
4251
4252 if (scb->target_id >= IPS_MAX_LD)
4253 return (0);
4254
4255 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4256 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4257 return (0);
4258 }
4259
4260 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4261 IPS_LD_OFFLINE
4262 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4263 IPS_LD_FREE
4264 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4265 IPS_LD_CRS
4266 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4267 IPS_LD_SYS)
4268 return (1);
4269 else
4270 return (0);
4271}
4272
4273/****************************************************************************/
4274/* */
4275/* Routine Name: ips_inquiry */
4276/* */
4277/* Routine Description: */
4278/* */
4279/* Simulate an inquiry command to a logical drive */
4280/* */
4281/****************************************************************************/
4282static int
4283ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4284{
4285 IPS_SCSI_INQ_DATA inquiry;
4286
4287 METHOD_TRACE("ips_inquiry", 1);
4288
4289 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4290
4291 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4292 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4293 inquiry.Version = IPS_SCSI_INQ_REV2;
4294 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4295 inquiry.AdditionalLength = 31;
4296 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4297 inquiry.Flags[1] =
4298 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4299 strncpy(inquiry.VendorId, "IBM ", 8);
4300 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4301 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4302
4303 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4304
4305 return (1);
4306}
4307
4308/****************************************************************************/
4309/* */
4310/* Routine Name: ips_rdcap */
4311/* */
4312/* Routine Description: */
4313/* */
4314/* Simulate a read capacity command to a logical drive */
4315/* */
4316/****************************************************************************/
4317static int
4318ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4319{
4320 IPS_SCSI_CAPACITY cap;
4321
4322 METHOD_TRACE("ips_rdcap", 1);
4323
4324 if (scb->scsi_cmd->bufflen < 8)
4325 return (0);
4326
4327 cap.lba =
4328 cpu_to_be32(le32_to_cpu
4329 (ha->logical_drive_info->
4330 drive_info[scb->target_id].sector_count) - 1);
4331 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4332
4333 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4334
4335 return (1);
4336}
4337
4338/****************************************************************************/
4339/* */
4340/* Routine Name: ips_msense */
4341/* */
4342/* Routine Description: */
4343/* */
4344/* Simulate a mode sense command to a logical drive */
4345/* */
4346/****************************************************************************/
4347static int
4348ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4349{
4350 uint16_t heads;
4351 uint16_t sectors;
4352 uint32_t cylinders;
4353 IPS_SCSI_MODE_PAGE_DATA mdata;
4354
4355 METHOD_TRACE("ips_msense", 1);
4356
4357 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4358 (ha->enq->ucMiscFlag & 0x8) == 0) {
4359 heads = IPS_NORM_HEADS;
4360 sectors = IPS_NORM_SECTORS;
4361 } else {
4362 heads = IPS_COMP_HEADS;
4363 sectors = IPS_COMP_SECTORS;
4364 }
4365
4366 cylinders =
4367 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4368 1) / (heads * sectors);
4369
4370 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4371
4372 mdata.hdr.BlockDescLength = 8;
4373
4374 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4375 case 0x03: /* page 3 */
4376 mdata.pdata.pg3.PageCode = 3;
4377 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4378 mdata.hdr.DataLength =
4379 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4380 mdata.pdata.pg3.TracksPerZone = 0;
4381 mdata.pdata.pg3.AltSectorsPerZone = 0;
4382 mdata.pdata.pg3.AltTracksPerZone = 0;
4383 mdata.pdata.pg3.AltTracksPerVolume = 0;
4384 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4385 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4386 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4387 mdata.pdata.pg3.TrackSkew = 0;
4388 mdata.pdata.pg3.CylinderSkew = 0;
4389 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4390 break;
4391
4392 case 0x4:
4393 mdata.pdata.pg4.PageCode = 4;
4394 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4395 mdata.hdr.DataLength =
4396 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4397 mdata.pdata.pg4.CylindersHigh =
4398 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4399 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4400 mdata.pdata.pg4.Heads = heads;
4401 mdata.pdata.pg4.WritePrecompHigh = 0;
4402 mdata.pdata.pg4.WritePrecompLow = 0;
4403 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4404 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4405 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4406 mdata.pdata.pg4.LandingZoneHigh = 0;
4407 mdata.pdata.pg4.LandingZoneLow = 0;
4408 mdata.pdata.pg4.flags = 0;
4409 mdata.pdata.pg4.RotationalOffset = 0;
4410 mdata.pdata.pg4.MediumRotationRate = 0;
4411 break;
4412 case 0x8:
4413 mdata.pdata.pg8.PageCode = 8;
4414 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4415 mdata.hdr.DataLength =
4416 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4417 /* everything else is left set to 0 */
4418 break;
4419
4420 default:
4421 return (0);
4422 } /* end switch */
4423
4424 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4425
4426 return (1);
4427}
4428
4429/****************************************************************************/
4430/* */
4431/* Routine Name: ips_reqsen */
4432/* */
4433/* Routine Description: */
4434/* */
4435/* Simulate a request sense command to a logical drive */
4436/* */
4437/****************************************************************************/
4438static int
4439ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4440{
4441 IPS_SCSI_REQSEN reqsen;
4442
4443 METHOD_TRACE("ips_reqsen", 1);
4444
4445 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4446
4447 reqsen.ResponseCode =
4448 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4449 reqsen.AdditionalLength = 10;
4450 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4451 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4452
4453 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4454
4455 return (1);
4456}
4457
4458/****************************************************************************/
4459/* */
4460/* Routine Name: ips_free */
4461/* */
4462/* Routine Description: */
4463/* */
4464/* Free any allocated space for this controller */
4465/* */
4466/****************************************************************************/
4467static void
4468ips_free(ips_ha_t * ha)
4469{
4470
4471 METHOD_TRACE("ips_free", 1);
4472
4473 if (ha) {
4474 if (ha->enq) {
4475 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4476 ha->enq, ha->enq_busaddr);
4477 ha->enq = NULL;
4478 }
4479
4480 if (ha->conf) {
4481 kfree(ha->conf);
4482 ha->conf = NULL;
4483 }
4484
4485 if (ha->adapt) {
4486 pci_free_consistent(ha->pcidev,
4487 sizeof (IPS_ADAPTER) +
4488 sizeof (IPS_IO_CMD), ha->adapt,
4489 ha->adapt->hw_status_start);
4490 ha->adapt = NULL;
4491 }
4492
4493 if (ha->logical_drive_info) {
4494 pci_free_consistent(ha->pcidev,
4495 sizeof (IPS_LD_INFO),
4496 ha->logical_drive_info,
4497 ha->logical_drive_info_dma_addr);
4498 ha->logical_drive_info = NULL;
4499 }
4500
4501 if (ha->nvram) {
4502 kfree(ha->nvram);
4503 ha->nvram = NULL;
4504 }
4505
4506 if (ha->subsys) {
4507 kfree(ha->subsys);
4508 ha->subsys = NULL;
4509 }
4510
4511 if (ha->ioctl_data) {
4512 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4513 ha->ioctl_data, ha->ioctl_busaddr);
4514 ha->ioctl_data = NULL;
4515 ha->ioctl_datasize = 0;
4516 ha->ioctl_len = 0;
4517 }
4518 ips_deallocatescbs(ha, ha->max_cmds);
4519
4520 /* free memory mapped (if applicable) */
4521 if (ha->mem_ptr) {
4522 iounmap(ha->ioremap_ptr);
4523 ha->ioremap_ptr = NULL;
4524 ha->mem_ptr = NULL;
4525 }
4526
4527 if (ha->mem_addr)
4528 release_mem_region(ha->mem_addr, ha->mem_len);
4529 ha->mem_addr = 0;
4530
4531 }
4532}
4533
4534/****************************************************************************/
4535/* */
4536/* Routine Name: ips_deallocatescbs */
4537/* */
4538/* Routine Description: */
4539/* */
4540/* Free the command blocks */
4541/* */
4542/****************************************************************************/
4543static int
4544ips_deallocatescbs(ips_ha_t * ha, int cmds)
4545{
4546 if (ha->scbs) {
4547 pci_free_consistent(ha->pcidev,
4548 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4549 ha->scbs->sg_list.list,
4550 ha->scbs->sg_busaddr);
4551 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4552 ha->scbs, ha->scbs->scb_busaddr);
4553 ha->scbs = NULL;
4554 } /* end if */
4555 return 1;
4556}
4557
4558/****************************************************************************/
4559/* */
4560/* Routine Name: ips_allocatescbs */
4561/* */
4562/* Routine Description: */
4563/* */
4564/* Allocate the command blocks */
4565/* */
4566/****************************************************************************/
4567static int
4568ips_allocatescbs(ips_ha_t * ha)
4569{
4570 ips_scb_t *scb_p;
4571 IPS_SG_LIST ips_sg;
4572 int i;
4573 dma_addr_t command_dma, sg_dma;
4574
4575 METHOD_TRACE("ips_allocatescbs", 1);
4576
4577 /* Allocate memory for the SCBs */
4578 ha->scbs =
4579 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4580 &command_dma);
4581 if (ha->scbs == NULL)
4582 return 0;
4583 ips_sg.list =
4584 pci_alloc_consistent(ha->pcidev,
4585 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4586 ha->max_cmds, &sg_dma);
4587 if (ips_sg.list == NULL) {
4588 pci_free_consistent(ha->pcidev,
4589 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4590 command_dma);
4591 return 0;
4592 }
4593
4594 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4595
4596 for (i = 0; i < ha->max_cmds; i++) {
4597 scb_p = &ha->scbs[i];
4598 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4599 /* set up S/G list */
4600 if (IPS_USE_ENH_SGLIST(ha)) {
4601 scb_p->sg_list.enh_list =
4602 ips_sg.enh_list + i * IPS_MAX_SG;
4603 scb_p->sg_busaddr =
4604 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4605 } else {
4606 scb_p->sg_list.std_list =
4607 ips_sg.std_list + i * IPS_MAX_SG;
4608 scb_p->sg_busaddr =
4609 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4610 }
4611
4612 /* add to the free list */
4613 if (i < ha->max_cmds - 1) {
4614 scb_p->q_next = ha->scb_freelist;
4615 ha->scb_freelist = scb_p;
4616 }
4617 }
4618
4619 /* success */
4620 return (1);
4621}
4622
4623/****************************************************************************/
4624/* */
4625/* Routine Name: ips_init_scb */
4626/* */
4627/* Routine Description: */
4628/* */
4629/* Initialize a CCB to default values */
4630/* */
4631/****************************************************************************/
4632static void
4633ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4634{
4635 IPS_SG_LIST sg_list;
4636 uint32_t cmd_busaddr, sg_busaddr;
4637 METHOD_TRACE("ips_init_scb", 1);
4638
4639 if (scb == NULL)
4640 return;
4641
4642 sg_list.list = scb->sg_list.list;
4643 cmd_busaddr = scb->scb_busaddr;
4644 sg_busaddr = scb->sg_busaddr;
4645 /* zero fill */
4646 memset(scb, 0, sizeof (ips_scb_t));
4647 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4648
4649 /* Initialize dummy command bucket */
4650 ha->dummy->op_code = 0xFF;
4651 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4652 + sizeof (IPS_ADAPTER));
4653 ha->dummy->command_id = IPS_MAX_CMDS;
4654
4655 /* set bus address of scb */
4656 scb->scb_busaddr = cmd_busaddr;
4657 scb->sg_busaddr = sg_busaddr;
4658 scb->sg_list.list = sg_list.list;
4659
4660 /* Neptune Fix */
4661 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4662 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4663 + sizeof (IPS_ADAPTER));
4664}
4665
4666/****************************************************************************/
4667/* */
4668/* Routine Name: ips_get_scb */
4669/* */
4670/* Routine Description: */
4671/* */
4672/* Initialize a CCB to default values */
4673/* */
4674/* ASSUMED to be callled from within a lock */
4675/* */
4676/****************************************************************************/
4677static ips_scb_t *
4678ips_getscb(ips_ha_t * ha)
4679{
4680 ips_scb_t *scb;
4681
4682 METHOD_TRACE("ips_getscb", 1);
4683
4684 if ((scb = ha->scb_freelist) == NULL) {
4685
4686 return (NULL);
4687 }
4688
4689 ha->scb_freelist = scb->q_next;
4690 scb->flags = 0;
4691 scb->q_next = NULL;
4692
4693 ips_init_scb(ha, scb);
4694
4695 return (scb);
4696}
4697
4698/****************************************************************************/
4699/* */
4700/* Routine Name: ips_free_scb */
4701/* */
4702/* Routine Description: */
4703/* */
4704/* Return an unused CCB back to the free list */
4705/* */
4706/* ASSUMED to be called from within a lock */
4707/* */
4708/****************************************************************************/
4709static void
4710ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4711{
4712
4713 METHOD_TRACE("ips_freescb", 1);
4714 if (scb->flags & IPS_SCB_MAP_SG)
4715 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4716 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
4717 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4718 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4719 IPS_DMA_DIR(scb));
4720
4721 /* check to make sure this is not our "special" scb */
4722 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4723 scb->q_next = ha->scb_freelist;
4724 ha->scb_freelist = scb;
4725 }
4726}
4727
4728/****************************************************************************/
4729/* */
4730/* Routine Name: ips_isinit_copperhead */
4731/* */
4732/* Routine Description: */
4733/* */
4734/* Is controller initialized ? */
4735/* */
4736/****************************************************************************/
4737static int
4738ips_isinit_copperhead(ips_ha_t * ha)
4739{
4740 uint8_t scpr;
4741 uint8_t isr;
4742
4743 METHOD_TRACE("ips_isinit_copperhead", 1);
4744
4745 isr = inb(ha->io_addr + IPS_REG_HISR);
4746 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4747
4748 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4749 return (0);
4750 else
4751 return (1);
4752}
4753
4754/****************************************************************************/
4755/* */
4756/* Routine Name: ips_isinit_copperhead_memio */
4757/* */
4758/* Routine Description: */
4759/* */
4760/* Is controller initialized ? */
4761/* */
4762/****************************************************************************/
4763static int
4764ips_isinit_copperhead_memio(ips_ha_t * ha)
4765{
4766 uint8_t isr = 0;
4767 uint8_t scpr;
4768
4769 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4770
4771 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4772 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4773
4774 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4775 return (0);
4776 else
4777 return (1);
4778}
4779
4780/****************************************************************************/
4781/* */
4782/* Routine Name: ips_isinit_morpheus */
4783/* */
4784/* Routine Description: */
4785/* */
4786/* Is controller initialized ? */
4787/* */
4788/****************************************************************************/
4789static int
4790ips_isinit_morpheus(ips_ha_t * ha)
4791{
4792 uint32_t post;
4793 uint32_t bits;
4794
4795 METHOD_TRACE("ips_is_init_morpheus", 1);
4796
4797 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4798 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4799
4800 if (post == 0)
4801 return (0);
4802 else if (bits & 0x3)
4803 return (0);
4804 else
4805 return (1);
4806}
4807
4808/****************************************************************************/
4809/* */
4810/* Routine Name: ips_enable_int_copperhead */
4811/* */
4812/* Routine Description: */
4813/* Turn on interrupts */
4814/* */
4815/****************************************************************************/
4816static void
4817ips_enable_int_copperhead(ips_ha_t * ha)
4818{
4819 METHOD_TRACE("ips_enable_int_copperhead", 1);
4820
4821 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4822 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4823}
4824
4825/****************************************************************************/
4826/* */
4827/* Routine Name: ips_enable_int_copperhead_memio */
4828/* */
4829/* Routine Description: */
4830/* Turn on interrupts */
4831/* */
4832/****************************************************************************/
4833static void
4834ips_enable_int_copperhead_memio(ips_ha_t * ha)
4835{
4836 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4837
4838 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4839 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4840}
4841
4842/****************************************************************************/
4843/* */
4844/* Routine Name: ips_enable_int_morpheus */
4845/* */
4846/* Routine Description: */
4847/* Turn on interrupts */
4848/* */
4849/****************************************************************************/
4850static void
4851ips_enable_int_morpheus(ips_ha_t * ha)
4852{
4853 uint32_t Oimr;
4854
4855 METHOD_TRACE("ips_enable_int_morpheus", 1);
4856
4857 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4858 Oimr &= ~0x08;
4859 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4860 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4861}
4862
4863/****************************************************************************/
4864/* */
4865/* Routine Name: ips_init_copperhead */
4866/* */
4867/* Routine Description: */
4868/* */
4869/* Initialize a copperhead controller */
4870/* */
4871/****************************************************************************/
4872static int
4873ips_init_copperhead(ips_ha_t * ha)
4874{
4875 uint8_t Isr;
4876 uint8_t Cbsp;
4877 uint8_t PostByte[IPS_MAX_POST_BYTES];
4878 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4879 int i, j;
4880
4881 METHOD_TRACE("ips_init_copperhead", 1);
4882
4883 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4884 for (j = 0; j < 45; j++) {
4885 Isr = inb(ha->io_addr + IPS_REG_HISR);
4886 if (Isr & IPS_BIT_GHI)
4887 break;
4888
4889 /* Delay for 1 Second */
4890 MDELAY(IPS_ONE_SEC);
4891 }
4892
4893 if (j >= 45)
4894 /* error occurred */
4895 return (0);
4896
4897 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4898 outb(Isr, ha->io_addr + IPS_REG_HISR);
4899 }
4900
4901 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4902 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4903 "reset controller fails (post status %x %x).\n",
4904 PostByte[0], PostByte[1]);
4905
4906 return (0);
4907 }
4908
4909 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4910 for (j = 0; j < 240; j++) {
4911 Isr = inb(ha->io_addr + IPS_REG_HISR);
4912 if (Isr & IPS_BIT_GHI)
4913 break;
4914
4915 /* Delay for 1 Second */
4916 MDELAY(IPS_ONE_SEC);
4917 }
4918
4919 if (j >= 240)
4920 /* error occurred */
4921 return (0);
4922
4923 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4924 outb(Isr, ha->io_addr + IPS_REG_HISR);
4925 }
4926
4927 for (i = 0; i < 240; i++) {
4928 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4929
4930 if ((Cbsp & IPS_BIT_OP) == 0)
4931 break;
4932
4933 /* Delay for 1 Second */
4934 MDELAY(IPS_ONE_SEC);
4935 }
4936
4937 if (i >= 240)
4938 /* reset failed */
4939 return (0);
4940
4941 /* setup CCCR */
4942 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4943
4944 /* Enable busmastering */
4945 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4946
4947 if (ha->revision_id == IPS_REVID_TROMBONE64)
4948 /* fix for anaconda64 */
4949 outl(0, ha->io_addr + IPS_REG_NDAE);
4950
4951 /* Enable interrupts */
4952 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4953
4954 return (1);
4955}
4956
4957/****************************************************************************/
4958/* */
4959/* Routine Name: ips_init_copperhead_memio */
4960/* */
4961/* Routine Description: */
4962/* */
4963/* Initialize a copperhead controller with memory mapped I/O */
4964/* */
4965/****************************************************************************/
4966static int
4967ips_init_copperhead_memio(ips_ha_t * ha)
4968{
4969 uint8_t Isr = 0;
4970 uint8_t Cbsp;
4971 uint8_t PostByte[IPS_MAX_POST_BYTES];
4972 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4973 int i, j;
4974
4975 METHOD_TRACE("ips_init_copperhead_memio", 1);
4976
4977 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4978 for (j = 0; j < 45; j++) {
4979 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4980 if (Isr & IPS_BIT_GHI)
4981 break;
4982
4983 /* Delay for 1 Second */
4984 MDELAY(IPS_ONE_SEC);
4985 }
4986
4987 if (j >= 45)
4988 /* error occurred */
4989 return (0);
4990
4991 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4992 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4993 }
4994
4995 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4996 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4997 "reset controller fails (post status %x %x).\n",
4998 PostByte[0], PostByte[1]);
4999
5000 return (0);
5001 }
5002
5003 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
5004 for (j = 0; j < 240; j++) {
5005 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5006 if (Isr & IPS_BIT_GHI)
5007 break;
5008
5009 /* Delay for 1 Second */
5010 MDELAY(IPS_ONE_SEC);
5011 }
5012
5013 if (j >= 240)
5014 /* error occurred */
5015 return (0);
5016
5017 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5018 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5019 }
5020
5021 for (i = 0; i < 240; i++) {
5022 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5023
5024 if ((Cbsp & IPS_BIT_OP) == 0)
5025 break;
5026
5027 /* Delay for 1 Second */
5028 MDELAY(IPS_ONE_SEC);
5029 }
5030
5031 if (i >= 240)
5032 /* error occurred */
5033 return (0);
5034
5035 /* setup CCCR */
5036 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5037
5038 /* Enable busmastering */
5039 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5040
5041 if (ha->revision_id == IPS_REVID_TROMBONE64)
5042 /* fix for anaconda64 */
5043 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5044
5045 /* Enable interrupts */
5046 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5047
5048 /* if we get here then everything went OK */
5049 return (1);
5050}
5051
5052/****************************************************************************/
5053/* */
5054/* Routine Name: ips_init_morpheus */
5055/* */
5056/* Routine Description: */
5057/* */
5058/* Initialize a morpheus controller */
5059/* */
5060/****************************************************************************/
5061static int
5062ips_init_morpheus(ips_ha_t * ha)
5063{
5064 uint32_t Post;
5065 uint32_t Config;
5066 uint32_t Isr;
5067 uint32_t Oimr;
5068 int i;
5069
5070 METHOD_TRACE("ips_init_morpheus", 1);
5071
5072 /* Wait up to 45 secs for Post */
5073 for (i = 0; i < 45; i++) {
5074 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5075
5076 if (Isr & IPS_BIT_I960_MSG0I)
5077 break;
5078
5079 /* Delay for 1 Second */
5080 MDELAY(IPS_ONE_SEC);
5081 }
5082
5083 if (i >= 45) {
5084 /* error occurred */
5085 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5086 "timeout waiting for post.\n");
5087
5088 return (0);
5089 }
5090
5091 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5092
5093 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5094 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5095 "Flashing Battery PIC, Please wait ...\n");
5096
5097 /* Clear the interrupt bit */
5098 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5099 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5100
5101 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5102 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5103 if (Post != 0x4F00)
5104 break;
5105 /* Delay for 1 Second */
5106 MDELAY(IPS_ONE_SEC);
5107 }
5108
5109 if (i >= 120) {
5110 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5111 "timeout waiting for Battery PIC Flash\n");
5112 return (0);
5113 }
5114
5115 }
5116
5117 /* Clear the interrupt bit */
5118 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5119 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5120
5121 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5122 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5123 "reset controller fails (post status %x).\n", Post);
5124
5125 return (0);
5126 }
5127
5128 /* Wait up to 240 secs for config bytes */
5129 for (i = 0; i < 240; i++) {
5130 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5131
5132 if (Isr & IPS_BIT_I960_MSG1I)
5133 break;
5134
5135 /* Delay for 1 Second */
5136 MDELAY(IPS_ONE_SEC);
5137 }
5138
5139 if (i >= 240) {
5140 /* error occurred */
5141 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5142 "timeout waiting for config.\n");
5143
5144 return (0);
5145 }
5146
5147 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5148
5149 /* Clear interrupt bit */
5150 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5151 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5152
5153 /* Turn on the interrupts */
5154 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5155 Oimr &= ~0x8;
5156 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5157
5158 /* if we get here then everything went OK */
5159
5160 /* Since we did a RESET, an EraseStripeLock may be needed */
5161 if (Post == 0xEF10) {
5162 if ((Config == 0x000F) || (Config == 0x0009))
5163 ha->requires_esl = 1;
5164 }
5165
5166 return (1);
5167}
5168
5169/****************************************************************************/
5170/* */
5171/* Routine Name: ips_reset_copperhead */
5172/* */
5173/* Routine Description: */
5174/* */
5175/* Reset the controller */
5176/* */
5177/****************************************************************************/
5178static int
5179ips_reset_copperhead(ips_ha_t * ha)
5180{
5181 int reset_counter;
5182
5183 METHOD_TRACE("ips_reset_copperhead", 1);
5184
5185 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5186 ips_name, ha->host_num, ha->io_addr, ha->irq);
5187
5188 reset_counter = 0;
5189
5190 while (reset_counter < 2) {
5191 reset_counter++;
5192
5193 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5194
5195 /* Delay for 1 Second */
5196 MDELAY(IPS_ONE_SEC);
5197
5198 outb(0, ha->io_addr + IPS_REG_SCPR);
5199
5200 /* Delay for 1 Second */
5201 MDELAY(IPS_ONE_SEC);
5202
5203 if ((*ha->func.init) (ha))
5204 break;
5205 else if (reset_counter >= 2) {
5206
5207 return (0);
5208 }
5209 }
5210
5211 return (1);
5212}
5213
5214/****************************************************************************/
5215/* */
5216/* Routine Name: ips_reset_copperhead_memio */
5217/* */
5218/* Routine Description: */
5219/* */
5220/* Reset the controller */
5221/* */
5222/****************************************************************************/
5223static int
5224ips_reset_copperhead_memio(ips_ha_t * ha)
5225{
5226 int reset_counter;
5227
5228 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5229
5230 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5231 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5232
5233 reset_counter = 0;
5234
5235 while (reset_counter < 2) {
5236 reset_counter++;
5237
5238 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5239
5240 /* Delay for 1 Second */
5241 MDELAY(IPS_ONE_SEC);
5242
5243 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5244
5245 /* Delay for 1 Second */
5246 MDELAY(IPS_ONE_SEC);
5247
5248 if ((*ha->func.init) (ha))
5249 break;
5250 else if (reset_counter >= 2) {
5251
5252 return (0);
5253 }
5254 }
5255
5256 return (1);
5257}
5258
5259/****************************************************************************/
5260/* */
5261/* Routine Name: ips_reset_morpheus */
5262/* */
5263/* Routine Description: */
5264/* */
5265/* Reset the controller */
5266/* */
5267/****************************************************************************/
5268static int
5269ips_reset_morpheus(ips_ha_t * ha)
5270{
5271 int reset_counter;
5272 uint8_t junk;
5273
5274 METHOD_TRACE("ips_reset_morpheus", 1);
5275
5276 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5277 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5278
5279 reset_counter = 0;
5280
5281 while (reset_counter < 2) {
5282 reset_counter++;
5283
5284 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5285
5286 /* Delay for 5 Seconds */
5287 MDELAY(5 * IPS_ONE_SEC);
5288
5289 /* Do a PCI config read to wait for adapter */
5290 pci_read_config_byte(ha->pcidev, 4, &junk);
5291
5292 if ((*ha->func.init) (ha))
5293 break;
5294 else if (reset_counter >= 2) {
5295
5296 return (0);
5297 }
5298 }
5299
5300 return (1);
5301}
5302
5303/****************************************************************************/
5304/* */
5305/* Routine Name: ips_statinit */
5306/* */
5307/* Routine Description: */
5308/* */
5309/* Initialize the status queues on the controller */
5310/* */
5311/****************************************************************************/
5312static void
5313ips_statinit(ips_ha_t * ha)
5314{
5315 uint32_t phys_status_start;
5316
5317 METHOD_TRACE("ips_statinit", 1);
5318
5319 ha->adapt->p_status_start = ha->adapt->status;
5320 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5321 ha->adapt->p_status_tail = ha->adapt->status;
5322
5323 phys_status_start = ha->adapt->hw_status_start;
5324 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5325 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5326 ha->io_addr + IPS_REG_SQER);
5327 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5328 ha->io_addr + IPS_REG_SQHR);
5329 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5330
5331 ha->adapt->hw_status_tail = phys_status_start;
5332}
5333
5334/****************************************************************************/
5335/* */
5336/* Routine Name: ips_statinit_memio */
5337/* */
5338/* Routine Description: */
5339/* */
5340/* Initialize the status queues on the controller */
5341/* */
5342/****************************************************************************/
5343static void
5344ips_statinit_memio(ips_ha_t * ha)
5345{
5346 uint32_t phys_status_start;
5347
5348 METHOD_TRACE("ips_statinit_memio", 1);
5349
5350 ha->adapt->p_status_start = ha->adapt->status;
5351 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5352 ha->adapt->p_status_tail = ha->adapt->status;
5353
5354 phys_status_start = ha->adapt->hw_status_start;
5355 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5356 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5357 ha->mem_ptr + IPS_REG_SQER);
5358 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5359 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5360
5361 ha->adapt->hw_status_tail = phys_status_start;
5362}
5363
5364/****************************************************************************/
5365/* */
5366/* Routine Name: ips_statupd_copperhead */
5367/* */
5368/* Routine Description: */
5369/* */
5370/* Remove an element from the status queue */
5371/* */
5372/****************************************************************************/
5373static uint32_t
5374ips_statupd_copperhead(ips_ha_t * ha)
5375{
5376 METHOD_TRACE("ips_statupd_copperhead", 1);
5377
5378 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5379 ha->adapt->p_status_tail++;
5380 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5381 } else {
5382 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5383 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5384 }
5385
5386 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5387 ha->io_addr + IPS_REG_SQTR);
5388
5389 return (ha->adapt->p_status_tail->value);
5390}
5391
5392/****************************************************************************/
5393/* */
5394/* Routine Name: ips_statupd_copperhead_memio */
5395/* */
5396/* Routine Description: */
5397/* */
5398/* Remove an element from the status queue */
5399/* */
5400/****************************************************************************/
5401static uint32_t
5402ips_statupd_copperhead_memio(ips_ha_t * ha)
5403{
5404 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5405
5406 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5407 ha->adapt->p_status_tail++;
5408 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5409 } else {
5410 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5411 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5412 }
5413
5414 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5415
5416 return (ha->adapt->p_status_tail->value);
5417}
5418
5419/****************************************************************************/
5420/* */
5421/* Routine Name: ips_statupd_morpheus */
5422/* */
5423/* Routine Description: */
5424/* */
5425/* Remove an element from the status queue */
5426/* */
5427/****************************************************************************/
5428static uint32_t
5429ips_statupd_morpheus(ips_ha_t * ha)
5430{
5431 uint32_t val;
5432
5433 METHOD_TRACE("ips_statupd_morpheus", 1);
5434
5435 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5436
5437 return (val);
5438}
5439
5440/****************************************************************************/
5441/* */
5442/* Routine Name: ips_issue_copperhead */
5443/* */
5444/* Routine Description: */
5445/* */
5446/* Send a command down to the controller */
5447/* */
5448/****************************************************************************/
5449static int
5450ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5451{
5452 uint32_t TimeOut;
5453 uint32_t val;
5454
5455 METHOD_TRACE("ips_issue_copperhead", 1);
5456
5457 if (scb->scsi_cmd) {
5458 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5459 ips_name,
5460 ha->host_num,
5461 scb->cdb[0],
5462 scb->cmd.basic_io.command_id,
5463 scb->bus, scb->target_id, scb->lun);
5464 } else {
5465 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5466 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5467 }
5468
5469 TimeOut = 0;
5470
5471 while ((val =
5472 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5473 udelay(1000);
5474
5475 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5476 if (!(val & IPS_BIT_START_STOP))
5477 break;
5478
5479 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5480 "ips_issue val [0x%x].\n", val);
5481 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5482 "ips_issue semaphore chk timeout.\n");
5483
5484 return (IPS_FAILURE);
5485 } /* end if */
5486 } /* end while */
5487
5488 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5489 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5490
5491 return (IPS_SUCCESS);
5492}
5493
5494/****************************************************************************/
5495/* */
5496/* Routine Name: ips_issue_copperhead_memio */
5497/* */
5498/* Routine Description: */
5499/* */
5500/* Send a command down to the controller */
5501/* */
5502/****************************************************************************/
5503static int
5504ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5505{
5506 uint32_t TimeOut;
5507 uint32_t val;
5508
5509 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5510
5511 if (scb->scsi_cmd) {
5512 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5513 ips_name,
5514 ha->host_num,
5515 scb->cdb[0],
5516 scb->cmd.basic_io.command_id,
5517 scb->bus, scb->target_id, scb->lun);
5518 } else {
5519 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5520 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5521 }
5522
5523 TimeOut = 0;
5524
5525 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5526 udelay(1000);
5527
5528 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5529 if (!(val & IPS_BIT_START_STOP))
5530 break;
5531
5532 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5533 "ips_issue val [0x%x].\n", val);
5534 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5535 "ips_issue semaphore chk timeout.\n");
5536
5537 return (IPS_FAILURE);
5538 } /* end if */
5539 } /* end while */
5540
5541 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5542 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5543
5544 return (IPS_SUCCESS);
5545}
5546
5547/****************************************************************************/
5548/* */
5549/* Routine Name: ips_issue_i2o */
5550/* */
5551/* Routine Description: */
5552/* */
5553/* Send a command down to the controller */
5554/* */
5555/****************************************************************************/
5556static int
5557ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5558{
5559
5560 METHOD_TRACE("ips_issue_i2o", 1);
5561
5562 if (scb->scsi_cmd) {
5563 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5564 ips_name,
5565 ha->host_num,
5566 scb->cdb[0],
5567 scb->cmd.basic_io.command_id,
5568 scb->bus, scb->target_id, scb->lun);
5569 } else {
5570 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5571 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5572 }
5573
5574 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5575
5576 return (IPS_SUCCESS);
5577}
5578
5579/****************************************************************************/
5580/* */
5581/* Routine Name: ips_issue_i2o_memio */
5582/* */
5583/* Routine Description: */
5584/* */
5585/* Send a command down to the controller */
5586/* */
5587/****************************************************************************/
5588static int
5589ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5590{
5591
5592 METHOD_TRACE("ips_issue_i2o_memio", 1);
5593
5594 if (scb->scsi_cmd) {
5595 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5596 ips_name,
5597 ha->host_num,
5598 scb->cdb[0],
5599 scb->cmd.basic_io.command_id,
5600 scb->bus, scb->target_id, scb->lun);
5601 } else {
5602 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5603 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5604 }
5605
5606 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5607
5608 return (IPS_SUCCESS);
5609}
5610
5611/****************************************************************************/
5612/* */
5613/* Routine Name: ips_isintr_copperhead */
5614/* */
5615/* Routine Description: */
5616/* */
5617/* Test to see if an interrupt is for us */
5618/* */
5619/****************************************************************************/
5620static int
5621ips_isintr_copperhead(ips_ha_t * ha)
5622{
5623 uint8_t Isr;
5624
5625 METHOD_TRACE("ips_isintr_copperhead", 2);
5626
5627 Isr = inb(ha->io_addr + IPS_REG_HISR);
5628
5629 if (Isr == 0xFF)
5630 /* ?!?! Nothing really there */
5631 return (0);
5632
5633 if (Isr & IPS_BIT_SCE)
5634 return (1);
5635 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5636 /* status queue overflow or GHI */
5637 /* just clear the interrupt */
5638 outb(Isr, ha->io_addr + IPS_REG_HISR);
5639 }
5640
5641 return (0);
5642}
5643
5644/****************************************************************************/
5645/* */
5646/* Routine Name: ips_isintr_copperhead_memio */
5647/* */
5648/* Routine Description: */
5649/* */
5650/* Test to see if an interrupt is for us */
5651/* */
5652/****************************************************************************/
5653static int
5654ips_isintr_copperhead_memio(ips_ha_t * ha)
5655{
5656 uint8_t Isr;
5657
5658 METHOD_TRACE("ips_isintr_memio", 2);
5659
5660 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5661
5662 if (Isr == 0xFF)
5663 /* ?!?! Nothing really there */
5664 return (0);
5665
5666 if (Isr & IPS_BIT_SCE)
5667 return (1);
5668 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5669 /* status queue overflow or GHI */
5670 /* just clear the interrupt */
5671 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5672 }
5673
5674 return (0);
5675}
5676
5677/****************************************************************************/
5678/* */
5679/* Routine Name: ips_isintr_morpheus */
5680/* */
5681/* Routine Description: */
5682/* */
5683/* Test to see if an interrupt is for us */
5684/* */
5685/****************************************************************************/
5686static int
5687ips_isintr_morpheus(ips_ha_t * ha)
5688{
5689 uint32_t Isr;
5690
5691 METHOD_TRACE("ips_isintr_morpheus", 2);
5692
5693 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5694
5695 if (Isr & IPS_BIT_I2O_OPQI)
5696 return (1);
5697 else
5698 return (0);
5699}
5700
5701/****************************************************************************/
5702/* */
5703/* Routine Name: ips_wait */
5704/* */
5705/* Routine Description: */
5706/* */
5707/* Wait for a command to complete */
5708/* */
5709/****************************************************************************/
5710static int
5711ips_wait(ips_ha_t * ha, int time, int intr)
5712{
5713 int ret;
5714 int done;
5715
5716 METHOD_TRACE("ips_wait", 1);
5717
5718 ret = IPS_FAILURE;
5719 done = FALSE;
5720
5721 time *= IPS_ONE_SEC; /* convert seconds */
5722
5723 while ((time > 0) && (!done)) {
5724 if (intr == IPS_INTR_ON) {
5725 if (ha->waitflag == FALSE) {
5726 ret = IPS_SUCCESS;
5727 done = TRUE;
5728 break;
5729 }
5730 } else if (intr == IPS_INTR_IORL) {
5731 if (ha->waitflag == FALSE) {
5732 /*
5733 * controller generated an interrupt to
5734 * acknowledge completion of the command
5735 * and ips_intr() has serviced the interrupt.
5736 */
5737 ret = IPS_SUCCESS;
5738 done = TRUE;
5739 break;
5740 }
5741
5742 /*
5743 * NOTE: we already have the io_request_lock so
5744 * even if we get an interrupt it won't get serviced
5745 * until after we finish.
5746 */
5747
5748 (*ha->func.intr) (ha);
5749 }
5750
5751 /* This looks like a very evil loop, but it only does this during start-up */
5752 udelay(1000);
5753 time--;
5754 }
5755
5756 return (ret);
5757}
5758
5759/****************************************************************************/
5760/* */
5761/* Routine Name: ips_write_driver_status */
5762/* */
5763/* Routine Description: */
5764/* */
5765/* Write OS/Driver version to Page 5 of the nvram on the controller */
5766/* */
5767/****************************************************************************/
5768static int
5769ips_write_driver_status(ips_ha_t * ha, int intr)
5770{
5771 METHOD_TRACE("ips_write_driver_status", 1);
5772
5773 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5774 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5775 "unable to read NVRAM page 5.\n");
5776
5777 return (0);
5778 }
5779
5780 /* check to make sure the page has a valid */
5781 /* signature */
5782 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5783 DEBUG_VAR(1,
5784 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5785 ips_name, ha->host_num, ha->nvram->signature);
5786 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5787 }
5788
5789 DEBUG_VAR(2,
5790 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5791 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5792 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5793 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5794 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5795 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5796 ha->nvram->bios_low[3]);
5797
5798 ips_get_bios_version(ha, intr);
5799
5800 /* change values (as needed) */
5801 ha->nvram->operating_system = IPS_OS_LINUX;
5802 ha->nvram->adapter_type = ha->ad_type;
5803 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5804 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5805 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5806 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5807
5808 ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
5809
5810 /* now update the page */
5811 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5812 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5813 "unable to write NVRAM page 5.\n");
5814
5815 return (0);
5816 }
5817
5818 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5819 ha->slot_num = ha->nvram->adapter_slot;
5820
5821 return (1);
5822}
5823
5824/****************************************************************************/
5825/* */
5826/* Routine Name: ips_read_adapter_status */
5827/* */
5828/* Routine Description: */
5829/* */
5830/* Do an Inquiry command to the adapter */
5831/* */
5832/****************************************************************************/
5833static int
5834ips_read_adapter_status(ips_ha_t * ha, int intr)
5835{
5836 ips_scb_t *scb;
5837 int ret;
5838
5839 METHOD_TRACE("ips_read_adapter_status", 1);
5840
5841 scb = &ha->scbs[ha->max_cmds - 1];
5842
5843 ips_init_scb(ha, scb);
5844
5845 scb->timeout = ips_cmd_timeout;
5846 scb->cdb[0] = IPS_CMD_ENQUIRY;
5847
5848 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5849 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5850 scb->cmd.basic_io.sg_count = 0;
5851 scb->cmd.basic_io.lba = 0;
5852 scb->cmd.basic_io.sector_count = 0;
5853 scb->cmd.basic_io.log_drv = 0;
5854 scb->data_len = sizeof (*ha->enq);
5855 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5856
5857 /* send command */
5858 if (((ret =
5859 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5860 || (ret == IPS_SUCCESS_IMM)
5861 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5862 return (0);
5863
5864 return (1);
5865}
5866
5867/****************************************************************************/
5868/* */
5869/* Routine Name: ips_read_subsystem_parameters */
5870/* */
5871/* Routine Description: */
5872/* */
5873/* Read subsystem parameters from the adapter */
5874/* */
5875/****************************************************************************/
5876static int
5877ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5878{
5879 ips_scb_t *scb;
5880 int ret;
5881
5882 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5883
5884 scb = &ha->scbs[ha->max_cmds - 1];
5885
5886 ips_init_scb(ha, scb);
5887
5888 scb->timeout = ips_cmd_timeout;
5889 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5890
5891 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5892 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5893 scb->cmd.basic_io.sg_count = 0;
5894 scb->cmd.basic_io.lba = 0;
5895 scb->cmd.basic_io.sector_count = 0;
5896 scb->cmd.basic_io.log_drv = 0;
5897 scb->data_len = sizeof (*ha->subsys);
5898 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5899
5900 /* send command */
5901 if (((ret =
5902 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5903 || (ret == IPS_SUCCESS_IMM)
5904 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5905 return (0);
5906
5907 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5908 return (1);
5909}
5910
5911/****************************************************************************/
5912/* */
5913/* Routine Name: ips_read_config */
5914/* */
5915/* Routine Description: */
5916/* */
5917/* Read the configuration on the adapter */
5918/* */
5919/****************************************************************************/
5920static int
5921ips_read_config(ips_ha_t * ha, int intr)
5922{
5923 ips_scb_t *scb;
5924 int i;
5925 int ret;
5926
5927 METHOD_TRACE("ips_read_config", 1);
5928
5929 /* set defaults for initiator IDs */
5930 for (i = 0; i < 4; i++)
5931 ha->conf->init_id[i] = 7;
5932
5933 scb = &ha->scbs[ha->max_cmds - 1];
5934
5935 ips_init_scb(ha, scb);
5936
5937 scb->timeout = ips_cmd_timeout;
5938 scb->cdb[0] = IPS_CMD_READ_CONF;
5939
5940 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5941 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5942 scb->data_len = sizeof (*ha->conf);
5943 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5944
5945 /* send command */
5946 if (((ret =
5947 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5948 || (ret == IPS_SUCCESS_IMM)
5949 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5950
5951 memset(ha->conf, 0, sizeof (IPS_CONF));
5952
5953 /* reset initiator IDs */
5954 for (i = 0; i < 4; i++)
5955 ha->conf->init_id[i] = 7;
5956
5957 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5958 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5959 IPS_CMD_CMPLT_WERROR)
5960 return (1);
5961
5962 return (0);
5963 }
5964
5965 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5966 return (1);
5967}
5968
5969/****************************************************************************/
5970/* */
5971/* Routine Name: ips_readwrite_page5 */
5972/* */
5973/* Routine Description: */
5974/* */
5975/* Read nvram page 5 from the adapter */
5976/* */
5977/****************************************************************************/
5978static int
5979ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5980{
5981 ips_scb_t *scb;
5982 int ret;
5983
5984 METHOD_TRACE("ips_readwrite_page5", 1);
5985
5986 scb = &ha->scbs[ha->max_cmds - 1];
5987
5988 ips_init_scb(ha, scb);
5989
5990 scb->timeout = ips_cmd_timeout;
5991 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5992
5993 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5994 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5995 scb->cmd.nvram.page = 5;
5996 scb->cmd.nvram.write = write;
5997 scb->cmd.nvram.reserved = 0;
5998 scb->cmd.nvram.reserved2 = 0;
5999 scb->data_len = sizeof (*ha->nvram);
6000 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
6001 if (write)
6002 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
6003
6004 /* issue the command */
6005 if (((ret =
6006 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6007 || (ret == IPS_SUCCESS_IMM)
6008 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
6009
6010 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6011
6012 return (0);
6013 }
6014 if (!write)
6015 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6016 return (1);
6017}
6018
6019/****************************************************************************/
6020/* */
6021/* Routine Name: ips_clear_adapter */
6022/* */
6023/* Routine Description: */
6024/* */
6025/* Clear the stripe lock tables */
6026/* */
6027/****************************************************************************/
6028static int
6029ips_clear_adapter(ips_ha_t * ha, int intr)
6030{
6031 ips_scb_t *scb;
6032 int ret;
6033
6034 METHOD_TRACE("ips_clear_adapter", 1);
6035
6036 scb = &ha->scbs[ha->max_cmds - 1];
6037
6038 ips_init_scb(ha, scb);
6039
6040 scb->timeout = ips_reset_timeout;
6041 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
6042
6043 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
6044 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6045 scb->cmd.config_sync.channel = 0;
6046 scb->cmd.config_sync.source_target = IPS_POCL;
6047 scb->cmd.config_sync.reserved = 0;
6048 scb->cmd.config_sync.reserved2 = 0;
6049 scb->cmd.config_sync.reserved3 = 0;
6050
6051 /* issue command */
6052 if (((ret =
6053 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6054 || (ret == IPS_SUCCESS_IMM)
6055 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6056 return (0);
6057
6058 /* send unlock stripe command */
6059 ips_init_scb(ha, scb);
6060
6061 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6062 scb->timeout = ips_reset_timeout;
6063
6064 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6065 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6066 scb->cmd.unlock_stripe.log_drv = 0;
6067 scb->cmd.unlock_stripe.control = IPS_CSL;
6068 scb->cmd.unlock_stripe.reserved = 0;
6069 scb->cmd.unlock_stripe.reserved2 = 0;
6070 scb->cmd.unlock_stripe.reserved3 = 0;
6071
6072 /* issue command */
6073 if (((ret =
6074 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6075 || (ret == IPS_SUCCESS_IMM)
6076 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6077 return (0);
6078
6079 return (1);
6080}
6081
6082/****************************************************************************/
6083/* */
6084/* Routine Name: ips_ffdc_reset */
6085/* */
6086/* Routine Description: */
6087/* */
6088/* FFDC: write reset info */
6089/* */
6090/****************************************************************************/
6091static void
6092ips_ffdc_reset(ips_ha_t * ha, int intr)
6093{
6094 ips_scb_t *scb;
6095
6096 METHOD_TRACE("ips_ffdc_reset", 1);
6097
6098 scb = &ha->scbs[ha->max_cmds - 1];
6099
6100 ips_init_scb(ha, scb);
6101
6102 scb->timeout = ips_cmd_timeout;
6103 scb->cdb[0] = IPS_CMD_FFDC;
6104 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6105 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6106 scb->cmd.ffdc.reset_count = ha->reset_count;
6107 scb->cmd.ffdc.reset_type = 0x80;
6108
6109 /* convert time to what the card wants */
6110 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6111
6112 /* issue command */
6113 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6114}
6115
6116/****************************************************************************/
6117/* */
6118/* Routine Name: ips_ffdc_time */
6119/* */
6120/* Routine Description: */
6121/* */
6122/* FFDC: write time info */
6123/* */
6124/****************************************************************************/
6125static void
6126ips_ffdc_time(ips_ha_t * ha)
6127{
6128 ips_scb_t *scb;
6129
6130 METHOD_TRACE("ips_ffdc_time", 1);
6131
6132 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6133
6134 scb = &ha->scbs[ha->max_cmds - 1];
6135
6136 ips_init_scb(ha, scb);
6137
6138 scb->timeout = ips_cmd_timeout;
6139 scb->cdb[0] = IPS_CMD_FFDC;
6140 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6141 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6142 scb->cmd.ffdc.reset_count = 0;
6143 scb->cmd.ffdc.reset_type = 0;
6144
6145 /* convert time to what the card wants */
6146 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6147
6148 /* issue command */
6149 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6150}
6151
6152/****************************************************************************/
6153/* */
6154/* Routine Name: ips_fix_ffdc_time */
6155/* */
6156/* Routine Description: */
6157/* Adjust time_t to what the card wants */
6158/* */
6159/****************************************************************************/
6160static void
6161ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6162{
6163 long days;
6164 long rem;
6165 int i;
6166 int year;
6167 int yleap;
6168 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6169 int month_lengths[12][2] = { {31, 31},
6170 {28, 29},
6171 {31, 31},
6172 {30, 30},
6173 {31, 31},
6174 {30, 30},
6175 {31, 31},
6176 {31, 31},
6177 {30, 30},
6178 {31, 31},
6179 {30, 30},
6180 {31, 31}
6181 };
6182
6183 METHOD_TRACE("ips_fix_ffdc_time", 1);
6184
6185 days = current_time / IPS_SECS_DAY;
6186 rem = current_time % IPS_SECS_DAY;
6187
6188 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6189 rem = rem % IPS_SECS_HOUR;
6190 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6191 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6192
6193 year = IPS_EPOCH_YEAR;
6194 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6195 int newy;
6196
6197 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6198 if (days < 0)
6199 --newy;
6200 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6201 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6202 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6203 year = newy;
6204 }
6205
6206 scb->cmd.ffdc.yearH = year / 100;
6207 scb->cmd.ffdc.yearL = year % 100;
6208
6209 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6210 days -= month_lengths[i][yleap];
6211
6212 scb->cmd.ffdc.month = i + 1;
6213 scb->cmd.ffdc.day = days + 1;
6214}
6215
6216/****************************************************************************
6217 * BIOS Flash Routines *
6218 ****************************************************************************/
6219
6220/****************************************************************************/
6221/* */
6222/* Routine Name: ips_erase_bios */
6223/* */
6224/* Routine Description: */
6225/* Erase the BIOS on the adapter */
6226/* */
6227/****************************************************************************/
6228static int
6229ips_erase_bios(ips_ha_t * ha)
6230{
6231 int timeout;
6232 uint8_t status = 0;
6233
6234 METHOD_TRACE("ips_erase_bios", 1);
6235
6236 status = 0;
6237
6238 /* Clear the status register */
6239 outl(0, ha->io_addr + IPS_REG_FLAP);
6240 if (ha->revision_id == IPS_REVID_TROMBONE64)
6241 udelay(25); /* 25 us */
6242
6243 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6244 if (ha->revision_id == IPS_REVID_TROMBONE64)
6245 udelay(25); /* 25 us */
6246
6247 /* Erase Setup */
6248 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6249 if (ha->revision_id == IPS_REVID_TROMBONE64)
6250 udelay(25); /* 25 us */
6251
6252 /* Erase Confirm */
6253 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6254 if (ha->revision_id == IPS_REVID_TROMBONE64)
6255 udelay(25); /* 25 us */
6256
6257 /* Erase Status */
6258 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6259 if (ha->revision_id == IPS_REVID_TROMBONE64)
6260 udelay(25); /* 25 us */
6261
6262 timeout = 80000; /* 80 seconds */
6263
6264 while (timeout > 0) {
6265 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6266 outl(0, ha->io_addr + IPS_REG_FLAP);
6267 udelay(25); /* 25 us */
6268 }
6269
6270 status = inb(ha->io_addr + IPS_REG_FLDP);
6271
6272 if (status & 0x80)
6273 break;
6274
6275 MDELAY(1);
6276 timeout--;
6277 }
6278
6279 /* check for timeout */
6280 if (timeout <= 0) {
6281 /* timeout */
6282
6283 /* try to suspend the erase */
6284 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6285 if (ha->revision_id == IPS_REVID_TROMBONE64)
6286 udelay(25); /* 25 us */
6287
6288 /* wait for 10 seconds */
6289 timeout = 10000;
6290 while (timeout > 0) {
6291 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6292 outl(0, ha->io_addr + IPS_REG_FLAP);
6293 udelay(25); /* 25 us */
6294 }
6295
6296 status = inb(ha->io_addr + IPS_REG_FLDP);
6297
6298 if (status & 0xC0)
6299 break;
6300
6301 MDELAY(1);
6302 timeout--;
6303 }
6304
6305 return (1);
6306 }
6307
6308 /* check for valid VPP */
6309 if (status & 0x08)
6310 /* VPP failure */
6311 return (1);
6312
6313 /* check for succesful flash */
6314 if (status & 0x30)
6315 /* sequence error */
6316 return (1);
6317
6318 /* Otherwise, we were successful */
6319 /* clear status */
6320 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6321 if (ha->revision_id == IPS_REVID_TROMBONE64)
6322 udelay(25); /* 25 us */
6323
6324 /* enable reads */
6325 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6326 if (ha->revision_id == IPS_REVID_TROMBONE64)
6327 udelay(25); /* 25 us */
6328
6329 return (0);
6330}
6331
6332/****************************************************************************/
6333/* */
6334/* Routine Name: ips_erase_bios_memio */
6335/* */
6336/* Routine Description: */
6337/* Erase the BIOS on the adapter */
6338/* */
6339/****************************************************************************/
6340static int
6341ips_erase_bios_memio(ips_ha_t * ha)
6342{
6343 int timeout;
6344 uint8_t status;
6345
6346 METHOD_TRACE("ips_erase_bios_memio", 1);
6347
6348 status = 0;
6349
6350 /* Clear the status register */
6351 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6352 if (ha->revision_id == IPS_REVID_TROMBONE64)
6353 udelay(25); /* 25 us */
6354
6355 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6356 if (ha->revision_id == IPS_REVID_TROMBONE64)
6357 udelay(25); /* 25 us */
6358
6359 /* Erase Setup */
6360 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6361 if (ha->revision_id == IPS_REVID_TROMBONE64)
6362 udelay(25); /* 25 us */
6363
6364 /* Erase Confirm */
6365 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6366 if (ha->revision_id == IPS_REVID_TROMBONE64)
6367 udelay(25); /* 25 us */
6368
6369 /* Erase Status */
6370 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6371 if (ha->revision_id == IPS_REVID_TROMBONE64)
6372 udelay(25); /* 25 us */
6373
6374 timeout = 80000; /* 80 seconds */
6375
6376 while (timeout > 0) {
6377 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6378 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6379 udelay(25); /* 25 us */
6380 }
6381
6382 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6383
6384 if (status & 0x80)
6385 break;
6386
6387 MDELAY(1);
6388 timeout--;
6389 }
6390
6391 /* check for timeout */
6392 if (timeout <= 0) {
6393 /* timeout */
6394
6395 /* try to suspend the erase */
6396 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6397 if (ha->revision_id == IPS_REVID_TROMBONE64)
6398 udelay(25); /* 25 us */
6399
6400 /* wait for 10 seconds */
6401 timeout = 10000;
6402 while (timeout > 0) {
6403 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6404 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6405 udelay(25); /* 25 us */
6406 }
6407
6408 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6409
6410 if (status & 0xC0)
6411 break;
6412
6413 MDELAY(1);
6414 timeout--;
6415 }
6416
6417 return (1);
6418 }
6419
6420 /* check for valid VPP */
6421 if (status & 0x08)
6422 /* VPP failure */
6423 return (1);
6424
6425 /* check for succesful flash */
6426 if (status & 0x30)
6427 /* sequence error */
6428 return (1);
6429
6430 /* Otherwise, we were successful */
6431 /* clear status */
6432 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6433 if (ha->revision_id == IPS_REVID_TROMBONE64)
6434 udelay(25); /* 25 us */
6435
6436 /* enable reads */
6437 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6438 if (ha->revision_id == IPS_REVID_TROMBONE64)
6439 udelay(25); /* 25 us */
6440
6441 return (0);
6442}
6443
6444/****************************************************************************/
6445/* */
6446/* Routine Name: ips_program_bios */
6447/* */
6448/* Routine Description: */
6449/* Program the BIOS on the adapter */
6450/* */
6451/****************************************************************************/
6452static int
6453ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6454 uint32_t offset)
6455{
6456 int i;
6457 int timeout;
6458 uint8_t status = 0;
6459
6460 METHOD_TRACE("ips_program_bios", 1);
6461
6462 status = 0;
6463
6464 for (i = 0; i < buffersize; i++) {
6465 /* write a byte */
6466 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6467 if (ha->revision_id == IPS_REVID_TROMBONE64)
6468 udelay(25); /* 25 us */
6469
6470 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6471 if (ha->revision_id == IPS_REVID_TROMBONE64)
6472 udelay(25); /* 25 us */
6473
6474 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6475 if (ha->revision_id == IPS_REVID_TROMBONE64)
6476 udelay(25); /* 25 us */
6477
6478 /* wait up to one second */
6479 timeout = 1000;
6480 while (timeout > 0) {
6481 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6482 outl(0, ha->io_addr + IPS_REG_FLAP);
6483 udelay(25); /* 25 us */
6484 }
6485
6486 status = inb(ha->io_addr + IPS_REG_FLDP);
6487
6488 if (status & 0x80)
6489 break;
6490
6491 MDELAY(1);
6492 timeout--;
6493 }
6494
6495 if (timeout == 0) {
6496 /* timeout error */
6497 outl(0, ha->io_addr + IPS_REG_FLAP);
6498 if (ha->revision_id == IPS_REVID_TROMBONE64)
6499 udelay(25); /* 25 us */
6500
6501 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6502 if (ha->revision_id == IPS_REVID_TROMBONE64)
6503 udelay(25); /* 25 us */
6504
6505 return (1);
6506 }
6507
6508 /* check the status */
6509 if (status & 0x18) {
6510 /* programming error */
6511 outl(0, ha->io_addr + IPS_REG_FLAP);
6512 if (ha->revision_id == IPS_REVID_TROMBONE64)
6513 udelay(25); /* 25 us */
6514
6515 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6516 if (ha->revision_id == IPS_REVID_TROMBONE64)
6517 udelay(25); /* 25 us */
6518
6519 return (1);
6520 }
6521 } /* end for */
6522
6523 /* Enable reading */
6524 outl(0, ha->io_addr + IPS_REG_FLAP);
6525 if (ha->revision_id == IPS_REVID_TROMBONE64)
6526 udelay(25); /* 25 us */
6527
6528 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6529 if (ha->revision_id == IPS_REVID_TROMBONE64)
6530 udelay(25); /* 25 us */
6531
6532 return (0);
6533}
6534
6535/****************************************************************************/
6536/* */
6537/* Routine Name: ips_program_bios_memio */
6538/* */
6539/* Routine Description: */
6540/* Program the BIOS on the adapter */
6541/* */
6542/****************************************************************************/
6543static int
6544ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6545 uint32_t offset)
6546{
6547 int i;
6548 int timeout;
6549 uint8_t status = 0;
6550
6551 METHOD_TRACE("ips_program_bios_memio", 1);
6552
6553 status = 0;
6554
6555 for (i = 0; i < buffersize; i++) {
6556 /* write a byte */
6557 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6558 if (ha->revision_id == IPS_REVID_TROMBONE64)
6559 udelay(25); /* 25 us */
6560
6561 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6562 if (ha->revision_id == IPS_REVID_TROMBONE64)
6563 udelay(25); /* 25 us */
6564
6565 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6566 if (ha->revision_id == IPS_REVID_TROMBONE64)
6567 udelay(25); /* 25 us */
6568
6569 /* wait up to one second */
6570 timeout = 1000;
6571 while (timeout > 0) {
6572 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6573 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6574 udelay(25); /* 25 us */
6575 }
6576
6577 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6578
6579 if (status & 0x80)
6580 break;
6581
6582 MDELAY(1);
6583 timeout--;
6584 }
6585
6586 if (timeout == 0) {
6587 /* timeout error */
6588 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6589 if (ha->revision_id == IPS_REVID_TROMBONE64)
6590 udelay(25); /* 25 us */
6591
6592 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6593 if (ha->revision_id == IPS_REVID_TROMBONE64)
6594 udelay(25); /* 25 us */
6595
6596 return (1);
6597 }
6598
6599 /* check the status */
6600 if (status & 0x18) {
6601 /* programming error */
6602 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6603 if (ha->revision_id == IPS_REVID_TROMBONE64)
6604 udelay(25); /* 25 us */
6605
6606 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6607 if (ha->revision_id == IPS_REVID_TROMBONE64)
6608 udelay(25); /* 25 us */
6609
6610 return (1);
6611 }
6612 } /* end for */
6613
6614 /* Enable reading */
6615 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6616 if (ha->revision_id == IPS_REVID_TROMBONE64)
6617 udelay(25); /* 25 us */
6618
6619 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6620 if (ha->revision_id == IPS_REVID_TROMBONE64)
6621 udelay(25); /* 25 us */
6622
6623 return (0);
6624}
6625
6626/****************************************************************************/
6627/* */
6628/* Routine Name: ips_verify_bios */
6629/* */
6630/* Routine Description: */
6631/* Verify the BIOS on the adapter */
6632/* */
6633/****************************************************************************/
6634static int
6635ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6636 uint32_t offset)
6637{
6638 uint8_t checksum;
6639 int i;
6640
6641 METHOD_TRACE("ips_verify_bios", 1);
6642
6643 /* test 1st byte */
6644 outl(0, ha->io_addr + IPS_REG_FLAP);
6645 if (ha->revision_id == IPS_REVID_TROMBONE64)
6646 udelay(25); /* 25 us */
6647
6648 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6649 return (1);
6650
6651 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6652 if (ha->revision_id == IPS_REVID_TROMBONE64)
6653 udelay(25); /* 25 us */
6654 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6655 return (1);
6656
6657 checksum = 0xff;
6658 for (i = 2; i < buffersize; i++) {
6659
6660 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6661 if (ha->revision_id == IPS_REVID_TROMBONE64)
6662 udelay(25); /* 25 us */
6663
6664 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6665 }
6666
6667 if (checksum != 0)
6668 /* failure */
6669 return (1);
6670 else
6671 /* success */
6672 return (0);
6673}
6674
6675/****************************************************************************/
6676/* */
6677/* Routine Name: ips_verify_bios_memio */
6678/* */
6679/* Routine Description: */
6680/* Verify the BIOS on the adapter */
6681/* */
6682/****************************************************************************/
6683static int
6684ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6685 uint32_t offset)
6686{
6687 uint8_t checksum;
6688 int i;
6689
6690 METHOD_TRACE("ips_verify_bios_memio", 1);
6691
6692 /* test 1st byte */
6693 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6694 if (ha->revision_id == IPS_REVID_TROMBONE64)
6695 udelay(25); /* 25 us */
6696
6697 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6698 return (1);
6699
6700 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6701 if (ha->revision_id == IPS_REVID_TROMBONE64)
6702 udelay(25); /* 25 us */
6703 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6704 return (1);
6705
6706 checksum = 0xff;
6707 for (i = 2; i < buffersize; i++) {
6708
6709 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6710 if (ha->revision_id == IPS_REVID_TROMBONE64)
6711 udelay(25); /* 25 us */
6712
6713 checksum =
6714 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6715 }
6716
6717 if (checksum != 0)
6718 /* failure */
6719 return (1);
6720 else
6721 /* success */
6722 return (0);
6723}
6724
6725/*---------------------------------------------------------------------------*/
6726/* Routine Name: ips_version_check */
6727/* */
6728/* Dependencies: */
6729/* Assumes that ips_read_adapter_status() is called first filling in */
6730/* the data for SubSystem Parameters. */
6731/* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
6732/* Data is available. */
6733/* */
6734/*---------------------------------------------------------------------------*/
6735static void
6736ips_version_check(ips_ha_t * ha, int intr)
6737{
6738 IPS_VERSION_DATA *VersionInfo;
6739 uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
6740 uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
6741 int MatchError;
6742 int rc;
6743 char BiosString[10];
6744 char FirmwareString[10];
6745
6746 METHOD_TRACE("ips_version_check", 1);
6747
6748 VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
6749
6750 memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6751 memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6752
6753 /* Get the Compatible BIOS Version from NVRAM Page 5 */
6754 memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
6755 IPS_COMPAT_ID_LENGTH);
6756
6757 rc = IPS_FAILURE;
6758 if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
6759 /* Get the Version Info with a Get Version Command */
6760 memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
6761 rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
6762 if (rc == IPS_SUCCESS)
6763 memcpy(FirmwareVersion, VersionInfo->compatibilityId,
6764 IPS_COMPAT_ID_LENGTH);
6765 }
6766
6767 if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
6768 /* Get the Firmware Version from Enquiry Data */
6769 memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
6770 IPS_COMPAT_ID_LENGTH);
6771 }
6772
6773 /* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
6774 /* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
6775 /* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
6776 /* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
6777
6778 MatchError = 0;
6779
6780 if (strncmp
6781 (FirmwareVersion, Compatable[ha->nvram->adapter_type],
6782 IPS_COMPAT_ID_LENGTH) != 0)
6783 MatchError = 1;
6784
6785 if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
6786 MatchError = 1;
6787
6788 ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
6789
6790 if (MatchError) {
6791 ha->nvram->version_mismatch = 1;
6792 if (ips_cd_boot == 0) {
6793 strncpy(&BiosString[0], ha->nvram->bios_high, 4);
6794 strncpy(&BiosString[4], ha->nvram->bios_low, 4);
6795 BiosString[8] = 0;
6796
6797 strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
6798 FirmwareString[8] = 0;
6799
6800 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6801 "Warning ! ! ! ServeRAID Version Mismatch\n");
6802 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6803 "Bios = %s, Firmware = %s, Device Driver = %s%s\n",
6804 BiosString, FirmwareString, IPS_VERSION_HIGH,
6805 IPS_VERSION_LOW);
6806 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6807 "These levels should match to avoid possible compatibility problems.\n");
6808 }
6809 } else {
6810 ha->nvram->version_mismatch = 0;
6811 }
6812
6813 return;
6814}
6815
6816/*---------------------------------------------------------------------------*/
6817/* Routine Name: ips_get_version_info */
6818/* */
6819/* Routine Description: */
6820/* Issue an internal GETVERSION Command */
6821/* */
6822/* Return Value: */
6823/* 0 if Successful, else non-zero */
6824/*---------------------------------------------------------------------------*/
6825static int
6826ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
6827{
6828 ips_scb_t *scb;
6829 int rc;
6830
6831 METHOD_TRACE("ips_get_version_info", 1);
6832
6833 scb = &ha->scbs[ha->max_cmds - 1];
6834
6835 ips_init_scb(ha, scb);
6836
6837 scb->timeout = ips_cmd_timeout;
6838 scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
6839 scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
6840 scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
6841 scb->cmd.version_info.reserved = 0;
6842 scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
6843 scb->cmd.version_info.reserved2 = 0;
6844 scb->data_len = sizeof (IPS_VERSION_DATA);
6845 scb->data_busaddr = Buffer;
6846 scb->cmd.version_info.buffer_addr = Buffer;
6847 scb->flags = 0;
6848
6849 /* issue command */
6850 rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6851 return (rc);
6852}
6853
6854/****************************************************************************/
6855/* */
6856/* Routine Name: ips_abort_init */
6857/* */
6858/* Routine Description: */
6859/* cleanup routine for a failed adapter initialization */
6860/****************************************************************************/
6861static int
6862ips_abort_init(ips_ha_t * ha, int index)
6863{
6864 ha->active = 0;
6865 ips_free(ha);
6866 ips_ha[index] = NULL;
6867 ips_sh[index] = NULL;
6868 return -1;
6869}
6870
6871/****************************************************************************/
6872/* */
6873/* Routine Name: ips_shift_controllers */
6874/* */
6875/* Routine Description: */
6876/* helper function for ordering adapters */
6877/****************************************************************************/
6878static void
6879ips_shift_controllers(int lowindex, int highindex)
6880{
6881 ips_ha_t *ha_sav = ips_ha[highindex];
6882 struct Scsi_Host *sh_sav = ips_sh[highindex];
6883 int i;
6884
6885 for (i = highindex; i > lowindex; i--) {
6886 ips_ha[i] = ips_ha[i - 1];
6887 ips_sh[i] = ips_sh[i - 1];
6888 ips_ha[i]->host_num = i;
6889 }
6890 ha_sav->host_num = lowindex;
6891 ips_ha[lowindex] = ha_sav;
6892 ips_sh[lowindex] = sh_sav;
6893}
6894
6895/****************************************************************************/
6896/* */
6897/* Routine Name: ips_order_controllers */
6898/* */
6899/* Routine Description: */
6900/* place controllers is the "proper" boot order */
6901/****************************************************************************/
6902static void
6903ips_order_controllers(void)
6904{
6905 int i, j, tmp, position = 0;
6906 IPS_NVRAM_P5 *nvram;
6907 if (!ips_ha[0])
6908 return;
6909 nvram = ips_ha[0]->nvram;
6910
6911 if (nvram->adapter_order[0]) {
6912 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6913 for (j = position; j < ips_num_controllers; j++) {
6914 switch (ips_ha[j]->ad_type) {
6915 case IPS_ADTYPE_SERVERAID6M:
6916 case IPS_ADTYPE_SERVERAID7M:
6917 if (nvram->adapter_order[i] == 'M') {
6918 ips_shift_controllers(position,
6919 j);
6920 position++;
6921 }
6922 break;
6923 case IPS_ADTYPE_SERVERAID4L:
6924 case IPS_ADTYPE_SERVERAID4M:
6925 case IPS_ADTYPE_SERVERAID4MX:
6926 case IPS_ADTYPE_SERVERAID4LX:
6927 if (nvram->adapter_order[i] == 'N') {
6928 ips_shift_controllers(position,
6929 j);
6930 position++;
6931 }
6932 break;
6933 case IPS_ADTYPE_SERVERAID6I:
6934 case IPS_ADTYPE_SERVERAID5I2:
6935 case IPS_ADTYPE_SERVERAID5I1:
6936 case IPS_ADTYPE_SERVERAID7k:
6937 if (nvram->adapter_order[i] == 'S') {
6938 ips_shift_controllers(position,
6939 j);
6940 position++;
6941 }
6942 break;
6943 case IPS_ADTYPE_SERVERAID:
6944 case IPS_ADTYPE_SERVERAID2:
6945 case IPS_ADTYPE_NAVAJO:
6946 case IPS_ADTYPE_KIOWA:
6947 case IPS_ADTYPE_SERVERAID3L:
6948 case IPS_ADTYPE_SERVERAID3:
6949 case IPS_ADTYPE_SERVERAID4H:
6950 if (nvram->adapter_order[i] == 'A') {
6951 ips_shift_controllers(position,
6952 j);
6953 position++;
6954 }
6955 break;
6956 default:
6957 break;
6958 }
6959 }
6960 }
6961 /* if adapter_order[0], then ordering is complete */
6962 return;
6963 }
6964 /* old bios, use older ordering */
6965 tmp = 0;
6966 for (i = position; i < ips_num_controllers; i++) {
6967 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6968 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6969 ips_shift_controllers(position, i);
6970 position++;
6971 tmp = 1;
6972 }
6973 }
6974 /* if there were no 5I cards, then don't do any extra ordering */
6975 if (!tmp)
6976 return;
6977 for (i = position; i < ips_num_controllers; i++) {
6978 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6979 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6980 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6981 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6982 ips_shift_controllers(position, i);
6983 position++;
6984 }
6985 }
6986
6987 return;
6988}
6989
6990/****************************************************************************/
6991/* */
6992/* Routine Name: ips_register_scsi */
6993/* */
6994/* Routine Description: */
6995/* perform any registration and setup with the scsi layer */
6996/****************************************************************************/
6997static int
6998ips_register_scsi(int index)
6999{
7000 struct Scsi_Host *sh;
7001 ips_ha_t *ha, *oldha = ips_ha[index];
7002 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
7003 if (!sh) {
7004 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
7005 "Unable to register controller with SCSI subsystem\n");
7006 return -1;
7007 }
7008 ha = IPS_HA(sh);
7009 memcpy(ha, oldha, sizeof (ips_ha_t));
7010 free_irq(oldha->irq, oldha);
7011 /* Install the interrupt handler with the new ha */
7012 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7013 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7014 "Unable to install interrupt handler\n");
7015 scsi_host_put(sh);
7016 return -1;
7017 }
7018
7019 kfree(oldha);
7020 ips_sh[index] = sh;
7021 ips_ha[index] = ha;
7022 IPS_SCSI_SET_DEVICE(sh, ha);
7023
7024 /* Store away needed values for later use */
7025 sh->io_port = ha->io_addr;
7026 sh->n_io_port = ha->io_addr ? 255 : 0;
7027 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7028 sh->irq = ha->irq;
7029 sh->sg_tablesize = sh->hostt->sg_tablesize;
7030 sh->can_queue = sh->hostt->can_queue;
7031 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
7032 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
7033 sh->use_clustering = sh->hostt->use_clustering;
7034
7035#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7)
7036 sh->max_sectors = 128;
7037#endif
7038
7039 sh->max_id = ha->ntargets;
7040 sh->max_lun = ha->nlun;
7041 sh->max_channel = ha->nbus - 1;
7042 sh->can_queue = ha->max_cmds - 1;
7043
7044 IPS_ADD_HOST(sh, NULL);
7045 return 0;
7046}
7047
7048/*---------------------------------------------------------------------------*/
7049/* Routine Name: ips_remove_device */
7050/* */
7051/* Routine Description: */
7052/* Remove one Adapter ( Hot Plugging ) */
7053/*---------------------------------------------------------------------------*/
7054static void __devexit
7055ips_remove_device(struct pci_dev *pci_dev)
7056{
7057 int i;
7058 struct Scsi_Host *sh;
7059 ips_ha_t *ha;
7060
7061 for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
7062 ha = ips_ha[i];
7063 if (ha) {
7064 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7065 (pci_dev->devfn == ha->pcidev->devfn)) {
7066 sh = ips_sh[i];
7067 ips_release(sh);
7068 }
7069 }
7070 }
7071}
7072
7073/****************************************************************************/
7074/* */
7075/* Routine Name: ips_module_init */
7076/* */
7077/* Routine Description: */
7078/* function called on module load */
7079/****************************************************************************/
7080static int __init
7081ips_module_init(void)
7082{
7083 if (pci_module_init(&ips_pci_driver) < 0)
7084 return -ENODEV;
7085 ips_driver_template.module = THIS_MODULE;
7086 ips_order_controllers();
7087 if (IPS_REGISTER_HOSTS(&ips_driver_template)) {
7088 pci_unregister_driver(&ips_pci_driver);
7089 return -ENODEV;
7090 }
7091 register_reboot_notifier(&ips_notifier);
7092 return 0;
7093}
7094
7095/****************************************************************************/
7096/* */
7097/* Routine Name: ips_module_exit */
7098/* */
7099/* Routine Description: */
7100/* function called on module unload */
7101/****************************************************************************/
7102static void __exit
7103ips_module_exit(void)
7104{
7105 IPS_UNREGISTER_HOSTS(&ips_driver_template);
7106 pci_unregister_driver(&ips_pci_driver);
7107 unregister_reboot_notifier(&ips_notifier);
7108}
7109
7110module_init(ips_module_init);
7111module_exit(ips_module_exit);
7112
7113/*---------------------------------------------------------------------------*/
7114/* Routine Name: ips_insert_device */
7115/* */
7116/* Routine Description: */
7117/* Add One Adapter ( Hot Plug ) */
7118/* */
7119/* Return Value: */
7120/* 0 if Successful, else non-zero */
7121/*---------------------------------------------------------------------------*/
7122static int __devinit
7123ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
7124{
7125 int index;
7126 int rc;
7127
7128 METHOD_TRACE("ips_insert_device", 1);
7129 if (pci_enable_device(pci_dev))
7130 return -1;
7131
7132 rc = ips_init_phase1(pci_dev, &index);
7133 if (rc == SUCCESS)
7134 rc = ips_init_phase2(index);
7135
7136 if (ips_hotplug)
7137 if (ips_register_scsi(index)) {
7138 ips_free(ips_ha[index]);
7139 rc = -1;
7140 }
7141
7142 if (rc == SUCCESS)
7143 ips_num_controllers++;
7144
7145 ips_next_controller = ips_num_controllers;
7146 return rc;
7147}
7148
7149/*---------------------------------------------------------------------------*/
7150/* Routine Name: ips_init_phase1 */
7151/* */
7152/* Routine Description: */
7153/* Adapter Initialization */
7154/* */
7155/* Return Value: */
7156/* 0 if Successful, else non-zero */
7157/*---------------------------------------------------------------------------*/
7158static int
7159ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7160{
7161 ips_ha_t *ha;
7162 uint32_t io_addr;
7163 uint32_t mem_addr;
7164 uint32_t io_len;
7165 uint32_t mem_len;
7166 uint8_t revision_id;
7167 uint8_t bus;
7168 uint8_t func;
7169 uint8_t irq;
7170 uint16_t subdevice_id;
7171 int j;
7172 int index;
7173 dma_addr_t dma_address;
7174 char __iomem *ioremap_ptr;
7175 char __iomem *mem_ptr;
7176 uint32_t IsDead;
7177
7178 METHOD_TRACE("ips_init_phase1", 1);
7179 index = IPS_MAX_ADAPTERS;
7180 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7181 if (ips_ha[j] == 0) {
7182 index = j;
7183 break;
7184 }
7185 }
7186
7187 if (index >= IPS_MAX_ADAPTERS)
7188 return -1;
7189
7190 /* stuff that we get in dev */
7191 irq = pci_dev->irq;
7192 bus = pci_dev->bus->number;
7193 func = pci_dev->devfn;
7194
7195 /* Init MEM/IO addresses to 0 */
7196 mem_addr = 0;
7197 io_addr = 0;
7198 mem_len = 0;
7199 io_len = 0;
7200
7201 for (j = 0; j < 2; j++) {
7202 if (!pci_resource_start(pci_dev, j))
7203 break;
7204
7205 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7206 io_addr = pci_resource_start(pci_dev, j);
7207 io_len = pci_resource_len(pci_dev, j);
7208 } else {
7209 mem_addr = pci_resource_start(pci_dev, j);
7210 mem_len = pci_resource_len(pci_dev, j);
7211 }
7212 }
7213
7214 /* setup memory mapped area (if applicable) */
7215 if (mem_addr) {
7216 uint32_t base;
7217 uint32_t offs;
7218
7219 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7220 IPS_PRINTK(KERN_WARNING, pci_dev,
7221 "Couldn't allocate IO Memory space %x len %d.\n",
7222 mem_addr, mem_len);
7223 return -1;
7224 }
7225
7226 base = mem_addr & PAGE_MASK;
7227 offs = mem_addr - base;
7228 ioremap_ptr = ioremap(base, PAGE_SIZE);
7229 mem_ptr = ioremap_ptr + offs;
7230 } else {
7231 ioremap_ptr = NULL;
7232 mem_ptr = NULL;
7233 }
7234
7235 /* setup I/O mapped area (if applicable) */
7236 if (io_addr) {
7237 if (!request_region(io_addr, io_len, "ips")) {
7238 IPS_PRINTK(KERN_WARNING, pci_dev,
7239 "Couldn't allocate IO space %x len %d.\n",
7240 io_addr, io_len);
7241 return -1;
7242 }
7243 }
7244
7245 /* get the revision ID */
7246 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
7247 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
7248 return -1;
7249 }
7250
7251 subdevice_id = pci_dev->subsystem_device;
7252
7253 /* found a controller */
7254 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7255 if (ha == NULL) {
7256 IPS_PRINTK(KERN_WARNING, pci_dev,
7257 "Unable to allocate temporary ha struct\n");
7258 return -1;
7259 }
7260
7261 memset(ha, 0, sizeof (ips_ha_t));
7262
7263 ips_sh[index] = NULL;
7264 ips_ha[index] = ha;
7265 ha->active = 1;
7266
7267 /* Store info in HA structure */
7268 ha->irq = irq;
7269 ha->io_addr = io_addr;
7270 ha->io_len = io_len;
7271 ha->mem_addr = mem_addr;
7272 ha->mem_len = mem_len;
7273 ha->mem_ptr = mem_ptr;
7274 ha->ioremap_ptr = ioremap_ptr;
7275 ha->host_num = (uint32_t) index;
7276 ha->revision_id = revision_id;
7277 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7278 ha->device_id = pci_dev->device;
7279 ha->subdevice_id = subdevice_id;
7280 ha->pcidev = pci_dev;
7281
7282 /*
7283 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7284 * addressing so don't enable it if the adapter can't support
7285 * it! Also, don't use 64bit addressing if dma addresses
7286 * are guaranteed to be < 4G.
7287 */
7288 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7289 !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
7290 (ha)->flags |= IPS_HA_ENH_SG;
7291 } else {
7292 if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
7293 printk(KERN_WARNING "Unable to set DMA Mask\n");
7294 return ips_abort_init(ha, index);
7295 }
7296 }
7297 if(ips_cd_boot && !ips_FlashData){
7298 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7299 &ips_flashbusaddr);
7300 }
7301
7302 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7303 &ha->enq_busaddr);
7304 if (!ha->enq) {
7305 IPS_PRINTK(KERN_WARNING, pci_dev,
7306 "Unable to allocate host inquiry structure\n");
7307 return ips_abort_init(ha, index);
7308 }
7309
7310 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7311 sizeof (IPS_IO_CMD), &dma_address);
7312 if (!ha->adapt) {
7313 IPS_PRINTK(KERN_WARNING, pci_dev,
7314 "Unable to allocate host adapt & dummy structures\n");
7315 return ips_abort_init(ha, index);
7316 }
7317 ha->adapt->hw_status_start = dma_address;
7318 ha->dummy = (void *) (ha->adapt + 1);
7319
7320
7321
7322 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7323 if (!ha->logical_drive_info) {
7324 IPS_PRINTK(KERN_WARNING, pci_dev,
7325 "Unable to allocate logical drive info structure\n");
7326 return ips_abort_init(ha, index);
7327 }
7328 ha->logical_drive_info_dma_addr = dma_address;
7329
7330
7331 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7332
7333 if (!ha->conf) {
7334 IPS_PRINTK(KERN_WARNING, pci_dev,
7335 "Unable to allocate host conf structure\n");
7336 return ips_abort_init(ha, index);
7337 }
7338
7339 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7340
7341 if (!ha->nvram) {
7342 IPS_PRINTK(KERN_WARNING, pci_dev,
7343 "Unable to allocate host NVRAM structure\n");
7344 return ips_abort_init(ha, index);
7345 }
7346
7347 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7348
7349 if (!ha->subsys) {
7350 IPS_PRINTK(KERN_WARNING, pci_dev,
7351 "Unable to allocate host subsystem structure\n");
7352 return ips_abort_init(ha, index);
7353 }
7354
7355 /* the ioctl buffer is now used during adapter initialization, so its
7356 * successful allocation is now required */
7357 if (ips_ioctlsize < PAGE_SIZE)
7358 ips_ioctlsize = PAGE_SIZE;
7359
7360 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7361 &ha->ioctl_busaddr);
7362 ha->ioctl_len = ips_ioctlsize;
7363 if (!ha->ioctl_data) {
7364 IPS_PRINTK(KERN_WARNING, pci_dev,
7365 "Unable to allocate IOCTL data\n");
7366 return ips_abort_init(ha, index);
7367 }
7368
7369 /*
7370 * Setup Functions
7371 */
7372 ips_setup_funclist(ha);
7373
7374 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7375 /* If Morpheus appears dead, reset it */
7376 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7377 if (IsDead == 0xDEADBEEF) {
7378 ips_reset_morpheus(ha);
7379 }
7380 }
7381
7382 /*
7383 * Initialize the card if it isn't already
7384 */
7385
7386 if (!(*ha->func.isinit) (ha)) {
7387 if (!(*ha->func.init) (ha)) {
7388 /*
7389 * Initialization failed
7390 */
7391 IPS_PRINTK(KERN_WARNING, pci_dev,
7392 "Unable to initialize controller\n");
7393 return ips_abort_init(ha, index);
7394 }
7395 }
7396
7397 *indexPtr = index;
7398 return SUCCESS;
7399}
7400
7401/*---------------------------------------------------------------------------*/
7402/* Routine Name: ips_init_phase2 */
7403/* */
7404/* Routine Description: */
7405/* Adapter Initialization Phase 2 */
7406/* */
7407/* Return Value: */
7408/* 0 if Successful, else non-zero */
7409/*---------------------------------------------------------------------------*/
7410static int
7411ips_init_phase2(int index)
7412{
7413 ips_ha_t *ha;
7414
7415 ha = ips_ha[index];
7416
7417 METHOD_TRACE("ips_init_phase2", 1);
7418 if (!ha->active) {
7419 ips_ha[index] = NULL;
7420 return -1;
7421 }
7422
7423 /* Install the interrupt handler */
7424 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7425 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7426 "Unable to install interrupt handler\n");
7427 return ips_abort_init(ha, index);
7428 }
7429
7430 /*
7431 * Allocate a temporary SCB for initialization
7432 */
7433 ha->max_cmds = 1;
7434 if (!ips_allocatescbs(ha)) {
7435 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7436 "Unable to allocate a CCB\n");
7437 free_irq(ha->irq, ha);
7438 return ips_abort_init(ha, index);
7439 }
7440
7441 if (!ips_hainit(ha)) {
7442 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7443 "Unable to initialize controller\n");
7444 free_irq(ha->irq, ha);
7445 return ips_abort_init(ha, index);
7446 }
7447 /* Free the temporary SCB */
7448 ips_deallocatescbs(ha, 1);
7449
7450 /* allocate CCBs */
7451 if (!ips_allocatescbs(ha)) {
7452 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7453 "Unable to allocate CCBs\n");
7454 free_irq(ha->irq, ha);
7455 return ips_abort_init(ha, index);
7456 }
7457
7458 return SUCCESS;
7459}
7460
7461#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9)
7462MODULE_LICENSE("GPL");
7463#endif
7464
7465MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7466
7467#ifdef MODULE_VERSION
7468MODULE_VERSION(IPS_VER_STRING);
7469#endif
7470
7471
7472/*
7473 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7474 * Emacs will notice this stuff at the end of the file and automatically
7475 * adjust the settings for this buffer only. This must remain at the end
7476 * of the file.
7477 * ---------------------------------------------------------------------------
7478 * Local variables:
7479 * c-indent-level: 2
7480 * c-brace-imaginary-offset: 0
7481 * c-brace-offset: -2
7482 * c-argdecl-indent: 2
7483 * c-label-offset: -2
7484 * c-continued-statement-offset: 2
7485 * c-continued-brace-offset: 0
7486 * indent-tabs-mode: nil
7487 * tab-width: 8
7488 * End:
7489 */
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