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[PATCH] qla2xxx: update version to 8.00.02b5-k
[mirror_ubuntu-zesty-kernel.git] / drivers / scsi / ips.c
CommitLineData
1da177e4
LT		 1/*****************************************************************************/
2/* ips.c -- driver for the Adaptec / IBM ServeRAID controller */
3/* */
4/* Written By: Keith Mitchell, IBM Corporation */
5/* Jack Hammer, Adaptec, Inc. */
6/* David Jeffery, Adaptec, Inc. */
7/* */
8/* Copyright (C) 2000 IBM Corporation */
9/* Copyright (C) 2002,2003 Adaptec, Inc. */
10/* */
11/* This program is free software; you can redistribute it and/or modify */
12/* it under the terms of the GNU General Public License as published by */
13/* the Free Software Foundation; either version 2 of the License, or */
14/* (at your option) any later version. */
15/* */
16/* This program is distributed in the hope that it will be useful, */
17/* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19/* GNU General Public License for more details. */
20/* */
21/* NO WARRANTY */
22/* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23/* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24/* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25/* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26/* solely responsible for determining the appropriateness of using and */
27/* distributing the Program and assumes all risks associated with its */
28/* exercise of rights under this Agreement, including but not limited to */
29/* the risks and costs of program errors, damage to or loss of data, */
30/* programs or equipment, and unavailability or interruption of operations. */
31/* */
32/* DISCLAIMER OF LIABILITY */
33/* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34/* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35/* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36/* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37/* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38/* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39/* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
40/* */
41/* You should have received a copy of the GNU General Public License */
42/* along with this program; if not, write to the Free Software */
43/* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
44/* */
45/* Bugs/Comments/Suggestions about this driver should be mailed to: */
46/* ipslinux@adaptec.com */
47/* */
48/* For system support issues, contact your local IBM Customer support. */
49/* Directions to find IBM Customer Support for each country can be found at: */
50/* http://www.ibm.com/planetwide/ */
51/* */
52/*****************************************************************************/
53
54/*****************************************************************************/
55/* Change Log */
56/* */
57/* 0.99.02 - Breakup commands that are bigger than 8 * the stripe size */
58/* 0.99.03 - Make interrupt routine handle all completed request on the */
59/* adapter not just the first one */
60/* - Make sure passthru commands get woken up if we run out of */
61/* SCBs */
62/* - Send all of the commands on the queue at once rather than */
63/* one at a time since the card will support it. */
64/* 0.99.04 - Fix race condition in the passthru mechanism -- this required */
65/* the interface to the utilities to change */
66/* - Fix error recovery code */
67/* 0.99.05 - Fix an oops when we get certain passthru commands */
68/* 1.00.00 - Initial Public Release */
69/* Functionally equivalent to 0.99.05 */
70/* 3.60.00 - Bump max commands to 128 for use with firmware 3.60 */
71/* - Change version to 3.60 to coincide with release numbering. */
72/* 3.60.01 - Remove bogus error check in passthru routine */
73/* 3.60.02 - Make DCDB direction based on lookup table */
74/* - Only allow one DCDB command to a SCSI ID at a time */
75/* 4.00.00 - Add support for ServeRAID 4 */
76/* 4.00.01 - Add support for First Failure Data Capture */
77/* 4.00.02 - Fix problem with PT DCDB with no buffer */
78/* 4.00.03 - Add alternative passthru interface */
79/* - Add ability to flash BIOS */
80/* 4.00.04 - Rename structures/constants to be prefixed with IPS_ */
81/* 4.00.05 - Remove wish_block from init routine */
82/* - Use linux/spinlock.h instead of asm/spinlock.h for kernels */
83/* 2.3.18 and later */
84/* - Sync with other changes from the 2.3 kernels */
85/* 4.00.06 - Fix timeout with initial FFDC command */
86/* 4.00.06a - Port to 2.4 (trivial) -- Christoph Hellwig <hch@infradead.org> */
87/* 4.10.00 - Add support for ServeRAID 4M/4L */
88/* 4.10.13 - Fix for dynamic unload and proc file system */
89/* 4.20.03 - Rename version to coincide with new release schedules */
90/* Performance fixes */
91/* Fix truncation of /proc files with cat */
92/* Merge in changes through kernel 2.4.0test1ac21 */
93/* 4.20.13 - Fix some failure cases / reset code */
94/* - Hook into the reboot_notifier to flush the controller cache */
95/* 4.50.01 - Fix problem when there is a hole in logical drive numbering */
96/* 4.70.09 - Use a Common ( Large Buffer ) for Flashing from the JCRM CD */
97/* - Add IPSSEND Flash Support */
98/* - Set Sense Data for Unknown SCSI Command */
99/* - Use Slot Number from NVRAM Page 5 */
100/* - Restore caller's DCDB Structure */
101/* 4.70.12 - Corrective actions for bad controller ( during initialization )*/
102/* 4.70.13 - Don't Send CDB's if we already know the device is not present */
103/* - Don't release HA Lock in ips_next() until SC taken off queue */
104/* - Unregister SCSI device in ips_release() */
105/* 4.70.15 - Fix Breakup for very large ( non-SG ) requests in ips_done() */
106/* 4.71.00 - Change all memory allocations to not use GFP_DMA flag */
107/* Code Clean-Up for 2.4.x kernel */
108/* 4.72.00 - Allow for a Scatter-Gather Element to exceed MAX_XFER Size */
109/* 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail ) */
110/* - Don't Issue Internal FFDC Command if there are Active Commands */
111/* - Close Window for getting too many IOCTL's active */
112/* 4.80.00 - Make ia64 Safe */
113/* 4.80.04 - Eliminate calls to strtok() if 2.4.x or greater */
114/* - Adjustments to Device Queue Depth */
115/* 4.80.14 - Take all semaphores off stack */
116/* - Clean Up New_IOCTL path */
117/* 4.80.20 - Set max_sectors in Scsi_Host structure ( if >= 2.4.7 kernel ) */
118/* - 5 second delay needed after resetting an i960 adapter */
119/* 4.80.26 - Clean up potential code problems ( Arjan's recommendations ) */
120/* 4.90.01 - Version Matching for FirmWare, BIOS, and Driver */
121/* 4.90.05 - Use New PCI Architecture to facilitate Hot Plug Development */
122/* 4.90.08 - Increase Delays in Flashing ( Trombone Only - 4H ) */
123/* 4.90.08 - Data Corruption if First Scatter Gather Element is > 64K */
124/* 4.90.11 - Don't actually RESET unless it's physically required */
125/* - Remove unused compile options */
126/* 5.00.01 - Sarasota ( 5i ) adapters must always be scanned first */
127/* - Get rid on IOCTL_NEW_COMMAND code */
128/* - Add Extended DCDB Commands for Tape Support in 5I */
129/* 5.10.12 - use pci_dma interfaces, update for 2.5 kernel changes */
130/* 5.10.15 - remove unused code (sem, macros, etc.) */
131/* 5.30.00 - use __devexit_p() */
132/* 6.00.00 - Add 6x Adapters and Battery Flash */
133/* 6.10.00 - Remove 1G Addressing Limitations */
134/* 6.11.xx - Get VersionInfo buffer off the stack ! DDTS 60401 */
135/* 6.11.xx - Make Logical Drive Info structure safe for DMA DDTS 60639 */
136/* 7.10.xx - Add highmem_io flag in SCSI Templete for 2.4 kernels */
137/* - Fix path/name for scsi_hosts.h include for 2.6 kernels */
138/* - Fix sort order of 7k */
139/* - Remove 3 unused "inline" functions */
140/*****************************************************************************/
141
142/*
143 * Conditional Compilation directives for this driver:
144 *
145 * IPS_DEBUG - Turn on debugging info
146 *
147 * Parameters:
148 *
149 * debug:<number> - Set debug level to <number>
150 * NOTE: only works when IPS_DEBUG compile directive is used.
151 * 1 - Normal debug messages
152 * 2 - Verbose debug messages
153 * 11 - Method trace (non interrupt)
154 * 12 - Method trace (includes interrupt)
155 *
156 * noi2o - Don't use I2O Queues (ServeRAID 4 only)
157 * nommap - Don't use memory mapped I/O
158 * ioctlsize - Initial size of the IOCTL buffer
159 */
160
161#include <asm/io.h>
162#include <asm/byteorder.h>
163#include <asm/page.h>
164#include <linux/stddef.h>
165#include <linux/version.h>
166#include <linux/string.h>
167#include <linux/errno.h>
168#include <linux/kernel.h>
169#include <linux/ioport.h>
170#include <linux/slab.h>
171#include <linux/delay.h>
172#include <linux/pci.h>
173#include <linux/proc_fs.h>
174#include <linux/reboot.h>
175#include <linux/interrupt.h>
176
177#include <linux/blkdev.h>
178#include <linux/types.h>
179
180#include <scsi/sg.h>
181
182#include "scsi.h"
183
184#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
185#include "hosts.h"
186#else
187#include <scsi/scsi_host.h>
188#endif
189
190#include "ips.h"
191
192#include <linux/module.h>
193
194#include <linux/stat.h>
195#include <linux/config.h>
196
197#include <linux/spinlock.h>
198#include <linux/init.h>
199
200#include <linux/smp.h>
201
202#ifdef MODULE
203static char *ips = NULL;
204module_param(ips, charp, 0);
205#endif
206
207/*
208 * DRIVER_VER
209 */
210#define IPS_VERSION_HIGH "7.10"
211#define IPS_VERSION_LOW ".18 "
212
213#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
214#warning "This driver has only been tested on the x86/ia64/x86_64 platforms"
215#endif
216
217#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,5,0)
218#include <linux/blk.h>
219#include "sd.h"
220#define IPS_SG_ADDRESS(sg) ((sg)->address)
221#define IPS_LOCK_SAVE(lock,flags) spin_lock_irqsave(&io_request_lock,flags)
222#define IPS_UNLOCK_RESTORE(lock,flags) spin_unlock_irqrestore(&io_request_lock,flags)
223#ifndef __devexit_p
224#define __devexit_p(x) x
225#endif
226#else
227#define IPS_SG_ADDRESS(sg) (page_address((sg)->page) ? \
228 page_address((sg)->page)+(sg)->offset : NULL)
229#define IPS_LOCK_SAVE(lock,flags) do{spin_lock(lock);(void)flags;}while(0)
230#define IPS_UNLOCK_RESTORE(lock,flags) do{spin_unlock(lock);(void)flags;}while(0)
231#endif
232
233#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
234 SCSI_DATA_NONE == scb->scsi_cmd->sc_data_direction) ? \
235 PCI_DMA_BIDIRECTIONAL : \
236 scsi_to_pci_dma_dir(scb->scsi_cmd->sc_data_direction))
237
238#ifdef IPS_DEBUG
239#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
240#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
241#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
242#else
243#define METHOD_TRACE(s, i)
244#define DEBUG(i, s)
245#define DEBUG_VAR(i, s, v...)
246#endif
247
248/*
249 * Function prototypes
250 */
251static int ips_detect(Scsi_Host_Template *);
252static int ips_release(struct Scsi_Host *);
253static int ips_eh_abort(Scsi_Cmnd *);
254static int ips_eh_reset(Scsi_Cmnd *);
255static int ips_queue(Scsi_Cmnd *, void (*)(Scsi_Cmnd *));
256static const char *ips_info(struct Scsi_Host *);
257static irqreturn_t do_ipsintr(int, void *, struct pt_regs *);
258static int ips_hainit(ips_ha_t *);
259static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
260static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
261static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
262static int ips_online(ips_ha_t *, ips_scb_t *);
263static int ips_inquiry(ips_ha_t *, ips_scb_t *);
264static int ips_rdcap(ips_ha_t *, ips_scb_t *);
265static int ips_msense(ips_ha_t *, ips_scb_t *);
266static int ips_reqsen(ips_ha_t *, ips_scb_t *);
267static int ips_deallocatescbs(ips_ha_t *, int);
268static int ips_allocatescbs(ips_ha_t *);
269static int ips_reset_copperhead(ips_ha_t *);
270static int ips_reset_copperhead_memio(ips_ha_t *);
271static int ips_reset_morpheus(ips_ha_t *);
272static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
273static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
274static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
275static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
276static int ips_isintr_copperhead(ips_ha_t *);
277static int ips_isintr_copperhead_memio(ips_ha_t *);
278static int ips_isintr_morpheus(ips_ha_t *);
279static int ips_wait(ips_ha_t *, int, int);
280static int ips_write_driver_status(ips_ha_t *, int);
281static int ips_read_adapter_status(ips_ha_t *, int);
282static int ips_read_subsystem_parameters(ips_ha_t *, int);
283static int ips_read_config(ips_ha_t *, int);
284static int ips_clear_adapter(ips_ha_t *, int);
285static int ips_readwrite_page5(ips_ha_t *, int, int);
286static int ips_init_copperhead(ips_ha_t *);
287static int ips_init_copperhead_memio(ips_ha_t *);
288static int ips_init_morpheus(ips_ha_t *);
289static int ips_isinit_copperhead(ips_ha_t *);
290static int ips_isinit_copperhead_memio(ips_ha_t *);
291static int ips_isinit_morpheus(ips_ha_t *);
292static int ips_erase_bios(ips_ha_t *);
293static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
294static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
295static int ips_erase_bios_memio(ips_ha_t *);
296static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
297static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
298static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
299static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
300static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
301static void ips_free_flash_copperhead(ips_ha_t * ha);
302static void ips_get_bios_version(ips_ha_t *, int);
303static void ips_identify_controller(ips_ha_t *);
304static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
305static void ips_enable_int_copperhead(ips_ha_t *);
306static void ips_enable_int_copperhead_memio(ips_ha_t *);
307static void ips_enable_int_morpheus(ips_ha_t *);
308static int ips_intr_copperhead(ips_ha_t *);
309static int ips_intr_morpheus(ips_ha_t *);
310static void ips_next(ips_ha_t *, int);
311static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
312static void ipsintr_done(ips_ha_t *, struct ips_scb *);
313static void ips_done(ips_ha_t *, ips_scb_t *);
314static void ips_free(ips_ha_t *);
315static void ips_init_scb(ips_ha_t *, ips_scb_t *);
316static void ips_freescb(ips_ha_t *, ips_scb_t *);
317static void ips_setup_funclist(ips_ha_t *);
318static void ips_statinit(ips_ha_t *);
319static void ips_statinit_memio(ips_ha_t *);
320static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
321static void ips_ffdc_reset(ips_ha_t *, int);
322static void ips_ffdc_time(ips_ha_t *);
323static uint32_t ips_statupd_copperhead(ips_ha_t *);
324static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
325static uint32_t ips_statupd_morpheus(ips_ha_t *);
326static ips_scb_t *ips_getscb(ips_ha_t *);
327static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
328static void ips_putq_wait_tail(ips_wait_queue_t *, Scsi_Cmnd *);
329static void ips_putq_copp_tail(ips_copp_queue_t *,
330 ips_copp_wait_item_t *);
331static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
332static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
333static Scsi_Cmnd *ips_removeq_wait_head(ips_wait_queue_t *);
334static Scsi_Cmnd *ips_removeq_wait(ips_wait_queue_t *, Scsi_Cmnd *);
335static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
336 ips_copp_wait_item_t *);
337static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
338
339static int ips_is_passthru(Scsi_Cmnd *);
340static int ips_make_passthru(ips_ha_t *, Scsi_Cmnd *, ips_scb_t *, int);
341static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
342static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
343static void ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data,
344 unsigned int count);
345static void ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned int count);
346
347static int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
348static int ips_host_info(ips_ha_t *, char *, off_t, int);
349static void copy_mem_info(IPS_INFOSTR *, char *, int);
350static int copy_info(IPS_INFOSTR *, char *, ...);
351static int ips_get_version_info(ips_ha_t * ha, dma_addr_t, int intr);
352static void ips_version_check(ips_ha_t * ha, int intr);
353static int ips_abort_init(ips_ha_t * ha, int index);
354static int ips_init_phase2(int index);
355
356static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
357static int ips_register_scsi(int index);
358
359/*
360 * global variables
361 */
362static const char ips_name[] = "ips";
363static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS]; /* Array of host controller structures */
364static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS]; /* Array of HA structures */
365static unsigned int ips_next_controller;
366static unsigned int ips_num_controllers;
367static unsigned int ips_released_controllers;
368static int ips_hotplug;
369static int ips_cmd_timeout = 60;
370static int ips_reset_timeout = 60 * 5;
371static int ips_force_memio = 1; /* Always use Memory Mapped I/O */
372static int ips_force_i2o = 1; /* Always use I2O command delivery */
373static int ips_ioctlsize = IPS_IOCTL_SIZE; /* Size of the ioctl buffer */
374static int ips_cd_boot; /* Booting from Manager CD */
375static char *ips_FlashData = NULL; /* CD Boot - Flash Data Buffer */
376static dma_addr_t ips_flashbusaddr;
377static long ips_FlashDataInUse; /* CD Boot - Flash Data In Use Flag */
378static uint32_t MaxLiteCmds = 32; /* Max Active Cmds for a Lite Adapter */
379static Scsi_Host_Template ips_driver_template = {
380 .detect = ips_detect,
381 .release = ips_release,
382 .info = ips_info,
383 .queuecommand = ips_queue,
384 .eh_abort_handler = ips_eh_abort,
385 .eh_host_reset_handler = ips_eh_reset,
386 .proc_name = "ips",
387#if LINUX_VERSION_CODE > KERNEL_VERSION(2,5,0)
388 .proc_info = ips_proc_info,
389 .slave_configure = ips_slave_configure,
390#else
391 .proc_info = ips_proc24_info,
392 .select_queue_depths = ips_select_queue_depth,
393#endif
394 .bios_param = ips_biosparam,
395 .this_id = -1,
396 .sg_tablesize = IPS_MAX_SG,
397 .cmd_per_lun = 3,
398 .use_clustering = ENABLE_CLUSTERING,
399#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
400 .use_new_eh_code = 1,
401#endif
402#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) && LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
403 .highmem_io = 1,
404#endif
405};
406
407static IPS_DEFINE_COMPAT_TABLE( Compatable ); /* Version Compatability Table */
408
409
410/* This table describes all ServeRAID Adapters */
411static struct pci_device_id ips_pci_table[] = {
412 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
413 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
414 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
415 { 0, }
416};
417
418MODULE_DEVICE_TABLE( pci, ips_pci_table );
419
420static char ips_hot_plug_name[] = "ips";
421
422static int __devinit ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
423static void __devexit ips_remove_device(struct pci_dev *pci_dev);
424
425static struct pci_driver ips_pci_driver = {
426 .name = ips_hot_plug_name,
427 .id_table = ips_pci_table,
428 .probe = ips_insert_device,
429 .remove = __devexit_p(ips_remove_device),
430};
431
432
433/*
434 * Necessary forward function protoypes
435 */
436static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
437
438#define MAX_ADAPTER_NAME 15
439
440static char ips_adapter_name[][30] = {
441 "ServeRAID",
442 "ServeRAID II",
443 "ServeRAID on motherboard",
444 "ServeRAID on motherboard",
445 "ServeRAID 3H",
446 "ServeRAID 3L",
447 "ServeRAID 4H",
448 "ServeRAID 4M",
449 "ServeRAID 4L",
450 "ServeRAID 4Mx",
451 "ServeRAID 4Lx",
452 "ServeRAID 5i",
453 "ServeRAID 5i",
454 "ServeRAID 6M",
455 "ServeRAID 6i",
456 "ServeRAID 7t",
457 "ServeRAID 7k",
458 "ServeRAID 7M"
459};
460
461static struct notifier_block ips_notifier = {
462 ips_halt, NULL, 0
463};
464
465/*
466 * Direction table
467 */
468static char ips_command_direction[] = {
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
470 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
472 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
473 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
474 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
475 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
476 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
478 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
479 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
480 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
481 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
482 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
483 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
484 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
487 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
488 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
489 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
490 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
491 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
492 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
493 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
494 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
495 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
496 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
497 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
498 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
499 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
500 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
501 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
502 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
503 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
504 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
505 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
506 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
507 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
508 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
509 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
510 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
511 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
512 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
513 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
514 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
515 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
516 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
517 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
518 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
519 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
520};
521
522
523/****************************************************************************/
524/* */
525/* Routine Name: ips_setup */
526/* */
527/* Routine Description: */
528/* */
529/* setup parameters to the driver */
530/* */
531/****************************************************************************/
532static int
533ips_setup(char *ips_str)
534{
535
536 int i;
537 char *key;
538 char *value;
539 IPS_OPTION options[] = {
540 {"noi2o", &ips_force_i2o, 0},
541 {"nommap", &ips_force_memio, 0},
542 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
543 {"cdboot", &ips_cd_boot, 0},
544 {"maxcmds", &MaxLiteCmds, 32},
545 };
546
547 /* Don't use strtok() anymore ( if 2.4 Kernel or beyond ) */
548 /* Search for value */
549 while ((key = strsep(&ips_str, ",."))) {
550 if (!*key)
551 continue;
552 value = strchr(key, ':');
553 if (value)
554 *value++ = '\0';
555 /*
556 * We now have key/value pairs.
557 * Update the variables
558 */
559 for (i = 0; i < (sizeof (options) / sizeof (options[0])); i++) {
560 if (strnicmp
561 (key, options[i].option_name,
562 strlen(options[i].option_name)) == 0) {
563 if (value)
564 *options[i].option_flag =
565 simple_strtoul(value, NULL, 0);
566 else
567 *options[i].option_flag =
568 options[i].option_value;
569 break;
570 }
571 }
572 }
573
574 return (1);
575}
576
577__setup("ips=", ips_setup);
578
579/****************************************************************************/
580/* */
581/* Routine Name: ips_detect */
582/* */
583/* Routine Description: */
584/* */
585/* Detect and initialize the driver */
586/* */
587/* NOTE: this routine is called under the io_request_lock spinlock */
588/* */
589/****************************************************************************/
590static int
591ips_detect(Scsi_Host_Template * SHT)
592{
593 int i;
594
595 METHOD_TRACE("ips_detect", 1);
596
597#ifdef MODULE
598 if (ips)
599 ips_setup(ips);
600#endif
601
602 for (i = 0; i < ips_num_controllers; i++) {
603 if (ips_register_scsi(i))
604 ips_free(ips_ha[i]);
605 ips_released_controllers++;
606 }
607 ips_hotplug = 1;
608 return (ips_num_controllers);
609}
610
611/****************************************************************************/
612/* configure the function pointers to use the functions that will work */
613/* with the found version of the adapter */
614/****************************************************************************/
615static void
616ips_setup_funclist(ips_ha_t * ha)
617{
618
619 /*
620 * Setup Functions
621 */
622 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
623 /* morpheus / marco / sebring */
624 ha->func.isintr = ips_isintr_morpheus;
625 ha->func.isinit = ips_isinit_morpheus;
626 ha->func.issue = ips_issue_i2o_memio;
627 ha->func.init = ips_init_morpheus;
628 ha->func.statupd = ips_statupd_morpheus;
629 ha->func.reset = ips_reset_morpheus;
630 ha->func.intr = ips_intr_morpheus;
631 ha->func.enableint = ips_enable_int_morpheus;
632 } else if (IPS_USE_MEMIO(ha)) {
633 /* copperhead w/MEMIO */
634 ha->func.isintr = ips_isintr_copperhead_memio;
635 ha->func.isinit = ips_isinit_copperhead_memio;
636 ha->func.init = ips_init_copperhead_memio;
637 ha->func.statupd = ips_statupd_copperhead_memio;
638 ha->func.statinit = ips_statinit_memio;
639 ha->func.reset = ips_reset_copperhead_memio;
640 ha->func.intr = ips_intr_copperhead;
641 ha->func.erasebios = ips_erase_bios_memio;
642 ha->func.programbios = ips_program_bios_memio;
643 ha->func.verifybios = ips_verify_bios_memio;
644 ha->func.enableint = ips_enable_int_copperhead_memio;
645 if (IPS_USE_I2O_DELIVER(ha))
646 ha->func.issue = ips_issue_i2o_memio;
647 else
648 ha->func.issue = ips_issue_copperhead_memio;
649 } else {
650 /* copperhead */
651 ha->func.isintr = ips_isintr_copperhead;
652 ha->func.isinit = ips_isinit_copperhead;
653 ha->func.init = ips_init_copperhead;
654 ha->func.statupd = ips_statupd_copperhead;
655 ha->func.statinit = ips_statinit;
656 ha->func.reset = ips_reset_copperhead;
657 ha->func.intr = ips_intr_copperhead;
658 ha->func.erasebios = ips_erase_bios;
659 ha->func.programbios = ips_program_bios;
660 ha->func.verifybios = ips_verify_bios;
661 ha->func.enableint = ips_enable_int_copperhead;
662
663 if (IPS_USE_I2O_DELIVER(ha))
664 ha->func.issue = ips_issue_i2o;
665 else
666 ha->func.issue = ips_issue_copperhead;
667 }
668}
669
670/****************************************************************************/
671/* */
672/* Routine Name: ips_release */
673/* */
674/* Routine Description: */
675/* */
676/* Remove a driver */
677/* */
678/****************************************************************************/
679static int
680ips_release(struct Scsi_Host *sh)
681{
682 ips_scb_t *scb;
683 ips_ha_t *ha;
684 int i;
685
686 METHOD_TRACE("ips_release", 1);
687
688 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
689
690 if (i == IPS_MAX_ADAPTERS) {
691 printk(KERN_WARNING
692 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
693 BUG();
694 return (FALSE);
695 }
696
697 ha = IPS_HA(sh);
698
699 if (!ha)
700 return (FALSE);
701
702 /* flush the cache on the controller */
703 scb = &ha->scbs[ha->max_cmds - 1];
704
705 ips_init_scb(ha, scb);
706
707 scb->timeout = ips_cmd_timeout;
708 scb->cdb[0] = IPS_CMD_FLUSH;
709
710 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
711 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
712 scb->cmd.flush_cache.state = IPS_NORM_STATE;
713 scb->cmd.flush_cache.reserved = 0;
714 scb->cmd.flush_cache.reserved2 = 0;
715 scb->cmd.flush_cache.reserved3 = 0;
716 scb->cmd.flush_cache.reserved4 = 0;
717
718 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
719
720 /* send command */
721 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
722 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
723
724 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
725
726 ips_sh[i] = NULL;
727 ips_ha[i] = NULL;
728
729 /* free extra memory */
730 ips_free(ha);
731
732 /* Free I/O Region */
733 if (ha->io_addr)
734 release_region(ha->io_addr, ha->io_len);
735
736 /* free IRQ */
737 free_irq(ha->irq, ha);
738
739 IPS_REMOVE_HOST(sh);
740 scsi_host_put(sh);
741
742 ips_released_controllers++;
743
744 return (FALSE);
745}
746
747/****************************************************************************/
748/* */
749/* Routine Name: ips_halt */
750/* */
751/* Routine Description: */
752/* */
753/* Perform cleanup when the system reboots */
754/* */
755/****************************************************************************/
756static int
757ips_halt(struct notifier_block *nb, ulong event, void *buf)
758{
759 ips_scb_t *scb;
760 ips_ha_t *ha;
761 int i;
762
763 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
764 (event != SYS_POWER_OFF))
765 return (NOTIFY_DONE);
766
767 for (i = 0; i < ips_next_controller; i++) {
768 ha = (ips_ha_t *) ips_ha[i];
769
770 if (!ha)
771 continue;
772
773 if (!ha->active)
774 continue;
775
776 /* flush the cache on the controller */
777 scb = &ha->scbs[ha->max_cmds - 1];
778
779 ips_init_scb(ha, scb);
780
781 scb->timeout = ips_cmd_timeout;
782 scb->cdb[0] = IPS_CMD_FLUSH;
783
784 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
785 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
786 scb->cmd.flush_cache.state = IPS_NORM_STATE;
787 scb->cmd.flush_cache.reserved = 0;
788 scb->cmd.flush_cache.reserved2 = 0;
789 scb->cmd.flush_cache.reserved3 = 0;
790 scb->cmd.flush_cache.reserved4 = 0;
791
792 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
793
794 /* send command */
795 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
796 IPS_FAILURE)
797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
798 "Incomplete Flush.\n");
799 else
800 IPS_PRINTK(KERN_WARNING, ha->pcidev,
801 "Flushing Complete.\n");
802 }
803
804 return (NOTIFY_OK);
805}
806
807/****************************************************************************/
808/* */
809/* Routine Name: ips_eh_abort */
810/* */
811/* Routine Description: */
812/* */
813/* Abort a command (using the new error code stuff) */
814/* Note: this routine is called under the io_request_lock */
815/****************************************************************************/
816int
817ips_eh_abort(Scsi_Cmnd * SC)
818{
819 ips_ha_t *ha;
820 ips_copp_wait_item_t *item;
821 int ret;
822
823 METHOD_TRACE("ips_eh_abort", 1);
824
825 if (!SC)
826 return (FAILED);
827
828 ha = (ips_ha_t *) SC->device->host->hostdata;
829
830 if (!ha)
831 return (FAILED);
832
833 if (!ha->active)
834 return (FAILED);
835
1da177e4
LT		 836 /* See if the command is on the copp queue */
837 item = ha->copp_waitlist.head;
838 while ((item) && (item->scsi_cmd != SC))
839 item = item->next;
840
841 if (item) {
842 /* Found it */
843 ips_removeq_copp(&ha->copp_waitlist, item);
844 ret = (SUCCESS);
845
846 /* See if the command is on the wait queue */
847 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
848 /* command not sent yet */
849 ret = (SUCCESS);
850 } else {
851 /* command must have already been sent */
852 ret = (FAILED);
853 }
854 return ret;
855}
856
857/****************************************************************************/
858/* */
859/* Routine Name: ips_eh_reset */
860/* */
861/* Routine Description: */
862/* */
863/* Reset the controller (with new eh error code) */
864/* */
865/* NOTE: this routine is called under the io_request_lock spinlock */
866/* */
867/****************************************************************************/
868static int
869ips_eh_reset(Scsi_Cmnd * SC)
870{
871 int ret;
872 int i;
873 ips_ha_t *ha;
874 ips_scb_t *scb;
875 ips_copp_wait_item_t *item;
876
877 METHOD_TRACE("ips_eh_reset", 1);
878
879#ifdef NO_IPS_RESET
880 return (FAILED);
881#else
882
883 if (!SC) {
884 DEBUG(1, "Reset called with NULL scsi command");
885
886 return (FAILED);
887 }
888
889 ha = (ips_ha_t *) SC->device->host->hostdata;
890
891 if (!ha) {
892 DEBUG(1, "Reset called with NULL ha struct");
893
894 return (FAILED);
895 }
896
897 if (!ha->active)
898 return (FAILED);
899
900 /* See if the command is on the copp queue */
901 item = ha->copp_waitlist.head;
902 while ((item) && (item->scsi_cmd != SC))
903 item = item->next;
904
905 if (item) {
906 /* Found it */
907 ips_removeq_copp(&ha->copp_waitlist, item);
908 return (SUCCESS);
909 }
910
911 /* See if the command is on the wait queue */
912 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
913 /* command not sent yet */
914 return (SUCCESS);
915 }
916
917 /* An explanation for the casual observer: */
918 /* Part of the function of a RAID controller is automatic error */
919 /* detection and recovery. As such, the only problem that physically */
920 /* resetting an adapter will ever fix is when, for some reason, */
921 /* the driver is not successfully communicating with the adapter. */
922 /* Therefore, we will attempt to flush this adapter. If that succeeds, */
923 /* then there's no real purpose in a physical reset. This will complete */
924 /* much faster and avoids any problems that might be caused by a */
925 /* physical reset ( such as having to fail all the outstanding I/O's ). */
926
927 if (ha->ioctl_reset == 0) { /* IF Not an IOCTL Requested Reset */
928 scb = &ha->scbs[ha->max_cmds - 1];
929
930 ips_init_scb(ha, scb);
931
932 scb->timeout = ips_cmd_timeout;
933 scb->cdb[0] = IPS_CMD_FLUSH;
934
935 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
936 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
937 scb->cmd.flush_cache.state = IPS_NORM_STATE;
938 scb->cmd.flush_cache.reserved = 0;
939 scb->cmd.flush_cache.reserved2 = 0;
940 scb->cmd.flush_cache.reserved3 = 0;
941 scb->cmd.flush_cache.reserved4 = 0;
942
943 /* Attempt the flush command */
944 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
945 if (ret == IPS_SUCCESS) {
946 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
947 "Reset Request - Flushed Cache\n");
948 return (SUCCESS);
949 }
950 }
951
952 /* Either we can't communicate with the adapter or it's an IOCTL request */
953 /* from a utility. A physical reset is needed at this point. */
954
955 ha->ioctl_reset = 0; /* Reset the IOCTL Requested Reset Flag */
956
957 /*
958 * command must have already been sent
959 * reset the controller
960 */
961 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
962 ret = (*ha->func.reset) (ha);
963
964 if (!ret) {
965 Scsi_Cmnd *scsi_cmd;
966
967 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
968 "Controller reset failed - controller now offline.\n");
969
970 /* Now fail all of the active commands */
971 DEBUG_VAR(1, "(%s%d) Failing active commands",
972 ips_name, ha->host_num);
973
974 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
975 scb->scsi_cmd->result = DID_ERROR << 16;
976 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
977 ips_freescb(ha, scb);
978 }
979
980 /* Now fail all of the pending commands */
981 DEBUG_VAR(1, "(%s%d) Failing pending commands",
982 ips_name, ha->host_num);
983
984 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
985 scsi_cmd->result = DID_ERROR;
986 scsi_cmd->scsi_done(scsi_cmd);
987 }
988
989 ha->active = FALSE;
990 return (FAILED);
991 }
992
993 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
994 Scsi_Cmnd *scsi_cmd;
995
996 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
997 "Controller reset failed - controller now offline.\n");
998
999 /* Now fail all of the active commands */
1000 DEBUG_VAR(1, "(%s%d) Failing active commands",
1001 ips_name, ha->host_num);
1002
1003 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1004 scb->scsi_cmd->result = DID_ERROR << 16;
1005 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1006 ips_freescb(ha, scb);
1007 }
1008
1009 /* Now fail all of the pending commands */
1010 DEBUG_VAR(1, "(%s%d) Failing pending commands",
1011 ips_name, ha->host_num);
1012
1013 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
1014 scsi_cmd->result = DID_ERROR << 16;
1015 scsi_cmd->scsi_done(scsi_cmd);
1016 }
1017
1018 ha->active = FALSE;
1019 return (FAILED);
1020 }
1021
1022 /* FFDC */
1023 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
1024 struct timeval tv;
1025
1026 do_gettimeofday(&tv);
1027 ha->last_ffdc = tv.tv_sec;
1028 ha->reset_count++;
1029 ips_ffdc_reset(ha, IPS_INTR_IORL);
1030 }
1031
1032 /* Now fail all of the active commands */
1033 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1034
1035 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1036 scb->scsi_cmd->result =
1037 (DID_RESET << 16) | (SUGGEST_RETRY << 24);
1038 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1039 ips_freescb(ha, scb);
1040 }
1041
1042 /* Reset DCDB active command bits */
1043 for (i = 1; i < ha->nbus; i++)
1044 ha->dcdb_active[i - 1] = 0;
1045
1046 /* Reset the number of active IOCTLs */
1047 ha->num_ioctl = 0;
1048
1049 ips_next(ha, IPS_INTR_IORL);
1050
1051 return (SUCCESS);
1052#endif /* NO_IPS_RESET */
1053
1054}
1055
1056/****************************************************************************/
1057/* */
1058/* Routine Name: ips_queue */
1059/* */
1060/* Routine Description: */
1061/* */
1062/* Send a command to the controller */
1063/* */
1064/* NOTE: */
1065/* Linux obtains io_request_lock before calling this function */
1066/* */
1067/****************************************************************************/
1068static int
1069ips_queue(Scsi_Cmnd * SC, void (*done) (Scsi_Cmnd *))
1070{
1071 ips_ha_t *ha;
1072 ips_passthru_t *pt;
1073
1074 METHOD_TRACE("ips_queue", 1);
1075
1076 ha = (ips_ha_t *) SC->device->host->hostdata;
1077
1078 if (!ha)
1079 return (1);
1080
1081 if (!ha->active)
1082 return (DID_ERROR);
1083
1084 if (ips_is_passthru(SC)) {
1085 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1086 SC->result = DID_BUS_BUSY << 16;
1087 done(SC);
1088
1089 return (0);
1090 }
1091 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1092 SC->result = DID_BUS_BUSY << 16;
1093 done(SC);
1094
1095 return (0);
1096 }
1097
1098 SC->scsi_done = done;
1099
1100 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1101 ips_name,
1102 ha->host_num,
1103 SC->cmnd[0],
1104 SC->device->channel, SC->device->id, SC->device->lun);
1105
1106 /* Check for command to initiator IDs */
1107 if ((SC->device->channel > 0)
1108 && (SC->device->id == ha->ha_id[SC->device->channel])) {
1109 SC->result = DID_NO_CONNECT << 16;
1110 done(SC);
1111
1112 return (0);
1113 }
1114
1115 if (ips_is_passthru(SC)) {
1116
1117 ips_copp_wait_item_t *scratch;
1118
1119 /* A Reset IOCTL is only sent by the boot CD in extreme cases. */
1120 /* There can never be any system activity ( network or disk ), but check */
1121 /* anyway just as a good practice. */
1122 pt = (ips_passthru_t *) SC->request_buffer;
1123 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1124 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1125 if (ha->scb_activelist.count != 0) {
1126 SC->result = DID_BUS_BUSY << 16;
1127 done(SC);
1128 return (0);
1129 }
1130 ha->ioctl_reset = 1; /* This reset request is from an IOCTL */
1131 ips_eh_reset(SC);
1132 SC->result = DID_OK << 16;
1133 SC->scsi_done(SC);
1134 return (0);
1135 }
1136
1137 /* allocate space for the scribble */
1138 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1139
1140 if (!scratch) {
1141 SC->result = DID_ERROR << 16;
1142 done(SC);
1143
1144 return (0);
1145 }
1146
1147 scratch->scsi_cmd = SC;
1148 scratch->next = NULL;
1149
1150 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1151 } else {
1152 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1153 }
1154
1155 ips_next(ha, IPS_INTR_IORL);
1156
1157 return (0);
1158}
1159
1160/****************************************************************************/
1161/* */
1162/* Routine Name: ips_biosparam */
1163/* */
1164/* Routine Description: */
1165/* */
1166/* Set bios geometry for the controller */
1167/* */
1168/****************************************************************************/
1169static int
1170#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1171ips_biosparam(Disk * disk, kdev_t dev, int geom[])
1172{
1173 ips_ha_t *ha = (ips_ha_t *) disk->device->host->hostdata;
1174 unsigned long capacity = disk->capacity;
1175#else
1176ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1177 sector_t capacity, int geom[])
1178{
1179 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1180#endif
1181 int heads;
1182 int sectors;
1183 int cylinders;
1184
1185 METHOD_TRACE("ips_biosparam", 1);
1186
1187 if (!ha)
1188 /* ?!?! host adater info invalid */
1189 return (0);
1190
1191 if (!ha->active)
1192 return (0);
1193
1194 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1195 /* ?!?! Enquiry command failed */
1196 return (0);
1197
1198 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1199 heads = IPS_NORM_HEADS;
1200 sectors = IPS_NORM_SECTORS;
1201 } else {
1202 heads = IPS_COMP_HEADS;
1203 sectors = IPS_COMP_SECTORS;
1204 }
1205
1206 cylinders = (unsigned long) capacity / (heads * sectors);
1207
1208 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1209 heads, sectors, cylinders);
1210
1211 geom[0] = heads;
1212 geom[1] = sectors;
1213 geom[2] = cylinders;
1214
1215 return (0);
1216}
1217
1218#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
1219
1220/* ips_proc24_info is a wrapper around ips_proc_info *
1221 * for compatibility with the 2.4 scsi parameters */
1222static int
1223ips_proc24_info(char *buffer, char **start, off_t offset, int length,
1224 int hostno, int func)
1225{
1226 int i;
1227
1228 for (i = 0; i < ips_next_controller; i++) {
1229 if (ips_sh[i] && ips_sh[i]->host_no == hostno) {
1230 return ips_proc_info(ips_sh[i], buffer, start,
1231 offset, length, func);
1232 }
1233 }
1234 return -EINVAL;
1235}
1236
1237/****************************************************************************/
1238/* */
1239/* Routine Name: ips_select_queue_depth */
1240/* */
1241/* Routine Description: */
1242/* */
1243/* Select queue depths for the devices on the contoller */
1244/* */
1245/****************************************************************************/
1246static void
1247ips_select_queue_depth(struct Scsi_Host *host, Scsi_Device * scsi_devs)
1248{
1249 Scsi_Device *device;
1250 ips_ha_t *ha;
1251 int count = 0;
1252 int min;
1253
1254 ha = IPS_HA(host);
1255 min = ha->max_cmds / 4;
1256
1257 for (device = scsi_devs; device; device = device->next) {
1258 if (device->host == host) {
1259 if ((device->channel == 0) && (device->type == 0))
1260 count++;
1261 }
1262 }
1263
1264 for (device = scsi_devs; device; device = device->next) {
1265 if (device->host == host) {
1266 if ((device->channel == 0) && (device->type == 0)) {
1267 device->queue_depth =
1268 (ha->max_cmds - 1) / count;
1269 if (device->queue_depth < min)
1270 device->queue_depth = min;
1271 } else {
1272 device->queue_depth = 2;
1273 }
1274
1275 if (device->queue_depth < 2)
1276 device->queue_depth = 2;
1277 }
1278 }
1279}
1280
1281#else
1282/****************************************************************************/
1283/* */
1284/* Routine Name: ips_slave_configure */
1285/* */
1286/* Routine Description: */
1287/* */
1288/* Set queue depths on devices once scan is complete */
1289/* */
1290/****************************************************************************/
1291static int
1292ips_slave_configure(Scsi_Device * SDptr)
1293{
1294 ips_ha_t *ha;
1295 int min;
1296
1297 ha = IPS_HA(SDptr->host);
1298 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1299 min = ha->max_cmds / 2;
1300 if (ha->enq->ucLogDriveCount <= 2)
1301 min = ha->max_cmds - 1;
1302 scsi_adjust_queue_depth(SDptr, MSG_ORDERED_TAG, min);
1303 }
1304 return 0;
1305}
1306#endif
1307
1308/****************************************************************************/
1309/* */
1310/* Routine Name: do_ipsintr */
1311/* */
1312/* Routine Description: */
1313/* */
1314/* Wrapper for the interrupt handler */
1315/* */
1316/****************************************************************************/
1317static irqreturn_t
1318do_ipsintr(int irq, void *dev_id, struct pt_regs * regs)
1319{
1320 ips_ha_t *ha;
1321 unsigned long cpu_flags;
1322 struct Scsi_Host *host;
1323 int irqstatus;
1324
1325 METHOD_TRACE("do_ipsintr", 2);
1326
1327 ha = (ips_ha_t *) dev_id;
1328 if (!ha)
1329 return IRQ_NONE;
1330 host = ips_sh[ha->host_num];
1331 /* interrupt during initialization */
1332 if (!host) {
1333 (*ha->func.intr) (ha);
1334 return IRQ_HANDLED;
1335 }
1336
1337 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
1338
1339 if (!ha->active) {
1340 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1341 return IRQ_HANDLED;
1342 }
1343
1344 irqstatus = (*ha->func.intr) (ha);
1345
1346 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
1347
1348 /* start the next command */
1349 ips_next(ha, IPS_INTR_ON);
1350 return IRQ_RETVAL(irqstatus);
1351}
1352
1353/****************************************************************************/
1354/* */
1355/* Routine Name: ips_intr_copperhead */
1356/* */
1357/* Routine Description: */
1358/* */
1359/* Polling interrupt handler */
1360/* */
1361/* ASSUMES interrupts are disabled */
1362/* */
1363/****************************************************************************/
1364int
1365ips_intr_copperhead(ips_ha_t * ha)
1366{
1367 ips_stat_t *sp;
1368 ips_scb_t *scb;
1369 IPS_STATUS cstatus;
1370 int intrstatus;
1371
1372 METHOD_TRACE("ips_intr", 2);
1373
1374 if (!ha)
1375 return 0;
1376
1377 if (!ha->active)
1378 return 0;
1379
1380 intrstatus = (*ha->func.isintr) (ha);
1381
1382 if (!intrstatus) {
1383 /*
1384 * Unexpected/Shared interrupt
1385 */
1386
1387 return 0;
1388 }
1389
1390 while (TRUE) {
1391 sp = &ha->sp;
1392
1393 intrstatus = (*ha->func.isintr) (ha);
1394
1395 if (!intrstatus)
1396 break;
1397 else
1398 cstatus.value = (*ha->func.statupd) (ha);
1399
1400 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1401 /* Spurious Interupt ? */
1402 continue;
1403 }
1404
1405 ips_chkstatus(ha, &cstatus);
1406 scb = (ips_scb_t *) sp->scb_addr;
1407
1408 /*
1409 * use the callback function to finish things up
1410 * NOTE: interrupts are OFF for this
1411 */
1412 (*scb->callback) (ha, scb);
1413 } /* end while */
1414 return 1;
1415}
1416
1417/****************************************************************************/
1418/* */
1419/* Routine Name: ips_intr_morpheus */
1420/* */
1421/* Routine Description: */
1422/* */
1423/* Polling interrupt handler */
1424/* */
1425/* ASSUMES interrupts are disabled */
1426/* */
1427/****************************************************************************/
1428int
1429ips_intr_morpheus(ips_ha_t * ha)
1430{
1431 ips_stat_t *sp;
1432 ips_scb_t *scb;
1433 IPS_STATUS cstatus;
1434 int intrstatus;
1435
1436 METHOD_TRACE("ips_intr_morpheus", 2);
1437
1438 if (!ha)
1439 return 0;
1440
1441 if (!ha->active)
1442 return 0;
1443
1444 intrstatus = (*ha->func.isintr) (ha);
1445
1446 if (!intrstatus) {
1447 /*
1448 * Unexpected/Shared interrupt
1449 */
1450
1451 return 0;
1452 }
1453
1454 while (TRUE) {
1455 sp = &ha->sp;
1456
1457 intrstatus = (*ha->func.isintr) (ha);
1458
1459 if (!intrstatus)
1460 break;
1461 else
1462 cstatus.value = (*ha->func.statupd) (ha);
1463
1464 if (cstatus.value == 0xffffffff)
1465 /* No more to process */
1466 break;
1467
1468 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1469 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1470 "Spurious interrupt; no ccb.\n");
1471
1472 continue;
1473 }
1474
1475 ips_chkstatus(ha, &cstatus);
1476 scb = (ips_scb_t *) sp->scb_addr;
1477
1478 /*
1479 * use the callback function to finish things up
1480 * NOTE: interrupts are OFF for this
1481 */
1482 (*scb->callback) (ha, scb);
1483 } /* end while */
1484 return 1;
1485}
1486
1487/****************************************************************************/
1488/* */
1489/* Routine Name: ips_info */
1490/* */
1491/* Routine Description: */
1492/* */
1493/* Return info about the driver */
1494/* */
1495/****************************************************************************/
1496static const char *
1497ips_info(struct Scsi_Host *SH)
1498{
1499 static char buffer[256];
1500 char *bp;
1501 ips_ha_t *ha;
1502
1503 METHOD_TRACE("ips_info", 1);
1504
1505 ha = IPS_HA(SH);
1506
1507 if (!ha)
1508 return (NULL);
1509
1510 bp = &buffer[0];
1511 memset(bp, 0, sizeof (buffer));
1512
1513 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1514 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1515
1516 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1517 strcat(bp, " <");
1518 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1519 strcat(bp, ">");
1520 }
1521
1522 return (bp);
1523}
1524
1525/****************************************************************************/
1526/* */
1527/* Routine Name: ips_proc_info */
1528/* */
1529/* Routine Description: */
1530/* */
1531/* The passthru interface for the driver */
1532/* */
1533/****************************************************************************/
1534static int
1535ips_proc_info(struct Scsi_Host *host, char *buffer, char **start, off_t offset,
1536 int length, int func)
1537{
1538 int i;
1539 int ret;
1540 ips_ha_t *ha = NULL;
1541
1542 METHOD_TRACE("ips_proc_info", 1);
1543
1544 /* Find our host structure */
1545 for (i = 0; i < ips_next_controller; i++) {
1546 if (ips_sh[i]) {
1547 if (ips_sh[i] == host) {
1548 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1549 break;
1550 }
1551 }
1552 }
1553
1554 if (!ha)
1555 return (-EINVAL);
1556
1557 if (func) {
1558 /* write */
1559 return (0);
1560 } else {
1561 /* read */
1562 if (start)
1563 *start = buffer;
1564
1565 ret = ips_host_info(ha, buffer, offset, length);
1566
1567 return (ret);
1568 }
1569}
1570
1571/*--------------------------------------------------------------------------*/
1572/* Helper Functions */
1573/*--------------------------------------------------------------------------*/
1574
1575/****************************************************************************/
1576/* */
1577/* Routine Name: ips_is_passthru */
1578/* */
1579/* Routine Description: */
1580/* */
1581/* Determine if the specified SCSI command is really a passthru command */
1582/* */
1583/****************************************************************************/
1584static int
1585ips_is_passthru(Scsi_Cmnd * SC)
1586{
1587 METHOD_TRACE("ips_is_passthru", 1);
1588
1589 if (!SC)
1590 return (0);
1591
1592 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1593 (SC->device->channel == 0) &&
1594 (SC->device->id == IPS_ADAPTER_ID) &&
1595 (SC->device->lun == 0) && SC->request_buffer) {
1596 if ((!SC->use_sg) && SC->request_bufflen &&
1597 (((char *) SC->request_buffer)[0] == 'C') &&
1598 (((char *) SC->request_buffer)[1] == 'O') &&
1599 (((char *) SC->request_buffer)[2] == 'P') &&
1600 (((char *) SC->request_buffer)[3] == 'P'))
1601 return 1;
1602 else if (SC->use_sg) {
1603 struct scatterlist *sg = SC->request_buffer;
1604 char *buffer = IPS_SG_ADDRESS(sg);
1605 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1606 buffer[2] == 'P' && buffer[3] == 'P')
1607 return 1;
1608 }
1609 }
1610 return 0;
1611}
1612
1613/****************************************************************************/
1614/* */
1615/* Routine Name: ips_alloc_passthru_buffer */
1616/* */
1617/* Routine Description: */
1618/* allocate a buffer large enough for the ioctl data if the ioctl buffer */
1619/* is too small or doesn't exist */
1620/****************************************************************************/
1621static int
1622ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1623{
1624 void *bigger_buf;
1625 dma_addr_t dma_busaddr;
1626
1627 if (ha->ioctl_data && length <= ha->ioctl_len)
1628 return 0;
1629 /* there is no buffer or it's not big enough, allocate a new one */
1630 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1631 if (bigger_buf) {
1632 /* free the old memory */
1633 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1634 ha->ioctl_busaddr);
1635 /* use the new memory */
1636 ha->ioctl_data = (char *) bigger_buf;
1637 ha->ioctl_len = length;
1638 ha->ioctl_busaddr = dma_busaddr;
1639 } else {
1640 return -1;
1641 }
1642 return 0;
1643}
1644
1645/****************************************************************************/
1646/* */
1647/* Routine Name: ips_make_passthru */
1648/* */
1649/* Routine Description: */
1650/* */
1651/* Make a passthru command out of the info in the Scsi block */
1652/* */
1653/****************************************************************************/
1654static int
1655ips_make_passthru(ips_ha_t * ha, Scsi_Cmnd * SC, ips_scb_t * scb, int intr)
1656{
1657 ips_passthru_t *pt;
1658 int length = 0;
1659 int ret;
1660
1661 METHOD_TRACE("ips_make_passthru", 1);
1662
1663 if (!SC->use_sg) {
1664 length = SC->request_bufflen;
1665 } else {
1666 struct scatterlist *sg = SC->request_buffer;
1667 int i;
1668 for (i = 0; i < SC->use_sg; i++)
1669 length += sg[i].length;
1670 }
1671 if (length < sizeof (ips_passthru_t)) {
1672 /* wrong size */
1673 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1674 ips_name, ha->host_num);
1675 return (IPS_FAILURE);
1676 }
1677 if (ips_alloc_passthru_buffer(ha, length)) {
1678 /* allocation failure! If ha->ioctl_data exists, use it to return
1679 some error codes. Return a failed command to the scsi layer. */
1680 if (ha->ioctl_data) {
1681 pt = (ips_passthru_t *) ha->ioctl_data;
1682 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1683 pt->BasicStatus = 0x0B;
1684 pt->ExtendedStatus = 0x00;
1685 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1686 }
1687 return IPS_FAILURE;
1688 }
1689 ha->ioctl_datasize = length;
1690
1691 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1692 pt = (ips_passthru_t *) ha->ioctl_data;
1693
1694 /*
1695 * Some notes about the passthru interface used
1696 *
1697 * IF the scsi op_code == 0x0d then we assume
1698 * that the data came along with/goes with the
1699 * packet we received from the sg driver. In this
1700 * case the CmdBSize field of the pt structure is
1701 * used for the size of the buffer.
1702 */
1703
1704 switch (pt->CoppCmd) {
1705 case IPS_NUMCTRLS:
1706 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1707 &ips_num_controllers, sizeof (int));
1708 ips_scmd_buf_write(SC, ha->ioctl_data,
1709 sizeof (ips_passthru_t) + sizeof (int));
1710 SC->result = DID_OK << 16;
1711
1712 return (IPS_SUCCESS_IMM);
1713
1714 case IPS_COPPUSRCMD:
1715 case IPS_COPPIOCCMD:
1716 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1717 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1718 /* wrong size */
1719 DEBUG_VAR(1,
1720 "(%s%d) Passthru structure wrong size",
1721 ips_name, ha->host_num);
1722
1723 return (IPS_FAILURE);
1724 }
1725
1726 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
1727 pt->CoppCP.cmd.flashfw.op_code ==
1728 IPS_CMD_RW_BIOSFW) {
1729 ret = ips_flash_copperhead(ha, pt, scb);
1730 ips_scmd_buf_write(SC, ha->ioctl_data,
1731 sizeof (ips_passthru_t));
1732 return ret;
1733 }
1734 if (ips_usrcmd(ha, pt, scb))
1735 return (IPS_SUCCESS);
1736 else
1737 return (IPS_FAILURE);
1738 }
1739
1740 break;
1741
1742 } /* end switch */
1743
1744 return (IPS_FAILURE);
1745}
1746
1747/****************************************************************************/
1748/* Routine Name: ips_flash_copperhead */
1749/* Routine Description: */
1750/* Flash the BIOS/FW on a Copperhead style controller */
1751/****************************************************************************/
1752static int
1753ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1754{
1755 int datasize;
1756
1757 /* Trombone is the only copperhead that can do packet flash, but only
1758 * for firmware. No one said it had to make sence. */
1759 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1760 if (ips_usrcmd(ha, pt, scb))
1761 return IPS_SUCCESS;
1762 else
1763 return IPS_FAILURE;
1764 }
1765 pt->BasicStatus = 0x0B;
1766 pt->ExtendedStatus = 0;
1767 scb->scsi_cmd->result = DID_OK << 16;
1768 /* IF it's OK to Use the "CD BOOT" Flash Buffer, then you can */
1769 /* avoid allocating a huge buffer per adapter ( which can fail ). */
1770 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1771 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1772 pt->BasicStatus = 0;
1773 return ips_flash_bios(ha, pt, scb);
1774 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1775 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1776 ha->flash_data = ips_FlashData;
1777 ha->flash_busaddr = ips_flashbusaddr;
1778 ha->flash_len = PAGE_SIZE << 7;
1779 ha->flash_datasize = 0;
1780 } else if (!ha->flash_data) {
1781 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1782 pt->CoppCP.cmd.flashfw.count;
1783 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1784 datasize,
1785 &ha->flash_busaddr);
1786 if (!ha->flash_data){
1787 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1788 return IPS_FAILURE;
1789 }
1790 ha->flash_datasize = 0;
1791 ha->flash_len = datasize;
1792 } else
1793 return IPS_FAILURE;
1794 } else {
1795 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1796 ha->flash_len) {
1797 ips_free_flash_copperhead(ha);
1798 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1799 "failed size sanity check\n");
1800 return IPS_FAILURE;
1801 }
1802 }
1803 if (!ha->flash_data)
1804 return IPS_FAILURE;
1805 pt->BasicStatus = 0;
1806 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1807 pt->CoppCP.cmd.flashfw.count);
1808 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1809 if (pt->CoppCP.cmd.flashfw.packet_num ==
1810 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1811 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1812 return ips_flash_bios(ha, pt, scb);
1813 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1814 return ips_flash_firmware(ha, pt, scb);
1815 }
1816 return IPS_SUCCESS_IMM;
1817}
1818
1819/****************************************************************************/
1820/* Routine Name: ips_flash_bios */
1821/* Routine Description: */
1822/* flashes the bios of a copperhead adapter */
1823/****************************************************************************/
1824static int
1825ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1826{
1827
1828 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1829 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1830 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1831 (!ha->func.verifybios))
1832 goto error;
1833 if ((*ha->func.erasebios) (ha)) {
1834 DEBUG_VAR(1,
1835 "(%s%d) flash bios failed - unable to erase flash",
1836 ips_name, ha->host_num);
1837 goto error;
1838 } else
1839 if ((*ha->func.programbios) (ha,
1840 ha->flash_data +
1841 IPS_BIOS_HEADER,
1842 ha->flash_datasize -
1843 IPS_BIOS_HEADER, 0)) {
1844 DEBUG_VAR(1,
1845 "(%s%d) flash bios failed - unable to flash",
1846 ips_name, ha->host_num);
1847 goto error;
1848 } else
1849 if ((*ha->func.verifybios) (ha,
1850 ha->flash_data +
1851 IPS_BIOS_HEADER,
1852 ha->flash_datasize -
1853 IPS_BIOS_HEADER, 0)) {
1854 DEBUG_VAR(1,
1855 "(%s%d) flash bios failed - unable to verify flash",
1856 ips_name, ha->host_num);
1857 goto error;
1858 }
1859 ips_free_flash_copperhead(ha);
1860 return IPS_SUCCESS_IMM;
1861 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1862 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1863 if (!ha->func.erasebios)
1864 goto error;
1865 if ((*ha->func.erasebios) (ha)) {
1866 DEBUG_VAR(1,
1867 "(%s%d) flash bios failed - unable to erase flash",
1868 ips_name, ha->host_num);
1869 goto error;
1870 }
1871 return IPS_SUCCESS_IMM;
1872 }
1873 error:
1874 pt->BasicStatus = 0x0B;
1875 pt->ExtendedStatus = 0x00;
1876 ips_free_flash_copperhead(ha);
1877 return IPS_FAILURE;
1878}
1879
1880/****************************************************************************/
1881/* */
1882/* Routine Name: ips_fill_scb_sg_single */
1883/* */
1884/* Routine Description: */
1885/* Fill in a single scb sg_list element from an address */
1886/* return a -1 if a breakup occurred */
1887/****************************************************************************/
1888static int
1889ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1890 ips_scb_t * scb, int indx, unsigned int e_len)
1891{
1892
1893 int ret_val = 0;
1894
1895 if ((scb->data_len + e_len) > ha->max_xfer) {
1896 e_len = ha->max_xfer - scb->data_len;
1897 scb->breakup = indx;
1898 ++scb->sg_break;
1899 ret_val = -1;
1900 } else {
1901 scb->breakup = 0;
1902 scb->sg_break = 0;
1903 }
1904 if (IPS_USE_ENH_SGLIST(ha)) {
1905 scb->sg_list.enh_list[indx].address_lo =
1906 cpu_to_le32(pci_dma_lo32(busaddr));
1907 scb->sg_list.enh_list[indx].address_hi =
1908 cpu_to_le32(pci_dma_hi32(busaddr));
1909 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1910 } else {
1911 scb->sg_list.std_list[indx].address =
1912 cpu_to_le32(pci_dma_lo32(busaddr));
1913 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1914 }
1915
1916 ++scb->sg_len;
1917 scb->data_len += e_len;
1918 return ret_val;
1919}
1920
1921/****************************************************************************/
1922/* Routine Name: ips_flash_firmware */
1923/* Routine Description: */
1924/* flashes the firmware of a copperhead adapter */
1925/****************************************************************************/
1926static int
1927ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1928{
1929 IPS_SG_LIST sg_list;
1930 uint32_t cmd_busaddr;
1931
1932 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1933 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1934 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1935 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1936 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1937 } else {
1938 pt->BasicStatus = 0x0B;
1939 pt->ExtendedStatus = 0x00;
1940 ips_free_flash_copperhead(ha);
1941 return IPS_FAILURE;
1942 }
1943 /* Save the S/G list pointer so it doesn't get clobbered */
1944 sg_list.list = scb->sg_list.list;
1945 cmd_busaddr = scb->scb_busaddr;
1946 /* copy in the CP */
1947 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1948 /* FIX stuff that might be wrong */
1949 scb->sg_list.list = sg_list.list;
1950 scb->scb_busaddr = cmd_busaddr;
1951 scb->bus = scb->scsi_cmd->device->channel;
1952 scb->target_id = scb->scsi_cmd->device->id;
1953 scb->lun = scb->scsi_cmd->device->lun;
1954 scb->sg_len = 0;
1955 scb->data_len = 0;
1956 scb->flags = 0;
1957 scb->op_code = 0;
1958 scb->callback = ipsintr_done;
1959 scb->timeout = ips_cmd_timeout;
1960
1961 scb->data_len = ha->flash_datasize;
1962 scb->data_busaddr =
1963 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1964 IPS_DMA_DIR(scb));
1965 scb->flags |= IPS_SCB_MAP_SINGLE;
1966 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1967 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1968 if (pt->TimeOut)
1969 scb->timeout = pt->TimeOut;
1970 scb->scsi_cmd->result = DID_OK << 16;
1971 return IPS_SUCCESS;
1972}
1973
1974/****************************************************************************/
1975/* Routine Name: ips_free_flash_copperhead */
1976/* Routine Description: */
1977/* release the memory resources used to hold the flash image */
1978/****************************************************************************/
1979static void
1980ips_free_flash_copperhead(ips_ha_t * ha)
1981{
1982 if (ha->flash_data == ips_FlashData)
1983 test_and_clear_bit(0, &ips_FlashDataInUse);
1984 else if (ha->flash_data)
1985 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1986 ha->flash_busaddr);
1987 ha->flash_data = NULL;
1988}
1989
1990/****************************************************************************/
1991/* */
1992/* Routine Name: ips_usrcmd */
1993/* */
1994/* Routine Description: */
1995/* */
1996/* Process a user command and make it ready to send */
1997/* */
1998/****************************************************************************/
1999static int
2000ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
2001{
2002 IPS_SG_LIST sg_list;
2003 uint32_t cmd_busaddr;
2004
2005 METHOD_TRACE("ips_usrcmd", 1);
2006
2007 if ((!scb) || (!pt) || (!ha))
2008 return (0);
2009
2010 /* Save the S/G list pointer so it doesn't get clobbered */
2011 sg_list.list = scb->sg_list.list;
2012 cmd_busaddr = scb->scb_busaddr;
2013 /* copy in the CP */
2014 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
2015 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
2016
2017 /* FIX stuff that might be wrong */
2018 scb->sg_list.list = sg_list.list;
2019 scb->scb_busaddr = cmd_busaddr;
2020 scb->bus = scb->scsi_cmd->device->channel;
2021 scb->target_id = scb->scsi_cmd->device->id;
2022 scb->lun = scb->scsi_cmd->device->lun;
2023 scb->sg_len = 0;
2024 scb->data_len = 0;
2025 scb->flags = 0;
2026 scb->op_code = 0;
2027 scb->callback = ipsintr_done;
2028 scb->timeout = ips_cmd_timeout;
2029 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
2030
2031 /* we don't support DCDB/READ/WRITE Scatter Gather */
2032 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
2033 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
2034 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
2035 return (0);
2036
2037 if (pt->CmdBSize) {
2038 scb->data_len = pt->CmdBSize;
2039 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
2040 } else {
2041 scb->data_busaddr = 0L;
2042 }
2043
2044 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2045 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
2046 (unsigned long) &scb->
2047 dcdb -
2048 (unsigned long) scb);
2049
2050 if (pt->CmdBSize) {
2051 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2052 scb->dcdb.buffer_pointer =
2053 cpu_to_le32(scb->data_busaddr);
2054 else
2055 scb->cmd.basic_io.sg_addr =
2056 cpu_to_le32(scb->data_busaddr);
2057 }
2058
2059 /* set timeouts */
2060 if (pt->TimeOut) {
2061 scb->timeout = pt->TimeOut;
2062
2063 if (pt->TimeOut <= 10)
2064 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
2065 else if (pt->TimeOut <= 60)
2066 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
2067 else
2068 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
2069 }
2070
2071 /* assume success */
2072 scb->scsi_cmd->result = DID_OK << 16;
2073
2074 /* success */
2075 return (1);
2076}
2077
2078/****************************************************************************/
2079/* */
2080/* Routine Name: ips_cleanup_passthru */
2081/* */
2082/* Routine Description: */
2083/* */
2084/* Cleanup after a passthru command */
2085/* */
2086/****************************************************************************/
2087static void
2088ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
2089{
2090 ips_passthru_t *pt;
2091
2092 METHOD_TRACE("ips_cleanup_passthru", 1);
2093
2094 if ((!scb) || (!scb->scsi_cmd) || (!scb->scsi_cmd->request_buffer)) {
2095 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2096 ips_name, ha->host_num);
2097
2098 return;
2099 }
2100 pt = (ips_passthru_t *) ha->ioctl_data;
2101
2102 /* Copy data back to the user */
2103 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB) /* Copy DCDB Back to Caller's Area */
2104 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2105
2106 pt->BasicStatus = scb->basic_status;
2107 pt->ExtendedStatus = scb->extended_status;
2108 pt->AdapterType = ha->ad_type;
2109
2110 if (ha->device_id == IPS_DEVICEID_COPPERHEAD &&
2111 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2112 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2113 ips_free_flash_copperhead(ha);
2114
2115 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2116}
2117
2118/****************************************************************************/
2119/* */
2120/* Routine Name: ips_host_info */
2121/* */
2122/* Routine Description: */
2123/* */
2124/* The passthru interface for the driver */
2125/* */
2126/****************************************************************************/
2127static int
2128ips_host_info(ips_ha_t * ha, char *ptr, off_t offset, int len)
2129{
2130 IPS_INFOSTR info;
2131
2132 METHOD_TRACE("ips_host_info", 1);
2133
2134 info.buffer = ptr;
2135 info.length = len;
2136 info.offset = offset;
2137 info.pos = 0;
2138 info.localpos = 0;
2139
2140 copy_info(&info, "\nIBM ServeRAID General Information:\n\n");
2141
2142 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2143 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2144 copy_info(&info, "\tController Type : %s\n",
2145 ips_adapter_name[ha->ad_type - 1]);
2146 else
2147 copy_info(&info,
2148 "\tController Type : Unknown\n");
2149
2150 if (ha->io_addr)
2151 copy_info(&info,
2152 "\tIO region : 0x%lx (%d bytes)\n",
2153 ha->io_addr, ha->io_len);
2154
2155 if (ha->mem_addr) {
2156 copy_info(&info,
2157 "\tMemory region : 0x%lx (%d bytes)\n",
2158 ha->mem_addr, ha->mem_len);
2159 copy_info(&info,
2160 "\tShared memory address : 0x%lx\n",
2161 ha->mem_ptr);
2162 }
2163
2164 copy_info(&info, "\tIRQ number : %d\n", ha->irq);
2165
2166 /* For the Next 3 lines Check for Binary 0 at the end and don't include it if it's there. */
2167 /* That keeps everything happy for "text" operations on the proc file. */
2168
2169 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2170 if (ha->nvram->bios_low[3] == 0) {
2171 copy_info(&info,
2172 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2173 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2174 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2175 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2176 ha->nvram->bios_low[2]);
2177
2178 } else {
2179 copy_info(&info,
2180 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2181 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2182 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2183 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2184 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2185 }
2186
2187 }
2188
2189 if (ha->enq->CodeBlkVersion[7] == 0) {
2190 copy_info(&info,
2191 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2192 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2193 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2194 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2195 ha->enq->CodeBlkVersion[6]);
2196 } else {
2197 copy_info(&info,
2198 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2199 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2200 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2201 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2202 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2203 }
2204
2205 if (ha->enq->BootBlkVersion[7] == 0) {
2206 copy_info(&info,
2207 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2208 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2209 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2210 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2211 ha->enq->BootBlkVersion[6]);
2212 } else {
2213 copy_info(&info,
2214 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2215 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2216 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2217 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2218 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2219 }
2220
2221 copy_info(&info, "\tDriver Version : %s%s\n",
2222 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2223
2224 copy_info(&info, "\tDriver Build : %d\n",
2225 IPS_BUILD_IDENT);
2226
2227 copy_info(&info, "\tMax Physical Devices : %d\n",
2228 ha->enq->ucMaxPhysicalDevices);
2229 copy_info(&info, "\tMax Active Commands : %d\n",
2230 ha->max_cmds);
2231 copy_info(&info, "\tCurrent Queued Commands : %d\n",
2232 ha->scb_waitlist.count);
2233 copy_info(&info, "\tCurrent Active Commands : %d\n",
2234 ha->scb_activelist.count - ha->num_ioctl);
2235 copy_info(&info, "\tCurrent Queued PT Commands : %d\n",
2236 ha->copp_waitlist.count);
2237 copy_info(&info, "\tCurrent Active PT Commands : %d\n",
2238 ha->num_ioctl);
2239
2240 copy_info(&info, "\n");
2241
2242 return (info.localpos);
2243}
2244
2245/****************************************************************************/
2246/* */
2247/* Routine Name: copy_mem_info */
2248/* */
2249/* Routine Description: */
2250/* */
2251/* Copy data into an IPS_INFOSTR structure */
2252/* */
2253/****************************************************************************/
2254static void
2255copy_mem_info(IPS_INFOSTR * info, char *data, int len)
2256{
2257 METHOD_TRACE("copy_mem_info", 1);
2258
2259 if (info->pos + len < info->offset) {
2260 info->pos += len;
2261 return;
2262 }
2263
2264 if (info->pos < info->offset) {
2265 data += (info->offset - info->pos);
2266 len -= (info->offset - info->pos);
2267 info->pos += (info->offset - info->pos);
2268 }
2269
2270 if (info->localpos + len > info->length)
2271 len = info->length - info->localpos;
2272
2273 if (len > 0) {
2274 memcpy(info->buffer + info->localpos, data, len);
2275 info->pos += len;
2276 info->localpos += len;
2277 }
2278}
2279
2280/****************************************************************************/
2281/* */
2282/* Routine Name: copy_info */
2283/* */
2284/* Routine Description: */
2285/* */
2286/* printf style wrapper for an info structure */
2287/* */
2288/****************************************************************************/
2289static int
2290copy_info(IPS_INFOSTR * info, char *fmt, ...)
2291{
2292 va_list args;
2293 char buf[128];
2294 int len;
2295
2296 METHOD_TRACE("copy_info", 1);
2297
2298 va_start(args, fmt);
2299 len = vsprintf(buf, fmt, args);
2300 va_end(args);
2301
2302 copy_mem_info(info, buf, len);
2303
2304 return (len);
2305}
2306
2307/****************************************************************************/
2308/* */
2309/* Routine Name: ips_identify_controller */
2310/* */
2311/* Routine Description: */
2312/* */
2313/* Identify this controller */
2314/* */
2315/****************************************************************************/
2316static void
2317ips_identify_controller(ips_ha_t * ha)
2318{
2319 METHOD_TRACE("ips_identify_controller", 1);
2320
2321 switch (ha->device_id) {
2322 case IPS_DEVICEID_COPPERHEAD:
2323 if (ha->revision_id <= IPS_REVID_SERVERAID) {
2324 ha->ad_type = IPS_ADTYPE_SERVERAID;
2325 } else if (ha->revision_id == IPS_REVID_SERVERAID2) {
2326 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2327 } else if (ha->revision_id == IPS_REVID_NAVAJO) {
2328 ha->ad_type = IPS_ADTYPE_NAVAJO;
2329 } else if ((ha->revision_id == IPS_REVID_SERVERAID2)
2330 && (ha->slot_num == 0)) {
2331 ha->ad_type = IPS_ADTYPE_KIOWA;
2332 } else if ((ha->revision_id >= IPS_REVID_CLARINETP1) &&
2333 (ha->revision_id <= IPS_REVID_CLARINETP3)) {
2334 if (ha->enq->ucMaxPhysicalDevices == 15)
2335 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2336 else
2337 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2338 } else if ((ha->revision_id >= IPS_REVID_TROMBONE32) &&
2339 (ha->revision_id <= IPS_REVID_TROMBONE64)) {
2340 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2341 }
2342 break;
2343
2344 case IPS_DEVICEID_MORPHEUS:
2345 switch (ha->subdevice_id) {
2346 case IPS_SUBDEVICEID_4L:
2347 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2348 break;
2349
2350 case IPS_SUBDEVICEID_4M:
2351 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2352 break;
2353
2354 case IPS_SUBDEVICEID_4MX:
2355 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2356 break;
2357
2358 case IPS_SUBDEVICEID_4LX:
2359 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2360 break;
2361
2362 case IPS_SUBDEVICEID_5I2:
2363 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2364 break;
2365
2366 case IPS_SUBDEVICEID_5I1:
2367 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2368 break;
2369 }
2370
2371 break;
2372
2373 case IPS_DEVICEID_MARCO:
2374 switch (ha->subdevice_id) {
2375 case IPS_SUBDEVICEID_6M:
2376 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2377 break;
2378 case IPS_SUBDEVICEID_6I:
2379 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2380 break;
2381 case IPS_SUBDEVICEID_7k:
2382 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2383 break;
2384 case IPS_SUBDEVICEID_7M:
2385 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2386 break;
2387 }
2388 break;
2389 }
2390}
2391
2392/****************************************************************************/
2393/* */
2394/* Routine Name: ips_get_bios_version */
2395/* */
2396/* Routine Description: */
2397/* */
2398/* Get the BIOS revision number */
2399/* */
2400/****************************************************************************/
2401static void
2402ips_get_bios_version(ips_ha_t * ha, int intr)
2403{
2404 ips_scb_t *scb;
2405 int ret;
2406 uint8_t major;
2407 uint8_t minor;
2408 uint8_t subminor;
2409 uint8_t *buffer;
2410 char hexDigits[] =
2411 { '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
2412 'D', 'E', 'F' };
2413
2414 METHOD_TRACE("ips_get_bios_version", 1);
2415
2416 major = 0;
2417 minor = 0;
2418
2419 strncpy(ha->bios_version, " ?", 8);
2420
2421 if (ha->device_id == IPS_DEVICEID_COPPERHEAD) {
2422 if (IPS_USE_MEMIO(ha)) {
2423 /* Memory Mapped I/O */
2424
2425 /* test 1st byte */
2426 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2427 if (ha->revision_id == IPS_REVID_TROMBONE64)
2428 udelay(25); /* 25 us */
2429
2430 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2431 return;
2432
2433 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2434 if (ha->revision_id == IPS_REVID_TROMBONE64)
2435 udelay(25); /* 25 us */
2436
2437 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2438 return;
2439
2440 /* Get Major version */
2441 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2442 if (ha->revision_id == IPS_REVID_TROMBONE64)
2443 udelay(25); /* 25 us */
2444
2445 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2446
2447 /* Get Minor version */
2448 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2449 if (ha->revision_id == IPS_REVID_TROMBONE64)
2450 udelay(25); /* 25 us */
2451 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2452
2453 /* Get SubMinor version */
2454 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2455 if (ha->revision_id == IPS_REVID_TROMBONE64)
2456 udelay(25); /* 25 us */
2457 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2458
2459 } else {
2460 /* Programmed I/O */
2461
2462 /* test 1st byte */
2463 outl(0, ha->io_addr + IPS_REG_FLAP);
2464 if (ha->revision_id == IPS_REVID_TROMBONE64)
2465 udelay(25); /* 25 us */
2466
2467 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2468 return;
2469
2470 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
2471 if (ha->revision_id == IPS_REVID_TROMBONE64)
2472 udelay(25); /* 25 us */
2473
2474 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2475 return;
2476
2477 /* Get Major version */
2478 outl(cpu_to_le32(0x1FF), ha->io_addr + IPS_REG_FLAP);
2479 if (ha->revision_id == IPS_REVID_TROMBONE64)
2480 udelay(25); /* 25 us */
2481
2482 major = inb(ha->io_addr + IPS_REG_FLDP);
2483
2484 /* Get Minor version */
2485 outl(cpu_to_le32(0x1FE), ha->io_addr + IPS_REG_FLAP);
2486 if (ha->revision_id == IPS_REVID_TROMBONE64)
2487 udelay(25); /* 25 us */
2488
2489 minor = inb(ha->io_addr + IPS_REG_FLDP);
2490
2491 /* Get SubMinor version */
2492 outl(cpu_to_le32(0x1FD), ha->io_addr + IPS_REG_FLAP);
2493 if (ha->revision_id == IPS_REVID_TROMBONE64)
2494 udelay(25); /* 25 us */
2495
2496 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2497
2498 }
2499 } else {
2500 /* Morpheus Family - Send Command to the card */
2501
2502 buffer = ha->ioctl_data;
2503
2504 memset(buffer, 0, 0x1000);
2505
2506 scb = &ha->scbs[ha->max_cmds - 1];
2507
2508 ips_init_scb(ha, scb);
2509
2510 scb->timeout = ips_cmd_timeout;
2511 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2512
2513 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2514 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2515 scb->cmd.flashfw.type = 1;
2516 scb->cmd.flashfw.direction = 0;
2517 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2518 scb->cmd.flashfw.total_packets = 1;
2519 scb->cmd.flashfw.packet_num = 0;
2520 scb->data_len = 0x1000;
2521 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2522
2523 /* issue the command */
2524 if (((ret =
2525 ips_send_wait(ha, scb, ips_cmd_timeout,
2526 intr)) == IPS_FAILURE)
2527 || (ret == IPS_SUCCESS_IMM)
2528 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2529 /* Error occurred */
2530
2531 return;
2532 }
2533
2534 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2535 major = buffer[0x1ff + 0xC0]; /* Offset 0x1ff after the header (0xc0) */
2536 minor = buffer[0x1fe + 0xC0]; /* Offset 0x1fe after the header (0xc0) */
2537 subminor = buffer[0x1fd + 0xC0]; /* Offset 0x1fd after the header (0xc0) */
2538 } else {
2539 return;
2540 }
2541 }
2542
2543 ha->bios_version[0] = hexDigits[(major & 0xF0) >> 4];
2544 ha->bios_version[1] = '.';
2545 ha->bios_version[2] = hexDigits[major & 0x0F];
2546 ha->bios_version[3] = hexDigits[subminor];
2547 ha->bios_version[4] = '.';
2548 ha->bios_version[5] = hexDigits[(minor & 0xF0) >> 4];
2549 ha->bios_version[6] = hexDigits[minor & 0x0F];
2550 ha->bios_version[7] = 0;
2551}
2552
2553/****************************************************************************/
2554/* */
2555/* Routine Name: ips_hainit */
2556/* */
2557/* Routine Description: */
2558/* */
2559/* Initialize the controller */
2560/* */
2561/* NOTE: Assumes to be called from with a lock */
2562/* */
2563/****************************************************************************/
2564static int
2565ips_hainit(ips_ha_t * ha)
2566{
2567 int i;
2568 struct timeval tv;
2569
2570 METHOD_TRACE("ips_hainit", 1);
2571
2572 if (!ha)
2573 return (0);
2574
2575 if (ha->func.statinit)
2576 (*ha->func.statinit) (ha);
2577
2578 if (ha->func.enableint)
2579 (*ha->func.enableint) (ha);
2580
2581 /* Send FFDC */
2582 ha->reset_count = 1;
2583 do_gettimeofday(&tv);
2584 ha->last_ffdc = tv.tv_sec;
2585 ips_ffdc_reset(ha, IPS_INTR_IORL);
2586
2587 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2588 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2589 "unable to read config from controller.\n");
2590
2591 return (0);
2592 }
2593 /* end if */
2594 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2595 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2596 "unable to read controller status.\n");
2597
2598 return (0);
2599 }
2600
2601 /* Identify this controller */
2602 ips_identify_controller(ha);
2603
2604 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2605 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2606 "unable to read subsystem parameters.\n");
2607
2608 return (0);
2609 }
2610
2611 /* write nvram user page 5 */
2612 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2613 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2614 "unable to write driver info to controller.\n");
2615
2616 return (0);
2617 }
2618
2619 /* If there are Logical Drives and a Reset Occurred, then an EraseStripeLock is Needed */
2620 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2621 ips_clear_adapter(ha, IPS_INTR_IORL);
2622
2623 /* set limits on SID, LUN, BUS */
2624 ha->ntargets = IPS_MAX_TARGETS + 1;
2625 ha->nlun = 1;
2626 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2627
2628 switch (ha->conf->logical_drive[0].ucStripeSize) {
2629 case 4:
2630 ha->max_xfer = 0x10000;
2631 break;
2632
2633 case 5:
2634 ha->max_xfer = 0x20000;
2635 break;
2636
2637 case 6:
2638 ha->max_xfer = 0x40000;
2639 break;
2640
2641 case 7:
2642 default:
2643 ha->max_xfer = 0x80000;
2644 break;
2645 }
2646
2647 /* setup max concurrent commands */
2648 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2649 /* Use the new method */
2650 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2651 } else {
2652 /* use the old method */
2653 switch (ha->conf->logical_drive[0].ucStripeSize) {
2654 case 4:
2655 ha->max_cmds = 32;
2656 break;
2657
2658 case 5:
2659 ha->max_cmds = 16;
2660 break;
2661
2662 case 6:
2663 ha->max_cmds = 8;
2664 break;
2665
2666 case 7:
2667 default:
2668 ha->max_cmds = 4;
2669 break;
2670 }
2671 }
2672
2673 /* Limit the Active Commands on a Lite Adapter */
2674 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2675 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2676 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2677 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2678 ha->max_cmds = MaxLiteCmds;
2679 }
2680
2681 /* set controller IDs */
2682 ha->ha_id[0] = IPS_ADAPTER_ID;
2683 for (i = 1; i < ha->nbus; i++) {
2684 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2685 ha->dcdb_active[i - 1] = 0;
2686 }
2687
2688 return (1);
2689}
2690
2691/****************************************************************************/
2692/* */
2693/* Routine Name: ips_next */
2694/* */
2695/* Routine Description: */
2696/* */
2697/* Take the next command off the queue and send it to the controller */
2698/* */
2699/****************************************************************************/
2700static void
2701ips_next(ips_ha_t * ha, int intr)
2702{
2703 ips_scb_t *scb;
2704 Scsi_Cmnd *SC;
2705 Scsi_Cmnd *p;
2706 Scsi_Cmnd *q;
2707 ips_copp_wait_item_t *item;
2708 int ret;
2709 unsigned long cpu_flags = 0;
2710 struct Scsi_Host *host;
2711 METHOD_TRACE("ips_next", 1);
2712
2713 if (!ha)
2714 return;
2715 host = ips_sh[ha->host_num];
2716 /*
2717 * Block access to the queue function so
2718 * this command won't time out
2719 */
2720 if (intr == IPS_INTR_ON)
2721 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2722
2723 if ((ha->subsys->param[3] & 0x300000)
2724 && (ha->scb_activelist.count == 0)) {
2725 struct timeval tv;
2726
2727 do_gettimeofday(&tv);
2728
2729 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2730 ha->last_ffdc = tv.tv_sec;
2731 ips_ffdc_time(ha);
2732 }
2733 }
2734
2735 /*
2736 * Send passthru commands
2737 * These have priority over normal I/O
2738 * but shouldn't affect performance too much
2739 * since we limit the number that can be active
2740 * on the card at any one time
2741 */
2742 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2743 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2744
2745 item = ips_removeq_copp_head(&ha->copp_waitlist);
2746 ha->num_ioctl++;
2747 if (intr == IPS_INTR_ON)
2748 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2749 scb->scsi_cmd = item->scsi_cmd;
2750 kfree(item);
2751
2752 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2753
2754 if (intr == IPS_INTR_ON)
2755 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2756 switch (ret) {
2757 case IPS_FAILURE:
2758 if (scb->scsi_cmd) {
2759 scb->scsi_cmd->result = DID_ERROR << 16;
2760 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2761 }
2762
2763 ips_freescb(ha, scb);
2764 break;
2765 case IPS_SUCCESS_IMM:
2766 if (scb->scsi_cmd) {
2767 scb->scsi_cmd->result = DID_OK << 16;
2768 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2769 }
2770
2771 ips_freescb(ha, scb);
2772 break;
2773 default:
2774 break;
2775 } /* end case */
2776
2777 if (ret != IPS_SUCCESS) {
2778 ha->num_ioctl--;
2779 continue;
2780 }
2781
2782 ret = ips_send_cmd(ha, scb);
2783
2784 if (ret == IPS_SUCCESS)
2785 ips_putq_scb_head(&ha->scb_activelist, scb);
2786 else
2787 ha->num_ioctl--;
2788
2789 switch (ret) {
2790 case IPS_FAILURE:
2791 if (scb->scsi_cmd) {
2792 scb->scsi_cmd->result = DID_ERROR << 16;
2793 }
2794
2795 ips_freescb(ha, scb);
2796 break;
2797 case IPS_SUCCESS_IMM:
2798 ips_freescb(ha, scb);
2799 break;
2800 default:
2801 break;
2802 } /* end case */
2803
2804 }
2805
2806 /*
2807 * Send "Normal" I/O commands
2808 */
2809
2810 p = ha->scb_waitlist.head;
2811 while ((p) && (scb = ips_getscb(ha))) {
2812 if ((p->device->channel > 0)
2813 && (ha->
2814 dcdb_active[p->device->channel -
2815 1] & (1 << p->device->id))) {
2816 ips_freescb(ha, scb);
2817 p = (Scsi_Cmnd *) p->host_scribble;
2818 continue;
2819 }
2820
2821 q = p;
2822 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2823
2824 if (intr == IPS_INTR_ON)
2825 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags); /* Unlock HA after command is taken off queue */
2826
2827 SC->result = DID_OK;
2828 SC->host_scribble = NULL;
2829
2830 memset(SC->sense_buffer, 0, sizeof (SC->sense_buffer));
2831
2832 scb->target_id = SC->device->id;
2833 scb->lun = SC->device->lun;
2834 scb->bus = SC->device->channel;
2835 scb->scsi_cmd = SC;
2836 scb->breakup = 0;
2837 scb->data_len = 0;
2838 scb->callback = ipsintr_done;
2839 scb->timeout = ips_cmd_timeout;
2840 memset(&scb->cmd, 0, 16);
2841
2842 /* copy in the CDB */
2843 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2844
2845 /* Now handle the data buffer */
2846 if (SC->use_sg) {
2847 struct scatterlist *sg;
2848 int i;
2849
2850 sg = SC->request_buffer;
2851 scb->sg_count = pci_map_sg(ha->pcidev, sg, SC->use_sg,
2852 scsi_to_pci_dma_dir(SC->
2853 sc_data_direction));
2854 scb->flags |= IPS_SCB_MAP_SG;
2855 for (i = 0; i < scb->sg_count; i++) {
2856 if (ips_fill_scb_sg_single
2857 (ha, sg_dma_address(&sg[i]), scb, i,
2858 sg_dma_len(&sg[i])) < 0)
2859 break;
2860 }
2861 scb->dcdb.transfer_length = scb->data_len;
2862 } else {
2863 if (SC->request_bufflen) {
2864 scb->data_busaddr =
2865 pci_map_single(ha->pcidev,
2866 SC->request_buffer,
2867 SC->request_bufflen,
2868 scsi_to_pci_dma_dir(SC->
2869 sc_data_direction));
2870 scb->flags |= IPS_SCB_MAP_SINGLE;
2871 ips_fill_scb_sg_single(ha, scb->data_busaddr,
2872 scb, 0,
2873 SC->request_bufflen);
2874 scb->dcdb.transfer_length = scb->data_len;
2875 } else {
2876 scb->data_busaddr = 0L;
2877 scb->sg_len = 0;
2878 scb->data_len = 0;
2879 scb->dcdb.transfer_length = 0;
2880 }
2881
2882 }
2883
2884 scb->dcdb.cmd_attribute =
2885 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2886
2887 /* Allow a WRITE BUFFER Command to Have no Data */
2888 /* This is Used by Tape Flash Utilites */
2889 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) && (scb->data_len == 0))
2890 scb->dcdb.cmd_attribute = 0;
2891
2892 if (!(scb->dcdb.cmd_attribute & 0x3))
2893 scb->dcdb.transfer_length = 0;
2894
2895 if (scb->data_len >= IPS_MAX_XFER) {
2896 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2897 scb->dcdb.transfer_length = 0;
2898 }
2899 if (intr == IPS_INTR_ON)
2900 IPS_LOCK_SAVE(host->host_lock, cpu_flags);
2901
2902 ret = ips_send_cmd(ha, scb);
2903
2904 switch (ret) {
2905 case IPS_SUCCESS:
2906 ips_putq_scb_head(&ha->scb_activelist, scb);
2907 break;
2908 case IPS_FAILURE:
2909 if (scb->scsi_cmd) {
2910 scb->scsi_cmd->result = DID_ERROR << 16;
2911 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2912 }
2913
2914 if (scb->bus)
2915 ha->dcdb_active[scb->bus - 1] &=
2916 ~(1 << scb->target_id);
2917
2918 ips_freescb(ha, scb);
2919 break;
2920 case IPS_SUCCESS_IMM:
2921 if (scb->scsi_cmd)
2922 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2923
2924 if (scb->bus)
2925 ha->dcdb_active[scb->bus - 1] &=
2926 ~(1 << scb->target_id);
2927
2928 ips_freescb(ha, scb);
2929 break;
2930 default:
2931 break;
2932 } /* end case */
2933
2934 p = (Scsi_Cmnd *) p->host_scribble;
2935
2936 } /* end while */
2937
2938 if (intr == IPS_INTR_ON)
2939 IPS_UNLOCK_RESTORE(host->host_lock, cpu_flags);
2940}
2941
2942/****************************************************************************/
2943/* */
2944/* Routine Name: ips_putq_scb_head */
2945/* */
2946/* Routine Description: */
2947/* */
2948/* Add an item to the head of the queue */
2949/* */
2950/* ASSUMED to be called from within the HA lock */
2951/* */
2952/****************************************************************************/
2953static void
2954ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2955{
2956 METHOD_TRACE("ips_putq_scb_head", 1);
2957
2958 if (!item)
2959 return;
2960
2961 item->q_next = queue->head;
2962 queue->head = item;
2963
2964 if (!queue->tail)
2965 queue->tail = item;
2966
2967 queue->count++;
2968}
2969
2970/****************************************************************************/
2971/* */
2972/* Routine Name: ips_removeq_scb_head */
2973/* */
2974/* Routine Description: */
2975/* */
2976/* Remove the head of the queue */
2977/* */
2978/* ASSUMED to be called from within the HA lock */
2979/* */
2980/****************************************************************************/
2981static ips_scb_t *
2982ips_removeq_scb_head(ips_scb_queue_t * queue)
2983{
2984 ips_scb_t *item;
2985
2986 METHOD_TRACE("ips_removeq_scb_head", 1);
2987
2988 item = queue->head;
2989
2990 if (!item) {
2991 return (NULL);
2992 }
2993
2994 queue->head = item->q_next;
2995 item->q_next = NULL;
2996
2997 if (queue->tail == item)
2998 queue->tail = NULL;
2999
3000 queue->count--;
3001
3002 return (item);
3003}
3004
3005/****************************************************************************/
3006/* */
3007/* Routine Name: ips_removeq_scb */
3008/* */
3009/* Routine Description: */
3010/* */
3011/* Remove an item from a queue */
3012/* */
3013/* ASSUMED to be called from within the HA lock */
3014/* */
3015/****************************************************************************/
3016static ips_scb_t *
3017ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
3018{
3019 ips_scb_t *p;
3020
3021 METHOD_TRACE("ips_removeq_scb", 1);
3022
3023 if (!item)
3024 return (NULL);
3025
3026 if (item == queue->head) {
3027 return (ips_removeq_scb_head(queue));
3028 }
3029
3030 p = queue->head;
3031
3032 while ((p) && (item != p->q_next))
3033 p = p->q_next;
3034
3035 if (p) {
3036 /* found a match */
3037 p->q_next = item->q_next;
3038
3039 if (!item->q_next)
3040 queue->tail = p;
3041
3042 item->q_next = NULL;
3043 queue->count--;
3044
3045 return (item);
3046 }
3047
3048 return (NULL);
3049}
3050
3051/****************************************************************************/
3052/* */
3053/* Routine Name: ips_putq_wait_tail */
3054/* */
3055/* Routine Description: */
3056/* */
3057/* Add an item to the tail of the queue */
3058/* */
3059/* ASSUMED to be called from within the HA lock */
3060/* */
3061/****************************************************************************/
3062static void
3063ips_putq_wait_tail(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3064{
3065 METHOD_TRACE("ips_putq_wait_tail", 1);
3066
3067 if (!item)
3068 return;
3069
3070 item->host_scribble = NULL;
3071
3072 if (queue->tail)
3073 queue->tail->host_scribble = (char *) item;
3074
3075 queue->tail = item;
3076
3077 if (!queue->head)
3078 queue->head = item;
3079
3080 queue->count++;
3081}
3082
3083/****************************************************************************/
3084/* */
3085/* Routine Name: ips_removeq_wait_head */
3086/* */
3087/* Routine Description: */
3088/* */
3089/* Remove the head of the queue */
3090/* */
3091/* ASSUMED to be called from within the HA lock */
3092/* */
3093/****************************************************************************/
3094static Scsi_Cmnd *
3095ips_removeq_wait_head(ips_wait_queue_t * queue)
3096{
3097 Scsi_Cmnd *item;
3098
3099 METHOD_TRACE("ips_removeq_wait_head", 1);
3100
3101 item = queue->head;
3102
3103 if (!item) {
3104 return (NULL);
3105 }
3106
3107 queue->head = (Scsi_Cmnd *) item->host_scribble;
3108 item->host_scribble = NULL;
3109
3110 if (queue->tail == item)
3111 queue->tail = NULL;
3112
3113 queue->count--;
3114
3115 return (item);
3116}
3117
3118/****************************************************************************/
3119/* */
3120/* Routine Name: ips_removeq_wait */
3121/* */
3122/* Routine Description: */
3123/* */
3124/* Remove an item from a queue */
3125/* */
3126/* ASSUMED to be called from within the HA lock */
3127/* */
3128/****************************************************************************/
3129static Scsi_Cmnd *
3130ips_removeq_wait(ips_wait_queue_t * queue, Scsi_Cmnd * item)
3131{
3132 Scsi_Cmnd *p;
3133
3134 METHOD_TRACE("ips_removeq_wait", 1);
3135
3136 if (!item)
3137 return (NULL);
3138
3139 if (item == queue->head) {
3140 return (ips_removeq_wait_head(queue));
3141 }
3142
3143 p = queue->head;
3144
3145 while ((p) && (item != (Scsi_Cmnd *) p->host_scribble))
3146 p = (Scsi_Cmnd *) p->host_scribble;
3147
3148 if (p) {
3149 /* found a match */
3150 p->host_scribble = item->host_scribble;
3151
3152 if (!item->host_scribble)
3153 queue->tail = p;
3154
3155 item->host_scribble = NULL;
3156 queue->count--;
3157
3158 return (item);
3159 }
3160
3161 return (NULL);
3162}
3163
3164/****************************************************************************/
3165/* */
3166/* Routine Name: ips_putq_copp_tail */
3167/* */
3168/* Routine Description: */
3169/* */
3170/* Add an item to the tail of the queue */
3171/* */
3172/* ASSUMED to be called from within the HA lock */
3173/* */
3174/****************************************************************************/
3175static void
3176ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3177{
3178 METHOD_TRACE("ips_putq_copp_tail", 1);
3179
3180 if (!item)
3181 return;
3182
3183 item->next = NULL;
3184
3185 if (queue->tail)
3186 queue->tail->next = item;
3187
3188 queue->tail = item;
3189
3190 if (!queue->head)
3191 queue->head = item;
3192
3193 queue->count++;
3194}
3195
3196/****************************************************************************/
3197/* */
3198/* Routine Name: ips_removeq_copp_head */
3199/* */
3200/* Routine Description: */
3201/* */
3202/* Remove the head of the queue */
3203/* */
3204/* ASSUMED to be called from within the HA lock */
3205/* */
3206/****************************************************************************/
3207static ips_copp_wait_item_t *
3208ips_removeq_copp_head(ips_copp_queue_t * queue)
3209{
3210 ips_copp_wait_item_t *item;
3211
3212 METHOD_TRACE("ips_removeq_copp_head", 1);
3213
3214 item = queue->head;
3215
3216 if (!item) {
3217 return (NULL);
3218 }
3219
3220 queue->head = item->next;
3221 item->next = NULL;
3222
3223 if (queue->tail == item)
3224 queue->tail = NULL;
3225
3226 queue->count--;
3227
3228 return (item);
3229}
3230
3231/****************************************************************************/
3232/* */
3233/* Routine Name: ips_removeq_copp */
3234/* */
3235/* Routine Description: */
3236/* */
3237/* Remove an item from a queue */
3238/* */
3239/* ASSUMED to be called from within the HA lock */
3240/* */
3241/****************************************************************************/
3242static ips_copp_wait_item_t *
3243ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3244{
3245 ips_copp_wait_item_t *p;
3246
3247 METHOD_TRACE("ips_removeq_copp", 1);
3248
3249 if (!item)
3250 return (NULL);
3251
3252 if (item == queue->head) {
3253 return (ips_removeq_copp_head(queue));
3254 }
3255
3256 p = queue->head;
3257
3258 while ((p) && (item != p->next))
3259 p = p->next;
3260
3261 if (p) {
3262 /* found a match */
3263 p->next = item->next;
3264
3265 if (!item->next)
3266 queue->tail = p;
3267
3268 item->next = NULL;
3269 queue->count--;
3270
3271 return (item);
3272 }
3273
3274 return (NULL);
3275}
3276
3277/****************************************************************************/
3278/* */
3279/* Routine Name: ipsintr_blocking */
3280/* */
3281/* Routine Description: */
3282/* */
3283/* Finalize an interrupt for internal commands */
3284/* */
3285/****************************************************************************/
3286static void
3287ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3288{
3289 METHOD_TRACE("ipsintr_blocking", 2);
3290
3291 ips_freescb(ha, scb);
3292 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3293 ha->waitflag = FALSE;
3294
3295 return;
3296 }
3297}
3298
3299/****************************************************************************/
3300/* */
3301/* Routine Name: ipsintr_done */
3302/* */
3303/* Routine Description: */
3304/* */
3305/* Finalize an interrupt for non-internal commands */
3306/* */
3307/****************************************************************************/
3308static void
3309ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3310{
3311 METHOD_TRACE("ipsintr_done", 2);
3312
3313 if (!scb) {
3314 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3315 "Spurious interrupt; scb NULL.\n");
3316
3317 return;
3318 }
3319
3320 if (scb->scsi_cmd == NULL) {
3321 /* unexpected interrupt */
3322 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3323 "Spurious interrupt; scsi_cmd not set.\n");
3324
3325 return;
3326 }
3327
3328 ips_done(ha, scb);
3329}
3330
3331/****************************************************************************/
3332/* */
3333/* Routine Name: ips_done */
3334/* */
3335/* Routine Description: */
3336/* */
3337/* Do housekeeping on completed commands */
3338/* ASSUMED to be called form within the request lock */
3339/****************************************************************************/
3340static void
3341ips_done(ips_ha_t * ha, ips_scb_t * scb)
3342{
3343 int ret;
3344
3345 METHOD_TRACE("ips_done", 1);
3346
3347 if (!scb)
3348 return;
3349
3350 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3351 ips_cleanup_passthru(ha, scb);
3352 ha->num_ioctl--;
3353 } else {
3354 /*
3355 * Check to see if this command had too much
3356 * data and had to be broke up. If so, queue
3357 * the rest of the data and continue.
3358 */
3359 if ((scb->breakup) || (scb->sg_break)) {
3360 /* we had a data breakup */
3361 scb->data_len = 0;
3362
3363 if (scb->sg_count) {
3364 /* S/G request */
3365 struct scatterlist *sg;
3366 int ips_sg_index = 0;
3367 int sg_dma_index;
3368
3369 sg = scb->scsi_cmd->request_buffer;
3370
3371 /* Spin forward to last dma chunk */
3372 sg_dma_index = scb->breakup;
3373
3374 /* Take care of possible partial on last chunk */
3375 ips_fill_scb_sg_single(ha,
3376 sg_dma_address(&sg
3377 [sg_dma_index]),
3378 scb, ips_sg_index++,
3379 sg_dma_len(&sg
3380 [sg_dma_index]));
3381
3382 for (; sg_dma_index < scb->sg_count;
3383 sg_dma_index++) {
3384 if (ips_fill_scb_sg_single
3385 (ha,
3386 sg_dma_address(&sg[sg_dma_index]),
3387 scb, ips_sg_index++,
3388 sg_dma_len(&sg[sg_dma_index])) < 0)
3389 break;
3390
3391 }
3392
3393 } else {
3394 /* Non S/G Request */
3395 (void) ips_fill_scb_sg_single(ha,
3396 scb->
3397 data_busaddr +
3398 (scb->sg_break *
3399 ha->max_xfer),
3400 scb, 0,
3401 scb->scsi_cmd->
3402 request_bufflen -
3403 (scb->sg_break *
3404 ha->max_xfer));
3405 }
3406
3407 scb->dcdb.transfer_length = scb->data_len;
3408 scb->dcdb.cmd_attribute |=
3409 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3410
3411 if (!(scb->dcdb.cmd_attribute & 0x3))
3412 scb->dcdb.transfer_length = 0;
3413
3414 if (scb->data_len >= IPS_MAX_XFER) {
3415 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3416 scb->dcdb.transfer_length = 0;
3417 }
3418
3419 ret = ips_send_cmd(ha, scb);
3420
3421 switch (ret) {
3422 case IPS_FAILURE:
3423 if (scb->scsi_cmd) {
3424 scb->scsi_cmd->result = DID_ERROR << 16;
3425 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3426 }
3427
3428 ips_freescb(ha, scb);
3429 break;
3430 case IPS_SUCCESS_IMM:
3431 if (scb->scsi_cmd) {
3432 scb->scsi_cmd->result = DID_ERROR << 16;
3433 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3434 }
3435
3436 ips_freescb(ha, scb);
3437 break;
3438 default:
3439 break;
3440 } /* end case */
3441
3442 return;
3443 }
3444 } /* end if passthru */
3445
3446 if (scb->bus) {
3447 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3448 }
3449
3450 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3451
3452 ips_freescb(ha, scb);
3453}
3454
3455/****************************************************************************/
3456/* */
3457/* Routine Name: ips_map_status */
3458/* */
3459/* Routine Description: */
3460/* */
3461/* Map Controller Error codes to Linux Error Codes */
3462/* */
3463/****************************************************************************/
3464static int
3465ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3466{
3467 int errcode;
3468 int device_error;
3469 uint32_t transfer_len;
3470 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3471
3472 METHOD_TRACE("ips_map_status", 1);
3473
3474 if (scb->bus) {
3475 DEBUG_VAR(2,
3476 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3477 ips_name, ha->host_num,
3478 scb->scsi_cmd->device->channel,
3479 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3480 scb->basic_status, scb->extended_status,
3481 scb->extended_status ==
3482 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3483 scb->extended_status ==
3484 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3485 scb->extended_status ==
3486 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3487 }
3488
3489 /* default driver error */
3490 errcode = DID_ERROR;
3491 device_error = 0;
3492
3493 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3494 case IPS_CMD_TIMEOUT:
3495 errcode = DID_TIME_OUT;
3496 break;
3497
3498 case IPS_INVAL_OPCO:
3499 case IPS_INVAL_CMD_BLK:
3500 case IPS_INVAL_PARM_BLK:
3501 case IPS_LD_ERROR:
3502 case IPS_CMD_CMPLT_WERROR:
3503 break;
3504
3505 case IPS_PHYS_DRV_ERROR:
3506 switch (scb->extended_status) {
3507 case IPS_ERR_SEL_TO:
3508 if (scb->bus)
3509 errcode = DID_NO_CONNECT;
3510
3511 break;
3512
3513 case IPS_ERR_OU_RUN:
3514 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3515 (scb->cmd.dcdb.op_code ==
3516 IPS_CMD_EXTENDED_DCDB_SG)) {
3517 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3518 transfer_len = tapeDCDB->transfer_length;
3519 } else {
3520 transfer_len =
3521 (uint32_t) scb->dcdb.transfer_length;
3522 }
3523
3524 if ((scb->bus) && (transfer_len < scb->data_len)) {
3525 /* Underrun - set default to no error */
3526 errcode = DID_OK;
3527
3528 /* Restrict access to physical DASD */
3529 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
3530 ((((char *) scb->scsi_cmd->
3531 buffer)[0] & 0x1f) == TYPE_DISK)) {
3532 /* underflow -- no error */
3533 /* restrict access to physical DASD */
3534 errcode = DID_TIME_OUT;
3535 break;
3536 }
3537 } else
3538 errcode = DID_ERROR;
3539
3540 break;
3541
3542 case IPS_ERR_RECOVERY:
3543 /* don't fail recovered errors */
3544 if (scb->bus)
3545 errcode = DID_OK;
3546
3547 break;
3548
3549 case IPS_ERR_HOST_RESET:
3550 case IPS_ERR_DEV_RESET:
3551 errcode = DID_RESET;
3552 break;
3553
3554 case IPS_ERR_CKCOND:
3555 if (scb->bus) {
3556 if ((scb->cmd.dcdb.op_code ==
3557 IPS_CMD_EXTENDED_DCDB)
3558 || (scb->cmd.dcdb.op_code ==
3559 IPS_CMD_EXTENDED_DCDB_SG)) {
3560 tapeDCDB =
3561 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3562 memcpy(scb->scsi_cmd->sense_buffer,
3563 tapeDCDB->sense_info,
3564 sizeof (scb->scsi_cmd->
3565 sense_buffer));
3566 } else {
3567 memcpy(scb->scsi_cmd->sense_buffer,
3568 scb->dcdb.sense_info,
3569 sizeof (scb->scsi_cmd->
3570 sense_buffer));
3571 }
3572 device_error = 2; /* check condition */
3573 }
3574
3575 errcode = DID_OK;
3576
3577 break;
3578
3579 default:
3580 errcode = DID_ERROR;
3581 break;
3582
3583 } /* end switch */
3584 } /* end switch */
3585
3586 scb->scsi_cmd->result = device_error | (errcode << 16);
3587
3588 return (1);
3589}
3590
3591/****************************************************************************/
3592/* */
3593/* Routine Name: ips_send_wait */
3594/* */
3595/* Routine Description: */
3596/* */
3597/* Send a command to the controller and wait for it to return */
3598/* */
3599/* The FFDC Time Stamp use this function for the callback, but doesn't */
3600/* actually need to wait. */
3601/****************************************************************************/
3602static int
3603ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3604{
3605 int ret;
3606
3607 METHOD_TRACE("ips_send_wait", 1);
3608
3609 if (intr != IPS_FFDC) { /* Won't be Waiting if this is a Time Stamp */
3610 ha->waitflag = TRUE;
3611 ha->cmd_in_progress = scb->cdb[0];
3612 }
3613 scb->callback = ipsintr_blocking;
3614 ret = ips_send_cmd(ha, scb);
3615
3616 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3617 return (ret);
3618
3619 if (intr != IPS_FFDC) /* Don't Wait around if this is a Time Stamp */
3620 ret = ips_wait(ha, timeout, intr);
3621
3622 return (ret);
3623}
3624
3625/****************************************************************************/
3626/* */
3627/* Routine Name: ips_scmd_buf_write */
3628/* */
3629/* Routine Description: */
3630/* Write data to Scsi_Cmnd request_buffer at proper offsets */
3631/****************************************************************************/
3632static void
3633ips_scmd_buf_write(Scsi_Cmnd * scmd, void *data, unsigned
3634 int count)
3635{
3636 if (scmd->use_sg) {
3637 int i;
3638 unsigned int min_cnt, xfer_cnt;
3639 char *cdata = (char *) data;
3640 struct scatterlist *sg = scmd->request_buffer;
3641 for (i = 0, xfer_cnt = 0;
3642 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3643 if (!IPS_SG_ADDRESS(&sg[i]))
3644 return;
3645 min_cnt = min(count - xfer_cnt, sg[i].length);
3646 memcpy(IPS_SG_ADDRESS(&sg[i]), &cdata[xfer_cnt],
3647 min_cnt);
3648 xfer_cnt += min_cnt;
3649 }
3650
3651 } else {
3652 unsigned int min_cnt = min(count, scmd->request_bufflen);
3653 memcpy(scmd->request_buffer, data, min_cnt);
3654 }
3655}
3656
3657/****************************************************************************/
3658/* */
3659/* Routine Name: ips_scmd_buf_read */
3660/* */
3661/* Routine Description: */
3662/* Copy data from a Scsi_Cmnd to a new, linear buffer */
3663/****************************************************************************/
3664static void
3665ips_scmd_buf_read(Scsi_Cmnd * scmd, void *data, unsigned
3666 int count)
3667{
3668 if (scmd->use_sg) {
3669 int i;
3670 unsigned int min_cnt, xfer_cnt;
3671 char *cdata = (char *) data;
3672 struct scatterlist *sg = scmd->request_buffer;
3673 for (i = 0, xfer_cnt = 0;
3674 (i < scmd->use_sg) && (xfer_cnt < count); i++) {
3675 if (!IPS_SG_ADDRESS(&sg[i]))
3676 return;
3677 min_cnt = min(count - xfer_cnt, sg[i].length);
3678 memcpy(&cdata[xfer_cnt], IPS_SG_ADDRESS(&sg[i]),
3679 min_cnt);
3680 xfer_cnt += min_cnt;
3681 }
3682
3683 } else {
3684 unsigned int min_cnt = min(count, scmd->request_bufflen);
3685 memcpy(data, scmd->request_buffer, min_cnt);
3686 }
3687}
3688
3689/****************************************************************************/
3690/* */
3691/* Routine Name: ips_send_cmd */
3692/* */
3693/* Routine Description: */
3694/* */
3695/* Map SCSI commands to ServeRAID commands for logical drives */
3696/* */
3697/****************************************************************************/
3698static int
3699ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3700{
3701 int ret;
3702 char *sp;
3703 int device_error;
3704 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3705 int TimeOut;
3706
3707 METHOD_TRACE("ips_send_cmd", 1);
3708
3709 ret = IPS_SUCCESS;
3710
3711 if (!scb->scsi_cmd) {
3712 /* internal command */
3713
3714 if (scb->bus > 0) {
3715 /* Controller commands can't be issued */
3716 /* to real devices -- fail them */
3717 if ((ha->waitflag == TRUE) &&
3718 (ha->cmd_in_progress == scb->cdb[0])) {
3719 ha->waitflag = FALSE;
3720 }
3721
3722 return (1);
3723 }
3724 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3725 /* command to logical bus -- interpret */
3726 ret = IPS_SUCCESS_IMM;
3727
3728 switch (scb->scsi_cmd->cmnd[0]) {
3729 case ALLOW_MEDIUM_REMOVAL:
3730 case REZERO_UNIT:
3731 case ERASE:
3732 case WRITE_FILEMARKS:
3733 case SPACE:
3734 scb->scsi_cmd->result = DID_ERROR << 16;
3735 break;
3736
3737 case START_STOP:
3738 scb->scsi_cmd->result = DID_OK << 16;
3739
3740 case TEST_UNIT_READY:
3741 case INQUIRY:
3742 if (scb->target_id == IPS_ADAPTER_ID) {
3743 /*
3744 * Either we have a TUR
3745 * or we have a SCSI inquiry
3746 */
3747 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3748 scb->scsi_cmd->result = DID_OK << 16;
3749
3750 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3751 IPS_SCSI_INQ_DATA inquiry;
3752
3753 memset(&inquiry, 0,
3754 sizeof (IPS_SCSI_INQ_DATA));
3755
3756 inquiry.DeviceType =
3757 IPS_SCSI_INQ_TYPE_PROCESSOR;
3758 inquiry.DeviceTypeQualifier =
3759 IPS_SCSI_INQ_LU_CONNECTED;
3760 inquiry.Version = IPS_SCSI_INQ_REV2;
3761 inquiry.ResponseDataFormat =
3762 IPS_SCSI_INQ_RD_REV2;
3763 inquiry.AdditionalLength = 31;
3764 inquiry.Flags[0] =
3765 IPS_SCSI_INQ_Address16;
3766 inquiry.Flags[1] =
3767 IPS_SCSI_INQ_WBus16 |
3768 IPS_SCSI_INQ_Sync;
3769 strncpy(inquiry.VendorId, "IBM ",
3770 8);
3771 strncpy(inquiry.ProductId,
3772 "SERVERAID ", 16);
3773 strncpy(inquiry.ProductRevisionLevel,
3774 "1.00", 4);
3775
3776 ips_scmd_buf_write(scb->scsi_cmd,
3777 &inquiry,
3778 sizeof (inquiry));
3779
3780 scb->scsi_cmd->result = DID_OK << 16;
3781 }
3782 } else {
3783 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3784 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3785 scb->cmd.logical_info.reserved = 0;
3786 scb->cmd.logical_info.reserved2 = 0;
3787 scb->data_len = sizeof (IPS_LD_INFO);
3788 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3789 scb->flags = 0;
3790 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3791 ret = IPS_SUCCESS;
3792 }
3793
3794 break;
3795
3796 case REQUEST_SENSE:
3797 ips_reqsen(ha, scb);
3798 scb->scsi_cmd->result = DID_OK << 16;
3799 break;
3800
3801 case READ_6:
3802 case WRITE_6:
3803 if (!scb->sg_len) {
3804 scb->cmd.basic_io.op_code =
3805 (scb->scsi_cmd->cmnd[0] ==
3806 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3807 scb->cmd.basic_io.enhanced_sg = 0;
3808 scb->cmd.basic_io.sg_addr =
3809 cpu_to_le32(scb->data_busaddr);
3810 } else {
3811 scb->cmd.basic_io.op_code =
3812 (scb->scsi_cmd->cmnd[0] ==
3813 READ_6) ? IPS_CMD_READ_SG :
3814 IPS_CMD_WRITE_SG;
3815 scb->cmd.basic_io.enhanced_sg =
3816 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3817 scb->cmd.basic_io.sg_addr =
3818 cpu_to_le32(scb->sg_busaddr);
3819 }
3820
3821 scb->cmd.basic_io.segment_4G = 0;
3822 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3823 scb->cmd.basic_io.log_drv = scb->target_id;
3824 scb->cmd.basic_io.sg_count = scb->sg_len;
3825
3826 if (scb->cmd.basic_io.lba)
3827 scb->cmd.basic_io.lba =
3828 cpu_to_le32(le32_to_cpu
3829 (scb->cmd.basic_io.lba) +
3830 le16_to_cpu(scb->cmd.basic_io.
3831 sector_count));
3832 else
3833 scb->cmd.basic_io.lba =
3834 (((scb->scsi_cmd->
3835 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3836 cmnd[2] << 8) |
3837 (scb->scsi_cmd->cmnd[3]));
3838
3839 scb->cmd.basic_io.sector_count =
3840 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3841
3842 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3843 scb->cmd.basic_io.sector_count =
3844 cpu_to_le16(256);
3845
3846 ret = IPS_SUCCESS;
3847 break;
3848
3849 case READ_10:
3850 case WRITE_10:
3851 if (!scb->sg_len) {
3852 scb->cmd.basic_io.op_code =
3853 (scb->scsi_cmd->cmnd[0] ==
3854 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3855 scb->cmd.basic_io.enhanced_sg = 0;
3856 scb->cmd.basic_io.sg_addr =
3857 cpu_to_le32(scb->data_busaddr);
3858 } else {
3859 scb->cmd.basic_io.op_code =
3860 (scb->scsi_cmd->cmnd[0] ==
3861 READ_10) ? IPS_CMD_READ_SG :
3862 IPS_CMD_WRITE_SG;
3863 scb->cmd.basic_io.enhanced_sg =
3864 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3865 scb->cmd.basic_io.sg_addr =
3866 cpu_to_le32(scb->sg_busaddr);
3867 }
3868
3869 scb->cmd.basic_io.segment_4G = 0;
3870 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3871 scb->cmd.basic_io.log_drv = scb->target_id;
3872 scb->cmd.basic_io.sg_count = scb->sg_len;
3873
3874 if (scb->cmd.basic_io.lba)
3875 scb->cmd.basic_io.lba =
3876 cpu_to_le32(le32_to_cpu
3877 (scb->cmd.basic_io.lba) +
3878 le16_to_cpu(scb->cmd.basic_io.
3879 sector_count));
3880 else
3881 scb->cmd.basic_io.lba =
3882 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3883 scsi_cmd->
3884 cmnd[3]
3885 << 16) |
3886 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3887 scsi_cmd->cmnd[5]);
3888
3889 scb->cmd.basic_io.sector_count =
3890 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3891
3892 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3893 /*
3894 * This is a null condition
3895 * we don't have to do anything
3896 * so just return
3897 */
3898 scb->scsi_cmd->result = DID_OK << 16;
3899 } else
3900 ret = IPS_SUCCESS;
3901
3902 break;
3903
3904 case RESERVE:
3905 case RELEASE:
3906 scb->scsi_cmd->result = DID_OK << 16;
3907 break;
3908
3909 case MODE_SENSE:
3910 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3911 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3912 scb->cmd.basic_io.segment_4G = 0;
3913 scb->cmd.basic_io.enhanced_sg = 0;
3914 scb->data_len = sizeof (*ha->enq);
3915 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3916 ret = IPS_SUCCESS;
3917 break;
3918
3919 case READ_CAPACITY:
3920 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3921 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3922 scb->cmd.logical_info.reserved = 0;
3923 scb->cmd.logical_info.reserved2 = 0;
3924 scb->cmd.logical_info.reserved3 = 0;
3925 scb->data_len = sizeof (IPS_LD_INFO);
3926 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3927 scb->flags = 0;
3928 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3929 ret = IPS_SUCCESS;
3930 break;
3931
3932 case SEND_DIAGNOSTIC:
3933 case REASSIGN_BLOCKS:
3934 case FORMAT_UNIT:
3935 case SEEK_10:
3936 case VERIFY:
3937 case READ_DEFECT_DATA:
3938 case READ_BUFFER:
3939 case WRITE_BUFFER:
3940 scb->scsi_cmd->result = DID_OK << 16;
3941 break;
3942
3943 default:
3944 /* Set the Return Info to appear like the Command was */
3945 /* attempted, a Check Condition occurred, and Sense */
3946 /* Data indicating an Invalid CDB OpCode is returned. */
3947 sp = (char *) scb->scsi_cmd->sense_buffer;
3948 memset(sp, 0, sizeof (scb->scsi_cmd->sense_buffer));
3949
3950 sp[0] = 0x70; /* Error Code */
3951 sp[2] = ILLEGAL_REQUEST; /* Sense Key 5 Illegal Req. */
3952 sp[7] = 0x0A; /* Additional Sense Length */
3953 sp[12] = 0x20; /* ASC = Invalid OpCode */
3954 sp[13] = 0x00; /* ASCQ */
3955
3956 device_error = 2; /* Indicate Check Condition */
3957 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3958 break;
3959 } /* end switch */
3960 }
3961 /* end if */
3962 if (ret == IPS_SUCCESS_IMM)
3963 return (ret);
3964
3965 /* setup DCDB */
3966 if (scb->bus > 0) {
3967
3968 /* If we already know the Device is Not there, no need to attempt a Command */
3969 /* This also protects an NT FailOver Controller from getting CDB's sent to it */
3970 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3971 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3972 return (IPS_SUCCESS_IMM);
3973 }
3974
3975 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3976 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3977 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3978 (unsigned long) &scb->
3979 dcdb -
3980 (unsigned long) scb);
3981 scb->cmd.dcdb.reserved = 0;
3982 scb->cmd.dcdb.reserved2 = 0;
3983 scb->cmd.dcdb.reserved3 = 0;
3984 scb->cmd.dcdb.segment_4G = 0;
3985 scb->cmd.dcdb.enhanced_sg = 0;
3986
3987 TimeOut = scb->scsi_cmd->timeout_per_command;
3988
3989 if (ha->subsys->param[4] & 0x00100000) { /* If NEW Tape DCDB is Supported */
3990 if (!scb->sg_len) {
3991 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3992 } else {
3993 scb->cmd.dcdb.op_code =
3994 IPS_CMD_EXTENDED_DCDB_SG;
3995 scb->cmd.dcdb.enhanced_sg =
3996 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3997 }
3998
3999 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb; /* Use Same Data Area as Old DCDB Struct */
4000 tapeDCDB->device_address =
4001 ((scb->bus - 1) << 4) | scb->target_id;
4002 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4003 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K; /* Always Turn OFF 64K Size Flag */
4004
4005 if (TimeOut) {
4006 if (TimeOut < (10 * HZ))
4007 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4008 else if (TimeOut < (60 * HZ))
4009 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4010 else if (TimeOut < (1200 * HZ))
4011 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4012 }
4013
4014 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
4015 tapeDCDB->reserved_for_LUN = 0;
4016 tapeDCDB->transfer_length = scb->data_len;
4017 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
4018 tapeDCDB->buffer_pointer =
4019 cpu_to_le32(scb->sg_busaddr);
4020 else
4021 tapeDCDB->buffer_pointer =
4022 cpu_to_le32(scb->data_busaddr);
4023 tapeDCDB->sg_count = scb->sg_len;
4024 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
4025 tapeDCDB->scsi_status = 0;
4026 tapeDCDB->reserved = 0;
4027 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
4028 scb->scsi_cmd->cmd_len);
4029 } else {
4030 if (!scb->sg_len) {
4031 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
4032 } else {
4033 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
4034 scb->cmd.dcdb.enhanced_sg =
4035 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
4036 }
4037
4038 scb->dcdb.device_address =
4039 ((scb->bus - 1) << 4) | scb->target_id;
4040 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
4041
4042 if (TimeOut) {
4043 if (TimeOut < (10 * HZ))
4044 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10; /* TimeOut is 10 Seconds */
4045 else if (TimeOut < (60 * HZ))
4046 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60; /* TimeOut is 60 Seconds */
4047 else if (TimeOut < (1200 * HZ))
4048 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M; /* TimeOut is 20 Minutes */
4049 }
4050
4051 scb->dcdb.transfer_length = scb->data_len;
4052 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
4053 scb->dcdb.transfer_length = 0;
4054 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
4055 scb->dcdb.buffer_pointer =
4056 cpu_to_le32(scb->sg_busaddr);
4057 else
4058 scb->dcdb.buffer_pointer =
4059 cpu_to_le32(scb->data_busaddr);
4060 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
4061 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
4062 scb->dcdb.sg_count = scb->sg_len;
4063 scb->dcdb.reserved = 0;
4064 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
4065 scb->scsi_cmd->cmd_len);
4066 scb->dcdb.scsi_status = 0;
4067 scb->dcdb.reserved2[0] = 0;
4068 scb->dcdb.reserved2[1] = 0;
4069 scb->dcdb.reserved2[2] = 0;
4070 }
4071 }
4072
4073 return ((*ha->func.issue) (ha, scb));
4074}
4075
4076/****************************************************************************/
4077/* */
4078/* Routine Name: ips_chk_status */
4079/* */
4080/* Routine Description: */
4081/* */
4082/* Check the status of commands to logical drives */
4083/* Assumed to be called with the HA lock */
4084/****************************************************************************/
4085static void
4086ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
4087{
4088 ips_scb_t *scb;
4089 ips_stat_t *sp;
4090 uint8_t basic_status;
4091 uint8_t ext_status;
4092 int errcode;
4093
4094 METHOD_TRACE("ips_chkstatus", 1);
4095
4096 scb = &ha->scbs[pstatus->fields.command_id];
4097 scb->basic_status = basic_status =
4098 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
4099 scb->extended_status = ext_status = pstatus->fields.extended_status;
4100
4101 sp = &ha->sp;
4102 sp->residue_len = 0;
4103 sp->scb_addr = (void *) scb;
4104
4105 /* Remove the item from the active queue */
4106 ips_removeq_scb(&ha->scb_activelist, scb);
4107
4108 if (!scb->scsi_cmd)
4109 /* internal commands are handled in do_ipsintr */
4110 return;
4111
4112 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
4113 ips_name,
4114 ha->host_num,
4115 scb->cdb[0],
4116 scb->cmd.basic_io.command_id,
4117 scb->bus, scb->target_id, scb->lun);
4118
4119 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
4120 /* passthru - just returns the raw result */
4121 return;
4122
4123 errcode = DID_OK;
4124
4125 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
4126 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
4127
4128 if (scb->bus == 0) {
4129 if ((basic_status & IPS_GSC_STATUS_MASK) ==
4130 IPS_CMD_RECOVERED_ERROR) {
4131 DEBUG_VAR(1,
4132 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4133 ips_name, ha->host_num,
4134 scb->cmd.basic_io.op_code,
4135 basic_status, ext_status);
4136 }
4137
4138 switch (scb->scsi_cmd->cmnd[0]) {
4139 case ALLOW_MEDIUM_REMOVAL:
4140 case REZERO_UNIT:
4141 case ERASE:
4142 case WRITE_FILEMARKS:
4143 case SPACE:
4144 errcode = DID_ERROR;
4145 break;
4146
4147 case START_STOP:
4148 break;
4149
4150 case TEST_UNIT_READY:
4151 if (!ips_online(ha, scb)) {
4152 errcode = DID_TIME_OUT;
4153 }
4154 break;
4155
4156 case INQUIRY:
4157 if (ips_online(ha, scb)) {
4158 ips_inquiry(ha, scb);
4159 } else {
4160 errcode = DID_TIME_OUT;
4161 }
4162 break;
4163
4164 case REQUEST_SENSE:
4165 ips_reqsen(ha, scb);
4166 break;
4167
4168 case READ_6:
4169 case WRITE_6:
4170 case READ_10:
4171 case WRITE_10:
4172 case RESERVE:
4173 case RELEASE:
4174 break;
4175
4176 case MODE_SENSE:
4177 if (!ips_online(ha, scb)
4178 || !ips_msense(ha, scb)) {
4179 errcode = DID_ERROR;
4180 }
4181 break;
4182
4183 case READ_CAPACITY:
4184 if (ips_online(ha, scb))
4185 ips_rdcap(ha, scb);
4186 else {
4187 errcode = DID_TIME_OUT;
4188 }
4189 break;
4190
4191 case SEND_DIAGNOSTIC:
4192 case REASSIGN_BLOCKS:
4193 break;
4194
4195 case FORMAT_UNIT:
4196 errcode = DID_ERROR;
4197 break;
4198
4199 case SEEK_10:
4200 case VERIFY:
4201 case READ_DEFECT_DATA:
4202 case READ_BUFFER:
4203 case WRITE_BUFFER:
4204 break;
4205
4206 default:
4207 errcode = DID_ERROR;
4208 } /* end switch */
4209
4210 scb->scsi_cmd->result = errcode << 16;
4211 } else { /* bus == 0 */
4212 /* restrict access to physical drives */
4213 if ((scb->scsi_cmd->cmnd[0] == INQUIRY) &&
4214 ((((char *) scb->scsi_cmd->buffer)[0] & 0x1f) ==
4215 TYPE_DISK)) {
4216
4217 scb->scsi_cmd->result = DID_TIME_OUT << 16;
4218 }
4219 } /* else */
4220 } else { /* recovered error / success */
4221 if (scb->bus == 0) {
4222 DEBUG_VAR(1,
4223 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
4224 ips_name, ha->host_num,
4225 scb->cmd.basic_io.op_code, basic_status,
4226 ext_status);
4227 }
4228
4229 ips_map_status(ha, scb, sp);
4230 } /* else */
4231}
4232
4233/****************************************************************************/
4234/* */
4235/* Routine Name: ips_online */
4236/* */
4237/* Routine Description: */
4238/* */
4239/* Determine if a logical drive is online */
4240/* */
4241/****************************************************************************/
4242static int
4243ips_online(ips_ha_t * ha, ips_scb_t * scb)
4244{
4245 METHOD_TRACE("ips_online", 1);
4246
4247 if (scb->target_id >= IPS_MAX_LD)
4248 return (0);
4249
4250 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4251 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4252 return (0);
4253 }
4254
4255 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4256 IPS_LD_OFFLINE
4257 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4258 IPS_LD_FREE
4259 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4260 IPS_LD_CRS
4261 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4262 IPS_LD_SYS)
4263 return (1);
4264 else
4265 return (0);
4266}
4267
4268/****************************************************************************/
4269/* */
4270/* Routine Name: ips_inquiry */
4271/* */
4272/* Routine Description: */
4273/* */
4274/* Simulate an inquiry command to a logical drive */
4275/* */
4276/****************************************************************************/
4277static int
4278ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4279{
4280 IPS_SCSI_INQ_DATA inquiry;
4281
4282 METHOD_TRACE("ips_inquiry", 1);
4283
4284 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4285
4286 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4287 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4288 inquiry.Version = IPS_SCSI_INQ_REV2;
4289 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4290 inquiry.AdditionalLength = 31;
4291 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4292 inquiry.Flags[1] =
4293 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4294 strncpy(inquiry.VendorId, "IBM ", 8);
4295 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4296 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4297
4298 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4299
4300 return (1);
4301}
4302
4303/****************************************************************************/
4304/* */
4305/* Routine Name: ips_rdcap */
4306/* */
4307/* Routine Description: */
4308/* */
4309/* Simulate a read capacity command to a logical drive */
4310/* */
4311/****************************************************************************/
4312static int
4313ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4314{
4315 IPS_SCSI_CAPACITY cap;
4316
4317 METHOD_TRACE("ips_rdcap", 1);
4318
4319 if (scb->scsi_cmd->bufflen < 8)
4320 return (0);
4321
4322 cap.lba =
4323 cpu_to_be32(le32_to_cpu
4324 (ha->logical_drive_info->
4325 drive_info[scb->target_id].sector_count) - 1);
4326 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4327
4328 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4329
4330 return (1);
4331}
4332
4333/****************************************************************************/
4334/* */
4335/* Routine Name: ips_msense */
4336/* */
4337/* Routine Description: */
4338/* */
4339/* Simulate a mode sense command to a logical drive */
4340/* */
4341/****************************************************************************/
4342static int
4343ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4344{
4345 uint16_t heads;
4346 uint16_t sectors;
4347 uint32_t cylinders;
4348 IPS_SCSI_MODE_PAGE_DATA mdata;
4349
4350 METHOD_TRACE("ips_msense", 1);
4351
4352 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4353 (ha->enq->ucMiscFlag & 0x8) == 0) {
4354 heads = IPS_NORM_HEADS;
4355 sectors = IPS_NORM_SECTORS;
4356 } else {
4357 heads = IPS_COMP_HEADS;
4358 sectors = IPS_COMP_SECTORS;
4359 }
4360
4361 cylinders =
4362 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4363 1) / (heads * sectors);
4364
4365 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4366
4367 mdata.hdr.BlockDescLength = 8;
4368
4369 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4370 case 0x03: /* page 3 */
4371 mdata.pdata.pg3.PageCode = 3;
4372 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4373 mdata.hdr.DataLength =
4374 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4375 mdata.pdata.pg3.TracksPerZone = 0;
4376 mdata.pdata.pg3.AltSectorsPerZone = 0;
4377 mdata.pdata.pg3.AltTracksPerZone = 0;
4378 mdata.pdata.pg3.AltTracksPerVolume = 0;
4379 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4380 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4381 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4382 mdata.pdata.pg3.TrackSkew = 0;
4383 mdata.pdata.pg3.CylinderSkew = 0;
4384 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4385 break;
4386
4387 case 0x4:
4388 mdata.pdata.pg4.PageCode = 4;
4389 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4390 mdata.hdr.DataLength =
4391 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4392 mdata.pdata.pg4.CylindersHigh =
4393 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4394 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4395 mdata.pdata.pg4.Heads = heads;
4396 mdata.pdata.pg4.WritePrecompHigh = 0;
4397 mdata.pdata.pg4.WritePrecompLow = 0;
4398 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4399 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4400 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4401 mdata.pdata.pg4.LandingZoneHigh = 0;
4402 mdata.pdata.pg4.LandingZoneLow = 0;
4403 mdata.pdata.pg4.flags = 0;
4404 mdata.pdata.pg4.RotationalOffset = 0;
4405 mdata.pdata.pg4.MediumRotationRate = 0;
4406 break;
4407 case 0x8:
4408 mdata.pdata.pg8.PageCode = 8;
4409 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4410 mdata.hdr.DataLength =
4411 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4412 /* everything else is left set to 0 */
4413 break;
4414
4415 default:
4416 return (0);
4417 } /* end switch */
4418
4419 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4420
4421 return (1);
4422}
4423
4424/****************************************************************************/
4425/* */
4426/* Routine Name: ips_reqsen */
4427/* */
4428/* Routine Description: */
4429/* */
4430/* Simulate a request sense command to a logical drive */
4431/* */
4432/****************************************************************************/
4433static int
4434ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4435{
4436 IPS_SCSI_REQSEN reqsen;
4437
4438 METHOD_TRACE("ips_reqsen", 1);
4439
4440 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4441
4442 reqsen.ResponseCode =
4443 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4444 reqsen.AdditionalLength = 10;
4445 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4446 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4447
4448 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4449
4450 return (1);
4451}
4452
4453/****************************************************************************/
4454/* */
4455/* Routine Name: ips_free */
4456/* */
4457/* Routine Description: */
4458/* */
4459/* Free any allocated space for this controller */
4460/* */
4461/****************************************************************************/
4462static void
4463ips_free(ips_ha_t * ha)
4464{
4465
4466 METHOD_TRACE("ips_free", 1);
4467
4468 if (ha) {
4469 if (ha->enq) {
4470 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4471 ha->enq, ha->enq_busaddr);
4472 ha->enq = NULL;
4473 }
4474
4475 if (ha->conf) {
4476 kfree(ha->conf);
4477 ha->conf = NULL;
4478 }
4479
4480 if (ha->adapt) {
4481 pci_free_consistent(ha->pcidev,
4482 sizeof (IPS_ADAPTER) +
4483 sizeof (IPS_IO_CMD), ha->adapt,
4484 ha->adapt->hw_status_start);
4485 ha->adapt = NULL;
4486 }
4487
4488 if (ha->logical_drive_info) {
4489 pci_free_consistent(ha->pcidev,
4490 sizeof (IPS_LD_INFO),
4491 ha->logical_drive_info,
4492 ha->logical_drive_info_dma_addr);
4493 ha->logical_drive_info = NULL;
4494 }
4495
4496 if (ha->nvram) {
4497 kfree(ha->nvram);
4498 ha->nvram = NULL;
4499 }
4500
4501 if (ha->subsys) {
4502 kfree(ha->subsys);
4503 ha->subsys = NULL;
4504 }
4505
4506 if (ha->ioctl_data) {
4507 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4508 ha->ioctl_data, ha->ioctl_busaddr);
4509 ha->ioctl_data = NULL;
4510 ha->ioctl_datasize = 0;
4511 ha->ioctl_len = 0;
4512 }
4513 ips_deallocatescbs(ha, ha->max_cmds);
4514
4515 /* free memory mapped (if applicable) */
4516 if (ha->mem_ptr) {
4517 iounmap(ha->ioremap_ptr);
4518 ha->ioremap_ptr = NULL;
4519 ha->mem_ptr = NULL;
4520 }
4521
4522 if (ha->mem_addr)
4523 release_mem_region(ha->mem_addr, ha->mem_len);
4524 ha->mem_addr = 0;
4525
4526 }
4527}
4528
4529/****************************************************************************/
4530/* */
4531/* Routine Name: ips_deallocatescbs */
4532/* */
4533/* Routine Description: */
4534/* */
4535/* Free the command blocks */
4536/* */
4537/****************************************************************************/
4538static int
4539ips_deallocatescbs(ips_ha_t * ha, int cmds)
4540{
4541 if (ha->scbs) {
4542 pci_free_consistent(ha->pcidev,
4543 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4544 ha->scbs->sg_list.list,
4545 ha->scbs->sg_busaddr);
4546 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4547 ha->scbs, ha->scbs->scb_busaddr);
4548 ha->scbs = NULL;
4549 } /* end if */
4550 return 1;
4551}
4552
4553/****************************************************************************/
4554/* */
4555/* Routine Name: ips_allocatescbs */
4556/* */
4557/* Routine Description: */
4558/* */
4559/* Allocate the command blocks */
4560/* */
4561/****************************************************************************/
4562static int
4563ips_allocatescbs(ips_ha_t * ha)
4564{
4565 ips_scb_t *scb_p;
4566 IPS_SG_LIST ips_sg;
4567 int i;
4568 dma_addr_t command_dma, sg_dma;
4569
4570 METHOD_TRACE("ips_allocatescbs", 1);
4571
4572 /* Allocate memory for the SCBs */
4573 ha->scbs =
4574 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4575 &command_dma);
4576 if (ha->scbs == NULL)
4577 return 0;
4578 ips_sg.list =
4579 pci_alloc_consistent(ha->pcidev,
4580 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4581 ha->max_cmds, &sg_dma);
4582 if (ips_sg.list == NULL) {
4583 pci_free_consistent(ha->pcidev,
4584 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4585 command_dma);
4586 return 0;
4587 }
4588
4589 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4590
4591 for (i = 0; i < ha->max_cmds; i++) {
4592 scb_p = &ha->scbs[i];
4593 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4594 /* set up S/G list */
4595 if (IPS_USE_ENH_SGLIST(ha)) {
4596 scb_p->sg_list.enh_list =
4597 ips_sg.enh_list + i * IPS_MAX_SG;
4598 scb_p->sg_busaddr =
4599 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4600 } else {
4601 scb_p->sg_list.std_list =
4602 ips_sg.std_list + i * IPS_MAX_SG;
4603 scb_p->sg_busaddr =
4604 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4605 }
4606
4607 /* add to the free list */
4608 if (i < ha->max_cmds - 1) {
4609 scb_p->q_next = ha->scb_freelist;
4610 ha->scb_freelist = scb_p;
4611 }
4612 }
4613
4614 /* success */
4615 return (1);
4616}
4617
4618/****************************************************************************/
4619/* */
4620/* Routine Name: ips_init_scb */
4621/* */
4622/* Routine Description: */
4623/* */
4624/* Initialize a CCB to default values */
4625/* */
4626/****************************************************************************/
4627static void
4628ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4629{
4630 IPS_SG_LIST sg_list;
4631 uint32_t cmd_busaddr, sg_busaddr;
4632 METHOD_TRACE("ips_init_scb", 1);
4633
4634 if (scb == NULL)
4635 return;
4636
4637 sg_list.list = scb->sg_list.list;
4638 cmd_busaddr = scb->scb_busaddr;
4639 sg_busaddr = scb->sg_busaddr;
4640 /* zero fill */
4641 memset(scb, 0, sizeof (ips_scb_t));
4642 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4643
4644 /* Initialize dummy command bucket */
4645 ha->dummy->op_code = 0xFF;
4646 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4647 + sizeof (IPS_ADAPTER));
4648 ha->dummy->command_id = IPS_MAX_CMDS;
4649
4650 /* set bus address of scb */
4651 scb->scb_busaddr = cmd_busaddr;
4652 scb->sg_busaddr = sg_busaddr;
4653 scb->sg_list.list = sg_list.list;
4654
4655 /* Neptune Fix */
4656 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4657 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4658 + sizeof (IPS_ADAPTER));
4659}
4660
4661/****************************************************************************/
4662/* */
4663/* Routine Name: ips_get_scb */
4664/* */
4665/* Routine Description: */
4666/* */
4667/* Initialize a CCB to default values */
4668/* */
4669/* ASSUMED to be callled from within a lock */
4670/* */
4671/****************************************************************************/
4672static ips_scb_t *
4673ips_getscb(ips_ha_t * ha)
4674{
4675 ips_scb_t *scb;
4676
4677 METHOD_TRACE("ips_getscb", 1);
4678
4679 if ((scb = ha->scb_freelist) == NULL) {
4680
4681 return (NULL);
4682 }
4683
4684 ha->scb_freelist = scb->q_next;
4685 scb->flags = 0;
4686 scb->q_next = NULL;
4687
4688 ips_init_scb(ha, scb);
4689
4690 return (scb);
4691}
4692
4693/****************************************************************************/
4694/* */
4695/* Routine Name: ips_free_scb */
4696/* */
4697/* Routine Description: */
4698/* */
4699/* Return an unused CCB back to the free list */
4700/* */
4701/* ASSUMED to be called from within a lock */
4702/* */
4703/****************************************************************************/
4704static void
4705ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4706{
4707
4708 METHOD_TRACE("ips_freescb", 1);
4709 if (scb->flags & IPS_SCB_MAP_SG)
4710 pci_unmap_sg(ha->pcidev, scb->scsi_cmd->request_buffer,
4711 scb->scsi_cmd->use_sg, IPS_DMA_DIR(scb));
4712 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4713 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4714 IPS_DMA_DIR(scb));
4715
4716 /* check to make sure this is not our "special" scb */
4717 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4718 scb->q_next = ha->scb_freelist;
4719 ha->scb_freelist = scb;
4720 }
4721}
4722
4723/****************************************************************************/
4724/* */
4725/* Routine Name: ips_isinit_copperhead */
4726/* */
4727/* Routine Description: */
4728/* */
4729/* Is controller initialized ? */
4730/* */
4731/****************************************************************************/
4732static int
4733ips_isinit_copperhead(ips_ha_t * ha)
4734{
4735 uint8_t scpr;
4736 uint8_t isr;
4737
4738 METHOD_TRACE("ips_isinit_copperhead", 1);
4739
4740 isr = inb(ha->io_addr + IPS_REG_HISR);
4741 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4742
4743 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4744 return (0);
4745 else
4746 return (1);
4747}
4748
4749/****************************************************************************/
4750/* */
4751/* Routine Name: ips_isinit_copperhead_memio */
4752/* */
4753/* Routine Description: */
4754/* */
4755/* Is controller initialized ? */
4756/* */
4757/****************************************************************************/
4758static int
4759ips_isinit_copperhead_memio(ips_ha_t * ha)
4760{
4761 uint8_t isr = 0;
4762 uint8_t scpr;
4763
4764 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4765
4766 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4767 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4768
4769 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4770 return (0);
4771 else
4772 return (1);
4773}
4774
4775/****************************************************************************/
4776/* */
4777/* Routine Name: ips_isinit_morpheus */
4778/* */
4779/* Routine Description: */
4780/* */
4781/* Is controller initialized ? */
4782/* */
4783/****************************************************************************/
4784static int
4785ips_isinit_morpheus(ips_ha_t * ha)
4786{
4787 uint32_t post;
4788 uint32_t bits;
4789
4790 METHOD_TRACE("ips_is_init_morpheus", 1);
4791
4792 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4793 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4794
4795 if (post == 0)
4796 return (0);
4797 else if (bits & 0x3)
4798 return (0);
4799 else
4800 return (1);
4801}
4802
4803/****************************************************************************/
4804/* */
4805/* Routine Name: ips_enable_int_copperhead */
4806/* */
4807/* Routine Description: */
4808/* Turn on interrupts */
4809/* */
4810/****************************************************************************/
4811static void
4812ips_enable_int_copperhead(ips_ha_t * ha)
4813{
4814 METHOD_TRACE("ips_enable_int_copperhead", 1);
4815
4816 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4817 inb(ha->io_addr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4818}
4819
4820/****************************************************************************/
4821/* */
4822/* Routine Name: ips_enable_int_copperhead_memio */
4823/* */
4824/* Routine Description: */
4825/* Turn on interrupts */
4826/* */
4827/****************************************************************************/
4828static void
4829ips_enable_int_copperhead_memio(ips_ha_t * ha)
4830{
4831 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4832
4833 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4834 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4835}
4836
4837/****************************************************************************/
4838/* */
4839/* Routine Name: ips_enable_int_morpheus */
4840/* */
4841/* Routine Description: */
4842/* Turn on interrupts */
4843/* */
4844/****************************************************************************/
4845static void
4846ips_enable_int_morpheus(ips_ha_t * ha)
4847{
4848 uint32_t Oimr;
4849
4850 METHOD_TRACE("ips_enable_int_morpheus", 1);
4851
4852 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4853 Oimr &= ~0x08;
4854 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4855 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4856}
4857
4858/****************************************************************************/
4859/* */
4860/* Routine Name: ips_init_copperhead */
4861/* */
4862/* Routine Description: */
4863/* */
4864/* Initialize a copperhead controller */
4865/* */
4866/****************************************************************************/
4867static int
4868ips_init_copperhead(ips_ha_t * ha)
4869{
4870 uint8_t Isr;
4871 uint8_t Cbsp;
4872 uint8_t PostByte[IPS_MAX_POST_BYTES];
4873 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4874 int i, j;
4875
4876 METHOD_TRACE("ips_init_copperhead", 1);
4877
4878 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4879 for (j = 0; j < 45; j++) {
4880 Isr = inb(ha->io_addr + IPS_REG_HISR);
4881 if (Isr & IPS_BIT_GHI)
4882 break;
4883
4884 /* Delay for 1 Second */
4885 MDELAY(IPS_ONE_SEC);
4886 }
4887
4888 if (j >= 45)
4889 /* error occurred */
4890 return (0);
4891
4892 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4893 outb(Isr, ha->io_addr + IPS_REG_HISR);
4894 }
4895
4896 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4897 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4898 "reset controller fails (post status %x %x).\n",
4899 PostByte[0], PostByte[1]);
4900
4901 return (0);
4902 }
4903
4904 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4905 for (j = 0; j < 240; j++) {
4906 Isr = inb(ha->io_addr + IPS_REG_HISR);
4907 if (Isr & IPS_BIT_GHI)
4908 break;
4909
4910 /* Delay for 1 Second */
4911 MDELAY(IPS_ONE_SEC);
4912 }
4913
4914 if (j >= 240)
4915 /* error occurred */
4916 return (0);
4917
4918 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4919 outb(Isr, ha->io_addr + IPS_REG_HISR);
4920 }
4921
4922 for (i = 0; i < 240; i++) {
4923 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4924
4925 if ((Cbsp & IPS_BIT_OP) == 0)
4926 break;
4927
4928 /* Delay for 1 Second */
4929 MDELAY(IPS_ONE_SEC);
4930 }
4931
4932 if (i >= 240)
4933 /* reset failed */
4934 return (0);
4935
4936 /* setup CCCR */
4937 outl(cpu_to_le32(0x1010), ha->io_addr + IPS_REG_CCCR);
4938
4939 /* Enable busmastering */
4940 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4941
4942 if (ha->revision_id == IPS_REVID_TROMBONE64)
4943 /* fix for anaconda64 */
4944 outl(0, ha->io_addr + IPS_REG_NDAE);
4945
4946 /* Enable interrupts */
4947 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4948
4949 return (1);
4950}
4951
4952/****************************************************************************/
4953/* */
4954/* Routine Name: ips_init_copperhead_memio */
4955/* */
4956/* Routine Description: */
4957/* */
4958/* Initialize a copperhead controller with memory mapped I/O */
4959/* */
4960/****************************************************************************/
4961static int
4962ips_init_copperhead_memio(ips_ha_t * ha)
4963{
4964 uint8_t Isr = 0;
4965 uint8_t Cbsp;
4966 uint8_t PostByte[IPS_MAX_POST_BYTES];
4967 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4968 int i, j;
4969
4970 METHOD_TRACE("ips_init_copperhead_memio", 1);
4971
4972 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4973 for (j = 0; j < 45; j++) {
4974 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4975 if (Isr & IPS_BIT_GHI)
4976 break;
4977
4978 /* Delay for 1 Second */
4979 MDELAY(IPS_ONE_SEC);
4980 }
4981
4982 if (j >= 45)
4983 /* error occurred */
4984 return (0);
4985
4986 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4987 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4988 }
4989
4990 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4991 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4992 "reset controller fails (post status %x %x).\n",
4993 PostByte[0], PostByte[1]);
4994
4995 return (0);
4996 }
4997
4998 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4999 for (j = 0; j < 240; j++) {
5000 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5001 if (Isr & IPS_BIT_GHI)
5002 break;
5003
5004 /* Delay for 1 Second */
5005 MDELAY(IPS_ONE_SEC);
5006 }
5007
5008 if (j >= 240)
5009 /* error occurred */
5010 return (0);
5011
5012 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
5013 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5014 }
5015
5016 for (i = 0; i < 240; i++) {
5017 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
5018
5019 if ((Cbsp & IPS_BIT_OP) == 0)
5020 break;
5021
5022 /* Delay for 1 Second */
5023 MDELAY(IPS_ONE_SEC);
5024 }
5025
5026 if (i >= 240)
5027 /* error occurred */
5028 return (0);
5029
5030 /* setup CCCR */
5031 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
5032
5033 /* Enable busmastering */
5034 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
5035
5036 if (ha->revision_id == IPS_REVID_TROMBONE64)
5037 /* fix for anaconda64 */
5038 writel(0, ha->mem_ptr + IPS_REG_NDAE);
5039
5040 /* Enable interrupts */
5041 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
5042
5043 /* if we get here then everything went OK */
5044 return (1);
5045}
5046
5047/****************************************************************************/
5048/* */
5049/* Routine Name: ips_init_morpheus */
5050/* */
5051/* Routine Description: */
5052/* */
5053/* Initialize a morpheus controller */
5054/* */
5055/****************************************************************************/
5056static int
5057ips_init_morpheus(ips_ha_t * ha)
5058{
5059 uint32_t Post;
5060 uint32_t Config;
5061 uint32_t Isr;
5062 uint32_t Oimr;
5063 int i;
5064
5065 METHOD_TRACE("ips_init_morpheus", 1);
5066
5067 /* Wait up to 45 secs for Post */
5068 for (i = 0; i < 45; i++) {
5069 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5070
5071 if (Isr & IPS_BIT_I960_MSG0I)
5072 break;
5073
5074 /* Delay for 1 Second */
5075 MDELAY(IPS_ONE_SEC);
5076 }
5077
5078 if (i >= 45) {
5079 /* error occurred */
5080 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5081 "timeout waiting for post.\n");
5082
5083 return (0);
5084 }
5085
5086 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5087
5088 if (Post == 0x4F00) { /* If Flashing the Battery PIC */
5089 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5090 "Flashing Battery PIC, Please wait ...\n");
5091
5092 /* Clear the interrupt bit */
5093 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5094 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5095
5096 for (i = 0; i < 120; i++) { /* Wait Up to 2 Min. for Completion */
5097 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
5098 if (Post != 0x4F00)
5099 break;
5100 /* Delay for 1 Second */
5101 MDELAY(IPS_ONE_SEC);
5102 }
5103
5104 if (i >= 120) {
5105 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5106 "timeout waiting for Battery PIC Flash\n");
5107 return (0);
5108 }
5109
5110 }
5111
5112 /* Clear the interrupt bit */
5113 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
5114 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5115
5116 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
5117 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5118 "reset controller fails (post status %x).\n", Post);
5119
5120 return (0);
5121 }
5122
5123 /* Wait up to 240 secs for config bytes */
5124 for (i = 0; i < 240; i++) {
5125 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5126
5127 if (Isr & IPS_BIT_I960_MSG1I)
5128 break;
5129
5130 /* Delay for 1 Second */
5131 MDELAY(IPS_ONE_SEC);
5132 }
5133
5134 if (i >= 240) {
5135 /* error occurred */
5136 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5137 "timeout waiting for config.\n");
5138
5139 return (0);
5140 }
5141
5142 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
5143
5144 /* Clear interrupt bit */
5145 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
5146 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
5147
5148 /* Turn on the interrupts */
5149 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
5150 Oimr &= ~0x8;
5151 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5152
5153 /* if we get here then everything went OK */
5154
5155 /* Since we did a RESET, an EraseStripeLock may be needed */
5156 if (Post == 0xEF10) {
5157 if ((Config == 0x000F) || (Config == 0x0009))
5158 ha->requires_esl = 1;
5159 }
5160
5161 return (1);
5162}
5163
5164/****************************************************************************/
5165/* */
5166/* Routine Name: ips_reset_copperhead */
5167/* */
5168/* Routine Description: */
5169/* */
5170/* Reset the controller */
5171/* */
5172/****************************************************************************/
5173static int
5174ips_reset_copperhead(ips_ha_t * ha)
5175{
5176 int reset_counter;
5177
5178 METHOD_TRACE("ips_reset_copperhead", 1);
5179
5180 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5181 ips_name, ha->host_num, ha->io_addr, ha->irq);
5182
5183 reset_counter = 0;
5184
5185 while (reset_counter < 2) {
5186 reset_counter++;
5187
5188 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5189
5190 /* Delay for 1 Second */
5191 MDELAY(IPS_ONE_SEC);
5192
5193 outb(0, ha->io_addr + IPS_REG_SCPR);
5194
5195 /* Delay for 1 Second */
5196 MDELAY(IPS_ONE_SEC);
5197
5198 if ((*ha->func.init) (ha))
5199 break;
5200 else if (reset_counter >= 2) {
5201
5202 return (0);
5203 }
5204 }
5205
5206 return (1);
5207}
5208
5209/****************************************************************************/
5210/* */
5211/* Routine Name: ips_reset_copperhead_memio */
5212/* */
5213/* Routine Description: */
5214/* */
5215/* Reset the controller */
5216/* */
5217/****************************************************************************/
5218static int
5219ips_reset_copperhead_memio(ips_ha_t * ha)
5220{
5221 int reset_counter;
5222
5223 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5224
5225 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5226 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5227
5228 reset_counter = 0;
5229
5230 while (reset_counter < 2) {
5231 reset_counter++;
5232
5233 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5234
5235 /* Delay for 1 Second */
5236 MDELAY(IPS_ONE_SEC);
5237
5238 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5239
5240 /* Delay for 1 Second */
5241 MDELAY(IPS_ONE_SEC);
5242
5243 if ((*ha->func.init) (ha))
5244 break;
5245 else if (reset_counter >= 2) {
5246
5247 return (0);
5248 }
5249 }
5250
5251 return (1);
5252}
5253
5254/****************************************************************************/
5255/* */
5256/* Routine Name: ips_reset_morpheus */
5257/* */
5258/* Routine Description: */
5259/* */
5260/* Reset the controller */
5261/* */
5262/****************************************************************************/
5263static int
5264ips_reset_morpheus(ips_ha_t * ha)
5265{
5266 int reset_counter;
5267 uint8_t junk;
5268
5269 METHOD_TRACE("ips_reset_morpheus", 1);
5270
5271 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5272 ips_name, ha->host_num, ha->mem_addr, ha->irq);
5273
5274 reset_counter = 0;
5275
5276 while (reset_counter < 2) {
5277 reset_counter++;
5278
5279 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5280
5281 /* Delay for 5 Seconds */
5282 MDELAY(5 * IPS_ONE_SEC);
5283
5284 /* Do a PCI config read to wait for adapter */
5285 pci_read_config_byte(ha->pcidev, 4, &junk);
5286
5287 if ((*ha->func.init) (ha))
5288 break;
5289 else if (reset_counter >= 2) {
5290
5291 return (0);
5292 }
5293 }
5294
5295 return (1);
5296}
5297
5298/****************************************************************************/
5299/* */
5300/* Routine Name: ips_statinit */
5301/* */
5302/* Routine Description: */
5303/* */
5304/* Initialize the status queues on the controller */
5305/* */
5306/****************************************************************************/
5307static void
5308ips_statinit(ips_ha_t * ha)
5309{
5310 uint32_t phys_status_start;
5311
5312 METHOD_TRACE("ips_statinit", 1);
5313
5314 ha->adapt->p_status_start = ha->adapt->status;
5315 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5316 ha->adapt->p_status_tail = ha->adapt->status;
5317
5318 phys_status_start = ha->adapt->hw_status_start;
5319 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQSR);
5320 outl(cpu_to_le32(phys_status_start + IPS_STATUS_Q_SIZE),
5321 ha->io_addr + IPS_REG_SQER);
5322 outl(cpu_to_le32(phys_status_start + IPS_STATUS_SIZE),
5323 ha->io_addr + IPS_REG_SQHR);
5324 outl(cpu_to_le32(phys_status_start), ha->io_addr + IPS_REG_SQTR);
5325
5326 ha->adapt->hw_status_tail = phys_status_start;
5327}
5328
5329/****************************************************************************/
5330/* */
5331/* Routine Name: ips_statinit_memio */
5332/* */
5333/* Routine Description: */
5334/* */
5335/* Initialize the status queues on the controller */
5336/* */
5337/****************************************************************************/
5338static void
5339ips_statinit_memio(ips_ha_t * ha)
5340{
5341 uint32_t phys_status_start;
5342
5343 METHOD_TRACE("ips_statinit_memio", 1);
5344
5345 ha->adapt->p_status_start = ha->adapt->status;
5346 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5347 ha->adapt->p_status_tail = ha->adapt->status;
5348
5349 phys_status_start = ha->adapt->hw_status_start;
5350 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5351 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5352 ha->mem_ptr + IPS_REG_SQER);
5353 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5354 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5355
5356 ha->adapt->hw_status_tail = phys_status_start;
5357}
5358
5359/****************************************************************************/
5360/* */
5361/* Routine Name: ips_statupd_copperhead */
5362/* */
5363/* Routine Description: */
5364/* */
5365/* Remove an element from the status queue */
5366/* */
5367/****************************************************************************/
5368static uint32_t
5369ips_statupd_copperhead(ips_ha_t * ha)
5370{
5371 METHOD_TRACE("ips_statupd_copperhead", 1);
5372
5373 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5374 ha->adapt->p_status_tail++;
5375 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5376 } else {
5377 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5378 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5379 }
5380
5381 outl(cpu_to_le32(ha->adapt->hw_status_tail),
5382 ha->io_addr + IPS_REG_SQTR);
5383
5384 return (ha->adapt->p_status_tail->value);
5385}
5386
5387/****************************************************************************/
5388/* */
5389/* Routine Name: ips_statupd_copperhead_memio */
5390/* */
5391/* Routine Description: */
5392/* */
5393/* Remove an element from the status queue */
5394/* */
5395/****************************************************************************/
5396static uint32_t
5397ips_statupd_copperhead_memio(ips_ha_t * ha)
5398{
5399 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5400
5401 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5402 ha->adapt->p_status_tail++;
5403 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5404 } else {
5405 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5406 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5407 }
5408
5409 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5410
5411 return (ha->adapt->p_status_tail->value);
5412}
5413
5414/****************************************************************************/
5415/* */
5416/* Routine Name: ips_statupd_morpheus */
5417/* */
5418/* Routine Description: */
5419/* */
5420/* Remove an element from the status queue */
5421/* */
5422/****************************************************************************/
5423static uint32_t
5424ips_statupd_morpheus(ips_ha_t * ha)
5425{
5426 uint32_t val;
5427
5428 METHOD_TRACE("ips_statupd_morpheus", 1);
5429
5430 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5431
5432 return (val);
5433}
5434
5435/****************************************************************************/
5436/* */
5437/* Routine Name: ips_issue_copperhead */
5438/* */
5439/* Routine Description: */
5440/* */
5441/* Send a command down to the controller */
5442/* */
5443/****************************************************************************/
5444static int
5445ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5446{
5447 uint32_t TimeOut;
5448 uint32_t val;
5449
5450 METHOD_TRACE("ips_issue_copperhead", 1);
5451
5452 if (scb->scsi_cmd) {
5453 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5454 ips_name,
5455 ha->host_num,
5456 scb->cdb[0],
5457 scb->cmd.basic_io.command_id,
5458 scb->bus, scb->target_id, scb->lun);
5459 } else {
5460 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5461 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5462 }
5463
5464 TimeOut = 0;
5465
5466 while ((val =
5467 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5468 udelay(1000);
5469
5470 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5471 if (!(val & IPS_BIT_START_STOP))
5472 break;
5473
5474 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5475 "ips_issue val [0x%x].\n", val);
5476 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5477 "ips_issue semaphore chk timeout.\n");
5478
5479 return (IPS_FAILURE);
5480 } /* end if */
5481 } /* end while */
5482
5483 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_CCSAR);
5484 outw(cpu_to_le32(IPS_BIT_START_CMD), ha->io_addr + IPS_REG_CCCR);
5485
5486 return (IPS_SUCCESS);
5487}
5488
5489/****************************************************************************/
5490/* */
5491/* Routine Name: ips_issue_copperhead_memio */
5492/* */
5493/* Routine Description: */
5494/* */
5495/* Send a command down to the controller */
5496/* */
5497/****************************************************************************/
5498static int
5499ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5500{
5501 uint32_t TimeOut;
5502 uint32_t val;
5503
5504 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5505
5506 if (scb->scsi_cmd) {
5507 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5508 ips_name,
5509 ha->host_num,
5510 scb->cdb[0],
5511 scb->cmd.basic_io.command_id,
5512 scb->bus, scb->target_id, scb->lun);
5513 } else {
5514 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5515 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5516 }
5517
5518 TimeOut = 0;
5519
5520 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5521 udelay(1000);
5522
5523 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5524 if (!(val & IPS_BIT_START_STOP))
5525 break;
5526
5527 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5528 "ips_issue val [0x%x].\n", val);
5529 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5530 "ips_issue semaphore chk timeout.\n");
5531
5532 return (IPS_FAILURE);
5533 } /* end if */
5534 } /* end while */
5535
5536 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5537 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5538
5539 return (IPS_SUCCESS);
5540}
5541
5542/****************************************************************************/
5543/* */
5544/* Routine Name: ips_issue_i2o */
5545/* */
5546/* Routine Description: */
5547/* */
5548/* Send a command down to the controller */
5549/* */
5550/****************************************************************************/
5551static int
5552ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5553{
5554
5555 METHOD_TRACE("ips_issue_i2o", 1);
5556
5557 if (scb->scsi_cmd) {
5558 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5559 ips_name,
5560 ha->host_num,
5561 scb->cdb[0],
5562 scb->cmd.basic_io.command_id,
5563 scb->bus, scb->target_id, scb->lun);
5564 } else {
5565 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5566 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5567 }
5568
5569 outl(cpu_to_le32(scb->scb_busaddr), ha->io_addr + IPS_REG_I2O_INMSGQ);
5570
5571 return (IPS_SUCCESS);
5572}
5573
5574/****************************************************************************/
5575/* */
5576/* Routine Name: ips_issue_i2o_memio */
5577/* */
5578/* Routine Description: */
5579/* */
5580/* Send a command down to the controller */
5581/* */
5582/****************************************************************************/
5583static int
5584ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5585{
5586
5587 METHOD_TRACE("ips_issue_i2o_memio", 1);
5588
5589 if (scb->scsi_cmd) {
5590 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5591 ips_name,
5592 ha->host_num,
5593 scb->cdb[0],
5594 scb->cmd.basic_io.command_id,
5595 scb->bus, scb->target_id, scb->lun);
5596 } else {
5597 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5598 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5599 }
5600
5601 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5602
5603 return (IPS_SUCCESS);
5604}
5605
5606/****************************************************************************/
5607/* */
5608/* Routine Name: ips_isintr_copperhead */
5609/* */
5610/* Routine Description: */
5611/* */
5612/* Test to see if an interrupt is for us */
5613/* */
5614/****************************************************************************/
5615static int
5616ips_isintr_copperhead(ips_ha_t * ha)
5617{
5618 uint8_t Isr;
5619
5620 METHOD_TRACE("ips_isintr_copperhead", 2);
5621
5622 Isr = inb(ha->io_addr + IPS_REG_HISR);
5623
5624 if (Isr == 0xFF)
5625 /* ?!?! Nothing really there */
5626 return (0);
5627
5628 if (Isr & IPS_BIT_SCE)
5629 return (1);
5630 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5631 /* status queue overflow or GHI */
5632 /* just clear the interrupt */
5633 outb(Isr, ha->io_addr + IPS_REG_HISR);
5634 }
5635
5636 return (0);
5637}
5638
5639/****************************************************************************/
5640/* */
5641/* Routine Name: ips_isintr_copperhead_memio */
5642/* */
5643/* Routine Description: */
5644/* */
5645/* Test to see if an interrupt is for us */
5646/* */
5647/****************************************************************************/
5648static int
5649ips_isintr_copperhead_memio(ips_ha_t * ha)
5650{
5651 uint8_t Isr;
5652
5653 METHOD_TRACE("ips_isintr_memio", 2);
5654
5655 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5656
5657 if (Isr == 0xFF)
5658 /* ?!?! Nothing really there */
5659 return (0);
5660
5661 if (Isr & IPS_BIT_SCE)
5662 return (1);
5663 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5664 /* status queue overflow or GHI */
5665 /* just clear the interrupt */
5666 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5667 }
5668
5669 return (0);
5670}
5671
5672/****************************************************************************/
5673/* */
5674/* Routine Name: ips_isintr_morpheus */
5675/* */
5676/* Routine Description: */
5677/* */
5678/* Test to see if an interrupt is for us */
5679/* */
5680/****************************************************************************/
5681static int
5682ips_isintr_morpheus(ips_ha_t * ha)
5683{
5684 uint32_t Isr;
5685
5686 METHOD_TRACE("ips_isintr_morpheus", 2);
5687
5688 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5689
5690 if (Isr & IPS_BIT_I2O_OPQI)
5691 return (1);
5692 else
5693 return (0);
5694}
5695
5696/****************************************************************************/
5697/* */
5698/* Routine Name: ips_wait */
5699/* */
5700/* Routine Description: */
5701/* */
5702/* Wait for a command to complete */
5703/* */
5704/****************************************************************************/
5705static int
5706ips_wait(ips_ha_t * ha, int time, int intr)
5707{
5708 int ret;
5709 int done;
5710
5711 METHOD_TRACE("ips_wait", 1);
5712
5713 ret = IPS_FAILURE;
5714 done = FALSE;
5715
5716 time *= IPS_ONE_SEC; /* convert seconds */
5717
5718 while ((time > 0) && (!done)) {
5719 if (intr == IPS_INTR_ON) {
5720 if (ha->waitflag == FALSE) {
5721 ret = IPS_SUCCESS;
5722 done = TRUE;
5723 break;
5724 }
5725 } else if (intr == IPS_INTR_IORL) {
5726 if (ha->waitflag == FALSE) {
5727 /*
5728 * controller generated an interrupt to
5729 * acknowledge completion of the command
5730 * and ips_intr() has serviced the interrupt.
5731 */
5732 ret = IPS_SUCCESS;
5733 done = TRUE;
5734 break;
5735 }
5736
5737 /*
5738 * NOTE: we already have the io_request_lock so
5739 * even if we get an interrupt it won't get serviced
5740 * until after we finish.
5741 */
5742
5743 (*ha->func.intr) (ha);
5744 }
5745
5746 /* This looks like a very evil loop, but it only does this during start-up */
5747 udelay(1000);
5748 time--;
5749 }
5750
5751 return (ret);
5752}
5753
5754/****************************************************************************/
5755/* */
5756/* Routine Name: ips_write_driver_status */
5757/* */
5758/* Routine Description: */
5759/* */
5760/* Write OS/Driver version to Page 5 of the nvram on the controller */
5761/* */
5762/****************************************************************************/
5763static int
5764ips_write_driver_status(ips_ha_t * ha, int intr)
5765{
5766 METHOD_TRACE("ips_write_driver_status", 1);
5767
5768 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5769 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5770 "unable to read NVRAM page 5.\n");
5771
5772 return (0);
5773 }
5774
5775 /* check to make sure the page has a valid */
5776 /* signature */
5777 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5778 DEBUG_VAR(1,
5779 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5780 ips_name, ha->host_num, ha->nvram->signature);
5781 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5782 }
5783
5784 DEBUG_VAR(2,
5785 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5786 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5787 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5788 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5789 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5790 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5791 ha->nvram->bios_low[3]);
5792
5793 ips_get_bios_version(ha, intr);
5794
5795 /* change values (as needed) */
5796 ha->nvram->operating_system = IPS_OS_LINUX;
5797 ha->nvram->adapter_type = ha->ad_type;
5798 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5799 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5800 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5801 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5802
5803 ips_version_check(ha, intr); /* Check BIOS/FW/Driver Versions */
5804
5805 /* now update the page */
5806 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5807 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5808 "unable to write NVRAM page 5.\n");
5809
5810 return (0);
5811 }
5812
5813 /* IF NVRAM Page 5 is OK, Use it for Slot Number Info Because Linux Doesn't Do Slots */
5814 ha->slot_num = ha->nvram->adapter_slot;
5815
5816 return (1);
5817}
5818
5819/****************************************************************************/
5820/* */
5821/* Routine Name: ips_read_adapter_status */
5822/* */
5823/* Routine Description: */
5824/* */
5825/* Do an Inquiry command to the adapter */
5826/* */
5827/****************************************************************************/
5828static int
5829ips_read_adapter_status(ips_ha_t * ha, int intr)
5830{
5831 ips_scb_t *scb;
5832 int ret;
5833
5834 METHOD_TRACE("ips_read_adapter_status", 1);
5835
5836 scb = &ha->scbs[ha->max_cmds - 1];
5837
5838 ips_init_scb(ha, scb);
5839
5840 scb->timeout = ips_cmd_timeout;
5841 scb->cdb[0] = IPS_CMD_ENQUIRY;
5842
5843 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5844 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5845 scb->cmd.basic_io.sg_count = 0;
5846 scb->cmd.basic_io.lba = 0;
5847 scb->cmd.basic_io.sector_count = 0;
5848 scb->cmd.basic_io.log_drv = 0;
5849 scb->data_len = sizeof (*ha->enq);
5850 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5851
5852 /* send command */
5853 if (((ret =
5854 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5855 || (ret == IPS_SUCCESS_IMM)
5856 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5857 return (0);
5858
5859 return (1);
5860}
5861
5862/****************************************************************************/
5863/* */
5864/* Routine Name: ips_read_subsystem_parameters */
5865/* */
5866/* Routine Description: */
5867/* */
5868/* Read subsystem parameters from the adapter */
5869/* */
5870/****************************************************************************/
5871static int
5872ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5873{
5874 ips_scb_t *scb;
5875 int ret;
5876
5877 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5878
5879 scb = &ha->scbs[ha->max_cmds - 1];
5880
5881 ips_init_scb(ha, scb);
5882
5883 scb->timeout = ips_cmd_timeout;
5884 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5885
5886 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5887 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5888 scb->cmd.basic_io.sg_count = 0;
5889 scb->cmd.basic_io.lba = 0;
5890 scb->cmd.basic_io.sector_count = 0;
5891 scb->cmd.basic_io.log_drv = 0;
5892 scb->data_len = sizeof (*ha->subsys);
5893 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5894
5895 /* send command */
5896 if (((ret =
5897 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5898 || (ret == IPS_SUCCESS_IMM)
5899 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5900 return (0);
5901
5902 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5903 return (1);
5904}
5905
5906/****************************************************************************/
5907/* */
5908/* Routine Name: ips_read_config */
5909/* */
5910/* Routine Description: */
5911/* */
5912/* Read the configuration on the adapter */
5913/* */
5914/****************************************************************************/
5915static int
5916ips_read_config(ips_ha_t * ha, int intr)
5917{
5918 ips_scb_t *scb;
5919 int i;
5920 int ret;
5921
5922 METHOD_TRACE("ips_read_config", 1);
5923
5924 /* set defaults for initiator IDs */
5925 for (i = 0; i < 4; i++)
5926 ha->conf->init_id[i] = 7;
5927
5928 scb = &ha->scbs[ha->max_cmds - 1];
5929
5930 ips_init_scb(ha, scb);
5931
5932 scb->timeout = ips_cmd_timeout;
5933 scb->cdb[0] = IPS_CMD_READ_CONF;
5934
5935 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5936 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5937 scb->data_len = sizeof (*ha->conf);
5938 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5939
5940 /* send command */
5941 if (((ret =
5942 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5943 || (ret == IPS_SUCCESS_IMM)
5944 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5945
5946 memset(ha->conf, 0, sizeof (IPS_CONF));
5947
5948 /* reset initiator IDs */
5949 for (i = 0; i < 4; i++)
5950 ha->conf->init_id[i] = 7;
5951
5952 /* Allow Completed with Errors, so JCRM can access the Adapter to fix the problems */
5953 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5954 IPS_CMD_CMPLT_WERROR)
5955 return (1);
5956
5957 return (0);
5958 }
5959
5960 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5961 return (1);
5962}
5963
5964/****************************************************************************/
5965/* */
5966/* Routine Name: ips_readwrite_page5 */
5967/* */
5968/* Routine Description: */
5969/* */
5970/* Read nvram page 5 from the adapter */
5971/* */
5972/****************************************************************************/
5973static int
5974ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5975{
5976 ips_scb_t *scb;
5977 int ret;
5978
5979 METHOD_TRACE("ips_readwrite_page5", 1);
5980
5981 scb = &ha->scbs[ha->max_cmds - 1];
5982
5983 ips_init_scb(ha, scb);
5984
5985 scb->timeout = ips_cmd_timeout;
5986 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5987
5988 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5989 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5990 scb->cmd.nvram.page = 5;
5991 scb->cmd.nvram.write = write;
5992 scb->cmd.nvram.reserved = 0;
5993 scb->cmd.nvram.reserved2 = 0;
5994 scb->data_len = sizeof (*ha->nvram);
5995 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5996 if (write)
5997 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5998
5999 /* issue the command */
6000 if (((ret =
6001 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6002 || (ret == IPS_SUCCESS_IMM)
6003 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
6004
6005 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
6006
6007 return (0);
6008 }
6009 if (!write)
6010 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
6011 return (1);
6012}
6013
6014/****************************************************************************/
6015/* */
6016/* Routine Name: ips_clear_adapter */
6017/* */
6018/* Routine Description: */
6019/* */
6020/* Clear the stripe lock tables */
6021/* */
6022/****************************************************************************/
6023static int
6024ips_clear_adapter(ips_ha_t * ha, int intr)
6025{
6026 ips_scb_t *scb;
6027 int ret;
6028
6029 METHOD_TRACE("ips_clear_adapter", 1);
6030
6031 scb = &ha->scbs[ha->max_cmds - 1];
6032
6033 ips_init_scb(ha, scb);
6034
6035 scb->timeout = ips_reset_timeout;
6036 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
6037
6038 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
6039 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
6040 scb->cmd.config_sync.channel = 0;
6041 scb->cmd.config_sync.source_target = IPS_POCL;
6042 scb->cmd.config_sync.reserved = 0;
6043 scb->cmd.config_sync.reserved2 = 0;
6044 scb->cmd.config_sync.reserved3 = 0;
6045
6046 /* issue command */
6047 if (((ret =
6048 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
6049 || (ret == IPS_SUCCESS_IMM)
6050 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6051 return (0);
6052
6053 /* send unlock stripe command */
6054 ips_init_scb(ha, scb);
6055
6056 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
6057 scb->timeout = ips_reset_timeout;
6058
6059 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
6060 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
6061 scb->cmd.unlock_stripe.log_drv = 0;
6062 scb->cmd.unlock_stripe.control = IPS_CSL;
6063 scb->cmd.unlock_stripe.reserved = 0;
6064 scb->cmd.unlock_stripe.reserved2 = 0;
6065 scb->cmd.unlock_stripe.reserved3 = 0;
6066
6067 /* issue command */
6068 if (((ret =
6069 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
6070 || (ret == IPS_SUCCESS_IMM)
6071 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
6072 return (0);
6073
6074 return (1);
6075}
6076
6077/****************************************************************************/
6078/* */
6079/* Routine Name: ips_ffdc_reset */
6080/* */
6081/* Routine Description: */
6082/* */
6083/* FFDC: write reset info */
6084/* */
6085/****************************************************************************/
6086static void
6087ips_ffdc_reset(ips_ha_t * ha, int intr)
6088{
6089 ips_scb_t *scb;
6090
6091 METHOD_TRACE("ips_ffdc_reset", 1);
6092
6093 scb = &ha->scbs[ha->max_cmds - 1];
6094
6095 ips_init_scb(ha, scb);
6096
6097 scb->timeout = ips_cmd_timeout;
6098 scb->cdb[0] = IPS_CMD_FFDC;
6099 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6100 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6101 scb->cmd.ffdc.reset_count = ha->reset_count;
6102 scb->cmd.ffdc.reset_type = 0x80;
6103
6104 /* convert time to what the card wants */
6105 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6106
6107 /* issue command */
6108 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6109}
6110
6111/****************************************************************************/
6112/* */
6113/* Routine Name: ips_ffdc_time */
6114/* */
6115/* Routine Description: */
6116/* */
6117/* FFDC: write time info */
6118/* */
6119/****************************************************************************/
6120static void
6121ips_ffdc_time(ips_ha_t * ha)
6122{
6123 ips_scb_t *scb;
6124
6125 METHOD_TRACE("ips_ffdc_time", 1);
6126
6127 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
6128
6129 scb = &ha->scbs[ha->max_cmds - 1];
6130
6131 ips_init_scb(ha, scb);
6132
6133 scb->timeout = ips_cmd_timeout;
6134 scb->cdb[0] = IPS_CMD_FFDC;
6135 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
6136 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
6137 scb->cmd.ffdc.reset_count = 0;
6138 scb->cmd.ffdc.reset_type = 0;
6139
6140 /* convert time to what the card wants */
6141 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
6142
6143 /* issue command */
6144 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
6145}
6146
6147/****************************************************************************/
6148/* */
6149/* Routine Name: ips_fix_ffdc_time */
6150/* */
6151/* Routine Description: */
6152/* Adjust time_t to what the card wants */
6153/* */
6154/****************************************************************************/
6155static void
6156ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
6157{
6158 long days;
6159 long rem;
6160 int i;
6161 int year;
6162 int yleap;
6163 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6164 int month_lengths[12][2] = { {31, 31},
6165 {28, 29},
6166 {31, 31},
6167 {30, 30},
6168 {31, 31},
6169 {30, 30},
6170 {31, 31},
6171 {31, 31},
6172 {30, 30},
6173 {31, 31},
6174 {30, 30},
6175 {31, 31}
6176 };
6177
6178 METHOD_TRACE("ips_fix_ffdc_time", 1);
6179
6180 days = current_time / IPS_SECS_DAY;
6181 rem = current_time % IPS_SECS_DAY;
6182
6183 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6184 rem = rem % IPS_SECS_HOUR;
6185 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6186 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6187
6188 year = IPS_EPOCH_YEAR;
6189 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6190 int newy;
6191
6192 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6193 if (days < 0)
6194 --newy;
6195 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6196 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6197 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6198 year = newy;
6199 }
6200
6201 scb->cmd.ffdc.yearH = year / 100;
6202 scb->cmd.ffdc.yearL = year % 100;
6203
6204 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6205 days -= month_lengths[i][yleap];
6206
6207 scb->cmd.ffdc.month = i + 1;
6208 scb->cmd.ffdc.day = days + 1;
6209}
6210
6211/****************************************************************************
6212 * BIOS Flash Routines *
6213 ****************************************************************************/
6214
6215/****************************************************************************/
6216/* */
6217/* Routine Name: ips_erase_bios */
6218/* */
6219/* Routine Description: */
6220/* Erase the BIOS on the adapter */
6221/* */
6222/****************************************************************************/
6223static int
6224ips_erase_bios(ips_ha_t * ha)
6225{
6226 int timeout;
6227 uint8_t status = 0;
6228
6229 METHOD_TRACE("ips_erase_bios", 1);
6230
6231 status = 0;
6232
6233 /* Clear the status register */
6234 outl(0, ha->io_addr + IPS_REG_FLAP);
6235 if (ha->revision_id == IPS_REVID_TROMBONE64)
6236 udelay(25); /* 25 us */
6237
6238 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6239 if (ha->revision_id == IPS_REVID_TROMBONE64)
6240 udelay(25); /* 25 us */
6241
6242 /* Erase Setup */
6243 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6244 if (ha->revision_id == IPS_REVID_TROMBONE64)
6245 udelay(25); /* 25 us */
6246
6247 /* Erase Confirm */
6248 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6249 if (ha->revision_id == IPS_REVID_TROMBONE64)
6250 udelay(25); /* 25 us */
6251
6252 /* Erase Status */
6253 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6254 if (ha->revision_id == IPS_REVID_TROMBONE64)
6255 udelay(25); /* 25 us */
6256
6257 timeout = 80000; /* 80 seconds */
6258
6259 while (timeout > 0) {
6260 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6261 outl(0, ha->io_addr + IPS_REG_FLAP);
6262 udelay(25); /* 25 us */
6263 }
6264
6265 status = inb(ha->io_addr + IPS_REG_FLDP);
6266
6267 if (status & 0x80)
6268 break;
6269
6270 MDELAY(1);
6271 timeout--;
6272 }
6273
6274 /* check for timeout */
6275 if (timeout <= 0) {
6276 /* timeout */
6277
6278 /* try to suspend the erase */
6279 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6280 if (ha->revision_id == IPS_REVID_TROMBONE64)
6281 udelay(25); /* 25 us */
6282
6283 /* wait for 10 seconds */
6284 timeout = 10000;
6285 while (timeout > 0) {
6286 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6287 outl(0, ha->io_addr + IPS_REG_FLAP);
6288 udelay(25); /* 25 us */
6289 }
6290
6291 status = inb(ha->io_addr + IPS_REG_FLDP);
6292
6293 if (status & 0xC0)
6294 break;
6295
6296 MDELAY(1);
6297 timeout--;
6298 }
6299
6300 return (1);
6301 }
6302
6303 /* check for valid VPP */
6304 if (status & 0x08)
6305 /* VPP failure */
6306 return (1);
6307
6308 /* check for succesful flash */
6309 if (status & 0x30)
6310 /* sequence error */
6311 return (1);
6312
6313 /* Otherwise, we were successful */
6314 /* clear status */
6315 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6316 if (ha->revision_id == IPS_REVID_TROMBONE64)
6317 udelay(25); /* 25 us */
6318
6319 /* enable reads */
6320 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6321 if (ha->revision_id == IPS_REVID_TROMBONE64)
6322 udelay(25); /* 25 us */
6323
6324 return (0);
6325}
6326
6327/****************************************************************************/
6328/* */
6329/* Routine Name: ips_erase_bios_memio */
6330/* */
6331/* Routine Description: */
6332/* Erase the BIOS on the adapter */
6333/* */
6334/****************************************************************************/
6335static int
6336ips_erase_bios_memio(ips_ha_t * ha)
6337{
6338 int timeout;
6339 uint8_t status;
6340
6341 METHOD_TRACE("ips_erase_bios_memio", 1);
6342
6343 status = 0;
6344
6345 /* Clear the status register */
6346 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6347 if (ha->revision_id == IPS_REVID_TROMBONE64)
6348 udelay(25); /* 25 us */
6349
6350 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6351 if (ha->revision_id == IPS_REVID_TROMBONE64)
6352 udelay(25); /* 25 us */
6353
6354 /* Erase Setup */
6355 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6356 if (ha->revision_id == IPS_REVID_TROMBONE64)
6357 udelay(25); /* 25 us */
6358
6359 /* Erase Confirm */
6360 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6361 if (ha->revision_id == IPS_REVID_TROMBONE64)
6362 udelay(25); /* 25 us */
6363
6364 /* Erase Status */
6365 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6366 if (ha->revision_id == IPS_REVID_TROMBONE64)
6367 udelay(25); /* 25 us */
6368
6369 timeout = 80000; /* 80 seconds */
6370
6371 while (timeout > 0) {
6372 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6373 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6374 udelay(25); /* 25 us */
6375 }
6376
6377 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6378
6379 if (status & 0x80)
6380 break;
6381
6382 MDELAY(1);
6383 timeout--;
6384 }
6385
6386 /* check for timeout */
6387 if (timeout <= 0) {
6388 /* timeout */
6389
6390 /* try to suspend the erase */
6391 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6392 if (ha->revision_id == IPS_REVID_TROMBONE64)
6393 udelay(25); /* 25 us */
6394
6395 /* wait for 10 seconds */
6396 timeout = 10000;
6397 while (timeout > 0) {
6398 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6399 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6400 udelay(25); /* 25 us */
6401 }
6402
6403 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6404
6405 if (status & 0xC0)
6406 break;
6407
6408 MDELAY(1);
6409 timeout--;
6410 }
6411
6412 return (1);
6413 }
6414
6415 /* check for valid VPP */
6416 if (status & 0x08)
6417 /* VPP failure */
6418 return (1);
6419
6420 /* check for succesful flash */
6421 if (status & 0x30)
6422 /* sequence error */
6423 return (1);
6424
6425 /* Otherwise, we were successful */
6426 /* clear status */
6427 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6428 if (ha->revision_id == IPS_REVID_TROMBONE64)
6429 udelay(25); /* 25 us */
6430
6431 /* enable reads */
6432 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6433 if (ha->revision_id == IPS_REVID_TROMBONE64)
6434 udelay(25); /* 25 us */
6435
6436 return (0);
6437}
6438
6439/****************************************************************************/
6440/* */
6441/* Routine Name: ips_program_bios */
6442/* */
6443/* Routine Description: */
6444/* Program the BIOS on the adapter */
6445/* */
6446/****************************************************************************/
6447static int
6448ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6449 uint32_t offset)
6450{
6451 int i;
6452 int timeout;
6453 uint8_t status = 0;
6454
6455 METHOD_TRACE("ips_program_bios", 1);
6456
6457 status = 0;
6458
6459 for (i = 0; i < buffersize; i++) {
6460 /* write a byte */
6461 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6462 if (ha->revision_id == IPS_REVID_TROMBONE64)
6463 udelay(25); /* 25 us */
6464
6465 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6466 if (ha->revision_id == IPS_REVID_TROMBONE64)
6467 udelay(25); /* 25 us */
6468
6469 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6470 if (ha->revision_id == IPS_REVID_TROMBONE64)
6471 udelay(25); /* 25 us */
6472
6473 /* wait up to one second */
6474 timeout = 1000;
6475 while (timeout > 0) {
6476 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6477 outl(0, ha->io_addr + IPS_REG_FLAP);
6478 udelay(25); /* 25 us */
6479 }
6480
6481 status = inb(ha->io_addr + IPS_REG_FLDP);
6482
6483 if (status & 0x80)
6484 break;
6485
6486 MDELAY(1);
6487 timeout--;
6488 }
6489
6490 if (timeout == 0) {
6491 /* timeout error */
6492 outl(0, ha->io_addr + IPS_REG_FLAP);
6493 if (ha->revision_id == IPS_REVID_TROMBONE64)
6494 udelay(25); /* 25 us */
6495
6496 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6497 if (ha->revision_id == IPS_REVID_TROMBONE64)
6498 udelay(25); /* 25 us */
6499
6500 return (1);
6501 }
6502
6503 /* check the status */
6504 if (status & 0x18) {
6505 /* programming error */
6506 outl(0, ha->io_addr + IPS_REG_FLAP);
6507 if (ha->revision_id == IPS_REVID_TROMBONE64)
6508 udelay(25); /* 25 us */
6509
6510 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6511 if (ha->revision_id == IPS_REVID_TROMBONE64)
6512 udelay(25); /* 25 us */
6513
6514 return (1);
6515 }
6516 } /* end for */
6517
6518 /* Enable reading */
6519 outl(0, ha->io_addr + IPS_REG_FLAP);
6520 if (ha->revision_id == IPS_REVID_TROMBONE64)
6521 udelay(25); /* 25 us */
6522
6523 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6524 if (ha->revision_id == IPS_REVID_TROMBONE64)
6525 udelay(25); /* 25 us */
6526
6527 return (0);
6528}
6529
6530/****************************************************************************/
6531/* */
6532/* Routine Name: ips_program_bios_memio */
6533/* */
6534/* Routine Description: */
6535/* Program the BIOS on the adapter */
6536/* */
6537/****************************************************************************/
6538static int
6539ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6540 uint32_t offset)
6541{
6542 int i;
6543 int timeout;
6544 uint8_t status = 0;
6545
6546 METHOD_TRACE("ips_program_bios_memio", 1);
6547
6548 status = 0;
6549
6550 for (i = 0; i < buffersize; i++) {
6551 /* write a byte */
6552 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6553 if (ha->revision_id == IPS_REVID_TROMBONE64)
6554 udelay(25); /* 25 us */
6555
6556 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6557 if (ha->revision_id == IPS_REVID_TROMBONE64)
6558 udelay(25); /* 25 us */
6559
6560 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6561 if (ha->revision_id == IPS_REVID_TROMBONE64)
6562 udelay(25); /* 25 us */
6563
6564 /* wait up to one second */
6565 timeout = 1000;
6566 while (timeout > 0) {
6567 if (ha->revision_id == IPS_REVID_TROMBONE64) {
6568 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6569 udelay(25); /* 25 us */
6570 }
6571
6572 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6573
6574 if (status & 0x80)
6575 break;
6576
6577 MDELAY(1);
6578 timeout--;
6579 }
6580
6581 if (timeout == 0) {
6582 /* timeout error */
6583 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6584 if (ha->revision_id == IPS_REVID_TROMBONE64)
6585 udelay(25); /* 25 us */
6586
6587 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6588 if (ha->revision_id == IPS_REVID_TROMBONE64)
6589 udelay(25); /* 25 us */
6590
6591 return (1);
6592 }
6593
6594 /* check the status */
6595 if (status & 0x18) {
6596 /* programming error */
6597 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6598 if (ha->revision_id == IPS_REVID_TROMBONE64)
6599 udelay(25); /* 25 us */
6600
6601 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6602 if (ha->revision_id == IPS_REVID_TROMBONE64)
6603 udelay(25); /* 25 us */
6604
6605 return (1);
6606 }
6607 } /* end for */
6608
6609 /* Enable reading */
6610 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6611 if (ha->revision_id == IPS_REVID_TROMBONE64)
6612 udelay(25); /* 25 us */
6613
6614 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6615 if (ha->revision_id == IPS_REVID_TROMBONE64)
6616 udelay(25); /* 25 us */
6617
6618 return (0);
6619}
6620
6621/****************************************************************************/
6622/* */
6623/* Routine Name: ips_verify_bios */
6624/* */
6625/* Routine Description: */
6626/* Verify the BIOS on the adapter */
6627/* */
6628/****************************************************************************/
6629static int
6630ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6631 uint32_t offset)
6632{
6633 uint8_t checksum;
6634 int i;
6635
6636 METHOD_TRACE("ips_verify_bios", 1);
6637
6638 /* test 1st byte */
6639 outl(0, ha->io_addr + IPS_REG_FLAP);
6640 if (ha->revision_id == IPS_REVID_TROMBONE64)
6641 udelay(25); /* 25 us */
6642
6643 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6644 return (1);
6645
6646 outl(cpu_to_le32(1), ha->io_addr + IPS_REG_FLAP);
6647 if (ha->revision_id == IPS_REVID_TROMBONE64)
6648 udelay(25); /* 25 us */
6649 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6650 return (1);
6651
6652 checksum = 0xff;
6653 for (i = 2; i < buffersize; i++) {
6654
6655 outl(cpu_to_le32(i + offset), ha->io_addr + IPS_REG_FLAP);
6656 if (ha->revision_id == IPS_REVID_TROMBONE64)
6657 udelay(25); /* 25 us */
6658
6659 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6660 }
6661
6662 if (checksum != 0)
6663 /* failure */
6664 return (1);
6665 else
6666 /* success */
6667 return (0);
6668}
6669
6670/****************************************************************************/
6671/* */
6672/* Routine Name: ips_verify_bios_memio */
6673/* */
6674/* Routine Description: */
6675/* Verify the BIOS on the adapter */
6676/* */
6677/****************************************************************************/
6678static int
6679ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6680 uint32_t offset)
6681{
6682 uint8_t checksum;
6683 int i;
6684
6685 METHOD_TRACE("ips_verify_bios_memio", 1);
6686
6687 /* test 1st byte */
6688 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6689 if (ha->revision_id == IPS_REVID_TROMBONE64)
6690 udelay(25); /* 25 us */
6691
6692 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6693 return (1);
6694
6695 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6696 if (ha->revision_id == IPS_REVID_TROMBONE64)
6697 udelay(25); /* 25 us */
6698 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6699 return (1);
6700
6701 checksum = 0xff;
6702 for (i = 2; i < buffersize; i++) {
6703
6704 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6705 if (ha->revision_id == IPS_REVID_TROMBONE64)
6706 udelay(25); /* 25 us */
6707
6708 checksum =
6709 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6710 }
6711
6712 if (checksum != 0)
6713 /* failure */
6714 return (1);
6715 else
6716 /* success */
6717 return (0);
6718}
6719
6720/*---------------------------------------------------------------------------*/
6721/* Routine Name: ips_version_check */
6722/* */
6723/* Dependencies: */
6724/* Assumes that ips_read_adapter_status() is called first filling in */
6725/* the data for SubSystem Parameters. */
6726/* Called from ips_write_driver_status() so it also assumes NVRAM Page 5 */
6727/* Data is available. */
6728/* */
6729/*---------------------------------------------------------------------------*/
6730static void
6731ips_version_check(ips_ha_t * ha, int intr)
6732{
6733 IPS_VERSION_DATA *VersionInfo;
6734 uint8_t FirmwareVersion[IPS_COMPAT_ID_LENGTH + 1];
6735 uint8_t BiosVersion[IPS_COMPAT_ID_LENGTH + 1];
6736 int MatchError;
6737 int rc;
6738 char BiosString[10];
6739 char FirmwareString[10];
6740
6741 METHOD_TRACE("ips_version_check", 1);
6742
6743 VersionInfo = ( IPS_VERSION_DATA * ) ha->ioctl_data;
6744
6745 memset(FirmwareVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6746 memset(BiosVersion, 0, IPS_COMPAT_ID_LENGTH + 1);
6747
6748 /* Get the Compatible BIOS Version from NVRAM Page 5 */
6749 memcpy(BiosVersion, ha->nvram->BiosCompatibilityID,
6750 IPS_COMPAT_ID_LENGTH);
6751
6752 rc = IPS_FAILURE;
6753 if (ha->subsys->param[4] & IPS_GET_VERSION_SUPPORT) { /* If Versioning is Supported */
6754 /* Get the Version Info with a Get Version Command */
6755 memset( VersionInfo, 0, sizeof (IPS_VERSION_DATA));
6756 rc = ips_get_version_info(ha, ha->ioctl_busaddr, intr);
6757 if (rc == IPS_SUCCESS)
6758 memcpy(FirmwareVersion, VersionInfo->compatibilityId,
6759 IPS_COMPAT_ID_LENGTH);
6760 }
6761
6762 if (rc != IPS_SUCCESS) { /* If Data Not Obtainable from a GetVersion Command */
6763 /* Get the Firmware Version from Enquiry Data */
6764 memcpy(FirmwareVersion, ha->enq->CodeBlkVersion,
6765 IPS_COMPAT_ID_LENGTH);
6766 }
6767
6768 /* printk(KERN_WARNING "Adapter's BIOS Version = %s\n", BiosVersion); */
6769 /* printk(KERN_WARNING "BIOS Compatible Version = %s\n", IPS_COMPAT_BIOS); */
6770 /* printk(KERN_WARNING "Adapter's Firmware Version = %s\n", FirmwareVersion); */
6771 /* printk(KERN_WARNING "Firmware Compatible Version = %s \n", Compatable[ ha->nvram->adapter_type ]); */
6772
6773 MatchError = 0;
6774
6775 if (strncmp
6776 (FirmwareVersion, Compatable[ha->nvram->adapter_type],
6777 IPS_COMPAT_ID_LENGTH) != 0)
6778 MatchError = 1;
6779
6780 if (strncmp(BiosVersion, IPS_COMPAT_BIOS, IPS_COMPAT_ID_LENGTH) != 0)
6781 MatchError = 1;
6782
6783 ha->nvram->versioning = 1; /* Indicate the Driver Supports Versioning */
6784
6785 if (MatchError) {
6786 ha->nvram->version_mismatch = 1;
6787 if (ips_cd_boot == 0) {
6788 strncpy(&BiosString[0], ha->nvram->bios_high, 4);
6789 strncpy(&BiosString[4], ha->nvram->bios_low, 4);
6790 BiosString[8] = 0;
6791
6792 strncpy(&FirmwareString[0], ha->enq->CodeBlkVersion, 8);
6793 FirmwareString[8] = 0;
6794
6795 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6796 "Warning ! ! ! ServeRAID Version Mismatch\n");
6797 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6798 "Bios = %s, Firmware = %s, Device Driver = %s%s\n",
6799 BiosString, FirmwareString, IPS_VERSION_HIGH,
6800 IPS_VERSION_LOW);
6801 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6802 "These levels should match to avoid possible compatibility problems.\n");
6803 }
6804 } else {
6805 ha->nvram->version_mismatch = 0;
6806 }
6807
6808 return;
6809}
6810
6811/*---------------------------------------------------------------------------*/
6812/* Routine Name: ips_get_version_info */
6813/* */
6814/* Routine Description: */
6815/* Issue an internal GETVERSION Command */
6816/* */
6817/* Return Value: */
6818/* 0 if Successful, else non-zero */
6819/*---------------------------------------------------------------------------*/
6820static int
6821ips_get_version_info(ips_ha_t * ha, dma_addr_t Buffer, int intr)
6822{
6823 ips_scb_t *scb;
6824 int rc;
6825
6826 METHOD_TRACE("ips_get_version_info", 1);
6827
6828 scb = &ha->scbs[ha->max_cmds - 1];
6829
6830 ips_init_scb(ha, scb);
6831
6832 scb->timeout = ips_cmd_timeout;
6833 scb->cdb[0] = IPS_CMD_GET_VERSION_INFO;
6834 scb->cmd.version_info.op_code = IPS_CMD_GET_VERSION_INFO;
6835 scb->cmd.version_info.command_id = IPS_COMMAND_ID(ha, scb);
6836 scb->cmd.version_info.reserved = 0;
6837 scb->cmd.version_info.count = sizeof (IPS_VERSION_DATA);
6838 scb->cmd.version_info.reserved2 = 0;
6839 scb->data_len = sizeof (IPS_VERSION_DATA);
6840 scb->data_busaddr = Buffer;
6841 scb->cmd.version_info.buffer_addr = Buffer;
6842 scb->flags = 0;
6843
6844 /* issue command */
6845 rc = ips_send_wait(ha, scb, ips_cmd_timeout, intr);
6846 return (rc);
6847}
6848
6849/****************************************************************************/
6850/* */
6851/* Routine Name: ips_abort_init */
6852/* */
6853/* Routine Description: */
6854/* cleanup routine for a failed adapter initialization */
6855/****************************************************************************/
6856static int
6857ips_abort_init(ips_ha_t * ha, int index)
6858{
6859 ha->active = 0;
6860 ips_free(ha);
6861 ips_ha[index] = NULL;
6862 ips_sh[index] = NULL;
6863 return -1;
6864}
6865
6866/****************************************************************************/
6867/* */
6868/* Routine Name: ips_shift_controllers */
6869/* */
6870/* Routine Description: */
6871/* helper function for ordering adapters */
6872/****************************************************************************/
6873static void
6874ips_shift_controllers(int lowindex, int highindex)
6875{
6876 ips_ha_t *ha_sav = ips_ha[highindex];
6877 struct Scsi_Host *sh_sav = ips_sh[highindex];
6878 int i;
6879
6880 for (i = highindex; i > lowindex; i--) {
6881 ips_ha[i] = ips_ha[i - 1];
6882 ips_sh[i] = ips_sh[i - 1];
6883 ips_ha[i]->host_num = i;
6884 }
6885 ha_sav->host_num = lowindex;
6886 ips_ha[lowindex] = ha_sav;
6887 ips_sh[lowindex] = sh_sav;
6888}
6889
6890/****************************************************************************/
6891/* */
6892/* Routine Name: ips_order_controllers */
6893/* */
6894/* Routine Description: */
6895/* place controllers is the "proper" boot order */
6896/****************************************************************************/
6897static void
6898ips_order_controllers(void)
6899{
6900 int i, j, tmp, position = 0;
6901 IPS_NVRAM_P5 *nvram;
6902 if (!ips_ha[0])
6903 return;
6904 nvram = ips_ha[0]->nvram;
6905
6906 if (nvram->adapter_order[0]) {
6907 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6908 for (j = position; j < ips_num_controllers; j++) {
6909 switch (ips_ha[j]->ad_type) {
6910 case IPS_ADTYPE_SERVERAID6M:
6911 case IPS_ADTYPE_SERVERAID7M:
6912 if (nvram->adapter_order[i] == 'M') {
6913 ips_shift_controllers(position,
6914 j);
6915 position++;
6916 }
6917 break;
6918 case IPS_ADTYPE_SERVERAID4L:
6919 case IPS_ADTYPE_SERVERAID4M:
6920 case IPS_ADTYPE_SERVERAID4MX:
6921 case IPS_ADTYPE_SERVERAID4LX:
6922 if (nvram->adapter_order[i] == 'N') {
6923 ips_shift_controllers(position,
6924 j);
6925 position++;
6926 }
6927 break;
6928 case IPS_ADTYPE_SERVERAID6I:
6929 case IPS_ADTYPE_SERVERAID5I2:
6930 case IPS_ADTYPE_SERVERAID5I1:
6931 case IPS_ADTYPE_SERVERAID7k:
6932 if (nvram->adapter_order[i] == 'S') {
6933 ips_shift_controllers(position,
6934 j);
6935 position++;
6936 }
6937 break;
6938 case IPS_ADTYPE_SERVERAID:
6939 case IPS_ADTYPE_SERVERAID2:
6940 case IPS_ADTYPE_NAVAJO:
6941 case IPS_ADTYPE_KIOWA:
6942 case IPS_ADTYPE_SERVERAID3L:
6943 case IPS_ADTYPE_SERVERAID3:
6944 case IPS_ADTYPE_SERVERAID4H:
6945 if (nvram->adapter_order[i] == 'A') {
6946 ips_shift_controllers(position,
6947 j);
6948 position++;
6949 }
6950 break;
6951 default:
6952 break;
6953 }
6954 }
6955 }
6956 /* if adapter_order[0], then ordering is complete */
6957 return;
6958 }
6959 /* old bios, use older ordering */
6960 tmp = 0;
6961 for (i = position; i < ips_num_controllers; i++) {
6962 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6963 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6964 ips_shift_controllers(position, i);
6965 position++;
6966 tmp = 1;
6967 }
6968 }
6969 /* if there were no 5I cards, then don't do any extra ordering */
6970 if (!tmp)
6971 return;
6972 for (i = position; i < ips_num_controllers; i++) {
6973 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6974 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6975 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6976 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6977 ips_shift_controllers(position, i);
6978 position++;
6979 }
6980 }
6981
6982 return;
6983}
6984
6985/****************************************************************************/
6986/* */
6987/* Routine Name: ips_register_scsi */
6988/* */
6989/* Routine Description: */
6990/* perform any registration and setup with the scsi layer */
6991/****************************************************************************/
6992static int
6993ips_register_scsi(int index)
6994{
6995 struct Scsi_Host *sh;
6996 ips_ha_t *ha, *oldha = ips_ha[index];
6997 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6998 if (!sh) {
6999 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
7000 "Unable to register controller with SCSI subsystem\n");
7001 return -1;
7002 }
7003 ha = IPS_HA(sh);
7004 memcpy(ha, oldha, sizeof (ips_ha_t));
7005 free_irq(oldha->irq, oldha);
7006 /* Install the interrupt handler with the new ha */
7007 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7008 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7009 "Unable to install interrupt handler\n");
7010 scsi_host_put(sh);
7011 return -1;
7012 }
7013
7014 kfree(oldha);
7015 ips_sh[index] = sh;
7016 ips_ha[index] = ha;
7017 IPS_SCSI_SET_DEVICE(sh, ha);
7018
7019 /* Store away needed values for later use */
7020 sh->io_port = ha->io_addr;
7021 sh->n_io_port = ha->io_addr ? 255 : 0;
7022 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
7023 sh->irq = ha->irq;
7024 sh->sg_tablesize = sh->hostt->sg_tablesize;
7025 sh->can_queue = sh->hostt->can_queue;
7026 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
7027 sh->unchecked_isa_dma = sh->hostt->unchecked_isa_dma;
7028 sh->use_clustering = sh->hostt->use_clustering;
7029
7030#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,7)
7031 sh->max_sectors = 128;
7032#endif
7033
7034 sh->max_id = ha->ntargets;
7035 sh->max_lun = ha->nlun;
7036 sh->max_channel = ha->nbus - 1;
7037 sh->can_queue = ha->max_cmds - 1;
7038
7039 IPS_ADD_HOST(sh, NULL);
7040 return 0;
7041}
7042
7043/*---------------------------------------------------------------------------*/
7044/* Routine Name: ips_remove_device */
7045/* */
7046/* Routine Description: */
7047/* Remove one Adapter ( Hot Plugging ) */
7048/*---------------------------------------------------------------------------*/
7049static void __devexit
7050ips_remove_device(struct pci_dev *pci_dev)
7051{
7052 int i;
7053 struct Scsi_Host *sh;
7054 ips_ha_t *ha;
7055
7056 for (i = 0; i < IPS_MAX_ADAPTERS; i++) {
7057 ha = ips_ha[i];
7058 if (ha) {
7059 if ((pci_dev->bus->number == ha->pcidev->bus->number) &&
7060 (pci_dev->devfn == ha->pcidev->devfn)) {
7061 sh = ips_sh[i];
7062 ips_release(sh);
7063 }
7064 }
7065 }
7066}
7067
7068/****************************************************************************/
7069/* */
7070/* Routine Name: ips_module_init */
7071/* */
7072/* Routine Description: */
7073/* function called on module load */
7074/****************************************************************************/
7075static int __init
7076ips_module_init(void)
7077{
7078 if (pci_module_init(&ips_pci_driver) < 0)
7079 return -ENODEV;
7080 ips_driver_template.module = THIS_MODULE;
7081 ips_order_controllers();
7082 if (IPS_REGISTER_HOSTS(&ips_driver_template)) {
7083 pci_unregister_driver(&ips_pci_driver);
7084 return -ENODEV;
7085 }
7086 register_reboot_notifier(&ips_notifier);
7087 return 0;
7088}
7089
7090/****************************************************************************/
7091/* */
7092/* Routine Name: ips_module_exit */
7093/* */
7094/* Routine Description: */
7095/* function called on module unload */
7096/****************************************************************************/
7097static void __exit
7098ips_module_exit(void)
7099{
7100 IPS_UNREGISTER_HOSTS(&ips_driver_template);
7101 pci_unregister_driver(&ips_pci_driver);
7102 unregister_reboot_notifier(&ips_notifier);
7103}
7104
7105module_init(ips_module_init);
7106module_exit(ips_module_exit);
7107
7108/*---------------------------------------------------------------------------*/
7109/* Routine Name: ips_insert_device */
7110/* */
7111/* Routine Description: */
7112/* Add One Adapter ( Hot Plug ) */
7113/* */
7114/* Return Value: */
7115/* 0 if Successful, else non-zero */
7116/*---------------------------------------------------------------------------*/
7117static int __devinit
7118ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
7119{
7120 int index;
7121 int rc;
7122
7123 METHOD_TRACE("ips_insert_device", 1);
7124 if (pci_enable_device(pci_dev))
7125 return -1;
7126
7127 rc = ips_init_phase1(pci_dev, &index);
7128 if (rc == SUCCESS)
7129 rc = ips_init_phase2(index);
7130
7131 if (ips_hotplug)
7132 if (ips_register_scsi(index)) {
7133 ips_free(ips_ha[index]);
7134 rc = -1;
7135 }
7136
7137 if (rc == SUCCESS)
7138 ips_num_controllers++;
7139
7140 ips_next_controller = ips_num_controllers;
7141 return rc;
7142}
7143
7144/*---------------------------------------------------------------------------*/
7145/* Routine Name: ips_init_phase1 */
7146/* */
7147/* Routine Description: */
7148/* Adapter Initialization */
7149/* */
7150/* Return Value: */
7151/* 0 if Successful, else non-zero */
7152/*---------------------------------------------------------------------------*/
7153static int
7154ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
7155{
7156 ips_ha_t *ha;
7157 uint32_t io_addr;
7158 uint32_t mem_addr;
7159 uint32_t io_len;
7160 uint32_t mem_len;
7161 uint8_t revision_id;
7162 uint8_t bus;
7163 uint8_t func;
7164 uint8_t irq;
7165 uint16_t subdevice_id;
7166 int j;
7167 int index;
7168 dma_addr_t dma_address;
7169 char __iomem *ioremap_ptr;
7170 char __iomem *mem_ptr;
7171 uint32_t IsDead;
7172
7173 METHOD_TRACE("ips_init_phase1", 1);
7174 index = IPS_MAX_ADAPTERS;
7175 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
7176 if (ips_ha[j] == 0) {
7177 index = j;
7178 break;
7179 }
7180 }
7181
7182 if (index >= IPS_MAX_ADAPTERS)
7183 return -1;
7184
7185 /* stuff that we get in dev */
7186 irq = pci_dev->irq;
7187 bus = pci_dev->bus->number;
7188 func = pci_dev->devfn;
7189
7190 /* Init MEM/IO addresses to 0 */
7191 mem_addr = 0;
7192 io_addr = 0;
7193 mem_len = 0;
7194 io_len = 0;
7195
7196 for (j = 0; j < 2; j++) {
7197 if (!pci_resource_start(pci_dev, j))
7198 break;
7199
7200 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
7201 io_addr = pci_resource_start(pci_dev, j);
7202 io_len = pci_resource_len(pci_dev, j);
7203 } else {
7204 mem_addr = pci_resource_start(pci_dev, j);
7205 mem_len = pci_resource_len(pci_dev, j);
7206 }
7207 }
7208
7209 /* setup memory mapped area (if applicable) */
7210 if (mem_addr) {
7211 uint32_t base;
7212 uint32_t offs;
7213
7214 if (!request_mem_region(mem_addr, mem_len, "ips")) {
7215 IPS_PRINTK(KERN_WARNING, pci_dev,
7216 "Couldn't allocate IO Memory space %x len %d.\n",
7217 mem_addr, mem_len);
7218 return -1;
7219 }
7220
7221 base = mem_addr & PAGE_MASK;
7222 offs = mem_addr - base;
7223 ioremap_ptr = ioremap(base, PAGE_SIZE);
7224 mem_ptr = ioremap_ptr + offs;
7225 } else {
7226 ioremap_ptr = NULL;
7227 mem_ptr = NULL;
7228 }
7229
7230 /* setup I/O mapped area (if applicable) */
7231 if (io_addr) {
7232 if (!request_region(io_addr, io_len, "ips")) {
7233 IPS_PRINTK(KERN_WARNING, pci_dev,
7234 "Couldn't allocate IO space %x len %d.\n",
7235 io_addr, io_len);
7236 return -1;
7237 }
7238 }
7239
7240 /* get the revision ID */
7241 if (pci_read_config_byte(pci_dev, PCI_REVISION_ID, &revision_id)) {
7242 IPS_PRINTK(KERN_WARNING, pci_dev, "Can't get revision id.\n");
7243 return -1;
7244 }
7245
7246 subdevice_id = pci_dev->subsystem_device;
7247
7248 /* found a controller */
7249 ha = kmalloc(sizeof (ips_ha_t), GFP_KERNEL);
7250 if (ha == NULL) {
7251 IPS_PRINTK(KERN_WARNING, pci_dev,
7252 "Unable to allocate temporary ha struct\n");
7253 return -1;
7254 }
7255
7256 memset(ha, 0, sizeof (ips_ha_t));
7257
7258 ips_sh[index] = NULL;
7259 ips_ha[index] = ha;
7260 ha->active = 1;
7261
7262 /* Store info in HA structure */
7263 ha->irq = irq;
7264 ha->io_addr = io_addr;
7265 ha->io_len = io_len;
7266 ha->mem_addr = mem_addr;
7267 ha->mem_len = mem_len;
7268 ha->mem_ptr = mem_ptr;
7269 ha->ioremap_ptr = ioremap_ptr;
7270 ha->host_num = (uint32_t) index;
7271 ha->revision_id = revision_id;
7272 ha->slot_num = PCI_SLOT(pci_dev->devfn);
7273 ha->device_id = pci_dev->device;
7274 ha->subdevice_id = subdevice_id;
7275 ha->pcidev = pci_dev;
7276
7277 /*
7278 * Set the pci_dev's dma_mask. Not all adapters support 64bit
7279 * addressing so don't enable it if the adapter can't support
7280 * it! Also, don't use 64bit addressing if dma addresses
7281 * are guaranteed to be < 4G.
7282 */
7283 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
7284 !pci_set_dma_mask(ha->pcidev, 0xffffffffffffffffULL)) {
7285 (ha)->flags |= IPS_HA_ENH_SG;
7286 } else {
7287 if (pci_set_dma_mask(ha->pcidev, 0xffffffffULL) != 0) {
7288 printk(KERN_WARNING "Unable to set DMA Mask\n");
7289 return ips_abort_init(ha, index);
7290 }
7291 }
7292 if(ips_cd_boot && !ips_FlashData){
7293 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
7294 &ips_flashbusaddr);
7295 }
7296
7297 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
7298 &ha->enq_busaddr);
7299 if (!ha->enq) {
7300 IPS_PRINTK(KERN_WARNING, pci_dev,
7301 "Unable to allocate host inquiry structure\n");
7302 return ips_abort_init(ha, index);
7303 }
7304
7305 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7306 sizeof (IPS_IO_CMD), &dma_address);
7307 if (!ha->adapt) {
7308 IPS_PRINTK(KERN_WARNING, pci_dev,
7309 "Unable to allocate host adapt & dummy structures\n");
7310 return ips_abort_init(ha, index);
7311 }
7312 ha->adapt->hw_status_start = dma_address;
7313 ha->dummy = (void *) (ha->adapt + 1);
7314
7315
7316
7317 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7318 if (!ha->logical_drive_info) {
7319 IPS_PRINTK(KERN_WARNING, pci_dev,
7320 "Unable to allocate logical drive info structure\n");
7321 return ips_abort_init(ha, index);
7322 }
7323 ha->logical_drive_info_dma_addr = dma_address;
7324
7325
7326 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7327
7328 if (!ha->conf) {
7329 IPS_PRINTK(KERN_WARNING, pci_dev,
7330 "Unable to allocate host conf structure\n");
7331 return ips_abort_init(ha, index);
7332 }
7333
7334 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7335
7336 if (!ha->nvram) {
7337 IPS_PRINTK(KERN_WARNING, pci_dev,
7338 "Unable to allocate host NVRAM structure\n");
7339 return ips_abort_init(ha, index);
7340 }
7341
7342 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7343
7344 if (!ha->subsys) {
7345 IPS_PRINTK(KERN_WARNING, pci_dev,
7346 "Unable to allocate host subsystem structure\n");
7347 return ips_abort_init(ha, index);
7348 }
7349
7350 /* the ioctl buffer is now used during adapter initialization, so its
7351 * successful allocation is now required */
7352 if (ips_ioctlsize < PAGE_SIZE)
7353 ips_ioctlsize = PAGE_SIZE;
7354
7355 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7356 &ha->ioctl_busaddr);
7357 ha->ioctl_len = ips_ioctlsize;
7358 if (!ha->ioctl_data) {
7359 IPS_PRINTK(KERN_WARNING, pci_dev,
7360 "Unable to allocate IOCTL data\n");
7361 return ips_abort_init(ha, index);
7362 }
7363
7364 /*
7365 * Setup Functions
7366 */
7367 ips_setup_funclist(ha);
7368
7369 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7370 /* If Morpheus appears dead, reset it */
7371 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7372 if (IsDead == 0xDEADBEEF) {
7373 ips_reset_morpheus(ha);
7374 }
7375 }
7376
7377 /*
7378 * Initialize the card if it isn't already
7379 */
7380
7381 if (!(*ha->func.isinit) (ha)) {
7382 if (!(*ha->func.init) (ha)) {
7383 /*
7384 * Initialization failed
7385 */
7386 IPS_PRINTK(KERN_WARNING, pci_dev,
7387 "Unable to initialize controller\n");
7388 return ips_abort_init(ha, index);
7389 }
7390 }
7391
7392 *indexPtr = index;
7393 return SUCCESS;
7394}
7395
7396/*---------------------------------------------------------------------------*/
7397/* Routine Name: ips_init_phase2 */
7398/* */
7399/* Routine Description: */
7400/* Adapter Initialization Phase 2 */
7401/* */
7402/* Return Value: */
7403/* 0 if Successful, else non-zero */
7404/*---------------------------------------------------------------------------*/
7405static int
7406ips_init_phase2(int index)
7407{
7408 ips_ha_t *ha;
7409
7410 ha = ips_ha[index];
7411
7412 METHOD_TRACE("ips_init_phase2", 1);
7413 if (!ha->active) {
7414 ips_ha[index] = NULL;
7415 return -1;
7416 }
7417
7418 /* Install the interrupt handler */
7419 if (request_irq(ha->irq, do_ipsintr, SA_SHIRQ, ips_name, ha)) {
7420 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7421 "Unable to install interrupt handler\n");
7422 return ips_abort_init(ha, index);
7423 }
7424
7425 /*
7426 * Allocate a temporary SCB for initialization
7427 */
7428 ha->max_cmds = 1;
7429 if (!ips_allocatescbs(ha)) {
7430 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7431 "Unable to allocate a CCB\n");
7432 free_irq(ha->irq, ha);
7433 return ips_abort_init(ha, index);
7434 }
7435
7436 if (!ips_hainit(ha)) {
7437 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7438 "Unable to initialize controller\n");
7439 free_irq(ha->irq, ha);
7440 return ips_abort_init(ha, index);
7441 }
7442 /* Free the temporary SCB */
7443 ips_deallocatescbs(ha, 1);
7444
7445 /* allocate CCBs */
7446 if (!ips_allocatescbs(ha)) {
7447 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7448 "Unable to allocate CCBs\n");
7449 free_irq(ha->irq, ha);
7450 return ips_abort_init(ha, index);
7451 }
7452
7453 return SUCCESS;
7454}
7455
7456#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,9)
7457MODULE_LICENSE("GPL");
7458#endif
7459
7460MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7461
7462#ifdef MODULE_VERSION
7463MODULE_VERSION(IPS_VER_STRING);
7464#endif
7465
7466
7467/*
7468 * Overrides for Emacs so that we almost follow Linus's tabbing style.
7469 * Emacs will notice this stuff at the end of the file and automatically
7470 * adjust the settings for this buffer only. This must remain at the end
7471 * of the file.
7472 * ---------------------------------------------------------------------------
7473 * Local variables:
7474 * c-indent-level: 2
7475 * c-brace-imaginary-offset: 0
7476 * c-brace-offset: -2
7477 * c-argdecl-indent: 2
7478 * c-label-offset: -2
7479 * c-continued-statement-offset: 2
7480 * c-continued-brace-offset: 0
7481 * indent-tabs-mode: nil
7482 * tab-width: 8
7483 * End:
7484 */
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