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6f231dda DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * BSD LICENSE | |
25 | * | |
26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
27 | * All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions | |
31 | * are met: | |
32 | * | |
33 | * * Redistributions of source code must retain the above copyright | |
34 | * notice, this list of conditions and the following disclaimer. | |
35 | * * Redistributions in binary form must reproduce the above copyright | |
36 | * notice, this list of conditions and the following disclaimer in | |
37 | * the documentation and/or other materials provided with the | |
38 | * distribution. | |
39 | * * Neither the name of Intel Corporation nor the names of its | |
40 | * contributors may be used to endorse or promote products derived | |
41 | * from this software without specific prior written permission. | |
42 | * | |
43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
54 | */ | |
cc9203bf DW |
55 | #include <linux/device.h> |
56 | #include <scsi/sas.h> | |
57 | #include "host.h" | |
6f231dda | 58 | #include "isci.h" |
6f231dda | 59 | #include "port.h" |
6f231dda | 60 | #include "host.h" |
d044af17 | 61 | #include "probe_roms.h" |
cc9203bf DW |
62 | #include "remote_device.h" |
63 | #include "request.h" | |
cc9203bf DW |
64 | #include "scu_completion_codes.h" |
65 | #include "scu_event_codes.h" | |
63a3a15f | 66 | #include "registers.h" |
cc9203bf DW |
67 | #include "scu_remote_node_context.h" |
68 | #include "scu_task_context.h" | |
69 | #include "scu_unsolicited_frame.h" | |
ce2b3261 | 70 | #include "timers.h" |
6f231dda | 71 | |
cc9203bf DW |
72 | #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200 |
73 | ||
74 | /** | |
75 | * smu_dcc_get_max_ports() - | |
76 | * | |
77 | * This macro returns the maximum number of logical ports supported by the | |
78 | * hardware. The caller passes in the value read from the device context | |
79 | * capacity register and this macro will mash and shift the value appropriately. | |
80 | */ | |
81 | #define smu_dcc_get_max_ports(dcc_value) \ | |
82 | (\ | |
83 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ | |
84 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \ | |
85 | ) | |
86 | ||
87 | /** | |
88 | * smu_dcc_get_max_task_context() - | |
89 | * | |
90 | * This macro returns the maximum number of task contexts supported by the | |
91 | * hardware. The caller passes in the value read from the device context | |
92 | * capacity register and this macro will mash and shift the value appropriately. | |
93 | */ | |
94 | #define smu_dcc_get_max_task_context(dcc_value) \ | |
95 | (\ | |
96 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ | |
97 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \ | |
98 | ) | |
99 | ||
100 | /** | |
101 | * smu_dcc_get_max_remote_node_context() - | |
102 | * | |
103 | * This macro returns the maximum number of remote node contexts supported by | |
104 | * the hardware. The caller passes in the value read from the device context | |
105 | * capacity register and this macro will mash and shift the value appropriately. | |
106 | */ | |
107 | #define smu_dcc_get_max_remote_node_context(dcc_value) \ | |
108 | (\ | |
109 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ | |
110 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \ | |
111 | ) | |
112 | ||
113 | ||
114 | #define SCIC_SDS_CONTROLLER_MIN_TIMER_COUNT 3 | |
115 | #define SCIC_SDS_CONTROLLER_MAX_TIMER_COUNT 3 | |
116 | ||
117 | /** | |
118 | * | |
119 | * | |
120 | * The number of milliseconds to wait for a phy to start. | |
121 | */ | |
122 | #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100 | |
123 | ||
124 | /** | |
125 | * | |
126 | * | |
127 | * The number of milliseconds to wait while a given phy is consuming power | |
128 | * before allowing another set of phys to consume power. Ultimately, this will | |
129 | * be specified by OEM parameter. | |
130 | */ | |
131 | #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500 | |
132 | ||
133 | /** | |
134 | * NORMALIZE_PUT_POINTER() - | |
135 | * | |
136 | * This macro will normalize the completion queue put pointer so its value can | |
137 | * be used as an array inde | |
138 | */ | |
139 | #define NORMALIZE_PUT_POINTER(x) \ | |
140 | ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK) | |
141 | ||
142 | ||
143 | /** | |
144 | * NORMALIZE_EVENT_POINTER() - | |
145 | * | |
146 | * This macro will normalize the completion queue event entry so its value can | |
147 | * be used as an index. | |
148 | */ | |
149 | #define NORMALIZE_EVENT_POINTER(x) \ | |
150 | (\ | |
151 | ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \ | |
152 | >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \ | |
153 | ) | |
154 | ||
155 | /** | |
156 | * INCREMENT_COMPLETION_QUEUE_GET() - | |
157 | * | |
158 | * This macro will increment the controllers completion queue index value and | |
159 | * possibly toggle the cycle bit if the completion queue index wraps back to 0. | |
160 | */ | |
161 | #define INCREMENT_COMPLETION_QUEUE_GET(controller, index, cycle) \ | |
162 | INCREMENT_QUEUE_GET(\ | |
163 | (index), \ | |
164 | (cycle), \ | |
165 | (controller)->completion_queue_entries, \ | |
166 | SMU_CQGR_CYCLE_BIT \ | |
167 | ) | |
168 | ||
169 | /** | |
170 | * INCREMENT_EVENT_QUEUE_GET() - | |
171 | * | |
172 | * This macro will increment the controllers event queue index value and | |
173 | * possibly toggle the event cycle bit if the event queue index wraps back to 0. | |
174 | */ | |
175 | #define INCREMENT_EVENT_QUEUE_GET(controller, index, cycle) \ | |
176 | INCREMENT_QUEUE_GET(\ | |
177 | (index), \ | |
178 | (cycle), \ | |
179 | (controller)->completion_event_entries, \ | |
180 | SMU_CQGR_EVENT_CYCLE_BIT \ | |
181 | ) | |
182 | ||
183 | ||
184 | /** | |
185 | * NORMALIZE_GET_POINTER() - | |
186 | * | |
187 | * This macro will normalize the completion queue get pointer so its value can | |
188 | * be used as an index into an array | |
189 | */ | |
190 | #define NORMALIZE_GET_POINTER(x) \ | |
191 | ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK) | |
192 | ||
193 | /** | |
194 | * NORMALIZE_GET_POINTER_CYCLE_BIT() - | |
195 | * | |
196 | * This macro will normalize the completion queue cycle pointer so it matches | |
197 | * the completion queue cycle bit | |
198 | */ | |
199 | #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \ | |
200 | ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT)) | |
201 | ||
202 | /** | |
203 | * COMPLETION_QUEUE_CYCLE_BIT() - | |
204 | * | |
205 | * This macro will return the cycle bit of the completion queue entry | |
206 | */ | |
207 | #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000) | |
208 | ||
209 | static bool scic_sds_controller_completion_queue_has_entries( | |
210 | struct scic_sds_controller *scic) | |
211 | { | |
212 | u32 get_value = scic->completion_queue_get; | |
213 | u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; | |
214 | ||
215 | if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == | |
216 | COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index])) | |
217 | return true; | |
218 | ||
219 | return false; | |
220 | } | |
221 | ||
222 | static bool scic_sds_controller_isr(struct scic_sds_controller *scic) | |
223 | { | |
224 | if (scic_sds_controller_completion_queue_has_entries(scic)) { | |
225 | return true; | |
226 | } else { | |
227 | /* | |
228 | * we have a spurious interrupt it could be that we have already | |
229 | * emptied the completion queue from a previous interrupt */ | |
230 | writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); | |
231 | ||
232 | /* | |
233 | * There is a race in the hardware that could cause us not to be notified | |
234 | * of an interrupt completion if we do not take this step. We will mask | |
235 | * then unmask the interrupts so if there is another interrupt pending | |
236 | * the clearing of the interrupt source we get the next interrupt message. */ | |
237 | writel(0xFF000000, &scic->smu_registers->interrupt_mask); | |
238 | writel(0, &scic->smu_registers->interrupt_mask); | |
239 | } | |
240 | ||
241 | return false; | |
242 | } | |
243 | ||
c7ef4031 | 244 | irqreturn_t isci_msix_isr(int vec, void *data) |
6f231dda | 245 | { |
c7ef4031 | 246 | struct isci_host *ihost = data; |
c7ef4031 | 247 | |
cc3dbd0a | 248 | if (scic_sds_controller_isr(&ihost->sci)) |
0cf89d1d | 249 | tasklet_schedule(&ihost->completion_tasklet); |
6f231dda | 250 | |
c7ef4031 | 251 | return IRQ_HANDLED; |
6f231dda DW |
252 | } |
253 | ||
cc9203bf DW |
254 | static bool scic_sds_controller_error_isr(struct scic_sds_controller *scic) |
255 | { | |
256 | u32 interrupt_status; | |
257 | ||
258 | interrupt_status = | |
259 | readl(&scic->smu_registers->interrupt_status); | |
260 | interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); | |
261 | ||
262 | if (interrupt_status != 0) { | |
263 | /* | |
264 | * There is an error interrupt pending so let it through and handle | |
265 | * in the callback */ | |
266 | return true; | |
267 | } | |
268 | ||
269 | /* | |
270 | * There is a race in the hardware that could cause us not to be notified | |
271 | * of an interrupt completion if we do not take this step. We will mask | |
272 | * then unmask the error interrupts so if there was another interrupt | |
273 | * pending we will be notified. | |
274 | * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ | |
275 | writel(0xff, &scic->smu_registers->interrupt_mask); | |
276 | writel(0, &scic->smu_registers->interrupt_mask); | |
277 | ||
278 | return false; | |
279 | } | |
280 | ||
281 | static void scic_sds_controller_task_completion(struct scic_sds_controller *scic, | |
282 | u32 completion_entry) | |
283 | { | |
284 | u32 index; | |
285 | struct scic_sds_request *io_request; | |
286 | ||
287 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
288 | io_request = scic->io_request_table[index]; | |
289 | ||
290 | /* Make sure that we really want to process this IO request */ | |
291 | if ( | |
292 | (io_request != NULL) | |
293 | && (io_request->io_tag != SCI_CONTROLLER_INVALID_IO_TAG) | |
294 | && ( | |
295 | scic_sds_io_tag_get_sequence(io_request->io_tag) | |
296 | == scic->io_request_sequence[index] | |
297 | ) | |
298 | ) { | |
299 | /* Yep this is a valid io request pass it along to the io request handler */ | |
300 | scic_sds_io_request_tc_completion(io_request, completion_entry); | |
301 | } | |
302 | } | |
303 | ||
304 | static void scic_sds_controller_sdma_completion(struct scic_sds_controller *scic, | |
305 | u32 completion_entry) | |
306 | { | |
307 | u32 index; | |
308 | struct scic_sds_request *io_request; | |
309 | struct scic_sds_remote_device *device; | |
310 | ||
311 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
312 | ||
313 | switch (scu_get_command_request_type(completion_entry)) { | |
314 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: | |
315 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: | |
316 | io_request = scic->io_request_table[index]; | |
317 | dev_warn(scic_to_dev(scic), | |
318 | "%s: SCIC SDS Completion type SDMA %x for io request " | |
319 | "%p\n", | |
320 | __func__, | |
321 | completion_entry, | |
322 | io_request); | |
323 | /* @todo For a post TC operation we need to fail the IO | |
324 | * request | |
325 | */ | |
326 | break; | |
327 | ||
328 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: | |
329 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: | |
330 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: | |
331 | device = scic->device_table[index]; | |
332 | dev_warn(scic_to_dev(scic), | |
333 | "%s: SCIC SDS Completion type SDMA %x for remote " | |
334 | "device %p\n", | |
335 | __func__, | |
336 | completion_entry, | |
337 | device); | |
338 | /* @todo For a port RNC operation we need to fail the | |
339 | * device | |
340 | */ | |
341 | break; | |
342 | ||
343 | default: | |
344 | dev_warn(scic_to_dev(scic), | |
345 | "%s: SCIC SDS Completion unknown SDMA completion " | |
346 | "type %x\n", | |
347 | __func__, | |
348 | completion_entry); | |
349 | break; | |
350 | ||
351 | } | |
352 | } | |
353 | ||
354 | static void scic_sds_controller_unsolicited_frame(struct scic_sds_controller *scic, | |
355 | u32 completion_entry) | |
356 | { | |
357 | u32 index; | |
358 | u32 frame_index; | |
359 | ||
360 | struct isci_host *ihost = scic_to_ihost(scic); | |
361 | struct scu_unsolicited_frame_header *frame_header; | |
362 | struct scic_sds_phy *phy; | |
363 | struct scic_sds_remote_device *device; | |
364 | ||
365 | enum sci_status result = SCI_FAILURE; | |
366 | ||
367 | frame_index = SCU_GET_FRAME_INDEX(completion_entry); | |
368 | ||
369 | frame_header = scic->uf_control.buffers.array[frame_index].header; | |
370 | scic->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; | |
371 | ||
372 | if (SCU_GET_FRAME_ERROR(completion_entry)) { | |
373 | /* | |
374 | * / @todo If the IAF frame or SIGNATURE FIS frame has an error will | |
375 | * / this cause a problem? We expect the phy initialization will | |
376 | * / fail if there is an error in the frame. */ | |
377 | scic_sds_controller_release_frame(scic, frame_index); | |
378 | return; | |
379 | } | |
380 | ||
381 | if (frame_header->is_address_frame) { | |
382 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
383 | phy = &ihost->phys[index].sci; | |
384 | result = scic_sds_phy_frame_handler(phy, frame_index); | |
385 | } else { | |
386 | ||
387 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
388 | ||
389 | if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
390 | /* | |
391 | * This is a signature fis or a frame from a direct attached SATA | |
392 | * device that has not yet been created. In either case forwared | |
393 | * the frame to the PE and let it take care of the frame data. */ | |
394 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
395 | phy = &ihost->phys[index].sci; | |
396 | result = scic_sds_phy_frame_handler(phy, frame_index); | |
397 | } else { | |
398 | if (index < scic->remote_node_entries) | |
399 | device = scic->device_table[index]; | |
400 | else | |
401 | device = NULL; | |
402 | ||
403 | if (device != NULL) | |
404 | result = scic_sds_remote_device_frame_handler(device, frame_index); | |
405 | else | |
406 | scic_sds_controller_release_frame(scic, frame_index); | |
407 | } | |
408 | } | |
409 | ||
410 | if (result != SCI_SUCCESS) { | |
411 | /* | |
412 | * / @todo Is there any reason to report some additional error message | |
413 | * / when we get this failure notifiction? */ | |
414 | } | |
415 | } | |
416 | ||
417 | static void scic_sds_controller_event_completion(struct scic_sds_controller *scic, | |
418 | u32 completion_entry) | |
419 | { | |
420 | struct isci_host *ihost = scic_to_ihost(scic); | |
421 | struct scic_sds_request *io_request; | |
422 | struct scic_sds_remote_device *device; | |
423 | struct scic_sds_phy *phy; | |
424 | u32 index; | |
425 | ||
426 | index = SCU_GET_COMPLETION_INDEX(completion_entry); | |
427 | ||
428 | switch (scu_get_event_type(completion_entry)) { | |
429 | case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: | |
430 | /* / @todo The driver did something wrong and we need to fix the condtion. */ | |
431 | dev_err(scic_to_dev(scic), | |
432 | "%s: SCIC Controller 0x%p received SMU command error " | |
433 | "0x%x\n", | |
434 | __func__, | |
435 | scic, | |
436 | completion_entry); | |
437 | break; | |
438 | ||
439 | case SCU_EVENT_TYPE_SMU_PCQ_ERROR: | |
440 | case SCU_EVENT_TYPE_SMU_ERROR: | |
441 | case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR: | |
442 | /* | |
443 | * / @todo This is a hardware failure and its likely that we want to | |
444 | * / reset the controller. */ | |
445 | dev_err(scic_to_dev(scic), | |
446 | "%s: SCIC Controller 0x%p received fatal controller " | |
447 | "event 0x%x\n", | |
448 | __func__, | |
449 | scic, | |
450 | completion_entry); | |
451 | break; | |
452 | ||
453 | case SCU_EVENT_TYPE_TRANSPORT_ERROR: | |
454 | io_request = scic->io_request_table[index]; | |
455 | scic_sds_io_request_event_handler(io_request, completion_entry); | |
456 | break; | |
457 | ||
458 | case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT: | |
459 | switch (scu_get_event_specifier(completion_entry)) { | |
460 | case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE: | |
461 | case SCU_EVENT_SPECIFIC_TASK_TIMEOUT: | |
462 | io_request = scic->io_request_table[index]; | |
463 | if (io_request != NULL) | |
464 | scic_sds_io_request_event_handler(io_request, completion_entry); | |
465 | else | |
466 | dev_warn(scic_to_dev(scic), | |
467 | "%s: SCIC Controller 0x%p received " | |
468 | "event 0x%x for io request object " | |
469 | "that doesnt exist.\n", | |
470 | __func__, | |
471 | scic, | |
472 | completion_entry); | |
473 | ||
474 | break; | |
475 | ||
476 | case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: | |
477 | device = scic->device_table[index]; | |
478 | if (device != NULL) | |
479 | scic_sds_remote_device_event_handler(device, completion_entry); | |
480 | else | |
481 | dev_warn(scic_to_dev(scic), | |
482 | "%s: SCIC Controller 0x%p received " | |
483 | "event 0x%x for remote device object " | |
484 | "that doesnt exist.\n", | |
485 | __func__, | |
486 | scic, | |
487 | completion_entry); | |
488 | ||
489 | break; | |
490 | } | |
491 | break; | |
492 | ||
493 | case SCU_EVENT_TYPE_BROADCAST_CHANGE: | |
494 | /* | |
495 | * direct the broadcast change event to the phy first and then let | |
496 | * the phy redirect the broadcast change to the port object */ | |
497 | case SCU_EVENT_TYPE_ERR_CNT_EVENT: | |
498 | /* | |
499 | * direct error counter event to the phy object since that is where | |
500 | * we get the event notification. This is a type 4 event. */ | |
501 | case SCU_EVENT_TYPE_OSSP_EVENT: | |
502 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(completion_entry); | |
503 | phy = &ihost->phys[index].sci; | |
504 | scic_sds_phy_event_handler(phy, completion_entry); | |
505 | break; | |
506 | ||
507 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX: | |
508 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: | |
509 | case SCU_EVENT_TYPE_RNC_OPS_MISC: | |
510 | if (index < scic->remote_node_entries) { | |
511 | device = scic->device_table[index]; | |
512 | ||
513 | if (device != NULL) | |
514 | scic_sds_remote_device_event_handler(device, completion_entry); | |
515 | } else | |
516 | dev_err(scic_to_dev(scic), | |
517 | "%s: SCIC Controller 0x%p received event 0x%x " | |
518 | "for remote device object 0x%0x that doesnt " | |
519 | "exist.\n", | |
520 | __func__, | |
521 | scic, | |
522 | completion_entry, | |
523 | index); | |
524 | ||
525 | break; | |
526 | ||
527 | default: | |
528 | dev_warn(scic_to_dev(scic), | |
529 | "%s: SCIC Controller received unknown event code %x\n", | |
530 | __func__, | |
531 | completion_entry); | |
532 | break; | |
533 | } | |
534 | } | |
535 | ||
536 | ||
537 | ||
538 | static void scic_sds_controller_process_completions(struct scic_sds_controller *scic) | |
539 | { | |
540 | u32 completion_count = 0; | |
541 | u32 completion_entry; | |
542 | u32 get_index; | |
543 | u32 get_cycle; | |
544 | u32 event_index; | |
545 | u32 event_cycle; | |
546 | ||
547 | dev_dbg(scic_to_dev(scic), | |
548 | "%s: completion queue begining get:0x%08x\n", | |
549 | __func__, | |
550 | scic->completion_queue_get); | |
551 | ||
552 | /* Get the component parts of the completion queue */ | |
553 | get_index = NORMALIZE_GET_POINTER(scic->completion_queue_get); | |
554 | get_cycle = SMU_CQGR_CYCLE_BIT & scic->completion_queue_get; | |
555 | ||
556 | event_index = NORMALIZE_EVENT_POINTER(scic->completion_queue_get); | |
557 | event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & scic->completion_queue_get; | |
558 | ||
559 | while ( | |
560 | NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) | |
561 | == COMPLETION_QUEUE_CYCLE_BIT(scic->completion_queue[get_index]) | |
562 | ) { | |
563 | completion_count++; | |
564 | ||
565 | completion_entry = scic->completion_queue[get_index]; | |
566 | INCREMENT_COMPLETION_QUEUE_GET(scic, get_index, get_cycle); | |
567 | ||
568 | dev_dbg(scic_to_dev(scic), | |
569 | "%s: completion queue entry:0x%08x\n", | |
570 | __func__, | |
571 | completion_entry); | |
572 | ||
573 | switch (SCU_GET_COMPLETION_TYPE(completion_entry)) { | |
574 | case SCU_COMPLETION_TYPE_TASK: | |
575 | scic_sds_controller_task_completion(scic, completion_entry); | |
576 | break; | |
577 | ||
578 | case SCU_COMPLETION_TYPE_SDMA: | |
579 | scic_sds_controller_sdma_completion(scic, completion_entry); | |
580 | break; | |
581 | ||
582 | case SCU_COMPLETION_TYPE_UFI: | |
583 | scic_sds_controller_unsolicited_frame(scic, completion_entry); | |
584 | break; | |
585 | ||
586 | case SCU_COMPLETION_TYPE_EVENT: | |
587 | INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle); | |
588 | scic_sds_controller_event_completion(scic, completion_entry); | |
589 | break; | |
590 | ||
591 | case SCU_COMPLETION_TYPE_NOTIFY: | |
592 | /* | |
593 | * Presently we do the same thing with a notify event that we do with the | |
594 | * other event codes. */ | |
595 | INCREMENT_EVENT_QUEUE_GET(scic, event_index, event_cycle); | |
596 | scic_sds_controller_event_completion(scic, completion_entry); | |
597 | break; | |
598 | ||
599 | default: | |
600 | dev_warn(scic_to_dev(scic), | |
601 | "%s: SCIC Controller received unknown " | |
602 | "completion type %x\n", | |
603 | __func__, | |
604 | completion_entry); | |
605 | break; | |
606 | } | |
607 | } | |
608 | ||
609 | /* Update the get register if we completed one or more entries */ | |
610 | if (completion_count > 0) { | |
611 | scic->completion_queue_get = | |
612 | SMU_CQGR_GEN_BIT(ENABLE) | | |
613 | SMU_CQGR_GEN_BIT(EVENT_ENABLE) | | |
614 | event_cycle | | |
615 | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_index) | | |
616 | get_cycle | | |
617 | SMU_CQGR_GEN_VAL(POINTER, get_index); | |
618 | ||
619 | writel(scic->completion_queue_get, | |
620 | &scic->smu_registers->completion_queue_get); | |
621 | ||
622 | } | |
623 | ||
624 | dev_dbg(scic_to_dev(scic), | |
625 | "%s: completion queue ending get:0x%08x\n", | |
626 | __func__, | |
627 | scic->completion_queue_get); | |
628 | ||
629 | } | |
630 | ||
631 | static void scic_sds_controller_error_handler(struct scic_sds_controller *scic) | |
632 | { | |
633 | u32 interrupt_status; | |
634 | ||
635 | interrupt_status = | |
636 | readl(&scic->smu_registers->interrupt_status); | |
637 | ||
638 | if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && | |
639 | scic_sds_controller_completion_queue_has_entries(scic)) { | |
640 | ||
641 | scic_sds_controller_process_completions(scic); | |
642 | writel(SMU_ISR_QUEUE_SUSPEND, &scic->smu_registers->interrupt_status); | |
643 | } else { | |
644 | dev_err(scic_to_dev(scic), "%s: status: %#x\n", __func__, | |
645 | interrupt_status); | |
646 | ||
647 | sci_base_state_machine_change_state(&scic->state_machine, | |
648 | SCI_BASE_CONTROLLER_STATE_FAILED); | |
649 | ||
650 | return; | |
651 | } | |
652 | ||
653 | /* If we dont process any completions I am not sure that we want to do this. | |
654 | * We are in the middle of a hardware fault and should probably be reset. | |
655 | */ | |
656 | writel(0, &scic->smu_registers->interrupt_mask); | |
657 | } | |
658 | ||
c7ef4031 | 659 | irqreturn_t isci_intx_isr(int vec, void *data) |
6f231dda | 660 | { |
6f231dda | 661 | irqreturn_t ret = IRQ_NONE; |
31e824ed | 662 | struct isci_host *ihost = data; |
cc3dbd0a | 663 | struct scic_sds_controller *scic = &ihost->sci; |
c7ef4031 | 664 | |
31e824ed DW |
665 | if (scic_sds_controller_isr(scic)) { |
666 | writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); | |
667 | tasklet_schedule(&ihost->completion_tasklet); | |
668 | ret = IRQ_HANDLED; | |
669 | } else if (scic_sds_controller_error_isr(scic)) { | |
670 | spin_lock(&ihost->scic_lock); | |
671 | scic_sds_controller_error_handler(scic); | |
672 | spin_unlock(&ihost->scic_lock); | |
673 | ret = IRQ_HANDLED; | |
6f231dda | 674 | } |
92f4f0f5 | 675 | |
6f231dda DW |
676 | return ret; |
677 | } | |
678 | ||
92f4f0f5 DW |
679 | irqreturn_t isci_error_isr(int vec, void *data) |
680 | { | |
681 | struct isci_host *ihost = data; | |
92f4f0f5 | 682 | |
cc3dbd0a AW |
683 | if (scic_sds_controller_error_isr(&ihost->sci)) |
684 | scic_sds_controller_error_handler(&ihost->sci); | |
92f4f0f5 DW |
685 | |
686 | return IRQ_HANDLED; | |
687 | } | |
6f231dda DW |
688 | |
689 | /** | |
690 | * isci_host_start_complete() - This function is called by the core library, | |
691 | * through the ISCI Module, to indicate controller start status. | |
692 | * @isci_host: This parameter specifies the ISCI host object | |
693 | * @completion_status: This parameter specifies the completion status from the | |
694 | * core library. | |
695 | * | |
696 | */ | |
cc9203bf | 697 | static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status) |
6f231dda | 698 | { |
0cf89d1d DW |
699 | if (completion_status != SCI_SUCCESS) |
700 | dev_info(&ihost->pdev->dev, | |
701 | "controller start timed out, continuing...\n"); | |
702 | isci_host_change_state(ihost, isci_ready); | |
703 | clear_bit(IHOST_START_PENDING, &ihost->flags); | |
704 | wake_up(&ihost->eventq); | |
6f231dda DW |
705 | } |
706 | ||
c7ef4031 | 707 | int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time) |
6f231dda | 708 | { |
4393aa4e | 709 | struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; |
6f231dda | 710 | |
77950f51 | 711 | if (test_bit(IHOST_START_PENDING, &ihost->flags)) |
6f231dda | 712 | return 0; |
6f231dda | 713 | |
77950f51 EN |
714 | /* todo: use sas_flush_discovery once it is upstream */ |
715 | scsi_flush_work(shost); | |
716 | ||
717 | scsi_flush_work(shost); | |
6f231dda | 718 | |
0cf89d1d DW |
719 | dev_dbg(&ihost->pdev->dev, |
720 | "%s: ihost->status = %d, time = %ld\n", | |
721 | __func__, isci_host_get_state(ihost), time); | |
6f231dda | 722 | |
6f231dda DW |
723 | return 1; |
724 | ||
725 | } | |
726 | ||
cc9203bf DW |
727 | /** |
728 | * scic_controller_get_suggested_start_timeout() - This method returns the | |
729 | * suggested scic_controller_start() timeout amount. The user is free to | |
730 | * use any timeout value, but this method provides the suggested minimum | |
731 | * start timeout value. The returned value is based upon empirical | |
732 | * information determined as a result of interoperability testing. | |
733 | * @controller: the handle to the controller object for which to return the | |
734 | * suggested start timeout. | |
735 | * | |
736 | * This method returns the number of milliseconds for the suggested start | |
737 | * operation timeout. | |
738 | */ | |
739 | static u32 scic_controller_get_suggested_start_timeout( | |
740 | struct scic_sds_controller *sc) | |
741 | { | |
742 | /* Validate the user supplied parameters. */ | |
743 | if (sc == NULL) | |
744 | return 0; | |
745 | ||
746 | /* | |
747 | * The suggested minimum timeout value for a controller start operation: | |
748 | * | |
749 | * Signature FIS Timeout | |
750 | * + Phy Start Timeout | |
751 | * + Number of Phy Spin Up Intervals | |
752 | * --------------------------------- | |
753 | * Number of milliseconds for the controller start operation. | |
754 | * | |
755 | * NOTE: The number of phy spin up intervals will be equivalent | |
756 | * to the number of phys divided by the number phys allowed | |
757 | * per interval - 1 (once OEM parameters are supported). | |
758 | * Currently we assume only 1 phy per interval. */ | |
759 | ||
760 | return SCIC_SDS_SIGNATURE_FIS_TIMEOUT | |
761 | + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT | |
762 | + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); | |
763 | } | |
764 | ||
765 | static void scic_controller_enable_interrupts( | |
766 | struct scic_sds_controller *scic) | |
767 | { | |
768 | BUG_ON(scic->smu_registers == NULL); | |
769 | writel(0, &scic->smu_registers->interrupt_mask); | |
770 | } | |
771 | ||
772 | void scic_controller_disable_interrupts( | |
773 | struct scic_sds_controller *scic) | |
774 | { | |
775 | BUG_ON(scic->smu_registers == NULL); | |
776 | writel(0xffffffff, &scic->smu_registers->interrupt_mask); | |
777 | } | |
778 | ||
779 | static void scic_sds_controller_enable_port_task_scheduler( | |
780 | struct scic_sds_controller *scic) | |
781 | { | |
782 | u32 port_task_scheduler_value; | |
783 | ||
784 | port_task_scheduler_value = | |
785 | readl(&scic->scu_registers->peg0.ptsg.control); | |
786 | port_task_scheduler_value |= | |
787 | (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | | |
788 | SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); | |
789 | writel(port_task_scheduler_value, | |
790 | &scic->scu_registers->peg0.ptsg.control); | |
791 | } | |
792 | ||
793 | static void scic_sds_controller_assign_task_entries(struct scic_sds_controller *scic) | |
794 | { | |
795 | u32 task_assignment; | |
796 | ||
797 | /* | |
798 | * Assign all the TCs to function 0 | |
799 | * TODO: Do we actually need to read this register to write it back? | |
800 | */ | |
801 | ||
802 | task_assignment = | |
803 | readl(&scic->smu_registers->task_context_assignment[0]); | |
804 | ||
805 | task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | | |
806 | (SMU_TCA_GEN_VAL(ENDING, scic->task_context_entries - 1)) | | |
807 | (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); | |
808 | ||
809 | writel(task_assignment, | |
810 | &scic->smu_registers->task_context_assignment[0]); | |
811 | ||
812 | } | |
813 | ||
814 | static void scic_sds_controller_initialize_completion_queue(struct scic_sds_controller *scic) | |
815 | { | |
816 | u32 index; | |
817 | u32 completion_queue_control_value; | |
818 | u32 completion_queue_get_value; | |
819 | u32 completion_queue_put_value; | |
820 | ||
821 | scic->completion_queue_get = 0; | |
822 | ||
823 | completion_queue_control_value = ( | |
824 | SMU_CQC_QUEUE_LIMIT_SET(scic->completion_queue_entries - 1) | |
825 | | SMU_CQC_EVENT_LIMIT_SET(scic->completion_event_entries - 1) | |
826 | ); | |
827 | ||
828 | writel(completion_queue_control_value, | |
829 | &scic->smu_registers->completion_queue_control); | |
830 | ||
831 | ||
832 | /* Set the completion queue get pointer and enable the queue */ | |
833 | completion_queue_get_value = ( | |
834 | (SMU_CQGR_GEN_VAL(POINTER, 0)) | |
835 | | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) | |
836 | | (SMU_CQGR_GEN_BIT(ENABLE)) | |
837 | | (SMU_CQGR_GEN_BIT(EVENT_ENABLE)) | |
838 | ); | |
839 | ||
840 | writel(completion_queue_get_value, | |
841 | &scic->smu_registers->completion_queue_get); | |
842 | ||
843 | /* Set the completion queue put pointer */ | |
844 | completion_queue_put_value = ( | |
845 | (SMU_CQPR_GEN_VAL(POINTER, 0)) | |
846 | | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) | |
847 | ); | |
848 | ||
849 | writel(completion_queue_put_value, | |
850 | &scic->smu_registers->completion_queue_put); | |
851 | ||
852 | /* Initialize the cycle bit of the completion queue entries */ | |
853 | for (index = 0; index < scic->completion_queue_entries; index++) { | |
854 | /* | |
855 | * If get.cycle_bit != completion_queue.cycle_bit | |
856 | * its not a valid completion queue entry | |
857 | * so at system start all entries are invalid */ | |
858 | scic->completion_queue[index] = 0x80000000; | |
859 | } | |
860 | } | |
861 | ||
862 | static void scic_sds_controller_initialize_unsolicited_frame_queue(struct scic_sds_controller *scic) | |
863 | { | |
864 | u32 frame_queue_control_value; | |
865 | u32 frame_queue_get_value; | |
866 | u32 frame_queue_put_value; | |
867 | ||
868 | /* Write the queue size */ | |
869 | frame_queue_control_value = | |
870 | SCU_UFQC_GEN_VAL(QUEUE_SIZE, | |
871 | scic->uf_control.address_table.count); | |
872 | ||
873 | writel(frame_queue_control_value, | |
874 | &scic->scu_registers->sdma.unsolicited_frame_queue_control); | |
875 | ||
876 | /* Setup the get pointer for the unsolicited frame queue */ | |
877 | frame_queue_get_value = ( | |
878 | SCU_UFQGP_GEN_VAL(POINTER, 0) | |
879 | | SCU_UFQGP_GEN_BIT(ENABLE_BIT) | |
880 | ); | |
881 | ||
882 | writel(frame_queue_get_value, | |
883 | &scic->scu_registers->sdma.unsolicited_frame_get_pointer); | |
884 | /* Setup the put pointer for the unsolicited frame queue */ | |
885 | frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); | |
886 | writel(frame_queue_put_value, | |
887 | &scic->scu_registers->sdma.unsolicited_frame_put_pointer); | |
888 | } | |
889 | ||
890 | /** | |
891 | * This method will attempt to transition into the ready state for the | |
892 | * controller and indicate that the controller start operation has completed | |
893 | * if all criteria are met. | |
894 | * @scic: This parameter indicates the controller object for which | |
895 | * to transition to ready. | |
896 | * @status: This parameter indicates the status value to be pass into the call | |
897 | * to scic_cb_controller_start_complete(). | |
898 | * | |
899 | * none. | |
900 | */ | |
901 | static void scic_sds_controller_transition_to_ready( | |
902 | struct scic_sds_controller *scic, | |
903 | enum sci_status status) | |
904 | { | |
905 | struct isci_host *ihost = scic_to_ihost(scic); | |
906 | ||
907 | if (scic->state_machine.current_state_id == | |
908 | SCI_BASE_CONTROLLER_STATE_STARTING) { | |
909 | /* | |
910 | * We move into the ready state, because some of the phys/ports | |
911 | * may be up and operational. | |
912 | */ | |
913 | sci_base_state_machine_change_state(&scic->state_machine, | |
914 | SCI_BASE_CONTROLLER_STATE_READY); | |
915 | ||
916 | isci_host_start_complete(ihost, status); | |
917 | } | |
918 | } | |
919 | ||
920 | static void scic_sds_controller_phy_timer_stop(struct scic_sds_controller *scic) | |
921 | { | |
922 | isci_timer_stop(scic->phy_startup_timer); | |
923 | ||
924 | scic->phy_startup_timer_pending = false; | |
925 | } | |
926 | ||
927 | static void scic_sds_controller_phy_timer_start(struct scic_sds_controller *scic) | |
928 | { | |
929 | isci_timer_start(scic->phy_startup_timer, | |
930 | SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); | |
931 | ||
932 | scic->phy_startup_timer_pending = true; | |
933 | } | |
934 | ||
4a33c525 AG |
935 | static bool is_phy_starting(struct scic_sds_phy *sci_phy) |
936 | { | |
937 | enum scic_sds_phy_states state; | |
938 | ||
939 | state = sci_phy->state_machine.current_state_id; | |
940 | switch (state) { | |
941 | case SCI_BASE_PHY_STATE_STARTING: | |
942 | case SCIC_SDS_PHY_STARTING_SUBSTATE_INITIAL: | |
943 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_SPEED_EN: | |
944 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_IAF_UF: | |
945 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SAS_POWER: | |
946 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_POWER: | |
947 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_PHY_EN: | |
948 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SATA_SPEED_EN: | |
949 | case SCIC_SDS_PHY_STARTING_SUBSTATE_AWAIT_SIG_FIS_UF: | |
950 | case SCIC_SDS_PHY_STARTING_SUBSTATE_FINAL: | |
951 | return true; | |
952 | default: | |
953 | return false; | |
954 | } | |
955 | } | |
956 | ||
cc9203bf DW |
957 | /** |
958 | * scic_sds_controller_start_next_phy - start phy | |
959 | * @scic: controller | |
960 | * | |
961 | * If all the phys have been started, then attempt to transition the | |
962 | * controller to the READY state and inform the user | |
963 | * (scic_cb_controller_start_complete()). | |
964 | */ | |
965 | static enum sci_status scic_sds_controller_start_next_phy(struct scic_sds_controller *scic) | |
966 | { | |
967 | struct isci_host *ihost = scic_to_ihost(scic); | |
968 | struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; | |
969 | struct scic_sds_phy *sci_phy; | |
970 | enum sci_status status; | |
971 | ||
972 | status = SCI_SUCCESS; | |
973 | ||
974 | if (scic->phy_startup_timer_pending) | |
975 | return status; | |
976 | ||
977 | if (scic->next_phy_to_start >= SCI_MAX_PHYS) { | |
978 | bool is_controller_start_complete = true; | |
979 | u32 state; | |
980 | u8 index; | |
981 | ||
982 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
983 | sci_phy = &ihost->phys[index].sci; | |
984 | state = sci_phy->state_machine.current_state_id; | |
985 | ||
4f20ef4f | 986 | if (!phy_get_non_dummy_port(sci_phy)) |
cc9203bf DW |
987 | continue; |
988 | ||
989 | /* The controller start operation is complete iff: | |
990 | * - all links have been given an opportunity to start | |
991 | * - have no indication of a connected device | |
992 | * - have an indication of a connected device and it has | |
993 | * finished the link training process. | |
994 | */ | |
995 | if ((sci_phy->is_in_link_training == false && | |
996 | state == SCI_BASE_PHY_STATE_INITIAL) || | |
997 | (sci_phy->is_in_link_training == false && | |
998 | state == SCI_BASE_PHY_STATE_STOPPED) || | |
999 | (sci_phy->is_in_link_training == true && | |
4a33c525 | 1000 | is_phy_starting(sci_phy))) { |
cc9203bf DW |
1001 | is_controller_start_complete = false; |
1002 | break; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | /* | |
1007 | * The controller has successfully finished the start process. | |
1008 | * Inform the SCI Core user and transition to the READY state. */ | |
1009 | if (is_controller_start_complete == true) { | |
1010 | scic_sds_controller_transition_to_ready(scic, SCI_SUCCESS); | |
1011 | scic_sds_controller_phy_timer_stop(scic); | |
1012 | } | |
1013 | } else { | |
1014 | sci_phy = &ihost->phys[scic->next_phy_to_start].sci; | |
1015 | ||
1016 | if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
4f20ef4f | 1017 | if (phy_get_non_dummy_port(sci_phy) == NULL) { |
cc9203bf DW |
1018 | scic->next_phy_to_start++; |
1019 | ||
1020 | /* Caution recursion ahead be forwarned | |
1021 | * | |
1022 | * The PHY was never added to a PORT in MPC mode | |
1023 | * so start the next phy in sequence This phy | |
1024 | * will never go link up and will not draw power | |
1025 | * the OEM parameters either configured the phy | |
1026 | * incorrectly for the PORT or it was never | |
1027 | * assigned to a PORT | |
1028 | */ | |
1029 | return scic_sds_controller_start_next_phy(scic); | |
1030 | } | |
1031 | } | |
1032 | ||
1033 | status = scic_sds_phy_start(sci_phy); | |
1034 | ||
1035 | if (status == SCI_SUCCESS) { | |
1036 | scic_sds_controller_phy_timer_start(scic); | |
1037 | } else { | |
1038 | dev_warn(scic_to_dev(scic), | |
1039 | "%s: Controller stop operation failed " | |
1040 | "to stop phy %d because of status " | |
1041 | "%d.\n", | |
1042 | __func__, | |
1043 | ihost->phys[scic->next_phy_to_start].sci.phy_index, | |
1044 | status); | |
1045 | } | |
1046 | ||
1047 | scic->next_phy_to_start++; | |
1048 | } | |
1049 | ||
1050 | return status; | |
1051 | } | |
1052 | ||
1053 | static void scic_sds_controller_phy_startup_timeout_handler(void *_scic) | |
1054 | { | |
1055 | struct scic_sds_controller *scic = _scic; | |
1056 | enum sci_status status; | |
1057 | ||
1058 | scic->phy_startup_timer_pending = false; | |
1059 | status = SCI_FAILURE; | |
1060 | while (status != SCI_SUCCESS) | |
1061 | status = scic_sds_controller_start_next_phy(scic); | |
1062 | } | |
1063 | ||
1064 | static enum sci_status scic_controller_start(struct scic_sds_controller *scic, | |
1065 | u32 timeout) | |
1066 | { | |
1067 | struct isci_host *ihost = scic_to_ihost(scic); | |
1068 | enum sci_status result; | |
1069 | u16 index; | |
1070 | ||
1071 | if (scic->state_machine.current_state_id != | |
1072 | SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
1073 | dev_warn(scic_to_dev(scic), | |
1074 | "SCIC Controller start operation requested in " | |
1075 | "invalid state\n"); | |
1076 | return SCI_FAILURE_INVALID_STATE; | |
1077 | } | |
1078 | ||
1079 | /* Build the TCi free pool */ | |
1080 | sci_pool_initialize(scic->tci_pool); | |
1081 | for (index = 0; index < scic->task_context_entries; index++) | |
1082 | sci_pool_put(scic->tci_pool, index); | |
1083 | ||
1084 | /* Build the RNi free pool */ | |
1085 | scic_sds_remote_node_table_initialize( | |
1086 | &scic->available_remote_nodes, | |
1087 | scic->remote_node_entries); | |
1088 | ||
1089 | /* | |
1090 | * Before anything else lets make sure we will not be | |
1091 | * interrupted by the hardware. | |
1092 | */ | |
1093 | scic_controller_disable_interrupts(scic); | |
1094 | ||
1095 | /* Enable the port task scheduler */ | |
1096 | scic_sds_controller_enable_port_task_scheduler(scic); | |
1097 | ||
1098 | /* Assign all the task entries to scic physical function */ | |
1099 | scic_sds_controller_assign_task_entries(scic); | |
1100 | ||
1101 | /* Now initialize the completion queue */ | |
1102 | scic_sds_controller_initialize_completion_queue(scic); | |
1103 | ||
1104 | /* Initialize the unsolicited frame queue for use */ | |
1105 | scic_sds_controller_initialize_unsolicited_frame_queue(scic); | |
1106 | ||
1107 | /* Start all of the ports on this controller */ | |
1108 | for (index = 0; index < scic->logical_port_entries; index++) { | |
1109 | struct scic_sds_port *sci_port = &ihost->ports[index].sci; | |
1110 | ||
d76f71d9 | 1111 | result = scic_sds_port_start(sci_port); |
cc9203bf DW |
1112 | if (result) |
1113 | return result; | |
1114 | } | |
1115 | ||
1116 | scic_sds_controller_start_next_phy(scic); | |
1117 | ||
1118 | isci_timer_start(scic->timeout_timer, timeout); | |
1119 | ||
1120 | sci_base_state_machine_change_state(&scic->state_machine, | |
1121 | SCI_BASE_CONTROLLER_STATE_STARTING); | |
1122 | ||
1123 | return SCI_SUCCESS; | |
1124 | } | |
1125 | ||
6f231dda DW |
1126 | void isci_host_scan_start(struct Scsi_Host *shost) |
1127 | { | |
4393aa4e | 1128 | struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; |
cc3dbd0a | 1129 | unsigned long tmo = scic_controller_get_suggested_start_timeout(&ihost->sci); |
6f231dda | 1130 | |
0cf89d1d | 1131 | set_bit(IHOST_START_PENDING, &ihost->flags); |
77950f51 EN |
1132 | |
1133 | spin_lock_irq(&ihost->scic_lock); | |
cc3dbd0a AW |
1134 | scic_controller_start(&ihost->sci, tmo); |
1135 | scic_controller_enable_interrupts(&ihost->sci); | |
77950f51 | 1136 | spin_unlock_irq(&ihost->scic_lock); |
6f231dda DW |
1137 | } |
1138 | ||
cc9203bf | 1139 | static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status) |
6f231dda | 1140 | { |
0cf89d1d | 1141 | isci_host_change_state(ihost, isci_stopped); |
cc3dbd0a | 1142 | scic_controller_disable_interrupts(&ihost->sci); |
0cf89d1d DW |
1143 | clear_bit(IHOST_STOP_PENDING, &ihost->flags); |
1144 | wake_up(&ihost->eventq); | |
6f231dda DW |
1145 | } |
1146 | ||
cc9203bf DW |
1147 | static void scic_sds_controller_completion_handler(struct scic_sds_controller *scic) |
1148 | { | |
1149 | /* Empty out the completion queue */ | |
1150 | if (scic_sds_controller_completion_queue_has_entries(scic)) | |
1151 | scic_sds_controller_process_completions(scic); | |
1152 | ||
1153 | /* Clear the interrupt and enable all interrupts again */ | |
1154 | writel(SMU_ISR_COMPLETION, &scic->smu_registers->interrupt_status); | |
1155 | /* Could we write the value of SMU_ISR_COMPLETION? */ | |
1156 | writel(0xFF000000, &scic->smu_registers->interrupt_mask); | |
1157 | writel(0, &scic->smu_registers->interrupt_mask); | |
1158 | } | |
1159 | ||
6f231dda DW |
1160 | /** |
1161 | * isci_host_completion_routine() - This function is the delayed service | |
1162 | * routine that calls the sci core library's completion handler. It's | |
1163 | * scheduled as a tasklet from the interrupt service routine when interrupts | |
1164 | * in use, or set as the timeout function in polled mode. | |
1165 | * @data: This parameter specifies the ISCI host object | |
1166 | * | |
1167 | */ | |
1168 | static void isci_host_completion_routine(unsigned long data) | |
1169 | { | |
1170 | struct isci_host *isci_host = (struct isci_host *)data; | |
11b00c19 JS |
1171 | struct list_head completed_request_list; |
1172 | struct list_head errored_request_list; | |
1173 | struct list_head *current_position; | |
1174 | struct list_head *next_position; | |
6f231dda DW |
1175 | struct isci_request *request; |
1176 | struct isci_request *next_request; | |
11b00c19 | 1177 | struct sas_task *task; |
6f231dda DW |
1178 | |
1179 | INIT_LIST_HEAD(&completed_request_list); | |
11b00c19 | 1180 | INIT_LIST_HEAD(&errored_request_list); |
6f231dda DW |
1181 | |
1182 | spin_lock_irq(&isci_host->scic_lock); | |
1183 | ||
cc3dbd0a | 1184 | scic_sds_controller_completion_handler(&isci_host->sci); |
c7ef4031 | 1185 | |
6f231dda | 1186 | /* Take the lists of completed I/Os from the host. */ |
11b00c19 | 1187 | |
6f231dda DW |
1188 | list_splice_init(&isci_host->requests_to_complete, |
1189 | &completed_request_list); | |
1190 | ||
11b00c19 JS |
1191 | /* Take the list of errored I/Os from the host. */ |
1192 | list_splice_init(&isci_host->requests_to_errorback, | |
1193 | &errored_request_list); | |
6f231dda DW |
1194 | |
1195 | spin_unlock_irq(&isci_host->scic_lock); | |
1196 | ||
1197 | /* Process any completions in the lists. */ | |
1198 | list_for_each_safe(current_position, next_position, | |
1199 | &completed_request_list) { | |
1200 | ||
1201 | request = list_entry(current_position, struct isci_request, | |
1202 | completed_node); | |
1203 | task = isci_request_access_task(request); | |
1204 | ||
1205 | /* Normal notification (task_done) */ | |
1206 | dev_dbg(&isci_host->pdev->dev, | |
1207 | "%s: Normal - request/task = %p/%p\n", | |
1208 | __func__, | |
1209 | request, | |
1210 | task); | |
1211 | ||
11b00c19 JS |
1212 | /* Return the task to libsas */ |
1213 | if (task != NULL) { | |
1214 | ||
1215 | task->lldd_task = NULL; | |
1216 | if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) { | |
6f231dda | 1217 | |
11b00c19 JS |
1218 | /* If the task is already in the abort path, |
1219 | * the task_done callback cannot be called. | |
1220 | */ | |
1221 | task->task_done(task); | |
1222 | } | |
1223 | } | |
6f231dda DW |
1224 | /* Free the request object. */ |
1225 | isci_request_free(isci_host, request); | |
1226 | } | |
11b00c19 | 1227 | list_for_each_entry_safe(request, next_request, &errored_request_list, |
6f231dda DW |
1228 | completed_node) { |
1229 | ||
1230 | task = isci_request_access_task(request); | |
1231 | ||
1232 | /* Use sas_task_abort */ | |
1233 | dev_warn(&isci_host->pdev->dev, | |
1234 | "%s: Error - request/task = %p/%p\n", | |
1235 | __func__, | |
1236 | request, | |
1237 | task); | |
1238 | ||
11b00c19 JS |
1239 | if (task != NULL) { |
1240 | ||
1241 | /* Put the task into the abort path if it's not there | |
1242 | * already. | |
1243 | */ | |
1244 | if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) | |
1245 | sas_task_abort(task); | |
1246 | ||
1247 | } else { | |
1248 | /* This is a case where the request has completed with a | |
1249 | * status such that it needed further target servicing, | |
1250 | * but the sas_task reference has already been removed | |
1251 | * from the request. Since it was errored, it was not | |
1252 | * being aborted, so there is nothing to do except free | |
1253 | * it. | |
1254 | */ | |
1255 | ||
1256 | spin_lock_irq(&isci_host->scic_lock); | |
1257 | /* Remove the request from the remote device's list | |
1258 | * of pending requests. | |
1259 | */ | |
1260 | list_del_init(&request->dev_node); | |
1261 | spin_unlock_irq(&isci_host->scic_lock); | |
1262 | ||
1263 | /* Free the request object. */ | |
1264 | isci_request_free(isci_host, request); | |
1265 | } | |
6f231dda DW |
1266 | } |
1267 | ||
1268 | } | |
1269 | ||
cc9203bf DW |
1270 | /** |
1271 | * scic_controller_stop() - This method will stop an individual controller | |
1272 | * object.This method will invoke the associated user callback upon | |
1273 | * completion. The completion callback is called when the following | |
1274 | * conditions are met: -# the method return status is SCI_SUCCESS. -# the | |
1275 | * controller has been quiesced. This method will ensure that all IO | |
1276 | * requests are quiesced, phys are stopped, and all additional operation by | |
1277 | * the hardware is halted. | |
1278 | * @controller: the handle to the controller object to stop. | |
1279 | * @timeout: This parameter specifies the number of milliseconds in which the | |
1280 | * stop operation should complete. | |
1281 | * | |
1282 | * The controller must be in the STARTED or STOPPED state. Indicate if the | |
1283 | * controller stop method succeeded or failed in some way. SCI_SUCCESS if the | |
1284 | * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the | |
1285 | * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the | |
1286 | * controller is not either in the STARTED or STOPPED states. | |
1287 | */ | |
1288 | static enum sci_status scic_controller_stop(struct scic_sds_controller *scic, | |
1289 | u32 timeout) | |
6f231dda | 1290 | { |
cc9203bf DW |
1291 | if (scic->state_machine.current_state_id != |
1292 | SCI_BASE_CONTROLLER_STATE_READY) { | |
1293 | dev_warn(scic_to_dev(scic), | |
1294 | "SCIC Controller stop operation requested in " | |
1295 | "invalid state\n"); | |
1296 | return SCI_FAILURE_INVALID_STATE; | |
1297 | } | |
6f231dda | 1298 | |
cc9203bf DW |
1299 | isci_timer_start(scic->timeout_timer, timeout); |
1300 | sci_base_state_machine_change_state(&scic->state_machine, | |
1301 | SCI_BASE_CONTROLLER_STATE_STOPPING); | |
1302 | return SCI_SUCCESS; | |
1303 | } | |
1304 | ||
1305 | /** | |
1306 | * scic_controller_reset() - This method will reset the supplied core | |
1307 | * controller regardless of the state of said controller. This operation is | |
1308 | * considered destructive. In other words, all current operations are wiped | |
1309 | * out. No IO completions for outstanding devices occur. Outstanding IO | |
1310 | * requests are not aborted or completed at the actual remote device. | |
1311 | * @controller: the handle to the controller object to reset. | |
1312 | * | |
1313 | * Indicate if the controller reset method succeeded or failed in some way. | |
1314 | * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if | |
1315 | * the controller reset operation is unable to complete. | |
1316 | */ | |
1317 | static enum sci_status scic_controller_reset(struct scic_sds_controller *scic) | |
1318 | { | |
1319 | switch (scic->state_machine.current_state_id) { | |
1320 | case SCI_BASE_CONTROLLER_STATE_RESET: | |
1321 | case SCI_BASE_CONTROLLER_STATE_READY: | |
1322 | case SCI_BASE_CONTROLLER_STATE_STOPPED: | |
1323 | case SCI_BASE_CONTROLLER_STATE_FAILED: | |
1324 | /* | |
1325 | * The reset operation is not a graceful cleanup, just | |
1326 | * perform the state transition. | |
1327 | */ | |
1328 | sci_base_state_machine_change_state(&scic->state_machine, | |
1329 | SCI_BASE_CONTROLLER_STATE_RESETTING); | |
1330 | return SCI_SUCCESS; | |
1331 | default: | |
1332 | dev_warn(scic_to_dev(scic), | |
1333 | "SCIC Controller reset operation requested in " | |
1334 | "invalid state\n"); | |
1335 | return SCI_FAILURE_INVALID_STATE; | |
1336 | } | |
1337 | } | |
1338 | ||
1339 | void isci_host_deinit(struct isci_host *ihost) | |
1340 | { | |
1341 | int i; | |
1342 | ||
1343 | isci_host_change_state(ihost, isci_stopping); | |
6f231dda | 1344 | for (i = 0; i < SCI_MAX_PORTS; i++) { |
e531381e | 1345 | struct isci_port *iport = &ihost->ports[i]; |
0cf89d1d DW |
1346 | struct isci_remote_device *idev, *d; |
1347 | ||
e531381e | 1348 | list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) { |
0cf89d1d | 1349 | isci_remote_device_change_state(idev, isci_stopping); |
6ad31fec | 1350 | isci_remote_device_stop(ihost, idev); |
6f231dda DW |
1351 | } |
1352 | } | |
1353 | ||
0cf89d1d | 1354 | set_bit(IHOST_STOP_PENDING, &ihost->flags); |
7c40a803 DW |
1355 | |
1356 | spin_lock_irq(&ihost->scic_lock); | |
cc3dbd0a | 1357 | scic_controller_stop(&ihost->sci, SCIC_CONTROLLER_STOP_TIMEOUT); |
7c40a803 DW |
1358 | spin_unlock_irq(&ihost->scic_lock); |
1359 | ||
0cf89d1d | 1360 | wait_for_stop(ihost); |
cc3dbd0a | 1361 | scic_controller_reset(&ihost->sci); |
5553ba2b EN |
1362 | |
1363 | /* Cancel any/all outstanding port timers */ | |
1364 | for (i = 0; i < ihost->sci.logical_port_entries; i++) { | |
1365 | struct scic_sds_port *sci_port = &ihost->ports[i].sci; | |
1366 | del_timer_sync(&sci_port->timer.timer); | |
1367 | } | |
1368 | ||
7c40a803 | 1369 | isci_timer_list_destroy(ihost); |
6f231dda DW |
1370 | } |
1371 | ||
6f231dda DW |
1372 | static void __iomem *scu_base(struct isci_host *isci_host) |
1373 | { | |
1374 | struct pci_dev *pdev = isci_host->pdev; | |
1375 | int id = isci_host->id; | |
1376 | ||
1377 | return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id; | |
1378 | } | |
1379 | ||
1380 | static void __iomem *smu_base(struct isci_host *isci_host) | |
1381 | { | |
1382 | struct pci_dev *pdev = isci_host->pdev; | |
1383 | int id = isci_host->id; | |
1384 | ||
1385 | return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id; | |
1386 | } | |
1387 | ||
b5f18a20 DJ |
1388 | static void isci_user_parameters_get( |
1389 | struct isci_host *isci_host, | |
1390 | union scic_user_parameters *scic_user_params) | |
1391 | { | |
1392 | struct scic_sds_user_parameters *u = &scic_user_params->sds1; | |
1393 | int i; | |
1394 | ||
1395 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
1396 | struct sci_phy_user_params *u_phy = &u->phys[i]; | |
1397 | ||
1398 | u_phy->max_speed_generation = phy_gen; | |
1399 | ||
1400 | /* we are not exporting these for now */ | |
1401 | u_phy->align_insertion_frequency = 0x7f; | |
1402 | u_phy->in_connection_align_insertion_frequency = 0xff; | |
1403 | u_phy->notify_enable_spin_up_insertion_frequency = 0x33; | |
1404 | } | |
1405 | ||
1406 | u->stp_inactivity_timeout = stp_inactive_to; | |
1407 | u->ssp_inactivity_timeout = ssp_inactive_to; | |
1408 | u->stp_max_occupancy_timeout = stp_max_occ_to; | |
1409 | u->ssp_max_occupancy_timeout = ssp_max_occ_to; | |
1410 | u->no_outbound_task_timeout = no_outbound_task_to; | |
1411 | u->max_number_concurrent_device_spin_up = max_concurr_spinup; | |
1412 | } | |
1413 | ||
9269e0e8 | 1414 | static void scic_sds_controller_initial_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1415 | { |
9269e0e8 | 1416 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1417 | |
1418 | sci_base_state_machine_change_state(&scic->state_machine, | |
1419 | SCI_BASE_CONTROLLER_STATE_RESET); | |
1420 | } | |
1421 | ||
9269e0e8 | 1422 | static inline void scic_sds_controller_starting_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1423 | { |
9269e0e8 | 1424 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1425 | |
1426 | isci_timer_stop(scic->timeout_timer); | |
1427 | } | |
1428 | ||
1429 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 | |
1430 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280 | |
1431 | #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000 | |
1432 | #define INTERRUPT_COALESCE_NUMBER_MAX 256 | |
1433 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7 | |
1434 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28 | |
1435 | ||
1436 | /** | |
1437 | * scic_controller_set_interrupt_coalescence() - This method allows the user to | |
1438 | * configure the interrupt coalescence. | |
1439 | * @controller: This parameter represents the handle to the controller object | |
1440 | * for which its interrupt coalesce register is overridden. | |
1441 | * @coalesce_number: Used to control the number of entries in the Completion | |
1442 | * Queue before an interrupt is generated. If the number of entries exceed | |
1443 | * this number, an interrupt will be generated. The valid range of the input | |
1444 | * is [0, 256]. A setting of 0 results in coalescing being disabled. | |
1445 | * @coalesce_timeout: Timeout value in microseconds. The valid range of the | |
1446 | * input is [0, 2700000] . A setting of 0 is allowed and results in no | |
1447 | * interrupt coalescing timeout. | |
1448 | * | |
1449 | * Indicate if the user successfully set the interrupt coalesce parameters. | |
1450 | * SCI_SUCCESS The user successfully updated the interrutp coalescence. | |
1451 | * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. | |
1452 | */ | |
1453 | static enum sci_status scic_controller_set_interrupt_coalescence( | |
1454 | struct scic_sds_controller *scic_controller, | |
1455 | u32 coalesce_number, | |
1456 | u32 coalesce_timeout) | |
1457 | { | |
1458 | u8 timeout_encode = 0; | |
1459 | u32 min = 0; | |
1460 | u32 max = 0; | |
1461 | ||
1462 | /* Check if the input parameters fall in the range. */ | |
1463 | if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX) | |
1464 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
1465 | ||
1466 | /* | |
1467 | * Defined encoding for interrupt coalescing timeout: | |
1468 | * Value Min Max Units | |
1469 | * ----- --- --- ----- | |
1470 | * 0 - - Disabled | |
1471 | * 1 13.3 20.0 ns | |
1472 | * 2 26.7 40.0 | |
1473 | * 3 53.3 80.0 | |
1474 | * 4 106.7 160.0 | |
1475 | * 5 213.3 320.0 | |
1476 | * 6 426.7 640.0 | |
1477 | * 7 853.3 1280.0 | |
1478 | * 8 1.7 2.6 us | |
1479 | * 9 3.4 5.1 | |
1480 | * 10 6.8 10.2 | |
1481 | * 11 13.7 20.5 | |
1482 | * 12 27.3 41.0 | |
1483 | * 13 54.6 81.9 | |
1484 | * 14 109.2 163.8 | |
1485 | * 15 218.5 327.7 | |
1486 | * 16 436.9 655.4 | |
1487 | * 17 873.8 1310.7 | |
1488 | * 18 1.7 2.6 ms | |
1489 | * 19 3.5 5.2 | |
1490 | * 20 7.0 10.5 | |
1491 | * 21 14.0 21.0 | |
1492 | * 22 28.0 41.9 | |
1493 | * 23 55.9 83.9 | |
1494 | * 24 111.8 167.8 | |
1495 | * 25 223.7 335.5 | |
1496 | * 26 447.4 671.1 | |
1497 | * 27 894.8 1342.2 | |
1498 | * 28 1.8 2.7 s | |
1499 | * Others Undefined */ | |
1500 | ||
1501 | /* | |
1502 | * Use the table above to decide the encode of interrupt coalescing timeout | |
1503 | * value for register writing. */ | |
1504 | if (coalesce_timeout == 0) | |
1505 | timeout_encode = 0; | |
1506 | else{ | |
1507 | /* make the timeout value in unit of (10 ns). */ | |
1508 | coalesce_timeout = coalesce_timeout * 100; | |
1509 | min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10; | |
1510 | max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10; | |
1511 | ||
1512 | /* get the encode of timeout for register writing. */ | |
1513 | for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN; | |
1514 | timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX; | |
1515 | timeout_encode++) { | |
1516 | if (min <= coalesce_timeout && max > coalesce_timeout) | |
1517 | break; | |
1518 | else if (coalesce_timeout >= max && coalesce_timeout < min * 2 | |
1519 | && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) { | |
1520 | if ((coalesce_timeout - max) < (2 * min - coalesce_timeout)) | |
1521 | break; | |
1522 | else{ | |
1523 | timeout_encode++; | |
1524 | break; | |
1525 | } | |
1526 | } else { | |
1527 | max = max * 2; | |
1528 | min = min * 2; | |
1529 | } | |
1530 | } | |
1531 | ||
1532 | if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1) | |
1533 | /* the value is out of range. */ | |
1534 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
1535 | } | |
1536 | ||
1537 | writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | | |
1538 | SMU_ICC_GEN_VAL(TIMER, timeout_encode), | |
1539 | &scic_controller->smu_registers->interrupt_coalesce_control); | |
1540 | ||
1541 | ||
1542 | scic_controller->interrupt_coalesce_number = (u16)coalesce_number; | |
1543 | scic_controller->interrupt_coalesce_timeout = coalesce_timeout / 100; | |
1544 | ||
1545 | return SCI_SUCCESS; | |
1546 | } | |
1547 | ||
1548 | ||
9269e0e8 | 1549 | static void scic_sds_controller_ready_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1550 | { |
9269e0e8 | 1551 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1552 | |
1553 | /* set the default interrupt coalescence number and timeout value. */ | |
1554 | scic_controller_set_interrupt_coalescence(scic, 0x10, 250); | |
1555 | } | |
1556 | ||
9269e0e8 | 1557 | static void scic_sds_controller_ready_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1558 | { |
9269e0e8 | 1559 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1560 | |
1561 | /* disable interrupt coalescence. */ | |
1562 | scic_controller_set_interrupt_coalescence(scic, 0, 0); | |
1563 | } | |
1564 | ||
1565 | static enum sci_status scic_sds_controller_stop_phys(struct scic_sds_controller *scic) | |
1566 | { | |
1567 | u32 index; | |
1568 | enum sci_status status; | |
1569 | enum sci_status phy_status; | |
1570 | struct isci_host *ihost = scic_to_ihost(scic); | |
1571 | ||
1572 | status = SCI_SUCCESS; | |
1573 | ||
1574 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
1575 | phy_status = scic_sds_phy_stop(&ihost->phys[index].sci); | |
1576 | ||
1577 | if (phy_status != SCI_SUCCESS && | |
1578 | phy_status != SCI_FAILURE_INVALID_STATE) { | |
1579 | status = SCI_FAILURE; | |
1580 | ||
1581 | dev_warn(scic_to_dev(scic), | |
1582 | "%s: Controller stop operation failed to stop " | |
1583 | "phy %d because of status %d.\n", | |
1584 | __func__, | |
1585 | ihost->phys[index].sci.phy_index, phy_status); | |
1586 | } | |
1587 | } | |
1588 | ||
1589 | return status; | |
1590 | } | |
1591 | ||
1592 | static enum sci_status scic_sds_controller_stop_ports(struct scic_sds_controller *scic) | |
1593 | { | |
1594 | u32 index; | |
1595 | enum sci_status port_status; | |
1596 | enum sci_status status = SCI_SUCCESS; | |
1597 | struct isci_host *ihost = scic_to_ihost(scic); | |
1598 | ||
1599 | for (index = 0; index < scic->logical_port_entries; index++) { | |
1600 | struct scic_sds_port *sci_port = &ihost->ports[index].sci; | |
cc9203bf | 1601 | |
8bc80d30 | 1602 | port_status = scic_sds_port_stop(sci_port); |
cc9203bf DW |
1603 | |
1604 | if ((port_status != SCI_SUCCESS) && | |
1605 | (port_status != SCI_FAILURE_INVALID_STATE)) { | |
1606 | status = SCI_FAILURE; | |
1607 | ||
1608 | dev_warn(scic_to_dev(scic), | |
1609 | "%s: Controller stop operation failed to " | |
1610 | "stop port %d because of status %d.\n", | |
1611 | __func__, | |
1612 | sci_port->logical_port_index, | |
1613 | port_status); | |
1614 | } | |
1615 | } | |
1616 | ||
1617 | return status; | |
1618 | } | |
1619 | ||
1620 | static enum sci_status scic_sds_controller_stop_devices(struct scic_sds_controller *scic) | |
1621 | { | |
1622 | u32 index; | |
1623 | enum sci_status status; | |
1624 | enum sci_status device_status; | |
1625 | ||
1626 | status = SCI_SUCCESS; | |
1627 | ||
1628 | for (index = 0; index < scic->remote_node_entries; index++) { | |
1629 | if (scic->device_table[index] != NULL) { | |
1630 | /* / @todo What timeout value do we want to provide to this request? */ | |
1631 | device_status = scic_remote_device_stop(scic->device_table[index], 0); | |
1632 | ||
1633 | if ((device_status != SCI_SUCCESS) && | |
1634 | (device_status != SCI_FAILURE_INVALID_STATE)) { | |
1635 | dev_warn(scic_to_dev(scic), | |
1636 | "%s: Controller stop operation failed " | |
1637 | "to stop device 0x%p because of " | |
1638 | "status %d.\n", | |
1639 | __func__, | |
1640 | scic->device_table[index], device_status); | |
1641 | } | |
1642 | } | |
1643 | } | |
1644 | ||
1645 | return status; | |
1646 | } | |
1647 | ||
9269e0e8 | 1648 | static void scic_sds_controller_stopping_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1649 | { |
9269e0e8 | 1650 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1651 | |
1652 | /* Stop all of the components for this controller */ | |
1653 | scic_sds_controller_stop_phys(scic); | |
1654 | scic_sds_controller_stop_ports(scic); | |
1655 | scic_sds_controller_stop_devices(scic); | |
1656 | } | |
1657 | ||
9269e0e8 | 1658 | static void scic_sds_controller_stopping_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1659 | { |
9269e0e8 | 1660 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1661 | |
1662 | isci_timer_stop(scic->timeout_timer); | |
1663 | } | |
1664 | ||
1665 | ||
1666 | /** | |
1667 | * scic_sds_controller_reset_hardware() - | |
1668 | * | |
1669 | * This method will reset the controller hardware. | |
1670 | */ | |
1671 | static void scic_sds_controller_reset_hardware(struct scic_sds_controller *scic) | |
1672 | { | |
1673 | /* Disable interrupts so we dont take any spurious interrupts */ | |
1674 | scic_controller_disable_interrupts(scic); | |
1675 | ||
1676 | /* Reset the SCU */ | |
1677 | writel(0xFFFFFFFF, &scic->smu_registers->soft_reset_control); | |
1678 | ||
1679 | /* Delay for 1ms to before clearing the CQP and UFQPR. */ | |
1680 | udelay(1000); | |
1681 | ||
1682 | /* The write to the CQGR clears the CQP */ | |
1683 | writel(0x00000000, &scic->smu_registers->completion_queue_get); | |
1684 | ||
1685 | /* The write to the UFQGP clears the UFQPR */ | |
1686 | writel(0, &scic->scu_registers->sdma.unsolicited_frame_get_pointer); | |
1687 | } | |
1688 | ||
9269e0e8 | 1689 | static void scic_sds_controller_resetting_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1690 | { |
9269e0e8 | 1691 | struct scic_sds_controller *scic = container_of(sm, typeof(*scic), state_machine); |
cc9203bf DW |
1692 | |
1693 | scic_sds_controller_reset_hardware(scic); | |
1694 | sci_base_state_machine_change_state(&scic->state_machine, | |
1695 | SCI_BASE_CONTROLLER_STATE_RESET); | |
1696 | } | |
1697 | ||
1698 | static const struct sci_base_state scic_sds_controller_state_table[] = { | |
1699 | [SCI_BASE_CONTROLLER_STATE_INITIAL] = { | |
1700 | .enter_state = scic_sds_controller_initial_state_enter, | |
1701 | }, | |
1702 | [SCI_BASE_CONTROLLER_STATE_RESET] = {}, | |
1703 | [SCI_BASE_CONTROLLER_STATE_INITIALIZING] = {}, | |
1704 | [SCI_BASE_CONTROLLER_STATE_INITIALIZED] = {}, | |
1705 | [SCI_BASE_CONTROLLER_STATE_STARTING] = { | |
1706 | .exit_state = scic_sds_controller_starting_state_exit, | |
1707 | }, | |
1708 | [SCI_BASE_CONTROLLER_STATE_READY] = { | |
1709 | .enter_state = scic_sds_controller_ready_state_enter, | |
1710 | .exit_state = scic_sds_controller_ready_state_exit, | |
1711 | }, | |
1712 | [SCI_BASE_CONTROLLER_STATE_RESETTING] = { | |
1713 | .enter_state = scic_sds_controller_resetting_state_enter, | |
1714 | }, | |
1715 | [SCI_BASE_CONTROLLER_STATE_STOPPING] = { | |
1716 | .enter_state = scic_sds_controller_stopping_state_enter, | |
1717 | .exit_state = scic_sds_controller_stopping_state_exit, | |
1718 | }, | |
1719 | [SCI_BASE_CONTROLLER_STATE_STOPPED] = {}, | |
1720 | [SCI_BASE_CONTROLLER_STATE_FAILED] = {} | |
1721 | }; | |
1722 | ||
1723 | static void scic_sds_controller_set_default_config_parameters(struct scic_sds_controller *scic) | |
1724 | { | |
1725 | /* these defaults are overridden by the platform / firmware */ | |
1726 | struct isci_host *ihost = scic_to_ihost(scic); | |
1727 | u16 index; | |
1728 | ||
1729 | /* Default to APC mode. */ | |
1730 | scic->oem_parameters.sds1.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE; | |
1731 | ||
1732 | /* Default to APC mode. */ | |
1733 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up = 1; | |
1734 | ||
1735 | /* Default to no SSC operation. */ | |
1736 | scic->oem_parameters.sds1.controller.do_enable_ssc = false; | |
1737 | ||
1738 | /* Initialize all of the port parameter information to narrow ports. */ | |
1739 | for (index = 0; index < SCI_MAX_PORTS; index++) { | |
1740 | scic->oem_parameters.sds1.ports[index].phy_mask = 0; | |
1741 | } | |
1742 | ||
1743 | /* Initialize all of the phy parameter information. */ | |
1744 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
1745 | /* Default to 6G (i.e. Gen 3) for now. */ | |
1746 | scic->user_parameters.sds1.phys[index].max_speed_generation = 3; | |
1747 | ||
1748 | /* the frequencies cannot be 0 */ | |
1749 | scic->user_parameters.sds1.phys[index].align_insertion_frequency = 0x7f; | |
1750 | scic->user_parameters.sds1.phys[index].in_connection_align_insertion_frequency = 0xff; | |
1751 | scic->user_parameters.sds1.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; | |
1752 | ||
1753 | /* | |
1754 | * Previous Vitesse based expanders had a arbitration issue that | |
1755 | * is worked around by having the upper 32-bits of SAS address | |
1756 | * with a value greater then the Vitesse company identifier. | |
1757 | * Hence, usage of 0x5FCFFFFF. */ | |
1758 | scic->oem_parameters.sds1.phys[index].sas_address.low = 0x1 + ihost->id; | |
1759 | scic->oem_parameters.sds1.phys[index].sas_address.high = 0x5FCFFFFF; | |
1760 | } | |
1761 | ||
1762 | scic->user_parameters.sds1.stp_inactivity_timeout = 5; | |
1763 | scic->user_parameters.sds1.ssp_inactivity_timeout = 5; | |
1764 | scic->user_parameters.sds1.stp_max_occupancy_timeout = 5; | |
1765 | scic->user_parameters.sds1.ssp_max_occupancy_timeout = 20; | |
1766 | scic->user_parameters.sds1.no_outbound_task_timeout = 20; | |
1767 | } | |
1768 | ||
1769 | ||
1770 | ||
1771 | /** | |
1772 | * scic_controller_construct() - This method will attempt to construct a | |
1773 | * controller object utilizing the supplied parameter information. | |
1774 | * @c: This parameter specifies the controller to be constructed. | |
1775 | * @scu_base: mapped base address of the scu registers | |
1776 | * @smu_base: mapped base address of the smu registers | |
1777 | * | |
1778 | * Indicate if the controller was successfully constructed or if it failed in | |
1779 | * some way. SCI_SUCCESS This value is returned if the controller was | |
1780 | * successfully constructed. SCI_WARNING_TIMER_CONFLICT This value is returned | |
1781 | * if the interrupt coalescence timer may cause SAS compliance issues for SMP | |
1782 | * Target mode response processing. SCI_FAILURE_UNSUPPORTED_CONTROLLER_TYPE | |
1783 | * This value is returned if the controller does not support the supplied type. | |
1784 | * SCI_FAILURE_UNSUPPORTED_INIT_DATA_VERSION This value is returned if the | |
1785 | * controller does not support the supplied initialization data version. | |
1786 | */ | |
1787 | static enum sci_status scic_controller_construct(struct scic_sds_controller *scic, | |
1788 | void __iomem *scu_base, | |
1789 | void __iomem *smu_base) | |
1790 | { | |
1791 | struct isci_host *ihost = scic_to_ihost(scic); | |
1792 | u8 i; | |
1793 | ||
1794 | sci_base_state_machine_construct(&scic->state_machine, | |
9269e0e8 DW |
1795 | scic_sds_controller_state_table, |
1796 | SCI_BASE_CONTROLLER_STATE_INITIAL); | |
cc9203bf DW |
1797 | |
1798 | sci_base_state_machine_start(&scic->state_machine); | |
1799 | ||
1800 | scic->scu_registers = scu_base; | |
1801 | scic->smu_registers = smu_base; | |
1802 | ||
1803 | scic_sds_port_configuration_agent_construct(&scic->port_agent); | |
1804 | ||
1805 | /* Construct the ports for this controller */ | |
1806 | for (i = 0; i < SCI_MAX_PORTS; i++) | |
1807 | scic_sds_port_construct(&ihost->ports[i].sci, i, scic); | |
1808 | scic_sds_port_construct(&ihost->ports[i].sci, SCIC_SDS_DUMMY_PORT, scic); | |
1809 | ||
1810 | /* Construct the phys for this controller */ | |
1811 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
1812 | /* Add all the PHYs to the dummy port */ | |
1813 | scic_sds_phy_construct(&ihost->phys[i].sci, | |
1814 | &ihost->ports[SCI_MAX_PORTS].sci, i); | |
1815 | } | |
1816 | ||
1817 | scic->invalid_phy_mask = 0; | |
1818 | ||
1819 | /* Set the default maximum values */ | |
1820 | scic->completion_event_entries = SCU_EVENT_COUNT; | |
1821 | scic->completion_queue_entries = SCU_COMPLETION_QUEUE_COUNT; | |
1822 | scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES; | |
1823 | scic->logical_port_entries = SCI_MAX_PORTS; | |
1824 | scic->task_context_entries = SCU_IO_REQUEST_COUNT; | |
1825 | scic->uf_control.buffers.count = SCU_UNSOLICITED_FRAME_COUNT; | |
1826 | scic->uf_control.address_table.count = SCU_UNSOLICITED_FRAME_COUNT; | |
1827 | ||
1828 | /* Initialize the User and OEM parameters to default values. */ | |
1829 | scic_sds_controller_set_default_config_parameters(scic); | |
1830 | ||
1831 | return scic_controller_reset(scic); | |
1832 | } | |
1833 | ||
1834 | int scic_oem_parameters_validate(struct scic_sds_oem_params *oem) | |
1835 | { | |
1836 | int i; | |
1837 | ||
1838 | for (i = 0; i < SCI_MAX_PORTS; i++) | |
1839 | if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) | |
1840 | return -EINVAL; | |
1841 | ||
1842 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1843 | if (oem->phys[i].sas_address.high == 0 && | |
1844 | oem->phys[i].sas_address.low == 0) | |
1845 | return -EINVAL; | |
1846 | ||
1847 | if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) { | |
1848 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1849 | if (oem->ports[i].phy_mask != 0) | |
1850 | return -EINVAL; | |
1851 | } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
1852 | u8 phy_mask = 0; | |
1853 | ||
1854 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1855 | phy_mask |= oem->ports[i].phy_mask; | |
1856 | ||
1857 | if (phy_mask == 0) | |
1858 | return -EINVAL; | |
1859 | } else | |
1860 | return -EINVAL; | |
1861 | ||
1862 | if (oem->controller.max_concurrent_dev_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT) | |
1863 | return -EINVAL; | |
1864 | ||
1865 | return 0; | |
1866 | } | |
1867 | ||
1868 | static enum sci_status scic_oem_parameters_set(struct scic_sds_controller *scic, | |
1869 | union scic_oem_parameters *scic_parms) | |
1870 | { | |
1871 | u32 state = scic->state_machine.current_state_id; | |
1872 | ||
1873 | if (state == SCI_BASE_CONTROLLER_STATE_RESET || | |
1874 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZING || | |
1875 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
1876 | ||
1877 | if (scic_oem_parameters_validate(&scic_parms->sds1)) | |
1878 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
1879 | scic->oem_parameters.sds1 = scic_parms->sds1; | |
1880 | ||
1881 | return SCI_SUCCESS; | |
1882 | } | |
1883 | ||
1884 | return SCI_FAILURE_INVALID_STATE; | |
1885 | } | |
1886 | ||
1887 | void scic_oem_parameters_get( | |
1888 | struct scic_sds_controller *scic, | |
1889 | union scic_oem_parameters *scic_parms) | |
1890 | { | |
1891 | memcpy(scic_parms, (&scic->oem_parameters), sizeof(*scic_parms)); | |
1892 | } | |
1893 | ||
1894 | static void scic_sds_controller_timeout_handler(void *_scic) | |
1895 | { | |
1896 | struct scic_sds_controller *scic = _scic; | |
1897 | struct isci_host *ihost = scic_to_ihost(scic); | |
1898 | struct sci_base_state_machine *sm = &scic->state_machine; | |
1899 | ||
1900 | if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STARTING) | |
1901 | scic_sds_controller_transition_to_ready(scic, SCI_FAILURE_TIMEOUT); | |
1902 | else if (sm->current_state_id == SCI_BASE_CONTROLLER_STATE_STOPPING) { | |
1903 | sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_FAILED); | |
1904 | isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT); | |
1905 | } else /* / @todo Now what do we want to do in this case? */ | |
1906 | dev_err(scic_to_dev(scic), | |
1907 | "%s: Controller timer fired when controller was not " | |
1908 | "in a state being timed.\n", | |
1909 | __func__); | |
1910 | } | |
1911 | ||
1912 | static enum sci_status scic_sds_controller_initialize_phy_startup(struct scic_sds_controller *scic) | |
1913 | { | |
1914 | struct isci_host *ihost = scic_to_ihost(scic); | |
1915 | ||
1916 | scic->phy_startup_timer = isci_timer_create(ihost, | |
1917 | scic, | |
1918 | scic_sds_controller_phy_startup_timeout_handler); | |
1919 | ||
1920 | if (scic->phy_startup_timer == NULL) | |
1921 | return SCI_FAILURE_INSUFFICIENT_RESOURCES; | |
1922 | else { | |
1923 | scic->next_phy_to_start = 0; | |
1924 | scic->phy_startup_timer_pending = false; | |
1925 | } | |
1926 | ||
1927 | return SCI_SUCCESS; | |
1928 | } | |
1929 | ||
1930 | static void scic_sds_controller_power_control_timer_start(struct scic_sds_controller *scic) | |
1931 | { | |
1932 | isci_timer_start(scic->power_control.timer, | |
1933 | SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); | |
1934 | ||
1935 | scic->power_control.timer_started = true; | |
1936 | } | |
1937 | ||
1938 | static void scic_sds_controller_power_control_timer_stop(struct scic_sds_controller *scic) | |
1939 | { | |
1940 | if (scic->power_control.timer_started) { | |
1941 | isci_timer_stop(scic->power_control.timer); | |
1942 | scic->power_control.timer_started = false; | |
1943 | } | |
1944 | } | |
1945 | ||
1946 | static void scic_sds_controller_power_control_timer_restart(struct scic_sds_controller *scic) | |
1947 | { | |
1948 | scic_sds_controller_power_control_timer_stop(scic); | |
1949 | scic_sds_controller_power_control_timer_start(scic); | |
1950 | } | |
1951 | ||
1952 | static void scic_sds_controller_power_control_timer_handler( | |
1953 | void *controller) | |
1954 | { | |
1955 | struct scic_sds_controller *scic; | |
1956 | ||
1957 | scic = (struct scic_sds_controller *)controller; | |
1958 | ||
1959 | scic->power_control.phys_granted_power = 0; | |
1960 | ||
1961 | if (scic->power_control.phys_waiting == 0) { | |
1962 | scic->power_control.timer_started = false; | |
1963 | } else { | |
1964 | struct scic_sds_phy *sci_phy = NULL; | |
1965 | u8 i; | |
1966 | ||
1967 | for (i = 0; | |
1968 | (i < SCI_MAX_PHYS) | |
1969 | && (scic->power_control.phys_waiting != 0); | |
1970 | i++) { | |
1971 | if (scic->power_control.requesters[i] != NULL) { | |
1972 | if (scic->power_control.phys_granted_power < | |
1973 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) { | |
1974 | sci_phy = scic->power_control.requesters[i]; | |
1975 | scic->power_control.requesters[i] = NULL; | |
1976 | scic->power_control.phys_waiting--; | |
1977 | scic->power_control.phys_granted_power++; | |
1978 | scic_sds_phy_consume_power_handler(sci_phy); | |
1979 | } else { | |
1980 | break; | |
1981 | } | |
1982 | } | |
1983 | } | |
1984 | ||
1985 | /* | |
1986 | * It doesn't matter if the power list is empty, we need to start the | |
1987 | * timer in case another phy becomes ready. | |
1988 | */ | |
1989 | scic_sds_controller_power_control_timer_start(scic); | |
1990 | } | |
1991 | } | |
1992 | ||
1993 | /** | |
1994 | * This method inserts the phy in the stagger spinup control queue. | |
1995 | * @scic: | |
1996 | * | |
1997 | * | |
1998 | */ | |
1999 | void scic_sds_controller_power_control_queue_insert( | |
2000 | struct scic_sds_controller *scic, | |
2001 | struct scic_sds_phy *sci_phy) | |
2002 | { | |
2003 | BUG_ON(sci_phy == NULL); | |
2004 | ||
2005 | if (scic->power_control.phys_granted_power < | |
2006 | scic->oem_parameters.sds1.controller.max_concurrent_dev_spin_up) { | |
2007 | scic->power_control.phys_granted_power++; | |
2008 | scic_sds_phy_consume_power_handler(sci_phy); | |
2009 | ||
2010 | /* | |
2011 | * stop and start the power_control timer. When the timer fires, the | |
2012 | * no_of_phys_granted_power will be set to 0 | |
2013 | */ | |
2014 | scic_sds_controller_power_control_timer_restart(scic); | |
2015 | } else { | |
2016 | /* Add the phy in the waiting list */ | |
2017 | scic->power_control.requesters[sci_phy->phy_index] = sci_phy; | |
2018 | scic->power_control.phys_waiting++; | |
2019 | } | |
2020 | } | |
2021 | ||
2022 | /** | |
2023 | * This method removes the phy from the stagger spinup control queue. | |
2024 | * @scic: | |
2025 | * | |
2026 | * | |
2027 | */ | |
2028 | void scic_sds_controller_power_control_queue_remove( | |
2029 | struct scic_sds_controller *scic, | |
2030 | struct scic_sds_phy *sci_phy) | |
2031 | { | |
2032 | BUG_ON(sci_phy == NULL); | |
2033 | ||
2034 | if (scic->power_control.requesters[sci_phy->phy_index] != NULL) { | |
2035 | scic->power_control.phys_waiting--; | |
2036 | } | |
2037 | ||
2038 | scic->power_control.requesters[sci_phy->phy_index] = NULL; | |
2039 | } | |
2040 | ||
2041 | #define AFE_REGISTER_WRITE_DELAY 10 | |
2042 | ||
2043 | /* Initialize the AFE for this phy index. We need to read the AFE setup from | |
2044 | * the OEM parameters | |
2045 | */ | |
2046 | static void scic_sds_controller_afe_initialization(struct scic_sds_controller *scic) | |
2047 | { | |
2048 | const struct scic_sds_oem_params *oem = &scic->oem_parameters.sds1; | |
2049 | u32 afe_status; | |
2050 | u32 phy_id; | |
2051 | ||
2052 | /* Clear DFX Status registers */ | |
2053 | writel(0x0081000f, &scic->scu_registers->afe.afe_dfx_master_control0); | |
2054 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2055 | ||
2056 | if (is_b0()) { | |
2057 | /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement | |
2058 | * Timer, PM Stagger Timer */ | |
2059 | writel(0x0007BFFF, &scic->scu_registers->afe.afe_pmsn_master_control2); | |
2060 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2061 | } | |
2062 | ||
2063 | /* Configure bias currents to normal */ | |
2064 | if (is_a0()) | |
2065 | writel(0x00005500, &scic->scu_registers->afe.afe_bias_control); | |
2066 | else if (is_a2()) | |
2067 | writel(0x00005A00, &scic->scu_registers->afe.afe_bias_control); | |
2068 | else if (is_b0()) | |
2069 | writel(0x00005F00, &scic->scu_registers->afe.afe_bias_control); | |
2070 | ||
2071 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2072 | ||
2073 | /* Enable PLL */ | |
2074 | if (is_b0()) | |
2075 | writel(0x80040A08, &scic->scu_registers->afe.afe_pll_control0); | |
2076 | else | |
2077 | writel(0x80040908, &scic->scu_registers->afe.afe_pll_control0); | |
2078 | ||
2079 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2080 | ||
2081 | /* Wait for the PLL to lock */ | |
2082 | do { | |
2083 | afe_status = readl(&scic->scu_registers->afe.afe_common_block_status); | |
2084 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2085 | } while ((afe_status & 0x00001000) == 0); | |
2086 | ||
2087 | if (is_a0() || is_a2()) { | |
2088 | /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ | |
2089 | writel(0x7bcc96ad, &scic->scu_registers->afe.afe_pmsn_master_control0); | |
2090 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2091 | } | |
2092 | ||
2093 | for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { | |
2094 | const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; | |
2095 | ||
2096 | if (is_b0()) { | |
2097 | /* Configure transmitter SSC parameters */ | |
2098 | writel(0x00030000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); | |
2099 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2100 | } else { | |
2101 | /* | |
2102 | * All defaults, except the Receive Word Alignament/Comma Detect | |
2103 | * Enable....(0xe800) */ | |
2104 | writel(0x00004512, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); | |
2105 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2106 | ||
2107 | writel(0x0050100F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1); | |
2108 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2109 | } | |
2110 | ||
2111 | /* | |
2112 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
2113 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
2114 | if (is_a0()) | |
2115 | writel(0x000003D4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); | |
2116 | else if (is_a2()) | |
2117 | writel(0x000003F0, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); | |
2118 | else { | |
2119 | /* Power down TX and RX (PWRDNTX and PWRDNRX) */ | |
2120 | writel(0x000003d7, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); | |
2121 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2122 | ||
2123 | /* | |
2124 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
2125 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
2126 | writel(0x000003d4, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); | |
2127 | } | |
2128 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2129 | ||
2130 | if (is_a0() || is_a2()) { | |
2131 | /* Enable TX equalization (0xe824) */ | |
2132 | writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); | |
2133 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2134 | } | |
2135 | ||
2136 | /* | |
2137 | * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On), | |
2138 | * RDD=0x0(RX Detect Enabled) ....(0xe800) */ | |
2139 | writel(0x00004100, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); | |
2140 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2141 | ||
2142 | /* Leave DFE/FFE on */ | |
2143 | if (is_a0()) | |
2144 | writel(0x3F09983F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); | |
2145 | else if (is_a2()) | |
2146 | writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); | |
2147 | else { | |
2148 | writel(0x3F11103F, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); | |
2149 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2150 | /* Enable TX equalization (0xe824) */ | |
2151 | writel(0x00040000, &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); | |
2152 | } | |
2153 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2154 | ||
2155 | writel(oem_phy->afe_tx_amp_control0, | |
2156 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0); | |
2157 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2158 | ||
2159 | writel(oem_phy->afe_tx_amp_control1, | |
2160 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1); | |
2161 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2162 | ||
2163 | writel(oem_phy->afe_tx_amp_control2, | |
2164 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2); | |
2165 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2166 | ||
2167 | writel(oem_phy->afe_tx_amp_control3, | |
2168 | &scic->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3); | |
2169 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2170 | } | |
2171 | ||
2172 | /* Transfer control to the PEs */ | |
2173 | writel(0x00010f00, &scic->scu_registers->afe.afe_dfx_master_control0); | |
2174 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2175 | } | |
2176 | ||
2177 | static enum sci_status scic_controller_set_mode(struct scic_sds_controller *scic, | |
2178 | enum sci_controller_mode operating_mode) | |
2179 | { | |
2180 | enum sci_status status = SCI_SUCCESS; | |
2181 | ||
2182 | if ((scic->state_machine.current_state_id == | |
2183 | SCI_BASE_CONTROLLER_STATE_INITIALIZING) || | |
2184 | (scic->state_machine.current_state_id == | |
2185 | SCI_BASE_CONTROLLER_STATE_INITIALIZED)) { | |
2186 | switch (operating_mode) { | |
2187 | case SCI_MODE_SPEED: | |
2188 | scic->remote_node_entries = SCI_MAX_REMOTE_DEVICES; | |
2189 | scic->task_context_entries = SCU_IO_REQUEST_COUNT; | |
2190 | scic->uf_control.buffers.count = | |
2191 | SCU_UNSOLICITED_FRAME_COUNT; | |
2192 | scic->completion_event_entries = SCU_EVENT_COUNT; | |
2193 | scic->completion_queue_entries = | |
2194 | SCU_COMPLETION_QUEUE_COUNT; | |
2195 | break; | |
2196 | ||
2197 | case SCI_MODE_SIZE: | |
2198 | scic->remote_node_entries = SCI_MIN_REMOTE_DEVICES; | |
2199 | scic->task_context_entries = SCI_MIN_IO_REQUESTS; | |
2200 | scic->uf_control.buffers.count = | |
2201 | SCU_MIN_UNSOLICITED_FRAMES; | |
2202 | scic->completion_event_entries = SCU_MIN_EVENTS; | |
2203 | scic->completion_queue_entries = | |
2204 | SCU_MIN_COMPLETION_QUEUE_ENTRIES; | |
2205 | break; | |
2206 | ||
2207 | default: | |
2208 | status = SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2209 | break; | |
2210 | } | |
2211 | } else | |
2212 | status = SCI_FAILURE_INVALID_STATE; | |
2213 | ||
2214 | return status; | |
2215 | } | |
2216 | ||
2217 | static void scic_sds_controller_initialize_power_control(struct scic_sds_controller *scic) | |
2218 | { | |
2219 | struct isci_host *ihost = scic_to_ihost(scic); | |
2220 | scic->power_control.timer = isci_timer_create(ihost, | |
2221 | scic, | |
2222 | scic_sds_controller_power_control_timer_handler); | |
2223 | ||
2224 | memset(scic->power_control.requesters, 0, | |
2225 | sizeof(scic->power_control.requesters)); | |
2226 | ||
2227 | scic->power_control.phys_waiting = 0; | |
2228 | scic->power_control.phys_granted_power = 0; | |
2229 | } | |
2230 | ||
2231 | static enum sci_status scic_controller_initialize(struct scic_sds_controller *scic) | |
2232 | { | |
2233 | struct sci_base_state_machine *sm = &scic->state_machine; | |
2234 | enum sci_status result = SCI_SUCCESS; | |
2235 | struct isci_host *ihost = scic_to_ihost(scic); | |
2236 | u32 index, state; | |
2237 | ||
2238 | if (scic->state_machine.current_state_id != | |
2239 | SCI_BASE_CONTROLLER_STATE_RESET) { | |
2240 | dev_warn(scic_to_dev(scic), | |
2241 | "SCIC Controller initialize operation requested " | |
2242 | "in invalid state\n"); | |
2243 | return SCI_FAILURE_INVALID_STATE; | |
2244 | } | |
2245 | ||
2246 | sci_base_state_machine_change_state(sm, SCI_BASE_CONTROLLER_STATE_INITIALIZING); | |
2247 | ||
2248 | scic->timeout_timer = isci_timer_create(ihost, scic, | |
2249 | scic_sds_controller_timeout_handler); | |
2250 | ||
2251 | scic_sds_controller_initialize_phy_startup(scic); | |
2252 | ||
2253 | scic_sds_controller_initialize_power_control(scic); | |
2254 | ||
2255 | /* | |
2256 | * There is nothing to do here for B0 since we do not have to | |
2257 | * program the AFE registers. | |
2258 | * / @todo The AFE settings are supposed to be correct for the B0 but | |
2259 | * / presently they seem to be wrong. */ | |
2260 | scic_sds_controller_afe_initialization(scic); | |
2261 | ||
2262 | if (result == SCI_SUCCESS) { | |
2263 | u32 status; | |
2264 | u32 terminate_loop; | |
2265 | ||
2266 | /* Take the hardware out of reset */ | |
2267 | writel(0, &scic->smu_registers->soft_reset_control); | |
2268 | ||
2269 | /* | |
2270 | * / @todo Provide meaningfull error code for hardware failure | |
2271 | * result = SCI_FAILURE_CONTROLLER_HARDWARE; */ | |
2272 | result = SCI_FAILURE; | |
2273 | terminate_loop = 100; | |
2274 | ||
2275 | while (terminate_loop-- && (result != SCI_SUCCESS)) { | |
2276 | /* Loop until the hardware reports success */ | |
2277 | udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); | |
2278 | status = readl(&scic->smu_registers->control_status); | |
2279 | ||
2280 | if ((status & SCU_RAM_INIT_COMPLETED) == | |
2281 | SCU_RAM_INIT_COMPLETED) | |
2282 | result = SCI_SUCCESS; | |
2283 | } | |
2284 | } | |
2285 | ||
2286 | if (result == SCI_SUCCESS) { | |
2287 | u32 max_supported_ports; | |
2288 | u32 max_supported_devices; | |
2289 | u32 max_supported_io_requests; | |
2290 | u32 device_context_capacity; | |
2291 | ||
2292 | /* | |
2293 | * Determine what are the actaul device capacities that the | |
2294 | * hardware will support */ | |
2295 | device_context_capacity = | |
2296 | readl(&scic->smu_registers->device_context_capacity); | |
2297 | ||
2298 | ||
2299 | max_supported_ports = smu_dcc_get_max_ports(device_context_capacity); | |
2300 | max_supported_devices = smu_dcc_get_max_remote_node_context(device_context_capacity); | |
2301 | max_supported_io_requests = smu_dcc_get_max_task_context(device_context_capacity); | |
2302 | ||
2303 | /* | |
2304 | * Make all PEs that are unassigned match up with the | |
2305 | * logical ports | |
2306 | */ | |
2307 | for (index = 0; index < max_supported_ports; index++) { | |
2308 | struct scu_port_task_scheduler_group_registers __iomem | |
2309 | *ptsg = &scic->scu_registers->peg0.ptsg; | |
2310 | ||
2311 | writel(index, &ptsg->protocol_engine[index]); | |
2312 | } | |
2313 | ||
2314 | /* Record the smaller of the two capacity values */ | |
2315 | scic->logical_port_entries = | |
2316 | min(max_supported_ports, scic->logical_port_entries); | |
2317 | ||
2318 | scic->task_context_entries = | |
2319 | min(max_supported_io_requests, | |
2320 | scic->task_context_entries); | |
2321 | ||
2322 | scic->remote_node_entries = | |
2323 | min(max_supported_devices, scic->remote_node_entries); | |
2324 | ||
2325 | /* | |
2326 | * Now that we have the correct hardware reported minimum values | |
2327 | * build the MDL for the controller. Default to a performance | |
2328 | * configuration. | |
2329 | */ | |
2330 | scic_controller_set_mode(scic, SCI_MODE_SPEED); | |
2331 | } | |
2332 | ||
2333 | /* Initialize hardware PCI Relaxed ordering in DMA engines */ | |
2334 | if (result == SCI_SUCCESS) { | |
2335 | u32 dma_configuration; | |
2336 | ||
2337 | /* Configure the payload DMA */ | |
2338 | dma_configuration = | |
2339 | readl(&scic->scu_registers->sdma.pdma_configuration); | |
2340 | dma_configuration |= | |
2341 | SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); | |
2342 | writel(dma_configuration, | |
2343 | &scic->scu_registers->sdma.pdma_configuration); | |
2344 | ||
2345 | /* Configure the control DMA */ | |
2346 | dma_configuration = | |
2347 | readl(&scic->scu_registers->sdma.cdma_configuration); | |
2348 | dma_configuration |= | |
2349 | SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); | |
2350 | writel(dma_configuration, | |
2351 | &scic->scu_registers->sdma.cdma_configuration); | |
2352 | } | |
2353 | ||
2354 | /* | |
2355 | * Initialize the PHYs before the PORTs because the PHY registers | |
2356 | * are accessed during the port initialization. | |
2357 | */ | |
2358 | if (result == SCI_SUCCESS) { | |
2359 | /* Initialize the phys */ | |
2360 | for (index = 0; | |
2361 | (result == SCI_SUCCESS) && (index < SCI_MAX_PHYS); | |
2362 | index++) { | |
2363 | result = scic_sds_phy_initialize( | |
2364 | &ihost->phys[index].sci, | |
2365 | &scic->scu_registers->peg0.pe[index].tl, | |
2366 | &scic->scu_registers->peg0.pe[index].ll); | |
2367 | } | |
2368 | } | |
2369 | ||
2370 | if (result == SCI_SUCCESS) { | |
2371 | /* Initialize the logical ports */ | |
2372 | for (index = 0; | |
2373 | (index < scic->logical_port_entries) && | |
2374 | (result == SCI_SUCCESS); | |
2375 | index++) { | |
2376 | result = scic_sds_port_initialize( | |
2377 | &ihost->ports[index].sci, | |
2378 | &scic->scu_registers->peg0.ptsg.port[index], | |
2379 | &scic->scu_registers->peg0.ptsg.protocol_engine, | |
2380 | &scic->scu_registers->peg0.viit[index]); | |
2381 | } | |
2382 | } | |
2383 | ||
2384 | if (result == SCI_SUCCESS) | |
2385 | result = scic_sds_port_configuration_agent_initialize( | |
2386 | scic, | |
2387 | &scic->port_agent); | |
2388 | ||
2389 | /* Advance the controller state machine */ | |
2390 | if (result == SCI_SUCCESS) | |
2391 | state = SCI_BASE_CONTROLLER_STATE_INITIALIZED; | |
2392 | else | |
2393 | state = SCI_BASE_CONTROLLER_STATE_FAILED; | |
2394 | sci_base_state_machine_change_state(sm, state); | |
2395 | ||
2396 | return result; | |
2397 | } | |
2398 | ||
2399 | static enum sci_status scic_user_parameters_set( | |
2400 | struct scic_sds_controller *scic, | |
2401 | union scic_user_parameters *scic_parms) | |
2402 | { | |
2403 | u32 state = scic->state_machine.current_state_id; | |
2404 | ||
2405 | if (state == SCI_BASE_CONTROLLER_STATE_RESET || | |
2406 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZING || | |
2407 | state == SCI_BASE_CONTROLLER_STATE_INITIALIZED) { | |
2408 | u16 index; | |
2409 | ||
2410 | /* | |
2411 | * Validate the user parameters. If they are not legal, then | |
2412 | * return a failure. | |
2413 | */ | |
2414 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
2415 | struct sci_phy_user_params *user_phy; | |
2416 | ||
2417 | user_phy = &scic_parms->sds1.phys[index]; | |
2418 | ||
2419 | if (!((user_phy->max_speed_generation <= | |
2420 | SCIC_SDS_PARM_MAX_SPEED) && | |
2421 | (user_phy->max_speed_generation > | |
2422 | SCIC_SDS_PARM_NO_SPEED))) | |
2423 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2424 | ||
2425 | if (user_phy->in_connection_align_insertion_frequency < | |
2426 | 3) | |
2427 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2428 | ||
2429 | if ((user_phy->in_connection_align_insertion_frequency < | |
2430 | 3) || | |
2431 | (user_phy->align_insertion_frequency == 0) || | |
2432 | (user_phy-> | |
2433 | notify_enable_spin_up_insertion_frequency == | |
2434 | 0)) | |
2435 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2436 | } | |
2437 | ||
2438 | if ((scic_parms->sds1.stp_inactivity_timeout == 0) || | |
2439 | (scic_parms->sds1.ssp_inactivity_timeout == 0) || | |
2440 | (scic_parms->sds1.stp_max_occupancy_timeout == 0) || | |
2441 | (scic_parms->sds1.ssp_max_occupancy_timeout == 0) || | |
2442 | (scic_parms->sds1.no_outbound_task_timeout == 0)) | |
2443 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2444 | ||
2445 | memcpy(&scic->user_parameters, scic_parms, sizeof(*scic_parms)); | |
2446 | ||
2447 | return SCI_SUCCESS; | |
2448 | } | |
2449 | ||
2450 | return SCI_FAILURE_INVALID_STATE; | |
2451 | } | |
2452 | ||
2453 | static int scic_controller_mem_init(struct scic_sds_controller *scic) | |
2454 | { | |
2455 | struct device *dev = scic_to_dev(scic); | |
2456 | dma_addr_t dma_handle; | |
2457 | enum sci_status result; | |
2458 | ||
2459 | scic->completion_queue = dmam_alloc_coherent(dev, | |
2460 | scic->completion_queue_entries * sizeof(u32), | |
2461 | &dma_handle, GFP_KERNEL); | |
2462 | if (!scic->completion_queue) | |
2463 | return -ENOMEM; | |
2464 | ||
2465 | writel(lower_32_bits(dma_handle), | |
2466 | &scic->smu_registers->completion_queue_lower); | |
2467 | writel(upper_32_bits(dma_handle), | |
2468 | &scic->smu_registers->completion_queue_upper); | |
2469 | ||
2470 | scic->remote_node_context_table = dmam_alloc_coherent(dev, | |
2471 | scic->remote_node_entries * | |
2472 | sizeof(union scu_remote_node_context), | |
2473 | &dma_handle, GFP_KERNEL); | |
2474 | if (!scic->remote_node_context_table) | |
2475 | return -ENOMEM; | |
2476 | ||
2477 | writel(lower_32_bits(dma_handle), | |
2478 | &scic->smu_registers->remote_node_context_lower); | |
2479 | writel(upper_32_bits(dma_handle), | |
2480 | &scic->smu_registers->remote_node_context_upper); | |
2481 | ||
2482 | scic->task_context_table = dmam_alloc_coherent(dev, | |
2483 | scic->task_context_entries * | |
2484 | sizeof(struct scu_task_context), | |
2485 | &dma_handle, GFP_KERNEL); | |
2486 | if (!scic->task_context_table) | |
2487 | return -ENOMEM; | |
2488 | ||
2489 | writel(lower_32_bits(dma_handle), | |
2490 | &scic->smu_registers->host_task_table_lower); | |
2491 | writel(upper_32_bits(dma_handle), | |
2492 | &scic->smu_registers->host_task_table_upper); | |
2493 | ||
2494 | result = scic_sds_unsolicited_frame_control_construct(scic); | |
2495 | if (result) | |
2496 | return result; | |
2497 | ||
2498 | /* | |
2499 | * Inform the silicon as to the location of the UF headers and | |
2500 | * address table. | |
2501 | */ | |
2502 | writel(lower_32_bits(scic->uf_control.headers.physical_address), | |
2503 | &scic->scu_registers->sdma.uf_header_base_address_lower); | |
2504 | writel(upper_32_bits(scic->uf_control.headers.physical_address), | |
2505 | &scic->scu_registers->sdma.uf_header_base_address_upper); | |
2506 | ||
2507 | writel(lower_32_bits(scic->uf_control.address_table.physical_address), | |
2508 | &scic->scu_registers->sdma.uf_address_table_lower); | |
2509 | writel(upper_32_bits(scic->uf_control.address_table.physical_address), | |
2510 | &scic->scu_registers->sdma.uf_address_table_upper); | |
2511 | ||
2512 | return 0; | |
2513 | } | |
2514 | ||
6f231dda DW |
2515 | int isci_host_init(struct isci_host *isci_host) |
2516 | { | |
d9c37390 | 2517 | int err = 0, i; |
6f231dda | 2518 | enum sci_status status; |
4711ba10 | 2519 | union scic_oem_parameters oem; |
6f231dda | 2520 | union scic_user_parameters scic_user_params; |
d044af17 | 2521 | struct isci_pci_info *pci_info = to_pci_info(isci_host->pdev); |
6f231dda | 2522 | |
7c40a803 | 2523 | isci_timer_list_construct(isci_host); |
6f231dda | 2524 | |
6f231dda DW |
2525 | spin_lock_init(&isci_host->state_lock); |
2526 | spin_lock_init(&isci_host->scic_lock); | |
2527 | spin_lock_init(&isci_host->queue_lock); | |
0cf89d1d | 2528 | init_waitqueue_head(&isci_host->eventq); |
6f231dda DW |
2529 | |
2530 | isci_host_change_state(isci_host, isci_starting); | |
2531 | isci_host->can_queue = ISCI_CAN_QUEUE_VAL; | |
2532 | ||
cc3dbd0a | 2533 | status = scic_controller_construct(&isci_host->sci, scu_base(isci_host), |
6f231dda DW |
2534 | smu_base(isci_host)); |
2535 | ||
2536 | if (status != SCI_SUCCESS) { | |
2537 | dev_err(&isci_host->pdev->dev, | |
2538 | "%s: scic_controller_construct failed - status = %x\n", | |
2539 | __func__, | |
2540 | status); | |
858d4aa7 | 2541 | return -ENODEV; |
6f231dda DW |
2542 | } |
2543 | ||
2544 | isci_host->sas_ha.dev = &isci_host->pdev->dev; | |
2545 | isci_host->sas_ha.lldd_ha = isci_host; | |
2546 | ||
d044af17 DW |
2547 | /* |
2548 | * grab initial values stored in the controller object for OEM and USER | |
2549 | * parameters | |
2550 | */ | |
b5f18a20 | 2551 | isci_user_parameters_get(isci_host, &scic_user_params); |
cc3dbd0a | 2552 | status = scic_user_parameters_set(&isci_host->sci, |
d044af17 DW |
2553 | &scic_user_params); |
2554 | if (status != SCI_SUCCESS) { | |
2555 | dev_warn(&isci_host->pdev->dev, | |
2556 | "%s: scic_user_parameters_set failed\n", | |
2557 | __func__); | |
2558 | return -ENODEV; | |
2559 | } | |
2560 | ||
cc3dbd0a | 2561 | scic_oem_parameters_get(&isci_host->sci, &oem); |
6f231dda | 2562 | |
d044af17 DW |
2563 | /* grab any OEM parameters specified in orom */ |
2564 | if (pci_info->orom) { | |
4711ba10 | 2565 | status = isci_parse_oem_parameters(&oem, |
d044af17 DW |
2566 | pci_info->orom, |
2567 | isci_host->id); | |
6f231dda DW |
2568 | if (status != SCI_SUCCESS) { |
2569 | dev_warn(&isci_host->pdev->dev, | |
2570 | "parsing firmware oem parameters failed\n"); | |
858d4aa7 | 2571 | return -EINVAL; |
6f231dda | 2572 | } |
4711ba10 DW |
2573 | } |
2574 | ||
cc3dbd0a | 2575 | status = scic_oem_parameters_set(&isci_host->sci, &oem); |
4711ba10 DW |
2576 | if (status != SCI_SUCCESS) { |
2577 | dev_warn(&isci_host->pdev->dev, | |
2578 | "%s: scic_oem_parameters_set failed\n", | |
2579 | __func__); | |
2580 | return -ENODEV; | |
6f231dda DW |
2581 | } |
2582 | ||
7c40a803 DW |
2583 | tasklet_init(&isci_host->completion_tasklet, |
2584 | isci_host_completion_routine, (unsigned long)isci_host); | |
2585 | ||
7c40a803 | 2586 | INIT_LIST_HEAD(&isci_host->requests_to_complete); |
11b00c19 | 2587 | INIT_LIST_HEAD(&isci_host->requests_to_errorback); |
7c40a803 DW |
2588 | |
2589 | spin_lock_irq(&isci_host->scic_lock); | |
cc3dbd0a | 2590 | status = scic_controller_initialize(&isci_host->sci); |
7c40a803 | 2591 | spin_unlock_irq(&isci_host->scic_lock); |
6f231dda DW |
2592 | if (status != SCI_SUCCESS) { |
2593 | dev_warn(&isci_host->pdev->dev, | |
2594 | "%s: scic_controller_initialize failed -" | |
2595 | " status = 0x%x\n", | |
2596 | __func__, status); | |
858d4aa7 | 2597 | return -ENODEV; |
6f231dda DW |
2598 | } |
2599 | ||
cc3dbd0a | 2600 | err = scic_controller_mem_init(&isci_host->sci); |
6f231dda | 2601 | if (err) |
858d4aa7 | 2602 | return err; |
6f231dda | 2603 | |
6f231dda | 2604 | isci_host->dma_pool = dmam_pool_create(DRV_NAME, &isci_host->pdev->dev, |
67ea838d | 2605 | sizeof(struct isci_request), |
6f231dda DW |
2606 | SLAB_HWCACHE_ALIGN, 0); |
2607 | ||
858d4aa7 DJ |
2608 | if (!isci_host->dma_pool) |
2609 | return -ENOMEM; | |
6f231dda | 2610 | |
d9c37390 | 2611 | for (i = 0; i < SCI_MAX_PORTS; i++) |
e531381e | 2612 | isci_port_init(&isci_host->ports[i], isci_host, i); |
6f231dda | 2613 | |
d9c37390 DW |
2614 | for (i = 0; i < SCI_MAX_PHYS; i++) |
2615 | isci_phy_init(&isci_host->phys[i], isci_host, i); | |
2616 | ||
2617 | for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) { | |
57f20f4e | 2618 | struct isci_remote_device *idev = &isci_host->devices[i]; |
d9c37390 DW |
2619 | |
2620 | INIT_LIST_HEAD(&idev->reqs_in_process); | |
2621 | INIT_LIST_HEAD(&idev->node); | |
2622 | spin_lock_init(&idev->state_lock); | |
2623 | } | |
6f231dda | 2624 | |
858d4aa7 | 2625 | return 0; |
6f231dda | 2626 | } |
cc9203bf DW |
2627 | |
2628 | void scic_sds_controller_link_up(struct scic_sds_controller *scic, | |
2629 | struct scic_sds_port *port, struct scic_sds_phy *phy) | |
2630 | { | |
2631 | switch (scic->state_machine.current_state_id) { | |
2632 | case SCI_BASE_CONTROLLER_STATE_STARTING: | |
2633 | scic_sds_controller_phy_timer_stop(scic); | |
2634 | scic->port_agent.link_up_handler(scic, &scic->port_agent, | |
2635 | port, phy); | |
2636 | scic_sds_controller_start_next_phy(scic); | |
2637 | break; | |
2638 | case SCI_BASE_CONTROLLER_STATE_READY: | |
2639 | scic->port_agent.link_up_handler(scic, &scic->port_agent, | |
2640 | port, phy); | |
2641 | break; | |
2642 | default: | |
2643 | dev_dbg(scic_to_dev(scic), | |
2644 | "%s: SCIC Controller linkup event from phy %d in " | |
2645 | "unexpected state %d\n", __func__, phy->phy_index, | |
2646 | scic->state_machine.current_state_id); | |
2647 | } | |
2648 | } | |
2649 | ||
2650 | void scic_sds_controller_link_down(struct scic_sds_controller *scic, | |
2651 | struct scic_sds_port *port, struct scic_sds_phy *phy) | |
2652 | { | |
2653 | switch (scic->state_machine.current_state_id) { | |
2654 | case SCI_BASE_CONTROLLER_STATE_STARTING: | |
2655 | case SCI_BASE_CONTROLLER_STATE_READY: | |
2656 | scic->port_agent.link_down_handler(scic, &scic->port_agent, | |
2657 | port, phy); | |
2658 | break; | |
2659 | default: | |
2660 | dev_dbg(scic_to_dev(scic), | |
2661 | "%s: SCIC Controller linkdown event from phy %d in " | |
2662 | "unexpected state %d\n", | |
2663 | __func__, | |
2664 | phy->phy_index, | |
2665 | scic->state_machine.current_state_id); | |
2666 | } | |
2667 | } | |
2668 | ||
2669 | /** | |
2670 | * This is a helper method to determine if any remote devices on this | |
2671 | * controller are still in the stopping state. | |
2672 | * | |
2673 | */ | |
2674 | static bool scic_sds_controller_has_remote_devices_stopping( | |
2675 | struct scic_sds_controller *controller) | |
2676 | { | |
2677 | u32 index; | |
2678 | ||
2679 | for (index = 0; index < controller->remote_node_entries; index++) { | |
2680 | if ((controller->device_table[index] != NULL) && | |
2681 | (controller->device_table[index]->state_machine.current_state_id | |
2682 | == SCI_BASE_REMOTE_DEVICE_STATE_STOPPING)) | |
2683 | return true; | |
2684 | } | |
2685 | ||
2686 | return false; | |
2687 | } | |
2688 | ||
2689 | /** | |
2690 | * This method is called by the remote device to inform the controller | |
2691 | * object that the remote device has stopped. | |
2692 | */ | |
2693 | void scic_sds_controller_remote_device_stopped(struct scic_sds_controller *scic, | |
2694 | struct scic_sds_remote_device *sci_dev) | |
2695 | { | |
2696 | if (scic->state_machine.current_state_id != | |
2697 | SCI_BASE_CONTROLLER_STATE_STOPPING) { | |
2698 | dev_dbg(scic_to_dev(scic), | |
2699 | "SCIC Controller 0x%p remote device stopped event " | |
2700 | "from device 0x%p in unexpected state %d\n", | |
2701 | scic, sci_dev, | |
2702 | scic->state_machine.current_state_id); | |
2703 | return; | |
2704 | } | |
2705 | ||
2706 | if (!scic_sds_controller_has_remote_devices_stopping(scic)) { | |
2707 | sci_base_state_machine_change_state(&scic->state_machine, | |
2708 | SCI_BASE_CONTROLLER_STATE_STOPPED); | |
2709 | } | |
2710 | } | |
2711 | ||
2712 | /** | |
2713 | * This method will write to the SCU PCP register the request value. The method | |
2714 | * is used to suspend/resume ports, devices, and phys. | |
2715 | * @scic: | |
2716 | * | |
2717 | * | |
2718 | */ | |
2719 | void scic_sds_controller_post_request( | |
2720 | struct scic_sds_controller *scic, | |
2721 | u32 request) | |
2722 | { | |
2723 | dev_dbg(scic_to_dev(scic), | |
2724 | "%s: SCIC Controller 0x%p post request 0x%08x\n", | |
2725 | __func__, | |
2726 | scic, | |
2727 | request); | |
2728 | ||
2729 | writel(request, &scic->smu_registers->post_context_port); | |
2730 | } | |
2731 | ||
2732 | /** | |
2733 | * This method will copy the soft copy of the task context into the physical | |
2734 | * memory accessible by the controller. | |
2735 | * @scic: This parameter specifies the controller for which to copy | |
2736 | * the task context. | |
2737 | * @sci_req: This parameter specifies the request for which the task | |
2738 | * context is being copied. | |
2739 | * | |
2740 | * After this call is made the SCIC_SDS_IO_REQUEST object will always point to | |
2741 | * the physical memory version of the task context. Thus, all subsequent | |
2742 | * updates to the task context are performed in the TC table (i.e. DMAable | |
2743 | * memory). none | |
2744 | */ | |
2745 | void scic_sds_controller_copy_task_context( | |
2746 | struct scic_sds_controller *scic, | |
2747 | struct scic_sds_request *sci_req) | |
2748 | { | |
2749 | struct scu_task_context *task_context_buffer; | |
2750 | ||
2751 | task_context_buffer = scic_sds_controller_get_task_context_buffer( | |
2752 | scic, sci_req->io_tag); | |
2753 | ||
2754 | memcpy(task_context_buffer, | |
2755 | sci_req->task_context_buffer, | |
2756 | offsetof(struct scu_task_context, sgl_snapshot_ac)); | |
2757 | ||
2758 | /* | |
2759 | * Now that the soft copy of the TC has been copied into the TC | |
2760 | * table accessible by the silicon. Thus, any further changes to | |
2761 | * the TC (e.g. TC termination) occur in the appropriate location. */ | |
2762 | sci_req->task_context_buffer = task_context_buffer; | |
2763 | } | |
2764 | ||
2765 | /** | |
2766 | * This method returns the task context buffer for the given io tag. | |
2767 | * @scic: | |
2768 | * @io_tag: | |
2769 | * | |
2770 | * struct scu_task_context* | |
2771 | */ | |
2772 | struct scu_task_context *scic_sds_controller_get_task_context_buffer( | |
2773 | struct scic_sds_controller *scic, | |
2774 | u16 io_tag | |
2775 | ) { | |
2776 | u16 task_index = scic_sds_io_tag_get_index(io_tag); | |
2777 | ||
2778 | if (task_index < scic->task_context_entries) { | |
2779 | return &scic->task_context_table[task_index]; | |
2780 | } | |
2781 | ||
2782 | return NULL; | |
2783 | } | |
2784 | ||
2785 | struct scic_sds_request *scic_request_by_tag(struct scic_sds_controller *scic, | |
2786 | u16 io_tag) | |
2787 | { | |
2788 | u16 task_index; | |
2789 | u16 task_sequence; | |
2790 | ||
2791 | task_index = scic_sds_io_tag_get_index(io_tag); | |
2792 | ||
2793 | if (task_index < scic->task_context_entries) { | |
2794 | if (scic->io_request_table[task_index] != NULL) { | |
2795 | task_sequence = scic_sds_io_tag_get_sequence(io_tag); | |
2796 | ||
2797 | if (task_sequence == scic->io_request_sequence[task_index]) { | |
2798 | return scic->io_request_table[task_index]; | |
2799 | } | |
2800 | } | |
2801 | } | |
2802 | ||
2803 | return NULL; | |
2804 | } | |
2805 | ||
2806 | /** | |
2807 | * This method allocates remote node index and the reserves the remote node | |
2808 | * context space for use. This method can fail if there are no more remote | |
2809 | * node index available. | |
2810 | * @scic: This is the controller object which contains the set of | |
2811 | * free remote node ids | |
2812 | * @sci_dev: This is the device object which is requesting the a remote node | |
2813 | * id | |
2814 | * @node_id: This is the remote node id that is assinged to the device if one | |
2815 | * is available | |
2816 | * | |
2817 | * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote | |
2818 | * node index available. | |
2819 | */ | |
2820 | enum sci_status scic_sds_controller_allocate_remote_node_context( | |
2821 | struct scic_sds_controller *scic, | |
2822 | struct scic_sds_remote_device *sci_dev, | |
2823 | u16 *node_id) | |
2824 | { | |
2825 | u16 node_index; | |
2826 | u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev); | |
2827 | ||
2828 | node_index = scic_sds_remote_node_table_allocate_remote_node( | |
2829 | &scic->available_remote_nodes, remote_node_count | |
2830 | ); | |
2831 | ||
2832 | if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
2833 | scic->device_table[node_index] = sci_dev; | |
2834 | ||
2835 | *node_id = node_index; | |
2836 | ||
2837 | return SCI_SUCCESS; | |
2838 | } | |
2839 | ||
2840 | return SCI_FAILURE_INSUFFICIENT_RESOURCES; | |
2841 | } | |
2842 | ||
2843 | /** | |
2844 | * This method frees the remote node index back to the available pool. Once | |
2845 | * this is done the remote node context buffer is no longer valid and can | |
2846 | * not be used. | |
2847 | * @scic: | |
2848 | * @sci_dev: | |
2849 | * @node_id: | |
2850 | * | |
2851 | */ | |
2852 | void scic_sds_controller_free_remote_node_context( | |
2853 | struct scic_sds_controller *scic, | |
2854 | struct scic_sds_remote_device *sci_dev, | |
2855 | u16 node_id) | |
2856 | { | |
2857 | u32 remote_node_count = scic_sds_remote_device_node_count(sci_dev); | |
2858 | ||
2859 | if (scic->device_table[node_id] == sci_dev) { | |
2860 | scic->device_table[node_id] = NULL; | |
2861 | ||
2862 | scic_sds_remote_node_table_release_remote_node_index( | |
2863 | &scic->available_remote_nodes, remote_node_count, node_id | |
2864 | ); | |
2865 | } | |
2866 | } | |
2867 | ||
2868 | /** | |
2869 | * This method returns the union scu_remote_node_context for the specified remote | |
2870 | * node id. | |
2871 | * @scic: | |
2872 | * @node_id: | |
2873 | * | |
2874 | * union scu_remote_node_context* | |
2875 | */ | |
2876 | union scu_remote_node_context *scic_sds_controller_get_remote_node_context_buffer( | |
2877 | struct scic_sds_controller *scic, | |
2878 | u16 node_id | |
2879 | ) { | |
2880 | if ( | |
2881 | (node_id < scic->remote_node_entries) | |
2882 | && (scic->device_table[node_id] != NULL) | |
2883 | ) { | |
2884 | return &scic->remote_node_context_table[node_id]; | |
2885 | } | |
2886 | ||
2887 | return NULL; | |
2888 | } | |
2889 | ||
2890 | /** | |
2891 | * | |
2892 | * @resposne_buffer: This is the buffer into which the D2H register FIS will be | |
2893 | * constructed. | |
2894 | * @frame_header: This is the frame header returned by the hardware. | |
2895 | * @frame_buffer: This is the frame buffer returned by the hardware. | |
2896 | * | |
2897 | * This method will combind the frame header and frame buffer to create a SATA | |
2898 | * D2H register FIS none | |
2899 | */ | |
2900 | void scic_sds_controller_copy_sata_response( | |
2901 | void *response_buffer, | |
2902 | void *frame_header, | |
2903 | void *frame_buffer) | |
2904 | { | |
2905 | memcpy(response_buffer, frame_header, sizeof(u32)); | |
2906 | ||
2907 | memcpy(response_buffer + sizeof(u32), | |
2908 | frame_buffer, | |
2909 | sizeof(struct dev_to_host_fis) - sizeof(u32)); | |
2910 | } | |
2911 | ||
2912 | /** | |
2913 | * This method releases the frame once this is done the frame is available for | |
2914 | * re-use by the hardware. The data contained in the frame header and frame | |
2915 | * buffer is no longer valid. The UF queue get pointer is only updated if UF | |
2916 | * control indicates this is appropriate. | |
2917 | * @scic: | |
2918 | * @frame_index: | |
2919 | * | |
2920 | */ | |
2921 | void scic_sds_controller_release_frame( | |
2922 | struct scic_sds_controller *scic, | |
2923 | u32 frame_index) | |
2924 | { | |
2925 | if (scic_sds_unsolicited_frame_control_release_frame( | |
2926 | &scic->uf_control, frame_index) == true) | |
2927 | writel(scic->uf_control.get, | |
2928 | &scic->scu_registers->sdma.unsolicited_frame_get_pointer); | |
2929 | } | |
2930 | ||
2931 | /** | |
2932 | * scic_controller_start_io() - This method is called by the SCI user to | |
2933 | * send/start an IO request. If the method invocation is successful, then | |
2934 | * the IO request has been queued to the hardware for processing. | |
2935 | * @controller: the handle to the controller object for which to start an IO | |
2936 | * request. | |
2937 | * @remote_device: the handle to the remote device object for which to start an | |
2938 | * IO request. | |
2939 | * @io_request: the handle to the io request object to start. | |
2940 | * @io_tag: This parameter specifies a previously allocated IO tag that the | |
2941 | * user desires to be utilized for this request. This parameter is optional. | |
2942 | * The user is allowed to supply SCI_CONTROLLER_INVALID_IO_TAG as the value | |
2943 | * for this parameter. | |
2944 | * | |
2945 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
2946 | * to ensure that each of the methods that may allocate or free available IO | |
2947 | * tags are handled in a mutually exclusive manner. This method is one of said | |
2948 | * methods requiring proper critical code section protection (e.g. semaphore, | |
2949 | * spin-lock, etc.). - For SATA, the user is required to manage NCQ tags. As a | |
2950 | * result, it is expected the user will have set the NCQ tag field in the host | |
2951 | * to device register FIS prior to calling this method. There is also a | |
2952 | * requirement for the user to call scic_stp_io_set_ncq_tag() prior to invoking | |
2953 | * the scic_controller_start_io() method. scic_controller_allocate_tag() for | |
2954 | * more information on allocating a tag. Indicate if the controller | |
2955 | * successfully started the IO request. SCI_SUCCESS if the IO request was | |
2956 | * successfully started. Determine the failure situations and return values. | |
2957 | */ | |
2958 | enum sci_status scic_controller_start_io( | |
2959 | struct scic_sds_controller *scic, | |
2960 | struct scic_sds_remote_device *rdev, | |
2961 | struct scic_sds_request *req, | |
2962 | u16 io_tag) | |
2963 | { | |
2964 | enum sci_status status; | |
2965 | ||
2966 | if (scic->state_machine.current_state_id != | |
2967 | SCI_BASE_CONTROLLER_STATE_READY) { | |
2968 | dev_warn(scic_to_dev(scic), "invalid state to start I/O"); | |
2969 | return SCI_FAILURE_INVALID_STATE; | |
2970 | } | |
2971 | ||
2972 | status = scic_sds_remote_device_start_io(scic, rdev, req); | |
2973 | if (status != SCI_SUCCESS) | |
2974 | return status; | |
2975 | ||
2976 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
2977 | scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(req)); | |
2978 | return SCI_SUCCESS; | |
2979 | } | |
2980 | ||
2981 | /** | |
2982 | * scic_controller_terminate_request() - This method is called by the SCI Core | |
2983 | * user to terminate an ongoing (i.e. started) core IO request. This does | |
2984 | * not abort the IO request at the target, but rather removes the IO request | |
2985 | * from the host controller. | |
2986 | * @controller: the handle to the controller object for which to terminate a | |
2987 | * request. | |
2988 | * @remote_device: the handle to the remote device object for which to | |
2989 | * terminate a request. | |
2990 | * @request: the handle to the io or task management request object to | |
2991 | * terminate. | |
2992 | * | |
2993 | * Indicate if the controller successfully began the terminate process for the | |
2994 | * IO request. SCI_SUCCESS if the terminate process was successfully started | |
2995 | * for the request. Determine the failure situations and return values. | |
2996 | */ | |
2997 | enum sci_status scic_controller_terminate_request( | |
2998 | struct scic_sds_controller *scic, | |
2999 | struct scic_sds_remote_device *rdev, | |
3000 | struct scic_sds_request *req) | |
3001 | { | |
3002 | enum sci_status status; | |
3003 | ||
3004 | if (scic->state_machine.current_state_id != | |
3005 | SCI_BASE_CONTROLLER_STATE_READY) { | |
3006 | dev_warn(scic_to_dev(scic), | |
3007 | "invalid state to terminate request\n"); | |
3008 | return SCI_FAILURE_INVALID_STATE; | |
3009 | } | |
3010 | ||
3011 | status = scic_sds_io_request_terminate(req); | |
3012 | if (status != SCI_SUCCESS) | |
3013 | return status; | |
3014 | ||
3015 | /* | |
3016 | * Utilize the original post context command and or in the POST_TC_ABORT | |
3017 | * request sub-type. | |
3018 | */ | |
3019 | scic_sds_controller_post_request(scic, | |
3020 | scic_sds_request_get_post_context(req) | | |
3021 | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); | |
3022 | return SCI_SUCCESS; | |
3023 | } | |
3024 | ||
3025 | /** | |
3026 | * scic_controller_complete_io() - This method will perform core specific | |
3027 | * completion operations for an IO request. After this method is invoked, | |
3028 | * the user should consider the IO request as invalid until it is properly | |
3029 | * reused (i.e. re-constructed). | |
3030 | * @controller: The handle to the controller object for which to complete the | |
3031 | * IO request. | |
3032 | * @remote_device: The handle to the remote device object for which to complete | |
3033 | * the IO request. | |
3034 | * @io_request: the handle to the io request object to complete. | |
3035 | * | |
3036 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
3037 | * to ensure that each of the methods that may allocate or free available IO | |
3038 | * tags are handled in a mutually exclusive manner. This method is one of said | |
3039 | * methods requiring proper critical code section protection (e.g. semaphore, | |
3040 | * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI | |
3041 | * Core user, using the scic_controller_allocate_io_tag() method, then it is | |
3042 | * the responsibility of the caller to invoke the scic_controller_free_io_tag() | |
3043 | * method to free the tag (i.e. this method will not free the IO tag). Indicate | |
3044 | * if the controller successfully completed the IO request. SCI_SUCCESS if the | |
3045 | * completion process was successful. | |
3046 | */ | |
3047 | enum sci_status scic_controller_complete_io( | |
3048 | struct scic_sds_controller *scic, | |
3049 | struct scic_sds_remote_device *rdev, | |
3050 | struct scic_sds_request *request) | |
3051 | { | |
3052 | enum sci_status status; | |
3053 | u16 index; | |
3054 | ||
3055 | switch (scic->state_machine.current_state_id) { | |
3056 | case SCI_BASE_CONTROLLER_STATE_STOPPING: | |
3057 | /* XXX: Implement this function */ | |
3058 | return SCI_FAILURE; | |
3059 | case SCI_BASE_CONTROLLER_STATE_READY: | |
3060 | status = scic_sds_remote_device_complete_io(scic, rdev, request); | |
3061 | if (status != SCI_SUCCESS) | |
3062 | return status; | |
3063 | ||
3064 | index = scic_sds_io_tag_get_index(request->io_tag); | |
3065 | scic->io_request_table[index] = NULL; | |
3066 | return SCI_SUCCESS; | |
3067 | default: | |
3068 | dev_warn(scic_to_dev(scic), "invalid state to complete I/O"); | |
3069 | return SCI_FAILURE_INVALID_STATE; | |
3070 | } | |
3071 | ||
3072 | } | |
3073 | ||
3074 | enum sci_status scic_controller_continue_io(struct scic_sds_request *sci_req) | |
3075 | { | |
3076 | struct scic_sds_controller *scic = sci_req->owning_controller; | |
3077 | ||
3078 | if (scic->state_machine.current_state_id != | |
3079 | SCI_BASE_CONTROLLER_STATE_READY) { | |
3080 | dev_warn(scic_to_dev(scic), "invalid state to continue I/O"); | |
3081 | return SCI_FAILURE_INVALID_STATE; | |
3082 | } | |
3083 | ||
3084 | scic->io_request_table[scic_sds_io_tag_get_index(sci_req->io_tag)] = sci_req; | |
3085 | scic_sds_controller_post_request(scic, scic_sds_request_get_post_context(sci_req)); | |
3086 | return SCI_SUCCESS; | |
3087 | } | |
3088 | ||
3089 | /** | |
3090 | * scic_controller_start_task() - This method is called by the SCIC user to | |
3091 | * send/start a framework task management request. | |
3092 | * @controller: the handle to the controller object for which to start the task | |
3093 | * management request. | |
3094 | * @remote_device: the handle to the remote device object for which to start | |
3095 | * the task management request. | |
3096 | * @task_request: the handle to the task request object to start. | |
3097 | * @io_tag: This parameter specifies a previously allocated IO tag that the | |
3098 | * user desires to be utilized for this request. Note this not the io_tag | |
3099 | * of the request being managed. It is to be utilized for the task request | |
3100 | * itself. This parameter is optional. The user is allowed to supply | |
3101 | * SCI_CONTROLLER_INVALID_IO_TAG as the value for this parameter. | |
3102 | * | |
3103 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
3104 | * to ensure that each of the methods that may allocate or free available IO | |
3105 | * tags are handled in a mutually exclusive manner. This method is one of said | |
3106 | * methods requiring proper critical code section protection (e.g. semaphore, | |
3107 | * spin-lock, etc.). - The user must synchronize this task with completion | |
3108 | * queue processing. If they are not synchronized then it is possible for the | |
3109 | * io requests that are being managed by the task request can complete before | |
3110 | * starting the task request. scic_controller_allocate_tag() for more | |
3111 | * information on allocating a tag. Indicate if the controller successfully | |
3112 | * started the IO request. SCI_TASK_SUCCESS if the task request was | |
3113 | * successfully started. SCI_TASK_FAILURE_REQUIRES_SCSI_ABORT This value is | |
3114 | * returned if there is/are task(s) outstanding that require termination or | |
3115 | * completion before this request can succeed. | |
3116 | */ | |
3117 | enum sci_task_status scic_controller_start_task( | |
3118 | struct scic_sds_controller *scic, | |
3119 | struct scic_sds_remote_device *rdev, | |
3120 | struct scic_sds_request *req, | |
3121 | u16 task_tag) | |
3122 | { | |
3123 | enum sci_status status; | |
3124 | ||
3125 | if (scic->state_machine.current_state_id != | |
3126 | SCI_BASE_CONTROLLER_STATE_READY) { | |
3127 | dev_warn(scic_to_dev(scic), | |
3128 | "%s: SCIC Controller starting task from invalid " | |
3129 | "state\n", | |
3130 | __func__); | |
3131 | return SCI_TASK_FAILURE_INVALID_STATE; | |
3132 | } | |
3133 | ||
3134 | status = scic_sds_remote_device_start_task(scic, rdev, req); | |
3135 | switch (status) { | |
3136 | case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: | |
3137 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
3138 | ||
3139 | /* | |
3140 | * We will let framework know this task request started successfully, | |
3141 | * although core is still woring on starting the request (to post tc when | |
3142 | * RNC is resumed.) | |
3143 | */ | |
3144 | return SCI_SUCCESS; | |
3145 | case SCI_SUCCESS: | |
3146 | scic->io_request_table[scic_sds_io_tag_get_index(req->io_tag)] = req; | |
3147 | ||
3148 | scic_sds_controller_post_request(scic, | |
3149 | scic_sds_request_get_post_context(req)); | |
3150 | break; | |
3151 | default: | |
3152 | break; | |
3153 | } | |
3154 | ||
3155 | return status; | |
3156 | } | |
3157 | ||
3158 | /** | |
3159 | * scic_controller_allocate_io_tag() - This method will allocate a tag from the | |
3160 | * pool of free IO tags. Direct allocation of IO tags by the SCI Core user | |
3161 | * is optional. The scic_controller_start_io() method will allocate an IO | |
3162 | * tag if this method is not utilized and the tag is not supplied to the IO | |
3163 | * construct routine. Direct allocation of IO tags may provide additional | |
3164 | * performance improvements in environments capable of supporting this usage | |
3165 | * model. Additionally, direct allocation of IO tags also provides | |
3166 | * additional flexibility to the SCI Core user. Specifically, the user may | |
3167 | * retain IO tags across the lives of multiple IO requests. | |
3168 | * @controller: the handle to the controller object for which to allocate the | |
3169 | * tag. | |
3170 | * | |
3171 | * IO tags are a protected resource. It is incumbent upon the SCI Core user to | |
3172 | * ensure that each of the methods that may allocate or free available IO tags | |
3173 | * are handled in a mutually exclusive manner. This method is one of said | |
3174 | * methods requiring proper critical code section protection (e.g. semaphore, | |
3175 | * spin-lock, etc.). An unsigned integer representing an available IO tag. | |
3176 | * SCI_CONTROLLER_INVALID_IO_TAG This value is returned if there are no | |
3177 | * currently available tags to be allocated. All return other values indicate a | |
3178 | * legitimate tag. | |
3179 | */ | |
3180 | u16 scic_controller_allocate_io_tag( | |
3181 | struct scic_sds_controller *scic) | |
3182 | { | |
3183 | u16 task_context; | |
3184 | u16 sequence_count; | |
3185 | ||
3186 | if (!sci_pool_empty(scic->tci_pool)) { | |
3187 | sci_pool_get(scic->tci_pool, task_context); | |
3188 | ||
3189 | sequence_count = scic->io_request_sequence[task_context]; | |
3190 | ||
3191 | return scic_sds_io_tag_construct(sequence_count, task_context); | |
3192 | } | |
3193 | ||
3194 | return SCI_CONTROLLER_INVALID_IO_TAG; | |
3195 | } | |
3196 | ||
3197 | /** | |
3198 | * scic_controller_free_io_tag() - This method will free an IO tag to the pool | |
3199 | * of free IO tags. This method provides the SCI Core user more flexibility | |
3200 | * with regards to IO tags. The user may desire to keep an IO tag after an | |
3201 | * IO request has completed, because they plan on re-using the tag for a | |
3202 | * subsequent IO request. This method is only legal if the tag was | |
3203 | * allocated via scic_controller_allocate_io_tag(). | |
3204 | * @controller: This parameter specifies the handle to the controller object | |
3205 | * for which to free/return the tag. | |
3206 | * @io_tag: This parameter represents the tag to be freed to the pool of | |
3207 | * available tags. | |
3208 | * | |
3209 | * - IO tags are a protected resource. It is incumbent upon the SCI Core user | |
3210 | * to ensure that each of the methods that may allocate or free available IO | |
3211 | * tags are handled in a mutually exclusive manner. This method is one of said | |
3212 | * methods requiring proper critical code section protection (e.g. semaphore, | |
3213 | * spin-lock, etc.). - If the IO tag for a request was allocated, by the SCI | |
3214 | * Core user, using the scic_controller_allocate_io_tag() method, then it is | |
3215 | * the responsibility of the caller to invoke this method to free the tag. This | |
3216 | * method returns an indication of whether the tag was successfully put back | |
3217 | * (freed) to the pool of available tags. SCI_SUCCESS This return value | |
3218 | * indicates the tag was successfully placed into the pool of available IO | |
3219 | * tags. SCI_FAILURE_INVALID_IO_TAG This value is returned if the supplied tag | |
3220 | * is not a valid IO tag value. | |
3221 | */ | |
3222 | enum sci_status scic_controller_free_io_tag( | |
3223 | struct scic_sds_controller *scic, | |
3224 | u16 io_tag) | |
3225 | { | |
3226 | u16 sequence; | |
3227 | u16 index; | |
3228 | ||
3229 | BUG_ON(io_tag == SCI_CONTROLLER_INVALID_IO_TAG); | |
3230 | ||
3231 | sequence = scic_sds_io_tag_get_sequence(io_tag); | |
3232 | index = scic_sds_io_tag_get_index(io_tag); | |
3233 | ||
3234 | if (!sci_pool_full(scic->tci_pool)) { | |
3235 | if (sequence == scic->io_request_sequence[index]) { | |
3236 | scic_sds_io_sequence_increment( | |
3237 | scic->io_request_sequence[index]); | |
3238 | ||
3239 | sci_pool_put(scic->tci_pool, index); | |
3240 | ||
3241 | return SCI_SUCCESS; | |
3242 | } | |
3243 | } | |
3244 | ||
3245 | return SCI_FAILURE_INVALID_IO_TAG; | |
3246 | } | |
3247 | ||
3248 |