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6f231dda DW |
1 | /* |
2 | * This file is provided under a dual BSD/GPLv2 license. When using or | |
3 | * redistributing this file, you may do so under either license. | |
4 | * | |
5 | * GPL LICENSE SUMMARY | |
6 | * | |
7 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of version 2 of the GNU General Public License as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
21 | * The full GNU General Public License is included in this distribution | |
22 | * in the file called LICENSE.GPL. | |
23 | * | |
24 | * BSD LICENSE | |
25 | * | |
26 | * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved. | |
27 | * All rights reserved. | |
28 | * | |
29 | * Redistribution and use in source and binary forms, with or without | |
30 | * modification, are permitted provided that the following conditions | |
31 | * are met: | |
32 | * | |
33 | * * Redistributions of source code must retain the above copyright | |
34 | * notice, this list of conditions and the following disclaimer. | |
35 | * * Redistributions in binary form must reproduce the above copyright | |
36 | * notice, this list of conditions and the following disclaimer in | |
37 | * the documentation and/or other materials provided with the | |
38 | * distribution. | |
39 | * * Neither the name of Intel Corporation nor the names of its | |
40 | * contributors may be used to endorse or promote products derived | |
41 | * from this software without specific prior written permission. | |
42 | * | |
43 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
44 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
45 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
46 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
47 | * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
48 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
49 | * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
50 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
51 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
52 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
53 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
54 | */ | |
ac668c69 | 55 | #include <linux/circ_buf.h> |
cc9203bf DW |
56 | #include <linux/device.h> |
57 | #include <scsi/sas.h> | |
58 | #include "host.h" | |
6f231dda | 59 | #include "isci.h" |
6f231dda | 60 | #include "port.h" |
6f231dda | 61 | #include "host.h" |
d044af17 | 62 | #include "probe_roms.h" |
cc9203bf DW |
63 | #include "remote_device.h" |
64 | #include "request.h" | |
cc9203bf DW |
65 | #include "scu_completion_codes.h" |
66 | #include "scu_event_codes.h" | |
63a3a15f | 67 | #include "registers.h" |
cc9203bf DW |
68 | #include "scu_remote_node_context.h" |
69 | #include "scu_task_context.h" | |
6f231dda | 70 | |
cc9203bf DW |
71 | #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200 |
72 | ||
7c78da31 | 73 | #define smu_max_ports(dcc_value) \ |
cc9203bf DW |
74 | (\ |
75 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \ | |
76 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \ | |
77 | ) | |
78 | ||
7c78da31 | 79 | #define smu_max_task_contexts(dcc_value) \ |
cc9203bf DW |
80 | (\ |
81 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \ | |
82 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \ | |
83 | ) | |
84 | ||
7c78da31 | 85 | #define smu_max_rncs(dcc_value) \ |
cc9203bf DW |
86 | (\ |
87 | (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \ | |
88 | >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \ | |
89 | ) | |
90 | ||
cc9203bf DW |
91 | #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100 |
92 | ||
93 | /** | |
94 | * | |
95 | * | |
96 | * The number of milliseconds to wait while a given phy is consuming power | |
97 | * before allowing another set of phys to consume power. Ultimately, this will | |
98 | * be specified by OEM parameter. | |
99 | */ | |
100 | #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500 | |
101 | ||
102 | /** | |
103 | * NORMALIZE_PUT_POINTER() - | |
104 | * | |
105 | * This macro will normalize the completion queue put pointer so its value can | |
106 | * be used as an array inde | |
107 | */ | |
108 | #define NORMALIZE_PUT_POINTER(x) \ | |
109 | ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK) | |
110 | ||
111 | ||
112 | /** | |
113 | * NORMALIZE_EVENT_POINTER() - | |
114 | * | |
115 | * This macro will normalize the completion queue event entry so its value can | |
116 | * be used as an index. | |
117 | */ | |
118 | #define NORMALIZE_EVENT_POINTER(x) \ | |
119 | (\ | |
120 | ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \ | |
121 | >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \ | |
122 | ) | |
123 | ||
cc9203bf DW |
124 | /** |
125 | * NORMALIZE_GET_POINTER() - | |
126 | * | |
127 | * This macro will normalize the completion queue get pointer so its value can | |
128 | * be used as an index into an array | |
129 | */ | |
130 | #define NORMALIZE_GET_POINTER(x) \ | |
131 | ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK) | |
132 | ||
133 | /** | |
134 | * NORMALIZE_GET_POINTER_CYCLE_BIT() - | |
135 | * | |
136 | * This macro will normalize the completion queue cycle pointer so it matches | |
137 | * the completion queue cycle bit | |
138 | */ | |
139 | #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \ | |
140 | ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT)) | |
141 | ||
142 | /** | |
143 | * COMPLETION_QUEUE_CYCLE_BIT() - | |
144 | * | |
145 | * This macro will return the cycle bit of the completion queue entry | |
146 | */ | |
147 | #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000) | |
148 | ||
12ef6544 EN |
149 | /* Init the state machine and call the state entry function (if any) */ |
150 | void sci_init_sm(struct sci_base_state_machine *sm, | |
151 | const struct sci_base_state *state_table, u32 initial_state) | |
152 | { | |
153 | sci_state_transition_t handler; | |
154 | ||
155 | sm->initial_state_id = initial_state; | |
156 | sm->previous_state_id = initial_state; | |
157 | sm->current_state_id = initial_state; | |
158 | sm->state_table = state_table; | |
159 | ||
160 | handler = sm->state_table[initial_state].enter_state; | |
161 | if (handler) | |
162 | handler(sm); | |
163 | } | |
164 | ||
165 | /* Call the state exit fn, update the current state, call the state entry fn */ | |
166 | void sci_change_state(struct sci_base_state_machine *sm, u32 next_state) | |
167 | { | |
168 | sci_state_transition_t handler; | |
169 | ||
170 | handler = sm->state_table[sm->current_state_id].exit_state; | |
171 | if (handler) | |
172 | handler(sm); | |
173 | ||
174 | sm->previous_state_id = sm->current_state_id; | |
175 | sm->current_state_id = next_state; | |
176 | ||
177 | handler = sm->state_table[sm->current_state_id].enter_state; | |
178 | if (handler) | |
179 | handler(sm); | |
180 | } | |
181 | ||
89a7301f | 182 | static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost) |
cc9203bf | 183 | { |
d9dcb4ba | 184 | u32 get_value = ihost->completion_queue_get; |
cc9203bf DW |
185 | u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK; |
186 | ||
187 | if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) == | |
d9dcb4ba | 188 | COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])) |
cc9203bf DW |
189 | return true; |
190 | ||
191 | return false; | |
192 | } | |
193 | ||
89a7301f | 194 | static bool sci_controller_isr(struct isci_host *ihost) |
cc9203bf | 195 | { |
89a7301f | 196 | if (sci_controller_completion_queue_has_entries(ihost)) { |
cc9203bf DW |
197 | return true; |
198 | } else { | |
199 | /* | |
200 | * we have a spurious interrupt it could be that we have already | |
201 | * emptied the completion queue from a previous interrupt */ | |
d9dcb4ba | 202 | writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); |
cc9203bf DW |
203 | |
204 | /* | |
205 | * There is a race in the hardware that could cause us not to be notified | |
206 | * of an interrupt completion if we do not take this step. We will mask | |
207 | * then unmask the interrupts so if there is another interrupt pending | |
208 | * the clearing of the interrupt source we get the next interrupt message. */ | |
d9dcb4ba DW |
209 | writel(0xFF000000, &ihost->smu_registers->interrupt_mask); |
210 | writel(0, &ihost->smu_registers->interrupt_mask); | |
cc9203bf DW |
211 | } |
212 | ||
213 | return false; | |
214 | } | |
215 | ||
c7ef4031 | 216 | irqreturn_t isci_msix_isr(int vec, void *data) |
6f231dda | 217 | { |
c7ef4031 | 218 | struct isci_host *ihost = data; |
c7ef4031 | 219 | |
89a7301f | 220 | if (sci_controller_isr(ihost)) |
0cf89d1d | 221 | tasklet_schedule(&ihost->completion_tasklet); |
6f231dda | 222 | |
c7ef4031 | 223 | return IRQ_HANDLED; |
6f231dda DW |
224 | } |
225 | ||
89a7301f | 226 | static bool sci_controller_error_isr(struct isci_host *ihost) |
cc9203bf DW |
227 | { |
228 | u32 interrupt_status; | |
229 | ||
230 | interrupt_status = | |
d9dcb4ba | 231 | readl(&ihost->smu_registers->interrupt_status); |
cc9203bf DW |
232 | interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND); |
233 | ||
234 | if (interrupt_status != 0) { | |
235 | /* | |
236 | * There is an error interrupt pending so let it through and handle | |
237 | * in the callback */ | |
238 | return true; | |
239 | } | |
240 | ||
241 | /* | |
242 | * There is a race in the hardware that could cause us not to be notified | |
243 | * of an interrupt completion if we do not take this step. We will mask | |
244 | * then unmask the error interrupts so if there was another interrupt | |
245 | * pending we will be notified. | |
246 | * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */ | |
d9dcb4ba DW |
247 | writel(0xff, &ihost->smu_registers->interrupt_mask); |
248 | writel(0, &ihost->smu_registers->interrupt_mask); | |
cc9203bf DW |
249 | |
250 | return false; | |
251 | } | |
252 | ||
89a7301f | 253 | static void sci_controller_task_completion(struct isci_host *ihost, u32 ent) |
cc9203bf | 254 | { |
89a7301f | 255 | u32 index = SCU_GET_COMPLETION_INDEX(ent); |
db056250 | 256 | struct isci_request *ireq = ihost->reqs[index]; |
cc9203bf DW |
257 | |
258 | /* Make sure that we really want to process this IO request */ | |
db056250 | 259 | if (test_bit(IREQ_ACTIVE, &ireq->flags) && |
5076a1a9 | 260 | ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG && |
d9dcb4ba | 261 | ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index]) |
89a7301f DW |
262 | /* Yep this is a valid io request pass it along to the |
263 | * io request handler | |
264 | */ | |
265 | sci_io_request_tc_completion(ireq, ent); | |
cc9203bf DW |
266 | } |
267 | ||
89a7301f | 268 | static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent) |
cc9203bf DW |
269 | { |
270 | u32 index; | |
5076a1a9 | 271 | struct isci_request *ireq; |
78a6f06e | 272 | struct isci_remote_device *idev; |
cc9203bf | 273 | |
89a7301f | 274 | index = SCU_GET_COMPLETION_INDEX(ent); |
cc9203bf | 275 | |
89a7301f | 276 | switch (scu_get_command_request_type(ent)) { |
cc9203bf DW |
277 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC: |
278 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC: | |
d9dcb4ba DW |
279 | ireq = ihost->reqs[index]; |
280 | dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n", | |
89a7301f | 281 | __func__, ent, ireq); |
cc9203bf DW |
282 | /* @todo For a post TC operation we need to fail the IO |
283 | * request | |
284 | */ | |
285 | break; | |
cc9203bf DW |
286 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC: |
287 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC: | |
288 | case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC: | |
d9dcb4ba DW |
289 | idev = ihost->device_table[index]; |
290 | dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n", | |
89a7301f | 291 | __func__, ent, idev); |
cc9203bf DW |
292 | /* @todo For a port RNC operation we need to fail the |
293 | * device | |
294 | */ | |
295 | break; | |
cc9203bf | 296 | default: |
d9dcb4ba | 297 | dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n", |
89a7301f | 298 | __func__, ent); |
cc9203bf | 299 | break; |
cc9203bf DW |
300 | } |
301 | } | |
302 | ||
89a7301f | 303 | static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent) |
cc9203bf DW |
304 | { |
305 | u32 index; | |
306 | u32 frame_index; | |
307 | ||
cc9203bf | 308 | struct scu_unsolicited_frame_header *frame_header; |
85280955 | 309 | struct isci_phy *iphy; |
78a6f06e | 310 | struct isci_remote_device *idev; |
cc9203bf DW |
311 | |
312 | enum sci_status result = SCI_FAILURE; | |
313 | ||
89a7301f | 314 | frame_index = SCU_GET_FRAME_INDEX(ent); |
cc9203bf | 315 | |
d9dcb4ba DW |
316 | frame_header = ihost->uf_control.buffers.array[frame_index].header; |
317 | ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE; | |
cc9203bf | 318 | |
89a7301f | 319 | if (SCU_GET_FRAME_ERROR(ent)) { |
cc9203bf DW |
320 | /* |
321 | * / @todo If the IAF frame or SIGNATURE FIS frame has an error will | |
322 | * / this cause a problem? We expect the phy initialization will | |
323 | * / fail if there is an error in the frame. */ | |
89a7301f | 324 | sci_controller_release_frame(ihost, frame_index); |
cc9203bf DW |
325 | return; |
326 | } | |
327 | ||
328 | if (frame_header->is_address_frame) { | |
89a7301f | 329 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); |
85280955 | 330 | iphy = &ihost->phys[index]; |
89a7301f | 331 | result = sci_phy_frame_handler(iphy, frame_index); |
cc9203bf DW |
332 | } else { |
333 | ||
89a7301f | 334 | index = SCU_GET_COMPLETION_INDEX(ent); |
cc9203bf DW |
335 | |
336 | if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
337 | /* | |
338 | * This is a signature fis or a frame from a direct attached SATA | |
339 | * device that has not yet been created. In either case forwared | |
340 | * the frame to the PE and let it take care of the frame data. */ | |
89a7301f | 341 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); |
85280955 | 342 | iphy = &ihost->phys[index]; |
89a7301f | 343 | result = sci_phy_frame_handler(iphy, frame_index); |
cc9203bf | 344 | } else { |
d9dcb4ba DW |
345 | if (index < ihost->remote_node_entries) |
346 | idev = ihost->device_table[index]; | |
cc9203bf | 347 | else |
78a6f06e | 348 | idev = NULL; |
cc9203bf | 349 | |
78a6f06e | 350 | if (idev != NULL) |
89a7301f | 351 | result = sci_remote_device_frame_handler(idev, frame_index); |
cc9203bf | 352 | else |
89a7301f | 353 | sci_controller_release_frame(ihost, frame_index); |
cc9203bf DW |
354 | } |
355 | } | |
356 | ||
357 | if (result != SCI_SUCCESS) { | |
358 | /* | |
359 | * / @todo Is there any reason to report some additional error message | |
360 | * / when we get this failure notifiction? */ | |
361 | } | |
362 | } | |
363 | ||
89a7301f | 364 | static void sci_controller_event_completion(struct isci_host *ihost, u32 ent) |
cc9203bf | 365 | { |
78a6f06e | 366 | struct isci_remote_device *idev; |
5076a1a9 | 367 | struct isci_request *ireq; |
85280955 | 368 | struct isci_phy *iphy; |
cc9203bf DW |
369 | u32 index; |
370 | ||
89a7301f | 371 | index = SCU_GET_COMPLETION_INDEX(ent); |
cc9203bf | 372 | |
89a7301f | 373 | switch (scu_get_event_type(ent)) { |
cc9203bf DW |
374 | case SCU_EVENT_TYPE_SMU_COMMAND_ERROR: |
375 | /* / @todo The driver did something wrong and we need to fix the condtion. */ | |
d9dcb4ba | 376 | dev_err(&ihost->pdev->dev, |
cc9203bf DW |
377 | "%s: SCIC Controller 0x%p received SMU command error " |
378 | "0x%x\n", | |
379 | __func__, | |
d9dcb4ba | 380 | ihost, |
89a7301f | 381 | ent); |
cc9203bf DW |
382 | break; |
383 | ||
384 | case SCU_EVENT_TYPE_SMU_PCQ_ERROR: | |
385 | case SCU_EVENT_TYPE_SMU_ERROR: | |
386 | case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR: | |
387 | /* | |
388 | * / @todo This is a hardware failure and its likely that we want to | |
389 | * / reset the controller. */ | |
d9dcb4ba | 390 | dev_err(&ihost->pdev->dev, |
cc9203bf DW |
391 | "%s: SCIC Controller 0x%p received fatal controller " |
392 | "event 0x%x\n", | |
393 | __func__, | |
d9dcb4ba | 394 | ihost, |
89a7301f | 395 | ent); |
cc9203bf DW |
396 | break; |
397 | ||
398 | case SCU_EVENT_TYPE_TRANSPORT_ERROR: | |
5076a1a9 | 399 | ireq = ihost->reqs[index]; |
89a7301f | 400 | sci_io_request_event_handler(ireq, ent); |
cc9203bf DW |
401 | break; |
402 | ||
403 | case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT: | |
89a7301f | 404 | switch (scu_get_event_specifier(ent)) { |
cc9203bf DW |
405 | case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE: |
406 | case SCU_EVENT_SPECIFIC_TASK_TIMEOUT: | |
5076a1a9 DW |
407 | ireq = ihost->reqs[index]; |
408 | if (ireq != NULL) | |
89a7301f | 409 | sci_io_request_event_handler(ireq, ent); |
cc9203bf | 410 | else |
d9dcb4ba | 411 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
412 | "%s: SCIC Controller 0x%p received " |
413 | "event 0x%x for io request object " | |
414 | "that doesnt exist.\n", | |
415 | __func__, | |
d9dcb4ba | 416 | ihost, |
89a7301f | 417 | ent); |
cc9203bf DW |
418 | |
419 | break; | |
420 | ||
421 | case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT: | |
d9dcb4ba | 422 | idev = ihost->device_table[index]; |
78a6f06e | 423 | if (idev != NULL) |
89a7301f | 424 | sci_remote_device_event_handler(idev, ent); |
cc9203bf | 425 | else |
d9dcb4ba | 426 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
427 | "%s: SCIC Controller 0x%p received " |
428 | "event 0x%x for remote device object " | |
429 | "that doesnt exist.\n", | |
430 | __func__, | |
d9dcb4ba | 431 | ihost, |
89a7301f | 432 | ent); |
cc9203bf DW |
433 | |
434 | break; | |
435 | } | |
436 | break; | |
437 | ||
438 | case SCU_EVENT_TYPE_BROADCAST_CHANGE: | |
439 | /* | |
440 | * direct the broadcast change event to the phy first and then let | |
441 | * the phy redirect the broadcast change to the port object */ | |
442 | case SCU_EVENT_TYPE_ERR_CNT_EVENT: | |
443 | /* | |
444 | * direct error counter event to the phy object since that is where | |
445 | * we get the event notification. This is a type 4 event. */ | |
446 | case SCU_EVENT_TYPE_OSSP_EVENT: | |
89a7301f | 447 | index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent); |
85280955 | 448 | iphy = &ihost->phys[index]; |
89a7301f | 449 | sci_phy_event_handler(iphy, ent); |
cc9203bf DW |
450 | break; |
451 | ||
452 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX: | |
453 | case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX: | |
454 | case SCU_EVENT_TYPE_RNC_OPS_MISC: | |
d9dcb4ba DW |
455 | if (index < ihost->remote_node_entries) { |
456 | idev = ihost->device_table[index]; | |
cc9203bf | 457 | |
78a6f06e | 458 | if (idev != NULL) |
89a7301f | 459 | sci_remote_device_event_handler(idev, ent); |
cc9203bf | 460 | } else |
d9dcb4ba | 461 | dev_err(&ihost->pdev->dev, |
cc9203bf DW |
462 | "%s: SCIC Controller 0x%p received event 0x%x " |
463 | "for remote device object 0x%0x that doesnt " | |
464 | "exist.\n", | |
465 | __func__, | |
d9dcb4ba | 466 | ihost, |
89a7301f | 467 | ent, |
cc9203bf DW |
468 | index); |
469 | ||
470 | break; | |
471 | ||
472 | default: | |
d9dcb4ba | 473 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
474 | "%s: SCIC Controller received unknown event code %x\n", |
475 | __func__, | |
89a7301f | 476 | ent); |
cc9203bf DW |
477 | break; |
478 | } | |
479 | } | |
480 | ||
89a7301f | 481 | static void sci_controller_process_completions(struct isci_host *ihost) |
cc9203bf DW |
482 | { |
483 | u32 completion_count = 0; | |
89a7301f | 484 | u32 ent; |
cc9203bf DW |
485 | u32 get_index; |
486 | u32 get_cycle; | |
994a9303 | 487 | u32 event_get; |
cc9203bf DW |
488 | u32 event_cycle; |
489 | ||
d9dcb4ba | 490 | dev_dbg(&ihost->pdev->dev, |
cc9203bf DW |
491 | "%s: completion queue begining get:0x%08x\n", |
492 | __func__, | |
d9dcb4ba | 493 | ihost->completion_queue_get); |
cc9203bf DW |
494 | |
495 | /* Get the component parts of the completion queue */ | |
d9dcb4ba DW |
496 | get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get); |
497 | get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get; | |
cc9203bf | 498 | |
d9dcb4ba DW |
499 | event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get); |
500 | event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get; | |
cc9203bf DW |
501 | |
502 | while ( | |
503 | NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle) | |
d9dcb4ba | 504 | == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]) |
cc9203bf DW |
505 | ) { |
506 | completion_count++; | |
507 | ||
89a7301f | 508 | ent = ihost->completion_queue[get_index]; |
994a9303 DW |
509 | |
510 | /* increment the get pointer and check for rollover to toggle the cycle bit */ | |
511 | get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) << | |
512 | (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT); | |
513 | get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1); | |
cc9203bf | 514 | |
d9dcb4ba | 515 | dev_dbg(&ihost->pdev->dev, |
cc9203bf DW |
516 | "%s: completion queue entry:0x%08x\n", |
517 | __func__, | |
89a7301f | 518 | ent); |
cc9203bf | 519 | |
89a7301f | 520 | switch (SCU_GET_COMPLETION_TYPE(ent)) { |
cc9203bf | 521 | case SCU_COMPLETION_TYPE_TASK: |
89a7301f | 522 | sci_controller_task_completion(ihost, ent); |
cc9203bf DW |
523 | break; |
524 | ||
525 | case SCU_COMPLETION_TYPE_SDMA: | |
89a7301f | 526 | sci_controller_sdma_completion(ihost, ent); |
cc9203bf DW |
527 | break; |
528 | ||
529 | case SCU_COMPLETION_TYPE_UFI: | |
89a7301f | 530 | sci_controller_unsolicited_frame(ihost, ent); |
cc9203bf DW |
531 | break; |
532 | ||
533 | case SCU_COMPLETION_TYPE_EVENT: | |
77cd72a5 DW |
534 | sci_controller_event_completion(ihost, ent); |
535 | break; | |
536 | ||
994a9303 DW |
537 | case SCU_COMPLETION_TYPE_NOTIFY: { |
538 | event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) << | |
539 | (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT); | |
540 | event_get = (event_get+1) & (SCU_MAX_EVENTS-1); | |
cc9203bf | 541 | |
89a7301f | 542 | sci_controller_event_completion(ihost, ent); |
cc9203bf | 543 | break; |
994a9303 | 544 | } |
cc9203bf | 545 | default: |
d9dcb4ba | 546 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
547 | "%s: SCIC Controller received unknown " |
548 | "completion type %x\n", | |
549 | __func__, | |
89a7301f | 550 | ent); |
cc9203bf DW |
551 | break; |
552 | } | |
553 | } | |
554 | ||
555 | /* Update the get register if we completed one or more entries */ | |
556 | if (completion_count > 0) { | |
d9dcb4ba | 557 | ihost->completion_queue_get = |
cc9203bf DW |
558 | SMU_CQGR_GEN_BIT(ENABLE) | |
559 | SMU_CQGR_GEN_BIT(EVENT_ENABLE) | | |
560 | event_cycle | | |
994a9303 | 561 | SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) | |
cc9203bf DW |
562 | get_cycle | |
563 | SMU_CQGR_GEN_VAL(POINTER, get_index); | |
564 | ||
d9dcb4ba DW |
565 | writel(ihost->completion_queue_get, |
566 | &ihost->smu_registers->completion_queue_get); | |
cc9203bf DW |
567 | |
568 | } | |
569 | ||
d9dcb4ba | 570 | dev_dbg(&ihost->pdev->dev, |
cc9203bf DW |
571 | "%s: completion queue ending get:0x%08x\n", |
572 | __func__, | |
d9dcb4ba | 573 | ihost->completion_queue_get); |
cc9203bf DW |
574 | |
575 | } | |
576 | ||
89a7301f | 577 | static void sci_controller_error_handler(struct isci_host *ihost) |
cc9203bf DW |
578 | { |
579 | u32 interrupt_status; | |
580 | ||
581 | interrupt_status = | |
d9dcb4ba | 582 | readl(&ihost->smu_registers->interrupt_status); |
cc9203bf DW |
583 | |
584 | if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) && | |
89a7301f | 585 | sci_controller_completion_queue_has_entries(ihost)) { |
cc9203bf | 586 | |
89a7301f | 587 | sci_controller_process_completions(ihost); |
d9dcb4ba | 588 | writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status); |
cc9203bf | 589 | } else { |
d9dcb4ba | 590 | dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__, |
cc9203bf DW |
591 | interrupt_status); |
592 | ||
d9dcb4ba | 593 | sci_change_state(&ihost->sm, SCIC_FAILED); |
cc9203bf DW |
594 | |
595 | return; | |
596 | } | |
597 | ||
598 | /* If we dont process any completions I am not sure that we want to do this. | |
599 | * We are in the middle of a hardware fault and should probably be reset. | |
600 | */ | |
d9dcb4ba | 601 | writel(0, &ihost->smu_registers->interrupt_mask); |
cc9203bf DW |
602 | } |
603 | ||
c7ef4031 | 604 | irqreturn_t isci_intx_isr(int vec, void *data) |
6f231dda | 605 | { |
6f231dda | 606 | irqreturn_t ret = IRQ_NONE; |
31e824ed | 607 | struct isci_host *ihost = data; |
c7ef4031 | 608 | |
89a7301f | 609 | if (sci_controller_isr(ihost)) { |
d9dcb4ba | 610 | writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); |
31e824ed DW |
611 | tasklet_schedule(&ihost->completion_tasklet); |
612 | ret = IRQ_HANDLED; | |
89a7301f | 613 | } else if (sci_controller_error_isr(ihost)) { |
31e824ed | 614 | spin_lock(&ihost->scic_lock); |
89a7301f | 615 | sci_controller_error_handler(ihost); |
31e824ed DW |
616 | spin_unlock(&ihost->scic_lock); |
617 | ret = IRQ_HANDLED; | |
6f231dda | 618 | } |
92f4f0f5 | 619 | |
6f231dda DW |
620 | return ret; |
621 | } | |
622 | ||
92f4f0f5 DW |
623 | irqreturn_t isci_error_isr(int vec, void *data) |
624 | { | |
625 | struct isci_host *ihost = data; | |
92f4f0f5 | 626 | |
89a7301f DW |
627 | if (sci_controller_error_isr(ihost)) |
628 | sci_controller_error_handler(ihost); | |
92f4f0f5 DW |
629 | |
630 | return IRQ_HANDLED; | |
631 | } | |
6f231dda DW |
632 | |
633 | /** | |
634 | * isci_host_start_complete() - This function is called by the core library, | |
635 | * through the ISCI Module, to indicate controller start status. | |
636 | * @isci_host: This parameter specifies the ISCI host object | |
637 | * @completion_status: This parameter specifies the completion status from the | |
638 | * core library. | |
639 | * | |
640 | */ | |
cc9203bf | 641 | static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status) |
6f231dda | 642 | { |
0cf89d1d DW |
643 | if (completion_status != SCI_SUCCESS) |
644 | dev_info(&ihost->pdev->dev, | |
645 | "controller start timed out, continuing...\n"); | |
646 | isci_host_change_state(ihost, isci_ready); | |
647 | clear_bit(IHOST_START_PENDING, &ihost->flags); | |
648 | wake_up(&ihost->eventq); | |
6f231dda DW |
649 | } |
650 | ||
c7ef4031 | 651 | int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time) |
6f231dda | 652 | { |
4393aa4e | 653 | struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; |
6f231dda | 654 | |
77950f51 | 655 | if (test_bit(IHOST_START_PENDING, &ihost->flags)) |
6f231dda | 656 | return 0; |
6f231dda | 657 | |
77950f51 EN |
658 | /* todo: use sas_flush_discovery once it is upstream */ |
659 | scsi_flush_work(shost); | |
660 | ||
661 | scsi_flush_work(shost); | |
6f231dda | 662 | |
0cf89d1d DW |
663 | dev_dbg(&ihost->pdev->dev, |
664 | "%s: ihost->status = %d, time = %ld\n", | |
665 | __func__, isci_host_get_state(ihost), time); | |
6f231dda | 666 | |
6f231dda DW |
667 | return 1; |
668 | ||
669 | } | |
670 | ||
cc9203bf | 671 | /** |
89a7301f DW |
672 | * sci_controller_get_suggested_start_timeout() - This method returns the |
673 | * suggested sci_controller_start() timeout amount. The user is free to | |
cc9203bf DW |
674 | * use any timeout value, but this method provides the suggested minimum |
675 | * start timeout value. The returned value is based upon empirical | |
676 | * information determined as a result of interoperability testing. | |
677 | * @controller: the handle to the controller object for which to return the | |
678 | * suggested start timeout. | |
679 | * | |
680 | * This method returns the number of milliseconds for the suggested start | |
681 | * operation timeout. | |
682 | */ | |
89a7301f | 683 | static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost) |
cc9203bf DW |
684 | { |
685 | /* Validate the user supplied parameters. */ | |
d9dcb4ba | 686 | if (!ihost) |
cc9203bf DW |
687 | return 0; |
688 | ||
689 | /* | |
690 | * The suggested minimum timeout value for a controller start operation: | |
691 | * | |
692 | * Signature FIS Timeout | |
693 | * + Phy Start Timeout | |
694 | * + Number of Phy Spin Up Intervals | |
695 | * --------------------------------- | |
696 | * Number of milliseconds for the controller start operation. | |
697 | * | |
698 | * NOTE: The number of phy spin up intervals will be equivalent | |
699 | * to the number of phys divided by the number phys allowed | |
700 | * per interval - 1 (once OEM parameters are supported). | |
701 | * Currently we assume only 1 phy per interval. */ | |
702 | ||
703 | return SCIC_SDS_SIGNATURE_FIS_TIMEOUT | |
704 | + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT | |
705 | + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); | |
706 | } | |
707 | ||
89a7301f | 708 | static void sci_controller_enable_interrupts(struct isci_host *ihost) |
cc9203bf | 709 | { |
d9dcb4ba DW |
710 | BUG_ON(ihost->smu_registers == NULL); |
711 | writel(0, &ihost->smu_registers->interrupt_mask); | |
cc9203bf DW |
712 | } |
713 | ||
89a7301f | 714 | void sci_controller_disable_interrupts(struct isci_host *ihost) |
cc9203bf | 715 | { |
d9dcb4ba DW |
716 | BUG_ON(ihost->smu_registers == NULL); |
717 | writel(0xffffffff, &ihost->smu_registers->interrupt_mask); | |
cc9203bf DW |
718 | } |
719 | ||
89a7301f | 720 | static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost) |
cc9203bf DW |
721 | { |
722 | u32 port_task_scheduler_value; | |
723 | ||
724 | port_task_scheduler_value = | |
d9dcb4ba | 725 | readl(&ihost->scu_registers->peg0.ptsg.control); |
cc9203bf DW |
726 | port_task_scheduler_value |= |
727 | (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) | | |
728 | SCU_PTSGCR_GEN_BIT(PTSG_ENABLE)); | |
729 | writel(port_task_scheduler_value, | |
d9dcb4ba | 730 | &ihost->scu_registers->peg0.ptsg.control); |
cc9203bf DW |
731 | } |
732 | ||
89a7301f | 733 | static void sci_controller_assign_task_entries(struct isci_host *ihost) |
cc9203bf DW |
734 | { |
735 | u32 task_assignment; | |
736 | ||
737 | /* | |
738 | * Assign all the TCs to function 0 | |
739 | * TODO: Do we actually need to read this register to write it back? | |
740 | */ | |
741 | ||
742 | task_assignment = | |
d9dcb4ba | 743 | readl(&ihost->smu_registers->task_context_assignment[0]); |
cc9203bf DW |
744 | |
745 | task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) | | |
d9dcb4ba | 746 | (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) | |
cc9203bf DW |
747 | (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE)); |
748 | ||
749 | writel(task_assignment, | |
d9dcb4ba | 750 | &ihost->smu_registers->task_context_assignment[0]); |
cc9203bf DW |
751 | |
752 | } | |
753 | ||
89a7301f | 754 | static void sci_controller_initialize_completion_queue(struct isci_host *ihost) |
cc9203bf DW |
755 | { |
756 | u32 index; | |
757 | u32 completion_queue_control_value; | |
758 | u32 completion_queue_get_value; | |
759 | u32 completion_queue_put_value; | |
760 | ||
d9dcb4ba | 761 | ihost->completion_queue_get = 0; |
cc9203bf | 762 | |
7c78da31 DW |
763 | completion_queue_control_value = |
764 | (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) | | |
765 | SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1)); | |
cc9203bf DW |
766 | |
767 | writel(completion_queue_control_value, | |
d9dcb4ba | 768 | &ihost->smu_registers->completion_queue_control); |
cc9203bf DW |
769 | |
770 | ||
771 | /* Set the completion queue get pointer and enable the queue */ | |
772 | completion_queue_get_value = ( | |
773 | (SMU_CQGR_GEN_VAL(POINTER, 0)) | |
774 | | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0)) | |
775 | | (SMU_CQGR_GEN_BIT(ENABLE)) | |
776 | | (SMU_CQGR_GEN_BIT(EVENT_ENABLE)) | |
777 | ); | |
778 | ||
779 | writel(completion_queue_get_value, | |
d9dcb4ba | 780 | &ihost->smu_registers->completion_queue_get); |
cc9203bf DW |
781 | |
782 | /* Set the completion queue put pointer */ | |
783 | completion_queue_put_value = ( | |
784 | (SMU_CQPR_GEN_VAL(POINTER, 0)) | |
785 | | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0)) | |
786 | ); | |
787 | ||
788 | writel(completion_queue_put_value, | |
d9dcb4ba | 789 | &ihost->smu_registers->completion_queue_put); |
cc9203bf DW |
790 | |
791 | /* Initialize the cycle bit of the completion queue entries */ | |
7c78da31 | 792 | for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) { |
cc9203bf DW |
793 | /* |
794 | * If get.cycle_bit != completion_queue.cycle_bit | |
795 | * its not a valid completion queue entry | |
796 | * so at system start all entries are invalid */ | |
d9dcb4ba | 797 | ihost->completion_queue[index] = 0x80000000; |
cc9203bf DW |
798 | } |
799 | } | |
800 | ||
89a7301f | 801 | static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost) |
cc9203bf DW |
802 | { |
803 | u32 frame_queue_control_value; | |
804 | u32 frame_queue_get_value; | |
805 | u32 frame_queue_put_value; | |
806 | ||
807 | /* Write the queue size */ | |
808 | frame_queue_control_value = | |
7c78da31 | 809 | SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES); |
cc9203bf DW |
810 | |
811 | writel(frame_queue_control_value, | |
d9dcb4ba | 812 | &ihost->scu_registers->sdma.unsolicited_frame_queue_control); |
cc9203bf DW |
813 | |
814 | /* Setup the get pointer for the unsolicited frame queue */ | |
815 | frame_queue_get_value = ( | |
816 | SCU_UFQGP_GEN_VAL(POINTER, 0) | |
817 | | SCU_UFQGP_GEN_BIT(ENABLE_BIT) | |
818 | ); | |
819 | ||
820 | writel(frame_queue_get_value, | |
d9dcb4ba | 821 | &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); |
cc9203bf DW |
822 | /* Setup the put pointer for the unsolicited frame queue */ |
823 | frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0); | |
824 | writel(frame_queue_put_value, | |
d9dcb4ba | 825 | &ihost->scu_registers->sdma.unsolicited_frame_put_pointer); |
cc9203bf DW |
826 | } |
827 | ||
89a7301f | 828 | static void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status) |
cc9203bf | 829 | { |
d9dcb4ba | 830 | if (ihost->sm.current_state_id == SCIC_STARTING) { |
cc9203bf DW |
831 | /* |
832 | * We move into the ready state, because some of the phys/ports | |
833 | * may be up and operational. | |
834 | */ | |
d9dcb4ba | 835 | sci_change_state(&ihost->sm, SCIC_READY); |
cc9203bf DW |
836 | |
837 | isci_host_start_complete(ihost, status); | |
838 | } | |
839 | } | |
840 | ||
85280955 | 841 | static bool is_phy_starting(struct isci_phy *iphy) |
4a33c525 | 842 | { |
89a7301f | 843 | enum sci_phy_states state; |
4a33c525 | 844 | |
85280955 | 845 | state = iphy->sm.current_state_id; |
4a33c525 | 846 | switch (state) { |
e301370a EN |
847 | case SCI_PHY_STARTING: |
848 | case SCI_PHY_SUB_INITIAL: | |
849 | case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN: | |
850 | case SCI_PHY_SUB_AWAIT_IAF_UF: | |
851 | case SCI_PHY_SUB_AWAIT_SAS_POWER: | |
852 | case SCI_PHY_SUB_AWAIT_SATA_POWER: | |
853 | case SCI_PHY_SUB_AWAIT_SATA_PHY_EN: | |
854 | case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN: | |
855 | case SCI_PHY_SUB_AWAIT_SIG_FIS_UF: | |
856 | case SCI_PHY_SUB_FINAL: | |
4a33c525 AG |
857 | return true; |
858 | default: | |
859 | return false; | |
860 | } | |
861 | } | |
862 | ||
cc9203bf | 863 | /** |
89a7301f | 864 | * sci_controller_start_next_phy - start phy |
cc9203bf DW |
865 | * @scic: controller |
866 | * | |
867 | * If all the phys have been started, then attempt to transition the | |
868 | * controller to the READY state and inform the user | |
89a7301f | 869 | * (sci_cb_controller_start_complete()). |
cc9203bf | 870 | */ |
89a7301f | 871 | static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost) |
cc9203bf | 872 | { |
89a7301f | 873 | struct sci_oem_params *oem = &ihost->oem_parameters; |
85280955 | 874 | struct isci_phy *iphy; |
cc9203bf DW |
875 | enum sci_status status; |
876 | ||
877 | status = SCI_SUCCESS; | |
878 | ||
d9dcb4ba | 879 | if (ihost->phy_startup_timer_pending) |
cc9203bf DW |
880 | return status; |
881 | ||
d9dcb4ba | 882 | if (ihost->next_phy_to_start >= SCI_MAX_PHYS) { |
cc9203bf DW |
883 | bool is_controller_start_complete = true; |
884 | u32 state; | |
885 | u8 index; | |
886 | ||
887 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
85280955 DW |
888 | iphy = &ihost->phys[index]; |
889 | state = iphy->sm.current_state_id; | |
cc9203bf | 890 | |
85280955 | 891 | if (!phy_get_non_dummy_port(iphy)) |
cc9203bf DW |
892 | continue; |
893 | ||
894 | /* The controller start operation is complete iff: | |
895 | * - all links have been given an opportunity to start | |
896 | * - have no indication of a connected device | |
897 | * - have an indication of a connected device and it has | |
898 | * finished the link training process. | |
899 | */ | |
85280955 DW |
900 | if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) || |
901 | (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) || | |
902 | (iphy->is_in_link_training == true && is_phy_starting(iphy))) { | |
cc9203bf DW |
903 | is_controller_start_complete = false; |
904 | break; | |
905 | } | |
906 | } | |
907 | ||
908 | /* | |
909 | * The controller has successfully finished the start process. | |
910 | * Inform the SCI Core user and transition to the READY state. */ | |
911 | if (is_controller_start_complete == true) { | |
89a7301f | 912 | sci_controller_transition_to_ready(ihost, SCI_SUCCESS); |
d9dcb4ba DW |
913 | sci_del_timer(&ihost->phy_timer); |
914 | ihost->phy_startup_timer_pending = false; | |
cc9203bf DW |
915 | } |
916 | } else { | |
d9dcb4ba | 917 | iphy = &ihost->phys[ihost->next_phy_to_start]; |
cc9203bf DW |
918 | |
919 | if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
85280955 | 920 | if (phy_get_non_dummy_port(iphy) == NULL) { |
d9dcb4ba | 921 | ihost->next_phy_to_start++; |
cc9203bf DW |
922 | |
923 | /* Caution recursion ahead be forwarned | |
924 | * | |
925 | * The PHY was never added to a PORT in MPC mode | |
926 | * so start the next phy in sequence This phy | |
927 | * will never go link up and will not draw power | |
928 | * the OEM parameters either configured the phy | |
929 | * incorrectly for the PORT or it was never | |
930 | * assigned to a PORT | |
931 | */ | |
89a7301f | 932 | return sci_controller_start_next_phy(ihost); |
cc9203bf DW |
933 | } |
934 | } | |
935 | ||
89a7301f | 936 | status = sci_phy_start(iphy); |
cc9203bf DW |
937 | |
938 | if (status == SCI_SUCCESS) { | |
d9dcb4ba | 939 | sci_mod_timer(&ihost->phy_timer, |
bb3dbdf6 | 940 | SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT); |
d9dcb4ba | 941 | ihost->phy_startup_timer_pending = true; |
cc9203bf | 942 | } else { |
d9dcb4ba | 943 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
944 | "%s: Controller stop operation failed " |
945 | "to stop phy %d because of status " | |
946 | "%d.\n", | |
947 | __func__, | |
d9dcb4ba | 948 | ihost->phys[ihost->next_phy_to_start].phy_index, |
cc9203bf DW |
949 | status); |
950 | } | |
951 | ||
d9dcb4ba | 952 | ihost->next_phy_to_start++; |
cc9203bf DW |
953 | } |
954 | ||
955 | return status; | |
956 | } | |
957 | ||
bb3dbdf6 | 958 | static void phy_startup_timeout(unsigned long data) |
cc9203bf | 959 | { |
bb3dbdf6 | 960 | struct sci_timer *tmr = (struct sci_timer *)data; |
d9dcb4ba | 961 | struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer); |
bb3dbdf6 | 962 | unsigned long flags; |
cc9203bf DW |
963 | enum sci_status status; |
964 | ||
bb3dbdf6 EN |
965 | spin_lock_irqsave(&ihost->scic_lock, flags); |
966 | ||
967 | if (tmr->cancel) | |
968 | goto done; | |
969 | ||
d9dcb4ba | 970 | ihost->phy_startup_timer_pending = false; |
bb3dbdf6 EN |
971 | |
972 | do { | |
89a7301f | 973 | status = sci_controller_start_next_phy(ihost); |
bb3dbdf6 EN |
974 | } while (status != SCI_SUCCESS); |
975 | ||
976 | done: | |
977 | spin_unlock_irqrestore(&ihost->scic_lock, flags); | |
cc9203bf DW |
978 | } |
979 | ||
ac668c69 DW |
980 | static u16 isci_tci_active(struct isci_host *ihost) |
981 | { | |
982 | return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); | |
983 | } | |
984 | ||
89a7301f | 985 | static enum sci_status sci_controller_start(struct isci_host *ihost, |
cc9203bf DW |
986 | u32 timeout) |
987 | { | |
cc9203bf DW |
988 | enum sci_status result; |
989 | u16 index; | |
990 | ||
d9dcb4ba DW |
991 | if (ihost->sm.current_state_id != SCIC_INITIALIZED) { |
992 | dev_warn(&ihost->pdev->dev, | |
cc9203bf DW |
993 | "SCIC Controller start operation requested in " |
994 | "invalid state\n"); | |
995 | return SCI_FAILURE_INVALID_STATE; | |
996 | } | |
997 | ||
998 | /* Build the TCi free pool */ | |
ac668c69 DW |
999 | BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8); |
1000 | ihost->tci_head = 0; | |
1001 | ihost->tci_tail = 0; | |
d9dcb4ba | 1002 | for (index = 0; index < ihost->task_context_entries; index++) |
ac668c69 | 1003 | isci_tci_free(ihost, index); |
cc9203bf DW |
1004 | |
1005 | /* Build the RNi free pool */ | |
89a7301f DW |
1006 | sci_remote_node_table_initialize(&ihost->available_remote_nodes, |
1007 | ihost->remote_node_entries); | |
cc9203bf DW |
1008 | |
1009 | /* | |
1010 | * Before anything else lets make sure we will not be | |
1011 | * interrupted by the hardware. | |
1012 | */ | |
89a7301f | 1013 | sci_controller_disable_interrupts(ihost); |
cc9203bf DW |
1014 | |
1015 | /* Enable the port task scheduler */ | |
89a7301f | 1016 | sci_controller_enable_port_task_scheduler(ihost); |
cc9203bf | 1017 | |
d9dcb4ba | 1018 | /* Assign all the task entries to ihost physical function */ |
89a7301f | 1019 | sci_controller_assign_task_entries(ihost); |
cc9203bf DW |
1020 | |
1021 | /* Now initialize the completion queue */ | |
89a7301f | 1022 | sci_controller_initialize_completion_queue(ihost); |
cc9203bf DW |
1023 | |
1024 | /* Initialize the unsolicited frame queue for use */ | |
89a7301f | 1025 | sci_controller_initialize_unsolicited_frame_queue(ihost); |
cc9203bf DW |
1026 | |
1027 | /* Start all of the ports on this controller */ | |
d9dcb4ba | 1028 | for (index = 0; index < ihost->logical_port_entries; index++) { |
ffe191c9 | 1029 | struct isci_port *iport = &ihost->ports[index]; |
cc9203bf | 1030 | |
89a7301f | 1031 | result = sci_port_start(iport); |
cc9203bf DW |
1032 | if (result) |
1033 | return result; | |
1034 | } | |
1035 | ||
89a7301f | 1036 | sci_controller_start_next_phy(ihost); |
cc9203bf | 1037 | |
d9dcb4ba | 1038 | sci_mod_timer(&ihost->timer, timeout); |
cc9203bf | 1039 | |
d9dcb4ba | 1040 | sci_change_state(&ihost->sm, SCIC_STARTING); |
cc9203bf DW |
1041 | |
1042 | return SCI_SUCCESS; | |
1043 | } | |
1044 | ||
6f231dda DW |
1045 | void isci_host_scan_start(struct Scsi_Host *shost) |
1046 | { | |
4393aa4e | 1047 | struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha; |
89a7301f | 1048 | unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost); |
6f231dda | 1049 | |
0cf89d1d | 1050 | set_bit(IHOST_START_PENDING, &ihost->flags); |
77950f51 EN |
1051 | |
1052 | spin_lock_irq(&ihost->scic_lock); | |
89a7301f DW |
1053 | sci_controller_start(ihost, tmo); |
1054 | sci_controller_enable_interrupts(ihost); | |
77950f51 | 1055 | spin_unlock_irq(&ihost->scic_lock); |
6f231dda DW |
1056 | } |
1057 | ||
cc9203bf | 1058 | static void isci_host_stop_complete(struct isci_host *ihost, enum sci_status completion_status) |
6f231dda | 1059 | { |
0cf89d1d | 1060 | isci_host_change_state(ihost, isci_stopped); |
89a7301f | 1061 | sci_controller_disable_interrupts(ihost); |
0cf89d1d DW |
1062 | clear_bit(IHOST_STOP_PENDING, &ihost->flags); |
1063 | wake_up(&ihost->eventq); | |
6f231dda DW |
1064 | } |
1065 | ||
89a7301f | 1066 | static void sci_controller_completion_handler(struct isci_host *ihost) |
cc9203bf DW |
1067 | { |
1068 | /* Empty out the completion queue */ | |
89a7301f DW |
1069 | if (sci_controller_completion_queue_has_entries(ihost)) |
1070 | sci_controller_process_completions(ihost); | |
cc9203bf DW |
1071 | |
1072 | /* Clear the interrupt and enable all interrupts again */ | |
d9dcb4ba | 1073 | writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status); |
cc9203bf | 1074 | /* Could we write the value of SMU_ISR_COMPLETION? */ |
d9dcb4ba DW |
1075 | writel(0xFF000000, &ihost->smu_registers->interrupt_mask); |
1076 | writel(0, &ihost->smu_registers->interrupt_mask); | |
cc9203bf DW |
1077 | } |
1078 | ||
6f231dda DW |
1079 | /** |
1080 | * isci_host_completion_routine() - This function is the delayed service | |
1081 | * routine that calls the sci core library's completion handler. It's | |
1082 | * scheduled as a tasklet from the interrupt service routine when interrupts | |
1083 | * in use, or set as the timeout function in polled mode. | |
1084 | * @data: This parameter specifies the ISCI host object | |
1085 | * | |
1086 | */ | |
1087 | static void isci_host_completion_routine(unsigned long data) | |
1088 | { | |
d9dcb4ba | 1089 | struct isci_host *ihost = (struct isci_host *)data; |
11b00c19 JS |
1090 | struct list_head completed_request_list; |
1091 | struct list_head errored_request_list; | |
1092 | struct list_head *current_position; | |
1093 | struct list_head *next_position; | |
6f231dda DW |
1094 | struct isci_request *request; |
1095 | struct isci_request *next_request; | |
11b00c19 | 1096 | struct sas_task *task; |
9b4be528 | 1097 | u16 active; |
6f231dda DW |
1098 | |
1099 | INIT_LIST_HEAD(&completed_request_list); | |
11b00c19 | 1100 | INIT_LIST_HEAD(&errored_request_list); |
6f231dda | 1101 | |
d9dcb4ba | 1102 | spin_lock_irq(&ihost->scic_lock); |
6f231dda | 1103 | |
89a7301f | 1104 | sci_controller_completion_handler(ihost); |
c7ef4031 | 1105 | |
6f231dda | 1106 | /* Take the lists of completed I/Os from the host. */ |
11b00c19 | 1107 | |
d9dcb4ba | 1108 | list_splice_init(&ihost->requests_to_complete, |
6f231dda DW |
1109 | &completed_request_list); |
1110 | ||
11b00c19 | 1111 | /* Take the list of errored I/Os from the host. */ |
d9dcb4ba | 1112 | list_splice_init(&ihost->requests_to_errorback, |
11b00c19 | 1113 | &errored_request_list); |
6f231dda | 1114 | |
d9dcb4ba | 1115 | spin_unlock_irq(&ihost->scic_lock); |
6f231dda DW |
1116 | |
1117 | /* Process any completions in the lists. */ | |
1118 | list_for_each_safe(current_position, next_position, | |
1119 | &completed_request_list) { | |
1120 | ||
1121 | request = list_entry(current_position, struct isci_request, | |
1122 | completed_node); | |
1123 | task = isci_request_access_task(request); | |
1124 | ||
1125 | /* Normal notification (task_done) */ | |
d9dcb4ba | 1126 | dev_dbg(&ihost->pdev->dev, |
6f231dda DW |
1127 | "%s: Normal - request/task = %p/%p\n", |
1128 | __func__, | |
1129 | request, | |
1130 | task); | |
1131 | ||
11b00c19 JS |
1132 | /* Return the task to libsas */ |
1133 | if (task != NULL) { | |
1134 | ||
1135 | task->lldd_task = NULL; | |
1136 | if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) { | |
6f231dda | 1137 | |
11b00c19 JS |
1138 | /* If the task is already in the abort path, |
1139 | * the task_done callback cannot be called. | |
1140 | */ | |
1141 | task->task_done(task); | |
1142 | } | |
1143 | } | |
312e0c24 | 1144 | |
d9dcb4ba DW |
1145 | spin_lock_irq(&ihost->scic_lock); |
1146 | isci_free_tag(ihost, request->io_tag); | |
1147 | spin_unlock_irq(&ihost->scic_lock); | |
6f231dda | 1148 | } |
11b00c19 | 1149 | list_for_each_entry_safe(request, next_request, &errored_request_list, |
6f231dda DW |
1150 | completed_node) { |
1151 | ||
1152 | task = isci_request_access_task(request); | |
1153 | ||
1154 | /* Use sas_task_abort */ | |
d9dcb4ba | 1155 | dev_warn(&ihost->pdev->dev, |
6f231dda DW |
1156 | "%s: Error - request/task = %p/%p\n", |
1157 | __func__, | |
1158 | request, | |
1159 | task); | |
1160 | ||
11b00c19 JS |
1161 | if (task != NULL) { |
1162 | ||
1163 | /* Put the task into the abort path if it's not there | |
1164 | * already. | |
1165 | */ | |
1166 | if (!(task->task_state_flags & SAS_TASK_STATE_ABORTED)) | |
1167 | sas_task_abort(task); | |
1168 | ||
1169 | } else { | |
1170 | /* This is a case where the request has completed with a | |
1171 | * status such that it needed further target servicing, | |
1172 | * but the sas_task reference has already been removed | |
1173 | * from the request. Since it was errored, it was not | |
1174 | * being aborted, so there is nothing to do except free | |
1175 | * it. | |
1176 | */ | |
1177 | ||
d9dcb4ba | 1178 | spin_lock_irq(&ihost->scic_lock); |
11b00c19 JS |
1179 | /* Remove the request from the remote device's list |
1180 | * of pending requests. | |
1181 | */ | |
1182 | list_del_init(&request->dev_node); | |
d9dcb4ba DW |
1183 | isci_free_tag(ihost, request->io_tag); |
1184 | spin_unlock_irq(&ihost->scic_lock); | |
11b00c19 | 1185 | } |
6f231dda DW |
1186 | } |
1187 | ||
9b4be528 DW |
1188 | /* the coalesence timeout doubles at each encoding step, so |
1189 | * update it based on the ilog2 value of the outstanding requests | |
1190 | */ | |
1191 | active = isci_tci_active(ihost); | |
1192 | writel(SMU_ICC_GEN_VAL(NUMBER, active) | | |
1193 | SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)), | |
1194 | &ihost->smu_registers->interrupt_coalesce_control); | |
6f231dda DW |
1195 | } |
1196 | ||
cc9203bf | 1197 | /** |
89a7301f | 1198 | * sci_controller_stop() - This method will stop an individual controller |
cc9203bf DW |
1199 | * object.This method will invoke the associated user callback upon |
1200 | * completion. The completion callback is called when the following | |
1201 | * conditions are met: -# the method return status is SCI_SUCCESS. -# the | |
1202 | * controller has been quiesced. This method will ensure that all IO | |
1203 | * requests are quiesced, phys are stopped, and all additional operation by | |
1204 | * the hardware is halted. | |
1205 | * @controller: the handle to the controller object to stop. | |
1206 | * @timeout: This parameter specifies the number of milliseconds in which the | |
1207 | * stop operation should complete. | |
1208 | * | |
1209 | * The controller must be in the STARTED or STOPPED state. Indicate if the | |
1210 | * controller stop method succeeded or failed in some way. SCI_SUCCESS if the | |
1211 | * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the | |
1212 | * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the | |
1213 | * controller is not either in the STARTED or STOPPED states. | |
1214 | */ | |
89a7301f | 1215 | static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout) |
6f231dda | 1216 | { |
d9dcb4ba DW |
1217 | if (ihost->sm.current_state_id != SCIC_READY) { |
1218 | dev_warn(&ihost->pdev->dev, | |
cc9203bf DW |
1219 | "SCIC Controller stop operation requested in " |
1220 | "invalid state\n"); | |
1221 | return SCI_FAILURE_INVALID_STATE; | |
1222 | } | |
6f231dda | 1223 | |
d9dcb4ba DW |
1224 | sci_mod_timer(&ihost->timer, timeout); |
1225 | sci_change_state(&ihost->sm, SCIC_STOPPING); | |
cc9203bf DW |
1226 | return SCI_SUCCESS; |
1227 | } | |
1228 | ||
1229 | /** | |
89a7301f | 1230 | * sci_controller_reset() - This method will reset the supplied core |
cc9203bf DW |
1231 | * controller regardless of the state of said controller. This operation is |
1232 | * considered destructive. In other words, all current operations are wiped | |
1233 | * out. No IO completions for outstanding devices occur. Outstanding IO | |
1234 | * requests are not aborted or completed at the actual remote device. | |
1235 | * @controller: the handle to the controller object to reset. | |
1236 | * | |
1237 | * Indicate if the controller reset method succeeded or failed in some way. | |
1238 | * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if | |
1239 | * the controller reset operation is unable to complete. | |
1240 | */ | |
89a7301f | 1241 | static enum sci_status sci_controller_reset(struct isci_host *ihost) |
cc9203bf | 1242 | { |
d9dcb4ba | 1243 | switch (ihost->sm.current_state_id) { |
e301370a EN |
1244 | case SCIC_RESET: |
1245 | case SCIC_READY: | |
1246 | case SCIC_STOPPED: | |
1247 | case SCIC_FAILED: | |
cc9203bf DW |
1248 | /* |
1249 | * The reset operation is not a graceful cleanup, just | |
1250 | * perform the state transition. | |
1251 | */ | |
d9dcb4ba | 1252 | sci_change_state(&ihost->sm, SCIC_RESETTING); |
cc9203bf DW |
1253 | return SCI_SUCCESS; |
1254 | default: | |
d9dcb4ba | 1255 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
1256 | "SCIC Controller reset operation requested in " |
1257 | "invalid state\n"); | |
1258 | return SCI_FAILURE_INVALID_STATE; | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | void isci_host_deinit(struct isci_host *ihost) | |
1263 | { | |
1264 | int i; | |
1265 | ||
ad4f4c1d DW |
1266 | /* disable output data selects */ |
1267 | for (i = 0; i < isci_gpio_count(ihost); i++) | |
1268 | writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); | |
1269 | ||
cc9203bf | 1270 | isci_host_change_state(ihost, isci_stopping); |
6f231dda | 1271 | for (i = 0; i < SCI_MAX_PORTS; i++) { |
e531381e | 1272 | struct isci_port *iport = &ihost->ports[i]; |
0cf89d1d DW |
1273 | struct isci_remote_device *idev, *d; |
1274 | ||
e531381e | 1275 | list_for_each_entry_safe(idev, d, &iport->remote_dev_list, node) { |
209fae14 DW |
1276 | if (test_bit(IDEV_ALLOCATED, &idev->flags)) |
1277 | isci_remote_device_stop(ihost, idev); | |
6f231dda DW |
1278 | } |
1279 | } | |
1280 | ||
0cf89d1d | 1281 | set_bit(IHOST_STOP_PENDING, &ihost->flags); |
7c40a803 DW |
1282 | |
1283 | spin_lock_irq(&ihost->scic_lock); | |
89a7301f | 1284 | sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT); |
7c40a803 DW |
1285 | spin_unlock_irq(&ihost->scic_lock); |
1286 | ||
0cf89d1d | 1287 | wait_for_stop(ihost); |
ad4f4c1d DW |
1288 | |
1289 | /* disable sgpio: where the above wait should give time for the | |
1290 | * enclosure to sample the gpios going inactive | |
1291 | */ | |
1292 | writel(0, &ihost->scu_registers->peg0.sgpio.interface_control); | |
1293 | ||
89a7301f | 1294 | sci_controller_reset(ihost); |
5553ba2b EN |
1295 | |
1296 | /* Cancel any/all outstanding port timers */ | |
d9dcb4ba | 1297 | for (i = 0; i < ihost->logical_port_entries; i++) { |
ffe191c9 DW |
1298 | struct isci_port *iport = &ihost->ports[i]; |
1299 | del_timer_sync(&iport->timer.timer); | |
5553ba2b EN |
1300 | } |
1301 | ||
a628d478 EN |
1302 | /* Cancel any/all outstanding phy timers */ |
1303 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
85280955 DW |
1304 | struct isci_phy *iphy = &ihost->phys[i]; |
1305 | del_timer_sync(&iphy->sata_timer.timer); | |
a628d478 EN |
1306 | } |
1307 | ||
d9dcb4ba | 1308 | del_timer_sync(&ihost->port_agent.timer.timer); |
ac0eeb4f | 1309 | |
d9dcb4ba | 1310 | del_timer_sync(&ihost->power_control.timer.timer); |
0473661a | 1311 | |
d9dcb4ba | 1312 | del_timer_sync(&ihost->timer.timer); |
6cb5853d | 1313 | |
d9dcb4ba | 1314 | del_timer_sync(&ihost->phy_timer.timer); |
6f231dda DW |
1315 | } |
1316 | ||
6f231dda DW |
1317 | static void __iomem *scu_base(struct isci_host *isci_host) |
1318 | { | |
1319 | struct pci_dev *pdev = isci_host->pdev; | |
1320 | int id = isci_host->id; | |
1321 | ||
1322 | return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id; | |
1323 | } | |
1324 | ||
1325 | static void __iomem *smu_base(struct isci_host *isci_host) | |
1326 | { | |
1327 | struct pci_dev *pdev = isci_host->pdev; | |
1328 | int id = isci_host->id; | |
1329 | ||
1330 | return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id; | |
1331 | } | |
1332 | ||
89a7301f | 1333 | static void isci_user_parameters_get(struct sci_user_parameters *u) |
b5f18a20 | 1334 | { |
b5f18a20 DJ |
1335 | int i; |
1336 | ||
1337 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
1338 | struct sci_phy_user_params *u_phy = &u->phys[i]; | |
1339 | ||
1340 | u_phy->max_speed_generation = phy_gen; | |
1341 | ||
1342 | /* we are not exporting these for now */ | |
1343 | u_phy->align_insertion_frequency = 0x7f; | |
1344 | u_phy->in_connection_align_insertion_frequency = 0xff; | |
1345 | u_phy->notify_enable_spin_up_insertion_frequency = 0x33; | |
1346 | } | |
1347 | ||
1348 | u->stp_inactivity_timeout = stp_inactive_to; | |
1349 | u->ssp_inactivity_timeout = ssp_inactive_to; | |
1350 | u->stp_max_occupancy_timeout = stp_max_occ_to; | |
1351 | u->ssp_max_occupancy_timeout = ssp_max_occ_to; | |
1352 | u->no_outbound_task_timeout = no_outbound_task_to; | |
7000f7c7 | 1353 | u->max_concurr_spinup = max_concurr_spinup; |
b5f18a20 DJ |
1354 | } |
1355 | ||
89a7301f | 1356 | static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1357 | { |
d9dcb4ba | 1358 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf | 1359 | |
d9dcb4ba | 1360 | sci_change_state(&ihost->sm, SCIC_RESET); |
cc9203bf DW |
1361 | } |
1362 | ||
89a7301f | 1363 | static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1364 | { |
d9dcb4ba | 1365 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf | 1366 | |
d9dcb4ba | 1367 | sci_del_timer(&ihost->timer); |
cc9203bf DW |
1368 | } |
1369 | ||
1370 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853 | |
1371 | #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280 | |
1372 | #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000 | |
1373 | #define INTERRUPT_COALESCE_NUMBER_MAX 256 | |
1374 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7 | |
1375 | #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28 | |
1376 | ||
1377 | /** | |
89a7301f | 1378 | * sci_controller_set_interrupt_coalescence() - This method allows the user to |
cc9203bf DW |
1379 | * configure the interrupt coalescence. |
1380 | * @controller: This parameter represents the handle to the controller object | |
1381 | * for which its interrupt coalesce register is overridden. | |
1382 | * @coalesce_number: Used to control the number of entries in the Completion | |
1383 | * Queue before an interrupt is generated. If the number of entries exceed | |
1384 | * this number, an interrupt will be generated. The valid range of the input | |
1385 | * is [0, 256]. A setting of 0 results in coalescing being disabled. | |
1386 | * @coalesce_timeout: Timeout value in microseconds. The valid range of the | |
1387 | * input is [0, 2700000] . A setting of 0 is allowed and results in no | |
1388 | * interrupt coalescing timeout. | |
1389 | * | |
1390 | * Indicate if the user successfully set the interrupt coalesce parameters. | |
1391 | * SCI_SUCCESS The user successfully updated the interrutp coalescence. | |
1392 | * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range. | |
1393 | */ | |
d9dcb4ba | 1394 | static enum sci_status |
89a7301f DW |
1395 | sci_controller_set_interrupt_coalescence(struct isci_host *ihost, |
1396 | u32 coalesce_number, | |
1397 | u32 coalesce_timeout) | |
cc9203bf DW |
1398 | { |
1399 | u8 timeout_encode = 0; | |
1400 | u32 min = 0; | |
1401 | u32 max = 0; | |
1402 | ||
1403 | /* Check if the input parameters fall in the range. */ | |
1404 | if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX) | |
1405 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
1406 | ||
1407 | /* | |
1408 | * Defined encoding for interrupt coalescing timeout: | |
1409 | * Value Min Max Units | |
1410 | * ----- --- --- ----- | |
1411 | * 0 - - Disabled | |
1412 | * 1 13.3 20.0 ns | |
1413 | * 2 26.7 40.0 | |
1414 | * 3 53.3 80.0 | |
1415 | * 4 106.7 160.0 | |
1416 | * 5 213.3 320.0 | |
1417 | * 6 426.7 640.0 | |
1418 | * 7 853.3 1280.0 | |
1419 | * 8 1.7 2.6 us | |
1420 | * 9 3.4 5.1 | |
1421 | * 10 6.8 10.2 | |
1422 | * 11 13.7 20.5 | |
1423 | * 12 27.3 41.0 | |
1424 | * 13 54.6 81.9 | |
1425 | * 14 109.2 163.8 | |
1426 | * 15 218.5 327.7 | |
1427 | * 16 436.9 655.4 | |
1428 | * 17 873.8 1310.7 | |
1429 | * 18 1.7 2.6 ms | |
1430 | * 19 3.5 5.2 | |
1431 | * 20 7.0 10.5 | |
1432 | * 21 14.0 21.0 | |
1433 | * 22 28.0 41.9 | |
1434 | * 23 55.9 83.9 | |
1435 | * 24 111.8 167.8 | |
1436 | * 25 223.7 335.5 | |
1437 | * 26 447.4 671.1 | |
1438 | * 27 894.8 1342.2 | |
1439 | * 28 1.8 2.7 s | |
1440 | * Others Undefined */ | |
1441 | ||
1442 | /* | |
1443 | * Use the table above to decide the encode of interrupt coalescing timeout | |
1444 | * value for register writing. */ | |
1445 | if (coalesce_timeout == 0) | |
1446 | timeout_encode = 0; | |
1447 | else{ | |
1448 | /* make the timeout value in unit of (10 ns). */ | |
1449 | coalesce_timeout = coalesce_timeout * 100; | |
1450 | min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10; | |
1451 | max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10; | |
1452 | ||
1453 | /* get the encode of timeout for register writing. */ | |
1454 | for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN; | |
1455 | timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX; | |
1456 | timeout_encode++) { | |
1457 | if (min <= coalesce_timeout && max > coalesce_timeout) | |
1458 | break; | |
1459 | else if (coalesce_timeout >= max && coalesce_timeout < min * 2 | |
1460 | && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) { | |
1461 | if ((coalesce_timeout - max) < (2 * min - coalesce_timeout)) | |
1462 | break; | |
1463 | else{ | |
1464 | timeout_encode++; | |
1465 | break; | |
1466 | } | |
1467 | } else { | |
1468 | max = max * 2; | |
1469 | min = min * 2; | |
1470 | } | |
1471 | } | |
1472 | ||
1473 | if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1) | |
1474 | /* the value is out of range. */ | |
1475 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
1476 | } | |
1477 | ||
1478 | writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) | | |
1479 | SMU_ICC_GEN_VAL(TIMER, timeout_encode), | |
d9dcb4ba | 1480 | &ihost->smu_registers->interrupt_coalesce_control); |
cc9203bf DW |
1481 | |
1482 | ||
d9dcb4ba DW |
1483 | ihost->interrupt_coalesce_number = (u16)coalesce_number; |
1484 | ihost->interrupt_coalesce_timeout = coalesce_timeout / 100; | |
cc9203bf DW |
1485 | |
1486 | return SCI_SUCCESS; | |
1487 | } | |
1488 | ||
1489 | ||
89a7301f | 1490 | static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1491 | { |
d9dcb4ba | 1492 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf DW |
1493 | |
1494 | /* set the default interrupt coalescence number and timeout value. */ | |
9b4be528 | 1495 | sci_controller_set_interrupt_coalescence(ihost, 0, 0); |
cc9203bf DW |
1496 | } |
1497 | ||
89a7301f | 1498 | static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1499 | { |
d9dcb4ba | 1500 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf DW |
1501 | |
1502 | /* disable interrupt coalescence. */ | |
89a7301f | 1503 | sci_controller_set_interrupt_coalescence(ihost, 0, 0); |
cc9203bf DW |
1504 | } |
1505 | ||
89a7301f | 1506 | static enum sci_status sci_controller_stop_phys(struct isci_host *ihost) |
cc9203bf DW |
1507 | { |
1508 | u32 index; | |
1509 | enum sci_status status; | |
1510 | enum sci_status phy_status; | |
cc9203bf DW |
1511 | |
1512 | status = SCI_SUCCESS; | |
1513 | ||
1514 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
89a7301f | 1515 | phy_status = sci_phy_stop(&ihost->phys[index]); |
cc9203bf DW |
1516 | |
1517 | if (phy_status != SCI_SUCCESS && | |
1518 | phy_status != SCI_FAILURE_INVALID_STATE) { | |
1519 | status = SCI_FAILURE; | |
1520 | ||
d9dcb4ba | 1521 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
1522 | "%s: Controller stop operation failed to stop " |
1523 | "phy %d because of status %d.\n", | |
1524 | __func__, | |
85280955 | 1525 | ihost->phys[index].phy_index, phy_status); |
cc9203bf DW |
1526 | } |
1527 | } | |
1528 | ||
1529 | return status; | |
1530 | } | |
1531 | ||
89a7301f | 1532 | static enum sci_status sci_controller_stop_ports(struct isci_host *ihost) |
cc9203bf DW |
1533 | { |
1534 | u32 index; | |
1535 | enum sci_status port_status; | |
1536 | enum sci_status status = SCI_SUCCESS; | |
cc9203bf | 1537 | |
d9dcb4ba | 1538 | for (index = 0; index < ihost->logical_port_entries; index++) { |
ffe191c9 | 1539 | struct isci_port *iport = &ihost->ports[index]; |
cc9203bf | 1540 | |
89a7301f | 1541 | port_status = sci_port_stop(iport); |
cc9203bf DW |
1542 | |
1543 | if ((port_status != SCI_SUCCESS) && | |
1544 | (port_status != SCI_FAILURE_INVALID_STATE)) { | |
1545 | status = SCI_FAILURE; | |
1546 | ||
d9dcb4ba | 1547 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
1548 | "%s: Controller stop operation failed to " |
1549 | "stop port %d because of status %d.\n", | |
1550 | __func__, | |
ffe191c9 | 1551 | iport->logical_port_index, |
cc9203bf DW |
1552 | port_status); |
1553 | } | |
1554 | } | |
1555 | ||
1556 | return status; | |
1557 | } | |
1558 | ||
89a7301f | 1559 | static enum sci_status sci_controller_stop_devices(struct isci_host *ihost) |
cc9203bf DW |
1560 | { |
1561 | u32 index; | |
1562 | enum sci_status status; | |
1563 | enum sci_status device_status; | |
1564 | ||
1565 | status = SCI_SUCCESS; | |
1566 | ||
d9dcb4ba DW |
1567 | for (index = 0; index < ihost->remote_node_entries; index++) { |
1568 | if (ihost->device_table[index] != NULL) { | |
cc9203bf | 1569 | /* / @todo What timeout value do we want to provide to this request? */ |
89a7301f | 1570 | device_status = sci_remote_device_stop(ihost->device_table[index], 0); |
cc9203bf DW |
1571 | |
1572 | if ((device_status != SCI_SUCCESS) && | |
1573 | (device_status != SCI_FAILURE_INVALID_STATE)) { | |
d9dcb4ba | 1574 | dev_warn(&ihost->pdev->dev, |
cc9203bf DW |
1575 | "%s: Controller stop operation failed " |
1576 | "to stop device 0x%p because of " | |
1577 | "status %d.\n", | |
1578 | __func__, | |
d9dcb4ba | 1579 | ihost->device_table[index], device_status); |
cc9203bf DW |
1580 | } |
1581 | } | |
1582 | } | |
1583 | ||
1584 | return status; | |
1585 | } | |
1586 | ||
89a7301f | 1587 | static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1588 | { |
d9dcb4ba | 1589 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf DW |
1590 | |
1591 | /* Stop all of the components for this controller */ | |
89a7301f DW |
1592 | sci_controller_stop_phys(ihost); |
1593 | sci_controller_stop_ports(ihost); | |
1594 | sci_controller_stop_devices(ihost); | |
cc9203bf DW |
1595 | } |
1596 | ||
89a7301f | 1597 | static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm) |
cc9203bf | 1598 | { |
d9dcb4ba | 1599 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf | 1600 | |
d9dcb4ba | 1601 | sci_del_timer(&ihost->timer); |
cc9203bf DW |
1602 | } |
1603 | ||
89a7301f | 1604 | static void sci_controller_reset_hardware(struct isci_host *ihost) |
cc9203bf DW |
1605 | { |
1606 | /* Disable interrupts so we dont take any spurious interrupts */ | |
89a7301f | 1607 | sci_controller_disable_interrupts(ihost); |
cc9203bf DW |
1608 | |
1609 | /* Reset the SCU */ | |
d9dcb4ba | 1610 | writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control); |
cc9203bf DW |
1611 | |
1612 | /* Delay for 1ms to before clearing the CQP and UFQPR. */ | |
1613 | udelay(1000); | |
1614 | ||
1615 | /* The write to the CQGR clears the CQP */ | |
d9dcb4ba | 1616 | writel(0x00000000, &ihost->smu_registers->completion_queue_get); |
cc9203bf DW |
1617 | |
1618 | /* The write to the UFQGP clears the UFQPR */ | |
d9dcb4ba | 1619 | writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); |
cc9203bf DW |
1620 | } |
1621 | ||
89a7301f | 1622 | static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm) |
cc9203bf | 1623 | { |
d9dcb4ba | 1624 | struct isci_host *ihost = container_of(sm, typeof(*ihost), sm); |
cc9203bf | 1625 | |
89a7301f | 1626 | sci_controller_reset_hardware(ihost); |
d9dcb4ba | 1627 | sci_change_state(&ihost->sm, SCIC_RESET); |
cc9203bf DW |
1628 | } |
1629 | ||
89a7301f | 1630 | static const struct sci_base_state sci_controller_state_table[] = { |
e301370a | 1631 | [SCIC_INITIAL] = { |
89a7301f | 1632 | .enter_state = sci_controller_initial_state_enter, |
cc9203bf | 1633 | }, |
e301370a EN |
1634 | [SCIC_RESET] = {}, |
1635 | [SCIC_INITIALIZING] = {}, | |
1636 | [SCIC_INITIALIZED] = {}, | |
1637 | [SCIC_STARTING] = { | |
89a7301f | 1638 | .exit_state = sci_controller_starting_state_exit, |
cc9203bf | 1639 | }, |
e301370a | 1640 | [SCIC_READY] = { |
89a7301f DW |
1641 | .enter_state = sci_controller_ready_state_enter, |
1642 | .exit_state = sci_controller_ready_state_exit, | |
cc9203bf | 1643 | }, |
e301370a | 1644 | [SCIC_RESETTING] = { |
89a7301f | 1645 | .enter_state = sci_controller_resetting_state_enter, |
cc9203bf | 1646 | }, |
e301370a | 1647 | [SCIC_STOPPING] = { |
89a7301f DW |
1648 | .enter_state = sci_controller_stopping_state_enter, |
1649 | .exit_state = sci_controller_stopping_state_exit, | |
cc9203bf | 1650 | }, |
e301370a EN |
1651 | [SCIC_STOPPED] = {}, |
1652 | [SCIC_FAILED] = {} | |
cc9203bf DW |
1653 | }; |
1654 | ||
89a7301f | 1655 | static void sci_controller_set_default_config_parameters(struct isci_host *ihost) |
cc9203bf DW |
1656 | { |
1657 | /* these defaults are overridden by the platform / firmware */ | |
cc9203bf DW |
1658 | u16 index; |
1659 | ||
1660 | /* Default to APC mode. */ | |
89a7301f | 1661 | ihost->oem_parameters.controller.mode_type = SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE; |
cc9203bf DW |
1662 | |
1663 | /* Default to APC mode. */ | |
7000f7c7 | 1664 | ihost->oem_parameters.controller.max_concurr_spin_up = 1; |
cc9203bf DW |
1665 | |
1666 | /* Default to no SSC operation. */ | |
89a7301f | 1667 | ihost->oem_parameters.controller.do_enable_ssc = false; |
cc9203bf DW |
1668 | |
1669 | /* Initialize all of the port parameter information to narrow ports. */ | |
1670 | for (index = 0; index < SCI_MAX_PORTS; index++) { | |
89a7301f | 1671 | ihost->oem_parameters.ports[index].phy_mask = 0; |
cc9203bf DW |
1672 | } |
1673 | ||
1674 | /* Initialize all of the phy parameter information. */ | |
1675 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
1676 | /* Default to 6G (i.e. Gen 3) for now. */ | |
89a7301f | 1677 | ihost->user_parameters.phys[index].max_speed_generation = 3; |
cc9203bf DW |
1678 | |
1679 | /* the frequencies cannot be 0 */ | |
89a7301f DW |
1680 | ihost->user_parameters.phys[index].align_insertion_frequency = 0x7f; |
1681 | ihost->user_parameters.phys[index].in_connection_align_insertion_frequency = 0xff; | |
1682 | ihost->user_parameters.phys[index].notify_enable_spin_up_insertion_frequency = 0x33; | |
cc9203bf DW |
1683 | |
1684 | /* | |
1685 | * Previous Vitesse based expanders had a arbitration issue that | |
1686 | * is worked around by having the upper 32-bits of SAS address | |
1687 | * with a value greater then the Vitesse company identifier. | |
1688 | * Hence, usage of 0x5FCFFFFF. */ | |
89a7301f DW |
1689 | ihost->oem_parameters.phys[index].sas_address.low = 0x1 + ihost->id; |
1690 | ihost->oem_parameters.phys[index].sas_address.high = 0x5FCFFFFF; | |
cc9203bf DW |
1691 | } |
1692 | ||
89a7301f DW |
1693 | ihost->user_parameters.stp_inactivity_timeout = 5; |
1694 | ihost->user_parameters.ssp_inactivity_timeout = 5; | |
1695 | ihost->user_parameters.stp_max_occupancy_timeout = 5; | |
1696 | ihost->user_parameters.ssp_max_occupancy_timeout = 20; | |
1697 | ihost->user_parameters.no_outbound_task_timeout = 20; | |
cc9203bf DW |
1698 | } |
1699 | ||
6cb5853d EN |
1700 | static void controller_timeout(unsigned long data) |
1701 | { | |
1702 | struct sci_timer *tmr = (struct sci_timer *)data; | |
d9dcb4ba DW |
1703 | struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer); |
1704 | struct sci_base_state_machine *sm = &ihost->sm; | |
6cb5853d EN |
1705 | unsigned long flags; |
1706 | ||
1707 | spin_lock_irqsave(&ihost->scic_lock, flags); | |
1708 | ||
1709 | if (tmr->cancel) | |
1710 | goto done; | |
1711 | ||
e301370a | 1712 | if (sm->current_state_id == SCIC_STARTING) |
89a7301f | 1713 | sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT); |
e301370a EN |
1714 | else if (sm->current_state_id == SCIC_STOPPING) { |
1715 | sci_change_state(sm, SCIC_FAILED); | |
6cb5853d EN |
1716 | isci_host_stop_complete(ihost, SCI_FAILURE_TIMEOUT); |
1717 | } else /* / @todo Now what do we want to do in this case? */ | |
d9dcb4ba | 1718 | dev_err(&ihost->pdev->dev, |
6cb5853d EN |
1719 | "%s: Controller timer fired when controller was not " |
1720 | "in a state being timed.\n", | |
1721 | __func__); | |
cc9203bf | 1722 | |
6cb5853d EN |
1723 | done: |
1724 | spin_unlock_irqrestore(&ihost->scic_lock, flags); | |
1725 | } | |
cc9203bf | 1726 | |
89a7301f DW |
1727 | static enum sci_status sci_controller_construct(struct isci_host *ihost, |
1728 | void __iomem *scu_base, | |
1729 | void __iomem *smu_base) | |
cc9203bf | 1730 | { |
cc9203bf DW |
1731 | u8 i; |
1732 | ||
89a7301f | 1733 | sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL); |
cc9203bf | 1734 | |
d9dcb4ba DW |
1735 | ihost->scu_registers = scu_base; |
1736 | ihost->smu_registers = smu_base; | |
cc9203bf | 1737 | |
89a7301f | 1738 | sci_port_configuration_agent_construct(&ihost->port_agent); |
cc9203bf DW |
1739 | |
1740 | /* Construct the ports for this controller */ | |
1741 | for (i = 0; i < SCI_MAX_PORTS; i++) | |
89a7301f DW |
1742 | sci_port_construct(&ihost->ports[i], i, ihost); |
1743 | sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost); | |
cc9203bf DW |
1744 | |
1745 | /* Construct the phys for this controller */ | |
1746 | for (i = 0; i < SCI_MAX_PHYS; i++) { | |
1747 | /* Add all the PHYs to the dummy port */ | |
89a7301f DW |
1748 | sci_phy_construct(&ihost->phys[i], |
1749 | &ihost->ports[SCI_MAX_PORTS], i); | |
cc9203bf DW |
1750 | } |
1751 | ||
d9dcb4ba | 1752 | ihost->invalid_phy_mask = 0; |
cc9203bf | 1753 | |
d9dcb4ba | 1754 | sci_init_timer(&ihost->timer, controller_timeout); |
6cb5853d | 1755 | |
cc9203bf | 1756 | /* Initialize the User and OEM parameters to default values. */ |
89a7301f | 1757 | sci_controller_set_default_config_parameters(ihost); |
cc9203bf | 1758 | |
89a7301f | 1759 | return sci_controller_reset(ihost); |
cc9203bf DW |
1760 | } |
1761 | ||
89a7301f | 1762 | int sci_oem_parameters_validate(struct sci_oem_params *oem) |
cc9203bf DW |
1763 | { |
1764 | int i; | |
1765 | ||
1766 | for (i = 0; i < SCI_MAX_PORTS; i++) | |
1767 | if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX) | |
1768 | return -EINVAL; | |
1769 | ||
1770 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1771 | if (oem->phys[i].sas_address.high == 0 && | |
1772 | oem->phys[i].sas_address.low == 0) | |
1773 | return -EINVAL; | |
1774 | ||
1775 | if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) { | |
1776 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1777 | if (oem->ports[i].phy_mask != 0) | |
1778 | return -EINVAL; | |
1779 | } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) { | |
1780 | u8 phy_mask = 0; | |
1781 | ||
1782 | for (i = 0; i < SCI_MAX_PHYS; i++) | |
1783 | phy_mask |= oem->ports[i].phy_mask; | |
1784 | ||
1785 | if (phy_mask == 0) | |
1786 | return -EINVAL; | |
1787 | } else | |
1788 | return -EINVAL; | |
1789 | ||
7000f7c7 AJ |
1790 | if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT || |
1791 | oem->controller.max_concurr_spin_up < 1) | |
cc9203bf DW |
1792 | return -EINVAL; |
1793 | ||
1794 | return 0; | |
1795 | } | |
1796 | ||
89a7301f | 1797 | static enum sci_status sci_oem_parameters_set(struct isci_host *ihost) |
cc9203bf | 1798 | { |
d9dcb4ba | 1799 | u32 state = ihost->sm.current_state_id; |
cc9203bf | 1800 | |
e301370a EN |
1801 | if (state == SCIC_RESET || |
1802 | state == SCIC_INITIALIZING || | |
1803 | state == SCIC_INITIALIZED) { | |
cc9203bf | 1804 | |
89a7301f | 1805 | if (sci_oem_parameters_validate(&ihost->oem_parameters)) |
cc9203bf | 1806 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
cc9203bf DW |
1807 | |
1808 | return SCI_SUCCESS; | |
1809 | } | |
1810 | ||
1811 | return SCI_FAILURE_INVALID_STATE; | |
1812 | } | |
1813 | ||
7000f7c7 AJ |
1814 | static u8 max_spin_up(struct isci_host *ihost) |
1815 | { | |
1816 | if (ihost->user_parameters.max_concurr_spinup) | |
1817 | return min_t(u8, ihost->user_parameters.max_concurr_spinup, | |
1818 | MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); | |
1819 | else | |
1820 | return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up, | |
1821 | MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT); | |
1822 | } | |
1823 | ||
0473661a | 1824 | static void power_control_timeout(unsigned long data) |
cc9203bf | 1825 | { |
0473661a | 1826 | struct sci_timer *tmr = (struct sci_timer *)data; |
d9dcb4ba | 1827 | struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer); |
85280955 | 1828 | struct isci_phy *iphy; |
0473661a EN |
1829 | unsigned long flags; |
1830 | u8 i; | |
cc9203bf | 1831 | |
0473661a | 1832 | spin_lock_irqsave(&ihost->scic_lock, flags); |
cc9203bf | 1833 | |
0473661a EN |
1834 | if (tmr->cancel) |
1835 | goto done; | |
1836 | ||
d9dcb4ba | 1837 | ihost->power_control.phys_granted_power = 0; |
0473661a | 1838 | |
d9dcb4ba DW |
1839 | if (ihost->power_control.phys_waiting == 0) { |
1840 | ihost->power_control.timer_started = false; | |
0473661a | 1841 | goto done; |
cc9203bf | 1842 | } |
cc9203bf | 1843 | |
0473661a | 1844 | for (i = 0; i < SCI_MAX_PHYS; i++) { |
cc9203bf | 1845 | |
d9dcb4ba | 1846 | if (ihost->power_control.phys_waiting == 0) |
0473661a | 1847 | break; |
cc9203bf | 1848 | |
d9dcb4ba | 1849 | iphy = ihost->power_control.requesters[i]; |
85280955 | 1850 | if (iphy == NULL) |
0473661a | 1851 | continue; |
cc9203bf | 1852 | |
7000f7c7 | 1853 | if (ihost->power_control.phys_granted_power >= max_spin_up(ihost)) |
0473661a | 1854 | break; |
cc9203bf | 1855 | |
d9dcb4ba DW |
1856 | ihost->power_control.requesters[i] = NULL; |
1857 | ihost->power_control.phys_waiting--; | |
1858 | ihost->power_control.phys_granted_power++; | |
89a7301f | 1859 | sci_phy_consume_power_handler(iphy); |
cc9203bf | 1860 | } |
0473661a EN |
1861 | |
1862 | /* | |
1863 | * It doesn't matter if the power list is empty, we need to start the | |
1864 | * timer in case another phy becomes ready. | |
1865 | */ | |
1866 | sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); | |
d9dcb4ba | 1867 | ihost->power_control.timer_started = true; |
0473661a EN |
1868 | |
1869 | done: | |
1870 | spin_unlock_irqrestore(&ihost->scic_lock, flags); | |
cc9203bf DW |
1871 | } |
1872 | ||
89a7301f DW |
1873 | void sci_controller_power_control_queue_insert(struct isci_host *ihost, |
1874 | struct isci_phy *iphy) | |
cc9203bf | 1875 | { |
85280955 | 1876 | BUG_ON(iphy == NULL); |
cc9203bf | 1877 | |
7000f7c7 | 1878 | if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) { |
d9dcb4ba | 1879 | ihost->power_control.phys_granted_power++; |
89a7301f | 1880 | sci_phy_consume_power_handler(iphy); |
cc9203bf DW |
1881 | |
1882 | /* | |
1883 | * stop and start the power_control timer. When the timer fires, the | |
1884 | * no_of_phys_granted_power will be set to 0 | |
1885 | */ | |
d9dcb4ba DW |
1886 | if (ihost->power_control.timer_started) |
1887 | sci_del_timer(&ihost->power_control.timer); | |
0473661a | 1888 | |
d9dcb4ba | 1889 | sci_mod_timer(&ihost->power_control.timer, |
0473661a | 1890 | SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL); |
d9dcb4ba | 1891 | ihost->power_control.timer_started = true; |
0473661a | 1892 | |
cc9203bf DW |
1893 | } else { |
1894 | /* Add the phy in the waiting list */ | |
d9dcb4ba DW |
1895 | ihost->power_control.requesters[iphy->phy_index] = iphy; |
1896 | ihost->power_control.phys_waiting++; | |
cc9203bf DW |
1897 | } |
1898 | } | |
1899 | ||
89a7301f DW |
1900 | void sci_controller_power_control_queue_remove(struct isci_host *ihost, |
1901 | struct isci_phy *iphy) | |
cc9203bf | 1902 | { |
85280955 | 1903 | BUG_ON(iphy == NULL); |
cc9203bf | 1904 | |
89a7301f | 1905 | if (ihost->power_control.requesters[iphy->phy_index]) |
d9dcb4ba | 1906 | ihost->power_control.phys_waiting--; |
cc9203bf | 1907 | |
d9dcb4ba | 1908 | ihost->power_control.requesters[iphy->phy_index] = NULL; |
cc9203bf DW |
1909 | } |
1910 | ||
1911 | #define AFE_REGISTER_WRITE_DELAY 10 | |
1912 | ||
1913 | /* Initialize the AFE for this phy index. We need to read the AFE setup from | |
1914 | * the OEM parameters | |
1915 | */ | |
89a7301f | 1916 | static void sci_controller_afe_initialization(struct isci_host *ihost) |
cc9203bf | 1917 | { |
89a7301f | 1918 | const struct sci_oem_params *oem = &ihost->oem_parameters; |
dc00c8b6 | 1919 | struct pci_dev *pdev = ihost->pdev; |
cc9203bf DW |
1920 | u32 afe_status; |
1921 | u32 phy_id; | |
1922 | ||
1923 | /* Clear DFX Status registers */ | |
d9dcb4ba | 1924 | writel(0x0081000f, &ihost->scu_registers->afe.afe_dfx_master_control0); |
cc9203bf DW |
1925 | udelay(AFE_REGISTER_WRITE_DELAY); |
1926 | ||
dc00c8b6 | 1927 | if (is_b0(pdev)) { |
cc9203bf DW |
1928 | /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement |
1929 | * Timer, PM Stagger Timer */ | |
d9dcb4ba | 1930 | writel(0x0007BFFF, &ihost->scu_registers->afe.afe_pmsn_master_control2); |
cc9203bf DW |
1931 | udelay(AFE_REGISTER_WRITE_DELAY); |
1932 | } | |
1933 | ||
1934 | /* Configure bias currents to normal */ | |
dc00c8b6 | 1935 | if (is_a2(pdev)) |
d9dcb4ba | 1936 | writel(0x00005A00, &ihost->scu_registers->afe.afe_bias_control); |
dc00c8b6 | 1937 | else if (is_b0(pdev) || is_c0(pdev)) |
d9dcb4ba | 1938 | writel(0x00005F00, &ihost->scu_registers->afe.afe_bias_control); |
cc9203bf DW |
1939 | |
1940 | udelay(AFE_REGISTER_WRITE_DELAY); | |
1941 | ||
1942 | /* Enable PLL */ | |
dc00c8b6 | 1943 | if (is_b0(pdev) || is_c0(pdev)) |
d9dcb4ba | 1944 | writel(0x80040A08, &ihost->scu_registers->afe.afe_pll_control0); |
cc9203bf | 1945 | else |
d9dcb4ba | 1946 | writel(0x80040908, &ihost->scu_registers->afe.afe_pll_control0); |
cc9203bf DW |
1947 | |
1948 | udelay(AFE_REGISTER_WRITE_DELAY); | |
1949 | ||
1950 | /* Wait for the PLL to lock */ | |
1951 | do { | |
d9dcb4ba | 1952 | afe_status = readl(&ihost->scu_registers->afe.afe_common_block_status); |
cc9203bf DW |
1953 | udelay(AFE_REGISTER_WRITE_DELAY); |
1954 | } while ((afe_status & 0x00001000) == 0); | |
1955 | ||
dc00c8b6 | 1956 | if (is_a2(pdev)) { |
cc9203bf | 1957 | /* Shorten SAS SNW lock time (RxLock timer value from 76 us to 50 us) */ |
d9dcb4ba | 1958 | writel(0x7bcc96ad, &ihost->scu_registers->afe.afe_pmsn_master_control0); |
cc9203bf DW |
1959 | udelay(AFE_REGISTER_WRITE_DELAY); |
1960 | } | |
1961 | ||
1962 | for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) { | |
1963 | const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id]; | |
1964 | ||
dc00c8b6 | 1965 | if (is_b0(pdev)) { |
cc9203bf | 1966 | /* Configure transmitter SSC parameters */ |
d9dcb4ba | 1967 | writel(0x00030000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); |
cc9203bf | 1968 | udelay(AFE_REGISTER_WRITE_DELAY); |
dc00c8b6 | 1969 | } else if (is_c0(pdev)) { |
dbb0743a | 1970 | /* Configure transmitter SSC parameters */ |
d9dcb4ba | 1971 | writel(0x0003000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_ssc_control); |
dbb0743a AG |
1972 | udelay(AFE_REGISTER_WRITE_DELAY); |
1973 | ||
1974 | /* | |
1975 | * All defaults, except the Receive Word Alignament/Comma Detect | |
1976 | * Enable....(0xe800) */ | |
d9dcb4ba | 1977 | writel(0x00004500, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); |
dbb0743a | 1978 | udelay(AFE_REGISTER_WRITE_DELAY); |
cc9203bf DW |
1979 | } else { |
1980 | /* | |
1981 | * All defaults, except the Receive Word Alignament/Comma Detect | |
1982 | * Enable....(0xe800) */ | |
d9dcb4ba | 1983 | writel(0x00004512, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); |
cc9203bf DW |
1984 | udelay(AFE_REGISTER_WRITE_DELAY); |
1985 | ||
d9dcb4ba | 1986 | writel(0x0050100F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control1); |
cc9203bf DW |
1987 | udelay(AFE_REGISTER_WRITE_DELAY); |
1988 | } | |
1989 | ||
1990 | /* | |
1991 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
1992 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
dc00c8b6 | 1993 | if (is_a2(pdev)) |
d9dcb4ba | 1994 | writel(0x000003F0, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
dc00c8b6 | 1995 | else if (is_b0(pdev)) { |
cc9203bf | 1996 | /* Power down TX and RX (PWRDNTX and PWRDNRX) */ |
d9dcb4ba | 1997 | writel(0x000003D7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
dbb0743a AG |
1998 | udelay(AFE_REGISTER_WRITE_DELAY); |
1999 | ||
2000 | /* | |
2001 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
2002 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
d9dcb4ba | 2003 | writel(0x000003D4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
dbb0743a | 2004 | } else { |
d9dcb4ba | 2005 | writel(0x000001E7, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
cc9203bf DW |
2006 | udelay(AFE_REGISTER_WRITE_DELAY); |
2007 | ||
2008 | /* | |
2009 | * Power up TX and RX out from power down (PWRDNTX and PWRDNRX) | |
2010 | * & increase TX int & ext bias 20%....(0xe85c) */ | |
d9dcb4ba | 2011 | writel(0x000001E4, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_channel_control); |
cc9203bf DW |
2012 | } |
2013 | udelay(AFE_REGISTER_WRITE_DELAY); | |
2014 | ||
dc00c8b6 | 2015 | if (is_a2(pdev)) { |
cc9203bf | 2016 | /* Enable TX equalization (0xe824) */ |
d9dcb4ba | 2017 | writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); |
cc9203bf DW |
2018 | udelay(AFE_REGISTER_WRITE_DELAY); |
2019 | } | |
2020 | ||
2021 | /* | |
2022 | * RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0, TPD=0x0(TX Power On), | |
2023 | * RDD=0x0(RX Detect Enabled) ....(0xe800) */ | |
d9dcb4ba | 2024 | writel(0x00004100, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_xcvr_control0); |
cc9203bf DW |
2025 | udelay(AFE_REGISTER_WRITE_DELAY); |
2026 | ||
2027 | /* Leave DFE/FFE on */ | |
dc00c8b6 | 2028 | if (is_a2(pdev)) |
d9dcb4ba | 2029 | writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
dc00c8b6 | 2030 | else if (is_b0(pdev)) { |
d9dcb4ba | 2031 | writel(0x3F11103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
cc9203bf | 2032 | udelay(AFE_REGISTER_WRITE_DELAY); |
dbb0743a | 2033 | /* Enable TX equalization (0xe824) */ |
d9dcb4ba | 2034 | writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); |
dbb0743a | 2035 | } else { |
d9dcb4ba | 2036 | writel(0x0140DF0F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control1); |
dbb0743a AG |
2037 | udelay(AFE_REGISTER_WRITE_DELAY); |
2038 | ||
d9dcb4ba | 2039 | writel(0x3F6F103F, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_rx_ssc_control0); |
dbb0743a AG |
2040 | udelay(AFE_REGISTER_WRITE_DELAY); |
2041 | ||
cc9203bf | 2042 | /* Enable TX equalization (0xe824) */ |
d9dcb4ba | 2043 | writel(0x00040000, &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_control); |
cc9203bf | 2044 | } |
dbb0743a | 2045 | |
cc9203bf DW |
2046 | udelay(AFE_REGISTER_WRITE_DELAY); |
2047 | ||
2048 | writel(oem_phy->afe_tx_amp_control0, | |
d9dcb4ba | 2049 | &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control0); |
cc9203bf DW |
2050 | udelay(AFE_REGISTER_WRITE_DELAY); |
2051 | ||
2052 | writel(oem_phy->afe_tx_amp_control1, | |
d9dcb4ba | 2053 | &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control1); |
cc9203bf DW |
2054 | udelay(AFE_REGISTER_WRITE_DELAY); |
2055 | ||
2056 | writel(oem_phy->afe_tx_amp_control2, | |
d9dcb4ba | 2057 | &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control2); |
cc9203bf DW |
2058 | udelay(AFE_REGISTER_WRITE_DELAY); |
2059 | ||
2060 | writel(oem_phy->afe_tx_amp_control3, | |
d9dcb4ba | 2061 | &ihost->scu_registers->afe.scu_afe_xcvr[phy_id].afe_tx_amp_control3); |
cc9203bf DW |
2062 | udelay(AFE_REGISTER_WRITE_DELAY); |
2063 | } | |
2064 | ||
2065 | /* Transfer control to the PEs */ | |
d9dcb4ba | 2066 | writel(0x00010f00, &ihost->scu_registers->afe.afe_dfx_master_control0); |
cc9203bf DW |
2067 | udelay(AFE_REGISTER_WRITE_DELAY); |
2068 | } | |
2069 | ||
89a7301f | 2070 | static void sci_controller_initialize_power_control(struct isci_host *ihost) |
cc9203bf | 2071 | { |
d9dcb4ba | 2072 | sci_init_timer(&ihost->power_control.timer, power_control_timeout); |
cc9203bf | 2073 | |
d9dcb4ba DW |
2074 | memset(ihost->power_control.requesters, 0, |
2075 | sizeof(ihost->power_control.requesters)); | |
cc9203bf | 2076 | |
d9dcb4ba DW |
2077 | ihost->power_control.phys_waiting = 0; |
2078 | ihost->power_control.phys_granted_power = 0; | |
cc9203bf DW |
2079 | } |
2080 | ||
89a7301f | 2081 | static enum sci_status sci_controller_initialize(struct isci_host *ihost) |
cc9203bf | 2082 | { |
d9dcb4ba | 2083 | struct sci_base_state_machine *sm = &ihost->sm; |
7c78da31 DW |
2084 | enum sci_status result = SCI_FAILURE; |
2085 | unsigned long i, state, val; | |
cc9203bf | 2086 | |
d9dcb4ba DW |
2087 | if (ihost->sm.current_state_id != SCIC_RESET) { |
2088 | dev_warn(&ihost->pdev->dev, | |
cc9203bf DW |
2089 | "SCIC Controller initialize operation requested " |
2090 | "in invalid state\n"); | |
2091 | return SCI_FAILURE_INVALID_STATE; | |
2092 | } | |
2093 | ||
e301370a | 2094 | sci_change_state(sm, SCIC_INITIALIZING); |
cc9203bf | 2095 | |
d9dcb4ba | 2096 | sci_init_timer(&ihost->phy_timer, phy_startup_timeout); |
bb3dbdf6 | 2097 | |
d9dcb4ba DW |
2098 | ihost->next_phy_to_start = 0; |
2099 | ihost->phy_startup_timer_pending = false; | |
cc9203bf | 2100 | |
89a7301f | 2101 | sci_controller_initialize_power_control(ihost); |
cc9203bf DW |
2102 | |
2103 | /* | |
2104 | * There is nothing to do here for B0 since we do not have to | |
2105 | * program the AFE registers. | |
2106 | * / @todo The AFE settings are supposed to be correct for the B0 but | |
2107 | * / presently they seem to be wrong. */ | |
89a7301f | 2108 | sci_controller_afe_initialization(ihost); |
cc9203bf | 2109 | |
cc9203bf | 2110 | |
7c78da31 | 2111 | /* Take the hardware out of reset */ |
d9dcb4ba | 2112 | writel(0, &ihost->smu_registers->soft_reset_control); |
cc9203bf | 2113 | |
7c78da31 DW |
2114 | /* |
2115 | * / @todo Provide meaningfull error code for hardware failure | |
2116 | * result = SCI_FAILURE_CONTROLLER_HARDWARE; */ | |
2117 | for (i = 100; i >= 1; i--) { | |
2118 | u32 status; | |
cc9203bf | 2119 | |
7c78da31 DW |
2120 | /* Loop until the hardware reports success */ |
2121 | udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME); | |
d9dcb4ba | 2122 | status = readl(&ihost->smu_registers->control_status); |
cc9203bf | 2123 | |
7c78da31 DW |
2124 | if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED) |
2125 | break; | |
2126 | } | |
2127 | if (i == 0) | |
2128 | goto out; | |
cc9203bf | 2129 | |
7c78da31 DW |
2130 | /* |
2131 | * Determine what are the actaul device capacities that the | |
2132 | * hardware will support */ | |
d9dcb4ba | 2133 | val = readl(&ihost->smu_registers->device_context_capacity); |
cc9203bf | 2134 | |
7c78da31 | 2135 | /* Record the smaller of the two capacity values */ |
d9dcb4ba DW |
2136 | ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS); |
2137 | ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS); | |
2138 | ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES); | |
cc9203bf | 2139 | |
7c78da31 DW |
2140 | /* |
2141 | * Make all PEs that are unassigned match up with the | |
2142 | * logical ports | |
2143 | */ | |
d9dcb4ba | 2144 | for (i = 0; i < ihost->logical_port_entries; i++) { |
7c78da31 | 2145 | struct scu_port_task_scheduler_group_registers __iomem |
d9dcb4ba | 2146 | *ptsg = &ihost->scu_registers->peg0.ptsg; |
cc9203bf | 2147 | |
7c78da31 | 2148 | writel(i, &ptsg->protocol_engine[i]); |
cc9203bf DW |
2149 | } |
2150 | ||
2151 | /* Initialize hardware PCI Relaxed ordering in DMA engines */ | |
d9dcb4ba | 2152 | val = readl(&ihost->scu_registers->sdma.pdma_configuration); |
7c78da31 | 2153 | val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); |
d9dcb4ba | 2154 | writel(val, &ihost->scu_registers->sdma.pdma_configuration); |
7c78da31 | 2155 | |
d9dcb4ba | 2156 | val = readl(&ihost->scu_registers->sdma.cdma_configuration); |
7c78da31 | 2157 | val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE); |
d9dcb4ba | 2158 | writel(val, &ihost->scu_registers->sdma.cdma_configuration); |
cc9203bf DW |
2159 | |
2160 | /* | |
2161 | * Initialize the PHYs before the PORTs because the PHY registers | |
2162 | * are accessed during the port initialization. | |
2163 | */ | |
7c78da31 | 2164 | for (i = 0; i < SCI_MAX_PHYS; i++) { |
89a7301f DW |
2165 | result = sci_phy_initialize(&ihost->phys[i], |
2166 | &ihost->scu_registers->peg0.pe[i].tl, | |
2167 | &ihost->scu_registers->peg0.pe[i].ll); | |
7c78da31 DW |
2168 | if (result != SCI_SUCCESS) |
2169 | goto out; | |
cc9203bf DW |
2170 | } |
2171 | ||
d9dcb4ba | 2172 | for (i = 0; i < ihost->logical_port_entries; i++) { |
89a7301f | 2173 | struct isci_port *iport = &ihost->ports[i]; |
7c78da31 | 2174 | |
89a7301f DW |
2175 | iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i]; |
2176 | iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0]; | |
2177 | iport->viit_registers = &ihost->scu_registers->peg0.viit[i]; | |
cc9203bf DW |
2178 | } |
2179 | ||
89a7301f | 2180 | result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent); |
cc9203bf | 2181 | |
7c78da31 | 2182 | out: |
cc9203bf DW |
2183 | /* Advance the controller state machine */ |
2184 | if (result == SCI_SUCCESS) | |
e301370a | 2185 | state = SCIC_INITIALIZED; |
cc9203bf | 2186 | else |
e301370a EN |
2187 | state = SCIC_FAILED; |
2188 | sci_change_state(sm, state); | |
cc9203bf DW |
2189 | |
2190 | return result; | |
2191 | } | |
2192 | ||
89a7301f DW |
2193 | static enum sci_status sci_user_parameters_set(struct isci_host *ihost, |
2194 | struct sci_user_parameters *sci_parms) | |
cc9203bf | 2195 | { |
d9dcb4ba | 2196 | u32 state = ihost->sm.current_state_id; |
cc9203bf | 2197 | |
e301370a EN |
2198 | if (state == SCIC_RESET || |
2199 | state == SCIC_INITIALIZING || | |
2200 | state == SCIC_INITIALIZED) { | |
cc9203bf DW |
2201 | u16 index; |
2202 | ||
2203 | /* | |
2204 | * Validate the user parameters. If they are not legal, then | |
2205 | * return a failure. | |
2206 | */ | |
2207 | for (index = 0; index < SCI_MAX_PHYS; index++) { | |
2208 | struct sci_phy_user_params *user_phy; | |
2209 | ||
89a7301f | 2210 | user_phy = &sci_parms->phys[index]; |
cc9203bf DW |
2211 | |
2212 | if (!((user_phy->max_speed_generation <= | |
2213 | SCIC_SDS_PARM_MAX_SPEED) && | |
2214 | (user_phy->max_speed_generation > | |
2215 | SCIC_SDS_PARM_NO_SPEED))) | |
2216 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2217 | ||
2218 | if (user_phy->in_connection_align_insertion_frequency < | |
2219 | 3) | |
2220 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2221 | ||
2222 | if ((user_phy->in_connection_align_insertion_frequency < | |
2223 | 3) || | |
2224 | (user_phy->align_insertion_frequency == 0) || | |
2225 | (user_phy-> | |
2226 | notify_enable_spin_up_insertion_frequency == | |
2227 | 0)) | |
2228 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; | |
2229 | } | |
2230 | ||
89a7301f DW |
2231 | if ((sci_parms->stp_inactivity_timeout == 0) || |
2232 | (sci_parms->ssp_inactivity_timeout == 0) || | |
2233 | (sci_parms->stp_max_occupancy_timeout == 0) || | |
2234 | (sci_parms->ssp_max_occupancy_timeout == 0) || | |
2235 | (sci_parms->no_outbound_task_timeout == 0)) | |
cc9203bf DW |
2236 | return SCI_FAILURE_INVALID_PARAMETER_VALUE; |
2237 | ||
89a7301f | 2238 | memcpy(&ihost->user_parameters, sci_parms, sizeof(*sci_parms)); |
cc9203bf DW |
2239 | |
2240 | return SCI_SUCCESS; | |
2241 | } | |
2242 | ||
2243 | return SCI_FAILURE_INVALID_STATE; | |
2244 | } | |
2245 | ||
89a7301f | 2246 | static int sci_controller_mem_init(struct isci_host *ihost) |
cc9203bf | 2247 | { |
d9dcb4ba | 2248 | struct device *dev = &ihost->pdev->dev; |
7c78da31 DW |
2249 | dma_addr_t dma; |
2250 | size_t size; | |
2251 | int err; | |
cc9203bf | 2252 | |
7c78da31 | 2253 | size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32); |
d9dcb4ba DW |
2254 | ihost->completion_queue = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); |
2255 | if (!ihost->completion_queue) | |
cc9203bf DW |
2256 | return -ENOMEM; |
2257 | ||
d9dcb4ba DW |
2258 | writel(lower_32_bits(dma), &ihost->smu_registers->completion_queue_lower); |
2259 | writel(upper_32_bits(dma), &ihost->smu_registers->completion_queue_upper); | |
cc9203bf | 2260 | |
d9dcb4ba DW |
2261 | size = ihost->remote_node_entries * sizeof(union scu_remote_node_context); |
2262 | ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &dma, | |
89a7301f | 2263 | GFP_KERNEL); |
d9dcb4ba | 2264 | if (!ihost->remote_node_context_table) |
cc9203bf DW |
2265 | return -ENOMEM; |
2266 | ||
d9dcb4ba DW |
2267 | writel(lower_32_bits(dma), &ihost->smu_registers->remote_node_context_lower); |
2268 | writel(upper_32_bits(dma), &ihost->smu_registers->remote_node_context_upper); | |
cc9203bf | 2269 | |
d9dcb4ba DW |
2270 | size = ihost->task_context_entries * sizeof(struct scu_task_context), |
2271 | ihost->task_context_table = dmam_alloc_coherent(dev, size, &dma, GFP_KERNEL); | |
2272 | if (!ihost->task_context_table) | |
cc9203bf DW |
2273 | return -ENOMEM; |
2274 | ||
d9dcb4ba DW |
2275 | ihost->task_context_dma = dma; |
2276 | writel(lower_32_bits(dma), &ihost->smu_registers->host_task_table_lower); | |
2277 | writel(upper_32_bits(dma), &ihost->smu_registers->host_task_table_upper); | |
cc9203bf | 2278 | |
89a7301f | 2279 | err = sci_unsolicited_frame_control_construct(ihost); |
7c78da31 DW |
2280 | if (err) |
2281 | return err; | |
cc9203bf DW |
2282 | |
2283 | /* | |
2284 | * Inform the silicon as to the location of the UF headers and | |
2285 | * address table. | |
2286 | */ | |
d9dcb4ba DW |
2287 | writel(lower_32_bits(ihost->uf_control.headers.physical_address), |
2288 | &ihost->scu_registers->sdma.uf_header_base_address_lower); | |
2289 | writel(upper_32_bits(ihost->uf_control.headers.physical_address), | |
2290 | &ihost->scu_registers->sdma.uf_header_base_address_upper); | |
cc9203bf | 2291 | |
d9dcb4ba DW |
2292 | writel(lower_32_bits(ihost->uf_control.address_table.physical_address), |
2293 | &ihost->scu_registers->sdma.uf_address_table_lower); | |
2294 | writel(upper_32_bits(ihost->uf_control.address_table.physical_address), | |
2295 | &ihost->scu_registers->sdma.uf_address_table_upper); | |
cc9203bf DW |
2296 | |
2297 | return 0; | |
2298 | } | |
2299 | ||
d9dcb4ba | 2300 | int isci_host_init(struct isci_host *ihost) |
6f231dda | 2301 | { |
d9c37390 | 2302 | int err = 0, i; |
6f231dda | 2303 | enum sci_status status; |
89a7301f | 2304 | struct sci_user_parameters sci_user_params; |
d9dcb4ba | 2305 | struct isci_pci_info *pci_info = to_pci_info(ihost->pdev); |
6f231dda | 2306 | |
d9dcb4ba DW |
2307 | spin_lock_init(&ihost->state_lock); |
2308 | spin_lock_init(&ihost->scic_lock); | |
2309 | init_waitqueue_head(&ihost->eventq); | |
6f231dda | 2310 | |
d9dcb4ba | 2311 | isci_host_change_state(ihost, isci_starting); |
6f231dda | 2312 | |
89a7301f DW |
2313 | status = sci_controller_construct(ihost, scu_base(ihost), |
2314 | smu_base(ihost)); | |
6f231dda DW |
2315 | |
2316 | if (status != SCI_SUCCESS) { | |
d9dcb4ba | 2317 | dev_err(&ihost->pdev->dev, |
89a7301f | 2318 | "%s: sci_controller_construct failed - status = %x\n", |
6f231dda DW |
2319 | __func__, |
2320 | status); | |
858d4aa7 | 2321 | return -ENODEV; |
6f231dda DW |
2322 | } |
2323 | ||
d9dcb4ba DW |
2324 | ihost->sas_ha.dev = &ihost->pdev->dev; |
2325 | ihost->sas_ha.lldd_ha = ihost; | |
6f231dda | 2326 | |
d044af17 DW |
2327 | /* |
2328 | * grab initial values stored in the controller object for OEM and USER | |
2329 | * parameters | |
2330 | */ | |
89a7301f DW |
2331 | isci_user_parameters_get(&sci_user_params); |
2332 | status = sci_user_parameters_set(ihost, &sci_user_params); | |
d044af17 | 2333 | if (status != SCI_SUCCESS) { |
d9dcb4ba | 2334 | dev_warn(&ihost->pdev->dev, |
89a7301f | 2335 | "%s: sci_user_parameters_set failed\n", |
d044af17 DW |
2336 | __func__); |
2337 | return -ENODEV; | |
2338 | } | |
2339 | ||
d044af17 DW |
2340 | /* grab any OEM parameters specified in orom */ |
2341 | if (pci_info->orom) { | |
89a7301f | 2342 | status = isci_parse_oem_parameters(&ihost->oem_parameters, |
d044af17 | 2343 | pci_info->orom, |
d9dcb4ba | 2344 | ihost->id); |
6f231dda | 2345 | if (status != SCI_SUCCESS) { |
d9dcb4ba | 2346 | dev_warn(&ihost->pdev->dev, |
6f231dda | 2347 | "parsing firmware oem parameters failed\n"); |
858d4aa7 | 2348 | return -EINVAL; |
6f231dda | 2349 | } |
4711ba10 DW |
2350 | } |
2351 | ||
89a7301f | 2352 | status = sci_oem_parameters_set(ihost); |
4711ba10 | 2353 | if (status != SCI_SUCCESS) { |
d9dcb4ba | 2354 | dev_warn(&ihost->pdev->dev, |
89a7301f | 2355 | "%s: sci_oem_parameters_set failed\n", |
4711ba10 DW |
2356 | __func__); |
2357 | return -ENODEV; | |
6f231dda DW |
2358 | } |
2359 | ||
d9dcb4ba DW |
2360 | tasklet_init(&ihost->completion_tasklet, |
2361 | isci_host_completion_routine, (unsigned long)ihost); | |
7c40a803 | 2362 | |
d9dcb4ba DW |
2363 | INIT_LIST_HEAD(&ihost->requests_to_complete); |
2364 | INIT_LIST_HEAD(&ihost->requests_to_errorback); | |
7c40a803 | 2365 | |
d9dcb4ba | 2366 | spin_lock_irq(&ihost->scic_lock); |
89a7301f | 2367 | status = sci_controller_initialize(ihost); |
d9dcb4ba | 2368 | spin_unlock_irq(&ihost->scic_lock); |
6f231dda | 2369 | if (status != SCI_SUCCESS) { |
d9dcb4ba | 2370 | dev_warn(&ihost->pdev->dev, |
89a7301f | 2371 | "%s: sci_controller_initialize failed -" |
6f231dda DW |
2372 | " status = 0x%x\n", |
2373 | __func__, status); | |
858d4aa7 | 2374 | return -ENODEV; |
6f231dda DW |
2375 | } |
2376 | ||
89a7301f | 2377 | err = sci_controller_mem_init(ihost); |
6f231dda | 2378 | if (err) |
858d4aa7 | 2379 | return err; |
6f231dda | 2380 | |
d9c37390 | 2381 | for (i = 0; i < SCI_MAX_PORTS; i++) |
d9dcb4ba | 2382 | isci_port_init(&ihost->ports[i], ihost, i); |
6f231dda | 2383 | |
d9c37390 | 2384 | for (i = 0; i < SCI_MAX_PHYS; i++) |
d9dcb4ba | 2385 | isci_phy_init(&ihost->phys[i], ihost, i); |
d9c37390 | 2386 | |
ad4f4c1d DW |
2387 | /* enable sgpio */ |
2388 | writel(1, &ihost->scu_registers->peg0.sgpio.interface_control); | |
2389 | for (i = 0; i < isci_gpio_count(ihost); i++) | |
2390 | writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]); | |
2391 | writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code); | |
2392 | ||
d9c37390 | 2393 | for (i = 0; i < SCI_MAX_REMOTE_DEVICES; i++) { |
d9dcb4ba | 2394 | struct isci_remote_device *idev = &ihost->devices[i]; |
d9c37390 DW |
2395 | |
2396 | INIT_LIST_HEAD(&idev->reqs_in_process); | |
2397 | INIT_LIST_HEAD(&idev->node); | |
d9c37390 | 2398 | } |
6f231dda | 2399 | |
db056250 DW |
2400 | for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) { |
2401 | struct isci_request *ireq; | |
2402 | dma_addr_t dma; | |
2403 | ||
d9dcb4ba | 2404 | ireq = dmam_alloc_coherent(&ihost->pdev->dev, |
db056250 DW |
2405 | sizeof(struct isci_request), &dma, |
2406 | GFP_KERNEL); | |
2407 | if (!ireq) | |
2408 | return -ENOMEM; | |
2409 | ||
d9dcb4ba DW |
2410 | ireq->tc = &ihost->task_context_table[i]; |
2411 | ireq->owning_controller = ihost; | |
db056250 DW |
2412 | spin_lock_init(&ireq->state_lock); |
2413 | ireq->request_daddr = dma; | |
d9dcb4ba DW |
2414 | ireq->isci_host = ihost; |
2415 | ihost->reqs[i] = ireq; | |
db056250 DW |
2416 | } |
2417 | ||
858d4aa7 | 2418 | return 0; |
6f231dda | 2419 | } |
cc9203bf | 2420 | |
89a7301f DW |
2421 | void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport, |
2422 | struct isci_phy *iphy) | |
cc9203bf | 2423 | { |
d9dcb4ba | 2424 | switch (ihost->sm.current_state_id) { |
e301370a | 2425 | case SCIC_STARTING: |
d9dcb4ba DW |
2426 | sci_del_timer(&ihost->phy_timer); |
2427 | ihost->phy_startup_timer_pending = false; | |
2428 | ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, | |
89a7301f DW |
2429 | iport, iphy); |
2430 | sci_controller_start_next_phy(ihost); | |
cc9203bf | 2431 | break; |
e301370a | 2432 | case SCIC_READY: |
d9dcb4ba | 2433 | ihost->port_agent.link_up_handler(ihost, &ihost->port_agent, |
89a7301f | 2434 | iport, iphy); |
cc9203bf DW |
2435 | break; |
2436 | default: | |
d9dcb4ba | 2437 | dev_dbg(&ihost->pdev->dev, |
cc9203bf | 2438 | "%s: SCIC Controller linkup event from phy %d in " |
85280955 | 2439 | "unexpected state %d\n", __func__, iphy->phy_index, |
d9dcb4ba | 2440 | ihost->sm.current_state_id); |
cc9203bf DW |
2441 | } |
2442 | } | |
2443 | ||
89a7301f DW |
2444 | void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport, |
2445 | struct isci_phy *iphy) | |
cc9203bf | 2446 | { |
d9dcb4ba | 2447 | switch (ihost->sm.current_state_id) { |
e301370a EN |
2448 | case SCIC_STARTING: |
2449 | case SCIC_READY: | |
d9dcb4ba | 2450 | ihost->port_agent.link_down_handler(ihost, &ihost->port_agent, |
ffe191c9 | 2451 | iport, iphy); |
cc9203bf DW |
2452 | break; |
2453 | default: | |
d9dcb4ba | 2454 | dev_dbg(&ihost->pdev->dev, |
cc9203bf DW |
2455 | "%s: SCIC Controller linkdown event from phy %d in " |
2456 | "unexpected state %d\n", | |
2457 | __func__, | |
85280955 | 2458 | iphy->phy_index, |
d9dcb4ba | 2459 | ihost->sm.current_state_id); |
cc9203bf DW |
2460 | } |
2461 | } | |
2462 | ||
89a7301f | 2463 | static bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost) |
cc9203bf DW |
2464 | { |
2465 | u32 index; | |
2466 | ||
d9dcb4ba DW |
2467 | for (index = 0; index < ihost->remote_node_entries; index++) { |
2468 | if ((ihost->device_table[index] != NULL) && | |
2469 | (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING)) | |
cc9203bf DW |
2470 | return true; |
2471 | } | |
2472 | ||
2473 | return false; | |
2474 | } | |
2475 | ||
89a7301f DW |
2476 | void sci_controller_remote_device_stopped(struct isci_host *ihost, |
2477 | struct isci_remote_device *idev) | |
cc9203bf | 2478 | { |
d9dcb4ba DW |
2479 | if (ihost->sm.current_state_id != SCIC_STOPPING) { |
2480 | dev_dbg(&ihost->pdev->dev, | |
cc9203bf DW |
2481 | "SCIC Controller 0x%p remote device stopped event " |
2482 | "from device 0x%p in unexpected state %d\n", | |
d9dcb4ba DW |
2483 | ihost, idev, |
2484 | ihost->sm.current_state_id); | |
cc9203bf DW |
2485 | return; |
2486 | } | |
2487 | ||
89a7301f | 2488 | if (!sci_controller_has_remote_devices_stopping(ihost)) |
d9dcb4ba | 2489 | sci_change_state(&ihost->sm, SCIC_STOPPED); |
cc9203bf DW |
2490 | } |
2491 | ||
89a7301f | 2492 | void sci_controller_post_request(struct isci_host *ihost, u32 request) |
cc9203bf | 2493 | { |
89a7301f DW |
2494 | dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n", |
2495 | __func__, ihost->id, request); | |
cc9203bf | 2496 | |
d9dcb4ba | 2497 | writel(request, &ihost->smu_registers->post_context_port); |
cc9203bf DW |
2498 | } |
2499 | ||
89a7301f | 2500 | struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag) |
cc9203bf DW |
2501 | { |
2502 | u16 task_index; | |
2503 | u16 task_sequence; | |
2504 | ||
dd047c8e | 2505 | task_index = ISCI_TAG_TCI(io_tag); |
cc9203bf | 2506 | |
d9dcb4ba DW |
2507 | if (task_index < ihost->task_context_entries) { |
2508 | struct isci_request *ireq = ihost->reqs[task_index]; | |
db056250 DW |
2509 | |
2510 | if (test_bit(IREQ_ACTIVE, &ireq->flags)) { | |
dd047c8e | 2511 | task_sequence = ISCI_TAG_SEQ(io_tag); |
cc9203bf | 2512 | |
d9dcb4ba | 2513 | if (task_sequence == ihost->io_request_sequence[task_index]) |
5076a1a9 | 2514 | return ireq; |
cc9203bf DW |
2515 | } |
2516 | } | |
2517 | ||
2518 | return NULL; | |
2519 | } | |
2520 | ||
2521 | /** | |
2522 | * This method allocates remote node index and the reserves the remote node | |
2523 | * context space for use. This method can fail if there are no more remote | |
2524 | * node index available. | |
2525 | * @scic: This is the controller object which contains the set of | |
2526 | * free remote node ids | |
2527 | * @sci_dev: This is the device object which is requesting the a remote node | |
2528 | * id | |
2529 | * @node_id: This is the remote node id that is assinged to the device if one | |
2530 | * is available | |
2531 | * | |
2532 | * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote | |
2533 | * node index available. | |
2534 | */ | |
89a7301f DW |
2535 | enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost, |
2536 | struct isci_remote_device *idev, | |
2537 | u16 *node_id) | |
cc9203bf DW |
2538 | { |
2539 | u16 node_index; | |
89a7301f | 2540 | u32 remote_node_count = sci_remote_device_node_count(idev); |
cc9203bf | 2541 | |
89a7301f | 2542 | node_index = sci_remote_node_table_allocate_remote_node( |
d9dcb4ba | 2543 | &ihost->available_remote_nodes, remote_node_count |
cc9203bf DW |
2544 | ); |
2545 | ||
2546 | if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) { | |
d9dcb4ba | 2547 | ihost->device_table[node_index] = idev; |
cc9203bf DW |
2548 | |
2549 | *node_id = node_index; | |
2550 | ||
2551 | return SCI_SUCCESS; | |
2552 | } | |
2553 | ||
2554 | return SCI_FAILURE_INSUFFICIENT_RESOURCES; | |
2555 | } | |
2556 | ||
89a7301f DW |
2557 | void sci_controller_free_remote_node_context(struct isci_host *ihost, |
2558 | struct isci_remote_device *idev, | |
2559 | u16 node_id) | |
cc9203bf | 2560 | { |
89a7301f | 2561 | u32 remote_node_count = sci_remote_device_node_count(idev); |
cc9203bf | 2562 | |
d9dcb4ba DW |
2563 | if (ihost->device_table[node_id] == idev) { |
2564 | ihost->device_table[node_id] = NULL; | |
cc9203bf | 2565 | |
89a7301f | 2566 | sci_remote_node_table_release_remote_node_index( |
d9dcb4ba | 2567 | &ihost->available_remote_nodes, remote_node_count, node_id |
cc9203bf DW |
2568 | ); |
2569 | } | |
2570 | } | |
2571 | ||
89a7301f DW |
2572 | void sci_controller_copy_sata_response(void *response_buffer, |
2573 | void *frame_header, | |
2574 | void *frame_buffer) | |
cc9203bf | 2575 | { |
89a7301f | 2576 | /* XXX type safety? */ |
cc9203bf DW |
2577 | memcpy(response_buffer, frame_header, sizeof(u32)); |
2578 | ||
2579 | memcpy(response_buffer + sizeof(u32), | |
2580 | frame_buffer, | |
2581 | sizeof(struct dev_to_host_fis) - sizeof(u32)); | |
2582 | } | |
2583 | ||
89a7301f | 2584 | void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index) |
cc9203bf | 2585 | { |
89a7301f | 2586 | if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index)) |
d9dcb4ba DW |
2587 | writel(ihost->uf_control.get, |
2588 | &ihost->scu_registers->sdma.unsolicited_frame_get_pointer); | |
cc9203bf DW |
2589 | } |
2590 | ||
312e0c24 DW |
2591 | void isci_tci_free(struct isci_host *ihost, u16 tci) |
2592 | { | |
2593 | u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1); | |
2594 | ||
2595 | ihost->tci_pool[tail] = tci; | |
2596 | ihost->tci_tail = tail + 1; | |
2597 | } | |
2598 | ||
2599 | static u16 isci_tci_alloc(struct isci_host *ihost) | |
2600 | { | |
2601 | u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1); | |
2602 | u16 tci = ihost->tci_pool[head]; | |
2603 | ||
2604 | ihost->tci_head = head + 1; | |
2605 | return tci; | |
2606 | } | |
2607 | ||
2608 | static u16 isci_tci_space(struct isci_host *ihost) | |
2609 | { | |
2610 | return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS); | |
2611 | } | |
2612 | ||
2613 | u16 isci_alloc_tag(struct isci_host *ihost) | |
2614 | { | |
2615 | if (isci_tci_space(ihost)) { | |
2616 | u16 tci = isci_tci_alloc(ihost); | |
d9dcb4ba | 2617 | u8 seq = ihost->io_request_sequence[tci]; |
312e0c24 DW |
2618 | |
2619 | return ISCI_TAG(seq, tci); | |
2620 | } | |
2621 | ||
2622 | return SCI_CONTROLLER_INVALID_IO_TAG; | |
2623 | } | |
2624 | ||
2625 | enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag) | |
2626 | { | |
312e0c24 DW |
2627 | u16 tci = ISCI_TAG_TCI(io_tag); |
2628 | u16 seq = ISCI_TAG_SEQ(io_tag); | |
2629 | ||
2630 | /* prevent tail from passing head */ | |
2631 | if (isci_tci_active(ihost) == 0) | |
2632 | return SCI_FAILURE_INVALID_IO_TAG; | |
2633 | ||
d9dcb4ba DW |
2634 | if (seq == ihost->io_request_sequence[tci]) { |
2635 | ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1); | |
312e0c24 DW |
2636 | |
2637 | isci_tci_free(ihost, tci); | |
2638 | ||
2639 | return SCI_SUCCESS; | |
2640 | } | |
2641 | return SCI_FAILURE_INVALID_IO_TAG; | |
2642 | } | |
2643 | ||
89a7301f DW |
2644 | enum sci_status sci_controller_start_io(struct isci_host *ihost, |
2645 | struct isci_remote_device *idev, | |
2646 | struct isci_request *ireq) | |
cc9203bf DW |
2647 | { |
2648 | enum sci_status status; | |
2649 | ||
d9dcb4ba DW |
2650 | if (ihost->sm.current_state_id != SCIC_READY) { |
2651 | dev_warn(&ihost->pdev->dev, "invalid state to start I/O"); | |
cc9203bf DW |
2652 | return SCI_FAILURE_INVALID_STATE; |
2653 | } | |
2654 | ||
89a7301f | 2655 | status = sci_remote_device_start_io(ihost, idev, ireq); |
cc9203bf DW |
2656 | if (status != SCI_SUCCESS) |
2657 | return status; | |
2658 | ||
5076a1a9 | 2659 | set_bit(IREQ_ACTIVE, &ireq->flags); |
34a99158 | 2660 | sci_controller_post_request(ihost, ireq->post_context); |
cc9203bf DW |
2661 | return SCI_SUCCESS; |
2662 | } | |
2663 | ||
89a7301f DW |
2664 | enum sci_status sci_controller_terminate_request(struct isci_host *ihost, |
2665 | struct isci_remote_device *idev, | |
2666 | struct isci_request *ireq) | |
cc9203bf | 2667 | { |
89a7301f DW |
2668 | /* terminate an ongoing (i.e. started) core IO request. This does not |
2669 | * abort the IO request at the target, but rather removes the IO | |
2670 | * request from the host controller. | |
2671 | */ | |
cc9203bf DW |
2672 | enum sci_status status; |
2673 | ||
d9dcb4ba DW |
2674 | if (ihost->sm.current_state_id != SCIC_READY) { |
2675 | dev_warn(&ihost->pdev->dev, | |
cc9203bf DW |
2676 | "invalid state to terminate request\n"); |
2677 | return SCI_FAILURE_INVALID_STATE; | |
2678 | } | |
2679 | ||
89a7301f | 2680 | status = sci_io_request_terminate(ireq); |
cc9203bf DW |
2681 | if (status != SCI_SUCCESS) |
2682 | return status; | |
2683 | ||
2684 | /* | |
2685 | * Utilize the original post context command and or in the POST_TC_ABORT | |
2686 | * request sub-type. | |
2687 | */ | |
89a7301f DW |
2688 | sci_controller_post_request(ihost, |
2689 | ireq->post_context | SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT); | |
cc9203bf DW |
2690 | return SCI_SUCCESS; |
2691 | } | |
2692 | ||
2693 | /** | |
89a7301f | 2694 | * sci_controller_complete_io() - This method will perform core specific |
cc9203bf DW |
2695 | * completion operations for an IO request. After this method is invoked, |
2696 | * the user should consider the IO request as invalid until it is properly | |
2697 | * reused (i.e. re-constructed). | |
89a7301f | 2698 | * @ihost: The handle to the controller object for which to complete the |
cc9203bf | 2699 | * IO request. |
89a7301f | 2700 | * @idev: The handle to the remote device object for which to complete |
cc9203bf | 2701 | * the IO request. |
89a7301f | 2702 | * @ireq: the handle to the io request object to complete. |
cc9203bf | 2703 | */ |
89a7301f DW |
2704 | enum sci_status sci_controller_complete_io(struct isci_host *ihost, |
2705 | struct isci_remote_device *idev, | |
2706 | struct isci_request *ireq) | |
cc9203bf DW |
2707 | { |
2708 | enum sci_status status; | |
2709 | u16 index; | |
2710 | ||
d9dcb4ba | 2711 | switch (ihost->sm.current_state_id) { |
e301370a | 2712 | case SCIC_STOPPING: |
cc9203bf DW |
2713 | /* XXX: Implement this function */ |
2714 | return SCI_FAILURE; | |
e301370a | 2715 | case SCIC_READY: |
89a7301f | 2716 | status = sci_remote_device_complete_io(ihost, idev, ireq); |
cc9203bf DW |
2717 | if (status != SCI_SUCCESS) |
2718 | return status; | |
2719 | ||
5076a1a9 DW |
2720 | index = ISCI_TAG_TCI(ireq->io_tag); |
2721 | clear_bit(IREQ_ACTIVE, &ireq->flags); | |
cc9203bf DW |
2722 | return SCI_SUCCESS; |
2723 | default: | |
d9dcb4ba | 2724 | dev_warn(&ihost->pdev->dev, "invalid state to complete I/O"); |
cc9203bf DW |
2725 | return SCI_FAILURE_INVALID_STATE; |
2726 | } | |
2727 | ||
2728 | } | |
2729 | ||
89a7301f | 2730 | enum sci_status sci_controller_continue_io(struct isci_request *ireq) |
cc9203bf | 2731 | { |
d9dcb4ba | 2732 | struct isci_host *ihost = ireq->owning_controller; |
cc9203bf | 2733 | |
d9dcb4ba DW |
2734 | if (ihost->sm.current_state_id != SCIC_READY) { |
2735 | dev_warn(&ihost->pdev->dev, "invalid state to continue I/O"); | |
cc9203bf DW |
2736 | return SCI_FAILURE_INVALID_STATE; |
2737 | } | |
2738 | ||
5076a1a9 | 2739 | set_bit(IREQ_ACTIVE, &ireq->flags); |
34a99158 | 2740 | sci_controller_post_request(ihost, ireq->post_context); |
cc9203bf DW |
2741 | return SCI_SUCCESS; |
2742 | } | |
2743 | ||
2744 | /** | |
89a7301f | 2745 | * sci_controller_start_task() - This method is called by the SCIC user to |
cc9203bf DW |
2746 | * send/start a framework task management request. |
2747 | * @controller: the handle to the controller object for which to start the task | |
2748 | * management request. | |
2749 | * @remote_device: the handle to the remote device object for which to start | |
2750 | * the task management request. | |
2751 | * @task_request: the handle to the task request object to start. | |
cc9203bf | 2752 | */ |
89a7301f DW |
2753 | enum sci_task_status sci_controller_start_task(struct isci_host *ihost, |
2754 | struct isci_remote_device *idev, | |
2755 | struct isci_request *ireq) | |
cc9203bf DW |
2756 | { |
2757 | enum sci_status status; | |
2758 | ||
d9dcb4ba DW |
2759 | if (ihost->sm.current_state_id != SCIC_READY) { |
2760 | dev_warn(&ihost->pdev->dev, | |
cc9203bf DW |
2761 | "%s: SCIC Controller starting task from invalid " |
2762 | "state\n", | |
2763 | __func__); | |
2764 | return SCI_TASK_FAILURE_INVALID_STATE; | |
2765 | } | |
2766 | ||
89a7301f | 2767 | status = sci_remote_device_start_task(ihost, idev, ireq); |
cc9203bf DW |
2768 | switch (status) { |
2769 | case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS: | |
db056250 | 2770 | set_bit(IREQ_ACTIVE, &ireq->flags); |
cc9203bf DW |
2771 | |
2772 | /* | |
2773 | * We will let framework know this task request started successfully, | |
2774 | * although core is still woring on starting the request (to post tc when | |
2775 | * RNC is resumed.) | |
2776 | */ | |
2777 | return SCI_SUCCESS; | |
2778 | case SCI_SUCCESS: | |
db056250 | 2779 | set_bit(IREQ_ACTIVE, &ireq->flags); |
34a99158 | 2780 | sci_controller_post_request(ihost, ireq->post_context); |
cc9203bf DW |
2781 | break; |
2782 | default: | |
2783 | break; | |
2784 | } | |
2785 | ||
2786 | return status; | |
2787 | } | |
ad4f4c1d DW |
2788 | |
2789 | static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data) | |
2790 | { | |
2791 | int d; | |
2792 | ||
2793 | /* no support for TX_GP_CFG */ | |
2794 | if (reg_index == 0) | |
2795 | return -EINVAL; | |
2796 | ||
2797 | for (d = 0; d < isci_gpio_count(ihost); d++) { | |
2798 | u32 val = 0x444; /* all ODx.n clear */ | |
2799 | int i; | |
2800 | ||
2801 | for (i = 0; i < 3; i++) { | |
2802 | int bit = (i << 2) + 2; | |
2803 | ||
2804 | bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i), | |
2805 | write_data, reg_index, | |
2806 | reg_count); | |
2807 | if (bit < 0) | |
2808 | break; | |
2809 | ||
2810 | /* if od is set, clear the 'invert' bit */ | |
2811 | val &= ~(bit << ((i << 2) + 2)); | |
2812 | } | |
2813 | ||
2814 | if (i < 3) | |
2815 | break; | |
2816 | writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]); | |
2817 | } | |
2818 | ||
2819 | /* unless reg_index is > 1, we should always be able to write at | |
2820 | * least one register | |
2821 | */ | |
2822 | return d > 0; | |
2823 | } | |
2824 | ||
2825 | int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index, | |
2826 | u8 reg_count, u8 *write_data) | |
2827 | { | |
2828 | struct isci_host *ihost = sas_ha->lldd_ha; | |
2829 | int written; | |
2830 | ||
2831 | switch (reg_type) { | |
2832 | case SAS_GPIO_REG_TX_GP: | |
2833 | written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data); | |
2834 | break; | |
2835 | default: | |
2836 | written = -EINVAL; | |
2837 | } | |
2838 | ||
2839 | return written; | |
2840 | } |