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1da177e4 1/*
af36d7f0
JG		 2 * libata-core.c - helper library for ATA
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2003-2004 Red Hat, Inc. All rights reserved.
9 * Copyright 2003-2004 Jeff Garzik
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; see the file COPYING. If not, write to
24 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *
27 * libata documentation is available via 'make {ps|pdf}docs',
28 * as Documentation/DocBook/libata.*
29 *
30 * Hardware documentation available from http://www.t13.org/ and
31 * http://www.sata-io.org/
32 *
1da177e4
LT		 33 */
34
35#include <linux/config.h>
36#include <linux/kernel.h>
37#include <linux/module.h>
38#include <linux/pci.h>
39#include <linux/init.h>
40#include <linux/list.h>
41#include <linux/mm.h>
42#include <linux/highmem.h>
43#include <linux/spinlock.h>
44#include <linux/blkdev.h>
45#include <linux/delay.h>
46#include <linux/timer.h>
47#include <linux/interrupt.h>
48#include <linux/completion.h>
49#include <linux/suspend.h>
50#include <linux/workqueue.h>
67846b30 51#include <linux/jiffies.h>
378f058c 52#include <linux/scatterlist.h>
1da177e4 53#include <scsi/scsi.h>
1da177e4 54#include "scsi_priv.h"
193515d5 55#include <scsi/scsi_cmnd.h>
1da177e4
LT		 56#include <scsi/scsi_host.h>
57#include <linux/libata.h>
58#include <asm/io.h>
59#include <asm/semaphore.h>
60#include <asm/byteorder.h>
61
62#include "libata.h"
63
6aff8f1f
TH		 64static unsigned int ata_dev_init_params(struct ata_port *ap,
65 struct ata_device *dev);
1da177e4
LT		 66static void ata_set_mode(struct ata_port *ap);
67static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev);
a6d5a51c
TH		 68static unsigned int ata_dev_xfermask(struct ata_port *ap,
69 struct ata_device *dev);
1da177e4
LT		 70
71static unsigned int ata_unique_id = 1;
72static struct workqueue_struct *ata_wq;
73
418dc1f5 74int atapi_enabled = 1;
1623c81e
JG		 75module_param(atapi_enabled, int, 0444);
76MODULE_PARM_DESC(atapi_enabled, "Enable discovery of ATAPI devices (0=off, 1=on)");
77
c3c013a2
JG		 78int libata_fua = 0;
79module_param_named(fua, libata_fua, int, 0444);
80MODULE_PARM_DESC(fua, "FUA support (0=off, 1=on)");
81
1da177e4
LT		 82MODULE_AUTHOR("Jeff Garzik");
83MODULE_DESCRIPTION("Library module for ATA devices");
84MODULE_LICENSE("GPL");
85MODULE_VERSION(DRV_VERSION);
86
0baab86b 87
1da177e4
LT		 88/**
89 * ata_tf_to_fis - Convert ATA taskfile to SATA FIS structure
90 * @tf: Taskfile to convert
91 * @fis: Buffer into which data will output
92 * @pmp: Port multiplier port
93 *
94 * Converts a standard ATA taskfile to a Serial ATA
95 * FIS structure (Register - Host to Device).
96 *
97 * LOCKING:
98 * Inherited from caller.
99 */
100
057ace5e 101void ata_tf_to_fis(const struct ata_taskfile *tf, u8 *fis, u8 pmp)
1da177e4
LT		 102{
103 fis[0] = 0x27; /* Register - Host to Device FIS */
104 fis[1] = (pmp & 0xf) | (1 << 7); /* Port multiplier number,
105 bit 7 indicates Command FIS */
106 fis[2] = tf->command;
107 fis[3] = tf->feature;
108
109 fis[4] = tf->lbal;
110 fis[5] = tf->lbam;
111 fis[6] = tf->lbah;
112 fis[7] = tf->device;
113
114 fis[8] = tf->hob_lbal;
115 fis[9] = tf->hob_lbam;
116 fis[10] = tf->hob_lbah;
117 fis[11] = tf->hob_feature;
118
119 fis[12] = tf->nsect;
120 fis[13] = tf->hob_nsect;
121 fis[14] = 0;
122 fis[15] = tf->ctl;
123
124 fis[16] = 0;
125 fis[17] = 0;
126 fis[18] = 0;
127 fis[19] = 0;
128}
129
130/**
131 * ata_tf_from_fis - Convert SATA FIS to ATA taskfile
132 * @fis: Buffer from which data will be input
133 * @tf: Taskfile to output
134 *
e12a1be6 135 * Converts a serial ATA FIS structure to a standard ATA taskfile.
1da177e4
LT		 136 *
137 * LOCKING:
138 * Inherited from caller.
139 */
140
057ace5e 141void ata_tf_from_fis(const u8 *fis, struct ata_taskfile *tf)
1da177e4
LT		 142{
143 tf->command = fis[2]; /* status */
144 tf->feature = fis[3]; /* error */
145
146 tf->lbal = fis[4];
147 tf->lbam = fis[5];
148 tf->lbah = fis[6];
149 tf->device = fis[7];
150
151 tf->hob_lbal = fis[8];
152 tf->hob_lbam = fis[9];
153 tf->hob_lbah = fis[10];
154
155 tf->nsect = fis[12];
156 tf->hob_nsect = fis[13];
157}
158
8cbd6df1
AL		 159static const u8 ata_rw_cmds[] = {
160 /* pio multi */
161 ATA_CMD_READ_MULTI,
162 ATA_CMD_WRITE_MULTI,
163 ATA_CMD_READ_MULTI_EXT,
164 ATA_CMD_WRITE_MULTI_EXT,
9a3dccc4
TH		 165 0,
166 0,
167 0,
168 ATA_CMD_WRITE_MULTI_FUA_EXT,
8cbd6df1
AL		 169 /* pio */
170 ATA_CMD_PIO_READ,
171 ATA_CMD_PIO_WRITE,
172 ATA_CMD_PIO_READ_EXT,
173 ATA_CMD_PIO_WRITE_EXT,
9a3dccc4
TH		 174 0,
175 0,
176 0,
177 0,
8cbd6df1
AL		 178 /* dma */
179 ATA_CMD_READ,
180 ATA_CMD_WRITE,
181 ATA_CMD_READ_EXT,
9a3dccc4
TH		 182 ATA_CMD_WRITE_EXT,
183 0,
184 0,
185 0,
186 ATA_CMD_WRITE_FUA_EXT
8cbd6df1 187};
1da177e4
LT		 188
189/**
8cbd6df1
AL		 190 * ata_rwcmd_protocol - set taskfile r/w commands and protocol
191 * @qc: command to examine and configure
1da177e4 192 *
8cbd6df1
AL		 193 * Examine the device configuration and tf->flags to calculate
194 * the proper read/write commands and protocol to use.
1da177e4
LT		 195 *
196 * LOCKING:
197 * caller.
198 */
9a3dccc4 199int ata_rwcmd_protocol(struct ata_queued_cmd *qc)
1da177e4 200{
8cbd6df1
AL		 201 struct ata_taskfile *tf = &qc->tf;
202 struct ata_device *dev = qc->dev;
9a3dccc4 203 u8 cmd;
1da177e4 204
9a3dccc4 205 int index, fua, lba48, write;
8cbd6df1 206
9a3dccc4 207 fua = (tf->flags & ATA_TFLAG_FUA) ? 4 : 0;
8cbd6df1
AL		 208 lba48 = (tf->flags & ATA_TFLAG_LBA48) ? 2 : 0;
209 write = (tf->flags & ATA_TFLAG_WRITE) ? 1 : 0;
1da177e4 210
8cbd6df1
AL		 211 if (dev->flags & ATA_DFLAG_PIO) {
212 tf->protocol = ATA_PROT_PIO;
9a3dccc4 213 index = dev->multi_count ? 0 : 8;
8d238e01
AC		 214 } else if (lba48 && (qc->ap->flags & ATA_FLAG_PIO_LBA48)) {
215 /* Unable to use DMA due to host limitation */
216 tf->protocol = ATA_PROT_PIO;
0565c26d 217 index = dev->multi_count ? 0 : 8;
8cbd6df1
AL		 218 } else {
219 tf->protocol = ATA_PROT_DMA;
9a3dccc4 220 index = 16;
8cbd6df1 221 }
1da177e4 222
9a3dccc4
TH		 223 cmd = ata_rw_cmds[index + fua + lba48 + write];
224 if (cmd) {
225 tf->command = cmd;
226 return 0;
227 }
228 return -1;
1da177e4
LT		 229}
230
cb95d562
TH		 231/**
232 * ata_pack_xfermask - Pack pio, mwdma and udma masks into xfer_mask
233 * @pio_mask: pio_mask
234 * @mwdma_mask: mwdma_mask
235 * @udma_mask: udma_mask
236 *
237 * Pack @pio_mask, @mwdma_mask and @udma_mask into a single
238 * unsigned int xfer_mask.
239 *
240 * LOCKING:
241 * None.
242 *
243 * RETURNS:
244 * Packed xfer_mask.
245 */
246static unsigned int ata_pack_xfermask(unsigned int pio_mask,
247 unsigned int mwdma_mask,
248 unsigned int udma_mask)
249{
250 return ((pio_mask << ATA_SHIFT_PIO) & ATA_MASK_PIO) |
251 ((mwdma_mask << ATA_SHIFT_MWDMA) & ATA_MASK_MWDMA) |
252 ((udma_mask << ATA_SHIFT_UDMA) & ATA_MASK_UDMA);
253}
254
255static const struct ata_xfer_ent {
256 unsigned int shift, bits;
257 u8 base;
258} ata_xfer_tbl[] = {
259 { ATA_SHIFT_PIO, ATA_BITS_PIO, XFER_PIO_0 },
260 { ATA_SHIFT_MWDMA, ATA_BITS_MWDMA, XFER_MW_DMA_0 },
261 { ATA_SHIFT_UDMA, ATA_BITS_UDMA, XFER_UDMA_0 },
262 { -1, },
263};
264
265/**
266 * ata_xfer_mask2mode - Find matching XFER_* for the given xfer_mask
267 * @xfer_mask: xfer_mask of interest
268 *
269 * Return matching XFER_* value for @xfer_mask. Only the highest
270 * bit of @xfer_mask is considered.
271 *
272 * LOCKING:
273 * None.
274 *
275 * RETURNS:
276 * Matching XFER_* value, 0 if no match found.
277 */
278static u8 ata_xfer_mask2mode(unsigned int xfer_mask)
279{
280 int highbit = fls(xfer_mask) - 1;
281 const struct ata_xfer_ent *ent;
282
283 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
284 if (highbit >= ent->shift && highbit < ent->shift + ent->bits)
285 return ent->base + highbit - ent->shift;
286 return 0;
287}
288
289/**
290 * ata_xfer_mode2mask - Find matching xfer_mask for XFER_*
291 * @xfer_mode: XFER_* of interest
292 *
293 * Return matching xfer_mask for @xfer_mode.
294 *
295 * LOCKING:
296 * None.
297 *
298 * RETURNS:
299 * Matching xfer_mask, 0 if no match found.
300 */
301static unsigned int ata_xfer_mode2mask(u8 xfer_mode)
302{
303 const struct ata_xfer_ent *ent;
304
305 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
306 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
307 return 1 << (ent->shift + xfer_mode - ent->base);
308 return 0;
309}
310
311/**
312 * ata_xfer_mode2shift - Find matching xfer_shift for XFER_*
313 * @xfer_mode: XFER_* of interest
314 *
315 * Return matching xfer_shift for @xfer_mode.
316 *
317 * LOCKING:
318 * None.
319 *
320 * RETURNS:
321 * Matching xfer_shift, -1 if no match found.
322 */
323static int ata_xfer_mode2shift(unsigned int xfer_mode)
324{
325 const struct ata_xfer_ent *ent;
326
327 for (ent = ata_xfer_tbl; ent->shift >= 0; ent++)
328 if (xfer_mode >= ent->base && xfer_mode < ent->base + ent->bits)
329 return ent->shift;
330 return -1;
331}
332
1da177e4 333/**
1da7b0d0
TH		 334 * ata_mode_string - convert xfer_mask to string
335 * @xfer_mask: mask of bits supported; only highest bit counts.
1da177e4
LT		 336 *
337 * Determine string which represents the highest speed
1da7b0d0 338 * (highest bit in @modemask).
1da177e4
LT		 339 *
340 * LOCKING:
341 * None.
342 *
343 * RETURNS:
344 * Constant C string representing highest speed listed in
1da7b0d0 345 * @mode_mask, or the constant C string "<n/a>".
1da177e4 346 */
1da7b0d0 347static const char *ata_mode_string(unsigned int xfer_mask)
1da177e4 348{
75f554bc
TH		 349 static const char * const xfer_mode_str[] = {
350 "PIO0",
351 "PIO1",
352 "PIO2",
353 "PIO3",
354 "PIO4",
355 "MWDMA0",
356 "MWDMA1",
357 "MWDMA2",
358 "UDMA/16",
359 "UDMA/25",
360 "UDMA/33",
361 "UDMA/44",
362 "UDMA/66",
363 "UDMA/100",
364 "UDMA/133",
365 "UDMA7",
366 };
1da7b0d0 367 int highbit;
1da177e4 368
1da7b0d0
TH		 369 highbit = fls(xfer_mask) - 1;
370 if (highbit >= 0 && highbit < ARRAY_SIZE(xfer_mode_str))
371 return xfer_mode_str[highbit];
1da177e4 372 return "<n/a>";
1da177e4
LT		 373}
374
375/**
376 * ata_pio_devchk - PATA device presence detection
377 * @ap: ATA channel to examine
378 * @device: Device to examine (starting at zero)
379 *
380 * This technique was originally described in
381 * Hale Landis's ATADRVR (www.ata-atapi.com), and
382 * later found its way into the ATA/ATAPI spec.
383 *
384 * Write a pattern to the ATA shadow registers,
385 * and if a device is present, it will respond by
386 * correctly storing and echoing back the
387 * ATA shadow register contents.
388 *
389 * LOCKING:
390 * caller.
391 */
392
393static unsigned int ata_pio_devchk(struct ata_port *ap,
394 unsigned int device)
395{
396 struct ata_ioports *ioaddr = &ap->ioaddr;
397 u8 nsect, lbal;
398
399 ap->ops->dev_select(ap, device);
400
401 outb(0x55, ioaddr->nsect_addr);
402 outb(0xaa, ioaddr->lbal_addr);
403
404 outb(0xaa, ioaddr->nsect_addr);
405 outb(0x55, ioaddr->lbal_addr);
406
407 outb(0x55, ioaddr->nsect_addr);
408 outb(0xaa, ioaddr->lbal_addr);
409
410 nsect = inb(ioaddr->nsect_addr);
411 lbal = inb(ioaddr->lbal_addr);
412
413 if ((nsect == 0x55) && (lbal == 0xaa))
414 return 1; /* we found a device */
415
416 return 0; /* nothing found */
417}
418
419/**
420 * ata_mmio_devchk - PATA device presence detection
421 * @ap: ATA channel to examine
422 * @device: Device to examine (starting at zero)
423 *
424 * This technique was originally described in
425 * Hale Landis's ATADRVR (www.ata-atapi.com), and
426 * later found its way into the ATA/ATAPI spec.
427 *
428 * Write a pattern to the ATA shadow registers,
429 * and if a device is present, it will respond by
430 * correctly storing and echoing back the
431 * ATA shadow register contents.
432 *
433 * LOCKING:
434 * caller.
435 */
436
437static unsigned int ata_mmio_devchk(struct ata_port *ap,
438 unsigned int device)
439{
440 struct ata_ioports *ioaddr = &ap->ioaddr;
441 u8 nsect, lbal;
442
443 ap->ops->dev_select(ap, device);
444
445 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
446 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
447
448 writeb(0xaa, (void __iomem *) ioaddr->nsect_addr);
449 writeb(0x55, (void __iomem *) ioaddr->lbal_addr);
450
451 writeb(0x55, (void __iomem *) ioaddr->nsect_addr);
452 writeb(0xaa, (void __iomem *) ioaddr->lbal_addr);
453
454 nsect = readb((void __iomem *) ioaddr->nsect_addr);
455 lbal = readb((void __iomem *) ioaddr->lbal_addr);
456
457 if ((nsect == 0x55) && (lbal == 0xaa))
458 return 1; /* we found a device */
459
460 return 0; /* nothing found */
461}
462
463/**
464 * ata_devchk - PATA device presence detection
465 * @ap: ATA channel to examine
466 * @device: Device to examine (starting at zero)
467 *
468 * Dispatch ATA device presence detection, depending
469 * on whether we are using PIO or MMIO to talk to the
470 * ATA shadow registers.
471 *
472 * LOCKING:
473 * caller.
474 */
475
476static unsigned int ata_devchk(struct ata_port *ap,
477 unsigned int device)
478{
479 if (ap->flags & ATA_FLAG_MMIO)
480 return ata_mmio_devchk(ap, device);
481 return ata_pio_devchk(ap, device);
482}
483
484/**
485 * ata_dev_classify - determine device type based on ATA-spec signature
486 * @tf: ATA taskfile register set for device to be identified
487 *
488 * Determine from taskfile register contents whether a device is
489 * ATA or ATAPI, as per "Signature and persistence" section
490 * of ATA/PI spec (volume 1, sect 5.14).
491 *
492 * LOCKING:
493 * None.
494 *
495 * RETURNS:
496 * Device type, %ATA_DEV_ATA, %ATA_DEV_ATAPI, or %ATA_DEV_UNKNOWN
497 * the event of failure.
498 */
499
057ace5e 500unsigned int ata_dev_classify(const struct ata_taskfile *tf)
1da177e4
LT		 501{
502 /* Apple's open source Darwin code hints that some devices only
503 * put a proper signature into the LBA mid/high registers,
504 * So, we only check those. It's sufficient for uniqueness.
505 */
506
507 if (((tf->lbam == 0) && (tf->lbah == 0)) ||
508 ((tf->lbam == 0x3c) && (tf->lbah == 0xc3))) {
509 DPRINTK("found ATA device by sig\n");
510 return ATA_DEV_ATA;
511 }
512
513 if (((tf->lbam == 0x14) && (tf->lbah == 0xeb)) ||
514 ((tf->lbam == 0x69) && (tf->lbah == 0x96))) {
515 DPRINTK("found ATAPI device by sig\n");
516 return ATA_DEV_ATAPI;
517 }
518
519 DPRINTK("unknown device\n");
520 return ATA_DEV_UNKNOWN;
521}
522
523/**
524 * ata_dev_try_classify - Parse returned ATA device signature
525 * @ap: ATA channel to examine
526 * @device: Device to examine (starting at zero)
b4dc7623 527 * @r_err: Value of error register on completion
1da177e4
LT		 528 *
529 * After an event -- SRST, E.D.D., or SATA COMRESET -- occurs,
530 * an ATA/ATAPI-defined set of values is placed in the ATA
531 * shadow registers, indicating the results of device detection
532 * and diagnostics.
533 *
534 * Select the ATA device, and read the values from the ATA shadow
535 * registers. Then parse according to the Error register value,
536 * and the spec-defined values examined by ata_dev_classify().
537 *
538 * LOCKING:
539 * caller.
b4dc7623
TH		 540 *
541 * RETURNS:
542 * Device type - %ATA_DEV_ATA, %ATA_DEV_ATAPI or %ATA_DEV_NONE.
1da177e4
LT		 543 */
544
b4dc7623
TH		 545static unsigned int
546ata_dev_try_classify(struct ata_port *ap, unsigned int device, u8 *r_err)
1da177e4 547{
1da177e4
LT		 548 struct ata_taskfile tf;
549 unsigned int class;
550 u8 err;
551
552 ap->ops->dev_select(ap, device);
553
554 memset(&tf, 0, sizeof(tf));
555
1da177e4 556 ap->ops->tf_read(ap, &tf);
0169e284 557 err = tf.feature;
b4dc7623
TH		 558 if (r_err)
559 *r_err = err;
1da177e4
LT		 560
561 /* see if device passed diags */
562 if (err == 1)
563 /* do nothing */ ;
564 else if ((device == 0) && (err == 0x81))
565 /* do nothing */ ;
566 else
b4dc7623 567 return ATA_DEV_NONE;
1da177e4 568
b4dc7623 569 /* determine if device is ATA or ATAPI */
1da177e4 570 class = ata_dev_classify(&tf);
b4dc7623 571
1da177e4 572 if (class == ATA_DEV_UNKNOWN)
b4dc7623 573 return ATA_DEV_NONE;
1da177e4 574 if ((class == ATA_DEV_ATA) && (ata_chk_status(ap) == 0))
b4dc7623
TH		 575 return ATA_DEV_NONE;
576 return class;
1da177e4
LT		 577}
578
579/**
6a62a04d 580 * ata_id_string - Convert IDENTIFY DEVICE page into string
1da177e4
LT		 581 * @id: IDENTIFY DEVICE results we will examine
582 * @s: string into which data is output
583 * @ofs: offset into identify device page
584 * @len: length of string to return. must be an even number.
585 *
586 * The strings in the IDENTIFY DEVICE page are broken up into
587 * 16-bit chunks. Run through the string, and output each
588 * 8-bit chunk linearly, regardless of platform.
589 *
590 * LOCKING:
591 * caller.
592 */
593
6a62a04d
TH		 594void ata_id_string(const u16 *id, unsigned char *s,
595 unsigned int ofs, unsigned int len)
1da177e4
LT		 596{
597 unsigned int c;
598
599 while (len > 0) {
600 c = id[ofs] >> 8;
601 *s = c;
602 s++;
603
604 c = id[ofs] & 0xff;
605 *s = c;
606 s++;
607
608 ofs++;
609 len -= 2;
610 }
611}
612
0e949ff3 613/**
6a62a04d 614 * ata_id_c_string - Convert IDENTIFY DEVICE page into C string
0e949ff3
TH		 615 * @id: IDENTIFY DEVICE results we will examine
616 * @s: string into which data is output
617 * @ofs: offset into identify device page
618 * @len: length of string to return. must be an odd number.
619 *
6a62a04d 620 * This function is identical to ata_id_string except that it
0e949ff3
TH		 621 * trims trailing spaces and terminates the resulting string with
622 * null. @len must be actual maximum length (even number) + 1.
623 *
624 * LOCKING:
625 * caller.
626 */
6a62a04d
TH		 627void ata_id_c_string(const u16 *id, unsigned char *s,
628 unsigned int ofs, unsigned int len)
0e949ff3
TH		 629{
630 unsigned char *p;
631
632 WARN_ON(!(len & 1));
633
6a62a04d 634 ata_id_string(id, s, ofs, len - 1);
0e949ff3
TH		 635
636 p = s + strnlen(s, len - 1);
637 while (p > s && p[-1] == ' ')
638 p--;
639 *p = '\0';
640}
0baab86b 641
2940740b
TH		 642static u64 ata_id_n_sectors(const u16 *id)
643{
644 if (ata_id_has_lba(id)) {
645 if (ata_id_has_lba48(id))
646 return ata_id_u64(id, 100);
647 else
648 return ata_id_u32(id, 60);
649 } else {
650 if (ata_id_current_chs_valid(id))
651 return ata_id_u32(id, 57);
652 else
653 return id[1] * id[3] * id[6];
654 }
655}
656
0baab86b
EF		 657/**
658 * ata_noop_dev_select - Select device 0/1 on ATA bus
659 * @ap: ATA channel to manipulate
660 * @device: ATA device (numbered from zero) to select
661 *
662 * This function performs no actual function.
663 *
664 * May be used as the dev_select() entry in ata_port_operations.
665 *
666 * LOCKING:
667 * caller.
668 */
1da177e4
LT		 669void ata_noop_dev_select (struct ata_port *ap, unsigned int device)
670{
671}
672
0baab86b 673
1da177e4
LT		 674/**
675 * ata_std_dev_select - Select device 0/1 on ATA bus
676 * @ap: ATA channel to manipulate
677 * @device: ATA device (numbered from zero) to select
678 *
679 * Use the method defined in the ATA specification to
680 * make either device 0, or device 1, active on the
0baab86b
EF		 681 * ATA channel. Works with both PIO and MMIO.
682 *
683 * May be used as the dev_select() entry in ata_port_operations.
1da177e4
LT		 684 *
685 * LOCKING:
686 * caller.
687 */
688
689void ata_std_dev_select (struct ata_port *ap, unsigned int device)
690{
691 u8 tmp;
692
693 if (device == 0)
694 tmp = ATA_DEVICE_OBS;
695 else
696 tmp = ATA_DEVICE_OBS | ATA_DEV1;
697
698 if (ap->flags & ATA_FLAG_MMIO) {
699 writeb(tmp, (void __iomem *) ap->ioaddr.device_addr);
700 } else {
701 outb(tmp, ap->ioaddr.device_addr);
702 }
703 ata_pause(ap); /* needed; also flushes, for mmio */
704}
705
706/**
707 * ata_dev_select - Select device 0/1 on ATA bus
708 * @ap: ATA channel to manipulate
709 * @device: ATA device (numbered from zero) to select
710 * @wait: non-zero to wait for Status register BSY bit to clear
711 * @can_sleep: non-zero if context allows sleeping
712 *
713 * Use the method defined in the ATA specification to
714 * make either device 0, or device 1, active on the
715 * ATA channel.
716 *
717 * This is a high-level version of ata_std_dev_select(),
718 * which additionally provides the services of inserting
719 * the proper pauses and status polling, where needed.
720 *
721 * LOCKING:
722 * caller.
723 */
724
725void ata_dev_select(struct ata_port *ap, unsigned int device,
726 unsigned int wait, unsigned int can_sleep)
727{
728 VPRINTK("ENTER, ata%u: device %u, wait %u\n",
729 ap->id, device, wait);
730
731 if (wait)
732 ata_wait_idle(ap);
733
734 ap->ops->dev_select(ap, device);
735
736 if (wait) {
737 if (can_sleep && ap->device[device].class == ATA_DEV_ATAPI)
738 msleep(150);
739 ata_wait_idle(ap);
740 }
741}
742
743/**
744 * ata_dump_id - IDENTIFY DEVICE info debugging output
0bd3300a 745 * @id: IDENTIFY DEVICE page to dump
1da177e4 746 *
0bd3300a
TH		 747 * Dump selected 16-bit words from the given IDENTIFY DEVICE
748 * page.
1da177e4
LT		 749 *
750 * LOCKING:
751 * caller.
752 */
753
0bd3300a 754static inline void ata_dump_id(const u16 *id)
1da177e4
LT		 755{
756 DPRINTK("49==0x%04x "
757 "53==0x%04x "
758 "63==0x%04x "
759 "64==0x%04x "
760 "75==0x%04x \n",
0bd3300a
TH		 761 id[49],
762 id[53],
763 id[63],
764 id[64],
765 id[75]);
1da177e4
LT		 766 DPRINTK("80==0x%04x "
767 "81==0x%04x "
768 "82==0x%04x "
769 "83==0x%04x "
770 "84==0x%04x \n",
0bd3300a
TH		 771 id[80],
772 id[81],
773 id[82],
774 id[83],
775 id[84]);
1da177e4
LT		 776 DPRINTK("88==0x%04x "
777 "93==0x%04x\n",
0bd3300a
TH		 778 id[88],
779 id[93]);
1da177e4
LT		 780}
781
cb95d562
TH		 782/**
783 * ata_id_xfermask - Compute xfermask from the given IDENTIFY data
784 * @id: IDENTIFY data to compute xfer mask from
785 *
786 * Compute the xfermask for this device. This is not as trivial
787 * as it seems if we must consider early devices correctly.
788 *
789 * FIXME: pre IDE drive timing (do we care ?).
790 *
791 * LOCKING:
792 * None.
793 *
794 * RETURNS:
795 * Computed xfermask
796 */
797static unsigned int ata_id_xfermask(const u16 *id)
798{
799 unsigned int pio_mask, mwdma_mask, udma_mask;
800
801 /* Usual case. Word 53 indicates word 64 is valid */
802 if (id[ATA_ID_FIELD_VALID] & (1 << 1)) {
803 pio_mask = id[ATA_ID_PIO_MODES] & 0x03;
804 pio_mask <<= 3;
805 pio_mask |= 0x7;
806 } else {
807 /* If word 64 isn't valid then Word 51 high byte holds
808 * the PIO timing number for the maximum. Turn it into
809 * a mask.
810 */
811 pio_mask = (2 << (id[ATA_ID_OLD_PIO_MODES] & 0xFF)) - 1 ;
812
813 /* But wait.. there's more. Design your standards by
814 * committee and you too can get a free iordy field to
815 * process. However its the speeds not the modes that
816 * are supported... Note drivers using the timing API
817 * will get this right anyway
818 */
819 }
820
821 mwdma_mask = id[ATA_ID_MWDMA_MODES] & 0x07;
fb21f0d0
TH		 822
823 udma_mask = 0;
824 if (id[ATA_ID_FIELD_VALID] & (1 << 2))
825 udma_mask = id[ATA_ID_UDMA_MODES] & 0xff;
cb95d562
TH		 826
827 return ata_pack_xfermask(pio_mask, mwdma_mask, udma_mask);
828}
829
86e45b6b
TH		 830/**
831 * ata_port_queue_task - Queue port_task
832 * @ap: The ata_port to queue port_task for
833 *
834 * Schedule @fn(@data) for execution after @delay jiffies using
835 * port_task. There is one port_task per port and it's the
836 * user(low level driver)'s responsibility to make sure that only
837 * one task is active at any given time.
838 *
839 * libata core layer takes care of synchronization between
840 * port_task and EH. ata_port_queue_task() may be ignored for EH
841 * synchronization.
842 *
843 * LOCKING:
844 * Inherited from caller.
845 */
846void ata_port_queue_task(struct ata_port *ap, void (*fn)(void *), void *data,
847 unsigned long delay)
848{
849 int rc;
850
2e755f68 851 if (ap->flags & ATA_FLAG_FLUSH_PORT_TASK)
86e45b6b
TH		 852 return;
853
854 PREPARE_WORK(&ap->port_task, fn, data);
855
856 if (!delay)
857 rc = queue_work(ata_wq, &ap->port_task);
858 else
859 rc = queue_delayed_work(ata_wq, &ap->port_task, delay);
860
861 /* rc == 0 means that another user is using port task */
862 WARN_ON(rc == 0);
863}
864
865/**
866 * ata_port_flush_task - Flush port_task
867 * @ap: The ata_port to flush port_task for
868 *
869 * After this function completes, port_task is guranteed not to
870 * be running or scheduled.
871 *
872 * LOCKING:
873 * Kernel thread context (may sleep)
874 */
875void ata_port_flush_task(struct ata_port *ap)
876{
877 unsigned long flags;
878
879 DPRINTK("ENTER\n");
880
881 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 882 ap->flags |= ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 883 spin_unlock_irqrestore(&ap->host_set->lock, flags);
884
885 DPRINTK("flush #1\n");
886 flush_workqueue(ata_wq);
887
888 /*
889 * At this point, if a task is running, it's guaranteed to see
890 * the FLUSH flag; thus, it will never queue pio tasks again.
891 * Cancel and flush.
892 */
893 if (!cancel_delayed_work(&ap->port_task)) {
894 DPRINTK("flush #2\n");
895 flush_workqueue(ata_wq);
896 }
897
898 spin_lock_irqsave(&ap->host_set->lock, flags);
2e755f68 899 ap->flags &= ~ATA_FLAG_FLUSH_PORT_TASK;
86e45b6b
TH		 900 spin_unlock_irqrestore(&ap->host_set->lock, flags);
901
902 DPRINTK("EXIT\n");
903}
904
77853bf2 905void ata_qc_complete_internal(struct ata_queued_cmd *qc)
a2a7a662 906{
77853bf2 907 struct completion *waiting = qc->private_data;
a2a7a662 908
77853bf2 909 qc->ap->ops->tf_read(qc->ap, &qc->tf);
a2a7a662 910 complete(waiting);
a2a7a662
TH		 911}
912
913/**
914 * ata_exec_internal - execute libata internal command
915 * @ap: Port to which the command is sent
916 * @dev: Device to which the command is sent
917 * @tf: Taskfile registers for the command and the result
918 * @dma_dir: Data tranfer direction of the command
919 * @buf: Data buffer of the command
920 * @buflen: Length of data buffer
921 *
922 * Executes libata internal command with timeout. @tf contains
923 * command on entry and result on return. Timeout and error
924 * conditions are reported via return value. No recovery action
925 * is taken after a command times out. It's caller's duty to
926 * clean up after timeout.
927 *
928 * LOCKING:
929 * None. Should be called with kernel context, might sleep.
930 */
931
932static unsigned
933ata_exec_internal(struct ata_port *ap, struct ata_device *dev,
934 struct ata_taskfile *tf,
935 int dma_dir, void *buf, unsigned int buflen)
936{
937 u8 command = tf->command;
938 struct ata_queued_cmd *qc;
939 DECLARE_COMPLETION(wait);
940 unsigned long flags;
77853bf2 941 unsigned int err_mask;
a2a7a662
TH		 942
943 spin_lock_irqsave(&ap->host_set->lock, flags);
944
945 qc = ata_qc_new_init(ap, dev);
946 BUG_ON(qc == NULL);
947
948 qc->tf = *tf;
949 qc->dma_dir = dma_dir;
950 if (dma_dir != DMA_NONE) {
951 ata_sg_init_one(qc, buf, buflen);
952 qc->nsect = buflen / ATA_SECT_SIZE;
953 }
954
77853bf2 955 qc->private_data = &wait;
a2a7a662
TH		 956 qc->complete_fn = ata_qc_complete_internal;
957
9a3d9eb0
TH		 958 qc->err_mask = ata_qc_issue(qc);
959 if (qc->err_mask)
8e436af9 960 ata_qc_complete(qc);
a2a7a662
TH		 961
962 spin_unlock_irqrestore(&ap->host_set->lock, flags);
963
964 if (!wait_for_completion_timeout(&wait, ATA_TMOUT_INTERNAL)) {
965 spin_lock_irqsave(&ap->host_set->lock, flags);
966
967 /* We're racing with irq here. If we lose, the
968 * following test prevents us from completing the qc
969 * again. If completion irq occurs after here but
970 * before the caller cleans up, it will result in a
971 * spurious interrupt. We can live with that.
972 */
77853bf2 973 if (qc->flags & ATA_QCFLAG_ACTIVE) {
11a56d24 974 qc->err_mask = AC_ERR_TIMEOUT;
a2a7a662
TH		 975 ata_qc_complete(qc);
976 printk(KERN_WARNING "ata%u: qc timeout (cmd 0x%x)\n",
977 ap->id, command);
978 }
979
980 spin_unlock_irqrestore(&ap->host_set->lock, flags);
981 }
982
77853bf2
TH		 983 *tf = qc->tf;
984 err_mask = qc->err_mask;
985
986 ata_qc_free(qc);
987
988 return err_mask;
a2a7a662
TH		 989}
990
1bc4ccff
AC		 991/**
992 * ata_pio_need_iordy - check if iordy needed
993 * @adev: ATA device
994 *
995 * Check if the current speed of the device requires IORDY. Used
996 * by various controllers for chip configuration.
997 */
998
999unsigned int ata_pio_need_iordy(const struct ata_device *adev)
1000{
1001 int pio;
1002 int speed = adev->pio_mode - XFER_PIO_0;
1003
1004 if (speed < 2)
1005 return 0;
1006 if (speed > 2)
1007 return 1;
1008
1009 /* If we have no drive specific rule, then PIO 2 is non IORDY */
1010
1011 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE */
1012 pio = adev->id[ATA_ID_EIDE_PIO];
1013 /* Is the speed faster than the drive allows non IORDY ? */
1014 if (pio) {
1015 /* This is cycle times not frequency - watch the logic! */
1016 if (pio > 240) /* PIO2 is 240nS per cycle */
1017 return 1;
1018 return 0;
1019 }
1020 }
1021 return 0;
1022}
1023
1da177e4 1024/**
49016aca
TH		 1025 * ata_dev_read_id - Read ID data from the specified device
1026 * @ap: port on which target device resides
1027 * @dev: target device
1028 * @p_class: pointer to class of the target device (may be changed)
1029 * @post_reset: is this read ID post-reset?
d9572b1d 1030 * @p_id: read IDENTIFY page (newly allocated)
1da177e4 1031 *
49016aca
TH		 1032 * Read ID data from the specified device. ATA_CMD_ID_ATA is
1033 * performed on ATA devices and ATA_CMD_ID_ATAPI on ATAPI
1034 * devices. This function also takes care of EDD signature
1035 * misreporting (to be removed once EDD support is gone) and
1036 * issues ATA_CMD_INIT_DEV_PARAMS for pre-ATA4 drives.
1da177e4
LT		 1037 *
1038 * LOCKING:
49016aca
TH		 1039 * Kernel thread context (may sleep)
1040 *
1041 * RETURNS:
1042 * 0 on success, -errno otherwise.
1da177e4 1043 */
49016aca 1044static int ata_dev_read_id(struct ata_port *ap, struct ata_device *dev,
d9572b1d 1045 unsigned int *p_class, int post_reset, u16 **p_id)
1da177e4 1046{
49016aca 1047 unsigned int class = *p_class;
1da177e4 1048 unsigned int using_edd;
a0123703 1049 struct ata_taskfile tf;
49016aca 1050 unsigned int err_mask = 0;
d9572b1d 1051 u16 *id;
49016aca
TH		 1052 const char *reason;
1053 int rc;
1da177e4 1054
49016aca 1055 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1056
61eb066a
TH		 1057 if (ap->ops->probe_reset ||
1058 ap->flags & (ATA_FLAG_SRST | ATA_FLAG_SATA_RESET))
1da177e4
LT		 1059 using_edd = 0;
1060 else
1061 using_edd = 1;
1062
49016aca 1063 ata_dev_select(ap, dev->devno, 1, 1); /* select device 0/1 */
1da177e4 1064
d9572b1d
TH		 1065 id = kmalloc(sizeof(id[0]) * ATA_ID_WORDS, GFP_KERNEL);
1066 if (id == NULL) {
1067 rc = -ENOMEM;
1068 reason = "out of memory";
1069 goto err_out;
1070 }
1071
49016aca
TH		 1072 retry:
1073 ata_tf_init(ap, &tf, dev->devno);
a0123703 1074
49016aca
TH		 1075 switch (class) {
1076 case ATA_DEV_ATA:
a0123703 1077 tf.command = ATA_CMD_ID_ATA;
49016aca
TH		 1078 break;
1079 case ATA_DEV_ATAPI:
a0123703 1080 tf.command = ATA_CMD_ID_ATAPI;
49016aca
TH		 1081 break;
1082 default:
1083 rc = -ENODEV;
1084 reason = "unsupported class";
1085 goto err_out;
1da177e4
LT		 1086 }
1087
a0123703 1088 tf.protocol = ATA_PROT_PIO;
1da177e4 1089
a0123703 1090 err_mask = ata_exec_internal(ap, dev, &tf, DMA_FROM_DEVICE,
49016aca 1091 id, sizeof(id[0]) * ATA_ID_WORDS);
1da177e4 1092
a0123703 1093 if (err_mask) {
49016aca
TH		 1094 rc = -EIO;
1095 reason = "I/O error";
1096
a0123703
TH		 1097 if (err_mask & ~AC_ERR_DEV)
1098 goto err_out;
0169e284 1099
1da177e4
LT		 1100 /*
1101 * arg! EDD works for all test cases, but seems to return
1102 * the ATA signature for some ATAPI devices. Until the
1103 * reason for this is found and fixed, we fix up the mess
1104 * here. If IDENTIFY DEVICE returns command aborted
1105 * (as ATAPI devices do), then we issue an
1106 * IDENTIFY PACKET DEVICE.
1107 *
1108 * ATA software reset (SRST, the default) does not appear
1109 * to have this problem.
1110 */
49016aca 1111 if ((using_edd) && (class == ATA_DEV_ATA)) {
a0123703 1112 u8 err = tf.feature;
1da177e4 1113 if (err & ATA_ABORTED) {
49016aca 1114 class = ATA_DEV_ATAPI;
1da177e4
LT		 1115 goto retry;
1116 }
1117 }
1118 goto err_out;
1119 }
1120
49016aca 1121 swap_buf_le16(id, ATA_ID_WORDS);
1da177e4
LT		 1122
1123 /* print device capabilities */
1124 printk(KERN_DEBUG "ata%u: dev %u cfg "
1125 "49:%04x 82:%04x 83:%04x 84:%04x 85:%04x 86:%04x 87:%04x 88:%04x\n",
49016aca
TH		 1126 ap->id, dev->devno,
1127 id[49], id[82], id[83], id[84], id[85], id[86], id[87], id[88]);
1128
1129 /* sanity check */
1130 if ((class == ATA_DEV_ATA) != ata_id_is_ata(id)) {
1131 rc = -EINVAL;
1132 reason = "device reports illegal type";
1133 goto err_out;
1134 }
1135
1136 if (post_reset && class == ATA_DEV_ATA) {
1137 /*
1138 * The exact sequence expected by certain pre-ATA4 drives is:
1139 * SRST RESET
1140 * IDENTIFY
1141 * INITIALIZE DEVICE PARAMETERS
1142 * anything else..
1143 * Some drives were very specific about that exact sequence.
1144 */
1145 if (ata_id_major_version(id) < 4 || !ata_id_has_lba(id)) {
1146 err_mask = ata_dev_init_params(ap, dev);
1147 if (err_mask) {
1148 rc = -EIO;
1149 reason = "INIT_DEV_PARAMS failed";
1150 goto err_out;
1151 }
1152
1153 /* current CHS translation info (id[53-58]) might be
1154 * changed. reread the identify device info.
1155 */
1156 post_reset = 0;
1157 goto retry;
1158 }
1159 }
1160
1161 *p_class = class;
d9572b1d 1162 *p_id = id;
49016aca
TH		 1163 return 0;
1164
1165 err_out:
1166 printk(KERN_WARNING "ata%u: dev %u failed to IDENTIFY (%s)\n",
1167 ap->id, dev->devno, reason);
d9572b1d 1168 kfree(id);
49016aca
TH		 1169 return rc;
1170}
1171
4b2f3ede
TH		 1172static inline u8 ata_dev_knobble(const struct ata_port *ap,
1173 struct ata_device *dev)
1174{
1175 return ((ap->cbl == ATA_CBL_SATA) && (!ata_id_is_sata(dev->id)));
1176}
1177
49016aca 1178/**
ffeae418
TH		 1179 * ata_dev_configure - Configure the specified ATA/ATAPI device
1180 * @ap: Port on which target device resides
1181 * @dev: Target device to configure
4c2d721a 1182 * @print_info: Enable device info printout
ffeae418
TH		 1183 *
1184 * Configure @dev according to @dev->id. Generic and low-level
1185 * driver specific fixups are also applied.
49016aca
TH		 1186 *
1187 * LOCKING:
ffeae418
TH		 1188 * Kernel thread context (may sleep)
1189 *
1190 * RETURNS:
1191 * 0 on success, -errno otherwise
49016aca 1192 */
4c2d721a
TH		 1193static int ata_dev_configure(struct ata_port *ap, struct ata_device *dev,
1194 int print_info)
49016aca 1195{
ff8854b2 1196 unsigned int xfer_mask;
49016aca
TH		 1197 int i, rc;
1198
1199 if (!ata_dev_present(dev)) {
1200 DPRINTK("ENTER/EXIT (host %u, dev %u) -- nodev\n",
ffeae418
TH		 1201 ap->id, dev->devno);
1202 return 0;
49016aca
TH		 1203 }
1204
ffeae418 1205 DPRINTK("ENTER, host %u, dev %u\n", ap->id, dev->devno);
1da177e4 1206
208a9933
TH		 1207 /* initialize to-be-configured parameters */
1208 dev->flags = 0;
1209 dev->max_sectors = 0;
1210 dev->cdb_len = 0;
1211 dev->n_sectors = 0;
1212 dev->cylinders = 0;
1213 dev->heads = 0;
1214 dev->sectors = 0;
1215
1da177e4
LT		 1216 /*
1217 * common ATA, ATAPI feature tests
1218 */
1219
8bf62ece
AL		 1220 /* we require DMA support (bits 8 of word 49) */
1221 if (!ata_id_has_dma(dev->id)) {
1222 printk(KERN_DEBUG "ata%u: no dma\n", ap->id);
ffeae418 1223 rc = -EINVAL;
1da177e4
LT		 1224 goto err_out_nosup;
1225 }
1226
ff8854b2
TH		 1227 /* find max transfer mode; for printk only */
1228 xfer_mask = ata_id_xfermask(dev->id);
1da177e4 1229
0bd3300a 1230 ata_dump_id(dev->id);
1da177e4
LT		 1231
1232 /* ATA-specific feature tests */
1233 if (dev->class == ATA_DEV_ATA) {
2940740b
TH		 1234 dev->n_sectors = ata_id_n_sectors(dev->id);
1235
8bf62ece 1236 if (ata_id_has_lba(dev->id)) {
4c2d721a 1237 const char *lba_desc;
8bf62ece 1238
4c2d721a
TH		 1239 lba_desc = "LBA";
1240 dev->flags |= ATA_DFLAG_LBA;
1241 if (ata_id_has_lba48(dev->id)) {
8bf62ece 1242 dev->flags |= ATA_DFLAG_LBA48;
4c2d721a
TH		 1243 lba_desc = "LBA48";
1244 }
8bf62ece
AL		 1245
1246 /* print device info to dmesg */
4c2d721a
TH		 1247 if (print_info)
1248 printk(KERN_INFO "ata%u: dev %u ATA-%d, "
1249 "max %s, %Lu sectors: %s\n",
1250 ap->id, dev->devno,
1251 ata_id_major_version(dev->id),
ff8854b2 1252 ata_mode_string(xfer_mask),
4c2d721a
TH		 1253 (unsigned long long)dev->n_sectors,
1254 lba_desc);
ffeae418 1255 } else {
8bf62ece
AL		 1256 /* CHS */
1257
1258 /* Default translation */
1259 dev->cylinders = dev->id[1];
1260 dev->heads = dev->id[3];
1261 dev->sectors = dev->id[6];
8bf62ece
AL		 1262
1263 if (ata_id_current_chs_valid(dev->id)) {
1264 /* Current CHS translation is valid. */
1265 dev->cylinders = dev->id[54];
1266 dev->heads = dev->id[55];
1267 dev->sectors = dev->id[56];
8bf62ece
AL		 1268 }
1269
1270 /* print device info to dmesg */
4c2d721a
TH		 1271 if (print_info)
1272 printk(KERN_INFO "ata%u: dev %u ATA-%d, "
1273 "max %s, %Lu sectors: CHS %u/%u/%u\n",
1274 ap->id, dev->devno,
1275 ata_id_major_version(dev->id),
ff8854b2 1276 ata_mode_string(xfer_mask),
4c2d721a
TH		 1277 (unsigned long long)dev->n_sectors,
1278 dev->cylinders, dev->heads, dev->sectors);
1da177e4
LT		 1279 }
1280
6e7846e9 1281 dev->cdb_len = 16;
1da177e4
LT		 1282 }
1283
1284 /* ATAPI-specific feature tests */
2c13b7ce 1285 else if (dev->class == ATA_DEV_ATAPI) {
1da177e4
LT		 1286 rc = atapi_cdb_len(dev->id);
1287 if ((rc < 12) || (rc > ATAPI_CDB_LEN)) {
1288 printk(KERN_WARNING "ata%u: unsupported CDB len\n", ap->id);
ffeae418 1289 rc = -EINVAL;
1da177e4
LT		 1290 goto err_out_nosup;
1291 }
6e7846e9 1292 dev->cdb_len = (unsigned int) rc;
1da177e4
LT		 1293
1294 /* print device info to dmesg */
4c2d721a
TH		 1295 if (print_info)
1296 printk(KERN_INFO "ata%u: dev %u ATAPI, max %s\n",
ff8854b2 1297 ap->id, dev->devno, ata_mode_string(xfer_mask));
1da177e4
LT		 1298 }
1299
6e7846e9
TH		 1300 ap->host->max_cmd_len = 0;
1301 for (i = 0; i < ATA_MAX_DEVICES; i++)
1302 ap->host->max_cmd_len = max_t(unsigned int,
1303 ap->host->max_cmd_len,
1304 ap->device[i].cdb_len);
1305
4b2f3ede
TH		 1306 /* limit bridge transfers to udma5, 200 sectors */
1307 if (ata_dev_knobble(ap, dev)) {
4c2d721a
TH		 1308 if (print_info)
1309 printk(KERN_INFO "ata%u(%u): applying bridge limits\n",
1310 ap->id, dev->devno);
4b2f3ede
TH		 1311 ap->udma_mask &= ATA_UDMA5;
1312 dev->max_sectors = ATA_MAX_SECTORS;
1313 }
1314
1315 if (ap->ops->dev_config)
1316 ap->ops->dev_config(ap, dev);
1317
1da177e4 1318 DPRINTK("EXIT, drv_stat = 0x%x\n", ata_chk_status(ap));
ffeae418 1319 return 0;
1da177e4
LT		 1320
1321err_out_nosup:
1322 printk(KERN_WARNING "ata%u: dev %u not supported, ignoring\n",
ffeae418 1323 ap->id, dev->devno);
1da177e4 1324 DPRINTK("EXIT, err\n");
ffeae418 1325 return rc;
1da177e4
LT		 1326}
1327
1328/**
1329 * ata_bus_probe - Reset and probe ATA bus
1330 * @ap: Bus to probe
1331 *
0cba632b
JG		 1332 * Master ATA bus probing function. Initiates a hardware-dependent
1333 * bus reset, then attempts to identify any devices found on
1334 * the bus.
1335 *
1da177e4 1336 * LOCKING:
0cba632b 1337 * PCI/etc. bus probe sem.
1da177e4
LT		 1338 *
1339 * RETURNS:
1340 * Zero on success, non-zero on error.
1341 */
1342
1343static int ata_bus_probe(struct ata_port *ap)
1344{
28ca5c57
TH		 1345 unsigned int classes[ATA_MAX_DEVICES];
1346 unsigned int i, rc, found = 0;
1da177e4 1347
28ca5c57 1348 ata_port_probe(ap);
c19ba8af 1349
2044470c
TH		 1350 /* reset and determine device classes */
1351 for (i = 0; i < ATA_MAX_DEVICES; i++)
1352 classes[i] = ATA_DEV_UNKNOWN;
2061a47a 1353
2044470c 1354 if (ap->ops->probe_reset) {
c19ba8af 1355 rc = ap->ops->probe_reset(ap, classes);
28ca5c57
TH		 1356 if (rc) {
1357 printk("ata%u: reset failed (errno=%d)\n", ap->id, rc);
1358 return rc;
c19ba8af 1359 }
28ca5c57 1360 } else {
c19ba8af
TH		 1361 ap->ops->phy_reset(ap);
1362
2044470c
TH		 1363 if (!(ap->flags & ATA_FLAG_PORT_DISABLED))
1364 for (i = 0; i < ATA_MAX_DEVICES; i++)
28ca5c57 1365 classes[i] = ap->device[i].class;
2044470c 1366
28ca5c57
TH		 1367 ata_port_probe(ap);
1368 }
1da177e4 1369
2044470c
TH		 1370 for (i = 0; i < ATA_MAX_DEVICES; i++)
1371 if (classes[i] == ATA_DEV_UNKNOWN)
1372 classes[i] = ATA_DEV_NONE;
1373
28ca5c57 1374 /* read IDENTIFY page and configure devices */
1da177e4 1375 for (i = 0; i < ATA_MAX_DEVICES; i++) {
ffeae418
TH		 1376 struct ata_device *dev = &ap->device[i];
1377
28ca5c57
TH		 1378 dev->class = classes[i];
1379
ffeae418
TH		 1380 if (!ata_dev_present(dev))
1381 continue;
1382
1383 WARN_ON(dev->id != NULL);
1384 if (ata_dev_read_id(ap, dev, &dev->class, 1, &dev->id)) {
1385 dev->class = ATA_DEV_NONE;
1386 continue;
1387 }
1388
4c2d721a 1389 if (ata_dev_configure(ap, dev, 1)) {
ffeae418
TH		 1390 dev->class++; /* disable device */
1391 continue;
1da177e4 1392 }
ffeae418 1393
ffeae418 1394 found = 1;
1da177e4
LT		 1395 }
1396
28ca5c57 1397 if (!found)
1da177e4
LT		 1398 goto err_out_disable;
1399
1400 ata_set_mode(ap);
1401 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1402 goto err_out_disable;
1403
1404 return 0;
1405
1406err_out_disable:
1407 ap->ops->port_disable(ap);
1da177e4
LT		 1408 return -1;
1409}
1410
1411/**
0cba632b
JG		 1412 * ata_port_probe - Mark port as enabled
1413 * @ap: Port for which we indicate enablement
1da177e4 1414 *
0cba632b
JG		 1415 * Modify @ap data structure such that the system
1416 * thinks that the entire port is enabled.
1417 *
1418 * LOCKING: host_set lock, or some other form of
1419 * serialization.
1da177e4
LT		 1420 */
1421
1422void ata_port_probe(struct ata_port *ap)
1423{
1424 ap->flags &= ~ATA_FLAG_PORT_DISABLED;
1425}
1426
3be680b7
TH		 1427/**
1428 * sata_print_link_status - Print SATA link status
1429 * @ap: SATA port to printk link status about
1430 *
1431 * This function prints link speed and status of a SATA link.
1432 *
1433 * LOCKING:
1434 * None.
1435 */
1436static void sata_print_link_status(struct ata_port *ap)
1437{
1438 u32 sstatus, tmp;
1439 const char *speed;
1440
1441 if (!ap->ops->scr_read)
1442 return;
1443
1444 sstatus = scr_read(ap, SCR_STATUS);
1445
1446 if (sata_dev_present(ap)) {
1447 tmp = (sstatus >> 4) & 0xf;
1448 if (tmp & (1 << 0))
1449 speed = "1.5";
1450 else if (tmp & (1 << 1))
1451 speed = "3.0";
1452 else
1453 speed = "<unknown>";
1454 printk(KERN_INFO "ata%u: SATA link up %s Gbps (SStatus %X)\n",
1455 ap->id, speed, sstatus);
1456 } else {
1457 printk(KERN_INFO "ata%u: SATA link down (SStatus %X)\n",
1458 ap->id, sstatus);
1459 }
1460}
1461
1da177e4 1462/**
780a87f7
JG		 1463 * __sata_phy_reset - Wake/reset a low-level SATA PHY
1464 * @ap: SATA port associated with target SATA PHY.
1da177e4 1465 *
780a87f7
JG		 1466 * This function issues commands to standard SATA Sxxx
1467 * PHY registers, to wake up the phy (and device), and
1468 * clear any reset condition.
1da177e4
LT		 1469 *
1470 * LOCKING:
0cba632b 1471 * PCI/etc. bus probe sem.
1da177e4
LT		 1472 *
1473 */
1474void __sata_phy_reset(struct ata_port *ap)
1475{
1476 u32 sstatus;
1477 unsigned long timeout = jiffies + (HZ * 5);
1478
1479 if (ap->flags & ATA_FLAG_SATA_RESET) {
cdcca89e
BR		 1480 /* issue phy wake/reset */
1481 scr_write_flush(ap, SCR_CONTROL, 0x301);
62ba2841
TH		 1482 /* Couldn't find anything in SATA I/II specs, but
1483 * AHCI-1.1 10.4.2 says at least 1 ms. */
1484 mdelay(1);
1da177e4 1485 }
cdcca89e 1486 scr_write_flush(ap, SCR_CONTROL, 0x300); /* phy wake/clear reset */
1da177e4
LT		 1487
1488 /* wait for phy to become ready, if necessary */
1489 do {
1490 msleep(200);
1491 sstatus = scr_read(ap, SCR_STATUS);
1492 if ((sstatus & 0xf) != 1)
1493 break;
1494 } while (time_before(jiffies, timeout));
1495
3be680b7
TH		 1496 /* print link status */
1497 sata_print_link_status(ap);
656563e3 1498
3be680b7
TH		 1499 /* TODO: phy layer with polling, timeouts, etc. */
1500 if (sata_dev_present(ap))
1da177e4 1501 ata_port_probe(ap);
3be680b7 1502 else
1da177e4 1503 ata_port_disable(ap);
1da177e4
LT		 1504
1505 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1506 return;
1507
1508 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
1509 ata_port_disable(ap);
1510 return;
1511 }
1512
1513 ap->cbl = ATA_CBL_SATA;
1514}
1515
1516/**
780a87f7
JG		 1517 * sata_phy_reset - Reset SATA bus.
1518 * @ap: SATA port associated with target SATA PHY.
1da177e4 1519 *
780a87f7
JG		 1520 * This function resets the SATA bus, and then probes
1521 * the bus for devices.
1da177e4
LT		 1522 *
1523 * LOCKING:
0cba632b 1524 * PCI/etc. bus probe sem.
1da177e4
LT		 1525 *
1526 */
1527void sata_phy_reset(struct ata_port *ap)
1528{
1529 __sata_phy_reset(ap);
1530 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1531 return;
1532 ata_bus_reset(ap);
1533}
1534
1535/**
780a87f7
JG		 1536 * ata_port_disable - Disable port.
1537 * @ap: Port to be disabled.
1da177e4 1538 *
780a87f7
JG		 1539 * Modify @ap data structure such that the system
1540 * thinks that the entire port is disabled, and should
1541 * never attempt to probe or communicate with devices
1542 * on this port.
1543 *
1544 * LOCKING: host_set lock, or some other form of
1545 * serialization.
1da177e4
LT		 1546 */
1547
1548void ata_port_disable(struct ata_port *ap)
1549{
1550 ap->device[0].class = ATA_DEV_NONE;
1551 ap->device[1].class = ATA_DEV_NONE;
1552 ap->flags |= ATA_FLAG_PORT_DISABLED;
1553}
1554
452503f9
AC		 1555/*
1556 * This mode timing computation functionality is ported over from
1557 * drivers/ide/ide-timing.h and was originally written by Vojtech Pavlik
1558 */
1559/*
1560 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds).
1561 * These were taken from ATA/ATAPI-6 standard, rev 0a, except
1562 * for PIO 5, which is a nonstandard extension and UDMA6, which
1563 * is currently supported only by Maxtor drives.
1564 */
1565
1566static const struct ata_timing ata_timing[] = {
1567
1568 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 },
1569 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 },
1570 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 },
1571 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 },
1572
1573 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 },
1574 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 },
1575 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 },
1576
1577/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */
1578
1579 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 },
1580 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 },
1581 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 },
1582
1583 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 },
1584 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 },
1585 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 },
1586
1587/* { XFER_PIO_5, 20, 50, 30, 100, 50, 30, 100, 0 }, */
1588 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 },
1589 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 },
1590
1591 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 },
1592 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 },
1593 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 },
1594
1595/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */
1596
1597 { 0xFF }
1598};
1599
1600#define ENOUGH(v,unit) (((v)-1)/(unit)+1)
1601#define EZ(v,unit) ((v)?ENOUGH(v,unit):0)
1602
1603static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT)
1604{
1605 q->setup = EZ(t->setup * 1000, T);
1606 q->act8b = EZ(t->act8b * 1000, T);
1607 q->rec8b = EZ(t->rec8b * 1000, T);
1608 q->cyc8b = EZ(t->cyc8b * 1000, T);
1609 q->active = EZ(t->active * 1000, T);
1610 q->recover = EZ(t->recover * 1000, T);
1611 q->cycle = EZ(t->cycle * 1000, T);
1612 q->udma = EZ(t->udma * 1000, UT);
1613}
1614
1615void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b,
1616 struct ata_timing *m, unsigned int what)
1617{
1618 if (what & ATA_TIMING_SETUP ) m->setup = max(a->setup, b->setup);
1619 if (what & ATA_TIMING_ACT8B ) m->act8b = max(a->act8b, b->act8b);
1620 if (what & ATA_TIMING_REC8B ) m->rec8b = max(a->rec8b, b->rec8b);
1621 if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b);
1622 if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active);
1623 if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover);
1624 if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle);
1625 if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma);
1626}
1627
1628static const struct ata_timing* ata_timing_find_mode(unsigned short speed)
1629{
1630 const struct ata_timing *t;
1631
1632 for (t = ata_timing; t->mode != speed; t++)
91190758 1633 if (t->mode == 0xFF)
452503f9
AC		 1634 return NULL;
1635 return t;
1636}
1637
1638int ata_timing_compute(struct ata_device *adev, unsigned short speed,
1639 struct ata_timing *t, int T, int UT)
1640{
1641 const struct ata_timing *s;
1642 struct ata_timing p;
1643
1644 /*
1645 * Find the mode.
75b1f2f8 1646 */
452503f9
AC		 1647
1648 if (!(s = ata_timing_find_mode(speed)))
1649 return -EINVAL;
1650
75b1f2f8
AL		 1651 memcpy(t, s, sizeof(*s));
1652
452503f9
AC		 1653 /*
1654 * If the drive is an EIDE drive, it can tell us it needs extended
1655 * PIO/MW_DMA cycle timing.
1656 */
1657
1658 if (adev->id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */
1659 memset(&p, 0, sizeof(p));
1660 if(speed >= XFER_PIO_0 && speed <= XFER_SW_DMA_0) {
1661 if (speed <= XFER_PIO_2) p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO];
1662 else p.cycle = p.cyc8b = adev->id[ATA_ID_EIDE_PIO_IORDY];
1663 } else if(speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) {
1664 p.cycle = adev->id[ATA_ID_EIDE_DMA_MIN];
1665 }
1666 ata_timing_merge(&p, t, t, ATA_TIMING_CYCLE | ATA_TIMING_CYC8B);
1667 }
1668
1669 /*
1670 * Convert the timing to bus clock counts.
1671 */
1672
75b1f2f8 1673 ata_timing_quantize(t, t, T, UT);
452503f9
AC		 1674
1675 /*
c893a3ae
RD		 1676 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY,
1677 * S.M.A.R.T * and some other commands. We have to ensure that the
1678 * DMA cycle timing is slower/equal than the fastest PIO timing.
452503f9
AC		 1679 */
1680
1681 if (speed > XFER_PIO_4) {
1682 ata_timing_compute(adev, adev->pio_mode, &p, T, UT);
1683 ata_timing_merge(&p, t, t, ATA_TIMING_ALL);
1684 }
1685
1686 /*
c893a3ae 1687 * Lengthen active & recovery time so that cycle time is correct.
452503f9
AC		 1688 */
1689
1690 if (t->act8b + t->rec8b < t->cyc8b) {
1691 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2;
1692 t->rec8b = t->cyc8b - t->act8b;
1693 }
1694
1695 if (t->active + t->recover < t->cycle) {
1696 t->active += (t->cycle - (t->active + t->recover)) / 2;
1697 t->recover = t->cycle - t->active;
1698 }
1699
1700 return 0;
1701}
1702
1da177e4
LT		 1703static void ata_dev_set_mode(struct ata_port *ap, struct ata_device *dev)
1704{
1da177e4
LT		 1705 if (!ata_dev_present(dev) || (ap->flags & ATA_FLAG_PORT_DISABLED))
1706 return;
1707
1708 if (dev->xfer_shift == ATA_SHIFT_PIO)
1709 dev->flags |= ATA_DFLAG_PIO;
1710
1711 ata_dev_set_xfermode(ap, dev);
1712
48a8a14f
TH		 1713 if (ata_dev_revalidate(ap, dev, 0)) {
1714 printk(KERN_ERR "ata%u: failed to revalidate after set "
1715 "xfermode, disabled\n", ap->id);
1716 ata_port_disable(ap);
1717 }
1718
23e71c3d
TH		 1719 DPRINTK("xfer_shift=%u, xfer_mode=0x%x\n",
1720 dev->xfer_shift, (int)dev->xfer_mode);
1da177e4
LT		 1721
1722 printk(KERN_INFO "ata%u: dev %u configured for %s\n",
23e71c3d
TH		 1723 ap->id, dev->devno,
1724 ata_mode_string(ata_xfer_mode2mask(dev->xfer_mode)));
1da177e4
LT		 1725}
1726
1727static int ata_host_set_pio(struct ata_port *ap)
1728{
a6d5a51c 1729 int i;
1da177e4
LT		 1730
1731 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1732 struct ata_device *dev = &ap->device[i];
a6d5a51c
TH		 1733
1734 if (!ata_dev_present(dev))
1735 continue;
1736
1737 if (!dev->pio_mode) {
1738 printk(KERN_WARNING "ata%u: no PIO support\n", ap->id);
1739 return -1;
1da177e4 1740 }
a6d5a51c
TH		 1741
1742 dev->xfer_mode = dev->pio_mode;
1743 dev->xfer_shift = ATA_SHIFT_PIO;
1744 if (ap->ops->set_piomode)
1745 ap->ops->set_piomode(ap, dev);
1da177e4
LT		 1746 }
1747
1748 return 0;
1749}
1750
a6d5a51c 1751static void ata_host_set_dma(struct ata_port *ap)
1da177e4
LT		 1752{
1753 int i;
1754
1755 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1756 struct ata_device *dev = &ap->device[i];
a6d5a51c
TH		 1757
1758 if (!ata_dev_present(dev) || !dev->dma_mode)
1759 continue;
1760
1761 dev->xfer_mode = dev->dma_mode;
1762 dev->xfer_shift = ata_xfer_mode2shift(dev->dma_mode);
1763 if (ap->ops->set_dmamode)
1764 ap->ops->set_dmamode(ap, dev);
1da177e4
LT		 1765 }
1766}
1767
1768/**
1769 * ata_set_mode - Program timings and issue SET FEATURES - XFER
1770 * @ap: port on which timings will be programmed
1771 *
780a87f7
JG		 1772 * Set ATA device disk transfer mode (PIO3, UDMA6, etc.).
1773 *
1da177e4 1774 * LOCKING:
0cba632b 1775 * PCI/etc. bus probe sem.
1da177e4
LT		 1776 */
1777static void ata_set_mode(struct ata_port *ap)
1778{
a6d5a51c 1779 int i, rc;
1da177e4 1780
a6d5a51c
TH		 1781 /* step 1: calculate xfer_mask */
1782 for (i = 0; i < ATA_MAX_DEVICES; i++) {
1783 struct ata_device *dev = &ap->device[i];
1784 unsigned int xfer_mask;
1785
1786 if (!ata_dev_present(dev))
1787 continue;
1788
1789 xfer_mask = ata_dev_xfermask(ap, dev);
1da177e4 1790
a6d5a51c
TH		 1791 dev->pio_mode = ata_xfer_mask2mode(xfer_mask & ATA_MASK_PIO);
1792 dev->dma_mode = ata_xfer_mask2mode(xfer_mask & (ATA_MASK_MWDMA |
1793 ATA_MASK_UDMA));
1794 }
1795
1796 /* step 2: always set host PIO timings */
1797 rc = ata_host_set_pio(ap);
1da177e4
LT		 1798 if (rc)
1799 goto err_out;
1800
a6d5a51c
TH		 1801 /* step 3: set host DMA timings */
1802 ata_host_set_dma(ap);
1da177e4
LT		 1803
1804 /* step 4: update devices' xfer mode */
a6d5a51c
TH		 1805 for (i = 0; i < ATA_MAX_DEVICES; i++)
1806 ata_dev_set_mode(ap, &ap->device[i]);
1da177e4
LT		 1807
1808 if (ap->flags & ATA_FLAG_PORT_DISABLED)
1809 return;
1810
1811 if (ap->ops->post_set_mode)
1812 ap->ops->post_set_mode(ap);
1813
1da177e4
LT		 1814 return;
1815
1816err_out:
1817 ata_port_disable(ap);
1818}
1819
1fdffbce
JG		 1820/**
1821 * ata_tf_to_host - issue ATA taskfile to host controller
1822 * @ap: port to which command is being issued
1823 * @tf: ATA taskfile register set
1824 *
1825 * Issues ATA taskfile register set to ATA host controller,
1826 * with proper synchronization with interrupt handler and
1827 * other threads.
1828 *
1829 * LOCKING:
1830 * spin_lock_irqsave(host_set lock)
1831 */
1832
1833static inline void ata_tf_to_host(struct ata_port *ap,
1834 const struct ata_taskfile *tf)
1835{
1836 ap->ops->tf_load(ap, tf);
1837 ap->ops->exec_command(ap, tf);
1838}
1839
1da177e4
LT		 1840/**
1841 * ata_busy_sleep - sleep until BSY clears, or timeout
1842 * @ap: port containing status register to be polled
1843 * @tmout_pat: impatience timeout
1844 * @tmout: overall timeout
1845 *
780a87f7
JG		 1846 * Sleep until ATA Status register bit BSY clears,
1847 * or a timeout occurs.
1848 *
1849 * LOCKING: None.
1da177e4
LT		 1850 */
1851
6f8b9958
TH		 1852unsigned int ata_busy_sleep (struct ata_port *ap,
1853 unsigned long tmout_pat, unsigned long tmout)
1da177e4
LT		 1854{
1855 unsigned long timer_start, timeout;
1856 u8 status;
1857
1858 status = ata_busy_wait(ap, ATA_BUSY, 300);
1859 timer_start = jiffies;
1860 timeout = timer_start + tmout_pat;
1861 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1862 msleep(50);
1863 status = ata_busy_wait(ap, ATA_BUSY, 3);
1864 }
1865
1866 if (status & ATA_BUSY)
1867 printk(KERN_WARNING "ata%u is slow to respond, "
1868 "please be patient\n", ap->id);
1869
1870 timeout = timer_start + tmout;
1871 while ((status & ATA_BUSY) && (time_before(jiffies, timeout))) {
1872 msleep(50);
1873 status = ata_chk_status(ap);
1874 }
1875
1876 if (status & ATA_BUSY) {
1877 printk(KERN_ERR "ata%u failed to respond (%lu secs)\n",
1878 ap->id, tmout / HZ);
1879 return 1;
1880 }
1881
1882 return 0;
1883}
1884
1885static void ata_bus_post_reset(struct ata_port *ap, unsigned int devmask)
1886{
1887 struct ata_ioports *ioaddr = &ap->ioaddr;
1888 unsigned int dev0 = devmask & (1 << 0);
1889 unsigned int dev1 = devmask & (1 << 1);
1890 unsigned long timeout;
1891
1892 /* if device 0 was found in ata_devchk, wait for its
1893 * BSY bit to clear
1894 */
1895 if (dev0)
1896 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1897
1898 /* if device 1 was found in ata_devchk, wait for
1899 * register access, then wait for BSY to clear
1900 */
1901 timeout = jiffies + ATA_TMOUT_BOOT;
1902 while (dev1) {
1903 u8 nsect, lbal;
1904
1905 ap->ops->dev_select(ap, 1);
1906 if (ap->flags & ATA_FLAG_MMIO) {
1907 nsect = readb((void __iomem *) ioaddr->nsect_addr);
1908 lbal = readb((void __iomem *) ioaddr->lbal_addr);
1909 } else {
1910 nsect = inb(ioaddr->nsect_addr);
1911 lbal = inb(ioaddr->lbal_addr);
1912 }
1913 if ((nsect == 1) && (lbal == 1))
1914 break;
1915 if (time_after(jiffies, timeout)) {
1916 dev1 = 0;
1917 break;
1918 }
1919 msleep(50); /* give drive a breather */
1920 }
1921 if (dev1)
1922 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1923
1924 /* is all this really necessary? */
1925 ap->ops->dev_select(ap, 0);
1926 if (dev1)
1927 ap->ops->dev_select(ap, 1);
1928 if (dev0)
1929 ap->ops->dev_select(ap, 0);
1930}
1931
1932/**
0cba632b
JG		 1933 * ata_bus_edd - Issue EXECUTE DEVICE DIAGNOSTIC command.
1934 * @ap: Port to reset and probe
1935 *
1936 * Use the EXECUTE DEVICE DIAGNOSTIC command to reset and
1937 * probe the bus. Not often used these days.
1da177e4
LT		 1938 *
1939 * LOCKING:
0cba632b 1940 * PCI/etc. bus probe sem.
e5338254 1941 * Obtains host_set lock.
1da177e4
LT		 1942 *
1943 */
1944
1945static unsigned int ata_bus_edd(struct ata_port *ap)
1946{
1947 struct ata_taskfile tf;
e5338254 1948 unsigned long flags;
1da177e4
LT		 1949
1950 /* set up execute-device-diag (bus reset) taskfile */
1951 /* also, take interrupts to a known state (disabled) */
1952 DPRINTK("execute-device-diag\n");
1953 ata_tf_init(ap, &tf, 0);
1954 tf.ctl |= ATA_NIEN;
1955 tf.command = ATA_CMD_EDD;
1956 tf.protocol = ATA_PROT_NODATA;
1957
1958 /* do bus reset */
e5338254 1959 spin_lock_irqsave(&ap->host_set->lock, flags);
1da177e4 1960 ata_tf_to_host(ap, &tf);
e5338254 1961 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1da177e4
LT		 1962
1963 /* spec says at least 2ms. but who knows with those
1964 * crazy ATAPI devices...
1965 */
1966 msleep(150);
1967
1968 return ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
1969}
1970
1971static unsigned int ata_bus_softreset(struct ata_port *ap,
1972 unsigned int devmask)
1973{
1974 struct ata_ioports *ioaddr = &ap->ioaddr;
1975
1976 DPRINTK("ata%u: bus reset via SRST\n", ap->id);
1977
1978 /* software reset. causes dev0 to be selected */
1979 if (ap->flags & ATA_FLAG_MMIO) {
1980 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1981 udelay(20); /* FIXME: flush */
1982 writeb(ap->ctl | ATA_SRST, (void __iomem *) ioaddr->ctl_addr);
1983 udelay(20); /* FIXME: flush */
1984 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
1985 } else {
1986 outb(ap->ctl, ioaddr->ctl_addr);
1987 udelay(10);
1988 outb(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
1989 udelay(10);
1990 outb(ap->ctl, ioaddr->ctl_addr);
1991 }
1992
1993 /* spec mandates ">= 2ms" before checking status.
1994 * We wait 150ms, because that was the magic delay used for
1995 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
1996 * between when the ATA command register is written, and then
1997 * status is checked. Because waiting for "a while" before
1998 * checking status is fine, post SRST, we perform this magic
1999 * delay here as well.
2000 */
2001 msleep(150);
2002
2003 ata_bus_post_reset(ap, devmask);
2004
2005 return 0;
2006}
2007
2008/**
2009 * ata_bus_reset - reset host port and associated ATA channel
2010 * @ap: port to reset
2011 *
2012 * This is typically the first time we actually start issuing
2013 * commands to the ATA channel. We wait for BSY to clear, then
2014 * issue EXECUTE DEVICE DIAGNOSTIC command, polling for its
2015 * result. Determine what devices, if any, are on the channel
2016 * by looking at the device 0/1 error register. Look at the signature
2017 * stored in each device's taskfile registers, to determine if
2018 * the device is ATA or ATAPI.
2019 *
2020 * LOCKING:
0cba632b
JG		 2021 * PCI/etc. bus probe sem.
2022 * Obtains host_set lock.
1da177e4
LT		 2023 *
2024 * SIDE EFFECTS:
2025 * Sets ATA_FLAG_PORT_DISABLED if bus reset fails.
2026 */
2027
2028void ata_bus_reset(struct ata_port *ap)
2029{
2030 struct ata_ioports *ioaddr = &ap->ioaddr;
2031 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2032 u8 err;
2033 unsigned int dev0, dev1 = 0, rc = 0, devmask = 0;
2034
2035 DPRINTK("ENTER, host %u, port %u\n", ap->id, ap->port_no);
2036
2037 /* determine if device 0/1 are present */
2038 if (ap->flags & ATA_FLAG_SATA_RESET)
2039 dev0 = 1;
2040 else {
2041 dev0 = ata_devchk(ap, 0);
2042 if (slave_possible)
2043 dev1 = ata_devchk(ap, 1);
2044 }
2045
2046 if (dev0)
2047 devmask |= (1 << 0);
2048 if (dev1)
2049 devmask |= (1 << 1);
2050
2051 /* select device 0 again */
2052 ap->ops->dev_select(ap, 0);
2053
2054 /* issue bus reset */
2055 if (ap->flags & ATA_FLAG_SRST)
2056 rc = ata_bus_softreset(ap, devmask);
2057 else if ((ap->flags & ATA_FLAG_SATA_RESET) == 0) {
2058 /* set up device control */
2059 if (ap->flags & ATA_FLAG_MMIO)
2060 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2061 else
2062 outb(ap->ctl, ioaddr->ctl_addr);
2063 rc = ata_bus_edd(ap);
2064 }
2065
2066 if (rc)
2067 goto err_out;
2068
2069 /*
2070 * determine by signature whether we have ATA or ATAPI devices
2071 */
b4dc7623 2072 ap->device[0].class = ata_dev_try_classify(ap, 0, &err);
1da177e4 2073 if ((slave_possible) && (err != 0x81))
b4dc7623 2074 ap->device[1].class = ata_dev_try_classify(ap, 1, &err);
1da177e4
LT		 2075
2076 /* re-enable interrupts */
2077 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2078 ata_irq_on(ap);
2079
2080 /* is double-select really necessary? */
2081 if (ap->device[1].class != ATA_DEV_NONE)
2082 ap->ops->dev_select(ap, 1);
2083 if (ap->device[0].class != ATA_DEV_NONE)
2084 ap->ops->dev_select(ap, 0);
2085
2086 /* if no devices were detected, disable this port */
2087 if ((ap->device[0].class == ATA_DEV_NONE) &&
2088 (ap->device[1].class == ATA_DEV_NONE))
2089 goto err_out;
2090
2091 if (ap->flags & (ATA_FLAG_SATA_RESET | ATA_FLAG_SRST)) {
2092 /* set up device control for ATA_FLAG_SATA_RESET */
2093 if (ap->flags & ATA_FLAG_MMIO)
2094 writeb(ap->ctl, (void __iomem *) ioaddr->ctl_addr);
2095 else
2096 outb(ap->ctl, ioaddr->ctl_addr);
2097 }
2098
2099 DPRINTK("EXIT\n");
2100 return;
2101
2102err_out:
2103 printk(KERN_ERR "ata%u: disabling port\n", ap->id);
2104 ap->ops->port_disable(ap);
2105
2106 DPRINTK("EXIT\n");
2107}
2108
7a7921e8
TH		 2109static int sata_phy_resume(struct ata_port *ap)
2110{
2111 unsigned long timeout = jiffies + (HZ * 5);
2112 u32 sstatus;
2113
2114 scr_write_flush(ap, SCR_CONTROL, 0x300);
2115
2116 /* Wait for phy to become ready, if necessary. */
2117 do {
2118 msleep(200);
2119 sstatus = scr_read(ap, SCR_STATUS);
2120 if ((sstatus & 0xf) != 1)
2121 return 0;
2122 } while (time_before(jiffies, timeout));
2123
2124 return -1;
2125}
2126
8a19ac89
TH		 2127/**
2128 * ata_std_probeinit - initialize probing
2129 * @ap: port to be probed
2130 *
2131 * @ap is about to be probed. Initialize it. This function is
2132 * to be used as standard callback for ata_drive_probe_reset().
3a39746a
TH		 2133 *
2134 * NOTE!!! Do not use this function as probeinit if a low level
2135 * driver implements only hardreset. Just pass NULL as probeinit
2136 * in that case. Using this function is probably okay but doing
2137 * so makes reset sequence different from the original
2138 * ->phy_reset implementation and Jeff nervous. :-P
8a19ac89
TH		 2139 */
2140extern void ata_std_probeinit(struct ata_port *ap)
2141{
3a39746a 2142 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read) {
8a19ac89 2143 sata_phy_resume(ap);
3a39746a
TH		 2144 if (sata_dev_present(ap))
2145 ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT);
2146 }
8a19ac89
TH		 2147}
2148
c2bd5804
TH		 2149/**
2150 * ata_std_softreset - reset host port via ATA SRST
2151 * @ap: port to reset
2152 * @verbose: fail verbosely
2153 * @classes: resulting classes of attached devices
2154 *
2155 * Reset host port using ATA SRST. This function is to be used
2156 * as standard callback for ata_drive_*_reset() functions.
2157 *
2158 * LOCKING:
2159 * Kernel thread context (may sleep)
2160 *
2161 * RETURNS:
2162 * 0 on success, -errno otherwise.
2163 */
2164int ata_std_softreset(struct ata_port *ap, int verbose, unsigned int *classes)
2165{
2166 unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
2167 unsigned int devmask = 0, err_mask;
2168 u8 err;
2169
2170 DPRINTK("ENTER\n");
2171
3a39746a
TH		 2172 if (ap->ops->scr_read && !sata_dev_present(ap)) {
2173 classes[0] = ATA_DEV_NONE;
2174 goto out;
2175 }
2176
c2bd5804
TH		 2177 /* determine if device 0/1 are present */
2178 if (ata_devchk(ap, 0))
2179 devmask |= (1 << 0);
2180 if (slave_possible && ata_devchk(ap, 1))
2181 devmask |= (1 << 1);
2182
c2bd5804
TH		 2183 /* select device 0 again */
2184 ap->ops->dev_select(ap, 0);
2185
2186 /* issue bus reset */
2187 DPRINTK("about to softreset, devmask=%x\n", devmask);
2188 err_mask = ata_bus_softreset(ap, devmask);
2189 if (err_mask) {
2190 if (verbose)
2191 printk(KERN_ERR "ata%u: SRST failed (err_mask=0x%x)\n",
2192 ap->id, err_mask);
2193 else
2194 DPRINTK("EXIT, softreset failed (err_mask=0x%x)\n",
2195 err_mask);
2196 return -EIO;
2197 }
2198
2199 /* determine by signature whether we have ATA or ATAPI devices */
2200 classes[0] = ata_dev_try_classify(ap, 0, &err);
2201 if (slave_possible && err != 0x81)
2202 classes[1] = ata_dev_try_classify(ap, 1, &err);
2203
3a39746a 2204 out:
c2bd5804
TH		 2205 DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
2206 return 0;
2207}
2208
2209/**
2210 * sata_std_hardreset - reset host port via SATA phy reset
2211 * @ap: port to reset
2212 * @verbose: fail verbosely
2213 * @class: resulting class of attached device
2214 *
2215 * SATA phy-reset host port using DET bits of SControl register.
2216 * This function is to be used as standard callback for
2217 * ata_drive_*_reset().
2218 *
2219 * LOCKING:
2220 * Kernel thread context (may sleep)
2221 *
2222 * RETURNS:
2223 * 0 on success, -errno otherwise.
2224 */
2225int sata_std_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
2226{
c2bd5804
TH		 2227 DPRINTK("ENTER\n");
2228
2229 /* Issue phy wake/reset */
2230 scr_write_flush(ap, SCR_CONTROL, 0x301);
2231
2232 /*
2233 * Couldn't find anything in SATA I/II specs, but AHCI-1.1
2234 * 10.4.2 says at least 1 ms.
2235 */
2236 msleep(1);
2237
7a7921e8
TH		 2238 /* Bring phy back */
2239 sata_phy_resume(ap);
c2bd5804 2240
c2bd5804
TH		 2241 /* TODO: phy layer with polling, timeouts, etc. */
2242 if (!sata_dev_present(ap)) {
2243 *class = ATA_DEV_NONE;
2244 DPRINTK("EXIT, link offline\n");
2245 return 0;
2246 }
2247
2248 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
2249 if (verbose)
2250 printk(KERN_ERR "ata%u: COMRESET failed "
2251 "(device not ready)\n", ap->id);
2252 else
2253 DPRINTK("EXIT, device not ready\n");
2254 return -EIO;
2255 }
2256
3a39746a
TH		 2257 ap->ops->dev_select(ap, 0); /* probably unnecessary */
2258
c2bd5804
TH		 2259 *class = ata_dev_try_classify(ap, 0, NULL);
2260
2261 DPRINTK("EXIT, class=%u\n", *class);
2262 return 0;
2263}
2264
2265/**
2266 * ata_std_postreset - standard postreset callback
2267 * @ap: the target ata_port
2268 * @classes: classes of attached devices
2269 *
2270 * This function is invoked after a successful reset. Note that
2271 * the device might have been reset more than once using
2272 * different reset methods before postreset is invoked.
c2bd5804
TH		 2273 *
2274 * This function is to be used as standard callback for
2275 * ata_drive_*_reset().
2276 *
2277 * LOCKING:
2278 * Kernel thread context (may sleep)
2279 */
2280void ata_std_postreset(struct ata_port *ap, unsigned int *classes)
2281{
2282 DPRINTK("ENTER\n");
2283
56497bd5 2284 /* set cable type if it isn't already set */
c2bd5804
TH		 2285 if (ap->cbl == ATA_CBL_NONE && ap->flags & ATA_FLAG_SATA)
2286 ap->cbl = ATA_CBL_SATA;
2287
2288 /* print link status */
2289 if (ap->cbl == ATA_CBL_SATA)
2290 sata_print_link_status(ap);
2291
3a39746a
TH		 2292 /* re-enable interrupts */
2293 if (ap->ioaddr.ctl_addr) /* FIXME: hack. create a hook instead */
2294 ata_irq_on(ap);
c2bd5804
TH		 2295
2296 /* is double-select really necessary? */
2297 if (classes[0] != ATA_DEV_NONE)
2298 ap->ops->dev_select(ap, 1);
2299 if (classes[1] != ATA_DEV_NONE)
2300 ap->ops->dev_select(ap, 0);
2301
3a39746a
TH		 2302 /* bail out if no device is present */
2303 if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
2304 DPRINTK("EXIT, no device\n");
2305 return;
2306 }
2307
2308 /* set up device control */
2309 if (ap->ioaddr.ctl_addr) {
2310 if (ap->flags & ATA_FLAG_MMIO)
2311 writeb(ap->ctl, (void __iomem *) ap->ioaddr.ctl_addr);
2312 else
2313 outb(ap->ctl, ap->ioaddr.ctl_addr);
2314 }
c2bd5804
TH		 2315
2316 DPRINTK("EXIT\n");
2317}
2318
2319/**
2320 * ata_std_probe_reset - standard probe reset method
2321 * @ap: prot to perform probe-reset
2322 * @classes: resulting classes of attached devices
2323 *
2324 * The stock off-the-shelf ->probe_reset method.
2325 *
2326 * LOCKING:
2327 * Kernel thread context (may sleep)
2328 *
2329 * RETURNS:
2330 * 0 on success, -errno otherwise.
2331 */
2332int ata_std_probe_reset(struct ata_port *ap, unsigned int *classes)
2333{
2334 ata_reset_fn_t hardreset;
2335
2336 hardreset = NULL;
b911fc3a 2337 if (ap->flags & ATA_FLAG_SATA && ap->ops->scr_read)
c2bd5804
TH		 2338 hardreset = sata_std_hardreset;
2339
8a19ac89 2340 return ata_drive_probe_reset(ap, ata_std_probeinit,
7944ea95 2341 ata_std_softreset, hardreset,
c2bd5804
TH		 2342 ata_std_postreset, classes);
2343}
2344
a62c0fc5
TH		 2345static int do_probe_reset(struct ata_port *ap, ata_reset_fn_t reset,
2346 ata_postreset_fn_t postreset,
2347 unsigned int *classes)
2348{
2349 int i, rc;
2350
2351 for (i = 0; i < ATA_MAX_DEVICES; i++)
2352 classes[i] = ATA_DEV_UNKNOWN;
2353
2354 rc = reset(ap, 0, classes);
2355 if (rc)
2356 return rc;
2357
2358 /* If any class isn't ATA_DEV_UNKNOWN, consider classification
2359 * is complete and convert all ATA_DEV_UNKNOWN to
2360 * ATA_DEV_NONE.
2361 */
2362 for (i = 0; i < ATA_MAX_DEVICES; i++)
2363 if (classes[i] != ATA_DEV_UNKNOWN)
2364 break;
2365
2366 if (i < ATA_MAX_DEVICES)
2367 for (i = 0; i < ATA_MAX_DEVICES; i++)
2368 if (classes[i] == ATA_DEV_UNKNOWN)
2369 classes[i] = ATA_DEV_NONE;
2370
2371 if (postreset)
2372 postreset(ap, classes);
2373
2374 return classes[0] != ATA_DEV_UNKNOWN ? 0 : -ENODEV;
2375}
2376
2377/**
2378 * ata_drive_probe_reset - Perform probe reset with given methods
2379 * @ap: port to reset
7944ea95 2380 * @probeinit: probeinit method (can be NULL)
a62c0fc5
TH		 2381 * @softreset: softreset method (can be NULL)
2382 * @hardreset: hardreset method (can be NULL)
2383 * @postreset: postreset method (can be NULL)
2384 * @classes: resulting classes of attached devices
2385 *
2386 * Reset the specified port and classify attached devices using
2387 * given methods. This function prefers softreset but tries all
2388 * possible reset sequences to reset and classify devices. This
2389 * function is intended to be used for constructing ->probe_reset
2390 * callback by low level drivers.
2391 *
2392 * Reset methods should follow the following rules.
2393 *
2394 * - Return 0 on sucess, -errno on failure.
2395 * - If classification is supported, fill classes[] with
2396 * recognized class codes.
2397 * - If classification is not supported, leave classes[] alone.
2398 * - If verbose is non-zero, print error message on failure;
2399 * otherwise, shut up.
2400 *
2401 * LOCKING:
2402 * Kernel thread context (may sleep)
2403 *
2404 * RETURNS:
2405 * 0 on success, -EINVAL if no reset method is avaliable, -ENODEV
2406 * if classification fails, and any error code from reset
2407 * methods.
2408 */
7944ea95 2409int ata_drive_probe_reset(struct ata_port *ap, ata_probeinit_fn_t probeinit,
a62c0fc5
TH		 2410 ata_reset_fn_t softreset, ata_reset_fn_t hardreset,
2411 ata_postreset_fn_t postreset, unsigned int *classes)
2412{
2413 int rc = -EINVAL;
2414
7944ea95
TH		 2415 if (probeinit)
2416 probeinit(ap);
2417
a62c0fc5
TH		 2418 if (softreset) {
2419 rc = do_probe_reset(ap, softreset, postreset, classes);
2420 if (rc == 0)
2421 return 0;
2422 }
2423
2424 if (!hardreset)
2425 return rc;
2426
2427 rc = do_probe_reset(ap, hardreset, postreset, classes);
2428 if (rc == 0 || rc != -ENODEV)
2429 return rc;
2430
2431 if (softreset)
2432 rc = do_probe_reset(ap, softreset, postreset, classes);
2433
2434 return rc;
2435}
2436
623a3128
TH		 2437/**
2438 * ata_dev_same_device - Determine whether new ID matches configured device
2439 * @ap: port on which the device to compare against resides
2440 * @dev: device to compare against
2441 * @new_class: class of the new device
2442 * @new_id: IDENTIFY page of the new device
2443 *
2444 * Compare @new_class and @new_id against @dev and determine
2445 * whether @dev is the device indicated by @new_class and
2446 * @new_id.
2447 *
2448 * LOCKING:
2449 * None.
2450 *
2451 * RETURNS:
2452 * 1 if @dev matches @new_class and @new_id, 0 otherwise.
2453 */
2454static int ata_dev_same_device(struct ata_port *ap, struct ata_device *dev,
2455 unsigned int new_class, const u16 *new_id)
2456{
2457 const u16 *old_id = dev->id;
2458 unsigned char model[2][41], serial[2][21];
2459 u64 new_n_sectors;
2460
2461 if (dev->class != new_class) {
2462 printk(KERN_INFO
2463 "ata%u: dev %u class mismatch %d != %d\n",
2464 ap->id, dev->devno, dev->class, new_class);
2465 return 0;
2466 }
2467
2468 ata_id_c_string(old_id, model[0], ATA_ID_PROD_OFS, sizeof(model[0]));
2469 ata_id_c_string(new_id, model[1], ATA_ID_PROD_OFS, sizeof(model[1]));
2470 ata_id_c_string(old_id, serial[0], ATA_ID_SERNO_OFS, sizeof(serial[0]));
2471 ata_id_c_string(new_id, serial[1], ATA_ID_SERNO_OFS, sizeof(serial[1]));
2472 new_n_sectors = ata_id_n_sectors(new_id);
2473
2474 if (strcmp(model[0], model[1])) {
2475 printk(KERN_INFO
2476 "ata%u: dev %u model number mismatch '%s' != '%s'\n",
2477 ap->id, dev->devno, model[0], model[1]);
2478 return 0;
2479 }
2480
2481 if (strcmp(serial[0], serial[1])) {
2482 printk(KERN_INFO
2483 "ata%u: dev %u serial number mismatch '%s' != '%s'\n",
2484 ap->id, dev->devno, serial[0], serial[1]);
2485 return 0;
2486 }
2487
2488 if (dev->class == ATA_DEV_ATA && dev->n_sectors != new_n_sectors) {
2489 printk(KERN_INFO
2490 "ata%u: dev %u n_sectors mismatch %llu != %llu\n",
2491 ap->id, dev->devno, (unsigned long long)dev->n_sectors,
2492 (unsigned long long)new_n_sectors);
2493 return 0;
2494 }
2495
2496 return 1;
2497}
2498
2499/**
2500 * ata_dev_revalidate - Revalidate ATA device
2501 * @ap: port on which the device to revalidate resides
2502 * @dev: device to revalidate
2503 * @post_reset: is this revalidation after reset?
2504 *
2505 * Re-read IDENTIFY page and make sure @dev is still attached to
2506 * the port.
2507 *
2508 * LOCKING:
2509 * Kernel thread context (may sleep)
2510 *
2511 * RETURNS:
2512 * 0 on success, negative errno otherwise
2513 */
2514int ata_dev_revalidate(struct ata_port *ap, struct ata_device *dev,
2515 int post_reset)
2516{
2517 unsigned int class;
2518 u16 *id;
2519 int rc;
2520
2521 if (!ata_dev_present(dev))
2522 return -ENODEV;
2523
2524 class = dev->class;
2525 id = NULL;
2526
2527 /* allocate & read ID data */
2528 rc = ata_dev_read_id(ap, dev, &class, post_reset, &id);
2529 if (rc)
2530 goto fail;
2531
2532 /* is the device still there? */
2533 if (!ata_dev_same_device(ap, dev, class, id)) {
2534 rc = -ENODEV;
2535 goto fail;
2536 }
2537
2538 kfree(dev->id);
2539 dev->id = id;
2540
2541 /* configure device according to the new ID */
2542 return ata_dev_configure(ap, dev, 0);
2543
2544 fail:
2545 printk(KERN_ERR "ata%u: dev %u revalidation failed (errno=%d)\n",
2546 ap->id, dev->devno, rc);
2547 kfree(id);
2548 return rc;
2549}
2550
98ac62de 2551static const char * const ata_dma_blacklist [] = {
1da177e4
LT		 2552 "WDC AC11000H",
2553 "WDC AC22100H",
2554 "WDC AC32500H",
2555 "WDC AC33100H",
2556 "WDC AC31600H",
2557 "WDC AC32100H",
2558 "WDC AC23200L",
2559 "Compaq CRD-8241B",
2560 "CRD-8400B",
2561 "CRD-8480B",
2562 "CRD-8482B",
2563 "CRD-84",
2564 "SanDisk SDP3B",
2565 "SanDisk SDP3B-64",
2566 "SANYO CD-ROM CRD",
2567 "HITACHI CDR-8",
2568 "HITACHI CDR-8335",
2569 "HITACHI CDR-8435",
2570 "Toshiba CD-ROM XM-6202B",
e922256a 2571 "TOSHIBA CD-ROM XM-1702BC",
1da177e4
LT		 2572 "CD-532E-A",
2573 "E-IDE CD-ROM CR-840",
2574 "CD-ROM Drive/F5A",
2575 "WPI CDD-820",
2576 "SAMSUNG CD-ROM SC-148C",
2577 "SAMSUNG CD-ROM SC",
2578 "SanDisk SDP3B-64",
1da177e4
LT		 2579 "ATAPI CD-ROM DRIVE 40X MAXIMUM",
2580 "_NEC DV5800A",
2581};
2582
057ace5e 2583static int ata_dma_blacklisted(const struct ata_device *dev)
1da177e4 2584{
2e02671d 2585 unsigned char model_num[41];
1da177e4
LT		 2586 int i;
2587
6a62a04d 2588 ata_id_c_string(dev->id, model_num, ATA_ID_PROD_OFS, sizeof(model_num));
1da177e4
LT		 2589
2590 for (i = 0; i < ARRAY_SIZE(ata_dma_blacklist); i++)
2e02671d 2591 if (!strcmp(ata_dma_blacklist[i], model_num))
1da177e4
LT		 2592 return 1;
2593
2594 return 0;
2595}
2596
a6d5a51c
TH		 2597/**
2598 * ata_dev_xfermask - Compute supported xfermask of the given device
2599 * @ap: Port on which the device to compute xfermask for resides
2600 * @dev: Device to compute xfermask for
2601 *
2602 * Compute supported xfermask of @dev. This function is
2603 * responsible for applying all known limits including host
2604 * controller limits, device blacklist, etc...
2605 *
2606 * LOCKING:
2607 * None.
2608 *
2609 * RETURNS:
2610 * Computed xfermask.
2611 */
2612static unsigned int ata_dev_xfermask(struct ata_port *ap,
2613 struct ata_device *dev)
1da177e4 2614{
a6d5a51c
TH		 2615 unsigned long xfer_mask;
2616 int i;
1da177e4 2617
a6d5a51c
TH		 2618 xfer_mask = ata_pack_xfermask(ap->pio_mask, ap->mwdma_mask,
2619 ap->udma_mask);
1da177e4 2620
a6d5a51c
TH		 2621 /* use port-wide xfermask for now */
2622 for (i = 0; i < ATA_MAX_DEVICES; i++) {
2623 struct ata_device *d = &ap->device[i];
2624 if (!ata_dev_present(d))
2625 continue;
2626 xfer_mask &= ata_id_xfermask(d->id);
2627 if (ata_dma_blacklisted(d))
2628 xfer_mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
1da177e4
LT		 2629 }
2630
a6d5a51c
TH		 2631 if (ata_dma_blacklisted(dev))
2632 printk(KERN_WARNING "ata%u: dev %u is on DMA blacklist, "
2633 "disabling DMA\n", ap->id, dev->devno);
2634
2635 return xfer_mask;
1da177e4
LT		 2636}
2637
1da177e4
LT		 2638/**
2639 * ata_dev_set_xfermode - Issue SET FEATURES - XFER MODE command
2640 * @ap: Port associated with device @dev
2641 * @dev: Device to which command will be sent
2642 *
780a87f7
JG		 2643 * Issue SET FEATURES - XFER MODE command to device @dev
2644 * on port @ap.
2645 *
1da177e4 2646 * LOCKING:
0cba632b 2647 * PCI/etc. bus probe sem.
1da177e4
LT		 2648 */
2649
2650static void ata_dev_set_xfermode(struct ata_port *ap, struct ata_device *dev)
2651{
a0123703 2652 struct ata_taskfile tf;
1da177e4
LT		 2653
2654 /* set up set-features taskfile */
2655 DPRINTK("set features - xfer mode\n");
2656
a0123703
TH		 2657 ata_tf_init(ap, &tf, dev->devno);
2658 tf.command = ATA_CMD_SET_FEATURES;
2659 tf.feature = SETFEATURES_XFER;
2660 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2661 tf.protocol = ATA_PROT_NODATA;
2662 tf.nsect = dev->xfer_mode;
1da177e4 2663
a0123703
TH		 2664 if (ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0)) {
2665 printk(KERN_ERR "ata%u: failed to set xfermode, disabled\n",
2666 ap->id);
1da177e4 2667 ata_port_disable(ap);
a0123703 2668 }
1da177e4
LT		 2669
2670 DPRINTK("EXIT\n");
2671}
2672
8bf62ece
AL		 2673/**
2674 * ata_dev_init_params - Issue INIT DEV PARAMS command
2675 * @ap: Port associated with device @dev
2676 * @dev: Device to which command will be sent
2677 *
2678 * LOCKING:
6aff8f1f
TH		 2679 * Kernel thread context (may sleep)
2680 *
2681 * RETURNS:
2682 * 0 on success, AC_ERR_* mask otherwise.
8bf62ece
AL		 2683 */
2684
6aff8f1f
TH		 2685static unsigned int ata_dev_init_params(struct ata_port *ap,
2686 struct ata_device *dev)
8bf62ece 2687{
a0123703 2688 struct ata_taskfile tf;
6aff8f1f 2689 unsigned int err_mask;
8bf62ece
AL		 2690 u16 sectors = dev->id[6];
2691 u16 heads = dev->id[3];
2692
2693 /* Number of sectors per track 1-255. Number of heads 1-16 */
2694 if (sectors < 1 || sectors > 255 || heads < 1 || heads > 16)
6aff8f1f 2695 return 0;
8bf62ece
AL		 2696
2697 /* set up init dev params taskfile */
2698 DPRINTK("init dev params \n");
2699
a0123703
TH		 2700 ata_tf_init(ap, &tf, dev->devno);
2701 tf.command = ATA_CMD_INIT_DEV_PARAMS;
2702 tf.flags |= ATA_TFLAG_ISADDR | ATA_TFLAG_DEVICE;
2703 tf.protocol = ATA_PROT_NODATA;
2704 tf.nsect = sectors;
2705 tf.device |= (heads - 1) & 0x0f; /* max head = num. of heads - 1 */
8bf62ece 2706
6aff8f1f 2707 err_mask = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
8bf62ece 2708
6aff8f1f
TH		 2709 DPRINTK("EXIT, err_mask=%x\n", err_mask);
2710 return err_mask;
8bf62ece
AL		 2711}
2712
1da177e4 2713/**
0cba632b
JG		 2714 * ata_sg_clean - Unmap DMA memory associated with command
2715 * @qc: Command containing DMA memory to be released
2716 *
2717 * Unmap all mapped DMA memory associated with this command.
1da177e4
LT		 2718 *
2719 * LOCKING:
0cba632b 2720 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2721 */
2722
2723static void ata_sg_clean(struct ata_queued_cmd *qc)
2724{
2725 struct ata_port *ap = qc->ap;
cedc9a47 2726 struct scatterlist *sg = qc->__sg;
1da177e4 2727 int dir = qc->dma_dir;
cedc9a47 2728 void *pad_buf = NULL;
1da177e4 2729
a4631474
TH		 2730 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
2731 WARN_ON(sg == NULL);
1da177e4
LT		 2732
2733 if (qc->flags & ATA_QCFLAG_SINGLE)
f131883e 2734 WARN_ON(qc->n_elem > 1);
1da177e4 2735
2c13b7ce 2736 VPRINTK("unmapping %u sg elements\n", qc->n_elem);
1da177e4 2737
cedc9a47
JG		 2738 /* if we padded the buffer out to 32-bit bound, and data
2739 * xfer direction is from-device, we must copy from the
2740 * pad buffer back into the supplied buffer
2741 */
2742 if (qc->pad_len && !(qc->tf.flags & ATA_TFLAG_WRITE))
2743 pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2744
2745 if (qc->flags & ATA_QCFLAG_SG) {
e1410f2d
JG		 2746 if (qc->n_elem)
2747 dma_unmap_sg(ap->host_set->dev, sg, qc->n_elem, dir);
cedc9a47
JG		 2748 /* restore last sg */
2749 sg[qc->orig_n_elem - 1].length += qc->pad_len;
2750 if (pad_buf) {
2751 struct scatterlist *psg = &qc->pad_sgent;
2752 void *addr = kmap_atomic(psg->page, KM_IRQ0);
2753 memcpy(addr + psg->offset, pad_buf, qc->pad_len);
dfa15988 2754 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 2755 }
2756 } else {
2e242fa9 2757 if (qc->n_elem)
e1410f2d
JG		 2758 dma_unmap_single(ap->host_set->dev,
2759 sg_dma_address(&sg[0]), sg_dma_len(&sg[0]),
2760 dir);
cedc9a47
JG		 2761 /* restore sg */
2762 sg->length += qc->pad_len;
2763 if (pad_buf)
2764 memcpy(qc->buf_virt + sg->length - qc->pad_len,
2765 pad_buf, qc->pad_len);
2766 }
1da177e4
LT		 2767
2768 qc->flags &= ~ATA_QCFLAG_DMAMAP;
cedc9a47 2769 qc->__sg = NULL;
1da177e4
LT		 2770}
2771
2772/**
2773 * ata_fill_sg - Fill PCI IDE PRD table
2774 * @qc: Metadata associated with taskfile to be transferred
2775 *
780a87f7
JG		 2776 * Fill PCI IDE PRD (scatter-gather) table with segments
2777 * associated with the current disk command.
2778 *
1da177e4 2779 * LOCKING:
780a87f7 2780 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 2781 *
2782 */
2783static void ata_fill_sg(struct ata_queued_cmd *qc)
2784{
1da177e4 2785 struct ata_port *ap = qc->ap;
cedc9a47
JG		 2786 struct scatterlist *sg;
2787 unsigned int idx;
1da177e4 2788
a4631474 2789 WARN_ON(qc->__sg == NULL);
f131883e 2790 WARN_ON(qc->n_elem == 0 && qc->pad_len == 0);
1da177e4
LT		 2791
2792 idx = 0;
cedc9a47 2793 ata_for_each_sg(sg, qc) {
1da177e4
LT		 2794 u32 addr, offset;
2795 u32 sg_len, len;
2796
2797 /* determine if physical DMA addr spans 64K boundary.
2798 * Note h/w doesn't support 64-bit, so we unconditionally
2799 * truncate dma_addr_t to u32.
2800 */
2801 addr = (u32) sg_dma_address(sg);
2802 sg_len = sg_dma_len(sg);
2803
2804 while (sg_len) {
2805 offset = addr & 0xffff;
2806 len = sg_len;
2807 if ((offset + sg_len) > 0x10000)
2808 len = 0x10000 - offset;
2809
2810 ap->prd[idx].addr = cpu_to_le32(addr);
2811 ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff);
2812 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
2813
2814 idx++;
2815 sg_len -= len;
2816 addr += len;
2817 }
2818 }
2819
2820 if (idx)
2821 ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
2822}
2823/**
2824 * ata_check_atapi_dma - Check whether ATAPI DMA can be supported
2825 * @qc: Metadata associated with taskfile to check
2826 *
780a87f7
JG		 2827 * Allow low-level driver to filter ATA PACKET commands, returning
2828 * a status indicating whether or not it is OK to use DMA for the
2829 * supplied PACKET command.
2830 *
1da177e4 2831 * LOCKING:
0cba632b
JG		 2832 * spin_lock_irqsave(host_set lock)
2833 *
1da177e4
LT		 2834 * RETURNS: 0 when ATAPI DMA can be used
2835 * nonzero otherwise
2836 */
2837int ata_check_atapi_dma(struct ata_queued_cmd *qc)
2838{
2839 struct ata_port *ap = qc->ap;
2840 int rc = 0; /* Assume ATAPI DMA is OK by default */
2841
2842 if (ap->ops->check_atapi_dma)
2843 rc = ap->ops->check_atapi_dma(qc);
2844
2845 return rc;
2846}
2847/**
2848 * ata_qc_prep - Prepare taskfile for submission
2849 * @qc: Metadata associated with taskfile to be prepared
2850 *
780a87f7
JG		 2851 * Prepare ATA taskfile for submission.
2852 *
1da177e4
LT		 2853 * LOCKING:
2854 * spin_lock_irqsave(host_set lock)
2855 */
2856void ata_qc_prep(struct ata_queued_cmd *qc)
2857{
2858 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2859 return;
2860
2861 ata_fill_sg(qc);
2862}
2863
0cba632b
JG		 2864/**
2865 * ata_sg_init_one - Associate command with memory buffer
2866 * @qc: Command to be associated
2867 * @buf: Memory buffer
2868 * @buflen: Length of memory buffer, in bytes.
2869 *
2870 * Initialize the data-related elements of queued_cmd @qc
2871 * to point to a single memory buffer, @buf of byte length @buflen.
2872 *
2873 * LOCKING:
2874 * spin_lock_irqsave(host_set lock)
2875 */
2876
1da177e4
LT		 2877void ata_sg_init_one(struct ata_queued_cmd *qc, void *buf, unsigned int buflen)
2878{
2879 struct scatterlist *sg;
2880
2881 qc->flags |= ATA_QCFLAG_SINGLE;
2882
2883 memset(&qc->sgent, 0, sizeof(qc->sgent));
cedc9a47 2884 qc->__sg = &qc->sgent;
1da177e4 2885 qc->n_elem = 1;
cedc9a47 2886 qc->orig_n_elem = 1;
1da177e4
LT		 2887 qc->buf_virt = buf;
2888
cedc9a47 2889 sg = qc->__sg;
f0612bbc 2890 sg_init_one(sg, buf, buflen);
1da177e4
LT		 2891}
2892
0cba632b
JG		 2893/**
2894 * ata_sg_init - Associate command with scatter-gather table.
2895 * @qc: Command to be associated
2896 * @sg: Scatter-gather table.
2897 * @n_elem: Number of elements in s/g table.
2898 *
2899 * Initialize the data-related elements of queued_cmd @qc
2900 * to point to a scatter-gather table @sg, containing @n_elem
2901 * elements.
2902 *
2903 * LOCKING:
2904 * spin_lock_irqsave(host_set lock)
2905 */
2906
1da177e4
LT		 2907void ata_sg_init(struct ata_queued_cmd *qc, struct scatterlist *sg,
2908 unsigned int n_elem)
2909{
2910 qc->flags |= ATA_QCFLAG_SG;
cedc9a47 2911 qc->__sg = sg;
1da177e4 2912 qc->n_elem = n_elem;
cedc9a47 2913 qc->orig_n_elem = n_elem;
1da177e4
LT		 2914}
2915
2916/**
0cba632b
JG		 2917 * ata_sg_setup_one - DMA-map the memory buffer associated with a command.
2918 * @qc: Command with memory buffer to be mapped.
2919 *
2920 * DMA-map the memory buffer associated with queued_cmd @qc.
1da177e4
LT		 2921 *
2922 * LOCKING:
2923 * spin_lock_irqsave(host_set lock)
2924 *
2925 * RETURNS:
0cba632b 2926 * Zero on success, negative on error.
1da177e4
LT		 2927 */
2928
2929static int ata_sg_setup_one(struct ata_queued_cmd *qc)
2930{
2931 struct ata_port *ap = qc->ap;
2932 int dir = qc->dma_dir;
cedc9a47 2933 struct scatterlist *sg = qc->__sg;
1da177e4 2934 dma_addr_t dma_address;
2e242fa9 2935 int trim_sg = 0;
1da177e4 2936
cedc9a47
JG		 2937 /* we must lengthen transfers to end on a 32-bit boundary */
2938 qc->pad_len = sg->length & 3;
2939 if (qc->pad_len) {
2940 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
2941 struct scatterlist *psg = &qc->pad_sgent;
2942
a4631474 2943 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 2944
2945 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
2946
2947 if (qc->tf.flags & ATA_TFLAG_WRITE)
2948 memcpy(pad_buf, qc->buf_virt + sg->length - qc->pad_len,
2949 qc->pad_len);
2950
2951 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
2952 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
2953 /* trim sg */
2954 sg->length -= qc->pad_len;
2e242fa9
TH		 2955 if (sg->length == 0)
2956 trim_sg = 1;
cedc9a47
JG		 2957
2958 DPRINTK("padding done, sg->length=%u pad_len=%u\n",
2959 sg->length, qc->pad_len);
2960 }
2961
2e242fa9
TH		 2962 if (trim_sg) {
2963 qc->n_elem--;
e1410f2d
JG		 2964 goto skip_map;
2965 }
2966
1da177e4 2967 dma_address = dma_map_single(ap->host_set->dev, qc->buf_virt,
32529e01 2968 sg->length, dir);
537a95d9
TH		 2969 if (dma_mapping_error(dma_address)) {
2970 /* restore sg */
2971 sg->length += qc->pad_len;
1da177e4 2972 return -1;
537a95d9 2973 }
1da177e4
LT		 2974
2975 sg_dma_address(sg) = dma_address;
32529e01 2976 sg_dma_len(sg) = sg->length;
1da177e4 2977
2e242fa9 2978skip_map:
1da177e4
LT		 2979 DPRINTK("mapped buffer of %d bytes for %s\n", sg_dma_len(sg),
2980 qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
2981
2982 return 0;
2983}
2984
2985/**
0cba632b
JG		 2986 * ata_sg_setup - DMA-map the scatter-gather table associated with a command.
2987 * @qc: Command with scatter-gather table to be mapped.
2988 *
2989 * DMA-map the scatter-gather table associated with queued_cmd @qc.
1da177e4
LT		 2990 *
2991 * LOCKING:
2992 * spin_lock_irqsave(host_set lock)
2993 *
2994 * RETURNS:
0cba632b 2995 * Zero on success, negative on error.
1da177e4
LT		 2996 *
2997 */
2998
2999static int ata_sg_setup(struct ata_queued_cmd *qc)
3000{
3001 struct ata_port *ap = qc->ap;
cedc9a47
JG		 3002 struct scatterlist *sg = qc->__sg;
3003 struct scatterlist *lsg = &sg[qc->n_elem - 1];
e1410f2d 3004 int n_elem, pre_n_elem, dir, trim_sg = 0;
1da177e4
LT		 3005
3006 VPRINTK("ENTER, ata%u\n", ap->id);
a4631474 3007 WARN_ON(!(qc->flags & ATA_QCFLAG_SG));
1da177e4 3008
cedc9a47
JG		 3009 /* we must lengthen transfers to end on a 32-bit boundary */
3010 qc->pad_len = lsg->length & 3;
3011 if (qc->pad_len) {
3012 void *pad_buf = ap->pad + (qc->tag * ATA_DMA_PAD_SZ);
3013 struct scatterlist *psg = &qc->pad_sgent;
3014 unsigned int offset;
3015
a4631474 3016 WARN_ON(qc->dev->class != ATA_DEV_ATAPI);
cedc9a47
JG		 3017
3018 memset(pad_buf, 0, ATA_DMA_PAD_SZ);
3019
3020 /*
3021 * psg->page/offset are used to copy to-be-written
3022 * data in this function or read data in ata_sg_clean.
3023 */
3024 offset = lsg->offset + lsg->length - qc->pad_len;
3025 psg->page = nth_page(lsg->page, offset >> PAGE_SHIFT);
3026 psg->offset = offset_in_page(offset);
3027
3028 if (qc->tf.flags & ATA_TFLAG_WRITE) {
3029 void *addr = kmap_atomic(psg->page, KM_IRQ0);
3030 memcpy(pad_buf, addr + psg->offset, qc->pad_len);
dfa15988 3031 kunmap_atomic(addr, KM_IRQ0);
cedc9a47
JG		 3032 }
3033
3034 sg_dma_address(psg) = ap->pad_dma + (qc->tag * ATA_DMA_PAD_SZ);
3035 sg_dma_len(psg) = ATA_DMA_PAD_SZ;
3036 /* trim last sg */
3037 lsg->length -= qc->pad_len;
e1410f2d
JG		 3038 if (lsg->length == 0)
3039 trim_sg = 1;
cedc9a47
JG		 3040
3041 DPRINTK("padding done, sg[%d].length=%u pad_len=%u\n",
3042 qc->n_elem - 1, lsg->length, qc->pad_len);
3043 }
3044
e1410f2d
JG		 3045 pre_n_elem = qc->n_elem;
3046 if (trim_sg && pre_n_elem)
3047 pre_n_elem--;
3048
3049 if (!pre_n_elem) {
3050 n_elem = 0;
3051 goto skip_map;
3052 }
3053
1da177e4 3054 dir = qc->dma_dir;
e1410f2d 3055 n_elem = dma_map_sg(ap->host_set->dev, sg, pre_n_elem, dir);
537a95d9
TH		 3056 if (n_elem < 1) {
3057 /* restore last sg */
3058 lsg->length += qc->pad_len;
1da177e4 3059 return -1;
537a95d9 3060 }
1da177e4
LT		 3061
3062 DPRINTK("%d sg elements mapped\n", n_elem);
3063
e1410f2d 3064skip_map:
1da177e4
LT		 3065 qc->n_elem = n_elem;
3066
3067 return 0;
3068}
3069
40e8c82c
TH		 3070/**
3071 * ata_poll_qc_complete - turn irq back on and finish qc
3072 * @qc: Command to complete
8e8b77dd 3073 * @err_mask: ATA status register content
40e8c82c
TH		 3074 *
3075 * LOCKING:
3076 * None. (grabs host lock)
3077 */
3078
a22e2eb0 3079void ata_poll_qc_complete(struct ata_queued_cmd *qc)
40e8c82c
TH		 3080{
3081 struct ata_port *ap = qc->ap;
b8f6153e 3082 unsigned long flags;
40e8c82c 3083
b8f6153e 3084 spin_lock_irqsave(&ap->host_set->lock, flags);
40e8c82c
TH		 3085 ap->flags &= ~ATA_FLAG_NOINTR;
3086 ata_irq_on(ap);
a22e2eb0 3087 ata_qc_complete(qc);
b8f6153e 3088 spin_unlock_irqrestore(&ap->host_set->lock, flags);
40e8c82c
TH		 3089}
3090
1da177e4 3091/**
c893a3ae 3092 * ata_pio_poll - poll using PIO, depending on current state
6f0ef4fa 3093 * @ap: the target ata_port
1da177e4
LT		 3094 *
3095 * LOCKING:
0cba632b 3096 * None. (executing in kernel thread context)
1da177e4
LT		 3097 *
3098 * RETURNS:
6f0ef4fa 3099 * timeout value to use
1da177e4
LT		 3100 */
3101
3102static unsigned long ata_pio_poll(struct ata_port *ap)
3103{
c14b8331 3104 struct ata_queued_cmd *qc;
1da177e4 3105 u8 status;
14be71f4
AL		 3106 unsigned int poll_state = HSM_ST_UNKNOWN;
3107 unsigned int reg_state = HSM_ST_UNKNOWN;
14be71f4 3108
c14b8331 3109 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3110 WARN_ON(qc == NULL);
c14b8331 3111
14be71f4
AL		 3112 switch (ap->hsm_task_state) {
3113 case HSM_ST:
3114 case HSM_ST_POLL:
3115 poll_state = HSM_ST_POLL;
3116 reg_state = HSM_ST;
1da177e4 3117 break;
14be71f4
AL		 3118 case HSM_ST_LAST:
3119 case HSM_ST_LAST_POLL:
3120 poll_state = HSM_ST_LAST_POLL;
3121 reg_state = HSM_ST_LAST;
1da177e4
LT		 3122 break;
3123 default:
3124 BUG();
3125 break;
3126 }
3127
3128 status = ata_chk_status(ap);
3129 if (status & ATA_BUSY) {
3130 if (time_after(jiffies, ap->pio_task_timeout)) {
11a56d24 3131 qc->err_mask |= AC_ERR_TIMEOUT;
7c398335 3132 ap->hsm_task_state = HSM_ST_TMOUT;
1da177e4
LT		 3133 return 0;
3134 }
14be71f4 3135 ap->hsm_task_state = poll_state;
1da177e4
LT		 3136 return ATA_SHORT_PAUSE;
3137 }
3138
14be71f4 3139 ap->hsm_task_state = reg_state;
1da177e4
LT		 3140 return 0;
3141}
3142
3143/**
6f0ef4fa
RD		 3144 * ata_pio_complete - check if drive is busy or idle
3145 * @ap: the target ata_port
1da177e4
LT		 3146 *
3147 * LOCKING:
0cba632b 3148 * None. (executing in kernel thread context)
7fb6ec28
JG		 3149 *
3150 * RETURNS:
3151 * Non-zero if qc completed, zero otherwise.
1da177e4
LT		 3152 */
3153
7fb6ec28 3154static int ata_pio_complete (struct ata_port *ap)
1da177e4
LT		 3155{
3156 struct ata_queued_cmd *qc;
3157 u8 drv_stat;
3158
3159 /*
31433ea3
AC		 3160 * This is purely heuristic. This is a fast path. Sometimes when
3161 * we enter, BSY will be cleared in a chk-status or two. If not,
3162 * the drive is probably seeking or something. Snooze for a couple
3163 * msecs, then chk-status again. If still busy, fall back to
14be71f4 3164 * HSM_ST_POLL state.
1da177e4 3165 */
fe79e683
AL		 3166 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3167 if (drv_stat & ATA_BUSY) {
1da177e4 3168 msleep(2);
fe79e683
AL		 3169 drv_stat = ata_busy_wait(ap, ATA_BUSY, 10);
3170 if (drv_stat & ATA_BUSY) {
14be71f4 3171 ap->hsm_task_state = HSM_ST_LAST_POLL;
1da177e4 3172 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
7fb6ec28 3173 return 0;
1da177e4
LT		 3174 }
3175 }
3176
c14b8331 3177 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3178 WARN_ON(qc == NULL);
c14b8331 3179
1da177e4
LT		 3180 drv_stat = ata_wait_idle(ap);
3181 if (!ata_ok(drv_stat)) {
1c848984 3182 qc->err_mask |= __ac_err_mask(drv_stat);
14be71f4 3183 ap->hsm_task_state = HSM_ST_ERR;
7fb6ec28 3184 return 0;
1da177e4
LT		 3185 }
3186
14be71f4 3187 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3188
a4631474 3189 WARN_ON(qc->err_mask);
a22e2eb0 3190 ata_poll_qc_complete(qc);
7fb6ec28
JG		 3191
3192 /* another command may start at this point */
3193
3194 return 1;
1da177e4
LT		 3195}
3196
0baab86b
EF		 3197
3198/**
c893a3ae 3199 * swap_buf_le16 - swap halves of 16-bit words in place
0baab86b
EF		 3200 * @buf: Buffer to swap
3201 * @buf_words: Number of 16-bit words in buffer.
3202 *
3203 * Swap halves of 16-bit words if needed to convert from
3204 * little-endian byte order to native cpu byte order, or
3205 * vice-versa.
3206 *
3207 * LOCKING:
6f0ef4fa 3208 * Inherited from caller.
0baab86b 3209 */
1da177e4
LT		 3210void swap_buf_le16(u16 *buf, unsigned int buf_words)
3211{
3212#ifdef __BIG_ENDIAN
3213 unsigned int i;
3214
3215 for (i = 0; i < buf_words; i++)
3216 buf[i] = le16_to_cpu(buf[i]);
3217#endif /* __BIG_ENDIAN */
3218}
3219
6ae4cfb5
AL		 3220/**
3221 * ata_mmio_data_xfer - Transfer data by MMIO
3222 * @ap: port to read/write
3223 * @buf: data buffer
3224 * @buflen: buffer length
344babaa 3225 * @write_data: read/write
6ae4cfb5
AL		 3226 *
3227 * Transfer data from/to the device data register by MMIO.
3228 *
3229 * LOCKING:
3230 * Inherited from caller.
6ae4cfb5
AL		 3231 */
3232
1da177e4
LT		 3233static void ata_mmio_data_xfer(struct ata_port *ap, unsigned char *buf,
3234 unsigned int buflen, int write_data)
3235{
3236 unsigned int i;
3237 unsigned int words = buflen >> 1;
3238 u16 *buf16 = (u16 *) buf;
3239 void __iomem *mmio = (void __iomem *)ap->ioaddr.data_addr;
3240
6ae4cfb5 3241 /* Transfer multiple of 2 bytes */
1da177e4
LT		 3242 if (write_data) {
3243 for (i = 0; i < words; i++)
3244 writew(le16_to_cpu(buf16[i]), mmio);
3245 } else {
3246 for (i = 0; i < words; i++)
3247 buf16[i] = cpu_to_le16(readw(mmio));
3248 }
6ae4cfb5
AL		 3249
3250 /* Transfer trailing 1 byte, if any. */
3251 if (unlikely(buflen & 0x01)) {
3252 u16 align_buf[1] = { 0 };
3253 unsigned char *trailing_buf = buf + buflen - 1;
3254
3255 if (write_data) {
3256 memcpy(align_buf, trailing_buf, 1);
3257 writew(le16_to_cpu(align_buf[0]), mmio);
3258 } else {
3259 align_buf[0] = cpu_to_le16(readw(mmio));
3260 memcpy(trailing_buf, align_buf, 1);
3261 }
3262 }
1da177e4
LT		 3263}
3264
6ae4cfb5
AL		 3265/**
3266 * ata_pio_data_xfer - Transfer data by PIO
3267 * @ap: port to read/write
3268 * @buf: data buffer
3269 * @buflen: buffer length
344babaa 3270 * @write_data: read/write
6ae4cfb5
AL		 3271 *
3272 * Transfer data from/to the device data register by PIO.
3273 *
3274 * LOCKING:
3275 * Inherited from caller.
6ae4cfb5
AL		 3276 */
3277
1da177e4
LT		 3278static void ata_pio_data_xfer(struct ata_port *ap, unsigned char *buf,
3279 unsigned int buflen, int write_data)
3280{
6ae4cfb5 3281 unsigned int words = buflen >> 1;
1da177e4 3282
6ae4cfb5 3283 /* Transfer multiple of 2 bytes */
1da177e4 3284 if (write_data)
6ae4cfb5 3285 outsw(ap->ioaddr.data_addr, buf, words);
1da177e4 3286 else
6ae4cfb5
AL		 3287 insw(ap->ioaddr.data_addr, buf, words);
3288
3289 /* Transfer trailing 1 byte, if any. */
3290 if (unlikely(buflen & 0x01)) {
3291 u16 align_buf[1] = { 0 };
3292 unsigned char *trailing_buf = buf + buflen - 1;
3293
3294 if (write_data) {
3295 memcpy(align_buf, trailing_buf, 1);
3296 outw(le16_to_cpu(align_buf[0]), ap->ioaddr.data_addr);
3297 } else {
3298 align_buf[0] = cpu_to_le16(inw(ap->ioaddr.data_addr));
3299 memcpy(trailing_buf, align_buf, 1);
3300 }
3301 }
1da177e4
LT		 3302}
3303
6ae4cfb5
AL		 3304/**
3305 * ata_data_xfer - Transfer data from/to the data register.
3306 * @ap: port to read/write
3307 * @buf: data buffer
3308 * @buflen: buffer length
3309 * @do_write: read/write
3310 *
3311 * Transfer data from/to the device data register.
3312 *
3313 * LOCKING:
3314 * Inherited from caller.
6ae4cfb5
AL		 3315 */
3316
1da177e4
LT		 3317static void ata_data_xfer(struct ata_port *ap, unsigned char *buf,
3318 unsigned int buflen, int do_write)
3319{
a1bd9e68
AC		 3320 /* Make the crap hardware pay the costs not the good stuff */
3321 if (unlikely(ap->flags & ATA_FLAG_IRQ_MASK)) {
3322 unsigned long flags;
3323 local_irq_save(flags);
3324 if (ap->flags & ATA_FLAG_MMIO)
3325 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3326 else
3327 ata_pio_data_xfer(ap, buf, buflen, do_write);
3328 local_irq_restore(flags);
3329 } else {
3330 if (ap->flags & ATA_FLAG_MMIO)
3331 ata_mmio_data_xfer(ap, buf, buflen, do_write);
3332 else
3333 ata_pio_data_xfer(ap, buf, buflen, do_write);
3334 }
1da177e4
LT		 3335}
3336
6ae4cfb5
AL		 3337/**
3338 * ata_pio_sector - Transfer ATA_SECT_SIZE (512 bytes) of data.
3339 * @qc: Command on going
3340 *
3341 * Transfer ATA_SECT_SIZE of data from/to the ATA device.
3342 *
3343 * LOCKING:
3344 * Inherited from caller.
3345 */
3346
1da177e4
LT		 3347static void ata_pio_sector(struct ata_queued_cmd *qc)
3348{
3349 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3350 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3351 struct ata_port *ap = qc->ap;
3352 struct page *page;
3353 unsigned int offset;
3354 unsigned char *buf;
3355
3356 if (qc->cursect == (qc->nsect - 1))
14be71f4 3357 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3358
3359 page = sg[qc->cursg].page;
3360 offset = sg[qc->cursg].offset + qc->cursg_ofs * ATA_SECT_SIZE;
3361
3362 /* get the current page and offset */
3363 page = nth_page(page, (offset >> PAGE_SHIFT));
3364 offset %= PAGE_SIZE;
3365
3366 buf = kmap(page) + offset;
3367
3368 qc->cursect++;
3369 qc->cursg_ofs++;
3370
32529e01 3371 if ((qc->cursg_ofs * ATA_SECT_SIZE) == (&sg[qc->cursg])->length) {
1da177e4
LT		 3372 qc->cursg++;
3373 qc->cursg_ofs = 0;
3374 }
3375
3376 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3377
3378 /* do the actual data transfer */
3379 do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
3380 ata_data_xfer(ap, buf, ATA_SECT_SIZE, do_write);
3381
3382 kunmap(page);
3383}
3384
6ae4cfb5
AL		 3385/**
3386 * __atapi_pio_bytes - Transfer data from/to the ATAPI device.
3387 * @qc: Command on going
3388 * @bytes: number of bytes
3389 *
3390 * Transfer Transfer data from/to the ATAPI device.
3391 *
3392 * LOCKING:
3393 * Inherited from caller.
3394 *
3395 */
3396
1da177e4
LT		 3397static void __atapi_pio_bytes(struct ata_queued_cmd *qc, unsigned int bytes)
3398{
3399 int do_write = (qc->tf.flags & ATA_TFLAG_WRITE);
cedc9a47 3400 struct scatterlist *sg = qc->__sg;
1da177e4
LT		 3401 struct ata_port *ap = qc->ap;
3402 struct page *page;
3403 unsigned char *buf;
3404 unsigned int offset, count;
3405
563a6e1f 3406 if (qc->curbytes + bytes >= qc->nbytes)
14be71f4 3407 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3408
3409next_sg:
563a6e1f 3410 if (unlikely(qc->cursg >= qc->n_elem)) {
7fb6ec28 3411 /*
563a6e1f
AL		 3412 * The end of qc->sg is reached and the device expects
3413 * more data to transfer. In order not to overrun qc->sg
3414 * and fulfill length specified in the byte count register,
3415 * - for read case, discard trailing data from the device
3416 * - for write case, padding zero data to the device
3417 */
3418 u16 pad_buf[1] = { 0 };
3419 unsigned int words = bytes >> 1;
3420 unsigned int i;
3421
3422 if (words) /* warning if bytes > 1 */
7fb6ec28 3423 printk(KERN_WARNING "ata%u: %u bytes trailing data\n",
563a6e1f
AL		 3424 ap->id, bytes);
3425
3426 for (i = 0; i < words; i++)
3427 ata_data_xfer(ap, (unsigned char*)pad_buf, 2, do_write);
3428
14be71f4 3429 ap->hsm_task_state = HSM_ST_LAST;
563a6e1f
AL		 3430 return;
3431 }
3432
cedc9a47 3433 sg = &qc->__sg[qc->cursg];
1da177e4 3434
1da177e4
LT		 3435 page = sg->page;
3436 offset = sg->offset + qc->cursg_ofs;
3437
3438 /* get the current page and offset */
3439 page = nth_page(page, (offset >> PAGE_SHIFT));
3440 offset %= PAGE_SIZE;
3441
6952df03 3442 /* don't overrun current sg */
32529e01 3443 count = min(sg->length - qc->cursg_ofs, bytes);
1da177e4
LT		 3444
3445 /* don't cross page boundaries */
3446 count = min(count, (unsigned int)PAGE_SIZE - offset);
3447
3448 buf = kmap(page) + offset;
3449
3450 bytes -= count;
3451 qc->curbytes += count;
3452 qc->cursg_ofs += count;
3453
32529e01 3454 if (qc->cursg_ofs == sg->length) {
1da177e4
LT		 3455 qc->cursg++;
3456 qc->cursg_ofs = 0;
3457 }
3458
3459 DPRINTK("data %s\n", qc->tf.flags & ATA_TFLAG_WRITE ? "write" : "read");
3460
3461 /* do the actual data transfer */
3462 ata_data_xfer(ap, buf, count, do_write);
3463
3464 kunmap(page);
3465
563a6e1f 3466 if (bytes)
1da177e4 3467 goto next_sg;
1da177e4
LT		 3468}
3469
6ae4cfb5
AL		 3470/**
3471 * atapi_pio_bytes - Transfer data from/to the ATAPI device.
3472 * @qc: Command on going
3473 *
3474 * Transfer Transfer data from/to the ATAPI device.
3475 *
3476 * LOCKING:
3477 * Inherited from caller.
6ae4cfb5
AL		 3478 */
3479
1da177e4
LT		 3480static void atapi_pio_bytes(struct ata_queued_cmd *qc)
3481{
3482 struct ata_port *ap = qc->ap;
3483 struct ata_device *dev = qc->dev;
3484 unsigned int ireason, bc_lo, bc_hi, bytes;
3485 int i_write, do_write = (qc->tf.flags & ATA_TFLAG_WRITE) ? 1 : 0;
3486
3487 ap->ops->tf_read(ap, &qc->tf);
3488 ireason = qc->tf.nsect;
3489 bc_lo = qc->tf.lbam;
3490 bc_hi = qc->tf.lbah;
3491 bytes = (bc_hi << 8) | bc_lo;
3492
3493 /* shall be cleared to zero, indicating xfer of data */
3494 if (ireason & (1 << 0))
3495 goto err_out;
3496
3497 /* make sure transfer direction matches expected */
3498 i_write = ((ireason & (1 << 1)) == 0) ? 1 : 0;
3499 if (do_write != i_write)
3500 goto err_out;
3501
3502 __atapi_pio_bytes(qc, bytes);
3503
3504 return;
3505
3506err_out:
3507 printk(KERN_INFO "ata%u: dev %u: ATAPI check failed\n",
3508 ap->id, dev->devno);
11a56d24 3509 qc->err_mask |= AC_ERR_HSM;
14be71f4 3510 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3511}
3512
3513/**
6f0ef4fa
RD		 3514 * ata_pio_block - start PIO on a block
3515 * @ap: the target ata_port
1da177e4
LT		 3516 *
3517 * LOCKING:
0cba632b 3518 * None. (executing in kernel thread context)
1da177e4
LT		 3519 */
3520
3521static void ata_pio_block(struct ata_port *ap)
3522{
3523 struct ata_queued_cmd *qc;
3524 u8 status;
3525
3526 /*
6f0ef4fa 3527 * This is purely heuristic. This is a fast path.
1da177e4
LT		 3528 * Sometimes when we enter, BSY will be cleared in
3529 * a chk-status or two. If not, the drive is probably seeking
3530 * or something. Snooze for a couple msecs, then
3531 * chk-status again. If still busy, fall back to
14be71f4 3532 * HSM_ST_POLL state.
1da177e4
LT		 3533 */
3534 status = ata_busy_wait(ap, ATA_BUSY, 5);
3535 if (status & ATA_BUSY) {
3536 msleep(2);
3537 status = ata_busy_wait(ap, ATA_BUSY, 10);
3538 if (status & ATA_BUSY) {
14be71f4 3539 ap->hsm_task_state = HSM_ST_POLL;
1da177e4
LT		 3540 ap->pio_task_timeout = jiffies + ATA_TMOUT_PIO;
3541 return;
3542 }
3543 }
3544
3545 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3546 WARN_ON(qc == NULL);
1da177e4 3547
fe79e683
AL		 3548 /* check error */
3549 if (status & (ATA_ERR | ATA_DF)) {
3550 qc->err_mask |= AC_ERR_DEV;
3551 ap->hsm_task_state = HSM_ST_ERR;
3552 return;
3553 }
3554
3555 /* transfer data if any */
1da177e4 3556 if (is_atapi_taskfile(&qc->tf)) {
fe79e683 3557 /* DRQ=0 means no more data to transfer */
1da177e4 3558 if ((status & ATA_DRQ) == 0) {
14be71f4 3559 ap->hsm_task_state = HSM_ST_LAST;
1da177e4
LT		 3560 return;
3561 }
3562
3563 atapi_pio_bytes(qc);
3564 } else {
3565 /* handle BSY=0, DRQ=0 as error */
3566 if ((status & ATA_DRQ) == 0) {
11a56d24 3567 qc->err_mask |= AC_ERR_HSM;
14be71f4 3568 ap->hsm_task_state = HSM_ST_ERR;
1da177e4
LT		 3569 return;
3570 }
3571
3572 ata_pio_sector(qc);
3573 }
3574}
3575
3576static void ata_pio_error(struct ata_port *ap)
3577{
3578 struct ata_queued_cmd *qc;
a7dac447 3579
1da177e4 3580 qc = ata_qc_from_tag(ap, ap->active_tag);
a4631474 3581 WARN_ON(qc == NULL);
1da177e4 3582
0565c26d
AL		 3583 if (qc->tf.command != ATA_CMD_PACKET)
3584 printk(KERN_WARNING "ata%u: PIO error\n", ap->id);
3585
1c848984
AL		 3586 /* make sure qc->err_mask is available to
3587 * know what's wrong and recover
3588 */
a4631474 3589 WARN_ON(qc->err_mask == 0);
1c848984 3590
14be71f4 3591 ap->hsm_task_state = HSM_ST_IDLE;
1da177e4 3592
a22e2eb0 3593 ata_poll_qc_complete(qc);
1da177e4
LT		 3594}
3595
3596static void ata_pio_task(void *_data)
3597{
3598 struct ata_port *ap = _data;
7fb6ec28
JG		 3599 unsigned long timeout;
3600 int qc_completed;
3601
3602fsm_start:
3603 timeout = 0;
3604 qc_completed = 0;
1da177e4 3605
14be71f4
AL		 3606 switch (ap->hsm_task_state) {
3607 case HSM_ST_IDLE:
1da177e4
LT		 3608 return;
3609
14be71f4 3610 case HSM_ST:
1da177e4
LT		 3611 ata_pio_block(ap);
3612 break;
3613
14be71f4 3614 case HSM_ST_LAST:
7fb6ec28 3615 qc_completed = ata_pio_complete(ap);
1da177e4
LT		 3616 break;
3617
14be71f4
AL		 3618 case HSM_ST_POLL:
3619 case HSM_ST_LAST_POLL:
1da177e4
LT		 3620 timeout = ata_pio_poll(ap);
3621 break;
3622
14be71f4
AL		 3623 case HSM_ST_TMOUT:
3624 case HSM_ST_ERR:
1da177e4
LT		 3625 ata_pio_error(ap);
3626 return;
3627 }
3628
3629 if (timeout)
8061f5f0 3630 ata_port_queue_task(ap, ata_pio_task, ap, timeout);
7fb6ec28
JG		 3631 else if (!qc_completed)
3632 goto fsm_start;
1da177e4
LT		 3633}
3634
8061f5f0
TH		 3635/**
3636 * atapi_packet_task - Write CDB bytes to hardware
3637 * @_data: Port to which ATAPI device is attached.
3638 *
3639 * When device has indicated its readiness to accept
3640 * a CDB, this function is called. Send the CDB.
3641 * If DMA is to be performed, exit immediately.
3642 * Otherwise, we are in polling mode, so poll
3643 * status under operation succeeds or fails.
3644 *
3645 * LOCKING:
3646 * Kernel thread context (may sleep)
3647 */
3648
3649static void atapi_packet_task(void *_data)
3650{
3651 struct ata_port *ap = _data;
3652 struct ata_queued_cmd *qc;
3653 u8 status;
3654
3655 qc = ata_qc_from_tag(ap, ap->active_tag);
3656 WARN_ON(qc == NULL);
3657 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
3658
3659 /* sleep-wait for BSY to clear */
3660 DPRINTK("busy wait\n");
3661 if (ata_busy_sleep(ap, ATA_TMOUT_CDB_QUICK, ATA_TMOUT_CDB)) {
3662 qc->err_mask |= AC_ERR_TIMEOUT;
3663 goto err_out;
3664 }
3665
3666 /* make sure DRQ is set */
3667 status = ata_chk_status(ap);
3668 if ((status & (ATA_BUSY | ATA_DRQ)) != ATA_DRQ) {
3669 qc->err_mask |= AC_ERR_HSM;
3670 goto err_out;
3671 }
3672
3673 /* send SCSI cdb */
3674 DPRINTK("send cdb\n");
3675 WARN_ON(qc->dev->cdb_len < 12);
3676
3677 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA ||
3678 qc->tf.protocol == ATA_PROT_ATAPI_NODATA) {
3679 unsigned long flags;
3680
3681 /* Once we're done issuing command and kicking bmdma,
3682 * irq handler takes over. To not lose irq, we need
3683 * to clear NOINTR flag before sending cdb, but
3684 * interrupt handler shouldn't be invoked before we're
3685 * finished. Hence, the following locking.
3686 */
3687 spin_lock_irqsave(&ap->host_set->lock, flags);
3688 ap->flags &= ~ATA_FLAG_NOINTR;
3689 ata_data_xfer(ap, qc->cdb, qc->dev->cdb_len, 1);
3690 if (qc->tf.protocol == ATA_PROT_ATAPI_DMA)
3691 ap->ops->bmdma_start(qc); /* initiate bmdma */
3692 spin_unlock_irqrestore(&ap->host_set->lock, flags);
3693 } else {
3694 ata_data_xfer(ap, qc->cdb, qc->dev->cdb_len, 1);
3695
3696 /* PIO commands are handled by polling */
3697 ap->hsm_task_state = HSM_ST;
3698 ata_port_queue_task(ap, ata_pio_task, ap, 0);
3699 }
3700
3701 return;
3702
3703err_out:
3704 ata_poll_qc_complete(qc);
3705}
3706
1da177e4
LT		 3707/**
3708 * ata_qc_timeout - Handle timeout of queued command
3709 * @qc: Command that timed out
3710 *
3711 * Some part of the kernel (currently, only the SCSI layer)
3712 * has noticed that the active command on port @ap has not
3713 * completed after a specified length of time. Handle this
3714 * condition by disabling DMA (if necessary) and completing
3715 * transactions, with error if necessary.
3716 *
3717 * This also handles the case of the "lost interrupt", where
3718 * for some reason (possibly hardware bug, possibly driver bug)
3719 * an interrupt was not delivered to the driver, even though the
3720 * transaction completed successfully.
3721 *
3722 * LOCKING:
0cba632b 3723 * Inherited from SCSI layer (none, can sleep)
1da177e4
LT		 3724 */
3725
3726static void ata_qc_timeout(struct ata_queued_cmd *qc)
3727{
3728 struct ata_port *ap = qc->ap;
b8f6153e 3729 struct ata_host_set *host_set = ap->host_set;
1da177e4 3730 u8 host_stat = 0, drv_stat;
b8f6153e 3731 unsigned long flags;
1da177e4
LT		 3732
3733 DPRINTK("ENTER\n");
3734
c18d06f8
TH		 3735 ap->hsm_task_state = HSM_ST_IDLE;
3736
b8f6153e
JG		 3737 spin_lock_irqsave(&host_set->lock, flags);
3738
1da177e4
LT		 3739 switch (qc->tf.protocol) {
3740
3741 case ATA_PROT_DMA:
3742 case ATA_PROT_ATAPI_DMA:
3743 host_stat = ap->ops->bmdma_status(ap);
3744
3745 /* before we do anything else, clear DMA-Start bit */
b73fc89f 3746 ap->ops->bmdma_stop(qc);
1da177e4
LT		 3747
3748 /* fall through */
3749
3750 default:
3751 ata_altstatus(ap);
3752 drv_stat = ata_chk_status(ap);
3753
3754 /* ack bmdma irq events */
3755 ap->ops->irq_clear(ap);
3756
3757 printk(KERN_ERR "ata%u: command 0x%x timeout, stat 0x%x host_stat 0x%x\n",
3758 ap->id, qc->tf.command, drv_stat, host_stat);
3759
3760 /* complete taskfile transaction */
a22e2eb0 3761 qc->err_mask |= ac_err_mask(drv_stat);
1da177e4
LT		 3762 break;
3763 }
b8f6153e
JG		 3764
3765 spin_unlock_irqrestore(&host_set->lock, flags);
3766
a72ec4ce
TH		 3767 ata_eh_qc_complete(qc);
3768
1da177e4
LT		 3769 DPRINTK("EXIT\n");
3770}
3771
3772/**
3773 * ata_eng_timeout - Handle timeout of queued command
3774 * @ap: Port on which timed-out command is active
3775 *
3776 * Some part of the kernel (currently, only the SCSI layer)
3777 * has noticed that the active command on port @ap has not
3778 * completed after a specified length of time. Handle this
3779 * condition by disabling DMA (if necessary) and completing
3780 * transactions, with error if necessary.
3781 *
3782 * This also handles the case of the "lost interrupt", where
3783 * for some reason (possibly hardware bug, possibly driver bug)
3784 * an interrupt was not delivered to the driver, even though the
3785 * transaction completed successfully.
3786 *
3787 * LOCKING:
3788 * Inherited from SCSI layer (none, can sleep)
3789 */
3790
3791void ata_eng_timeout(struct ata_port *ap)
3792{
1da177e4
LT		 3793 DPRINTK("ENTER\n");
3794
f6379020 3795 ata_qc_timeout(ata_qc_from_tag(ap, ap->active_tag));
1da177e4 3796
1da177e4
LT		 3797 DPRINTK("EXIT\n");
3798}
3799
3800/**
3801 * ata_qc_new - Request an available ATA command, for queueing
3802 * @ap: Port associated with device @dev
3803 * @dev: Device from whom we request an available command structure
3804 *
3805 * LOCKING:
0cba632b 3806 * None.
1da177e4
LT		 3807 */
3808
3809static struct ata_queued_cmd *ata_qc_new(struct ata_port *ap)
3810{
3811 struct ata_queued_cmd *qc = NULL;
3812 unsigned int i;
3813
3814 for (i = 0; i < ATA_MAX_QUEUE; i++)
3815 if (!test_and_set_bit(i, &ap->qactive)) {
3816 qc = ata_qc_from_tag(ap, i);
3817 break;
3818 }
3819
3820 if (qc)
3821 qc->tag = i;
3822
3823 return qc;
3824}
3825
3826/**
3827 * ata_qc_new_init - Request an available ATA command, and initialize it
3828 * @ap: Port associated with device @dev
3829 * @dev: Device from whom we request an available command structure
3830 *
3831 * LOCKING:
0cba632b 3832 * None.
1da177e4
LT		 3833 */
3834
3835struct ata_queued_cmd *ata_qc_new_init(struct ata_port *ap,
3836 struct ata_device *dev)
3837{
3838 struct ata_queued_cmd *qc;
3839
3840 qc = ata_qc_new(ap);
3841 if (qc) {
1da177e4
LT		 3842 qc->scsicmd = NULL;
3843 qc->ap = ap;
3844 qc->dev = dev;
1da177e4 3845
2c13b7ce 3846 ata_qc_reinit(qc);
1da177e4
LT		 3847 }
3848
3849 return qc;
3850}
3851
1da177e4
LT		 3852/**
3853 * ata_qc_free - free unused ata_queued_cmd
3854 * @qc: Command to complete
3855 *
3856 * Designed to free unused ata_queued_cmd object
3857 * in case something prevents using it.
3858 *
3859 * LOCKING:
0cba632b 3860 * spin_lock_irqsave(host_set lock)
1da177e4
LT		 3861 */
3862void ata_qc_free(struct ata_queued_cmd *qc)
3863{
4ba946e9
TH		 3864 struct ata_port *ap = qc->ap;
3865 unsigned int tag;
3866
a4631474 3867 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
1da177e4 3868
4ba946e9
TH		 3869 qc->flags = 0;
3870 tag = qc->tag;
3871 if (likely(ata_tag_valid(tag))) {
3872 if (tag == ap->active_tag)
3873 ap->active_tag = ATA_TAG_POISON;
3874 qc->tag = ATA_TAG_POISON;
3875 clear_bit(tag, &ap->qactive);
3876 }
1da177e4
LT		 3877}
3878
76014427 3879void __ata_qc_complete(struct ata_queued_cmd *qc)
1da177e4 3880{
a4631474
TH		 3881 WARN_ON(qc == NULL); /* ata_qc_from_tag _might_ return NULL */
3882 WARN_ON(!(qc->flags & ATA_QCFLAG_ACTIVE));
1da177e4
LT		 3883
3884 if (likely(qc->flags & ATA_QCFLAG_DMAMAP))
3885 ata_sg_clean(qc);
3886
3f3791d3
AL		 3887 /* atapi: mark qc as inactive to prevent the interrupt handler
3888 * from completing the command twice later, before the error handler
3889 * is called. (when rc != 0 and atapi request sense is needed)
3890 */
3891 qc->flags &= ~ATA_QCFLAG_ACTIVE;
3892
1da177e4 3893 /* call completion callback */
77853bf2 3894 qc->complete_fn(qc);
1da177e4
LT		 3895}
3896
3897static inline int ata_should_dma_map(struct ata_queued_cmd *qc)
3898{
3899 struct ata_port *ap = qc->ap;
3900
3901 switch (qc->tf.protocol) {
3902 case ATA_PROT_DMA:
3903 case ATA_PROT_ATAPI_DMA:
3904 return 1;
3905
3906 case ATA_PROT_ATAPI:
3907 case ATA_PROT_PIO:
3908 case ATA_PROT_PIO_MULT:
3909 if (ap->flags & ATA_FLAG_PIO_DMA)
3910 return 1;
3911
3912 /* fall through */
3913
3914 default:
3915 return 0;
3916 }
3917
3918 /* never reached */
3919}
3920
3921/**
3922 * ata_qc_issue - issue taskfile to device
3923 * @qc: command to issue to device
3924 *
3925 * Prepare an ATA command to submission to device.
3926 * This includes mapping the data into a DMA-able
3927 * area, filling in the S/G table, and finally
3928 * writing the taskfile to hardware, starting the command.
3929 *
3930 * LOCKING:
3931 * spin_lock_irqsave(host_set lock)
3932 *
3933 * RETURNS:
9a3d9eb0 3934 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3935 */
3936
9a3d9eb0 3937unsigned int ata_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 3938{
3939 struct ata_port *ap = qc->ap;
3940
3941 if (ata_should_dma_map(qc)) {
3942 if (qc->flags & ATA_QCFLAG_SG) {
3943 if (ata_sg_setup(qc))
8e436af9 3944 goto sg_err;
1da177e4
LT		 3945 } else if (qc->flags & ATA_QCFLAG_SINGLE) {
3946 if (ata_sg_setup_one(qc))
8e436af9 3947 goto sg_err;
1da177e4
LT		 3948 }
3949 } else {
3950 qc->flags &= ~ATA_QCFLAG_DMAMAP;
3951 }
3952
3953 ap->ops->qc_prep(qc);
3954
3955 qc->ap->active_tag = qc->tag;
3956 qc->flags |= ATA_QCFLAG_ACTIVE;
3957
3958 return ap->ops->qc_issue(qc);
3959
8e436af9
TH		 3960sg_err:
3961 qc->flags &= ~ATA_QCFLAG_DMAMAP;
9a3d9eb0 3962 return AC_ERR_SYSTEM;
1da177e4
LT		 3963}
3964
0baab86b 3965
1da177e4
LT		 3966/**
3967 * ata_qc_issue_prot - issue taskfile to device in proto-dependent manner
3968 * @qc: command to issue to device
3969 *
3970 * Using various libata functions and hooks, this function
3971 * starts an ATA command. ATA commands are grouped into
3972 * classes called "protocols", and issuing each type of protocol
3973 * is slightly different.
3974 *
0baab86b
EF		 3975 * May be used as the qc_issue() entry in ata_port_operations.
3976 *
1da177e4
LT		 3977 * LOCKING:
3978 * spin_lock_irqsave(host_set lock)
3979 *
3980 * RETURNS:
9a3d9eb0 3981 * Zero on success, AC_ERR_* mask on failure
1da177e4
LT		 3982 */
3983
9a3d9eb0 3984unsigned int ata_qc_issue_prot(struct ata_queued_cmd *qc)
1da177e4
LT		 3985{
3986 struct ata_port *ap = qc->ap;
3987
3988 ata_dev_select(ap, qc->dev->devno, 1, 0);
3989
3990 switch (qc->tf.protocol) {
3991 case ATA_PROT_NODATA:
e5338254 3992 ata_tf_to_host(ap, &qc->tf);
1da177e4
LT		 3993 break;
3994
3995 case ATA_PROT_DMA:
3996 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
3997 ap->ops->bmdma_setup(qc); /* set up bmdma */
3998 ap->ops->bmdma_start(qc); /* initiate bmdma */
3999 break;
4000
4001 case ATA_PROT_PIO: /* load tf registers, initiate polling pio */
4002 ata_qc_set_polling(qc);
e5338254 4003 ata_tf_to_host(ap, &qc->tf);
14be71f4 4004 ap->hsm_task_state = HSM_ST;
8061f5f0 4005 ata_port_queue_task(ap, ata_pio_task, ap, 0);
1da177e4
LT		 4006 break;
4007
4008 case ATA_PROT_ATAPI:
4009 ata_qc_set_polling(qc);
e5338254 4010 ata_tf_to_host(ap, &qc->tf);
8061f5f0 4011 ata_port_queue_task(ap, atapi_packet_task, ap, 0);
1da177e4
LT		 4012 break;
4013
4014 case ATA_PROT_ATAPI_NODATA:
c1389503 4015 ap->flags |= ATA_FLAG_NOINTR;
e5338254 4016 ata_tf_to_host(ap, &qc->tf);
8061f5f0 4017 ata_port_queue_task(ap, atapi_packet_task, ap, 0);
1da177e4
LT		 4018 break;
4019
4020 case ATA_PROT_ATAPI_DMA:
c1389503 4021 ap->flags |= ATA_FLAG_NOINTR;
1da177e4
LT		 4022 ap->ops->tf_load(ap, &qc->tf); /* load tf registers */
4023 ap->ops->bmdma_setup(qc); /* set up bmdma */
8061f5f0 4024 ata_port_queue_task(ap, atapi_packet_task, ap, 0);
1da177e4
LT		 4025 break;
4026
4027 default:
4028 WARN_ON(1);
9a3d9eb0 4029 return AC_ERR_SYSTEM;
1da177e4
LT		 4030 }
4031
4032 return 0;
4033}
4034
4035/**
0baab86b 4036 * ata_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction
1da177e4
LT		 4037 * @qc: Info associated with this ATA transaction.
4038 *
4039 * LOCKING:
4040 * spin_lock_irqsave(host_set lock)
4041 */
4042
4043static void ata_bmdma_setup_mmio (struct ata_queued_cmd *qc)
4044{
4045 struct ata_port *ap = qc->ap;
4046 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4047 u8 dmactl;
4048 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4049
4050 /* load PRD table addr. */
4051 mb(); /* make sure PRD table writes are visible to controller */
4052 writel(ap->prd_dma, mmio + ATA_DMA_TABLE_OFS);
4053
4054 /* specify data direction, triple-check start bit is clear */
4055 dmactl = readb(mmio + ATA_DMA_CMD);
4056 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4057 if (!rw)
4058 dmactl |= ATA_DMA_WR;
4059 writeb(dmactl, mmio + ATA_DMA_CMD);
4060
4061 /* issue r/w command */
4062 ap->ops->exec_command(ap, &qc->tf);
4063}
4064
4065/**
b73fc89f 4066 * ata_bmdma_start_mmio - Start a PCI IDE BMDMA transaction
1da177e4
LT		 4067 * @qc: Info associated with this ATA transaction.
4068 *
4069 * LOCKING:
4070 * spin_lock_irqsave(host_set lock)
4071 */
4072
4073static void ata_bmdma_start_mmio (struct ata_queued_cmd *qc)
4074{
4075 struct ata_port *ap = qc->ap;
4076 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4077 u8 dmactl;
4078
4079 /* start host DMA transaction */
4080 dmactl = readb(mmio + ATA_DMA_CMD);
4081 writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
4082
4083 /* Strictly, one may wish to issue a readb() here, to
4084 * flush the mmio write. However, control also passes
4085 * to the hardware at this point, and it will interrupt
4086 * us when we are to resume control. So, in effect,
4087 * we don't care when the mmio write flushes.
4088 * Further, a read of the DMA status register _immediately_
4089 * following the write may not be what certain flaky hardware
4090 * is expected, so I think it is best to not add a readb()
4091 * without first all the MMIO ATA cards/mobos.
4092 * Or maybe I'm just being paranoid.
4093 */
4094}
4095
4096/**
4097 * ata_bmdma_setup_pio - Set up PCI IDE BMDMA transaction (PIO)
4098 * @qc: Info associated with this ATA transaction.
4099 *
4100 * LOCKING:
4101 * spin_lock_irqsave(host_set lock)
4102 */
4103
4104static void ata_bmdma_setup_pio (struct ata_queued_cmd *qc)
4105{
4106 struct ata_port *ap = qc->ap;
4107 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
4108 u8 dmactl;
4109
4110 /* load PRD table addr. */
4111 outl(ap->prd_dma, ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
4112
4113 /* specify data direction, triple-check start bit is clear */
4114 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4115 dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
4116 if (!rw)
4117 dmactl |= ATA_DMA_WR;
4118 outb(dmactl, ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4119
4120 /* issue r/w command */
4121 ap->ops->exec_command(ap, &qc->tf);
4122}
4123
4124/**
4125 * ata_bmdma_start_pio - Start a PCI IDE BMDMA transaction (PIO)
4126 * @qc: Info associated with this ATA transaction.
4127 *
4128 * LOCKING:
4129 * spin_lock_irqsave(host_set lock)
4130 */
4131
4132static void ata_bmdma_start_pio (struct ata_queued_cmd *qc)
4133{
4134 struct ata_port *ap = qc->ap;
4135 u8 dmactl;
4136
4137 /* start host DMA transaction */
4138 dmactl = inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4139 outb(dmactl | ATA_DMA_START,
4140 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4141}
4142
0baab86b
EF		 4143
4144/**
4145 * ata_bmdma_start - Start a PCI IDE BMDMA transaction
4146 * @qc: Info associated with this ATA transaction.
4147 *
4148 * Writes the ATA_DMA_START flag to the DMA command register.
4149 *
4150 * May be used as the bmdma_start() entry in ata_port_operations.
4151 *
4152 * LOCKING:
4153 * spin_lock_irqsave(host_set lock)
4154 */
1da177e4
LT		 4155void ata_bmdma_start(struct ata_queued_cmd *qc)
4156{
4157 if (qc->ap->flags & ATA_FLAG_MMIO)
4158 ata_bmdma_start_mmio(qc);
4159 else
4160 ata_bmdma_start_pio(qc);
4161}
4162
0baab86b
EF		 4163
4164/**
4165 * ata_bmdma_setup - Set up PCI IDE BMDMA transaction
4166 * @qc: Info associated with this ATA transaction.
4167 *
4168 * Writes address of PRD table to device's PRD Table Address
4169 * register, sets the DMA control register, and calls
4170 * ops->exec_command() to start the transfer.
4171 *
4172 * May be used as the bmdma_setup() entry in ata_port_operations.
4173 *
4174 * LOCKING:
4175 * spin_lock_irqsave(host_set lock)
4176 */
1da177e4
LT		 4177void ata_bmdma_setup(struct ata_queued_cmd *qc)
4178{
4179 if (qc->ap->flags & ATA_FLAG_MMIO)
4180 ata_bmdma_setup_mmio(qc);
4181 else
4182 ata_bmdma_setup_pio(qc);
4183}
4184
0baab86b
EF		 4185
4186/**
4187 * ata_bmdma_irq_clear - Clear PCI IDE BMDMA interrupt.
decc6d0b 4188 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 4189 *
4190 * Clear interrupt and error flags in DMA status register.
4191 *
4192 * May be used as the irq_clear() entry in ata_port_operations.
4193 *
4194 * LOCKING:
4195 * spin_lock_irqsave(host_set lock)
4196 */
4197
1da177e4
LT		 4198void ata_bmdma_irq_clear(struct ata_port *ap)
4199{
4200 if (ap->flags & ATA_FLAG_MMIO) {
4201 void __iomem *mmio = ((void __iomem *) ap->ioaddr.bmdma_addr) + ATA_DMA_STATUS;
4202 writeb(readb(mmio), mmio);
4203 } else {
4204 unsigned long addr = ap->ioaddr.bmdma_addr + ATA_DMA_STATUS;
4205 outb(inb(addr), addr);
4206 }
4207
4208}
4209
0baab86b
EF		 4210
4211/**
4212 * ata_bmdma_status - Read PCI IDE BMDMA status
decc6d0b 4213 * @ap: Port associated with this ATA transaction.
0baab86b
EF		 4214 *
4215 * Read and return BMDMA status register.
4216 *
4217 * May be used as the bmdma_status() entry in ata_port_operations.
4218 *
4219 * LOCKING:
4220 * spin_lock_irqsave(host_set lock)
4221 */
4222
1da177e4
LT		 4223u8 ata_bmdma_status(struct ata_port *ap)
4224{
4225 u8 host_stat;
4226 if (ap->flags & ATA_FLAG_MMIO) {
4227 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4228 host_stat = readb(mmio + ATA_DMA_STATUS);
4229 } else
ee500aab 4230 host_stat = inb(ap->ioaddr.bmdma_addr + ATA_DMA_STATUS);
1da177e4
LT		 4231 return host_stat;
4232}
4233
0baab86b
EF		 4234
4235/**
4236 * ata_bmdma_stop - Stop PCI IDE BMDMA transfer
b73fc89f 4237 * @qc: Command we are ending DMA for
0baab86b
EF		 4238 *
4239 * Clears the ATA_DMA_START flag in the dma control register
4240 *
4241 * May be used as the bmdma_stop() entry in ata_port_operations.
4242 *
4243 * LOCKING:
4244 * spin_lock_irqsave(host_set lock)
4245 */
4246
b73fc89f 4247void ata_bmdma_stop(struct ata_queued_cmd *qc)
1da177e4 4248{
b73fc89f 4249 struct ata_port *ap = qc->ap;
1da177e4
LT		 4250 if (ap->flags & ATA_FLAG_MMIO) {
4251 void __iomem *mmio = (void __iomem *) ap->ioaddr.bmdma_addr;
4252
4253 /* clear start/stop bit */
4254 writeb(readb(mmio + ATA_DMA_CMD) & ~ATA_DMA_START,
4255 mmio + ATA_DMA_CMD);
4256 } else {
4257 /* clear start/stop bit */
4258 outb(inb(ap->ioaddr.bmdma_addr + ATA_DMA_CMD) & ~ATA_DMA_START,
4259 ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
4260 }
4261
4262 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
4263 ata_altstatus(ap); /* dummy read */
4264}
4265
4266/**
4267 * ata_host_intr - Handle host interrupt for given (port, task)
4268 * @ap: Port on which interrupt arrived (possibly...)
4269 * @qc: Taskfile currently active in engine
4270 *
4271 * Handle host interrupt for given queued command. Currently,
4272 * only DMA interrupts are handled. All other commands are
4273 * handled via polling with interrupts disabled (nIEN bit).
4274 *
4275 * LOCKING:
4276 * spin_lock_irqsave(host_set lock)
4277 *
4278 * RETURNS:
4279 * One if interrupt was handled, zero if not (shared irq).
4280 */
4281
4282inline unsigned int ata_host_intr (struct ata_port *ap,
4283 struct ata_queued_cmd *qc)
4284{
4285 u8 status, host_stat;
4286
4287 switch (qc->tf.protocol) {
4288
4289 case ATA_PROT_DMA:
4290 case ATA_PROT_ATAPI_DMA:
4291 case ATA_PROT_ATAPI:
4292 /* check status of DMA engine */
4293 host_stat = ap->ops->bmdma_status(ap);
4294 VPRINTK("ata%u: host_stat 0x%X\n", ap->id, host_stat);
4295
4296 /* if it's not our irq... */
4297 if (!(host_stat & ATA_DMA_INTR))
4298 goto idle_irq;
4299
4300 /* before we do anything else, clear DMA-Start bit */
b73fc89f 4301 ap->ops->bmdma_stop(qc);
1da177e4
LT		 4302
4303 /* fall through */
4304
4305 case ATA_PROT_ATAPI_NODATA:
4306 case ATA_PROT_NODATA:
4307 /* check altstatus */
4308 status = ata_altstatus(ap);
4309 if (status & ATA_BUSY)
4310 goto idle_irq;
4311
4312 /* check main status, clearing INTRQ */
4313 status = ata_chk_status(ap);
4314 if (unlikely(status & ATA_BUSY))
4315 goto idle_irq;
4316 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
4317 ap->id, qc->tf.protocol, status);
4318
4319 /* ack bmdma irq events */
4320 ap->ops->irq_clear(ap);
4321
4322 /* complete taskfile transaction */
a22e2eb0
AL		 4323 qc->err_mask |= ac_err_mask(status);
4324 ata_qc_complete(qc);
1da177e4
LT		 4325 break;
4326
4327 default:
4328 goto idle_irq;
4329 }
4330
4331 return 1; /* irq handled */
4332
4333idle_irq:
4334 ap->stats.idle_irq++;
4335
4336#ifdef ATA_IRQ_TRAP
4337 if ((ap->stats.idle_irq % 1000) == 0) {
4338 handled = 1;
4339 ata_irq_ack(ap, 0); /* debug trap */
4340 printk(KERN_WARNING "ata%d: irq trap\n", ap->id);
4341 }
4342#endif
4343 return 0; /* irq not handled */
4344}
4345
4346/**
4347 * ata_interrupt - Default ATA host interrupt handler
0cba632b
JG		 4348 * @irq: irq line (unused)
4349 * @dev_instance: pointer to our ata_host_set information structure
1da177e4
LT		 4350 * @regs: unused
4351 *
0cba632b
JG		 4352 * Default interrupt handler for PCI IDE devices. Calls
4353 * ata_host_intr() for each port that is not disabled.
4354 *
1da177e4 4355 * LOCKING:
0cba632b 4356 * Obtains host_set lock during operation.
1da177e4
LT		 4357 *
4358 * RETURNS:
0cba632b 4359 * IRQ_NONE or IRQ_HANDLED.
1da177e4
LT		 4360 */
4361
4362irqreturn_t ata_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
4363{
4364 struct ata_host_set *host_set = dev_instance;
4365 unsigned int i;
4366 unsigned int handled = 0;
4367 unsigned long flags;
4368
4369 /* TODO: make _irqsave conditional on x86 PCI IDE legacy mode */
4370 spin_lock_irqsave(&host_set->lock, flags);
4371
4372 for (i = 0; i < host_set->n_ports; i++) {
4373 struct ata_port *ap;
4374
4375 ap = host_set->ports[i];
c1389503
TH		 4376 if (ap &&
4377 !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
1da177e4
LT		 4378 struct ata_queued_cmd *qc;
4379
4380 qc = ata_qc_from_tag(ap, ap->active_tag);
21b1ed74
AL		 4381 if (qc && (!(qc->tf.ctl & ATA_NIEN)) &&
4382 (qc->flags & ATA_QCFLAG_ACTIVE))
1da177e4
LT		 4383 handled |= ata_host_intr(ap, qc);
4384 }
4385 }
4386
4387 spin_unlock_irqrestore(&host_set->lock, flags);
4388
4389 return IRQ_RETVAL(handled);
4390}
4391
0baab86b 4392
9b847548
JA		 4393/*
4394 * Execute a 'simple' command, that only consists of the opcode 'cmd' itself,
4395 * without filling any other registers
4396 */
4397static int ata_do_simple_cmd(struct ata_port *ap, struct ata_device *dev,
4398 u8 cmd)
4399{
4400 struct ata_taskfile tf;
4401 int err;
4402
4403 ata_tf_init(ap, &tf, dev->devno);
4404
4405 tf.command = cmd;
4406 tf.flags |= ATA_TFLAG_DEVICE;
4407 tf.protocol = ATA_PROT_NODATA;
4408
4409 err = ata_exec_internal(ap, dev, &tf, DMA_NONE, NULL, 0);
4410 if (err)
4411 printk(KERN_ERR "%s: ata command failed: %d\n",
4412 __FUNCTION__, err);
4413
4414 return err;
4415}
4416
4417static int ata_flush_cache(struct ata_port *ap, struct ata_device *dev)
4418{
4419 u8 cmd;
4420
4421 if (!ata_try_flush_cache(dev))
4422 return 0;
4423
4424 if (ata_id_has_flush_ext(dev->id))
4425 cmd = ATA_CMD_FLUSH_EXT;
4426 else
4427 cmd = ATA_CMD_FLUSH;
4428
4429 return ata_do_simple_cmd(ap, dev, cmd);
4430}
4431
4432static int ata_standby_drive(struct ata_port *ap, struct ata_device *dev)
4433{
4434 return ata_do_simple_cmd(ap, dev, ATA_CMD_STANDBYNOW1);
4435}
4436
4437static int ata_start_drive(struct ata_port *ap, struct ata_device *dev)
4438{
4439 return ata_do_simple_cmd(ap, dev, ATA_CMD_IDLEIMMEDIATE);
4440}
4441
4442/**
4443 * ata_device_resume - wakeup a previously suspended devices
c893a3ae
RD		 4444 * @ap: port the device is connected to
4445 * @dev: the device to resume
9b847548
JA		 4446 *
4447 * Kick the drive back into action, by sending it an idle immediate
4448 * command and making sure its transfer mode matches between drive
4449 * and host.
4450 *
4451 */
4452int ata_device_resume(struct ata_port *ap, struct ata_device *dev)
4453{
4454 if (ap->flags & ATA_FLAG_SUSPENDED) {
4455 ap->flags &= ~ATA_FLAG_SUSPENDED;
4456 ata_set_mode(ap);
4457 }
4458 if (!ata_dev_present(dev))
4459 return 0;
4460 if (dev->class == ATA_DEV_ATA)
4461 ata_start_drive(ap, dev);
4462
4463 return 0;
4464}
4465
4466/**
4467 * ata_device_suspend - prepare a device for suspend
c893a3ae
RD		 4468 * @ap: port the device is connected to
4469 * @dev: the device to suspend
9b847548
JA		 4470 *
4471 * Flush the cache on the drive, if appropriate, then issue a
4472 * standbynow command.
9b847548
JA		 4473 */
4474int ata_device_suspend(struct ata_port *ap, struct ata_device *dev)
4475{
4476 if (!ata_dev_present(dev))
4477 return 0;
4478 if (dev->class == ATA_DEV_ATA)
4479 ata_flush_cache(ap, dev);
4480
4481 ata_standby_drive(ap, dev);
4482 ap->flags |= ATA_FLAG_SUSPENDED;
4483 return 0;
4484}
4485
c893a3ae
RD		 4486/**
4487 * ata_port_start - Set port up for dma.
4488 * @ap: Port to initialize
4489 *
4490 * Called just after data structures for each port are
4491 * initialized. Allocates space for PRD table.
4492 *
4493 * May be used as the port_start() entry in ata_port_operations.
4494 *
4495 * LOCKING:
4496 * Inherited from caller.
4497 */
4498
1da177e4
LT		 4499int ata_port_start (struct ata_port *ap)
4500{
4501 struct device *dev = ap->host_set->dev;
6037d6bb 4502 int rc;
1da177e4
LT		 4503
4504 ap->prd = dma_alloc_coherent(dev, ATA_PRD_TBL_SZ, &ap->prd_dma, GFP_KERNEL);
4505 if (!ap->prd)
4506 return -ENOMEM;
4507
6037d6bb
JG		 4508 rc = ata_pad_alloc(ap, dev);
4509 if (rc) {
cedc9a47 4510 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4511 return rc;
cedc9a47
JG		 4512 }
4513
1da177e4
LT		 4514 DPRINTK("prd alloc, virt %p, dma %llx\n", ap->prd, (unsigned long long) ap->prd_dma);
4515
4516 return 0;
4517}
4518
0baab86b
EF		 4519
4520/**
4521 * ata_port_stop - Undo ata_port_start()
4522 * @ap: Port to shut down
4523 *
4524 * Frees the PRD table.
4525 *
4526 * May be used as the port_stop() entry in ata_port_operations.
4527 *
4528 * LOCKING:
6f0ef4fa 4529 * Inherited from caller.
0baab86b
EF		 4530 */
4531
1da177e4
LT		 4532void ata_port_stop (struct ata_port *ap)
4533{
4534 struct device *dev = ap->host_set->dev;
4535
4536 dma_free_coherent(dev, ATA_PRD_TBL_SZ, ap->prd, ap->prd_dma);
6037d6bb 4537 ata_pad_free(ap, dev);
1da177e4
LT		 4538}
4539
aa8f0dc6
JG		 4540void ata_host_stop (struct ata_host_set *host_set)
4541{
4542 if (host_set->mmio_base)
4543 iounmap(host_set->mmio_base);
4544}
4545
4546
1da177e4
LT		 4547/**
4548 * ata_host_remove - Unregister SCSI host structure with upper layers
4549 * @ap: Port to unregister
4550 * @do_unregister: 1 if we fully unregister, 0 to just stop the port
4551 *
4552 * LOCKING:
6f0ef4fa 4553 * Inherited from caller.
1da177e4
LT		 4554 */
4555
4556static void ata_host_remove(struct ata_port *ap, unsigned int do_unregister)
4557{
4558 struct Scsi_Host *sh = ap->host;
4559
4560 DPRINTK("ENTER\n");
4561
4562 if (do_unregister)
4563 scsi_remove_host(sh);
4564
4565 ap->ops->port_stop(ap);
4566}
4567
4568/**
4569 * ata_host_init - Initialize an ata_port structure
4570 * @ap: Structure to initialize
4571 * @host: associated SCSI mid-layer structure
4572 * @host_set: Collection of hosts to which @ap belongs
4573 * @ent: Probe information provided by low-level driver
4574 * @port_no: Port number associated with this ata_port
4575 *
0cba632b
JG		 4576 * Initialize a new ata_port structure, and its associated
4577 * scsi_host.
4578 *
1da177e4 4579 * LOCKING:
0cba632b 4580 * Inherited from caller.
1da177e4
LT		 4581 */
4582
4583static void ata_host_init(struct ata_port *ap, struct Scsi_Host *host,
4584 struct ata_host_set *host_set,
057ace5e 4585 const struct ata_probe_ent *ent, unsigned int port_no)
1da177e4
LT		 4586{
4587 unsigned int i;
4588
4589 host->max_id = 16;
4590 host->max_lun = 1;
4591 host->max_channel = 1;
4592 host->unique_id = ata_unique_id++;
4593 host->max_cmd_len = 12;
12413197 4594
1da177e4
LT		 4595 ap->flags = ATA_FLAG_PORT_DISABLED;
4596 ap->id = host->unique_id;
4597 ap->host = host;
4598 ap->ctl = ATA_DEVCTL_OBS;
4599 ap->host_set = host_set;
4600 ap->port_no = port_no;
4601 ap->hard_port_no =
4602 ent->legacy_mode ? ent->hard_port_no : port_no;
4603 ap->pio_mask = ent->pio_mask;
4604 ap->mwdma_mask = ent->mwdma_mask;
4605 ap->udma_mask = ent->udma_mask;
4606 ap->flags |= ent->host_flags;
4607 ap->ops = ent->port_ops;
4608 ap->cbl = ATA_CBL_NONE;
4609 ap->active_tag = ATA_TAG_POISON;
4610 ap->last_ctl = 0xFF;
4611
86e45b6b 4612 INIT_WORK(&ap->port_task, NULL, NULL);
a72ec4ce 4613 INIT_LIST_HEAD(&ap->eh_done_q);
1da177e4
LT		 4614
4615 for (i = 0; i < ATA_MAX_DEVICES; i++)
4616 ap->device[i].devno = i;
4617
4618#ifdef ATA_IRQ_TRAP
4619 ap->stats.unhandled_irq = 1;
4620 ap->stats.idle_irq = 1;
4621#endif
4622
4623 memcpy(&ap->ioaddr, &ent->port[port_no], sizeof(struct ata_ioports));
4624}
4625
4626/**
4627 * ata_host_add - Attach low-level ATA driver to system
4628 * @ent: Information provided by low-level driver
4629 * @host_set: Collections of ports to which we add
4630 * @port_no: Port number associated with this host
4631 *
0cba632b
JG		 4632 * Attach low-level ATA driver to system.
4633 *
1da177e4 4634 * LOCKING:
0cba632b 4635 * PCI/etc. bus probe sem.
1da177e4
LT		 4636 *
4637 * RETURNS:
0cba632b 4638 * New ata_port on success, for NULL on error.
1da177e4
LT		 4639 */
4640
057ace5e 4641static struct ata_port * ata_host_add(const struct ata_probe_ent *ent,
1da177e4
LT		 4642 struct ata_host_set *host_set,
4643 unsigned int port_no)
4644{
4645 struct Scsi_Host *host;
4646 struct ata_port *ap;
4647 int rc;
4648
4649 DPRINTK("ENTER\n");
4650 host = scsi_host_alloc(ent->sht, sizeof(struct ata_port));
4651 if (!host)
4652 return NULL;
4653
4654 ap = (struct ata_port *) &host->hostdata[0];
4655
4656 ata_host_init(ap, host, host_set, ent, port_no);
4657
4658 rc = ap->ops->port_start(ap);
4659 if (rc)
4660 goto err_out;
4661
4662 return ap;
4663
4664err_out:
4665 scsi_host_put(host);
4666 return NULL;
4667}
4668
4669/**
0cba632b
JG		 4670 * ata_device_add - Register hardware device with ATA and SCSI layers
4671 * @ent: Probe information describing hardware device to be registered
4672 *
4673 * This function processes the information provided in the probe
4674 * information struct @ent, allocates the necessary ATA and SCSI
4675 * host information structures, initializes them, and registers
4676 * everything with requisite kernel subsystems.
4677 *
4678 * This function requests irqs, probes the ATA bus, and probes
4679 * the SCSI bus.
1da177e4
LT		 4680 *
4681 * LOCKING:
0cba632b 4682 * PCI/etc. bus probe sem.
1da177e4
LT		 4683 *
4684 * RETURNS:
0cba632b 4685 * Number of ports registered. Zero on error (no ports registered).
1da177e4
LT		 4686 */
4687
057ace5e 4688int ata_device_add(const struct ata_probe_ent *ent)
1da177e4
LT		 4689{
4690 unsigned int count = 0, i;
4691 struct device *dev = ent->dev;
4692 struct ata_host_set *host_set;
4693
4694 DPRINTK("ENTER\n");
4695 /* alloc a container for our list of ATA ports (buses) */
57f3bda8 4696 host_set = kzalloc(sizeof(struct ata_host_set) +
1da177e4
LT		 4697 (ent->n_ports * sizeof(void *)), GFP_KERNEL);
4698 if (!host_set)
4699 return 0;
1da177e4
LT		 4700 spin_lock_init(&host_set->lock);
4701
4702 host_set->dev = dev;
4703 host_set->n_ports = ent->n_ports;
4704 host_set->irq = ent->irq;
4705 host_set->mmio_base = ent->mmio_base;
4706 host_set->private_data = ent->private_data;
4707 host_set->ops = ent->port_ops;
4708
4709 /* register each port bound to this device */
4710 for (i = 0; i < ent->n_ports; i++) {
4711 struct ata_port *ap;
4712 unsigned long xfer_mode_mask;
4713
4714 ap = ata_host_add(ent, host_set, i);
4715 if (!ap)
4716 goto err_out;
4717
4718 host_set->ports[i] = ap;
4719 xfer_mode_mask =(ap->udma_mask << ATA_SHIFT_UDMA) |
4720 (ap->mwdma_mask << ATA_SHIFT_MWDMA) |
4721 (ap->pio_mask << ATA_SHIFT_PIO);
4722
4723 /* print per-port info to dmesg */
4724 printk(KERN_INFO "ata%u: %cATA max %s cmd 0x%lX ctl 0x%lX "
4725 "bmdma 0x%lX irq %lu\n",
4726 ap->id,
4727 ap->flags & ATA_FLAG_SATA ? 'S' : 'P',
4728 ata_mode_string(xfer_mode_mask),
4729 ap->ioaddr.cmd_addr,
4730 ap->ioaddr.ctl_addr,
4731 ap->ioaddr.bmdma_addr,
4732 ent->irq);
4733
4734 ata_chk_status(ap);
4735 host_set->ops->irq_clear(ap);
4736 count++;
4737 }
4738
57f3bda8
RD		 4739 if (!count)
4740 goto err_free_ret;
1da177e4
LT		 4741
4742 /* obtain irq, that is shared between channels */
4743 if (request_irq(ent->irq, ent->port_ops->irq_handler, ent->irq_flags,
4744 DRV_NAME, host_set))
4745 goto err_out;
4746
4747 /* perform each probe synchronously */
4748 DPRINTK("probe begin\n");
4749 for (i = 0; i < count; i++) {
4750 struct ata_port *ap;
4751 int rc;
4752
4753 ap = host_set->ports[i];
4754
c893a3ae 4755 DPRINTK("ata%u: bus probe begin\n", ap->id);
1da177e4 4756 rc = ata_bus_probe(ap);
c893a3ae 4757 DPRINTK("ata%u: bus probe end\n", ap->id);
1da177e4
LT		 4758
4759 if (rc) {
4760 /* FIXME: do something useful here?
4761 * Current libata behavior will
4762 * tear down everything when
4763 * the module is removed
4764 * or the h/w is unplugged.
4765 */
4766 }
4767
4768 rc = scsi_add_host(ap->host, dev);
4769 if (rc) {
4770 printk(KERN_ERR "ata%u: scsi_add_host failed\n",
4771 ap->id);
4772 /* FIXME: do something useful here */
4773 /* FIXME: handle unconditional calls to
4774 * scsi_scan_host and ata_host_remove, below,
4775 * at the very least
4776 */
4777 }
4778 }
4779
4780 /* probes are done, now scan each port's disk(s) */
c893a3ae 4781 DPRINTK("host probe begin\n");
1da177e4
LT		 4782 for (i = 0; i < count; i++) {
4783 struct ata_port *ap = host_set->ports[i];
4784
644dd0cc 4785 ata_scsi_scan_host(ap);
1da177e4
LT		 4786 }
4787
4788 dev_set_drvdata(dev, host_set);
4789
4790 VPRINTK("EXIT, returning %u\n", ent->n_ports);
4791 return ent->n_ports; /* success */
4792
4793err_out:
4794 for (i = 0; i < count; i++) {
4795 ata_host_remove(host_set->ports[i], 1);
4796 scsi_host_put(host_set->ports[i]->host);
4797 }
57f3bda8 4798err_free_ret:
1da177e4
LT		 4799 kfree(host_set);
4800 VPRINTK("EXIT, returning 0\n");
4801 return 0;
4802}
4803
17b14451
AC		 4804/**
4805 * ata_host_set_remove - PCI layer callback for device removal
4806 * @host_set: ATA host set that was removed
4807 *
4808 * Unregister all objects associated with this host set. Free those
4809 * objects.
4810 *
4811 * LOCKING:
4812 * Inherited from calling layer (may sleep).
4813 */
4814
17b14451
AC		 4815void ata_host_set_remove(struct ata_host_set *host_set)
4816{
4817 struct ata_port *ap;
4818 unsigned int i;
4819
4820 for (i = 0; i < host_set->n_ports; i++) {
4821 ap = host_set->ports[i];
4822 scsi_remove_host(ap->host);
4823 }
4824
4825 free_irq(host_set->irq, host_set);
4826
4827 for (i = 0; i < host_set->n_ports; i++) {
4828 ap = host_set->ports[i];
4829
4830 ata_scsi_release(ap->host);
4831
4832 if ((ap->flags & ATA_FLAG_NO_LEGACY) == 0) {
4833 struct ata_ioports *ioaddr = &ap->ioaddr;
4834
4835 if (ioaddr->cmd_addr == 0x1f0)
4836 release_region(0x1f0, 8);
4837 else if (ioaddr->cmd_addr == 0x170)
4838 release_region(0x170, 8);
4839 }
4840
4841 scsi_host_put(ap->host);
4842 }
4843
4844 if (host_set->ops->host_stop)
4845 host_set->ops->host_stop(host_set);
4846
4847 kfree(host_set);
4848}
4849
1da177e4
LT		 4850/**
4851 * ata_scsi_release - SCSI layer callback hook for host unload
4852 * @host: libata host to be unloaded
4853 *
4854 * Performs all duties necessary to shut down a libata port...
4855 * Kill port kthread, disable port, and release resources.
4856 *
4857 * LOCKING:
4858 * Inherited from SCSI layer.
4859 *
4860 * RETURNS:
4861 * One.
4862 */
4863
4864int ata_scsi_release(struct Scsi_Host *host)
4865{
4866 struct ata_port *ap = (struct ata_port *) &host->hostdata[0];
d9572b1d 4867 int i;
1da177e4
LT		 4868
4869 DPRINTK("ENTER\n");
4870
4871 ap->ops->port_disable(ap);
4872 ata_host_remove(ap, 0);
d9572b1d
TH		 4873 for (i = 0; i < ATA_MAX_DEVICES; i++)
4874 kfree(ap->device[i].id);
1da177e4
LT		 4875
4876 DPRINTK("EXIT\n");
4877 return 1;
4878}
4879
4880/**
4881 * ata_std_ports - initialize ioaddr with standard port offsets.
4882 * @ioaddr: IO address structure to be initialized
0baab86b
EF		 4883 *
4884 * Utility function which initializes data_addr, error_addr,
4885 * feature_addr, nsect_addr, lbal_addr, lbam_addr, lbah_addr,
4886 * device_addr, status_addr, and command_addr to standard offsets
4887 * relative to cmd_addr.
4888 *
4889 * Does not set ctl_addr, altstatus_addr, bmdma_addr, or scr_addr.
1da177e4 4890 */
0baab86b 4891
1da177e4
LT		 4892void ata_std_ports(struct ata_ioports *ioaddr)
4893{
4894 ioaddr->data_addr = ioaddr->cmd_addr + ATA_REG_DATA;
4895 ioaddr->error_addr = ioaddr->cmd_addr + ATA_REG_ERR;
4896 ioaddr->feature_addr = ioaddr->cmd_addr + ATA_REG_FEATURE;
4897 ioaddr->nsect_addr = ioaddr->cmd_addr + ATA_REG_NSECT;
4898 ioaddr->lbal_addr = ioaddr->cmd_addr + ATA_REG_LBAL;
4899 ioaddr->lbam_addr = ioaddr->cmd_addr + ATA_REG_LBAM;
4900 ioaddr->lbah_addr = ioaddr->cmd_addr + ATA_REG_LBAH;
4901 ioaddr->device_addr = ioaddr->cmd_addr + ATA_REG_DEVICE;
4902 ioaddr->status_addr = ioaddr->cmd_addr + ATA_REG_STATUS;
4903 ioaddr->command_addr = ioaddr->cmd_addr + ATA_REG_CMD;
4904}
4905
0baab86b 4906
374b1873
JG		 4907#ifdef CONFIG_PCI
4908
4909void ata_pci_host_stop (struct ata_host_set *host_set)
4910{
4911 struct pci_dev *pdev = to_pci_dev(host_set->dev);
4912
4913 pci_iounmap(pdev, host_set->mmio_base);
4914}
4915
1da177e4
LT		 4916/**
4917 * ata_pci_remove_one - PCI layer callback for device removal
4918 * @pdev: PCI device that was removed
4919 *
4920 * PCI layer indicates to libata via this hook that
6f0ef4fa 4921 * hot-unplug or module unload event has occurred.
1da177e4
LT		 4922 * Handle this by unregistering all objects associated
4923 * with this PCI device. Free those objects. Then finally
4924 * release PCI resources and disable device.
4925 *
4926 * LOCKING:
4927 * Inherited from PCI layer (may sleep).
4928 */
4929
4930void ata_pci_remove_one (struct pci_dev *pdev)
4931{
4932 struct device *dev = pci_dev_to_dev(pdev);
4933 struct ata_host_set *host_set = dev_get_drvdata(dev);
1da177e4 4934
17b14451 4935 ata_host_set_remove(host_set);
1da177e4
LT		 4936 pci_release_regions(pdev);
4937 pci_disable_device(pdev);
4938 dev_set_drvdata(dev, NULL);
4939}
4940
4941/* move to PCI subsystem */
057ace5e 4942int pci_test_config_bits(struct pci_dev *pdev, const struct pci_bits *bits)
1da177e4
LT		 4943{
4944 unsigned long tmp = 0;
4945
4946 switch (bits->width) {
4947 case 1: {
4948 u8 tmp8 = 0;
4949 pci_read_config_byte(pdev, bits->reg, &tmp8);
4950 tmp = tmp8;
4951 break;
4952 }
4953 case 2: {
4954 u16 tmp16 = 0;
4955 pci_read_config_word(pdev, bits->reg, &tmp16);
4956 tmp = tmp16;
4957 break;
4958 }
4959 case 4: {
4960 u32 tmp32 = 0;
4961 pci_read_config_dword(pdev, bits->reg, &tmp32);
4962 tmp = tmp32;
4963 break;
4964 }
4965
4966 default:
4967 return -EINVAL;
4968 }
4969
4970 tmp &= bits->mask;
4971
4972 return (tmp == bits->val) ? 1 : 0;
4973}
9b847548
JA		 4974
4975int ata_pci_device_suspend(struct pci_dev *pdev, pm_message_t state)
4976{
4977 pci_save_state(pdev);
4978 pci_disable_device(pdev);
4979 pci_set_power_state(pdev, PCI_D3hot);
4980 return 0;
4981}
4982
4983int ata_pci_device_resume(struct pci_dev *pdev)
4984{
4985 pci_set_power_state(pdev, PCI_D0);
4986 pci_restore_state(pdev);
4987 pci_enable_device(pdev);
4988 pci_set_master(pdev);
4989 return 0;
4990}
1da177e4
LT		 4991#endif /* CONFIG_PCI */
4992
4993
1da177e4
LT		 4994static int __init ata_init(void)
4995{
4996 ata_wq = create_workqueue("ata");
4997 if (!ata_wq)
4998 return -ENOMEM;
4999
5000 printk(KERN_DEBUG "libata version " DRV_VERSION " loaded.\n");
5001 return 0;
5002}
5003
5004static void __exit ata_exit(void)
5005{
5006 destroy_workqueue(ata_wq);
5007}
5008
5009module_init(ata_init);
5010module_exit(ata_exit);
5011
67846b30
JG		 5012static unsigned long ratelimit_time;
5013static spinlock_t ata_ratelimit_lock = SPIN_LOCK_UNLOCKED;
5014
5015int ata_ratelimit(void)
5016{
5017 int rc;
5018 unsigned long flags;
5019
5020 spin_lock_irqsave(&ata_ratelimit_lock, flags);
5021
5022 if (time_after(jiffies, ratelimit_time)) {
5023 rc = 1;
5024 ratelimit_time = jiffies + (HZ/5);
5025 } else
5026 rc = 0;
5027
5028 spin_unlock_irqrestore(&ata_ratelimit_lock, flags);
5029
5030 return rc;
5031}
5032
1da177e4
LT		 5033/*
5034 * libata is essentially a library of internal helper functions for
5035 * low-level ATA host controller drivers. As such, the API/ABI is
5036 * likely to change as new drivers are added and updated.
5037 * Do not depend on ABI/API stability.
5038 */
5039
5040EXPORT_SYMBOL_GPL(ata_std_bios_param);
5041EXPORT_SYMBOL_GPL(ata_std_ports);
5042EXPORT_SYMBOL_GPL(ata_device_add);
17b14451 5043EXPORT_SYMBOL_GPL(ata_host_set_remove);
1da177e4
LT		 5044EXPORT_SYMBOL_GPL(ata_sg_init);
5045EXPORT_SYMBOL_GPL(ata_sg_init_one);
76014427 5046EXPORT_SYMBOL_GPL(__ata_qc_complete);
1da177e4
LT		 5047EXPORT_SYMBOL_GPL(ata_qc_issue_prot);
5048EXPORT_SYMBOL_GPL(ata_eng_timeout);
5049EXPORT_SYMBOL_GPL(ata_tf_load);
5050EXPORT_SYMBOL_GPL(ata_tf_read);
5051EXPORT_SYMBOL_GPL(ata_noop_dev_select);
5052EXPORT_SYMBOL_GPL(ata_std_dev_select);
5053EXPORT_SYMBOL_GPL(ata_tf_to_fis);
5054EXPORT_SYMBOL_GPL(ata_tf_from_fis);
5055EXPORT_SYMBOL_GPL(ata_check_status);
5056EXPORT_SYMBOL_GPL(ata_altstatus);
1da177e4
LT		 5057EXPORT_SYMBOL_GPL(ata_exec_command);
5058EXPORT_SYMBOL_GPL(ata_port_start);
5059EXPORT_SYMBOL_GPL(ata_port_stop);
aa8f0dc6 5060EXPORT_SYMBOL_GPL(ata_host_stop);
1da177e4
LT		 5061EXPORT_SYMBOL_GPL(ata_interrupt);
5062EXPORT_SYMBOL_GPL(ata_qc_prep);
5063EXPORT_SYMBOL_GPL(ata_bmdma_setup);
5064EXPORT_SYMBOL_GPL(ata_bmdma_start);
5065EXPORT_SYMBOL_GPL(ata_bmdma_irq_clear);
5066EXPORT_SYMBOL_GPL(ata_bmdma_status);
5067EXPORT_SYMBOL_GPL(ata_bmdma_stop);
5068EXPORT_SYMBOL_GPL(ata_port_probe);
5069EXPORT_SYMBOL_GPL(sata_phy_reset);
5070EXPORT_SYMBOL_GPL(__sata_phy_reset);
5071EXPORT_SYMBOL_GPL(ata_bus_reset);
8a19ac89 5072EXPORT_SYMBOL_GPL(ata_std_probeinit);
c2bd5804
TH		 5073EXPORT_SYMBOL_GPL(ata_std_softreset);
5074EXPORT_SYMBOL_GPL(sata_std_hardreset);
5075EXPORT_SYMBOL_GPL(ata_std_postreset);
5076EXPORT_SYMBOL_GPL(ata_std_probe_reset);
a62c0fc5 5077EXPORT_SYMBOL_GPL(ata_drive_probe_reset);
623a3128 5078EXPORT_SYMBOL_GPL(ata_dev_revalidate);
1da177e4 5079EXPORT_SYMBOL_GPL(ata_port_disable);
67846b30 5080EXPORT_SYMBOL_GPL(ata_ratelimit);
6f8b9958 5081EXPORT_SYMBOL_GPL(ata_busy_sleep);
86e45b6b 5082EXPORT_SYMBOL_GPL(ata_port_queue_task);
1da177e4
LT		 5083EXPORT_SYMBOL_GPL(ata_scsi_ioctl);
5084EXPORT_SYMBOL_GPL(ata_scsi_queuecmd);
f29841e0 5085EXPORT_SYMBOL_GPL(ata_scsi_timed_out);
1da177e4
LT		 5086EXPORT_SYMBOL_GPL(ata_scsi_error);
5087EXPORT_SYMBOL_GPL(ata_scsi_slave_config);
5088EXPORT_SYMBOL_GPL(ata_scsi_release);
5089EXPORT_SYMBOL_GPL(ata_host_intr);
5090EXPORT_SYMBOL_GPL(ata_dev_classify);
6a62a04d
TH		 5091EXPORT_SYMBOL_GPL(ata_id_string);
5092EXPORT_SYMBOL_GPL(ata_id_c_string);
1da177e4 5093EXPORT_SYMBOL_GPL(ata_scsi_simulate);
a72ec4ce
TH		 5094EXPORT_SYMBOL_GPL(ata_eh_qc_complete);
5095EXPORT_SYMBOL_GPL(ata_eh_qc_retry);
1da177e4 5096
1bc4ccff 5097EXPORT_SYMBOL_GPL(ata_pio_need_iordy);
452503f9
AC		 5098EXPORT_SYMBOL_GPL(ata_timing_compute);
5099EXPORT_SYMBOL_GPL(ata_timing_merge);
5100
1da177e4
LT		 5101#ifdef CONFIG_PCI
5102EXPORT_SYMBOL_GPL(pci_test_config_bits);
374b1873 5103EXPORT_SYMBOL_GPL(ata_pci_host_stop);
1da177e4
LT		 5104EXPORT_SYMBOL_GPL(ata_pci_init_native_mode);
5105EXPORT_SYMBOL_GPL(ata_pci_init_one);
5106EXPORT_SYMBOL_GPL(ata_pci_remove_one);
9b847548
JA		 5107EXPORT_SYMBOL_GPL(ata_pci_device_suspend);
5108EXPORT_SYMBOL_GPL(ata_pci_device_resume);
1da177e4 5109#endif /* CONFIG_PCI */
9b847548
JA		 5110
5111EXPORT_SYMBOL_GPL(ata_device_suspend);
5112EXPORT_SYMBOL_GPL(ata_device_resume);
5113EXPORT_SYMBOL_GPL(ata_scsi_device_suspend);
5114EXPORT_SYMBOL_GPL(ata_scsi_device_resume);
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