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[mirror_ubuntu-kernels.git] / drivers / scsi / lpfc / lpfc.h
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dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
4ae2ebde 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
2e0fef85 24#include <scsi/scsi_host.h>
895427bd 25#include <linux/ktime.h>
f485c18d 26#include <linux/workqueue.h>
88a2cfbb
JS		 27
28#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
29#define CONFIG_SCSI_LPFC_DEBUG_FS
30#endif
31
dea3101e 32struct lpfc_sli2_slim;
33
5402a315
JS		 34#define ELX_MODEL_NAME_SIZE 80
35
3772a991
JS		 36#define LPFC_PCI_DEV_LP 0x1
37#define LPFC_PCI_DEV_OC 0x2
38
39#define LPFC_SLI_REV2 2
40#define LPFC_SLI_REV3 3
41#define LPFC_SLI_REV4 4
42
97eab634 43#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 44#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
45 requests */
46#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
47 the NameServer before giving up. */
445cf4f4 48#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 49#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 50#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
51 cmnd for menlo needs nearly twice as for firmware
52 downloads using bsg */
96f7077f
JS		 53
54#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
5b9e70b2 55#define LPFC_MAX_BG_SLI4_SEG_CNT_DIF 128 /* sg element count for BlockGuard */
96f7077f 56#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 57#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
81e6a637 58#define LPFC_MIN_SG_SEG_CNT 32 /* sg element count per scsi cmnd */
09294d46
JS		 59#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
60#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
d73154ba 61#define LPFC_MAX_NVME_SEG_CNT 256 /* max SGL element cnt per NVME cmnd */
09294d46 62
0558056c 63#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 64#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 65#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 66#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a 67#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 68#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 69#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 70
ea2151b4
JS		 71#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
72 collection. */
92d7f7b0
JS		 73/*
74 * Following time intervals are used of adjusting SCSI device
75 * queue depths when there are driver resource error or Firmware
76 * resource error.
77 */
256ec0d0
JS		 78/* 1 Second */
79#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 80
81/* Number of exchanges reserved for discovery to complete */
82#define LPFC_DISC_IOCB_BUFF_COUNT 20
83
858c9f6c 84#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 85#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 86
9399627f
JS		 87/* Error Attention event polling interval */
88#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
89
dea3101e 90/* Define macros for 64 bit support */
91#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
92#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
93#define getPaddr(high, low) ((dma_addr_t)( \
94 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
95/* Provide maximum configuration definitions. */
96#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e 97#define FC_MAX_ADPTMSG 64
98
99#define MAX_HBAEVT 32
96418b5e 100#define MAX_HBAS_NO_RESET 16
dea3101e 101
9399627f
JS		 102/* Number of MSI-X vectors the driver uses */
103#define LPFC_MSIX_VECTORS 2
104
5e9d9b82 105/* lpfc wait event data ready flag */
2ade92ae 106#define LPFC_DATA_READY 0 /* bit 0 */
5e9d9b82 107
809c7536
JS		 108/* queue dump line buffer size */
109#define LPFC_LBUF_SZ 128
110
618a5230
JS		 111/* mailbox system shutdown options */
112#define LPFC_MBX_NO_WAIT 0
113#define LPFC_MBX_WAIT 1
114
875fbdfe
JSEC		 115enum lpfc_polling_flags {
116 ENABLE_FCP_RING_POLLING = 0x1,
117 DISABLE_FCP_RING_INT = 0x2
118};
119
895427bd
JS		 120struct perf_prof {
121 uint16_t cmd_cpu[40];
122 uint16_t rsp_cpu[40];
123 uint16_t qh_cpu[40];
124 uint16_t wqidx[40];
125};
126
01649561
JS		 127/*
128 * Provide for FC4 TYPE x28 - NVME. The
129 * bit mask for FCP and NVME is 0x8 identically
130 * because they are 32 bit positions distance.
131 */
a0f2d3ef
JS		 132#define LPFC_FC4_TYPE_BITMASK 0x00000100
133
dea3101e 134/* Provide DMA memory definitions the driver uses per port instance. */
135struct lpfc_dmabuf {
136 struct list_head list;
137 void *virt; /* virtual address ptr */
138 dma_addr_t phys; /* mapped address */
76bb24ef 139 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e 140};
141
6c621a22
JS		 142struct lpfc_nvmet_ctxbuf {
143 struct list_head list;
144 struct lpfc_nvmet_rcv_ctx *context;
145 struct lpfc_iocbq *iocbq;
146 struct lpfc_sglq *sglq;
472e146d 147 struct work_struct defer_work;
6c621a22
JS		 148};
149
dea3101e 150struct lpfc_dma_pool {
151 struct lpfc_dmabuf *elements;
152 uint32_t max_count;
153 uint32_t current_count;
154};
155
ed957684 156struct hbq_dmabuf {
da0436e9 157 struct lpfc_dmabuf hbuf;
ed957684 158 struct lpfc_dmabuf dbuf;
895427bd
JS		 159 uint16_t total_size;
160 uint16_t bytes_recv;
ed957684 161 uint32_t tag;
4d9ab994 162 struct lpfc_cq_event cq_event;
45ed1190 163 unsigned long time_stamp;
895427bd
JS		 164 void *context;
165};
166
167struct rqb_dmabuf {
168 struct lpfc_dmabuf hbuf;
169 struct lpfc_dmabuf dbuf;
170 uint16_t total_size;
171 uint16_t bytes_recv;
a8cf5dfe 172 uint16_t idx;
895427bd
JS		 173 struct lpfc_queue *hrq; /* ptr to associated Header RQ */
174 struct lpfc_queue *drq; /* ptr to associated Data RQ */
ed957684
JS		 175};
176
dea3101e 177/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
178#define MEM_PRI 0x100
179
180
181/****************************************************************************/
182/* Device VPD save area */
183/****************************************************************************/
184typedef struct lpfc_vpd {
185 uint32_t status; /* vpd status value */
186 uint32_t length; /* number of bytes actually returned */
187 struct {
188 uint32_t rsvd1; /* Revision numbers */
189 uint32_t biuRev;
190 uint32_t smRev;
191 uint32_t smFwRev;
192 uint32_t endecRev;
193 uint16_t rBit;
194 uint8_t fcphHigh;
195 uint8_t fcphLow;
196 uint8_t feaLevelHigh;
197 uint8_t feaLevelLow;
198 uint32_t postKernRev;
199 uint32_t opFwRev;
200 uint8_t opFwName[16];
201 uint32_t sli1FwRev;
202 uint8_t sli1FwName[16];
203 uint32_t sli2FwRev;
204 uint8_t sli2FwName[16];
205 } rev;
92d7f7b0
JS		 206 struct {
207#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 208 uint32_t rsvd3 :19; /* Reserved */
209 uint32_t cdss : 1; /* Configure Data Security SLI */
210 uint32_t rsvd2 : 3; /* Reserved */
211 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 212 uint32_t cmv : 1; /* Configure Max VPIs */
213 uint32_t ccrp : 1; /* Config Command Ring Polling */
214 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
215 uint32_t chbs : 1; /* Cofigure Host Backing store */
216 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
217 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
218 uint32_t cmx : 1; /* Configure Max XRIs */
219 uint32_t cmr : 1; /* Configure Max RPIs */
220#else /* __LITTLE_ENDIAN */
221 uint32_t cmr : 1; /* Configure Max RPIs */
222 uint32_t cmx : 1; /* Configure Max XRIs */
223 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
224 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
225 uint32_t chbs : 1; /* Cofigure Host Backing store */
226 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
227 uint32_t ccrp : 1; /* Config Command Ring Polling */
228 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 229 uint32_t cbg : 1; /* Configure BlockGuard */
230 uint32_t rsvd2 : 3; /* Reserved */
231 uint32_t cdss : 1; /* Configure Data Security SLI */
232 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 233#endif
234 } sli3Feat;
dea3101e 235} lpfc_vpd_t;
236
dea3101e 237
238/*
239 * lpfc stat counters
240 */
241struct lpfc_stats {
242 /* Statistics for ELS commands */
243 uint32_t elsLogiCol;
244 uint32_t elsRetryExceeded;
245 uint32_t elsXmitRetry;
246 uint32_t elsDelayRetry;
247 uint32_t elsRcvDrop;
248 uint32_t elsRcvFrame;
249 uint32_t elsRcvRSCN;
250 uint32_t elsRcvRNID;
251 uint32_t elsRcvFARP;
252 uint32_t elsRcvFARPR;
253 uint32_t elsRcvFLOGI;
254 uint32_t elsRcvPLOGI;
255 uint32_t elsRcvADISC;
256 uint32_t elsRcvPDISC;
257 uint32_t elsRcvFAN;
258 uint32_t elsRcvLOGO;
259 uint32_t elsRcvPRLO;
260 uint32_t elsRcvPRLI;
7bb3b137 261 uint32_t elsRcvLIRR;
12265f68 262 uint32_t elsRcvRLS;
7bb3b137
JW		 263 uint32_t elsRcvRPS;
264 uint32_t elsRcvRPL;
5ffc266e 265 uint32_t elsRcvRRQ;
12265f68
JS		 266 uint32_t elsRcvRTV;
267 uint32_t elsRcvECHO;
8b017a30 268 uint32_t elsRcvLCB;
86478875 269 uint32_t elsRcvRDP;
dea3101e 270 uint32_t elsXmitFLOGI;
92d7f7b0 271 uint32_t elsXmitFDISC;
dea3101e 272 uint32_t elsXmitPLOGI;
273 uint32_t elsXmitPRLI;
274 uint32_t elsXmitADISC;
275 uint32_t elsXmitLOGO;
276 uint32_t elsXmitSCR;
277 uint32_t elsXmitRNID;
278 uint32_t elsXmitFARP;
279 uint32_t elsXmitFARPR;
280 uint32_t elsXmitACC;
281 uint32_t elsXmitLSRJT;
282
283 uint32_t frameRcvBcast;
284 uint32_t frameRcvMulti;
285 uint32_t strayXmitCmpl;
286 uint32_t frameXmitDelay;
287 uint32_t xriCmdCmpl;
288 uint32_t xriStatErr;
289 uint32_t LinkUp;
290 uint32_t LinkDown;
291 uint32_t LinkMultiEvent;
292 uint32_t NoRcvBuf;
293 uint32_t fcpCmd;
294 uint32_t fcpCmpl;
295 uint32_t fcpRspErr;
296 uint32_t fcpRemoteStop;
297 uint32_t fcpPortRjt;
298 uint32_t fcpPortBusy;
299 uint32_t fcpError;
300 uint32_t fcpLocalErr;
301};
302
2e0fef85
JS		 303struct lpfc_hba;
304
92d7f7b0 305
2e0fef85 306enum discovery_state {
92d7f7b0
JS		 307 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
308 LPFC_VPORT_FAILED = 1, /* vport has failed */
309 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
310 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
311 LPFC_FDISC = 8, /* FDISC sent for vport */
312 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
313 * configured */
314 LPFC_NS_REG = 10, /* Register with NameServer */
315 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
316 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
317 * device authentication / discovery */
318 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
319 LPFC_VPORT_READY = 32,
2e0fef85
JS		 320};
321
322enum hba_state {
323 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
324 LPFC_WARM_START = 1, /* HBA state after selective reset */
325 LPFC_INIT_START = 2, /* Initial state after board reset */
326 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
327 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
328 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 329 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 330 * CLEAR_LA */
92d7f7b0 331 LPFC_HBA_READY = 32,
2e0fef85
JS		 332 LPFC_HBA_ERROR = -1
333};
334
1dc5ec24
JS		 335struct lpfc_trunk_link_state {
336 enum hba_state state;
337 uint8_t fault;
338};
339
340struct lpfc_trunk_link {
341 struct lpfc_trunk_link_state link0,
342 link1,
343 link2,
344 link3;
345};
346
2e0fef85 347struct lpfc_vport {
2e0fef85 348 struct lpfc_hba *phba;
3772a991 349 struct list_head listentry;
2e0fef85
JS		 350 uint8_t port_type;
351#define LPFC_PHYSICAL_PORT 1
352#define LPFC_NPIV_PORT 2
353#define LPFC_FABRIC_PORT 3
354 enum discovery_state port_state;
355
92d7f7b0 356 uint16_t vpi;
da0436e9 357 uint16_t vfi;
c868595d
JS		 358 uint8_t vpi_state;
359#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 360
361 uint32_t fc_flag; /* FC flags */
362/* Several of these flags are HBA centric and should be moved to
363 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
364 */
92d7f7b0
JS		 365#define FC_PT2PT 0x1 /* pt2pt with no fabric */
366#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
367#define FC_DISC_TMO 0x4 /* Discovery timer running */
368#define FC_PUBLIC_LOOP 0x8 /* Public loop */
369#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
370#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
371#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
372#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
373#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 374#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 375#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 376#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 377#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
378#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
379#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
380#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 381#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
382#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 383#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 384#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
385#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
386#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 387#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 388
7ee5d43e
JS		 389 uint32_t ct_flags;
390#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
391#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
392#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
393#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
394#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
395
2e0fef85
JS		 396 struct list_head fc_nodes;
397
398 /* Keep counters for the number of entries in each list. */
399 uint16_t fc_plogi_cnt;
400 uint16_t fc_adisc_cnt;
401 uint16_t fc_reglogin_cnt;
402 uint16_t fc_prli_cnt;
403 uint16_t fc_unmap_cnt;
404 uint16_t fc_map_cnt;
405 uint16_t fc_npr_cnt;
406 uint16_t fc_unused_cnt;
407 struct serv_parm fc_sparam; /* buffer for our service parameters */
408
409 uint32_t fc_myDID; /* fibre channel S_ID */
410 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 411 struct lpfc_name fabric_portname;
412 struct lpfc_name fabric_nodename;
2e0fef85
JS		 413
414 int32_t stopped; /* HBA has not been restarted since last ERATT */
415 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
416
a0f2d3ef
JS		 417 uint32_t num_disc_nodes; /* in addition to hba_state */
418 uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
2e0fef85
JS		 419
420 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
421 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 422 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 423 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
424 struct lpfc_name fc_nodename; /* fc nodename */
425 struct lpfc_name fc_portname; /* fc portname */
426
427 struct lpfc_work_evt disc_timeout_evt;
428
429 struct timer_list fc_disctmo; /* Discovery rescue timer */
430 uint8_t fc_ns_retry; /* retries for fabric nameserver */
431 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
432
433 spinlock_t work_port_lock;
434 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 435#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
436#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
92494144 437#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 438
439#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
440#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 441#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 442#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
443#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 444#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85 445
2e0fef85 446 struct timer_list els_tmofunc;
92494144 447 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 448
449 int unreg_vpi_cmpl;
450
451 uint8_t load_flag;
452#define FC_LOADING 0x1 /* HBA in process of loading drvr */
453#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
4258e98e 454#define FC_ALLOW_FDMI 0x4 /* port is ready for FDMI requests */
3de2a653
JS		 455 /* Vport Config Parameters */
456 uint32_t cfg_scan_down;
457 uint32_t cfg_lun_queue_depth;
458 uint32_t cfg_nodev_tmo;
459 uint32_t cfg_devloss_tmo;
460 uint32_t cfg_restrict_login;
461 uint32_t cfg_peer_port_login;
462 uint32_t cfg_fcp_class;
463 uint32_t cfg_use_adisc;
3de2a653 464 uint32_t cfg_discovery_threads;
e8b62011 465 uint32_t cfg_log_verbose;
f6e84790 466 uint32_t cfg_enable_fc4_type;
3de2a653 467 uint32_t cfg_max_luns;
7ee5d43e 468 uint32_t cfg_enable_da_id;
977b5a0a 469 uint32_t cfg_max_scsicmpl_time;
7dc517df 470 uint32_t cfg_tgt_queue_depth;
3cb01c57 471 uint32_t cfg_first_burst_size;
3de2a653 472 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 473
474 struct fc_vport *fc_vport;
475
923e4b6a 476#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 477 struct dentry *debug_disc_trc;
478 struct dentry *debug_nodelist;
bd2cdd5e 479 struct dentry *debug_nvmestat;
4c47efc1 480 struct dentry *debug_scsistat;
bd2cdd5e
JS		 481 struct dentry *debug_nvmektime;
482 struct dentry *debug_cpucheck;
51ef4c26
JS		 483 struct dentry *vport_debugfs_root;
484 struct lpfc_debugfs_trc *disc_trc;
485 atomic_t disc_trc_cnt;
486#endif
ea2151b4
JS		 487 uint8_t stat_data_enabled;
488 uint8_t stat_data_blocked;
da0436e9 489 struct list_head rcv_buffer_list;
45ed1190 490 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 491 uint32_t vport_flag;
492#define STATIC_VPORT 1
aeb3c817
JS		 493#define FAWWPN_SET 2
494#define FAWWPN_PARAM_CHG 4
4258e98e
JS		 495
496 uint16_t fdmi_num_disc;
497 uint32_t fdmi_hba_mask;
498 uint32_t fdmi_port_mask;
895427bd
JS		 499
500 /* There is a single nvme instance per vport. */
501 struct nvme_fc_local_port *localport;
502 uint8_t nvmei_support; /* driver supports NVME Initiator */
503 uint32_t last_fcp_wqidx;
d496b9a7 504 uint32_t rcv_flogi_cnt; /* How many unsol FLOGIs ACK'd. */
2e0fef85
JS		 505};
506
ed957684
JS		 507struct hbq_s {
508 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 509 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 510 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
511 uint32_t hbqPutIdx; /* HBQ slot to use */
512 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 513 void *hbq_virt; /* Virtual ptr to this hbq */
514 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
515 /* Callback for HBQ buffer allocation */
516 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
517 /* Callback for HBQ buffer free */
518 void (*hbq_free_buffer) (struct lpfc_hba *,
519 struct hbq_dmabuf *);
ed957684
JS		 520};
521
51ef4c26 522/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 523#define LPFC_ELS_HBQ 0
895427bd 524#define LPFC_MAX_HBQS 1
ed957684 525
7af67051
JS		 526enum hba_temp_state {
527 HBA_NORMAL_TEMP,
528 HBA_OVER_TEMP
529};
530
db2378e0
JS		 531enum intr_type_t {
532 NONE = 0,
533 INTx,
534 MSI,
535 MSIX,
536};
537
6dd9e31c 538#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 539struct unsol_rcv_ct_ctx {
540 uint32_t ctxt_id;
541 uint32_t SID;
6dd9e31c
JS		 542 uint32_t valid;
543#define UNSOL_INVALID 0
544#define UNSOL_VALID 1
7851fe2c
JS		 545 uint16_t oxid;
546 uint16_t rxid;
f1c3b0fc
JS		 547};
548
76a95d75
JS		 549#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
550#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
551#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
552#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
553#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
554#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
555#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
d38dd52c 556#define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
fbd8a6ba
JS		 557#define LPFC_USER_LINK_SPEED_64G 64 /* 64 Gigabaud */
558#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_64G
559
560#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32, 64"
76a95d75 561
7ad20aa9
JS		 562enum nemb_type {
563 nemb_mse = 1,
564 nemb_hbd
565};
566
567enum mbox_type {
568 mbox_rd = 1,
569 mbox_wr
570};
571
572enum dma_type {
573 dma_mbox = 1,
574 dma_ebuf
575};
576
577enum sta_type {
578 sta_pre_addr = 1,
579 sta_pos_addr
580};
581
582struct lpfc_mbox_ext_buf_ctx {
583 uint32_t state;
584#define LPFC_BSG_MBOX_IDLE 0
585#define LPFC_BSG_MBOX_HOST 1
586#define LPFC_BSG_MBOX_PORT 2
587#define LPFC_BSG_MBOX_DONE 3
588#define LPFC_BSG_MBOX_ABTS 4
589 enum nemb_type nembType;
590 enum mbox_type mboxType;
591 uint32_t numBuf;
592 uint32_t mbxTag;
593 uint32_t seqNum;
594 struct lpfc_dmabuf *mbx_dmabuf;
595 struct list_head ext_dmabuf_list;
596};
597
c490850a
JS		 598struct lpfc_epd_pool {
599 /* Expedite pool */
600 struct list_head list;
601 u32 count;
602 spinlock_t lock; /* lock for expedite pool */
603};
604
d2cc9bcd
JS		 605struct lpfc_ras_fwlog {
606 uint8_t *fwlog_buff;
607 uint32_t fw_buffcount; /* Buffer size posted to FW */
608#define LPFC_RAS_BUFF_ENTERIES 16 /* Each entry can hold max of 64k */
609#define LPFC_RAS_MAX_ENTRY_SIZE (64 * 1024)
610#define LPFC_RAS_MIN_BUFF_POST_SIZE (256 * 1024)
611#define LPFC_RAS_MAX_BUFF_POST_SIZE (1024 * 1024)
612 uint32_t fw_loglevel; /* Log level set */
613 struct lpfc_dmabuf lwpd;
614 struct list_head fwlog_buff_list;
615
616 /* RAS support status on adapter */
617 bool ras_hwsupport; /* RAS Support available on HW or not */
618 bool ras_enabled; /* Ras Enabled for the function */
619#define LPFC_RAS_DISABLE_LOGGING 0x00
620#define LPFC_RAS_ENABLE_LOGGING 0x01
621 bool ras_active; /* RAS logging running state */
622};
623
dea3101e 624struct lpfc_hba {
3772a991 625 /* SCSI interface function jump table entries */
c490850a 626 struct lpfc_io_buf * (*lpfc_get_scsi_buf)
ace44e48
JS		 627 (struct lpfc_hba *phba, struct lpfc_nodelist *ndlp,
628 struct scsi_cmnd *cmnd);
3772a991 629 int (*lpfc_scsi_prep_dma_buf)
c490850a 630 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991 631 void (*lpfc_scsi_unprep_dma_buf)
c490850a 632 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991 633 void (*lpfc_release_scsi_buf)
c490850a 634 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991
JS		 635 void (*lpfc_rampdown_queue_depth)
636 (struct lpfc_hba *);
637 void (*lpfc_scsi_prep_cmnd)
c490850a 638 (struct lpfc_vport *, struct lpfc_io_buf *,
3772a991 639 struct lpfc_nodelist *);
acd6859b 640
3772a991
JS		 641 /* IOCB interface function jump table entries */
642 int (*__lpfc_sli_issue_iocb)
643 (struct lpfc_hba *, uint32_t,
644 struct lpfc_iocbq *, uint32_t);
645 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
646 struct lpfc_iocbq *);
647 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 648 IOCB_t * (*lpfc_get_iocb_from_iocbq)
649 (struct lpfc_iocbq *);
650 void (*lpfc_scsi_cmd_iocb_cmpl)
651 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
652
653 /* MBOX interface function jump table entries */
654 int (*lpfc_sli_issue_mbox)
655 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 656
3772a991
JS		 657 /* Slow-path IOCB process function jump table entries */
658 void (*lpfc_sli_handle_slow_ring_event)
659 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
660 uint32_t mask);
acd6859b 661
3772a991
JS		 662 /* INIT device interface function jump table entries */
663 int (*lpfc_sli_hbq_to_firmware)
664 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
665 int (*lpfc_sli_brdrestart)
666 (struct lpfc_hba *);
667 int (*lpfc_sli_brdready)
668 (struct lpfc_hba *, uint32_t);
669 void (*lpfc_handle_eratt)
670 (struct lpfc_hba *);
671 void (*lpfc_stop_port)
672 (struct lpfc_hba *);
84d1b006 673 int (*lpfc_hba_init_link)
6e7288d9 674 (struct lpfc_hba *, uint32_t);
84d1b006 675 int (*lpfc_hba_down_link)
6e7288d9 676 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 677 int (*lpfc_selective_reset)
678 (struct lpfc_hba *);
3772a991 679
acd6859b 680 int (*lpfc_bg_scsi_prep_dma_buf)
c490850a 681 (struct lpfc_hba *, struct lpfc_io_buf *);
acd6859b
JS		 682 /* Add new entries here */
683
c490850a
JS		 684 /* expedite pool */
685 struct lpfc_epd_pool epd_pool;
686
3772a991
JS		 687 /* SLI4 specific HBA data structure */
688 struct lpfc_sli4_hba sli4_hba;
689
f485c18d 690 struct workqueue_struct *wq;
32517fc0 691 struct delayed_work eq_delay_work;
f485c18d 692
dea3101e 693 struct lpfc_sli sli;
3772a991
JS		 694 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
695 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 696 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 697#define LPFC_SLI3_HBQ_ENABLED 0x01
698#define LPFC_SLI3_NPIV_ENABLED 0x02
699#define LPFC_SLI3_VPORT_TEARDOWN 0x04
700#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 701#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 702#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 703#define LPFC_SLI4_PERFH_ENABLED 0x80
704#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 705 uint32_t iocb_cmd_size;
706 uint32_t iocb_rsp_size;
2e0fef85 707
1dc5ec24 708 struct lpfc_trunk_link trunk_link;
2e0fef85
JS		 709 enum hba_state link_state;
710 uint32_t link_flag; /* link state flags */
311464ec 711#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 712 /* This flag is set while issuing */
713 /* INIT_LINK mailbox command */
92d7f7b0 714#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 715#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
ae9e28f3 716#define LS_MDS_LINK_DOWN 0x8 /* MDS Diagnostics Link Down */
53e13ee0 717#define LS_MDS_LOOPBACK 0x10 /* MDS Diagnostics Link Up (Loopback) */
2e0fef85 718
9399627f
JS		 719 uint32_t hba_flag; /* hba generic flags */
720#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 721#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 722#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 723#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9 724#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
da0436e9
JS		 725#define ELS_XRI_ABORT_EVENT 0x40
726#define ASYNC_EVENT 0x80
a0c87cbd 727#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 728#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
729#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
730#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
731#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
732#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 733#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 734#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
0293635e 735#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
65791f1f 736#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
c691816e
JS		 737#define HBA_FORCED_LINK_SPEED 0x40000 /*
738 * Firmware supports Forced Link Speed
739 * capability
740 */
895427bd 741#define HBA_NVME_IOQ_FLUSH 0x80000 /* NVME IO queues flushed. */
0a9e9687 742#define HBA_FLOGI_ISSUED 0x100000 /* FLOGI was issued */
895427bd 743
45ed1190 744 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 745 struct lpfc_dmabuf slim2p;
746
747 MAILBOX_t *mbox;
7a470277 748 uint32_t *mbox_ext;
7ad20aa9 749 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 750 uint32_t ha_copy;
34b02dcd
JS		 751 struct _PCB *pcb;
752 struct _IOCB *IOCBs;
2e0fef85 753
34b02dcd 754 struct lpfc_dmabuf hbqslimp;
2e0fef85 755
dea3101e 756 uint16_t pci_cfg_value;
757
dea3101e 758 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
759
760 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 761 uint32_t link_events;
dea3101e 762
dea3101e 763 /* These fields used to be binfo */
dea3101e 764 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 765 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 766 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e 767 uint32_t fc_edtov; /* E_D_TOV timer value */
768 uint32_t fc_arbtov; /* ARB_TOV timer value */
769 uint32_t fc_ratov; /* R_A_TOV timer value */
770 uint32_t fc_rttov; /* R_T_TOV timer value */
771 uint32_t fc_altov; /* AL_TOV timer value */
772 uint32_t fc_crtov; /* C_R_TOV timer value */
dea3101e 773
dea3101e 774 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
775 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
776
dea3101e 777 uint32_t lmt;
dea3101e 778
779 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 780 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e 781
782 struct lpfc_stats fc_stat;
783
dea3101e 784 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
785 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
786
2e0fef85
JS		 787 uint8_t wwnn[8];
788 uint8_t wwpn[8];
dea3101e 789 uint32_t RandomData[7];
7bdedb34 790 uint8_t fcp_embed_io;
895427bd
JS		 791 uint8_t nvme_support; /* Firmware supports NVME */
792 uint8_t nvmet_support; /* driver supports NVMET */
f358dd0c 793#define LPFC_NVMET_MAX_PORTS 32
7bdedb34 794 uint8_t mds_diags_support;
44fd7fe3 795 uint8_t bbcredit_support;
c176ffa0 796 uint8_t enab_exp_wqcq_pages;
dea3101e 797
3de2a653 798 /* HBA Config Parameters */
dea3101e 799 uint32_t cfg_ack0;
c490850a 800 uint32_t cfg_xri_rebalancing;
78b2d852 801 uint32_t cfg_enable_npiv;
19ca7609 802 uint32_t cfg_enable_rrq;
dea3101e 803 uint32_t cfg_topology;
dea3101e 804 uint32_t cfg_link_speed;
7d791df7
JS		 805#define LPFC_FCF_FOV 1 /* Fast fcf failover */
806#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
807 uint32_t cfg_fcf_failover_policy;
49aa143d 808 uint32_t cfg_fcp_io_sched;
7ea92eb4 809 uint32_t cfg_ns_query;
a6571c6e 810 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e 811 uint32_t cfg_cr_delay;
812 uint32_t cfg_cr_count;
cf5bf97e 813 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 814 uint32_t cfg_multi_ring_rctl;
815 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 816 uint32_t cfg_poll;
817 uint32_t cfg_poll_tmo;
0c411222 818 uint32_t cfg_task_mgmt_tmo;
4ff43246 819 uint32_t cfg_use_msi;
0cf07f84 820 uint32_t cfg_auto_imax;
da0436e9 821 uint32_t cfg_fcp_imax;
32517fc0
JS		 822 uint32_t cfg_cq_poll_threshold;
823 uint32_t cfg_cq_max_proc_limit;
7bb03bbf 824 uint32_t cfg_fcp_cpu_map;
cdb42bec 825 uint32_t cfg_hdw_queue;
6a828b0f 826 uint32_t cfg_irq_chann;
f358dd0c 827 uint32_t cfg_suppress_rsp;
895427bd 828 uint32_t cfg_nvme_oas;
4e565cf0 829 uint32_t cfg_nvme_embed_cmd;
2448e484 830 uint32_t cfg_nvmet_mrq_post;
2d7dbc4c 831 uint32_t cfg_nvmet_mrq;
f358dd0c 832 uint32_t cfg_enable_nvmet;
895427bd 833 uint32_t cfg_nvme_enable_fb;
2d7dbc4c 834 uint32_t cfg_nvmet_fb_size;
96f7077f 835 uint32_t cfg_total_seg_cnt;
dea3101e 836 uint32_t cfg_sg_seg_cnt;
4d4c4a4a 837 uint32_t cfg_nvme_seg_cnt;
5b9e70b2 838 uint32_t cfg_scsi_seg_cnt;
dea3101e 839 uint32_t cfg_sg_dma_buf_size;
352e5fd1
JS		 840 uint64_t cfg_soft_wwnn;
841 uint64_t cfg_soft_wwpn;
3de2a653 842 uint32_t cfg_hba_queue_depth;
13815c83
JS		 843 uint32_t cfg_enable_hba_reset;
844 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 845 uint32_t cfg_fof;
846 uint32_t cfg_EnableXLane;
847 uint8_t cfg_oas_tgt_wwpn[8];
848 uint8_t cfg_oas_vpt_wwpn[8];
849 uint32_t cfg_oas_lun_state;
850#define OAS_LUN_ENABLE 1
851#define OAS_LUN_DISABLE 0
852 uint32_t cfg_oas_lun_status;
853#define OAS_LUN_STATUS_EXISTS 0x01
854 uint32_t cfg_oas_flags;
855#define OAS_FIND_ANY_VPORT 0x01
856#define OAS_FIND_ANY_TARGET 0x02
857#define OAS_LUN_VALID 0x04
c92c841c 858 uint32_t cfg_oas_priority;
1ba981fd 859 uint32_t cfg_XLanePriority;
81301a9b 860 uint32_t cfg_enable_bg;
b3b98b74
JS		 861 uint32_t cfg_prot_mask;
862 uint32_t cfg_prot_guard;
7a470277 863 uint32_t cfg_hostmem_hgp;
da0436e9 864 uint32_t cfg_log_verbose;
f6e84790 865 uint32_t cfg_enable_fc4_type;
0d878419 866 uint32_t cfg_aer_support;
912e3acd 867 uint32_t cfg_sriov_nr_virtfn;
c71ab861 868 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 869 uint32_t cfg_iocb_cnt;
84d1b006 870 uint32_t cfg_suppress_link_up;
cff261f6 871 uint32_t cfg_rrq_xri_bitmap_sz;
8eb8b960 872 uint32_t cfg_delay_discovery;
12247e81 873 uint32_t cfg_sli_mode;
e40a02c1
JS		 874#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
875#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
876#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 877 uint32_t cfg_enable_dss;
4258e98e
JS		 878 uint32_t cfg_fdmi_on;
879#define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
880#define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
4258e98e 881 uint32_t cfg_enable_SmartSAN;
7bdedb34 882 uint32_t cfg_enable_mds_diags;
d2cc9bcd
JS		 883 uint32_t cfg_ras_fwlog_level;
884 uint32_t cfg_ras_fwlog_buffsize;
885 uint32_t cfg_ras_fwlog_func;
1351e69f
JS		 886 uint32_t cfg_enable_bbcr; /* Enable BB Credit Recovery */
887 uint32_t cfg_enable_dpp; /* Enable Direct Packet Push */
895427bd
JS		 888#define LPFC_ENABLE_FCP 1
889#define LPFC_ENABLE_NVME 2
890#define LPFC_ENABLE_BOTH 3
414abe0a 891 uint32_t cfg_enable_pbde;
f358dd0c 892 struct nvmet_fc_target_port *targetport;
dea3101e 893 lpfc_vpd_t vpd; /* vital product data */
894
dea3101e 895 struct pci_dev *pcidev;
896 struct list_head work_list;
897 uint32_t work_ha; /* Host Attention Bits for WT */
898 uint32_t work_ha_mask; /* HA Bits owned by WT */
899 uint32_t work_hs; /* HS stored in case of ERRAT */
900 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 901
5e9d9b82 902 wait_queue_head_t work_waitq;
dea3101e 903 struct task_struct *worker_thread;
d7c255b2 904 unsigned long data_flags;
dea3101e 905
3163f725 906 uint32_t hbq_in_use; /* HBQs in use flag */
ed957684 907 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 908 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 909
895427bd
JS		 910 atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
911 atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
8fa38513 912
115a4124
JS		 913 phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
914 phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
915 phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
dea3101e 916 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
917 PCI BAR0 */
918 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
919 PCI BAR2 */
920
962bc51b
JS		 921 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
922 PCI BAR0 with dual-ULP support */
923 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
924 PCI BAR2 with dual-ULP support */
925 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
926 PCI BAR4 with dual-ULP support */
927#define PCI_64BIT_BAR0 0
928#define PCI_64BIT_BAR2 2
929#define PCI_64BIT_BAR4 4
dea3101e 930 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
931 void __iomem *HAregaddr; /* virtual address for host attn reg */
932 void __iomem *CAregaddr; /* virtual address for chip attn reg */
933 void __iomem *HSregaddr; /* virtual address for host status
934 reg */
935 void __iomem *HCregaddr; /* virtual address for host ctl reg */
936
ed957684 937 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 938 struct lpfc_pgp *port_gp;
ed957684 939 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 940 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 941
dea3101e 942 int brd_no; /* FC board number */
dea3101e 943 char SerialNumber[32]; /* adapter Serial Number */
944 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
945 char ModelDesc[256]; /* Model Description */
946 char ModelName[80]; /* Model Name */
947 char ProgramType[256]; /* Program Type */
948 char Port[20]; /* Port No */
949 uint8_t vpd_flag; /* VPD data flag */
950
951#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
952#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
953#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
954#define VPD_PORT 0x8 /* valid vpd port data */
955#define VPD_MASK 0xf /* mask for any vpd data */
956
352e5fd1
JS		 957 uint8_t soft_wwn_enable;
958
875fbdfe 959 struct timer_list fcp_poll_timer;
9399627f 960 struct timer_list eratt_poll;
65791f1f 961 uint32_t eratt_poll_interval;
875fbdfe 962
81301a9b
JS		 963 uint64_t bg_guard_err_cnt;
964 uint64_t bg_apptag_err_cnt;
965 uint64_t bg_reftag_err_cnt;
dea3101e 966
dea3101e 967 /* fastpath list. */
a40fc5f0
JS		 968 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
969 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
970 struct list_head lpfc_scsi_buf_list_get;
971 struct list_head lpfc_scsi_buf_list_put;
dea3101e 972 uint32_t total_scsi_bufs;
973 struct list_head lpfc_iocb_list;
974 uint32_t total_iocbq_bufs;
19ca7609 975 struct list_head active_rrq_list;
2e0fef85 976 spinlock_t hbalock;
dea3101e 977
771db5c0
RP		 978 /* dma_mem_pools */
979 struct dma_pool *lpfc_sg_dma_buf_pool;
980 struct dma_pool *lpfc_mbuf_pool;
981 struct dma_pool *lpfc_hrb_pool; /* header receive buffer pool */
982 struct dma_pool *lpfc_drb_pool; /* data receive buffer pool */
983 struct dma_pool *lpfc_nvmet_drb_pool; /* data receive buffer pool */
984 struct dma_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
985 struct dma_pool *txrdy_payload_pool;
dea3101e 986 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
987
988 mempool_t *mbox_mem_pool;
989 mempool_t *nlp_mem_pool;
19ca7609 990 mempool_t *rrq_pool;
cff261f6 991 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 992
993 struct fc_host_statistics link_stats;
db2378e0 994 enum intr_type_t intr_type;
5b75da2f
JS		 995 uint32_t intr_mode;
996#define LPFC_INTR_ERROR 0xFFFFFFFF
2e0fef85 997 struct list_head port_list;
523128e5 998 spinlock_t port_list_lock; /* lock for port_list mutations */
549e55cd
JS		 999 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
1000 uint16_t max_vpi; /* Maximum virtual nports */
8b47ae69
JS		 1001#define LPFC_MAX_VPI 0xFF /* Max number VPI supported 0 - 0xff */
1002#define LPFC_MAX_VPORTS 0x100 /* Max vports per port, with pport */
da0436e9
JS		 1003 uint16_t max_vports; /*
1004 * For IOV HBAs max_vpi can change
1005 * after a reset. max_vports is max
1006 * number of vports present. This can
1007 * be greater than max_vpi.
1008 */
1009 uint16_t vpi_base;
1010 uint16_t vfi_base;
549e55cd 1011 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 1012 uint16_t *vpi_ids;
1013 uint16_t vpi_count;
1014 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 1015
1016 /* Data structure used by fabric iocb scheduler */
1017 struct list_head fabric_iocb_list;
1018 atomic_t fabric_iocb_count;
1019 struct timer_list fabric_block_timer;
1020 unsigned long bit_flags;
1021#define FABRIC_COMANDS_BLOCKED 0
1022 atomic_t num_rsrc_err;
1023 atomic_t num_cmd_success;
1024 unsigned long last_rsrc_error_time;
1025 unsigned long last_ramp_down_time;
923e4b6a 1026#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 1027 struct dentry *hba_debugfs_root;
1028 atomic_t debugfs_vport_count;
c490850a 1029 struct dentry *debug_multixri_pools;
78b2d852 1030 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 1031 struct dentry *debug_dumpHostSlim;
1032 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 1033 struct dentry *debug_dumpData; /* BlockGuard BPL */
1034 struct dentry *debug_dumpDif; /* BlockGuard BPL */
1035 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 1036 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
1037 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 1038 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
1039 struct dentry *debug_writeApp; /* inject write app_tag errors */
1040 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 1041 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 1042 struct dentry *debug_readApp; /* inject read app_tag errors */
1043 struct dentry *debug_readRef; /* inject read ref_tag errors */
1044
bd2cdd5e
JS		 1045 struct dentry *debug_nvmeio_trc;
1046 struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
5e5b511d 1047 struct dentry *debug_hdwqinfo;
6a828b0f
JS		 1048#ifdef LPFC_HDWQ_LOCK_STAT
1049 struct dentry *debug_lockstat;
1050#endif
bd2cdd5e
JS		 1051 atomic_t nvmeio_trc_cnt;
1052 uint32_t nvmeio_trc_size;
1053 uint32_t nvmeio_trc_output_idx;
1054
f9bb2da1
JS		 1055 /* T10 DIF error injection */
1056 uint32_t lpfc_injerr_wgrd_cnt;
1057 uint32_t lpfc_injerr_wapp_cnt;
1058 uint32_t lpfc_injerr_wref_cnt;
acd6859b 1059 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 1060 uint32_t lpfc_injerr_rapp_cnt;
1061 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 1062 uint32_t lpfc_injerr_nportid;
1063 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 1064 sector_t lpfc_injerr_lba;
acd6859b 1065#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 1066
a58cbd52
JS		 1067 struct dentry *debug_slow_ring_trc;
1068 struct lpfc_debugfs_trc *slow_ring_trc;
1069 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 1070 /* iDiag debugfs sub-directory */
1071 struct dentry *idiag_root;
1072 struct dentry *idiag_pci_cfg;
b76f2dc9 1073 struct dentry *idiag_bar_acc;
2a622bfb 1074 struct dentry *idiag_que_info;
86a80846
JS		 1075 struct dentry *idiag_que_acc;
1076 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 1077 struct dentry *idiag_ctl_acc;
1078 struct dentry *idiag_mbx_acc;
1079 struct dentry *idiag_ext_acc;
07bcd98e 1080 uint8_t lpfc_idiag_last_eq;
858c9f6c 1081#endif
bd2cdd5e 1082 uint16_t nvmeio_trc_on;
858c9f6c 1083
0ff10d46
JS		 1084 /* Used for deferred freeing of ELS data buffers */
1085 struct list_head elsbuf;
1086 int elsbuf_cnt;
1087 int elsbuf_prev_cnt;
1088
57127f15 1089 uint8_t temp_sensor_support;
858c9f6c
JS		 1090 /* Fields used for heart beat. */
1091 unsigned long last_completion_time;
bc73905a 1092 unsigned long skipped_hb;
858c9f6c
JS		 1093 struct timer_list hb_tmofunc;
1094 uint8_t hb_outstanding;
19ca7609 1095 struct timer_list rrq_tmr;
84774a4d 1096 enum hba_temp_state over_temp_state;
e47c9093
JS		 1097 /* ndlp reference management */
1098 spinlock_t ndlp_lock;
76bb24ef
JS		 1099 /*
1100 * Following bit will be set for all buffer tags which are not
1101 * associated with any HBQ.
1102 */
1103#define QUE_BUFTAG_BIT (1<<31)
1104 uint32_t buffer_tag_count;
84774a4d
JS		 1105 int wait_4_mlo_maint_flg;
1106 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 1107 /* data structure used for latency data collection */
1108#define LPFC_NO_BUCKET 0
1109#define LPFC_LINEAR_BUCKET 1
1110#define LPFC_POWER2_BUCKET 2
1111 uint8_t bucket_type;
1112 uint32_t bucket_base;
1113 uint32_t bucket_step;
1114
1115/* Maximum number of events that can be outstanding at any time*/
1116#define LPFC_MAX_EVT_COUNT 512
1117 atomic_t fast_event_count;
32b9793f
JS		 1118 uint32_t fcoe_eventtag;
1119 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 1120 uint32_t fcoe_cvl_eventtag;
1121 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 1122 struct lpfc_fcf fcf;
1123 uint8_t fc_map[3];
1124 uint8_t valid_vlan;
1125 uint16_t vlan_id;
1126 struct list_head fcf_conn_rec_list;
f1c3b0fc 1127
0a9e9687
JS		 1128 bool defer_flogi_acc_flag;
1129 uint16_t defer_flogi_acc_rx_id;
1130 uint16_t defer_flogi_acc_ox_id;
1131
4fede78f 1132 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 1133 struct list_head ct_ev_waiters;
6dd9e31c 1134 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 1135 uint32_t ctx_idx;
e2aed29f 1136
d2cc9bcd
JS		 1137 /* RAS Support */
1138 struct lpfc_ras_fwlog ras_fwlog;
1139
e2aed29f
JS		 1140 uint8_t menlo_flag; /* menlo generic flags */
1141#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 1142 uint32_t iocb_cnt;
1143 uint32_t iocb_max;
d7c47992 1144 atomic_t sdev_cnt;
bc73905a
JS		 1145 uint8_t fips_spec_rev;
1146 uint8_t fips_level;
1ba981fd
JS		 1147 spinlock_t devicelock; /* lock for luns list */
1148 mempool_t *device_data_mem_pool;
1149 struct list_head luns;
310429ef
JS		 1150#define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
1151#define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
1152#define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
1153#define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
1154#define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
1155#define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
1156#define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
1157#define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
1158#define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
1159#define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
1160 uint16_t sfp_alarm;
1161 uint16_t sfp_warning;
bd2cdd5e
JS		 1162
1163#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
bd2cdd5e
JS		 1164 uint16_t cpucheck_on;
1165#define LPFC_CHECK_OFF 0
1166#define LPFC_CHECK_NVME_IO 1
f358dd0c
JS		 1167#define LPFC_CHECK_NVMET_RCV 2
1168#define LPFC_CHECK_NVMET_IO 4
6a828b0f 1169#define LPFC_CHECK_SCSI_IO 8
bd2cdd5e
JS		 1170 uint16_t ktime_on;
1171 uint64_t ktime_data_samples;
1172 uint64_t ktime_status_samples;
1173 uint64_t ktime_last_cmd;
1174 uint64_t ktime_seg1_total;
1175 uint64_t ktime_seg1_min;
1176 uint64_t ktime_seg1_max;
1177 uint64_t ktime_seg2_total;
1178 uint64_t ktime_seg2_min;
1179 uint64_t ktime_seg2_max;
1180 uint64_t ktime_seg3_total;
1181 uint64_t ktime_seg3_min;
1182 uint64_t ktime_seg3_max;
1183 uint64_t ktime_seg4_total;
1184 uint64_t ktime_seg4_min;
1185 uint64_t ktime_seg4_max;
1186 uint64_t ktime_seg5_total;
1187 uint64_t ktime_seg5_min;
1188 uint64_t ktime_seg5_max;
1189 uint64_t ktime_seg6_total;
1190 uint64_t ktime_seg6_min;
1191 uint64_t ktime_seg6_max;
1192 uint64_t ktime_seg7_total;
1193 uint64_t ktime_seg7_min;
1194 uint64_t ktime_seg7_max;
1195 uint64_t ktime_seg8_total;
1196 uint64_t ktime_seg8_min;
1197 uint64_t ktime_seg8_max;
1198 uint64_t ktime_seg9_total;
1199 uint64_t ktime_seg9_min;
1200 uint64_t ktime_seg9_max;
1201 uint64_t ktime_seg10_total;
1202 uint64_t ktime_seg10_min;
1203 uint64_t ktime_seg10_max;
1204#endif
dea3101e 1205};
1206
2e0fef85
JS		 1207static inline struct Scsi_Host *
1208lpfc_shost_from_vport(struct lpfc_vport *vport)
1209{
1210 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
1211}
1212
5b8bd0c9 1213static inline void
2e0fef85
JS		 1214lpfc_set_loopback_flag(struct lpfc_hba *phba)
1215{
5b8bd0c9 1216 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1217 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1218 else
2e0fef85
JS		 1219 phba->link_flag &= ~LS_LOOPBACK_MODE;
1220}
1221
1222static inline int
1223lpfc_is_link_up(struct lpfc_hba *phba)
1224{
1225 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1226 phba->link_state == LPFC_CLEAR_LA ||
1227 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1228}
dea3101e 1229
5e9d9b82
JS		 1230static inline void
1231lpfc_worker_wake_up(struct lpfc_hba *phba)
1232{
1233 /* Set the lpfc data pending flag */
1234 set_bit(LPFC_DATA_READY, &phba->data_flags);
1235
1236 /* Wake up worker thread */
1237 wake_up(&phba->work_waitq);
1238 return;
1239}
1240
9940b97b
JS		 1241static inline int
1242lpfc_readl(void __iomem *addr, uint32_t *data)
1243{
1244 uint32_t temp;
1245 temp = readl(addr);
1246 if (temp == 0xffffffff)
1247 return -EIO;
1248 *data = temp;
1249 return 0;
1250}
1251
1252static inline int
9399627f
JS		 1253lpfc_sli_read_hs(struct lpfc_hba *phba)
1254{
1255 /*
1256 * There was a link/board error. Read the status register to retrieve
1257 * the error event and process it.
1258 */
1259 phba->sli.slistat.err_attn_event++;
1260
9940b97b
JS		 1261 /* Save status info and check for unplug error */
1262 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1263 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1264 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1265 return -EIO;
1266 }
9399627f
JS		 1267
1268 /* Clear chip Host Attention error bit */
1269 writel(HA_ERATT, phba->HAregaddr);
1270 readl(phba->HAregaddr); /* flush */
1271 phba->pport->stopped = 1;
1272
9940b97b 1273 return 0;
9399627f 1274}
895427bd
JS		 1275
1276static inline struct lpfc_sli_ring *
1277lpfc_phba_elsring(struct lpfc_hba *phba)
1278{
5a9eeff5
JS		 1279 /* Return NULL if sli_rev has become invalid due to bad fw */
1280 if (phba->sli_rev != LPFC_SLI_REV4 &&
1281 phba->sli_rev != LPFC_SLI_REV3 &&
1282 phba->sli_rev != LPFC_SLI_REV2)
1283 return NULL;
1284
0c9c6a75
JS		 1285 if (phba->sli_rev == LPFC_SLI_REV4) {
1286 if (phba->sli4_hba.els_wq)
1287 return phba->sli4_hba.els_wq->pring;
1288 else
1289 return NULL;
1290 }
895427bd
JS		 1291 return &phba->sli.sli3_ring[LPFC_ELS_RING];
1292}
32517fc0
JS		 1293
1294/**
1295 * lpfc_sli4_mod_hba_eq_delay - update EQ delay
1296 * @phba: Pointer to HBA context object.
1297 * @q: The Event Queue to update.
1298 * @delay: The delay value (in us) to be written.
1299 *
1300 **/
1301static inline void
1302lpfc_sli4_mod_hba_eq_delay(struct lpfc_hba *phba, struct lpfc_queue *eq,
1303 u32 delay)
1304{
1305 struct lpfc_register reg_data;
1306
1307 reg_data.word0 = 0;
1308 bf_set(lpfc_sliport_eqdelay_id, &reg_data, eq->queue_id);
1309 bf_set(lpfc_sliport_eqdelay_delay, &reg_data, delay);
1310 writel(reg_data.word0, phba->sli4_hba.u.if_type2.EQDregaddr);
1311 eq->q_mode = delay;
1312}
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