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dea3101e JB |
1 | /******************************************************************* |
2 | * This file is part of the Emulex Linux Device Driver for * | |
c44ce173 | 3 | * Fibre Channel Host Bus Adapters. * |
9413afff | 4 | * Copyright (C) 2004-2007 Emulex. All rights reserved. * |
c44ce173 | 5 | * EMULEX and SLI are trademarks of Emulex. * |
dea3101e | 6 | * www.emulex.com * |
c44ce173 | 7 | * Portions Copyright (C) 2004-2005 Christoph Hellwig * |
dea3101e JB |
8 | * * |
9 | * This program is free software; you can redistribute it and/or * | |
c44ce173 JSEC |
10 | * modify it under the terms of version 2 of the GNU General * |
11 | * Public License as published by the Free Software Foundation. * | |
12 | * This program is distributed in the hope that it will be useful. * | |
13 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * | |
14 | * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * | |
15 | * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * | |
16 | * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * | |
17 | * TO BE LEGALLY INVALID. See the GNU General Public License for * | |
18 | * more details, a copy of which can be found in the file COPYING * | |
19 | * included with this package. * | |
dea3101e JB |
20 | *******************************************************************/ |
21 | ||
dea3101e JB |
22 | #include <linux/blkdev.h> |
23 | #include <linux/pci.h> | |
24 | #include <linux/interrupt.h> | |
25 | ||
f888ba3c JSEC |
26 | #include <scsi/scsi_device.h> |
27 | #include <scsi/scsi_transport_fc.h> | |
28 | ||
91886523 JSEC |
29 | #include <scsi/scsi.h> |
30 | ||
dea3101e JB |
31 | #include "lpfc_hw.h" |
32 | #include "lpfc_sli.h" | |
33 | #include "lpfc_disc.h" | |
34 | #include "lpfc_scsi.h" | |
35 | #include "lpfc.h" | |
36 | #include "lpfc_logmsg.h" | |
37 | #include "lpfc_crtn.h" | |
38 | #include "lpfc_compat.h" | |
39 | ||
40 | /**********************************************/ | |
41 | ||
42 | /* mailbox command */ | |
43 | /**********************************************/ | |
44 | void | |
45 | lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset) | |
46 | { | |
47 | MAILBOX_t *mb; | |
48 | void *ctx; | |
49 | ||
50 | mb = &pmb->mb; | |
51 | ctx = pmb->context2; | |
52 | ||
53 | /* Setup to dump VPD region */ | |
54 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
55 | mb->mbxCommand = MBX_DUMP_MEMORY; | |
56 | mb->un.varDmp.cv = 1; | |
57 | mb->un.varDmp.type = DMP_NV_PARAMS; | |
58 | mb->un.varDmp.entry_index = offset; | |
59 | mb->un.varDmp.region_id = DMP_REGION_VPD; | |
60 | mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t)); | |
61 | mb->un.varDmp.co = 0; | |
62 | mb->un.varDmp.resp_offset = 0; | |
63 | pmb->context2 = ctx; | |
64 | mb->mbxOwner = OWN_HOST; | |
65 | return; | |
66 | } | |
67 | ||
68 | /**********************************************/ | |
69 | /* lpfc_read_nv Issue a READ NVPARAM */ | |
70 | /* mailbox command */ | |
71 | /**********************************************/ | |
72 | void | |
73 | lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
74 | { | |
75 | MAILBOX_t *mb; | |
76 | ||
77 | mb = &pmb->mb; | |
78 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
79 | mb->mbxCommand = MBX_READ_NV; | |
80 | mb->mbxOwner = OWN_HOST; | |
81 | return; | |
82 | } | |
83 | ||
84 | /**********************************************/ | |
85 | /* lpfc_read_la Issue a READ LA */ | |
86 | /* mailbox command */ | |
87 | /**********************************************/ | |
88 | int | |
89 | lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp) | |
90 | { | |
91 | MAILBOX_t *mb; | |
92 | struct lpfc_sli *psli; | |
93 | ||
94 | psli = &phba->sli; | |
95 | mb = &pmb->mb; | |
96 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
97 | ||
98 | INIT_LIST_HEAD(&mp->list); | |
99 | mb->mbxCommand = MBX_READ_LA64; | |
100 | mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128; | |
101 | mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys); | |
102 | mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys); | |
103 | ||
104 | /* Save address for later completion and set the owner to host so that | |
105 | * the FW knows this mailbox is available for processing. | |
106 | */ | |
107 | pmb->context1 = (uint8_t *) mp; | |
108 | mb->mbxOwner = OWN_HOST; | |
2e0fef85 | 109 | return 0; |
dea3101e JB |
110 | } |
111 | ||
112 | /**********************************************/ | |
113 | /* lpfc_clear_la Issue a CLEAR LA */ | |
114 | /* mailbox command */ | |
115 | /**********************************************/ | |
116 | void | |
117 | lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
118 | { | |
119 | MAILBOX_t *mb; | |
120 | ||
121 | mb = &pmb->mb; | |
122 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
123 | ||
124 | mb->un.varClearLA.eventTag = phba->fc_eventTag; | |
125 | mb->mbxCommand = MBX_CLEAR_LA; | |
126 | mb->mbxOwner = OWN_HOST; | |
127 | return; | |
128 | } | |
129 | ||
130 | /**************************************************/ | |
131 | /* lpfc_config_link Issue a CONFIG LINK */ | |
132 | /* mailbox command */ | |
133 | /**************************************************/ | |
134 | void | |
135 | lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
136 | { | |
2e0fef85 | 137 | struct lpfc_vport *vport = phba->pport; |
dea3101e JB |
138 | MAILBOX_t *mb = &pmb->mb; |
139 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
140 | ||
141 | /* NEW_FEATURE | |
142 | * SLI-2, Coalescing Response Feature. | |
143 | */ | |
144 | if (phba->cfg_cr_delay) { | |
145 | mb->un.varCfgLnk.cr = 1; | |
146 | mb->un.varCfgLnk.ci = 1; | |
147 | mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay; | |
148 | mb->un.varCfgLnk.cr_count = phba->cfg_cr_count; | |
149 | } | |
150 | ||
2e0fef85 | 151 | mb->un.varCfgLnk.myId = vport->fc_myDID; |
dea3101e JB |
152 | mb->un.varCfgLnk.edtov = phba->fc_edtov; |
153 | mb->un.varCfgLnk.arbtov = phba->fc_arbtov; | |
154 | mb->un.varCfgLnk.ratov = phba->fc_ratov; | |
155 | mb->un.varCfgLnk.rttov = phba->fc_rttov; | |
156 | mb->un.varCfgLnk.altov = phba->fc_altov; | |
157 | mb->un.varCfgLnk.crtov = phba->fc_crtov; | |
158 | mb->un.varCfgLnk.citov = phba->fc_citov; | |
159 | ||
160 | if (phba->cfg_ack0) | |
161 | mb->un.varCfgLnk.ack0_enable = 1; | |
162 | ||
163 | mb->mbxCommand = MBX_CONFIG_LINK; | |
164 | mb->mbxOwner = OWN_HOST; | |
165 | return; | |
166 | } | |
167 | ||
168 | /**********************************************/ | |
169 | /* lpfc_init_link Issue an INIT LINK */ | |
170 | /* mailbox command */ | |
171 | /**********************************************/ | |
172 | void | |
173 | lpfc_init_link(struct lpfc_hba * phba, | |
174 | LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed) | |
175 | { | |
176 | lpfc_vpd_t *vpd; | |
177 | struct lpfc_sli *psli; | |
178 | MAILBOX_t *mb; | |
179 | ||
180 | mb = &pmb->mb; | |
181 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
182 | ||
183 | psli = &phba->sli; | |
184 | switch (topology) { | |
185 | case FLAGS_TOPOLOGY_MODE_LOOP_PT: | |
186 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; | |
187 | mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; | |
188 | break; | |
189 | case FLAGS_TOPOLOGY_MODE_PT_PT: | |
190 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; | |
191 | break; | |
192 | case FLAGS_TOPOLOGY_MODE_LOOP: | |
193 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP; | |
194 | break; | |
195 | case FLAGS_TOPOLOGY_MODE_PT_LOOP: | |
196 | mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT; | |
197 | mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER; | |
198 | break; | |
367c2713 JW |
199 | case FLAGS_LOCAL_LB: |
200 | mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB; | |
201 | break; | |
dea3101e JB |
202 | } |
203 | ||
4b0b91d4 JS |
204 | /* Enable asynchronous ABTS responses from firmware */ |
205 | mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT; | |
206 | ||
dea3101e JB |
207 | /* NEW_FEATURE |
208 | * Setting up the link speed | |
209 | */ | |
210 | vpd = &phba->vpd; | |
211 | if (vpd->rev.feaLevelHigh >= 0x02){ | |
2e0fef85 | 212 | switch (linkspeed){ |
dea3101e JB |
213 | case LINK_SPEED_1G: |
214 | case LINK_SPEED_2G: | |
215 | case LINK_SPEED_4G: | |
b87eab38 | 216 | case LINK_SPEED_8G: |
dea3101e JB |
217 | mb->un.varInitLnk.link_flags |= |
218 | FLAGS_LINK_SPEED; | |
219 | mb->un.varInitLnk.link_speed = linkspeed; | |
220 | break; | |
221 | case LINK_SPEED_AUTO: | |
222 | default: | |
223 | mb->un.varInitLnk.link_speed = | |
224 | LINK_SPEED_AUTO; | |
225 | break; | |
226 | } | |
227 | ||
228 | } | |
229 | else | |
230 | mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO; | |
231 | ||
232 | mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK; | |
233 | mb->mbxOwner = OWN_HOST; | |
234 | mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA; | |
235 | return; | |
236 | } | |
237 | ||
238 | /**********************************************/ | |
239 | /* lpfc_read_sparam Issue a READ SPARAM */ | |
240 | /* mailbox command */ | |
241 | /**********************************************/ | |
242 | int | |
243 | lpfc_read_sparam(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
244 | { | |
245 | struct lpfc_dmabuf *mp; | |
246 | MAILBOX_t *mb; | |
247 | struct lpfc_sli *psli; | |
248 | ||
249 | psli = &phba->sli; | |
250 | mb = &pmb->mb; | |
251 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
252 | ||
253 | mb->mbxOwner = OWN_HOST; | |
254 | ||
255 | /* Get a buffer to hold the HBAs Service Parameters */ | |
256 | ||
257 | if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) || | |
258 | ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { | |
c9475cb0 | 259 | kfree(mp); |
dea3101e JB |
260 | mb->mbxCommand = MBX_READ_SPARM64; |
261 | /* READ_SPARAM: no buffers */ | |
262 | lpfc_printf_log(phba, | |
263 | KERN_WARNING, | |
264 | LOG_MBOX, | |
265 | "%d:0301 READ_SPARAM: no buffers\n", | |
266 | phba->brd_no); | |
2e0fef85 | 267 | return 1; |
dea3101e JB |
268 | } |
269 | INIT_LIST_HEAD(&mp->list); | |
270 | mb->mbxCommand = MBX_READ_SPARM64; | |
271 | mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); | |
272 | mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys); | |
273 | mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys); | |
274 | ||
275 | /* save address for completion */ | |
276 | pmb->context1 = mp; | |
277 | ||
2e0fef85 | 278 | return 0; |
dea3101e JB |
279 | } |
280 | ||
281 | /********************************************/ | |
282 | /* lpfc_unreg_did Issue a UNREG_DID */ | |
283 | /* mailbox command */ | |
284 | /********************************************/ | |
285 | void | |
2e0fef85 | 286 | lpfc_unreg_did(struct lpfc_hba *phba, uint32_t did, LPFC_MBOXQ_t *pmb) |
dea3101e JB |
287 | { |
288 | MAILBOX_t *mb; | |
289 | ||
290 | mb = &pmb->mb; | |
291 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
292 | ||
293 | mb->un.varUnregDID.did = did; | |
294 | ||
295 | mb->mbxCommand = MBX_UNREG_D_ID; | |
296 | mb->mbxOwner = OWN_HOST; | |
297 | return; | |
298 | } | |
299 | ||
dea3101e JB |
300 | /**********************************************/ |
301 | /* lpfc_read_nv Issue a READ CONFIG */ | |
302 | /* mailbox command */ | |
303 | /**********************************************/ | |
304 | void | |
305 | lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
306 | { | |
307 | MAILBOX_t *mb; | |
308 | ||
309 | mb = &pmb->mb; | |
310 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
311 | ||
312 | mb->mbxCommand = MBX_READ_CONFIG; | |
313 | mb->mbxOwner = OWN_HOST; | |
314 | return; | |
315 | } | |
316 | ||
7bb3b137 JW |
317 | /*************************************************/ |
318 | /* lpfc_read_lnk_stat Issue a READ LINK STATUS */ | |
319 | /* mailbox command */ | |
320 | /*************************************************/ | |
321 | void | |
322 | lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
323 | { | |
324 | MAILBOX_t *mb; | |
325 | ||
326 | mb = &pmb->mb; | |
327 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
328 | ||
329 | mb->mbxCommand = MBX_READ_LNK_STAT; | |
330 | mb->mbxOwner = OWN_HOST; | |
331 | return; | |
332 | } | |
333 | ||
dea3101e JB |
334 | /********************************************/ |
335 | /* lpfc_reg_login Issue a REG_LOGIN */ | |
336 | /* mailbox command */ | |
337 | /********************************************/ | |
338 | int | |
2e0fef85 JS |
339 | lpfc_reg_login(struct lpfc_hba *phba, uint32_t did, uint8_t *param, |
340 | LPFC_MBOXQ_t *pmb, uint32_t flag) | |
dea3101e | 341 | { |
2e0fef85 | 342 | MAILBOX_t *mb = &pmb->mb; |
dea3101e JB |
343 | uint8_t *sparam; |
344 | struct lpfc_dmabuf *mp; | |
dea3101e | 345 | |
dea3101e JB |
346 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); |
347 | ||
348 | mb->un.varRegLogin.rpi = 0; | |
349 | mb->un.varRegLogin.did = did; | |
350 | mb->un.varWords[30] = flag; /* Set flag to issue action on cmpl */ | |
351 | ||
352 | mb->mbxOwner = OWN_HOST; | |
353 | ||
354 | /* Get a buffer to hold NPorts Service Parameters */ | |
355 | if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) || | |
356 | ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) { | |
c9475cb0 | 357 | kfree(mp); |
dea3101e JB |
358 | mb->mbxCommand = MBX_REG_LOGIN64; |
359 | /* REG_LOGIN: no buffers */ | |
360 | lpfc_printf_log(phba, | |
361 | KERN_WARNING, | |
362 | LOG_MBOX, | |
363 | "%d:0302 REG_LOGIN: no buffers Data x%x x%x\n", | |
364 | phba->brd_no, | |
365 | (uint32_t) did, (uint32_t) flag); | |
2e0fef85 | 366 | return 1; |
dea3101e JB |
367 | } |
368 | INIT_LIST_HEAD(&mp->list); | |
369 | sparam = mp->virt; | |
370 | ||
371 | /* Copy param's into a new buffer */ | |
372 | memcpy(sparam, param, sizeof (struct serv_parm)); | |
373 | ||
374 | /* save address for completion */ | |
375 | pmb->context1 = (uint8_t *) mp; | |
376 | ||
377 | mb->mbxCommand = MBX_REG_LOGIN64; | |
378 | mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm); | |
379 | mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys); | |
380 | mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys); | |
381 | ||
2e0fef85 | 382 | return 0; |
dea3101e JB |
383 | } |
384 | ||
385 | /**********************************************/ | |
386 | /* lpfc_unreg_login Issue a UNREG_LOGIN */ | |
387 | /* mailbox command */ | |
388 | /**********************************************/ | |
389 | void | |
2e0fef85 | 390 | lpfc_unreg_login(struct lpfc_hba *phba, uint32_t rpi, LPFC_MBOXQ_t * pmb) |
dea3101e JB |
391 | { |
392 | MAILBOX_t *mb; | |
393 | ||
394 | mb = &pmb->mb; | |
395 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
396 | ||
397 | mb->un.varUnregLogin.rpi = (uint16_t) rpi; | |
398 | mb->un.varUnregLogin.rsvd1 = 0; | |
399 | ||
400 | mb->mbxCommand = MBX_UNREG_LOGIN; | |
401 | mb->mbxOwner = OWN_HOST; | |
402 | return; | |
403 | } | |
404 | ||
405 | static void | |
406 | lpfc_config_pcb_setup(struct lpfc_hba * phba) | |
407 | { | |
408 | struct lpfc_sli *psli = &phba->sli; | |
409 | struct lpfc_sli_ring *pring; | |
410 | PCB_t *pcbp = &phba->slim2p->pcb; | |
411 | dma_addr_t pdma_addr; | |
412 | uint32_t offset; | |
2e0fef85 | 413 | uint32_t iocbCnt = 0; |
dea3101e JB |
414 | int i; |
415 | ||
dea3101e JB |
416 | pcbp->maxRing = (psli->num_rings - 1); |
417 | ||
dea3101e JB |
418 | for (i = 0; i < psli->num_rings; i++) { |
419 | pring = &psli->ring[i]; | |
2e0fef85 | 420 | |
dea3101e JB |
421 | /* A ring MUST have both cmd and rsp entries defined to be |
422 | valid */ | |
423 | if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) { | |
424 | pcbp->rdsc[i].cmdEntries = 0; | |
425 | pcbp->rdsc[i].rspEntries = 0; | |
426 | pcbp->rdsc[i].cmdAddrHigh = 0; | |
427 | pcbp->rdsc[i].rspAddrHigh = 0; | |
428 | pcbp->rdsc[i].cmdAddrLow = 0; | |
429 | pcbp->rdsc[i].rspAddrLow = 0; | |
430 | pring->cmdringaddr = NULL; | |
431 | pring->rspringaddr = NULL; | |
432 | continue; | |
433 | } | |
434 | /* Command ring setup for ring */ | |
435 | pring->cmdringaddr = | |
436 | (void *)&phba->slim2p->IOCBs[iocbCnt]; | |
437 | pcbp->rdsc[i].cmdEntries = pring->numCiocb; | |
438 | ||
439 | offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - | |
440 | (uint8_t *)phba->slim2p; | |
441 | pdma_addr = phba->slim2p_mapping + offset; | |
442 | pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr); | |
443 | pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr); | |
444 | iocbCnt += pring->numCiocb; | |
445 | ||
446 | /* Response ring setup for ring */ | |
447 | pring->rspringaddr = | |
448 | (void *)&phba->slim2p->IOCBs[iocbCnt]; | |
449 | ||
450 | pcbp->rdsc[i].rspEntries = pring->numRiocb; | |
451 | offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] - | |
452 | (uint8_t *)phba->slim2p; | |
453 | pdma_addr = phba->slim2p_mapping + offset; | |
454 | pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr); | |
455 | pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr); | |
456 | iocbCnt += pring->numRiocb; | |
457 | } | |
458 | } | |
459 | ||
460 | void | |
461 | lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
462 | { | |
2e0fef85 | 463 | MAILBOX_t *mb = &pmb->mb; |
dea3101e JB |
464 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); |
465 | mb->un.varRdRev.cv = 1; | |
466 | mb->mbxCommand = MBX_READ_REV; | |
467 | mb->mbxOwner = OWN_HOST; | |
468 | return; | |
469 | } | |
470 | ||
471 | void | |
472 | lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb) | |
473 | { | |
474 | int i; | |
475 | MAILBOX_t *mb = &pmb->mb; | |
476 | struct lpfc_sli *psli; | |
477 | struct lpfc_sli_ring *pring; | |
478 | ||
479 | memset(pmb, 0, sizeof (LPFC_MBOXQ_t)); | |
480 | ||
481 | mb->un.varCfgRing.ring = ring; | |
482 | mb->un.varCfgRing.maxOrigXchg = 0; | |
483 | mb->un.varCfgRing.maxRespXchg = 0; | |
484 | mb->un.varCfgRing.recvNotify = 1; | |
485 | ||
486 | psli = &phba->sli; | |
487 | pring = &psli->ring[ring]; | |
488 | mb->un.varCfgRing.numMask = pring->num_mask; | |
489 | mb->mbxCommand = MBX_CONFIG_RING; | |
490 | mb->mbxOwner = OWN_HOST; | |
491 | ||
492 | /* Is this ring configured for a specific profile */ | |
493 | if (pring->prt[0].profile) { | |
494 | mb->un.varCfgRing.profile = pring->prt[0].profile; | |
495 | return; | |
496 | } | |
497 | ||
498 | /* Otherwise we setup specific rctl / type masks for this ring */ | |
499 | for (i = 0; i < pring->num_mask; i++) { | |
500 | mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl; | |
501 | if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ) | |
502 | mb->un.varCfgRing.rrRegs[i].rmask = 0xff; | |
503 | else | |
504 | mb->un.varCfgRing.rrRegs[i].rmask = 0xfe; | |
505 | mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type; | |
506 | mb->un.varCfgRing.rrRegs[i].tmask = 0xff; | |
507 | } | |
508 | ||
509 | return; | |
510 | } | |
511 | ||
512 | void | |
513 | lpfc_config_port(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
514 | { | |
515 | MAILBOX_t *mb = &pmb->mb; | |
516 | dma_addr_t pdma_addr; | |
517 | uint32_t bar_low, bar_high; | |
518 | size_t offset; | |
4cc2da1d | 519 | struct lpfc_hgp hgp; |
dea3101e | 520 | void __iomem *to_slim; |
f91b392c | 521 | int i; |
dea3101e JB |
522 | |
523 | memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); | |
524 | mb->mbxCommand = MBX_CONFIG_PORT; | |
525 | mb->mbxOwner = OWN_HOST; | |
526 | ||
527 | mb->un.varCfgPort.pcbLen = sizeof(PCB_t); | |
528 | ||
529 | offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p; | |
530 | pdma_addr = phba->slim2p_mapping + offset; | |
531 | mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr); | |
532 | mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr); | |
533 | ||
534 | /* Now setup pcb */ | |
535 | phba->slim2p->pcb.type = TYPE_NATIVE_SLI2; | |
536 | phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2; | |
537 | ||
538 | /* Setup Mailbox pointers */ | |
539 | phba->slim2p->pcb.mailBoxSize = sizeof(MAILBOX_t); | |
540 | offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p; | |
541 | pdma_addr = phba->slim2p_mapping + offset; | |
542 | phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr); | |
543 | phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr); | |
544 | ||
545 | /* | |
546 | * Setup Host Group ring pointer. | |
547 | * | |
548 | * For efficiency reasons, the ring get/put pointers can be | |
549 | * placed in adapter memory (SLIM) rather than in host memory. | |
550 | * This allows firmware to avoid PCI reads/writes when updating | |
551 | * and checking pointers. | |
552 | * | |
553 | * The firmware recognizes the use of SLIM memory by comparing | |
554 | * the address of the get/put pointers structure with that of | |
555 | * the SLIM BAR (BAR0). | |
556 | * | |
557 | * Caution: be sure to use the PCI config space value of BAR0/BAR1 | |
558 | * (the hardware's view of the base address), not the OS's | |
559 | * value of pci_resource_start() as the OS value may be a cookie | |
560 | * for ioremap/iomap. | |
561 | */ | |
562 | ||
563 | ||
564 | pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low); | |
565 | pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high); | |
566 | ||
567 | ||
568 | /* mask off BAR0's flag bits 0 - 3 */ | |
569 | phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) + | |
570 | (SLIMOFF*sizeof(uint32_t)); | |
571 | if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64) | |
572 | phba->slim2p->pcb.hgpAddrHigh = bar_high; | |
573 | else | |
574 | phba->slim2p->pcb.hgpAddrHigh = 0; | |
575 | /* write HGP data to SLIM at the required longword offset */ | |
4cc2da1d | 576 | memset(&hgp, 0, sizeof(struct lpfc_hgp)); |
dea3101e | 577 | to_slim = phba->MBslimaddr + (SLIMOFF*sizeof (uint32_t)); |
f91b392c JSEC |
578 | |
579 | for (i=0; i < phba->sli.num_rings; i++) { | |
580 | lpfc_memcpy_to_slim(to_slim, &hgp, sizeof(struct lpfc_hgp)); | |
581 | to_slim += sizeof (struct lpfc_hgp); | |
582 | } | |
dea3101e JB |
583 | |
584 | /* Setup Port Group ring pointer */ | |
585 | offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port - | |
586 | (uint8_t *)phba->slim2p; | |
587 | pdma_addr = phba->slim2p_mapping + offset; | |
588 | phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr); | |
589 | phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr); | |
590 | ||
591 | /* Use callback routine to setp rings in the pcb */ | |
592 | lpfc_config_pcb_setup(phba); | |
593 | ||
594 | /* special handling for LC HBAs */ | |
595 | if (lpfc_is_LC_HBA(phba->pcidev->device)) { | |
596 | uint32_t hbainit[5]; | |
597 | ||
598 | lpfc_hba_init(phba, hbainit); | |
599 | ||
600 | memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20); | |
601 | } | |
602 | ||
603 | /* Swap PCB if needed */ | |
604 | lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb, | |
605 | sizeof (PCB_t)); | |
606 | ||
607 | lpfc_printf_log(phba, KERN_INFO, LOG_INIT, | |
608 | "%d:0405 Service Level Interface (SLI) 2 selected\n", | |
609 | phba->brd_no); | |
610 | } | |
611 | ||
41415862 JW |
612 | void |
613 | lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb) | |
614 | { | |
615 | MAILBOX_t *mb = &pmb->mb; | |
616 | ||
617 | memset(pmb, 0, sizeof(LPFC_MBOXQ_t)); | |
618 | mb->mbxCommand = MBX_KILL_BOARD; | |
619 | mb->mbxOwner = OWN_HOST; | |
620 | return; | |
621 | } | |
622 | ||
dea3101e JB |
623 | void |
624 | lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq) | |
625 | { | |
626 | struct lpfc_sli *psli; | |
627 | ||
628 | psli = &phba->sli; | |
629 | ||
630 | list_add_tail(&mbq->list, &psli->mboxq); | |
631 | ||
632 | psli->mboxq_cnt++; | |
633 | ||
634 | return; | |
635 | } | |
636 | ||
637 | LPFC_MBOXQ_t * | |
638 | lpfc_mbox_get(struct lpfc_hba * phba) | |
639 | { | |
640 | LPFC_MBOXQ_t *mbq = NULL; | |
641 | struct lpfc_sli *psli = &phba->sli; | |
642 | ||
2e0fef85 | 643 | list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, list); |
dea3101e JB |
644 | if (mbq) { |
645 | psli->mboxq_cnt--; | |
646 | } | |
647 | ||
648 | return mbq; | |
649 | } | |
a309a6b6 JS |
650 | |
651 | int | |
652 | lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd) | |
653 | { | |
654 | switch (cmd) { | |
655 | case MBX_WRITE_NV: /* 0x03 */ | |
656 | case MBX_UPDATE_CFG: /* 0x1B */ | |
657 | case MBX_DOWN_LOAD: /* 0x1C */ | |
658 | case MBX_DEL_LD_ENTRY: /* 0x1D */ | |
659 | case MBX_LOAD_AREA: /* 0x81 */ | |
660 | case MBX_FLASH_WR_ULA: /* 0x98 */ | |
661 | case MBX_LOAD_EXP_ROM: /* 0x9C */ | |
662 | return LPFC_MBOX_TMO_FLASH_CMD; | |
663 | } | |
664 | return LPFC_MBOX_TMO; | |
665 | } |