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scsi: lpfc: NVME Target: Add debugfs support
[mirror_ubuntu-artful-kernel.git] / drivers / scsi / lpfc / lpfc_sli4.h
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da0436e9
JS		 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
51f4ca3c 4 * Copyright (C) 2009-2016 Emulex. All rights reserved. *
da0436e9
JS		 5 * EMULEX and SLI are trademarks of Emulex. *
6 * www.emulex.com *
7 * *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
20
21#define LPFC_ACTIVE_MBOX_WAIT_CNT 100
5af5eee7
JS		 22#define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000
23#define LPFC_XRI_EXCH_BUSY_WAIT_T1 10
24#define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000
da0436e9 25#define LPFC_RELEASE_NOTIFICATION_INTERVAL 32
da0436e9 26#define LPFC_RPI_LOW_WATER_MARK 10
ecfd03c6 27
a93ff37a
JS		 28#define LPFC_UNREG_FCF 1
29#define LPFC_SKIP_UNREG_FCF 0
30
ecfd03c6
JS		 31/* Amount of time in seconds for waiting FCF rediscovery to complete */
32#define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */
33
da0436e9
JS		 34/* Number of SGL entries can be posted in a 4KB nonembedded mbox command */
35#define LPFC_NEMBED_MBOX_SGL_CNT 254
36
67d12733 37/* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */
895427bd
JS		 38#define LPFC_HBA_IO_CHAN_MIN 0
39#define LPFC_HBA_IO_CHAN_MAX 32
40#define LPFC_FCP_IO_CHAN_DEF 4
41#define LPFC_NVME_IO_CHAN_DEF 0
da0436e9 42
1ba981fd
JS		 43/* Number of channels used for Flash Optimized Fabric (FOF) operations */
44
45#define LPFC_FOF_IO_CHAN_NUM 1
46
da0436e9
JS		 47/*
48 * Provide the default FCF Record attributes used by the driver
49 * when nonFIP mode is configured and there is no other default
50 * FCF Record attributes.
51 */
52#define LPFC_FCOE_FCF_DEF_INDEX 0
53#define LPFC_FCOE_FCF_GET_FIRST 0xFFFF
54#define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF
55
dbb6b3ab
JS		 56#define LPFC_FCOE_NULL_VID 0xFFF
57#define LPFC_FCOE_IGNORE_VID 0xFFFF
58
da0436e9
JS		 59/* First 3 bytes of default FCF MAC is specified by FC_MAP */
60#define LPFC_FCOE_FCF_MAC3 0xFF
61#define LPFC_FCOE_FCF_MAC4 0xFF
62#define LPFC_FCOE_FCF_MAC5 0xFE
63#define LPFC_FCOE_FCF_MAP0 0x0E
64#define LPFC_FCOE_FCF_MAP1 0xFC
65#define LPFC_FCOE_FCF_MAP2 0x00
98fc5dd9 66#define LPFC_FCOE_MAX_RCV_SIZE 0x800
da0436e9
JS		 67#define LPFC_FCOE_FKA_ADV_PER 0
68#define LPFC_FCOE_FIP_PRIORITY 0x80
69
6669f9bb
JS		 70#define sli4_sid_from_fc_hdr(fc_hdr) \
71 ((fc_hdr)->fh_s_id[0] << 16 | \
72 (fc_hdr)->fh_s_id[1] << 8 | \
73 (fc_hdr)->fh_s_id[2])
74
939723a4
JS		 75#define sli4_did_from_fc_hdr(fc_hdr) \
76 ((fc_hdr)->fh_d_id[0] << 16 | \
77 (fc_hdr)->fh_d_id[1] << 8 | \
78 (fc_hdr)->fh_d_id[2])
79
5ffc266e
JS		 80#define sli4_fctl_from_fc_hdr(fc_hdr) \
81 ((fc_hdr)->fh_f_ctl[0] << 16 | \
82 (fc_hdr)->fh_f_ctl[1] << 8 | \
83 (fc_hdr)->fh_f_ctl[2])
84
939723a4
JS		 85#define sli4_type_from_fc_hdr(fc_hdr) \
86 ((fc_hdr)->fh_type)
87
88a2cfbb
JS		 88#define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000
89
c71ab861
JS		 90#define INT_FW_UPGRADE 0
91#define RUN_FW_UPGRADE 1
92
da0436e9
JS		 93enum lpfc_sli4_queue_type {
94 LPFC_EQ,
95 LPFC_GCQ,
96 LPFC_MCQ,
97 LPFC_WCQ,
98 LPFC_RCQ,
99 LPFC_MQ,
100 LPFC_WQ,
101 LPFC_HRQ,
102 LPFC_DRQ
103};
104
105/* The queue sub-type defines the functional purpose of the queue */
106enum lpfc_sli4_queue_subtype {
107 LPFC_NONE,
108 LPFC_MBOX,
109 LPFC_FCP,
110 LPFC_ELS,
895427bd 111 LPFC_NVME,
f358dd0c 112 LPFC_NVMET,
895427bd 113 LPFC_NVME_LS,
da0436e9
JS		 114 LPFC_USOL
115};
116
117union sli4_qe {
118 void *address;
119 struct lpfc_eqe *eqe;
120 struct lpfc_cqe *cqe;
121 struct lpfc_mcqe *mcqe;
122 struct lpfc_wcqe_complete *wcqe_complete;
123 struct lpfc_wcqe_release *wcqe_release;
124 struct sli4_wcqe_xri_aborted *wcqe_xri_aborted;
125 struct lpfc_rcqe_complete *rcqe_complete;
126 struct lpfc_mqe *mqe;
127 union lpfc_wqe *wqe;
0c651878 128 union lpfc_wqe128 *wqe128;
da0436e9
JS		 129 struct lpfc_rqe *rqe;
130};
131
895427bd
JS		 132/* RQ buffer list */
133struct lpfc_rqb {
134 uint16_t entry_count; /* Current number of RQ slots */
135 uint16_t buffer_count; /* Current number of buffers posted */
136 struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */
137 /* Callback for HBQ buffer allocation */
138 struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *);
139 /* Callback for HBQ buffer free */
140 void (*rqb_free_buffer)(struct lpfc_hba *,
141 struct rqb_dmabuf *);
142};
143
da0436e9
JS		 144struct lpfc_queue {
145 struct list_head list;
895427bd 146 struct list_head wq_list;
da0436e9
JS		 147 enum lpfc_sli4_queue_type type;
148 enum lpfc_sli4_queue_subtype subtype;
149 struct lpfc_hba *phba;
150 struct list_head child_list;
895427bd
JS		 151 struct list_head page_list;
152 struct list_head sgl_list;
da0436e9
JS		 153 uint32_t entry_count; /* Number of entries to support on the queue */
154 uint32_t entry_size; /* Size of each queue entry. */
73d91e50
JS		 155 uint32_t entry_repost; /* Count of entries before doorbell is rung */
156#define LPFC_QUEUE_MIN_REPOST 8
da0436e9 157 uint32_t queue_id; /* Queue ID assigned by the hardware */
2a622bfb 158 uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */
da0436e9 159 uint32_t page_count; /* Number of pages allocated for this queue */
da0436e9
JS		 160 uint32_t host_index; /* The host's index for putting or getting */
161 uint32_t hba_index; /* The last known hba index for get or put */
b84daac9 162
2a76a283 163 struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */
895427bd 164 struct lpfc_rqb *rqbp; /* ptr to RQ buffers */
2a76a283 165
895427bd 166 uint16_t sgl_list_cnt;
962bc51b
JS		 167 uint16_t db_format;
168#define LPFC_DB_RING_FORMAT 0x01
169#define LPFC_DB_LIST_FORMAT 0x02
170 void __iomem *db_regaddr;
b84daac9
JS		 171 /* For q stats */
172 uint32_t q_cnt_1;
173 uint32_t q_cnt_2;
174 uint32_t q_cnt_3;
175 uint64_t q_cnt_4;
176/* defines for EQ stats */
177#define EQ_max_eqe q_cnt_1
178#define EQ_no_entry q_cnt_2
179#define EQ_badstate q_cnt_3
180#define EQ_processed q_cnt_4
181
182/* defines for CQ stats */
183#define CQ_mbox q_cnt_1
184#define CQ_max_cqe q_cnt_1
185#define CQ_release_wqe q_cnt_2
186#define CQ_xri_aborted q_cnt_3
187#define CQ_wq q_cnt_4
188
189/* defines for WQ stats */
190#define WQ_overflow q_cnt_1
191#define WQ_posted q_cnt_4
192
193/* defines for RQ stats */
194#define RQ_no_posted_buf q_cnt_1
195#define RQ_no_buf_found q_cnt_2
196#define RQ_buf_trunc q_cnt_3
197#define RQ_rcv_buf q_cnt_4
198
895427bd
JS		 199 uint64_t isr_timestamp;
200 struct lpfc_queue *assoc_qp;
da0436e9
JS		 201 union sli4_qe qe[1]; /* array to index entries (must be last) */
202};
203
da0436e9 204struct lpfc_sli4_link {
8b68cd52 205 uint16_t speed;
da0436e9
JS		 206 uint8_t duplex;
207 uint8_t status;
70f3c073
JS		 208 uint8_t type;
209 uint8_t number;
da0436e9 210 uint8_t fault;
65467b6b 211 uint16_t logical_speed;
70f3c073 212 uint16_t topology;
da0436e9
JS		 213};
214
ecfd03c6
JS		 215struct lpfc_fcf_rec {
216 uint8_t fabric_name[8];
217 uint8_t switch_name[8];
da0436e9
JS		 218 uint8_t mac_addr[6];
219 uint16_t fcf_indx;
ecfd03c6
JS		 220 uint32_t priority;
221 uint16_t vlan_id;
222 uint32_t addr_mode;
223 uint32_t flag;
224#define BOOT_ENABLE 0x01
225#define RECORD_VALID 0x02
226};
227
7d791df7
JS		 228struct lpfc_fcf_pri_rec {
229 uint16_t fcf_index;
230#define LPFC_FCF_ON_PRI_LIST 0x0001
231#define LPFC_FCF_FLOGI_FAILED 0x0002
232 uint16_t flag;
233 uint32_t priority;
234};
235
236struct lpfc_fcf_pri {
237 struct list_head list;
238 struct lpfc_fcf_pri_rec fcf_rec;
239};
240
241/*
242 * Maximum FCF table index, it is for driver internal book keeping, it
243 * just needs to be no less than the supported HBA's FCF table size.
244 */
245#define LPFC_SLI4_FCF_TBL_INDX_MAX 32
246
ecfd03c6 247struct lpfc_fcf {
da0436e9
JS		 248 uint16_t fcfi;
249 uint32_t fcf_flag;
250#define FCF_AVAILABLE 0x01 /* FCF available for discovery */
251#define FCF_REGISTERED 0x02 /* FCF registered with FW */
ecfd03c6
JS		 252#define FCF_SCAN_DONE 0x04 /* FCF table scan done */
253#define FCF_IN_USE 0x08 /* Atleast one discovery completed */
0c9ab6f5
JS		 254#define FCF_INIT_DISC 0x10 /* Initial FCF discovery */
255#define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */
256#define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */
257#define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC)
258#define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */
259#define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */
260#define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */
a93ff37a 261#define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT)
da0436e9 262 uint32_t addr_mode;
999d813f 263 uint32_t eligible_fcf_cnt;
ecfd03c6
JS		 264 struct lpfc_fcf_rec current_rec;
265 struct lpfc_fcf_rec failover_rec;
7d791df7
JS		 266 struct list_head fcf_pri_list;
267 struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX];
268 uint32_t current_fcf_scan_pri;
ecfd03c6 269 struct timer_list redisc_wait;
0c9ab6f5 270 unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */
da0436e9
JS		 271};
272
0c9ab6f5 273
da0436e9
JS		 274#define LPFC_REGION23_SIGNATURE "RG23"
275#define LPFC_REGION23_VERSION 1
276#define LPFC_REGION23_LAST_REC 0xff
a0c87cbd
JS		 277#define DRIVER_SPECIFIC_TYPE 0xA2
278#define LINUX_DRIVER_ID 0x20
279#define PORT_STE_TYPE 0x1
280
da0436e9
JS		 281struct lpfc_fip_param_hdr {
282 uint8_t type;
283#define FCOE_PARAM_TYPE 0xA0
284 uint8_t length;
285#define FCOE_PARAM_LENGTH 2
286 uint8_t parm_version;
287#define FIPP_VERSION 0x01
288 uint8_t parm_flags;
289#define lpfc_fip_param_hdr_fipp_mode_SHIFT 6
290#define lpfc_fip_param_hdr_fipp_mode_MASK 0x3
291#define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags
6a9c52cf 292#define FIPP_MODE_ON 0x1
da0436e9
JS		 293#define FIPP_MODE_OFF 0x0
294#define FIPP_VLAN_VALID 0x1
295};
296
297struct lpfc_fcoe_params {
298 uint8_t fc_map[3];
299 uint8_t reserved1;
300 uint16_t vlan_tag;
301 uint8_t reserved[2];
302};
303
304struct lpfc_fcf_conn_hdr {
305 uint8_t type;
306#define FCOE_CONN_TBL_TYPE 0xA1
307 uint8_t length; /* words */
308 uint8_t reserved[2];
309};
310
311struct lpfc_fcf_conn_rec {
312 uint16_t flags;
313#define FCFCNCT_VALID 0x0001
314#define FCFCNCT_BOOT 0x0002
315#define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */
316#define FCFCNCT_FBNM_VALID 0x0008
317#define FCFCNCT_SWNM_VALID 0x0010
318#define FCFCNCT_VLAN_VALID 0x0020
319#define FCFCNCT_AM_VALID 0x0040
320#define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */
321#define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */
322
323 uint16_t vlan_tag;
324 uint8_t fabric_name[8];
325 uint8_t switch_name[8];
326};
327
328struct lpfc_fcf_conn_entry {
329 struct list_head list;
330 struct lpfc_fcf_conn_rec conn_rec;
331};
332
333/*
334 * Define the host's bootstrap mailbox. This structure contains
335 * the member attributes needed to create, use, and destroy the
336 * bootstrap mailbox region.
337 *
338 * The macro definitions for the bmbx data structure are defined
339 * in lpfc_hw4.h with the register definition.
340 */
341struct lpfc_bmbx {
342 struct lpfc_dmabuf *dmabuf;
343 struct dma_address dma_address;
344 void *avirt;
345 dma_addr_t aphys;
346 uint32_t bmbx_size;
347};
348
349#define LPFC_EQE_SIZE LPFC_EQE_SIZE_4
350
351#define LPFC_EQE_SIZE_4B 4
352#define LPFC_EQE_SIZE_16B 16
353#define LPFC_CQE_SIZE 16
354#define LPFC_WQE_SIZE 64
0c651878 355#define LPFC_WQE128_SIZE 128
da0436e9
JS		 356#define LPFC_MQE_SIZE 256
357#define LPFC_RQE_SIZE 8
358
359#define LPFC_EQE_DEF_COUNT 1024
ff78d8f9 360#define LPFC_CQE_DEF_COUNT 1024
f1126688 361#define LPFC_WQE_DEF_COUNT 256
0c651878 362#define LPFC_WQE128_DEF_COUNT 128
895427bd 363#define LPFC_WQE128_MAX_COUNT 256
da0436e9
JS		 364#define LPFC_MQE_DEF_COUNT 16
365#define LPFC_RQE_DEF_COUNT 512
366
367#define LPFC_QUEUE_NOARM false
368#define LPFC_QUEUE_REARM true
369
370
371/*
372 * SLI4 CT field defines
373 */
374#define SLI4_CT_RPI 0
375#define SLI4_CT_VPI 1
376#define SLI4_CT_VFI 2
377#define SLI4_CT_FCFI 3
378
da0436e9
JS		 379/*
380 * SLI4 specific data structures
381 */
382struct lpfc_max_cfg_param {
383 uint16_t max_xri;
384 uint16_t xri_base;
385 uint16_t xri_used;
386 uint16_t max_rpi;
387 uint16_t rpi_base;
388 uint16_t rpi_used;
389 uint16_t max_vpi;
390 uint16_t vpi_base;
391 uint16_t vpi_used;
392 uint16_t max_vfi;
393 uint16_t vfi_base;
394 uint16_t vfi_used;
395 uint16_t max_fcfi;
da0436e9
JS		 396 uint16_t fcfi_used;
397 uint16_t max_eq;
398 uint16_t max_rq;
399 uint16_t max_cq;
400 uint16_t max_wq;
401};
402
403struct lpfc_hba;
404/* SLI4 HBA multi-fcp queue handler struct */
895427bd 405struct lpfc_hba_eq_hdl {
da0436e9
JS		 406 uint32_t idx;
407 struct lpfc_hba *phba;
895427bd
JS		 408 atomic_t hba_eq_in_use;
409 struct cpumask *cpumask;
410 /* CPU affinitsed to or 0xffffffff if multiple */
411 uint32_t cpu;
412#define LPFC_MULTI_CPU_AFFINITY 0xffffffff
da0436e9
JS		 413};
414
28baac74
JS		 415/* Port Capabilities for SLI4 Parameters */
416struct lpfc_pc_sli4_params {
417 uint32_t supported;
418 uint32_t if_type;
419 uint32_t sli_rev;
420 uint32_t sli_family;
421 uint32_t featurelevel_1;
422 uint32_t featurelevel_2;
423 uint32_t proto_types;
424#define LPFC_SLI4_PROTO_FCOE 0x0000001
425#define LPFC_SLI4_PROTO_FC 0x0000002
426#define LPFC_SLI4_PROTO_NIC 0x0000004
427#define LPFC_SLI4_PROTO_ISCSI 0x0000008
428#define LPFC_SLI4_PROTO_RDMA 0x0000010
429 uint32_t sge_supp_len;
430 uint32_t if_page_sz;
431 uint32_t rq_db_window;
432 uint32_t loopbk_scope;
1ba981fd 433 uint32_t oas_supported;
28baac74
JS		 434 uint32_t eq_pages_max;
435 uint32_t eqe_size;
436 uint32_t cq_pages_max;
437 uint32_t cqe_size;
438 uint32_t mq_pages_max;
439 uint32_t mqe_size;
440 uint32_t mq_elem_cnt;
441 uint32_t wq_pages_max;
442 uint32_t wqe_size;
443 uint32_t rq_pages_max;
444 uint32_t rqe_size;
445 uint32_t hdr_pages_max;
446 uint32_t hdr_size;
447 uint32_t hdr_pp_align;
448 uint32_t sgl_pages_max;
449 uint32_t sgl_pp_align;
fedd3b7b
JS		 450 uint8_t cqv;
451 uint8_t mqv;
452 uint8_t wqv;
453 uint8_t rqv;
0c651878
JS		 454 uint8_t wqsize;
455#define LPFC_WQ_SZ64_SUPPORT 1
456#define LPFC_WQ_SZ128_SUPPORT 2
895427bd 457 uint8_t wqpcnt;
28baac74
JS		 458};
459
912e3acd
JS		 460struct lpfc_iov {
461 uint32_t pf_number;
462 uint32_t vf_number;
463};
464
cd1c8301
JS		 465struct lpfc_sli4_lnk_info {
466 uint8_t lnk_dv;
467#define LPFC_LNK_DAT_INVAL 0
468#define LPFC_LNK_DAT_VAL 1
469 uint8_t lnk_tp;
470#define LPFC_LNK_GE 0x0 /* FCoE */
471#define LPFC_LNK_FC 0x1 /* FC */
472 uint8_t lnk_no;
448193b5 473 uint8_t optic_state;
cd1c8301
JS		 474};
475
895427bd 476#define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \
1ba981fd 477 LPFC_FOF_IO_CHAN_NUM)
4305f183
JS		 478#define LPFC_SLI4_HANDLER_NAME_SZ 16
479
7bb03bbf
JS		 480/* Used for IRQ vector to CPU mapping */
481struct lpfc_vector_map_info {
482 uint16_t phys_id;
483 uint16_t core_id;
484 uint16_t irq;
485 uint16_t channel_id;
7bb03bbf
JS		 486};
487#define LPFC_VECTOR_MAP_EMPTY 0xffff
7bb03bbf 488
da0436e9
JS		 489/* SLI4 HBA data structure entries */
490struct lpfc_sli4_hba {
491 void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for
492 PCI BAR0, config space registers */
493 void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for
494 PCI BAR1, control registers */
495 void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for
496 PCI BAR2, doorbell registers */
2fcee4bf
JS		 497 union {
498 struct {
499 /* IF Type 0, BAR 0 PCI cfg space reg mem map */
500 void __iomem *UERRLOregaddr;
501 void __iomem *UERRHIregaddr;
502 void __iomem *UEMASKLOregaddr;
503 void __iomem *UEMASKHIregaddr;
504 } if_type0;
505 struct {
506 /* IF Type 2, BAR 0 PCI cfg space reg mem map. */
507 void __iomem *STATUSregaddr;
508 void __iomem *CTRLregaddr;
509 void __iomem *ERR1regaddr;
2e90f4b5
JS		 510#define SLIPORT_ERR1_REG_ERR_CODE_1 0x1
511#define SLIPORT_ERR1_REG_ERR_CODE_2 0x2
2fcee4bf 512 void __iomem *ERR2regaddr;
2e90f4b5
JS		 513#define SLIPORT_ERR2_REG_FW_RESTART 0x0
514#define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1
515#define SLIPORT_ERR2_REG_FORCED_DUMP 0x2
516#define SLIPORT_ERR2_REG_FAILURE_EQ 0x3
517#define SLIPORT_ERR2_REG_FAILURE_CQ 0x4
518#define SLIPORT_ERR2_REG_FAILURE_BUS 0x5
519#define SLIPORT_ERR2_REG_FAILURE_RQ 0x6
2fcee4bf
JS		 520 } if_type2;
521 } u;
522
523 /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */
524 void __iomem *PSMPHRregaddr;
525
526 /* Well-known SLI INTF register memory map. */
527 void __iomem *SLIINTFregaddr;
528
529 /* IF type 0, BAR 1 function CSR register memory map */
530 void __iomem *ISRregaddr; /* HST_ISR register */
531 void __iomem *IMRregaddr; /* HST_IMR register */
532 void __iomem *ISCRregaddr; /* HST_ISCR register */
533 /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */
534 void __iomem *RQDBregaddr; /* RQ_DOORBELL register */
535 void __iomem *WQDBregaddr; /* WQ_DOORBELL register */
536 void __iomem *EQCQDBregaddr; /* EQCQ_DOORBELL register */
537 void __iomem *MQDBregaddr; /* MQ_DOORBELL register */
538 void __iomem *BMBXregaddr; /* BootStrap MBX register */
da0436e9 539
a747c9ce
JS		 540 uint32_t ue_mask_lo;
541 uint32_t ue_mask_hi;
65791f1f
JS		 542 uint32_t ue_to_sr;
543 uint32_t ue_to_rp;
28baac74
JS		 544 struct lpfc_register sli_intf;
545 struct lpfc_pc_sli4_params pc_sli4_params;
1ba981fd 546 uint8_t handler_name[LPFC_SLI4_HANDLER_CNT][LPFC_SLI4_HANDLER_NAME_SZ];
895427bd 547 struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */
67d12733 548
da0436e9 549 /* Pointers to the constructed SLI4 queues */
895427bd
JS		 550 struct lpfc_queue **hba_eq; /* Event queues for HBA */
551 struct lpfc_queue **fcp_cq; /* Fast-path FCP compl queue */
552 struct lpfc_queue **nvme_cq; /* Fast-path NVME compl queue */
2d7dbc4c
JS		 553 struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */
554 struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */
555 struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */
895427bd
JS		 556 struct lpfc_queue **fcp_wq; /* Fast-path FCP work queue */
557 struct lpfc_queue **nvme_wq; /* Fast-path NVME work queue */
67d12733 558 uint16_t *fcp_cq_map;
895427bd
JS		 559 uint16_t *nvme_cq_map;
560 struct list_head lpfc_wq_list;
67d12733
JS		 561
562 struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */
563 struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */
895427bd 564 struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */
da0436e9
JS		 565 struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */
566 struct lpfc_queue *els_wq; /* Slow-path ELS work queue */
895427bd 567 struct lpfc_queue *nvmels_wq; /* NVME LS work queue */
da0436e9
JS		 568 struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */
569 struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */
da0436e9 570
895427bd
JS		 571 struct lpfc_name wwnn;
572 struct lpfc_name wwpn;
573
9a86ed48 574 uint32_t fw_func_mode; /* FW function protocol mode */
962bc51b
JS		 575 uint32_t ulp0_mode; /* ULP0 protocol mode */
576 uint32_t ulp1_mode; /* ULP1 protocol mode */
577
1ba981fd
JS		 578 struct lpfc_queue *fof_eq; /* Flash Optimized Fabric Event queue */
579
580 /* Optimized Access Storage specific queues/structures */
581
582 struct lpfc_queue *oas_cq; /* OAS completion queue */
583 struct lpfc_queue *oas_wq; /* OAS Work queue */
584 struct lpfc_sli_ring *oas_ring;
585 uint64_t oas_next_lun;
586 uint8_t oas_next_tgt_wwpn[8];
587 uint8_t oas_next_vpt_wwpn[8];
588
da0436e9
JS		 589 /* Setup information for various queue parameters */
590 int eq_esize;
591 int eq_ecount;
592 int cq_esize;
593 int cq_ecount;
594 int wq_esize;
595 int wq_ecount;
596 int mq_esize;
597 int mq_ecount;
598 int rq_esize;
599 int rq_ecount;
600#define LPFC_SP_EQ_MAX_INTR_SEC 10000
601#define LPFC_FP_EQ_MAX_INTR_SEC 10000
602
603 uint32_t intr_enable;
604 struct lpfc_bmbx bmbx;
605 struct lpfc_max_cfg_param max_cfg_param;
6d368e53
JS		 606 uint16_t extents_in_use; /* must allocate resource extents. */
607 uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */
da0436e9
JS		 608 uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */
609 uint16_t next_rpi;
895427bd
JS		 610 uint16_t nvme_xri_max;
611 uint16_t nvme_xri_cnt;
612 uint16_t nvme_xri_start;
da0436e9
JS		 613 uint16_t scsi_xri_max;
614 uint16_t scsi_xri_cnt;
6d368e53 615 uint16_t scsi_xri_start;
895427bd 616 uint16_t els_xri_cnt;
f358dd0c 617 uint16_t nvmet_xri_cnt;
895427bd 618 struct list_head lpfc_els_sgl_list;
da0436e9 619 struct list_head lpfc_abts_els_sgl_list;
f358dd0c
JS		 620 struct list_head lpfc_nvmet_sgl_list;
621 struct list_head lpfc_abts_nvmet_sgl_list;
da0436e9 622 struct list_head lpfc_abts_scsi_buf_list;
895427bd 623 struct list_head lpfc_abts_nvme_buf_list;
da0436e9
JS		 624 struct lpfc_sglq **lpfc_sglq_active_list;
625 struct list_head lpfc_rpi_hdr_list;
626 unsigned long *rpi_bmask;
6d368e53 627 uint16_t *rpi_ids;
da0436e9 628 uint16_t rpi_count;
6d368e53
JS		 629 struct list_head lpfc_rpi_blk_list;
630 unsigned long *xri_bmask;
631 uint16_t *xri_ids;
6d368e53
JS		 632 struct list_head lpfc_xri_blk_list;
633 unsigned long *vfi_bmask;
634 uint16_t *vfi_ids;
635 uint16_t vfi_count;
636 struct list_head lpfc_vfi_blk_list;
da0436e9 637 struct lpfc_sli4_flags sli4_flags;
45ed1190 638 struct list_head sp_queue_event;
da0436e9
JS		 639 struct list_head sp_cqe_event_pool;
640 struct list_head sp_asynce_work_queue;
641 struct list_head sp_fcp_xri_aborted_work_queue;
642 struct list_head sp_els_xri_aborted_work_queue;
643 struct list_head sp_unsol_work_queue;
644 struct lpfc_sli4_link link_state;
cd1c8301
JS		 645 struct lpfc_sli4_lnk_info lnk_info;
646 uint32_t pport_name_sta;
647#define LPFC_SLI4_PPNAME_NON 0
648#define LPFC_SLI4_PPNAME_GET 1
912e3acd 649 struct lpfc_iov iov;
895427bd 650 spinlock_t abts_nvme_buf_list_lock; /* list of aborted SCSI IOs */
da0436e9 651 spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */
895427bd 652 spinlock_t sgl_list_lock; /* list of aborted els IOs */
f358dd0c 653 spinlock_t nvmet_io_lock;
8b017a30 654 uint32_t physical_port;
7bb03bbf
JS		 655
656 /* CPU to vector mapping information */
657 struct lpfc_vector_map_info *cpu_map;
658 uint16_t num_online_cpu;
659 uint16_t num_present_cpu;
76fd07a6 660 uint16_t curr_disp_cpu;
2d7dbc4c
JS		 661
662 uint16_t nvmet_mrq_post_idx;
da0436e9
JS		 663};
664
665enum lpfc_sge_type {
666 GEN_BUFF_TYPE,
895427bd 667 SCSI_BUFF_TYPE,
f358dd0c 668 NVMET_BUFF_TYPE
da0436e9
JS		 669};
670
0f65ff68
JS		 671enum lpfc_sgl_state {
672 SGL_FREED,
673 SGL_ALLOCATED,
674 SGL_XRI_ABORTED
675};
676
da0436e9
JS		 677struct lpfc_sglq {
678 /* lpfc_sglqs are used in double linked lists */
679 struct list_head list;
680 struct list_head clist;
681 enum lpfc_sge_type buff_type; /* is this a scsi sgl */
0f65ff68 682 enum lpfc_sgl_state state;
19ca7609 683 struct lpfc_nodelist *ndlp; /* ndlp associated with IO */
da0436e9 684 uint16_t iotag; /* pre-assigned IO tag */
6d368e53 685 uint16_t sli4_lxritag; /* logical pre-assigned xri. */
da0436e9
JS		 686 uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */
687 struct sli4_sge *sgl; /* pre-assigned SGL */
688 void *virt; /* virtual address. */
689 dma_addr_t phys; /* physical address */
690};
691
692struct lpfc_rpi_hdr {
693 struct list_head list;
694 uint32_t len;
695 struct lpfc_dmabuf *dmabuf;
696 uint32_t page_count;
697 uint32_t start_rpi;
698};
699
6d368e53
JS		 700struct lpfc_rsrc_blks {
701 struct list_head list;
702 uint16_t rsrc_start;
703 uint16_t rsrc_size;
704 uint16_t rsrc_used;
705};
706
86478875
JS		 707struct lpfc_rdp_context {
708 struct lpfc_nodelist *ndlp;
709 uint16_t ox_id;
710 uint16_t rx_id;
711 READ_LNK_VAR link_stat;
712 uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE];
713 uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE];
714 void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int);
715};
716
8b017a30
JS		 717struct lpfc_lcb_context {
718 uint8_t sub_command;
719 uint8_t type;
720 uint8_t frequency;
721 uint16_t ox_id;
722 uint16_t rx_id;
723 struct lpfc_nodelist *ndlp;
724};
725
726
da0436e9
JS		 727/*
728 * SLI4 specific function prototypes
729 */
730int lpfc_pci_function_reset(struct lpfc_hba *);
73d91e50 731int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *);
da0436e9 732int lpfc_sli4_hba_setup(struct lpfc_hba *);
da0436e9
JS		 733int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t,
734 uint8_t, uint32_t, bool);
735void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *);
736void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t);
737void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t,
738 struct lpfc_mbx_sge *);
0c9ab6f5
JS		 739int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *,
740 uint16_t);
da0436e9
JS		 741
742void lpfc_sli4_hba_reset(struct lpfc_hba *);
743struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t,
744 uint32_t);
745void lpfc_sli4_queue_free(struct lpfc_queue *);
a2fc4aef 746int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t);
895427bd 747int lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq);
a2fc4aef 748int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 749 struct lpfc_queue *, uint32_t, uint32_t);
2d7dbc4c
JS		 750int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp,
751 struct lpfc_queue **eqp, uint32_t type,
752 uint32_t subtype);
b19a061a
JS		 753int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *,
754 struct lpfc_queue *, uint32_t);
a2fc4aef 755int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 756 struct lpfc_queue *, uint32_t);
a2fc4aef 757int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *,
da0436e9 758 struct lpfc_queue *, struct lpfc_queue *, uint32_t);
2d7dbc4c
JS		 759int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp,
760 struct lpfc_queue **drqp, struct lpfc_queue **cqp,
761 uint32_t subtype);
73d91e50 762void lpfc_rq_adjust_repost(struct lpfc_hba *, struct lpfc_queue *, int);
a2fc4aef
JS		 763int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *);
764int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *);
765int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *);
766int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *);
767int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *,
da0436e9
JS		 768 struct lpfc_queue *);
769int lpfc_sli4_queue_setup(struct lpfc_hba *);
770void lpfc_sli4_queue_unset(struct lpfc_hba *);
771int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t);
772int lpfc_sli4_repost_scsi_sgl_list(struct lpfc_hba *);
01649561 773int lpfc_repost_nvme_sgl_list(struct lpfc_hba *phba);
da0436e9 774uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *);
f7bc6434 775void lpfc_sli4_free_xri(struct lpfc_hba *, int);
da0436e9 776int lpfc_sli4_post_async_mbox(struct lpfc_hba *);
da0436e9
JS		 777int lpfc_sli4_post_scsi_sgl_block(struct lpfc_hba *, struct list_head *, int);
778struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
779struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *);
780void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
781void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *);
782int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *);
783int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *);
784int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *);
785struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *);
786void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *);
787int lpfc_sli4_alloc_rpi(struct lpfc_hba *);
788void lpfc_sli4_free_rpi(struct lpfc_hba *, int);
789void lpfc_sli4_remove_rpis(struct lpfc_hba *);
790void lpfc_sli4_async_event_proc(struct lpfc_hba *);
ecfd03c6 791void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *);
6b5151fd
JS		 792int lpfc_sli4_resume_rpi(struct lpfc_nodelist *,
793 void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *);
da0436e9
JS		 794void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *);
795void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *);
796void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *,
797 struct sli4_wcqe_xri_aborted *);
798void lpfc_sli4_els_xri_aborted(struct lpfc_hba *,
799 struct sli4_wcqe_xri_aborted *);
1151e3ec
JS		 800void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *);
801void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *);
da0436e9
JS		 802int lpfc_sli4_brdreset(struct lpfc_hba *);
803int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *);
804void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *);
805int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *);
895427bd 806int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba);
76a95d75 807int lpfc_sli4_init_vpi(struct lpfc_vport *);
da0436e9
JS		 808uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool);
809uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool);
810void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t);
0c9ab6f5
JS		 811int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t);
812int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t);
813int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t);
814void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
815void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
816void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *);
817int lpfc_sli4_unregister_fcf(struct lpfc_hba *);
da0436e9 818int lpfc_sli4_post_status_check(struct lpfc_hba *);
a183a15f
JS		 819uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
820uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *);
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