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da0436e9 JS |
1 | /******************************************************************* |
2 | * This file is part of the Emulex Linux Device Driver for * | |
3 | * Fibre Channel Host Bus Adapters. * | |
d080abe0 JS |
4 | * Copyright (C) 2017 Broadcom. All Rights Reserved. The term * |
5 | * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. * | |
51f4ca3c | 6 | * Copyright (C) 2009-2016 Emulex. All rights reserved. * |
da0436e9 | 7 | * EMULEX and SLI are trademarks of Emulex. * |
d080abe0 | 8 | * www.broadcom.com * |
da0436e9 JS |
9 | * * |
10 | * This program is free software; you can redistribute it and/or * | |
11 | * modify it under the terms of version 2 of the GNU General * | |
12 | * Public License as published by the Free Software Foundation. * | |
13 | * This program is distributed in the hope that it will be useful. * | |
14 | * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND * | |
15 | * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, * | |
16 | * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE * | |
17 | * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD * | |
18 | * TO BE LEGALLY INVALID. See the GNU General Public License for * | |
19 | * more details, a copy of which can be found in the file COPYING * | |
20 | * included with this package. * | |
21 | *******************************************************************/ | |
22 | ||
23 | #define LPFC_ACTIVE_MBOX_WAIT_CNT 100 | |
5af5eee7 JS |
24 | #define LPFC_XRI_EXCH_BUSY_WAIT_TMO 10000 |
25 | #define LPFC_XRI_EXCH_BUSY_WAIT_T1 10 | |
26 | #define LPFC_XRI_EXCH_BUSY_WAIT_T2 30000 | |
da0436e9 | 27 | #define LPFC_RPI_LOW_WATER_MARK 10 |
ecfd03c6 | 28 | |
a93ff37a JS |
29 | #define LPFC_UNREG_FCF 1 |
30 | #define LPFC_SKIP_UNREG_FCF 0 | |
31 | ||
ecfd03c6 JS |
32 | /* Amount of time in seconds for waiting FCF rediscovery to complete */ |
33 | #define LPFC_FCF_REDISCOVER_WAIT_TMO 2000 /* msec */ | |
34 | ||
da0436e9 JS |
35 | /* Number of SGL entries can be posted in a 4KB nonembedded mbox command */ |
36 | #define LPFC_NEMBED_MBOX_SGL_CNT 254 | |
37 | ||
67d12733 | 38 | /* Multi-queue arrangement for FCP EQ/CQ/WQ tuples */ |
895427bd JS |
39 | #define LPFC_HBA_IO_CHAN_MIN 0 |
40 | #define LPFC_HBA_IO_CHAN_MAX 32 | |
41 | #define LPFC_FCP_IO_CHAN_DEF 4 | |
42 | #define LPFC_NVME_IO_CHAN_DEF 0 | |
da0436e9 | 43 | |
1ba981fd JS |
44 | /* Number of channels used for Flash Optimized Fabric (FOF) operations */ |
45 | ||
46 | #define LPFC_FOF_IO_CHAN_NUM 1 | |
47 | ||
da0436e9 JS |
48 | /* |
49 | * Provide the default FCF Record attributes used by the driver | |
50 | * when nonFIP mode is configured and there is no other default | |
51 | * FCF Record attributes. | |
52 | */ | |
53 | #define LPFC_FCOE_FCF_DEF_INDEX 0 | |
54 | #define LPFC_FCOE_FCF_GET_FIRST 0xFFFF | |
55 | #define LPFC_FCOE_FCF_NEXT_NONE 0xFFFF | |
56 | ||
dbb6b3ab JS |
57 | #define LPFC_FCOE_NULL_VID 0xFFF |
58 | #define LPFC_FCOE_IGNORE_VID 0xFFFF | |
59 | ||
da0436e9 JS |
60 | /* First 3 bytes of default FCF MAC is specified by FC_MAP */ |
61 | #define LPFC_FCOE_FCF_MAC3 0xFF | |
62 | #define LPFC_FCOE_FCF_MAC4 0xFF | |
63 | #define LPFC_FCOE_FCF_MAC5 0xFE | |
64 | #define LPFC_FCOE_FCF_MAP0 0x0E | |
65 | #define LPFC_FCOE_FCF_MAP1 0xFC | |
66 | #define LPFC_FCOE_FCF_MAP2 0x00 | |
98fc5dd9 | 67 | #define LPFC_FCOE_MAX_RCV_SIZE 0x800 |
da0436e9 JS |
68 | #define LPFC_FCOE_FKA_ADV_PER 0 |
69 | #define LPFC_FCOE_FIP_PRIORITY 0x80 | |
70 | ||
6669f9bb JS |
71 | #define sli4_sid_from_fc_hdr(fc_hdr) \ |
72 | ((fc_hdr)->fh_s_id[0] << 16 | \ | |
73 | (fc_hdr)->fh_s_id[1] << 8 | \ | |
74 | (fc_hdr)->fh_s_id[2]) | |
75 | ||
939723a4 JS |
76 | #define sli4_did_from_fc_hdr(fc_hdr) \ |
77 | ((fc_hdr)->fh_d_id[0] << 16 | \ | |
78 | (fc_hdr)->fh_d_id[1] << 8 | \ | |
79 | (fc_hdr)->fh_d_id[2]) | |
80 | ||
5ffc266e JS |
81 | #define sli4_fctl_from_fc_hdr(fc_hdr) \ |
82 | ((fc_hdr)->fh_f_ctl[0] << 16 | \ | |
83 | (fc_hdr)->fh_f_ctl[1] << 8 | \ | |
84 | (fc_hdr)->fh_f_ctl[2]) | |
85 | ||
939723a4 JS |
86 | #define sli4_type_from_fc_hdr(fc_hdr) \ |
87 | ((fc_hdr)->fh_type) | |
88 | ||
88a2cfbb JS |
89 | #define LPFC_FW_RESET_MAXIMUM_WAIT_10MS_CNT 12000 |
90 | ||
c71ab861 JS |
91 | #define INT_FW_UPGRADE 0 |
92 | #define RUN_FW_UPGRADE 1 | |
93 | ||
da0436e9 JS |
94 | enum lpfc_sli4_queue_type { |
95 | LPFC_EQ, | |
96 | LPFC_GCQ, | |
97 | LPFC_MCQ, | |
98 | LPFC_WCQ, | |
99 | LPFC_RCQ, | |
100 | LPFC_MQ, | |
101 | LPFC_WQ, | |
102 | LPFC_HRQ, | |
103 | LPFC_DRQ | |
104 | }; | |
105 | ||
106 | /* The queue sub-type defines the functional purpose of the queue */ | |
107 | enum lpfc_sli4_queue_subtype { | |
108 | LPFC_NONE, | |
109 | LPFC_MBOX, | |
110 | LPFC_FCP, | |
111 | LPFC_ELS, | |
895427bd | 112 | LPFC_NVME, |
f358dd0c | 113 | LPFC_NVMET, |
895427bd | 114 | LPFC_NVME_LS, |
da0436e9 JS |
115 | LPFC_USOL |
116 | }; | |
117 | ||
118 | union sli4_qe { | |
119 | void *address; | |
120 | struct lpfc_eqe *eqe; | |
121 | struct lpfc_cqe *cqe; | |
122 | struct lpfc_mcqe *mcqe; | |
123 | struct lpfc_wcqe_complete *wcqe_complete; | |
124 | struct lpfc_wcqe_release *wcqe_release; | |
125 | struct sli4_wcqe_xri_aborted *wcqe_xri_aborted; | |
126 | struct lpfc_rcqe_complete *rcqe_complete; | |
127 | struct lpfc_mqe *mqe; | |
128 | union lpfc_wqe *wqe; | |
0c651878 | 129 | union lpfc_wqe128 *wqe128; |
da0436e9 JS |
130 | struct lpfc_rqe *rqe; |
131 | }; | |
132 | ||
895427bd JS |
133 | /* RQ buffer list */ |
134 | struct lpfc_rqb { | |
135 | uint16_t entry_count; /* Current number of RQ slots */ | |
136 | uint16_t buffer_count; /* Current number of buffers posted */ | |
137 | struct list_head rqb_buffer_list; /* buffers assigned to this HBQ */ | |
138 | /* Callback for HBQ buffer allocation */ | |
139 | struct rqb_dmabuf *(*rqb_alloc_buffer)(struct lpfc_hba *); | |
140 | /* Callback for HBQ buffer free */ | |
141 | void (*rqb_free_buffer)(struct lpfc_hba *, | |
142 | struct rqb_dmabuf *); | |
143 | }; | |
144 | ||
da0436e9 JS |
145 | struct lpfc_queue { |
146 | struct list_head list; | |
895427bd | 147 | struct list_head wq_list; |
da0436e9 JS |
148 | enum lpfc_sli4_queue_type type; |
149 | enum lpfc_sli4_queue_subtype subtype; | |
150 | struct lpfc_hba *phba; | |
151 | struct list_head child_list; | |
895427bd JS |
152 | struct list_head page_list; |
153 | struct list_head sgl_list; | |
da0436e9 JS |
154 | uint32_t entry_count; /* Number of entries to support on the queue */ |
155 | uint32_t entry_size; /* Size of each queue entry. */ | |
73d91e50 | 156 | uint32_t entry_repost; /* Count of entries before doorbell is rung */ |
64eb4dcb JS |
157 | #define LPFC_EQ_REPOST 8 |
158 | #define LPFC_MQ_REPOST 8 | |
159 | #define LPFC_CQ_REPOST 64 | |
61f3d4bf | 160 | #define LPFC_RQ_REPOST 64 |
64eb4dcb | 161 | #define LPFC_RELEASE_NOTIFICATION_INTERVAL 32 /* For WQs */ |
da0436e9 | 162 | uint32_t queue_id; /* Queue ID assigned by the hardware */ |
2a622bfb | 163 | uint32_t assoc_qid; /* Queue ID associated with, for CQ/WQ/MQ */ |
da0436e9 | 164 | uint32_t page_count; /* Number of pages allocated for this queue */ |
da0436e9 JS |
165 | uint32_t host_index; /* The host's index for putting or getting */ |
166 | uint32_t hba_index; /* The last known hba index for get or put */ | |
b84daac9 | 167 | |
2a76a283 | 168 | struct lpfc_sli_ring *pring; /* ptr to io ring associated with q */ |
895427bd | 169 | struct lpfc_rqb *rqbp; /* ptr to RQ buffers */ |
2a76a283 | 170 | |
895427bd | 171 | uint16_t sgl_list_cnt; |
962bc51b JS |
172 | uint16_t db_format; |
173 | #define LPFC_DB_RING_FORMAT 0x01 | |
174 | #define LPFC_DB_LIST_FORMAT 0x02 | |
175 | void __iomem *db_regaddr; | |
b84daac9 JS |
176 | /* For q stats */ |
177 | uint32_t q_cnt_1; | |
178 | uint32_t q_cnt_2; | |
179 | uint32_t q_cnt_3; | |
180 | uint64_t q_cnt_4; | |
181 | /* defines for EQ stats */ | |
182 | #define EQ_max_eqe q_cnt_1 | |
183 | #define EQ_no_entry q_cnt_2 | |
184 | #define EQ_badstate q_cnt_3 | |
185 | #define EQ_processed q_cnt_4 | |
186 | ||
187 | /* defines for CQ stats */ | |
188 | #define CQ_mbox q_cnt_1 | |
189 | #define CQ_max_cqe q_cnt_1 | |
190 | #define CQ_release_wqe q_cnt_2 | |
191 | #define CQ_xri_aborted q_cnt_3 | |
192 | #define CQ_wq q_cnt_4 | |
193 | ||
194 | /* defines for WQ stats */ | |
195 | #define WQ_overflow q_cnt_1 | |
196 | #define WQ_posted q_cnt_4 | |
197 | ||
198 | /* defines for RQ stats */ | |
199 | #define RQ_no_posted_buf q_cnt_1 | |
200 | #define RQ_no_buf_found q_cnt_2 | |
547077a4 | 201 | #define RQ_buf_posted q_cnt_3 |
b84daac9 JS |
202 | #define RQ_rcv_buf q_cnt_4 |
203 | ||
895427bd JS |
204 | uint64_t isr_timestamp; |
205 | struct lpfc_queue *assoc_qp; | |
da0436e9 JS |
206 | union sli4_qe qe[1]; /* array to index entries (must be last) */ |
207 | }; | |
208 | ||
da0436e9 | 209 | struct lpfc_sli4_link { |
8b68cd52 | 210 | uint16_t speed; |
da0436e9 JS |
211 | uint8_t duplex; |
212 | uint8_t status; | |
70f3c073 JS |
213 | uint8_t type; |
214 | uint8_t number; | |
da0436e9 | 215 | uint8_t fault; |
65467b6b | 216 | uint16_t logical_speed; |
70f3c073 | 217 | uint16_t topology; |
da0436e9 JS |
218 | }; |
219 | ||
ecfd03c6 JS |
220 | struct lpfc_fcf_rec { |
221 | uint8_t fabric_name[8]; | |
222 | uint8_t switch_name[8]; | |
da0436e9 JS |
223 | uint8_t mac_addr[6]; |
224 | uint16_t fcf_indx; | |
ecfd03c6 JS |
225 | uint32_t priority; |
226 | uint16_t vlan_id; | |
227 | uint32_t addr_mode; | |
228 | uint32_t flag; | |
229 | #define BOOT_ENABLE 0x01 | |
230 | #define RECORD_VALID 0x02 | |
231 | }; | |
232 | ||
7d791df7 JS |
233 | struct lpfc_fcf_pri_rec { |
234 | uint16_t fcf_index; | |
235 | #define LPFC_FCF_ON_PRI_LIST 0x0001 | |
236 | #define LPFC_FCF_FLOGI_FAILED 0x0002 | |
237 | uint16_t flag; | |
238 | uint32_t priority; | |
239 | }; | |
240 | ||
241 | struct lpfc_fcf_pri { | |
242 | struct list_head list; | |
243 | struct lpfc_fcf_pri_rec fcf_rec; | |
244 | }; | |
245 | ||
246 | /* | |
247 | * Maximum FCF table index, it is for driver internal book keeping, it | |
248 | * just needs to be no less than the supported HBA's FCF table size. | |
249 | */ | |
250 | #define LPFC_SLI4_FCF_TBL_INDX_MAX 32 | |
251 | ||
ecfd03c6 | 252 | struct lpfc_fcf { |
da0436e9 JS |
253 | uint16_t fcfi; |
254 | uint32_t fcf_flag; | |
255 | #define FCF_AVAILABLE 0x01 /* FCF available for discovery */ | |
256 | #define FCF_REGISTERED 0x02 /* FCF registered with FW */ | |
ecfd03c6 JS |
257 | #define FCF_SCAN_DONE 0x04 /* FCF table scan done */ |
258 | #define FCF_IN_USE 0x08 /* Atleast one discovery completed */ | |
0c9ab6f5 JS |
259 | #define FCF_INIT_DISC 0x10 /* Initial FCF discovery */ |
260 | #define FCF_DEAD_DISC 0x20 /* FCF DEAD fast FCF failover discovery */ | |
261 | #define FCF_ACVL_DISC 0x40 /* All CVL fast FCF failover discovery */ | |
262 | #define FCF_DISCOVERY (FCF_INIT_DISC | FCF_DEAD_DISC | FCF_ACVL_DISC) | |
263 | #define FCF_REDISC_PEND 0x80 /* FCF rediscovery pending */ | |
264 | #define FCF_REDISC_EVT 0x100 /* FCF rediscovery event to worker thread */ | |
265 | #define FCF_REDISC_FOV 0x200 /* Post FCF rediscovery fast failover */ | |
a93ff37a | 266 | #define FCF_REDISC_PROG (FCF_REDISC_PEND | FCF_REDISC_EVT) |
da0436e9 | 267 | uint32_t addr_mode; |
999d813f | 268 | uint32_t eligible_fcf_cnt; |
ecfd03c6 JS |
269 | struct lpfc_fcf_rec current_rec; |
270 | struct lpfc_fcf_rec failover_rec; | |
7d791df7 JS |
271 | struct list_head fcf_pri_list; |
272 | struct lpfc_fcf_pri fcf_pri[LPFC_SLI4_FCF_TBL_INDX_MAX]; | |
273 | uint32_t current_fcf_scan_pri; | |
ecfd03c6 | 274 | struct timer_list redisc_wait; |
0c9ab6f5 | 275 | unsigned long *fcf_rr_bmask; /* Eligible FCF indexes for RR failover */ |
da0436e9 JS |
276 | }; |
277 | ||
0c9ab6f5 | 278 | |
da0436e9 JS |
279 | #define LPFC_REGION23_SIGNATURE "RG23" |
280 | #define LPFC_REGION23_VERSION 1 | |
281 | #define LPFC_REGION23_LAST_REC 0xff | |
a0c87cbd JS |
282 | #define DRIVER_SPECIFIC_TYPE 0xA2 |
283 | #define LINUX_DRIVER_ID 0x20 | |
284 | #define PORT_STE_TYPE 0x1 | |
285 | ||
da0436e9 JS |
286 | struct lpfc_fip_param_hdr { |
287 | uint8_t type; | |
288 | #define FCOE_PARAM_TYPE 0xA0 | |
289 | uint8_t length; | |
290 | #define FCOE_PARAM_LENGTH 2 | |
291 | uint8_t parm_version; | |
292 | #define FIPP_VERSION 0x01 | |
293 | uint8_t parm_flags; | |
294 | #define lpfc_fip_param_hdr_fipp_mode_SHIFT 6 | |
295 | #define lpfc_fip_param_hdr_fipp_mode_MASK 0x3 | |
296 | #define lpfc_fip_param_hdr_fipp_mode_WORD parm_flags | |
6a9c52cf | 297 | #define FIPP_MODE_ON 0x1 |
da0436e9 JS |
298 | #define FIPP_MODE_OFF 0x0 |
299 | #define FIPP_VLAN_VALID 0x1 | |
300 | }; | |
301 | ||
302 | struct lpfc_fcoe_params { | |
303 | uint8_t fc_map[3]; | |
304 | uint8_t reserved1; | |
305 | uint16_t vlan_tag; | |
306 | uint8_t reserved[2]; | |
307 | }; | |
308 | ||
309 | struct lpfc_fcf_conn_hdr { | |
310 | uint8_t type; | |
311 | #define FCOE_CONN_TBL_TYPE 0xA1 | |
312 | uint8_t length; /* words */ | |
313 | uint8_t reserved[2]; | |
314 | }; | |
315 | ||
316 | struct lpfc_fcf_conn_rec { | |
317 | uint16_t flags; | |
318 | #define FCFCNCT_VALID 0x0001 | |
319 | #define FCFCNCT_BOOT 0x0002 | |
320 | #define FCFCNCT_PRIMARY 0x0004 /* if not set, Secondary */ | |
321 | #define FCFCNCT_FBNM_VALID 0x0008 | |
322 | #define FCFCNCT_SWNM_VALID 0x0010 | |
323 | #define FCFCNCT_VLAN_VALID 0x0020 | |
324 | #define FCFCNCT_AM_VALID 0x0040 | |
325 | #define FCFCNCT_AM_PREFERRED 0x0080 /* if not set, AM Required */ | |
326 | #define FCFCNCT_AM_SPMA 0x0100 /* if not set, FPMA */ | |
327 | ||
328 | uint16_t vlan_tag; | |
329 | uint8_t fabric_name[8]; | |
330 | uint8_t switch_name[8]; | |
331 | }; | |
332 | ||
333 | struct lpfc_fcf_conn_entry { | |
334 | struct list_head list; | |
335 | struct lpfc_fcf_conn_rec conn_rec; | |
336 | }; | |
337 | ||
338 | /* | |
339 | * Define the host's bootstrap mailbox. This structure contains | |
340 | * the member attributes needed to create, use, and destroy the | |
341 | * bootstrap mailbox region. | |
342 | * | |
343 | * The macro definitions for the bmbx data structure are defined | |
344 | * in lpfc_hw4.h with the register definition. | |
345 | */ | |
346 | struct lpfc_bmbx { | |
347 | struct lpfc_dmabuf *dmabuf; | |
348 | struct dma_address dma_address; | |
349 | void *avirt; | |
350 | dma_addr_t aphys; | |
351 | uint32_t bmbx_size; | |
352 | }; | |
353 | ||
354 | #define LPFC_EQE_SIZE LPFC_EQE_SIZE_4 | |
355 | ||
356 | #define LPFC_EQE_SIZE_4B 4 | |
357 | #define LPFC_EQE_SIZE_16B 16 | |
358 | #define LPFC_CQE_SIZE 16 | |
359 | #define LPFC_WQE_SIZE 64 | |
0c651878 | 360 | #define LPFC_WQE128_SIZE 128 |
da0436e9 JS |
361 | #define LPFC_MQE_SIZE 256 |
362 | #define LPFC_RQE_SIZE 8 | |
363 | ||
364 | #define LPFC_EQE_DEF_COUNT 1024 | |
ff78d8f9 | 365 | #define LPFC_CQE_DEF_COUNT 1024 |
f1126688 | 366 | #define LPFC_WQE_DEF_COUNT 256 |
0c651878 | 367 | #define LPFC_WQE128_DEF_COUNT 128 |
895427bd | 368 | #define LPFC_WQE128_MAX_COUNT 256 |
da0436e9 JS |
369 | #define LPFC_MQE_DEF_COUNT 16 |
370 | #define LPFC_RQE_DEF_COUNT 512 | |
371 | ||
372 | #define LPFC_QUEUE_NOARM false | |
373 | #define LPFC_QUEUE_REARM true | |
374 | ||
375 | ||
376 | /* | |
377 | * SLI4 CT field defines | |
378 | */ | |
379 | #define SLI4_CT_RPI 0 | |
380 | #define SLI4_CT_VPI 1 | |
381 | #define SLI4_CT_VFI 2 | |
382 | #define SLI4_CT_FCFI 3 | |
383 | ||
da0436e9 JS |
384 | /* |
385 | * SLI4 specific data structures | |
386 | */ | |
387 | struct lpfc_max_cfg_param { | |
388 | uint16_t max_xri; | |
389 | uint16_t xri_base; | |
390 | uint16_t xri_used; | |
391 | uint16_t max_rpi; | |
392 | uint16_t rpi_base; | |
393 | uint16_t rpi_used; | |
394 | uint16_t max_vpi; | |
395 | uint16_t vpi_base; | |
396 | uint16_t vpi_used; | |
397 | uint16_t max_vfi; | |
398 | uint16_t vfi_base; | |
399 | uint16_t vfi_used; | |
400 | uint16_t max_fcfi; | |
da0436e9 JS |
401 | uint16_t fcfi_used; |
402 | uint16_t max_eq; | |
403 | uint16_t max_rq; | |
404 | uint16_t max_cq; | |
405 | uint16_t max_wq; | |
406 | }; | |
407 | ||
408 | struct lpfc_hba; | |
409 | /* SLI4 HBA multi-fcp queue handler struct */ | |
b83d005e | 410 | #define LPFC_SLI4_HANDLER_NAME_SZ 16 |
895427bd | 411 | struct lpfc_hba_eq_hdl { |
da0436e9 | 412 | uint32_t idx; |
b83d005e | 413 | char handler_name[LPFC_SLI4_HANDLER_NAME_SZ]; |
da0436e9 | 414 | struct lpfc_hba *phba; |
895427bd JS |
415 | atomic_t hba_eq_in_use; |
416 | struct cpumask *cpumask; | |
417 | /* CPU affinitsed to or 0xffffffff if multiple */ | |
418 | uint32_t cpu; | |
419 | #define LPFC_MULTI_CPU_AFFINITY 0xffffffff | |
da0436e9 JS |
420 | }; |
421 | ||
28baac74 JS |
422 | /* Port Capabilities for SLI4 Parameters */ |
423 | struct lpfc_pc_sli4_params { | |
424 | uint32_t supported; | |
425 | uint32_t if_type; | |
426 | uint32_t sli_rev; | |
427 | uint32_t sli_family; | |
428 | uint32_t featurelevel_1; | |
429 | uint32_t featurelevel_2; | |
430 | uint32_t proto_types; | |
431 | #define LPFC_SLI4_PROTO_FCOE 0x0000001 | |
432 | #define LPFC_SLI4_PROTO_FC 0x0000002 | |
433 | #define LPFC_SLI4_PROTO_NIC 0x0000004 | |
434 | #define LPFC_SLI4_PROTO_ISCSI 0x0000008 | |
435 | #define LPFC_SLI4_PROTO_RDMA 0x0000010 | |
436 | uint32_t sge_supp_len; | |
437 | uint32_t if_page_sz; | |
438 | uint32_t rq_db_window; | |
439 | uint32_t loopbk_scope; | |
1ba981fd | 440 | uint32_t oas_supported; |
28baac74 JS |
441 | uint32_t eq_pages_max; |
442 | uint32_t eqe_size; | |
443 | uint32_t cq_pages_max; | |
444 | uint32_t cqe_size; | |
445 | uint32_t mq_pages_max; | |
446 | uint32_t mqe_size; | |
447 | uint32_t mq_elem_cnt; | |
448 | uint32_t wq_pages_max; | |
449 | uint32_t wqe_size; | |
450 | uint32_t rq_pages_max; | |
451 | uint32_t rqe_size; | |
452 | uint32_t hdr_pages_max; | |
453 | uint32_t hdr_size; | |
454 | uint32_t hdr_pp_align; | |
455 | uint32_t sgl_pages_max; | |
456 | uint32_t sgl_pp_align; | |
fedd3b7b JS |
457 | uint8_t cqv; |
458 | uint8_t mqv; | |
459 | uint8_t wqv; | |
460 | uint8_t rqv; | |
0c651878 JS |
461 | uint8_t wqsize; |
462 | #define LPFC_WQ_SZ64_SUPPORT 1 | |
463 | #define LPFC_WQ_SZ128_SUPPORT 2 | |
895427bd | 464 | uint8_t wqpcnt; |
28baac74 JS |
465 | }; |
466 | ||
912e3acd JS |
467 | struct lpfc_iov { |
468 | uint32_t pf_number; | |
469 | uint32_t vf_number; | |
470 | }; | |
471 | ||
cd1c8301 JS |
472 | struct lpfc_sli4_lnk_info { |
473 | uint8_t lnk_dv; | |
474 | #define LPFC_LNK_DAT_INVAL 0 | |
475 | #define LPFC_LNK_DAT_VAL 1 | |
476 | uint8_t lnk_tp; | |
477 | #define LPFC_LNK_GE 0x0 /* FCoE */ | |
478 | #define LPFC_LNK_FC 0x1 /* FC */ | |
479 | uint8_t lnk_no; | |
448193b5 | 480 | uint8_t optic_state; |
cd1c8301 JS |
481 | }; |
482 | ||
895427bd | 483 | #define LPFC_SLI4_HANDLER_CNT (LPFC_HBA_IO_CHAN_MAX+ \ |
1ba981fd | 484 | LPFC_FOF_IO_CHAN_NUM) |
4305f183 | 485 | |
7bb03bbf JS |
486 | /* Used for IRQ vector to CPU mapping */ |
487 | struct lpfc_vector_map_info { | |
488 | uint16_t phys_id; | |
489 | uint16_t core_id; | |
490 | uint16_t irq; | |
491 | uint16_t channel_id; | |
7bb03bbf JS |
492 | }; |
493 | #define LPFC_VECTOR_MAP_EMPTY 0xffff | |
7bb03bbf | 494 | |
da0436e9 JS |
495 | /* SLI4 HBA data structure entries */ |
496 | struct lpfc_sli4_hba { | |
497 | void __iomem *conf_regs_memmap_p; /* Kernel memory mapped address for | |
498 | PCI BAR0, config space registers */ | |
499 | void __iomem *ctrl_regs_memmap_p; /* Kernel memory mapped address for | |
500 | PCI BAR1, control registers */ | |
501 | void __iomem *drbl_regs_memmap_p; /* Kernel memory mapped address for | |
502 | PCI BAR2, doorbell registers */ | |
2fcee4bf JS |
503 | union { |
504 | struct { | |
505 | /* IF Type 0, BAR 0 PCI cfg space reg mem map */ | |
506 | void __iomem *UERRLOregaddr; | |
507 | void __iomem *UERRHIregaddr; | |
508 | void __iomem *UEMASKLOregaddr; | |
509 | void __iomem *UEMASKHIregaddr; | |
510 | } if_type0; | |
511 | struct { | |
512 | /* IF Type 2, BAR 0 PCI cfg space reg mem map. */ | |
513 | void __iomem *STATUSregaddr; | |
514 | void __iomem *CTRLregaddr; | |
515 | void __iomem *ERR1regaddr; | |
2e90f4b5 JS |
516 | #define SLIPORT_ERR1_REG_ERR_CODE_1 0x1 |
517 | #define SLIPORT_ERR1_REG_ERR_CODE_2 0x2 | |
2fcee4bf | 518 | void __iomem *ERR2regaddr; |
2e90f4b5 JS |
519 | #define SLIPORT_ERR2_REG_FW_RESTART 0x0 |
520 | #define SLIPORT_ERR2_REG_FUNC_PROVISON 0x1 | |
521 | #define SLIPORT_ERR2_REG_FORCED_DUMP 0x2 | |
522 | #define SLIPORT_ERR2_REG_FAILURE_EQ 0x3 | |
523 | #define SLIPORT_ERR2_REG_FAILURE_CQ 0x4 | |
524 | #define SLIPORT_ERR2_REG_FAILURE_BUS 0x5 | |
525 | #define SLIPORT_ERR2_REG_FAILURE_RQ 0x6 | |
2fcee4bf JS |
526 | } if_type2; |
527 | } u; | |
528 | ||
529 | /* IF type 0, BAR1 and if type 2, Bar 0 CSR register memory map */ | |
530 | void __iomem *PSMPHRregaddr; | |
531 | ||
532 | /* Well-known SLI INTF register memory map. */ | |
533 | void __iomem *SLIINTFregaddr; | |
534 | ||
535 | /* IF type 0, BAR 1 function CSR register memory map */ | |
536 | void __iomem *ISRregaddr; /* HST_ISR register */ | |
537 | void __iomem *IMRregaddr; /* HST_IMR register */ | |
538 | void __iomem *ISCRregaddr; /* HST_ISCR register */ | |
539 | /* IF type 0, BAR 0 and if type 2, BAR 0 doorbell register memory map */ | |
540 | void __iomem *RQDBregaddr; /* RQ_DOORBELL register */ | |
541 | void __iomem *WQDBregaddr; /* WQ_DOORBELL register */ | |
542 | void __iomem *EQCQDBregaddr; /* EQCQ_DOORBELL register */ | |
543 | void __iomem *MQDBregaddr; /* MQ_DOORBELL register */ | |
544 | void __iomem *BMBXregaddr; /* BootStrap MBX register */ | |
da0436e9 | 545 | |
a747c9ce JS |
546 | uint32_t ue_mask_lo; |
547 | uint32_t ue_mask_hi; | |
65791f1f JS |
548 | uint32_t ue_to_sr; |
549 | uint32_t ue_to_rp; | |
28baac74 JS |
550 | struct lpfc_register sli_intf; |
551 | struct lpfc_pc_sli4_params pc_sli4_params; | |
895427bd | 552 | struct lpfc_hba_eq_hdl *hba_eq_hdl; /* HBA per-WQ handle */ |
67d12733 | 553 | |
da0436e9 | 554 | /* Pointers to the constructed SLI4 queues */ |
895427bd JS |
555 | struct lpfc_queue **hba_eq; /* Event queues for HBA */ |
556 | struct lpfc_queue **fcp_cq; /* Fast-path FCP compl queue */ | |
557 | struct lpfc_queue **nvme_cq; /* Fast-path NVME compl queue */ | |
2d7dbc4c JS |
558 | struct lpfc_queue **nvmet_cqset; /* Fast-path NVMET CQ Set queues */ |
559 | struct lpfc_queue **nvmet_mrq_hdr; /* Fast-path NVMET hdr MRQs */ | |
560 | struct lpfc_queue **nvmet_mrq_data; /* Fast-path NVMET data MRQs */ | |
895427bd JS |
561 | struct lpfc_queue **fcp_wq; /* Fast-path FCP work queue */ |
562 | struct lpfc_queue **nvme_wq; /* Fast-path NVME work queue */ | |
67d12733 | 563 | uint16_t *fcp_cq_map; |
895427bd JS |
564 | uint16_t *nvme_cq_map; |
565 | struct list_head lpfc_wq_list; | |
67d12733 JS |
566 | |
567 | struct lpfc_queue *mbx_cq; /* Slow-path mailbox complete queue */ | |
568 | struct lpfc_queue *els_cq; /* Slow-path ELS response complete queue */ | |
895427bd | 569 | struct lpfc_queue *nvmels_cq; /* NVME LS complete queue */ |
da0436e9 JS |
570 | struct lpfc_queue *mbx_wq; /* Slow-path MBOX work queue */ |
571 | struct lpfc_queue *els_wq; /* Slow-path ELS work queue */ | |
895427bd | 572 | struct lpfc_queue *nvmels_wq; /* NVME LS work queue */ |
da0436e9 JS |
573 | struct lpfc_queue *hdr_rq; /* Slow-path Header Receive queue */ |
574 | struct lpfc_queue *dat_rq; /* Slow-path Data Receive queue */ | |
da0436e9 | 575 | |
895427bd JS |
576 | struct lpfc_name wwnn; |
577 | struct lpfc_name wwpn; | |
578 | ||
9a86ed48 | 579 | uint32_t fw_func_mode; /* FW function protocol mode */ |
962bc51b JS |
580 | uint32_t ulp0_mode; /* ULP0 protocol mode */ |
581 | uint32_t ulp1_mode; /* ULP1 protocol mode */ | |
582 | ||
1ba981fd JS |
583 | struct lpfc_queue *fof_eq; /* Flash Optimized Fabric Event queue */ |
584 | ||
585 | /* Optimized Access Storage specific queues/structures */ | |
586 | ||
587 | struct lpfc_queue *oas_cq; /* OAS completion queue */ | |
588 | struct lpfc_queue *oas_wq; /* OAS Work queue */ | |
589 | struct lpfc_sli_ring *oas_ring; | |
590 | uint64_t oas_next_lun; | |
591 | uint8_t oas_next_tgt_wwpn[8]; | |
592 | uint8_t oas_next_vpt_wwpn[8]; | |
593 | ||
da0436e9 JS |
594 | /* Setup information for various queue parameters */ |
595 | int eq_esize; | |
596 | int eq_ecount; | |
597 | int cq_esize; | |
598 | int cq_ecount; | |
599 | int wq_esize; | |
600 | int wq_ecount; | |
601 | int mq_esize; | |
602 | int mq_ecount; | |
603 | int rq_esize; | |
604 | int rq_ecount; | |
605 | #define LPFC_SP_EQ_MAX_INTR_SEC 10000 | |
606 | #define LPFC_FP_EQ_MAX_INTR_SEC 10000 | |
607 | ||
608 | uint32_t intr_enable; | |
609 | struct lpfc_bmbx bmbx; | |
610 | struct lpfc_max_cfg_param max_cfg_param; | |
6d368e53 JS |
611 | uint16_t extents_in_use; /* must allocate resource extents. */ |
612 | uint16_t rpi_hdrs_in_use; /* must post rpi hdrs if set. */ | |
da0436e9 JS |
613 | uint16_t next_xri; /* last_xri - max_cfg_param.xri_base = used */ |
614 | uint16_t next_rpi; | |
895427bd JS |
615 | uint16_t nvme_xri_max; |
616 | uint16_t nvme_xri_cnt; | |
617 | uint16_t nvme_xri_start; | |
da0436e9 JS |
618 | uint16_t scsi_xri_max; |
619 | uint16_t scsi_xri_cnt; | |
6d368e53 | 620 | uint16_t scsi_xri_start; |
895427bd | 621 | uint16_t els_xri_cnt; |
f358dd0c | 622 | uint16_t nvmet_xri_cnt; |
6c621a22 | 623 | uint16_t nvmet_ctx_cnt; |
a8cf5dfe JS |
624 | uint16_t nvmet_io_wait_cnt; |
625 | uint16_t nvmet_io_wait_total; | |
895427bd | 626 | struct list_head lpfc_els_sgl_list; |
da0436e9 | 627 | struct list_head lpfc_abts_els_sgl_list; |
f358dd0c | 628 | struct list_head lpfc_nvmet_sgl_list; |
86c67379 | 629 | struct list_head lpfc_abts_nvmet_ctx_list; |
da0436e9 | 630 | struct list_head lpfc_abts_scsi_buf_list; |
895427bd | 631 | struct list_head lpfc_abts_nvme_buf_list; |
a8cf5dfe JS |
632 | struct list_head lpfc_nvmet_ctx_list; |
633 | struct list_head lpfc_nvmet_io_wait_list; | |
da0436e9 JS |
634 | struct lpfc_sglq **lpfc_sglq_active_list; |
635 | struct list_head lpfc_rpi_hdr_list; | |
636 | unsigned long *rpi_bmask; | |
6d368e53 | 637 | uint16_t *rpi_ids; |
da0436e9 | 638 | uint16_t rpi_count; |
6d368e53 JS |
639 | struct list_head lpfc_rpi_blk_list; |
640 | unsigned long *xri_bmask; | |
641 | uint16_t *xri_ids; | |
6d368e53 JS |
642 | struct list_head lpfc_xri_blk_list; |
643 | unsigned long *vfi_bmask; | |
644 | uint16_t *vfi_ids; | |
645 | uint16_t vfi_count; | |
646 | struct list_head lpfc_vfi_blk_list; | |
da0436e9 | 647 | struct lpfc_sli4_flags sli4_flags; |
45ed1190 | 648 | struct list_head sp_queue_event; |
da0436e9 JS |
649 | struct list_head sp_cqe_event_pool; |
650 | struct list_head sp_asynce_work_queue; | |
651 | struct list_head sp_fcp_xri_aborted_work_queue; | |
652 | struct list_head sp_els_xri_aborted_work_queue; | |
318083ad | 653 | struct list_head sp_nvme_xri_aborted_work_queue; |
da0436e9 JS |
654 | struct list_head sp_unsol_work_queue; |
655 | struct lpfc_sli4_link link_state; | |
cd1c8301 JS |
656 | struct lpfc_sli4_lnk_info lnk_info; |
657 | uint32_t pport_name_sta; | |
658 | #define LPFC_SLI4_PPNAME_NON 0 | |
659 | #define LPFC_SLI4_PPNAME_GET 1 | |
912e3acd | 660 | struct lpfc_iov iov; |
895427bd | 661 | spinlock_t abts_nvme_buf_list_lock; /* list of aborted SCSI IOs */ |
da0436e9 | 662 | spinlock_t abts_scsi_buf_list_lock; /* list of aborted SCSI IOs */ |
895427bd | 663 | spinlock_t sgl_list_lock; /* list of aborted els IOs */ |
f358dd0c | 664 | spinlock_t nvmet_io_lock; |
a8cf5dfe | 665 | spinlock_t nvmet_io_wait_lock; /* IOs waiting for ctx resources */ |
8b017a30 | 666 | uint32_t physical_port; |
7bb03bbf JS |
667 | |
668 | /* CPU to vector mapping information */ | |
669 | struct lpfc_vector_map_info *cpu_map; | |
670 | uint16_t num_online_cpu; | |
671 | uint16_t num_present_cpu; | |
76fd07a6 | 672 | uint16_t curr_disp_cpu; |
da0436e9 JS |
673 | }; |
674 | ||
675 | enum lpfc_sge_type { | |
676 | GEN_BUFF_TYPE, | |
895427bd | 677 | SCSI_BUFF_TYPE, |
f358dd0c | 678 | NVMET_BUFF_TYPE |
da0436e9 JS |
679 | }; |
680 | ||
0f65ff68 JS |
681 | enum lpfc_sgl_state { |
682 | SGL_FREED, | |
683 | SGL_ALLOCATED, | |
684 | SGL_XRI_ABORTED | |
685 | }; | |
686 | ||
da0436e9 JS |
687 | struct lpfc_sglq { |
688 | /* lpfc_sglqs are used in double linked lists */ | |
689 | struct list_head list; | |
690 | struct list_head clist; | |
691 | enum lpfc_sge_type buff_type; /* is this a scsi sgl */ | |
0f65ff68 | 692 | enum lpfc_sgl_state state; |
19ca7609 | 693 | struct lpfc_nodelist *ndlp; /* ndlp associated with IO */ |
da0436e9 | 694 | uint16_t iotag; /* pre-assigned IO tag */ |
6d368e53 | 695 | uint16_t sli4_lxritag; /* logical pre-assigned xri. */ |
da0436e9 JS |
696 | uint16_t sli4_xritag; /* pre-assigned XRI, (OXID) tag. */ |
697 | struct sli4_sge *sgl; /* pre-assigned SGL */ | |
698 | void *virt; /* virtual address. */ | |
699 | dma_addr_t phys; /* physical address */ | |
700 | }; | |
701 | ||
702 | struct lpfc_rpi_hdr { | |
703 | struct list_head list; | |
704 | uint32_t len; | |
705 | struct lpfc_dmabuf *dmabuf; | |
706 | uint32_t page_count; | |
707 | uint32_t start_rpi; | |
845d9e8d | 708 | uint16_t next_rpi; |
da0436e9 JS |
709 | }; |
710 | ||
6d368e53 JS |
711 | struct lpfc_rsrc_blks { |
712 | struct list_head list; | |
713 | uint16_t rsrc_start; | |
714 | uint16_t rsrc_size; | |
715 | uint16_t rsrc_used; | |
716 | }; | |
717 | ||
86478875 JS |
718 | struct lpfc_rdp_context { |
719 | struct lpfc_nodelist *ndlp; | |
720 | uint16_t ox_id; | |
721 | uint16_t rx_id; | |
722 | READ_LNK_VAR link_stat; | |
723 | uint8_t page_a0[DMP_SFF_PAGE_A0_SIZE]; | |
724 | uint8_t page_a2[DMP_SFF_PAGE_A2_SIZE]; | |
725 | void (*cmpl)(struct lpfc_hba *, struct lpfc_rdp_context*, int); | |
726 | }; | |
727 | ||
8b017a30 JS |
728 | struct lpfc_lcb_context { |
729 | uint8_t sub_command; | |
730 | uint8_t type; | |
731 | uint8_t frequency; | |
732 | uint16_t ox_id; | |
733 | uint16_t rx_id; | |
734 | struct lpfc_nodelist *ndlp; | |
735 | }; | |
736 | ||
737 | ||
da0436e9 JS |
738 | /* |
739 | * SLI4 specific function prototypes | |
740 | */ | |
741 | int lpfc_pci_function_reset(struct lpfc_hba *); | |
73d91e50 | 742 | int lpfc_sli4_pdev_status_reg_wait(struct lpfc_hba *); |
da0436e9 | 743 | int lpfc_sli4_hba_setup(struct lpfc_hba *); |
da0436e9 JS |
744 | int lpfc_sli4_config(struct lpfc_hba *, struct lpfcMboxq *, uint8_t, |
745 | uint8_t, uint32_t, bool); | |
746 | void lpfc_sli4_mbox_cmd_free(struct lpfc_hba *, struct lpfcMboxq *); | |
747 | void lpfc_sli4_mbx_sge_set(struct lpfcMboxq *, uint32_t, dma_addr_t, uint32_t); | |
748 | void lpfc_sli4_mbx_sge_get(struct lpfcMboxq *, uint32_t, | |
749 | struct lpfc_mbx_sge *); | |
0c9ab6f5 JS |
750 | int lpfc_sli4_mbx_read_fcf_rec(struct lpfc_hba *, struct lpfcMboxq *, |
751 | uint16_t); | |
da0436e9 JS |
752 | |
753 | void lpfc_sli4_hba_reset(struct lpfc_hba *); | |
754 | struct lpfc_queue *lpfc_sli4_queue_alloc(struct lpfc_hba *, uint32_t, | |
755 | uint32_t); | |
756 | void lpfc_sli4_queue_free(struct lpfc_queue *); | |
a2fc4aef | 757 | int lpfc_eq_create(struct lpfc_hba *, struct lpfc_queue *, uint32_t); |
895427bd | 758 | int lpfc_modify_hba_eq_delay(struct lpfc_hba *phba, uint32_t startq); |
a2fc4aef | 759 | int lpfc_cq_create(struct lpfc_hba *, struct lpfc_queue *, |
da0436e9 | 760 | struct lpfc_queue *, uint32_t, uint32_t); |
2d7dbc4c JS |
761 | int lpfc_cq_create_set(struct lpfc_hba *phba, struct lpfc_queue **cqp, |
762 | struct lpfc_queue **eqp, uint32_t type, | |
763 | uint32_t subtype); | |
b19a061a JS |
764 | int32_t lpfc_mq_create(struct lpfc_hba *, struct lpfc_queue *, |
765 | struct lpfc_queue *, uint32_t); | |
a2fc4aef | 766 | int lpfc_wq_create(struct lpfc_hba *, struct lpfc_queue *, |
da0436e9 | 767 | struct lpfc_queue *, uint32_t); |
a2fc4aef | 768 | int lpfc_rq_create(struct lpfc_hba *, struct lpfc_queue *, |
da0436e9 | 769 | struct lpfc_queue *, struct lpfc_queue *, uint32_t); |
2d7dbc4c JS |
770 | int lpfc_mrq_create(struct lpfc_hba *phba, struct lpfc_queue **hrqp, |
771 | struct lpfc_queue **drqp, struct lpfc_queue **cqp, | |
772 | uint32_t subtype); | |
a2fc4aef JS |
773 | int lpfc_eq_destroy(struct lpfc_hba *, struct lpfc_queue *); |
774 | int lpfc_cq_destroy(struct lpfc_hba *, struct lpfc_queue *); | |
775 | int lpfc_mq_destroy(struct lpfc_hba *, struct lpfc_queue *); | |
776 | int lpfc_wq_destroy(struct lpfc_hba *, struct lpfc_queue *); | |
777 | int lpfc_rq_destroy(struct lpfc_hba *, struct lpfc_queue *, | |
da0436e9 JS |
778 | struct lpfc_queue *); |
779 | int lpfc_sli4_queue_setup(struct lpfc_hba *); | |
780 | void lpfc_sli4_queue_unset(struct lpfc_hba *); | |
781 | int lpfc_sli4_post_sgl(struct lpfc_hba *, dma_addr_t, dma_addr_t, uint16_t); | |
782 | int lpfc_sli4_repost_scsi_sgl_list(struct lpfc_hba *); | |
01649561 | 783 | int lpfc_repost_nvme_sgl_list(struct lpfc_hba *phba); |
da0436e9 | 784 | uint16_t lpfc_sli4_next_xritag(struct lpfc_hba *); |
f7bc6434 | 785 | void lpfc_sli4_free_xri(struct lpfc_hba *, int); |
da0436e9 | 786 | int lpfc_sli4_post_async_mbox(struct lpfc_hba *); |
da0436e9 JS |
787 | int lpfc_sli4_post_scsi_sgl_block(struct lpfc_hba *, struct list_head *, int); |
788 | struct lpfc_cq_event *__lpfc_sli4_cq_event_alloc(struct lpfc_hba *); | |
789 | struct lpfc_cq_event *lpfc_sli4_cq_event_alloc(struct lpfc_hba *); | |
790 | void __lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); | |
791 | void lpfc_sli4_cq_event_release(struct lpfc_hba *, struct lpfc_cq_event *); | |
792 | int lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *); | |
793 | int lpfc_sli4_post_rpi_hdr(struct lpfc_hba *, struct lpfc_rpi_hdr *); | |
794 | int lpfc_sli4_post_all_rpi_hdrs(struct lpfc_hba *); | |
795 | struct lpfc_rpi_hdr *lpfc_sli4_create_rpi_hdr(struct lpfc_hba *); | |
796 | void lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *); | |
797 | int lpfc_sli4_alloc_rpi(struct lpfc_hba *); | |
798 | void lpfc_sli4_free_rpi(struct lpfc_hba *, int); | |
799 | void lpfc_sli4_remove_rpis(struct lpfc_hba *); | |
800 | void lpfc_sli4_async_event_proc(struct lpfc_hba *); | |
ecfd03c6 | 801 | void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *); |
6b5151fd JS |
802 | int lpfc_sli4_resume_rpi(struct lpfc_nodelist *, |
803 | void (*)(struct lpfc_hba *, LPFC_MBOXQ_t *), void *); | |
da0436e9 | 804 | void lpfc_sli4_fcp_xri_abort_event_proc(struct lpfc_hba *); |
318083ad | 805 | void lpfc_sli4_nvme_xri_abort_event_proc(struct lpfc_hba *phba); |
da0436e9 JS |
806 | void lpfc_sli4_els_xri_abort_event_proc(struct lpfc_hba *); |
807 | void lpfc_sli4_fcp_xri_aborted(struct lpfc_hba *, | |
808 | struct sli4_wcqe_xri_aborted *); | |
318083ad JS |
809 | void lpfc_sli4_nvme_xri_aborted(struct lpfc_hba *phba, |
810 | struct sli4_wcqe_xri_aborted *axri); | |
811 | void lpfc_sli4_nvmet_xri_aborted(struct lpfc_hba *phba, | |
812 | struct sli4_wcqe_xri_aborted *axri); | |
da0436e9 JS |
813 | void lpfc_sli4_els_xri_aborted(struct lpfc_hba *, |
814 | struct sli4_wcqe_xri_aborted *); | |
1151e3ec JS |
815 | void lpfc_sli4_vport_delete_els_xri_aborted(struct lpfc_vport *); |
816 | void lpfc_sli4_vport_delete_fcp_xri_aborted(struct lpfc_vport *); | |
da0436e9 JS |
817 | int lpfc_sli4_brdreset(struct lpfc_hba *); |
818 | int lpfc_sli4_add_fcf_record(struct lpfc_hba *, struct fcf_record *); | |
819 | void lpfc_sli_remove_dflt_fcf(struct lpfc_hba *); | |
820 | int lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *); | |
895427bd | 821 | int lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba); |
76a95d75 | 822 | int lpfc_sli4_init_vpi(struct lpfc_vport *); |
da0436e9 JS |
823 | uint32_t lpfc_sli4_cq_release(struct lpfc_queue *, bool); |
824 | uint32_t lpfc_sli4_eq_release(struct lpfc_queue *, bool); | |
825 | void lpfc_sli4_fcfi_unreg(struct lpfc_hba *, uint16_t); | |
0c9ab6f5 JS |
826 | int lpfc_sli4_fcf_scan_read_fcf_rec(struct lpfc_hba *, uint16_t); |
827 | int lpfc_sli4_fcf_rr_read_fcf_rec(struct lpfc_hba *, uint16_t); | |
828 | int lpfc_sli4_read_fcf_rec(struct lpfc_hba *, uint16_t); | |
829 | void lpfc_mbx_cmpl_fcf_scan_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); | |
830 | void lpfc_mbx_cmpl_fcf_rr_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); | |
831 | void lpfc_mbx_cmpl_read_fcf_rec(struct lpfc_hba *, LPFC_MBOXQ_t *); | |
832 | int lpfc_sli4_unregister_fcf(struct lpfc_hba *); | |
da0436e9 | 833 | int lpfc_sli4_post_status_check(struct lpfc_hba *); |
a183a15f JS |
834 | uint8_t lpfc_sli_config_mbox_subsys_get(struct lpfc_hba *, LPFC_MBOXQ_t *); |
835 | uint8_t lpfc_sli_config_mbox_opcode_get(struct lpfc_hba *, LPFC_MBOXQ_t *); |