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[SCSI] aic7xxx: fix swapped arguments in ahc_find_pci_device
[mirror_ubuntu-bionic-kernel.git] / drivers / scsi / megaraid / megaraid_sas.h
CommitLineData
c4a3e0a5 1/*
3f1530c1 2 * Linux MegaRAID driver for SAS based RAID controllers
c4a3e0a5 3 *
ae59057b 4 * Copyright (c) 2003-2012 LSI Corporation.
c4a3e0a5 5 *
3f1530c1
AR		 6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
c4a3e0a5 10 *
3f1530c1
AR		 11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
c4a3e0a5 15 *
3f1530c1
AR		 16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * FILE: megaraid_sas.h
21 *
22 * Authors: LSI Corporation
23 *
24 * Send feedback to: <megaraidlinux@lsi.com>
25 *
26 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035
27 * ATTN: Linuxraid
c4a3e0a5
BS		 28 */
29
30#ifndef LSI_MEGARAID_SAS_H
31#define LSI_MEGARAID_SAS_H
32
a69b74d3 33/*
c4a3e0a5
BS		 34 * MegaRAID SAS Driver meta data
35 */
2b4857c3
AR		 36#define MEGASAS_VERSION "06.700.06.00-rc1"
37#define MEGASAS_RELDATE "Aug. 31, 2013"
38#define MEGASAS_EXT_VERSION "Sat. Aug. 31 17:00:00 PDT 2013"
0e98936c
SP		 39
40/*
41 * Device IDs
42 */
43#define PCI_DEVICE_ID_LSI_SAS1078R 0x0060
af7a5647 44#define PCI_DEVICE_ID_LSI_SAS1078DE 0x007C
0e98936c 45#define PCI_DEVICE_ID_LSI_VERDE_ZCR 0x0413
6610a6b3
YB		 46#define PCI_DEVICE_ID_LSI_SAS1078GEN2 0x0078
47#define PCI_DEVICE_ID_LSI_SAS0079GEN2 0x0079
87911122
YB		 48#define PCI_DEVICE_ID_LSI_SAS0073SKINNY 0x0073
49#define PCI_DEVICE_ID_LSI_SAS0071SKINNY 0x0071
9c915a8c 50#define PCI_DEVICE_ID_LSI_FUSION 0x005b
36807e67 51#define PCI_DEVICE_ID_LSI_INVADER 0x005d
21d3c710 52#define PCI_DEVICE_ID_LSI_FURY 0x005f
0e98936c 53
39b72c3c
SS		 54/*
55 * Intel HBA SSDIDs
56 */
57#define MEGARAID_INTEL_RS3DC080_SSDID 0x9360
58#define MEGARAID_INTEL_RS3DC040_SSDID 0x9362
59#define MEGARAID_INTEL_RS3SC008_SSDID 0x9380
60#define MEGARAID_INTEL_RS3MC044_SSDID 0x9381
61#define MEGARAID_INTEL_RS3WC080_SSDID 0x9341
62#define MEGARAID_INTEL_RS3WC040_SSDID 0x9343
63
64/*
65 * Intel HBA branding
66 */
67#define MEGARAID_INTEL_RS3DC080_BRANDING \
68 "Intel(R) RAID Controller RS3DC080"
69#define MEGARAID_INTEL_RS3DC040_BRANDING \
70 "Intel(R) RAID Controller RS3DC040"
71#define MEGARAID_INTEL_RS3SC008_BRANDING \
72 "Intel(R) RAID Controller RS3SC008"
73#define MEGARAID_INTEL_RS3MC044_BRANDING \
74 "Intel(R) RAID Controller RS3MC044"
75#define MEGARAID_INTEL_RS3WC080_BRANDING \
76 "Intel(R) RAID Controller RS3WC080"
77#define MEGARAID_INTEL_RS3WC040_BRANDING \
78 "Intel(R) RAID Controller RS3WC040"
79
c4a3e0a5
BS		 80/*
81 * =====================================
82 * MegaRAID SAS MFI firmware definitions
83 * =====================================
84 */
85
86/*
87 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker for
88 * protocol between the software and firmware. Commands are issued using
89 * "message frames"
90 */
91
a69b74d3 92/*
c4a3e0a5
BS		 93 * FW posts its state in upper 4 bits of outbound_msg_0 register
94 */
95#define MFI_STATE_MASK 0xF0000000
96#define MFI_STATE_UNDEFINED 0x00000000
97#define MFI_STATE_BB_INIT 0x10000000
98#define MFI_STATE_FW_INIT 0x40000000
99#define MFI_STATE_WAIT_HANDSHAKE 0x60000000
100#define MFI_STATE_FW_INIT_2 0x70000000
101#define MFI_STATE_DEVICE_SCAN 0x80000000
e3bbff9f 102#define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000
c4a3e0a5
BS		 103#define MFI_STATE_FLUSH_CACHE 0xA0000000
104#define MFI_STATE_READY 0xB0000000
105#define MFI_STATE_OPERATIONAL 0xC0000000
106#define MFI_STATE_FAULT 0xF0000000
7e70e733
AR		 107#define MFI_RESET_REQUIRED 0x00000001
108#define MFI_RESET_ADAPTER 0x00000002
c4a3e0a5
BS		 109#define MEGAMFI_FRAME_SIZE 64
110
a69b74d3 111/*
c4a3e0a5
BS		 112 * During FW init, clear pending cmds & reset state using inbound_msg_0
113 *
114 * ABORT : Abort all pending cmds
115 * READY : Move from OPERATIONAL to READY state; discard queue info
116 * MFIMODE : Discard (possible) low MFA posted in 64-bit mode (??)
117 * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
e3bbff9f
SP		 118 * HOTPLUG : Resume from Hotplug
119 * MFI_STOP_ADP : Send signal to FW to stop processing
c4a3e0a5 120 */
39a98554 121#define WRITE_SEQUENCE_OFFSET (0x0000000FC) /* I20 */
122#define HOST_DIAGNOSTIC_OFFSET (0x000000F8) /* I20 */
123#define DIAG_WRITE_ENABLE (0x00000080)
124#define DIAG_RESET_ADAPTER (0x00000004)
125
126#define MFI_ADP_RESET 0x00000040
e3bbff9f 127#define MFI_INIT_ABORT 0x00000001
c4a3e0a5
BS		 128#define MFI_INIT_READY 0x00000002
129#define MFI_INIT_MFIMODE 0x00000004
130#define MFI_INIT_CLEAR_HANDSHAKE 0x00000008
e3bbff9f
SP		 131#define MFI_INIT_HOTPLUG 0x00000010
132#define MFI_STOP_ADP 0x00000020
133#define MFI_RESET_FLAGS MFI_INIT_READY| \
134 MFI_INIT_MFIMODE| \
135 MFI_INIT_ABORT
c4a3e0a5 136
a69b74d3 137/*
c4a3e0a5
BS		 138 * MFI frame flags
139 */
140#define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000
141#define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001
142#define MFI_FRAME_SGL32 0x0000
143#define MFI_FRAME_SGL64 0x0002
144#define MFI_FRAME_SENSE32 0x0000
145#define MFI_FRAME_SENSE64 0x0004
146#define MFI_FRAME_DIR_NONE 0x0000
147#define MFI_FRAME_DIR_WRITE 0x0008
148#define MFI_FRAME_DIR_READ 0x0010
149#define MFI_FRAME_DIR_BOTH 0x0018
f4c9a131 150#define MFI_FRAME_IEEE 0x0020
c4a3e0a5 151
a69b74d3 152/*
c4a3e0a5
BS		 153 * Definition for cmd_status
154 */
155#define MFI_CMD_STATUS_POLL_MODE 0xFF
156
a69b74d3 157/*
c4a3e0a5
BS		 158 * MFI command opcodes
159 */
160#define MFI_CMD_INIT 0x00
161#define MFI_CMD_LD_READ 0x01
162#define MFI_CMD_LD_WRITE 0x02
163#define MFI_CMD_LD_SCSI_IO 0x03
164#define MFI_CMD_PD_SCSI_IO 0x04
165#define MFI_CMD_DCMD 0x05
166#define MFI_CMD_ABORT 0x06
167#define MFI_CMD_SMP 0x07
168#define MFI_CMD_STP 0x08
e5f93a36 169#define MFI_CMD_INVALID 0xff
c4a3e0a5
BS		 170
171#define MR_DCMD_CTRL_GET_INFO 0x01010000
bdc6fb8d 172#define MR_DCMD_LD_GET_LIST 0x03010000
21c9e160 173#define MR_DCMD_LD_LIST_QUERY 0x03010100
c4a3e0a5
BS		 174
175#define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000
176#define MR_FLUSH_CTRL_CACHE 0x01
177#define MR_FLUSH_DISK_CACHE 0x02
178
179#define MR_DCMD_CTRL_SHUTDOWN 0x01050000
31ea7088 180#define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000
c4a3e0a5
BS		 181#define MR_ENABLE_DRIVE_SPINDOWN 0x01
182
183#define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100
184#define MR_DCMD_CTRL_EVENT_GET 0x01040300
185#define MR_DCMD_CTRL_EVENT_WAIT 0x01040500
186#define MR_DCMD_LD_GET_PROPERTIES 0x03030000
187
188#define MR_DCMD_CLUSTER 0x08000000
189#define MR_DCMD_CLUSTER_RESET_ALL 0x08010100
190#define MR_DCMD_CLUSTER_RESET_LD 0x08010200
81e403ce 191#define MR_DCMD_PD_LIST_QUERY 0x02010100
c4a3e0a5 192
bc93d425
SS		 193/*
194 * Global functions
195 */
196extern u8 MR_ValidateMapInfo(struct megasas_instance *instance);
197
198
a69b74d3 199/*
c4a3e0a5
BS		 200 * MFI command completion codes
201 */
202enum MFI_STAT {
203 MFI_STAT_OK = 0x00,
204 MFI_STAT_INVALID_CMD = 0x01,
205 MFI_STAT_INVALID_DCMD = 0x02,
206 MFI_STAT_INVALID_PARAMETER = 0x03,
207 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04,
208 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05,
209 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06,
210 MFI_STAT_APP_IN_USE = 0x07,
211 MFI_STAT_APP_NOT_INITIALIZED = 0x08,
212 MFI_STAT_ARRAY_INDEX_INVALID = 0x09,
213 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a,
214 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b,
215 MFI_STAT_DEVICE_NOT_FOUND = 0x0c,
216 MFI_STAT_DRIVE_TOO_SMALL = 0x0d,
217 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e,
218 MFI_STAT_FLASH_BUSY = 0x0f,
219 MFI_STAT_FLASH_ERROR = 0x10,
220 MFI_STAT_FLASH_IMAGE_BAD = 0x11,
221 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12,
222 MFI_STAT_FLASH_NOT_OPEN = 0x13,
223 MFI_STAT_FLASH_NOT_STARTED = 0x14,
224 MFI_STAT_FLUSH_FAILED = 0x15,
225 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16,
226 MFI_STAT_LD_CC_IN_PROGRESS = 0x17,
227 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18,
228 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19,
229 MFI_STAT_LD_MAX_CONFIGURED = 0x1a,
230 MFI_STAT_LD_NOT_OPTIMAL = 0x1b,
231 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c,
232 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d,
233 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e,
234 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f,
235 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20,
236 MFI_STAT_MFC_HW_ERROR = 0x21,
237 MFI_STAT_NO_HW_PRESENT = 0x22,
238 MFI_STAT_NOT_FOUND = 0x23,
239 MFI_STAT_NOT_IN_ENCL = 0x24,
240 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25,
241 MFI_STAT_PD_TYPE_WRONG = 0x26,
242 MFI_STAT_PR_DISABLED = 0x27,
243 MFI_STAT_ROW_INDEX_INVALID = 0x28,
244 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29,
245 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a,
246 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b,
247 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c,
248 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d,
249 MFI_STAT_SCSI_IO_FAILED = 0x2e,
250 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f,
251 MFI_STAT_SHUTDOWN_FAILED = 0x30,
252 MFI_STAT_TIME_NOT_SET = 0x31,
253 MFI_STAT_WRONG_STATE = 0x32,
254 MFI_STAT_LD_OFFLINE = 0x33,
255 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34,
256 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35,
257 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36,
258 MFI_STAT_I2C_ERRORS_DETECTED = 0x37,
259 MFI_STAT_PCI_ERRORS_DETECTED = 0x38,
36807e67 260 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67,
c4a3e0a5
BS		 261
262 MFI_STAT_INVALID_STATUS = 0xFF
263};
264
265/*
266 * Number of mailbox bytes in DCMD message frame
267 */
268#define MFI_MBOX_SIZE 12
269
270enum MR_EVT_CLASS {
271
272 MR_EVT_CLASS_DEBUG = -2,
273 MR_EVT_CLASS_PROGRESS = -1,
274 MR_EVT_CLASS_INFO = 0,
275 MR_EVT_CLASS_WARNING = 1,
276 MR_EVT_CLASS_CRITICAL = 2,
277 MR_EVT_CLASS_FATAL = 3,
278 MR_EVT_CLASS_DEAD = 4,
279
280};
281
282enum MR_EVT_LOCALE {
283
284 MR_EVT_LOCALE_LD = 0x0001,
285 MR_EVT_LOCALE_PD = 0x0002,
286 MR_EVT_LOCALE_ENCL = 0x0004,
287 MR_EVT_LOCALE_BBU = 0x0008,
288 MR_EVT_LOCALE_SAS = 0x0010,
289 MR_EVT_LOCALE_CTRL = 0x0020,
290 MR_EVT_LOCALE_CONFIG = 0x0040,
291 MR_EVT_LOCALE_CLUSTER = 0x0080,
292 MR_EVT_LOCALE_ALL = 0xffff,
293
294};
295
296enum MR_EVT_ARGS {
297
298 MR_EVT_ARGS_NONE,
299 MR_EVT_ARGS_CDB_SENSE,
300 MR_EVT_ARGS_LD,
301 MR_EVT_ARGS_LD_COUNT,
302 MR_EVT_ARGS_LD_LBA,
303 MR_EVT_ARGS_LD_OWNER,
304 MR_EVT_ARGS_LD_LBA_PD_LBA,
305 MR_EVT_ARGS_LD_PROG,
306 MR_EVT_ARGS_LD_STATE,
307 MR_EVT_ARGS_LD_STRIP,
308 MR_EVT_ARGS_PD,
309 MR_EVT_ARGS_PD_ERR,
310 MR_EVT_ARGS_PD_LBA,
311 MR_EVT_ARGS_PD_LBA_LD,
312 MR_EVT_ARGS_PD_PROG,
313 MR_EVT_ARGS_PD_STATE,
314 MR_EVT_ARGS_PCI,
315 MR_EVT_ARGS_RATE,
316 MR_EVT_ARGS_STR,
317 MR_EVT_ARGS_TIME,
318 MR_EVT_ARGS_ECC,
81e403ce
YB		 319 MR_EVT_ARGS_LD_PROP,
320 MR_EVT_ARGS_PD_SPARE,
321 MR_EVT_ARGS_PD_INDEX,
322 MR_EVT_ARGS_DIAG_PASS,
323 MR_EVT_ARGS_DIAG_FAIL,
324 MR_EVT_ARGS_PD_LBA_LBA,
325 MR_EVT_ARGS_PORT_PHY,
326 MR_EVT_ARGS_PD_MISSING,
327 MR_EVT_ARGS_PD_ADDRESS,
328 MR_EVT_ARGS_BITMAP,
329 MR_EVT_ARGS_CONNECTOR,
330 MR_EVT_ARGS_PD_PD,
331 MR_EVT_ARGS_PD_FRU,
332 MR_EVT_ARGS_PD_PATHINFO,
333 MR_EVT_ARGS_PD_POWER_STATE,
334 MR_EVT_ARGS_GENERIC,
335};
c4a3e0a5 336
81e403ce
YB		 337/*
338 * define constants for device list query options
339 */
340enum MR_PD_QUERY_TYPE {
341 MR_PD_QUERY_TYPE_ALL = 0,
342 MR_PD_QUERY_TYPE_STATE = 1,
343 MR_PD_QUERY_TYPE_POWER_STATE = 2,
344 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3,
345 MR_PD_QUERY_TYPE_SPEED = 4,
346 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5,
c4a3e0a5
BS		 347};
348
21c9e160
AR		 349enum MR_LD_QUERY_TYPE {
350 MR_LD_QUERY_TYPE_ALL = 0,
351 MR_LD_QUERY_TYPE_EXPOSED_TO_HOST = 1,
352 MR_LD_QUERY_TYPE_USED_TGT_IDS = 2,
353 MR_LD_QUERY_TYPE_CLUSTER_ACCESS = 3,
354 MR_LD_QUERY_TYPE_CLUSTER_LOCALE = 4,
355};
356
357
7e8a75f4
YB		 358#define MR_EVT_CFG_CLEARED 0x0004
359#define MR_EVT_LD_STATE_CHANGE 0x0051
360#define MR_EVT_PD_INSERTED 0x005b
361#define MR_EVT_PD_REMOVED 0x0070
362#define MR_EVT_LD_CREATED 0x008a
363#define MR_EVT_LD_DELETED 0x008b
364#define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db
365#define MR_EVT_LD_OFFLINE 0x00fc
366#define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152
367#define MAX_LOGICAL_DRIVES 64
368
81e403ce
YB		 369enum MR_PD_STATE {
370 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00,
371 MR_PD_STATE_UNCONFIGURED_BAD = 0x01,
372 MR_PD_STATE_HOT_SPARE = 0x02,
373 MR_PD_STATE_OFFLINE = 0x10,
374 MR_PD_STATE_FAILED = 0x11,
375 MR_PD_STATE_REBUILD = 0x14,
376 MR_PD_STATE_ONLINE = 0x18,
377 MR_PD_STATE_COPYBACK = 0x20,
378 MR_PD_STATE_SYSTEM = 0x40,
379 };
380
381
382 /*
383 * defines the physical drive address structure
384 */
385struct MR_PD_ADDRESS {
386 u16 deviceId;
387 u16 enclDeviceId;
388
389 union {
390 struct {
391 u8 enclIndex;
392 u8 slotNumber;
393 } mrPdAddress;
394 struct {
395 u8 enclPosition;
396 u8 enclConnectorIndex;
397 } mrEnclAddress;
398 };
399 u8 scsiDevType;
400 union {
401 u8 connectedPortBitmap;
402 u8 connectedPortNumbers;
403 };
404 u64 sasAddr[2];
405} __packed;
406
407/*
408 * defines the physical drive list structure
409 */
410struct MR_PD_LIST {
411 u32 size;
412 u32 count;
413 struct MR_PD_ADDRESS addr[1];
414} __packed;
415
416struct megasas_pd_list {
417 u16 tid;
418 u8 driveType;
419 u8 driveState;
420} __packed;
421
bdc6fb8d
YB		 422 /*
423 * defines the logical drive reference structure
424 */
425union MR_LD_REF {
426 struct {
427 u8 targetId;
428 u8 reserved;
429 u16 seqNum;
430 };
431 u32 ref;
432} __packed;
433
434/*
435 * defines the logical drive list structure
436 */
437struct MR_LD_LIST {
438 u32 ldCount;
439 u32 reserved;
440 struct {
441 union MR_LD_REF ref;
442 u8 state;
443 u8 reserved[3];
444 u64 size;
445 } ldList[MAX_LOGICAL_DRIVES];
446} __packed;
447
21c9e160
AR		 448struct MR_LD_TARGETID_LIST {
449 u32 size;
450 u32 count;
451 u8 pad[3];
452 u8 targetId[MAX_LOGICAL_DRIVES];
453};
454
455
c4a3e0a5
BS		 456/*
457 * SAS controller properties
458 */
459struct megasas_ctrl_prop {
460
461 u16 seq_num;
462 u16 pred_fail_poll_interval;
463 u16 intr_throttle_count;
464 u16 intr_throttle_timeouts;
465 u8 rebuild_rate;
466 u8 patrol_read_rate;
467 u8 bgi_rate;
468 u8 cc_rate;
469 u8 recon_rate;
470 u8 cache_flush_interval;
471 u8 spinup_drv_count;
472 u8 spinup_delay;
473 u8 cluster_enable;
474 u8 coercion_mode;
475 u8 alarm_enable;
476 u8 disable_auto_rebuild;
477 u8 disable_battery_warn;
478 u8 ecc_bucket_size;
479 u16 ecc_bucket_leak_rate;
480 u8 restore_hotspare_on_insertion;
481 u8 expose_encl_devices;
39a98554 482 u8 maintainPdFailHistory;
483 u8 disallowHostRequestReordering;
484 u8 abortCCOnError;
485 u8 loadBalanceMode;
486 u8 disableAutoDetectBackplane;
487
488 u8 snapVDSpace;
489
490 /*
491 * Add properties that can be controlled by
492 * a bit in the following structure.
493 */
39a98554 494 struct {
495 u32 copyBackDisabled : 1;
496 u32 SMARTerEnabled : 1;
497 u32 prCorrectUnconfiguredAreas : 1;
498 u32 useFdeOnly : 1;
499 u32 disableNCQ : 1;
500 u32 SSDSMARTerEnabled : 1;
501 u32 SSDPatrolReadEnabled : 1;
502 u32 enableSpinDownUnconfigured : 1;
503 u32 autoEnhancedImport : 1;
504 u32 enableSecretKeyControl : 1;
505 u32 disableOnlineCtrlReset : 1;
506 u32 allowBootWithPinnedCache : 1;
507 u32 disableSpinDownHS : 1;
508 u32 enableJBOD : 1;
509 u32 reserved :18;
510 } OnOffProperties;
511 u8 autoSnapVDSpace;
512 u8 viewSpace;
513 u16 spinDownTime;
514 u8 reserved[24];
81e403ce 515} __packed;
c4a3e0a5
BS		 516
517/*
518 * SAS controller information
519 */
520struct megasas_ctrl_info {
521
522 /*
523 * PCI device information
524 */
525 struct {
526
527 u16 vendor_id;
528 u16 device_id;
529 u16 sub_vendor_id;
530 u16 sub_device_id;
531 u8 reserved[24];
532
533 } __attribute__ ((packed)) pci;
534
535 /*
536 * Host interface information
537 */
538 struct {
539
540 u8 PCIX:1;
541 u8 PCIE:1;
542 u8 iSCSI:1;
543 u8 SAS_3G:1;
544 u8 reserved_0:4;
545 u8 reserved_1[6];
546 u8 port_count;
547 u64 port_addr[8];
548
549 } __attribute__ ((packed)) host_interface;
550
551 /*
552 * Device (backend) interface information
553 */
554 struct {
555
556 u8 SPI:1;
557 u8 SAS_3G:1;
558 u8 SATA_1_5G:1;
559 u8 SATA_3G:1;
560 u8 reserved_0:4;
561 u8 reserved_1[6];
562 u8 port_count;
563 u64 port_addr[8];
564
565 } __attribute__ ((packed)) device_interface;
566
567 /*
568 * List of components residing in flash. All str are null terminated
569 */
570 u32 image_check_word;
571 u32 image_component_count;
572
573 struct {
574
575 char name[8];
576 char version[32];
577 char build_date[16];
578 char built_time[16];
579
580 } __attribute__ ((packed)) image_component[8];
581
582 /*
583 * List of flash components that have been flashed on the card, but
584 * are not in use, pending reset of the adapter. This list will be
585 * empty if a flash operation has not occurred. All stings are null
586 * terminated
587 */
588 u32 pending_image_component_count;
589
590 struct {
591
592 char name[8];
593 char version[32];
594 char build_date[16];
595 char build_time[16];
596
597 } __attribute__ ((packed)) pending_image_component[8];
598
599 u8 max_arms;
600 u8 max_spans;
601 u8 max_arrays;
602 u8 max_lds;
603
604 char product_name[80];
605 char serial_no[32];
606
607 /*
608 * Other physical/controller/operation information. Indicates the
609 * presence of the hardware
610 */
611 struct {
612
613 u32 bbu:1;
614 u32 alarm:1;
615 u32 nvram:1;
616 u32 uart:1;
617 u32 reserved:28;
618
619 } __attribute__ ((packed)) hw_present;
620
621 u32 current_fw_time;
622
623 /*
624 * Maximum data transfer sizes
625 */
626 u16 max_concurrent_cmds;
627 u16 max_sge_count;
628 u32 max_request_size;
629
630 /*
631 * Logical and physical device counts
632 */
633 u16 ld_present_count;
634 u16 ld_degraded_count;
635 u16 ld_offline_count;
636
637 u16 pd_present_count;
638 u16 pd_disk_present_count;
639 u16 pd_disk_pred_failure_count;
640 u16 pd_disk_failed_count;
641
642 /*
643 * Memory size information
644 */
645 u16 nvram_size;
646 u16 memory_size;
647 u16 flash_size;
648
649 /*
650 * Error counters
651 */
652 u16 mem_correctable_error_count;
653 u16 mem_uncorrectable_error_count;
654
655 /*
656 * Cluster information
657 */
658 u8 cluster_permitted;
659 u8 cluster_active;
660
661 /*
662 * Additional max data transfer sizes
663 */
664 u16 max_strips_per_io;
665
666 /*
667 * Controller capabilities structures
668 */
669 struct {
670
671 u32 raid_level_0:1;
672 u32 raid_level_1:1;
673 u32 raid_level_5:1;
674 u32 raid_level_1E:1;
675 u32 raid_level_6:1;
676 u32 reserved:27;
677
678 } __attribute__ ((packed)) raid_levels;
679
680 struct {
681
682 u32 rbld_rate:1;
683 u32 cc_rate:1;
684 u32 bgi_rate:1;
685 u32 recon_rate:1;
686 u32 patrol_rate:1;
687 u32 alarm_control:1;
688 u32 cluster_supported:1;
689 u32 bbu:1;
690 u32 spanning_allowed:1;
691 u32 dedicated_hotspares:1;
692 u32 revertible_hotspares:1;
693 u32 foreign_config_import:1;
694 u32 self_diagnostic:1;
695 u32 mixed_redundancy_arr:1;
696 u32 global_hot_spares:1;
697 u32 reserved:17;
698
699 } __attribute__ ((packed)) adapter_operations;
700
701 struct {
702
703 u32 read_policy:1;
704 u32 write_policy:1;
705 u32 io_policy:1;
706 u32 access_policy:1;
707 u32 disk_cache_policy:1;
708 u32 reserved:27;
709
710 } __attribute__ ((packed)) ld_operations;
711
712 struct {
713
714 u8 min;
715 u8 max;
716 u8 reserved[2];
717
718 } __attribute__ ((packed)) stripe_sz_ops;
719
720 struct {
721
722 u32 force_online:1;
723 u32 force_offline:1;
724 u32 force_rebuild:1;
725 u32 reserved:29;
726
727 } __attribute__ ((packed)) pd_operations;
728
729 struct {
730
731 u32 ctrl_supports_sas:1;
732 u32 ctrl_supports_sata:1;
733 u32 allow_mix_in_encl:1;
734 u32 allow_mix_in_ld:1;
735 u32 allow_sata_in_cluster:1;
736 u32 reserved:27;
737
738 } __attribute__ ((packed)) pd_mix_support;
739
740 /*
741 * Define ECC single-bit-error bucket information
742 */
743 u8 ecc_bucket_count;
744 u8 reserved_2[11];
745
746 /*
747 * Include the controller properties (changeable items)
748 */
749 struct megasas_ctrl_prop properties;
750
751 /*
752 * Define FW pkg version (set in envt v'bles on OEM basis)
753 */
754 char package_version[0x60];
755
c4a3e0a5 756
bc93d425
SS		 757 /*
758 * If adapterOperations.supportMoreThan8Phys is set,
759 * and deviceInterface.portCount is greater than 8,
760 * SAS Addrs for first 8 ports shall be populated in
761 * deviceInterface.portAddr, and the rest shall be
762 * populated in deviceInterfacePortAddr2.
763 */
764 u64 deviceInterfacePortAddr2[8]; /*6a0h */
765 u8 reserved3[128]; /*6e0h */
766
767 struct { /*760h */
768 u16 minPdRaidLevel_0:4;
769 u16 maxPdRaidLevel_0:12;
770
771 u16 minPdRaidLevel_1:4;
772 u16 maxPdRaidLevel_1:12;
773
774 u16 minPdRaidLevel_5:4;
775 u16 maxPdRaidLevel_5:12;
776
777 u16 minPdRaidLevel_1E:4;
778 u16 maxPdRaidLevel_1E:12;
779
780 u16 minPdRaidLevel_6:4;
781 u16 maxPdRaidLevel_6:12;
782
783 u16 minPdRaidLevel_10:4;
784 u16 maxPdRaidLevel_10:12;
785
786 u16 minPdRaidLevel_50:4;
787 u16 maxPdRaidLevel_50:12;
788
789 u16 minPdRaidLevel_60:4;
790 u16 maxPdRaidLevel_60:12;
791
792 u16 minPdRaidLevel_1E_RLQ0:4;
793 u16 maxPdRaidLevel_1E_RLQ0:12;
794
795 u16 minPdRaidLevel_1E0_RLQ0:4;
796 u16 maxPdRaidLevel_1E0_RLQ0:12;
797
798 u16 reserved[6];
799 } pdsForRaidLevels;
800
801 u16 maxPds; /*780h */
802 u16 maxDedHSPs; /*782h */
803 u16 maxGlobalHSPs; /*784h */
804 u16 ddfSize; /*786h */
805 u8 maxLdsPerArray; /*788h */
806 u8 partitionsInDDF; /*789h */
807 u8 lockKeyBinding; /*78ah */
808 u8 maxPITsPerLd; /*78bh */
809 u8 maxViewsPerLd; /*78ch */
810 u8 maxTargetId; /*78dh */
811 u16 maxBvlVdSize; /*78eh */
812
813 u16 maxConfigurableSSCSize; /*790h */
814 u16 currentSSCsize; /*792h */
815
816 char expanderFwVersion[12]; /*794h */
817
818 u16 PFKTrialTimeRemaining; /*7A0h */
819
820 u16 cacheMemorySize; /*7A2h */
821
822 struct { /*7A4h */
823 u32 supportPIcontroller:1;
824 u32 supportLdPIType1:1;
825 u32 supportLdPIType2:1;
826 u32 supportLdPIType3:1;
827 u32 supportLdBBMInfo:1;
828 u32 supportShieldState:1;
829 u32 blockSSDWriteCacheChange:1;
830 u32 supportSuspendResumeBGops:1;
831 u32 supportEmergencySpares:1;
832 u32 supportSetLinkSpeed:1;
833 u32 supportBootTimePFKChange:1;
834 u32 supportJBOD:1;
835 u32 disableOnlinePFKChange:1;
836 u32 supportPerfTuning:1;
837 u32 supportSSDPatrolRead:1;
838 u32 realTimeScheduler:1;
839
840 u32 supportResetNow:1;
841 u32 supportEmulatedDrives:1;
842 u32 headlessMode:1;
843 u32 dedicatedHotSparesLimited:1;
844
845
846 u32 supportUnevenSpans:1;
847 u32 reserved:11;
848 } adapterOperations2;
849
850 u8 driverVersion[32]; /*7A8h */
851 u8 maxDAPdCountSpinup60; /*7C8h */
852 u8 temperatureROC; /*7C9h */
853 u8 temperatureCtrl; /*7CAh */
854 u8 reserved4; /*7CBh */
855 u16 maxConfigurablePds; /*7CCh */
856
857
858 u8 reserved5[2]; /*0x7CDh */
859
860 /*
861 * HA cluster information
862 */
863 struct {
864 u32 peerIsPresent:1;
865 u32 peerIsIncompatible:1;
866 u32 hwIncompatible:1;
867 u32 fwVersionMismatch:1;
868 u32 ctrlPropIncompatible:1;
869 u32 premiumFeatureMismatch:1;
870 u32 reserved:26;
871 } cluster;
872
873 char clusterId[16]; /*7D4h */
874
875 u8 pad[0x800-0x7E4]; /*7E4 */
81e403ce 876} __packed;
c4a3e0a5
BS		 877
878/*
879 * ===============================
880 * MegaRAID SAS driver definitions
881 * ===============================
882 */
883#define MEGASAS_MAX_PD_CHANNELS 2
21c9e160 884#define MEGASAS_MAX_LD_CHANNELS 1
c4a3e0a5
BS		 885#define MEGASAS_MAX_CHANNELS (MEGASAS_MAX_PD_CHANNELS + \
886 MEGASAS_MAX_LD_CHANNELS)
887#define MEGASAS_MAX_DEV_PER_CHANNEL 128
888#define MEGASAS_DEFAULT_INIT_ID -1
889#define MEGASAS_MAX_LUN 8
890#define MEGASAS_MAX_LD 64
6bf579a3 891#define MEGASAS_DEFAULT_CMD_PER_LUN 256
81e403ce
YB		 892#define MEGASAS_MAX_PD (MEGASAS_MAX_PD_CHANNELS * \
893 MEGASAS_MAX_DEV_PER_CHANNEL)
bdc6fb8d
YB		 894#define MEGASAS_MAX_LD_IDS (MEGASAS_MAX_LD_CHANNELS * \
895 MEGASAS_MAX_DEV_PER_CHANNEL)
c4a3e0a5 896
1fd10685 897#define MEGASAS_MAX_SECTORS (2*1024)
42a8d2b3 898#define MEGASAS_MAX_SECTORS_IEEE (2*128)
658dcedb
SP		 899#define MEGASAS_DBG_LVL 1
900
05e9ebbe
SP		 901#define MEGASAS_FW_BUSY 1
902
d532dbe2 903/* Frame Type */
904#define IO_FRAME 0
905#define PTHRU_FRAME 1
906
c4a3e0a5
BS		 907/*
908 * When SCSI mid-layer calls driver's reset routine, driver waits for
909 * MEGASAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note
910 * that the driver cannot _actually_ abort or reset pending commands. While
911 * it is waiting for the commands to complete, it prints a diagnostic message
912 * every MEGASAS_RESET_NOTICE_INTERVAL seconds
913 */
914#define MEGASAS_RESET_WAIT_TIME 180
2a3681e5 915#define MEGASAS_INTERNAL_CMD_WAIT_TIME 180
c4a3e0a5 916#define MEGASAS_RESET_NOTICE_INTERVAL 5
c4a3e0a5 917#define MEGASAS_IOCTL_CMD 0
05e9ebbe 918#define MEGASAS_DEFAULT_CMD_TIMEOUT 90
c5daa6a9 919#define MEGASAS_THROTTLE_QUEUE_DEPTH 16
c4a3e0a5
BS		 920
921/*
922 * FW reports the maximum of number of commands that it can accept (maximum
923 * commands that can be outstanding) at any time. The driver must report a
924 * lower number to the mid layer because it can issue a few internal commands
925 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs
926 * is shown below
927 */
928#define MEGASAS_INT_CMDS 32
7bebf5c7 929#define MEGASAS_SKINNY_INT_CMDS 5
c4a3e0a5 930
d46a3ad6 931#define MEGASAS_MAX_MSIX_QUEUES 128
c4a3e0a5
BS		 932/*
933 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
934 * SGLs based on the size of dma_addr_t
935 */
936#define IS_DMA64 (sizeof(dma_addr_t) == 8)
937
39a98554 938#define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001
939
940#define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001
941#define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002
942#define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004
943
c4a3e0a5 944#define MFI_OB_INTR_STATUS_MASK 0x00000002
14faea9f 945#define MFI_POLL_TIMEOUT_SECS 60
c4a3e0a5 946
f9876f0b 947#define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000
6610a6b3
YB		 948#define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001
949#define MFI_GEN2_ENABLE_INTERRUPT_MASK (0x00000001 | 0x00000004)
87911122
YB		 950#define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000
951#define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001)
0e98936c 952
39a98554 953#define MFI_1068_PCSR_OFFSET 0x84
954#define MFI_1068_FW_HANDSHAKE_OFFSET 0x64
955#define MFI_1068_FW_READY 0xDDDD0000
d46a3ad6
SS		 956
957#define MR_MAX_REPLY_QUEUES_OFFSET 0X0000001F
958#define MR_MAX_REPLY_QUEUES_EXT_OFFSET 0X003FC000
959#define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14
960#define MR_MAX_MSIX_REG_ARRAY 16
0e98936c
SP		 961/*
962* register set for both 1068 and 1078 controllers
963* structure extended for 1078 registers
964*/
f9876f0b 965
c4a3e0a5 966struct megasas_register_set {
9c915a8c
AR		 967 u32 doorbell; /*0000h*/
968 u32 fusion_seq_offset; /*0004h*/
969 u32 fusion_host_diag; /*0008h*/
970 u32 reserved_01; /*000Ch*/
c4a3e0a5 971
f9876f0b
SP		 972 u32 inbound_msg_0; /*0010h*/
973 u32 inbound_msg_1; /*0014h*/
974 u32 outbound_msg_0; /*0018h*/
975 u32 outbound_msg_1; /*001Ch*/
c4a3e0a5 976
f9876f0b
SP		 977 u32 inbound_doorbell; /*0020h*/
978 u32 inbound_intr_status; /*0024h*/
979 u32 inbound_intr_mask; /*0028h*/
c4a3e0a5 980
f9876f0b
SP		 981 u32 outbound_doorbell; /*002Ch*/
982 u32 outbound_intr_status; /*0030h*/
983 u32 outbound_intr_mask; /*0034h*/
c4a3e0a5 984
f9876f0b 985 u32 reserved_1[2]; /*0038h*/
c4a3e0a5 986
f9876f0b
SP		 987 u32 inbound_queue_port; /*0040h*/
988 u32 outbound_queue_port; /*0044h*/
c4a3e0a5 989
9c915a8c
AR		 990 u32 reserved_2[9]; /*0048h*/
991 u32 reply_post_host_index; /*006Ch*/
992 u32 reserved_2_2[12]; /*0070h*/
c4a3e0a5 993
f9876f0b 994 u32 outbound_doorbell_clear; /*00A0h*/
c4a3e0a5 995
f9876f0b
SP		 996 u32 reserved_3[3]; /*00A4h*/
997
998 u32 outbound_scratch_pad ; /*00B0h*/
9c915a8c 999 u32 outbound_scratch_pad_2; /*00B4h*/
f9876f0b 1000
9c915a8c 1001 u32 reserved_4[2]; /*00B8h*/
f9876f0b
SP		 1002
1003 u32 inbound_low_queue_port ; /*00C0h*/
1004
1005 u32 inbound_high_queue_port ; /*00C4h*/
1006
1007 u32 reserved_5; /*00C8h*/
39a98554 1008 u32 res_6[11]; /*CCh*/
1009 u32 host_diag;
1010 u32 seq_offset;
1011 u32 index_registers[807]; /*00CCh*/
c4a3e0a5
BS		 1012} __attribute__ ((packed));
1013
1014struct megasas_sge32 {
1015
1016 u32 phys_addr;
1017 u32 length;
1018
1019} __attribute__ ((packed));
1020
1021struct megasas_sge64 {
1022
1023 u64 phys_addr;
1024 u32 length;
1025
1026} __attribute__ ((packed));
1027
f4c9a131
YB		 1028struct megasas_sge_skinny {
1029 u64 phys_addr;
1030 u32 length;
1031 u32 flag;
1032} __packed;
1033
c4a3e0a5
BS		 1034union megasas_sgl {
1035
1036 struct megasas_sge32 sge32[1];
1037 struct megasas_sge64 sge64[1];
f4c9a131 1038 struct megasas_sge_skinny sge_skinny[1];
c4a3e0a5
BS		 1039
1040} __attribute__ ((packed));
1041
1042struct megasas_header {
1043
1044 u8 cmd; /*00h */
1045 u8 sense_len; /*01h */
1046 u8 cmd_status; /*02h */
1047 u8 scsi_status; /*03h */
1048
1049 u8 target_id; /*04h */
1050 u8 lun; /*05h */
1051 u8 cdb_len; /*06h */
1052 u8 sge_count; /*07h */
1053
1054 u32 context; /*08h */
1055 u32 pad_0; /*0Ch */
1056
1057 u16 flags; /*10h */
1058 u16 timeout; /*12h */
1059 u32 data_xferlen; /*14h */
1060
1061} __attribute__ ((packed));
1062
1063union megasas_sgl_frame {
1064
1065 struct megasas_sge32 sge32[8];
1066 struct megasas_sge64 sge64[5];
1067
1068} __attribute__ ((packed));
1069
d46a3ad6
SS		 1070typedef union _MFI_CAPABILITIES {
1071 struct {
1072 u32 support_fp_remote_lun:1;
1073 u32 support_additional_msix:1;
1074 u32 reserved:30;
1075 } mfi_capabilities;
1076 u32 reg;
1077} MFI_CAPABILITIES;
1078
c4a3e0a5
BS		 1079struct megasas_init_frame {
1080
1081 u8 cmd; /*00h */
1082 u8 reserved_0; /*01h */
1083 u8 cmd_status; /*02h */
1084
1085 u8 reserved_1; /*03h */
d46a3ad6 1086 MFI_CAPABILITIES driver_operations; /*04h*/
c4a3e0a5
BS		 1087
1088 u32 context; /*08h */
1089 u32 pad_0; /*0Ch */
1090
1091 u16 flags; /*10h */
1092 u16 reserved_3; /*12h */
1093 u32 data_xfer_len; /*14h */
1094
1095 u32 queue_info_new_phys_addr_lo; /*18h */
1096 u32 queue_info_new_phys_addr_hi; /*1Ch */
1097 u32 queue_info_old_phys_addr_lo; /*20h */
1098 u32 queue_info_old_phys_addr_hi; /*24h */
1099
1100 u32 reserved_4[6]; /*28h */
1101
1102} __attribute__ ((packed));
1103
1104struct megasas_init_queue_info {
1105
1106 u32 init_flags; /*00h */
1107 u32 reply_queue_entries; /*04h */
1108
1109 u32 reply_queue_start_phys_addr_lo; /*08h */
1110 u32 reply_queue_start_phys_addr_hi; /*0Ch */
1111 u32 producer_index_phys_addr_lo; /*10h */
1112 u32 producer_index_phys_addr_hi; /*14h */
1113 u32 consumer_index_phys_addr_lo; /*18h */
1114 u32 consumer_index_phys_addr_hi; /*1Ch */
1115
1116} __attribute__ ((packed));
1117
1118struct megasas_io_frame {
1119
1120 u8 cmd; /*00h */
1121 u8 sense_len; /*01h */
1122 u8 cmd_status; /*02h */
1123 u8 scsi_status; /*03h */
1124
1125 u8 target_id; /*04h */
1126 u8 access_byte; /*05h */
1127 u8 reserved_0; /*06h */
1128 u8 sge_count; /*07h */
1129
1130 u32 context; /*08h */
1131 u32 pad_0; /*0Ch */
1132
1133 u16 flags; /*10h */
1134 u16 timeout; /*12h */
1135 u32 lba_count; /*14h */
1136
1137 u32 sense_buf_phys_addr_lo; /*18h */
1138 u32 sense_buf_phys_addr_hi; /*1Ch */
1139
1140 u32 start_lba_lo; /*20h */
1141 u32 start_lba_hi; /*24h */
1142
1143 union megasas_sgl sgl; /*28h */
1144
1145} __attribute__ ((packed));
1146
1147struct megasas_pthru_frame {
1148
1149 u8 cmd; /*00h */
1150 u8 sense_len; /*01h */
1151 u8 cmd_status; /*02h */
1152 u8 scsi_status; /*03h */
1153
1154 u8 target_id; /*04h */
1155 u8 lun; /*05h */
1156 u8 cdb_len; /*06h */
1157 u8 sge_count; /*07h */
1158
1159 u32 context; /*08h */
1160 u32 pad_0; /*0Ch */
1161
1162 u16 flags; /*10h */
1163 u16 timeout; /*12h */
1164 u32 data_xfer_len; /*14h */
1165
1166 u32 sense_buf_phys_addr_lo; /*18h */
1167 u32 sense_buf_phys_addr_hi; /*1Ch */
1168
1169 u8 cdb[16]; /*20h */
1170 union megasas_sgl sgl; /*30h */
1171
1172} __attribute__ ((packed));
1173
1174struct megasas_dcmd_frame {
1175
1176 u8 cmd; /*00h */
1177 u8 reserved_0; /*01h */
1178 u8 cmd_status; /*02h */
1179 u8 reserved_1[4]; /*03h */
1180 u8 sge_count; /*07h */
1181
1182 u32 context; /*08h */
1183 u32 pad_0; /*0Ch */
1184
1185 u16 flags; /*10h */
1186 u16 timeout; /*12h */
1187
1188 u32 data_xfer_len; /*14h */
1189 u32 opcode; /*18h */
1190
1191 union { /*1Ch */
1192 u8 b[12];
1193 u16 s[6];
1194 u32 w[3];
1195 } mbox;
1196
1197 union megasas_sgl sgl; /*28h */
1198
1199} __attribute__ ((packed));
1200
1201struct megasas_abort_frame {
1202
1203 u8 cmd; /*00h */
1204 u8 reserved_0; /*01h */
1205 u8 cmd_status; /*02h */
1206
1207 u8 reserved_1; /*03h */
1208 u32 reserved_2; /*04h */
1209
1210 u32 context; /*08h */
1211 u32 pad_0; /*0Ch */
1212
1213 u16 flags; /*10h */
1214 u16 reserved_3; /*12h */
1215 u32 reserved_4; /*14h */
1216
1217 u32 abort_context; /*18h */
1218 u32 pad_1; /*1Ch */
1219
1220 u32 abort_mfi_phys_addr_lo; /*20h */
1221 u32 abort_mfi_phys_addr_hi; /*24h */
1222
1223 u32 reserved_5[6]; /*28h */
1224
1225} __attribute__ ((packed));
1226
1227struct megasas_smp_frame {
1228
1229 u8 cmd; /*00h */
1230 u8 reserved_1; /*01h */
1231 u8 cmd_status; /*02h */
1232 u8 connection_status; /*03h */
1233
1234 u8 reserved_2[3]; /*04h */
1235 u8 sge_count; /*07h */
1236
1237 u32 context; /*08h */
1238 u32 pad_0; /*0Ch */
1239
1240 u16 flags; /*10h */
1241 u16 timeout; /*12h */
1242
1243 u32 data_xfer_len; /*14h */
1244 u64 sas_addr; /*18h */
1245
1246 union {
1247 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: req */
1248 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: req */
1249 } sgl;
1250
1251} __attribute__ ((packed));
1252
1253struct megasas_stp_frame {
1254
1255 u8 cmd; /*00h */
1256 u8 reserved_1; /*01h */
1257 u8 cmd_status; /*02h */
1258 u8 reserved_2; /*03h */
1259
1260 u8 target_id; /*04h */
1261 u8 reserved_3[2]; /*05h */
1262 u8 sge_count; /*07h */
1263
1264 u32 context; /*08h */
1265 u32 pad_0; /*0Ch */
1266
1267 u16 flags; /*10h */
1268 u16 timeout; /*12h */
1269
1270 u32 data_xfer_len; /*14h */
1271
1272 u16 fis[10]; /*18h */
1273 u32 stp_flags;
1274
1275 union {
1276 struct megasas_sge32 sge32[2]; /* [0]: resp [1]: data */
1277 struct megasas_sge64 sge64[2]; /* [0]: resp [1]: data */
1278 } sgl;
1279
1280} __attribute__ ((packed));
1281
1282union megasas_frame {
1283
1284 struct megasas_header hdr;
1285 struct megasas_init_frame init;
1286 struct megasas_io_frame io;
1287 struct megasas_pthru_frame pthru;
1288 struct megasas_dcmd_frame dcmd;
1289 struct megasas_abort_frame abort;
1290 struct megasas_smp_frame smp;
1291 struct megasas_stp_frame stp;
1292
1293 u8 raw_bytes[64];
1294};
1295
1296struct megasas_cmd;
1297
1298union megasas_evt_class_locale {
1299
1300 struct {
1301 u16 locale;
1302 u8 reserved;
1303 s8 class;
1304 } __attribute__ ((packed)) members;
1305
1306 u32 word;
1307
1308} __attribute__ ((packed));
1309
1310struct megasas_evt_log_info {
1311 u32 newest_seq_num;
1312 u32 oldest_seq_num;
1313 u32 clear_seq_num;
1314 u32 shutdown_seq_num;
1315 u32 boot_seq_num;
1316
1317} __attribute__ ((packed));
1318
1319struct megasas_progress {
1320
1321 u16 progress;
1322 u16 elapsed_seconds;
1323
1324} __attribute__ ((packed));
1325
1326struct megasas_evtarg_ld {
1327
1328 u16 target_id;
1329 u8 ld_index;
1330 u8 reserved;
1331
1332} __attribute__ ((packed));
1333
1334struct megasas_evtarg_pd {
1335 u16 device_id;
1336 u8 encl_index;
1337 u8 slot_number;
1338
1339} __attribute__ ((packed));
1340
1341struct megasas_evt_detail {
1342
1343 u32 seq_num;
1344 u32 time_stamp;
1345 u32 code;
1346 union megasas_evt_class_locale cl;
1347 u8 arg_type;
1348 u8 reserved1[15];
1349
1350 union {
1351 struct {
1352 struct megasas_evtarg_pd pd;
1353 u8 cdb_length;
1354 u8 sense_length;
1355 u8 reserved[2];
1356 u8 cdb[16];
1357 u8 sense[64];
1358 } __attribute__ ((packed)) cdbSense;
1359
1360 struct megasas_evtarg_ld ld;
1361
1362 struct {
1363 struct megasas_evtarg_ld ld;
1364 u64 count;
1365 } __attribute__ ((packed)) ld_count;
1366
1367 struct {
1368 u64 lba;
1369 struct megasas_evtarg_ld ld;
1370 } __attribute__ ((packed)) ld_lba;
1371
1372 struct {
1373 struct megasas_evtarg_ld ld;
1374 u32 prevOwner;
1375 u32 newOwner;
1376 } __attribute__ ((packed)) ld_owner;
1377
1378 struct {
1379 u64 ld_lba;
1380 u64 pd_lba;
1381 struct megasas_evtarg_ld ld;
1382 struct megasas_evtarg_pd pd;
1383 } __attribute__ ((packed)) ld_lba_pd_lba;
1384
1385 struct {
1386 struct megasas_evtarg_ld ld;
1387 struct megasas_progress prog;
1388 } __attribute__ ((packed)) ld_prog;
1389
1390 struct {
1391 struct megasas_evtarg_ld ld;
1392 u32 prev_state;
1393 u32 new_state;
1394 } __attribute__ ((packed)) ld_state;
1395
1396 struct {
1397 u64 strip;
1398 struct megasas_evtarg_ld ld;
1399 } __attribute__ ((packed)) ld_strip;
1400
1401 struct megasas_evtarg_pd pd;
1402
1403 struct {
1404 struct megasas_evtarg_pd pd;
1405 u32 err;
1406 } __attribute__ ((packed)) pd_err;
1407
1408 struct {
1409 u64 lba;
1410 struct megasas_evtarg_pd pd;
1411 } __attribute__ ((packed)) pd_lba;
1412
1413 struct {
1414 u64 lba;
1415 struct megasas_evtarg_pd pd;
1416 struct megasas_evtarg_ld ld;
1417 } __attribute__ ((packed)) pd_lba_ld;
1418
1419 struct {
1420 struct megasas_evtarg_pd pd;
1421 struct megasas_progress prog;
1422 } __attribute__ ((packed)) pd_prog;
1423
1424 struct {
1425 struct megasas_evtarg_pd pd;
1426 u32 prevState;
1427 u32 newState;
1428 } __attribute__ ((packed)) pd_state;
1429
1430 struct {
1431 u16 vendorId;
1432 u16 deviceId;
1433 u16 subVendorId;
1434 u16 subDeviceId;
1435 } __attribute__ ((packed)) pci;
1436
1437 u32 rate;
1438 char str[96];
1439
1440 struct {
1441 u32 rtc;
1442 u32 elapsedSeconds;
1443 } __attribute__ ((packed)) time;
1444
1445 struct {
1446 u32 ecar;
1447 u32 elog;
1448 char str[64];
1449 } __attribute__ ((packed)) ecc;
1450
1451 u8 b[96];
1452 u16 s[48];
1453 u32 w[24];
1454 u64 d[12];
1455 } args;
1456
1457 char description[128];
1458
1459} __attribute__ ((packed));
1460
7e8a75f4 1461struct megasas_aen_event {
c1d390d8 1462 struct delayed_work hotplug_work;
7e8a75f4
YB		 1463 struct megasas_instance *instance;
1464};
1465
c8e858fe
AR		 1466struct megasas_irq_context {
1467 struct megasas_instance *instance;
1468 u32 MSIxIndex;
1469};
1470
c4a3e0a5
BS		 1471struct megasas_instance {
1472
1473 u32 *producer;
1474 dma_addr_t producer_h;
1475 u32 *consumer;
1476 dma_addr_t consumer_h;
1477
1478 u32 *reply_queue;
1479 dma_addr_t reply_queue_h;
1480
1481 unsigned long base_addr;
1482 struct megasas_register_set __iomem *reg_set;
d46a3ad6 1483 u32 *reply_post_host_index_addr[MR_MAX_MSIX_REG_ARRAY];
81e403ce 1484 struct megasas_pd_list pd_list[MEGASAS_MAX_PD];
bdc6fb8d 1485 u8 ld_ids[MEGASAS_MAX_LD_IDS];
c4a3e0a5 1486 s8 init_id;
c4a3e0a5
BS		 1487
1488 u16 max_num_sge;
1489 u16 max_fw_cmds;
9c915a8c
AR		 1490 /* For Fusion its num IOCTL cmds, for others MFI based its
1491 max_fw_cmds */
1492 u16 max_mfi_cmds;
c4a3e0a5 1493 u32 max_sectors_per_req;
7e8a75f4 1494 struct megasas_aen_event *ev;
c4a3e0a5
BS		 1495
1496 struct megasas_cmd **cmd_list;
1497 struct list_head cmd_pool;
39a98554 1498 /* used to sync fire the cmd to fw */
c4a3e0a5 1499 spinlock_t cmd_pool_lock;
39a98554 1500 /* used to sync fire the cmd to fw */
1501 spinlock_t hba_lock;
7343eb65 1502 /* used to synch producer, consumer ptrs in dpc */
1503 spinlock_t completion_lock;
c4a3e0a5
BS		 1504 struct dma_pool *frame_dma_pool;
1505 struct dma_pool *sense_dma_pool;
1506
1507 struct megasas_evt_detail *evt_detail;
1508 dma_addr_t evt_detail_h;
1509 struct megasas_cmd *aen_cmd;
e5a69e27 1510 struct mutex aen_mutex;
c4a3e0a5
BS		 1511 struct semaphore ioctl_sem;
1512
1513 struct Scsi_Host *host;
1514
1515 wait_queue_head_t int_cmd_wait_q;
1516 wait_queue_head_t abort_cmd_wait_q;
1517
1518 struct pci_dev *pdev;
1519 u32 unique_id;
39a98554 1520 u32 fw_support_ieee;
c4a3e0a5 1521
e4a082c7 1522 atomic_t fw_outstanding;
39a98554 1523 atomic_t fw_reset_no_pci_access;
1341c939
SP		 1524
1525 struct megasas_instance_template *instancet;
5d018ad0 1526 struct tasklet_struct isr_tasklet;
39a98554 1527 struct work_struct work_init;
05e9ebbe
SP		 1528
1529 u8 flag;
c3518837 1530 u8 unload;
f4c9a131 1531 u8 flag_ieee;
39a98554 1532 u8 issuepend_done;
1533 u8 disableOnlineCtrlReset;
bc93d425 1534 u8 UnevenSpanSupport;
39a98554 1535 u8 adprecovery;
05e9ebbe 1536 unsigned long last_time;
39a98554 1537 u32 mfiStatus;
1538 u32 last_seq_num;
ad84db2e 1539
39a98554 1540 struct list_head internal_reset_pending_q;
80d9da98 1541
25985edc 1542 /* Ptr to hba specific information */
9c915a8c 1543 void *ctrl_context;
c8e858fe
AR		 1544 unsigned int msix_vectors;
1545 struct msix_entry msixentry[MEGASAS_MAX_MSIX_QUEUES];
1546 struct megasas_irq_context irq_context[MEGASAS_MAX_MSIX_QUEUES];
9c915a8c
AR		 1547 u64 map_id;
1548 struct megasas_cmd *map_update_cmd;
b6d5d880 1549 unsigned long bar;
9c915a8c
AR		 1550 long reset_flags;
1551 struct mutex reset_mutex;
c5daa6a9 1552 int throttlequeuedepth;
d46a3ad6 1553 u8 mask_interrupts;
404a8a1a 1554 u8 is_imr;
39a98554 1555};
1556
1557enum {
1558 MEGASAS_HBA_OPERATIONAL = 0,
1559 MEGASAS_ADPRESET_SM_INFAULT = 1,
1560 MEGASAS_ADPRESET_SM_FW_RESET_SUCCESS = 2,
1561 MEGASAS_ADPRESET_SM_OPERATIONAL = 3,
1562 MEGASAS_HW_CRITICAL_ERROR = 4,
1563 MEGASAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD,
c4a3e0a5
BS		 1564};
1565
0c79e681
YB		 1566struct megasas_instance_template {
1567 void (*fire_cmd)(struct megasas_instance *, dma_addr_t, \
1568 u32, struct megasas_register_set __iomem *);
1569
d46a3ad6
SS		 1570 void (*enable_intr)(struct megasas_instance *);
1571 void (*disable_intr)(struct megasas_instance *);
0c79e681
YB		 1572
1573 int (*clear_intr)(struct megasas_register_set __iomem *);
1574
1575 u32 (*read_fw_status_reg)(struct megasas_register_set __iomem *);
39a98554 1576 int (*adp_reset)(struct megasas_instance *, \
1577 struct megasas_register_set __iomem *);
1578 int (*check_reset)(struct megasas_instance *, \
1579 struct megasas_register_set __iomem *);
cd50ba8e
AR		 1580 irqreturn_t (*service_isr)(int irq, void *devp);
1581 void (*tasklet)(unsigned long);
1582 u32 (*init_adapter)(struct megasas_instance *);
1583 u32 (*build_and_issue_cmd) (struct megasas_instance *,
1584 struct scsi_cmnd *);
1585 void (*issue_dcmd) (struct megasas_instance *instance,
1586 struct megasas_cmd *cmd);
0c79e681
YB		 1587};
1588
c4a3e0a5
BS		 1589#define MEGASAS_IS_LOGICAL(scp) \
1590 (scp->device->channel < MEGASAS_MAX_PD_CHANNELS) ? 0 : 1
1591
1592#define MEGASAS_DEV_INDEX(inst, scp) \
1593 ((scp->device->channel % 2) * MEGASAS_MAX_DEV_PER_CHANNEL) + \
1594 scp->device->id
1595
1596struct megasas_cmd {
1597
1598 union megasas_frame *frame;
1599 dma_addr_t frame_phys_addr;
1600 u8 *sense;
1601 dma_addr_t sense_phys_addr;
1602
1603 u32 index;
1604 u8 sync_cmd;
1605 u8 cmd_status;
39a98554 1606 u8 abort_aen;
1607 u8 retry_for_fw_reset;
1608
c4a3e0a5
BS		 1609
1610 struct list_head list;
1611 struct scsi_cmnd *scmd;
1612 struct megasas_instance *instance;
9c915a8c
AR		 1613 union {
1614 struct {
1615 u16 smid;
1616 u16 resvd;
1617 } context;
1618 u32 frame_count;
1619 };
c4a3e0a5
BS		 1620};
1621
1622#define MAX_MGMT_ADAPTERS 1024
1623#define MAX_IOCTL_SGE 16
1624
1625struct megasas_iocpacket {
1626
1627 u16 host_no;
1628 u16 __pad1;
1629 u32 sgl_off;
1630 u32 sge_count;
1631 u32 sense_off;
1632 u32 sense_len;
1633 union {
1634 u8 raw[128];
1635 struct megasas_header hdr;
1636 } frame;
1637
1638 struct iovec sgl[MAX_IOCTL_SGE];
1639
1640} __attribute__ ((packed));
1641
1642struct megasas_aen {
1643 u16 host_no;
1644 u16 __pad1;
1645 u32 seq_num;
1646 u32 class_locale_word;
1647} __attribute__ ((packed));
1648
1649#ifdef CONFIG_COMPAT
1650struct compat_megasas_iocpacket {
1651 u16 host_no;
1652 u16 __pad1;
1653 u32 sgl_off;
1654 u32 sge_count;
1655 u32 sense_off;
1656 u32 sense_len;
1657 union {
1658 u8 raw[128];
1659 struct megasas_header hdr;
1660 } frame;
1661 struct compat_iovec sgl[MAX_IOCTL_SGE];
1662} __attribute__ ((packed));
1663
0e98936c 1664#define MEGASAS_IOC_FIRMWARE32 _IOWR('M', 1, struct compat_megasas_iocpacket)
c4a3e0a5
BS		 1665#endif
1666
cb59aa6a 1667#define MEGASAS_IOC_FIRMWARE _IOWR('M', 1, struct megasas_iocpacket)
c4a3e0a5
BS		 1668#define MEGASAS_IOC_GET_AEN _IOW('M', 3, struct megasas_aen)
1669
1670struct megasas_mgmt_info {
1671
1672 u16 count;
1673 struct megasas_instance *instance[MAX_MGMT_ADAPTERS];
1674 int max_index;
1675};
1676
21c9e160
AR		 1677u8
1678MR_BuildRaidContext(struct megasas_instance *instance,
1679 struct IO_REQUEST_INFO *io_info,
1680 struct RAID_CONTEXT *pRAID_Context,
1681 struct MR_FW_RAID_MAP_ALL *map, u8 **raidLUN);
1682u16 MR_TargetIdToLdGet(u32 ldTgtId, struct MR_FW_RAID_MAP_ALL *map);
1683struct MR_LD_RAID *MR_LdRaidGet(u32 ld, struct MR_FW_RAID_MAP_ALL *map);
1684u16 MR_ArPdGet(u32 ar, u32 arm, struct MR_FW_RAID_MAP_ALL *map);
1685u16 MR_LdSpanArrayGet(u32 ld, u32 span, struct MR_FW_RAID_MAP_ALL *map);
1686u16 MR_PdDevHandleGet(u32 pd, struct MR_FW_RAID_MAP_ALL *map);
1687u16 MR_GetLDTgtId(u32 ld, struct MR_FW_RAID_MAP_ALL *map);
1688
c4a3e0a5 1689#endif /*LSI_MEGARAID_SAS_H */
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